1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter MIPS Dependent Features
12 @node Machine Dependencies
13 @chapter MIPS Dependent Features
16 @cindex MIPS processor
17 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
18 different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
19 and MIPS64. For information about the @sc{mips} instruction set, see
20 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
21 For an overview of @sc{mips} assembly conventions, see ``Appendix D:
22 Assembly Language Programming'' in the same work.
25 * MIPS Opts:: Assembler options
26 * MIPS Object:: ECOFF object code
27 * MIPS Stabs:: Directives for debugging information
28 * MIPS ISA:: Directives to override the ISA level
29 * MIPS symbol sizes:: Directives to override the size of symbols
30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
31 * MIPS insn:: Directive to mark data as an instruction
32 * MIPS option stack:: Directives to save and restore options
33 * MIPS ASE instruction generation overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS floating-point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 This option sets the largest size of an object that can be referenced
49 implicitly with the @code{gp} register. It is only accepted for targets
50 that use @sc{ecoff} format. The default value is 8.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
87 Generate code for a particular MIPS Instruction Set Architecture level.
88 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
89 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
90 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
91 @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2},
92 @samp{-mips64}, and @samp{-mips64r2}
94 @sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64},
95 and @sc{MIPS64 Release 2}
96 ISA processors, respectively. You can also switch
97 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
98 override the ISA level}.
102 Some macros have different expansions for 32-bit and 64-bit registers.
103 The register sizes are normally inferred from the ISA and ABI, but these
104 flags force a certain group of registers to be treated as 32 bits wide at
105 all times. @samp{-mgp32} controls the size of general-purpose registers
106 and @samp{-mfp32} controls the size of floating-point registers.
108 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
109 of registers to be changed for parts of an object. The default value is
110 restored by @code{.set gp=default} and @code{.set fp=default}.
112 On some MIPS variants there is a 32-bit mode flag; when this flag is
113 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
114 save the 32-bit registers on a context switch, so it is essential never
115 to use the 64-bit registers.
119 Assume that 64-bit registers are available. This is provided in the
120 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
122 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
123 of registers to be changed for parts of an object. The default value is
124 restored by @code{.set gp=default} and @code{.set fp=default}.
128 Generate code for the MIPS 16 processor. This is equivalent to putting
129 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
130 turns off this option.
133 @itemx -mno-micromips
134 Generate code for the microMIPS processor. This is equivalent to putting
135 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
136 turns off this option. This is equivalent to putting @code{.set nomicromips}
137 at the start of the assembly file.
140 @itemx -mno-smartmips
141 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
142 provides a number of new instructions which target smartcard and
143 cryptographic applications. This is equivalent to putting
144 @code{.set smartmips} at the start of the assembly file.
145 @samp{-mno-smartmips} turns off this option.
149 Generate code for the MIPS-3D Application Specific Extension.
150 This tells the assembler to accept MIPS-3D instructions.
151 @samp{-no-mips3d} turns off this option.
155 Generate code for the MDMX Application Specific Extension.
156 This tells the assembler to accept MDMX instructions.
157 @samp{-no-mdmx} turns off this option.
161 Generate code for the DSP Release 1 Application Specific Extension.
162 This tells the assembler to accept DSP Release 1 instructions.
163 @samp{-mno-dsp} turns off this option.
167 Generate code for the DSP Release 2 Application Specific Extension.
168 This option implies -mdsp.
169 This tells the assembler to accept DSP Release 2 instructions.
170 @samp{-mno-dspr2} turns off this option.
174 Generate code for the MT Application Specific Extension.
175 This tells the assembler to accept MT instructions.
176 @samp{-mno-mt} turns off this option.
180 Generate code for the MCU Application Specific Extension.
181 This tells the assembler to accept MCU instructions.
182 @samp{-mno-mcu} turns off this option.
186 Generate code for the Virtualization Application Specific Extension.
187 This tells the assembler to accept Virtualization instructions.
188 @samp{-mno-virt} turns off this option.
192 Cause nops to be inserted if the read of the destination register
193 of an mfhi or mflo instruction occurs in the following two instructions.
195 @item -mfix-loongson2f-jump
196 @itemx -mno-fix-loongson2f-jump
197 Eliminate instruction fetch from outside 256M region to work around the
198 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
199 the kernel may crash. The issue has been solved in latest processor
200 batches, but this fix has no side effect to them.
202 @item -mfix-loongson2f-nop
203 @itemx -mno-fix-loongson2f-nop
204 Replace nops by @code{or at,at,zero} to work around the Loongson2F
205 @samp{nop} errata. Without it, under extreme cases, cpu might
206 deadlock. The issue has been solved in latest loongson2f batches, but
207 this fix has no side effect to them.
210 @itemx -mno-fix-vr4120
211 Insert nops to work around certain VR4120 errata. This option is
212 intended to be used on GCC-generated code: it is not designed to catch
213 all problems in hand-written assembler code.
216 @itemx -mno-fix-vr4130
217 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
221 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
224 @itemx -mno-fix-cn63xxp1
225 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
226 certain CN63XXP1 errata.
230 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
231 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
232 etc.), and to not schedule @samp{nop} instructions around accesses to
233 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
238 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
239 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
240 instructions around accesses to the @samp{HI} and @samp{LO} registers.
241 @samp{-no-m4650} turns off this option.
247 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
248 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
249 specific to that chip, and to schedule for that chip's hazards.
251 @item -march=@var{cpu}
252 Generate code for a particular MIPS cpu. It is exactly equivalent to
253 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
254 understood. Valid @var{cpu} value are:
339 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
340 accepted as synonyms for @samp{@var{n}f1_1}. These values are
343 @item -mtune=@var{cpu}
344 Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
345 identical to @samp{-march=@var{cpu}}.
347 @item -mabi=@var{abi}
348 Record which ABI the source code uses. The recognized arguments
349 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
355 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
356 the beginning of the assembler input. @xref{MIPS symbol sizes}.
358 @cindex @code{-nocpp} ignored (MIPS)
360 This option is ignored. It is accepted for command-line compatibility with
361 other assemblers, which use it to turn off C style preprocessing. With
362 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
363 @sc{gnu} assembler itself never runs the C preprocessor.
367 Disable or enable floating-point instructions. Note that by default
368 floating-point instructions are always allowed even with CPU targets
369 that don't have support for these instructions.
372 @itemx -mdouble-float
373 Disable or enable double-precision floating-point operations. Note
374 that by default double-precision floating-point operations are always
375 allowed even with CPU targets that don't have support for these
378 @item --construct-floats
379 @itemx --no-construct-floats
380 The @code{--no-construct-floats} option disables the construction of
381 double width floating point constants by loading the two halves of the
382 value into the two single width floating point registers that make up
383 the double width register. This feature is useful if the processor
384 support the FR bit in its status register, and this bit is known (by
385 the programmer) to be set. This bit prevents the aliasing of the double
386 width register by the single width registers.
388 By default @code{--construct-floats} is selected, allowing construction
389 of these floating point constants.
392 @itemx --no-relax-branch
393 The @samp{--relax-branch} option enables the relaxation of out-of-range
394 branches. Any branches whose target cannot be reached directly are
395 converted to a small instruction sequence including an inverse-condition
396 branch to the physically next instruction, and a jump to the original
397 target is inserted between the two instructions. In PIC code the jump
398 will involve further instructions for address calculation.
400 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
401 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
402 relaxation, because they have no complementing counterparts. They could
403 be relaxed with the use of a longer sequence involving another branch,
404 however this has not been implemented and if their target turns out of
405 reach, they produce an error even if branch relaxation is enabled.
407 Also no @sc{mips16} branches are ever relaxed.
409 By default @samp{--no-relax-branch} is selected, causing any out-of-range
410 branches to produce an error.
414 @c FIXME! (1) reflect these options (next item too) in option summaries;
415 @c (2) stop teasing, say _which_ instructions expanded _how_.
416 @code{@value{AS}} automatically macro expands certain division and
417 multiplication instructions to check for overflow and division by zero. This
418 option causes @code{@value{AS}} to generate code to take a trap exception
419 rather than a break exception when an error is detected. The trap instructions
420 are only supported at Instruction Set Architecture level 2 and higher.
424 Generate code to take a break exception rather than a trap exception when an
425 error is detected. This is the default.
429 Control generation of @code{.pdr} sections. Off by default on IRIX, on
434 When generating code using the Unix calling conventions (selected by
435 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
436 which can go into a shared library. The @samp{-mno-shared} option
437 tells gas to generate code which uses the calling convention, but can
438 not go into a shared library. The resulting code is slightly more
439 efficient. This option only affects the handling of the
440 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
444 @section MIPS ECOFF object code
446 @cindex ECOFF sections
447 @cindex MIPS ECOFF sections
448 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
449 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
450 additional sections are @code{.rdata}, used for read-only data,
451 @code{.sdata}, used for small data, and @code{.sbss}, used for small
454 @cindex small objects, MIPS ECOFF
455 @cindex @code{gp} register, MIPS
456 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
457 register to form the address of a ``small object''. Any object in the
458 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
459 For external objects, or for objects in the @code{.bss} section, you can use
460 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
461 @code{$gp}; the default value is 8, meaning that a reference to any object
462 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
463 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
464 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
465 or @code{sbss} in any case). The size of an object in the @code{.bss} section
466 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
467 size of an external object may be set with the @code{.extern} directive. For
468 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
469 in length, whie leaving @code{sym} otherwise undefined.
471 Using small @sc{ecoff} objects requires linker support, and assumes that the
472 @code{$gp} register is correctly initialized (normally done automatically by
473 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
477 @section Directives for debugging information
479 @cindex MIPS debugging directives
480 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
481 generating debugging information which are not support by traditional @sc{mips}
482 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
483 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
484 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
485 generated by the three @code{.stab} directives can only be read by @sc{gdb},
486 not by traditional @sc{mips} debuggers (this enhancement is required to fully
487 support C++ debugging). These directives are primarily used by compilers, not
488 assembly language programmers!
490 @node MIPS symbol sizes
491 @section Directives to override the size of symbols
493 @cindex @code{.set sym32}
494 @cindex @code{.set nosym32}
495 The n64 ABI allows symbols to have any 64-bit value. Although this
496 provides a great deal of flexibility, it means that some macros have
497 much longer expansions than their 32-bit counterparts. For example,
498 the non-PIC expansion of @samp{dla $4,sym} is usually:
503 daddiu $4,$4,%higher(sym)
504 daddiu $1,$1,%lo(sym)
509 whereas the 32-bit expansion is simply:
513 daddiu $4,$4,%lo(sym)
516 n64 code is sometimes constructed in such a way that all symbolic
517 constants are known to have 32-bit values, and in such cases, it's
518 preferable to use the 32-bit expansion instead of the 64-bit
521 You can use the @code{.set sym32} directive to tell the assembler
522 that, from this point on, all expressions of the form
523 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
524 have 32-bit values. For example:
533 will cause the assembler to treat @samp{sym}, @code{sym+16} and
534 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
535 addresses is not affected.
537 The directive @code{.set nosym32} ends a @code{.set sym32} block and
538 reverts to the normal behavior. It is also possible to change the
539 symbol size using the command-line options @option{-msym32} and
542 These options and directives are always accepted, but at present,
543 they have no effect for anything other than n64.
546 @section Directives to override the ISA level
548 @cindex MIPS ISA override
549 @kindex @code{.set mips@var{n}}
550 @sc{gnu} @code{@value{AS}} supports an additional directive to change
551 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
552 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
554 The values other than 0 make the assembler accept instructions
555 for the corresponding @sc{isa} level, from that point on in the
556 assembly. @code{.set mips@var{n}} affects not only which instructions
557 are permitted, but also how certain macros are expanded. @code{.set
558 mips0} restores the @sc{isa} level to its original level: either the
559 level you selected with command line options, or the default for your
560 configuration. You can use this feature to permit specific @sc{mips3}
561 instructions while assembling in 32 bit mode. Use this directive with
564 @cindex MIPS CPU override
565 @kindex @code{.set arch=@var{cpu}}
566 The @code{.set arch=@var{cpu}} directive provides even finer control.
567 It changes the effective CPU target and allows the assembler to use
568 instructions specific to a particular CPU. All CPUs supported by the
569 @samp{-march} command line option are also selectable by this directive.
570 The original value is restored by @code{.set arch=default}.
572 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
573 in which it will assemble instructions for the MIPS 16 processor. Use
574 @code{.set nomips16} to return to normal 32 bit mode.
576 Traditional @sc{mips} assemblers do not support this directive.
578 The directive @code{.set micromips} puts the assembler into microMIPS mode,
579 in which it will assemble instructions for the microMIPS processor. Use
580 @code{.set nomicromips} to return to normal 32 bit mode.
582 Traditional @sc{mips} assemblers do not support this directive.
584 @node MIPS autoextend
585 @section Directives for extending MIPS 16 bit instructions
587 @kindex @code{.set autoextend}
588 @kindex @code{.set noautoextend}
589 By default, MIPS 16 instructions are automatically extended to 32 bits
590 when necessary. The directive @code{.set noautoextend} will turn this
591 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
592 must be explicitly extended with the @code{.e} modifier (e.g.,
593 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
594 to once again automatically extend instructions when necessary.
596 This directive is only meaningful when in MIPS 16 mode. Traditional
597 @sc{mips} assemblers do not support this directive.
600 @section Directive to mark data as an instruction
603 The @code{.insn} directive tells @code{@value{AS}} that the following
604 data is actually instructions. This makes a difference in MIPS 16 and
605 microMIPS modes: when loading the address of a label which precedes
606 instructions, @code{@value{AS}} automatically adds 1 to the value, so
607 that jumping to the loaded address will do the right thing.
609 @kindex @code{.global}
610 The @code{.global} and @code{.globl} directives supported by
611 @code{@value{AS}} will by default mark the symbol as pointing to a
612 region of data not code. This means that, for example, any
613 instructions following such a symbol will not be disassembled by
614 @code{objdump} as it will regard them as data. To change this
615 behaviour an optional section name can be placed after the symbol name
616 in the @code{.global} directive. If this section exists and is known
617 to be a code section, then the symbol will be marked as poiting at
618 code not data. Ie the syntax for the directive is:
620 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
622 Here is a short example:
625 .global foo .text, bar, baz .data
635 @node MIPS option stack
636 @section Directives to save and restore options
638 @cindex MIPS option stack
639 @kindex @code{.set push}
640 @kindex @code{.set pop}
641 The directives @code{.set push} and @code{.set pop} may be used to save
642 and restore the current settings for all the options which are
643 controlled by @code{.set}. The @code{.set push} directive saves the
644 current settings on a stack. The @code{.set pop} directive pops the
645 stack and restores the settings.
647 These directives can be useful inside an macro which must change an
648 option such as the ISA level or instruction reordering but does not want
649 to change the state of the code which invoked the macro.
651 Traditional @sc{mips} assemblers do not support these directives.
653 @node MIPS ASE instruction generation overrides
654 @section Directives to control generation of MIPS ASE instructions
656 @cindex MIPS MIPS-3D instruction generation override
657 @kindex @code{.set mips3d}
658 @kindex @code{.set nomips3d}
659 The directive @code{.set mips3d} makes the assembler accept instructions
660 from the MIPS-3D Application Specific Extension from that point on
661 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
662 instructions from being accepted.
664 @cindex SmartMIPS instruction generation override
665 @kindex @code{.set smartmips}
666 @kindex @code{.set nosmartmips}
667 The directive @code{.set smartmips} makes the assembler accept
668 instructions from the SmartMIPS Application Specific Extension to the
669 MIPS32 @sc{isa} from that point on in the assembly. The
670 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
673 @cindex MIPS MDMX instruction generation override
674 @kindex @code{.set mdmx}
675 @kindex @code{.set nomdmx}
676 The directive @code{.set mdmx} makes the assembler accept instructions
677 from the MDMX Application Specific Extension from that point on
678 in the assembly. The @code{.set nomdmx} directive prevents MDMX
679 instructions from being accepted.
681 @cindex MIPS DSP Release 1 instruction generation override
682 @kindex @code{.set dsp}
683 @kindex @code{.set nodsp}
684 The directive @code{.set dsp} makes the assembler accept instructions
685 from the DSP Release 1 Application Specific Extension from that point
686 on in the assembly. The @code{.set nodsp} directive prevents DSP
687 Release 1 instructions from being accepted.
689 @cindex MIPS DSP Release 2 instruction generation override
690 @kindex @code{.set dspr2}
691 @kindex @code{.set nodspr2}
692 The directive @code{.set dspr2} makes the assembler accept instructions
693 from the DSP Release 2 Application Specific Extension from that point
694 on in the assembly. This dirctive implies @code{.set dsp}. The
695 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
698 @cindex MIPS MT instruction generation override
699 @kindex @code{.set mt}
700 @kindex @code{.set nomt}
701 The directive @code{.set mt} makes the assembler accept instructions
702 from the MT Application Specific Extension from that point on
703 in the assembly. The @code{.set nomt} directive prevents MT
704 instructions from being accepted.
706 @cindex MIPS MCU instruction generation override
707 @kindex @code{.set mcu}
708 @kindex @code{.set nomcu}
709 The directive @code{.set mcu} makes the assembler accept instructions
710 from the MCU Application Specific Extension from that point on
711 in the assembly. The @code{.set nomcu} directive prevents MCU
712 instructions from being accepted.
714 @cindex Virtualization instruction generation override
715 @kindex @code{.set virt}
716 @kindex @code{.set novirt}
717 The directive @code{.set virt} makes the assembler accept instructions
718 from the Virtualization Application Specific Extension from that point
719 on in the assembly. The @code{.set novirt} directive prevents Virtualization
720 instructions from being accepted.
722 Traditional @sc{mips} assemblers do not support these directives.
724 @node MIPS floating-point
725 @section Directives to override floating-point options
727 @cindex Disable floating-point instructions
728 @kindex @code{.set softfloat}
729 @kindex @code{.set hardfloat}
730 The directives @code{.set softfloat} and @code{.set hardfloat} provide
731 finer control of disabling and enabling float-point instructions.
732 These directives always override the default (that hard-float
733 instructions are accepted) or the command-line options
734 (@samp{-msoft-float} and @samp{-mhard-float}).
736 @cindex Disable single-precision floating-point operations
737 @kindex @code{.set singlefloat}
738 @kindex @code{.set doublefloat}
739 The directives @code{.set singlefloat} and @code{.set doublefloat}
740 provide finer control of disabling and enabling double-precision
741 float-point operations. These directives always override the default
742 (that double-precision operations are accepted) or the command-line
743 options (@samp{-msingle-float} and @samp{-mdouble-float}).
745 Traditional @sc{mips} assemblers do not support these directives.
748 @section Syntactical considerations for the MIPS assembler
750 * MIPS-Chars:: Special Characters
754 @subsection Special Characters
756 @cindex line comment character, MIPS
757 @cindex MIPS line comment character
758 The presence of a @samp{#} on a line indicates the start of a comment
759 that extends to the end of the current line.
761 If a @samp{#} appears as the first character of a line, the whole line
762 is treated as a comment, but in this case the line can also be a
763 logical line number directive (@pxref{Comments}) or a
764 preprocessor control command (@pxref{Preprocessing}).
766 @cindex line separator, MIPS
767 @cindex statement separator, MIPS
768 @cindex MIPS line separator
769 The @samp{;} character can be used to separate statements on the same