1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
16 different @sc{mips} processors, and MIPS ISA levels I through IV. For
17 information about the @sc{mips} instruction set, see @cite{MIPS RISC
18 Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
19 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
20 Programming'' in the same work.
23 * MIPS Opts:: Assembler options
24 * MIPS Object:: ECOFF object code
25 * MIPS Stabs:: Directives for debugging information
26 * MIPS ISA:: Directives to override the ISA level
27 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
28 * MIPS insn:: Directive to mark data as an instruction
29 * MIPS option stack:: Directives to save and restore options
33 @section Assembler options
35 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
39 @cindex @code{-G} option (MIPS)
41 This option sets the largest size of an object that can be referenced
42 implicitly with the @code{gp} register. It is only accepted for targets
43 that use @sc{ecoff} format. The default value is 8.
45 @cindex @code{-EB} option (MIPS)
46 @cindex @code{-EL} option (MIPS)
47 @cindex MIPS big-endian output
48 @cindex MIPS little-endian output
49 @cindex big-endian output, MIPS
50 @cindex little-endian output, MIPS
53 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
54 little-endian output at run time (unlike the other @sc{gnu} development
55 tools, which must be configured for one or the other). Use @samp{-EB}
56 to select big-endian output, and @samp{-EL} for little-endian.
58 @cindex MIPS architecture options
63 Generate code for a particular MIPS Instruction Set Architecture level.
64 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
65 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
66 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
67 @sc{r10000} processors. You can also switch instruction sets during the
68 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
72 Generate code for the MIPS 16 processor. This is equivalent to putting
73 @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
74 turns off this option.
78 Generate code for the LSI @sc{r4010} chip. This tells the assembler to
79 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
80 etc.), and to not schedule @samp{nop} instructions around accesses to
81 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
86 Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
87 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
88 instructions around accesses to the @samp{HI} and @samp{LO} registers.
89 @samp{-no-m4650} turns off this option.
91 @c start-sanitize-tx19
99 @c start-sanitize-vr4xxx
102 @c end-sanitize-vr4xxx
103 @c start-sanitize-4320
107 @c start-sanitize-tx49
111 @c start-sanitize-cygnus
114 @c end-sanitize-cygnus
115 @c start-sanitize-r5900
118 @c end-sanitize-r5900
119 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
120 @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
121 specific to that chip, and to schedule for that chip's hazards.
123 @item -mcpu=@var{cpu}
124 Generate code for a particular MIPS cpu. It is exactly equivalent to
125 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
126 understood. Valid @var{cpu} value are:
129 @c start-sanitize-tx19
138 @c start-sanitize-vr4xxx
141 @c end-sanitize-vr4xxx
143 @c start-sanitize-vr4320
145 @c end-sanitize-vr4320
149 @c start-sanitize-tx49
153 @c start-sanitize-cygnus
155 @c end-sanitize-cygnus
156 @c start-sanitize-r5900
158 @c end-sanitize-r5900
165 @cindex @code{-nocpp} ignored (MIPS)
167 This option is ignored. It is accepted for command-line compatibility with
168 other assemblers, which use it to turn off C style preprocessing. With
169 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
170 @sc{gnu} assembler itself never runs the C preprocessor.
174 @c FIXME! (1) reflect these options (next item too) in option summaries;
175 @c (2) stop teasing, say _which_ instructions expanded _how_.
176 @code{@value{AS}} automatically macro expands certain division and
177 multiplication instructions to check for overflow and division by zero. This
178 option causes @code{@value{AS}} to generate code to take a trap exception
179 rather than a break exception when an error is detected. The trap instructions
180 are only supported at Instruction Set Architecture level 2 and higher.
184 Generate code to take a break exception rather than a trap exception when an
185 error is detected. This is the default.
189 @section MIPS ECOFF object code
191 @cindex ECOFF sections
192 @cindex MIPS ECOFF sections
193 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
194 besides the usual @code{.text}, @code{.data} and @code{.bss}. The
195 additional sections are @code{.rdata}, used for read-only data,
196 @code{.sdata}, used for small data, and @code{.sbss}, used for small
199 @cindex small objects, MIPS ECOFF
200 @cindex @code{gp} register, MIPS
201 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
202 register to form the address of a ``small object''. Any object in the
203 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
204 For external objects, or for objects in the @code{.bss} section, you can use
205 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
206 @code{$gp}; the default value is 8, meaning that a reference to any object
207 eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
208 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
209 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
210 or @code{sbss} in any case). The size of an object in the @code{.bss} section
211 is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
212 size of an external object may be set with the @code{.extern} directive. For
213 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
214 in length, whie leaving @code{sym} otherwise undefined.
216 Using small @sc{ecoff} objects requires linker support, and assumes that the
217 @code{$gp} register is correctly initialized (normally done automatically by
218 the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
222 @section Directives for debugging information
224 @cindex MIPS debugging directives
225 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
226 generating debugging information which are not support by traditional @sc{mips}
227 assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
228 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
229 @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
230 generated by the three @code{.stab} directives can only be read by @sc{gdb},
231 not by traditional @sc{mips} debuggers (this enhancement is required to fully
232 support C++ debugging). These directives are primarily used by compilers, not
233 assembly language programmers!
236 @section Directives to override the ISA level
238 @cindex MIPS ISA override
239 @kindex @code{.set mips@var{n}}
240 @sc{gnu} @code{@value{AS}} supports an additional directive to change
241 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
242 mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1
243 to 4 makes the assembler accept instructions for the corresponding
244 @sc{isa} level, from that point on in the assembly. @code{.set
245 mips@var{n}} affects not only which instructions are permitted, but also
246 how certain macros are expanded. @code{.set mips0} restores the
247 @sc{isa} level to its original level: either the level you selected with
248 command line options, or the default for your configuration. You can
249 use this feature to permit specific @sc{r4000} instructions while
250 assembling in 32 bit mode. Use this directive with care!
252 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
253 in which it will assemble instructions for the MIPS 16 processor. Use
254 @samp{.set nomips16} to return to normal 32 bit mode.
256 Traditional @sc{mips} assemblers do not support this directive.
258 @node MIPS autoextend
259 @section Directives for extending MIPS 16 bit instructions
261 @kindex @code{.set autoextend}
262 @kindex @code{.set noautoextend}
263 By default, MIPS 16 instructions are automatically extended to 32 bits
264 when necessary. The directive @samp{.set noautoextend} will turn this
265 off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
266 must be explicitly extended with the @samp{.e} modifier (e.g.,
267 @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
268 to once again automatically extend instructions when necessary.
270 This directive is only meaningful when in MIPS 16 mode. Traditional
271 @sc{mips} assemblers do not support this directive.
274 @section Directive to mark data as an instruction
277 The @code{.insn} directive tells @code{@value{AS}} that the following
278 data is actually instructions. This makes a difference in MIPS 16 mode:
279 when loading the address of a label which precedes instructions,
280 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
281 the loaded address will do the right thing.
283 @node MIPS option stack
284 @section Directives to save and restore options
286 @cindex MIPS option stack
287 @kindex @code{.set push}
288 @kindex @code{.set pop}
289 The directives @code{.set push} and @code{.set pop} may be used to save
290 and restore the current settings for all the options which are
291 controlled by @code{.set}. The @code{.set push} directive saves the
292 current settings on a stack. The @code{.set pop} directive pops the
293 stack and restores the settings.
295 These directives can be useful inside an macro which must change an
296 option such as the ISA level or instruction reordering but does not want
297 to change the state of the code which invoked the macro.
299 Traditional @sc{mips} assemblers do not support these directives.