1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
91 Generate code for a particular MIPS Instruction Set Architecture level.
92 @samp{-mips1} corresponds to the R2000 and R3000 processors,
93 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
94 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
95 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
96 @samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and
97 @samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
98 MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2,
99 MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. You
100 can also switch instruction sets during the assembly; see @ref{MIPS ISA,
101 Directives to override the ISA level}.
105 Some macros have different expansions for 32-bit and 64-bit registers.
106 The register sizes are normally inferred from the ISA and ABI, but these
107 flags force a certain group of registers to be treated as 32 bits wide at
108 all times. @samp{-mgp32} controls the size of general-purpose registers
109 and @samp{-mfp32} controls the size of floating-point registers.
111 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
112 of registers to be changed for parts of an object. The default value is
113 restored by @code{.set gp=default} and @code{.set fp=default}.
115 On some MIPS variants there is a 32-bit mode flag; when this flag is
116 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
117 save the 32-bit registers on a context switch, so it is essential never
118 to use the 64-bit registers.
122 Assume that 64-bit registers are available. This is provided in the
123 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
125 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
126 of registers to be changed for parts of an object. The default value is
127 restored by @code{.set gp=default} and @code{.set fp=default}.
130 Make no assumptions about whether 32-bit or 64-bit floating-point
131 registers are available. This is provided to support having modules
132 compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can
133 only be used with MIPS II and above.
135 The @code{.set fp=xx} directive allows a part of an object to be marked
136 as not making assumptions about 32-bit or 64-bit FP registers. The
137 default value is restored by @code{.set fp=default}.
140 @itemx -mno-odd-spreg
141 Enable use of floating-point operations on odd-numbered single-precision
142 registers when supported by the ISA. @samp{-mfpxx} implies
143 @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}
147 Generate code for the MIPS 16 processor. This is equivalent to putting
148 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
149 turns off this option.
152 @itemx -mno-micromips
153 Generate code for the microMIPS processor. This is equivalent to putting
154 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
155 turns off this option. This is equivalent to putting @code{.set nomicromips}
156 at the start of the assembly file.
159 @itemx -mno-smartmips
160 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
161 provides a number of new instructions which target smartcard and
162 cryptographic applications. This is equivalent to putting
163 @code{.set smartmips} at the start of the assembly file.
164 @samp{-mno-smartmips} turns off this option.
168 Generate code for the MIPS-3D Application Specific Extension.
169 This tells the assembler to accept MIPS-3D instructions.
170 @samp{-no-mips3d} turns off this option.
174 Generate code for the MDMX Application Specific Extension.
175 This tells the assembler to accept MDMX instructions.
176 @samp{-no-mdmx} turns off this option.
180 Generate code for the DSP Release 1 Application Specific Extension.
181 This tells the assembler to accept DSP Release 1 instructions.
182 @samp{-mno-dsp} turns off this option.
186 Generate code for the DSP Release 2 Application Specific Extension.
187 This option implies -mdsp.
188 This tells the assembler to accept DSP Release 2 instructions.
189 @samp{-mno-dspr2} turns off this option.
193 Generate code for the MT Application Specific Extension.
194 This tells the assembler to accept MT instructions.
195 @samp{-mno-mt} turns off this option.
199 Generate code for the MCU Application Specific Extension.
200 This tells the assembler to accept MCU instructions.
201 @samp{-mno-mcu} turns off this option.
205 Generate code for the MIPS SIMD Architecture Extension.
206 This tells the assembler to accept MSA instructions.
207 @samp{-mno-msa} turns off this option.
211 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
212 This tells the assembler to accept XPA instructions.
213 @samp{-mno-xpa} turns off this option.
217 Generate code for the Virtualization Application Specific Extension.
218 This tells the assembler to accept Virtualization instructions.
219 @samp{-mno-virt} turns off this option.
223 Only use 32-bit instruction encodings when generating code for the
224 microMIPS processor. This option inhibits the use of any 16-bit
225 instructions. This is equivalent to putting @code{.set insn32} at
226 the start of the assembly file. @samp{-mno-insn32} turns off this
227 option. This is equivalent to putting @code{.set noinsn32} at the
228 start of the assembly file. By default @samp{-mno-insn32} is
229 selected, allowing all instructions to be used.
233 Cause nops to be inserted if the read of the destination register
234 of an mfhi or mflo instruction occurs in the following two instructions.
237 @itemx -mno-fix-rm7000
238 Cause nops to be inserted if a dmult or dmultu instruction is
239 followed by a load instruction.
241 @item -mfix-loongson2f-jump
242 @itemx -mno-fix-loongson2f-jump
243 Eliminate instruction fetch from outside 256M region to work around the
244 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
245 the kernel may crash. The issue has been solved in latest processor
246 batches, but this fix has no side effect to them.
248 @item -mfix-loongson2f-nop
249 @itemx -mno-fix-loongson2f-nop
250 Replace nops by @code{or at,at,zero} to work around the Loongson2F
251 @samp{nop} errata. Without it, under extreme cases, the CPU might
252 deadlock. The issue has been solved in later Loongson2F batches, but
253 this fix has no side effect to them.
256 @itemx -mno-fix-vr4120
257 Insert nops to work around certain VR4120 errata. This option is
258 intended to be used on GCC-generated code: it is not designed to catch
259 all problems in hand-written assembler code.
262 @itemx -mno-fix-vr4130
263 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
267 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
270 @itemx -mno-fix-cn63xxp1
271 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
272 certain CN63XXP1 errata.
276 Generate code for the LSI R4010 chip. This tells the assembler to
277 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
278 etc.), and to not schedule @samp{nop} instructions around accesses to
279 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
284 Generate code for the MIPS R4650 chip. This tells the assembler to accept
285 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
286 instructions around accesses to the @samp{HI} and @samp{LO} registers.
287 @samp{-no-m4650} turns off this option.
293 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
294 R@var{nnnn} chip. This tells the assembler to accept instructions
295 specific to that chip, and to schedule for that chip's hazards.
297 @item -march=@var{cpu}
298 Generate code for a particular MIPS CPU. It is exactly equivalent to
299 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
300 understood. Valid @var{cpu} value are:
386 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
387 accepted as synonyms for @samp{@var{n}f1_1}. These values are
390 @item -mtune=@var{cpu}
391 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
392 identical to @samp{-march=@var{cpu}}.
394 @item -mabi=@var{abi}
395 Record which ABI the source code uses. The recognized arguments
396 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
402 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
403 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
405 @cindex @code{-nocpp} ignored (MIPS)
407 This option is ignored. It is accepted for command-line compatibility with
408 other assemblers, which use it to turn off C style preprocessing. With
409 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
410 @sc{gnu} assembler itself never runs the C preprocessor.
414 Disable or enable floating-point instructions. Note that by default
415 floating-point instructions are always allowed even with CPU targets
416 that don't have support for these instructions.
419 @itemx -mdouble-float
420 Disable or enable double-precision floating-point operations. Note
421 that by default double-precision floating-point operations are always
422 allowed even with CPU targets that don't have support for these
425 @item --construct-floats
426 @itemx --no-construct-floats
427 The @code{--no-construct-floats} option disables the construction of
428 double width floating point constants by loading the two halves of the
429 value into the two single width floating point registers that make up
430 the double width register. This feature is useful if the processor
431 support the FR bit in its status register, and this bit is known (by
432 the programmer) to be set. This bit prevents the aliasing of the double
433 width register by the single width registers.
435 By default @code{--construct-floats} is selected, allowing construction
436 of these floating point constants.
439 @itemx --no-relax-branch
440 The @samp{--relax-branch} option enables the relaxation of out-of-range
441 branches. Any branches whose target cannot be reached directly are
442 converted to a small instruction sequence including an inverse-condition
443 branch to the physically next instruction, and a jump to the original
444 target is inserted between the two instructions. In PIC code the jump
445 will involve further instructions for address calculation.
447 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
448 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
449 relaxation, because they have no complementing counterparts. They could
450 be relaxed with the use of a longer sequence involving another branch,
451 however this has not been implemented and if their target turns out of
452 reach, they produce an error even if branch relaxation is enabled.
454 Also no MIPS16 branches are ever relaxed.
456 By default @samp{--no-relax-branch} is selected, causing any out-of-range
457 branches to produce an error.
459 @cindex @option{-mnan=} command line option, MIPS
460 @item -mnan=@var{encoding}
461 This option indicates whether the source code uses the IEEE 2008
462 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
463 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
464 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
466 @option{-mnan=legacy} is the default if no @option{-mnan} option or
467 @code{.nan} directive is used.
471 @c FIXME! (1) reflect these options (next item too) in option summaries;
472 @c (2) stop teasing, say _which_ instructions expanded _how_.
473 @code{@value{AS}} automatically macro expands certain division and
474 multiplication instructions to check for overflow and division by zero. This
475 option causes @code{@value{AS}} to generate code to take a trap exception
476 rather than a break exception when an error is detected. The trap instructions
477 are only supported at Instruction Set Architecture level 2 and higher.
481 Generate code to take a break exception rather than a trap exception when an
482 error is detected. This is the default.
486 Control generation of @code{.pdr} sections. Off by default on IRIX, on
491 When generating code using the Unix calling conventions (selected by
492 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
493 which can go into a shared library. The @samp{-mno-shared} option
494 tells gas to generate code which uses the calling convention, but can
495 not go into a shared library. The resulting code is slightly more
496 efficient. This option only affects the handling of the
497 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
501 @section High-level assembly macros
503 MIPS assemblers have traditionally provided a wider range of
504 instructions than the MIPS architecture itself. These extra
505 instructions are usually referred to as ``macro'' instructions
506 @footnote{The term ``macro'' is somewhat overloaded here, since
507 these macros have no relation to those defined by @code{.macro},
508 @pxref{Macro,, @code{.macro}}.}.
510 Some MIPS macro instructions extend an underlying architectural instruction
511 while others are entirely new. An example of the former type is @code{and},
512 which allows the third operand to be either a register or an arbitrary
513 immediate value. Examples of the latter type include @code{bgt}, which
514 branches to the third operand when the first operand is greater than
515 the second operand, and @code{ulh}, which implements an unaligned
518 One of the most common extensions provided by macros is to expand
519 memory offsets to the full address range (32 or 64 bits) and to allow
520 symbolic offsets such as @samp{my_data + 4} to be used in place of
521 integer constants. For example, the architectural instruction
522 @code{lbu} allows only a signed 16-bit offset, whereas the macro
523 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
524 The implementation of these symbolic offsets depends on several factors,
525 such as whether the assembler is generating SVR4-style PIC (selected by
526 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
527 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
528 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
529 of small data accesses}).
531 @kindex @code{.set macro}
532 @kindex @code{.set nomacro}
533 Sometimes it is undesirable to have one assembly instruction expand
534 to several machine instructions. The directive @code{.set nomacro}
535 tells the assembler to warn when this happens. @code{.set macro}
536 restores the default behavior.
538 @cindex @code{at} register, MIPS
539 @kindex @code{.set at=@var{reg}}
540 Some macro instructions need a temporary register to store intermediate
541 results. This register is usually @code{$1}, also known as @code{$at},
542 but it can be changed to any core register @var{reg} using
543 @code{.set at=@var{reg}}. Note that @code{$at} always refers
544 to @code{$1} regardless of which register is being used as the
547 @kindex @code{.set at}
548 @kindex @code{.set noat}
549 Implicit uses of the temporary register in macros could interfere with
550 explicit uses in the assembly code. The assembler therefore warns
551 whenever it sees an explicit use of the temporary register. The directive
552 @code{.set noat} silences this warning while @code{.set at} restores
553 the default behavior. It is safe to use @code{.set noat} while
554 @code{.set nomacro} is in effect since single-instruction macros
555 never need a temporary register.
557 Note that while the @sc{gnu} assembler provides these macros for compatibility,
558 it does not make any attempt to optimize them with the surrounding code.
560 @node MIPS Symbol Sizes
561 @section Directives to override the size of symbols
563 @kindex @code{.set sym32}
564 @kindex @code{.set nosym32}
565 The n64 ABI allows symbols to have any 64-bit value. Although this
566 provides a great deal of flexibility, it means that some macros have
567 much longer expansions than their 32-bit counterparts. For example,
568 the non-PIC expansion of @samp{dla $4,sym} is usually:
573 daddiu $4,$4,%higher(sym)
574 daddiu $1,$1,%lo(sym)
579 whereas the 32-bit expansion is simply:
583 daddiu $4,$4,%lo(sym)
586 n64 code is sometimes constructed in such a way that all symbolic
587 constants are known to have 32-bit values, and in such cases, it's
588 preferable to use the 32-bit expansion instead of the 64-bit
591 You can use the @code{.set sym32} directive to tell the assembler
592 that, from this point on, all expressions of the form
593 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
594 have 32-bit values. For example:
603 will cause the assembler to treat @samp{sym}, @code{sym+16} and
604 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
605 addresses is not affected.
607 The directive @code{.set nosym32} ends a @code{.set sym32} block and
608 reverts to the normal behavior. It is also possible to change the
609 symbol size using the command-line options @option{-msym32} and
612 These options and directives are always accepted, but at present,
613 they have no effect for anything other than n64.
615 @node MIPS Small Data
616 @section Controlling the use of small data accesses
618 @c This section deliberately glosses over the possibility of using -G
619 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
620 @cindex small data, MIPS
621 @cindex @code{gp} register, MIPS
622 It often takes several instructions to load the address of a symbol.
623 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
624 of @samp{dla $4,addr} is usually:
628 daddiu $4,$4,%lo(addr)
631 The sequence is much longer when @samp{addr} is a 64-bit symbol.
632 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
634 In order to cut down on this overhead, most embedded MIPS systems
635 set aside a 64-kilobyte ``small data'' area and guarantee that all
636 data of size @var{n} and smaller will be placed in that area.
637 The limit @var{n} is passed to both the assembler and the linker
638 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
639 Assembler options}. Note that the same value of @var{n} must be used
640 when linking and when assembling all input files to the link; any
641 inconsistency could cause a relocation overflow error.
643 The size of an object in the @code{.bss} section is set by the
644 @code{.comm} or @code{.lcomm} directive that defines it. The size of
645 an external object may be set with the @code{.extern} directive. For
646 example, @samp{.extern sym,4} declares that the object at @code{sym}
647 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
649 When no @option{-G} option is given, the default limit is 8 bytes.
650 The option @option{-G 0} prevents any data from being automatically
653 It is also possible to mark specific objects as small by putting them
654 in the special sections @code{.sdata} and @code{.sbss}, which are
655 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
656 The toolchain will treat such data as small regardless of the
659 On startup, systems that support a small data area are expected to
660 initialize register @code{$28}, also known as @code{$gp}, in such a
661 way that small data can be accessed using a 16-bit offset from that
662 register. For example, when @samp{addr} is small data,
663 the @samp{dla $4,addr} instruction above is equivalent to:
666 daddiu $4,$28,%gp_rel(addr)
669 Small data is not supported for SVR4-style PIC.
672 @section Directives to override the ISA level
674 @cindex MIPS ISA override
675 @kindex @code{.set mips@var{n}}
676 @sc{gnu} @code{@value{AS}} supports an additional directive to change
677 the MIPS Instruction Set Architecture level on the fly: @code{.set
678 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
679 32r5, 64, 64r2, 64r3 or 64r5.
680 The values other than 0 make the assembler accept instructions
681 for the corresponding ISA level, from that point on in the
682 assembly. @code{.set mips@var{n}} affects not only which instructions
683 are permitted, but also how certain macros are expanded. @code{.set
684 mips0} restores the ISA level to its original level: either the
685 level you selected with command line options, or the default for your
686 configuration. You can use this feature to permit specific MIPS III
687 instructions while assembling in 32 bit mode. Use this directive with
690 @cindex MIPS CPU override
691 @kindex @code{.set arch=@var{cpu}}
692 The @code{.set arch=@var{cpu}} directive provides even finer control.
693 It changes the effective CPU target and allows the assembler to use
694 instructions specific to a particular CPU. All CPUs supported by the
695 @samp{-march} command line option are also selectable by this directive.
696 The original value is restored by @code{.set arch=default}.
698 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
699 in which it will assemble instructions for the MIPS 16 processor. Use
700 @code{.set nomips16} to return to normal 32 bit mode.
702 Traditional MIPS assemblers do not support this directive.
704 The directive @code{.set micromips} puts the assembler into microMIPS mode,
705 in which it will assemble instructions for the microMIPS processor. Use
706 @code{.set nomicromips} to return to normal 32 bit mode.
708 Traditional MIPS assemblers do not support this directive.
710 @node MIPS assembly options
711 @section Directives to control code generation
713 @cindex MIPS directives to override command line options
714 @kindex @code{.module}
715 The @code{.module} directive allows command line options to be set directly
716 from assembly. The format of the directive matches the @code{.set}
717 directive but only those options which are relevant to a whole module are
718 supported. The effect of a @code{.module} directive is the same as the
719 corresponding command line option. Where @code{.set} directives support
720 returning to a default then the @code{.module} directives do not as they
723 These module-level directives must appear first in assembly.
725 Traditional MIPS assemblers do not support this directive.
727 @cindex MIPS 32-bit microMIPS instruction generation override
728 @kindex @code{.set insn32}
729 @kindex @code{.set noinsn32}
730 The directive @code{.set insn32} makes the assembler only use 32-bit
731 instruction encodings when generating code for the microMIPS processor.
732 This directive inhibits the use of any 16-bit instructions from that
733 point on in the assembly. The @code{.set noinsn32} directive allows
734 16-bit instructions to be accepted.
736 Traditional MIPS assemblers do not support this directive.
738 @node MIPS autoextend
739 @section Directives for extending MIPS 16 bit instructions
741 @kindex @code{.set autoextend}
742 @kindex @code{.set noautoextend}
743 By default, MIPS 16 instructions are automatically extended to 32 bits
744 when necessary. The directive @code{.set noautoextend} will turn this
745 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
746 must be explicitly extended with the @code{.e} modifier (e.g.,
747 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
748 to once again automatically extend instructions when necessary.
750 This directive is only meaningful when in MIPS 16 mode. Traditional
751 MIPS assemblers do not support this directive.
754 @section Directive to mark data as an instruction
757 The @code{.insn} directive tells @code{@value{AS}} that the following
758 data is actually instructions. This makes a difference in MIPS 16 and
759 microMIPS modes: when loading the address of a label which precedes
760 instructions, @code{@value{AS}} automatically adds 1 to the value, so
761 that jumping to the loaded address will do the right thing.
763 @kindex @code{.global}
764 The @code{.global} and @code{.globl} directives supported by
765 @code{@value{AS}} will by default mark the symbol as pointing to a
766 region of data not code. This means that, for example, any
767 instructions following such a symbol will not be disassembled by
768 @code{objdump} as it will regard them as data. To change this
769 behaviour an optional section name can be placed after the symbol name
770 in the @code{.global} directive. If this section exists and is known
771 to be a code section, then the symbol will be marked as poiting at
772 code not data. Ie the syntax for the directive is:
774 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
776 Here is a short example:
779 .global foo .text, bar, baz .data
790 @section Directives to control the FP ABI
792 * MIPS FP ABI History:: History of FP ABIs
793 * MIPS FP ABI Variants:: Supported FP ABIs
794 * MIPS FP ABI Selection:: Automatic selection of FP ABI
795 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
798 @node MIPS FP ABI History
799 @subsection History of FP ABIs
800 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
801 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
802 The MIPS ABIs support a variety of different floating-point extensions
803 where calling-convention and register sizes vary for floating-point data.
804 The extensions exist to support a wide variety of optional architecture
805 features. The resulting ABI variants are generally incompatible with each
806 other and must be tracked carefully.
808 Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}}
809 directive is used to indicate which ABI is in use by a specific module.
810 It was then left to the user to ensure that command line options and the
811 selected ABI were compatible with some potential for inconsistencies.
813 @node MIPS FP ABI Variants
814 @subsection Supported FP ABIs
815 The supported floating-point ABI variants are:
818 @item 0 - No floating-point
819 This variant is used to indicate that floating-point is not used within
820 the module at all and therefore has no impact on the ABI. This is the
823 @item 1 - Double-precision
824 This variant indicates that double-precision support is used. For 64-bit
825 ABIs this means that 64-bit wide floating-point registers are required.
826 For 32-bit ABIs this means that 32-bit wide floating-point registers are
827 required and double-precision operations use pairs of registers.
829 @item 2 - Single-precision
830 This variant indicates that single-precision support is used. Double
831 precision operations will be supported via soft-float routines.
834 This variant indicates that although floating-point support is used all
835 operations are emulated in software. This means the ABI is modified to
836 pass all floating-point data in general-purpose registers.
839 This variant existed as an initial attempt at supporting 64-bit wide
840 floating-point registers for O32 ABI on a MIPS32r2 cpu. This has been
841 superceded by @value{5}, @value{6} and @value{7}.
843 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
844 This variant is used by 32-bit ABIs to indicate that the floating-point
845 code in the module has been designed to operate correctly with either
846 32-bit wide or 64-bit wide floating-point registers. Double-precision
847 support is used. Only O32 currently supports this variant and requires
848 a minimum architecture of MIPS II.
850 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
851 This variant is used by 32-bit ABIs to indicate that the floating-point
852 code in the module requires 64-bit wide floating-point registers.
853 Double-precision support is used. Only O32 currently supports this
854 variant and requires a minimum architecture of MIPS32r2.
856 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
857 This variant is used by 32-bit ABIs to indicate that the floating-point
858 code in the module requires 64-bit wide floating-point registers.
859 Double-precision support is used. This differs from the previous ABI
860 as it restricts use of odd-numbered single-precision registers. Only
861 O32 currently supports this variant and requires a minimum architecture
865 @node MIPS FP ABI Selection
866 @subsection Automatic selection of FP ABI
867 @cindex @code{.module fp=@var{nn}} directive, MIPS
868 In order to simplify and add safety to the process of selecting the
869 correct floating-point ABI, the assembler will automatically infer the
870 correct @code{.gnu_attribute 4, @var{n}} directive based on command line
871 options and @code{.module} overrides. Where an explicit
872 @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning
873 will be raised if it does not match an inferred setting.
875 The floating-point ABI is inferred as follows. If @samp{-msoft-float}
876 has been used the module will be marked as soft-float. If
877 @samp{-msingle-float} has been used then the module will be marked as
878 single-precision. The remaining ABIs are then selected based
879 on the FP register width. Double-precision is selected if the width
880 of GP and FP registers match and the special double-precision variants
881 for 32-bit ABIs are then selected depending on @samp{-mfpxx},
882 @samp{-mfp64} and @samp{-mno-odd-spreg}.
884 @node MIPS FP ABI Compatibility
885 @subsection Linking different FP ABI variants
886 Modules using the default FP ABI (no floating-point) can be linked with
887 any other (singular) FP ABI variant.
889 Special compatibility support exists for O32 with the four
890 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
891 designed to be compatible with the standard double-precision ABI and the
892 @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be
893 built as @samp{-mfpxx} to ensure the maximum compatibility with other
894 modules produced for more specific needs. The only FP ABIs which cannot
895 be linked together are the standard double-precision ABI and the full
896 @samp{-mfp64} ABI with @samp{-modd-spreg}.
898 @node MIPS NaN Encodings
899 @section Directives to record which NaN encoding is being used
901 @cindex MIPS IEEE 754 NaN data encoding selection
902 @cindex @code{.nan} directive, MIPS
903 The IEEE 754 floating-point standard defines two types of not-a-number
904 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
905 of the standard did not specify how these two types should be
906 distinguished. Most implementations followed the i387 model, in which
907 the first bit of the significand is set for quiet NaNs and clear for
908 signalling NaNs. However, the original MIPS implementation assigned the
909 opposite meaning to the bit, so that it was set for signalling NaNs and
910 clear for quiet NaNs.
912 The 2008 revision of the standard formally suggested the i387 choice
913 and as from Sep 2012 the current release of the MIPS architecture
914 therefore optionally supports that form. Code that uses one NaN encoding
915 would usually be incompatible with code that uses the other NaN encoding,
916 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
917 encoding is being used.
919 Assembly files can use the @code{.nan} directive to select between the
920 two encodings. @samp{.nan 2008} says that the assembly file uses the
921 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
922 the original MIPS encoding. If several @code{.nan} directives are given,
923 the final setting is the one that is used.
925 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
926 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
927 respectively. However, any @code{.nan} directive overrides the
928 command-line setting.
930 @samp{.nan legacy} is the default if no @code{.nan} directive or
931 @option{-mnan} option is given.
933 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
934 therefore these directives do not affect code generation. They simply
935 control the setting of the @code{EF_MIPS_NAN2008} flag.
937 Traditional MIPS assemblers do not support these directives.
939 @node MIPS Option Stack
940 @section Directives to save and restore options
942 @cindex MIPS option stack
943 @kindex @code{.set push}
944 @kindex @code{.set pop}
945 The directives @code{.set push} and @code{.set pop} may be used to save
946 and restore the current settings for all the options which are
947 controlled by @code{.set}. The @code{.set push} directive saves the
948 current settings on a stack. The @code{.set pop} directive pops the
949 stack and restores the settings.
951 These directives can be useful inside an macro which must change an
952 option such as the ISA level or instruction reordering but does not want
953 to change the state of the code which invoked the macro.
955 Traditional MIPS assemblers do not support these directives.
957 @node MIPS ASE Instruction Generation Overrides
958 @section Directives to control generation of MIPS ASE instructions
960 @cindex MIPS MIPS-3D instruction generation override
961 @kindex @code{.set mips3d}
962 @kindex @code{.set nomips3d}
963 The directive @code{.set mips3d} makes the assembler accept instructions
964 from the MIPS-3D Application Specific Extension from that point on
965 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
966 instructions from being accepted.
968 @cindex SmartMIPS instruction generation override
969 @kindex @code{.set smartmips}
970 @kindex @code{.set nosmartmips}
971 The directive @code{.set smartmips} makes the assembler accept
972 instructions from the SmartMIPS Application Specific Extension to the
973 MIPS32 ISA from that point on in the assembly. The
974 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
977 @cindex MIPS MDMX instruction generation override
978 @kindex @code{.set mdmx}
979 @kindex @code{.set nomdmx}
980 The directive @code{.set mdmx} makes the assembler accept instructions
981 from the MDMX Application Specific Extension from that point on
982 in the assembly. The @code{.set nomdmx} directive prevents MDMX
983 instructions from being accepted.
985 @cindex MIPS DSP Release 1 instruction generation override
986 @kindex @code{.set dsp}
987 @kindex @code{.set nodsp}
988 The directive @code{.set dsp} makes the assembler accept instructions
989 from the DSP Release 1 Application Specific Extension from that point
990 on in the assembly. The @code{.set nodsp} directive prevents DSP
991 Release 1 instructions from being accepted.
993 @cindex MIPS DSP Release 2 instruction generation override
994 @kindex @code{.set dspr2}
995 @kindex @code{.set nodspr2}
996 The directive @code{.set dspr2} makes the assembler accept instructions
997 from the DSP Release 2 Application Specific Extension from that point
998 on in the assembly. This dirctive implies @code{.set dsp}. The
999 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1002 @cindex MIPS MT instruction generation override
1003 @kindex @code{.set mt}
1004 @kindex @code{.set nomt}
1005 The directive @code{.set mt} makes the assembler accept instructions
1006 from the MT Application Specific Extension from that point on
1007 in the assembly. The @code{.set nomt} directive prevents MT
1008 instructions from being accepted.
1010 @cindex MIPS MCU instruction generation override
1011 @kindex @code{.set mcu}
1012 @kindex @code{.set nomcu}
1013 The directive @code{.set mcu} makes the assembler accept instructions
1014 from the MCU Application Specific Extension from that point on
1015 in the assembly. The @code{.set nomcu} directive prevents MCU
1016 instructions from being accepted.
1018 @cindex MIPS SIMD Architecture instruction generation override
1019 @kindex @code{.set msa}
1020 @kindex @code{.set nomsa}
1021 The directive @code{.set msa} makes the assembler accept instructions
1022 from the MIPS SIMD Architecture Extension from that point on
1023 in the assembly. The @code{.set nomsa} directive prevents MSA
1024 instructions from being accepted.
1026 @cindex Virtualization instruction generation override
1027 @kindex @code{.set virt}
1028 @kindex @code{.set novirt}
1029 The directive @code{.set virt} makes the assembler accept instructions
1030 from the Virtualization Application Specific Extension from that point
1031 on in the assembly. The @code{.set novirt} directive prevents Virtualization
1032 instructions from being accepted.
1034 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1035 @kindex @code{.set xpa}
1036 @kindex @code{.set noxpa}
1037 The directive @code{.set xpa} makes the assembler accept instructions
1038 from the XPA Extension from that point on in the assembly. The
1039 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1041 Traditional MIPS assemblers do not support these directives.
1043 @node MIPS Floating-Point
1044 @section Directives to override floating-point options
1046 @cindex Disable floating-point instructions
1047 @kindex @code{.set softfloat}
1048 @kindex @code{.set hardfloat}
1049 The directives @code{.set softfloat} and @code{.set hardfloat} provide
1050 finer control of disabling and enabling float-point instructions.
1051 These directives always override the default (that hard-float
1052 instructions are accepted) or the command-line options
1053 (@samp{-msoft-float} and @samp{-mhard-float}).
1055 @cindex Disable single-precision floating-point operations
1056 @kindex @code{.set singlefloat}
1057 @kindex @code{.set doublefloat}
1058 The directives @code{.set singlefloat} and @code{.set doublefloat}
1059 provide finer control of disabling and enabling double-precision
1060 float-point operations. These directives always override the default
1061 (that double-precision operations are accepted) or the command-line
1062 options (@samp{-msingle-float} and @samp{-mdouble-float}).
1064 Traditional MIPS assemblers do not support these directives.
1067 @section Syntactical considerations for the MIPS assembler
1069 * MIPS-Chars:: Special Characters
1073 @subsection Special Characters
1075 @cindex line comment character, MIPS
1076 @cindex MIPS line comment character
1077 The presence of a @samp{#} on a line indicates the start of a comment
1078 that extends to the end of the current line.
1080 If a @samp{#} appears as the first character of a line, the whole line
1081 is treated as a comment, but in this case the line can also be a
1082 logical line number directive (@pxref{Comments}) or a
1083 preprocessor control command (@pxref{Preprocessing}).
1085 @cindex line separator, MIPS
1086 @cindex statement separator, MIPS
1087 @cindex MIPS line separator
1088 The @samp{;} character can be used to separate statements on the same
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