1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2003
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter M32R Dependent Features
11 @node Machine Dependencies
12 @chapter M32R Dependent Features
17 * M32R-Opts:: M32R Options
18 * M32R-Directives:: M32R Directives
19 * M32R-Warnings:: M32R Warnings
28 The Renease M32R version of @code{@value{AS}} has a few machine
34 @cindex @samp{-m32rx} option, M32RX
35 @cindex architecture options, M32RX
36 @cindex M32R architecture options
37 @code{@value{AS}} can assemble code for several different members of the
38 Renesas M32R family. Normally the default is to assemble code for
39 the M32R microprocessor. This option may be used to change the default
40 to the M32RX microprocessor, which adds some more instructions to the
41 basic M32R instruction set, and some additional parameters to some of
42 the original instructions.
45 @cindex @samp{-m32rx} option, M32R2
46 @cindex architecture options, M32R2
47 @cindex M32R architecture options
48 This option changes the target processor to the the M32R2
52 @cindex @samp{-m32r} option, M32R
53 @cindex architecture options, M32R
54 @cindex M32R architecture options
55 This option can be used to restore the assembler's default behaviour of
56 assembling for the M32R microprocessor. This can be useful if the
57 default has been changed by a previous command line option.
60 @cindex @code{-little} option, M32R
61 This option tells the assembler to produce little-endian code and
62 data. The default is dependent upon how the toolchain was
66 @cindex @code{-EL} option, M32R
67 This is a synonum for @emph{-little}.
70 @cindex @code{-big} option, M32R
71 This option tells the assembler to produce big-endian code and
75 @cindex @code{-EB} option, M32R
76 This is a synonum for @emph{-big}.
79 @cindex @code{-parallel} option, M32RX
80 This option tells the assembler to attempts to combine two sequential
81 instructions into a single, parallel instruction, where it is legal to
85 @cindex @code{-no-parallel} option, M32RX
86 This option disables a previously enabled @emph{-parallel} option.
89 @cindex @code{-O} option, M32RX
90 This option tells the assembler to attempt to optimize the
91 instructions that it produces. This includes filling delay slots and
92 converting sequential instructions into parallel ones. This option
93 implies @emph{-parallel}.
95 @item -warn-explicit-parallel-conflicts
96 @cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
97 Instructs @code{@value{AS}} to produce warning messages when
98 questionable parallel instructions are encountered. This option is
99 enabled by default, but @code{@value{GCC}} disables it when it invokes
100 @code{@value{AS}} directly. Questionable instructions are those whoes
101 behaviour would be different if they were executed sequentially. For
102 example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
103 different result from @samp{mv r1, r2 \n mv r3, r1} since the former
104 moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
108 @cindex @samp{-Wp} option, M32RX
109 This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts}
112 @item -no-warn-explicit-parallel-conflicts
113 @cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX
114 Instructs @code{@value{AS}} not to produce warning messages when
115 questionable parallel instructions are encountered.
118 @cindex @samp{-Wnp} option, M32RX
119 This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
122 @item -error-explicit-parallel-conflicts
123 @cindex @samp{-error-explicit-parallel-conflicts} option, M32RX
124 This option performs the same thing as the
125 @emph{-warn-explicit-parallel-conflicts} expcept that instead of
126 warning messages being produced, error messages will be produced. If
127 any error messages are generated then GAS will not produce an output
130 @item -no-error-explicit-parallel-conflicts
131 @cindex @samp{-no-error-explicit-parallel-conflicts} option, M32RX
132 This option disables a previously enabled
133 @emph{-error-explicit-parallel-conflicts} option.
136 @cindex @samp{-Ep} option, M32RX
137 This is a shorter synonym for the @emph{-error-explicit-parallel-conflicts}
141 @cindex @samp{-Enp} option, M32RX
142 This is a shorter synonym for the @emph{-no-error-explicit-parallel-conflicts}
145 @item -warn-unmatched-high
146 @cindex @samp{-warn-unmatched-high} option, M32R
147 This option tells the assembler to produce a warning message if a
148 @code{.high} pseudo op is encountered without a mathcing @code{.low}
149 pseudo op. The presence of such an unmatches pseudo op usually
150 indicates a programming error.
152 @item -no-warn-unmatched-high
153 @cindex @samp{-no-warn-unmatched-high} option, M32R
154 Disables a previously enabled @emph{-warn-unmatched-high} option.
157 @cindex @samp{-Wuh} option, M32RX
158 This is a shorter synonym for the @emph{-warn-unmatched-high} option.
161 @cindex @samp{-Wnuh} option, M32RX
162 This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
166 @node M32R-Directives
167 @section M32R Directives
168 @cindex directives, M32R
169 @cindex M32R directives
171 The Renease M32R version of @code{@value{AS}} has a few architecture
176 @cindex @code{low} directive, M32R
177 @item low @var{expression}
178 The @code{low} directive computes the value of its expression and
179 places the lower 16-bits of the result into the immediate-field of the
180 instruction. For example:
183 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
184 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
187 @item high @var{expression}
188 @cindex @code{high} directive, M32R
189 The @code{high} directive computes the value of its expression and
190 places the upper 16-bits of the result into the immediate-field of the
191 instruction. For example:
194 seth r0, #high(0x12345678) ; compute r0 = 0x12340000
195 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
198 @item shigh @var{expression}
199 @cindex @code{shigh} directive, M32R
200 The @code{shigh} directive is very similar to the @code{high}
201 directive. It also computes the value of its expression and places
202 the upper 16-bits of the result into the immediate-field of the
203 instruction. The difference is that @code{shigh} also checks to see
204 if the lower 16-bits could be interpreted as a signed number, and if
205 so it assumes that a borrow will occur from the upper-16 bits. To
206 compensate for this the @code{shigh} directive pre-biases the upper
207 16 bit value by adding one to it. For example:
212 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
213 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
216 In the second example the lower 16-bits are 0x8000. If these are
217 treated as a signed value and sign extended to 32-bits then the value
218 becomes 0xffff8000. If this value is then added to 0x00010000 then
219 the result is 0x00008000.
221 This behaviour is to allow for the different semantics of the
222 @code{or3} and @code{add3} instructions. The @code{or3} instruction
223 treats its 16-bit immediate argument as unsigned whereas the
224 @code{add3} treats its 16-bit immediate as a signed value. So for
228 seth r0, #shigh(0x00008000)
229 add3 r0, r0, #low(0x00008000)
232 Produces the correct result in r0, whereas:
235 seth r0, #shigh(0x00008000)
236 or3 r0, r0, #low(0x00008000)
239 Stores 0xffff8000 into r0.
241 Note - the @code{shigh} directive does not know where in the assembly
242 source code the lower 16-bits of the value are going set, so it cannot
243 check to make sure that an @code{or3} instruction is being used rather
244 than an @code{add3} instruction. It is up to the programmer to make
245 sure that correct directives are used.
247 @cindex @code{.m32r} directive, M32R
249 The directive performs a similar thing as the @emph{-m32r} command
250 line option. It tells the assembler to only accept M32R instructions
251 from now on. An instructions from later M32R architectures are
254 @cindex @code{.m32rx} directive, M32RX
256 The directive performs a similar thing as the @emph{-m32rx} command
257 line option. It tells the assembler to start accepting the extra
258 instructions in the M32RX ISA as well as the ordinary M32R ISA.
260 @cindex @code{.m32r2} directive, M32R2
262 The directive performs a similar thing as the @emph{-m32r2} command
263 line option. It tells the assembler to start accepting the extra
264 instructions in the M32R2 ISA as well as the ordinary M32R ISA.
266 @cindex @code{.little} directive, M32RX
268 The directive performs a similar thing as the @emph{-little} command
269 line option. It tells the assembler to start producing little-endian
270 code and data. This option should be used with care as producing
271 mixed-endian binary files is frought with danger.
273 @cindex @code{.big} directive, M32RX
275 The directive performs a similar thing as the @emph{-big} command
276 line option. It tells the assembler to start producing big-endian
277 code and data. This option should be used with care as producing
278 mixed-endian binary files is frought with danger.
283 @section M32R Warnings
285 @cindex warnings, M32R
286 @cindex M32R warnings
288 There are several warning and error messages that can be produced by
289 @code{@value{AS}} which are specific to the M32R:
293 @item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
294 This message is only produced if warnings for explicit parallel
295 conflicts have been enabled. It indicates that the assembler has
296 encountered a parallel instruction in which the destination register of
297 the left hand instruction is used as an input register in the right hand
298 instruction. For example in this code fragment
299 @samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
300 move instruction and the input to the neg instruction.
302 @item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
303 This message is only produced if warnings for explicit parallel
304 conflicts have been enabled. It indicates that the assembler has
305 encountered a parallel instruction in which the destination register of
306 the right hand instruction is used as an input register in the left hand
307 instruction. For example in this code fragment
308 @samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
309 neg instruction and the input to the move instruction.
311 @item instruction @samp{...} is for the M32RX only
312 This message is produced when the assembler encounters an instruction
313 which is only supported by the M32Rx processor, and the @samp{-m32rx}
314 command line flag has not been specified to allow assembly of such
317 @item unknown instruction @samp{...}
318 This message is produced when the assembler encounters an instruction
319 which it does not recognise.
321 @item only the NOP instruction can be issued in parallel on the m32r
322 This message is produced when the assembler encounters a parallel
323 instruction which does not involve a NOP instruction and the
324 @samp{-m32rx} command line flag has not been specified. Only the M32Rx
325 processor is able to execute two instructions in parallel.
327 @item instruction @samp{...} cannot be executed in parallel.
328 This message is produced when the assembler encounters a parallel
329 instruction which is made up of one or two instructions which cannot be
330 executed in parallel.
332 @item Instructions share the same execution pipeline
333 This message is produced when the assembler encounters a parallel
334 instruction whoes components both use the same execution pipeline.
336 @item Instructions write to the same destination register.
337 This message is produced when the assembler encounters a parallel
338 instruction where both components attempt to modify the same register.
339 For example these code fragments will produce this message:
340 @samp{mv r1, r2 || neg r1, r3}
341 @samp{jl r0 || mv r14, r1}
342 @samp{st r2, @@-r1 || mv r1, r3}
343 @samp{mv r1, r2 || ld r0, @@r1+}
344 @samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)