1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
29 @cindex ARM options (none)
30 @cindex options for ARM (none)
34 @cindex @code{-mcpu=} command line option, ARM
35 @item -mcpu=@var{processor}[+@var{extension}@dots]
36 This option specifies the target processor. The assembler will issue an
37 error message if an attempt is made to assemble an instruction which
38 will not execute on the target processor. The following processor names are
92 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
93 @code{i80200} (Intel XScale processor)
96 The special name @code{all} may be used to allow the
97 assembler to accept instructions valid for any ARM processor.
99 In addition to the basic instruction set, the assembler can be told to
100 accept various extension mnemonics that extend the processor using the
101 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
102 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
103 are currently supported:
108 @cindex @code{-march=} command line option, ARM
109 @item -march=@var{architecture}[+@var{extension}@dots]
110 This option specifies the target architecture. The assembler will issue
111 an error message if an attempt is made to assemble an instruction which
112 will not execute on the target architecture. The following architecture
113 names are recognized:
131 If both @code{-mcpu} and
132 @code{-march} are specified, the assembler will use
133 the setting for @code{-mcpu}.
135 The architecture option can be extended with the same instruction set
136 extension options as the @code{-mcpu} option.
138 @cindex @code{-mfpu=} command line option, ARM
139 @item -mfpu=@var{floating-point-format}
141 This option specifies the floating point format to assemble for. The
142 assembler will issue an error message if an attempt is made to assemble
143 an instruction which will not execute on the target floating point unit.
144 The following format options are recognized:
162 In addition to determining which instructions are assembled, this option
163 also affects the way in which the @code{.double} assembler directive behaves
164 when assembling little-endian code.
166 The default is dependent on the processor selected. For Architecture 5 or
167 later, the default is to assembler for VFP instructions; for earlier
168 architectures the default is to assemble for FPA instructions.
170 @cindex @code{-mthumb} command line option, ARM
172 This option specifies that the assembler should start assembling Thumb
173 instructions; that is, it should behave as though the file starts with a
174 @code{.code 16} directive.
176 @cindex @code{-mthumb-interwork} command line option, ARM
177 @item -mthumb-interwork
178 This option specifies that the output generated by the assembler should
179 be marked as supporting interworking.
181 @cindex @code{-mapcs} command line option, ARM
182 @item -mapcs @code{[26|32]}
183 This option specifies that the output generated by the assembler should
184 be marked as supporting the indicated version of the Arm Procedure.
187 @cindex @code{-matpcs} command line option, ARM
189 This option specifies that the output generated by the assembler should
190 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
191 enabled this option will cause the assembler to create an empty
192 debugging section in the object file called .arm.atpcs. Debuggers can
193 use this to determine the ABI being used by.
195 @cindex @code{-mapcs-float} command line option, ARM
197 This indicates the the floating point variant of the APCS should be
198 used. In this variant floating point arguments are passed in FP
199 registers rather than integer registers.
201 @cindex @code{-mapcs-reentrant} command line option, ARM
202 @item -mapcs-reentrant
203 This indicates that the reentrant variant of the APCS should be used.
204 This variant supports position independent code.
206 @cindex @code{-EB} command line option, ARM
208 This option specifies that the output generated by the assembler should
209 be marked as being encoded for a big-endian processor.
211 @cindex @code{-EL} command line option, ARM
213 This option specifies that the output generated by the assembler should
214 be marked as being encoded for a little-endian processor.
216 @cindex @code{-k} command line option, ARM
217 @cindex PIC code generation for ARM
219 This option specifies that the output of the assembler should be marked
220 as position-independent code (PIC).
222 @cindex @code{-moabi} command line option, ARM
224 This indicates that the code should be assembled using the old ARM ELF
225 conventions, based on a beta release release of the ARM-ELF
226 specifications, rather than the default conventions which are based on
227 the final release of the ARM-ELF specifications.
235 * ARM-Chars:: Special Characters
236 * ARM-Regs:: Register Names
240 @subsection Special Characters
242 @cindex line comment character, ARM
243 @cindex ARM line comment character
244 The presence of a @samp{@@} on a line indicates the start of a comment
245 that extends to the end of the current line. If a @samp{#} appears as
246 the first character of a line, the whole line is treated as a comment.
248 @cindex line separator, ARM
249 @cindex statement separator, ARM
250 @cindex ARM line separator
251 The @samp{;} character can be used instead of a newline to separate
254 @cindex immediate character, ARM
255 @cindex ARM immediate character
256 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
258 @cindex identifiers, ARM
259 @cindex ARM identifiers
260 *TODO* Explain about /data modifier on symbols.
263 @subsection Register Names
265 @cindex ARM register names
266 @cindex register names, ARM
267 *TODO* Explain about ARM register naming, and the predefined names.
269 @node ARM Floating Point
270 @section Floating Point
272 @cindex floating point, ARM (@sc{ieee})
273 @cindex ARM floating point (@sc{ieee})
274 The ARM family uses @sc{ieee} floating-point numbers.
279 @section ARM Machine Directives
281 @cindex machine directives, ARM
282 @cindex ARM machine directives
285 @cindex @code{align} directive, ARM
286 @item .align @var{expression} [, @var{expression}]
287 This is the generic @var{.align} directive. For the ARM however if the
288 first argument is zero (ie no alignment is needed) the assembler will
289 behave as if the argument had been 2 (ie pad to the next four byte
290 boundary). This is for compatability with ARM's own assembler.
292 @cindex @code{req} directive, ARM
293 @item @var{name} .req @var{register name}
294 This creates an alias for @var{register name} called @var{name}. For
301 @cindex @code{code} directive, ARM
302 @item .code @code{[16|32]}
303 This directive selects the instruction set being generated. The value 16
304 selects Thumb, with the value 32 selecting ARM.
306 @cindex @code{thumb} directive, ARM
308 This performs the same action as @var{.code 16}.
310 @cindex @code{arm} directive, ARM
312 This performs the same action as @var{.code 32}.
314 @cindex @code{force_thumb} directive, ARM
316 This directive forces the selection of Thumb instructions, even if the
317 target processor does not support those instructions
319 @cindex @code{thumb_func} directive, ARM
321 This directive specifies that the following symbol is the name of a
322 Thumb encoded function. This information is necessary in order to allow
323 the assembler and linker to generate correct code for interworking
324 between Arm and Thumb instructions and should be used even if
325 interworking is not going to be performed. The presence of this
326 directive also implies @code{.thumb}
328 @cindex @code{thumb_set} directive, ARM
330 This performs the equivalent of a @code{.set} directive in that it
331 creates a symbol which is an alias for another symbol (possibly not yet
332 defined). This directive also has the added property in that it marks
333 the aliased symbol as being a thumb function entry point, in the same
334 way that the @code{.thumb_func} directive does.
336 @cindex @code{.ltorg} directive, ARM
338 This directive causes the current contents of the literal pool to be
339 dumped into the current section (which is assumed to be the .text
340 section) at the current location (aligned to a word boundary).
342 @cindex @code{.pool} directive, ARM
344 This is a synonym for .ltorg.
352 @cindex opcodes for ARM
353 @code{@value{AS}} implements all the standard ARM opcodes. It also
354 implements several pseudo opcodes, including several synthetic load
359 @cindex @code{NOP} pseudo op, ARM
365 This pseudo op will always evaluate to a legal ARM instruction that does
366 nothing. Currently it will evaluate to MOV r0, r0.
368 @cindex @code{LDR reg,=<label>} pseudo op, ARM
371 ldr <register> , = <expression>
374 If expression evaluates to a numeric constant then a MOV or MVN
375 instruction will be used in place of the LDR instruction, if the
376 constant can be generated by either of these instructions. Otherwise
377 the constant will be placed into the nearest literal pool (if it not
378 already there) and a PC relative LDR instruction will be generated.
380 @cindex @code{ADR reg,<label>} pseudo op, ARM
383 adr <register> <label>
386 This instruction will load the address of @var{label} into the indicated
387 register. The instruction will evaluate to a PC relative ADD or SUB
388 instruction depending upon where the label is located. If the label is
389 out of range, or if it is not defined in the same file (and section) as
390 the ADR instruction, then an error will be generated. This instruction
391 will not make use of the literal pool.
393 @cindex @code{ADRL reg,<label>} pseudo op, ARM
396 adrl <register> <label>
399 This instruction will load the address of @var{label} into the indicated
400 register. The instruction will evaluate to one or two PC relative ADD
401 or SUB instructions depending upon where the label is located. If a
402 second instruction is not needed a NOP instruction will be generated in
403 its place, so that this instruction is always 8 bytes long.
405 If the label is out of range, or if it is not defined in the same file
406 (and section) as the ADRL instruction, then an error will be generated.
407 This instruction will not make use of the literal pool.
411 For information on the ARM or Thumb instruction sets, see @cite{ARM
412 Software Development Toolkit Reference Manual}, Advanced RISC Machines