1 @c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
28 @cindex ARM options (none)
29 @cindex options for ARM (none)
31 @cindex @code{-marm} command line option, ARM
32 @item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}]
33 This option specifies the target processor. The assembler will issue an
34 error message if an attempt is made to assemble an instruction which
35 will not execute on the target processor.
36 @cindex @code{-marmv} command line option, ARM
37 @item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}]
38 This option specifies the target architecture. The assembler will issue
39 an error message if an attempt is made to assemble an instruction which
40 will not execute on the target architecture.
41 @cindex @code{-mthumb} command line option, ARM
43 This option specifies that only Thumb instructions should be assembled.
44 @cindex @code{-mall} command line option, ARM
46 This option specifies that any Arm or Thumb instruction should be assembled.
47 @cindex @code{-mfpa} command line option, ARM
48 @item -mfpa [@var{10}|@var{11}]
49 This option specifies the floating point architecture in use on the
51 @cindex @code{-mfpe-old} command line option, ARM
53 Do not allow the assemble of floating point multiple instructions.
54 @cindex @code{-mno-fpu} command line option, ARM
56 Do not allow the assembly of any floating point instructions.
57 @cindex @code{-mthumb-interwork} command line option, ARM
58 @item -mthumb-interwork
59 This option specifies that the output generated by the assembler should
60 be marked as supporting interworking.
61 @cindex @code{-mapcs} command line option, ARM
62 @item -mapcs [@var{26}|@var{32}]
63 This option specifies that the output generated by the assembler should
64 be marked as supporting the indicated version of the Arm Procedure.
67 This indicates the the floating point variant of the APCS should be
68 used. In this variant floating point arguments are passed in FP
69 registers ratehr than integer registers.
70 @item -mapcs-reentrant
71 This indicates that the reentrant variant of the APCS should be used.
72 This variant supports position independent code.
73 @cindex @code{-EB} command line option, ARM
75 This option specifies that the output generated by the assembler should
76 be marked as being encoded for a big-endian processor.
77 @cindex @code{-EL} command line option, ARM
79 This option specifies that the output generated by the assembler should
80 be marked as being encoded for a little-endian processor.
81 @cindex @code{-k} command line option, ARM
82 @cindex PIC code generation for ARM
84 This option enables the generation of PIC (position independent code).
86 This indicates that the code should be assembled using the old ARM ELF
87 conventions, based on a beta release release of the ARM-ELF
88 specifications, rather than the default conventions which are based on
89 the final release of the ARM-ELF specifications.
96 * ARM-Chars:: Special Characters
97 * ARM-Regs:: Register Names
101 @subsection Special Characters
103 @cindex line comment character, ARM
104 @cindex ARM line comment character
105 The presence of a @samp{#} and @samp{@@} on a line indicates the start of
106 a comment that extends to the end of the current line.
108 @cindex identifiers, ARM
109 @cindex ARM identifiers
110 *TODO* Explain about /data modifier on symbols.
113 @subsection Register Names
115 @cindex ARM register names
116 @cindex register names, ARM
117 *TODO* Explain about ARM register naming, and the predefined names.
119 @node ARM Floating Point
120 @section Floating Point
122 @cindex floating point, ARM (@sc{ieee})
123 @cindex ARM floating point (@sc{ieee})
124 The ARM family uses @sc{ieee} floating-point numbers.
129 @section ARM Machine Directives
131 @cindex machine directives, ARM
132 @cindex ARM machine directives
135 @cindex @code{req} directive, ARM
136 @item @var{name} .req @var{register name}
137 This creates an alias for @var{register name} called @var{name}. For
144 @cindex @code{code} directive, ARM
145 @item .code [@var{16}|@var{32}]
146 This directive selects the instruction set being generated. The value 16
147 selects Thumb, with the value 32 selecting ARM.
149 @cindex @code{thumb} directive, ARM
151 This performs the same action as @var{.code 16}.
153 @cindex @code{arm} directive, ARM
155 This performs the same action as @var{.code 32}.
157 @cindex @code{force_thumb} directive, ARM
159 This directive forces the selection of Thumb instructions, even if the
160 target processor does not support those instructions
162 @cindex @code{thumb_func} directive, ARM
164 This directive specifies that the following symbol is the name of a
165 Thumb encoded function. This information is necessary in order to allow
166 the assembler and linker to generate correct code for interworking
167 between Arm and Thumb instructions and should be used even if
168 interworking is not going to be performed.
170 @cindex @code{thumb_set} directive, ARM
172 This performs the equivalent of a @code{.set} directive in that it
173 creates a symbol which is an alias for another symbol (possibly not yet
174 defined). This directive also has the added property in that it marks
175 the aliased symbol as being a thumb function entry point, in the same
176 way that the @code{.thumb_func} directive does.
178 @cindex @code{.ltorg} directive, ARM
180 This directive causes the current contents of the literal pool to be
181 dumped into the current section (which is assumed to be the .text
182 section) at the current location (aligned to a word boundary).
184 @cindex @code{.pool} directive, ARM
186 This is a synonym for .ltorg.
194 @cindex opcodes for ARM
195 @code{@value{AS}} implements all the standard ARM opcodes. It also
196 implements several pseudo opcodes, including several synthetic load
201 @cindex @code{NOP} pseudo op, ARM
207 This pseudo op will always evaluate to a legal ARM instruction that does
208 nothing. Currently it will evaluate to MOV r0, r0.
210 @cindex @code{LDR reg,=<label>} pseudo op, ARM
213 ldr <register> , = <expression>
216 If expression evaluates to a numeric constant then a MOV or MVN
217 instruction will be used in place of the LDR instruction, if the
218 constant can be generated by either of these instructions. Otherwise
219 the constant will be placed into the nearest literal pool (if it not
220 already there) and a PC relative LDR instruction will be generated.
222 @cindex @code{ADR reg,<label>} pseudo op, ARM
225 adr <register> <label>
228 This instruction will load the address of @var{label} into the indicated
229 register. The instruction will evaluate to a PC relative ADD or SUB
230 instruction depending upon where the label is located. If the label is
231 out of range, or if it is not defined in the same file (and section) as
232 the ADR instruction, then an error will be generated. This instruction
233 will not make use of the literal pool.
235 @cindex @code{ADRL reg,<label>} pseudo op, ARM
238 adrl <register> <label>
241 This instruction will load the address of @var{label} into the indicated
242 register. The instruction will evaluate to one or two a PC relative ADD
243 or SUB instructions depending upon where the label is located. If a
244 second instruction is not needed a NOP instruction will be generated in
245 its place, so that this instruction is always 8 bytes long.
247 If the label is out of range, or if it is not defined in the same file
248 (and section) as the ADRL instruction, then an error will be generated.
249 This instruction will not make use of the literal pool.
253 For information on the ARM or Thumb instruction sets, see @cite{ARM
254 Software Development Toolkit Reference Manual}, Advanced RISC Machines