1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
113 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
114 @code{i80200} (Intel XScale processor)
115 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
118 The special name @code{all} may be used to allow the
119 assembler to accept instructions valid for any ARM processor.
121 In addition to the basic instruction set, the assembler can be told to
122 accept various extension mnemonics that extend the processor using the
123 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
124 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
125 are currently supported:
131 @cindex @code{-march=} command line option, ARM
132 @item -march=@var{architecture}[+@var{extension}@dots{}]
133 This option specifies the target architecture. The assembler will issue
134 an error message if an attempt is made to assemble an instruction which
135 will not execute on the target architecture. The following architecture
136 names are recognized:
164 If both @code{-mcpu} and
165 @code{-march} are specified, the assembler will use
166 the setting for @code{-mcpu}.
168 The architecture option can be extended with the same instruction set
169 extension options as the @code{-mcpu} option.
171 @cindex @code{-mfpu=} command line option, ARM
172 @item -mfpu=@var{floating-point-format}
174 This option specifies the floating point format to assemble for. The
175 assembler will issue an error message if an attempt is made to assemble
176 an instruction which will not execute on the target floating point unit.
177 The following format options are recognized:
199 In addition to determining which instructions are assembled, this option
200 also affects the way in which the @code{.double} assembler directive behaves
201 when assembling little-endian code.
203 The default is dependent on the processor selected. For Architecture 5 or
204 later, the default is to assembler for VFP instructions; for earlier
205 architectures the default is to assemble for FPA instructions.
207 @cindex @code{-mthumb} command line option, ARM
209 This option specifies that the assembler should start assembling Thumb
210 instructions; that is, it should behave as though the file starts with a
211 @code{.code 16} directive.
213 @cindex @code{-mthumb-interwork} command line option, ARM
214 @item -mthumb-interwork
215 This option specifies that the output generated by the assembler should
216 be marked as supporting interworking.
218 @cindex @code{-mapcs} command line option, ARM
219 @item -mapcs @code{[26|32]}
220 This option specifies that the output generated by the assembler should
221 be marked as supporting the indicated version of the Arm Procedure.
224 @cindex @code{-matpcs} command line option, ARM
226 This option specifies that the output generated by the assembler should
227 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
228 enabled this option will cause the assembler to create an empty
229 debugging section in the object file called .arm.atpcs. Debuggers can
230 use this to determine the ABI being used by.
232 @cindex @code{-mapcs-float} command line option, ARM
234 This indicates the floating point variant of the APCS should be
235 used. In this variant floating point arguments are passed in FP
236 registers rather than integer registers.
238 @cindex @code{-mapcs-reentrant} command line option, ARM
239 @item -mapcs-reentrant
240 This indicates that the reentrant variant of the APCS should be used.
241 This variant supports position independent code.
243 @cindex @code{-mfloat-abi=} command line option, ARM
244 @item -mfloat-abi=@var{abi}
245 This option specifies that the output generated by the assembler should be
246 marked as using specified floating point ABI.
247 The following values are recognized:
253 @cindex @code{-eabi=} command line option, ARM
254 @item -meabi=@var{ver}
255 This option specifies which EABI version the produced object files should
257 The following values are recognised:
262 @cindex @code{-EB} command line option, ARM
264 This option specifies that the output generated by the assembler should
265 be marked as being encoded for a big-endian processor.
267 @cindex @code{-EL} command line option, ARM
269 This option specifies that the output generated by the assembler should
270 be marked as being encoded for a little-endian processor.
272 @cindex @code{-k} command line option, ARM
273 @cindex PIC code generation for ARM
275 This option specifies that the output of the assembler should be marked
276 as position-independent code (PIC).
284 * ARM-Chars:: Special Characters
285 * ARM-Regs:: Register Names
289 @subsection Special Characters
291 @cindex line comment character, ARM
292 @cindex ARM line comment character
293 The presence of a @samp{@@} on a line indicates the start of a comment
294 that extends to the end of the current line. If a @samp{#} appears as
295 the first character of a line, the whole line is treated as a comment.
297 @cindex line separator, ARM
298 @cindex statement separator, ARM
299 @cindex ARM line separator
300 The @samp{;} character can be used instead of a newline to separate
303 @cindex immediate character, ARM
304 @cindex ARM immediate character
305 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
307 @cindex identifiers, ARM
308 @cindex ARM identifiers
309 *TODO* Explain about /data modifier on symbols.
312 @subsection Register Names
314 @cindex ARM register names
315 @cindex register names, ARM
316 *TODO* Explain about ARM register naming, and the predefined names.
318 @node ARM Floating Point
319 @section Floating Point
321 @cindex floating point, ARM (@sc{ieee})
322 @cindex ARM floating point (@sc{ieee})
323 The ARM family uses @sc{ieee} floating-point numbers.
328 @section ARM Machine Directives
330 @cindex machine directives, ARM
331 @cindex ARM machine directives
334 @cindex @code{align} directive, ARM
335 @item .align @var{expression} [, @var{expression}]
336 This is the generic @var{.align} directive. For the ARM however if the
337 first argument is zero (ie no alignment is needed) the assembler will
338 behave as if the argument had been 2 (ie pad to the next four byte
339 boundary). This is for compatibility with ARM's own assembler.
341 @cindex @code{req} directive, ARM
342 @item @var{name} .req @var{register name}
343 This creates an alias for @var{register name} called @var{name}. For
350 @cindex @code{unreq} directive, ARM
351 @item .unreq @var{alias-name}
352 This undefines a register alias which was previously defined using the
353 @code{req} directive. For example:
360 An error occurs if the name is undefined. Note - this pseudo op can
361 be used to delete builtin in register name aliases (eg 'r0'). This
362 should only be done if it is really necessary.
364 @cindex @code{code} directive, ARM
365 @item .code @code{[16|32]}
366 This directive selects the instruction set being generated. The value 16
367 selects Thumb, with the value 32 selecting ARM.
369 @cindex @code{thumb} directive, ARM
371 This performs the same action as @var{.code 16}.
373 @cindex @code{arm} directive, ARM
375 This performs the same action as @var{.code 32}.
377 @cindex @code{force_thumb} directive, ARM
379 This directive forces the selection of Thumb instructions, even if the
380 target processor does not support those instructions
382 @cindex @code{thumb_func} directive, ARM
384 This directive specifies that the following symbol is the name of a
385 Thumb encoded function. This information is necessary in order to allow
386 the assembler and linker to generate correct code for interworking
387 between Arm and Thumb instructions and should be used even if
388 interworking is not going to be performed. The presence of this
389 directive also implies @code{.thumb}
391 @cindex @code{thumb_set} directive, ARM
393 This performs the equivalent of a @code{.set} directive in that it
394 creates a symbol which is an alias for another symbol (possibly not yet
395 defined). This directive also has the added property in that it marks
396 the aliased symbol as being a thumb function entry point, in the same
397 way that the @code{.thumb_func} directive does.
399 @cindex @code{.ltorg} directive, ARM
401 This directive causes the current contents of the literal pool to be
402 dumped into the current section (which is assumed to be the .text
403 section) at the current location (aligned to a word boundary).
404 @code{GAS} maintains a separate literal pool for each section and each
405 sub-section. The @code{.ltorg} directive will only affect the literal
406 pool of the current section and sub-section. At the end of assembly
407 all remaining, un-empty literal pools will automatically be dumped.
409 Note - older versions of @code{GAS} would dump the current literal
410 pool any time a section change occurred. This is no longer done, since
411 it prevents accurate control of the placement of literal pools.
413 @cindex @code{.pool} directive, ARM
415 This is a synonym for .ltorg.
417 @cindex @code{.fnstart} directive, ARM
418 @item .unwind_fnstart
419 Marks the start of a function with an unwind table entry.
421 @cindex @code{.fnend} directive, ARM
423 Marks the end of a function with an unwind table entry. The unwind index
424 table entry is created when this directive is processed.
426 If no personality routine has been specified then standard personality
427 routine 0 or 1 will be used, depending on the number of unwind opcodes
430 @cindex @code{.cantunwind} directive, ARM
432 Prevents unwinding through the current function. No personality routine
433 or exception table data is required or permitted.
435 @cindex @code{.personality} directive, ARM
436 @item .personality @var{name}
437 Sets the personality routine for the current function to @var{name}.
439 @cindex @code{.personalityindex} directive, ARM
440 @item .personalityindex @var{index}
441 Sets the personality routine for the current function to the EABI standard
442 routine number @var{index}
444 @cindex @code{.handlerdata} directive, ARM
446 Marks the end of the current function, and the start of the exception table
447 entry for that function. Anything between this directive and the
448 @code{.fnend} directive will be added to the exception table entry.
450 Must be preceded by a @code{.personality} or @code{.personalityindex}
453 @cindex @code{.save} directive, ARM
454 @item .save @var{reglist}
455 Generate unwinder annotations to restore the registers in @var{reglist}.
456 The format of @var{reglist} is the same as the corresponding store-multiple
460 @exdent @emph{core registers}
461 .save @{r4, r5, r6, lr@}
462 stmfd sp!, @{r4, r5, r6, lr@}
463 @exdent @emph{FPA registers}
466 @exdent @emph{VFP registers}
467 .save @{d8, d9, d10@}
468 fstmdf sp!, @{d8, d9, d10@}
469 @exdent @emph{iWMMXt registers}
471 wstrd wr11, [sp, #-8]!
472 wstrd wr10, [sp, #-8]!
475 wstrd wr11, [sp, #-8]!
477 wstrd wr10, [sp, #-8]!
480 @cindex @code{.pad} directive, ARM
481 @item .pad #@var{count}
482 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
483 A positive value indicates the function prologue allocated stack space by
484 decrementing the stack pointer.
486 @cindex @code{.movsp} directive, ARM
487 @item .movsp @var{reg}
488 Tell the unwinder that @var{reg} contains the current stack pointer.
490 @cindex @code{.setfp} directive, ARM
491 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
492 Make all unwinder annotations relaive to a frame pointer. Without this
493 the unwinder will use offsets from the stack pointer.
495 The syntax of this directive is the same as the @code{sub} or @code{mov}
496 instruction used to set the frame pointer. @var{spreg} must be either
497 @code{sp} or mentioned in a previous @code{.movsp} directive.
507 @cindex @code{.unwind_raw} directive, ARM
508 @item .raw @var{offset}, @var{byte1}, @dots{}
509 Insert one of more arbitary unwind opcode bytes, which are known to adjust
510 the stack pointer by @var{offset} bytes.
512 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
515 @cindex @code{.cpu} directive, ARM
516 @item .cpu @var{name}
517 Select the target processor. Valid values for @var{name} are the same as
518 for the @option{-mcpu} commandline option.
520 @cindex @code{.arch} directive, ARM
521 @item .arch @var{name}
522 Select the target architecture. Valid values for @var{name} are the same as
523 for the @option{-march} commandline option.
525 @cindex @code{.fpu} directive, ARM
526 @item .fpu @var{name}
527 Select the floating point unit to assemble for. Valid values for @var{name}
528 are the same as for the @option{-mfpu} commandline option.
530 @cindex @code{.eabi_attribute} directive, ARM
531 @item .eabi_attribute @var{tag}, @var{value}
532 Set the EABI object attribute number @var{tag} to @var{value}. The value
533 is either a @code{number}, @code{"string"}, or @code{number, "string"}
534 depending on the tag.
542 @cindex opcodes for ARM
543 @code{@value{AS}} implements all the standard ARM opcodes. It also
544 implements several pseudo opcodes, including several synthetic load
549 @cindex @code{NOP} pseudo op, ARM
555 This pseudo op will always evaluate to a legal ARM instruction that does
556 nothing. Currently it will evaluate to MOV r0, r0.
558 @cindex @code{LDR reg,=<label>} pseudo op, ARM
561 ldr <register> , = <expression>
564 If expression evaluates to a numeric constant then a MOV or MVN
565 instruction will be used in place of the LDR instruction, if the
566 constant can be generated by either of these instructions. Otherwise
567 the constant will be placed into the nearest literal pool (if it not
568 already there) and a PC relative LDR instruction will be generated.
570 @cindex @code{ADR reg,<label>} pseudo op, ARM
573 adr <register> <label>
576 This instruction will load the address of @var{label} into the indicated
577 register. The instruction will evaluate to a PC relative ADD or SUB
578 instruction depending upon where the label is located. If the label is
579 out of range, or if it is not defined in the same file (and section) as
580 the ADR instruction, then an error will be generated. This instruction
581 will not make use of the literal pool.
583 @cindex @code{ADRL reg,<label>} pseudo op, ARM
586 adrl <register> <label>
589 This instruction will load the address of @var{label} into the indicated
590 register. The instruction will evaluate to one or two PC relative ADD
591 or SUB instructions depending upon where the label is located. If a
592 second instruction is not needed a NOP instruction will be generated in
593 its place, so that this instruction is always 8 bytes long.
595 If the label is out of range, or if it is not defined in the same file
596 (and section) as the ADRL instruction, then an error will be generated.
597 This instruction will not make use of the literal pool.
601 For information on the ARM or Thumb instruction sets, see @cite{ARM
602 Software Development Toolkit Reference Manual}, Advanced RISC Machines
605 @node ARM Mapping Symbols
606 @section Mapping Symbols
608 The ARM ELF specification requires that special symbols be inserted
609 into object files to mark certain features:
615 At the start of a region of code containing ARM instructions.
619 At the start of a region of code containing THUMB instructions.
623 At the start of a region of data.
627 The assembler will automatically insert these symbols for you - there
628 is no need to code them yourself. Support for tagging symbols ($b,
629 $f, $p and $m) which is also mentioned in the current ARM ELF
630 specification is not implemented. This is because they have been
631 dropped from the new EABI and so tools cannot rely upon their