1 @c Copyright (C) 1996-2017 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
144 @code{cortex-m0plus},
147 @code{marvell-whitney},
150 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
151 @code{i80200} (Intel XScale processor)
152 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
155 The special name @code{all} may be used to allow the
156 assembler to accept instructions valid for any ARM processor.
158 In addition to the basic instruction set, the assembler can be told to
159 accept various extension mnemonics that extend the processor using the
160 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
161 is equivalent to specifying @code{-mcpu=ep9312}.
163 Multiple extensions may be specified, separated by a @code{+}. The
164 extensions should be specified in ascending alphabetical order.
166 Some extensions may be restricted to particular architectures; this is
167 documented in the list of extensions below.
169 Extension mnemonics may also be removed from those the assembler accepts.
170 This is done be prepending @code{no} to the option that adds the extension.
171 Extensions that are removed should be listed after all extensions which have
172 been added, again in ascending alphabetical order. For example,
173 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
176 The following extensions are currently supported:
178 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
179 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
180 @code{fp} (Floating Point Extensions for v8-A architecture),
181 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
182 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
183 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
188 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
190 @code{os} (Operating System for v6M architecture),
191 @code{sec} (Security Extensions for v6K and v7-A architectures),
192 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
193 @code{virt} (Virtualization Extensions for v7-A architecture, implies
195 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
196 @code{ras} (Reliability, Availability and Serviceability extensions
197 for v8-A architecture),
198 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
203 @cindex @code{-march=} command line option, ARM
204 @item -march=@var{architecture}[+@var{extension}@dots{}]
205 This option specifies the target architecture. The assembler will issue
206 an error message if an attempt is made to assemble an instruction which
207 will not execute on the target architecture. The following architecture
208 names are recognized:
247 If both @code{-mcpu} and
248 @code{-march} are specified, the assembler will use
249 the setting for @code{-mcpu}.
251 The architecture option can be extended with the same instruction set
252 extension options as the @code{-mcpu} option.
254 @cindex @code{-mfpu=} command line option, ARM
255 @item -mfpu=@var{floating-point-format}
257 This option specifies the floating point format to assemble for. The
258 assembler will issue an error message if an attempt is made to assemble
259 an instruction which will not execute on the target floating point unit.
260 The following format options are recognized:
280 @code{vfpv3-d16-fp16},
297 @code{neon-fp-armv8},
298 @code{crypto-neon-fp-armv8},
299 @code{neon-fp-armv8.1}
301 @code{crypto-neon-fp-armv8.1}.
303 In addition to determining which instructions are assembled, this option
304 also affects the way in which the @code{.double} assembler directive behaves
305 when assembling little-endian code.
307 The default is dependent on the processor selected. For Architecture 5 or
308 later, the default is to assemble for VFP instructions; for earlier
309 architectures the default is to assemble for FPA instructions.
311 @cindex @code{-mthumb} command line option, ARM
313 This option specifies that the assembler should start assembling Thumb
314 instructions; that is, it should behave as though the file starts with a
315 @code{.code 16} directive.
317 @cindex @code{-mthumb-interwork} command line option, ARM
318 @item -mthumb-interwork
319 This option specifies that the output generated by the assembler should
320 be marked as supporting interworking.
322 @cindex @code{-mimplicit-it} command line option, ARM
323 @item -mimplicit-it=never
324 @itemx -mimplicit-it=always
325 @itemx -mimplicit-it=arm
326 @itemx -mimplicit-it=thumb
327 The @code{-mimplicit-it} option controls the behavior of the assembler when
328 conditional instructions are not enclosed in IT blocks.
329 There are four possible behaviors.
330 If @code{never} is specified, such constructs cause a warning in ARM
331 code and an error in Thumb-2 code.
332 If @code{always} is specified, such constructs are accepted in both
333 ARM and Thumb-2 code, where the IT instruction is added implicitly.
334 If @code{arm} is specified, such constructs are accepted in ARM code
335 and cause an error in Thumb-2 code.
336 If @code{thumb} is specified, such constructs cause a warning in ARM
337 code and are accepted in Thumb-2 code. If you omit this option, the
338 behavior is equivalent to @code{-mimplicit-it=arm}.
340 @cindex @code{-mapcs-26} command line option, ARM
341 @cindex @code{-mapcs-32} command line option, ARM
344 These options specify that the output generated by the assembler should
345 be marked as supporting the indicated version of the Arm Procedure.
348 @cindex @code{-matpcs} command line option, ARM
350 This option specifies that the output generated by the assembler should
351 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
352 enabled this option will cause the assembler to create an empty
353 debugging section in the object file called .arm.atpcs. Debuggers can
354 use this to determine the ABI being used by.
356 @cindex @code{-mapcs-float} command line option, ARM
358 This indicates the floating point variant of the APCS should be
359 used. In this variant floating point arguments are passed in FP
360 registers rather than integer registers.
362 @cindex @code{-mapcs-reentrant} command line option, ARM
363 @item -mapcs-reentrant
364 This indicates that the reentrant variant of the APCS should be used.
365 This variant supports position independent code.
367 @cindex @code{-mfloat-abi=} command line option, ARM
368 @item -mfloat-abi=@var{abi}
369 This option specifies that the output generated by the assembler should be
370 marked as using specified floating point ABI.
371 The following values are recognized:
377 @cindex @code{-eabi=} command line option, ARM
378 @item -meabi=@var{ver}
379 This option specifies which EABI version the produced object files should
381 The following values are recognized:
387 @cindex @code{-EB} command line option, ARM
389 This option specifies that the output generated by the assembler should
390 be marked as being encoded for a big-endian processor.
392 Note: If a program is being built for a system with big-endian data
393 and little-endian instructions then it should be assembled with the
394 @option{-EB} option, (all of it, code and data) and then linked with
395 the @option{--be8} option. This will reverse the endianness of the
396 instructions back to little-endian, but leave the data as big-endian.
398 @cindex @code{-EL} command line option, ARM
400 This option specifies that the output generated by the assembler should
401 be marked as being encoded for a little-endian processor.
403 @cindex @code{-k} command line option, ARM
404 @cindex PIC code generation for ARM
406 This option specifies that the output of the assembler should be marked
407 as position-independent code (PIC).
409 @cindex @code{--fix-v4bx} command line option, ARM
411 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
412 the linker option of the same name.
414 @cindex @code{-mwarn-deprecated} command line option, ARM
415 @item -mwarn-deprecated
416 @itemx -mno-warn-deprecated
417 Enable or disable warnings about using deprecated options or
418 features. The default is to warn.
420 @cindex @code{-mccs} command line option, ARM
422 Turns on CodeComposer Studio assembly syntax compatibility mode.
424 @cindex @code{-mwarn-syms} command line option, ARM
426 @itemx -mno-warn-syms
427 Enable or disable warnings about symbols that match the names of ARM
428 instructions. The default is to warn.
436 * ARM-Instruction-Set:: Instruction Set
437 * ARM-Chars:: Special Characters
438 * ARM-Regs:: Register Names
439 * ARM-Relocations:: Relocations
440 * ARM-Neon-Alignment:: NEON Alignment Specifiers
443 @node ARM-Instruction-Set
444 @subsection Instruction Set Syntax
445 Two slightly different syntaxes are support for ARM and THUMB
446 instructions. The default, @code{divided}, uses the old style where
447 ARM and THUMB instructions had their own, separate syntaxes. The new,
448 @code{unified} syntax, which can be selected via the @code{.syntax}
449 directive, and has the following main features:
453 Immediate operands do not require a @code{#} prefix.
456 The @code{IT} instruction may appear, and if it does it is validated
457 against subsequent conditional affixes. In ARM mode it does not
458 generate machine code, in THUMB mode it does.
461 For ARM instructions the conditional affixes always appear at the end
462 of the instruction. For THUMB instructions conditional affixes can be
463 used, but only inside the scope of an @code{IT} instruction.
466 All of the instructions new to the V6T2 architecture (and later) are
467 available. (Only a few such instructions can be written in the
468 @code{divided} syntax).
471 The @code{.N} and @code{.W} suffixes are recognized and honored.
474 All instructions set the flags if and only if they have an @code{s}
479 @subsection Special Characters
481 @cindex line comment character, ARM
482 @cindex ARM line comment character
483 The presence of a @samp{@@} anywhere on a line indicates the start of
484 a comment that extends to the end of that line.
486 If a @samp{#} appears as the first character of a line then the whole
487 line is treated as a comment, but in this case the line could also be
488 a logical line number directive (@pxref{Comments}) or a preprocessor
489 control command (@pxref{Preprocessing}).
491 @cindex line separator, ARM
492 @cindex statement separator, ARM
493 @cindex ARM line separator
494 The @samp{;} character can be used instead of a newline to separate
497 @cindex immediate character, ARM
498 @cindex ARM immediate character
499 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
501 @cindex identifiers, ARM
502 @cindex ARM identifiers
503 *TODO* Explain about /data modifier on symbols.
506 @subsection Register Names
508 @cindex ARM register names
509 @cindex register names, ARM
510 *TODO* Explain about ARM register naming, and the predefined names.
512 @node ARM-Relocations
513 @subsection ARM relocation generation
515 @cindex data relocations, ARM
516 @cindex ARM data relocations
517 Specific data relocations can be generated by putting the relocation name
518 in parentheses after the symbol name. For example:
524 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
526 The following relocations are supported:
542 For compatibility with older toolchains the assembler also accepts
543 @code{(PLT)} after branch targets. On legacy targets this will
544 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
545 targets it will encode either the @samp{R_ARM_CALL} or
546 @samp{R_ARM_JUMP24} relocation, as appropriate.
548 @cindex MOVW and MOVT relocations, ARM
549 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
550 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
551 respectively. For example to load the 32-bit address of foo into r0:
554 MOVW r0, #:lower16:foo
555 MOVT r0, #:upper16:foo
558 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
559 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
560 generated by prefixing the value with @samp{#:lower0_7:#},
561 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
562 respectively. For example to load the 32-bit address of foo into r0:
565 MOVS r0, #:upper8_15:#foo
567 ADDS r0, #:upper0_7:#foo
569 ADDS r0, #:lower8_15:#foo
571 ADDS r0, #:lower0_7:#foo
574 @node ARM-Neon-Alignment
575 @subsection NEON Alignment Specifiers
577 @cindex alignment for NEON instructions
578 Some NEON load/store instructions allow an optional address
580 The ARM documentation specifies that this is indicated by
581 @samp{@@ @var{align}}. However GAS already interprets
582 the @samp{@@} character as a "line comment" start,
583 so @samp{: @var{align}} is used instead. For example:
586 vld1.8 @{q0@}, [r0, :128]
589 @node ARM Floating Point
590 @section Floating Point
592 @cindex floating point, ARM (@sc{ieee})
593 @cindex ARM floating point (@sc{ieee})
594 The ARM family uses @sc{ieee} floating-point numbers.
597 @section ARM Machine Directives
599 @cindex machine directives, ARM
600 @cindex ARM machine directives
603 @c AAAAAAAAAAAAAAAAAAAAAAAAA
606 @cindex @code{.2byte} directive, ARM
607 @cindex @code{.4byte} directive, ARM
608 @cindex @code{.8byte} directive, ARM
609 @item .2byte @var{expression} [, @var{expression}]*
610 @itemx .4byte @var{expression} [, @var{expression}]*
611 @itemx .8byte @var{expression} [, @var{expression}]*
612 These directives write 2, 4 or 8 byte values to the output section.
615 @cindex @code{.align} directive, ARM
616 @item .align @var{expression} [, @var{expression}]
617 This is the generic @var{.align} directive. For the ARM however if the
618 first argument is zero (ie no alignment is needed) the assembler will
619 behave as if the argument had been 2 (ie pad to the next four byte
620 boundary). This is for compatibility with ARM's own assembler.
622 @cindex @code{.arch} directive, ARM
623 @item .arch @var{name}
624 Select the target architecture. Valid values for @var{name} are the same as
625 for the @option{-march} commandline option.
627 Specifying @code{.arch} clears any previously selected architecture
630 @cindex @code{.arch_extension} directive, ARM
631 @item .arch_extension @var{name}
632 Add or remove an architecture extension to the target architecture. Valid
633 values for @var{name} are the same as those accepted as architectural
634 extensions by the @option{-mcpu} commandline option.
636 @code{.arch_extension} may be used multiple times to add or remove extensions
637 incrementally to the architecture being compiled for.
639 @cindex @code{.arm} directive, ARM
641 This performs the same action as @var{.code 32}.
643 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
645 @cindex @code{.bss} directive, ARM
647 This directive switches to the @code{.bss} section.
649 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
651 @cindex @code{.cantunwind} directive, ARM
653 Prevents unwinding through the current function. No personality routine
654 or exception table data is required or permitted.
656 @cindex @code{.code} directive, ARM
657 @item .code @code{[16|32]}
658 This directive selects the instruction set being generated. The value 16
659 selects Thumb, with the value 32 selecting ARM.
661 @cindex @code{.cpu} directive, ARM
662 @item .cpu @var{name}
663 Select the target processor. Valid values for @var{name} are the same as
664 for the @option{-mcpu} commandline option.
666 Specifying @code{.cpu} clears any previously selected architecture
669 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
671 @cindex @code{.dn} and @code{.qn} directives, ARM
672 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
673 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
675 The @code{dn} and @code{qn} directives are used to create typed
676 and/or indexed register aliases for use in Advanced SIMD Extension
677 (Neon) instructions. The former should be used to create aliases
678 of double-precision registers, and the latter to create aliases of
679 quad-precision registers.
681 If these directives are used to create typed aliases, those aliases can
682 be used in Neon instructions instead of writing types after the mnemonic
683 or after each operand. For example:
692 This is equivalent to writing the following:
698 Aliases created using @code{dn} or @code{qn} can be destroyed using
701 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
703 @cindex @code{.eabi_attribute} directive, ARM
704 @item .eabi_attribute @var{tag}, @var{value}
705 Set the EABI object attribute @var{tag} to @var{value}.
707 The @var{tag} is either an attribute number, or one of the following:
708 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
709 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
710 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
711 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
712 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
713 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
714 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
715 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
716 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
717 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
718 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
719 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
720 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
721 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
722 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
723 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
724 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
725 @code{Tag_conformance}, @code{Tag_T2EE_use},
726 @code{Tag_Virtualization_use}
728 The @var{value} is either a @code{number}, @code{"string"}, or
729 @code{number, "string"} depending on the tag.
731 Note - the following legacy values are also accepted by @var{tag}:
732 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
733 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
735 @cindex @code{.even} directive, ARM
737 This directive aligns to an even-numbered address.
739 @cindex @code{.extend} directive, ARM
740 @cindex @code{.ldouble} directive, ARM
741 @item .extend @var{expression} [, @var{expression}]*
742 @itemx .ldouble @var{expression} [, @var{expression}]*
743 These directives write 12byte long double floating-point values to the
744 output section. These are not compatible with current ARM processors
747 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
750 @cindex @code{.fnend} directive, ARM
752 Marks the end of a function with an unwind table entry. The unwind index
753 table entry is created when this directive is processed.
755 If no personality routine has been specified then standard personality
756 routine 0 or 1 will be used, depending on the number of unwind opcodes
760 @cindex @code{.fnstart} directive, ARM
762 Marks the start of a function with an unwind table entry.
764 @cindex @code{.force_thumb} directive, ARM
766 This directive forces the selection of Thumb instructions, even if the
767 target processor does not support those instructions
769 @cindex @code{.fpu} directive, ARM
770 @item .fpu @var{name}
771 Select the floating-point unit to assemble for. Valid values for @var{name}
772 are the same as for the @option{-mfpu} commandline option.
774 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
775 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
777 @cindex @code{.handlerdata} directive, ARM
779 Marks the end of the current function, and the start of the exception table
780 entry for that function. Anything between this directive and the
781 @code{.fnend} directive will be added to the exception table entry.
783 Must be preceded by a @code{.personality} or @code{.personalityindex}
786 @c IIIIIIIIIIIIIIIIIIIIIIIIII
788 @cindex @code{.inst} directive, ARM
789 @item .inst @var{opcode} [ , @dots{} ]
790 @itemx .inst.n @var{opcode} [ , @dots{} ]
791 @itemx .inst.w @var{opcode} [ , @dots{} ]
792 Generates the instruction corresponding to the numerical value @var{opcode}.
793 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
794 specified explicitly, overriding the normal encoding rules.
796 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
797 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
798 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
800 @item .ldouble @var{expression} [, @var{expression}]*
803 @cindex @code{.ltorg} directive, ARM
805 This directive causes the current contents of the literal pool to be
806 dumped into the current section (which is assumed to be the .text
807 section) at the current location (aligned to a word boundary).
808 @code{GAS} maintains a separate literal pool for each section and each
809 sub-section. The @code{.ltorg} directive will only affect the literal
810 pool of the current section and sub-section. At the end of assembly
811 all remaining, un-empty literal pools will automatically be dumped.
813 Note - older versions of @code{GAS} would dump the current literal
814 pool any time a section change occurred. This is no longer done, since
815 it prevents accurate control of the placement of literal pools.
817 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
819 @cindex @code{.movsp} directive, ARM
820 @item .movsp @var{reg} [, #@var{offset}]
821 Tell the unwinder that @var{reg} contains an offset from the current
822 stack pointer. If @var{offset} is not specified then it is assumed to be
825 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
826 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
828 @cindex @code{.object_arch} directive, ARM
829 @item .object_arch @var{name}
830 Override the architecture recorded in the EABI object attribute section.
831 Valid values for @var{name} are the same as for the @code{.arch} directive.
832 Typically this is useful when code uses runtime detection of CPU features.
834 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
836 @cindex @code{.packed} directive, ARM
837 @item .packed @var{expression} [, @var{expression}]*
838 This directive writes 12-byte packed floating-point values to the
839 output section. These are not compatible with current ARM processors
843 @cindex @code{.pad} directive, ARM
844 @item .pad #@var{count}
845 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
846 A positive value indicates the function prologue allocated stack space by
847 decrementing the stack pointer.
849 @cindex @code{.personality} directive, ARM
850 @item .personality @var{name}
851 Sets the personality routine for the current function to @var{name}.
853 @cindex @code{.personalityindex} directive, ARM
854 @item .personalityindex @var{index}
855 Sets the personality routine for the current function to the EABI standard
856 routine number @var{index}
858 @cindex @code{.pool} directive, ARM
860 This is a synonym for .ltorg.
862 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
863 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
865 @cindex @code{.req} directive, ARM
866 @item @var{name} .req @var{register name}
867 This creates an alias for @var{register name} called @var{name}. For
874 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
877 @cindex @code{.save} directive, ARM
878 @item .save @var{reglist}
879 Generate unwinder annotations to restore the registers in @var{reglist}.
880 The format of @var{reglist} is the same as the corresponding store-multiple
884 @exdent @emph{core registers}
885 .save @{r4, r5, r6, lr@}
886 stmfd sp!, @{r4, r5, r6, lr@}
887 @exdent @emph{FPA registers}
890 @exdent @emph{VFP registers}
891 .save @{d8, d9, d10@}
892 fstmdx sp!, @{d8, d9, d10@}
893 @exdent @emph{iWMMXt registers}
895 wstrd wr11, [sp, #-8]!
896 wstrd wr10, [sp, #-8]!
899 wstrd wr11, [sp, #-8]!
901 wstrd wr10, [sp, #-8]!
905 @cindex @code{.setfp} directive, ARM
906 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
907 Make all unwinder annotations relative to a frame pointer. Without this
908 the unwinder will use offsets from the stack pointer.
910 The syntax of this directive is the same as the @code{add} or @code{mov}
911 instruction used to set the frame pointer. @var{spreg} must be either
912 @code{sp} or mentioned in a previous @code{.movsp} directive.
922 @cindex @code{.secrel32} directive, ARM
923 @item .secrel32 @var{expression} [, @var{expression}]*
924 This directive emits relocations that evaluate to the section-relative
925 offset of each expression's symbol. This directive is only supported
928 @cindex @code{.syntax} directive, ARM
929 @item .syntax [@code{unified} | @code{divided}]
930 This directive sets the Instruction Set Syntax as described in the
931 @ref{ARM-Instruction-Set} section.
933 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
935 @cindex @code{.thumb} directive, ARM
937 This performs the same action as @var{.code 16}.
939 @cindex @code{.thumb_func} directive, ARM
941 This directive specifies that the following symbol is the name of a
942 Thumb encoded function. This information is necessary in order to allow
943 the assembler and linker to generate correct code for interworking
944 between Arm and Thumb instructions and should be used even if
945 interworking is not going to be performed. The presence of this
946 directive also implies @code{.thumb}
948 This directive is not necessary when generating EABI objects. On these
949 targets the encoding is implicit when generating Thumb code.
951 @cindex @code{.thumb_set} directive, ARM
953 This performs the equivalent of a @code{.set} directive in that it
954 creates a symbol which is an alias for another symbol (possibly not yet
955 defined). This directive also has the added property in that it marks
956 the aliased symbol as being a thumb function entry point, in the same
957 way that the @code{.thumb_func} directive does.
959 @cindex @code{.tlsdescseq} directive, ARM
960 @item .tlsdescseq @var{tls-variable}
961 This directive is used to annotate parts of an inlined TLS descriptor
962 trampoline. Normally the trampoline is provided by the linker, and
963 this directive is not needed.
965 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
967 @cindex @code{.unreq} directive, ARM
968 @item .unreq @var{alias-name}
969 This undefines a register alias which was previously defined using the
970 @code{req}, @code{dn} or @code{qn} directives. For example:
977 An error occurs if the name is undefined. Note - this pseudo op can
978 be used to delete builtin in register name aliases (eg 'r0'). This
979 should only be done if it is really necessary.
981 @cindex @code{.unwind_raw} directive, ARM
982 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
983 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
984 the stack pointer by @var{offset} bytes.
986 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
989 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
991 @cindex @code{.vsave} directive, ARM
992 @item .vsave @var{vfp-reglist}
993 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
994 using FLDMD. Also works for VFPv3 registers
995 that are to be restored using VLDM.
996 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1000 @exdent @emph{VFP registers}
1001 .vsave @{d8, d9, d10@}
1002 fstmdd sp!, @{d8, d9, d10@}
1003 @exdent @emph{VFPv3 registers}
1004 .vsave @{d15, d16, d17@}
1005 vstm sp!, @{d15, d16, d17@}
1008 Since FLDMX and FSTMX are now deprecated, this directive should be
1009 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1011 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1012 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1013 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1014 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1022 @cindex opcodes for ARM
1023 @code{@value{AS}} implements all the standard ARM opcodes. It also
1024 implements several pseudo opcodes, including several synthetic load
1029 @cindex @code{NOP} pseudo op, ARM
1035 This pseudo op will always evaluate to a legal ARM instruction that does
1036 nothing. Currently it will evaluate to MOV r0, r0.
1038 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1041 ldr <register> , = <expression>
1044 If expression evaluates to a numeric constant then a MOV or MVN
1045 instruction will be used in place of the LDR instruction, if the
1046 constant can be generated by either of these instructions. Otherwise
1047 the constant will be placed into the nearest literal pool (if it not
1048 already there) and a PC relative LDR instruction will be generated.
1050 @cindex @code{ADR reg,<label>} pseudo op, ARM
1053 adr <register> <label>
1056 This instruction will load the address of @var{label} into the indicated
1057 register. The instruction will evaluate to a PC relative ADD or SUB
1058 instruction depending upon where the label is located. If the label is
1059 out of range, or if it is not defined in the same file (and section) as
1060 the ADR instruction, then an error will be generated. This instruction
1061 will not make use of the literal pool.
1063 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1066 adrl <register> <label>
1069 This instruction will load the address of @var{label} into the indicated
1070 register. The instruction will evaluate to one or two PC relative ADD
1071 or SUB instructions depending upon where the label is located. If a
1072 second instruction is not needed a NOP instruction will be generated in
1073 its place, so that this instruction is always 8 bytes long.
1075 If the label is out of range, or if it is not defined in the same file
1076 (and section) as the ADRL instruction, then an error will be generated.
1077 This instruction will not make use of the literal pool.
1081 For information on the ARM or Thumb instruction sets, see @cite{ARM
1082 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1085 @node ARM Mapping Symbols
1086 @section Mapping Symbols
1088 The ARM ELF specification requires that special symbols be inserted
1089 into object files to mark certain features:
1095 At the start of a region of code containing ARM instructions.
1099 At the start of a region of code containing THUMB instructions.
1103 At the start of a region of data.
1107 The assembler will automatically insert these symbols for you - there
1108 is no need to code them yourself. Support for tagging symbols ($b,
1109 $f, $p and $m) which is also mentioned in the current ARM ELF
1110 specification is not implemented. This is because they have been
1111 dropped from the new EABI and so tools cannot rely upon their
1114 @node ARM Unwinding Tutorial
1117 The ABI for the ARM Architecture specifies a standard format for
1118 exception unwind information. This information is used when an
1119 exception is thrown to determine where control should be transferred.
1120 In particular, the unwind information is used to determine which
1121 function called the function that threw the exception, and which
1122 function called that one, and so forth. This information is also used
1123 to restore the values of callee-saved registers in the function
1124 catching the exception.
1126 If you are writing functions in assembly code, and those functions
1127 call other functions that throw exceptions, you must use assembly
1128 pseudo ops to ensure that appropriate exception unwind information is
1129 generated. Otherwise, if one of the functions called by your assembly
1130 code throws an exception, the run-time library will be unable to
1131 unwind the stack through your assembly code and your program will not
1134 To illustrate the use of these pseudo ops, we will examine the code
1135 that G++ generates for the following C++ input:
1138 void callee (int *);
1149 This example does not show how to throw or catch an exception from
1150 assembly code. That is a much more complex operation and should
1151 always be done in a high-level language, such as C++, that directly
1152 supports exceptions.
1154 The code generated by one particular version of G++ when compiling the
1161 @ Function supports interworking.
1162 @ args = 0, pretend = 0, frame = 8
1163 @ frame_needed = 1, uses_anonymous_args = 0
1185 Of course, the sequence of instructions varies based on the options
1186 you pass to GCC and on the version of GCC in use. The exact
1187 instructions are not important since we are focusing on the pseudo ops
1188 that are used to generate unwind information.
1190 An important assumption made by the unwinder is that the stack frame
1191 does not change during the body of the function. In particular, since
1192 we assume that the assembly code does not itself throw an exception,
1193 the only point where an exception can be thrown is from a call, such
1194 as the @code{bl} instruction above. At each call site, the same saved
1195 registers (including @code{lr}, which indicates the return address)
1196 must be located in the same locations relative to the frame pointer.
1198 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1199 op appears immediately before the first instruction of the function
1200 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1201 op appears immediately after the last instruction of the function.
1202 These pseudo ops specify the range of the function.
1204 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1205 @code{.pad}) matters; their exact locations are irrelevant. In the
1206 example above, the compiler emits the pseudo ops with particular
1207 instructions. That makes it easier to understand the code, but it is
1208 not required for correctness. It would work just as well to emit all
1209 of the pseudo ops other than @code{.fnend} in the same order, but
1210 immediately after @code{.fnstart}.
1212 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1213 indicates registers that have been saved to the stack so that they can
1214 be restored before the function returns. The argument to the
1215 @code{.save} pseudo op is a list of registers to save. If a register
1216 is ``callee-saved'' (as specified by the ABI) and is modified by the
1217 function you are writing, then your code must save the value before it
1218 is modified and restore the original value before the function
1219 returns. If an exception is thrown, the run-time library restores the
1220 values of these registers from their locations on the stack before
1221 returning control to the exception handler. (Of course, if an
1222 exception is not thrown, the function that contains the @code{.save}
1223 pseudo op restores these registers in the function epilogue, as is
1224 done with the @code{ldmfd} instruction above.)
1226 You do not have to save callee-saved registers at the very beginning
1227 of the function and you do not need to use the @code{.save} pseudo op
1228 immediately following the point at which the registers are saved.
1229 However, if you modify a callee-saved register, you must save it on
1230 the stack before modifying it and before calling any functions which
1231 might throw an exception. And, you must use the @code{.save} pseudo
1232 op to indicate that you have done so.
1234 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1235 modification of the stack pointer that does not save any registers.
1236 The argument is the number of bytes (in decimal) that are subtracted
1237 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1238 subtracting from the stack pointer increases the size of the stack.)
1240 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1241 indicates the register that contains the frame pointer. The first
1242 argument is the register that is set, which is typically @code{fp}.
1243 The second argument indicates the register from which the frame
1244 pointer takes its value. The third argument, if present, is the value
1245 (in decimal) added to the register specified by the second argument to
1246 compute the value of the frame pointer. You should not modify the
1247 frame pointer in the body of the function.
1249 If you do not use a frame pointer, then you should not use the
1250 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1251 should avoid modifying the stack pointer outside of the function
1252 prologue. Otherwise, the run-time library will be unable to find
1253 saved registers when it is unwinding the stack.
1255 The pseudo ops described above are sufficient for writing assembly
1256 code that calls functions which may throw exceptions. If you need to
1257 know more about the object-file format used to represent unwind
1258 information, you may consult the @cite{Exception Handling ABI for the
1259 ARM Architecture} available from @uref{http://infocenter.arm.com}.
projects / external / binutils.git / blob