1 @c Copyright 2000, 2001, 2005 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARC Dependent Features
12 @node Machine Dependencies
13 @chapter ARC Dependent Features
16 @set ARC_CORE_DEFAULT 6
20 * ARC Options:: Options
22 * ARC Floating Point:: Floating Point
23 * ARC Directives:: ARC Machine Directives
24 * ARC Opcodes:: Opcodes
30 @cindex ARC options (none)
31 @cindex options for ARC (none)
35 @cindex @code{-marc[5|6|7|8]} command line option, ARC
37 This option selects the core processor variant. Using
38 @code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
43 @cindex @code{arc5} arc5, ARC
47 @cindex @code{arc6} arc6, ARC
49 Jump-and-link (jl) instruction. No requirement of an instruction between
50 setting flags and conditional jump. For example:
57 @cindex @code{arc7} arc7, ARC
59 Break (brk) and sleep (sleep) instructions.
61 @cindex @code{arc8} arc8, ARC
63 Software interrupt (swi) instruction.
67 Note: the @code{.option} directive can to be used to select a core
68 variant from within assembly code.
70 @cindex @code{-EB} command line option, ARC
72 This option specifies that the output generated by the assembler should
73 be marked as being encoded for a big-endian processor.
75 @cindex @code{-EL} command line option, ARC
77 This option specifies that the output generated by the assembler should
78 be marked as being encoded for a little-endian processor - this is the
87 * ARC-Chars:: Special Characters
88 * ARC-Regs:: Register Names
92 @subsection Special Characters
94 @cindex ARC special characters
95 @cindex special characters, ARC
99 @subsection Register Names
101 @cindex ARC register names
102 @cindex register names, ARC
106 @node ARC Floating Point
107 @section Floating Point
109 @cindex floating point, ARC (@sc{ieee})
110 @cindex ARC floating point (@sc{ieee})
111 The ARC core does not currently have hardware floating point
112 support. Software floating point support is provided by @code{GCC}
113 and uses @sc{ieee} floating-point numbers.
117 @section ARC Machine Directives
119 @cindex machine directives, ARC
120 @cindex ARC machine directives
121 The ARC version of @code{@value{AS}} supports the following additional
126 @cindex @code{2byte} directive, ARC
127 @item .2byte @var{expressions}
130 @cindex @code{3byte} directive, ARC
131 @item .3byte @var{expressions}
134 @cindex @code{4byte} directive, ARC
135 @item .4byte @var{expressions}
138 @cindex @code{extAuxRegister} directive, ARC
139 @item .extAuxRegister @var{name},@var{address},@var{mode}
140 The ARCtangent A4 has extensible auxiliary register space. The
141 auxiliary registers can be defined in the assembler source code by
142 using this directive. The first parameter is the @var{name} of the
143 new auxiallry register. The second parameter is the @var{address} of
144 the register in the auxiliary register memory map for the variant of
145 the ARC. The third parameter specifies the @var{mode} in which the
146 register can be operated is and it can be one of:
151 @item r|w (read or write)
157 .extAuxRegister mulhi,0x12,w
160 This specifies an extension auxiliary register called @emph{mulhi}
161 which is at address 0x12 in the memory space and which is only
164 @cindex @code{extCondCode} directive, ARC
165 @item .extCondCode @var{suffix},@var{value}
166 The condition codes on the ARCtangent A4 are extensible and can be
167 specified by means of this assembler directive. They are specified
168 by the suffix and the value for the condition code. They can be used to
169 specify extra condition codes with any values. For example:
172 .extCondCode is_busy,0x14
178 @cindex @code{extCoreRegister} directive, ARC
179 @item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
180 Specifies an extension core register @var{name} for the application.
181 This allows a register @var{name} with a valid @var{regnum} between 0
182 and 60, with the following as valid values for @var{mode}
185 @item @emph{r} (readonly)
186 @item @emph{w} (write only)
187 @item @emph{r|w} (read or write)
191 The other parameter gives a description of the register having a
192 @var{shortcut} in the pipeline. The valid values are:
196 @item cannot_shortcut
202 .extCoreRegister mlo,57,r,can_shortcut
205 This defines an extension core register mlo with the value 57 which
206 can shortcut the pipeline.
208 @cindex @code{extInstruction} directive, ARC
209 @item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
210 The ARCtangent A4 allows the user to specify extension instructions.
211 The extension instructions are not macros. The assembler creates
212 encodings for use of these instructions according to the specification
213 by the user. The parameters are:
217 Name of the extension instruction
220 Opcode to be used. (Bits 27:31 in the encoding). Valid values
223 @item @var{subopcode}
224 Subopcode to be used. Valid values are from 0x09-0x3f. However the
225 correct value also depends on @var{syntaxclass}
227 @item @var{suffixclass}
228 Determines the kinds of suffixes to be allowed. Valid values are
229 @code{SUFFIX_NONE}, @code{SUFFIX_COND},
230 @code{SUFFIX_FLAG} which indicates the absence or presence of
231 conditional suffixes and flag setting by the extension instruction.
232 It is also possible to specify that an instruction sets the flags and
233 is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
235 @item @var{syntaxclass}
236 Determines the syntax class for the instruction. It can have the
241 2 Operand Instruction
243 3 Operand Instruction
246 In addition there could be modifiers for the syntax class as described
250 Syntax Class Modifiers are:
252 @item @code{OP1_MUST_BE_IMM}:
253 Modifies syntax class SYNTAX_3OP, specifying that the first operand
254 of a three-operand instruction must be an immediate (i.e. the result
255 is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
256 SYNTAX_3OP as given in the example below. This could usually be used
257 to set the flags using specific instructions and not retain results.
259 @item @code{OP1_IMM_IMPLIED}:
260 Modifies syntax class SYNTAX_20P, it specifies that there is an
261 implied immediate destination operand which does not appear in the
262 syntax. For example, if the source code contains an instruction like:
268 it really means that the first argument is an implied immediate (that
269 is, the result is discarded). This is the same as though the source
270 code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
276 For example, defining 64-bit multiplier with immediate operands:
279 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
280 SYNTAX_3OP|OP1_MUST_BE_IMM
283 The above specifies an extension instruction called mp64 which has 3 operands,
284 sets the flags, can be used with a condition code, for which the
285 first operand is an immediate. (Equivalent to discarding the result
289 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
292 This describes a 2 operand instruction with an implicit first
293 immediate operand. The result of this operation would be discarded.
295 @cindex @code{half} directive, ARC
296 @item .half @var{expressions}
299 @cindex @code{long} directive, ARC
300 @item .long @var{expressions}
303 @cindex @code{option} directive, ARC
304 @item .option @var{arc|arc5|arc6|arc7|arc8}
305 The @code{.option} directive must be followed by the desired core
306 version. Again @code{arc} is an alias for
307 @code{arc@value{ARC_CORE_DEFAULT}}.
309 Note: the @code{.option} directive overrides the command line option
310 @code{-marc}; a warning is emitted when the version is not consistent
311 between the two - even for the implicit default core version
312 (arc@value{ARC_CORE_DEFAULT}).
314 @cindex @code{short} directive, ARC
315 @item .short @var{expressions}
318 @cindex @code{word} directive, ARC
319 @item .word @var{expressions}
329 @cindex opcodes for ARC
331 For information on the ARC instruction set, see @cite{ARC Programmers
332 Reference Manual}, ARC International (www.arc.com)