1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars[] = "#";
62 const char line_comment_chars[] = "#";
63 const char line_separator_chars[] = ";";
64 const char EXP_CHARS[] = "eE";
65 const char FLT_CHARS[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
72 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn;
79 size_t xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
81 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end = FALSE;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name;
112 const char *lit4_seg_name;
113 const char *init_lit_seg_name;
114 const char *fini_lit_seg_name;
121 static lit_state default_lit_sections;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct *next;
134 static seg_list literal_head_h;
135 static seg_list *literal_head = &literal_head_h;
136 static seg_list init_literal_head_h;
137 static seg_list *init_literal_head = &init_literal_head_h;
138 static seg_list fini_literal_head_h;
139 static seg_list *fini_literal_head = &fini_literal_head_h;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct *next;
154 static sym_list *insn_labels = NULL;
155 static sym_list *free_insn_labels = NULL;
156 static sym_list *saved_insn_labels = NULL;
158 static sym_list *literal_syms;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16 = 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals = 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal : 1;
264 unsigned is_insn : 1;
265 unsigned is_data : 1;
266 unsigned is_unreachable : 1;
270 unsigned is_loop_target : 1;
271 unsigned is_branch_target : 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority : 2;
274 unsigned is_no_density : 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform : 1;
279 unsigned is_no_reorder : 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit : 1;
284 unsigned is_align : 1;
285 unsigned alignment : 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct *next;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single;
334 xtensa_format narrowest;
335 xtensa_format widest;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots[MAX_FORMATS];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format[MAX_FORMATS];
352 } op_placement_info, *op_placement_info_table;
354 op_placement_info_table op_placement_table;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix,
376 directive_absolute_literals,
377 directive_last_directive
383 bfd_boolean can_be_negated;
386 const directive_infoS directive_info[] =
389 { "literal", FALSE },
391 { "transform", TRUE },
392 { "freeregs", FALSE },
393 { "longcalls", TRUE },
394 { "literal_prefix", FALSE },
395 { "schedule", TRUE },
396 { "absolute-literals", TRUE }
399 bfd_boolean directive_state[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE, /* transform */
409 FALSE, /* freeregs */
410 FALSE, /* longcalls */
411 FALSE, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE /* absolute_literals */
416 FALSE /* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT get_expanded_loop_offset (xtensa_opcode);
440 static fragS *get_literal_pool_location (segT);
441 static void set_literal_pool_location (segT, fragS *);
442 static void xtensa_set_frag_assembly_state (fragS *);
443 static void finish_vinsn (vliw_insn *);
444 static bfd_boolean emit_single_op (TInsn *);
445 static int total_frag_text_expansion (fragS *);
447 /* Alignment Functions. */
449 static size_t get_text_align_power (int);
450 static addressT get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS *);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT, subsegT);
459 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
460 static float get_subseg_total_freq (segT, subsegT);
461 static float get_subseg_target_freq (segT, subsegT);
462 static void set_subseg_freq (segT, subsegT, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state *);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
470 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
471 static void xtensa_restore_emit_state (emit_state *);
472 static void cache_literal_section
473 (seg_list *, const char *, segT *, bfd_boolean);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection *, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
483 static int xg_get_single_size (xtensa_opcode);
484 static xtensa_format xg_get_single_format (xtensa_opcode);
486 /* TInsn and IStack functions. */
488 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
489 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
490 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
491 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
492 static bfd_boolean tinsn_check_arguments (const TInsn *);
493 static void tinsn_from_chars (TInsn *, char *, int);
494 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
495 static int get_num_stack_text_bytes (IStack *);
496 static int get_num_stack_literal_bytes (IStack *);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn *);
501 static void xg_clear_vinsn (vliw_insn *);
502 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
503 static void xg_free_vinsn (vliw_insn *);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn *, char *, fragS *, bfd_boolean);
506 static void vinsn_from_chars (vliw_insn *, char *);
508 /* Expression Utilities. */
510 bfd_boolean expr_is_const (const expressionS *);
511 offsetT get_expr_const (const expressionS *);
512 void set_expr_const (expressionS *, offsetT);
513 bfd_boolean expr_is_register (const expressionS *);
514 offsetT get_expr_register (const expressionS *);
515 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
516 static void set_expr_symbol_offset_diff
517 (expressionS *, symbolS *, symbolS *, offsetT);
518 bfd_boolean expr_is_equal (expressionS *, expressionS *);
519 static void copy_expr (expressionS *, const expressionS *);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa;
529 extern int target_big_endian;
531 static xtensa_opcode xtensa_addi_opcode;
532 static xtensa_opcode xtensa_addmi_opcode;
533 static xtensa_opcode xtensa_call0_opcode;
534 static xtensa_opcode xtensa_call4_opcode;
535 static xtensa_opcode xtensa_call8_opcode;
536 static xtensa_opcode xtensa_call12_opcode;
537 static xtensa_opcode xtensa_callx0_opcode;
538 static xtensa_opcode xtensa_callx4_opcode;
539 static xtensa_opcode xtensa_callx8_opcode;
540 static xtensa_opcode xtensa_callx12_opcode;
541 static xtensa_opcode xtensa_const16_opcode;
542 static xtensa_opcode xtensa_entry_opcode;
543 static xtensa_opcode xtensa_movi_opcode;
544 static xtensa_opcode xtensa_movi_n_opcode;
545 static xtensa_opcode xtensa_isync_opcode;
546 static xtensa_opcode xtensa_jx_opcode;
547 static xtensa_opcode xtensa_l32r_opcode;
548 static xtensa_opcode xtensa_loop_opcode;
549 static xtensa_opcode xtensa_loopnez_opcode;
550 static xtensa_opcode xtensa_loopgtz_opcode;
551 static xtensa_opcode xtensa_nop_opcode;
552 static xtensa_opcode xtensa_nop_n_opcode;
553 static xtensa_opcode xtensa_or_opcode;
554 static xtensa_opcode xtensa_ret_opcode;
555 static xtensa_opcode xtensa_ret_n_opcode;
556 static xtensa_opcode xtensa_retw_opcode;
557 static xtensa_opcode xtensa_retw_n_opcode;
558 static xtensa_opcode xtensa_rsr_lcount_opcode;
559 static xtensa_opcode xtensa_waiti_opcode;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section = TRUE;
565 static bfd_boolean align_targets = TRUE;
566 static bfd_boolean warn_unaligned_branch_targets = FALSE;
567 static bfd_boolean has_a0_b_retw = FALSE;
568 static bfd_boolean workaround_a0_b_retw = FALSE;
569 static bfd_boolean workaround_b_j_loop_end = FALSE;
570 static bfd_boolean workaround_short_loop = FALSE;
571 static bfd_boolean maybe_has_short_loop = FALSE;
572 static bfd_boolean workaround_close_loop_end = FALSE;
573 static bfd_boolean maybe_has_close_loop_end = FALSE;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops = FALSE;
585 xtensa_setup_hw_workarounds (int earliest, int latest)
587 if (earliest > latest)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest < 105000 || latest < 105000)
593 workaround_a0_b_retw |= TRUE;
594 workaround_b_j_loop_end |= TRUE;
595 workaround_short_loop |= TRUE;
596 workaround_close_loop_end |= TRUE;
597 workaround_all_short_loops |= TRUE;
604 option_density = OPTION_MD_BASE,
611 option_no_link_relax,
619 option_text_section_literals,
620 option_no_text_section_literals,
622 option_absolute_literals,
623 option_no_absolute_literals,
625 option_align_targets,
626 option_no_align_targets,
628 option_warn_unaligned_targets,
633 option_workaround_a0_b_retw,
634 option_no_workaround_a0_b_retw,
636 option_workaround_b_j_loop_end,
637 option_no_workaround_b_j_loop_end,
639 option_workaround_short_loop,
640 option_no_workaround_short_loop,
642 option_workaround_all_short_loops,
643 option_no_workaround_all_short_loops,
645 option_workaround_close_loop_end,
646 option_no_workaround_close_loop_end,
648 option_no_workarounds,
650 option_rename_section_name,
653 option_prefer_const16,
655 option_target_hardware
658 const char *md_shortopts = "";
660 struct option md_longopts[] =
662 { "density", no_argument, NULL, option_density },
663 { "no-density", no_argument, NULL, option_no_density },
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument, NULL, option_relax },
668 { "no-relax", no_argument, NULL, option_no_relax },
669 { "generics", no_argument, NULL, option_generics },
670 { "no-generics", no_argument, NULL, option_no_generics },
672 { "transform", no_argument, NULL, option_transform },
673 { "no-transform", no_argument, NULL, option_no_transform },
674 { "text-section-literals", no_argument, NULL, option_text_section_literals },
675 { "no-text-section-literals", no_argument, NULL,
676 option_no_text_section_literals },
677 { "absolute-literals", no_argument, NULL, option_absolute_literals },
678 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument, NULL, option_align_targets },
682 { "no-target-align", no_argument, NULL, option_no_align_targets },
683 { "warn-unaligned-targets", no_argument, NULL,
684 option_warn_unaligned_targets },
685 { "longcalls", no_argument, NULL, option_longcalls },
686 { "no-longcalls", no_argument, NULL, option_no_longcalls },
688 { "no-workaround-a0-b-retw", no_argument, NULL,
689 option_no_workaround_a0_b_retw },
690 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
692 { "no-workaround-b-j-loop-end", no_argument, NULL,
693 option_no_workaround_b_j_loop_end },
694 { "workaround-b-j-loop-end", no_argument, NULL,
695 option_workaround_b_j_loop_end },
697 { "no-workaround-short-loops", no_argument, NULL,
698 option_no_workaround_short_loop },
699 { "workaround-short-loops", no_argument, NULL,
700 option_workaround_short_loop },
702 { "no-workaround-all-short-loops", no_argument, NULL,
703 option_no_workaround_all_short_loops },
704 { "workaround-all-short-loop", no_argument, NULL,
705 option_workaround_all_short_loops },
707 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
708 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
710 { "no-workarounds", no_argument, NULL, option_no_workarounds },
712 { "no-workaround-close-loop-end", no_argument, NULL,
713 option_no_workaround_close_loop_end },
714 { "workaround-close-loop-end", no_argument, NULL,
715 option_workaround_close_loop_end },
717 { "rename-section", required_argument, NULL, option_rename_section_name },
719 { "link-relax", no_argument, NULL, option_link_relax },
720 { "no-link-relax", no_argument, NULL, option_no_link_relax },
722 { "target-hardware", required_argument, NULL, option_target_hardware },
724 { NULL, no_argument, NULL, 0 }
727 size_t md_longopts_size = sizeof md_longopts;
731 md_parse_option (int c, char *arg)
736 as_warn (_("--density option is ignored"));
738 case option_no_density:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax:
744 case option_no_link_relax:
747 case option_generics:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform, arg);
750 case option_no_generics:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform, arg);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform, arg);
756 case option_no_relax:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform, arg);
759 case option_longcalls:
760 directive_state[directive_longcalls] = TRUE;
762 case option_no_longcalls:
763 directive_state[directive_longcalls] = FALSE;
765 case option_text_section_literals:
766 use_literal_section = FALSE;
768 case option_no_text_section_literals:
769 use_literal_section = TRUE;
771 case option_absolute_literals:
772 if (!absolute_literals_supported)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state[directive_absolute_literals] = TRUE;
779 case option_no_absolute_literals:
780 directive_state[directive_absolute_literals] = FALSE;
783 case option_workaround_a0_b_retw:
784 workaround_a0_b_retw = TRUE;
786 case option_no_workaround_a0_b_retw:
787 workaround_a0_b_retw = FALSE;
789 case option_workaround_b_j_loop_end:
790 workaround_b_j_loop_end = TRUE;
792 case option_no_workaround_b_j_loop_end:
793 workaround_b_j_loop_end = FALSE;
796 case option_workaround_short_loop:
797 workaround_short_loop = TRUE;
799 case option_no_workaround_short_loop:
800 workaround_short_loop = FALSE;
803 case option_workaround_all_short_loops:
804 workaround_all_short_loops = TRUE;
806 case option_no_workaround_all_short_loops:
807 workaround_all_short_loops = FALSE;
810 case option_workaround_close_loop_end:
811 workaround_close_loop_end = TRUE;
813 case option_no_workaround_close_loop_end:
814 workaround_close_loop_end = FALSE;
817 case option_no_workarounds:
818 workaround_a0_b_retw = FALSE;
819 workaround_b_j_loop_end = FALSE;
820 workaround_short_loop = FALSE;
821 workaround_all_short_loops = FALSE;
822 workaround_close_loop_end = FALSE;
825 case option_align_targets:
826 align_targets = TRUE;
828 case option_no_align_targets:
829 align_targets = FALSE;
832 case option_warn_unaligned_targets:
833 warn_unaligned_branch_targets = TRUE;
836 case option_rename_section_name:
837 build_section_rename (arg);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware:
859 int earliest, latest = 0;
860 if (*arg == 0 || *arg == '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest = strtol (arg, &arg, 0);
867 else if (*arg == '-')
870 as_fatal (_("invalid target hardware version"));
871 latest = strtol (arg, &arg, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest, latest);
880 case option_transform:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state[directive_transform] = FALSE;
902 md_show_usage (FILE *stream)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS *sym)
924 if (!free_insn_labels)
925 l = (sym_list *) xmalloc (sizeof (sym_list));
928 l = free_insn_labels;
929 free_insn_labels = l->next;
933 l->next = insn_labels;
939 xtensa_clear_insn_labels (void)
943 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
979 for (lit = insn_labels; lit; lit = lit->next)
981 symbolS *lit_sym = lit->sym;
982 if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
984 S_SET_VALUE (lit_sym, new_offset);
985 symbol_set_frag (lit_sym, new_frag);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive;
997 bfd_boolean old_state;
1001 struct state_stackS_struct *prev;
1004 state_stackS *directive_state_stack;
1006 const pseudo_typeS md_pseudo_table[] =
1008 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position, 0 },
1010 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons, 4 },
1012 { "word", xtensa_elf_cons, 4 },
1013 { "short", xtensa_elf_cons, 2 },
1014 { "begin", xtensa_begin_directive, 0 },
1015 { "end", xtensa_end_directive, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc, 0 },
1017 { "literal", xtensa_literal_pseudo, 0 },
1018 { "frequency", xtensa_frequency_pseudo, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end);
1029 return directive_state[directive_transform];
1034 use_longcalls (void)
1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end);
1039 return directive_state[directive_longcalls] && use_transform ();
1044 do_align_targets (void)
1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end);
1049 return align_targets && use_transform ();
1054 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1058 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS));
1060 as_where (&file, &line);
1062 stack->directive = directive;
1063 stack->negated = negated;
1064 stack->old_state = directive_state[directive];
1067 stack->datum = datum;
1068 stack->prev = directive_state_stack;
1069 directive_state_stack = stack;
1071 directive_state[directive] = !negated;
1076 directive_pop (directiveE *directive,
1077 bfd_boolean *negated,
1082 state_stackS *top = directive_state_stack;
1084 if (!directive_state_stack)
1086 as_bad (_("unmatched end directive"));
1087 *directive = directive_none;
1091 directive_state[directive_state_stack->directive] = top->old_state;
1092 *directive = top->directive;
1093 *negated = top->negated;
1096 *datum = top->datum;
1097 directive_state_stack = top->prev;
1103 directive_balance (void)
1105 while (directive_state_stack)
1107 directiveE directive;
1108 bfd_boolean negated;
1113 directive_pop (&directive, &negated, &file, &line, &datum);
1114 as_warn_where ((char *) file, line,
1115 _(".begin directive with no matching .end directive"));
1121 inside_directive (directiveE dir)
1123 state_stackS *top = directive_state_stack;
1125 while (top && top->directive != dir)
1128 return (top != NULL);
1133 get_directive (directiveE *directive, bfd_boolean *negated)
1137 char *directive_string;
1139 if (strncmp (input_line_pointer, "no-", 3) != 0)
1144 input_line_pointer += 3;
1147 len = strspn (input_line_pointer,
1148 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1150 /* This code is a hack to make .begin [no-][generics|relax] exactly
1151 equivalent to .begin [no-]transform. We should remove it when
1152 we stop accepting those options. */
1154 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1156 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1157 directive_string = "transform";
1159 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1161 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1162 directive_string = "transform";
1165 directive_string = input_line_pointer;
1167 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1169 if (strncmp (directive_string, directive_info[i].name, len) == 0)
1171 input_line_pointer += len;
1172 *directive = (directiveE) i;
1173 if (*negated && !directive_info[i].can_be_negated)
1174 as_bad (_("directive %s cannot be negated"),
1175 directive_info[i].name);
1180 as_bad (_("unknown directive"));
1181 *directive = (directiveE) XTENSA_UNDEFINED;
1186 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1188 directiveE directive;
1189 bfd_boolean negated;
1194 get_directive (&directive, &negated);
1195 if (directive == (directiveE) XTENSA_UNDEFINED)
1197 discard_rest_of_line ();
1201 if (cur_vinsn.inside_bundle)
1202 as_bad (_("directives are not valid inside bundles"));
1206 case directive_literal:
1207 if (!inside_directive (directive_literal))
1209 /* Previous labels go with whatever follows this directive, not with
1210 the literal, so save them now. */
1211 saved_insn_labels = insn_labels;
1214 as_warn (_(".begin literal is deprecated; use .literal instead"));
1215 state = (emit_state *) xmalloc (sizeof (emit_state));
1216 xtensa_switch_to_literal_fragment (state);
1217 directive_push (directive_literal, negated, state);
1220 case directive_literal_prefix:
1221 /* Have to flush pending output because a movi relaxed to an l32r
1222 might produce a literal. */
1223 md_flush_pending_output ();
1224 /* Check to see if the current fragment is a literal
1225 fragment. If it is, then this operation is not allowed. */
1226 if (generating_literals)
1228 as_bad (_("cannot set literal_prefix inside literal fragment"));
1232 /* Allocate the literal state for this section and push
1233 onto the directive stack. */
1234 ls = xmalloc (sizeof (lit_state));
1237 *ls = default_lit_sections;
1239 directive_push (directive_literal_prefix, negated, ls);
1241 /* Parse the new prefix from the input_line_pointer. */
1243 len = strspn (input_line_pointer,
1244 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1245 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1247 /* Process the new prefix. */
1248 xtensa_literal_prefix (input_line_pointer, len);
1250 /* Skip the name in the input line. */
1251 input_line_pointer += len;
1254 case directive_freeregs:
1255 /* This information is currently unused, but we'll accept the statement
1256 and just discard the rest of the line. This won't check the syntax,
1257 but it will accept every correct freeregs directive. */
1258 input_line_pointer += strcspn (input_line_pointer, "\n");
1259 directive_push (directive_freeregs, negated, 0);
1262 case directive_schedule:
1263 md_flush_pending_output ();
1264 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1265 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1266 directive_push (directive_schedule, negated, 0);
1267 xtensa_set_frag_assembly_state (frag_now);
1270 case directive_density:
1271 as_warn (_(".begin [no-]density is ignored"));
1274 case directive_absolute_literals:
1275 md_flush_pending_output ();
1276 if (!absolute_literals_supported && !negated)
1278 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1281 xtensa_set_frag_assembly_state (frag_now);
1282 directive_push (directive, negated, 0);
1286 md_flush_pending_output ();
1287 xtensa_set_frag_assembly_state (frag_now);
1288 directive_push (directive, negated, 0);
1292 demand_empty_rest_of_line ();
1297 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1299 directiveE begin_directive, end_directive;
1300 bfd_boolean begin_negated, end_negated;
1304 emit_state **state_ptr;
1307 if (cur_vinsn.inside_bundle)
1308 as_bad (_("directives are not valid inside bundles"));
1310 get_directive (&end_directive, &end_negated);
1312 md_flush_pending_output ();
1314 switch (end_directive)
1316 case (directiveE) XTENSA_UNDEFINED:
1317 discard_rest_of_line ();
1320 case directive_density:
1321 as_warn (_(".end [no-]density is ignored"));
1322 demand_empty_rest_of_line ();
1325 case directive_absolute_literals:
1326 if (!absolute_literals_supported && !end_negated)
1328 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1329 demand_empty_rest_of_line ();
1338 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1339 directive_pop (&begin_directive, &begin_negated, &file, &line,
1340 (const void **) state_ptr);
1342 if (begin_directive != directive_none)
1344 if (begin_directive != end_directive || begin_negated != end_negated)
1346 as_bad (_("does not match begin %s%s at %s:%d"),
1347 begin_negated ? "no-" : "",
1348 directive_info[begin_directive].name, file, line);
1352 switch (end_directive)
1354 case directive_literal:
1355 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1356 xtensa_restore_emit_state (state);
1357 xtensa_set_frag_assembly_state (frag_now);
1359 if (!inside_directive (directive_literal))
1361 /* Restore the list of current labels. */
1362 xtensa_clear_insn_labels ();
1363 insn_labels = saved_insn_labels;
1367 case directive_literal_prefix:
1368 /* Restore the default collection sections from saved state. */
1369 s = (lit_state *) state;
1372 if (use_literal_section)
1373 default_lit_sections = *s;
1375 /* free the state storage */
1379 case directive_schedule:
1380 case directive_freeregs:
1384 xtensa_set_frag_assembly_state (frag_now);
1390 demand_empty_rest_of_line ();
1394 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1396 static bfd_boolean xtensa_loc_directive_seen = FALSE;
1399 xtensa_dwarf2_directive_loc (int x)
1401 xtensa_loc_directive_seen = TRUE;
1402 dwarf2_directive_loc (x);
1407 xtensa_dwarf2_emit_insn (int size, struct dwarf2_line_info *loc)
1409 if (debug_type != DEBUG_DWARF2 && ! xtensa_loc_directive_seen)
1411 xtensa_loc_directive_seen = FALSE;
1412 dwarf2_gen_line_info (frag_now_fix () - size, loc);
1416 /* Place an aligned literal fragment at the current location. */
1419 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1421 md_flush_pending_output ();
1423 if (inside_directive (directive_literal))
1424 as_warn (_(".literal_position inside literal directive; ignoring"));
1425 xtensa_mark_literal_pool_location ();
1427 demand_empty_rest_of_line ();
1428 xtensa_clear_insn_labels ();
1432 /* Support .literal label, expr, ... */
1435 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1438 char *p, *base_name;
1442 if (inside_directive (directive_literal))
1444 as_bad (_(".literal not allowed inside .begin literal region"));
1445 ignore_rest_of_line ();
1449 md_flush_pending_output ();
1451 /* Previous labels go with whatever follows this directive, not with
1452 the literal, so save them now. */
1453 saved_insn_labels = insn_labels;
1456 /* If we are using text-section literals, then this is the right value... */
1459 base_name = input_line_pointer;
1461 xtensa_switch_to_literal_fragment (&state);
1463 /* ...but if we aren't using text-section-literals, then we
1464 need to put them in the section we just switched to. */
1465 if (use_literal_section || directive_state[directive_absolute_literals])
1468 /* All literals are aligned to four-byte boundaries. */
1469 frag_align (2, 0, 0);
1470 record_alignment (now_seg, 2);
1472 c = get_symbol_end ();
1473 /* Just after name is now '\0'. */
1474 p = input_line_pointer;
1478 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1480 as_bad (_("expected comma or colon after symbol name; "
1481 "rest of line ignored"));
1482 ignore_rest_of_line ();
1483 xtensa_restore_emit_state (&state);
1491 input_line_pointer++; /* skip ',' or ':' */
1493 xtensa_elf_cons (4);
1495 xtensa_restore_emit_state (&state);
1497 /* Restore the list of current labels. */
1498 xtensa_clear_insn_labels ();
1499 insn_labels = saved_insn_labels;
1504 xtensa_literal_prefix (char const *start, int len)
1506 char *name, *linkonce_suffix;
1507 char *newname, *newname4;
1508 size_t linkonce_len;
1510 /* Get a null-terminated copy of the name. */
1511 name = xmalloc (len + 1);
1514 strncpy (name, start, len);
1517 /* Allocate the sections (interesting note: the memory pointing to
1518 the name is actually used for the name by the new section). */
1520 newname = xmalloc (len + strlen (".literal") + 1);
1521 newname4 = xmalloc (len + strlen (".lit4") + 1);
1523 linkonce_len = sizeof (".gnu.linkonce.") - 1;
1524 if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
1525 && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
1527 strcpy (newname, ".gnu.linkonce.literal");
1528 strcpy (newname4, ".gnu.linkonce.lit4");
1530 strcat (newname, linkonce_suffix);
1531 strcat (newname4, linkonce_suffix);
1535 int suffix_pos = len;
1537 /* If the section name ends with ".text", then replace that suffix
1538 instead of appending an additional suffix. */
1539 if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
1542 strcpy (newname, name);
1543 strcpy (newname4, name);
1545 strcpy (newname + suffix_pos, ".literal");
1546 strcpy (newname4 + suffix_pos, ".lit4");
1549 /* Note that cache_literal_section does not create a segment if
1550 it already exists. */
1551 default_lit_sections.lit_seg = NULL;
1552 default_lit_sections.lit4_seg = NULL;
1554 /* Canonicalizing section names allows renaming literal
1555 sections to occur correctly. */
1556 default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
1557 default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
1563 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1566 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1568 float fall_through_f, target_f;
1570 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1571 if (fall_through_f < 0)
1573 as_bad (_("fall through frequency must be greater than 0"));
1574 ignore_rest_of_line ();
1578 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1581 as_bad (_("branch target frequency must be greater than 0"));
1582 ignore_rest_of_line ();
1586 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1588 demand_empty_rest_of_line ();
1592 /* Like normal .long/.short/.word, except support @plt, etc.
1593 Clobbers input_line_pointer, checks end-of-line. */
1596 xtensa_elf_cons (int nbytes)
1599 bfd_reloc_code_real_type reloc;
1601 md_flush_pending_output ();
1603 if (cur_vinsn.inside_bundle)
1604 as_bad (_("directives are not valid inside bundles"));
1606 if (is_it_end_of_statement ())
1608 demand_empty_rest_of_line ();
1615 if (exp.X_op == O_symbol
1616 && *input_line_pointer == '@'
1617 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1620 reloc_howto_type *reloc_howto =
1621 bfd_reloc_type_lookup (stdoutput, reloc);
1623 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1624 as_bad (_("unsupported relocation"));
1625 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1626 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1627 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1628 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1629 as_bad (_("opcode-specific %s relocation used outside "
1630 "an instruction"), reloc_howto->name);
1631 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1632 as_bad (_("%s relocations do not fit in %d bytes"),
1633 reloc_howto->name, nbytes);
1636 char *p = frag_more ((int) nbytes);
1637 xtensa_set_frag_assembly_state (frag_now);
1638 fix_new_exp (frag_now, p - frag_now->fr_literal,
1639 nbytes, &exp, 0, reloc);
1643 emit_expr (&exp, (unsigned int) nbytes);
1645 while (*input_line_pointer++ == ',');
1647 input_line_pointer--; /* Put terminator back into stream. */
1648 demand_empty_rest_of_line ();
1652 /* Parsing and Idiom Translation. */
1654 /* Parse @plt, etc. and return the desired relocation. */
1655 static bfd_reloc_code_real_type
1656 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1662 bfd_reloc_code_real_type reloc;
1670 struct map_bfd *ptr;
1672 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1674 static struct map_bfd mapping[] =
1676 MAP ("l", BFD_RELOC_LO16),
1677 MAP ("h", BFD_RELOC_HI16),
1678 MAP ("plt", BFD_RELOC_XTENSA_PLT),
1679 { (char *) 0, 0, BFD_RELOC_UNUSED }
1683 return BFD_RELOC_NONE;
1685 for (ch = *str, str2 = ident;
1686 (str2 < ident + sizeof (ident) - 1
1687 && (ISALNUM (ch) || ch == '@'));
1690 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1697 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
1698 if (ch == ptr->string[0]
1699 && len == ptr->length
1700 && memcmp (ident, ptr->string, ptr->length) == 0)
1702 /* Now check for "identifier@suffix+constant". */
1703 if (*str == '-' || *str == '+')
1705 char *orig_line = input_line_pointer;
1706 expressionS new_exp;
1708 input_line_pointer = str;
1709 expression (&new_exp);
1710 if (new_exp.X_op == O_constant)
1712 exp_p->X_add_number += new_exp.X_add_number;
1713 str = input_line_pointer;
1716 if (&input_line_pointer != str_p)
1717 input_line_pointer = orig_line;
1724 return BFD_RELOC_UNUSED;
1729 expression_end (const char *name)
1752 #define ERROR_REG_NUM ((unsigned) -1)
1755 tc_get_register (const char *prefix)
1758 const char *next_expr;
1759 const char *old_line_pointer;
1762 old_line_pointer = input_line_pointer;
1764 if (*input_line_pointer == '$')
1765 ++input_line_pointer;
1767 /* Accept "sp" as a synonym for "a1". */
1768 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1769 && expression_end (input_line_pointer + 2))
1771 input_line_pointer += 2;
1772 return 1; /* AR[1] */
1775 while (*input_line_pointer++ == *prefix++)
1777 --input_line_pointer;
1782 as_bad (_("bad register name: %s"), old_line_pointer);
1783 return ERROR_REG_NUM;
1786 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1788 as_bad (_("bad register number: %s"), input_line_pointer);
1789 return ERROR_REG_NUM;
1794 while (ISDIGIT ((int) *input_line_pointer))
1795 reg = reg * 10 + *input_line_pointer++ - '0';
1797 if (!(next_expr = expression_end (input_line_pointer)))
1799 as_bad (_("bad register name: %s"), old_line_pointer);
1800 return ERROR_REG_NUM;
1803 input_line_pointer = (char *) next_expr;
1810 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1812 xtensa_isa isa = xtensa_default_isa;
1814 /* Check if this is an immediate operand. */
1815 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1817 bfd_reloc_code_real_type reloc;
1818 segT t = expression (tok);
1819 if (t == absolute_section
1820 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1822 assert (tok->X_op == O_constant);
1823 tok->X_op = O_symbol;
1824 tok->X_add_symbol = &abs_symbol;
1827 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1828 && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1829 && (reloc != BFD_RELOC_NONE))
1834 case BFD_RELOC_UNUSED:
1835 as_bad (_("unsupported relocation"));
1838 case BFD_RELOC_XTENSA_PLT:
1839 tok->X_op = O_pltrel;
1842 case BFD_RELOC_LO16:
1843 if (tok->X_op == O_constant)
1844 tok->X_add_number &= 0xffff;
1849 case BFD_RELOC_HI16:
1850 if (tok->X_op == O_constant)
1851 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1860 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1861 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1863 if (reg != ERROR_REG_NUM) /* Already errored */
1866 if (xtensa_operand_encode (isa, opc, opnd, &buf))
1867 as_bad (_("register number out of range"));
1870 tok->X_op = O_register;
1871 tok->X_add_symbol = 0;
1872 tok->X_add_number = reg;
1877 /* Split up the arguments for an opcode or pseudo-op. */
1880 tokenize_arguments (char **args, char *str)
1882 char *old_input_line_pointer;
1883 bfd_boolean saw_comma = FALSE;
1884 bfd_boolean saw_arg = FALSE;
1885 bfd_boolean saw_colon = FALSE;
1887 char *arg_end, *arg;
1890 /* Save and restore input_line_pointer around this function. */
1891 old_input_line_pointer = input_line_pointer;
1892 input_line_pointer = str;
1894 while (*input_line_pointer)
1897 switch (*input_line_pointer)
1904 input_line_pointer++;
1905 if (saw_comma || saw_colon || !saw_arg)
1911 input_line_pointer++;
1912 if (saw_comma || saw_colon || !saw_arg)
1918 if (!saw_comma && !saw_colon && saw_arg)
1921 arg_end = input_line_pointer + 1;
1922 while (!expression_end (arg_end))
1925 arg_len = arg_end - input_line_pointer;
1926 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
1927 args[num_args] = arg;
1931 strncpy (arg, input_line_pointer, arg_len);
1932 arg[arg_len] = '\0';
1934 input_line_pointer = arg_end;
1944 if (saw_comma || saw_colon)
1946 input_line_pointer = old_input_line_pointer;
1951 as_bad (_("extra comma"));
1953 as_bad (_("extra colon"));
1955 as_bad (_("missing argument"));
1957 as_bad (_("missing comma or colon"));
1958 input_line_pointer = old_input_line_pointer;
1963 /* Parse the arguments to an opcode. Return TRUE on error. */
1966 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
1968 expressionS *tok, *last_tok;
1969 xtensa_opcode opcode = insn->opcode;
1970 bfd_boolean had_error = TRUE;
1971 xtensa_isa isa = xtensa_default_isa;
1972 int n, num_regs = 0;
1973 int opcode_operand_count;
1974 int opnd_cnt, last_opnd_cnt;
1975 unsigned int next_reg = 0;
1976 char *old_input_line_pointer;
1978 if (insn->insn_type == ITYPE_LITERAL)
1979 opcode_operand_count = 1;
1981 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
1984 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
1986 /* Save and restore input_line_pointer around this function. */
1987 old_input_line_pointer = input_line_pointer;
1993 /* Skip invisible operands. */
1994 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2000 for (n = 0; n < num_args; n++)
2002 input_line_pointer = arg_strings[n];
2003 if (*input_line_pointer == ':')
2005 xtensa_regfile opnd_rf;
2006 input_line_pointer++;
2009 assert (opnd_cnt > 0);
2011 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2013 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2014 as_warn (_("incorrect register number, ignoring"));
2019 if (opnd_cnt >= opcode_operand_count)
2021 as_warn (_("too many arguments"));
2024 assert (opnd_cnt < MAX_INSN_ARGS);
2026 expression_maybe_register (opcode, opnd_cnt, tok);
2027 next_reg = tok->X_add_number + 1;
2029 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2031 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2033 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2034 /* minus 1 because we are seeing one right now */
2040 last_opnd_cnt = opnd_cnt;
2047 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2051 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2054 insn->ntok = tok - insn->tok;
2058 input_line_pointer = old_input_line_pointer;
2064 get_invisible_operands (TInsn *insn)
2066 xtensa_isa isa = xtensa_default_isa;
2067 static xtensa_insnbuf slotbuf = NULL;
2069 xtensa_opcode opc = insn->opcode;
2070 int slot, opnd, fmt_found;
2074 slotbuf = xtensa_insnbuf_alloc (isa);
2076 /* Find format/slot where this can be encoded. */
2079 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2081 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2083 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2089 if (fmt_found) break;
2094 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2098 /* First encode all the visible operands
2099 (to deal with shared field operands). */
2100 for (opnd = 0; opnd < insn->ntok; opnd++)
2102 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2103 && (insn->tok[opnd].X_op == O_register
2104 || insn->tok[opnd].X_op == O_constant))
2106 val = insn->tok[opnd].X_add_number;
2107 xtensa_operand_encode (isa, opc, opnd, &val);
2108 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2112 /* Then pull out the values for the invisible ones. */
2113 for (opnd = 0; opnd < insn->ntok; opnd++)
2115 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2117 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2118 xtensa_operand_decode (isa, opc, opnd, &val);
2119 insn->tok[opnd].X_add_number = val;
2120 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2121 insn->tok[opnd].X_op = O_register;
2123 insn->tok[opnd].X_op = O_constant;
2132 xg_reverse_shift_count (char **cnt_argp)
2134 char *cnt_arg, *new_arg;
2135 cnt_arg = *cnt_argp;
2137 /* replace the argument with "31-(argument)" */
2138 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6);
2139 sprintf (new_arg, "31-(%s)", cnt_arg);
2142 *cnt_argp = new_arg;
2146 /* If "arg" is a constant expression, return non-zero with the value
2150 xg_arg_is_constant (char *arg, offsetT *valp)
2153 char *save_ptr = input_line_pointer;
2155 input_line_pointer = arg;
2157 input_line_pointer = save_ptr;
2159 if (exp.X_op == O_constant)
2161 *valp = exp.X_add_number;
2170 xg_replace_opname (char **popname, char *newop)
2173 *popname = (char *) xmalloc (strlen (newop) + 1);
2174 strcpy (*popname, newop);
2179 xg_check_num_args (int *pnum_args,
2184 int num_args = *pnum_args;
2186 if (num_args < expected_num)
2188 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2189 num_args, opname, expected_num);
2193 if (num_args > expected_num)
2195 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2196 num_args, opname, expected_num);
2197 while (num_args-- > expected_num)
2199 free (arg_strings[num_args]);
2200 arg_strings[num_args] = 0;
2202 *pnum_args = expected_num;
2210 /* If the register is not specified as part of the opcode,
2211 then get it from the operand and move it to the opcode. */
2214 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2216 xtensa_isa isa = xtensa_default_isa;
2218 char *opname, *new_opname;
2219 const char *sr_name;
2220 int is_user, is_write;
2221 bfd_boolean has_underbar = FALSE;
2226 has_underbar = TRUE;
2229 is_user = (opname[1] == 'u');
2230 is_write = (opname[0] == 'w');
2232 /* Opname == [rw]ur or [rwx]sr... */
2234 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2237 /* Check if the argument is a symbolic register name. */
2238 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2239 /* Handle WSR to "INTSET" as a special case. */
2240 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2241 && !strcasecmp (arg_strings[1], "intset"))
2242 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2243 if (sr == XTENSA_UNDEFINED
2244 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2246 /* Maybe it's a register number.... */
2248 if (!xg_arg_is_constant (arg_strings[1], &val))
2250 as_bad (_("invalid register '%s' for '%s' instruction"),
2251 arg_strings[1], opname);
2254 sr = xtensa_sysreg_lookup (isa, val, is_user);
2255 if (sr == XTENSA_UNDEFINED)
2257 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2263 /* Remove the last argument, which is now part of the opcode. */
2264 free (arg_strings[1]);
2268 /* Translate the opcode. */
2269 sr_name = xtensa_sysreg_name (isa, sr);
2270 /* Another special case for "WSR.INTSET".... */
2271 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2273 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2274 sprintf (new_opname, "%s%s.%s", (has_underbar ? "_" : ""),
2277 *popname = new_opname;
2284 xtensa_translate_old_userreg_ops (char **popname)
2286 xtensa_isa isa = xtensa_default_isa;
2288 char *opname, *new_opname;
2289 const char *sr_name;
2290 bfd_boolean has_underbar = FALSE;
2293 if (opname[0] == '_')
2295 has_underbar = TRUE;
2299 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2300 if (sr != XTENSA_UNDEFINED)
2302 /* The new default name ("nnn") is different from the old default
2303 name ("URnnn"). The old default is handled below, and we don't
2304 want to recognize [RW]nnn, so do nothing if the name is the (new)
2306 static char namebuf[10];
2307 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2308 if (strcmp (namebuf, opname + 1) == 0)
2316 /* Only continue if the reg name is "URnnn". */
2317 if (opname[1] != 'u' || opname[2] != 'r')
2319 val = strtoul (opname + 3, &end, 10);
2323 sr = xtensa_sysreg_lookup (isa, val, 1);
2324 if (sr == XTENSA_UNDEFINED)
2326 as_bad (_("invalid register number (%ld) for '%s'"),
2332 /* Translate the opcode. */
2333 sr_name = xtensa_sysreg_name (isa, sr);
2334 new_opname = (char *) xmalloc (strlen (sr_name) + 6);
2335 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2336 opname[0], sr_name);
2338 *popname = new_opname;
2345 xtensa_translate_zero_immed (char *old_op,
2355 assert (opname[0] != '_');
2357 if (strcmp (opname, old_op) != 0)
2360 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2362 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2364 xg_replace_opname (popname, new_op);
2365 free (arg_strings[1]);
2366 arg_strings[1] = arg_strings[2];
2375 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2376 Returns non-zero if an error was found. */
2379 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2381 char *opname = *popname;
2382 bfd_boolean has_underbar = FALSE;
2384 if (cur_vinsn.inside_bundle)
2389 has_underbar = TRUE;
2393 if (strcmp (opname, "mov") == 0)
2395 if (use_transform () && !has_underbar && density_supported)
2396 xg_replace_opname (popname, "mov.n");
2399 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2401 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2402 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
2403 strcpy (arg_strings[2], arg_strings[1]);
2409 if (strcmp (opname, "bbsi.l") == 0)
2411 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2413 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2414 if (target_big_endian)
2415 xg_reverse_shift_count (&arg_strings[1]);
2419 if (strcmp (opname, "bbci.l") == 0)
2421 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2423 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2424 if (target_big_endian)
2425 xg_reverse_shift_count (&arg_strings[1]);
2429 if (xtensa_nop_opcode == XTENSA_UNDEFINED
2430 && strcmp (opname, "nop") == 0)
2432 if (use_transform () && !has_underbar && density_supported)
2433 xg_replace_opname (popname, "nop.n");
2436 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2438 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2439 arg_strings[0] = (char *) xmalloc (3);
2440 arg_strings[1] = (char *) xmalloc (3);
2441 arg_strings[2] = (char *) xmalloc (3);
2442 strcpy (arg_strings[0], "a1");
2443 strcpy (arg_strings[1], "a1");
2444 strcpy (arg_strings[2], "a1");
2450 /* Recognize [RW]UR and [RWX]SR. */
2451 if ((((opname[0] == 'r' || opname[0] == 'w')
2452 && (opname[1] == 'u' || opname[1] == 's'))
2453 || (opname[0] == 'x' && opname[1] == 's'))
2455 && opname[3] == '\0')
2456 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2458 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2459 [RW]<name> if <name> is the non-default name of a user register. */
2460 if ((opname[0] == 'r' || opname[0] == 'w')
2461 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2462 return xtensa_translate_old_userreg_ops (popname);
2464 /* Relax branches that don't allow comparisons against an immediate value
2465 of zero to the corresponding branches with implicit zero immediates. */
2466 if (!has_underbar && use_transform ())
2468 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2469 pnum_args, arg_strings))
2472 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2473 pnum_args, arg_strings))
2476 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2477 pnum_args, arg_strings))
2480 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2481 pnum_args, arg_strings))
2489 /* Functions for dealing with the Xtensa ISA. */
2491 /* Currently the assembler only allows us to use a single target per
2492 fragment. Because of this, only one operand for a given
2493 instruction may be symbolic. If there is a PC-relative operand,
2494 the last one is chosen. Otherwise, the result is the number of the
2495 last immediate operand, and if there are none of those, we fail and
2499 get_relaxable_immed (xtensa_opcode opcode)
2501 int last_immed = -1;
2504 if (opcode == XTENSA_UNDEFINED)
2507 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2508 for (opi = noperands - 1; opi >= 0; opi--)
2510 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2512 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2514 if (last_immed == -1
2515 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2522 static xtensa_opcode
2523 get_opcode_from_buf (const char *buf, int slot)
2525 static xtensa_insnbuf insnbuf = NULL;
2526 static xtensa_insnbuf slotbuf = NULL;
2527 xtensa_isa isa = xtensa_default_isa;
2532 insnbuf = xtensa_insnbuf_alloc (isa);
2533 slotbuf = xtensa_insnbuf_alloc (isa);
2536 xtensa_insnbuf_from_chars (isa, insnbuf, buf, 0);
2537 fmt = xtensa_format_decode (isa, insnbuf);
2538 if (fmt == XTENSA_UNDEFINED)
2539 return XTENSA_UNDEFINED;
2541 if (slot >= xtensa_format_num_slots (isa, fmt))
2542 return XTENSA_UNDEFINED;
2544 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2545 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2549 #ifdef TENSILICA_DEBUG
2551 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2554 xtensa_print_insn_table (void)
2556 int num_opcodes, num_operands;
2557 xtensa_opcode opcode;
2558 xtensa_isa isa = xtensa_default_isa;
2560 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2561 for (opcode = 0; opcode < num_opcodes; opcode++)
2564 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2565 num_operands = xtensa_opcode_num_operands (isa, opcode);
2566 for (opn = 0; opn < num_operands; opn++)
2568 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2570 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2572 xtensa_regfile opnd_rf =
2573 xtensa_operand_regfile (isa, opcode, opn);
2574 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2576 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2577 fputs ("[lLr] ", stderr);
2579 fputs ("i ", stderr);
2581 fprintf (stderr, "\n");
2587 print_vliw_insn (xtensa_insnbuf vbuf)
2589 xtensa_isa isa = xtensa_default_isa;
2590 xtensa_format f = xtensa_format_decode (isa, vbuf);
2591 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2594 fprintf (stderr, "format = %d\n", f);
2596 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2598 xtensa_opcode opcode;
2602 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2603 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2604 opname = xtensa_opcode_name (isa, opcode);
2606 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2607 fprintf (stderr, " operands = ");
2609 operands < xtensa_opcode_num_operands (isa, opcode);
2613 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2615 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2616 xtensa_operand_decode (isa, opcode, operands, &val);
2617 fprintf (stderr, "%d ", val);
2619 fprintf (stderr, "\n");
2621 xtensa_insnbuf_free (isa, sbuf);
2624 #endif /* TENSILICA_DEBUG */
2628 is_direct_call_opcode (xtensa_opcode opcode)
2630 xtensa_isa isa = xtensa_default_isa;
2631 int n, num_operands;
2633 if (xtensa_opcode_is_call (isa, opcode) == 0)
2636 num_operands = xtensa_opcode_num_operands (isa, opcode);
2637 for (n = 0; n < num_operands; n++)
2639 if (xtensa_operand_is_register (isa, opcode, n) == 0
2640 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2647 /* Convert from BFD relocation type code to slot and operand number.
2648 Returns non-zero on failure. */
2651 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2653 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2654 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2656 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2659 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2660 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2662 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2672 /* Convert from slot number to BFD relocation type code for the
2673 standard PC-relative relocations. Return BFD_RELOC_NONE on
2676 static bfd_reloc_code_real_type
2677 encode_reloc (int slot)
2679 if (slot < 0 || slot > 14)
2680 return BFD_RELOC_NONE;
2682 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2686 /* Convert from slot numbers to BFD relocation type code for the
2687 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2689 static bfd_reloc_code_real_type
2690 encode_alt_reloc (int slot)
2692 if (slot < 0 || slot > 14)
2693 return BFD_RELOC_NONE;
2695 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2700 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2703 xtensa_opcode opcode,
2709 uint32 valbuf = value;
2711 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2713 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2715 as_bad_where ((char *) file, line,
2716 _("operand %u is out of range for '%s'"), value,
2717 xtensa_opcode_name (xtensa_default_isa, opcode));
2719 as_bad_where ((char *) file, line,
2720 _("operand %u is invalid for '%s'"), value,
2721 xtensa_opcode_name (xtensa_default_isa, opcode));
2725 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2731 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2734 xtensa_opcode opcode,
2738 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2739 fmt, slot, slotbuf, &val);
2740 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2745 /* Checks for rules from xtensa-relax tables. */
2747 /* The routine xg_instruction_matches_option_term must return TRUE
2748 when a given option term is true. The meaning of all of the option
2749 terms is given interpretation by this function. This is needed when
2750 an option depends on the state of a directive, but there are no such
2751 options in use right now. */
2754 xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
2755 const ReqOrOption *option)
2757 if (strcmp (option->option_name, "realnop") == 0
2758 || strncmp (option->option_name, "IsaUse", 6) == 0)
2760 /* These conditions were evaluated statically when building the
2761 relaxation table. There's no need to reevaluate them now. */
2766 as_fatal (_("internal error: unknown option name '%s'"),
2767 option->option_name);
2773 xg_instruction_matches_or_options (TInsn *insn,
2774 const ReqOrOptionList *or_option)
2776 const ReqOrOption *option;
2777 /* Must match each of the AND terms. */
2778 for (option = or_option; option != NULL; option = option->next)
2780 if (xg_instruction_matches_option_term (insn, option))
2788 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2790 const ReqOption *req_options;
2791 /* Must match each of the AND terms. */
2792 for (req_options = options;
2793 req_options != NULL;
2794 req_options = req_options->next)
2796 /* Must match one of the OR clauses. */
2797 if (!xg_instruction_matches_or_options (insn,
2798 req_options->or_option_terms))
2805 /* Return the transition rule that matches or NULL if none matches. */
2808 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2810 PreconditionList *condition_l;
2812 if (rule->opcode != insn->opcode)
2815 for (condition_l = rule->conditions;
2816 condition_l != NULL;
2817 condition_l = condition_l->next)
2821 Precondition *cond = condition_l->precond;
2826 /* The expression must be the constant. */
2827 assert (cond->op_num < insn->ntok);
2828 exp1 = &insn->tok[cond->op_num];
2829 if (expr_is_const (exp1))
2834 if (get_expr_const (exp1) != cond->op_data)
2838 if (get_expr_const (exp1) == cond->op_data)
2845 else if (expr_is_register (exp1))
2850 if (get_expr_register (exp1) != cond->op_data)
2854 if (get_expr_register (exp1) == cond->op_data)
2866 assert (cond->op_num < insn->ntok);
2867 assert (cond->op_data < insn->ntok);
2868 exp1 = &insn->tok[cond->op_num];
2869 exp2 = &insn->tok[cond->op_data];
2874 if (!expr_is_equal (exp1, exp2))
2878 if (expr_is_equal (exp1, exp2))
2890 if (!xg_instruction_matches_options (insn, rule->options))
2898 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
2900 bfd_boolean a_greater = FALSE;
2901 bfd_boolean b_greater = FALSE;
2903 ReqOptionList *l_a = a->options;
2904 ReqOptionList *l_b = b->options;
2906 /* We only care if they both are the same except for
2907 a const16 vs. an l32r. */
2909 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2911 ReqOrOptionList *l_or_a = l_a->or_option_terms;
2912 ReqOrOptionList *l_or_b = l_b->or_option_terms;
2913 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
2915 if (l_or_a->is_true != l_or_b->is_true)
2917 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
2919 /* This is the case we care about. */
2920 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
2921 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
2928 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
2929 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
2939 l_or_a = l_or_a->next;
2940 l_or_b = l_or_b->next;
2942 if (l_or_a || l_or_b)
2951 /* Incomparable if the substitution was used differently in two cases. */
2952 if (a_greater && b_greater)
2964 static TransitionRule *
2965 xg_instruction_match (TInsn *insn)
2967 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
2969 assert (insn->opcode < table->num_opcodes);
2971 /* Walk through all of the possible transitions. */
2972 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
2974 TransitionRule *rule = l->rule;
2975 if (xg_instruction_matches_rule (insn, rule))
2982 /* Various Other Internal Functions. */
2985 is_unique_insn_expansion (TransitionRule *r)
2987 if (!r->to_instr || r->to_instr->next != NULL)
2989 if (r->to_instr->typ != INSTR_INSTR)
2996 xg_get_build_instr_size (BuildInstr *insn)
2998 assert (insn->typ == INSTR_INSTR);
2999 return xg_get_single_size (insn->opcode);
3004 xg_is_narrow_insn (TInsn *insn)
3006 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3009 assert (insn->insn_type == ITYPE_INSN);
3010 assert (insn->opcode < table->num_opcodes);
3012 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3014 TransitionRule *rule = l->rule;
3016 if (xg_instruction_matches_rule (insn, rule)
3017 && is_unique_insn_expansion (rule))
3019 /* It only generates one instruction... */
3020 assert (insn->insn_type == ITYPE_INSN);
3021 /* ...and it is a larger instruction. */
3022 if (xg_get_single_size (insn->opcode)
3023 < xg_get_build_instr_size (rule->to_instr))
3031 return (num_match == 1);
3036 xg_is_single_relaxable_insn (TInsn *insn)
3038 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3041 assert (insn->insn_type == ITYPE_INSN);
3042 assert (insn->opcode < table->num_opcodes);
3044 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3046 TransitionRule *rule = l->rule;
3048 if (xg_instruction_matches_rule (insn, rule)
3049 && is_unique_insn_expansion (rule))
3051 /* It only generates one instruction... */
3052 assert (insn->insn_type == ITYPE_INSN);
3053 /* ... and it is a larger instruction. */
3054 if (xg_get_single_size (insn->opcode)
3055 <= xg_get_build_instr_size (rule->to_instr))
3063 return (num_match == 1);
3067 /* Return the maximum number of bytes this opcode can expand to. */
3070 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3072 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3074 int max_size = xg_get_single_size (opcode);
3076 assert (opcode < table->num_opcodes);
3078 for (l = table->table[opcode]; l != NULL; l = l->next)
3080 TransitionRule *rule = l->rule;
3081 BuildInstr *build_list;
3086 build_list = rule->to_instr;
3087 if (is_unique_insn_expansion (rule))
3089 assert (build_list->typ == INSTR_INSTR);
3090 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3093 for (; build_list != NULL; build_list = build_list->next)
3095 switch (build_list->typ)
3098 this_size += xg_get_single_size (build_list->opcode);
3100 case INSTR_LITERAL_DEF:
3101 case INSTR_LABEL_DEF:
3106 if (this_size > max_size)
3107 max_size = this_size;
3113 /* Return the maximum number of literal bytes this opcode can generate. */
3116 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3118 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3122 assert (opcode < table->num_opcodes);
3124 for (l = table->table[opcode]; l != NULL; l = l->next)
3126 TransitionRule *rule = l->rule;
3127 BuildInstr *build_list;
3132 build_list = rule->to_instr;
3133 if (is_unique_insn_expansion (rule))
3135 assert (build_list->typ == INSTR_INSTR);
3136 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3139 for (; build_list != NULL; build_list = build_list->next)
3141 switch (build_list->typ)
3143 case INSTR_LITERAL_DEF:
3144 /* Hard-coded 4-byte literal. */
3148 case INSTR_LABEL_DEF:
3153 if (this_size > max_size)
3154 max_size = this_size;
3161 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3163 int steps_taken = 0;
3164 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3167 assert (insn->insn_type == ITYPE_INSN);
3168 assert (insn->opcode < table->num_opcodes);
3170 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3172 TransitionRule *rule = l->rule;
3174 if (xg_instruction_matches_rule (insn, rule))
3176 if (steps_taken == lateral_steps)
3186 get_special_literal_symbol (void)
3188 static symbolS *sym = NULL;
3191 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3197 get_special_label_symbol (void)
3199 static symbolS *sym = NULL;
3202 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3208 xg_valid_literal_expression (const expressionS *exp)
3225 /* This will check to see if the value can be converted into the
3226 operand type. It will return TRUE if it does not fit. */
3229 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3231 uint32 valbuf = value;
3232 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3238 /* Assumes: All immeds are constants. Check that all constants fit
3239 into their immeds; return FALSE if not. */
3242 xg_immeds_fit (const TInsn *insn)
3244 xtensa_isa isa = xtensa_default_isa;
3248 assert (insn->insn_type == ITYPE_INSN);
3249 for (i = 0; i < n; ++i)
3251 const expressionS *expr = &insn->tok[i];
3252 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3259 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3264 /* The symbol should have a fixup associated with it. */
3273 /* This should only be called after we have an initial
3274 estimate of the addresses. */
3277 xg_symbolic_immeds_fit (const TInsn *insn,
3283 xtensa_isa isa = xtensa_default_isa;
3291 assert (insn->insn_type == ITYPE_INSN);
3293 for (i = 0; i < n; ++i)
3295 const expressionS *expr = &insn->tok[i];
3296 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3303 if (xg_check_operand (expr->X_add_number, insn->opcode, i))
3309 /* Check for the worst case. */
3310 if (xg_check_operand (0xffff, insn->opcode, i))
3315 /* We only allow symbols for pc-relative stuff.
3316 If pc_frag == 0, then we don't have frag locations yet. */
3320 /* If it is PC-relative and the symbol is not in the same
3321 segment as the PC.... */
3322 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0
3323 || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
3326 /* If it is a weak symbol, then assume it won't reach. This will
3327 only affect calls when longcalls are enabled, because if
3328 longcalls are disabled, then the call is marked as a specific
3330 if (S_IS_WEAK (expr->X_add_symbol))
3333 symbolP = expr->X_add_symbol;
3334 sym_frag = symbol_get_frag (symbolP);
3335 target = S_GET_VALUE (symbolP) + expr->X_add_number;
3336 pc = pc_frag->fr_address + pc_offset;
3338 /* If frag has yet to be reached on this pass, assume it
3339 will move by STRETCH just as we did. If this is not so,
3340 it will be because some frag between grows, and that will
3341 force another pass. Beware zero-length frags. There
3342 should be a faster way to do this. */
3345 && sym_frag->relax_marker != pc_frag->relax_marker
3346 && S_GET_SEGMENT (symbolP) == pc_seg)
3351 new_offset = target;
3352 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3353 if (xg_check_operand (new_offset, insn->opcode, i))
3358 /* The symbol should have a fixup associated with it. */
3367 /* Return TRUE on success. */
3370 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3375 memset (targ, 0, sizeof (TInsn));
3376 targ->loc = insn->loc;
3381 targ->opcode = bi->opcode;
3382 targ->insn_type = ITYPE_INSN;
3383 targ->is_specific_opcode = FALSE;
3385 for (; op != NULL; op = op->next)
3387 int op_num = op->op_num;
3388 int op_data = op->op_data;
3390 assert (op->op_num < MAX_INSN_ARGS);
3392 if (targ->ntok <= op_num)
3393 targ->ntok = op_num + 1;
3398 set_expr_const (&targ->tok[op_num], op_data);
3401 assert (op_data < insn->ntok);
3402 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3405 sym = get_special_literal_symbol ();
3406 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3409 sym = get_special_label_symbol ();
3410 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3412 case OP_OPERAND_HI16U:
3413 case OP_OPERAND_LOW16U:
3414 assert (op_data < insn->ntok);
3415 if (expr_is_const (&insn->tok[op_data]))
3418 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3419 val = xg_apply_userdef_op_fn (op->typ,
3422 targ->tok[op_num].X_add_number = val;
3426 /* For const16 we can create relocations for these. */
3427 if (targ->opcode == XTENSA_UNDEFINED
3428 || (targ->opcode != xtensa_const16_opcode))
3430 assert (op_data < insn->ntok);
3431 /* Need to build a O_lo16 or O_hi16. */
3432 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3433 if (targ->tok[op_num].X_op == O_symbol)
3435 if (op->typ == OP_OPERAND_HI16U)
3436 targ->tok[op_num].X_op = O_hi16;
3437 else if (op->typ == OP_OPERAND_LOW16U)
3438 targ->tok[op_num].X_op = O_lo16;
3445 /* currently handles:
3448 OP_OPERAND_F32MINUS */
3449 if (xg_has_userdef_op_fn (op->typ))
3451 assert (op_data < insn->ntok);
3452 if (expr_is_const (&insn->tok[op_data]))
3455 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3456 val = xg_apply_userdef_op_fn (op->typ,
3459 targ->tok[op_num].X_add_number = val;
3462 return FALSE; /* We cannot use a relocation for this. */
3471 case INSTR_LITERAL_DEF:
3473 targ->opcode = XTENSA_UNDEFINED;
3474 targ->insn_type = ITYPE_LITERAL;
3475 targ->is_specific_opcode = FALSE;
3476 for (; op != NULL; op = op->next)
3478 int op_num = op->op_num;
3479 int op_data = op->op_data;
3480 assert (op->op_num < MAX_INSN_ARGS);
3482 if (targ->ntok <= op_num)
3483 targ->ntok = op_num + 1;
3488 assert (op_data < insn->ntok);
3489 /* We can only pass resolvable literals through. */
3490 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3492 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3504 case INSTR_LABEL_DEF:
3506 targ->opcode = XTENSA_UNDEFINED;
3507 targ->insn_type = ITYPE_LABEL;
3508 targ->is_specific_opcode = FALSE;
3509 /* Literal with no ops is a label? */
3510 assert (op == NULL);
3521 /* Return TRUE on success. */
3524 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3526 for (; bi != NULL; bi = bi->next)
3528 TInsn *next_insn = istack_push_space (istack);
3530 if (!xg_build_to_insn (next_insn, insn, bi))
3537 /* Return TRUE on valid expansion. */
3540 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3542 int stack_size = istack->ninsn;
3543 int steps_taken = 0;
3544 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3547 assert (insn->insn_type == ITYPE_INSN);
3548 assert (insn->opcode < table->num_opcodes);
3550 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3552 TransitionRule *rule = l->rule;
3554 if (xg_instruction_matches_rule (insn, rule))
3556 if (lateral_steps == steps_taken)
3560 /* This is it. Expand the rule to the stack. */
3561 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3564 /* Check to see if it fits. */
3565 for (i = stack_size; i < istack->ninsn; i++)
3567 TInsn *insn = &istack->insn[i];
3569 if (insn->insn_type == ITYPE_INSN
3570 && !tinsn_has_symbolic_operands (insn)
3571 && !xg_immeds_fit (insn))
3573 istack->ninsn = stack_size;
3587 xg_expand_narrow (TInsn *targ, TInsn *insn)
3589 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3592 assert (insn->insn_type == ITYPE_INSN);
3593 assert (insn->opcode < table->num_opcodes);
3595 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3597 TransitionRule *rule = l->rule;
3598 if (xg_instruction_matches_rule (insn, rule)
3599 && is_unique_insn_expansion (rule))
3601 /* Is it a larger instruction? */
3602 if (xg_get_single_size (insn->opcode)
3603 <= xg_get_build_instr_size (rule->to_instr))
3605 xg_build_to_insn (targ, insn, rule->to_instr);
3614 /* Relax the assembly instruction at least "min_steps".
3615 Return the number of steps taken. */
3618 xg_assembly_relax (IStack *istack,
3621 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3622 offsetT pc_offset, /* offset in fragment */
3623 int min_steps, /* minimum conversion steps */
3624 long stretch) /* number of bytes stretched so far */
3626 int steps_taken = 0;
3628 /* assert (has no symbolic operands)
3629 Some of its immeds don't fit.
3630 Try to build a relaxed version.
3631 This may go through a couple of stages
3632 of single instruction transformations before
3635 TInsn single_target;
3637 int lateral_steps = 0;
3638 int istack_size = istack->ninsn;
3640 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3641 && steps_taken >= min_steps)
3643 istack_push (istack, insn);
3646 current_insn = *insn;
3648 /* Walk through all of the single instruction expansions. */
3649 while (xg_is_single_relaxable_insn (¤t_insn))
3651 int error_val = xg_expand_narrow (&single_target, ¤t_insn);
3653 assert (!error_val);
3655 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3659 if (steps_taken >= min_steps)
3661 istack_push (istack, &single_target);
3665 current_insn = single_target;
3668 /* Now check for a multi-instruction expansion. */
3669 while (xg_is_relaxable_insn (¤t_insn, lateral_steps))
3671 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset,
3674 if (steps_taken >= min_steps)
3676 istack_push (istack, ¤t_insn);
3681 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps))
3683 if (steps_taken >= min_steps)
3687 istack->ninsn = istack_size;
3690 /* It's not going to work -- use the original. */
3691 istack_push (istack, insn);
3697 xg_force_frag_space (int size)
3699 /* This may have the side effect of creating a new fragment for the
3700 space to go into. I just do not like the name of the "frag"
3707 xg_finish_frag (char *last_insn,
3708 enum xtensa_relax_statesE frag_state,
3709 enum xtensa_relax_statesE slot0_state,
3711 bfd_boolean is_insn)
3713 /* Finish off this fragment so that it has at LEAST the desired
3714 max_growth. If it doesn't fit in this fragment, close this one
3715 and start a new one. In either case, return a pointer to the
3716 beginning of the growth area. */
3720 xg_force_frag_space (max_growth);
3722 old_frag = frag_now;
3724 frag_now->fr_opcode = last_insn;
3726 frag_now->tc_frag_data.is_insn = TRUE;
3728 frag_var (rs_machine_dependent, max_growth, max_growth,
3729 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3731 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3732 xtensa_set_frag_assembly_state (frag_now);
3734 /* Just to make sure that we did not split it up. */
3735 assert (old_frag->fr_next == frag_now);
3739 /* Return TRUE if the target frag is one of the next non-empty frags. */
3742 is_next_frag_target (const fragS *fragP, const fragS *target)
3747 for (; fragP; fragP = fragP->fr_next)
3749 if (fragP == target)
3751 if (fragP->fr_fix != 0)
3753 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3755 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3756 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3758 if (fragP->fr_type == rs_space)
3766 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3768 xtensa_isa isa = xtensa_default_isa;
3770 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3775 if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
3776 && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
3779 for (i = 0; i < num_ops; i++)
3781 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3787 if (target_op == -1)
3790 if (insn->ntok <= target_op)
3793 if (insn->tok[target_op].X_op != O_symbol)
3796 sym = insn->tok[target_op].X_add_symbol;
3800 if (insn->tok[target_op].X_add_number != 0)
3803 target_frag = symbol_get_frag (sym);
3804 if (target_frag == NULL)
3807 if (is_next_frag_target (fragP->fr_next, target_frag)
3808 && S_GET_VALUE (sym) == target_frag->fr_address)
3816 xg_add_branch_and_loop_targets (TInsn *insn)
3818 xtensa_isa isa = xtensa_default_isa;
3819 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3821 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3824 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3825 && insn->tok[i].X_op == O_symbol)
3826 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3830 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3831 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3835 for (i = 0; i < insn->ntok && i < num_ops; i++)
3837 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3838 && insn->tok[i].X_op == O_symbol)
3840 symbolS *sym = insn->tok[i].X_add_symbol;
3841 symbol_get_tc (sym)->is_branch_target = TRUE;
3842 if (S_IS_DEFINED (sym))
3843 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3850 /* Return FALSE if no error. */
3853 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3858 switch (instr_spec->typ)
3861 new_insn->insn_type = ITYPE_INSN;
3862 new_insn->opcode = instr_spec->opcode;
3863 new_insn->is_specific_opcode = FALSE;
3864 new_insn->loc = old_insn->loc;
3866 case INSTR_LITERAL_DEF:
3867 new_insn->insn_type = ITYPE_LITERAL;
3868 new_insn->opcode = XTENSA_UNDEFINED;
3869 new_insn->is_specific_opcode = FALSE;
3870 new_insn->loc = old_insn->loc;
3872 case INSTR_LABEL_DEF:
3873 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3877 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3880 const expressionS *src_exp;
3886 /* The expression must be the constant. */
3887 assert (b_op->op_num < MAX_INSN_ARGS);
3888 exp = &new_insn->tok[b_op->op_num];
3889 set_expr_const (exp, b_op->op_data);
3893 assert (b_op->op_num < MAX_INSN_ARGS);
3894 assert (b_op->op_data < (unsigned) old_insn->ntok);
3895 src_exp = &old_insn->tok[b_op->op_data];
3896 exp = &new_insn->tok[b_op->op_num];
3897 copy_expr (exp, src_exp);
3902 as_bad (_("can't handle generation of literal/labels yet"));
3906 as_bad (_("can't handle undefined OP TYPE"));
3911 new_insn->ntok = num_ops;
3916 /* Return TRUE if it was simplified. */
3919 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
3921 TransitionRule *rule;
3922 BuildInstr *insn_spec;
3924 if (old_insn->is_specific_opcode || !density_supported)
3927 rule = xg_instruction_match (old_insn);
3931 insn_spec = rule->to_instr;
3932 /* There should only be one. */
3933 assert (insn_spec != NULL);
3934 assert (insn_spec->next == NULL);
3935 if (insn_spec->next != NULL)
3938 xg_build_token_insn (insn_spec, old_insn, new_insn);
3944 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3945 l32i.n. (2) Check the number of operands. (3) Place the instruction
3946 tokens into the stack or if we can relax it at assembly time, place
3947 multiple instructions/literals onto the stack. Return FALSE if no
3951 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
3955 memset (&new_insn, 0, sizeof (TInsn));
3957 /* Narrow it if we can. xg_simplify_insn now does all the
3958 appropriate checking (e.g., for the density option). */
3959 if (xg_simplify_insn (orig_insn, &new_insn))
3960 orig_insn = &new_insn;
3962 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
3964 if (orig_insn->ntok < noperands)
3966 as_bad (_("found %d operands for '%s': Expected %d"),
3968 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3972 if (orig_insn->ntok > noperands)
3973 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3975 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
3978 /* If there are not enough operands, we will assert above. If there
3979 are too many, just cut out the extras here. */
3981 orig_insn->ntok = noperands;
3985 Instructions with all constant immeds:
3986 Assemble them and relax the instruction if possible.
3987 Give error if not possible; no fixup needed.
3989 Instructions with symbolic immeds:
3990 Assemble them with a Fix up (that may cause instruction expansion).
3991 Also close out the fragment if the fixup may cause instruction expansion.
3993 There are some other special cases where we need alignment.
3994 1) before certain instructions with required alignment (OPCODE_ALIGN)
3995 2) before labels that have jumps (LABEL_ALIGN)
3996 3) after call instructions (RETURN_ALIGN)
3997 Multiple of these may be possible on the same fragment.
3998 If so, make sure to satisfy the required alignment.
3999 Then try to get the desired alignment. */
4001 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4004 if (orig_insn->is_specific_opcode || !use_transform ())
4006 istack_push (istack, orig_insn);
4010 if (tinsn_has_symbolic_operands (orig_insn))
4012 if (tinsn_has_complex_operands (orig_insn))
4013 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4015 istack_push (istack, orig_insn);
4019 if (xg_immeds_fit (orig_insn))
4020 istack_push (istack, orig_insn);
4022 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4029 /* Return TRUE if the section flags are marked linkonce
4030 or the name is .gnu.linkonce*. */
4033 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4035 flagword flags, link_once_flags;
4037 flags = bfd_get_section_flags (abfd, sec);
4038 link_once_flags = (flags & SEC_LINK_ONCE);
4040 /* Flags might not be set yet. */
4041 if (!link_once_flags)
4043 static size_t len = sizeof ".gnu.linkonce.t.";
4045 if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
4046 link_once_flags = SEC_LINK_ONCE;
4048 return (link_once_flags != 0);
4053 xtensa_add_literal_sym (symbolS *sym)
4057 l = (sym_list *) xmalloc (sizeof (sym_list));
4059 l->next = literal_syms;
4065 xtensa_create_literal_symbol (segT sec, fragS *frag)
4067 static int lit_num = 0;
4068 static char name[256];
4071 sprintf (name, ".L_lit_sym%d", lit_num);
4073 /* Create a local symbol. If it is in a linkonce section, we have to
4074 be careful to make sure that if it is used in a relocation that the
4075 symbol will be in the output file. */
4076 if (get_is_linkonce_section (stdoutput, sec))
4078 symbolP = symbol_new (name, sec, 0, frag);
4079 S_CLEAR_EXTERNAL (symbolP);
4080 /* symbolP->local = 1; */
4083 symbolP = symbol_new (name, sec, 0, frag);
4085 xtensa_add_literal_sym (symbolP);
4087 frag->tc_frag_data.is_literal = TRUE;
4093 /* Currently all literals that are generated here are 32-bit L32R targets. */
4096 xg_assemble_literal (/* const */ TInsn *insn)
4099 symbolS *lit_sym = NULL;
4101 /* size = 4 for L32R. It could easily be larger when we move to
4102 larger constants. Add a parameter later. */
4103 offsetT litsize = 4;
4104 offsetT litalign = 2; /* 2^2 = 4 */
4105 expressionS saved_loc;
4106 expressionS * emit_val;
4108 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4110 assert (insn->insn_type == ITYPE_LITERAL);
4111 assert (insn->ntok == 1); /* must be only one token here */
4113 xtensa_switch_to_literal_fragment (&state);
4115 emit_val = &insn->tok[0];
4116 if (emit_val->X_op == O_big)
4118 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4121 /* This happens when someone writes a "movi a2, big_number". */
4122 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4123 _("invalid immediate"));
4124 xtensa_restore_emit_state (&state);
4129 /* Force a 4-byte align here. Note that this opens a new frag, so all
4130 literals done with this function have a frag to themselves. That's
4131 important for the way text section literals work. */
4132 frag_align (litalign, 0, 0);
4133 record_alignment (now_seg, litalign);
4135 if (emit_val->X_op == O_pltrel)
4137 char *p = frag_more (litsize);
4138 xtensa_set_frag_assembly_state (frag_now);
4139 if (emit_val->X_add_symbol)
4140 emit_val->X_op = O_symbol;
4142 emit_val->X_op = O_constant;
4143 fix_new_exp (frag_now, p - frag_now->fr_literal,
4144 litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
4147 emit_expr (emit_val, litsize);
4149 assert (frag_now->tc_frag_data.literal_frag == NULL);
4150 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4151 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4152 lit_sym = frag_now->fr_symbol;
4153 frag_now->tc_frag_data.is_literal = TRUE;
4156 xtensa_restore_emit_state (&state);
4162 xg_assemble_literal_space (/* const */ int size, int slot)
4165 /* We might have to do something about this alignment. It only
4166 takes effect if something is placed here. */
4167 offsetT litalign = 2; /* 2^2 = 4 */
4168 fragS *lit_saved_frag;
4170 assert (size % 4 == 0);
4172 xtensa_switch_to_literal_fragment (&state);
4174 /* Force a 4-byte align here. */
4175 frag_align (litalign, 0, 0);
4176 record_alignment (now_seg, litalign);
4178 xg_force_frag_space (size);
4180 lit_saved_frag = frag_now;
4181 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4182 frag_now->tc_frag_data.is_literal = TRUE;
4183 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4184 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4187 xtensa_restore_emit_state (&state);
4188 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4192 /* Put in a fixup record based on the opcode.
4193 Return TRUE on success. */
4196 xg_add_opcode_fix (TInsn *tinsn,
4204 xtensa_opcode opcode = tinsn->opcode;
4205 bfd_reloc_code_real_type reloc;
4206 reloc_howto_type *howto;
4210 reloc = BFD_RELOC_NONE;
4212 /* First try the special cases for "alternate" relocs. */
4213 if (opcode == xtensa_l32r_opcode)
4215 if (fragP->tc_frag_data.use_absolute_literals)
4216 reloc = encode_alt_reloc (slot);
4218 else if (opcode == xtensa_const16_opcode)
4220 if (expr->X_op == O_lo16)
4222 reloc = encode_reloc (slot);
4223 expr->X_op = O_symbol;
4225 else if (expr->X_op == O_hi16)
4227 reloc = encode_alt_reloc (slot);
4228 expr->X_op = O_symbol;
4232 if (opnum != get_relaxable_immed (opcode))
4234 as_bad (_("invalid relocation for operand %i of '%s'"),
4235 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4239 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4240 into the symbol table where the generic portions of the assembler
4241 won't know what to do with them. */
4242 if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
4244 as_bad (_("invalid expression for operand %i of '%s'"),
4245 opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
4249 /* Next try the generic relocs. */
4250 if (reloc == BFD_RELOC_NONE)
4251 reloc = encode_reloc (slot);
4252 if (reloc == BFD_RELOC_NONE)
4254 as_bad (_("invalid relocation in instruction slot %i"), slot);
4258 howto = bfd_reloc_type_lookup (stdoutput, reloc);
4261 as_bad (_("undefined symbol for opcode \"%s\""),
4262 xtensa_opcode_name (xtensa_default_isa, opcode));
4266 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4267 the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
4268 howto->pc_relative, reloc);
4269 the_fix->fx_no_overflow = 1;
4271 if (expr->X_add_symbol
4272 && (S_IS_EXTERNAL (expr->X_add_symbol)
4273 || S_IS_WEAK (expr->X_add_symbol)))
4274 the_fix->fx_plt = TRUE;
4276 the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
4277 the_fix->tc_fix_data.X_add_number = expr->X_add_number;
4278 the_fix->tc_fix_data.slot = slot;
4285 xg_emit_insn_to_buf (TInsn *tinsn,
4290 bfd_boolean build_fix)
4292 static xtensa_insnbuf insnbuf = NULL;
4293 bfd_boolean has_symbolic_immed = FALSE;
4294 bfd_boolean ok = TRUE;
4296 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4298 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4299 if (has_symbolic_immed && build_fix)
4302 int opnum = get_relaxable_immed (tinsn->opcode);
4303 expressionS *exp = &tinsn->tok[opnum];
4305 if (!xg_add_opcode_fix (tinsn, opnum, fmt, 0, exp, fragP, offset))
4308 fragP->tc_frag_data.is_insn = TRUE;
4309 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4315 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4317 symbolS *sym = get_special_literal_symbol ();
4321 assert (insn->insn_type == ITYPE_INSN);
4322 for (i = 0; i < insn->ntok; i++)
4323 if (insn->tok[i].X_add_symbol == sym)
4324 insn->tok[i].X_add_symbol = lit_sym;
4330 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4332 symbolS *sym = get_special_label_symbol ();
4334 /* assert (!insn->is_literal); */
4335 for (i = 0; i < insn->ntok; i++)
4336 if (insn->tok[i].X_add_symbol == sym)
4337 insn->tok[i].X_add_symbol = label_sym;
4342 /* Return TRUE if the instruction can write to the specified
4343 integer register. */
4346 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4350 xtensa_isa isa = xtensa_default_isa;
4352 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4354 for (i = 0; i < num_ops; i++)
4357 inout = xtensa_operand_inout (isa, insn->opcode, i);
4358 if ((inout == 'o' || inout == 'm')
4359 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4361 xtensa_regfile opnd_rf =
4362 xtensa_operand_regfile (isa, insn->opcode, i);
4363 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4365 if ((insn->tok[i].X_op == O_register)
4366 && (insn->tok[i].X_add_number == regnum))
4376 is_bad_loopend_opcode (const TInsn *tinsn)
4378 xtensa_opcode opcode = tinsn->opcode;
4380 if (opcode == XTENSA_UNDEFINED)
4383 if (opcode == xtensa_call0_opcode
4384 || opcode == xtensa_callx0_opcode
4385 || opcode == xtensa_call4_opcode
4386 || opcode == xtensa_callx4_opcode
4387 || opcode == xtensa_call8_opcode
4388 || opcode == xtensa_callx8_opcode
4389 || opcode == xtensa_call12_opcode
4390 || opcode == xtensa_callx12_opcode
4391 || opcode == xtensa_isync_opcode
4392 || opcode == xtensa_ret_opcode
4393 || opcode == xtensa_ret_n_opcode
4394 || opcode == xtensa_retw_opcode
4395 || opcode == xtensa_retw_n_opcode
4396 || opcode == xtensa_waiti_opcode
4397 || opcode == xtensa_rsr_lcount_opcode)
4404 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4405 This allows the debugger to add unaligned labels.
4406 Also, the assembler generates stabs labels that need
4407 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4410 is_unaligned_label (symbolS *sym)
4412 const char *name = S_GET_NAME (sym);
4413 static size_t fake_size = 0;
4417 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4420 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4422 fake_size = strlen (FAKE_LABEL_NAME);
4425 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4426 && (name[fake_size] == 'F'
4427 || name[fake_size] == 'L'
4428 || (name[fake_size] == 'e'
4429 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4437 next_non_empty_frag (const fragS *fragP)
4439 fragS *next_fragP = fragP->fr_next;
4441 /* Sometimes an empty will end up here due storage allocation issues.
4442 So we have to skip until we find something legit. */
4443 while (next_fragP && next_fragP->fr_fix == 0)
4444 next_fragP = next_fragP->fr_next;
4446 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4454 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4456 xtensa_opcode out_opcode;
4457 const fragS *next_fragP = next_non_empty_frag (fragP);
4459 if (next_fragP == NULL)
4462 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4463 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4465 *opcode = out_opcode;
4473 frag_format_size (const fragS *fragP)
4475 static xtensa_insnbuf insnbuf = NULL;
4476 xtensa_isa isa = xtensa_default_isa;
4481 insnbuf = xtensa_insnbuf_alloc (isa);
4484 return XTENSA_UNDEFINED;
4486 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal, 0);
4488 fmt = xtensa_format_decode (isa, insnbuf);
4489 if (fmt == XTENSA_UNDEFINED)
4490 return XTENSA_UNDEFINED;
4491 fmt_size = xtensa_format_length (isa, fmt);
4493 /* If the next format won't be changing due to relaxation, just
4494 return the length of the first format. */
4495 if (fragP->fr_opcode != fragP->fr_literal)
4498 /* If during relaxation we have to pull an instruction out of a
4499 multi-slot instruction, we will return the more conservative
4500 number. This works because alignment on bigger instructions
4501 is more restrictive than alignment on smaller instructions.
4502 This is more conservative than we would like, but it happens
4505 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4508 /* If we aren't doing one of our own relaxations or it isn't
4509 slot-based, then the insn size won't change. */
4510 if (fragP->fr_type != rs_machine_dependent)
4512 if (fragP->fr_subtype != RELAX_SLOTS)
4515 /* If an instruction is about to grow, return the longer size. */
4516 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4517 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
4520 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4521 return 2 + fragP->tc_frag_data.text_expansion[0];
4528 next_frag_format_size (const fragS *fragP)
4530 const fragS *next_fragP = next_non_empty_frag (fragP);
4531 return frag_format_size (next_fragP);
4535 /* If the next legit fragment is an end-of-loop marker,
4536 switch its state so it will instantiate a NOP. */
4539 update_next_frag_state (fragS *fragP)
4541 fragS *next_fragP = fragP->fr_next;
4542 fragS *new_target = NULL;
4546 /* We are guaranteed there will be one of these... */
4547 while (!(next_fragP->fr_type == rs_machine_dependent
4548 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4549 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4550 next_fragP = next_fragP->fr_next;
4552 assert (next_fragP->fr_type == rs_machine_dependent
4553 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4554 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4556 /* ...and one of these. */
4557 new_target = next_fragP->fr_next;
4558 while (!(new_target->fr_type == rs_machine_dependent
4559 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4560 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4561 new_target = new_target->fr_next;
4563 assert (new_target->fr_type == rs_machine_dependent
4564 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4565 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4568 while (next_fragP && next_fragP->fr_fix == 0)
4570 if (next_fragP->fr_type == rs_machine_dependent
4571 && next_fragP->fr_subtype == RELAX_LOOP_END)
4573 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4577 next_fragP = next_fragP->fr_next;
4583 next_frag_is_branch_target (const fragS *fragP)
4585 /* Sometimes an empty will end up here due to storage allocation issues,
4586 so we have to skip until we find something legit. */
4587 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4589 if (fragP->tc_frag_data.is_branch_target)
4591 if (fragP->fr_fix != 0)
4599 next_frag_is_loop_target (const fragS *fragP)
4601 /* Sometimes an empty will end up here due storage allocation issues.
4602 So we have to skip until we find something legit. */
4603 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4605 if (fragP->tc_frag_data.is_loop_target)
4607 if (fragP->fr_fix != 0)
4615 next_frag_pre_opcode_bytes (const fragS *fragp)
4617 const fragS *next_fragp = fragp->fr_next;
4618 xtensa_opcode next_opcode;
4620 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4623 /* Sometimes an empty will end up here due to storage allocation issues,
4624 so we have to skip until we find something legit. */
4625 while (next_fragp->fr_fix == 0)
4626 next_fragp = next_fragp->fr_next;
4628 if (next_fragp->fr_type != rs_machine_dependent)
4631 /* There is some implicit knowledge encoded in here.
4632 The LOOP instructions that are NOT RELAX_IMMED have
4633 been relaxed. Note that we can assume that the LOOP
4634 instruction is in slot 0 because loops aren't bundleable. */
4635 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4636 return get_expanded_loop_offset (next_opcode);
4642 /* Mark a location where we can later insert literal frags. Update
4643 the section's literal_pool_loc, so subsequent literals can be
4644 placed nearest to their use. */
4647 xtensa_mark_literal_pool_location (void)
4649 /* Any labels pointing to the current location need
4650 to be adjusted to after the literal pool. */
4652 fragS *pool_location;
4654 if (use_literal_section && !directive_state[directive_absolute_literals])
4657 frag_align (2, 0, 0);
4658 record_alignment (now_seg, 2);
4660 /* We stash info in the fr_var of these frags
4661 so we can later move the literal's fixes into this
4662 frchain's fix list. We can use fr_var because fr_var's
4663 interpretation depends solely on the fr_type and subtype. */
4664 pool_location = frag_now;
4665 frag_variant (rs_machine_dependent, 0, (int) frchain_now,
4666 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4667 xtensa_set_frag_assembly_state (frag_now);
4668 frag_variant (rs_machine_dependent, 0, (int) now_seg,
4669 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4670 xtensa_set_frag_assembly_state (frag_now);
4672 /* Now put a frag into the literal pool that points to this location. */
4673 set_literal_pool_location (now_seg, pool_location);
4674 xtensa_switch_to_non_abs_literal_fragment (&s);
4675 frag_align (2, 0, 0);
4676 record_alignment (now_seg, 2);
4678 /* Close whatever frag is there. */
4679 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4680 xtensa_set_frag_assembly_state (frag_now);
4681 frag_now->tc_frag_data.literal_frag = pool_location;
4682 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4683 xtensa_restore_emit_state (&s);
4684 xtensa_set_frag_assembly_state (frag_now);
4688 /* Build a nop of the correct size into tinsn. */
4691 build_nop (TInsn *tinsn, int size)
4697 tinsn->opcode = xtensa_nop_n_opcode;
4699 if (tinsn->opcode == XTENSA_UNDEFINED)
4700 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4704 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4706 tinsn->opcode = xtensa_or_opcode;
4707 set_expr_const (&tinsn->tok[0], 1);
4708 set_expr_const (&tinsn->tok[1], 1);
4709 set_expr_const (&tinsn->tok[2], 1);
4713 tinsn->opcode = xtensa_nop_opcode;
4715 assert (tinsn->opcode != XTENSA_UNDEFINED);
4720 /* Assemble a NOP of the requested size in the buffer. User must have
4721 allocated "buf" with at least "size" bytes. */
4724 assemble_nop (size_t size, char *buf)
4726 static xtensa_insnbuf insnbuf = NULL;
4729 build_nop (&tinsn, size);
4732 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4734 tinsn_to_insnbuf (&tinsn, insnbuf);
4735 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf, 0);
4739 /* Return the number of bytes for the offset of the expanded loop
4740 instruction. This should be incorporated into the relaxation
4741 specification but is hard-coded here. This is used to auto-align
4742 the loop instruction. It is invalid to call this function if the
4743 configuration does not have loops or if the opcode is not a loop
4747 get_expanded_loop_offset (xtensa_opcode opcode)
4749 /* This is the OFFSET of the loop instruction in the expanded loop.
4750 This MUST correspond directly to the specification of the loop
4751 expansion. It will be validated on fragment conversion. */
4752 assert (opcode != XTENSA_UNDEFINED);
4753 if (opcode == xtensa_loop_opcode)
4755 if (opcode == xtensa_loopnez_opcode)
4757 if (opcode == xtensa_loopgtz_opcode)
4759 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4765 get_literal_pool_location (segT seg)
4767 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4772 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4774 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4778 /* Set frag assembly state should be called when a new frag is
4779 opened and after a frag has been closed. */
4782 xtensa_set_frag_assembly_state (fragS *fragP)
4784 if (!density_supported)
4785 fragP->tc_frag_data.is_no_density = TRUE;
4787 /* This function is called from subsegs_finish, which is called
4788 after xtensa_end, so we can't use "use_transform" or
4789 "use_schedule" here. */
4790 if (!directive_state[directive_transform])
4791 fragP->tc_frag_data.is_no_transform = TRUE;
4792 fragP->tc_frag_data.use_absolute_literals =
4793 directive_state[directive_absolute_literals];
4794 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4799 relaxable_section (asection *sec)
4801 return (sec->flags & SEC_DEBUGGING) == 0;
4806 xtensa_find_unmarked_state_frags (void)
4810 /* Walk over each fragment of all of the current segments. For each
4811 unmarked fragment, mark it with the same info as the previous
4813 for (seclist = &stdoutput->sections;
4814 seclist && *seclist;
4815 seclist = &(*seclist)->next)
4817 segT sec = *seclist;
4818 segment_info_type *seginfo;
4821 flags = bfd_get_section_flags (stdoutput, sec);
4822 if (flags & SEC_DEBUGGING)
4824 if (!(flags & SEC_ALLOC))
4827 seginfo = seg_info (sec);
4828 if (seginfo && seginfo->frchainP)
4830 fragS *last_fragP = 0;
4831 for (fragP = seginfo->frchainP->frch_root; fragP;
4832 fragP = fragP->fr_next)
4834 if (fragP->fr_fix != 0
4835 && !fragP->tc_frag_data.is_assembly_state_set)
4837 if (last_fragP == 0)
4839 as_warn_where (fragP->fr_file, fragP->fr_line,
4840 _("assembly state not set for first frag in section %s"),
4845 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4846 fragP->tc_frag_data.is_no_density =
4847 last_fragP->tc_frag_data.is_no_density;
4848 fragP->tc_frag_data.is_no_transform =
4849 last_fragP->tc_frag_data.is_no_transform;
4850 fragP->tc_frag_data.use_absolute_literals =
4851 last_fragP->tc_frag_data.use_absolute_literals;
4854 if (fragP->tc_frag_data.is_assembly_state_set)
4863 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
4865 void *unused ATTRIBUTE_UNUSED)
4867 flagword flags = bfd_get_section_flags (abfd, sec);
4868 segment_info_type *seginfo = seg_info (sec);
4869 fragS *frag = seginfo->frchainP->frch_root;
4871 if (flags & SEC_CODE)
4873 xtensa_isa isa = xtensa_default_isa;
4874 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4875 while (frag != NULL)
4877 if (frag->tc_frag_data.is_branch_target)
4883 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4884 fmt = xtensa_format_decode (isa, insnbuf);
4885 op_size = xtensa_format_length (isa, fmt);
4886 frag_addr = frag->fr_address % xtensa_fetch_width;
4887 if (frag_addr + op_size > (int) xtensa_fetch_width)
4888 as_warn_where (frag->fr_file, frag->fr_line,
4889 _("unaligned branch target: %d bytes at 0x%lx"),
4890 op_size, frag->fr_address);
4892 frag = frag->fr_next;
4894 xtensa_insnbuf_free (isa, insnbuf);
4900 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
4902 void *unused ATTRIBUTE_UNUSED)
4904 flagword flags = bfd_get_section_flags (abfd, sec);
4905 segment_info_type *seginfo = seg_info (sec);
4906 fragS *frag = seginfo->frchainP->frch_root;
4907 xtensa_isa isa = xtensa_default_isa;
4909 if (flags & SEC_CODE)
4911 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
4912 while (frag != NULL)
4914 if (frag->tc_frag_data.is_first_loop_insn)
4920 xtensa_insnbuf_from_chars (isa, insnbuf, frag->fr_literal, 0);
4921 fmt = xtensa_format_decode (isa, insnbuf);
4922 op_size = xtensa_format_length (isa, fmt);
4923 frag_addr = frag->fr_address % xtensa_fetch_width;
4925 if (frag_addr + op_size > (signed) xtensa_fetch_width)
4926 as_warn_where (frag->fr_file, frag->fr_line,
4927 _("unaligned loop: %d bytes at 0x%lx"),
4928 op_size, frag->fr_address);
4930 frag = frag->fr_next;
4932 xtensa_insnbuf_free (isa, insnbuf);
4938 xg_apply_fix_value (fixS *fixP, valueT val)
4940 xtensa_isa isa = xtensa_default_isa;
4941 static xtensa_insnbuf insnbuf = NULL;
4942 static xtensa_insnbuf slotbuf = NULL;
4945 bfd_boolean alt_reloc;
4946 xtensa_opcode opcode;
4947 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
4949 (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
4951 as_fatal (_("unexpected fix"));
4955 insnbuf = xtensa_insnbuf_alloc (isa);
4956 slotbuf = xtensa_insnbuf_alloc (isa);
4959 xtensa_insnbuf_from_chars (isa, insnbuf, fixpos, 0);
4960 fmt = xtensa_format_decode (isa, insnbuf);
4961 if (fmt == XTENSA_UNDEFINED)
4962 as_fatal (_("undecodable fix"));
4963 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
4964 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
4965 if (opcode == XTENSA_UNDEFINED)
4966 as_fatal (_("undecodable fix"));
4968 /* CONST16 immediates are not PC-relative, despite the fact that we
4969 reuse the normal PC-relative operand relocations for the low part
4970 of a CONST16 operand. */
4971 if (opcode == xtensa_const16_opcode)
4974 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
4975 get_relaxable_immed (opcode), val,
4976 fixP->fx_file, fixP->fx_line);
4978 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
4979 xtensa_insnbuf_to_chars (isa, insnbuf, fixpos, 0);
4985 /* External Functions and Other GAS Hooks. */
4988 xtensa_target_format (void)
4990 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
4995 xtensa_file_arch_init (bfd *abfd)
4997 bfd_set_private_flags (abfd, 0x100 | 0x200);
5002 md_number_to_chars (char *buf, valueT val, int n)
5004 if (target_big_endian)
5005 number_to_chars_bigendian (buf, val, n);
5007 number_to_chars_littleendian (buf, val, n);
5011 /* This function is called once, at assembler startup time. It should
5012 set up all the tables, etc. that the MD part of the assembler will
5018 segT current_section = now_seg;
5019 int current_subsec = now_subseg;
5022 xtensa_default_isa = xtensa_isa_init (0, 0);
5023 isa = xtensa_default_isa;
5027 /* Set up the .literal, .fini.literal and .init.literal sections. */
5028 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5029 default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
5030 default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
5031 default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
5032 default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
5034 subseg_set (current_section, current_subsec);
5036 xg_init_vinsn (&cur_vinsn);
5038 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5039 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5040 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5041 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5042 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5043 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5044 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5045 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5046 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5047 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5048 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5049 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5050 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5051 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5052 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5053 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5054 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5055 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5056 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5057 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5058 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5059 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5060 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5061 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5062 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5063 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5064 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5065 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5066 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5068 init_op_placement_info_table ();
5070 /* Set up the assembly state. */
5071 if (!frag_now->tc_frag_data.is_assembly_state_set)
5072 xtensa_set_frag_assembly_state (frag_now);
5076 /* TC_INIT_FIX_DATA hook */
5079 xtensa_init_fix_data (fixS *x)
5081 x->tc_fix_data.slot = 0;
5082 x->tc_fix_data.X_add_symbol = NULL;
5083 x->tc_fix_data.X_add_number = 0;
5087 /* tc_frob_label hook */
5090 xtensa_frob_label (symbolS *sym)
5092 /* Since the label was already attached to a frag associated with the
5093 previous basic block, it now needs to be reset to the current frag. */
5094 symbol_set_frag (sym, frag_now);
5095 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5097 if (generating_literals)
5098 xtensa_add_literal_sym (sym);
5100 xtensa_add_insn_label (sym);
5102 if (symbol_get_tc (sym)->is_loop_target
5103 && (get_last_insn_flags (now_seg, now_subseg)
5104 & FLAG_IS_BAD_LOOPEND) != 0)
5105 as_bad (_("invalid last instruction for a zero-overhead loop"));
5107 /* No target aligning in the absolute section. */
5108 if (now_seg != absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym)
5111 && !generating_literals)
5113 float freq = get_subseg_target_freq (now_seg, now_subseg);
5114 xtensa_set_frag_assembly_state (frag_now);
5116 /* The only time this type of frag grows is when there is a
5117 negatable branch that needs to be relaxed as the last
5118 instruction in a zero-overhead loop. Because alignment frags
5119 are so common, marking them all as possibly growing four
5120 bytes makes any worst-case analysis appear much worse than it
5121 is. So, we make fr_var not actually reflect the amount of
5122 memory allocated at the end of this frag, but rather the
5123 amount of memory this frag might grow. The "4, 0" below
5124 allocates four bytes at the end of the frag for room to grow
5125 if we need to relax a loop end with a NOP. Frags prior to
5126 this one might grow to align this one, but the frag itself
5127 won't grow unless it meets the condition above. */
5129 #define RELAX_LOOP_END_BYTES 4
5131 frag_var (rs_machine_dependent,
5132 RELAX_LOOP_END_BYTES, (int) freq,
5133 RELAX_DESIRE_ALIGN_IF_TARGET,
5134 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5135 xtensa_set_frag_assembly_state (frag_now);
5136 xtensa_move_labels (frag_now, 0, TRUE);
5139 /* We need to mark the following properties even if we aren't aligning. */
5141 /* If the label is already known to be a branch target, i.e., a
5142 forward branch, mark the frag accordingly. Backward branches
5143 are handled by xg_add_branch_and_loop_targets. */
5144 if (symbol_get_tc (sym)->is_branch_target)
5145 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5147 /* Loops only go forward, so they can be identified here. */
5148 if (symbol_get_tc (sym)->is_loop_target)
5149 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5153 /* tc_unrecognized_line hook */
5156 xtensa_unrecognized_line (int ch)
5161 if (cur_vinsn.inside_bundle == 0)
5163 /* PR8110: Cannot emit line number info inside a FLIX bundle
5164 when using --gstabs. Temporarily disable debug info. */
5165 generate_lineno_debug ();
5166 if (debug_type == DEBUG_STABS)
5168 xt_saved_debug_type = debug_type;
5169 debug_type = DEBUG_NONE;
5172 cur_vinsn.inside_bundle = 1;
5176 as_bad (_("extra opening brace"));
5182 if (cur_vinsn.inside_bundle)
5183 finish_vinsn (&cur_vinsn);
5186 as_bad (_("extra closing brace"));
5191 as_bad (_("syntax error"));
5198 /* md_flush_pending_output hook */
5201 xtensa_flush_pending_output (void)
5203 if (cur_vinsn.inside_bundle)
5204 as_bad (_("missing closing brace"));
5206 /* If there is a non-zero instruction fragment, close it. */
5207 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5209 frag_wane (frag_now);
5211 xtensa_set_frag_assembly_state (frag_now);
5213 frag_now->tc_frag_data.is_insn = FALSE;
5215 xtensa_clear_insn_labels ();
5219 /* We had an error while parsing an instruction. The string might look
5220 like this: "insn arg1, arg2 }". If so, we need to see the closing
5221 brace and reset some fields. Otherwise, the vinsn never gets closed
5222 and the num_slots field will grow past the end of the array of slots,
5223 and bad things happen. */
5226 error_reset_cur_vinsn (void)
5228 if (cur_vinsn.inside_bundle)
5230 if (*input_line_pointer == '}'
5231 || *(input_line_pointer - 1) == '}'
5232 || *(input_line_pointer - 2) == '}')
5233 xg_clear_vinsn (&cur_vinsn);
5239 md_assemble (char *str)
5241 xtensa_isa isa = xtensa_default_isa;
5244 bfd_boolean has_underbar = FALSE;
5245 char *arg_strings[MAX_INSN_ARGS];
5247 TInsn orig_insn; /* Original instruction from the input. */
5249 tinsn_init (&orig_insn);
5251 /* Split off the opcode. */
5252 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5253 opname = xmalloc (opnamelen + 1);
5254 memcpy (opname, str, opnamelen);
5255 opname[opnamelen] = '\0';
5257 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5260 as_bad (_("syntax error"));
5264 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5267 /* Check for an underbar prefix. */
5270 has_underbar = TRUE;
5274 orig_insn.insn_type = ITYPE_INSN;
5276 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5278 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5279 if (orig_insn.opcode == XTENSA_UNDEFINED)
5281 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5282 if (fmt == XTENSA_UNDEFINED)
5284 as_bad (_("unknown opcode or format name '%s'"), opname);
5285 error_reset_cur_vinsn ();
5288 if (!cur_vinsn.inside_bundle)
5290 as_bad (_("format names only valid inside bundles"));
5291 error_reset_cur_vinsn ();
5294 if (cur_vinsn.format != XTENSA_UNDEFINED)
5295 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5297 cur_vinsn.format = fmt;
5298 free (has_underbar ? opname - 1 : opname);
5299 error_reset_cur_vinsn ();
5303 /* Special case: The call instructions should be marked "specific opcode"
5304 to keep them from expanding. */
5305 if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
5306 orig_insn.is_specific_opcode = TRUE;
5308 /* Parse the arguments. */
5309 if (parse_arguments (&orig_insn, num_args, arg_strings))
5311 as_bad (_("syntax error"));
5312 error_reset_cur_vinsn ();
5316 /* Free the opcode and argument strings, now that they've been parsed. */
5317 free (has_underbar ? opname - 1 : opname);
5319 while (num_args-- > 0)
5320 free (arg_strings[num_args]);
5322 /* Get expressions for invisible operands. */
5323 if (get_invisible_operands (&orig_insn))
5325 error_reset_cur_vinsn ();
5329 /* Check for the right number and type of arguments. */
5330 if (tinsn_check_arguments (&orig_insn))
5332 error_reset_cur_vinsn ();
5336 dwarf2_where (&orig_insn.loc);
5338 xg_add_branch_and_loop_targets (&orig_insn);
5340 /* Special-case for "entry" instruction. */
5341 if (orig_insn.opcode == xtensa_entry_opcode)
5343 /* Check that the third opcode (#2) is >= 16. */
5344 if (orig_insn.ntok >= 3)
5346 expressionS *exp = &orig_insn.tok[2];
5350 if (exp->X_add_number < 16)
5351 as_warn (_("entry instruction with stack decrement < 16"));
5355 as_warn (_("entry instruction with non-constant decrement"));
5361 assemble_tokens (opcode, tok, ntok);
5362 expand the tokens from the orig_insn into the
5363 stack of instructions that will not expand
5364 unless required at relaxation time. */
5366 if (!cur_vinsn.inside_bundle)
5367 emit_single_op (&orig_insn);
5368 else /* We are inside a bundle. */
5370 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5371 cur_vinsn.num_slots++;
5372 if (*input_line_pointer == '}'
5373 || *(input_line_pointer - 1) == '}'
5374 || *(input_line_pointer - 2) == '}')
5375 finish_vinsn (&cur_vinsn);
5378 /* We've just emitted a new instruction so clear the list of labels. */
5379 xtensa_clear_insn_labels ();
5383 /* HANDLE_ALIGN hook */
5385 /* For a .align directive, we mark the previous block with the alignment
5386 information. This will be placed in the object file in the
5387 property section corresponding to this section. */
5390 xtensa_handle_align (fragS *fragP)
5393 && ! fragP->tc_frag_data.is_literal
5394 && (fragP->fr_type == rs_align
5395 || fragP->fr_type == rs_align_code)
5396 && fragP->fr_address + fragP->fr_fix > 0
5397 && fragP->fr_offset > 0
5398 && now_seg != bss_section)
5400 fragP->tc_frag_data.is_align = TRUE;
5401 fragP->tc_frag_data.alignment = fragP->fr_offset;
5404 if (fragP->fr_type == rs_align_test)
5407 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5409 as_bad_where (fragP->fr_file, fragP->fr_line,
5410 _("unaligned entry instruction"));
5415 /* TC_FRAG_INIT hook */
5418 xtensa_frag_init (fragS *frag)
5420 xtensa_set_frag_assembly_state (frag);
5425 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5431 /* Round up a section size to the appropriate boundary. */
5434 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5436 return size; /* Byte alignment is fine. */
5441 md_pcrel_from (fixS *fixP)
5444 static xtensa_insnbuf insnbuf = NULL;
5445 static xtensa_insnbuf slotbuf = NULL;
5448 xtensa_opcode opcode;
5451 xtensa_isa isa = xtensa_default_isa;
5452 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5453 bfd_boolean alt_reloc;
5455 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5460 insnbuf = xtensa_insnbuf_alloc (isa);
5461 slotbuf = xtensa_insnbuf_alloc (isa);
5464 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5465 xtensa_insnbuf_from_chars (isa, insnbuf, insn_p, 0);
5466 fmt = xtensa_format_decode (isa, insnbuf);
5468 if (fmt == XTENSA_UNDEFINED)
5469 as_fatal (_("bad instruction format"));
5471 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5472 as_fatal (_("invalid relocation"));
5474 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5475 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5477 /* Check for "alternate" relocations (operand not specified). None
5478 of the current uses for these are really PC-relative. */
5479 if (alt_reloc || opcode == xtensa_const16_opcode)
5481 if (opcode != xtensa_l32r_opcode
5482 && opcode != xtensa_const16_opcode)
5483 as_fatal (_("invalid relocation for '%s' instruction"),
5484 xtensa_opcode_name (isa, opcode));
5488 opnum = get_relaxable_immed (opcode);
5490 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5491 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5493 as_bad_where (fixP->fx_file,
5495 _("invalid relocation for operand %d of '%s'"),
5496 opnum, xtensa_opcode_name (isa, opcode));
5499 return 0 - opnd_value;
5503 /* TC_FORCE_RELOCATION hook */
5506 xtensa_force_relocation (fixS *fix)
5508 switch (fix->fx_r_type)
5510 case BFD_RELOC_XTENSA_ASM_EXPAND:
5511 case BFD_RELOC_XTENSA_SLOT0_ALT:
5512 case BFD_RELOC_XTENSA_SLOT1_ALT:
5513 case BFD_RELOC_XTENSA_SLOT2_ALT:
5514 case BFD_RELOC_XTENSA_SLOT3_ALT:
5515 case BFD_RELOC_XTENSA_SLOT4_ALT:
5516 case BFD_RELOC_XTENSA_SLOT5_ALT:
5517 case BFD_RELOC_XTENSA_SLOT6_ALT:
5518 case BFD_RELOC_XTENSA_SLOT7_ALT:
5519 case BFD_RELOC_XTENSA_SLOT8_ALT:
5520 case BFD_RELOC_XTENSA_SLOT9_ALT:
5521 case BFD_RELOC_XTENSA_SLOT10_ALT:
5522 case BFD_RELOC_XTENSA_SLOT11_ALT:
5523 case BFD_RELOC_XTENSA_SLOT12_ALT:
5524 case BFD_RELOC_XTENSA_SLOT13_ALT:
5525 case BFD_RELOC_XTENSA_SLOT14_ALT:
5531 if (linkrelax && fix->fx_addsy
5532 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5535 return generic_force_reloc (fix);
5539 /* TC_VALIDATE_FIX_SUB hook */
5542 xtensa_validate_fix_sub (fixS *fix)
5544 segT add_symbol_segment, sub_symbol_segment;
5546 /* The difference of two symbols should be resolved by the assembler when
5547 linkrelax is not set. If the linker may relax the section containing
5548 the symbols, then an Xtensa DIFF relocation must be generated so that
5549 the linker knows to adjust the difference value. */
5550 if (!linkrelax || fix->fx_addsy == NULL)
5553 /* Make sure both symbols are in the same segment, and that segment is
5554 "normal" and relaxable. If the segment is not "normal", then the
5555 fix is not valid. If the segment is not "relaxable", then the fix
5556 should have been handled earlier. */
5557 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5558 if (! SEG_NORMAL (add_symbol_segment) ||
5559 ! relaxable_section (add_symbol_segment))
5561 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5562 return (sub_symbol_segment == add_symbol_segment);
5566 /* NO_PSEUDO_DOT hook */
5568 /* This function has nothing to do with pseudo dots, but this is the
5569 nearest macro to where the check needs to take place. FIXME: This
5573 xtensa_check_inside_bundle (void)
5575 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5576 as_bad (_("directives are not valid inside bundles"));
5578 /* This function must always return FALSE because it is called via a
5579 macro that has nothing to do with bundling. */
5584 /* md_elf_section_change_hook */
5587 xtensa_elf_section_change_hook (void)
5589 /* Set up the assembly state. */
5590 if (!frag_now->tc_frag_data.is_assembly_state_set)
5591 xtensa_set_frag_assembly_state (frag_now);
5595 /* tc_fix_adjustable hook */
5598 xtensa_fix_adjustable (fixS *fixP)
5600 /* An offset is not allowed in combination with the difference of two
5601 symbols, but that cannot be easily detected after a local symbol
5602 has been adjusted to a (section+offset) form. Return 0 so that such
5603 an fix will not be adjusted. */
5604 if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
5605 && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
5608 /* We need the symbol name for the VTABLE entries. */
5609 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5610 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5618 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
5620 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5623 switch (fixP->fx_r_type)
5628 if (linkrelax && fixP->fx_subsy)
5630 switch (fixP->fx_r_type)
5633 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5636 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5639 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
5645 /* An offset is only allowed when it results from adjusting a
5646 local symbol into a section-relative offset. If the offset
5647 came from the original expression, tc_fix_adjustable will have
5648 prevented the fix from being converted to a section-relative
5649 form so that we can flag the error here. */
5650 if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy))
5651 as_bad_where (fixP->fx_file, fixP->fx_line,
5652 _("cannot represent subtraction with an offset"));
5654 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5655 - S_GET_VALUE (fixP->fx_subsy));
5657 /* The difference value gets written out, and the DIFF reloc
5658 identifies the address of the subtracted symbol (i.e., the one
5659 with the lowest address). */
5661 fixP->fx_offset -= val;
5662 fixP->fx_subsy = NULL;
5664 else if (! fixP->fx_addsy)
5671 md_number_to_chars (fixpos, val, fixP->fx_size);
5672 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
5675 case BFD_RELOC_XTENSA_SLOT0_OP:
5676 case BFD_RELOC_XTENSA_SLOT1_OP:
5677 case BFD_RELOC_XTENSA_SLOT2_OP:
5678 case BFD_RELOC_XTENSA_SLOT3_OP:
5679 case BFD_RELOC_XTENSA_SLOT4_OP:
5680 case BFD_RELOC_XTENSA_SLOT5_OP:
5681 case BFD_RELOC_XTENSA_SLOT6_OP:
5682 case BFD_RELOC_XTENSA_SLOT7_OP:
5683 case BFD_RELOC_XTENSA_SLOT8_OP:
5684 case BFD_RELOC_XTENSA_SLOT9_OP:
5685 case BFD_RELOC_XTENSA_SLOT10_OP:
5686 case BFD_RELOC_XTENSA_SLOT11_OP:
5687 case BFD_RELOC_XTENSA_SLOT12_OP:
5688 case BFD_RELOC_XTENSA_SLOT13_OP:
5689 case BFD_RELOC_XTENSA_SLOT14_OP:
5692 /* Write the tentative value of a PC-relative relocation to a
5693 local symbol into the instruction. The value will be ignored
5694 by the linker, and it makes the object file disassembly
5695 readable when all branch targets are encoded in relocations. */
5697 assert (fixP->fx_addsy);
5698 if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt
5699 && !S_FORCE_RELOC (fixP->fx_addsy, 1))
5701 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
5702 - md_pcrel_from (fixP));
5703 (void) xg_apply_fix_value (fixP, val);
5706 else if (! fixP->fx_addsy)
5709 if (xg_apply_fix_value (fixP, val))
5714 case BFD_RELOC_XTENSA_PLT:
5715 case BFD_RELOC_XTENSA_ASM_EXPAND:
5716 case BFD_RELOC_XTENSA_SLOT0_ALT:
5717 case BFD_RELOC_XTENSA_SLOT1_ALT:
5718 case BFD_RELOC_XTENSA_SLOT2_ALT:
5719 case BFD_RELOC_XTENSA_SLOT3_ALT:
5720 case BFD_RELOC_XTENSA_SLOT4_ALT:
5721 case BFD_RELOC_XTENSA_SLOT5_ALT:
5722 case BFD_RELOC_XTENSA_SLOT6_ALT:
5723 case BFD_RELOC_XTENSA_SLOT7_ALT:
5724 case BFD_RELOC_XTENSA_SLOT8_ALT:
5725 case BFD_RELOC_XTENSA_SLOT9_ALT:
5726 case BFD_RELOC_XTENSA_SLOT10_ALT:
5727 case BFD_RELOC_XTENSA_SLOT11_ALT:
5728 case BFD_RELOC_XTENSA_SLOT12_ALT:
5729 case BFD_RELOC_XTENSA_SLOT13_ALT:
5730 case BFD_RELOC_XTENSA_SLOT14_ALT:
5731 /* These all need to be resolved at link-time. Do nothing now. */
5734 case BFD_RELOC_VTABLE_INHERIT:
5735 case BFD_RELOC_VTABLE_ENTRY:
5740 as_bad (_("unhandled local relocation fix %s"),
5741 bfd_get_reloc_code_name (fixP->fx_r_type));
5747 md_atof (int type, char *litP, int *sizeP)
5750 LITTLENUM_TYPE words[4];
5766 return "bad call to md_atof";
5769 t = atof_ieee (input_line_pointer, type, words);
5771 input_line_pointer = t;
5775 for (i = prec - 1; i >= 0; i--)
5778 if (target_big_endian)
5779 idx = (prec - 1 - i);
5781 md_number_to_chars (litP, (valueT) words[idx], 2);
5790 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
5792 return total_frag_text_expansion (fragP);
5796 /* Translate internal representation of relocation info to BFD target
5800 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
5804 reloc = (arelent *) xmalloc (sizeof (arelent));
5805 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5806 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5807 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5809 /* Make sure none of our internal relocations make it this far.
5810 They'd better have been fully resolved by this point. */
5811 assert ((int) fixp->fx_r_type > 0);
5813 reloc->addend = fixp->fx_offset;
5815 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
5816 if (reloc->howto == NULL)
5818 as_bad_where (fixp->fx_file, fixp->fx_line,
5819 _("cannot represent `%s' relocation in object file"),
5820 bfd_get_reloc_code_name (fixp->fx_r_type));
5821 free (reloc->sym_ptr_ptr);
5826 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
5827 as_fatal (_("internal error? cannot generate `%s' relocation"),
5828 bfd_get_reloc_code_name (fixp->fx_r_type));
5834 /* Checks for resource conflicts between instructions. */
5836 /* The func unit stuff could be implemented as bit-vectors rather
5837 than the iterative approach here. If it ends up being too
5838 slow, we will switch it. */
5841 new_resource_table (void *data,
5844 unit_num_copies_func uncf,
5845 opcode_num_units_func onuf,
5846 opcode_funcUnit_use_unit_func ouuf,
5847 opcode_funcUnit_use_stage_func ousf)
5850 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
5852 rt->cycles = cycles;
5853 rt->allocated_cycles = cycles;
5855 rt->unit_num_copies = uncf;
5856 rt->opcode_num_units = onuf;
5857 rt->opcode_unit_use = ouuf;
5858 rt->opcode_unit_stage = ousf;
5860 rt->units = (char **) xcalloc (cycles, sizeof (char *));
5861 for (i = 0; i < cycles; i++)
5862 rt->units[i] = (char *) xcalloc (nu, sizeof (char));
5869 clear_resource_table (resource_table *rt)
5872 for (i = 0; i < rt->allocated_cycles; i++)
5873 for (j = 0; j < rt->num_units; j++)
5874 rt->units[i][j] = 0;
5878 /* We never shrink it, just fake it into thinking so. */
5881 resize_resource_table (resource_table *rt, int cycles)
5885 rt->cycles = cycles;
5886 if (cycles <= rt->allocated_cycles)
5889 old_cycles = rt->allocated_cycles;
5890 rt->allocated_cycles = cycles;
5892 rt->units = xrealloc (rt->units, sizeof (char *) * rt->allocated_cycles);
5893 for (i = 0; i < old_cycles; i++)
5894 rt->units[i] = xrealloc (rt->units[i], sizeof (char) * rt->num_units);
5895 for (i = old_cycles; i < cycles; i++)
5896 rt->units[i] = xcalloc (rt->num_units, sizeof (char));
5901 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
5904 int uses = (rt->opcode_num_units) (rt->data, opcode);
5906 for (i = 0; i < uses; i++)
5908 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5909 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5910 int copies_in_use = rt->units[stage + cycle][unit];
5911 int copies = (rt->unit_num_copies) (rt->data, unit);
5912 if (copies_in_use >= copies)
5920 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5923 int uses = (rt->opcode_num_units) (rt->data, opcode);
5925 for (i = 0; i < uses; i++)
5927 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5928 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5929 /* Note that this allows resources to be oversubscribed. That's
5930 essential to the way the optional scheduler works.
5931 resources_available reports when a resource is over-subscribed,
5932 so it's easy to tell. */
5933 rt->units[stage + cycle][unit]++;
5939 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
5942 int uses = (rt->opcode_num_units) (rt->data, opcode);
5944 for (i = 0; i < uses; i++)
5946 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
5947 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
5948 rt->units[stage + cycle][unit]--;
5949 assert (rt->units[stage + cycle][unit] >= 0);
5954 /* Wrapper functions make parameterized resource reservation
5958 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
5960 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5966 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
5968 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
5973 /* Note that this function does not check issue constraints, but
5974 solely whether the hardware is available to execute the given
5975 instructions together. It also doesn't check if the tinsns
5976 write the same state, or access the same tieports. That is
5977 checked by check_t1_t2_reads_and_writes. */
5980 resources_conflict (vliw_insn *vinsn)
5983 static resource_table *rt = NULL;
5985 /* This is the most common case by far. Optimize it. */
5986 if (vinsn->num_slots == 1)
5991 xtensa_isa isa = xtensa_default_isa;
5992 rt = new_resource_table
5993 (isa, xtensa_isa_num_pipe_stages (isa),
5994 xtensa_isa_num_funcUnits (isa),
5995 (unit_num_copies_func) xtensa_funcUnit_num_copies,
5996 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
5997 opcode_funcUnit_use_unit,
5998 opcode_funcUnit_use_stage);
6001 clear_resource_table (rt);
6003 for (i = 0; i < vinsn->num_slots; i++)
6005 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6007 reserve_resources (rt, vinsn->slots[i].opcode, 0);
6014 /* finish_vinsn, emit_single_op and helper functions. */
6016 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6017 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6018 static void bundle_single_op (TInsn *);
6019 static void xg_assemble_vliw_tokens (vliw_insn *);
6022 /* We have reached the end of a bundle; emit into the frag. */
6025 finish_vinsn (vliw_insn *vinsn)
6032 if (find_vinsn_conflicts (vinsn))
6034 xg_clear_vinsn (vinsn);
6038 /* First, find a format that works. */
6039 if (vinsn->format == XTENSA_UNDEFINED)
6040 vinsn->format = xg_find_narrowest_format (vinsn);
6042 if (vinsn->format == XTENSA_UNDEFINED)
6044 as_where (&file_name, &line);
6045 as_bad_where (file_name, line,
6046 _("couldn't find a valid instruction format"));
6047 fprintf (stderr, _(" ops were: "));
6048 for (i = 0; i < vinsn->num_slots; i++)
6049 fprintf (stderr, _(" %s;"),
6050 xtensa_opcode_name (xtensa_default_isa,
6051 vinsn->slots[i].opcode));
6052 fprintf (stderr, _("\n"));
6053 xg_clear_vinsn (vinsn);
6057 if (vinsn->num_slots
6058 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
6060 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6061 xtensa_format_name (xtensa_default_isa, vinsn->format),
6062 xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
6064 xg_clear_vinsn (vinsn);
6068 if (resources_conflict (vinsn))
6070 as_where (&file_name, &line);
6071 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6072 fprintf (stderr, " ops were: ");
6073 for (i = 0; i < vinsn->num_slots; i++)
6074 fprintf (stderr, " %s;",
6075 xtensa_opcode_name (xtensa_default_isa,
6076 vinsn->slots[i].opcode));
6077 fprintf (stderr, "\n");
6078 xg_clear_vinsn (vinsn);
6082 for (i = 0; i < vinsn->num_slots; i++)
6084 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6086 symbolS *lit_sym = NULL;
6088 bfd_boolean e = FALSE;
6089 bfd_boolean saved_density = density_supported;
6091 /* We don't want to narrow ops inside multi-slot bundles. */
6092 if (vinsn->num_slots > 1)
6093 density_supported = FALSE;
6095 istack_init (&slotstack);
6096 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6098 vinsn->slots[i].opcode =
6099 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6101 vinsn->slots[i].ntok = 0;
6104 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6110 density_supported = saved_density;
6114 xg_clear_vinsn (vinsn);
6118 for (j = 0; j < slotstack.ninsn; j++)
6120 TInsn *insn = &slotstack.insn[j];
6121 if (insn->insn_type == ITYPE_LITERAL)
6123 assert (lit_sym == NULL);
6124 lit_sym = xg_assemble_literal (insn);
6128 assert (insn->insn_type == ITYPE_INSN);
6130 xg_resolve_literals (insn, lit_sym);
6131 if (j != slotstack.ninsn - 1)
6132 emit_single_op (insn);
6136 if (vinsn->num_slots > 1)
6138 if (opcode_fits_format_slot
6139 (slotstack.insn[slotstack.ninsn - 1].opcode,
6142 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6146 bundle_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6147 if (vinsn->format == XTENSA_UNDEFINED)
6148 vinsn->slots[i].opcode = xtensa_nop_opcode;
6150 vinsn->slots[i].opcode
6151 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6154 vinsn->slots[i].ntok = 0;
6159 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6160 vinsn->format = XTENSA_UNDEFINED;
6165 /* Now check resource conflicts on the modified bundle. */
6166 if (resources_conflict (vinsn))
6168 as_where (&file_name, &line);
6169 as_bad_where (file_name, line, _("illegal resource usage in bundle"));
6170 fprintf (stderr, " ops were: ");
6171 for (i = 0; i < vinsn->num_slots; i++)
6172 fprintf (stderr, " %s;",
6173 xtensa_opcode_name (xtensa_default_isa,
6174 vinsn->slots[i].opcode));
6175 fprintf (stderr, "\n");
6176 xg_clear_vinsn (vinsn);
6180 /* First, find a format that works. */
6181 if (vinsn->format == XTENSA_UNDEFINED)
6182 vinsn->format = xg_find_narrowest_format (vinsn);
6184 xg_assemble_vliw_tokens (vinsn);
6186 xg_clear_vinsn (vinsn);
6190 /* Given an vliw instruction, what conflicts are there in register
6191 usage and in writes to states and queues?
6193 This function does two things:
6194 1. Reports an error when a vinsn contains illegal combinations
6195 of writes to registers states or queues.
6196 2. Marks individual tinsns as not relaxable if the combination
6197 contains antidependencies.
6199 Job 2 handles things like swap semantics in instructions that need
6200 to be relaxed. For example,
6204 normally would be relaxed to
6209 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6211 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6213 then we can't relax it into
6216 { add a0, a1, a0 ; add a2, a0, a4 ; }
6218 because the value of a0 is trashed before the second add can read it. */
6220 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6223 find_vinsn_conflicts (vliw_insn *vinsn)
6227 xtensa_isa isa = xtensa_default_isa;
6229 assert (!past_xtensa_end);
6231 for (i = 0 ; i < vinsn->num_slots; i++)
6233 TInsn *op1 = &vinsn->slots[i];
6234 if (op1->is_specific_opcode)
6235 op1->keep_wide = TRUE;
6237 op1->keep_wide = FALSE;
6240 for (i = 0 ; i < vinsn->num_slots; i++)
6242 TInsn *op1 = &vinsn->slots[i];
6244 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6247 for (j = 0; j < vinsn->num_slots; j++)
6251 TInsn *op2 = &vinsn->slots[j];
6252 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6253 switch (conflict_type)
6256 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6257 xtensa_opcode_name (isa, op1->opcode), i,
6258 xtensa_opcode_name (isa, op2->opcode), j);
6261 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6262 xtensa_opcode_name (isa, op1->opcode), i,
6263 xtensa_opcode_name (isa, op2->opcode), j);
6266 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6267 xtensa_opcode_name (isa, op1->opcode), i,
6268 xtensa_opcode_name (isa, op2->opcode), j);
6271 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6272 xtensa_opcode_name (isa, op1->opcode), i,
6273 xtensa_opcode_name (isa, op2->opcode), j);
6276 /* Everything is OK. */
6279 op2->is_specific_opcode = (op2->is_specific_opcode
6280 || conflict_type == 'a');
6287 as_bad (_("multiple branches or jumps in the same bundle"));
6295 /* Check how the state used by t1 and t2 relate.
6298 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6299 case B: no relationship between what is read and written (both could
6300 read the same reg though)
6301 case C: t1 writes a register t2 writes (a register conflict within a
6303 case D: t1 writes a state that t2 also writes
6304 case E: t1 writes a tie queue that t2 also writes
6305 case F: two volatile queue accesses
6309 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6311 xtensa_isa isa = xtensa_default_isa;
6312 xtensa_regfile t1_regfile, t2_regfile;
6314 int t1_base_reg, t1_last_reg;
6315 int t2_base_reg, t2_last_reg;
6316 char t1_inout, t2_inout;
6318 char conflict = 'b';
6323 bfd_boolean t1_volatile = FALSE;
6324 bfd_boolean t2_volatile = FALSE;
6326 /* Check registers. */
6327 for (j = 0; j < t2->ntok; j++)
6329 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6332 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6333 t2_base_reg = t2->tok[j].X_add_number;
6334 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6336 for (i = 0; i < t1->ntok; i++)
6338 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6341 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6343 if (t1_regfile != t2_regfile)
6346 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6347 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6349 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6350 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6352 if (t1_inout == 'm' || t1_inout == 'o'
6353 || t2_inout == 'm' || t2_inout == 'o')
6360 t1_base_reg = t1->tok[i].X_add_number;
6361 t1_last_reg = (t1_base_reg
6362 + xtensa_operand_num_regs (isa, t1->opcode, i));
6364 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6366 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6368 if (t1_reg != t2_reg)
6371 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6377 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6383 if (t1_inout != 'i' && t2_inout != 'i')
6391 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6392 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6393 for (j = 0; j < t2_states; j++)
6395 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6396 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6397 for (i = 0; i < t1_states; i++)
6399 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6400 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6404 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6410 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6416 if (t1_inout != 'i' && t2_inout != 'i')
6421 /* Check tieports. */
6422 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6423 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6424 for (j = 0; j < t2_interfaces; j++)
6426 xtensa_interface t2_int
6427 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6428 int t2_class = xtensa_interface_class_id (isa, t2_int);
6430 t2_inout = xtensa_interface_inout (isa, j);
6431 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6434 for (i = 0; i < t1_interfaces; i++)
6436 xtensa_interface t1_int
6437 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6438 int t1_class = xtensa_interface_class_id (isa, t2_int);
6440 t1_inout = xtensa_interface_inout (isa, i);
6441 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6444 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6447 if (t1_int != t2_int)
6450 if (t2_inout == 'i' && t1_inout == 'o')
6456 if (t1_inout == 'i' && t2_inout == 'o')
6462 if (t1_inout != 'i' && t2_inout != 'i')
6471 static xtensa_format
6472 xg_find_narrowest_format (vliw_insn *vinsn)
6474 /* Right now we assume that the ops within the vinsn are properly
6475 ordered for the slots that the programmer wanted them in. In
6476 other words, we don't rearrange the ops in hopes of finding a
6477 better format. The scheduler handles that. */
6479 xtensa_isa isa = xtensa_default_isa;
6480 xtensa_format format;
6481 vliw_insn v_copy = *vinsn;
6482 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6484 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6487 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6491 for (slot = 0; slot < v_copy.num_slots; slot++)
6493 if (v_copy.slots[slot].opcode == nop_opcode)
6495 v_copy.slots[slot].opcode =
6496 xtensa_format_slot_nop_opcode (isa, format, slot);
6497 v_copy.slots[slot].ntok = 0;
6500 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6503 else if (v_copy.num_slots > 1)
6506 /* Try the widened version. */
6507 if (!v_copy.slots[slot].keep_wide
6508 && !v_copy.slots[slot].is_specific_opcode
6509 && xg_is_narrow_insn (&v_copy.slots[slot])
6510 && !xg_expand_narrow (&widened, &v_copy.slots[slot])
6511 && opcode_fits_format_slot (widened.opcode,
6514 /* The xg_is_narrow clause requires some explanation:
6516 addi can be "widened" to an addmi, which is then
6517 expanded to an addmi/addi pair if the immediate
6518 requires it, but here we must have a single widen
6521 xg_is_narrow tells us that addi isn't really
6522 narrow. The widen_spec_list says that there are
6525 v_copy.slots[slot] = widened;
6530 if (fit == v_copy.num_slots)
6533 xtensa_format_encode (isa, format, vinsn->insnbuf);
6534 vinsn->format = format;
6540 if (format == xtensa_isa_num_formats (isa))
6541 return XTENSA_UNDEFINED;
6547 /* Return the additional space needed in a frag
6548 for possible relaxations of any ops in a VLIW insn.
6549 Also fill out the relaxations that might be required of
6550 each tinsn in the vinsn. */
6553 relaxation_requirements (vliw_insn *vinsn)
6555 int extra_space = 0;
6558 for (slot = 0; slot < vinsn->num_slots; slot++)
6560 TInsn *tinsn = &vinsn->slots[slot];
6561 if (!tinsn_has_symbolic_operands (tinsn))
6563 /* A narrow instruction could be widened later to help
6564 alignment issues. */
6565 if (xg_is_narrow_insn (tinsn)
6566 && !tinsn->is_specific_opcode
6567 && vinsn->num_slots == 1)
6569 /* Difference in bytes between narrow and wide insns... */
6571 tinsn->subtype = RELAX_NARROW;
6572 tinsn->record_fix = TRUE;
6577 tinsn->record_fix = FALSE;
6578 /* No extra_space needed. */
6583 if (workaround_b_j_loop_end
6584 && tinsn->opcode == xtensa_jx_opcode
6585 && use_transform ())
6587 /* Add 2 of these. */
6588 extra_space += 3; /* for the nop size */
6589 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6592 /* Need to assemble it with space for the relocation. */
6593 if (xg_is_relaxable_insn (tinsn, 0)
6594 && !tinsn->is_specific_opcode)
6596 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6597 int max_literal_size =
6598 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6600 tinsn->literal_space = max_literal_size;
6602 tinsn->subtype = RELAX_IMMED;
6603 tinsn->record_fix = FALSE;
6604 extra_space += max_size;
6608 tinsn->record_fix = TRUE;
6609 /* No extra space needed. */
6618 bundle_single_op (TInsn *orig_insn)
6620 xtensa_isa isa = xtensa_default_isa;
6625 v.format = op_placement_table[orig_insn->opcode].narrowest;
6626 assert (v.format != XTENSA_UNDEFINED);
6627 v.num_slots = xtensa_format_num_slots (isa, v.format);
6630 !opcode_fits_format_slot (orig_insn->opcode, v.format, slot);
6633 v.slots[slot].opcode =
6634 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6635 v.slots[slot].ntok = 0;
6636 v.slots[slot].insn_type = ITYPE_INSN;
6639 v.slots[slot] = *orig_insn;
6642 for ( ; slot < v.num_slots; slot++)
6644 v.slots[slot].opcode =
6645 xtensa_format_slot_nop_opcode (isa, v.format, slot);
6646 v.slots[slot].ntok = 0;
6647 v.slots[slot].insn_type = ITYPE_INSN;
6656 emit_single_op (TInsn *orig_insn)
6659 IStack istack; /* put instructions into here */
6660 symbolS *lit_sym = NULL;
6661 symbolS *label_sym = NULL;
6663 istack_init (&istack);
6665 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6666 Because the scheduling and bundling characteristics of movi and
6667 l32r or const16 are so different, we can do much better if we relax
6668 it prior to scheduling and bundling, rather than after. */
6669 if ((orig_insn->opcode == xtensa_movi_opcode
6670 || orig_insn->opcode == xtensa_movi_n_opcode)
6671 && !cur_vinsn.inside_bundle
6672 && (orig_insn->tok[1].X_op == O_symbol
6673 || orig_insn->tok[1].X_op == O_pltrel))
6674 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6676 if (xg_expand_assembly_insn (&istack, orig_insn))
6679 for (i = 0; i < istack.ninsn; i++)
6681 TInsn *insn = &istack.insn[i];
6682 switch (insn->insn_type)
6685 assert (lit_sym == NULL);
6686 lit_sym = xg_assemble_literal (insn);
6690 static int relaxed_sym_idx = 0;
6691 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
6692 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
6694 assert (label_sym == NULL);
6695 label_sym = symbol_find_or_make (label);
6702 xg_resolve_literals (insn, lit_sym);
6704 xg_resolve_labels (insn, label_sym);
6705 bundle_single_op (insn);
6717 total_frag_text_expansion (fragS *fragP)
6720 int total_expansion = 0;
6722 for (slot = 0; slot < MAX_SLOTS; slot++)
6723 total_expansion += fragP->tc_frag_data.text_expansion[slot];
6725 return total_expansion;
6729 /* Emit a vliw instruction to the current fragment. */
6732 xg_assemble_vliw_tokens (vliw_insn *vinsn)
6734 bfd_boolean finish_frag = FALSE;
6735 bfd_boolean is_jump = FALSE;
6736 bfd_boolean is_branch = FALSE;
6737 xtensa_isa isa = xtensa_default_isa;
6743 struct dwarf2_line_info best_loc;
6745 best_loc.line = INT_MAX;
6747 if (generating_literals)
6749 static int reported = 0;
6751 as_bad_where (frag_now->fr_file, frag_now->fr_line,
6752 _("cannot assemble into a literal fragment"));
6759 if (frag_now_fix () != 0
6760 && (! frag_now->tc_frag_data.is_insn
6761 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6762 || !use_transform () != frag_now->tc_frag_data.is_no_transform
6763 || (directive_state[directive_absolute_literals]
6764 != frag_now->tc_frag_data.use_absolute_literals)))
6766 frag_wane (frag_now);
6768 xtensa_set_frag_assembly_state (frag_now);
6771 if (workaround_a0_b_retw
6772 && vinsn->num_slots == 1
6773 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
6774 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
6775 && use_transform ())
6777 has_a0_b_retw = TRUE;
6779 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6780 After the first assembly pass we will check all of them and
6781 add a nop if needed. */
6782 frag_now->tc_frag_data.is_insn = TRUE;
6783 frag_var (rs_machine_dependent, 4, 4,
6784 RELAX_ADD_NOP_IF_A0_B_RETW,
6785 frag_now->fr_symbol,
6786 frag_now->fr_offset,
6788 xtensa_set_frag_assembly_state (frag_now);
6789 frag_now->tc_frag_data.is_insn = TRUE;
6790 frag_var (rs_machine_dependent, 4, 4,
6791 RELAX_ADD_NOP_IF_A0_B_RETW,
6792 frag_now->fr_symbol,
6793 frag_now->fr_offset,
6795 xtensa_set_frag_assembly_state (frag_now);
6798 for (i = 0; i < vinsn->num_slots; i++)
6800 /* See if the instruction implies an aligned section. */
6801 if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
6802 record_alignment (now_seg, 2);
6804 /* Also determine the best line number for debug info. */
6805 best_loc = vinsn->slots[i].loc.line < best_loc.line
6806 ? vinsn->slots[i].loc : best_loc;
6809 /* Special cases for instructions that force an alignment... */
6810 /* None of these opcodes are bundle-able. */
6811 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
6815 xtensa_set_frag_assembly_state (frag_now);
6816 frag_now->tc_frag_data.is_insn = TRUE;
6818 max_fill = get_text_align_max_fill_size
6819 (get_text_align_power (xtensa_fetch_width),
6820 TRUE, frag_now->tc_frag_data.is_no_density);
6822 if (use_transform ())
6823 frag_var (rs_machine_dependent, max_fill, max_fill,
6824 RELAX_ALIGN_NEXT_OPCODE,
6825 frag_now->fr_symbol,
6826 frag_now->fr_offset,
6829 frag_var (rs_machine_dependent, 0, 0,
6830 RELAX_CHECK_ALIGN_NEXT_OPCODE, 0, 0, NULL);
6831 xtensa_set_frag_assembly_state (frag_now);
6833 xtensa_move_labels (frag_now, 0, FALSE);
6836 if (vinsn->slots[0].opcode == xtensa_entry_opcode
6837 && !vinsn->slots[0].is_specific_opcode)
6839 xtensa_mark_literal_pool_location ();
6840 xtensa_move_labels (frag_now, 0, TRUE);
6841 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
6844 if (vinsn->num_slots == 1)
6846 if (workaround_a0_b_retw && use_transform ())
6847 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
6848 is_register_writer (&vinsn->slots[0], "a", 0));
6850 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
6851 is_bad_loopend_opcode (&vinsn->slots[0]));
6854 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
6856 insn_size = xtensa_format_length (isa, vinsn->format);
6858 extra_space = relaxation_requirements (vinsn);
6860 /* vinsn_to_insnbuf will produce the error. */
6861 if (vinsn->format != XTENSA_UNDEFINED)
6863 f = (char *) frag_more (insn_size + extra_space);
6864 xtensa_set_frag_assembly_state (frag_now);
6865 frag_now->tc_frag_data.is_insn = TRUE;
6868 vinsn_to_insnbuf (vinsn, f, frag_now, TRUE);
6869 if (vinsn->format == XTENSA_UNDEFINED)
6872 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, f, 0);
6874 xtensa_dwarf2_emit_insn (insn_size - extra_space, &best_loc);
6876 for (slot = 0; slot < vinsn->num_slots; slot++)
6878 TInsn *tinsn = &vinsn->slots[slot];
6879 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
6880 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
6881 frag_now->tc_frag_data.slot_sub_symbols[slot] = tinsn->sub_symbol;
6882 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
6883 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
6884 if (tinsn->literal_space != 0)
6885 xg_assemble_literal_space (tinsn->literal_space, slot);
6887 if (tinsn->subtype == RELAX_NARROW)
6888 assert (vinsn->num_slots == 1);
6889 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
6891 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
6894 if (tinsn->subtype || tinsn->symbol || tinsn->record_fix
6895 || tinsn->offset || tinsn->literal_frag || is_jump || is_branch)
6899 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6900 frag_now->tc_frag_data.is_specific_opcode = TRUE;
6904 frag_variant (rs_machine_dependent,
6905 extra_space, extra_space, RELAX_SLOTS,
6906 frag_now->fr_symbol, frag_now->fr_offset, f);
6907 xtensa_set_frag_assembly_state (frag_now);
6910 /* Special cases for loops:
6911 close_loop_end should be inserted AFTER short_loop.
6912 Make sure that CLOSE loops are processed BEFORE short_loops
6913 when converting them. */
6915 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6916 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
6917 && !vinsn->slots[0].is_specific_opcode)
6919 if (workaround_short_loop && use_transform ())
6921 maybe_has_short_loop = TRUE;
6922 frag_now->tc_frag_data.is_insn = TRUE;
6923 frag_var (rs_machine_dependent, 4, 4,
6924 RELAX_ADD_NOP_IF_SHORT_LOOP,
6925 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6926 frag_now->tc_frag_data.is_insn = TRUE;
6927 frag_var (rs_machine_dependent, 4, 4,
6928 RELAX_ADD_NOP_IF_SHORT_LOOP,
6929 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6932 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6933 loop at least 12 bytes away from another loop's end. */
6934 if (workaround_close_loop_end && use_transform ())
6936 maybe_has_close_loop_end = TRUE;
6937 frag_now->tc_frag_data.is_insn = TRUE;
6938 frag_var (rs_machine_dependent, 12, 12,
6939 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
6940 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6944 if (use_transform ())
6948 assert (finish_frag);
6949 frag_var (rs_machine_dependent,
6950 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6952 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6953 xtensa_set_frag_assembly_state (frag_now);
6955 else if (is_branch && align_targets)
6957 assert (finish_frag);
6958 frag_var (rs_machine_dependent,
6959 UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
6960 RELAX_MAYBE_UNREACHABLE,
6961 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6962 xtensa_set_frag_assembly_state (frag_now);
6963 frag_var (rs_machine_dependent,
6965 RELAX_MAYBE_DESIRE_ALIGN,
6966 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6967 xtensa_set_frag_assembly_state (frag_now);
6971 /* Now, if the original opcode was a call... */
6972 if (do_align_targets ()
6973 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
6975 float freq = get_subseg_total_freq (now_seg, now_subseg);
6976 frag_now->tc_frag_data.is_insn = TRUE;
6977 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
6978 frag_now->fr_symbol, frag_now->fr_offset, NULL);
6979 xtensa_set_frag_assembly_state (frag_now);
6982 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
6984 frag_wane (frag_now);
6986 xtensa_set_frag_assembly_state (frag_now);
6991 /* xtensa_end and helper functions. */
6993 static void xtensa_cleanup_align_frags (void);
6994 static void xtensa_fix_target_frags (void);
6995 static void xtensa_mark_narrow_branches (void);
6996 static void xtensa_mark_zcl_first_insns (void);
6997 static void xtensa_fix_a0_b_retw_frags (void);
6998 static void xtensa_fix_b_j_loop_end_frags (void);
6999 static void xtensa_fix_close_loop_end_frags (void);
7000 static void xtensa_fix_short_loop_frags (void);
7001 static void xtensa_sanity_check (void);
7006 directive_balance ();
7007 xtensa_flush_pending_output ();
7009 past_xtensa_end = TRUE;
7011 xtensa_move_literals ();
7013 xtensa_reorder_segments ();
7014 xtensa_cleanup_align_frags ();
7015 xtensa_fix_target_frags ();
7016 if (workaround_a0_b_retw && has_a0_b_retw)
7017 xtensa_fix_a0_b_retw_frags ();
7018 if (workaround_b_j_loop_end)
7019 xtensa_fix_b_j_loop_end_frags ();
7021 /* "close_loop_end" should be processed BEFORE "short_loop". */
7022 if (workaround_close_loop_end && maybe_has_close_loop_end)
7023 xtensa_fix_close_loop_end_frags ();
7025 if (workaround_short_loop && maybe_has_short_loop)
7026 xtensa_fix_short_loop_frags ();
7027 xtensa_mark_narrow_branches ();
7028 xtensa_mark_zcl_first_insns ();
7030 xtensa_sanity_check ();
7035 xtensa_cleanup_align_frags (void)
7039 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7042 /* Walk over all of the fragments in a subsection. */
7043 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7045 if ((fragP->fr_type == rs_align
7046 || fragP->fr_type == rs_align_code
7047 || (fragP->fr_type == rs_machine_dependent
7048 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7049 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7050 && fragP->fr_fix == 0)
7052 fragS *next = fragP->fr_next;
7055 && next->fr_fix == 0
7056 && next->fr_type == rs_machine_dependent
7057 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7060 next = next->fr_next;
7063 /* If we don't widen branch targets, then they
7064 will be easier to align. */
7065 if (fragP->tc_frag_data.is_branch_target
7066 && fragP->fr_opcode == fragP->fr_literal
7067 && fragP->fr_type == rs_machine_dependent
7068 && fragP->fr_subtype == RELAX_SLOTS
7069 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7071 if (fragP->fr_type == rs_machine_dependent
7072 && fragP->fr_subtype == RELAX_UNREACHABLE)
7073 fragP->tc_frag_data.is_unreachable = TRUE;
7079 /* Re-process all of the fragments looking to convert all of the
7080 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7081 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7082 If the next fragment starts with a loop target, AND the previous
7083 fragment can be expanded to negate the branch, convert this to a
7084 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7086 static bfd_boolean frag_can_negate_branch (fragS *);
7089 xtensa_fix_target_frags (void)
7093 /* When this routine is called, all of the subsections are still intact
7094 so we walk over subsections instead of sections. */
7095 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7097 bfd_boolean prev_frag_can_negate_branch = FALSE;
7100 /* Walk over all of the fragments in a subsection. */
7101 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7103 if (fragP->fr_type == rs_machine_dependent
7104 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7106 if (next_frag_is_loop_target (fragP))
7108 if (prev_frag_can_negate_branch)
7110 fragP->fr_subtype = RELAX_LOOP_END;
7111 /* See the comment near the frag_var with a
7112 RELAX_DESIRE_ALIGN to see why we do this. */
7113 fragP->fr_var = RELAX_LOOP_END_BYTES;
7117 if (next_frag_is_branch_target (fragP))
7118 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7123 else if (next_frag_is_branch_target (fragP))
7124 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
7128 if (fragP->fr_fix != 0)
7129 prev_frag_can_negate_branch = FALSE;
7130 if (frag_can_negate_branch (fragP))
7131 prev_frag_can_negate_branch = TRUE;
7138 frag_can_negate_branch (fragS *fragP)
7140 xtensa_isa isa = xtensa_default_isa;
7144 if (fragP->fr_type != rs_machine_dependent
7145 || fragP->fr_subtype != RELAX_SLOTS)
7148 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7150 for (slot = 0; slot < xtensa_format_num_slots (isa, vinsn.format); slot++)
7152 if ((fragP->tc_frag_data.slot_subtypes[slot] == RELAX_IMMED)
7153 && xtensa_opcode_is_branch (isa, vinsn.slots[slot].opcode) == 1)
7161 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
7164 xtensa_mark_narrow_branches (void)
7168 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7171 /* Walk over all of the fragments in a subsection. */
7172 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7174 if (fragP->fr_type == rs_machine_dependent
7175 && fragP->fr_subtype == RELAX_SLOTS
7176 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
7179 const expressionS *expr;
7182 vinsn_from_chars (&vinsn, fragP->fr_opcode);
7183 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
7185 expr = &vinsn.slots[0].tok[1];
7186 symbolP = expr->X_add_symbol;
7188 if (vinsn.num_slots == 1
7189 && xtensa_opcode_is_branch (xtensa_default_isa,
7190 vinsn.slots[0].opcode)
7191 && xg_get_single_size (vinsn.slots[0].opcode) == 2
7192 && is_narrow_branch_guaranteed_in_range (fragP,
7195 fragP->fr_subtype = RELAX_SLOTS;
7196 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
7204 /* A branch is typically widened only when its target is out of
7205 range. However, we would like to widen them to align a subsequent
7206 branch target when possible.
7208 Because the branch relaxation code is so convoluted, the optimal solution
7209 (combining the two cases) is difficult to get right in all circumstances.
7210 We therefore go with an "almost as good" solution, where we only
7211 use for alignment narrow branches that definitely will not expand to a
7212 jump and a branch. These functions find and mark these cases. */
7214 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7215 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7216 We start counting beginning with the frag after the 2-byte branch, so the
7217 maximum offset is (4 - 2) + 63 = 65. */
7218 #define MAX_IMMED6 65
7220 static size_t unrelaxed_frag_max_size (fragS *);
7223 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
7225 const expressionS *expr = &tinsn->tok[1];
7226 symbolS *symbolP = expr->X_add_symbol;
7227 fragS *target_frag = symbol_get_frag (symbolP);
7228 size_t max_distance = expr->X_add_number;
7229 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
7230 if (is_branch_jmp_to_next (tinsn, fragP))
7233 /* The branch doesn't branch over it's own frag,
7234 but over the subsequent ones. */
7235 fragP = fragP->fr_next;
7236 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
7238 max_distance += unrelaxed_frag_max_size (fragP);
7239 fragP = fragP->fr_next;
7241 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
7248 xtensa_mark_zcl_first_insns (void)
7252 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7255 /* Walk over all of the fragments in a subsection. */
7256 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7258 if (fragP->fr_type == rs_machine_dependent
7259 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
7260 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
7262 /* Find the loop frag. */
7263 fragS *targ_frag = next_non_empty_frag (fragP);
7264 /* Find the first insn frag. */
7265 targ_frag = next_non_empty_frag (targ_frag);
7267 /* Of course, sometimes (mostly for toy test cases) a
7268 zero-cost loop instruction is the last in a section. */
7271 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
7272 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
7281 /* Re-process all of the fragments looking to convert all of the
7282 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7283 conditional branch or a retw/retw.n, convert this frag to one that
7284 will generate a NOP. In any case close it off with a .fill 0. */
7286 static bfd_boolean next_instrs_are_b_retw (fragS *);
7289 xtensa_fix_a0_b_retw_frags (void)
7293 /* When this routine is called, all of the subsections are still intact
7294 so we walk over subsections instead of sections. */
7295 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7299 /* Walk over all of the fragments in a subsection. */
7300 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7302 if (fragP->fr_type == rs_machine_dependent
7303 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
7305 if (next_instrs_are_b_retw (fragP))
7307 if (fragP->tc_frag_data.is_no_transform)
7308 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7310 relax_frag_add_nop (fragP);
7320 next_instrs_are_b_retw (fragS *fragP)
7322 xtensa_opcode opcode;
7324 const fragS *next_fragP = next_non_empty_frag (fragP);
7325 static xtensa_insnbuf insnbuf = NULL;
7326 static xtensa_insnbuf slotbuf = NULL;
7327 xtensa_isa isa = xtensa_default_isa;
7330 bfd_boolean branch_seen = FALSE;
7334 insnbuf = xtensa_insnbuf_alloc (isa);
7335 slotbuf = xtensa_insnbuf_alloc (isa);
7338 if (next_fragP == NULL)
7341 /* Check for the conditional branch. */
7342 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7343 fmt = xtensa_format_decode (isa, insnbuf);
7344 if (fmt == XTENSA_UNDEFINED)
7347 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7349 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
7350 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
7352 branch_seen = (branch_seen
7353 || xtensa_opcode_is_branch (isa, opcode) == 1);
7359 offset += xtensa_format_length (isa, fmt);
7360 if (offset == next_fragP->fr_fix)
7362 next_fragP = next_non_empty_frag (next_fragP);
7366 if (next_fragP == NULL)
7369 /* Check for the retw/retw.n. */
7370 xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset], 0);
7371 fmt = xtensa_format_decode (isa, insnbuf);
7373 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7374 have no problems. */
7375 if (fmt == XTENSA_UNDEFINED
7376 || xtensa_format_num_slots (isa, fmt) != 1)
7379 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
7380 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
7382 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
7389 /* Re-process all of the fragments looking to convert all of the
7390 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7391 loop end label, convert this frag to one that will generate a NOP.
7392 In any case close it off with a .fill 0. */
7394 static bfd_boolean next_instr_is_loop_end (fragS *);
7397 xtensa_fix_b_j_loop_end_frags (void)
7401 /* When this routine is called, all of the subsections are still intact
7402 so we walk over subsections instead of sections. */
7403 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7407 /* Walk over all of the fragments in a subsection. */
7408 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7410 if (fragP->fr_type == rs_machine_dependent
7411 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
7413 if (next_instr_is_loop_end (fragP))
7415 if (fragP->tc_frag_data.is_no_transform)
7416 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7418 relax_frag_add_nop (fragP);
7428 next_instr_is_loop_end (fragS *fragP)
7430 const fragS *next_fragP;
7432 if (next_frag_is_loop_target (fragP))
7435 next_fragP = next_non_empty_frag (fragP);
7436 if (next_fragP == NULL)
7439 if (!next_frag_is_loop_target (next_fragP))
7442 /* If the size is >= 3 then there is more than one instruction here.
7443 The hardware bug will not fire. */
7444 if (next_fragP->fr_fix > 3)
7451 /* Re-process all of the fragments looking to convert all of the
7452 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7453 not MY loop's loop end within 12 bytes, add enough nops here to
7454 make it at least 12 bytes away. In any case close it off with a
7457 static size_t min_bytes_to_other_loop_end (fragS *, fragS *, offsetT, size_t);
7460 xtensa_fix_close_loop_end_frags (void)
7464 /* When this routine is called, all of the subsections are still intact
7465 so we walk over subsections instead of sections. */
7466 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7470 fragS *current_target = NULL;
7471 offsetT current_offset = 0;
7473 /* Walk over all of the fragments in a subsection. */
7474 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7476 if (fragP->fr_type == rs_machine_dependent
7477 && ((fragP->fr_subtype == RELAX_IMMED)
7478 || ((fragP->fr_subtype == RELAX_SLOTS)
7479 && (fragP->tc_frag_data.slot_subtypes[0]
7482 /* Read it. If the instruction is a loop, get the target. */
7484 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7485 if (xtensa_opcode_is_loop (xtensa_default_isa,
7486 t_insn.opcode) == 1)
7488 /* Get the current fragment target. */
7489 if (fragP->tc_frag_data.slot_symbols[0])
7491 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7492 current_target = symbol_get_frag (sym);
7493 current_offset = fragP->fr_offset;
7499 && fragP->fr_type == rs_machine_dependent
7500 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
7503 size_t bytes_added = 0;
7505 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7506 /* Max out at 12. */
7507 min_bytes = min_bytes_to_other_loop_end
7508 (fragP->fr_next, current_target, current_offset,
7509 REQUIRED_LOOP_DIVIDING_BYTES);
7511 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
7513 if (fragP->tc_frag_data.is_no_transform)
7514 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7517 while (min_bytes + bytes_added
7518 < REQUIRED_LOOP_DIVIDING_BYTES)
7522 if (fragP->fr_var < length)
7523 as_fatal (_("fr_var %lu < length %d"),
7524 fragP->fr_var, length);
7527 assemble_nop (length,
7528 fragP->fr_literal + fragP->fr_fix);
7529 fragP->fr_fix += length;
7530 fragP->fr_var -= length;
7532 bytes_added += length;
7538 assert (fragP->fr_type != rs_machine_dependent
7539 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
7545 static size_t unrelaxed_frag_min_size (fragS *);
7548 min_bytes_to_other_loop_end (fragS *fragP,
7549 fragS *current_target,
7550 offsetT current_offset,
7554 fragS *current_fragP;
7556 for (current_fragP = fragP;
7558 current_fragP = current_fragP->fr_next)
7560 if (current_fragP->tc_frag_data.is_loop_target
7561 && current_fragP != current_target)
7562 return offset + current_offset;
7564 offset += unrelaxed_frag_min_size (current_fragP);
7566 if (offset + current_offset >= max_size)
7574 unrelaxed_frag_min_size (fragS *fragP)
7576 size_t size = fragP->fr_fix;
7579 if (fragP->fr_type == rs_fill)
7580 size += fragP->fr_offset;
7587 unrelaxed_frag_max_size (fragS *fragP)
7589 size_t size = fragP->fr_fix;
7590 switch (fragP->fr_type)
7593 /* Empty frags created by the obstack allocation scheme
7594 end up with type 0. */
7599 size += fragP->fr_offset;
7607 /* No further adjustments needed. */
7609 case rs_machine_dependent:
7610 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
7611 size += fragP->fr_var;
7614 /* We had darn well better know how big it is. */
7623 /* Re-process all of the fragments looking to convert all
7624 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7627 1) the instruction size count to the loop end label
7628 is too short (<= 2 instructions),
7629 2) loop has a jump or branch in it
7632 1) workaround_all_short_loops is TRUE
7633 2) The generating loop was a 'loopgtz' or 'loopnez'
7634 3) the instruction size count to the loop end label is too short
7636 then convert this frag (and maybe the next one) to generate a NOP.
7637 In any case close it off with a .fill 0. */
7639 static size_t count_insns_to_loop_end (fragS *, bfd_boolean, size_t);
7640 static bfd_boolean branch_before_loop_end (fragS *);
7643 xtensa_fix_short_loop_frags (void)
7647 /* When this routine is called, all of the subsections are still intact
7648 so we walk over subsections instead of sections. */
7649 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7652 fragS *current_target = NULL;
7653 offsetT current_offset = 0;
7654 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
7656 /* Walk over all of the fragments in a subsection. */
7657 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7659 /* Check on the current loop. */
7660 if (fragP->fr_type == rs_machine_dependent
7661 && ((fragP->fr_subtype == RELAX_IMMED)
7662 || ((fragP->fr_subtype == RELAX_SLOTS)
7663 && (fragP->tc_frag_data.slot_subtypes[0]
7668 /* Read it. If the instruction is a loop, get the target. */
7669 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7670 if (xtensa_opcode_is_loop (xtensa_default_isa,
7671 t_insn.opcode) == 1)
7673 /* Get the current fragment target. */
7674 if (fragP->tc_frag_data.slot_symbols[0])
7676 symbolS *sym = fragP->tc_frag_data.slot_symbols[0];
7677 current_target = symbol_get_frag (sym);
7678 current_offset = fragP->fr_offset;
7679 current_opcode = t_insn.opcode;
7684 if (fragP->fr_type == rs_machine_dependent
7685 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7688 count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
7690 && (branch_before_loop_end (fragP->fr_next)
7691 || (workaround_all_short_loops
7692 && current_opcode != XTENSA_UNDEFINED
7693 && current_opcode != xtensa_loop_opcode)))
7695 if (fragP->tc_frag_data.is_no_transform)
7696 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7698 relax_frag_add_nop (fragP);
7707 static size_t unrelaxed_frag_min_insn_count (fragS *);
7710 count_insns_to_loop_end (fragS *base_fragP,
7711 bfd_boolean count_relax_add,
7714 fragS *fragP = NULL;
7715 size_t insn_count = 0;
7719 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
7721 insn_count += unrelaxed_frag_min_insn_count (fragP);
7722 if (insn_count >= max_count)
7725 if (count_relax_add)
7727 if (fragP->fr_type == rs_machine_dependent
7728 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
7730 /* In order to add the appropriate number of
7731 NOPs, we count an instruction for downstream
7734 if (insn_count >= max_count)
7744 unrelaxed_frag_min_insn_count (fragS *fragP)
7746 xtensa_isa isa = xtensa_default_isa;
7747 static xtensa_insnbuf insnbuf = NULL;
7748 size_t insn_count = 0;
7751 if (!fragP->tc_frag_data.is_insn)
7755 insnbuf = xtensa_insnbuf_alloc (isa);
7757 /* Decode the fixed instructions. */
7758 while (offset < fragP->fr_fix)
7762 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7763 fmt = xtensa_format_decode (isa, insnbuf);
7765 if (fmt == XTENSA_UNDEFINED)
7767 as_fatal (_("undecodable instruction in instruction frag"));
7770 offset += xtensa_format_length (isa, fmt);
7778 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
7781 branch_before_loop_end (fragS *base_fragP)
7785 for (fragP = base_fragP;
7786 fragP && !fragP->tc_frag_data.is_loop_target;
7787 fragP = fragP->fr_next)
7789 if (unrelaxed_frag_has_b_j (fragP))
7797 unrelaxed_frag_has_b_j (fragS *fragP)
7799 static xtensa_insnbuf insnbuf = NULL;
7800 xtensa_isa isa = xtensa_default_isa;
7803 if (!fragP->tc_frag_data.is_insn)
7807 insnbuf = xtensa_insnbuf_alloc (isa);
7809 /* Decode the fixed instructions. */
7810 while (offset < fragP->fr_fix)
7815 xtensa_insnbuf_from_chars (isa, insnbuf, fragP->fr_literal + offset, 0);
7816 fmt = xtensa_format_decode (isa, insnbuf);
7817 if (fmt == XTENSA_UNDEFINED)
7820 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
7822 xtensa_opcode opcode =
7823 get_opcode_from_buf (fragP->fr_literal + offset, slot);
7824 if (xtensa_opcode_is_branch (isa, opcode) == 1
7825 || xtensa_opcode_is_jump (isa, opcode) == 1)
7828 offset += xtensa_format_length (isa, fmt);
7834 /* Checks to be made after initial assembly but before relaxation. */
7836 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
7837 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
7840 xtensa_sanity_check (void)
7847 as_where (&file_name, &line);
7848 for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
7852 /* Walk over all of the fragments in a subsection. */
7853 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7855 /* Currently we only check for empty loops here. */
7856 if (fragP->fr_type == rs_machine_dependent
7857 && fragP->fr_subtype == RELAX_IMMED)
7859 static xtensa_insnbuf insnbuf = NULL;
7862 if (fragP->fr_opcode != NULL)
7865 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7866 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
7867 tinsn_immed_from_frag (&t_insn, fragP, 0);
7869 if (xtensa_opcode_is_loop (xtensa_default_isa,
7870 t_insn.opcode) == 1)
7872 if (is_empty_loop (&t_insn, fragP))
7874 new_logical_line (fragP->fr_file, fragP->fr_line);
7875 as_bad (_("invalid empty loop"));
7877 if (!is_local_forward_loop (&t_insn, fragP))
7879 new_logical_line (fragP->fr_file, fragP->fr_line);
7880 as_bad (_("loop target does not follow "
7881 "loop instruction in section"));
7888 new_logical_line (file_name, line);
7892 #define LOOP_IMMED_OPN 1
7894 /* Return TRUE if the loop target is the next non-zero fragment. */
7897 is_empty_loop (const TInsn *insn, fragS *fragP)
7899 const expressionS *expr;
7903 if (insn->insn_type != ITYPE_INSN)
7906 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
7909 if (insn->ntok <= LOOP_IMMED_OPN)
7912 expr = &insn->tok[LOOP_IMMED_OPN];
7914 if (expr->X_op != O_symbol)
7917 symbolP = expr->X_add_symbol;
7921 if (symbol_get_frag (symbolP) == NULL)
7924 if (S_GET_VALUE (symbolP) != 0)
7927 /* Walk through the zero-size fragments from this one. If we find
7928 the target fragment, then this is a zero-size loop. */
7930 for (next_fragP = fragP->fr_next;
7932 next_fragP = next_fragP->fr_next)
7934 if (next_fragP == symbol_get_frag (symbolP))
7936 if (next_fragP->fr_fix != 0)
7944 is_local_forward_loop (const TInsn *insn, fragS *fragP)
7946 const expressionS *expr;
7950 if (insn->insn_type != ITYPE_INSN)
7953 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
7956 if (insn->ntok <= LOOP_IMMED_OPN)
7959 expr = &insn->tok[LOOP_IMMED_OPN];
7961 if (expr->X_op != O_symbol)
7964 symbolP = expr->X_add_symbol;
7968 if (symbol_get_frag (symbolP) == NULL)
7971 /* Walk through fragments until we find the target.
7972 If we do not find the target, then this is an invalid loop. */
7974 for (next_fragP = fragP->fr_next;
7976 next_fragP = next_fragP->fr_next)
7978 if (next_fragP == symbol_get_frag (symbolP))
7986 /* Alignment Functions. */
7989 get_text_align_power (int target_size)
7992 for (i = 0; i < sizeof (size_t); i++)
7994 if (target_size <= (1 << i))
8003 get_text_align_max_fill_size (int align_pow,
8004 bfd_boolean use_nops,
8005 bfd_boolean use_no_density)
8008 return (1 << align_pow);
8010 return 3 * (1 << align_pow);
8012 return 1 + (1 << align_pow);
8016 /* get_text_align_fill_size ()
8020 target_size = size of next instruction
8021 align_pow = get_text_align_power (target_size).
8025 address = current address + loop instruction size;
8026 target_size = 3 (for 2 or 3 byte target)
8027 = 4 (for 4 byte target)
8028 = 8 (for 8 byte target)
8029 align_pow = get_text_align_power (target_size);
8031 use_no_density = set appropriately
8033 address = current address + loop instruction size;
8035 align_pow = get_text_align_power (target_size);
8037 use_no_density = 0. */
8040 get_text_align_fill_size (addressT address,
8043 bfd_boolean use_nops,
8044 bfd_boolean use_no_density)
8048 align_pow: log2 (required alignment).
8050 target_size: alignment must allow the new_address and
8051 new_address+target_size-1.
8053 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8055 use_no_density: if use_nops and use_no_density, we can only use
8058 Usually the align_pow is the power of 2 that is greater than
8059 or equal to the target_size. This handles the 2-byte, 3-byte
8060 and 8-byte instructions.
8064 (1) aligning an instruction properly, but without using NOPs.
8065 E.G.: a 3-byte instruction can go on any address where address mod 4
8066 is zero or one. The aligner uses this case to find the optimal
8067 number of fill bytes for relax_frag_for_align.
8069 (2) aligning an instruction properly, but where we might need to use
8070 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8071 or similar to get the optimal location. */
8073 size_t alignment = (1 << align_pow);
8075 assert (target_size != 0);
8079 unsigned fill_bytes;
8080 for (fill_bytes = 0; fill_bytes < alignment; fill_bytes++)
8082 addressT end_address = address + target_size - 1 + fill_bytes;
8083 addressT start_address = address + fill_bytes;
8084 if ((end_address >> align_pow) == (start_address >> align_pow))
8090 /* This is the slightly harder case. */
8091 assert ((int) alignment >= target_size);
8092 assert (target_size > 0);
8093 if (!use_no_density)
8096 for (i = 0; i < alignment * 2; i++)
8100 if ((address + i) >> align_pow
8101 == (address + i + target_size - 1) >> align_pow)
8109 /* Can only fill multiples of 3. */
8110 for (i = 0; i <= alignment * 3; i += 3)
8112 if ((address + i) >> align_pow
8113 == (address + i + target_size - 1) >> align_pow)
8122 /* This will assert if it is not possible. */
8125 get_text_align_nop_count (size_t fill_size, bfd_boolean use_no_density)
8130 assert (fill_size % 3 == 0);
8131 return (fill_size / 3);
8134 assert (fill_size != 1); /* Bad argument. */
8136 while (fill_size > 1)
8138 size_t insn_size = 3;
8139 if (fill_size == 2 || fill_size == 4)
8141 fill_size -= insn_size;
8144 assert (fill_size != 1); /* Bad algorithm. */
8150 get_text_align_nth_nop_size (size_t fill_size,
8152 bfd_boolean use_no_density)
8156 assert (get_text_align_nop_count (fill_size, use_no_density) > n);
8161 while (fill_size > 1)
8163 size_t insn_size = 3;
8164 if (fill_size == 2 || fill_size == 4)
8166 fill_size -= insn_size;
8176 /* For the given fragment, find the appropriate address
8177 for it to begin at if we are using NOPs to align it. */
8180 get_noop_aligned_address (fragS *fragP, addressT address)
8182 /* The rule is: get next fragment's FIRST instruction. Find
8183 the smallest number of bytes that need to be added to
8184 ensure that the next fragment's FIRST instruction will fit
8187 E.G., 2 bytes : 0, 1, 2 mod 4
8190 If the FIRST instruction MIGHT be relaxed,
8191 assume that it will become a 3-byte instruction.
8193 Note again here that LOOP instructions are not bundleable,
8194 and this relaxation only applies to LOOP opcodes. */
8196 size_t fill_size = 0;
8197 int first_insn_size;
8199 addressT pre_opcode_bytes;
8202 xtensa_opcode opcode;
8203 bfd_boolean is_loop;
8205 assert (fragP->fr_type == rs_machine_dependent);
8206 assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
8208 /* Find the loop frag. */
8209 first_insn = next_non_empty_frag (fragP);
8210 /* Now find the first insn frag. */
8211 first_insn = next_non_empty_frag (first_insn);
8213 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
8215 loop_insn_size = xg_get_single_size (opcode);
8217 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
8218 pre_opcode_bytes += loop_insn_size;
8220 /* For loops, the alignment depends on the size of the
8221 instruction following the loop, not the LOOP instruction. */
8223 if (first_insn == NULL)
8226 assert (first_insn->tc_frag_data.is_first_loop_insn);
8228 first_insn_size = frag_format_size (first_insn);
8230 if (first_insn_size == 2 || first_insn_size == XTENSA_UNDEFINED)
8231 first_insn_size = 3; /* ISA specifies this */
8233 /* If it was 8, then we'll need a larger alignment for the section. */
8234 alignment = get_text_align_power (first_insn_size);
8236 /* Is now_seg valid? */
8237 record_alignment (now_seg, alignment);
8239 fill_size = get_text_align_fill_size
8240 (address + pre_opcode_bytes,
8241 get_text_align_power (first_insn_size),
8242 first_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
8244 return address + fill_size;
8248 /* 3 mechanisms for relaxing an alignment:
8250 Align to a power of 2.
8251 Align so the next fragment's instruction does not cross a word boundary.
8252 Align the current instruction so that if the next instruction
8253 were 3 bytes, it would not cross a word boundary.
8257 zeros - This is easy; always insert zeros.
8258 nops - 3-byte and 2-byte instructions
8262 >=5 : 3-byte instruction + fn (n-3)
8263 widening - widen previous instructions. */
8266 get_aligned_diff (fragS *fragP, addressT address, addressT *max_diff)
8268 addressT target_address, loop_insn_offset;
8270 xtensa_opcode loop_opcode;
8271 bfd_boolean is_loop;
8272 int text_align_power;
8275 assert (fragP->fr_type == rs_machine_dependent);
8276 switch (fragP->fr_subtype)
8278 case RELAX_DESIRE_ALIGN:
8279 target_size = next_frag_format_size (fragP);
8280 if (target_size == XTENSA_UNDEFINED)
8282 text_align_power = get_text_align_power (xtensa_fetch_width);
8283 opt_diff = get_text_align_fill_size (address, text_align_power,
8284 target_size, FALSE, FALSE);
8286 *max_diff = opt_diff + xtensa_fetch_width
8287 - (target_size + ((address + opt_diff) % xtensa_fetch_width));
8288 assert (*max_diff >= opt_diff);
8291 case RELAX_ALIGN_NEXT_OPCODE:
8292 target_size = next_frag_format_size (fragP);
8293 loop_insn_offset = 0;
8294 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
8297 /* If the loop has been expanded then the LOOP instruction
8298 could be at an offset from this fragment. */
8299 if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
8301 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
8303 if (target_size == 2)
8304 target_size = 3; /* ISA specifies this */
8306 /* In an ideal world, which is what we are shooting for here,
8307 we wouldn't need to use any NOPs immediately prior to the
8308 LOOP instruction. If this approach fails, relax_frag_loop_align
8309 will call get_noop_aligned_address. */
8311 address + loop_insn_offset + xg_get_single_size (loop_opcode);
8312 text_align_power = get_text_align_power (target_size),
8313 opt_diff = get_text_align_fill_size (target_address, text_align_power,
8314 target_size, FALSE, FALSE);
8316 *max_diff = xtensa_fetch_width
8317 - ((target_address + opt_diff) % xtensa_fetch_width)
8318 - target_size + opt_diff;
8319 assert (*max_diff >= opt_diff);
8330 /* md_relax_frag Hook and Helper Functions. */
8332 static long relax_frag_loop_align (fragS *, long);
8333 static long relax_frag_for_align (fragS *, long);
8334 static long relax_frag_immed
8335 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
8338 /* Return the number of bytes added to this fragment, given that the
8339 input has been stretched already by "stretch". */
8342 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
8344 xtensa_isa isa = xtensa_default_isa;
8345 int unreported = fragP->tc_frag_data.unreported_expansion;
8346 long new_stretch = 0;
8349 static xtensa_insnbuf vbuf = NULL;
8350 int slot, num_slots;
8353 as_where (&file_name, &line);
8354 new_logical_line (fragP->fr_file, fragP->fr_line);
8356 fragP->tc_frag_data.unreported_expansion = 0;
8358 switch (fragP->fr_subtype)
8360 case RELAX_ALIGN_NEXT_OPCODE:
8361 /* Always convert. */
8362 if (fragP->tc_frag_data.relax_seen)
8363 new_stretch = relax_frag_loop_align (fragP, stretch);
8366 case RELAX_LOOP_END:
8370 case RELAX_LOOP_END_ADD_NOP:
8371 /* Add a NOP and switch to .fill 0. */
8372 new_stretch = relax_frag_add_nop (fragP);
8376 case RELAX_DESIRE_ALIGN:
8377 /* Do nothing. The narrowing before this frag will either align
8382 case RELAX_LITERAL_FINAL:
8385 case RELAX_LITERAL_NR:
8387 fragP->fr_subtype = RELAX_LITERAL_FINAL;
8388 assert (unreported == lit_size);
8389 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
8390 fragP->fr_var -= lit_size;
8391 fragP->fr_fix += lit_size;
8397 vbuf = xtensa_insnbuf_alloc (isa);
8399 xtensa_insnbuf_from_chars (isa, vbuf, fragP->fr_opcode, 0);
8400 fmt = xtensa_format_decode (isa, vbuf);
8401 num_slots = xtensa_format_num_slots (isa, fmt);
8403 for (slot = 0; slot < num_slots; slot++)
8405 switch (fragP->tc_frag_data.slot_subtypes[slot])
8408 if (fragP->tc_frag_data.relax_seen)
8409 new_stretch += relax_frag_for_align (fragP, stretch);
8413 case RELAX_IMMED_STEP1:
8414 case RELAX_IMMED_STEP2:
8415 /* Place the immediate. */
8416 new_stretch += relax_frag_immed
8417 (now_seg, fragP, stretch,
8418 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
8419 fmt, slot, stretched_p, FALSE);
8423 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8429 case RELAX_LITERAL_POOL_BEGIN:
8430 case RELAX_LITERAL_POOL_END:
8431 case RELAX_MAYBE_UNREACHABLE:
8432 case RELAX_MAYBE_DESIRE_ALIGN:
8433 /* No relaxation required. */
8436 case RELAX_FILL_NOP:
8437 case RELAX_UNREACHABLE:
8438 if (fragP->tc_frag_data.relax_seen)
8439 new_stretch += relax_frag_for_align (fragP, stretch);
8443 as_bad (_("bad relaxation state"));
8446 /* Tell gas we need another relaxation pass. */
8447 if (! fragP->tc_frag_data.relax_seen)
8449 fragP->tc_frag_data.relax_seen = TRUE;
8453 new_logical_line (file_name, line);
8459 relax_frag_loop_align (fragS *fragP, long stretch)
8461 addressT old_address, old_next_address, old_size;
8462 addressT new_address, new_next_address, new_size;
8465 /* All the frags with relax_frag_for_alignment prior to this one in the
8466 section have been done, hopefully eliminating the need for a NOP here.
8467 But, this will put it in if necessary. */
8469 /* Calculate the old address of this fragment and the next fragment. */
8470 old_address = fragP->fr_address - stretch;
8471 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
8472 fragP->tc_frag_data.text_expansion[0]);
8473 old_size = old_next_address - old_address;
8475 /* Calculate the new address of this fragment and the next fragment. */
8476 new_address = fragP->fr_address;
8478 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
8479 new_size = new_next_address - new_address;
8481 growth = new_size - old_size;
8483 /* Fix up the text_expansion field and return the new growth. */
8484 fragP->tc_frag_data.text_expansion[0] += growth;
8489 /* Add a NOP instruction. */
8492 relax_frag_add_nop (fragS *fragP)
8494 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
8495 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
8496 assemble_nop (length, nop_buf);
8497 fragP->tc_frag_data.is_insn = TRUE;
8499 if (fragP->fr_var < length)
8501 as_fatal (_("fr_var (%ld) < length (%d)"), fragP->fr_var, length);
8505 fragP->fr_fix += length;
8506 fragP->fr_var -= length;
8511 static long future_alignment_required (fragS *, long);
8514 relax_frag_for_align (fragS *fragP, long stretch)
8516 /* Overview of the relaxation procedure for alignment:
8517 We can widen with NOPs or by widening instructions or by filling
8518 bytes after jump instructions. Find the opportune places and widen
8519 them if necessary. */
8524 assert (fragP->fr_subtype == RELAX_FILL_NOP
8525 || fragP->fr_subtype == RELAX_UNREACHABLE
8526 || (fragP->fr_subtype == RELAX_SLOTS
8527 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
8529 stretch_me = future_alignment_required (fragP, stretch);
8530 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
8536 /* We expanded on a previous pass. Can we shrink now? */
8537 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
8538 if (shrink <= stretch && stretch > 0)
8540 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8546 /* Below here, diff > 0. */
8547 fragP->tc_frag_data.text_expansion[0] = stretch_me;
8553 /* Return the address of the next frag that should be aligned.
8555 By "address" we mean the address it _would_ be at if there
8556 is no action taken to align it between here and the target frag.
8557 In other words, if no narrows and no fill nops are used between
8558 here and the frag to align, _even_if_ some of the frags we use
8559 to align targets have already expanded on a previous relaxation
8562 Also, count each frag that may be used to help align the target.
8564 Return 0 if there are no frags left in the chain that need to be
8568 find_address_of_next_align_frag (fragS **fragPP,
8572 bfd_boolean *paddable)
8574 fragS *fragP = *fragPP;
8575 addressT address = fragP->fr_address;
8577 /* Do not reset the counts to 0. */
8581 /* Limit this to a small search. */
8587 address += fragP->fr_fix;
8589 if (fragP->fr_type == rs_fill)
8590 address += fragP->fr_offset * fragP->fr_var;
8591 else if (fragP->fr_type == rs_machine_dependent)
8593 switch (fragP->fr_subtype)
8595 case RELAX_UNREACHABLE:
8599 case RELAX_FILL_NOP:
8601 if (!fragP->tc_frag_data.is_no_density)
8606 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8611 address += total_frag_text_expansion (fragP);;
8615 address += fragP->tc_frag_data.text_expansion[0];
8618 case RELAX_ALIGN_NEXT_OPCODE:
8619 case RELAX_DESIRE_ALIGN:
8623 case RELAX_MAYBE_UNREACHABLE:
8624 case RELAX_MAYBE_DESIRE_ALIGN:
8629 /* Just punt if we don't know the type. */
8636 /* Just punt if we don't know the type. */
8640 fragP = fragP->fr_next;
8648 static long bytes_to_stretch (fragS *, int, int, int, int);
8650 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8651 I'll leave this in until I am more confident this works. */
8653 #define LOOKAHEAD_ALIGNER 1
8656 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
8658 fragS *this_frag = fragP;
8662 int narrow_nops = 0;
8663 bfd_boolean paddable = FALSE;
8664 offsetT local_opt_diff;
8667 int stretch_amount = 0;
8668 int local_stretch_amount;
8669 int global_stretch_amount;
8671 address = find_address_of_next_align_frag
8672 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
8676 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
8677 opt_diff = local_opt_diff;
8678 assert (opt_diff >= 0);
8679 assert (max_diff >= opt_diff);
8682 #ifdef LOOKAHEAD_ALIGNER
8684 fragP = fragP->fr_next;
8686 while (fragP && opt_diff < max_diff && address)
8688 /* We only use these to determine if we can exit early
8689 because there will be plenty of ways to align future
8691 unsigned int glob_widens = 0;
8694 bfd_boolean glob_pad = 0;
8695 address = find_address_of_next_align_frag
8696 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
8697 /* If there is a padable portion, then skip. */
8698 if (glob_pad || (glob_widens >= xtensa_fetch_width))
8703 offsetT next_m_diff;
8704 offsetT next_o_diff;
8706 /* Downrange frags haven't had stretch added to them yet. */
8709 /* The address also includes any text expansion from this
8710 frag in a previous pass, but we don't want that. */
8711 address -= this_frag->tc_frag_data.text_expansion[0];
8713 /* Assume we are going to move at least opt_diff. In
8714 reality, we might not be able to, but assuming that
8715 we will helps catch cases where moving opt_diff pushes
8716 the next target from aligned to unaligned. */
8717 address += opt_diff;
8719 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
8721 /* Now cleanup for the adjustments to address. */
8722 next_o_diff += opt_diff;
8723 next_m_diff += opt_diff;
8724 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
8725 opt_diff = next_o_diff;
8726 if (next_m_diff < max_diff)
8727 max_diff = next_m_diff;
8728 fragP = fragP->fr_next;
8731 #endif /* LOOKAHEAD_ALIGNER */
8732 /* If there are enough wideners in between, do it. */
8735 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
8737 assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
8742 local_stretch_amount
8743 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8744 num_widens, local_opt_diff);
8745 #ifdef LOOKAHEAD_ALIGNER
8746 global_stretch_amount
8747 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
8748 num_widens, opt_diff);
8749 /* If the condition below is true, then the frag couldn't
8750 stretch the correct amount for the global case, so we just
8751 optimize locally. We'll rely on the subsequent frags to get
8752 the correct alignment in the global case. */
8753 if (global_stretch_amount < local_stretch_amount)
8754 stretch_amount = local_stretch_amount;
8756 stretch_amount = global_stretch_amount;
8757 #else /* ! LOOKAHEAD_ALIGNER */
8758 stretch_amount = local_stretch_amount;
8759 #endif /* ! LOOKAHEAD_ALIGNER */
8760 if (this_frag->fr_subtype == RELAX_SLOTS
8761 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8762 assert (stretch_amount <= 1);
8763 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
8765 if (this_frag->tc_frag_data.is_no_density)
8766 assert (stretch_amount == 3 || stretch_amount == 0);
8768 assert (stretch_amount <= 3);
8771 return stretch_amount;
8775 /* The idea: widen everything you can to get a target or loop aligned,
8776 then start using NOPs.
8778 When we must have a NOP, here is a table of how we decide
8779 (so you don't have to fight through the control flow below):
8781 wide_nops = the number of wide NOPs available for aligning
8782 narrow_nops = the number of narrow NOPs available for aligning
8783 (a subset of wide_nops)
8784 widens = the number of narrow instructions that should be widened
8791 b 0 1 1 (case 3a makes this case unnecessary)
8794 c 0 1 2 (case 4a makes this case unnecessary)
8797 c 0 2 1 (case 5b makes this case unnecessary)
8800 c 0 1 4 (case 6b makes this case unneccesary)
8801 d 1 1 1 (case 6a makes this case unnecessary)
8802 e 0 2 2 (case 6a makes this case unnecessary)
8803 f 0 3 0 (case 6a makes this case unnecessary)
8806 c 1 1 2 (case 7b makes this case unnecessary)
8807 d 0 1 5 (case 7a makes this case unnecessary)
8808 e 0 2 3 (case 7b makes this case unnecessary)
8809 f 0 3 1 (case 7b makes this case unnecessary)
8810 g 1 2 1 (case 7b makes this case unnecessary)
8814 bytes_to_stretch (fragS *this_frag,
8820 int bytes_short = desired_diff - num_widens;
8822 assert (desired_diff >= 0 && desired_diff < 8);
8823 if (desired_diff == 0)
8826 assert (wide_nops > 0 || num_widens > 0);
8828 /* Always prefer widening to NOP-filling. */
8829 if (bytes_short < 0)
8831 /* There are enough RELAX_NARROW frags after this one
8832 to align the target without widening this frag in any way. */
8836 if (bytes_short == 0)
8838 /* Widen every narrow between here and the align target
8839 and the align target will be properly aligned. */
8840 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8846 /* From here we will need at least one NOP to get an alignment.
8847 However, we may not be able to align at all, in which case,
8849 if (this_frag->fr_subtype == RELAX_FILL_NOP)
8851 switch (desired_diff)
8856 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
8857 return 2; /* case 2 */
8863 return 3; /* case 3a */
8865 if (num_widens >= 1 && wide_nops == 1)
8866 return 3; /* case 4a */
8867 if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
8868 return 2; /* case 4b */
8871 if (num_widens >= 2 && wide_nops == 1)
8872 return 3; /* case 5a */
8873 /* We will need two nops. Are there enough nops
8874 between here and the align target? */
8875 if (wide_nops < 2 || narrow_nops == 0)
8877 /* Are there other nops closer that can serve instead? */
8878 if (wide_nops > 2 && narrow_nops > 1)
8880 /* Take the density one first, because there might not be
8881 another density one available. */
8882 if (!this_frag->tc_frag_data.is_no_density)
8883 return 2; /* case 5b narrow */
8885 return 3; /* case 5b wide */
8889 return 3; /* case 6a */
8890 else if (num_widens >= 3 && wide_nops == 1)
8891 return 3; /* case 6b */
8894 if (wide_nops == 1 && num_widens >= 4)
8895 return 3; /* case 7a */
8896 else if (wide_nops == 2 && num_widens >= 1)
8897 return 3; /* case 7b */
8905 /* We will need a NOP no matter what, but should we widen
8906 this instruction to help?
8908 This is a RELAX_FRAG_NARROW frag. */
8909 switch (desired_diff)
8918 if (wide_nops >= 1 && num_widens == 1)
8919 return 1; /* case 4a */
8922 if (wide_nops >= 1 && num_widens == 2)
8923 return 1; /* case 5a */
8927 return 0; /* case 6a */
8928 else if (wide_nops >= 1 && num_widens == 3)
8929 return 1; /* case 6b */
8932 if (wide_nops >= 1 && num_widens == 4)
8933 return 1; /* case 7a */
8934 else if (wide_nops >= 2 && num_widens == 1)
8935 return 1; /* case 7b */
8948 relax_frag_immed (segT segP,
8955 bfd_boolean estimate_only)
8958 vliw_insn orig_vinsn;
8960 bfd_boolean negatable_branch = FALSE;
8961 bfd_boolean branch_jmp_to_next = FALSE;
8962 bfd_boolean wide_insn = FALSE;
8963 xtensa_isa isa = xtensa_default_isa;
8965 offsetT frag_offset;
8968 int num_text_bytes, num_literal_bytes;
8969 int literal_diff, total_text_diff, this_text_diff, first;
8971 assert (fragP->fr_opcode != NULL);
8973 xg_init_vinsn (&orig_vinsn);
8974 vinsn_from_chars (&orig_vinsn, fragP->fr_opcode);
8975 if (xtensa_format_num_slots (isa, fmt) > 1)
8978 tinsn = orig_vinsn.slots[slot];
8979 tinsn_immed_from_frag (&tinsn, fragP, slot);
8981 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
8984 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
8985 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
8987 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
8989 old_size = xtensa_format_length (isa, fmt);
8991 /* Special case: replace a branch to the next instruction with a NOP.
8992 This is required to work around a hardware bug in T1040.0 and also
8993 serves as an optimization. */
8995 if (branch_jmp_to_next
8996 && ((old_size == 2) || (old_size == 3))
8997 && !next_frag_is_loop_target (fragP))
9000 /* Here is the fun stuff: Get the immediate field from this
9001 instruction. If it fits, we are done. If not, find the next
9002 instruction sequence that fits. */
9004 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9005 istack_init (&istack);
9006 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
9007 min_steps, stretch);
9008 if (num_steps < min_steps)
9010 as_fatal (_("internal error: relaxation failed"));
9014 if (num_steps > RELAX_IMMED_MAXSTEPS)
9016 as_fatal (_("internal error: relaxation requires too many steps"));
9020 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
9022 /* Figure out the number of bytes needed. */
9024 num_literal_bytes = get_num_stack_literal_bytes (&istack);
9026 num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
9028 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
9030 num_text_bytes = get_num_stack_text_bytes (&istack);
9033 num_text_bytes += old_size;
9034 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
9035 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
9037 total_text_diff = num_text_bytes - old_size;
9038 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
9040 /* It MUST get larger. If not, we could get an infinite loop. */
9041 assert (num_text_bytes >= 0);
9042 assert (literal_diff >= 0);
9043 assert (total_text_diff >= 0);
9045 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
9046 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
9047 assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
9048 assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
9050 /* Find the associated expandable literal for this. */
9051 if (literal_diff != 0)
9053 lit_fragP = fragP->tc_frag_data.literal_frags[slot];
9056 assert (literal_diff == 4);
9057 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
9059 /* We expect that the literal section state has NOT been
9061 assert (lit_fragP->fr_type == rs_machine_dependent
9062 && lit_fragP->fr_subtype == RELAX_LITERAL);
9063 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
9065 /* We need to mark this section for another iteration
9071 if (negatable_branch && istack.ninsn > 1)
9072 update_next_frag_state (fragP);
9074 return this_text_diff;
9078 /* md_convert_frag Hook and Helper Functions. */
9080 static void convert_frag_align_next_opcode (fragS *);
9081 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
9082 static void convert_frag_fill_nop (fragS *);
9083 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
9086 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
9088 static xtensa_insnbuf vbuf = NULL;
9089 xtensa_isa isa = xtensa_default_isa;
9096 as_where (&file_name, &line);
9097 new_logical_line (fragp->fr_file, fragp->fr_line);
9099 switch (fragp->fr_subtype)
9101 case RELAX_ALIGN_NEXT_OPCODE:
9102 /* Always convert. */
9103 convert_frag_align_next_opcode (fragp);
9106 case RELAX_DESIRE_ALIGN:
9107 /* Do nothing. If not aligned already, too bad. */
9111 case RELAX_LITERAL_FINAL:
9116 vbuf = xtensa_insnbuf_alloc (isa);
9118 xtensa_insnbuf_from_chars (isa, vbuf, fragp->fr_opcode, 0);
9119 fmt = xtensa_format_decode (isa, vbuf);
9120 num_slots = xtensa_format_num_slots (isa, fmt);
9122 for (slot = 0; slot < num_slots; slot++)
9124 switch (fragp->tc_frag_data.slot_subtypes[slot])
9127 convert_frag_narrow (sec, fragp, fmt, slot);
9131 case RELAX_IMMED_STEP1:
9132 case RELAX_IMMED_STEP2:
9133 /* Place the immediate. */
9136 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9141 /* This is OK because some slots could have
9142 relaxations and others have none. */
9148 case RELAX_UNREACHABLE:
9149 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
9150 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
9151 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
9155 case RELAX_MAYBE_UNREACHABLE:
9156 case RELAX_MAYBE_DESIRE_ALIGN:
9160 case RELAX_FILL_NOP:
9161 convert_frag_fill_nop (fragp);
9164 case RELAX_LITERAL_NR:
9165 if (use_literal_section)
9167 /* This should have been handled during relaxation. When
9168 relaxing a code segment, literals sometimes need to be
9169 added to the corresponding literal segment. If that
9170 literal segment has already been relaxed, then we end up
9171 in this situation. Marking the literal segments as data
9172 would make this happen less often (since GAS always relaxes
9173 code before data), but we could still get into trouble if
9174 there are instructions in a segment that is not marked as
9175 containing code. Until we can implement a better solution,
9176 cheat and adjust the addresses of all the following frags.
9177 This could break subsequent alignments, but the linker's
9178 literal coalescing will do that anyway. */
9181 fragp->fr_subtype = RELAX_LITERAL_FINAL;
9182 assert (fragp->tc_frag_data.unreported_expansion == 4);
9183 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
9186 for (f = fragp->fr_next; f; f = f->fr_next)
9190 as_bad (_("invalid relaxation fragment result"));
9195 new_logical_line (file_name, line);
9200 convert_frag_align_next_opcode (fragS *fragp)
9202 char *nop_buf; /* Location for Writing. */
9205 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
9206 addressT aligned_address;
9207 size_t fill_size, nop_count;
9209 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
9211 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
9212 nop_count = get_text_align_nop_count (fill_size, use_no_density);
9213 nop_buf = fragp->fr_literal + fragp->fr_fix;
9215 for (i = 0; i < nop_count; i++)
9218 nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
9220 assemble_nop (nop_size, nop_buf);
9221 nop_buf += nop_size;
9224 fragp->fr_fix += fill_size;
9225 fragp->fr_var -= fill_size;
9230 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
9232 TInsn tinsn, single_target;
9233 xtensa_format single_fmt;
9234 int size, old_size, diff, error_val;
9235 offsetT frag_offset;
9238 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
9240 if (xtensa_opcode_is_branch (xtensa_default_isa, tinsn.opcode) == 1)
9242 assert (fragP->tc_frag_data.text_expansion[0] == 1
9243 || fragP->tc_frag_data.text_expansion[0] == 0);
9244 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
9249 if (fragP->tc_frag_data.text_expansion[0] == 0)
9251 /* No conversion. */
9256 assert (fragP->fr_opcode != NULL);
9258 /* Frags in this relaxation state should only contain
9259 single instruction bundles. */
9260 tinsn_immed_from_frag (&tinsn, fragP, 0);
9262 /* Just convert it to a wide form.... */
9264 old_size = xg_get_single_size (tinsn.opcode);
9266 tinsn_init (&single_target);
9267 frag_offset = fragP->fr_opcode - fragP->fr_literal;
9269 error_val = xg_expand_narrow (&single_target, &tinsn);
9272 as_bad (_("unable to widen instruction"));
9276 size = xg_get_single_size (single_target.opcode);
9277 single_fmt = xg_get_single_format (single_target.opcode);
9279 xg_emit_insn_to_buf (&single_target, single_fmt, fragP->fr_opcode,
9280 fragP, frag_offset, TRUE);
9282 diff = size - old_size;
9284 assert (diff <= fragP->fr_var);
9285 fragP->fr_var -= diff;
9286 fragP->fr_fix += diff;
9294 convert_frag_fill_nop (fragS *fragP)
9296 char *loc = &fragP->fr_literal[fragP->fr_fix];
9297 int size = fragP->tc_frag_data.text_expansion[0];
9298 assert ((unsigned) size == (fragP->fr_next->fr_address
9299 - fragP->fr_address - fragP->fr_fix));
9302 /* No conversion. */
9306 assemble_nop (size, loc);
9307 fragP->tc_frag_data.is_insn = TRUE;
9308 fragP->fr_var -= size;
9309 fragP->fr_fix += size;
9314 static fixS *fix_new_exp_in_seg
9315 (segT, subsegT, fragS *, int, int, expressionS *, int,
9316 bfd_reloc_code_real_type);
9317 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
9320 convert_frag_immed (segT segP,
9326 char *immed_instr = fragP->fr_opcode;
9328 bfd_boolean expanded = FALSE;
9329 bfd_boolean branch_jmp_to_next = FALSE;
9330 char *fr_opcode = fragP->fr_opcode;
9331 vliw_insn orig_vinsn;
9332 xtensa_isa isa = xtensa_default_isa;
9333 bfd_boolean wide_insn = FALSE;
9335 bfd_boolean is_loop;
9337 assert (fr_opcode != NULL);
9339 xg_init_vinsn (&orig_vinsn);
9341 vinsn_from_chars (&orig_vinsn, fr_opcode);
9342 if (xtensa_format_num_slots (isa, fmt) > 1)
9345 orig_tinsn = orig_vinsn.slots[slot];
9346 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
9348 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
9350 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
9351 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
9353 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
9355 /* Conversion just inserts a NOP and marks the fix as completed. */
9356 bytes = xtensa_format_length (isa, fmt);
9359 orig_vinsn.slots[slot].opcode =
9360 xtensa_format_slot_nop_opcode (isa, orig_vinsn.format, slot);
9361 orig_vinsn.slots[slot].ntok = 0;
9365 bytes += fragP->tc_frag_data.text_expansion[0];
9366 assert (bytes == 2 || bytes == 3);
9367 build_nop (&orig_vinsn.slots[0], bytes);
9368 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
9370 vinsn_to_insnbuf (&orig_vinsn, fr_opcode, frag_now, FALSE);
9371 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf, fr_opcode, 0);
9374 else if (!orig_tinsn.is_specific_opcode)
9376 /* Here is the fun stuff: Get the immediate field from this
9377 instruction. If it fits, we're done. If not, find the next
9378 instruction sequence that fits. */
9382 symbolS *lit_sym = NULL;
9384 int target_offset = 0;
9387 symbolS *gen_label = NULL;
9388 offsetT frag_offset;
9389 bfd_boolean first = TRUE;
9390 bfd_boolean last_is_jump;
9392 /* It does not fit. Find something that does and
9393 convert immediately. */
9394 frag_offset = fr_opcode - fragP->fr_literal;
9395 istack_init (&istack);
9396 xg_assembly_relax (&istack, &orig_tinsn,
9397 segP, fragP, frag_offset, min_steps, 0);
9399 old_size = xtensa_format_length (isa, fmt);
9401 /* Assemble this right inline. */
9403 /* First, create the mapping from a label name to the REAL label. */
9405 for (i = 0; i < istack.ninsn; i++)
9407 TInsn *tinsn = &istack.insn[i];
9410 switch (tinsn->insn_type)
9413 if (lit_sym != NULL)
9414 as_bad (_("multiple literals in expansion"));
9415 /* First find the appropriate space in the literal pool. */
9416 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9417 if (lit_frag == NULL)
9418 as_bad (_("no registered fragment for literal"));
9419 if (tinsn->ntok != 1)
9420 as_bad (_("number of literal tokens != 1"));
9422 /* Set the literal symbol and add a fixup. */
9423 lit_sym = lit_frag->fr_symbol;
9427 if (align_targets && !is_loop)
9429 fragS *unreach = fragP->fr_next;
9430 while (!(unreach->fr_type == rs_machine_dependent
9431 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9432 || unreach->fr_subtype == RELAX_UNREACHABLE)))
9434 unreach = unreach->fr_next;
9437 assert (unreach->fr_type == rs_machine_dependent
9438 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
9439 || unreach->fr_subtype == RELAX_UNREACHABLE));
9441 target_offset += unreach->tc_frag_data.text_expansion[0];
9443 assert (gen_label == NULL);
9444 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
9445 fr_opcode - fragP->fr_literal
9446 + target_offset, fragP);
9450 if (first && wide_insn)
9452 target_offset += xtensa_format_length (isa, fmt);
9454 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9455 target_offset += xg_get_single_size (tinsn->opcode);
9458 target_offset += xg_get_single_size (tinsn->opcode);
9465 last_is_jump = FALSE;
9466 for (i = 0; i < istack.ninsn; i++)
9468 TInsn *tinsn = &istack.insn[i];
9472 bfd_reloc_code_real_type reloc_type;
9474 switch (tinsn->insn_type)
9477 lit_frag = fragP->tc_frag_data.literal_frags[slot];
9478 /* Already checked. */
9479 assert (lit_frag != NULL);
9480 assert (lit_sym != NULL);
9481 assert (tinsn->ntok == 1);
9483 target_seg = S_GET_SEGMENT (lit_sym);
9484 assert (target_seg);
9485 if (tinsn->tok[0].X_op == O_pltrel)
9486 reloc_type = BFD_RELOC_XTENSA_PLT;
9488 reloc_type = BFD_RELOC_32;
9489 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
9490 &tinsn->tok[0], FALSE, reloc_type);
9497 xg_resolve_labels (tinsn, gen_label);
9498 xg_resolve_literals (tinsn, lit_sym);
9499 if (wide_insn && first)
9502 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9504 tinsn->record_fix = TRUE;
9505 orig_vinsn.slots[slot] = *tinsn;
9509 orig_vinsn.slots[slot].opcode =
9510 xtensa_format_slot_nop_opcode (isa, fmt, slot);
9511 orig_vinsn.slots[slot].ntok = 0;
9512 orig_vinsn.slots[slot].record_fix = FALSE;
9514 vinsn_to_insnbuf (&orig_vinsn, immed_instr, fragP, TRUE);
9515 xtensa_insnbuf_to_chars (isa, orig_vinsn.insnbuf,
9517 fragP->tc_frag_data.is_insn = TRUE;
9518 size = xtensa_format_length (isa, fmt);
9519 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
9521 xtensa_format single_fmt =
9522 xg_get_single_format (tinsn->opcode);
9525 (tinsn, single_fmt, immed_instr + size, fragP,
9526 immed_instr - fragP->fr_literal + size, TRUE);
9527 size += xg_get_single_size (tinsn->opcode);
9532 xtensa_format single_format;
9533 size = xg_get_single_size (tinsn->opcode);
9534 single_format = xg_get_single_format (tinsn->opcode);
9535 xg_emit_insn_to_buf (tinsn, single_format, immed_instr,
9537 immed_instr - fragP->fr_literal, TRUE);
9539 immed_instr += size;
9545 diff = total_size - old_size;
9549 assert (diff <= fragP->fr_var);
9550 fragP->fr_var -= diff;
9551 fragP->fr_fix += diff;
9555 xg_free_vinsn (&orig_vinsn);
9557 /* Check for undefined immediates in LOOP instructions. */
9561 sym = orig_tinsn.tok[1].X_add_symbol;
9562 if (sym != NULL && !S_IS_DEFINED (sym))
9564 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9567 sym = orig_tinsn.tok[1].X_op_symbol;
9568 if (sym != NULL && !S_IS_DEFINED (sym))
9570 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
9575 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
9576 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
9578 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
9580 /* Add an expansion note on the expanded instruction. */
9581 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
9582 &orig_tinsn.tok[0], TRUE,
9583 BFD_RELOC_XTENSA_ASM_EXPAND);
9588 /* Add a new fix expression into the desired segment. We have to
9589 switch to that segment to do this. */
9592 fix_new_exp_in_seg (segT new_seg,
9599 bfd_reloc_code_real_type r_type)
9603 subsegT subseg = now_subseg;
9605 assert (new_seg != 0);
9606 subseg_set (new_seg, new_subseg);
9608 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
9609 subseg_set (seg, subseg);
9614 /* Relax a loop instruction so that it can span loop >256 bytes.
9620 addi as, as, lo8 (label-.L1)
9621 addmi as, as, mid8 (label-.L1)
9632 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
9637 unsigned long target;
9638 static xtensa_insnbuf insnbuf = NULL;
9639 unsigned int loop_length, loop_length_hi, loop_length_lo;
9640 xtensa_isa isa = xtensa_default_isa;
9641 addressT loop_offset;
9642 addressT addi_offset = 9;
9643 addressT addmi_offset = 12;
9645 size_t target_count;
9648 insnbuf = xtensa_insnbuf_alloc (isa);
9650 /* Get the loop offset. */
9651 loop_offset = get_expanded_loop_offset (tinsn->opcode);
9653 /* Validate that there really is a LOOP at the loop_offset. Because
9654 loops are not bundleable, we can assume that the instruction will be
9656 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
9657 tinsn_immed_from_frag (&loop_insn, fragP, 0);
9659 assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
9660 addi_offset += loop_offset;
9661 addmi_offset += loop_offset;
9663 assert (tinsn->ntok == 2);
9664 if (tinsn->tok[1].X_op == O_constant)
9665 target = tinsn->tok[1].X_add_number;
9666 else if (tinsn->tok[1].X_op == O_symbol)
9668 /* Find the fragment. */
9669 symbolS *sym = tinsn->tok[1].X_add_symbol;
9670 assert (S_GET_SEGMENT (sym) == segP
9671 || S_GET_SEGMENT (sym) == absolute_section);
9672 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
9676 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
9681 know (symbolP->sy_frag);
9682 know (!(S_GET_SEGMENT (symbolP) == absolute_section)
9683 || symbol_get_frag (symbolP) == &zero_address_frag);
9685 loop_length = target - (fragP->fr_address + fragP->fr_fix);
9686 loop_length_hi = loop_length & ~0x0ff;
9687 loop_length_lo = loop_length & 0x0ff;
9688 if (loop_length_lo >= 128)
9690 loop_length_lo -= 256;
9691 loop_length_hi += 256;
9694 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9695 32512. If the loop is larger than that, then we just fail. */
9696 if (loop_length_hi > 32512)
9697 as_bad_where (fragP->fr_file, fragP->fr_line,
9698 _("loop too long for LOOP instruction"));
9700 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
9701 assert (addi_insn.opcode == xtensa_addi_opcode);
9703 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
9704 assert (addmi_insn.opcode == xtensa_addmi_opcode);
9706 set_expr_const (&addi_insn.tok[2], loop_length_lo);
9707 tinsn_to_insnbuf (&addi_insn, insnbuf);
9709 fragP->tc_frag_data.is_insn = TRUE;
9710 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset, 0);
9712 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
9713 tinsn_to_insnbuf (&addmi_insn, insnbuf);
9714 xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset, 0);
9716 /* Walk through all of the frags from here to the loop end
9717 and mark them as no_transform to keep them from being modified
9718 by the linker. If we ever have a relocation for the
9719 addi/addmi of the difference of two symbols we can remove this. */
9722 for (next_fragP = fragP; next_fragP != NULL;
9723 next_fragP = next_fragP->fr_next)
9725 next_fragP->tc_frag_data.is_no_transform = TRUE;
9726 if (next_fragP->tc_frag_data.is_loop_target)
9728 if (target_count == 2)
9734 /* A map that keeps information on a per-subsegment basis. This is
9735 maintained during initial assembly, but is invalid once the
9736 subsegments are smashed together. I.E., it cannot be used during
9739 typedef struct subseg_map_struct
9747 float total_freq; /* fall-through + branch target frequency */
9748 float target_freq; /* branch target frequency alone */
9750 struct subseg_map_struct *next;
9754 static subseg_map *sseg_map = NULL;
9757 get_subseg_info (segT seg, subsegT subseg)
9759 subseg_map *subseg_e;
9761 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
9763 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
9771 add_subseg_info (segT seg, subsegT subseg)
9773 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
9774 memset (subseg_e, 0, sizeof (subseg_map));
9775 subseg_e->seg = seg;
9776 subseg_e->subseg = subseg;
9777 subseg_e->flags = 0;
9778 /* Start off considering every branch target very important. */
9779 subseg_e->target_freq = 1.0;
9780 subseg_e->total_freq = 1.0;
9781 subseg_e->next = sseg_map;
9782 sseg_map = subseg_e;
9788 get_last_insn_flags (segT seg, subsegT subseg)
9790 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9792 return subseg_e->flags;
9798 set_last_insn_flags (segT seg,
9803 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9805 subseg_e = add_subseg_info (seg, subseg);
9807 subseg_e->flags |= fl;
9809 subseg_e->flags &= ~fl;
9814 get_subseg_total_freq (segT seg, subsegT subseg)
9816 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9818 return subseg_e->total_freq;
9824 get_subseg_target_freq (segT seg, subsegT subseg)
9826 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9828 return subseg_e->target_freq;
9834 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
9836 subseg_map *subseg_e = get_subseg_info (seg, subseg);
9838 subseg_e = add_subseg_info (seg, subseg);
9839 subseg_e->total_freq = total_f;
9840 subseg_e->target_freq = target_f;
9844 /* Segment Lists and emit_state Stuff. */
9846 /* Remove the segment from the global sections list. */
9849 xtensa_remove_section (segT sec)
9851 /* Handle brain-dead bfd_section_list_remove macro, which
9852 expect the address of the prior section's "next" field, not
9853 just the address of the section to remove. */
9855 segT *ps_next_ptr = &stdoutput->sections;
9856 while (*ps_next_ptr != sec && *ps_next_ptr != NULL)
9857 ps_next_ptr = &(*ps_next_ptr)->next;
9859 assert (*ps_next_ptr != NULL);
9861 bfd_section_list_remove (stdoutput, ps_next_ptr);
9866 xtensa_insert_section (segT after_sec, segT sec)
9868 segT *after_sec_next;
9869 if (after_sec == NULL)
9870 after_sec_next = &stdoutput->sections;
9872 after_sec_next = &after_sec->next;
9874 bfd_section_list_insert (stdoutput, after_sec_next, sec);
9879 xtensa_move_seg_list_to_beginning (seg_list *head)
9884 segT literal_section = head->seg;
9886 /* Move the literal section to the front of the section list. */
9887 assert (literal_section);
9888 xtensa_remove_section (literal_section);
9889 xtensa_insert_section (NULL, literal_section);
9896 static void mark_literal_frags (seg_list *);
9899 xtensa_move_literals (void)
9902 frchainS *frchain_from, *frchain_to;
9903 fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after;
9904 fragS **frag_splice;
9907 fixS *fix, *next_fix, **fix_splice;
9910 mark_literal_frags (literal_head->next);
9911 mark_literal_frags (init_literal_head->next);
9912 mark_literal_frags (fini_literal_head->next);
9914 if (use_literal_section)
9917 segment = literal_head->next;
9920 frchain_from = seg_info (segment->seg)->frchainP;
9921 search_frag = frchain_from->frch_root;
9922 literal_pool = NULL;
9924 frag_splice = &(frchain_from->frch_root);
9926 while (!search_frag->tc_frag_data.literal_frag)
9928 assert (search_frag->fr_fix == 0
9929 || search_frag->fr_type == rs_align);
9930 search_frag = search_frag->fr_next;
9933 assert (search_frag->tc_frag_data.literal_frag->fr_subtype
9934 == RELAX_LITERAL_POOL_BEGIN);
9935 xtensa_switch_section_emit_state (&state, segment->seg, 0);
9937 /* Make sure that all the frags in this series are closed, and
9938 that there is at least one left over of zero-size. This
9939 prevents us from making a segment with an frchain without any
9941 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9942 xtensa_set_frag_assembly_state (frag_now);
9943 last_frag = frag_now;
9944 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
9945 xtensa_set_frag_assembly_state (frag_now);
9947 while (search_frag != frag_now)
9949 next_frag = search_frag->fr_next;
9951 /* First, move the frag out of the literal section and
9952 to the appropriate place. */
9953 if (search_frag->tc_frag_data.literal_frag)
9955 literal_pool = search_frag->tc_frag_data.literal_frag;
9956 assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
9957 /* Note that we set this fr_var to be a fix
9958 chain when we created the literal pool location
9959 as RELAX_LITERAL_POOL_BEGIN. */
9960 frchain_to = (frchainS *) literal_pool->fr_var;
9962 insert_after = literal_pool;
9964 while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
9965 insert_after = insert_after->fr_next;
9967 dest_seg = (segT) insert_after->fr_next->fr_var;
9969 *frag_splice = next_frag;
9970 search_frag->fr_next = insert_after->fr_next;
9971 insert_after->fr_next = search_frag;
9972 search_frag->tc_frag_data.lit_seg = dest_seg;
9974 /* Now move any fixups associated with this frag to the
9976 fix = frchain_from->fix_root;
9977 fix_splice = &(frchain_from->fix_root);
9980 next_fix = fix->fx_next;
9981 if (fix->fx_frag == search_frag)
9983 *fix_splice = next_fix;
9984 fix->fx_next = frchain_to->fix_root;
9985 frchain_to->fix_root = fix;
9986 if (frchain_to->fix_tail == NULL)
9987 frchain_to->fix_tail = fix;
9990 fix_splice = &(fix->fx_next);
9993 search_frag = next_frag;
9996 if (frchain_from->fix_root != NULL)
9998 frchain_from = seg_info (segment->seg)->frchainP;
9999 as_warn (_("fixes not all moved from %s"), segment->seg->name);
10001 assert (frchain_from->fix_root == NULL);
10003 frchain_from->fix_tail = NULL;
10004 xtensa_restore_emit_state (&state);
10005 segment = segment->next;
10008 /* Now fix up the SEGMENT value for all the literal symbols. */
10009 for (lit = literal_syms; lit; lit = lit->next)
10011 symbolS *lit_sym = lit->sym;
10012 segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
10014 S_SET_SEGMENT (lit_sym, dest_seg);
10019 /* Walk over all the frags for segments in a list and mark them as
10020 containing literals. As clunky as this is, we can't rely on frag_var
10021 and frag_variant to get called in all situations. */
10024 mark_literal_frags (seg_list *segment)
10026 frchainS *frchain_from;
10027 fragS *search_frag;
10031 frchain_from = seg_info (segment->seg)->frchainP;
10032 search_frag = frchain_from->frch_root;
10033 while (search_frag)
10035 search_frag->tc_frag_data.is_literal = TRUE;
10036 search_frag = search_frag->fr_next;
10038 segment = segment->next;
10044 xtensa_reorder_seg_list (seg_list *head, segT after)
10046 /* Move all of the sections in the section list to come
10047 after "after" in the gnu segment list. */
10052 segT literal_section = head->seg;
10054 /* Move the literal section after "after". */
10055 assert (literal_section);
10056 if (literal_section != after)
10058 xtensa_remove_section (literal_section);
10059 xtensa_insert_section (after, literal_section);
10067 /* Push all the literal segments to the end of the gnu list. */
10070 xtensa_reorder_segments (void)
10077 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10083 /* Now that we have the last section, push all the literal
10084 sections to the end. */
10085 xtensa_reorder_seg_list (literal_head, last_sec);
10086 xtensa_reorder_seg_list (init_literal_head, last_sec);
10087 xtensa_reorder_seg_list (fini_literal_head, last_sec);
10089 /* Now perform the final error check. */
10090 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
10092 assert (new_count == old_count);
10096 /* Change the emit state (seg, subseg, and frag related stuff) to the
10097 correct location. Return a emit_state which can be passed to
10098 xtensa_restore_emit_state to return to current fragment. */
10101 xtensa_switch_to_literal_fragment (emit_state *result)
10103 if (directive_state[directive_absolute_literals])
10105 cache_literal_section (0, default_lit_sections.lit4_seg_name,
10106 &default_lit_sections.lit4_seg, FALSE);
10107 xtensa_switch_section_emit_state (result,
10108 default_lit_sections.lit4_seg, 0);
10111 xtensa_switch_to_non_abs_literal_fragment (result);
10113 /* Do a 4-byte align here. */
10114 frag_align (2, 0, 0);
10115 record_alignment (now_seg, 2);
10120 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
10122 /* When we mark a literal pool location, we want to put a frag in
10123 the literal pool that points to it. But to do that, we want to
10124 switch_to_literal_fragment. But literal sections don't have
10125 literal pools, so their location is always null, so we would
10126 recurse forever. This is kind of hacky, but it works. */
10128 static bfd_boolean recursive = FALSE;
10129 fragS *pool_location = get_literal_pool_location (now_seg);
10130 bfd_boolean is_init =
10131 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
10133 bfd_boolean is_fini =
10134 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
10136 if (pool_location == NULL
10137 && !use_literal_section
10139 && !is_init && ! is_fini)
10141 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10143 xtensa_mark_literal_pool_location ();
10147 /* Special case: If we are in the ".fini" or ".init" section, then
10148 we will ALWAYS be generating to the ".fini.literal" and
10149 ".init.literal" sections. */
10153 cache_literal_section (init_literal_head,
10154 default_lit_sections.init_lit_seg_name,
10155 &default_lit_sections.init_lit_seg, TRUE);
10156 xtensa_switch_section_emit_state (result,
10157 default_lit_sections.init_lit_seg, 0);
10161 cache_literal_section (fini_literal_head,
10162 default_lit_sections.fini_lit_seg_name,
10163 &default_lit_sections.fini_lit_seg, TRUE);
10164 xtensa_switch_section_emit_state (result,
10165 default_lit_sections.fini_lit_seg, 0);
10169 cache_literal_section (literal_head,
10170 default_lit_sections.lit_seg_name,
10171 &default_lit_sections.lit_seg, TRUE);
10172 xtensa_switch_section_emit_state (result,
10173 default_lit_sections.lit_seg, 0);
10176 if (!use_literal_section
10177 && !is_init && !is_fini
10178 && get_literal_pool_location (now_seg) != pool_location)
10180 /* Close whatever frag is there. */
10181 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10182 xtensa_set_frag_assembly_state (frag_now);
10183 frag_now->tc_frag_data.literal_frag = pool_location;
10184 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
10185 xtensa_set_frag_assembly_state (frag_now);
10190 /* Call this function before emitting data into the literal section.
10191 This is a helper function for xtensa_switch_to_literal_fragment.
10192 This is similar to a .section new_now_seg subseg. */
10195 xtensa_switch_section_emit_state (emit_state *state,
10197 subsegT new_now_subseg)
10199 state->name = now_seg->name;
10200 state->now_seg = now_seg;
10201 state->now_subseg = now_subseg;
10202 state->generating_literals = generating_literals;
10203 generating_literals++;
10204 subseg_set (new_now_seg, new_now_subseg);
10208 /* Use to restore the emitting into the normal place. */
10211 xtensa_restore_emit_state (emit_state *state)
10213 generating_literals = state->generating_literals;
10214 subseg_set (state->now_seg, state->now_subseg);
10218 /* Get a segment of a given name. If the segment is already
10219 present, return it; otherwise, create a new one. */
10222 cache_literal_section (seg_list *head,
10225 bfd_boolean is_code)
10227 segT current_section = now_seg;
10228 int current_subsec = now_subseg;
10234 /* Check if the named section exists. */
10235 for (seg = stdoutput->sections; seg; seg = seg->next)
10237 if (!strcmp (segment_name (seg), name))
10243 /* Create a new literal section. */
10244 seg = subseg_new (name, (subsegT) 0);
10247 /* Add the newly created literal segment to the specified list. */
10248 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
10250 n->next = head->next;
10253 bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
10254 SEC_READONLY | SEC_ALLOC | SEC_LOAD
10255 | (is_code ? SEC_CODE : SEC_DATA));
10256 bfd_set_section_alignment (stdoutput, seg, 2);
10260 subseg_set (current_section, current_subsec);
10264 /* Property Tables Stuff. */
10266 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10267 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10268 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10270 typedef bfd_boolean (*frag_predicate) (const fragS *);
10271 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
10273 static bfd_boolean get_frag_is_literal (const fragS *);
10274 static void xtensa_create_property_segments
10275 (frag_predicate, frag_predicate, const char *, xt_section_type);
10276 static void xtensa_create_xproperty_segments
10277 (frag_flags_fn, const char *, xt_section_type);
10278 static segment_info_type *retrieve_segment_info (segT);
10279 static segT retrieve_xtensa_section (char *);
10280 static bfd_boolean section_has_property (segT, frag_predicate);
10281 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
10282 static void add_xt_block_frags
10283 (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
10284 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
10285 static void xtensa_frag_flags_init (frag_flags *);
10286 static void get_frag_property_flags (const fragS *, frag_flags *);
10287 static bfd_vma frag_flags_to_number (const frag_flags *);
10288 static void add_xt_prop_frags
10289 (segT, segT, xtensa_block_info **, frag_flags_fn);
10291 /* Set up property tables after relaxation. */
10294 xtensa_post_relax_hook (void)
10296 xtensa_move_seg_list_to_beginning (literal_head);
10297 xtensa_move_seg_list_to_beginning (init_literal_head);
10298 xtensa_move_seg_list_to_beginning (fini_literal_head);
10300 xtensa_find_unmarked_state_frags ();
10302 if (use_literal_section)
10303 xtensa_create_property_segments (get_frag_is_literal,
10305 XTENSA_LIT_SEC_NAME,
10307 xtensa_create_xproperty_segments (get_frag_property_flags,
10308 XTENSA_PROP_SEC_NAME,
10311 if (warn_unaligned_branch_targets)
10312 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
10313 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
10317 /* This function is only meaningful after xtensa_move_literals. */
10320 get_frag_is_literal (const fragS *fragP)
10322 assert (fragP != NULL);
10323 return fragP->tc_frag_data.is_literal;
10328 xtensa_create_property_segments (frag_predicate property_function,
10329 frag_predicate end_property_function,
10330 const char *section_name_base,
10331 xt_section_type sec_type)
10335 /* Walk over all of the current segments.
10336 Walk over each fragment
10337 For each non-empty fragment,
10338 Build a property record (append where possible). */
10340 for (seclist = &stdoutput->sections;
10341 seclist && *seclist;
10342 seclist = &(*seclist)->next)
10344 segT sec = *seclist;
10347 flags = bfd_get_section_flags (stdoutput, sec);
10348 if (flags & SEC_DEBUGGING)
10350 if (!(flags & SEC_ALLOC))
10353 if (section_has_property (sec, property_function))
10355 char *property_section_name =
10356 xtensa_get_property_section_name (sec, section_name_base);
10357 segT insn_sec = retrieve_xtensa_section (property_section_name);
10358 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10359 xtensa_block_info **xt_blocks =
10360 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10361 /* Walk over all of the frchains here and add new sections. */
10362 add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
10363 end_property_function);
10367 /* Now we fill them out.... */
10369 for (seclist = &stdoutput->sections;
10370 seclist && *seclist;
10371 seclist = &(*seclist)->next)
10373 segment_info_type *seginfo;
10374 xtensa_block_info *block;
10375 segT sec = *seclist;
10377 seginfo = seg_info (sec);
10378 block = seginfo->tc_segment_info_data.blocks[sec_type];
10382 xtensa_block_info *cur_block;
10383 /* This is a section with some data. */
10387 for (cur_block = block; cur_block; cur_block = cur_block->next)
10390 rec_size = num_recs * 8;
10391 bfd_set_section_size (stdoutput, sec, rec_size);
10393 /* In order to make this work with the assembler, we have to
10394 build some frags and then build the "fixups" for it. It
10395 would be easier to just set the contents then set the
10400 /* Allocate a fragment and leak it. */
10404 frchainS *frchainP;
10408 frag_size = sizeof (fragS) + rec_size;
10409 fragP = (fragS *) xmalloc (frag_size);
10411 memset (fragP, 0, frag_size);
10412 fragP->fr_address = 0;
10413 fragP->fr_next = NULL;
10414 fragP->fr_fix = rec_size;
10416 fragP->fr_type = rs_fill;
10417 /* The rest are zeros. */
10419 frchainP = seginfo->frchainP;
10420 frchainP->frch_root = fragP;
10421 frchainP->frch_last = fragP;
10423 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10424 memset (fixes, 0, sizeof (fixS) * num_recs);
10426 seginfo->fix_root = fixes;
10427 seginfo->fix_tail = &fixes[num_recs - 1];
10429 frag_data = &fragP->fr_literal[0];
10430 for (i = 0; i < num_recs; i++)
10432 fixS *fix = &fixes[i];
10433 assert (cur_block);
10435 /* Write the fixup. */
10436 if (i != num_recs - 1)
10437 fix->fx_next = &fixes[i + 1];
10439 fix->fx_next = NULL;
10442 fix->fx_frag = fragP;
10443 fix->fx_where = i * 8;
10444 fix->fx_addsy = section_symbol (cur_block->sec);
10445 fix->fx_offset = cur_block->offset;
10446 fix->fx_r_type = BFD_RELOC_32;
10447 fix->fx_file = "Internal Assembly";
10450 /* Write the length. */
10451 md_number_to_chars (&frag_data[4 + 8 * i],
10452 cur_block->size, 4);
10453 cur_block = cur_block->next;
10462 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
10463 const char *section_name_base,
10464 xt_section_type sec_type)
10468 /* Walk over all of the current segments.
10469 Walk over each fragment.
10470 For each fragment that has instructions,
10471 build an instruction record (append where possible). */
10473 for (seclist = &stdoutput->sections;
10474 seclist && *seclist;
10475 seclist = &(*seclist)->next)
10477 segT sec = *seclist;
10480 flags = bfd_get_section_flags (stdoutput, sec);
10481 if (flags & SEC_DEBUGGING)
10483 if (!(flags & SEC_ALLOC))
10486 if (section_has_xproperty (sec, flag_fn))
10488 char *property_section_name =
10489 xtensa_get_property_section_name (sec, section_name_base);
10490 segT insn_sec = retrieve_xtensa_section (property_section_name);
10491 segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
10492 xtensa_block_info **xt_blocks =
10493 &xt_seg_info->tc_segment_info_data.blocks[sec_type];
10494 /* Walk over all of the frchains here and add new sections. */
10495 add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
10499 /* Now we fill them out.... */
10501 for (seclist = &stdoutput->sections;
10502 seclist && *seclist;
10503 seclist = &(*seclist)->next)
10505 segment_info_type *seginfo;
10506 xtensa_block_info *block;
10507 segT sec = *seclist;
10509 seginfo = seg_info (sec);
10510 block = seginfo->tc_segment_info_data.blocks[sec_type];
10514 xtensa_block_info *cur_block;
10515 /* This is a section with some data. */
10519 for (cur_block = block; cur_block; cur_block = cur_block->next)
10522 rec_size = num_recs * (8 + 4);
10523 bfd_set_section_size (stdoutput, sec, rec_size);
10525 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10527 /* In order to make this work with the assembler, we have to build
10528 some frags then build the "fixups" for it. It would be easier to
10529 just set the contents then set the arlents. */
10533 /* Allocate a fragment and (unfortunately) leak it. */
10537 frchainS *frchainP;
10541 frag_size = sizeof (fragS) + rec_size;
10542 fragP = (fragS *) xmalloc (frag_size);
10544 memset (fragP, 0, frag_size);
10545 fragP->fr_address = 0;
10546 fragP->fr_next = NULL;
10547 fragP->fr_fix = rec_size;
10549 fragP->fr_type = rs_fill;
10550 /* The rest are zeros. */
10552 frchainP = seginfo->frchainP;
10553 frchainP->frch_root = fragP;
10554 frchainP->frch_last = fragP;
10556 fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
10557 memset (fixes, 0, sizeof (fixS) * num_recs);
10559 seginfo->fix_root = fixes;
10560 seginfo->fix_tail = &fixes[num_recs - 1];
10562 frag_data = &fragP->fr_literal[0];
10563 for (i = 0; i < num_recs; i++)
10565 fixS *fix = &fixes[i];
10566 assert (cur_block);
10568 /* Write the fixup. */
10569 if (i != num_recs - 1)
10570 fix->fx_next = &fixes[i + 1];
10572 fix->fx_next = NULL;
10575 fix->fx_frag = fragP;
10576 fix->fx_where = i * (8 + 4);
10577 fix->fx_addsy = section_symbol (cur_block->sec);
10578 fix->fx_offset = cur_block->offset;
10579 fix->fx_r_type = BFD_RELOC_32;
10580 fix->fx_file = "Internal Assembly";
10583 /* Write the length. */
10584 md_number_to_chars (&frag_data[4 + (8+4) * i],
10585 cur_block->size, 4);
10586 md_number_to_chars (&frag_data[8 + (8+4) * i],
10587 frag_flags_to_number (&cur_block->flags),
10589 cur_block = cur_block->next;
10597 static segment_info_type *
10598 retrieve_segment_info (segT seg)
10600 segment_info_type *seginfo;
10601 seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
10604 frchainS *frchainP;
10606 seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
10607 memset ((void *) seginfo, 0, sizeof (*seginfo));
10608 seginfo->fix_root = NULL;
10609 seginfo->fix_tail = NULL;
10610 seginfo->bfd_section = seg;
10612 /* We will not be dealing with these, only our special ones. */
10613 bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
10615 frchainP = (frchainS *) xmalloc (sizeof (frchainS));
10616 frchainP->frch_root = NULL;
10617 frchainP->frch_last = NULL;
10618 frchainP->frch_next = NULL;
10619 frchainP->frch_seg = seg;
10620 frchainP->frch_subseg = 0;
10621 frchainP->fix_root = NULL;
10622 frchainP->fix_tail = NULL;
10623 /* Do not init the objstack. */
10624 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10625 /* frchainP->frch_frag_now = fragP; */
10626 frchainP->frch_frag_now = NULL;
10628 seginfo->frchainP = frchainP;
10636 retrieve_xtensa_section (char *sec_name)
10638 bfd *abfd = stdoutput;
10639 flagword flags, out_flags, link_once_flags;
10642 flags = bfd_get_section_flags (abfd, now_seg);
10643 link_once_flags = (flags & SEC_LINK_ONCE);
10644 if (link_once_flags)
10645 link_once_flags |= (flags & SEC_LINK_DUPLICATES);
10646 out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
10648 s = bfd_make_section_old_way (abfd, sec_name);
10650 as_bad (_("could not create section %s"), sec_name);
10651 if (!bfd_set_section_flags (abfd, s, out_flags))
10652 as_bad (_("invalid flag combination on section %s"), sec_name);
10659 section_has_property (segT sec, frag_predicate property_function)
10661 segment_info_type *seginfo = seg_info (sec);
10664 if (seginfo && seginfo->frchainP)
10666 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10668 if (property_function (fragP)
10669 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10678 section_has_xproperty (segT sec, frag_flags_fn property_function)
10680 segment_info_type *seginfo = seg_info (sec);
10683 if (seginfo && seginfo->frchainP)
10685 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
10687 frag_flags prop_flags;
10688 property_function (fragP, &prop_flags);
10689 if (!xtensa_frag_flags_is_empty (&prop_flags))
10697 /* Two types of block sections exist right now: literal and insns. */
10700 add_xt_block_frags (segT sec,
10702 xtensa_block_info **xt_block,
10703 frag_predicate property_function,
10704 frag_predicate end_property_function)
10706 segment_info_type *seg_info;
10707 segment_info_type *xt_seg_info;
10708 bfd_vma seg_offset;
10711 xt_seg_info = retrieve_segment_info (xt_block_sec);
10712 seg_info = retrieve_segment_info (sec);
10714 /* Build it if needed. */
10715 while (*xt_block != NULL)
10716 xt_block = &(*xt_block)->next;
10717 /* We are either at NULL at the beginning or at the end. */
10719 /* Walk through the frags. */
10722 if (seg_info->frchainP)
10724 for (fragP = seg_info->frchainP->frch_root;
10726 fragP = fragP->fr_next)
10728 if (property_function (fragP)
10729 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
10731 if (*xt_block != NULL)
10733 if ((*xt_block)->offset + (*xt_block)->size
10734 == fragP->fr_address)
10735 (*xt_block)->size += fragP->fr_fix;
10737 xt_block = &((*xt_block)->next);
10739 if (*xt_block == NULL)
10741 xtensa_block_info *new_block = (xtensa_block_info *)
10742 xmalloc (sizeof (xtensa_block_info));
10743 new_block->sec = sec;
10744 new_block->offset = fragP->fr_address;
10745 new_block->size = fragP->fr_fix;
10746 new_block->next = NULL;
10747 xtensa_frag_flags_init (&new_block->flags);
10748 *xt_block = new_block;
10750 if (end_property_function
10751 && end_property_function (fragP))
10753 xt_block = &((*xt_block)->next);
10761 /* Break the encapsulation of add_xt_prop_frags here. */
10764 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
10766 if (prop_flags->is_literal
10767 || prop_flags->is_insn
10768 || prop_flags->is_data
10769 || prop_flags->is_unreachable)
10776 xtensa_frag_flags_init (frag_flags *prop_flags)
10778 memset (prop_flags, 0, sizeof (frag_flags));
10783 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
10785 xtensa_frag_flags_init (prop_flags);
10786 if (fragP->tc_frag_data.is_literal)
10787 prop_flags->is_literal = TRUE;
10788 if (fragP->tc_frag_data.is_unreachable)
10789 prop_flags->is_unreachable = TRUE;
10790 else if (fragP->tc_frag_data.is_insn)
10792 prop_flags->is_insn = TRUE;
10793 if (fragP->tc_frag_data.is_loop_target)
10794 prop_flags->insn.is_loop_target = TRUE;
10795 if (fragP->tc_frag_data.is_branch_target)
10796 prop_flags->insn.is_branch_target = TRUE;
10797 if (fragP->tc_frag_data.is_specific_opcode
10798 || fragP->tc_frag_data.is_no_transform)
10799 prop_flags->insn.is_no_transform = TRUE;
10800 if (fragP->tc_frag_data.is_no_density)
10801 prop_flags->insn.is_no_density = TRUE;
10802 if (fragP->tc_frag_data.use_absolute_literals)
10803 prop_flags->insn.is_abslit = TRUE;
10805 if (fragP->tc_frag_data.is_align)
10807 prop_flags->is_align = TRUE;
10808 prop_flags->alignment = fragP->tc_frag_data.alignment;
10809 if (xtensa_frag_flags_is_empty (prop_flags))
10810 prop_flags->is_data = TRUE;
10816 frag_flags_to_number (const frag_flags *prop_flags)
10819 if (prop_flags->is_literal)
10820 num |= XTENSA_PROP_LITERAL;
10821 if (prop_flags->is_insn)
10822 num |= XTENSA_PROP_INSN;
10823 if (prop_flags->is_data)
10824 num |= XTENSA_PROP_DATA;
10825 if (prop_flags->is_unreachable)
10826 num |= XTENSA_PROP_UNREACHABLE;
10827 if (prop_flags->insn.is_loop_target)
10828 num |= XTENSA_PROP_INSN_LOOP_TARGET;
10829 if (prop_flags->insn.is_branch_target)
10831 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
10832 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
10835 if (prop_flags->insn.is_no_density)
10836 num |= XTENSA_PROP_INSN_NO_DENSITY;
10837 if (prop_flags->insn.is_no_transform)
10838 num |= XTENSA_PROP_INSN_NO_TRANSFORM;
10839 if (prop_flags->insn.is_no_reorder)
10840 num |= XTENSA_PROP_INSN_NO_REORDER;
10841 if (prop_flags->insn.is_abslit)
10842 num |= XTENSA_PROP_INSN_ABSLIT;
10844 if (prop_flags->is_align)
10846 num |= XTENSA_PROP_ALIGN;
10847 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
10855 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
10856 const frag_flags *prop_flags_2)
10858 /* Cannot combine with an end marker. */
10860 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
10862 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
10864 if (prop_flags_1->is_data != prop_flags_2->is_data)
10867 if (prop_flags_1->is_insn)
10869 /* Properties of the beginning of the frag. */
10870 if (prop_flags_2->insn.is_loop_target)
10872 if (prop_flags_2->insn.is_branch_target)
10874 if (prop_flags_1->insn.is_no_density !=
10875 prop_flags_2->insn.is_no_density)
10877 if (prop_flags_1->insn.is_no_transform !=
10878 prop_flags_2->insn.is_no_transform)
10880 if (prop_flags_1->insn.is_no_reorder !=
10881 prop_flags_2->insn.is_no_reorder)
10883 if (prop_flags_1->insn.is_abslit !=
10884 prop_flags_2->insn.is_abslit)
10888 if (prop_flags_1->is_align)
10896 xt_block_aligned_size (const xtensa_block_info *xt_block)
10901 if (!xt_block->flags.is_align)
10902 return xt_block->size;
10904 end_addr = xt_block->offset + xt_block->size;
10905 align_bits = xt_block->flags.alignment;
10906 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
10907 return end_addr - xt_block->offset;
10912 xtensa_xt_block_combine (xtensa_block_info *xt_block,
10913 const xtensa_block_info *xt_block_2)
10915 if (xt_block->sec != xt_block_2->sec)
10917 if (xt_block->offset + xt_block_aligned_size (xt_block)
10918 != xt_block_2->offset)
10921 if (xt_block_2->size == 0
10922 && (!xt_block_2->flags.is_unreachable
10923 || xt_block->flags.is_unreachable))
10925 if (xt_block_2->flags.is_align
10926 && xt_block->flags.is_align)
10928 /* Nothing needed. */
10929 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
10934 if (xt_block_2->flags.is_align)
10936 /* Push alignment to previous entry. */
10937 xt_block->flags.is_align = xt_block_2->flags.is_align;
10938 xt_block->flags.alignment = xt_block_2->flags.alignment;
10943 if (!xtensa_frag_flags_combinable (&xt_block->flags,
10944 &xt_block_2->flags))
10947 xt_block->size += xt_block_2->size;
10949 if (xt_block_2->flags.is_align)
10951 xt_block->flags.is_align = TRUE;
10952 xt_block->flags.alignment = xt_block_2->flags.alignment;
10960 add_xt_prop_frags (segT sec,
10962 xtensa_block_info **xt_block,
10963 frag_flags_fn property_function)
10965 segment_info_type *seg_info;
10966 segment_info_type *xt_seg_info;
10967 bfd_vma seg_offset;
10970 xt_seg_info = retrieve_segment_info (xt_block_sec);
10971 seg_info = retrieve_segment_info (sec);
10972 /* Build it if needed. */
10973 while (*xt_block != NULL)
10975 xt_block = &(*xt_block)->next;
10977 /* We are either at NULL at the beginning or at the end. */
10979 /* Walk through the frags. */
10982 if (seg_info->frchainP)
10984 for (fragP = seg_info->frchainP->frch_root; fragP;
10985 fragP = fragP->fr_next)
10987 xtensa_block_info tmp_block;
10988 tmp_block.sec = sec;
10989 tmp_block.offset = fragP->fr_address;
10990 tmp_block.size = fragP->fr_fix;
10991 tmp_block.next = NULL;
10992 property_function (fragP, &tmp_block.flags);
10994 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
10995 /* && fragP->fr_fix != 0) */
10997 if ((*xt_block) == NULL
10998 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
11000 xtensa_block_info *new_block;
11001 if ((*xt_block) != NULL)
11002 xt_block = &(*xt_block)->next;
11003 new_block = (xtensa_block_info *)
11004 xmalloc (sizeof (xtensa_block_info));
11005 *new_block = tmp_block;
11006 *xt_block = new_block;
11014 /* op_placement_info_table */
11016 /* op_placement_info makes it easier to determine which
11017 ops can go in which slots. */
11020 init_op_placement_info_table (void)
11022 xtensa_isa isa = xtensa_default_isa;
11023 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
11024 xtensa_opcode opcode;
11027 int num_opcodes = xtensa_isa_num_opcodes (isa);
11029 op_placement_table = (op_placement_info_table)
11030 xmalloc (sizeof (op_placement_info) * num_opcodes);
11031 assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
11033 for (opcode = 0; opcode < num_opcodes; opcode++)
11035 op_placement_info *opi = &op_placement_table[opcode];
11036 /* FIXME: Make tinsn allocation dynamic. */
11037 if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
11038 as_fatal (_("too many operands in instruction"));
11039 opi->single = XTENSA_UNDEFINED;
11040 opi->single_size = 0;
11041 opi->widest = XTENSA_UNDEFINED;
11042 opi->widest_size = 0;
11043 opi->narrowest = XTENSA_UNDEFINED;
11044 opi->narrowest_size = 0x7F;
11046 opi->num_formats = 0;
11048 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
11050 opi->slots[fmt] = 0;
11051 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
11053 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
11055 int fmt_length = xtensa_format_length (isa, fmt);
11057 set_bit (fmt, opi->formats);
11058 set_bit (slot, opi->slots[fmt]);
11059 /* opi->slot_count[fmt]++; */
11060 if (fmt_length < opi->narrowest_size)
11062 opi->narrowest = fmt;
11063 opi->narrowest_size = fmt_length;
11065 if (fmt_length > opi->widest_size)
11068 opi->widest_size = fmt_length;
11070 if (xtensa_format_num_slots (isa, fmt) == 1)
11072 if (opi->single_size == 0
11073 || fmt_length < opi->single_size)
11076 opi->single_size = fmt_length;
11082 opi->num_formats++;
11085 xtensa_insnbuf_free (isa, ibuf);
11090 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
11092 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
11096 /* If the opcode is available in a single slot format, return its size. */
11099 xg_get_single_size (xtensa_opcode opcode)
11101 assert (op_placement_table[opcode].single != XTENSA_UNDEFINED);
11102 return op_placement_table[opcode].single_size;
11106 static xtensa_format
11107 xg_get_single_format (xtensa_opcode opcode)
11109 return op_placement_table[opcode].single;
11113 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11116 istack_init (IStack *stack)
11118 memset (stack, 0, sizeof (IStack));
11124 istack_empty (IStack *stack)
11126 return (stack->ninsn == 0);
11131 istack_full (IStack *stack)
11133 return (stack->ninsn == MAX_ISTACK);
11137 /* Return a pointer to the top IStack entry.
11138 It is an error to call this if istack_empty () is TRUE. */
11141 istack_top (IStack *stack)
11143 int rec = stack->ninsn - 1;
11144 assert (!istack_empty (stack));
11145 return &stack->insn[rec];
11149 /* Add a new TInsn to an IStack.
11150 It is an error to call this if istack_full () is TRUE. */
11153 istack_push (IStack *stack, TInsn *insn)
11155 int rec = stack->ninsn;
11156 assert (!istack_full (stack));
11157 stack->insn[rec] = *insn;
11162 /* Clear space for the next TInsn on the IStack and return a pointer
11163 to it. It is an error to call this if istack_full () is TRUE. */
11166 istack_push_space (IStack *stack)
11168 int rec = stack->ninsn;
11170 assert (!istack_full (stack));
11171 insn = &stack->insn[rec];
11172 memset (insn, 0, sizeof (TInsn));
11178 /* Remove the last pushed instruction. It is an error to call this if
11179 istack_empty () returns TRUE. */
11182 istack_pop (IStack *stack)
11184 int rec = stack->ninsn - 1;
11185 assert (!istack_empty (stack));
11187 memset (&stack->insn[rec], 0, sizeof (TInsn));
11191 /* TInsn functions. */
11194 tinsn_init (TInsn *dst)
11196 memset (dst, 0, sizeof (TInsn));
11200 /* Get the ``num''th token of the TInsn.
11201 It is illegal to call this if num > insn->ntoks. */
11204 tinsn_get_tok (TInsn *insn, int num)
11206 assert (num < insn->ntok);
11207 return &insn->tok[num];
11211 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11214 tinsn_has_symbolic_operands (const TInsn *insn)
11217 int n = insn->ntok;
11219 assert (insn->insn_type == ITYPE_INSN);
11221 for (i = 0; i < n; ++i)
11223 switch (insn->tok[i].X_op)
11237 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
11239 xtensa_isa isa = xtensa_default_isa;
11241 int n = insn->ntok;
11243 assert (insn->insn_type == ITYPE_INSN);
11245 for (i = 0; i < n; ++i)
11247 switch (insn->tok[i].X_op)
11255 /* Errors for these types are caught later. */
11260 /* Symbolic immediates are only allowed on the last immediate
11261 operand. At this time, CONST16 is the only opcode where we
11262 support non-PC-relative relocations. (It isn't necessary
11263 to complain about non-PC-relative relocations here, but
11264 otherwise, no error is reported until the relocations are
11265 generated, and the assembler won't get that far if there
11266 are any other errors. It's nice to see all the problems
11268 if (i != get_relaxable_immed (insn->opcode)
11269 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
11270 && insn->opcode != xtensa_const16_opcode))
11272 as_bad (_("invalid symbolic operand %d on '%s'"),
11273 i, xtensa_opcode_name (isa, insn->opcode));
11282 /* For assembly code with complex expressions (e.g. subtraction),
11283 we have to build them in the literal pool so that
11284 their results are calculated correctly after relaxation.
11285 The relaxation only handles expressions that
11286 boil down to SYMBOL + OFFSET. */
11289 tinsn_has_complex_operands (const TInsn *insn)
11292 int n = insn->ntok;
11293 assert (insn->insn_type == ITYPE_INSN);
11294 for (i = 0; i < n; ++i)
11296 switch (insn->tok[i].X_op)
11312 /* Convert the constant operands in the tinsn to insnbuf.
11313 Return TRUE if there is a symbol in the immediate field.
11315 Before this is called,
11316 1) the number of operands are correct
11317 2) the tinsn is a ITYPE_INSN
11318 3) ONLY the relaxable_ is built
11319 4) All operands are O_constant, O_symbol. All constants fit
11320 The return value tells whether there are any remaining O_symbols. */
11323 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
11325 static xtensa_insnbuf slotbuf = 0;
11326 xtensa_isa isa = xtensa_default_isa;
11327 xtensa_opcode opcode = tinsn->opcode;
11328 xtensa_format fmt = xg_get_single_format (opcode);
11329 bfd_boolean has_fixup = FALSE;
11330 int noperands = xtensa_opcode_num_operands (isa, opcode);
11337 slotbuf = xtensa_insnbuf_alloc (isa);
11339 assert (tinsn->insn_type == ITYPE_INSN);
11340 if (noperands != tinsn->ntok)
11341 as_fatal (_("operand number mismatch"));
11343 if (xtensa_opcode_encode (isa, fmt, 0, slotbuf, opcode))
11344 as_fatal (_("cannot encode opcode"));
11346 for (i = 0; i < noperands; ++i)
11348 expressionS *expr = &tinsn->tok[i];
11349 switch (expr->X_op)
11352 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11354 /* The register number has already been checked in
11355 expression_maybe_register, so we don't need to check here. */
11356 opnd_value = expr->X_add_number;
11357 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11358 xtensa_operand_set_field (isa, opcode, i, fmt, 0,
11359 slotbuf, opnd_value);
11363 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11365 as_where (&file_name, &line);
11366 /* It is a constant and we called this function,
11367 then we have to try to fit it. */
11368 xtensa_insnbuf_set_operand (slotbuf, fmt, 0, opcode, i,
11369 expr->X_add_number, file_name, line);
11378 xtensa_format_encode (isa, fmt, insnbuf);
11379 xtensa_format_set_slot (isa, fmt, 0, insnbuf, slotbuf);
11385 /* Convert the constant operands in the tinsn to slotbuf.
11386 Return TRUE if there is a symbol in the immediate field.
11387 (Eventually this should replace tinsn_to_insnbuf.) */
11389 /* Before this is called,
11390 1) the number of operands are correct
11391 2) the tinsn is a ITYPE_INSN
11392 3) ONLY the relaxable_ is built
11393 4) All operands are
11394 O_constant, O_symbol
11397 The return value tells whether there are any remaining O_symbols. */
11400 tinsn_to_slotbuf (xtensa_format fmt,
11403 xtensa_insnbuf slotbuf)
11405 xtensa_isa isa = xtensa_default_isa;
11406 xtensa_opcode opcode = tinsn->opcode;
11407 bfd_boolean has_fixup = FALSE;
11408 int noperands = xtensa_opcode_num_operands (isa, opcode);
11411 *((int *) &slotbuf[0]) = 0;
11412 *((int *) &slotbuf[1]) = 0;
11413 assert (tinsn->insn_type == ITYPE_INSN);
11414 if (noperands != tinsn->ntok)
11415 as_fatal (_("operand number mismatch"));
11417 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
11419 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11420 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
11424 for (i = 0; i < noperands; i++)
11426 expressionS *expr = &tinsn->tok[i];
11431 switch (expr->X_op)
11434 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11436 /* The register number has already been checked in
11437 expression_maybe_register, so we don't need to check here. */
11438 opnd_value = expr->X_add_number;
11439 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
11440 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
11443 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
11447 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
11449 as_where (&file_name, &line);
11450 /* It is a constant and we called this function
11451 then we have to try to fit it. */
11452 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
11453 expr->X_add_number, file_name, line);
11466 /* Check the instruction arguments. Return TRUE on failure. */
11469 tinsn_check_arguments (const TInsn *insn)
11471 xtensa_isa isa = xtensa_default_isa;
11472 xtensa_opcode opcode = insn->opcode;
11474 if (opcode == XTENSA_UNDEFINED)
11476 as_bad (_("invalid opcode"));
11480 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
11482 as_bad (_("too few operands"));
11486 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
11488 as_bad (_("too many operands"));
11495 /* Load an instruction from its encoded form. */
11498 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
11502 xg_init_vinsn (&vinsn);
11503 vinsn_from_chars (&vinsn, f);
11505 *tinsn = vinsn.slots[slot];
11506 xg_free_vinsn (&vinsn);
11511 tinsn_from_insnbuf (TInsn *tinsn,
11512 xtensa_insnbuf slotbuf,
11517 xtensa_isa isa = xtensa_default_isa;
11519 /* Find the immed. */
11520 tinsn_init (tinsn);
11521 tinsn->insn_type = ITYPE_INSN;
11522 tinsn->is_specific_opcode = FALSE; /* must not be specific */
11523 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
11524 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
11525 for (i = 0; i < tinsn->ntok; i++)
11527 set_expr_const (&tinsn->tok[i],
11528 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
11529 tinsn->opcode, i));
11534 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11537 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
11539 xtensa_opcode opcode = tinsn->opcode;
11542 if (fragP->tc_frag_data.slot_symbols[slot])
11544 opnum = get_relaxable_immed (opcode);
11545 assert (opnum >= 0);
11546 if (fragP->tc_frag_data.slot_sub_symbols[slot])
11548 set_expr_symbol_offset_diff
11549 (&tinsn->tok[opnum],
11550 fragP->tc_frag_data.slot_symbols[slot],
11551 fragP->tc_frag_data.slot_sub_symbols[slot],
11552 fragP->tc_frag_data.slot_offsets[slot]);
11556 set_expr_symbol_offset
11557 (&tinsn->tok[opnum],
11558 fragP->tc_frag_data.slot_symbols[slot],
11559 fragP->tc_frag_data.slot_offsets[slot]);
11566 get_num_stack_text_bytes (IStack *istack)
11569 int text_bytes = 0;
11571 for (i = 0; i < istack->ninsn; i++)
11573 TInsn *tinsn = &istack->insn[i];
11574 if (tinsn->insn_type == ITYPE_INSN)
11575 text_bytes += xg_get_single_size (tinsn->opcode);
11582 get_num_stack_literal_bytes (IStack *istack)
11587 for (i = 0; i < istack->ninsn; i++)
11589 TInsn *tinsn = &istack->insn[i];
11590 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
11597 /* vliw_insn functions. */
11600 xg_init_vinsn (vliw_insn *v)
11603 xtensa_isa isa = xtensa_default_isa;
11605 xg_clear_vinsn (v);
11607 v->insnbuf = xtensa_insnbuf_alloc (isa);
11608 if (v->insnbuf == NULL)
11609 as_fatal (_("out of memory"));
11611 for (i = 0; i < MAX_SLOTS; i++)
11613 tinsn_init (&v->slots[i]);
11614 v->slots[i].opcode = XTENSA_UNDEFINED;
11615 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
11616 if (v->slotbuf[i] == NULL)
11617 as_fatal (_("out of memory"));
11623 xg_clear_vinsn (vliw_insn *v)
11626 v->format = XTENSA_UNDEFINED;
11628 v->inside_bundle = FALSE;
11630 if (xt_saved_debug_type != DEBUG_NONE)
11631 debug_type = xt_saved_debug_type;
11633 for (i = 0; i < MAX_SLOTS; i++)
11635 memset (&v->slots[i], 0, sizeof (TInsn));
11636 v->slots[i].opcode = XTENSA_UNDEFINED;
11642 vinsn_has_specific_opcodes (vliw_insn *v)
11646 for (i = 0; i < v->num_slots; i++)
11648 if (v->slots[i].is_specific_opcode)
11656 xg_free_vinsn (vliw_insn *v)
11659 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
11660 for (i = 0; i < MAX_SLOTS; i++)
11661 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
11665 /* Before this is called, we should have
11666 filled out the following fields:
11668 1) the number of operands for each opcode are correct
11669 2) the tinsn in the slots are ITYPE_INSN
11670 3) ONLY the relaxable_ is built
11671 4) All operands are
11672 O_constant, O_symbol
11675 The return value tells whether there are any remaining O_symbols. */
11678 vinsn_to_insnbuf (vliw_insn *vinsn,
11681 bfd_boolean record_fixup)
11683 xtensa_isa isa = xtensa_default_isa;
11684 xtensa_format fmt = vinsn->format;
11685 xtensa_insnbuf insnbuf = vinsn->insnbuf;
11687 bfd_boolean has_fixup = FALSE;
11689 xtensa_format_encode (isa, fmt, insnbuf);
11691 for (slot = 0; slot < vinsn->num_slots; slot++)
11693 TInsn *tinsn = &vinsn->slots[slot];
11694 bfd_boolean tinsn_has_fixup =
11695 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
11696 vinsn->slotbuf[slot]);
11698 xtensa_format_set_slot (isa, fmt, slot,
11699 insnbuf, vinsn->slotbuf[slot]);
11700 /* tinsn_has_fixup tracks if there is a fixup at all.
11701 record_fixup controls globally. I.E., we use this
11702 function from several places, some of which are after
11703 fixups have already been recorded. Finally,
11704 tinsn->record_fixup controls based on the individual ops,
11705 which may or may not need it based on the relaxation
11707 if (tinsn_has_fixup && record_fixup)
11710 xtensa_opcode opcode = tinsn->opcode;
11711 int noperands = xtensa_opcode_num_operands (isa, opcode);
11714 for (i = 0; i < noperands; i++)
11716 expressionS* expr = &tinsn->tok[i];
11717 switch (expr->X_op)
11722 if (get_relaxable_immed (opcode) == i)
11724 if (tinsn->record_fix || expr->X_op != O_symbol)
11726 if (!xg_add_opcode_fix
11727 (tinsn, i, fmt, slot, expr, fragP,
11728 frag_offset - fragP->fr_literal))
11729 as_bad (_("instruction with constant operands does not fit"));
11733 tinsn->symbol = expr->X_add_symbol;
11734 tinsn->offset = expr->X_add_number;
11738 as_bad (_("invalid operand %d on '%s'"),
11739 i, xtensa_opcode_name (isa, opcode));
11747 if (get_relaxable_immed (opcode) == i)
11749 if (tinsn->record_fix)
11750 as_bad (_("invalid subtract operand"));
11753 tinsn->symbol = expr->X_add_symbol;
11754 tinsn->sub_symbol = expr->X_op_symbol;
11755 tinsn->offset = expr->X_add_number;
11759 as_bad (_("invalid operand %d on '%s'"),
11760 i, xtensa_opcode_name (isa, opcode));
11764 as_bad (_("invalid expression for operand %d on '%s'"),
11765 i, xtensa_opcode_name (isa, opcode));
11777 vinsn_from_chars (vliw_insn *vinsn, char *f)
11779 static xtensa_insnbuf insnbuf = NULL;
11780 static xtensa_insnbuf slotbuf = NULL;
11783 xtensa_isa isa = xtensa_default_isa;
11787 insnbuf = xtensa_insnbuf_alloc (isa);
11788 slotbuf = xtensa_insnbuf_alloc (isa);
11791 xtensa_insnbuf_from_chars (isa, insnbuf, f, 0);
11792 fmt = xtensa_format_decode (isa, insnbuf);
11793 if (fmt == XTENSA_UNDEFINED)
11794 as_fatal (_("cannot decode instruction format"));
11795 vinsn->format = fmt;
11796 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
11798 for (i = 0; i < vinsn->num_slots; i++)
11800 TInsn *tinsn = &vinsn->slots[i];
11801 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
11802 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
11807 /* Expression utilities. */
11809 /* Return TRUE if the expression is an integer constant. */
11812 expr_is_const (const expressionS *s)
11814 return (s->X_op == O_constant);
11818 /* Get the expression constant.
11819 Calling this is illegal if expr_is_const () returns TRUE. */
11822 get_expr_const (const expressionS *s)
11824 assert (expr_is_const (s));
11825 return s->X_add_number;
11829 /* Set the expression to a constant value. */
11832 set_expr_const (expressionS *s, offsetT val)
11834 s->X_op = O_constant;
11835 s->X_add_number = val;
11836 s->X_add_symbol = NULL;
11837 s->X_op_symbol = NULL;
11842 expr_is_register (const expressionS *s)
11844 return (s->X_op == O_register);
11848 /* Get the expression constant.
11849 Calling this is illegal if expr_is_const () returns TRUE. */
11852 get_expr_register (const expressionS *s)
11854 assert (expr_is_register (s));
11855 return s->X_add_number;
11859 /* Set the expression to a symbol + constant offset. */
11862 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
11864 s->X_op = O_symbol;
11865 s->X_add_symbol = sym;
11866 s->X_op_symbol = NULL; /* unused */
11867 s->X_add_number = offset;
11871 /* Set the expression to symbol - minus_sym + offset. */
11874 set_expr_symbol_offset_diff (expressionS *s,
11876 symbolS *minus_sym,
11879 s->X_op = O_subtract;
11880 s->X_add_symbol = sym;
11881 s->X_op_symbol = minus_sym; /* unused */
11882 s->X_add_number = offset;
11886 /* Return TRUE if the two expressions are equal. */
11889 expr_is_equal (expressionS *s1, expressionS *s2)
11891 if (s1->X_op != s2->X_op)
11893 if (s1->X_add_symbol != s2->X_add_symbol)
11895 if (s1->X_op_symbol != s2->X_op_symbol)
11897 if (s1->X_add_number != s2->X_add_number)
11904 copy_expr (expressionS *dst, const expressionS *src)
11906 memcpy (dst, src, sizeof (expressionS));
11910 /* Support for the "--rename-section" option. */
11912 struct rename_section_struct
11916 struct rename_section_struct *next;
11919 static struct rename_section_struct *section_rename;
11922 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11923 entries to the section_rename list. Note: Specifying multiple
11924 renamings separated by colons is not documented and is retained only
11925 for backward compatibility. */
11928 build_section_rename (const char *arg)
11930 struct rename_section_struct *r;
11931 char *this_arg = NULL;
11932 char *next_arg = NULL;
11934 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
11936 char *old_name, *new_name;
11940 next_arg = strchr (this_arg, ':');
11948 old_name = this_arg;
11949 new_name = strchr (this_arg, '=');
11951 if (*old_name == '\0')
11953 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11956 if (!new_name || new_name[1] == '\0')
11958 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11965 /* Check for invalid section renaming. */
11966 for (r = section_rename; r != NULL; r = r->next)
11968 if (strcmp (r->old_name, old_name) == 0)
11969 as_bad (_("section %s renamed multiple times"), old_name);
11970 if (strcmp (r->new_name, new_name) == 0)
11971 as_bad (_("multiple sections remapped to output section %s"),
11976 r = (struct rename_section_struct *)
11977 xmalloc (sizeof (struct rename_section_struct));
11978 r->old_name = xstrdup (old_name);
11979 r->new_name = xstrdup (new_name);
11980 r->next = section_rename;
11981 section_rename = r;
11987 xtensa_section_rename (char *name)
11989 struct rename_section_struct *r = section_rename;
11991 for (r = section_rename; r != NULL; r = r->next)
11993 if (strcmp (r->old_name, name) == 0)
11994 return r->new_name;