1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "xtensa-config.h"
31 #include "elf/xtensa.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars[] = "#";
65 const char line_comment_chars[] = "#";
66 const char line_separator_chars[] = ";";
67 const char EXP_CHARS[] = "eE";
68 const char FLT_CHARS[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported;
75 bfd_boolean absolute_literals_supported;
77 static vliw_insn cur_vinsn;
79 unsigned xtensa_num_pipe_stages;
80 unsigned xtensa_fetch_width;
82 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end = FALSE;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg;
121 static lit_state default_lit_sections;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct *next;
134 static seg_list literal_head_h;
135 static seg_list *literal_head = &literal_head_h;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct *next;
150 static sym_list *insn_labels = NULL;
151 static sym_list *free_insn_labels = NULL;
152 static sym_list *saved_insn_labels = NULL;
154 static sym_list *literal_syms;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16 = 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals = 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
217 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
218 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
221 /* Alignment is specified in the block BEFORE the one that needs
222 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
223 get the required alignment specified as a power of 2. Use
224 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
225 alignment. Be careful of side effects since the SET will evaluate
226 flags twice. Also, note that the SIZE of a block in the property
227 table does not include the alignment size, so the alignment fill
228 must be calculated to determine if two blocks are contiguous.
229 TEXT_ALIGN is not currently implemented but is a placeholder for a
230 possible future implementation. */
232 #define XTENSA_PROP_ALIGN 0x00000800
234 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
236 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
237 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
238 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
240 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
243 /* Structure for saving instruction and alignment per-fragment data
244 that will be written to the object file. This structure is
245 equivalent to the actual data that will be written out to the file
246 but is easier to use. We provide a conversion to file flags
247 in frag_flags_to_number. */
249 typedef struct frag_flags_struct frag_flags;
251 struct frag_flags_struct
253 /* is_literal should only be used after xtensa_move_literals.
254 If you need to check if you are generating a literal fragment,
255 then use the generating_literals global. */
257 unsigned is_literal : 1;
258 unsigned is_insn : 1;
259 unsigned is_data : 1;
260 unsigned is_unreachable : 1;
262 /* is_specific_opcode implies no_transform. */
263 unsigned is_no_transform : 1;
267 unsigned is_loop_target : 1;
268 unsigned is_branch_target : 1; /* Branch targets have a priority. */
269 unsigned bt_align_priority : 2;
271 unsigned is_no_density : 1;
272 /* no_longcalls flag does not need to be placed in the object file. */
274 unsigned is_no_reorder : 1;
276 /* Uses absolute literal addressing for l32r. */
277 unsigned is_abslit : 1;
279 unsigned is_align : 1;
280 unsigned alignment : 5;
284 /* Structure for saving information about a block of property data
285 for frags that have the same flags. */
286 struct xtensa_block_info_struct
292 struct xtensa_block_info_struct *next;
296 /* Structure for saving the current state before emitting literals. */
297 typedef struct emit_state_struct
302 int generating_literals;
306 /* Opcode placement information */
308 typedef unsigned long long bitfield;
309 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
310 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
311 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
313 #define MAX_FORMATS 32
315 typedef struct op_placement_info_struct
318 /* A number describing how restrictive the issue is for this
319 opcode. For example, an opcode that fits lots of different
320 formats has a high freedom, as does an opcode that fits
321 only one format but many slots in that format. The most
322 restrictive is the opcode that fits only one slot in one
325 xtensa_format narrowest;
329 /* formats is a bitfield with the Nth bit set
330 if the opcode fits in the Nth xtensa_format. */
333 /* slots[N]'s Mth bit is set if the op fits in the
334 Mth slot of the Nth xtensa_format. */
335 bitfield slots[MAX_FORMATS];
337 /* A count of the number of slots in a given format
338 an op can fit (i.e., the bitcount of the slot field above). */
339 char slots_in_format[MAX_FORMATS];
341 } op_placement_info, *op_placement_info_table;
343 op_placement_info_table op_placement_table;
346 /* Extra expression types. */
348 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
349 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
350 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
351 #define O_pcrel O_md4 /* value is a PC-relative offset */
352 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
353 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
354 #define O_tlscall O_md7 /* TLS_CALL relocation */
355 #define O_tpoff O_md8 /* TPOFF relocation */
356 #define O_dtpoff O_md9 /* DTPOFF relocation */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel),
373 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel),
374 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc),
375 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg),
376 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall),
377 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff),
378 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff),
392 directive_literal_prefix,
394 directive_absolute_literals,
395 directive_last_directive
401 bfd_boolean can_be_negated;
404 const directive_infoS directive_info[] =
407 { "literal", FALSE },
409 { "transform", TRUE },
410 { "freeregs", FALSE },
411 { "longcalls", TRUE },
412 { "literal_prefix", FALSE },
413 { "schedule", TRUE },
414 { "absolute-literals", TRUE }
417 bfd_boolean directive_state[] =
422 TRUE, /* transform */
423 FALSE, /* freeregs */
424 FALSE, /* longcalls */
425 FALSE, /* literal_prefix */
426 FALSE, /* schedule */
427 FALSE /* absolute_literals */
430 /* A circular list of all potential and actual literal pool locations
434 struct litpool_frag *next;
435 struct litpool_frag *prev;
438 short priority; /* 1, 2, or 3 -- 1 is highest */
439 short original_priority;
443 /* Map a segment to its litpool_frag list. */
446 struct litpool_seg *next;
448 struct litpool_frag frag_list;
449 int frag_count; /* since last litpool location */
452 static struct litpool_seg litpool_seg_list;
454 /* Limit maximal size of auto litpool by half of the j range. */
455 #define MAX_AUTO_POOL_LITERALS 16384
457 /* Limit maximal size of explicit literal pool by l32r range. */
458 #define MAX_EXPLICIT_POOL_LITERALS 65536
460 #define MAX_POOL_LITERALS \
461 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
463 /* Directive functions. */
465 static void xtensa_begin_directive (int);
466 static void xtensa_end_directive (int);
467 static void xtensa_literal_prefix (void);
468 static void xtensa_literal_position (int);
469 static void xtensa_literal_pseudo (int);
470 static void xtensa_frequency_pseudo (int);
471 static void xtensa_elf_cons (int);
472 static void xtensa_leb128 (int);
474 /* Parsing and Idiom Translation. */
476 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
478 /* Various Other Internal Functions. */
480 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
481 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
482 static void xtensa_mark_literal_pool_location (void);
483 static addressT get_expanded_loop_offset (xtensa_opcode);
484 static fragS *get_literal_pool_location (segT);
485 static void set_literal_pool_location (segT, fragS *);
486 static void xtensa_set_frag_assembly_state (fragS *);
487 static void finish_vinsn (vliw_insn *);
488 static bfd_boolean emit_single_op (TInsn *);
489 static int total_frag_text_expansion (fragS *);
490 static bfd_boolean use_trampolines = TRUE;
491 static void xtensa_check_frag_count (void);
492 static void xtensa_create_trampoline_frag (bfd_boolean);
493 static void xtensa_maybe_create_trampoline_frag (void);
494 struct trampoline_frag;
495 static int init_trampoline_frag (fragS *);
496 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset);
497 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean, bfd_boolean);
498 static bfd_boolean auto_litpools = FALSE;
499 static int auto_litpool_limit = 0;
501 /* Alignment Functions. */
503 static int get_text_align_power (unsigned);
504 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
505 static int branch_align_power (segT);
507 /* Helpers for xtensa_relax_frag(). */
509 static long relax_frag_add_nop (fragS *);
511 /* Accessors for additional per-subsegment information. */
513 static unsigned get_last_insn_flags (segT, subsegT);
514 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
515 static float get_subseg_total_freq (segT, subsegT);
516 static float get_subseg_target_freq (segT, subsegT);
517 static void set_subseg_freq (segT, subsegT, float, float);
519 /* Segment list functions. */
521 static void xtensa_move_literals (void);
522 static void xtensa_reorder_segments (void);
523 static void xtensa_switch_to_literal_fragment (emit_state *);
524 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
525 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
526 static void xtensa_restore_emit_state (emit_state *);
527 static segT cache_literal_section (bfd_boolean);
529 /* op_placement_info functions. */
531 static void init_op_placement_info_table (void);
532 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
533 static int xg_get_single_size (xtensa_opcode);
534 static xtensa_format xg_get_single_format (xtensa_opcode);
535 static int xg_get_single_slot (xtensa_opcode);
537 /* TInsn and IStack functions. */
539 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
540 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
541 static bfd_boolean tinsn_has_complex_operands (const TInsn *);
542 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
543 static bfd_boolean tinsn_check_arguments (const TInsn *);
544 static void tinsn_from_chars (TInsn *, char *, int);
545 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
546 static int get_num_stack_text_bytes (IStack *);
547 static int get_num_stack_literal_bytes (IStack *);
548 static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
550 /* vliw_insn functions. */
552 static void xg_init_vinsn (vliw_insn *);
553 static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
554 static void xg_clear_vinsn (vliw_insn *);
555 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
556 static void xg_free_vinsn (vliw_insn *);
557 static bfd_boolean vinsn_to_insnbuf
558 (vliw_insn *, char *, fragS *, bfd_boolean);
559 static void vinsn_from_chars (vliw_insn *, char *);
561 /* Expression Utilities. */
563 bfd_boolean expr_is_const (const expressionS *);
564 offsetT get_expr_const (const expressionS *);
565 void set_expr_const (expressionS *, offsetT);
566 bfd_boolean expr_is_register (const expressionS *);
567 offsetT get_expr_register (const expressionS *);
568 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
569 bfd_boolean expr_is_equal (expressionS *, expressionS *);
570 static void copy_expr (expressionS *, const expressionS *);
572 /* Section renaming. */
574 static void build_section_rename (const char *);
577 /* ISA imported from bfd. */
578 extern xtensa_isa xtensa_default_isa;
580 extern int target_big_endian;
582 static xtensa_opcode xtensa_addi_opcode;
583 static xtensa_opcode xtensa_addmi_opcode;
584 static xtensa_opcode xtensa_call0_opcode;
585 static xtensa_opcode xtensa_call4_opcode;
586 static xtensa_opcode xtensa_call8_opcode;
587 static xtensa_opcode xtensa_call12_opcode;
588 static xtensa_opcode xtensa_callx0_opcode;
589 static xtensa_opcode xtensa_callx4_opcode;
590 static xtensa_opcode xtensa_callx8_opcode;
591 static xtensa_opcode xtensa_callx12_opcode;
592 static xtensa_opcode xtensa_const16_opcode;
593 static xtensa_opcode xtensa_entry_opcode;
594 static xtensa_opcode xtensa_extui_opcode;
595 static xtensa_opcode xtensa_movi_opcode;
596 static xtensa_opcode xtensa_movi_n_opcode;
597 static xtensa_opcode xtensa_isync_opcode;
598 static xtensa_opcode xtensa_j_opcode;
599 static xtensa_opcode xtensa_jx_opcode;
600 static xtensa_opcode xtensa_l32r_opcode;
601 static xtensa_opcode xtensa_loop_opcode;
602 static xtensa_opcode xtensa_loopnez_opcode;
603 static xtensa_opcode xtensa_loopgtz_opcode;
604 static xtensa_opcode xtensa_nop_opcode;
605 static xtensa_opcode xtensa_nop_n_opcode;
606 static xtensa_opcode xtensa_or_opcode;
607 static xtensa_opcode xtensa_ret_opcode;
608 static xtensa_opcode xtensa_ret_n_opcode;
609 static xtensa_opcode xtensa_retw_opcode;
610 static xtensa_opcode xtensa_retw_n_opcode;
611 static xtensa_opcode xtensa_rsr_lcount_opcode;
612 static xtensa_opcode xtensa_waiti_opcode;
613 static int config_max_slots = 0;
616 /* Command-line Options. */
618 bfd_boolean use_literal_section = TRUE;
619 enum flix_level produce_flix = FLIX_ALL;
620 static bfd_boolean align_targets = TRUE;
621 static bfd_boolean warn_unaligned_branch_targets = FALSE;
622 static bfd_boolean has_a0_b_retw = FALSE;
623 static bfd_boolean workaround_a0_b_retw = FALSE;
624 static bfd_boolean workaround_b_j_loop_end = FALSE;
625 static bfd_boolean workaround_short_loop = FALSE;
626 static bfd_boolean maybe_has_short_loop = FALSE;
627 static bfd_boolean workaround_close_loop_end = FALSE;
628 static bfd_boolean maybe_has_close_loop_end = FALSE;
629 static bfd_boolean enforce_three_byte_loop_align = FALSE;
631 /* When workaround_short_loops is TRUE, all loops with early exits must
632 have at least 3 instructions. workaround_all_short_loops is a modifier
633 to the workaround_short_loop flag. In addition to the
634 workaround_short_loop actions, all straightline loopgtz and loopnez
635 must have at least 3 instructions. */
637 static bfd_boolean workaround_all_short_loops = FALSE;
639 /* Generate individual property section for every section.
640 This option is defined in BDF library. */
641 extern bfd_boolean elf32xtensa_separate_props;
644 xtensa_setup_hw_workarounds (int earliest, int latest)
646 if (earliest > latest)
647 as_fatal (_("illegal range of target hardware versions"));
649 /* Enable all workarounds for pre-T1050.0 hardware. */
650 if (earliest < 105000 || latest < 105000)
652 workaround_a0_b_retw |= TRUE;
653 workaround_b_j_loop_end |= TRUE;
654 workaround_short_loop |= TRUE;
655 workaround_close_loop_end |= TRUE;
656 workaround_all_short_loops |= TRUE;
657 enforce_three_byte_loop_align = TRUE;
664 option_density = OPTION_MD_BASE,
668 option_no_generate_flix,
675 option_no_link_relax,
683 option_text_section_literals,
684 option_no_text_section_literals,
686 option_absolute_literals,
687 option_no_absolute_literals,
689 option_align_targets,
690 option_no_align_targets,
692 option_warn_unaligned_targets,
697 option_workaround_a0_b_retw,
698 option_no_workaround_a0_b_retw,
700 option_workaround_b_j_loop_end,
701 option_no_workaround_b_j_loop_end,
703 option_workaround_short_loop,
704 option_no_workaround_short_loop,
706 option_workaround_all_short_loops,
707 option_no_workaround_all_short_loops,
709 option_workaround_close_loop_end,
710 option_no_workaround_close_loop_end,
712 option_no_workarounds,
714 option_rename_section_name,
717 option_prefer_const16,
719 option_target_hardware,
722 option_no_trampolines,
724 option_auto_litpools,
725 option_no_auto_litpools,
726 option_auto_litpool_limit,
728 option_separate_props,
729 option_no_separate_props,
732 const char *md_shortopts = "";
734 struct option md_longopts[] =
736 { "density", no_argument, NULL, option_density },
737 { "no-density", no_argument, NULL, option_no_density },
739 { "flix", no_argument, NULL, option_flix },
740 { "no-generate-flix", no_argument, NULL, option_no_generate_flix },
741 { "no-allow-flix", no_argument, NULL, option_no_flix },
743 /* Both "relax" and "generics" are deprecated and treated as equivalent
744 to the "transform" option. */
745 { "relax", no_argument, NULL, option_relax },
746 { "no-relax", no_argument, NULL, option_no_relax },
747 { "generics", no_argument, NULL, option_generics },
748 { "no-generics", no_argument, NULL, option_no_generics },
750 { "transform", no_argument, NULL, option_transform },
751 { "no-transform", no_argument, NULL, option_no_transform },
752 { "text-section-literals", no_argument, NULL, option_text_section_literals },
753 { "no-text-section-literals", no_argument, NULL,
754 option_no_text_section_literals },
755 { "absolute-literals", no_argument, NULL, option_absolute_literals },
756 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
757 /* This option was changed from -align-target to -target-align
758 because it conflicted with the "-al" option. */
759 { "target-align", no_argument, NULL, option_align_targets },
760 { "no-target-align", no_argument, NULL, option_no_align_targets },
761 { "warn-unaligned-targets", no_argument, NULL,
762 option_warn_unaligned_targets },
763 { "longcalls", no_argument, NULL, option_longcalls },
764 { "no-longcalls", no_argument, NULL, option_no_longcalls },
766 { "no-workaround-a0-b-retw", no_argument, NULL,
767 option_no_workaround_a0_b_retw },
768 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
770 { "no-workaround-b-j-loop-end", no_argument, NULL,
771 option_no_workaround_b_j_loop_end },
772 { "workaround-b-j-loop-end", no_argument, NULL,
773 option_workaround_b_j_loop_end },
775 { "no-workaround-short-loops", no_argument, NULL,
776 option_no_workaround_short_loop },
777 { "workaround-short-loops", no_argument, NULL,
778 option_workaround_short_loop },
780 { "no-workaround-all-short-loops", no_argument, NULL,
781 option_no_workaround_all_short_loops },
782 { "workaround-all-short-loop", no_argument, NULL,
783 option_workaround_all_short_loops },
785 { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
786 { "prefer-const16", no_argument, NULL, option_prefer_const16 },
788 { "no-workarounds", no_argument, NULL, option_no_workarounds },
790 { "no-workaround-close-loop-end", no_argument, NULL,
791 option_no_workaround_close_loop_end },
792 { "workaround-close-loop-end", no_argument, NULL,
793 option_workaround_close_loop_end },
795 { "rename-section", required_argument, NULL, option_rename_section_name },
797 { "link-relax", no_argument, NULL, option_link_relax },
798 { "no-link-relax", no_argument, NULL, option_no_link_relax },
800 { "target-hardware", required_argument, NULL, option_target_hardware },
802 { "trampolines", no_argument, NULL, option_trampolines },
803 { "no-trampolines", no_argument, NULL, option_no_trampolines },
805 { "auto-litpools", no_argument, NULL, option_auto_litpools },
806 { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools },
807 { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit },
809 { "separate-prop-tables", no_argument, NULL, option_separate_props },
811 { NULL, no_argument, NULL, 0 }
814 size_t md_longopts_size = sizeof md_longopts;
818 md_parse_option (int c, const char *arg)
823 as_warn (_("--density option is ignored"));
825 case option_no_density:
826 as_warn (_("--no-density option is ignored"));
828 case option_link_relax:
831 case option_no_link_relax:
835 produce_flix = FLIX_ALL;
837 case option_no_generate_flix:
838 produce_flix = FLIX_NO_GENERATE;
841 produce_flix = FLIX_NONE;
843 case option_generics:
844 as_warn (_("--generics is deprecated; use --transform instead"));
845 return md_parse_option (option_transform, arg);
846 case option_no_generics:
847 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
848 return md_parse_option (option_no_transform, arg);
850 as_warn (_("--relax is deprecated; use --transform instead"));
851 return md_parse_option (option_transform, arg);
852 case option_no_relax:
853 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
854 return md_parse_option (option_no_transform, arg);
855 case option_longcalls:
856 directive_state[directive_longcalls] = TRUE;
858 case option_no_longcalls:
859 directive_state[directive_longcalls] = FALSE;
861 case option_text_section_literals:
862 use_literal_section = FALSE;
864 case option_no_text_section_literals:
865 use_literal_section = TRUE;
867 case option_absolute_literals:
868 if (!absolute_literals_supported)
870 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
873 directive_state[directive_absolute_literals] = TRUE;
875 case option_no_absolute_literals:
876 directive_state[directive_absolute_literals] = FALSE;
879 case option_workaround_a0_b_retw:
880 workaround_a0_b_retw = TRUE;
882 case option_no_workaround_a0_b_retw:
883 workaround_a0_b_retw = FALSE;
885 case option_workaround_b_j_loop_end:
886 workaround_b_j_loop_end = TRUE;
888 case option_no_workaround_b_j_loop_end:
889 workaround_b_j_loop_end = FALSE;
892 case option_workaround_short_loop:
893 workaround_short_loop = TRUE;
895 case option_no_workaround_short_loop:
896 workaround_short_loop = FALSE;
899 case option_workaround_all_short_loops:
900 workaround_all_short_loops = TRUE;
902 case option_no_workaround_all_short_loops:
903 workaround_all_short_loops = FALSE;
906 case option_workaround_close_loop_end:
907 workaround_close_loop_end = TRUE;
909 case option_no_workaround_close_loop_end:
910 workaround_close_loop_end = FALSE;
913 case option_no_workarounds:
914 workaround_a0_b_retw = FALSE;
915 workaround_b_j_loop_end = FALSE;
916 workaround_short_loop = FALSE;
917 workaround_all_short_loops = FALSE;
918 workaround_close_loop_end = FALSE;
921 case option_align_targets:
922 align_targets = TRUE;
924 case option_no_align_targets:
925 align_targets = FALSE;
928 case option_warn_unaligned_targets:
929 warn_unaligned_branch_targets = TRUE;
932 case option_rename_section_name:
933 build_section_rename (arg);
937 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
938 should be emitted or not. FIXME: Not implemented. */
941 case option_prefer_l32r:
943 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
947 case option_prefer_const16:
949 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
953 case option_target_hardware:
955 int earliest, latest = 0;
957 if (*arg == 0 || *arg == '-')
958 as_fatal (_("invalid target hardware version"));
960 earliest = strtol (arg, &end, 0);
964 else if (*end == '-')
967 as_fatal (_("invalid target hardware version"));
968 latest = strtol (end, &end, 0);
971 as_fatal (_("invalid target hardware version"));
973 xtensa_setup_hw_workarounds (earliest, latest);
977 case option_transform:
978 /* This option has no affect other than to use the defaults,
979 which are already set. */
982 case option_no_transform:
983 /* This option turns off all transformations of any kind.
984 However, because we want to preserve the state of other
985 directives, we only change its own field. Thus, before
986 you perform any transformation, always check if transform
987 is available. If you use the functions we provide for this
988 purpose, you will be ok. */
989 directive_state[directive_transform] = FALSE;
992 case option_trampolines:
993 use_trampolines = TRUE;
996 case option_no_trampolines:
997 use_trampolines = FALSE;
1000 case option_auto_litpools:
1001 auto_litpools = TRUE;
1002 use_literal_section = FALSE;
1003 if (auto_litpool_limit <= 0)
1004 auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2;
1007 case option_no_auto_litpools:
1008 auto_litpools = FALSE;
1009 auto_litpool_limit = -1;
1012 case option_auto_litpool_limit:
1016 if (auto_litpool_limit < 0)
1017 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1018 if (*arg == 0 || *arg == '-')
1019 as_fatal (_("invalid auto-litpool-limit argument"));
1020 value = strtol (arg, &end, 10);
1022 as_fatal (_("invalid auto-litpool-limit argument"));
1023 if (value < 100 || value > 10000)
1024 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1025 auto_litpool_limit = value;
1026 auto_litpools = TRUE;
1027 use_literal_section = FALSE;
1031 case option_separate_props:
1032 elf32xtensa_separate_props = TRUE;
1035 case option_no_separate_props:
1036 elf32xtensa_separate_props = FALSE;
1046 md_show_usage (FILE *stream)
1050 --[no-]text-section-literals\n\
1051 [Do not] put literals in the text section\n\
1052 --[no-]absolute-literals\n\
1053 [Do not] default to use non-PC-relative literals\n\
1054 --[no-]target-align [Do not] try to align branch targets\n\
1055 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1056 --[no-]transform [Do not] transform instructions\n\
1057 --flix both allow hand-written and generate flix bundles\n\
1058 --no-generate-flix allow hand-written but do not generate\n\
1060 --no-allow-flix neither allow hand-written nor generate\n\
1062 --rename-section old=new Rename section 'old' to 'new'\n\
1063 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1064 when jumps do not reach their targets\n\
1065 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1066 --auto-litpool-limit=<value>\n\
1067 (range 100-10000) Maximum number of blocks of\n\
1068 instructions to emit between literal pool\n\
1069 locations; implies --auto-litpools flag\n\
1070 --[no-]separate-prop-tables\n\
1071 [Do not] place Xtensa property records into\n\
1072 individual property sections for each section.\n\
1073 Default is to generate single property section.\n", stream);
1077 /* Functions related to the list of current label symbols. */
1080 xtensa_add_insn_label (symbolS *sym)
1084 if (!free_insn_labels)
1085 l = XNEW (sym_list);
1088 l = free_insn_labels;
1089 free_insn_labels = l->next;
1093 l->next = insn_labels;
1099 xtensa_clear_insn_labels (void)
1103 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1111 xtensa_move_labels (fragS *new_frag, valueT new_offset)
1115 for (lit = insn_labels; lit; lit = lit->next)
1117 symbolS *lit_sym = lit->sym;
1118 S_SET_VALUE (lit_sym, new_offset);
1119 symbol_set_frag (lit_sym, new_frag);
1124 /* Directive data and functions. */
1126 typedef struct state_stackS_struct
1128 directiveE directive;
1129 bfd_boolean negated;
1130 bfd_boolean old_state;
1134 struct state_stackS_struct *prev;
1137 state_stackS *directive_state_stack;
1139 const pseudo_typeS md_pseudo_table[] =
1141 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
1142 { "literal_position", xtensa_literal_position, 0 },
1143 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */
1144 { "long", xtensa_elf_cons, 4 },
1145 { "word", xtensa_elf_cons, 4 },
1146 { "4byte", xtensa_elf_cons, 4 },
1147 { "short", xtensa_elf_cons, 2 },
1148 { "2byte", xtensa_elf_cons, 2 },
1149 { "sleb128", xtensa_leb128, 1},
1150 { "uleb128", xtensa_leb128, 0},
1151 { "begin", xtensa_begin_directive, 0 },
1152 { "end", xtensa_end_directive, 0 },
1153 { "literal", xtensa_literal_pseudo, 0 },
1154 { "frequency", xtensa_frequency_pseudo, 0 },
1160 use_transform (void)
1162 /* After md_end, you should be checking frag by frag, rather
1163 than state directives. */
1164 gas_assert (!past_xtensa_end);
1165 return directive_state[directive_transform];
1170 do_align_targets (void)
1172 /* Do not use this function after md_end; just look at align_targets
1173 instead. There is no target-align directive, so alignment is either
1174 enabled for all frags or not done at all. */
1175 gas_assert (!past_xtensa_end);
1176 return align_targets && use_transform ();
1181 directive_push (directiveE directive, bfd_boolean negated, const void *datum)
1185 state_stackS *stack = XNEW (state_stackS);
1187 file = as_where (&line);
1189 stack->directive = directive;
1190 stack->negated = negated;
1191 stack->old_state = directive_state[directive];
1194 stack->datum = datum;
1195 stack->prev = directive_state_stack;
1196 directive_state_stack = stack;
1198 directive_state[directive] = !negated;
1203 directive_pop (directiveE *directive,
1204 bfd_boolean *negated,
1209 state_stackS *top = directive_state_stack;
1211 if (!directive_state_stack)
1213 as_bad (_("unmatched .end directive"));
1214 *directive = directive_none;
1218 directive_state[directive_state_stack->directive] = top->old_state;
1219 *directive = top->directive;
1220 *negated = top->negated;
1223 *datum = top->datum;
1224 directive_state_stack = top->prev;
1230 directive_balance (void)
1232 while (directive_state_stack)
1234 directiveE directive;
1235 bfd_boolean negated;
1240 directive_pop (&directive, &negated, &file, &line, &datum);
1241 as_warn_where ((char *) file, line,
1242 _(".begin directive with no matching .end directive"));
1248 inside_directive (directiveE dir)
1250 state_stackS *top = directive_state_stack;
1252 while (top && top->directive != dir)
1255 return (top != NULL);
1260 get_directive (directiveE *directive, bfd_boolean *negated)
1264 const char *directive_string;
1266 if (strncmp (input_line_pointer, "no-", 3) != 0)
1271 input_line_pointer += 3;
1274 len = strspn (input_line_pointer,
1275 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1277 /* This code is a hack to make .begin [no-][generics|relax] exactly
1278 equivalent to .begin [no-]transform. We should remove it when
1279 we stop accepting those options. */
1281 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
1283 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1284 directive_string = "transform";
1286 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
1288 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1289 directive_string = "transform";
1292 directive_string = input_line_pointer;
1294 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1296 if (strncmp (directive_string, directive_info[i].name, len) == 0)
1298 input_line_pointer += len;
1299 *directive = (directiveE) i;
1300 if (*negated && !directive_info[i].can_be_negated)
1301 as_bad (_("directive %s cannot be negated"),
1302 directive_info[i].name);
1307 as_bad (_("unknown directive"));
1308 *directive = (directiveE) XTENSA_UNDEFINED;
1313 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1315 directiveE directive;
1316 bfd_boolean negated;
1320 get_directive (&directive, &negated);
1321 if (directive == (directiveE) XTENSA_UNDEFINED)
1323 discard_rest_of_line ();
1327 if (cur_vinsn.inside_bundle)
1328 as_bad (_("directives are not valid inside bundles"));
1332 case directive_literal:
1333 if (!inside_directive (directive_literal))
1335 /* Previous labels go with whatever follows this directive, not with
1336 the literal, so save them now. */
1337 saved_insn_labels = insn_labels;
1340 as_warn (_(".begin literal is deprecated; use .literal instead"));
1341 state = XNEW (emit_state);
1342 xtensa_switch_to_literal_fragment (state);
1343 directive_push (directive_literal, negated, state);
1346 case directive_literal_prefix:
1347 /* Have to flush pending output because a movi relaxed to an l32r
1348 might produce a literal. */
1349 md_flush_pending_output ();
1350 /* Check to see if the current fragment is a literal
1351 fragment. If it is, then this operation is not allowed. */
1352 if (generating_literals)
1354 as_bad (_("cannot set literal_prefix inside literal fragment"));
1358 /* Allocate the literal state for this section and push
1359 onto the directive stack. */
1360 ls = XNEW (lit_state);
1363 *ls = default_lit_sections;
1364 directive_push (directive_literal_prefix, negated, ls);
1366 /* Process the new prefix. */
1367 xtensa_literal_prefix ();
1370 case directive_freeregs:
1371 /* This information is currently unused, but we'll accept the statement
1372 and just discard the rest of the line. This won't check the syntax,
1373 but it will accept every correct freeregs directive. */
1374 input_line_pointer += strcspn (input_line_pointer, "\n");
1375 directive_push (directive_freeregs, negated, 0);
1378 case directive_schedule:
1379 md_flush_pending_output ();
1380 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1381 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1382 directive_push (directive_schedule, negated, 0);
1383 xtensa_set_frag_assembly_state (frag_now);
1386 case directive_density:
1387 as_warn (_(".begin [no-]density is ignored"));
1390 case directive_absolute_literals:
1391 md_flush_pending_output ();
1392 if (!absolute_literals_supported && !negated)
1394 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1397 xtensa_set_frag_assembly_state (frag_now);
1398 directive_push (directive, negated, 0);
1402 md_flush_pending_output ();
1403 xtensa_set_frag_assembly_state (frag_now);
1404 directive_push (directive, negated, 0);
1408 demand_empty_rest_of_line ();
1413 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1415 directiveE begin_directive, end_directive;
1416 bfd_boolean begin_negated, end_negated;
1420 emit_state **state_ptr;
1423 if (cur_vinsn.inside_bundle)
1424 as_bad (_("directives are not valid inside bundles"));
1426 get_directive (&end_directive, &end_negated);
1428 md_flush_pending_output ();
1430 switch ((int) end_directive)
1432 case XTENSA_UNDEFINED:
1433 discard_rest_of_line ();
1436 case (int) directive_density:
1437 as_warn (_(".end [no-]density is ignored"));
1438 demand_empty_rest_of_line ();
1441 case (int) directive_absolute_literals:
1442 if (!absolute_literals_supported && !end_negated)
1444 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1445 demand_empty_rest_of_line ();
1454 state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1455 directive_pop (&begin_directive, &begin_negated, &file, &line,
1456 (const void **) state_ptr);
1458 if (begin_directive != directive_none)
1460 if (begin_directive != end_directive || begin_negated != end_negated)
1462 as_bad (_("does not match begin %s%s at %s:%d"),
1463 begin_negated ? "no-" : "",
1464 directive_info[begin_directive].name, file, line);
1468 switch (end_directive)
1470 case directive_literal:
1471 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1472 xtensa_restore_emit_state (state);
1473 xtensa_set_frag_assembly_state (frag_now);
1475 if (!inside_directive (directive_literal))
1477 /* Restore the list of current labels. */
1478 xtensa_clear_insn_labels ();
1479 insn_labels = saved_insn_labels;
1483 case directive_literal_prefix:
1484 /* Restore the default collection sections from saved state. */
1485 s = (lit_state *) state;
1487 default_lit_sections = *s;
1489 /* Free the state storage. */
1490 free (s->lit_prefix);
1494 case directive_schedule:
1495 case directive_freeregs:
1499 xtensa_set_frag_assembly_state (frag_now);
1505 demand_empty_rest_of_line ();
1509 /* Place an aligned literal fragment at the current location. */
1512 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1514 md_flush_pending_output ();
1516 if (inside_directive (directive_literal))
1517 as_warn (_(".literal_position inside literal directive; ignoring"));
1518 xtensa_mark_literal_pool_location ();
1520 demand_empty_rest_of_line ();
1521 xtensa_clear_insn_labels ();
1525 /* Support .literal label, expr, ... */
1528 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1531 char *p, *base_name;
1535 if (inside_directive (directive_literal))
1537 as_bad (_(".literal not allowed inside .begin literal region"));
1538 ignore_rest_of_line ();
1542 md_flush_pending_output ();
1544 /* Previous labels go with whatever follows this directive, not with
1545 the literal, so save them now. */
1546 saved_insn_labels = insn_labels;
1549 /* If we are using text-section literals, then this is the right value... */
1552 base_name = input_line_pointer;
1554 xtensa_switch_to_literal_fragment (&state);
1556 /* ...but if we aren't using text-section-literals, then we
1557 need to put them in the section we just switched to. */
1558 if (use_literal_section || directive_state[directive_absolute_literals])
1561 /* FIXME, despite the previous comments, dest_seg is unused... */
1564 /* All literals are aligned to four-byte boundaries. */
1565 frag_align (2, 0, 0);
1566 record_alignment (now_seg, 2);
1568 c = get_symbol_name (&base_name);
1569 /* Just after name is now '\0'. */
1570 p = input_line_pointer;
1572 SKIP_WHITESPACE_AFTER_NAME ();
1574 if (*input_line_pointer != ',' && *input_line_pointer != ':')
1576 as_bad (_("expected comma or colon after symbol name; "
1577 "rest of line ignored"));
1578 ignore_rest_of_line ();
1579 xtensa_restore_emit_state (&state);
1587 input_line_pointer++; /* skip ',' or ':' */
1589 xtensa_elf_cons (4);
1591 xtensa_restore_emit_state (&state);
1593 /* Restore the list of current labels. */
1594 xtensa_clear_insn_labels ();
1595 insn_labels = saved_insn_labels;
1600 xtensa_literal_prefix (void)
1605 /* Parse the new prefix from the input_line_pointer. */
1607 len = strspn (input_line_pointer,
1608 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1609 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1611 /* Get a null-terminated copy of the name. */
1612 name = xmemdup0 (input_line_pointer, len);
1614 /* Skip the name in the input line. */
1615 input_line_pointer += len;
1617 default_lit_sections.lit_prefix = name;
1619 /* Clear cached literal sections, since the prefix has changed. */
1620 default_lit_sections.lit_seg = NULL;
1621 default_lit_sections.lit4_seg = NULL;
1625 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1628 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1630 float fall_through_f, target_f;
1632 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1633 if (fall_through_f < 0)
1635 as_bad (_("fall through frequency must be greater than 0"));
1636 ignore_rest_of_line ();
1640 target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1643 as_bad (_("branch target frequency must be greater than 0"));
1644 ignore_rest_of_line ();
1648 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1650 demand_empty_rest_of_line ();
1654 /* Like normal .long/.short/.word, except support @plt, etc.
1655 Clobbers input_line_pointer, checks end-of-line. */
1658 xtensa_elf_cons (int nbytes)
1661 bfd_reloc_code_real_type reloc;
1663 md_flush_pending_output ();
1665 if (cur_vinsn.inside_bundle)
1666 as_bad (_("directives are not valid inside bundles"));
1668 if (is_it_end_of_statement ())
1670 demand_empty_rest_of_line ();
1677 if (exp.X_op == O_symbol
1678 && *input_line_pointer == '@'
1679 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1682 reloc_howto_type *reloc_howto =
1683 bfd_reloc_type_lookup (stdoutput, reloc);
1685 if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1686 as_bad (_("unsupported relocation"));
1687 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1688 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1689 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1690 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1691 as_bad (_("opcode-specific %s relocation used outside "
1692 "an instruction"), reloc_howto->name);
1693 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1694 as_bad (ngettext ("%s relocations do not fit in %d byte",
1695 "%s relocations do not fit in %d bytes",
1697 reloc_howto->name, nbytes);
1698 else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC
1699 || reloc == BFD_RELOC_XTENSA_TLS_ARG
1700 || reloc == BFD_RELOC_XTENSA_TLS_CALL)
1701 as_bad (_("invalid use of %s relocation"), reloc_howto->name);
1704 char *p = frag_more ((int) nbytes);
1705 xtensa_set_frag_assembly_state (frag_now);
1706 fix_new_exp (frag_now, p - frag_now->fr_literal,
1707 nbytes, &exp, reloc_howto->pc_relative, reloc);
1712 xtensa_set_frag_assembly_state (frag_now);
1713 emit_expr (&exp, (unsigned int) nbytes);
1716 while (*input_line_pointer++ == ',');
1718 input_line_pointer--; /* Put terminator back into stream. */
1719 demand_empty_rest_of_line ();
1722 static bfd_boolean is_leb128_expr;
1725 xtensa_leb128 (int sign)
1727 is_leb128_expr = TRUE;
1729 is_leb128_expr = FALSE;
1733 /* Parsing and Idiom Translation. */
1735 /* Parse @plt, etc. and return the desired relocation. */
1736 static bfd_reloc_code_real_type
1737 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1747 return BFD_RELOC_NONE;
1749 for (ch = *str, str2 = ident;
1750 (str2 < ident + sizeof (ident) - 1
1751 && (ISALNUM (ch) || ch == '@'));
1754 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1761 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1762 if (ch == suffix_relocs[i].suffix[0]
1763 && len == suffix_relocs[i].length
1764 && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0)
1766 /* Now check for "identifier@suffix+constant". */
1767 if (*str == '-' || *str == '+')
1769 char *orig_line = input_line_pointer;
1770 expressionS new_exp;
1772 input_line_pointer = str;
1773 expression (&new_exp);
1774 if (new_exp.X_op == O_constant)
1776 exp_p->X_add_number += new_exp.X_add_number;
1777 str = input_line_pointer;
1780 if (&input_line_pointer != str_p)
1781 input_line_pointer = orig_line;
1785 return suffix_relocs[i].reloc;
1788 return BFD_RELOC_UNUSED;
1792 /* Find the matching operator type. */
1794 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1796 operatorT operator = O_illegal;
1799 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1801 if (suffix_relocs[i].reloc == reloc)
1803 operator = suffix_relocs[i].operator;
1807 gas_assert (operator != O_illegal);
1812 /* Find the matching reloc type. */
1813 static bfd_reloc_code_real_type
1814 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal)
1817 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1819 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1821 if (suffix_relocs[i].operator == operator)
1823 reloc = suffix_relocs[i].reloc;
1830 if (reloc == BFD_RELOC_XTENSA_TLS_FUNC)
1831 return BFD_RELOC_XTENSA_TLSDESC_FN;
1832 else if (reloc == BFD_RELOC_XTENSA_TLS_ARG)
1833 return BFD_RELOC_XTENSA_TLSDESC_ARG;
1836 if (reloc == BFD_RELOC_UNUSED)
1837 return BFD_RELOC_32;
1844 expression_end (const char *name)
1867 #define ERROR_REG_NUM ((unsigned) -1)
1870 tc_get_register (const char *prefix)
1873 const char *next_expr;
1874 const char *old_line_pointer;
1877 old_line_pointer = input_line_pointer;
1879 if (*input_line_pointer == '$')
1880 ++input_line_pointer;
1882 /* Accept "sp" as a synonym for "a1". */
1883 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1884 && expression_end (input_line_pointer + 2))
1886 input_line_pointer += 2;
1887 return 1; /* AR[1] */
1890 while (*input_line_pointer++ == *prefix++)
1892 --input_line_pointer;
1897 as_bad (_("bad register name: %s"), old_line_pointer);
1898 return ERROR_REG_NUM;
1901 if (!ISDIGIT ((unsigned char) *input_line_pointer))
1903 as_bad (_("bad register number: %s"), input_line_pointer);
1904 return ERROR_REG_NUM;
1909 while (ISDIGIT ((int) *input_line_pointer))
1910 reg = reg * 10 + *input_line_pointer++ - '0';
1912 if (!(next_expr = expression_end (input_line_pointer)))
1914 as_bad (_("bad register name: %s"), old_line_pointer);
1915 return ERROR_REG_NUM;
1918 input_line_pointer = (char *) next_expr;
1925 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1927 xtensa_isa isa = xtensa_default_isa;
1929 /* Check if this is an immediate operand. */
1930 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1932 bfd_reloc_code_real_type reloc;
1933 segT t = expression (tok);
1935 if (t == absolute_section
1936 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1938 gas_assert (tok->X_op == O_constant);
1939 tok->X_op = O_symbol;
1940 tok->X_add_symbol = &abs_symbol;
1943 if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1944 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1949 case BFD_RELOC_LO16:
1950 if (tok->X_op == O_constant)
1952 tok->X_add_number &= 0xffff;
1956 case BFD_RELOC_HI16:
1957 if (tok->X_op == O_constant)
1959 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1963 case BFD_RELOC_UNUSED:
1964 as_bad (_("unsupported relocation"));
1966 case BFD_RELOC_32_PCREL:
1967 as_bad (_("pcrel relocation not allowed in an instruction"));
1972 tok->X_op = map_suffix_reloc_to_operator (reloc);
1977 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1978 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1980 if (reg != ERROR_REG_NUM) /* Already errored */
1983 if (xtensa_operand_encode (isa, opc, opnd, &buf))
1984 as_bad (_("register number out of range"));
1987 tok->X_op = O_register;
1988 tok->X_add_symbol = 0;
1989 tok->X_add_number = reg;
1994 /* Split up the arguments for an opcode or pseudo-op. */
1997 tokenize_arguments (char **args, char *str)
1999 char *old_input_line_pointer;
2000 bfd_boolean saw_comma = FALSE;
2001 bfd_boolean saw_arg = FALSE;
2002 bfd_boolean saw_colon = FALSE;
2004 char *arg_end, *arg;
2007 /* Save and restore input_line_pointer around this function. */
2008 old_input_line_pointer = input_line_pointer;
2009 input_line_pointer = str;
2011 while (*input_line_pointer)
2014 switch (*input_line_pointer)
2021 input_line_pointer++;
2022 if (saw_comma || saw_colon || !saw_arg)
2028 input_line_pointer++;
2029 if (saw_comma || saw_colon || !saw_arg)
2035 if (!saw_comma && !saw_colon && saw_arg)
2038 arg_end = input_line_pointer + 1;
2039 while (!expression_end (arg_end))
2042 arg_len = arg_end - input_line_pointer;
2043 arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1);
2044 args[num_args] = arg;
2048 strncpy (arg, input_line_pointer, arg_len);
2049 arg[arg_len] = '\0';
2051 input_line_pointer = arg_end;
2061 if (saw_comma || saw_colon)
2063 input_line_pointer = old_input_line_pointer;
2068 as_bad (_("extra comma"));
2070 as_bad (_("extra colon"));
2072 as_bad (_("missing argument"));
2074 as_bad (_("missing comma or colon"));
2075 input_line_pointer = old_input_line_pointer;
2080 /* Parse the arguments to an opcode. Return TRUE on error. */
2083 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
2085 expressionS *tok, *last_tok;
2086 xtensa_opcode opcode = insn->opcode;
2087 bfd_boolean had_error = TRUE;
2088 xtensa_isa isa = xtensa_default_isa;
2089 int n, num_regs = 0;
2090 int opcode_operand_count;
2091 int opnd_cnt, last_opnd_cnt;
2092 unsigned int next_reg = 0;
2093 char *old_input_line_pointer;
2095 if (insn->insn_type == ITYPE_LITERAL)
2096 opcode_operand_count = 1;
2098 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
2101 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2103 /* Save and restore input_line_pointer around this function. */
2104 old_input_line_pointer = input_line_pointer;
2110 /* Skip invisible operands. */
2111 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2117 for (n = 0; n < num_args; n++)
2119 input_line_pointer = arg_strings[n];
2120 if (*input_line_pointer == ':')
2122 xtensa_regfile opnd_rf;
2123 input_line_pointer++;
2126 gas_assert (opnd_cnt > 0);
2128 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2130 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2131 as_warn (_("incorrect register number, ignoring"));
2136 if (opnd_cnt >= opcode_operand_count)
2138 as_warn (_("too many arguments"));
2141 gas_assert (opnd_cnt < MAX_INSN_ARGS);
2143 expression_maybe_register (opcode, opnd_cnt, tok);
2144 next_reg = tok->X_add_number + 1;
2146 if (tok->X_op == O_illegal || tok->X_op == O_absent)
2148 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2150 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2151 /* minus 1 because we are seeing one right now */
2157 last_opnd_cnt = opnd_cnt;
2158 demand_empty_rest_of_line ();
2165 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2169 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2172 insn->ntok = tok - insn->tok;
2176 input_line_pointer = old_input_line_pointer;
2182 get_invisible_operands (TInsn *insn)
2184 xtensa_isa isa = xtensa_default_isa;
2185 static xtensa_insnbuf slotbuf = NULL;
2187 xtensa_opcode opc = insn->opcode;
2188 int slot, opnd, fmt_found;
2192 slotbuf = xtensa_insnbuf_alloc (isa);
2194 /* Find format/slot where this can be encoded. */
2197 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2199 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2201 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2207 if (fmt_found) break;
2212 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2216 /* First encode all the visible operands
2217 (to deal with shared field operands). */
2218 for (opnd = 0; opnd < insn->ntok; opnd++)
2220 if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2221 && (insn->tok[opnd].X_op == O_register
2222 || insn->tok[opnd].X_op == O_constant))
2224 val = insn->tok[opnd].X_add_number;
2225 xtensa_operand_encode (isa, opc, opnd, &val);
2226 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2230 /* Then pull out the values for the invisible ones. */
2231 for (opnd = 0; opnd < insn->ntok; opnd++)
2233 if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2235 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2236 xtensa_operand_decode (isa, opc, opnd, &val);
2237 insn->tok[opnd].X_add_number = val;
2238 if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2239 insn->tok[opnd].X_op = O_register;
2241 insn->tok[opnd].X_op = O_constant;
2250 xg_reverse_shift_count (char **cnt_argp)
2252 char *cnt_arg, *new_arg;
2253 cnt_arg = *cnt_argp;
2255 /* replace the argument with "31-(argument)" */
2256 new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL);
2259 *cnt_argp = new_arg;
2263 /* If "arg" is a constant expression, return non-zero with the value
2267 xg_arg_is_constant (char *arg, offsetT *valp)
2270 char *save_ptr = input_line_pointer;
2272 input_line_pointer = arg;
2274 input_line_pointer = save_ptr;
2276 if (exp.X_op == O_constant)
2278 *valp = exp.X_add_number;
2287 xg_replace_opname (char **popname, const char *newop)
2290 *popname = xstrdup (newop);
2295 xg_check_num_args (int *pnum_args,
2300 int num_args = *pnum_args;
2302 if (num_args < expected_num)
2304 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2305 num_args, opname, expected_num);
2309 if (num_args > expected_num)
2311 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2312 num_args, opname, expected_num);
2313 while (num_args-- > expected_num)
2315 free (arg_strings[num_args]);
2316 arg_strings[num_args] = 0;
2318 *pnum_args = expected_num;
2326 /* If the register is not specified as part of the opcode,
2327 then get it from the operand and move it to the opcode. */
2330 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2332 xtensa_isa isa = xtensa_default_isa;
2334 char *opname, *new_opname;
2335 const char *sr_name;
2336 int is_user, is_write;
2341 is_user = (opname[1] == 'u');
2342 is_write = (opname[0] == 'w');
2344 /* Opname == [rw]ur or [rwx]sr... */
2346 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2349 /* Check if the argument is a symbolic register name. */
2350 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2351 /* Handle WSR to "INTSET" as a special case. */
2352 if (sr == XTENSA_UNDEFINED && is_write && !is_user
2353 && !strcasecmp (arg_strings[1], "intset"))
2354 sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2355 if (sr == XTENSA_UNDEFINED
2356 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2358 /* Maybe it's a register number.... */
2360 if (!xg_arg_is_constant (arg_strings[1], &val))
2362 as_bad (_("invalid register '%s' for '%s' instruction"),
2363 arg_strings[1], opname);
2366 sr = xtensa_sysreg_lookup (isa, val, is_user);
2367 if (sr == XTENSA_UNDEFINED)
2369 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2370 (long) val, opname);
2375 /* Remove the last argument, which is now part of the opcode. */
2376 free (arg_strings[1]);
2380 /* Translate the opcode. */
2381 sr_name = xtensa_sysreg_name (isa, sr);
2382 /* Another special case for "WSR.INTSET".... */
2383 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2385 new_opname = concat (*popname, ".", sr_name, (char *) NULL);
2387 *popname = new_opname;
2394 xtensa_translate_old_userreg_ops (char **popname)
2396 xtensa_isa isa = xtensa_default_isa;
2398 char *opname, *new_opname;
2399 const char *sr_name;
2400 bfd_boolean has_underbar = FALSE;
2403 if (opname[0] == '_')
2405 has_underbar = TRUE;
2409 sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2410 if (sr != XTENSA_UNDEFINED)
2412 /* The new default name ("nnn") is different from the old default
2413 name ("URnnn"). The old default is handled below, and we don't
2414 want to recognize [RW]nnn, so do nothing if the name is the (new)
2416 static char namebuf[10];
2417 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2418 if (strcmp (namebuf, opname + 1) == 0)
2426 /* Only continue if the reg name is "URnnn". */
2427 if (opname[1] != 'u' || opname[2] != 'r')
2429 val = strtoul (opname + 3, &end, 10);
2433 sr = xtensa_sysreg_lookup (isa, val, 1);
2434 if (sr == XTENSA_UNDEFINED)
2436 as_bad (_("invalid register number (%ld) for '%s'"),
2437 (long) val, opname);
2442 /* Translate the opcode. */
2443 sr_name = xtensa_sysreg_name (isa, sr);
2444 new_opname = XNEWVEC (char, strlen (sr_name) + 6);
2445 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2446 opname[0], sr_name);
2448 *popname = new_opname;
2455 xtensa_translate_zero_immed (const char *old_op,
2465 gas_assert (opname[0] != '_');
2467 if (strcmp (opname, old_op) != 0)
2470 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2472 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2474 xg_replace_opname (popname, new_op);
2475 free (arg_strings[1]);
2476 arg_strings[1] = arg_strings[2];
2485 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2486 Returns non-zero if an error was found. */
2489 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2491 char *opname = *popname;
2492 bfd_boolean has_underbar = FALSE;
2496 has_underbar = TRUE;
2500 if (strcmp (opname, "mov") == 0)
2502 if (use_transform () && !has_underbar && density_supported)
2503 xg_replace_opname (popname, "mov.n");
2506 if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2508 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2509 arg_strings[2] = xstrdup (arg_strings[1]);
2515 if (strcmp (opname, "bbsi.l") == 0)
2517 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2519 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2520 if (target_big_endian)
2521 xg_reverse_shift_count (&arg_strings[1]);
2525 if (strcmp (opname, "bbci.l") == 0)
2527 if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2529 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2530 if (target_big_endian)
2531 xg_reverse_shift_count (&arg_strings[1]);
2535 /* Don't do anything special with NOPs inside FLIX instructions. They
2536 are handled elsewhere. Real NOP instructions are always available
2537 in configurations with FLIX, so this should never be an issue but
2538 check for it anyway. */
2539 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
2540 && strcmp (opname, "nop") == 0)
2542 if (use_transform () && !has_underbar && density_supported)
2543 xg_replace_opname (popname, "nop.n");
2546 if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2548 xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2549 arg_strings[0] = xstrdup ("a1");
2550 arg_strings[1] = xstrdup ("a1");
2551 arg_strings[2] = xstrdup ("a1");
2557 /* Recognize [RW]UR and [RWX]SR. */
2558 if ((((opname[0] == 'r' || opname[0] == 'w')
2559 && (opname[1] == 'u' || opname[1] == 's'))
2560 || (opname[0] == 'x' && opname[1] == 's'))
2562 && opname[3] == '\0')
2563 return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2565 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2566 [RW]<name> if <name> is the non-default name of a user register. */
2567 if ((opname[0] == 'r' || opname[0] == 'w')
2568 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2569 return xtensa_translate_old_userreg_ops (popname);
2571 /* Relax branches that don't allow comparisons against an immediate value
2572 of zero to the corresponding branches with implicit zero immediates. */
2573 if (!has_underbar && use_transform ())
2575 if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2576 pnum_args, arg_strings))
2579 if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2580 pnum_args, arg_strings))
2583 if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2584 pnum_args, arg_strings))
2587 if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2588 pnum_args, arg_strings))
2596 /* Functions for dealing with the Xtensa ISA. */
2598 /* Currently the assembler only allows us to use a single target per
2599 fragment. Because of this, only one operand for a given
2600 instruction may be symbolic. If there is a PC-relative operand,
2601 the last one is chosen. Otherwise, the result is the number of the
2602 last immediate operand, and if there are none of those, we fail and
2606 get_relaxable_immed (xtensa_opcode opcode)
2608 int last_immed = -1;
2611 if (opcode == XTENSA_UNDEFINED)
2614 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2615 for (opi = noperands - 1; opi >= 0; opi--)
2617 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2619 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2621 if (last_immed == -1
2622 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2629 static xtensa_opcode
2630 get_opcode_from_buf (const char *buf, int slot)
2632 static xtensa_insnbuf insnbuf = NULL;
2633 static xtensa_insnbuf slotbuf = NULL;
2634 xtensa_isa isa = xtensa_default_isa;
2639 insnbuf = xtensa_insnbuf_alloc (isa);
2640 slotbuf = xtensa_insnbuf_alloc (isa);
2643 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2644 fmt = xtensa_format_decode (isa, insnbuf);
2645 if (fmt == XTENSA_UNDEFINED)
2646 return XTENSA_UNDEFINED;
2648 if (slot >= xtensa_format_num_slots (isa, fmt))
2649 return XTENSA_UNDEFINED;
2651 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2652 return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2656 #ifdef TENSILICA_DEBUG
2658 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2661 xtensa_print_insn_table (void)
2663 int num_opcodes, num_operands;
2664 xtensa_opcode opcode;
2665 xtensa_isa isa = xtensa_default_isa;
2667 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2668 for (opcode = 0; opcode < num_opcodes; opcode++)
2671 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2672 num_operands = xtensa_opcode_num_operands (isa, opcode);
2673 for (opn = 0; opn < num_operands; opn++)
2675 if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2677 if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2679 xtensa_regfile opnd_rf =
2680 xtensa_operand_regfile (isa, opcode, opn);
2681 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2683 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2684 fputs ("[lLr] ", stderr);
2686 fputs ("i ", stderr);
2688 fprintf (stderr, "\n");
2694 print_vliw_insn (xtensa_insnbuf vbuf)
2696 xtensa_isa isa = xtensa_default_isa;
2697 xtensa_format f = xtensa_format_decode (isa, vbuf);
2698 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2701 fprintf (stderr, "format = %d\n", f);
2703 for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2705 xtensa_opcode opcode;
2709 xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2710 opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2711 opname = xtensa_opcode_name (isa, opcode);
2713 fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2714 fprintf (stderr, " operands = ");
2716 operands < xtensa_opcode_num_operands (isa, opcode);
2720 if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2722 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2723 xtensa_operand_decode (isa, opcode, operands, &val);
2724 fprintf (stderr, "%d ", val);
2726 fprintf (stderr, "\n");
2728 xtensa_insnbuf_free (isa, sbuf);
2731 #endif /* TENSILICA_DEBUG */
2735 is_direct_call_opcode (xtensa_opcode opcode)
2737 xtensa_isa isa = xtensa_default_isa;
2738 int n, num_operands;
2740 if (xtensa_opcode_is_call (isa, opcode) != 1)
2743 num_operands = xtensa_opcode_num_operands (isa, opcode);
2744 for (n = 0; n < num_operands; n++)
2746 if (xtensa_operand_is_register (isa, opcode, n) == 0
2747 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2754 /* Convert from BFD relocation type code to slot and operand number.
2755 Returns non-zero on failure. */
2758 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
2760 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2761 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2763 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2766 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2767 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2769 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2779 /* Convert from slot number to BFD relocation type code for the
2780 standard PC-relative relocations. Return BFD_RELOC_NONE on
2783 static bfd_reloc_code_real_type
2784 encode_reloc (int slot)
2786 if (slot < 0 || slot > 14)
2787 return BFD_RELOC_NONE;
2789 return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2793 /* Convert from slot numbers to BFD relocation type code for the
2794 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2796 static bfd_reloc_code_real_type
2797 encode_alt_reloc (int slot)
2799 if (slot < 0 || slot > 14)
2800 return BFD_RELOC_NONE;
2802 return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2807 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2810 xtensa_opcode opcode,
2816 uint32 valbuf = value;
2818 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2820 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2822 as_bad_where ((char *) file, line,
2823 _("operand %d of '%s' has out of range value '%u'"),
2825 xtensa_opcode_name (xtensa_default_isa, opcode),
2828 as_bad_where ((char *) file, line,
2829 _("operand %d of '%s' has invalid value '%u'"),
2831 xtensa_opcode_name (xtensa_default_isa, opcode),
2836 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2842 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2845 xtensa_opcode opcode,
2849 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2850 fmt, slot, slotbuf, &val);
2851 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2856 /* Checks for rules from xtensa-relax tables. */
2858 /* The routine xg_instruction_matches_option_term must return TRUE
2859 when a given option term is true. The meaning of all of the option
2860 terms is given interpretation by this function. */
2863 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
2865 if (strcmp (option->option_name, "realnop") == 0
2866 || strncmp (option->option_name, "IsaUse", 6) == 0)
2868 /* These conditions were evaluated statically when building the
2869 relaxation table. There's no need to reevaluate them now. */
2872 else if (strcmp (option->option_name, "FREEREG") == 0)
2873 return insn->extra_arg.X_op == O_register;
2876 as_fatal (_("internal error: unknown option name '%s'"),
2877 option->option_name);
2883 xg_instruction_matches_or_options (TInsn *insn,
2884 const ReqOrOptionList *or_option)
2886 const ReqOrOption *option;
2887 /* Must match each of the AND terms. */
2888 for (option = or_option; option != NULL; option = option->next)
2890 if (xg_instruction_matches_option_term (insn, option))
2898 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2900 const ReqOption *req_options;
2901 /* Must match each of the AND terms. */
2902 for (req_options = options;
2903 req_options != NULL;
2904 req_options = req_options->next)
2906 /* Must match one of the OR clauses. */
2907 if (!xg_instruction_matches_or_options (insn,
2908 req_options->or_option_terms))
2915 /* Return the transition rule that matches or NULL if none matches. */
2918 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2920 PreconditionList *condition_l;
2922 if (rule->opcode != insn->opcode)
2925 for (condition_l = rule->conditions;
2926 condition_l != NULL;
2927 condition_l = condition_l->next)
2931 Precondition *cond = condition_l->precond;
2936 /* The expression must be the constant. */
2937 gas_assert (cond->op_num < insn->ntok);
2938 exp1 = &insn->tok[cond->op_num];
2939 if (expr_is_const (exp1))
2944 if (get_expr_const (exp1) != cond->op_data)
2948 if (get_expr_const (exp1) == cond->op_data)
2955 else if (expr_is_register (exp1))
2960 if (get_expr_register (exp1) != cond->op_data)
2964 if (get_expr_register (exp1) == cond->op_data)
2976 gas_assert (cond->op_num < insn->ntok);
2977 gas_assert (cond->op_data < insn->ntok);
2978 exp1 = &insn->tok[cond->op_num];
2979 exp2 = &insn->tok[cond->op_data];
2984 if (!expr_is_equal (exp1, exp2))
2988 if (expr_is_equal (exp1, exp2))
3000 if (!xg_instruction_matches_options (insn, rule->options))
3008 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
3010 bfd_boolean a_greater = FALSE;
3011 bfd_boolean b_greater = FALSE;
3013 ReqOptionList *l_a = a->options;
3014 ReqOptionList *l_b = b->options;
3016 /* We only care if they both are the same except for
3017 a const16 vs. an l32r. */
3019 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3021 ReqOrOptionList *l_or_a = l_a->or_option_terms;
3022 ReqOrOptionList *l_or_b = l_b->or_option_terms;
3023 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3025 if (l_or_a->is_true != l_or_b->is_true)
3027 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
3029 /* This is the case we care about. */
3030 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
3031 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
3038 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
3039 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
3049 l_or_a = l_or_a->next;
3050 l_or_b = l_or_b->next;
3052 if (l_or_a || l_or_b)
3061 /* Incomparable if the substitution was used differently in two cases. */
3062 if (a_greater && b_greater)
3074 static TransitionRule *
3075 xg_instruction_match (TInsn *insn)
3077 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
3079 gas_assert (insn->opcode < table->num_opcodes);
3081 /* Walk through all of the possible transitions. */
3082 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3084 TransitionRule *rule = l->rule;
3085 if (xg_instruction_matches_rule (insn, rule))
3092 /* Various Other Internal Functions. */
3095 is_unique_insn_expansion (TransitionRule *r)
3097 if (!r->to_instr || r->to_instr->next != NULL)
3099 if (r->to_instr->typ != INSTR_INSTR)
3105 /* Check if there is exactly one relaxation for INSN that converts it to
3106 another instruction of equal or larger size. If so, and if TARG is
3107 non-null, go ahead and generate the relaxed instruction into TARG. If
3108 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3109 instruction, i.e., ignore relaxations that convert to an instruction of
3110 equal size. In some contexts where this function is used, only
3111 a single widening is allowed and the NARROW_ONLY argument is used to
3112 exclude cases like ADDI being "widened" to an ADDMI, which may
3113 later be relaxed to an ADDMI/ADDI pair. */
3116 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
3118 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3120 TransitionRule *match = 0;
3122 gas_assert (insn->insn_type == ITYPE_INSN);
3123 gas_assert (insn->opcode < table->num_opcodes);
3125 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3127 TransitionRule *rule = l->rule;
3129 if (xg_instruction_matches_rule (insn, rule)
3130 && is_unique_insn_expansion (rule)
3131 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3132 <= xg_get_single_size (rule->to_instr->opcode)))
3143 xg_build_to_insn (targ, insn, match->to_instr);
3148 /* Return the maximum number of bytes this opcode can expand to. */
3151 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3153 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3155 int max_size = xg_get_single_size (opcode);
3157 gas_assert (opcode < table->num_opcodes);
3159 for (l = table->table[opcode]; l != NULL; l = l->next)
3161 TransitionRule *rule = l->rule;
3162 BuildInstr *build_list;
3167 build_list = rule->to_instr;
3168 if (is_unique_insn_expansion (rule))
3170 gas_assert (build_list->typ == INSTR_INSTR);
3171 this_size = xg_get_max_insn_widen_size (build_list->opcode);
3174 for (; build_list != NULL; build_list = build_list->next)
3176 switch (build_list->typ)
3179 this_size += xg_get_single_size (build_list->opcode);
3181 case INSTR_LITERAL_DEF:
3182 case INSTR_LABEL_DEF:
3187 if (this_size > max_size)
3188 max_size = this_size;
3194 /* Return the maximum number of literal bytes this opcode can generate. */
3197 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3199 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3203 gas_assert (opcode < table->num_opcodes);
3205 for (l = table->table[opcode]; l != NULL; l = l->next)
3207 TransitionRule *rule = l->rule;
3208 BuildInstr *build_list;
3213 build_list = rule->to_instr;
3214 if (is_unique_insn_expansion (rule))
3216 gas_assert (build_list->typ == INSTR_INSTR);
3217 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3220 for (; build_list != NULL; build_list = build_list->next)
3222 switch (build_list->typ)
3224 case INSTR_LITERAL_DEF:
3225 /* Hard-coded 4-byte literal. */
3229 case INSTR_LABEL_DEF:
3234 if (this_size > max_size)
3235 max_size = this_size;
3242 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3244 int steps_taken = 0;
3245 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3248 gas_assert (insn->insn_type == ITYPE_INSN);
3249 gas_assert (insn->opcode < table->num_opcodes);
3251 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3253 TransitionRule *rule = l->rule;
3255 if (xg_instruction_matches_rule (insn, rule))
3257 if (steps_taken == lateral_steps)
3267 get_special_literal_symbol (void)
3269 static symbolS *sym = NULL;
3272 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3278 get_special_label_symbol (void)
3280 static symbolS *sym = NULL;
3283 sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3289 xg_valid_literal_expression (const expressionS *exp)
3311 /* This will check to see if the value can be converted into the
3312 operand type. It will return TRUE if it does not fit. */
3315 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3317 uint32 valbuf = value;
3318 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3324 /* Assumes: All immeds are constants. Check that all constants fit
3325 into their immeds; return FALSE if not. */
3328 xg_immeds_fit (const TInsn *insn)
3330 xtensa_isa isa = xtensa_default_isa;
3334 gas_assert (insn->insn_type == ITYPE_INSN);
3335 for (i = 0; i < n; ++i)
3337 const expressionS *exp = &insn->tok[i];
3339 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3346 if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3351 /* The symbol should have a fixup associated with it. */
3360 /* This should only be called after we have an initial
3361 estimate of the addresses. */
3364 xg_symbolic_immeds_fit (const TInsn *insn,
3370 xtensa_isa isa = xtensa_default_isa;
3378 gas_assert (insn->insn_type == ITYPE_INSN);
3380 for (i = 0; i < n; ++i)
3382 const expressionS *exp = &insn->tok[i];
3384 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3391 if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3397 /* Check for the worst case. */
3398 if (xg_check_operand (0xffff, insn->opcode, i))
3403 /* We only allow symbols for PC-relative references.
3404 If pc_frag == 0, then we don't have frag locations yet. */
3406 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3409 /* If it is a weak symbol or a symbol in a different section,
3410 it cannot be known to fit at assembly time. */
3411 if (S_IS_WEAK (exp->X_add_symbol)
3412 || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg)
3414 /* For a direct call with --no-longcalls, be optimistic and
3415 assume it will be in range. If the symbol is weak and
3416 undefined, it may remain undefined at link-time, in which
3417 case it will have a zero value and almost certainly be out
3418 of range for a direct call; thus, relax for undefined weak
3419 symbols even if longcalls is not enabled. */
3420 if (is_direct_call_opcode (insn->opcode)
3421 && ! pc_frag->tc_frag_data.use_longcalls
3422 && (! S_IS_WEAK (exp->X_add_symbol)
3423 || S_IS_DEFINED (exp->X_add_symbol)))
3429 symbolP = exp->X_add_symbol;
3430 sym_frag = symbol_get_frag (symbolP);
3431 target = S_GET_VALUE (symbolP) + exp->X_add_number;
3432 pc = pc_frag->fr_address + pc_offset;
3434 /* If frag has yet to be reached on this pass, assume it
3435 will move by STRETCH just as we did. If this is not so,
3436 it will be because some frag between grows, and that will
3437 force another pass. Beware zero-length frags. There
3438 should be a faster way to do this. */
3441 && sym_frag->relax_marker != pc_frag->relax_marker
3442 && S_GET_SEGMENT (symbolP) == pc_seg)
3447 new_offset = target;
3448 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3449 if (xg_check_operand (new_offset, insn->opcode, i))
3454 /* The symbol should have a fixup associated with it. */
3463 /* Return TRUE on success. */
3466 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3472 targ->debug_line = insn->debug_line;
3473 targ->loc_directive_seen = insn->loc_directive_seen;
3478 targ->opcode = bi->opcode;
3479 targ->insn_type = ITYPE_INSN;
3480 targ->is_specific_opcode = FALSE;
3482 for (; op != NULL; op = op->next)
3484 int op_num = op->op_num;
3485 int op_data = op->op_data;
3487 gas_assert (op->op_num < MAX_INSN_ARGS);
3489 if (targ->ntok <= op_num)
3490 targ->ntok = op_num + 1;
3495 set_expr_const (&targ->tok[op_num], op_data);
3498 gas_assert (op_data < insn->ntok);
3499 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3502 if (insn->extra_arg.X_op != O_register)
3504 copy_expr (&targ->tok[op_num], &insn->extra_arg);
3507 sym = get_special_literal_symbol ();
3508 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3509 if (insn->tok[op_data].X_op == O_tlsfunc
3510 || insn->tok[op_data].X_op == O_tlsarg)
3511 copy_expr (&targ->extra_arg, &insn->tok[op_data]);
3514 sym = get_special_label_symbol ();
3515 set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3517 case OP_OPERAND_HI16U:
3518 case OP_OPERAND_LOW16U:
3519 gas_assert (op_data < insn->ntok);
3520 if (expr_is_const (&insn->tok[op_data]))
3523 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3524 val = xg_apply_userdef_op_fn (op->typ,
3527 targ->tok[op_num].X_add_number = val;
3531 /* For const16 we can create relocations for these. */
3532 if (targ->opcode == XTENSA_UNDEFINED
3533 || (targ->opcode != xtensa_const16_opcode))
3535 gas_assert (op_data < insn->ntok);
3536 /* Need to build a O_lo16 or O_hi16. */
3537 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3538 if (targ->tok[op_num].X_op == O_symbol)
3540 if (op->typ == OP_OPERAND_HI16U)
3541 targ->tok[op_num].X_op = O_hi16;
3542 else if (op->typ == OP_OPERAND_LOW16U)
3543 targ->tok[op_num].X_op = O_lo16;
3550 /* currently handles:
3553 OP_OPERAND_F32MINUS */
3554 if (xg_has_userdef_op_fn (op->typ))
3556 gas_assert (op_data < insn->ntok);
3557 if (expr_is_const (&insn->tok[op_data]))
3560 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3561 val = xg_apply_userdef_op_fn (op->typ,
3564 targ->tok[op_num].X_add_number = val;
3567 return FALSE; /* We cannot use a relocation for this. */
3576 case INSTR_LITERAL_DEF:
3578 targ->opcode = XTENSA_UNDEFINED;
3579 targ->insn_type = ITYPE_LITERAL;
3580 targ->is_specific_opcode = FALSE;
3581 for (; op != NULL; op = op->next)
3583 int op_num = op->op_num;
3584 int op_data = op->op_data;
3585 gas_assert (op->op_num < MAX_INSN_ARGS);
3587 if (targ->ntok <= op_num)
3588 targ->ntok = op_num + 1;
3593 gas_assert (op_data < insn->ntok);
3594 /* We can only pass resolvable literals through. */
3595 if (!xg_valid_literal_expression (&insn->tok[op_data]))
3597 copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3609 case INSTR_LABEL_DEF:
3611 targ->opcode = XTENSA_UNDEFINED;
3612 targ->insn_type = ITYPE_LABEL;
3613 targ->is_specific_opcode = FALSE;
3614 /* Literal with no ops is a label? */
3615 gas_assert (op == NULL);
3626 /* Return TRUE on success. */
3629 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3631 for (; bi != NULL; bi = bi->next)
3633 TInsn *next_insn = istack_push_space (istack);
3635 if (!xg_build_to_insn (next_insn, insn, bi))
3642 /* Return TRUE on valid expansion. */
3645 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3647 int stack_size = istack->ninsn;
3648 int steps_taken = 0;
3649 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3652 gas_assert (insn->insn_type == ITYPE_INSN);
3653 gas_assert (insn->opcode < table->num_opcodes);
3655 for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3657 TransitionRule *rule = l->rule;
3659 if (xg_instruction_matches_rule (insn, rule))
3661 if (lateral_steps == steps_taken)
3665 /* This is it. Expand the rule to the stack. */
3666 if (!xg_build_to_stack (istack, insn, rule->to_instr))
3669 /* Check to see if it fits. */
3670 for (i = stack_size; i < istack->ninsn; i++)
3672 TInsn *tinsn = &istack->insn[i];
3674 if (tinsn->insn_type == ITYPE_INSN
3675 && !tinsn_has_symbolic_operands (tinsn)
3676 && !xg_immeds_fit (tinsn))
3678 istack->ninsn = stack_size;
3691 /* Relax the assembly instruction at least "min_steps".
3692 Return the number of steps taken.
3694 For relaxation to correctly terminate, every relaxation chain must
3695 terminate in one of two ways:
3697 1. If the chain from one instruction to the next consists entirely of
3698 single instructions, then the chain *must* handle all possible
3699 immediates without failing. It must not ever fail because an
3700 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3701 chain is one example. L32R loads 32 bits, and there cannot be an
3702 immediate larger than 32 bits, so it satisfies this condition.
3703 Single instruction relaxation chains are as defined by
3704 xg_is_single_relaxable_instruction.
3706 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3707 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3709 Strictly speaking, in most cases you can violate condition 1 and be OK
3710 -- in particular when the last two instructions have the same single
3711 size. But nevertheless, you should guarantee the above two conditions.
3713 We could fix this so that single-instruction expansions correctly
3714 terminate when they can't handle the range, but the error messages are
3715 worse, and it actually turns out that in every case but one (18-bit wide
3716 branches), you need a multi-instruction expansion to get the full range
3717 anyway. And because 18-bit branches are handled identically to 15-bit
3718 branches, there isn't any point in changing it. */
3721 xg_assembly_relax (IStack *istack,
3724 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */
3725 offsetT pc_offset, /* offset in fragment */
3726 int min_steps, /* minimum conversion steps */
3727 long stretch) /* number of bytes stretched so far */
3729 int steps_taken = 0;
3731 /* Some of its immeds don't fit. Try to build a relaxed version.
3732 This may go through a couple of stages of single instruction
3733 transformations before we get there. */
3735 TInsn single_target;
3737 int lateral_steps = 0;
3738 int istack_size = istack->ninsn;
3740 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3741 && steps_taken >= min_steps)
3743 istack_push (istack, insn);
3746 current_insn = *insn;
3748 /* Walk through all of the single instruction expansions. */
3749 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE))
3752 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3755 if (steps_taken >= min_steps)
3757 istack_push (istack, &single_target);
3761 current_insn = single_target;
3764 /* Now check for a multi-instruction expansion. */
3765 while (xg_is_relaxable_insn (¤t_insn, lateral_steps))
3767 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset,
3770 if (steps_taken >= min_steps)
3772 istack_push (istack, ¤t_insn);
3777 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps))
3779 if (steps_taken >= min_steps)
3783 istack->ninsn = istack_size;
3786 /* It's not going to work -- use the original. */
3787 istack_push (istack, insn);
3793 xg_finish_frag (char *last_insn,
3794 enum xtensa_relax_statesE frag_state,
3795 enum xtensa_relax_statesE slot0_state,
3797 bfd_boolean is_insn)
3799 /* Finish off this fragment so that it has at LEAST the desired
3800 max_growth. If it doesn't fit in this fragment, close this one
3801 and start a new one. In either case, return a pointer to the
3802 beginning of the growth area. */
3806 frag_grow (max_growth);
3807 old_frag = frag_now;
3809 frag_now->fr_opcode = last_insn;
3811 frag_now->tc_frag_data.is_insn = TRUE;
3813 frag_var (rs_machine_dependent, max_growth, max_growth,
3814 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3816 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3817 xtensa_set_frag_assembly_state (frag_now);
3819 /* Just to make sure that we did not split it up. */
3820 gas_assert (old_frag->fr_next == frag_now);
3824 /* Return TRUE if the target frag is one of the next non-empty frags. */
3827 is_next_frag_target (const fragS *fragP, const fragS *target)
3832 for (; fragP; fragP = fragP->fr_next)
3834 if (fragP == target)
3836 if (fragP->fr_fix != 0)
3838 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3840 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3841 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3843 if (fragP->fr_type == rs_space)
3851 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3853 xtensa_isa isa = xtensa_default_isa;
3855 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3860 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3861 && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
3864 for (i = 0; i < num_ops; i++)
3866 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3872 if (target_op == -1)
3875 if (insn->ntok <= target_op)
3878 if (insn->tok[target_op].X_op != O_symbol)
3881 sym = insn->tok[target_op].X_add_symbol;
3885 if (insn->tok[target_op].X_add_number != 0)
3888 target_frag = symbol_get_frag (sym);
3889 if (target_frag == NULL)
3892 if (is_next_frag_target (fragP->fr_next, target_frag)
3893 && S_GET_VALUE (sym) == target_frag->fr_address)
3901 xg_add_branch_and_loop_targets (TInsn *insn)
3903 xtensa_isa isa = xtensa_default_isa;
3904 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3906 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3909 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3910 && insn->tok[i].X_op == O_symbol)
3911 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
3915 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3916 || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3920 for (i = 0; i < insn->ntok && i < num_ops; i++)
3922 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3923 && insn->tok[i].X_op == O_symbol)
3925 symbolS *sym = insn->tok[i].X_add_symbol;
3926 symbol_get_tc (sym)->is_branch_target = TRUE;
3927 if (S_IS_DEFINED (sym))
3928 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
3935 /* Return FALSE if no error. */
3938 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3943 switch (instr_spec->typ)
3946 new_insn->insn_type = ITYPE_INSN;
3947 new_insn->opcode = instr_spec->opcode;
3949 case INSTR_LITERAL_DEF:
3950 new_insn->insn_type = ITYPE_LITERAL;
3951 new_insn->opcode = XTENSA_UNDEFINED;
3953 case INSTR_LABEL_DEF:
3956 new_insn->is_specific_opcode = FALSE;
3957 new_insn->debug_line = old_insn->debug_line;
3958 new_insn->loc_directive_seen = old_insn->loc_directive_seen;
3960 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3963 const expressionS *src_exp;
3969 /* The expression must be the constant. */
3970 gas_assert (b_op->op_num < MAX_INSN_ARGS);
3971 exp = &new_insn->tok[b_op->op_num];
3972 set_expr_const (exp, b_op->op_data);
3976 gas_assert (b_op->op_num < MAX_INSN_ARGS);
3977 gas_assert (b_op->op_data < (unsigned) old_insn->ntok);
3978 src_exp = &old_insn->tok[b_op->op_data];
3979 exp = &new_insn->tok[b_op->op_num];
3980 copy_expr (exp, src_exp);
3985 as_bad (_("can't handle generation of literal/labels yet"));
3989 as_bad (_("can't handle undefined OP TYPE"));
3994 new_insn->ntok = num_ops;
3999 /* Return TRUE if it was simplified. */
4002 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
4004 TransitionRule *rule;
4005 BuildInstr *insn_spec;
4007 if (old_insn->is_specific_opcode || !density_supported)
4010 rule = xg_instruction_match (old_insn);
4014 insn_spec = rule->to_instr;
4015 /* There should only be one. */
4016 gas_assert (insn_spec != NULL);
4017 gas_assert (insn_spec->next == NULL);
4018 if (insn_spec->next != NULL)
4021 xg_build_token_insn (insn_spec, old_insn, new_insn);
4027 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4028 l32i.n. (2) Check the number of operands. (3) Place the instruction
4029 tokens into the stack or relax it and place multiple
4030 instructions/literals onto the stack. Return FALSE if no error. */
4033 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
4037 bfd_boolean do_expand;
4039 tinsn_init (&new_insn);
4041 /* Narrow it if we can. xg_simplify_insn now does all the
4042 appropriate checking (e.g., for the density option). */
4043 if (xg_simplify_insn (orig_insn, &new_insn))
4044 orig_insn = &new_insn;
4046 noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4048 if (orig_insn->ntok < noperands)
4050 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4051 "found %d operands for '%s': Expected %d",
4054 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4058 if (orig_insn->ntok > noperands)
4059 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4060 "found %d operands for '%s': Expected %d",
4063 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4066 /* If there are not enough operands, we will assert above. If there
4067 are too many, just cut out the extras here. */
4068 orig_insn->ntok = noperands;
4070 if (tinsn_has_invalid_symbolic_operands (orig_insn))
4073 /* Special case for extui opcode which has constraints not handled
4074 by the ordinary operand encoding checks. The number of operands
4075 and related syntax issues have already been checked. */
4076 if (orig_insn->opcode == xtensa_extui_opcode)
4078 int shiftimm = orig_insn->tok[2].X_add_number;
4079 int maskimm = orig_insn->tok[3].X_add_number;
4080 if (shiftimm + maskimm > 32)
4082 as_bad (_("immediate operands sum to greater than 32"));
4087 /* If the instruction will definitely need to be relaxed, it is better
4088 to expand it now for better scheduling. Decide whether to expand
4090 do_expand = (!orig_insn->is_specific_opcode && use_transform ());
4092 /* Calls should be expanded to longcalls only in the backend relaxation
4093 so that the assembly scheduler will keep the L32R/CALLX instructions
4095 if (is_direct_call_opcode (orig_insn->opcode))
4098 if (tinsn_has_symbolic_operands (orig_insn))
4100 /* The values of symbolic operands are not known yet, so only expand
4101 now if an operand is "complex" (e.g., difference of symbols) and
4102 will have to be stored as a literal regardless of the value. */
4103 if (!tinsn_has_complex_operands (orig_insn))
4106 else if (xg_immeds_fit (orig_insn))
4110 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4112 istack_push (istack, orig_insn);
4118 /* Return TRUE if the section flags are marked linkonce
4119 or the name is .gnu.linkonce.*. */
4121 static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
4124 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4126 flagword flags, link_once_flags;
4128 flags = bfd_get_section_flags (abfd, sec);
4129 link_once_flags = (flags & SEC_LINK_ONCE);
4131 /* Flags might not be set yet. */
4132 if (!link_once_flags
4133 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
4134 link_once_flags = SEC_LINK_ONCE;
4136 return (link_once_flags != 0);
4141 xtensa_add_literal_sym (symbolS *sym)
4145 l = XNEW (sym_list);
4147 l->next = literal_syms;
4153 xtensa_create_literal_symbol (segT sec, fragS *frag)
4155 static int lit_num = 0;
4156 static char name[256];
4159 sprintf (name, ".L_lit_sym%d", lit_num);
4161 /* Create a local symbol. If it is in a linkonce section, we have to
4162 be careful to make sure that if it is used in a relocation that the
4163 symbol will be in the output file. */
4164 if (get_is_linkonce_section (stdoutput, sec))
4166 symbolP = symbol_new (name, sec, 0, frag);
4167 S_CLEAR_EXTERNAL (symbolP);
4168 /* symbolP->local = 1; */
4171 symbolP = symbol_new (name, sec, 0, frag);
4173 xtensa_add_literal_sym (symbolP);
4180 /* Currently all literals that are generated here are 32-bit L32R targets. */
4183 xg_assemble_literal (/* const */ TInsn *insn)
4186 symbolS *lit_sym = NULL;
4187 bfd_reloc_code_real_type reloc;
4188 bfd_boolean pcrel = FALSE;
4191 /* size = 4 for L32R. It could easily be larger when we move to
4192 larger constants. Add a parameter later. */
4193 offsetT litsize = 4;
4194 offsetT litalign = 2; /* 2^2 = 4 */
4195 expressionS saved_loc;
4196 expressionS * emit_val;
4198 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4200 gas_assert (insn->insn_type == ITYPE_LITERAL);
4201 gas_assert (insn->ntok == 1); /* must be only one token here */
4203 xtensa_switch_to_literal_fragment (&state);
4205 emit_val = &insn->tok[0];
4206 if (emit_val->X_op == O_big)
4208 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4211 /* This happens when someone writes a "movi a2, big_number". */
4212 as_bad_where (frag_now->fr_file, frag_now->fr_line,
4213 _("invalid immediate"));
4214 xtensa_restore_emit_state (&state);
4219 /* Force a 4-byte align here. Note that this opens a new frag, so all
4220 literals done with this function have a frag to themselves. That's
4221 important for the way text section literals work. */
4222 frag_align (litalign, 0, 0);
4223 record_alignment (now_seg, litalign);
4225 switch (emit_val->X_op)
4235 p = frag_more (litsize);
4236 xtensa_set_frag_assembly_state (frag_now);
4237 reloc = map_operator_to_reloc (emit_val->X_op, TRUE);
4238 if (emit_val->X_add_symbol)
4239 emit_val->X_op = O_symbol;
4241 emit_val->X_op = O_constant;
4242 fix_new_exp (frag_now, p - frag_now->fr_literal,
4243 litsize, emit_val, pcrel, reloc);
4247 emit_expr (emit_val, litsize);
4251 gas_assert (frag_now->tc_frag_data.literal_frag == NULL);
4252 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4253 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4254 lit_sym = frag_now->fr_symbol;
4257 xtensa_restore_emit_state (&state);
4263 xg_assemble_literal_space (/* const */ int size, int slot)
4266 /* We might have to do something about this alignment. It only
4267 takes effect if something is placed here. */
4268 offsetT litalign = 2; /* 2^2 = 4 */
4269 fragS *lit_saved_frag;
4271 gas_assert (size % 4 == 0);
4273 xtensa_switch_to_literal_fragment (&state);
4275 /* Force a 4-byte align here. */
4276 frag_align (litalign, 0, 0);
4277 record_alignment (now_seg, litalign);
4281 lit_saved_frag = frag_now;
4282 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4283 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4284 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
4287 xtensa_restore_emit_state (&state);
4288 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4292 /* Put in a fixup record based on the opcode.
4293 Return TRUE on success. */
4296 xg_add_opcode_fix (TInsn *tinsn,
4304 xtensa_opcode opcode = tinsn->opcode;
4305 bfd_reloc_code_real_type reloc;
4306 reloc_howto_type *howto;
4310 reloc = BFD_RELOC_NONE;
4312 /* First try the special cases for "alternate" relocs. */
4313 if (opcode == xtensa_l32r_opcode)
4315 if (fragP->tc_frag_data.use_absolute_literals)
4316 reloc = encode_alt_reloc (slot);
4318 else if (opcode == xtensa_const16_opcode)
4320 if (exp->X_op == O_lo16)
4322 reloc = encode_reloc (slot);
4323 exp->X_op = O_symbol;
4325 else if (exp->X_op == O_hi16)
4327 reloc = encode_alt_reloc (slot);
4328 exp->X_op = O_symbol;
4332 if (opnum != get_relaxable_immed (opcode))
4334 as_bad (_("invalid relocation for operand %i of '%s'"),
4335 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4339 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4340 into the symbol table where the generic portions of the assembler
4341 won't know what to do with them. */
4342 if (exp->X_op == O_lo16 || exp->X_op == O_hi16)
4344 as_bad (_("invalid expression for operand %i of '%s'"),
4345 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4349 /* Next try the generic relocs. */
4350 if (reloc == BFD_RELOC_NONE)
4351 reloc = encode_reloc (slot);
4352 if (reloc == BFD_RELOC_NONE)
4354 as_bad (_("invalid relocation in instruction slot %i"), slot);
4358 howto = bfd_reloc_type_lookup (stdoutput, reloc);
4361 as_bad (_("undefined symbol for opcode \"%s\""),
4362 xtensa_opcode_name (xtensa_default_isa, opcode));
4366 fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4367 the_fix = fix_new_exp (fragP, offset, fmt_length, exp,
4368 howto->pc_relative, reloc);
4369 the_fix->fx_no_overflow = 1;
4370 the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol;
4371 the_fix->tc_fix_data.X_add_number = exp->X_add_number;
4372 the_fix->tc_fix_data.slot = slot;
4379 xg_emit_insn_to_buf (TInsn *tinsn,
4383 bfd_boolean build_fix)
4385 static xtensa_insnbuf insnbuf = NULL;
4386 bfd_boolean has_symbolic_immed = FALSE;
4387 bfd_boolean ok = TRUE;
4390 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4392 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4393 if (has_symbolic_immed && build_fix)
4396 xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4397 int slot = xg_get_single_slot (tinsn->opcode);
4398 int opnum = get_relaxable_immed (tinsn->opcode);
4399 expressionS *exp = &tinsn->tok[opnum];
4401 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
4404 fragP->tc_frag_data.is_insn = TRUE;
4405 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4406 (unsigned char *) buf, 0);
4412 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4414 symbolS *sym = get_special_literal_symbol ();
4418 gas_assert (insn->insn_type == ITYPE_INSN);
4419 for (i = 0; i < insn->ntok; i++)
4420 if (insn->tok[i].X_add_symbol == sym)
4421 insn->tok[i].X_add_symbol = lit_sym;
4427 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4429 symbolS *sym = get_special_label_symbol ();
4431 for (i = 0; i < insn->ntok; i++)
4432 if (insn->tok[i].X_add_symbol == sym)
4433 insn->tok[i].X_add_symbol = label_sym;
4438 /* Return TRUE if the instruction can write to the specified
4439 integer register. */
4442 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4446 xtensa_isa isa = xtensa_default_isa;
4448 num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4450 for (i = 0; i < num_ops; i++)
4453 inout = xtensa_operand_inout (isa, insn->opcode, i);
4454 if ((inout == 'o' || inout == 'm')
4455 && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4457 xtensa_regfile opnd_rf =
4458 xtensa_operand_regfile (isa, insn->opcode, i);
4459 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4461 if ((insn->tok[i].X_op == O_register)
4462 && (insn->tok[i].X_add_number == regnum))
4472 is_bad_loopend_opcode (const TInsn *tinsn)
4474 xtensa_opcode opcode = tinsn->opcode;
4476 if (opcode == XTENSA_UNDEFINED)
4479 if (opcode == xtensa_call0_opcode
4480 || opcode == xtensa_callx0_opcode
4481 || opcode == xtensa_call4_opcode
4482 || opcode == xtensa_callx4_opcode
4483 || opcode == xtensa_call8_opcode
4484 || opcode == xtensa_callx8_opcode
4485 || opcode == xtensa_call12_opcode
4486 || opcode == xtensa_callx12_opcode
4487 || opcode == xtensa_isync_opcode
4488 || opcode == xtensa_ret_opcode
4489 || opcode == xtensa_ret_n_opcode
4490 || opcode == xtensa_retw_opcode
4491 || opcode == xtensa_retw_n_opcode
4492 || opcode == xtensa_waiti_opcode
4493 || opcode == xtensa_rsr_lcount_opcode)
4500 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4501 This allows the debugger to add unaligned labels.
4502 Also, the assembler generates stabs labels that need
4503 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4506 is_unaligned_label (symbolS *sym)
4508 const char *name = S_GET_NAME (sym);
4509 static size_t fake_size = 0;
4513 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4516 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4518 fake_size = strlen (FAKE_LABEL_NAME);
4521 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4522 && (name[fake_size] == 'F'
4523 || name[fake_size] == 'L'
4524 || (name[fake_size] == 'e'
4525 && strncmp ("endfunc", name+fake_size, 7) == 0)))
4533 next_non_empty_frag (const fragS *fragP)
4535 fragS *next_fragP = fragP->fr_next;
4537 /* Sometimes an empty will end up here due storage allocation issues.
4538 So we have to skip until we find something legit. */
4539 while (next_fragP && next_fragP->fr_fix == 0)
4540 next_fragP = next_fragP->fr_next;
4542 if (next_fragP == NULL || next_fragP->fr_fix == 0)
4550 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4552 xtensa_opcode out_opcode;
4553 const fragS *next_fragP = next_non_empty_frag (fragP);
4555 if (next_fragP == NULL)
4558 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4559 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4561 *opcode = out_opcode;
4569 frag_format_size (const fragS *fragP)
4571 static xtensa_insnbuf insnbuf = NULL;
4572 xtensa_isa isa = xtensa_default_isa;
4577 insnbuf = xtensa_insnbuf_alloc (isa);
4580 return XTENSA_UNDEFINED;
4582 xtensa_insnbuf_from_chars (isa, insnbuf,
4583 (unsigned char *) fragP->fr_literal, 0);
4585 fmt = xtensa_format_decode (isa, insnbuf);
4586 if (fmt == XTENSA_UNDEFINED)
4587 return XTENSA_UNDEFINED;
4588 fmt_size = xtensa_format_length (isa, fmt);
4590 /* If the next format won't be changing due to relaxation, just
4591 return the length of the first format. */
4592 if (fragP->fr_opcode != fragP->fr_literal)
4595 /* If during relaxation we have to pull an instruction out of a
4596 multi-slot instruction, we will return the more conservative
4597 number. This works because alignment on bigger instructions
4598 is more restrictive than alignment on smaller instructions.
4599 This is more conservative than we would like, but it happens
4602 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4605 /* If we aren't doing one of our own relaxations or it isn't
4606 slot-based, then the insn size won't change. */
4607 if (fragP->fr_type != rs_machine_dependent)
4609 if (fragP->fr_subtype != RELAX_SLOTS)
4612 /* If an instruction is about to grow, return the longer size. */
4613 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4614 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4615 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
4617 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4618 instruction in the relaxed version is of length 3. (The case
4619 where we have to pull the instruction out of a FLIX bundle
4620 is handled conservatively above.) However, frags with opcodes
4621 that are expanding to wide branches end up having formats that
4622 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4623 we can't tell directly what format the relaxer picked. This
4624 is a wart in the design of the relaxer that should someday be
4625 fixed, but would require major changes, or at least should
4626 be accompanied by major changes to make use of that data.
4628 In any event, we can tell that we are expanding from a single-slot
4629 format to a wider one with the logic below. */
4632 int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0];
4634 for (i = 0; i < xtensa_isa_num_formats (isa); i++)
4636 if (relaxed_size == xtensa_format_length (isa, i))
4637 return relaxed_size;
4643 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4644 return 2 + fragP->tc_frag_data.text_expansion[0];
4651 next_frag_format_size (const fragS *fragP)
4653 const fragS *next_fragP = next_non_empty_frag (fragP);
4654 return frag_format_size (next_fragP);
4658 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4659 required two-byte instructions to be treated as three-byte instructions
4660 for loop instruction alignment. This restriction was removed beginning
4661 with Xtensa LX. Now the only requirement on loop instruction alignment
4662 is that the first instruction of the loop must appear at an address that
4663 does not cross a fetch boundary. */
4666 get_loop_align_size (int insn_size)
4668 if (insn_size == XTENSA_UNDEFINED)
4669 return xtensa_fetch_width;
4671 if (enforce_three_byte_loop_align && insn_size == 2)
4678 /* If the next legit fragment is an end-of-loop marker,
4679 switch its state so it will instantiate a NOP. */
4682 update_next_frag_state (fragS *fragP)
4684 fragS *next_fragP = fragP->fr_next;
4685 fragS *new_target = NULL;
4689 /* We are guaranteed there will be one of these... */
4690 while (!(next_fragP->fr_type == rs_machine_dependent
4691 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4692 || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4693 next_fragP = next_fragP->fr_next;
4695 gas_assert (next_fragP->fr_type == rs_machine_dependent
4696 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4697 || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4699 /* ...and one of these. */
4700 new_target = next_fragP->fr_next;
4701 while (!(new_target->fr_type == rs_machine_dependent
4702 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4703 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4704 new_target = new_target->fr_next;
4706 gas_assert (new_target->fr_type == rs_machine_dependent
4707 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4708 || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4711 while (next_fragP && next_fragP->fr_fix == 0)
4713 if (next_fragP->fr_type == rs_machine_dependent
4714 && next_fragP->fr_subtype == RELAX_LOOP_END)
4716 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4720 next_fragP = next_fragP->fr_next;
4726 next_frag_is_branch_target (const fragS *fragP)
4728 /* Sometimes an empty will end up here due to storage allocation issues,
4729 so we have to skip until we find something legit. */
4730 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4732 if (fragP->tc_frag_data.is_branch_target)
4734 if (fragP->fr_fix != 0)
4742 next_frag_is_loop_target (const fragS *fragP)
4744 /* Sometimes an empty will end up here due storage allocation issues.
4745 So we have to skip until we find something legit. */
4746 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4748 if (fragP->tc_frag_data.is_loop_target)
4750 if (fragP->fr_fix != 0)
4757 /* As specified in the relaxation table, when a loop instruction is
4758 relaxed, there are 24 bytes between the loop instruction itself and
4759 the first instruction in the loop. */
4761 #define RELAXED_LOOP_INSN_BYTES 24
4764 next_frag_pre_opcode_bytes (const fragS *fragp)
4766 const fragS *next_fragp = fragp->fr_next;
4767 xtensa_opcode next_opcode;
4769 if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4772 /* Sometimes an empty will end up here due to storage allocation issues,
4773 so we have to skip until we find something legit. */
4774 while (next_fragp->fr_fix == 0)
4775 next_fragp = next_fragp->fr_next;
4777 if (next_fragp->fr_type != rs_machine_dependent)
4780 /* There is some implicit knowledge encoded in here.
4781 The LOOP instructions that are NOT RELAX_IMMED have
4782 been relaxed. Note that we can assume that the LOOP
4783 instruction is in slot 0 because loops aren't bundleable. */
4784 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4785 return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES;
4791 /* Mark a location where we can later insert literal frags. Update
4792 the section's literal_pool_loc, so subsequent literals can be
4793 placed nearest to their use. */
4796 xtensa_mark_literal_pool_location (void)
4798 /* Any labels pointing to the current location need
4799 to be adjusted to after the literal pool. */
4801 fragS *pool_location;
4803 if (use_literal_section)
4806 /* We stash info in these frags so we can later move the literal's
4807 fixes into this frchain's fix list. */
4808 pool_location = frag_now;
4809 frag_now->tc_frag_data.lit_frchain = frchain_now;
4810 frag_now->tc_frag_data.literal_frag = frag_now;
4811 /* Just record this frag. */
4812 xtensa_maybe_create_literal_pool_frag (FALSE, FALSE);
4813 frag_variant (rs_machine_dependent, 0, 0,
4814 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4815 xtensa_set_frag_assembly_state (frag_now);
4816 frag_now->tc_frag_data.lit_seg = now_seg;
4817 frag_variant (rs_machine_dependent, 0, 0,
4818 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4819 xtensa_set_frag_assembly_state (frag_now);
4821 /* Now put a frag into the literal pool that points to this location. */
4822 set_literal_pool_location (now_seg, pool_location);
4823 xtensa_switch_to_non_abs_literal_fragment (&s);
4824 frag_align (2, 0, 0);
4825 record_alignment (now_seg, 2);
4827 /* Close whatever frag is there. */
4828 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4829 xtensa_set_frag_assembly_state (frag_now);
4830 frag_now->tc_frag_data.literal_frag = pool_location;
4831 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
4832 xtensa_restore_emit_state (&s);
4833 xtensa_set_frag_assembly_state (frag_now);
4837 /* Build a nop of the correct size into tinsn. */
4840 build_nop (TInsn *tinsn, int size)
4846 tinsn->opcode = xtensa_nop_n_opcode;
4848 if (tinsn->opcode == XTENSA_UNDEFINED)
4849 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4853 if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4855 tinsn->opcode = xtensa_or_opcode;
4856 set_expr_const (&tinsn->tok[0], 1);
4857 set_expr_const (&tinsn->tok[1], 1);
4858 set_expr_const (&tinsn->tok[2], 1);
4862 tinsn->opcode = xtensa_nop_opcode;
4864 gas_assert (tinsn->opcode != XTENSA_UNDEFINED);
4869 /* Assemble a NOP of the requested size in the buffer. User must have
4870 allocated "buf" with at least "size" bytes. */
4873 assemble_nop (int size, char *buf)
4875 static xtensa_insnbuf insnbuf = NULL;
4878 build_nop (&tinsn, size);
4881 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4883 tinsn_to_insnbuf (&tinsn, insnbuf);
4884 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4885 (unsigned char *) buf, 0);
4889 /* Return the number of bytes for the offset of the expanded loop
4890 instruction. This should be incorporated into the relaxation
4891 specification but is hard-coded here. This is used to auto-align
4892 the loop instruction. It is invalid to call this function if the
4893 configuration does not have loops or if the opcode is not a loop
4897 get_expanded_loop_offset (xtensa_opcode opcode)
4899 /* This is the OFFSET of the loop instruction in the expanded loop.
4900 This MUST correspond directly to the specification of the loop
4901 expansion. It will be validated on fragment conversion. */
4902 gas_assert (opcode != XTENSA_UNDEFINED);
4903 if (opcode == xtensa_loop_opcode)
4905 if (opcode == xtensa_loopnez_opcode)
4907 if (opcode == xtensa_loopgtz_opcode)
4909 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4915 get_literal_pool_location (segT seg)
4917 struct litpool_seg *lps = litpool_seg_list.next;
4918 struct litpool_frag *lpf;
4919 for ( ; lps && lps->seg->id != seg->id; lps = lps->next)
4923 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4924 { /* Skip "candidates" for now. */
4925 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
4929 /* Must convert a lower-priority pool. */
4930 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4932 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN)
4935 /* Still no match -- try for a low priority pool. */
4936 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4938 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
4942 return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4947 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4949 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4953 /* Set frag assembly state should be called when a new frag is
4954 opened and after a frag has been closed. */
4957 xtensa_set_frag_assembly_state (fragS *fragP)
4959 if (!density_supported)
4960 fragP->tc_frag_data.is_no_density = TRUE;
4962 /* This function is called from subsegs_finish, which is called
4963 after xtensa_end, so we can't use "use_transform" or
4964 "use_schedule" here. */
4965 if (!directive_state[directive_transform])
4966 fragP->tc_frag_data.is_no_transform = TRUE;
4967 if (directive_state[directive_longcalls])
4968 fragP->tc_frag_data.use_longcalls = TRUE;
4969 fragP->tc_frag_data.use_absolute_literals =
4970 directive_state[directive_absolute_literals];
4971 fragP->tc_frag_data.is_assembly_state_set = TRUE;
4976 relaxable_section (asection *sec)
4978 return ((sec->flags & SEC_DEBUGGING) == 0
4979 && strcmp (sec->name, ".eh_frame") != 0);
4984 xtensa_mark_frags_for_org (void)
4988 /* Walk over each fragment of all of the current segments. If we find
4989 a .org frag in any of the segments, mark all frags prior to it as
4990 "no transform", which will prevent linker optimizations from messing
4991 up the .org distance. This should be done after
4992 xtensa_find_unmarked_state_frags, because we don't want to worry here
4993 about that function trashing the data we save here. */
4995 for (seclist = &stdoutput->sections;
4996 seclist && *seclist;
4997 seclist = &(*seclist)->next)
4999 segT sec = *seclist;
5000 segment_info_type *seginfo;
5003 flags = bfd_get_section_flags (stdoutput, sec);
5004 if (flags & SEC_DEBUGGING)
5006 if (!(flags & SEC_ALLOC))
5009 seginfo = seg_info (sec);
5010 if (seginfo && seginfo->frchainP)
5012 fragS *last_fragP = seginfo->frchainP->frch_root;
5013 for (fragP = seginfo->frchainP->frch_root; fragP;
5014 fragP = fragP->fr_next)
5016 /* cvt_frag_to_fill has changed the fr_type of org frags to
5017 rs_fill, so use the value as cached in rs_subtype here. */
5018 if (fragP->fr_subtype == RELAX_ORG)
5020 while (last_fragP != fragP->fr_next)
5022 last_fragP->tc_frag_data.is_no_transform = TRUE;
5023 last_fragP = last_fragP->fr_next;
5033 xtensa_find_unmarked_state_frags (void)
5037 /* Walk over each fragment of all of the current segments. For each
5038 unmarked fragment, mark it with the same info as the previous
5040 for (seclist = &stdoutput->sections;
5041 seclist && *seclist;
5042 seclist = &(*seclist)->next)
5044 segT sec = *seclist;
5045 segment_info_type *seginfo;
5048 flags = bfd_get_section_flags (stdoutput, sec);
5049 if (flags & SEC_DEBUGGING)
5051 if (!(flags & SEC_ALLOC))
5054 seginfo = seg_info (sec);
5055 if (seginfo && seginfo->frchainP)
5057 fragS *last_fragP = 0;
5058 for (fragP = seginfo->frchainP->frch_root; fragP;
5059 fragP = fragP->fr_next)
5061 if (fragP->fr_fix != 0
5062 && !fragP->tc_frag_data.is_assembly_state_set)
5064 if (last_fragP == 0)
5066 as_warn_where (fragP->fr_file, fragP->fr_line,
5067 _("assembly state not set for first frag in section %s"),
5072 fragP->tc_frag_data.is_assembly_state_set = TRUE;
5073 fragP->tc_frag_data.is_no_density =
5074 last_fragP->tc_frag_data.is_no_density;
5075 fragP->tc_frag_data.is_no_transform =
5076 last_fragP->tc_frag_data.is_no_transform;
5077 fragP->tc_frag_data.use_longcalls =
5078 last_fragP->tc_frag_data.use_longcalls;
5079 fragP->tc_frag_data.use_absolute_literals =
5080 last_fragP->tc_frag_data.use_absolute_literals;
5083 if (fragP->tc_frag_data.is_assembly_state_set)
5092 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
5094 void *unused ATTRIBUTE_UNUSED)
5096 flagword flags = bfd_get_section_flags (abfd, sec);
5097 segment_info_type *seginfo = seg_info (sec);
5098 fragS *frag = seginfo->frchainP->frch_root;
5100 if (flags & SEC_CODE)
5102 xtensa_isa isa = xtensa_default_isa;
5103 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5104 while (frag != NULL)
5106 if (frag->tc_frag_data.is_branch_target)
5109 addressT branch_align, frag_addr;
5112 xtensa_insnbuf_from_chars
5113 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5114 fmt = xtensa_format_decode (isa, insnbuf);
5115 op_size = xtensa_format_length (isa, fmt);
5116 branch_align = 1 << branch_align_power (sec);
5117 frag_addr = frag->fr_address % branch_align;
5118 if (frag_addr + op_size > branch_align)
5119 as_warn_where (frag->fr_file, frag->fr_line,
5120 _("unaligned branch target: %d bytes at 0x%lx"),
5121 op_size, (long) frag->fr_address);
5123 frag = frag->fr_next;
5125 xtensa_insnbuf_free (isa, insnbuf);
5131 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
5133 void *unused ATTRIBUTE_UNUSED)
5135 flagword flags = bfd_get_section_flags (abfd, sec);
5136 segment_info_type *seginfo = seg_info (sec);
5137 fragS *frag = seginfo->frchainP->frch_root;
5138 xtensa_isa isa = xtensa_default_isa;
5140 if (flags & SEC_CODE)
5142 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5143 while (frag != NULL)
5145 if (frag->tc_frag_data.is_first_loop_insn)
5151 if (frag->fr_fix == 0)
5152 frag = next_non_empty_frag (frag);
5156 xtensa_insnbuf_from_chars
5157 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5158 fmt = xtensa_format_decode (isa, insnbuf);
5159 op_size = xtensa_format_length (isa, fmt);
5160 frag_addr = frag->fr_address % xtensa_fetch_width;
5162 if (frag_addr + op_size > xtensa_fetch_width)
5163 as_warn_where (frag->fr_file, frag->fr_line,
5164 _("unaligned loop: %d bytes at 0x%lx"),
5165 op_size, (long) frag->fr_address);
5168 frag = frag->fr_next;
5170 xtensa_insnbuf_free (isa, insnbuf);
5176 xg_apply_fix_value (fixS *fixP, valueT val)
5178 xtensa_isa isa = xtensa_default_isa;
5179 static xtensa_insnbuf insnbuf = NULL;
5180 static xtensa_insnbuf slotbuf = NULL;
5183 bfd_boolean alt_reloc;
5184 xtensa_opcode opcode;
5185 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5187 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc)
5189 as_fatal (_("unexpected fix"));
5193 insnbuf = xtensa_insnbuf_alloc (isa);
5194 slotbuf = xtensa_insnbuf_alloc (isa);
5197 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5198 fmt = xtensa_format_decode (isa, insnbuf);
5199 if (fmt == XTENSA_UNDEFINED)
5200 as_fatal (_("undecodable fix"));
5201 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5202 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5203 if (opcode == XTENSA_UNDEFINED)
5204 as_fatal (_("undecodable fix"));
5206 /* CONST16 immediates are not PC-relative, despite the fact that we
5207 reuse the normal PC-relative operand relocations for the low part
5208 of a CONST16 operand. */
5209 if (opcode == xtensa_const16_opcode)
5212 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5213 get_relaxable_immed (opcode), val,
5214 fixP->fx_file, fixP->fx_line);
5216 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5217 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5223 /* External Functions and Other GAS Hooks. */
5226 xtensa_target_format (void)
5228 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5233 xtensa_file_arch_init (bfd *abfd)
5235 bfd_set_private_flags (abfd, 0x100 | 0x200);
5240 md_number_to_chars (char *buf, valueT val, int n)
5242 if (target_big_endian)
5243 number_to_chars_bigendian (buf, val, n);
5245 number_to_chars_littleendian (buf, val, n);
5249 xg_init_global_config (void)
5251 target_big_endian = XCHAL_HAVE_BE;
5253 density_supported = XCHAL_HAVE_DENSITY;
5254 absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
5255 xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
5257 directive_state[directive_density] = XCHAL_HAVE_DENSITY;
5258 directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS;
5262 xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED)
5264 xg_init_global_config ();
5267 /* This function is called once, at assembler startup time. It should
5268 set up all the tables, etc. that the MD part of the assembler will
5274 segT current_section = now_seg;
5275 int current_subsec = now_subseg;
5279 xtensa_default_isa = xtensa_isa_init (0, 0);
5280 isa = xtensa_default_isa;
5284 /* Set up the literal sections. */
5285 memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5287 subseg_set (current_section, current_subsec);
5289 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5290 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5291 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5292 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5293 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5294 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5295 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5296 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5297 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5298 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5299 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5300 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5301 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
5302 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5303 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5304 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5305 xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
5306 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5307 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5308 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5309 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5310 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5311 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5312 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5313 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5314 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5315 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5316 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5317 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5318 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5319 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5321 for (i = 0; i < xtensa_isa_num_formats (isa); i++)
5323 int format_slots = xtensa_format_num_slots (isa, i);
5324 if (format_slots > config_max_slots)
5325 config_max_slots = format_slots;
5328 xg_init_vinsn (&cur_vinsn);
5330 xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa);
5332 init_op_placement_info_table ();
5334 /* Set up the assembly state. */
5335 if (!frag_now->tc_frag_data.is_assembly_state_set)
5336 xtensa_set_frag_assembly_state (frag_now);
5340 /* TC_INIT_FIX_DATA hook */
5343 xtensa_init_fix_data (fixS *x)
5345 x->tc_fix_data.slot = 0;
5346 x->tc_fix_data.X_add_symbol = NULL;
5347 x->tc_fix_data.X_add_number = 0;
5351 /* tc_frob_label hook */
5354 xtensa_frob_label (symbolS *sym)
5358 if (cur_vinsn.inside_bundle)
5360 as_bad (_("labels are not valid inside bundles"));
5364 freq = get_subseg_target_freq (now_seg, now_subseg);
5366 /* Since the label was already attached to a frag associated with the
5367 previous basic block, it now needs to be reset to the current frag. */
5368 symbol_set_frag (sym, frag_now);
5369 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5371 if (generating_literals)
5372 xtensa_add_literal_sym (sym);
5374 xtensa_add_insn_label (sym);
5376 if (symbol_get_tc (sym)->is_loop_target)
5378 if ((get_last_insn_flags (now_seg, now_subseg)
5379 & FLAG_IS_BAD_LOOPEND) != 0)
5380 as_bad (_("invalid last instruction for a zero-overhead loop"));
5382 xtensa_set_frag_assembly_state (frag_now);
5383 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5384 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5386 xtensa_set_frag_assembly_state (frag_now);
5387 xtensa_move_labels (frag_now, 0);
5390 /* No target aligning in the absolute section. */
5391 if (now_seg != absolute_section
5392 && !is_unaligned_label (sym)
5393 && !generating_literals)
5395 xtensa_set_frag_assembly_state (frag_now);
5397 if (do_align_targets ())
5398 frag_var (rs_machine_dependent, 0, (int) freq,
5399 RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol,
5400 frag_now->fr_offset, NULL);
5402 frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
5403 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5404 xtensa_set_frag_assembly_state (frag_now);
5405 xtensa_move_labels (frag_now, 0);
5408 /* We need to mark the following properties even if we aren't aligning. */
5410 /* If the label is already known to be a branch target, i.e., a
5411 forward branch, mark the frag accordingly. Backward branches
5412 are handled by xg_add_branch_and_loop_targets. */
5413 if (symbol_get_tc (sym)->is_branch_target)
5414 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
5416 /* Loops only go forward, so they can be identified here. */
5417 if (symbol_get_tc (sym)->is_loop_target)
5418 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
5420 dwarf2_emit_label (sym);
5424 /* tc_unrecognized_line hook */
5427 xtensa_unrecognized_line (int ch)
5432 if (cur_vinsn.inside_bundle == 0)
5434 /* PR8110: Cannot emit line number info inside a FLIX bundle
5435 when using --gstabs. Temporarily disable debug info. */
5436 generate_lineno_debug ();
5437 if (debug_type == DEBUG_STABS)
5439 xt_saved_debug_type = debug_type;
5440 debug_type = DEBUG_NONE;
5443 cur_vinsn.inside_bundle = 1;
5447 as_bad (_("extra opening brace"));
5453 if (cur_vinsn.inside_bundle)
5454 finish_vinsn (&cur_vinsn);
5457 as_bad (_("extra closing brace"));
5462 as_bad (_("syntax error"));
5469 /* md_flush_pending_output hook */
5472 xtensa_flush_pending_output (void)
5474 /* This line fixes a bug where automatically generated gstabs info
5475 separates a function label from its entry instruction, ending up
5476 with the literal position between the function label and the entry
5477 instruction and crashing code. It only happens with --gstabs and
5478 --text-section-literals, and when several other obscure relaxation
5479 conditions are met. */
5480 if (outputting_stabs_line_debug)
5483 if (cur_vinsn.inside_bundle)
5484 as_bad (_("missing closing brace"));
5486 /* If there is a non-zero instruction fragment, close it. */
5487 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5489 frag_wane (frag_now);
5491 xtensa_set_frag_assembly_state (frag_now);
5493 frag_now->tc_frag_data.is_insn = FALSE;
5495 xtensa_clear_insn_labels ();
5499 /* We had an error while parsing an instruction. The string might look
5500 like this: "insn arg1, arg2 }". If so, we need to see the closing
5501 brace and reset some fields. Otherwise, the vinsn never gets closed
5502 and the num_slots field will grow past the end of the array of slots,
5503 and bad things happen. */
5506 error_reset_cur_vinsn (void)
5508 if (cur_vinsn.inside_bundle)
5510 if (*input_line_pointer == '}'
5511 || *(input_line_pointer - 1) == '}'
5512 || *(input_line_pointer - 2) == '}')
5513 xg_clear_vinsn (&cur_vinsn);
5519 md_assemble (char *str)
5521 xtensa_isa isa = xtensa_default_isa;
5524 bfd_boolean has_underbar = FALSE;
5525 char *arg_strings[MAX_INSN_ARGS];
5527 TInsn orig_insn; /* Original instruction from the input. */
5529 tinsn_init (&orig_insn);
5531 /* Split off the opcode. */
5532 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5533 opname = xstrndup (str, opnamelen);
5535 num_args = tokenize_arguments (arg_strings, str + opnamelen);
5538 as_bad (_("syntax error"));
5542 if (xg_translate_idioms (&opname, &num_args, arg_strings))
5545 /* Check for an underbar prefix. */
5548 has_underbar = TRUE;
5552 orig_insn.insn_type = ITYPE_INSN;
5554 orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5555 orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5557 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5558 extra argument and set the opcode to "CALLXn". */
5559 if (orig_insn.opcode == XTENSA_UNDEFINED
5560 && strncasecmp (opname, "callx", 5) == 0)
5562 unsigned long window_size;
5565 window_size = strtoul (opname + 5, &suffix, 10);
5566 if (suffix != opname + 5
5567 && (window_size == 0
5570 || window_size == 12)
5571 && strcasecmp (suffix, ".tls") == 0)
5573 switch (window_size)
5575 case 0: orig_insn.opcode = xtensa_callx0_opcode; break;
5576 case 4: orig_insn.opcode = xtensa_callx4_opcode; break;
5577 case 8: orig_insn.opcode = xtensa_callx8_opcode; break;
5578 case 12: orig_insn.opcode = xtensa_callx12_opcode; break;
5582 as_bad (_("wrong number of operands for '%s'"), opname);
5585 bfd_reloc_code_real_type reloc;
5586 char *old_input_line_pointer;
5587 expressionS *tok = &orig_insn.extra_arg;
5589 old_input_line_pointer = input_line_pointer;
5590 input_line_pointer = arg_strings[num_args - 1];
5593 if (tok->X_op == O_symbol
5594 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
5595 == BFD_RELOC_XTENSA_TLS_CALL))
5596 tok->X_op = map_suffix_reloc_to_operator (reloc);
5598 as_bad (_("bad relocation expression for '%s'"), opname);
5600 input_line_pointer = old_input_line_pointer;
5606 /* Special case: Check for "j.l" pseudo op. */
5607 if (orig_insn.opcode == XTENSA_UNDEFINED
5608 && strncasecmp (opname, "j.l", 3) == 0)
5611 as_bad (_("wrong number of operands for '%s'"), opname);
5614 char *old_input_line_pointer;
5615 expressionS *tok = &orig_insn.extra_arg;
5617 old_input_line_pointer = input_line_pointer;
5618 input_line_pointer = arg_strings[num_args - 1];
5620 expression_maybe_register (xtensa_jx_opcode, 0, tok);
5621 input_line_pointer = old_input_line_pointer;
5624 orig_insn.opcode = xtensa_j_opcode;
5628 if (orig_insn.opcode == XTENSA_UNDEFINED)
5630 xtensa_format fmt = xtensa_format_lookup (isa, opname);
5631 if (fmt == XTENSA_UNDEFINED)
5633 as_bad (_("unknown opcode or format name '%s'"), opname);
5634 error_reset_cur_vinsn ();
5637 if (!cur_vinsn.inside_bundle)
5639 as_bad (_("format names only valid inside bundles"));
5640 error_reset_cur_vinsn ();
5643 if (cur_vinsn.format != XTENSA_UNDEFINED)
5644 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5646 cur_vinsn.format = fmt;
5647 free (has_underbar ? opname - 1 : opname);
5648 error_reset_cur_vinsn ();
5652 /* Parse the arguments. */
5653 if (parse_arguments (&orig_insn, num_args, arg_strings))
5655 as_bad (_("syntax error"));
5656 error_reset_cur_vinsn ();
5660 /* Free the opcode and argument strings, now that they've been parsed. */
5661 free (has_underbar ? opname - 1 : opname);
5663 while (num_args-- > 0)
5664 free (arg_strings[num_args]);
5666 /* Get expressions for invisible operands. */
5667 if (get_invisible_operands (&orig_insn))
5669 error_reset_cur_vinsn ();
5673 /* Check for the right number and type of arguments. */
5674 if (tinsn_check_arguments (&orig_insn))
5676 error_reset_cur_vinsn ();
5680 /* Record the line number for each TInsn, because a FLIX bundle may be
5681 spread across multiple input lines and individual instructions may be
5682 moved around in some cases. */
5683 orig_insn.loc_directive_seen = dwarf2_loc_directive_seen;
5684 dwarf2_where (&orig_insn.debug_line);
5685 dwarf2_consume_line_info ();
5687 xg_add_branch_and_loop_targets (&orig_insn);
5689 /* Check that immediate value for ENTRY is >= 16. */
5690 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
5692 expressionS *exp = &orig_insn.tok[2];
5693 if (exp->X_op == O_constant && exp->X_add_number < 16)
5694 as_warn (_("entry instruction with stack decrement < 16"));
5698 assemble_tokens (opcode, tok, ntok);
5699 expand the tokens from the orig_insn into the
5700 stack of instructions that will not expand
5701 unless required at relaxation time. */
5703 if (!cur_vinsn.inside_bundle)
5704 emit_single_op (&orig_insn);
5705 else /* We are inside a bundle. */
5707 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5708 cur_vinsn.num_slots++;
5709 if (*input_line_pointer == '}'
5710 || *(input_line_pointer - 1) == '}'
5711 || *(input_line_pointer - 2) == '}')
5712 finish_vinsn (&cur_vinsn);
5715 /* We've just emitted a new instruction so clear the list of labels. */
5716 xtensa_clear_insn_labels ();
5718 xtensa_check_frag_count ();
5722 /* HANDLE_ALIGN hook */
5724 /* For a .align directive, we mark the previous block with the alignment
5725 information. This will be placed in the object file in the
5726 property section corresponding to this section. */
5729 xtensa_handle_align (fragS *fragP)
5732 && ! fragP->tc_frag_data.is_literal
5733 && (fragP->fr_type == rs_align
5734 || fragP->fr_type == rs_align_code)
5735 && fragP->fr_offset > 0
5736 && now_seg != bss_section)
5738 fragP->tc_frag_data.is_align = TRUE;
5739 fragP->tc_frag_data.alignment = fragP->fr_offset;
5742 if (fragP->fr_type == rs_align_test)
5745 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5747 as_bad_where (fragP->fr_file, fragP->fr_line,
5748 _("unaligned entry instruction"));
5751 if (linkrelax && fragP->fr_type == rs_org)
5752 fragP->fr_subtype = RELAX_ORG;
5756 /* TC_FRAG_INIT hook */
5759 xtensa_frag_init (fragS *frag)
5761 xtensa_set_frag_assembly_state (frag);
5766 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5772 /* Round up a section size to the appropriate boundary. */
5775 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5777 return size; /* Byte alignment is fine. */
5782 md_pcrel_from (fixS *fixP)
5785 static xtensa_insnbuf insnbuf = NULL;
5786 static xtensa_insnbuf slotbuf = NULL;
5789 xtensa_opcode opcode;
5792 xtensa_isa isa = xtensa_default_isa;
5793 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5794 bfd_boolean alt_reloc;
5796 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5799 if (fixP->fx_r_type == BFD_RELOC_32_PCREL)
5804 insnbuf = xtensa_insnbuf_alloc (isa);
5805 slotbuf = xtensa_insnbuf_alloc (isa);
5808 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5809 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5810 fmt = xtensa_format_decode (isa, insnbuf);
5812 if (fmt == XTENSA_UNDEFINED)
5813 as_fatal (_("bad instruction format"));
5815 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5816 as_fatal (_("invalid relocation"));
5818 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5819 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5821 /* Check for "alternate" relocations (operand not specified). None
5822 of the current uses for these are really PC-relative. */
5823 if (alt_reloc || opcode == xtensa_const16_opcode)
5825 if (opcode != xtensa_l32r_opcode
5826 && opcode != xtensa_const16_opcode)
5827 as_fatal (_("invalid relocation for '%s' instruction"),
5828 xtensa_opcode_name (isa, opcode));
5832 opnum = get_relaxable_immed (opcode);
5834 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5835 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5837 as_bad_where (fixP->fx_file,
5839 _("invalid relocation for operand %d of '%s'"),
5840 opnum, xtensa_opcode_name (isa, opcode));
5843 return 0 - opnd_value;
5847 /* TC_FORCE_RELOCATION hook */
5850 xtensa_force_relocation (fixS *fix)
5852 switch (fix->fx_r_type)
5854 case BFD_RELOC_XTENSA_ASM_EXPAND:
5855 case BFD_RELOC_XTENSA_SLOT0_ALT:
5856 case BFD_RELOC_XTENSA_SLOT1_ALT:
5857 case BFD_RELOC_XTENSA_SLOT2_ALT:
5858 case BFD_RELOC_XTENSA_SLOT3_ALT:
5859 case BFD_RELOC_XTENSA_SLOT4_ALT:
5860 case BFD_RELOC_XTENSA_SLOT5_ALT:
5861 case BFD_RELOC_XTENSA_SLOT6_ALT:
5862 case BFD_RELOC_XTENSA_SLOT7_ALT:
5863 case BFD_RELOC_XTENSA_SLOT8_ALT:
5864 case BFD_RELOC_XTENSA_SLOT9_ALT:
5865 case BFD_RELOC_XTENSA_SLOT10_ALT:
5866 case BFD_RELOC_XTENSA_SLOT11_ALT:
5867 case BFD_RELOC_XTENSA_SLOT12_ALT:
5868 case BFD_RELOC_XTENSA_SLOT13_ALT:
5869 case BFD_RELOC_XTENSA_SLOT14_ALT:
5875 if (linkrelax && fix->fx_addsy
5876 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5879 return generic_force_reloc (fix);
5883 /* TC_VALIDATE_FIX_SUB hook */
5886 xtensa_validate_fix_sub (fixS *fix)
5888 segT add_symbol_segment, sub_symbol_segment;
5890 /* The difference of two symbols should be resolved by the assembler when
5891 linkrelax is not set. If the linker may relax the section containing
5892 the symbols, then an Xtensa DIFF relocation must be generated so that
5893 the linker knows to adjust the difference value. */
5894 if (!linkrelax || fix->fx_addsy == NULL)
5897 /* Make sure both symbols are in the same segment, and that segment is
5898 "normal" and relaxable. If the segment is not "normal", then the
5899 fix is not valid. If the segment is not "relaxable", then the fix
5900 should have been handled earlier. */
5901 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5902 if (! SEG_NORMAL (add_symbol_segment) ||
5903 ! relaxable_section (add_symbol_segment))
5905 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5906 return (sub_symbol_segment == add_symbol_segment);
5910 /* NO_PSEUDO_DOT hook */
5912 /* This function has nothing to do with pseudo dots, but this is the
5913 nearest macro to where the check needs to take place. FIXME: This
5917 xtensa_check_inside_bundle (void)
5919 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5920 as_bad (_("directives are not valid inside bundles"));
5922 /* This function must always return FALSE because it is called via a
5923 macro that has nothing to do with bundling. */
5928 /* md_elf_section_change_hook */
5931 xtensa_elf_section_change_hook (void)
5933 /* Set up the assembly state. */
5934 if (!frag_now->tc_frag_data.is_assembly_state_set)
5935 xtensa_set_frag_assembly_state (frag_now);
5939 /* tc_fix_adjustable hook */
5942 xtensa_fix_adjustable (fixS *fixP)
5944 /* We need the symbol name for the VTABLE entries. */
5945 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5946 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5953 /* tc_symbol_new_hook */
5955 symbolS *expr_symbols = NULL;
5958 xtensa_symbol_new_hook (symbolS *sym)
5960 if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
5962 symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5969 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5971 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5974 /* Subtracted symbols are only allowed for a few relocation types, and
5975 unless linkrelax is enabled, they should not make it to this point. */
5976 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5977 || fixP->fx_r_type == BFD_RELOC_16
5978 || fixP->fx_r_type == BFD_RELOC_8)))
5979 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
5981 switch (fixP->fx_r_type)
5983 case BFD_RELOC_32_PCREL:
5989 switch (fixP->fx_r_type)
5992 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
5993 fixP->fx_signed = 0;
5996 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
5997 fixP->fx_signed = 0;
6000 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
6001 fixP->fx_signed = 0;
6007 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6008 - S_GET_VALUE (fixP->fx_subsy));
6010 /* The difference value gets written out, and the DIFF reloc
6011 identifies the address of the subtracted symbol (i.e., the one
6012 with the lowest address). */
6014 fixP->fx_offset -= val;
6015 fixP->fx_subsy = NULL;
6017 else if (! fixP->fx_addsy)
6022 else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)
6024 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
6030 case BFD_RELOC_XTENSA_PLT:
6031 md_number_to_chars (fixpos, val, fixP->fx_size);
6032 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
6035 case BFD_RELOC_XTENSA_TLSDESC_FN:
6036 case BFD_RELOC_XTENSA_TLSDESC_ARG:
6037 case BFD_RELOC_XTENSA_TLS_TPOFF:
6038 case BFD_RELOC_XTENSA_TLS_DTPOFF:
6039 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6040 md_number_to_chars (fixpos, 0, fixP->fx_size);
6041 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */
6044 case BFD_RELOC_XTENSA_SLOT0_OP:
6045 case BFD_RELOC_XTENSA_SLOT1_OP:
6046 case BFD_RELOC_XTENSA_SLOT2_OP:
6047 case BFD_RELOC_XTENSA_SLOT3_OP:
6048 case BFD_RELOC_XTENSA_SLOT4_OP:
6049 case BFD_RELOC_XTENSA_SLOT5_OP:
6050 case BFD_RELOC_XTENSA_SLOT6_OP:
6051 case BFD_RELOC_XTENSA_SLOT7_OP:
6052 case BFD_RELOC_XTENSA_SLOT8_OP:
6053 case BFD_RELOC_XTENSA_SLOT9_OP:
6054 case BFD_RELOC_XTENSA_SLOT10_OP:
6055 case BFD_RELOC_XTENSA_SLOT11_OP:
6056 case BFD_RELOC_XTENSA_SLOT12_OP:
6057 case BFD_RELOC_XTENSA_SLOT13_OP:
6058 case BFD_RELOC_XTENSA_SLOT14_OP:
6061 /* Write the tentative value of a PC-relative relocation to a
6062 local symbol into the instruction. The value will be ignored
6063 by the linker, and it makes the object file disassembly
6064 readable when all branch targets are encoded in relocations. */
6066 gas_assert (fixP->fx_addsy);
6067 if (S_GET_SEGMENT (fixP->fx_addsy) == seg
6068 && !S_FORCE_RELOC (fixP->fx_addsy, 1))
6070 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6071 - md_pcrel_from (fixP));
6072 (void) xg_apply_fix_value (fixP, val);
6075 else if (! fixP->fx_addsy)
6078 if (xg_apply_fix_value (fixP, val))
6083 case BFD_RELOC_XTENSA_ASM_EXPAND:
6084 case BFD_RELOC_XTENSA_TLS_FUNC:
6085 case BFD_RELOC_XTENSA_TLS_ARG:
6086 case BFD_RELOC_XTENSA_TLS_CALL:
6087 case BFD_RELOC_XTENSA_SLOT0_ALT:
6088 case BFD_RELOC_XTENSA_SLOT1_ALT:
6089 case BFD_RELOC_XTENSA_SLOT2_ALT:
6090 case BFD_RELOC_XTENSA_SLOT3_ALT:
6091 case BFD_RELOC_XTENSA_SLOT4_ALT:
6092 case BFD_RELOC_XTENSA_SLOT5_ALT:
6093 case BFD_RELOC_XTENSA_SLOT6_ALT:
6094 case BFD_RELOC_XTENSA_SLOT7_ALT:
6095 case BFD_RELOC_XTENSA_SLOT8_ALT:
6096 case BFD_RELOC_XTENSA_SLOT9_ALT:
6097 case BFD_RELOC_XTENSA_SLOT10_ALT:
6098 case BFD_RELOC_XTENSA_SLOT11_ALT:
6099 case BFD_RELOC_XTENSA_SLOT12_ALT:
6100 case BFD_RELOC_XTENSA_SLOT13_ALT:
6101 case BFD_RELOC_XTENSA_SLOT14_ALT:
6102 /* These all need to be resolved at link-time. Do nothing now. */
6105 case BFD_RELOC_VTABLE_INHERIT:
6106 case BFD_RELOC_VTABLE_ENTRY:
6111 as_bad (_("unhandled local relocation fix %s"),
6112 bfd_get_reloc_code_name (fixP->fx_r_type));
6118 md_atof (int type, char *litP, int *sizeP)
6120 return ieee_md_atof (type, litP, sizeP, target_big_endian);
6125 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
6127 return total_frag_text_expansion (fragP);
6131 /* Translate internal representation of relocation info to BFD target
6135 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
6139 reloc = XNEW (arelent);
6140 reloc->sym_ptr_ptr = XNEW (asymbol *);
6141 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6142 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6144 /* Make sure none of our internal relocations make it this far.
6145 They'd better have been fully resolved by this point. */
6146 gas_assert ((int) fixp->fx_r_type > 0);
6148 reloc->addend = fixp->fx_offset;
6150 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6151 if (reloc->howto == NULL)
6153 as_bad_where (fixp->fx_file, fixp->fx_line,
6154 _("cannot represent `%s' relocation in object file"),
6155 bfd_get_reloc_code_name (fixp->fx_r_type));
6156 free (reloc->sym_ptr_ptr);
6161 if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
6162 as_fatal (_("internal error; cannot generate `%s' relocation"),
6163 bfd_get_reloc_code_name (fixp->fx_r_type));
6169 /* Checks for resource conflicts between instructions. */
6171 /* The func unit stuff could be implemented as bit-vectors rather
6172 than the iterative approach here. If it ends up being too
6173 slow, we will switch it. */
6176 new_resource_table (void *data,
6179 unit_num_copies_func uncf,
6180 opcode_num_units_func onuf,
6181 opcode_funcUnit_use_unit_func ouuf,
6182 opcode_funcUnit_use_stage_func ousf)
6185 resource_table *rt = XNEW (resource_table);
6187 rt->cycles = cycles;
6188 rt->allocated_cycles = cycles;
6190 rt->unit_num_copies = uncf;
6191 rt->opcode_num_units = onuf;
6192 rt->opcode_unit_use = ouuf;
6193 rt->opcode_unit_stage = ousf;
6195 rt->units = XCNEWVEC (unsigned char *, cycles);
6196 for (i = 0; i < cycles; i++)
6197 rt->units[i] = XCNEWVEC (unsigned char, nu);
6204 clear_resource_table (resource_table *rt)
6207 for (i = 0; i < rt->allocated_cycles; i++)
6208 for (j = 0; j < rt->num_units; j++)
6209 rt->units[i][j] = 0;
6213 /* We never shrink it, just fake it into thinking so. */
6216 resize_resource_table (resource_table *rt, int cycles)
6220 rt->cycles = cycles;
6221 if (cycles <= rt->allocated_cycles)
6224 old_cycles = rt->allocated_cycles;
6225 rt->allocated_cycles = cycles;
6227 rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles);
6228 for (i = 0; i < old_cycles; i++)
6229 rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units);
6230 for (i = old_cycles; i < cycles; i++)
6231 rt->units[i] = XCNEWVEC (unsigned char, rt->num_units);
6236 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6239 int uses = (rt->opcode_num_units) (rt->data, opcode);
6241 for (i = 0; i < uses; i++)
6243 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6244 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6245 int copies_in_use = rt->units[stage + cycle][unit];
6246 int copies = (rt->unit_num_copies) (rt->data, unit);
6247 if (copies_in_use >= copies)
6255 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6258 int uses = (rt->opcode_num_units) (rt->data, opcode);
6260 for (i = 0; i < uses; i++)
6262 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6263 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6264 /* Note that this allows resources to be oversubscribed. That's
6265 essential to the way the optional scheduler works.
6266 resources_available reports when a resource is over-subscribed,
6267 so it's easy to tell. */
6268 rt->units[stage + cycle][unit]++;
6274 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6277 int uses = (rt->opcode_num_units) (rt->data, opcode);
6279 for (i = 0; i < uses; i++)
6281 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6282 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6283 gas_assert (rt->units[stage + cycle][unit] > 0);
6284 rt->units[stage + cycle][unit]--;
6289 /* Wrapper functions make parameterized resource reservation
6293 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6295 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6301 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6303 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6308 /* Note that this function does not check issue constraints, but
6309 solely whether the hardware is available to execute the given
6310 instructions together. It also doesn't check if the tinsns
6311 write the same state, or access the same tieports. That is
6312 checked by check_t1_t2_reads_and_writes. */
6315 resources_conflict (vliw_insn *vinsn)
6318 static resource_table *rt = NULL;
6320 /* This is the most common case by far. Optimize it. */
6321 if (vinsn->num_slots == 1)
6326 xtensa_isa isa = xtensa_default_isa;
6327 rt = new_resource_table
6328 (isa, xtensa_num_pipe_stages,
6329 xtensa_isa_num_funcUnits (isa),
6330 (unit_num_copies_func) xtensa_funcUnit_num_copies,
6331 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6332 opcode_funcUnit_use_unit,
6333 opcode_funcUnit_use_stage);
6336 clear_resource_table (rt);
6338 for (i = 0; i < vinsn->num_slots; i++)
6340 if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6342 reserve_resources (rt, vinsn->slots[i].opcode, 0);
6349 /* finish_vinsn, emit_single_op and helper functions. */
6351 static bfd_boolean find_vinsn_conflicts (vliw_insn *);
6352 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6353 static void xg_assemble_vliw_tokens (vliw_insn *);
6356 /* We have reached the end of a bundle; emit into the frag. */
6359 finish_vinsn (vliw_insn *vinsn)
6365 if (find_vinsn_conflicts (vinsn))
6367 xg_clear_vinsn (vinsn);
6371 /* First, find a format that works. */
6372 if (vinsn->format == XTENSA_UNDEFINED)
6373 vinsn->format = xg_find_narrowest_format (vinsn);
6375 slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format);
6377 && produce_flix == FLIX_NONE)
6379 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6380 xg_clear_vinsn (vinsn);
6384 if (vinsn->format == XTENSA_UNDEFINED)
6386 as_bad (_("couldn't find a valid instruction format"));
6387 fprintf (stderr, _(" ops were: "));
6388 for (i = 0; i < vinsn->num_slots; i++)
6389 fprintf (stderr, _(" %s;"),
6390 xtensa_opcode_name (xtensa_default_isa,
6391 vinsn->slots[i].opcode));
6392 fprintf (stderr, _("\n"));
6393 xg_clear_vinsn (vinsn);
6397 if (vinsn->num_slots != slots)
6399 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6400 xtensa_format_name (xtensa_default_isa, vinsn->format),
6401 slots, vinsn->num_slots);
6402 xg_clear_vinsn (vinsn);
6406 if (resources_conflict (vinsn))
6408 as_bad (_("illegal resource usage in bundle"));
6409 fprintf (stderr, " ops were: ");
6410 for (i = 0; i < vinsn->num_slots; i++)
6411 fprintf (stderr, " %s;",
6412 xtensa_opcode_name (xtensa_default_isa,
6413 vinsn->slots[i].opcode));
6414 fprintf (stderr, "\n");
6415 xg_clear_vinsn (vinsn);
6419 for (i = 0; i < vinsn->num_slots; i++)
6421 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6423 symbolS *lit_sym = NULL;
6425 bfd_boolean e = FALSE;
6426 bfd_boolean saved_density = density_supported;
6428 /* We don't want to narrow ops inside multi-slot bundles. */
6429 if (vinsn->num_slots > 1)
6430 density_supported = FALSE;
6432 istack_init (&slotstack);
6433 if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6435 vinsn->slots[i].opcode =
6436 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6438 vinsn->slots[i].ntok = 0;
6441 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6447 density_supported = saved_density;
6451 xg_clear_vinsn (vinsn);
6455 for (j = 0; j < slotstack.ninsn; j++)
6457 TInsn *insn = &slotstack.insn[j];
6458 if (insn->insn_type == ITYPE_LITERAL)
6460 gas_assert (lit_sym == NULL);
6461 lit_sym = xg_assemble_literal (insn);
6465 gas_assert (insn->insn_type == ITYPE_INSN);
6467 xg_resolve_literals (insn, lit_sym);
6468 if (j != slotstack.ninsn - 1)
6469 emit_single_op (insn);
6473 if (vinsn->num_slots > 1)
6475 if (opcode_fits_format_slot
6476 (slotstack.insn[slotstack.ninsn - 1].opcode,
6479 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6483 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6484 if (vinsn->format == XTENSA_UNDEFINED)
6485 vinsn->slots[i].opcode = xtensa_nop_opcode;
6487 vinsn->slots[i].opcode
6488 = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6491 vinsn->slots[i].ntok = 0;
6496 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6497 vinsn->format = XTENSA_UNDEFINED;
6502 /* Now check resource conflicts on the modified bundle. */
6503 if (resources_conflict (vinsn))
6505 as_bad (_("illegal resource usage in bundle"));
6506 fprintf (stderr, " ops were: ");
6507 for (i = 0; i < vinsn->num_slots; i++)
6508 fprintf (stderr, " %s;",
6509 xtensa_opcode_name (xtensa_default_isa,
6510 vinsn->slots[i].opcode));
6511 fprintf (stderr, "\n");
6512 xg_clear_vinsn (vinsn);
6516 /* First, find a format that works. */
6517 if (vinsn->format == XTENSA_UNDEFINED)
6518 vinsn->format = xg_find_narrowest_format (vinsn);
6520 xg_assemble_vliw_tokens (vinsn);
6522 xg_clear_vinsn (vinsn);
6524 xtensa_check_frag_count ();
6528 /* Given an vliw instruction, what conflicts are there in register
6529 usage and in writes to states and queues?
6531 This function does two things:
6532 1. Reports an error when a vinsn contains illegal combinations
6533 of writes to registers states or queues.
6534 2. Marks individual tinsns as not relaxable if the combination
6535 contains antidependencies.
6537 Job 2 handles things like swap semantics in instructions that need
6538 to be relaxed. For example,
6542 normally would be relaxed to
6547 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6549 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6551 then we can't relax it into
6554 { add a0, a1, a0 ; add a2, a0, a4 ; }
6556 because the value of a0 is trashed before the second add can read it. */
6558 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6561 find_vinsn_conflicts (vliw_insn *vinsn)
6565 xtensa_isa isa = xtensa_default_isa;
6567 gas_assert (!past_xtensa_end);
6569 for (i = 0 ; i < vinsn->num_slots; i++)
6571 TInsn *op1 = &vinsn->slots[i];
6572 if (op1->is_specific_opcode)
6573 op1->keep_wide = TRUE;
6575 op1->keep_wide = FALSE;
6578 for (i = 0 ; i < vinsn->num_slots; i++)
6580 TInsn *op1 = &vinsn->slots[i];
6582 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6585 for (j = 0; j < vinsn->num_slots; j++)
6589 TInsn *op2 = &vinsn->slots[j];
6590 char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6591 switch (conflict_type)
6594 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6595 xtensa_opcode_name (isa, op1->opcode), i,
6596 xtensa_opcode_name (isa, op2->opcode), j);
6599 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6600 xtensa_opcode_name (isa, op1->opcode), i,
6601 xtensa_opcode_name (isa, op2->opcode), j);
6604 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6605 xtensa_opcode_name (isa, op1->opcode), i,
6606 xtensa_opcode_name (isa, op2->opcode), j);
6609 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6610 xtensa_opcode_name (isa, op1->opcode), i,
6611 xtensa_opcode_name (isa, op2->opcode), j);
6614 /* Everything is OK. */
6617 op2->is_specific_opcode = (op2->is_specific_opcode
6618 || conflict_type == 'a');
6625 as_bad (_("multiple branches or jumps in the same bundle"));
6633 /* Check how the state used by t1 and t2 relate.
6636 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6637 case B: no relationship between what is read and written (both could
6638 read the same reg though)
6639 case C: t1 writes a register t2 writes (a register conflict within a
6641 case D: t1 writes a state that t2 also writes
6642 case E: t1 writes a tie queue that t2 also writes
6643 case F: two volatile queue accesses
6647 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6649 xtensa_isa isa = xtensa_default_isa;
6650 xtensa_regfile t1_regfile, t2_regfile;
6652 int t1_base_reg, t1_last_reg;
6653 int t2_base_reg, t2_last_reg;
6654 char t1_inout, t2_inout;
6656 char conflict = 'b';
6661 bfd_boolean t1_volatile = FALSE;
6662 bfd_boolean t2_volatile = FALSE;
6664 /* Check registers. */
6665 for (j = 0; j < t2->ntok; j++)
6667 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6670 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6671 t2_base_reg = t2->tok[j].X_add_number;
6672 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6674 for (i = 0; i < t1->ntok; i++)
6676 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6679 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6681 if (t1_regfile != t2_regfile)
6684 t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6685 t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6687 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6688 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6690 if (t1_inout == 'm' || t1_inout == 'o'
6691 || t2_inout == 'm' || t2_inout == 'o')
6698 t1_base_reg = t1->tok[i].X_add_number;
6699 t1_last_reg = (t1_base_reg
6700 + xtensa_operand_num_regs (isa, t1->opcode, i));
6702 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6704 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6706 if (t1_reg != t2_reg)
6709 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6715 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6721 if (t1_inout != 'i' && t2_inout != 'i')
6729 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6730 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6731 for (j = 0; j < t2_states; j++)
6733 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6734 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6735 for (i = 0; i < t1_states; i++)
6737 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6738 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6739 if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1)
6742 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6748 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6754 if (t1_inout != 'i' && t2_inout != 'i')
6759 /* Check tieports. */
6760 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6761 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6762 for (j = 0; j < t2_interfaces; j++)
6764 xtensa_interface t2_int
6765 = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6766 int t2_class = xtensa_interface_class_id (isa, t2_int);
6768 t2_inout = xtensa_interface_inout (isa, t2_int);
6769 if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6772 for (i = 0; i < t1_interfaces; i++)
6774 xtensa_interface t1_int
6775 = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6776 int t1_class = xtensa_interface_class_id (isa, t1_int);
6778 t1_inout = xtensa_interface_inout (isa, t1_int);
6779 if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6782 if (t1_volatile && t2_volatile && (t1_class == t2_class))
6785 if (t1_int != t2_int)
6788 if (t2_inout == 'i' && t1_inout == 'o')
6794 if (t1_inout == 'i' && t2_inout == 'o')
6800 if (t1_inout != 'i' && t2_inout != 'i')
6809 static xtensa_format
6810 xg_find_narrowest_format (vliw_insn *vinsn)
6812 /* Right now we assume that the ops within the vinsn are properly
6813 ordered for the slots that the programmer wanted them in. In
6814 other words, we don't rearrange the ops in hopes of finding a
6815 better format. The scheduler handles that. */
6817 xtensa_isa isa = xtensa_default_isa;
6818 xtensa_format format;
6819 xtensa_opcode nop_opcode = xtensa_nop_opcode;
6821 if (vinsn->num_slots == 1)
6822 return xg_get_single_format (vinsn->slots[0].opcode);
6824 for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6827 xg_copy_vinsn (&v_copy, vinsn);
6828 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6832 for (slot = 0; slot < v_copy.num_slots; slot++)
6834 if (v_copy.slots[slot].opcode == nop_opcode)
6836 v_copy.slots[slot].opcode =
6837 xtensa_format_slot_nop_opcode (isa, format, slot);
6838 v_copy.slots[slot].ntok = 0;
6841 if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6844 else if (v_copy.num_slots > 1)
6847 /* Try the widened version. */
6848 if (!v_copy.slots[slot].keep_wide
6849 && !v_copy.slots[slot].is_specific_opcode
6850 && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6852 && opcode_fits_format_slot (widened.opcode,
6855 v_copy.slots[slot] = widened;
6860 if (fit == v_copy.num_slots)
6862 xg_copy_vinsn (vinsn, &v_copy);
6863 xtensa_format_encode (isa, format, vinsn->insnbuf);
6864 vinsn->format = format;
6870 if (format == xtensa_isa_num_formats (isa))
6871 return XTENSA_UNDEFINED;
6877 /* Return the additional space needed in a frag
6878 for possible relaxations of any ops in a VLIW insn.
6879 Also fill out the relaxations that might be required of
6880 each tinsn in the vinsn. */
6883 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
6885 bfd_boolean finish_frag = FALSE;
6886 int extra_space = 0;
6889 for (slot = 0; slot < vinsn->num_slots; slot++)
6891 TInsn *tinsn = &vinsn->slots[slot];
6892 if (!tinsn_has_symbolic_operands (tinsn))
6894 /* A narrow instruction could be widened later to help
6895 alignment issues. */
6896 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
6897 && !tinsn->is_specific_opcode
6898 && vinsn->num_slots == 1)
6900 /* Difference in bytes between narrow and wide insns... */
6902 tinsn->subtype = RELAX_NARROW;
6907 if (workaround_b_j_loop_end
6908 && tinsn->opcode == xtensa_jx_opcode
6909 && use_transform ())
6911 /* Add 2 of these. */
6912 extra_space += 3; /* for the nop size */
6913 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6916 /* Need to assemble it with space for the relocation. */
6917 if (xg_is_relaxable_insn (tinsn, 0)
6918 && !tinsn->is_specific_opcode)
6920 int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6921 int max_literal_size =
6922 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6924 tinsn->literal_space = max_literal_size;
6926 tinsn->subtype = RELAX_IMMED;
6927 extra_space += max_size;
6931 /* A fix record will be added for this instruction prior
6932 to relaxation, so make it end the frag. */
6937 *pfinish_frag = finish_frag;
6943 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
6945 xtensa_isa isa = xtensa_default_isa;
6946 int slot, chosen_slot;
6948 vinsn->format = xg_get_single_format (tinsn->opcode);
6949 gas_assert (vinsn->format != XTENSA_UNDEFINED);
6950 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
6952 chosen_slot = xg_get_single_slot (tinsn->opcode);
6953 for (slot = 0; slot < vinsn->num_slots; slot++)
6955 if (slot == chosen_slot)
6956 vinsn->slots[slot] = *tinsn;
6959 vinsn->slots[slot].opcode =
6960 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6961 vinsn->slots[slot].ntok = 0;
6962 vinsn->slots[slot].insn_type = ITYPE_INSN;
6969 emit_single_op (TInsn *orig_insn)
6972 IStack istack; /* put instructions into here */
6973 symbolS *lit_sym = NULL;
6974 symbolS *label_sym = NULL;
6976 istack_init (&istack);
6978 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6979 Because the scheduling and bundling characteristics of movi and
6980 l32r or const16 are so different, we can do much better if we relax
6981 it prior to scheduling and bundling, rather than after. */
6982 if ((orig_insn->opcode == xtensa_movi_opcode
6983 || orig_insn->opcode == xtensa_movi_n_opcode)
6984 && !cur_vinsn.inside_bundle
6985 && (orig_insn->tok[1].X_op == O_symbol
6986 || orig_insn->tok[1].X_op == O_pltrel
6987 || orig_insn->tok[1].X_op == O_tlsfunc
6988 || orig_insn->tok[1].X_op == O_tlsarg
6989 || orig_insn->tok[1].X_op == O_tpoff
6990 || orig_insn->tok[1].X_op == O_dtpoff)
6991 && !orig_insn->is_specific_opcode && use_transform ())
6992 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
6994 if (xg_expand_assembly_insn (&istack, orig_insn))
6997 for (i = 0; i < istack.ninsn; i++)
6999 TInsn *insn = &istack.insn[i];
7000 switch (insn->insn_type)
7003 gas_assert (lit_sym == NULL);
7004 lit_sym = xg_assemble_literal (insn);
7008 static int relaxed_sym_idx = 0;
7009 char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12);
7010 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
7012 gas_assert (label_sym == NULL);
7013 label_sym = symbol_find_or_make (label);
7014 gas_assert (label_sym);
7022 xg_resolve_literals (insn, lit_sym);
7024 xg_resolve_labels (insn, label_sym);
7026 bundle_tinsn (insn, &v);
7041 total_frag_text_expansion (fragS *fragP)
7044 int total_expansion = 0;
7046 for (slot = 0; slot < config_max_slots; slot++)
7047 total_expansion += fragP->tc_frag_data.text_expansion[slot];
7049 return total_expansion;
7053 /* Emit a vliw instruction to the current fragment. */
7056 xg_assemble_vliw_tokens (vliw_insn *vinsn)
7058 bfd_boolean finish_frag;
7059 bfd_boolean is_jump = FALSE;
7060 bfd_boolean is_branch = FALSE;
7061 xtensa_isa isa = xtensa_default_isa;
7066 struct dwarf2_line_info debug_line;
7067 bfd_boolean loc_directive_seen = FALSE;
7070 memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
7072 if (generating_literals)
7074 static int reported = 0;
7076 as_bad_where (frag_now->fr_file, frag_now->fr_line,
7077 _("cannot assemble into a literal fragment"));
7084 if (frag_now_fix () != 0
7085 && (! frag_now->tc_frag_data.is_insn
7086 || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7087 || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform
7088 || (directive_state[directive_longcalls]
7089 != frag_now->tc_frag_data.use_longcalls)
7090 || (directive_state[directive_absolute_literals]
7091 != frag_now->tc_frag_data.use_absolute_literals)))
7093 frag_wane (frag_now);
7095 xtensa_set_frag_assembly_state (frag_now);
7098 if (workaround_a0_b_retw
7099 && vinsn->num_slots == 1
7100 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
7101 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
7102 && use_transform ())
7104 has_a0_b_retw = TRUE;
7106 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7107 After the first assembly pass we will check all of them and
7108 add a nop if needed. */
7109 frag_now->tc_frag_data.is_insn = TRUE;
7110 frag_var (rs_machine_dependent, 4, 4,
7111 RELAX_ADD_NOP_IF_A0_B_RETW,
7112 frag_now->fr_symbol,
7113 frag_now->fr_offset,
7115 xtensa_set_frag_assembly_state (frag_now);
7116 frag_now->tc_frag_data.is_insn = TRUE;
7117 frag_var (rs_machine_dependent, 4, 4,
7118 RELAX_ADD_NOP_IF_A0_B_RETW,
7119 frag_now->fr_symbol,
7120 frag_now->fr_offset,
7122 xtensa_set_frag_assembly_state (frag_now);
7125 for (slot = 0; slot < vinsn->num_slots; slot++)
7127 tinsn = &vinsn->slots[slot];
7129 /* See if the instruction implies an aligned section. */
7130 if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1)
7131 record_alignment (now_seg, 2);
7133 /* Determine the best line number for debug info. */
7134 if ((tinsn->loc_directive_seen || !loc_directive_seen)
7135 && (tinsn->debug_line.filenum != debug_line.filenum
7136 || tinsn->debug_line.line < debug_line.line
7137 || tinsn->debug_line.column < debug_line.column))
7138 debug_line = tinsn->debug_line;
7139 if (tinsn->loc_directive_seen)
7140 loc_directive_seen = TRUE;
7143 /* Special cases for instructions that force an alignment... */
7144 /* None of these opcodes are bundle-able. */
7145 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
7149 /* Remember the symbol that marks the end of the loop in the frag
7150 that marks the start of the loop. This way we can easily find
7151 the end of the loop at the beginning, without adding special code
7152 to mark the loop instructions themselves. */
7153 symbolS *target_sym = NULL;
7154 if (vinsn->slots[0].tok[1].X_op == O_symbol)
7155 target_sym = vinsn->slots[0].tok[1].X_add_symbol;
7157 xtensa_set_frag_assembly_state (frag_now);
7158 frag_now->tc_frag_data.is_insn = TRUE;
7160 max_fill = get_text_align_max_fill_size
7161 (get_text_align_power (xtensa_fetch_width),
7162 TRUE, frag_now->tc_frag_data.is_no_density);
7164 if (use_transform ())
7165 frag_var (rs_machine_dependent, max_fill, max_fill,
7166 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7168 frag_var (rs_machine_dependent, 0, 0,
7169 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7170 xtensa_set_frag_assembly_state (frag_now);
7173 if (vinsn->slots[0].opcode == xtensa_entry_opcode
7174 && !vinsn->slots[0].is_specific_opcode)
7176 xtensa_mark_literal_pool_location ();
7177 xtensa_move_labels (frag_now, 0);
7178 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7181 if (vinsn->num_slots == 1)
7183 if (workaround_a0_b_retw && use_transform ())
7184 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7185 is_register_writer (&vinsn->slots[0], "a", 0));
7187 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7188 is_bad_loopend_opcode (&vinsn->slots[0]));
7191 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
7193 insn_size = xtensa_format_length (isa, vinsn->format);
7195 extra_space = relaxation_requirements (vinsn, &finish_frag);
7197 /* vinsn_to_insnbuf will produce the error. */
7198 if (vinsn->format != XTENSA_UNDEFINED)
7200 f = frag_more (insn_size + extra_space);
7201 xtensa_set_frag_assembly_state (frag_now);
7202 frag_now->tc_frag_data.is_insn = TRUE;
7205 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
7206 if (vinsn->format == XTENSA_UNDEFINED)
7209 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
7211 if (debug_type == DEBUG_DWARF2 || loc_directive_seen)
7212 dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space),
7215 for (slot = 0; slot < vinsn->num_slots; slot++)
7217 tinsn = &vinsn->slots[slot];
7218 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7219 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7220 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7221 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7222 if (tinsn->opcode == xtensa_l32r_opcode)
7223 frag_now->tc_frag_data.literal_frags[slot]
7224 = symbol_get_frag (tinsn->tok[1].X_add_symbol);
7225 if (tinsn->literal_space != 0)
7226 xg_assemble_literal_space (tinsn->literal_space, slot);
7227 frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
7229 if (tinsn->subtype == RELAX_NARROW)
7230 gas_assert (vinsn->num_slots == 1);
7231 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7233 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7236 if (tinsn->subtype || tinsn->symbol || tinsn->offset
7237 || tinsn->literal_frag || is_jump || is_branch)
7241 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7242 frag_now->tc_frag_data.is_specific_opcode = TRUE;
7246 frag_variant (rs_machine_dependent,
7247 extra_space, extra_space, RELAX_SLOTS,
7248 frag_now->fr_symbol, frag_now->fr_offset, f);
7249 xtensa_set_frag_assembly_state (frag_now);
7252 /* Special cases for loops:
7253 close_loop_end should be inserted AFTER short_loop.
7254 Make sure that CLOSE loops are processed BEFORE short_loops
7255 when converting them. */
7257 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7258 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
7259 && !vinsn->slots[0].is_specific_opcode)
7261 if (workaround_short_loop && use_transform ())
7263 maybe_has_short_loop = TRUE;
7264 frag_now->tc_frag_data.is_insn = TRUE;
7265 frag_var (rs_machine_dependent, 4, 4,
7266 RELAX_ADD_NOP_IF_SHORT_LOOP,
7267 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7268 frag_now->tc_frag_data.is_insn = TRUE;
7269 frag_var (rs_machine_dependent, 4, 4,
7270 RELAX_ADD_NOP_IF_SHORT_LOOP,
7271 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7274 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7275 loop at least 12 bytes away from another loop's end. */
7276 if (workaround_close_loop_end && use_transform ())
7278 maybe_has_close_loop_end = TRUE;
7279 frag_now->tc_frag_data.is_insn = TRUE;
7280 frag_var (rs_machine_dependent, 12, 12,
7281 RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7282 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7286 if (use_transform ())
7290 gas_assert (finish_frag);
7291 frag_var (rs_machine_dependent,
7292 xtensa_fetch_width, xtensa_fetch_width,
7294 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7295 xtensa_set_frag_assembly_state (frag_now);
7296 xtensa_maybe_create_trampoline_frag ();
7297 /* Always create one here. */
7298 xtensa_maybe_create_literal_pool_frag (TRUE, FALSE);
7300 else if (is_branch && do_align_targets ())
7302 gas_assert (finish_frag);
7303 frag_var (rs_machine_dependent,
7304 xtensa_fetch_width, xtensa_fetch_width,
7305 RELAX_MAYBE_UNREACHABLE,
7306 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7307 xtensa_set_frag_assembly_state (frag_now);
7308 frag_var (rs_machine_dependent,
7310 RELAX_MAYBE_DESIRE_ALIGN,
7311 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7312 xtensa_set_frag_assembly_state (frag_now);
7316 /* Now, if the original opcode was a call... */
7317 if (do_align_targets ()
7318 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7320 float freq = get_subseg_total_freq (now_seg, now_subseg);
7321 frag_now->tc_frag_data.is_insn = TRUE;
7322 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7323 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7324 xtensa_set_frag_assembly_state (frag_now);
7327 if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7329 frag_wane (frag_now);
7331 xtensa_set_frag_assembly_state (frag_now);
7336 /* xtensa_end and helper functions. */
7338 static void xtensa_cleanup_align_frags (void);
7339 static void xtensa_fix_target_frags (void);
7340 static void xtensa_mark_narrow_branches (void);
7341 static void xtensa_mark_zcl_first_insns (void);
7342 static void xtensa_mark_difference_of_two_symbols (void);
7343 static void xtensa_fix_a0_b_retw_frags (void);
7344 static void xtensa_fix_b_j_loop_end_frags (void);
7345 static void xtensa_fix_close_loop_end_frags (void);
7346 static void xtensa_fix_short_loop_frags (void);
7347 static void xtensa_sanity_check (void);
7348 static void xtensa_add_config_info (void);
7353 directive_balance ();
7354 xtensa_flush_pending_output ();
7356 past_xtensa_end = TRUE;
7358 xtensa_move_literals ();
7360 xtensa_reorder_segments ();
7361 xtensa_cleanup_align_frags ();
7362 xtensa_fix_target_frags ();
7363 if (workaround_a0_b_retw && has_a0_b_retw)
7364 xtensa_fix_a0_b_retw_frags ();
7365 if (workaround_b_j_loop_end)
7366 xtensa_fix_b_j_loop_end_frags ();
7368 /* "close_loop_end" should be processed BEFORE "short_loop". */
7369 if (workaround_close_loop_end && maybe_has_close_loop_end)
7370 xtensa_fix_close_loop_end_frags ();
7372 if (workaround_short_loop && maybe_has_short_loop)
7373 xtensa_fix_short_loop_frags ();
7375 xtensa_mark_narrow_branches ();
7376 xtensa_mark_zcl_first_insns ();
7378 xtensa_sanity_check ();
7380 xtensa_add_config_info ();
7382 xtensa_check_frag_count ();
7385 struct trampoline_chain_entry
7391 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7392 of locations of trampoline jumps leading there. Jumps are represented
7393 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7395 struct trampoline_chain
7397 struct trampoline_chain_entry target;
7398 struct trampoline_chain_entry *entry;
7401 bfd_boolean needs_sorting;
7404 struct trampoline_chain_index
7406 struct trampoline_chain *entry;
7409 bfd_boolean needs_sorting;
7412 struct trampoline_index
7419 struct trampoline_seg
7421 struct trampoline_seg *next;
7423 /* Trampolines ordered by their frag fr_address */
7424 struct trampoline_index index;
7425 /* Known trampoline chains ordered by (sym, offset) pair */
7426 struct trampoline_chain_index chain_index;
7429 static struct trampoline_seg trampoline_seg_list;
7430 #define J_RANGE (128 * 1024)
7431 #define J_MARGIN 4096
7433 static int unreachable_count = 0;
7437 xtensa_maybe_create_trampoline_frag (void)
7439 if (!use_trampolines)
7442 /* We create an area for possible trampolines every 10 unreachable frags.
7443 These are preferred over the ones not preceded by an unreachable frag,
7444 because we don't have to jump around them. This function is called after
7445 each RELAX_UNREACHABLE frag is created. */
7447 if (++unreachable_count > 10)
7449 xtensa_create_trampoline_frag (FALSE);
7450 clear_frag_count ();
7451 unreachable_count = 0;
7456 xtensa_check_frag_count (void)
7458 if (!use_trampolines || frag_now->tc_frag_data.is_no_transform)
7461 /* We create an area for possible trampolines every 8000 frags or so. This
7462 is an estimate based on the max range of a "j" insn (+/-128K) divided
7463 by a typical frag byte count (16), minus a few for safety. This function
7464 is called after each source line is processed. */
7466 if (get_frag_count () > 8000)
7468 xtensa_create_trampoline_frag (TRUE);
7469 clear_frag_count ();
7470 unreachable_count = 0;
7473 /* We create an area for a possible literal pool every N (default 5000)
7475 xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
7478 static xtensa_insnbuf trampoline_buf = NULL;
7479 static xtensa_insnbuf trampoline_slotbuf = NULL;
7481 static xtensa_insnbuf litpool_buf = NULL;
7482 static xtensa_insnbuf litpool_slotbuf = NULL;
7484 #define TRAMPOLINE_FRAG_SIZE 3000
7486 static struct trampoline_seg *
7487 find_trampoline_seg (asection *seg)
7489 struct trampoline_seg *ts = trampoline_seg_list.next;
7490 static struct trampoline_seg *mr;
7492 if (mr && mr->seg == seg)
7495 for ( ; ts; ts = ts->next)
7507 static size_t xg_find_trampoline (const struct trampoline_index *idx,
7511 size_t b = idx->n_entries;
7515 size_t c = (a + b) / 2;
7517 if (idx->entry[c]->fr_address <= addr)
7525 static void xg_add_trampoline_to_index (struct trampoline_index *idx,
7528 if (idx->n_entries == idx->n_max)
7530 idx->n_max = (idx->n_entries + 1) * 2;
7531 idx->entry = xrealloc (idx->entry,
7532 sizeof (*idx->entry) * idx->n_max);
7534 idx->entry[idx->n_entries] = fragP;
7538 static void xg_remove_trampoline_from_index (struct trampoline_index *idx,
7541 gas_assert (i < idx->n_entries);
7542 memmove (idx->entry + i, idx->entry + i + 1,
7543 (idx->n_entries - i - 1) * sizeof (*idx->entry));
7547 static void xg_add_trampoline_to_seg (struct trampoline_seg *ts,
7550 xg_add_trampoline_to_index (&ts->index, fragP);
7554 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around)
7556 /* Emit a frag where we can place intermediate jump instructions,
7557 in case we need to jump farther than 128K bytes.
7558 Each jump instruction takes three bytes.
7559 We allocate enough for 1000 trampolines in each frag.
7560 If that's not enough, oh well. */
7562 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
7565 int size = TRAMPOLINE_FRAG_SIZE;
7569 ts = XCNEW(struct trampoline_seg);
7570 ts->next = trampoline_seg_list.next;
7571 trampoline_seg_list.next = ts;
7575 frag_wane (frag_now);
7577 xtensa_set_frag_assembly_state (frag_now);
7578 varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL);
7579 fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG);
7580 if (trampoline_buf == NULL)
7582 trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa);
7583 trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7585 fragP->tc_frag_data.needs_jump_around = needs_jump_around;
7586 xg_add_trampoline_to_seg (ts, fragP);
7589 static bfd_boolean xg_is_trampoline_frag_full (const fragS *fragP)
7591 return fragP->fr_var < 3;
7594 static int xg_order_trampoline_chain_entry (const void *a, const void *b)
7596 const struct trampoline_chain_entry *pa = a;
7597 const struct trampoline_chain_entry *pb = b;
7599 if (pa->sym == pb->sym ||
7600 S_GET_VALUE (pa->sym) == S_GET_VALUE (pb->sym))
7601 if (pa->offset == pb->offset)
7604 return pa->offset < pb->offset ? -1 : 1;
7606 return S_GET_VALUE (pa->sym) < S_GET_VALUE (pb->sym) ? -1 : 1;
7609 static void xg_sort_trampoline_chain (struct trampoline_chain *tc)
7611 qsort (tc->entry, tc->n_entries, sizeof (*tc->entry),
7612 xg_order_trampoline_chain_entry);
7613 tc->needs_sorting = FALSE;
7616 /* Find entry index in the given chain with maximal address <= source. */
7617 static size_t xg_find_chain_entry (struct trampoline_chain *tc,
7621 size_t b = tc->n_entries;
7623 if (tc->needs_sorting)
7624 xg_sort_trampoline_chain (tc);
7628 size_t c = (a + b) / 2;
7629 struct trampoline_chain_entry *e = tc->entry + c;
7631 if (S_GET_VALUE(e->sym) + e->offset <= source)
7639 /* Find the best jump target for the source in the given trampoline chain.
7640 The best jump target is the one that results in the shortest path to the
7641 final target, it's the location of the jump closest to the final target,
7642 but within the J_RANGE - J_MARGIN from the source. */
7643 static struct trampoline_chain_entry *
7644 xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source)
7646 addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset;
7647 size_t i = xg_find_chain_entry (tc, source);
7648 struct trampoline_chain_entry *e = tc->entry + i;
7649 int step = target < source ? -1 : 1;
7650 addressT chained_target;
7653 if (target > source &&
7654 S_GET_VALUE(e->sym) + e->offset <= source &&
7655 i + 1 < tc->n_entries)
7658 while (i + step < tc->n_entries)
7660 struct trampoline_chain_entry *next = tc->entry + i + step;
7662 chained_target = S_GET_VALUE(next->sym) + next->offset;
7663 off = source - chained_target;
7665 if (labs (off) >= J_RANGE - J_MARGIN)
7672 chained_target = S_GET_VALUE(e->sym) + e->offset;
7673 off = source - chained_target;
7675 if (labs (off) < J_MARGIN ||
7676 labs (off) >= J_RANGE - J_MARGIN)
7678 return tc->entry + i;
7681 static int xg_order_trampoline_chain (const void *a, const void *b)
7683 const struct trampoline_chain *_pa = a;
7684 const struct trampoline_chain *_pb = b;
7685 const struct trampoline_chain_entry *pa = &_pa->target;
7686 const struct trampoline_chain_entry *pb = &_pb->target;
7687 symbolS *s1 = pa->sym;
7688 symbolS *s2 = pb->sym;
7691 tmp = symbol_symbolS (s1);
7695 tmp = symbol_symbolS (s2);
7700 if (pa->offset == pb->offset)
7703 return pa->offset < pb->offset ? -1 : 1;
7705 return s1 < s2 ? -1 : 1;
7708 static struct trampoline_chain *
7709 xg_get_trampoline_chain (struct trampoline_seg *ts,
7713 struct trampoline_chain_index *idx = &ts->chain_index;
7714 struct trampoline_chain c;
7716 if (idx->needs_sorting)
7718 qsort (idx->entry, idx->n_entries, sizeof (*idx->entry),
7719 xg_order_trampoline_chain);
7720 idx->needs_sorting = FALSE;
7723 c.target.offset = offset;
7724 return bsearch (&c, idx->entry, idx->n_entries,
7725 sizeof (struct trampoline_chain),
7726 xg_order_trampoline_chain);
7729 /* Find trampoline chain in the given trampoline segment that is going
7730 to the *sym + *offset. If found, replace *sym and *offset with the
7731 best jump target in that chain. */
7732 static struct trampoline_chain *
7733 xg_find_best_eq_target (struct trampoline_seg *ts,
7734 addressT source, symbolS **sym,
7737 struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset);
7741 struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source);
7744 *offset = e->offset;
7749 static void xg_add_location_to_chain (struct trampoline_chain *tc,
7750 symbolS *sym, addressT offset)
7752 struct trampoline_chain_entry *e;
7754 if (tc->n_entries == tc->n_max)
7756 tc->n_max = (tc->n_max + 1) * 2;
7757 tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max);
7759 e = tc->entry + tc->n_entries;
7763 tc->needs_sorting = TRUE;
7766 static struct trampoline_chain *
7767 xg_create_trampoline_chain (struct trampoline_seg *ts,
7768 symbolS *sym, addressT offset)
7770 struct trampoline_chain_index *idx = &ts->chain_index;
7771 struct trampoline_chain *tc;
7773 if (idx->n_entries == idx->n_max)
7775 idx->n_max = (idx->n_max + 1) * 2;
7776 idx->entry = xrealloc (idx->entry,
7777 sizeof (*idx->entry) * idx->n_max);
7780 tc = idx->entry + idx->n_entries;
7781 tc->target.sym = sym;
7782 tc->target.offset = offset;
7786 xg_add_location_to_chain (tc, sym, offset);
7789 idx->needs_sorting = TRUE;
7794 void dump_trampolines (void);
7797 dump_trampolines (void)
7799 struct trampoline_seg *ts = trampoline_seg_list.next;
7801 for ( ; ts; ts = ts->next)
7804 asection *seg = ts->seg;
7808 fprintf(stderr, "SECTION %s\n", seg->name);
7810 for (i = 0; i < ts->index.n_entries; ++i)
7812 fragS *tf = ts->index.entry[i];
7814 fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n",
7815 (int)tf->fr_address, (int)tf->fr_fix,
7816 tf->tc_frag_data.needs_jump_around ? "T" : "F");
7821 static void dump_litpools (void) __attribute__ ((unused));
7824 dump_litpools (void)
7826 struct litpool_seg *lps = litpool_seg_list.next;
7827 struct litpool_frag *lpf;
7829 for ( ; lps ; lps = lps->next )
7831 printf("litpool seg %s\n", lps->seg->name);
7832 for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next )
7834 fragS *litfrag = lpf->fragP->fr_next;
7836 while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END)
7838 if (litfrag->fr_fix == 4)
7840 litfrag = litfrag->fr_next;
7842 printf(" %ld <%d:%d> (%d) [%d]: ",
7843 lpf->addr, lpf->priority, lpf->original_priority,
7844 lpf->fragP->fr_line, count);
7845 //dump_frag(lpf->fragP);
7851 xtensa_maybe_create_literal_pool_frag (bfd_boolean create,
7852 bfd_boolean only_if_needed)
7854 struct litpool_seg *lps = litpool_seg_list.next;
7856 struct litpool_frag *lpf;
7857 bfd_boolean needed = FALSE;
7859 if (use_literal_section || !auto_litpools)
7862 for ( ; lps ; lps = lps->next )
7864 if (lps->seg == now_seg)
7870 lps = XCNEW (struct litpool_seg);
7871 lps->next = litpool_seg_list.next;
7872 litpool_seg_list.next = lps;
7874 lps->frag_list.next = &lps->frag_list;
7875 lps->frag_list.prev = &lps->frag_list;
7876 /* Put candidate literal pool at the beginning of every section,
7877 so that even when section starts with literal load there's a
7878 literal pool available. */
7879 lps->frag_count = auto_litpool_limit;
7888 if (past_xtensa_end || !use_transform() ||
7889 frag_now->tc_frag_data.is_no_transform)
7893 if (auto_litpool_limit <= 0)
7895 /* Don't create a litpool based only on frag count. */
7898 else if (lps->frag_count > auto_litpool_limit)
7915 int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */
7916 /* Create a potential site for a literal pool. */
7917 frag_wane (frag_now);
7919 xtensa_set_frag_assembly_state (frag_now);
7921 fragP->tc_frag_data.lit_frchain = frchain_now;
7922 fragP->tc_frag_data.literal_frag = fragP;
7923 frag_var (rs_machine_dependent, size, size,
7925 RELAX_LITERAL_POOL_CANDIDATE_BEGIN :
7926 RELAX_LITERAL_POOL_BEGIN,
7928 frag_now->tc_frag_data.lit_seg = now_seg;
7929 frag_variant (rs_machine_dependent, 0, 0,
7930 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
7931 xtensa_set_frag_assembly_state (frag_now);
7935 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7936 just record it here. */
7940 lpf = XNEW (struct litpool_frag);
7941 /* Insert at tail of circular list. */
7943 lps->frag_list.prev->next = lpf;
7944 lpf->next = &lps->frag_list;
7945 lpf->prev = lps->frag_list.prev;
7946 lps->frag_list.prev = lpf;
7948 lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1;
7949 lpf->original_priority = lpf->priority;
7950 lpf->literal_count = 0;
7952 lps->frag_count = 0;
7956 xtensa_cleanup_align_frags (void)
7961 for (s = stdoutput->sections; s; s = s->next)
7962 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7965 /* Walk over all of the fragments in a subsection. */
7966 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7968 if ((fragP->fr_type == rs_align
7969 || fragP->fr_type == rs_align_code
7970 || (fragP->fr_type == rs_machine_dependent
7971 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
7972 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
7973 && fragP->fr_fix == 0)
7975 fragS *next = fragP->fr_next;
7978 && next->fr_fix == 0
7979 && next->fr_type == rs_machine_dependent
7980 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
7983 next = next->fr_next;
7986 /* If we don't widen branch targets, then they
7987 will be easier to align. */
7988 if (fragP->tc_frag_data.is_branch_target
7989 && fragP->fr_opcode == fragP->fr_literal
7990 && fragP->fr_type == rs_machine_dependent
7991 && fragP->fr_subtype == RELAX_SLOTS
7992 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
7994 if (fragP->fr_type == rs_machine_dependent
7995 && fragP->fr_subtype == RELAX_UNREACHABLE)
7996 fragP->tc_frag_data.is_unreachable = TRUE;
8002 /* Re-process all of the fragments looking to convert all of the
8003 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
8004 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
8005 Otherwise, convert to a .fill 0. */
8008 xtensa_fix_target_frags (void)
8013 /* When this routine is called, all of the subsections are still intact
8014 so we walk over subsections instead of sections. */
8015 for (s = stdoutput->sections; s; s = s->next)
8016 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8020 /* Walk over all of the fragments in a subsection. */
8021 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8023 if (fragP->fr_type == rs_machine_dependent
8024 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
8026 if (next_frag_is_branch_target (fragP))
8027 fragP->fr_subtype = RELAX_DESIRE_ALIGN;
8036 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
8039 xtensa_mark_narrow_branches (void)
8044 for (s = stdoutput->sections; s; s = s->next)
8045 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8048 /* Walk over all of the fragments in a subsection. */
8049 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8051 if (fragP->fr_type == rs_machine_dependent
8052 && fragP->fr_subtype == RELAX_SLOTS
8053 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8057 vinsn_from_chars (&vinsn, fragP->fr_opcode);
8058 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
8060 if (vinsn.num_slots == 1
8061 && xtensa_opcode_is_branch (xtensa_default_isa,
8062 vinsn.slots[0].opcode) == 1
8063 && xg_get_single_size (vinsn.slots[0].opcode) == 2
8064 && is_narrow_branch_guaranteed_in_range (fragP,
8067 fragP->fr_subtype = RELAX_SLOTS;
8068 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
8069 fragP->tc_frag_data.is_aligning_branch = 1;
8077 /* A branch is typically widened only when its target is out of
8078 range. However, we would like to widen them to align a subsequent
8079 branch target when possible.
8081 Because the branch relaxation code is so convoluted, the optimal solution
8082 (combining the two cases) is difficult to get right in all circumstances.
8083 We therefore go with an "almost as good" solution, where we only
8084 use for alignment narrow branches that definitely will not expand to a
8085 jump and a branch. These functions find and mark these cases. */
8087 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8088 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8089 We start counting beginning with the frag after the 2-byte branch, so the
8090 maximum offset is (4 - 2) + 63 = 65. */
8091 #define MAX_IMMED6 65
8093 static offsetT unrelaxed_frag_max_size (fragS *);
8096 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
8098 const expressionS *exp = &tinsn->tok[1];
8099 symbolS *symbolP = exp->X_add_symbol;
8100 offsetT max_distance = exp->X_add_number;
8103 if (exp->X_op != O_symbol)
8106 target_frag = symbol_get_frag (symbolP);
8108 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
8109 if (is_branch_jmp_to_next (tinsn, fragP))
8112 /* The branch doesn't branch over it's own frag,
8113 but over the subsequent ones. */
8114 fragP = fragP->fr_next;
8115 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
8117 max_distance += unrelaxed_frag_max_size (fragP);
8118 fragP = fragP->fr_next;
8120 if (max_distance <= MAX_IMMED6 && fragP == target_frag)
8127 xtensa_mark_zcl_first_insns (void)
8132 for (s = stdoutput->sections; s; s = s->next)
8133 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8136 /* Walk over all of the fragments in a subsection. */
8137 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8139 if (fragP->fr_type == rs_machine_dependent
8140 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8141 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8143 /* Find the loop frag. */
8144 fragS *loop_frag = next_non_empty_frag (fragP);
8145 /* Find the first insn frag. */
8146 fragS *targ_frag = next_non_empty_frag (loop_frag);
8148 /* Handle a corner case that comes up in hardware
8149 diagnostics. The original assembly looks like this:
8152 <empty_frag>--not found by next_non_empty_frag
8155 Depending on the start address, the assembler may or
8156 may not change it to look something like this:
8159 nop--frag isn't empty anymore
8162 So set up to check the alignment of the nop if it
8164 while (loop_frag != targ_frag)
8166 if (loop_frag->fr_type == rs_machine_dependent
8167 && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8168 || loop_frag->fr_subtype
8169 == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8170 targ_frag = loop_frag;
8172 loop_frag = loop_frag->fr_next;
8175 /* Of course, sometimes (mostly for toy test cases) a
8176 zero-cost loop instruction is the last in a section. */
8179 targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
8180 /* Do not widen a frag that is the first instruction of a
8181 zero-cost loop. It makes that loop harder to align. */
8182 if (targ_frag->fr_type == rs_machine_dependent
8183 && targ_frag->fr_subtype == RELAX_SLOTS
8184 && (targ_frag->tc_frag_data.slot_subtypes[0]
8187 if (targ_frag->tc_frag_data.is_aligning_branch)
8188 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
8191 frag_wane (targ_frag);
8192 targ_frag->tc_frag_data.slot_subtypes[0] = 0;
8196 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
8204 /* When a difference-of-symbols expression is encoded as a uleb128 or
8205 sleb128 value, the linker is unable to adjust that value to account for
8206 link-time relaxation. Mark all the code between such symbols so that
8207 its size cannot be changed by linker relaxation. */
8210 xtensa_mark_difference_of_two_symbols (void)
8214 for (expr_sym = expr_symbols; expr_sym;
8215 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
8217 expressionS *exp = symbol_get_value_expression (expr_sym);
8219 if (exp->X_op == O_subtract)
8221 symbolS *left = exp->X_add_symbol;
8222 symbolS *right = exp->X_op_symbol;
8224 /* Difference of two symbols not in the same section
8225 are handled with relocations in the linker. */
8226 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
8232 if (symbol_get_frag (left)->fr_address
8233 <= symbol_get_frag (right)->fr_address)
8235 start = symbol_get_frag (left);
8236 end = symbol_get_frag (right);
8240 start = symbol_get_frag (right);
8241 end = symbol_get_frag (left);
8244 if (start->tc_frag_data.no_transform_end != NULL)
8245 walk = start->tc_frag_data.no_transform_end;
8250 walk->tc_frag_data.is_no_transform = 1;
8251 walk = walk->fr_next;
8253 while (walk && walk->fr_address < end->fr_address);
8255 start->tc_frag_data.no_transform_end = walk;
8262 /* Re-process all of the fragments looking to convert all of the
8263 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8264 conditional branch or a retw/retw.n, convert this frag to one that
8265 will generate a NOP. In any case close it off with a .fill 0. */
8267 static bfd_boolean next_instrs_are_b_retw (fragS *);
8270 xtensa_fix_a0_b_retw_frags (void)
8275 /* When this routine is called, all of the subsections are still intact
8276 so we walk over subsections instead of sections. */
8277 for (s = stdoutput->sections; s; s = s->next)
8278 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8282 /* Walk over all of the fragments in a subsection. */
8283 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8285 if (fragP->fr_type == rs_machine_dependent
8286 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
8288 if (next_instrs_are_b_retw (fragP))
8290 if (fragP->tc_frag_data.is_no_transform)
8291 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8293 relax_frag_add_nop (fragP);
8303 next_instrs_are_b_retw (fragS *fragP)
8305 xtensa_opcode opcode;
8307 const fragS *next_fragP = next_non_empty_frag (fragP);
8308 static xtensa_insnbuf insnbuf = NULL;
8309 static xtensa_insnbuf slotbuf = NULL;
8310 xtensa_isa isa = xtensa_default_isa;
8313 bfd_boolean branch_seen = FALSE;
8317 insnbuf = xtensa_insnbuf_alloc (isa);
8318 slotbuf = xtensa_insnbuf_alloc (isa);
8321 if (next_fragP == NULL)
8324 /* Check for the conditional branch. */
8325 xtensa_insnbuf_from_chars
8326 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8327 fmt = xtensa_format_decode (isa, insnbuf);
8328 if (fmt == XTENSA_UNDEFINED)
8331 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8333 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
8334 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
8336 branch_seen = (branch_seen
8337 || xtensa_opcode_is_branch (isa, opcode) == 1);
8343 offset += xtensa_format_length (isa, fmt);
8344 if (offset == next_fragP->fr_fix)
8346 next_fragP = next_non_empty_frag (next_fragP);
8350 if (next_fragP == NULL)
8353 /* Check for the retw/retw.n. */
8354 xtensa_insnbuf_from_chars
8355 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8356 fmt = xtensa_format_decode (isa, insnbuf);
8358 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8359 have no problems. */
8360 if (fmt == XTENSA_UNDEFINED
8361 || xtensa_format_num_slots (isa, fmt) != 1)
8364 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
8365 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
8367 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
8374 /* Re-process all of the fragments looking to convert all of the
8375 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8376 loop end label, convert this frag to one that will generate a NOP.
8377 In any case close it off with a .fill 0. */
8379 static bfd_boolean next_instr_is_loop_end (fragS *);
8382 xtensa_fix_b_j_loop_end_frags (void)
8387 /* When this routine is called, all of the subsections are still intact
8388 so we walk over subsections instead of sections. */
8389 for (s = stdoutput->sections; s; s = s->next)
8390 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8394 /* Walk over all of the fragments in a subsection. */
8395 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8397 if (fragP->fr_type == rs_machine_dependent
8398 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
8400 if (next_instr_is_loop_end (fragP))
8402 if (fragP->tc_frag_data.is_no_transform)
8403 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8405 relax_frag_add_nop (fragP);
8415 next_instr_is_loop_end (fragS *fragP)
8417 const fragS *next_fragP;
8419 if (next_frag_is_loop_target (fragP))
8422 next_fragP = next_non_empty_frag (fragP);
8423 if (next_fragP == NULL)
8426 if (!next_frag_is_loop_target (next_fragP))
8429 /* If the size is >= 3 then there is more than one instruction here.
8430 The hardware bug will not fire. */
8431 if (next_fragP->fr_fix > 3)
8438 /* Re-process all of the fragments looking to convert all of the
8439 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8440 not MY loop's loop end within 12 bytes, add enough nops here to
8441 make it at least 12 bytes away. In any case close it off with a
8444 static offsetT min_bytes_to_other_loop_end
8445 (fragS *, fragS *, offsetT);
8448 xtensa_fix_close_loop_end_frags (void)
8453 /* When this routine is called, all of the subsections are still intact
8454 so we walk over subsections instead of sections. */
8455 for (s = stdoutput->sections; s; s = s->next)
8456 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8460 fragS *current_target = NULL;
8462 /* Walk over all of the fragments in a subsection. */
8463 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8465 if (fragP->fr_type == rs_machine_dependent
8466 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8467 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8468 current_target = symbol_get_frag (fragP->fr_symbol);
8471 && fragP->fr_type == rs_machine_dependent
8472 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
8475 int bytes_added = 0;
8477 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8478 /* Max out at 12. */
8479 min_bytes = min_bytes_to_other_loop_end
8480 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
8482 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
8484 if (fragP->tc_frag_data.is_no_transform)
8485 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8488 while (min_bytes + bytes_added
8489 < REQUIRED_LOOP_DIVIDING_BYTES)
8493 if (fragP->fr_var < length)
8494 as_fatal (_("fr_var %lu < length %d"),
8495 (long) fragP->fr_var, length);
8498 assemble_nop (length,
8499 fragP->fr_literal + fragP->fr_fix);
8500 fragP->fr_fix += length;
8501 fragP->fr_var -= length;
8503 bytes_added += length;
8509 gas_assert (fragP->fr_type != rs_machine_dependent
8510 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
8516 static offsetT unrelaxed_frag_min_size (fragS *);
8519 min_bytes_to_other_loop_end (fragS *fragP,
8520 fragS *current_target,
8524 fragS *current_fragP;
8526 for (current_fragP = fragP;
8528 current_fragP = current_fragP->fr_next)
8530 if (current_fragP->tc_frag_data.is_loop_target
8531 && current_fragP != current_target)
8534 offset += unrelaxed_frag_min_size (current_fragP);
8536 if (offset >= max_size)
8544 unrelaxed_frag_min_size (fragS *fragP)
8546 offsetT size = fragP->fr_fix;
8548 /* Add fill size. */
8549 if (fragP->fr_type == rs_fill)
8550 size += fragP->fr_offset;
8557 unrelaxed_frag_max_size (fragS *fragP)
8559 offsetT size = fragP->fr_fix;
8560 switch (fragP->fr_type)
8563 /* Empty frags created by the obstack allocation scheme
8564 end up with type 0. */
8569 size += fragP->fr_offset;
8577 /* No further adjustments needed. */
8579 case rs_machine_dependent:
8580 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
8581 size += fragP->fr_var;
8584 /* We had darn well better know how big it is. */
8593 /* Re-process all of the fragments looking to convert all
8594 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8597 1) the instruction size count to the loop end label
8598 is too short (<= 2 instructions),
8599 2) loop has a jump or branch in it
8602 1) workaround_all_short_loops is TRUE
8603 2) The generating loop was a 'loopgtz' or 'loopnez'
8604 3) the instruction size count to the loop end label is too short
8606 then convert this frag (and maybe the next one) to generate a NOP.
8607 In any case close it off with a .fill 0. */
8609 static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
8610 static bfd_boolean branch_before_loop_end (fragS *);
8613 xtensa_fix_short_loop_frags (void)
8618 /* When this routine is called, all of the subsections are still intact
8619 so we walk over subsections instead of sections. */
8620 for (s = stdoutput->sections; s; s = s->next)
8621 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8624 xtensa_opcode current_opcode = XTENSA_UNDEFINED;
8626 /* Walk over all of the fragments in a subsection. */
8627 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8629 if (fragP->fr_type == rs_machine_dependent
8630 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8631 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8634 fragS *loop_frag = next_non_empty_frag (fragP);
8635 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
8636 current_opcode = t_insn.opcode;
8637 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa,
8638 current_opcode) == 1);
8641 if (fragP->fr_type == rs_machine_dependent
8642 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8644 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
8645 && (branch_before_loop_end (fragP->fr_next)
8646 || (workaround_all_short_loops
8647 && current_opcode != XTENSA_UNDEFINED
8648 && current_opcode != xtensa_loop_opcode)))
8650 if (fragP->tc_frag_data.is_no_transform)
8651 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8653 relax_frag_add_nop (fragP);
8662 static int unrelaxed_frag_min_insn_count (fragS *);
8665 count_insns_to_loop_end (fragS *base_fragP,
8666 bfd_boolean count_relax_add,
8669 fragS *fragP = NULL;
8674 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
8676 insn_count += unrelaxed_frag_min_insn_count (fragP);
8677 if (insn_count >= max_count)
8680 if (count_relax_add)
8682 if (fragP->fr_type == rs_machine_dependent
8683 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8685 /* In order to add the appropriate number of
8686 NOPs, we count an instruction for downstream
8689 if (insn_count >= max_count)
8699 unrelaxed_frag_min_insn_count (fragS *fragP)
8701 xtensa_isa isa = xtensa_default_isa;
8702 static xtensa_insnbuf insnbuf = NULL;
8706 if (!fragP->tc_frag_data.is_insn)
8710 insnbuf = xtensa_insnbuf_alloc (isa);
8712 /* Decode the fixed instructions. */
8713 while (offset < fragP->fr_fix)
8717 xtensa_insnbuf_from_chars
8718 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8719 fmt = xtensa_format_decode (isa, insnbuf);
8721 if (fmt == XTENSA_UNDEFINED)
8723 as_fatal (_("undecodable instruction in instruction frag"));
8726 offset += xtensa_format_length (isa, fmt);
8734 static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
8737 branch_before_loop_end (fragS *base_fragP)
8741 for (fragP = base_fragP;
8742 fragP && !fragP->tc_frag_data.is_loop_target;
8743 fragP = fragP->fr_next)
8745 if (unrelaxed_frag_has_b_j (fragP))
8753 unrelaxed_frag_has_b_j (fragS *fragP)
8755 static xtensa_insnbuf insnbuf = NULL;
8756 xtensa_isa isa = xtensa_default_isa;
8759 if (!fragP->tc_frag_data.is_insn)
8763 insnbuf = xtensa_insnbuf_alloc (isa);
8765 /* Decode the fixed instructions. */
8766 while (offset < fragP->fr_fix)
8771 xtensa_insnbuf_from_chars
8772 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8773 fmt = xtensa_format_decode (isa, insnbuf);
8774 if (fmt == XTENSA_UNDEFINED)
8777 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8779 xtensa_opcode opcode =
8780 get_opcode_from_buf (fragP->fr_literal + offset, slot);
8781 if (xtensa_opcode_is_branch (isa, opcode) == 1
8782 || xtensa_opcode_is_jump (isa, opcode) == 1)
8785 offset += xtensa_format_length (isa, fmt);
8791 /* Checks to be made after initial assembly but before relaxation. */
8793 static bfd_boolean is_empty_loop (const TInsn *, fragS *);
8794 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
8797 xtensa_sanity_check (void)
8799 const char *file_name;
8804 file_name = as_where (&line);
8805 for (s = stdoutput->sections; s; s = s->next)
8806 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8810 /* Walk over all of the fragments in a subsection. */
8811 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8813 if (fragP->fr_type == rs_machine_dependent
8814 && fragP->fr_subtype == RELAX_SLOTS
8815 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8817 static xtensa_insnbuf insnbuf = NULL;
8820 if (fragP->fr_opcode != NULL)
8823 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8824 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8825 tinsn_immed_from_frag (&t_insn, fragP, 0);
8827 if (xtensa_opcode_is_loop (xtensa_default_isa,
8828 t_insn.opcode) == 1)
8830 if (is_empty_loop (&t_insn, fragP))
8832 new_logical_line (fragP->fr_file, fragP->fr_line);
8833 as_bad (_("invalid empty loop"));
8835 if (!is_local_forward_loop (&t_insn, fragP))
8837 new_logical_line (fragP->fr_file, fragP->fr_line);
8838 as_bad (_("loop target does not follow "
8839 "loop instruction in section"));
8846 new_logical_line (file_name, line);
8850 #define LOOP_IMMED_OPN 1
8852 /* Return TRUE if the loop target is the next non-zero fragment. */
8855 is_empty_loop (const TInsn *insn, fragS *fragP)
8857 const expressionS *exp;
8861 if (insn->insn_type != ITYPE_INSN)
8864 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8867 if (insn->ntok <= LOOP_IMMED_OPN)
8870 exp = &insn->tok[LOOP_IMMED_OPN];
8872 if (exp->X_op != O_symbol)
8875 symbolP = exp->X_add_symbol;
8879 if (symbol_get_frag (symbolP) == NULL)
8882 if (S_GET_VALUE (symbolP) != 0)
8885 /* Walk through the zero-size fragments from this one. If we find
8886 the target fragment, then this is a zero-size loop. */
8888 for (next_fragP = fragP->fr_next;
8890 next_fragP = next_fragP->fr_next)
8892 if (next_fragP == symbol_get_frag (symbolP))
8894 if (next_fragP->fr_fix != 0)
8902 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8904 const expressionS *exp;
8908 if (insn->insn_type != ITYPE_INSN)
8911 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8914 if (insn->ntok <= LOOP_IMMED_OPN)
8917 exp = &insn->tok[LOOP_IMMED_OPN];
8919 if (exp->X_op != O_symbol)
8922 symbolP = exp->X_add_symbol;
8926 if (symbol_get_frag (symbolP) == NULL)
8929 /* Walk through fragments until we find the target.
8930 If we do not find the target, then this is an invalid loop. */
8932 for (next_fragP = fragP->fr_next;
8934 next_fragP = next_fragP->fr_next)
8936 if (next_fragP == symbol_get_frag (symbolP))
8944 #define XTINFO_NAME "Xtensa_Info"
8945 #define XTINFO_NAMESZ 12
8946 #define XTINFO_TYPE 1
8949 xtensa_add_config_info (void)
8955 info_sec = subseg_new (".xtensa.info", 0);
8956 bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
8958 data = XNEWVEC (char, 100);
8959 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8960 XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
8961 sz = strlen (data) + 1;
8963 /* Add enough null terminators to pad to a word boundary. */
8966 while ((sz & 3) != 0);
8968 /* Follow the standard note section layout:
8969 First write the length of the name string. */
8971 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
8973 /* Next comes the length of the "descriptor", i.e., the actual data. */
8975 md_number_to_chars (p, (valueT) sz, 4);
8977 /* Write the note type. */
8979 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
8981 /* Write the name field. */
8982 p = frag_more (XTINFO_NAMESZ);
8983 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
8985 /* Finally, write the descriptor. */
8987 memcpy (p, data, sz);
8993 /* Alignment Functions. */
8996 get_text_align_power (unsigned target_size)
8998 if (target_size <= 4)
9001 if (target_size <= 8)
9004 if (target_size <= 16)
9007 if (target_size <= 32)
9010 if (target_size <= 64)
9013 if (target_size <= 128)
9016 if (target_size <= 256)
9019 if (target_size <= 512)
9022 if (target_size <= 1024)
9031 get_text_align_max_fill_size (int align_pow,
9032 bfd_boolean use_nops,
9033 bfd_boolean use_no_density)
9036 return (1 << align_pow);
9038 return 3 * (1 << align_pow);
9040 return 1 + (1 << align_pow);
9044 /* Calculate the minimum bytes of fill needed at "address" to align a
9045 target instruction of size "target_size" so that it does not cross a
9046 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9047 the fill can be an arbitrary number of bytes. Otherwise, the space must
9048 be filled by NOP instructions. */
9051 get_text_align_fill_size (addressT address,
9054 bfd_boolean use_nops,
9055 bfd_boolean use_no_density)
9057 addressT alignment, fill, fill_limit, fill_step;
9058 bfd_boolean skip_one = FALSE;
9060 alignment = (1 << align_pow);
9061 gas_assert (target_size > 0 && alignment >= (addressT) target_size);
9065 fill_limit = alignment;
9068 else if (!use_no_density)
9070 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9071 fill_limit = alignment * 2;
9077 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9078 fill_limit = alignment * 3;
9082 /* Try all fill sizes until finding one that works. */
9083 for (fill = 0; fill < fill_limit; fill += fill_step)
9085 if (skip_one && fill == 1)
9087 if ((address + fill) >> align_pow
9088 == (address + fill + target_size - 1) >> align_pow)
9097 branch_align_power (segT sec)
9099 /* If the Xtensa processor has a fetch width of X, and
9100 the section is aligned to at least that boundary, then a branch
9101 target need only fit within that aligned block of memory to avoid
9102 a stall. Otherwise, try to fit branch targets within 4-byte
9103 aligned blocks (which may be insufficient, e.g., if the section
9104 has no alignment, but it's good enough). */
9105 int fetch_align = get_text_align_power(xtensa_fetch_width);
9106 int sec_align = get_recorded_alignment (sec);
9108 if (sec_align >= fetch_align)
9115 /* This will assert if it is not possible. */
9118 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
9124 gas_assert (fill_size % 3 == 0);
9125 return (fill_size / 3);
9128 gas_assert (fill_size != 1); /* Bad argument. */
9130 while (fill_size > 1)
9133 if (fill_size == 2 || fill_size == 4)
9135 fill_size -= insn_size;
9138 gas_assert (fill_size != 1); /* Bad algorithm. */
9144 get_text_align_nth_nop_size (offsetT fill_size,
9146 bfd_boolean use_no_density)
9153 gas_assert (fill_size != 1); /* Bad argument. */
9155 while (fill_size > 1)
9158 if (fill_size == 2 || fill_size == 4)
9160 fill_size -= insn_size;
9170 /* For the given fragment, find the appropriate address
9171 for it to begin at if we are using NOPs to align it. */
9174 get_noop_aligned_address (fragS *fragP, addressT address)
9176 /* The rule is: get next fragment's FIRST instruction. Find
9177 the smallest number of bytes that need to be added to
9178 ensure that the next fragment's FIRST instruction will fit
9181 E.G., 2 bytes : 0, 1, 2 mod 4
9184 If the FIRST instruction MIGHT be relaxed,
9185 assume that it will become a 3-byte instruction.
9187 Note again here that LOOP instructions are not bundleable,
9188 and this relaxation only applies to LOOP opcodes. */
9191 int first_insn_size;
9193 addressT pre_opcode_bytes;
9196 xtensa_opcode opcode;
9197 bfd_boolean is_loop;
9199 gas_assert (fragP->fr_type == rs_machine_dependent);
9200 gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
9202 /* Find the loop frag. */
9203 first_insn = next_non_empty_frag (fragP);
9204 /* Now find the first insn frag. */
9205 first_insn = next_non_empty_frag (first_insn);
9207 is_loop = next_frag_opcode_is_loop (fragP, &opcode);
9208 gas_assert (is_loop);
9209 loop_insn_size = xg_get_single_size (opcode);
9211 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
9212 pre_opcode_bytes += loop_insn_size;
9214 /* For loops, the alignment depends on the size of the
9215 instruction following the loop, not the LOOP instruction. */
9217 if (first_insn == NULL)
9218 first_insn_size = xtensa_fetch_width;
9220 first_insn_size = get_loop_align_size (frag_format_size (first_insn));
9222 /* If it was 8, then we'll need a larger alignment for the section. */
9223 align_power = get_text_align_power (first_insn_size);
9224 record_alignment (now_seg, align_power);
9226 fill_size = get_text_align_fill_size
9227 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
9228 fragP->tc_frag_data.is_no_density);
9230 return address + fill_size;
9234 /* 3 mechanisms for relaxing an alignment:
9236 Align to a power of 2.
9237 Align so the next fragment's instruction does not cross a word boundary.
9238 Align the current instruction so that if the next instruction
9239 were 3 bytes, it would not cross a word boundary.
9243 zeros - This is easy; always insert zeros.
9244 nops - 3-byte and 2-byte instructions
9248 >=5 : 3-byte instruction + fn (n-3)
9249 widening - widen previous instructions. */
9252 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
9254 addressT target_address, loop_insn_offset;
9256 xtensa_opcode loop_opcode;
9257 bfd_boolean is_loop;
9260 offsetT branch_align;
9263 gas_assert (fragP->fr_type == rs_machine_dependent);
9264 switch (fragP->fr_subtype)
9266 case RELAX_DESIRE_ALIGN:
9267 target_size = next_frag_format_size (fragP);
9268 if (target_size == XTENSA_UNDEFINED)
9270 align_power = branch_align_power (now_seg);
9271 branch_align = 1 << align_power;
9272 /* Don't count on the section alignment being as large as the target. */
9273 if (target_size > branch_align)
9274 target_size = branch_align;
9275 opt_diff = get_text_align_fill_size (address, align_power,
9276 target_size, FALSE, FALSE);
9278 *max_diff = (opt_diff + branch_align
9279 - (target_size + ((address + opt_diff) % branch_align)));
9280 gas_assert (*max_diff >= opt_diff);
9283 case RELAX_ALIGN_NEXT_OPCODE:
9284 /* The next non-empty frag after this one holds the LOOP instruction
9285 that needs to be aligned. The required alignment depends on the
9286 size of the next non-empty frag after the loop frag, i.e., the
9287 first instruction in the loop. */
9288 loop_frag = next_non_empty_frag (fragP);
9289 target_size = get_loop_align_size (next_frag_format_size (loop_frag));
9290 loop_insn_offset = 0;
9291 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
9292 gas_assert (is_loop);
9294 /* If the loop has been expanded then the LOOP instruction
9295 could be at an offset from this fragment. */
9296 if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED)
9297 loop_insn_offset = get_expanded_loop_offset (loop_opcode);
9299 /* In an ideal world, which is what we are shooting for here,
9300 we wouldn't need to use any NOPs immediately prior to the
9301 LOOP instruction. If this approach fails, relax_frag_loop_align
9302 will call get_noop_aligned_address. */
9304 address + loop_insn_offset + xg_get_single_size (loop_opcode);
9305 align_power = get_text_align_power (target_size);
9306 opt_diff = get_text_align_fill_size (target_address, align_power,
9307 target_size, FALSE, FALSE);
9309 *max_diff = xtensa_fetch_width
9310 - ((target_address + opt_diff) % xtensa_fetch_width)
9311 - target_size + opt_diff;
9312 gas_assert (*max_diff >= opt_diff);
9323 /* md_relax_frag Hook and Helper Functions. */
9325 static long relax_frag_loop_align (fragS *, long);
9326 static long relax_frag_for_align (fragS *, long);
9327 static long relax_frag_immed
9328 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
9330 /* Get projected address for the first fulcrum on a path from source to
9332 static addressT xg_get_fulcrum (addressT source, addressT target)
9334 offsetT delta = target - source;
9337 n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN);
9338 return source + delta / n;
9341 /* Given trampoline index, source and target of a jump find the best
9342 candidate trampoline for the first fulcrum. The best trampoline is
9343 the one in the reach of "j' instruction from the source, closest to
9344 the projected fulcrum address, and preferrably w/o a jump around or
9345 with already initialized jump around. */
9346 static size_t xg_find_best_trampoline (struct trampoline_index *idx,
9347 addressT source, addressT target)
9349 addressT fulcrum = xg_get_fulcrum (source, target);
9352 size_t base_tr = xg_find_trampoline (idx, fulcrum);
9355 /* Check trampoline frags around the base_tr to find the best. */
9356 for (dist = 0; checked; ++dist)
9359 size_t tr = base_tr - dist;
9363 /* Trampolines are checked in the following order:
9364 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9365 for (i = 0; i < 2; ++i, tr = base_tr + dist + 1)
9366 if (tr < idx->n_entries)
9368 fragS *trampoline_frag = idx->entry[tr];
9371 /* Don't check trampolines outside source - target interval. */
9372 if ((trampoline_frag->fr_address < source &&
9373 trampoline_frag->fr_address < target) ||
9374 (trampoline_frag->fr_address > source &&
9375 trampoline_frag->fr_address > target))
9378 /* Don't choose trampoline that contains the source. */
9379 if (source >= trampoline_frag->fr_address
9380 && source <= trampoline_frag->fr_address +
9381 trampoline_frag->fr_fix)
9384 off = trampoline_frag->fr_address - fulcrum;
9385 /* Stop if some trampoline is found and the search is more than
9386 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9387 around is nice, but it shouldn't have much overhead. */
9388 if (best < idx->n_entries && labs (off) > J_RANGE / 4)
9391 off = trampoline_frag->fr_address - source;
9392 if (labs (off) < J_RANGE - J_MARGIN)
9395 /* Stop if a trampoline w/o jump around is found or initialized
9396 trampoline with jump around is found. */
9397 if (!trampoline_frag->tc_frag_data.needs_jump_around ||
9398 trampoline_frag->fr_fix)
9400 else if (best >= idx->n_entries)
9406 if (best < idx->n_entries)
9409 as_fatal (_("cannot find suitable trampoline"));
9412 static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP)
9414 symbolS *s = fixP->fx_addsy;
9415 addressT source = fixP->fx_frag->fr_address;
9416 addressT target = S_GET_VALUE (s) + fixP->fx_offset;
9417 size_t tr = xg_find_best_trampoline (idx, source, target);
9418 fragS *trampoline_frag = idx->entry[tr];
9421 init_trampoline_frag (trampoline_frag);
9422 newfixP = xg_append_jump (trampoline_frag,
9423 fixP->fx_addsy, fixP->fx_offset);
9425 /* Adjust the fixup for the original "j" instruction to
9426 point to the newly added jump. */
9427 fixP->fx_addsy = trampoline_frag->fr_symbol;
9428 fixP->fx_offset = trampoline_frag->fr_fix - 3;
9429 fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol;
9430 fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3;
9432 trampoline_frag->tc_frag_data.relax_seen = FALSE;
9434 if (xg_is_trampoline_frag_full (trampoline_frag))
9435 xg_remove_trampoline_from_index (idx, tr);
9440 static bfd_boolean xg_is_relaxable_fixup (fixS *fixP)
9442 xtensa_isa isa = xtensa_default_isa;
9443 addressT addr = fixP->fx_frag->fr_address;
9446 symbolS *s = fixP->fx_addsy;
9449 xtensa_opcode opcode;
9451 if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP ||
9452 fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP)
9455 target = S_GET_VALUE (s) + fixP->fx_offset;
9456 delta = target - addr;
9458 if (labs (delta) < J_RANGE - J_MARGIN)
9461 xtensa_insnbuf_from_chars (isa, trampoline_buf,
9462 (unsigned char *) fixP->fx_frag->fr_literal +
9464 fmt = xtensa_format_decode (isa, trampoline_buf);
9465 gas_assert (fmt != XTENSA_UNDEFINED);
9466 slot = fixP->tc_fix_data.slot;
9467 xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf);
9468 opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf);
9469 return opcode == xtensa_j_opcode;
9472 static void xg_relax_fixups (struct trampoline_seg *ts)
9474 struct trampoline_index *idx = &ts->index;
9475 segment_info_type *seginfo = seg_info (now_seg);
9478 for (fx = seginfo->fix_root; fx; fx = fx->fx_next)
9481 struct trampoline_chain *tc = NULL;
9483 if (xg_is_relaxable_fixup (fixP))
9485 tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address,
9486 &fixP->fx_addsy, &fixP->fx_offset);
9488 tc = xg_create_trampoline_chain (ts, fixP->fx_addsy,
9493 while (xg_is_relaxable_fixup (fixP))
9495 fixP = xg_relax_fixup (idx, fixP);
9496 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
9502 /* Given a trampoline frag relax all jumps that might want to use this
9503 trampoline. Only do real work once per relaxation cycle, when
9504 xg_relax_trampoline is called for the first trampoline in the now_seg.
9505 Don't use stretch, don't update new_stretch: place fulcrums with a
9506 slack to tolerate code movement. In the worst case if a jump between
9507 two trampolines wouldn't reach the next relaxation pass will fix it. */
9508 static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED,
9509 long *new_stretch ATTRIBUTE_UNUSED)
9511 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9513 if (ts->index.n_entries && ts->index.entry[0] == fragP)
9514 xg_relax_fixups (ts);
9517 /* Return the number of bytes added to this fragment, given that the
9518 input has been stretched already by "stretch". */
9521 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
9523 xtensa_isa isa = xtensa_default_isa;
9524 int unreported = fragP->tc_frag_data.unreported_expansion;
9525 long new_stretch = 0;
9526 const char *file_name;
9529 static xtensa_insnbuf vbuf = NULL;
9530 int slot, num_slots;
9533 file_name = as_where (&line);
9534 new_logical_line (fragP->fr_file, fragP->fr_line);
9536 fragP->tc_frag_data.unreported_expansion = 0;
9538 switch (fragP->fr_subtype)
9540 case RELAX_ALIGN_NEXT_OPCODE:
9541 /* Always convert. */
9542 if (fragP->tc_frag_data.relax_seen)
9543 new_stretch = relax_frag_loop_align (fragP, stretch);
9546 case RELAX_LOOP_END:
9550 case RELAX_LOOP_END_ADD_NOP:
9551 /* Add a NOP and switch to .fill 0. */
9552 new_stretch = relax_frag_add_nop (fragP);
9556 case RELAX_DESIRE_ALIGN:
9557 /* Do nothing. The narrowing before this frag will either align
9562 case RELAX_LITERAL_FINAL:
9565 case RELAX_LITERAL_NR:
9567 fragP->fr_subtype = RELAX_LITERAL_FINAL;
9568 gas_assert (unreported == lit_size);
9569 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
9570 fragP->fr_var -= lit_size;
9571 fragP->fr_fix += lit_size;
9577 vbuf = xtensa_insnbuf_alloc (isa);
9579 xtensa_insnbuf_from_chars
9580 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
9581 fmt = xtensa_format_decode (isa, vbuf);
9582 num_slots = xtensa_format_num_slots (isa, fmt);
9584 for (slot = 0; slot < num_slots; slot++)
9586 switch (fragP->tc_frag_data.slot_subtypes[slot])
9589 if (fragP->tc_frag_data.relax_seen)
9590 new_stretch += relax_frag_for_align (fragP, stretch);
9594 case RELAX_IMMED_STEP1:
9595 case RELAX_IMMED_STEP2:
9596 case RELAX_IMMED_STEP3:
9597 /* Place the immediate. */
9598 new_stretch += relax_frag_immed
9599 (now_seg, fragP, stretch,
9600 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9601 fmt, slot, stretched_p, FALSE);
9605 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9611 case RELAX_LITERAL_POOL_BEGIN:
9612 if (fragP->fr_var != 0)
9614 /* We have a converted "candidate" literal pool;
9615 assemble a jump around it. */
9617 if (!litpool_slotbuf)
9619 litpool_buf = xtensa_insnbuf_alloc (isa);
9620 litpool_slotbuf = xtensa_insnbuf_alloc (isa);
9623 fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */
9624 fragP->tc_frag_data.is_insn = TRUE;
9626 insn.insn_type = ITYPE_INSN;
9627 insn.opcode = xtensa_j_opcode;
9629 set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol,
9631 fmt = xg_get_single_format (xtensa_j_opcode);
9632 tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf);
9633 xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf);
9634 xtensa_insnbuf_to_chars (isa, litpool_buf,
9635 (unsigned char *)fragP->fr_literal +
9640 fix_new (fragP, 0, 3, fragP->fr_symbol, 0, TRUE,
9641 BFD_RELOC_XTENSA_SLOT0_OP);
9645 case RELAX_LITERAL_POOL_END:
9646 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN:
9647 case RELAX_MAYBE_UNREACHABLE:
9648 case RELAX_MAYBE_DESIRE_ALIGN:
9649 /* No relaxation required. */
9652 case RELAX_FILL_NOP:
9653 case RELAX_UNREACHABLE:
9654 if (fragP->tc_frag_data.relax_seen)
9655 new_stretch += relax_frag_for_align (fragP, stretch);
9658 case RELAX_TRAMPOLINE:
9659 if (fragP->tc_frag_data.relax_seen)
9660 xg_relax_trampoline (fragP, stretch, &new_stretch);
9664 as_bad (_("bad relaxation state"));
9667 /* Tell gas we need another relaxation pass. */
9668 if (! fragP->tc_frag_data.relax_seen)
9670 fragP->tc_frag_data.relax_seen = TRUE;
9674 new_logical_line (file_name, line);
9680 relax_frag_loop_align (fragS *fragP, long stretch)
9682 addressT old_address, old_next_address, old_size;
9683 addressT new_address, new_next_address, new_size;
9686 /* All the frags with relax_frag_for_alignment prior to this one in the
9687 section have been done, hopefully eliminating the need for a NOP here.
9688 But, this will put it in if necessary. */
9690 /* Calculate the old address of this fragment and the next fragment. */
9691 old_address = fragP->fr_address - stretch;
9692 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
9693 fragP->tc_frag_data.text_expansion[0]);
9694 old_size = old_next_address - old_address;
9696 /* Calculate the new address of this fragment and the next fragment. */
9697 new_address = fragP->fr_address;
9699 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
9700 new_size = new_next_address - new_address;
9702 growth = new_size - old_size;
9704 /* Fix up the text_expansion field and return the new growth. */
9705 fragP->tc_frag_data.text_expansion[0] += growth;
9710 /* Add a NOP instruction. */
9713 relax_frag_add_nop (fragS *fragP)
9715 char *nop_buf = fragP->fr_literal + fragP->fr_fix;
9716 int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
9717 assemble_nop (length, nop_buf);
9718 fragP->tc_frag_data.is_insn = TRUE;
9720 if (fragP->fr_var < length)
9722 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
9726 fragP->fr_fix += length;
9727 fragP->fr_var -= length;
9732 static long future_alignment_required (fragS *, long);
9735 relax_frag_for_align (fragS *fragP, long stretch)
9737 /* Overview of the relaxation procedure for alignment:
9738 We can widen with NOPs or by widening instructions or by filling
9739 bytes after jump instructions. Find the opportune places and widen
9740 them if necessary. */
9745 gas_assert (fragP->fr_subtype == RELAX_FILL_NOP
9746 || fragP->fr_subtype == RELAX_UNREACHABLE
9747 || (fragP->fr_subtype == RELAX_SLOTS
9748 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
9750 stretch_me = future_alignment_required (fragP, stretch);
9751 diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
9757 /* We expanded on a previous pass. Can we shrink now? */
9758 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
9759 if (shrink <= stretch && stretch > 0)
9761 fragP->tc_frag_data.text_expansion[0] = stretch_me;
9767 /* Below here, diff > 0. */
9768 fragP->tc_frag_data.text_expansion[0] = stretch_me;
9774 /* Return the address of the next frag that should be aligned.
9776 By "address" we mean the address it _would_ be at if there
9777 is no action taken to align it between here and the target frag.
9778 In other words, if no narrows and no fill nops are used between
9779 here and the frag to align, _even_if_ some of the frags we use
9780 to align targets have already expanded on a previous relaxation
9783 Also, count each frag that may be used to help align the target.
9785 Return 0 if there are no frags left in the chain that need to be
9789 find_address_of_next_align_frag (fragS **fragPP,
9793 bfd_boolean *paddable)
9795 fragS *fragP = *fragPP;
9796 addressT address = fragP->fr_address;
9798 /* Do not reset the counts to 0. */
9802 /* Limit this to a small search. */
9803 if (*widens >= (int) xtensa_fetch_width)
9808 address += fragP->fr_fix;
9810 if (fragP->fr_type == rs_fill)
9811 address += fragP->fr_offset * fragP->fr_var;
9812 else if (fragP->fr_type == rs_machine_dependent)
9814 switch (fragP->fr_subtype)
9816 case RELAX_UNREACHABLE:
9820 case RELAX_FILL_NOP:
9822 if (!fragP->tc_frag_data.is_no_density)
9827 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9832 address += total_frag_text_expansion (fragP);
9836 address += fragP->tc_frag_data.text_expansion[0];
9839 case RELAX_ALIGN_NEXT_OPCODE:
9840 case RELAX_DESIRE_ALIGN:
9844 case RELAX_MAYBE_UNREACHABLE:
9845 case RELAX_MAYBE_DESIRE_ALIGN:
9850 /* Just punt if we don't know the type. */
9857 /* Just punt if we don't know the type. */
9861 fragP = fragP->fr_next;
9869 static long bytes_to_stretch (fragS *, int, int, int, int);
9872 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
9874 fragS *this_frag = fragP;
9878 int narrow_nops = 0;
9879 bfd_boolean paddable = FALSE;
9880 offsetT local_opt_diff;
9883 int stretch_amount = 0;
9884 int local_stretch_amount;
9885 int global_stretch_amount;
9887 address = find_address_of_next_align_frag
9888 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
9892 if (this_frag->tc_frag_data.is_aligning_branch)
9893 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
9895 frag_wane (this_frag);
9899 local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
9900 opt_diff = local_opt_diff;
9901 gas_assert (opt_diff >= 0);
9902 gas_assert (max_diff >= opt_diff);
9907 fragP = fragP->fr_next;
9909 while (fragP && opt_diff < max_diff && address)
9911 /* We only use these to determine if we can exit early
9912 because there will be plenty of ways to align future
9914 int glob_widens = 0;
9917 bfd_boolean glob_pad = 0;
9918 address = find_address_of_next_align_frag
9919 (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
9920 /* If there is a padable portion, then skip. */
9921 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
9926 offsetT next_m_diff;
9927 offsetT next_o_diff;
9929 /* Downrange frags haven't had stretch added to them yet. */
9932 /* The address also includes any text expansion from this
9933 frag in a previous pass, but we don't want that. */
9934 address -= this_frag->tc_frag_data.text_expansion[0];
9936 /* Assume we are going to move at least opt_diff. In
9937 reality, we might not be able to, but assuming that
9938 we will helps catch cases where moving opt_diff pushes
9939 the next target from aligned to unaligned. */
9940 address += opt_diff;
9942 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
9944 /* Now cleanup for the adjustments to address. */
9945 next_o_diff += opt_diff;
9946 next_m_diff += opt_diff;
9947 if (next_o_diff <= max_diff && next_o_diff > opt_diff)
9948 opt_diff = next_o_diff;
9949 if (next_m_diff < max_diff)
9950 max_diff = next_m_diff;
9951 fragP = fragP->fr_next;
9955 /* If there are enough wideners in between, do it. */
9958 if (this_frag->fr_subtype == RELAX_UNREACHABLE)
9960 gas_assert (opt_diff <= (signed) xtensa_fetch_width);
9965 local_stretch_amount
9966 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9967 num_widens, local_opt_diff);
9968 global_stretch_amount
9969 = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9970 num_widens, opt_diff);
9971 /* If the condition below is true, then the frag couldn't
9972 stretch the correct amount for the global case, so we just
9973 optimize locally. We'll rely on the subsequent frags to get
9974 the correct alignment in the global case. */
9975 if (global_stretch_amount < local_stretch_amount)
9976 stretch_amount = local_stretch_amount;
9978 stretch_amount = global_stretch_amount;
9980 if (this_frag->fr_subtype == RELAX_SLOTS
9981 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9982 gas_assert (stretch_amount <= 1);
9983 else if (this_frag->fr_subtype == RELAX_FILL_NOP)
9985 if (this_frag->tc_frag_data.is_no_density)
9986 gas_assert (stretch_amount == 3 || stretch_amount == 0);
9988 gas_assert (stretch_amount <= 3);
9991 return stretch_amount;
9995 /* The idea: widen everything you can to get a target or loop aligned,
9996 then start using NOPs.
9998 wide_nops = the number of wide NOPs available for aligning
9999 narrow_nops = the number of narrow NOPs available for aligning
10000 (a subset of wide_nops)
10001 widens = the number of narrow instructions that should be widened
10006 bytes_to_stretch (fragS *this_frag,
10015 int bytes_short = desired_diff - num_widens;
10017 gas_assert (desired_diff >= 0
10018 && desired_diff < (signed) xtensa_fetch_width);
10019 if (desired_diff == 0)
10022 gas_assert (wide_nops > 0 || num_widens > 0);
10024 /* Always prefer widening to NOP-filling. */
10025 if (bytes_short < 0)
10027 /* There are enough RELAX_NARROW frags after this one
10028 to align the target without widening this frag in any way. */
10032 if (bytes_short == 0)
10034 /* Widen every narrow between here and the align target
10035 and the align target will be properly aligned. */
10036 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10042 /* From here we will need at least one NOP to get an alignment.
10043 However, we may not be able to align at all, in which case,
10045 nops_needed = desired_diff / 3;
10047 /* If there aren't enough nops, don't widen. */
10048 if (nops_needed > wide_nops)
10051 /* First try it with all wide nops. */
10052 nop_bytes = nops_needed * 3;
10053 extra_bytes = desired_diff - nop_bytes;
10055 if (nop_bytes + num_widens >= desired_diff)
10057 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10059 else if (num_widens == extra_bytes)
10064 /* Add a narrow nop. */
10068 if (narrow_nops == 0 || nops_needed > wide_nops)
10071 if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0)
10073 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10074 return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10075 else if (num_widens == extra_bytes)
10080 /* Replace a wide nop with a narrow nop--we can get here if
10081 extra_bytes was negative in the previous conditional. */
10082 if (narrow_nops == 1)
10086 if (nop_bytes + num_widens >= desired_diff)
10088 if (this_frag->fr_subtype == RELAX_FILL_NOP)
10089 return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10090 else if (num_widens == extra_bytes)
10095 /* If we can't satisfy any of the above cases, then we can't align
10096 using padding or fill nops. */
10102 xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP)
10104 symbolS *sym = tinsn->tok[0].X_add_symbol;
10105 addressT source = fragP->fr_address;
10106 addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number;
10107 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10110 if (!ts || !ts->index.n_entries)
10113 i = xg_find_best_trampoline (&ts->index, source, target);
10115 return ts->index.entry[i];
10119 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10120 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10121 and finish the frag if it's full (but don't remove it from the trampoline
10122 frag index). Return fixup for the newly created jump. */
10123 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset)
10128 xtensa_isa isa = xtensa_default_isa;
10130 gas_assert (fragP->fr_var >= 3);
10131 tinsn_init (&insn);
10132 insn.insn_type = ITYPE_INSN;
10133 insn.opcode = xtensa_j_opcode;
10135 set_expr_symbol_offset (&insn.tok[0], sym, offset);
10136 fmt = xg_get_single_format (xtensa_j_opcode);
10137 tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
10138 xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
10139 xtensa_insnbuf_to_chars (isa, trampoline_buf,
10140 (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3);
10141 fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, TRUE,
10142 BFD_RELOC_XTENSA_SLOT0_OP);
10143 fixP->tc_fix_data.slot = 0;
10145 fragP->fr_fix += 3;
10146 fragP->fr_var -= 3;
10148 /* Adjust the jump around this trampoline (if present). */
10149 if (fragP->tc_frag_data.jump_around_fix)
10150 fragP->tc_frag_data.jump_around_fix->fx_offset += 3;
10152 /* Do we have room for more? */
10153 if (xg_is_trampoline_frag_full (fragP))
10156 fragP->fr_subtype = 0;
10164 init_trampoline_frag (fragS *fp)
10168 if (fp->fr_fix == 0)
10171 char label[10 + 2 * sizeof(fp)];
10173 sprintf (label, ".L0_TR_%p", fp);
10174 lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp);
10175 fp->fr_symbol = lsym;
10176 if (fp->tc_frag_data.needs_jump_around)
10178 fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3);
10186 xg_get_single_symbol_slot (fragS *fragP)
10191 for (i = 0; i < MAX_SLOTS; ++i)
10192 if (fragP->tc_frag_data.slot_symbols[i])
10194 gas_assert (slot == -1);
10198 gas_assert (slot >= 0 && slot < MAX_SLOTS);
10204 add_jump_to_trampoline (fragS *tramp, fragS *origfrag)
10206 int slot = xg_get_single_symbol_slot (origfrag);
10209 /* Assemble a jump to the target label in the trampoline frag. */
10210 fixP = xg_append_jump (tramp,
10211 origfrag->tc_frag_data.slot_symbols[slot],
10212 origfrag->tc_frag_data.slot_offsets[slot]);
10214 /* Modify the original j to point here. */
10215 origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol;
10216 origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3;
10218 /* If trampoline is full, remove it from the list. */
10219 if (xg_is_trampoline_frag_full (tramp))
10221 struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10222 size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address);
10224 gas_assert (ts->index.entry[tr] == tramp);
10225 xg_remove_trampoline_from_index (&ts->index, tr);
10233 relax_frag_immed (segT segP,
10240 bfd_boolean estimate_only)
10244 bfd_boolean negatable_branch = FALSE;
10245 bfd_boolean branch_jmp_to_next = FALSE;
10246 bfd_boolean from_wide_insn = FALSE;
10247 xtensa_isa isa = xtensa_default_isa;
10249 offsetT frag_offset;
10251 int num_text_bytes, num_literal_bytes;
10252 int literal_diff, total_text_diff, this_text_diff;
10254 gas_assert (fragP->fr_opcode != NULL);
10256 xg_clear_vinsn (&cur_vinsn);
10257 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
10258 if (cur_vinsn.num_slots > 1)
10259 from_wide_insn = TRUE;
10261 tinsn = cur_vinsn.slots[slot];
10262 tinsn_immed_from_frag (&tinsn, fragP, slot);
10264 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
10267 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10268 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
10270 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
10272 old_size = xtensa_format_length (isa, fmt);
10274 /* Special case: replace a branch to the next instruction with a NOP.
10275 This is required to work around a hardware bug in T1040.0 and also
10276 serves as an optimization. */
10278 if (branch_jmp_to_next
10279 && ((old_size == 2) || (old_size == 3))
10280 && !next_frag_is_loop_target (fragP))
10283 /* Here is the fun stuff: Get the immediate field from this
10284 instruction. If it fits, we are done. If not, find the next
10285 instruction sequence that fits. */
10287 frag_offset = fragP->fr_opcode - fragP->fr_literal;
10288 istack_init (&istack);
10289 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
10290 min_steps, stretch);
10291 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10293 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
10295 /* Figure out the number of bytes needed. */
10296 num_literal_bytes = get_num_stack_literal_bytes (&istack);
10298 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10299 num_text_bytes = get_num_stack_text_bytes (&istack);
10301 if (from_wide_insn)
10304 while (istack.insn[first].opcode == XTENSA_UNDEFINED)
10307 num_text_bytes += old_size;
10308 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
10309 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
10312 /* The first instruction in the relaxed sequence will go after
10313 the current wide instruction, and thus its symbolic immediates
10316 istack_init (&istack);
10317 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
10318 frag_offset + old_size,
10319 min_steps, stretch + old_size);
10320 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10322 fragP->tc_frag_data.slot_subtypes[slot]
10323 = (int) RELAX_IMMED + num_steps;
10325 num_literal_bytes = get_num_stack_literal_bytes (&istack);
10327 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10329 num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
10333 total_text_diff = num_text_bytes - old_size;
10334 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
10336 /* It MUST get larger. If not, we could get an infinite loop. */
10337 gas_assert (num_text_bytes >= 0);
10338 gas_assert (literal_diff >= 0);
10339 gas_assert (total_text_diff >= 0);
10341 fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
10342 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
10343 gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
10344 gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
10346 /* Find the associated expandable literal for this. */
10347 if (literal_diff != 0)
10349 fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot];
10352 gas_assert (literal_diff == 4);
10353 lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
10355 /* We expect that the literal section state has NOT been
10357 gas_assert (lit_fragP->fr_type == rs_machine_dependent
10358 && lit_fragP->fr_subtype == RELAX_LITERAL);
10359 lit_fragP->fr_subtype = RELAX_LITERAL_NR;
10361 /* We need to mark this section for another iteration
10367 if (negatable_branch && istack.ninsn > 1)
10368 update_next_frag_state (fragP);
10370 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10371 if (istack.ninsn > 2 &&
10372 istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL &&
10373 istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN &&
10374 istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode)
10376 TInsn *jinsn = &istack.insn[istack.ninsn - 2];
10377 struct trampoline_seg *ts = find_trampoline_seg (segP);
10378 struct trampoline_chain *tc = NULL;
10381 !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10384 int s = xg_get_single_symbol_slot (fragP);
10385 addressT offset = fragP->tc_frag_data.slot_offsets[s];
10387 tc = xg_find_best_eq_target (ts, fragP->fr_address,
10388 &fragP->tc_frag_data.slot_symbols[s],
10392 tc = xg_create_trampoline_chain (ts,
10393 fragP->tc_frag_data.slot_symbols[s],
10395 fragP->tc_frag_data.slot_offsets[s] = offset;
10396 tinsn_immed_from_frag (jinsn, fragP, s);
10399 if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10402 fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP);
10408 this_text_diff += init_trampoline_frag (tf) + 3;
10409 fixP = add_jump_to_trampoline (tf, fragP);
10410 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
10412 fragP->tc_frag_data.relax_seen = FALSE;
10416 /* If target symbol is undefined, assume it will reach once linked. */
10417 expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0];
10419 if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol))
10421 as_bad_where (fragP->fr_file, fragP->fr_line,
10422 _("jump target out of range; no usable trampoline found"));
10428 return this_text_diff;
10432 /* md_convert_frag Hook and Helper Functions. */
10434 static void convert_frag_align_next_opcode (fragS *);
10435 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
10436 static void convert_frag_fill_nop (fragS *);
10437 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
10440 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
10442 static xtensa_insnbuf vbuf = NULL;
10443 xtensa_isa isa = xtensa_default_isa;
10447 const char *file_name;
10450 file_name = as_where (&line);
10451 new_logical_line (fragp->fr_file, fragp->fr_line);
10453 switch (fragp->fr_subtype)
10455 case RELAX_ALIGN_NEXT_OPCODE:
10456 /* Always convert. */
10457 convert_frag_align_next_opcode (fragp);
10460 case RELAX_DESIRE_ALIGN:
10461 /* Do nothing. If not aligned already, too bad. */
10464 case RELAX_LITERAL:
10465 case RELAX_LITERAL_FINAL:
10470 vbuf = xtensa_insnbuf_alloc (isa);
10472 xtensa_insnbuf_from_chars
10473 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
10474 fmt = xtensa_format_decode (isa, vbuf);
10475 num_slots = xtensa_format_num_slots (isa, fmt);
10477 for (slot = 0; slot < num_slots; slot++)
10479 switch (fragp->tc_frag_data.slot_subtypes[slot])
10482 convert_frag_narrow (sec, fragp, fmt, slot);
10486 case RELAX_IMMED_STEP1:
10487 case RELAX_IMMED_STEP2:
10488 case RELAX_IMMED_STEP3:
10489 /* Place the immediate. */
10492 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
10497 /* This is OK because some slots could have
10498 relaxations and others have none. */
10504 case RELAX_UNREACHABLE:
10505 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
10506 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
10507 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
10511 case RELAX_MAYBE_UNREACHABLE:
10512 case RELAX_MAYBE_DESIRE_ALIGN:
10516 case RELAX_FILL_NOP:
10517 convert_frag_fill_nop (fragp);
10520 case RELAX_LITERAL_NR:
10521 if (use_literal_section)
10523 /* This should have been handled during relaxation. When
10524 relaxing a code segment, literals sometimes need to be
10525 added to the corresponding literal segment. If that
10526 literal segment has already been relaxed, then we end up
10527 in this situation. Marking the literal segments as data
10528 would make this happen less often (since GAS always relaxes
10529 code before data), but we could still get into trouble if
10530 there are instructions in a segment that is not marked as
10531 containing code. Until we can implement a better solution,
10532 cheat and adjust the addresses of all the following frags.
10533 This could break subsequent alignments, but the linker's
10534 literal coalescing will do that anyway. */
10537 fragp->fr_subtype = RELAX_LITERAL_FINAL;
10538 gas_assert (fragp->tc_frag_data.unreported_expansion == 4);
10539 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
10540 fragp->fr_var -= 4;
10541 fragp->fr_fix += 4;
10542 for (f = fragp->fr_next; f; f = f->fr_next)
10543 f->fr_address += 4;
10546 as_bad (_("invalid relaxation fragment result"));
10549 case RELAX_TRAMPOLINE:
10554 new_logical_line (file_name, line);
10559 convert_frag_align_next_opcode (fragS *fragp)
10561 char *nop_buf; /* Location for Writing. */
10562 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
10563 addressT aligned_address;
10565 int nop, nop_count;
10567 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
10569 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
10570 nop_count = get_text_align_nop_count (fill_size, use_no_density);
10571 nop_buf = fragp->fr_literal + fragp->fr_fix;
10573 for (nop = 0; nop < nop_count; nop++)
10576 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
10578 assemble_nop (nop_size, nop_buf);
10579 nop_buf += nop_size;
10582 fragp->fr_fix += fill_size;
10583 fragp->fr_var -= fill_size;
10588 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
10590 TInsn tinsn, single_target;
10591 int size, old_size, diff;
10592 offsetT frag_offset;
10594 gas_assert (slot == 0);
10595 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
10597 if (fragP->tc_frag_data.is_aligning_branch == 1)
10599 gas_assert (fragP->tc_frag_data.text_expansion[0] == 1
10600 || fragP->tc_frag_data.text_expansion[0] == 0);
10601 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
10606 if (fragP->tc_frag_data.text_expansion[0] == 0)
10608 /* No conversion. */
10613 gas_assert (fragP->fr_opcode != NULL);
10615 /* Frags in this relaxation state should only contain
10616 single instruction bundles. */
10617 tinsn_immed_from_frag (&tinsn, fragP, 0);
10619 /* Just convert it to a wide form.... */
10621 old_size = xg_get_single_size (tinsn.opcode);
10623 tinsn_init (&single_target);
10624 frag_offset = fragP->fr_opcode - fragP->fr_literal;
10626 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
10628 as_bad (_("unable to widen instruction"));
10632 size = xg_get_single_size (single_target.opcode);
10633 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
10634 frag_offset, TRUE);
10636 diff = size - old_size;
10637 gas_assert (diff >= 0);
10638 gas_assert (diff <= fragP->fr_var);
10639 fragP->fr_var -= diff;
10640 fragP->fr_fix += diff;
10648 convert_frag_fill_nop (fragS *fragP)
10650 char *loc = &fragP->fr_literal[fragP->fr_fix];
10651 int size = fragP->tc_frag_data.text_expansion[0];
10652 gas_assert ((unsigned) size == (fragP->fr_next->fr_address
10653 - fragP->fr_address - fragP->fr_fix));
10656 /* No conversion. */
10660 assemble_nop (size, loc);
10661 fragP->tc_frag_data.is_insn = TRUE;
10662 fragP->fr_var -= size;
10663 fragP->fr_fix += size;
10668 static fixS *fix_new_exp_in_seg
10669 (segT, subsegT, fragS *, int, int, expressionS *, int,
10670 bfd_reloc_code_real_type);
10671 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
10674 convert_frag_immed (segT segP,
10680 char *immed_instr = fragP->fr_opcode;
10682 bfd_boolean expanded = FALSE;
10683 bfd_boolean branch_jmp_to_next = FALSE;
10684 char *fr_opcode = fragP->fr_opcode;
10685 xtensa_isa isa = xtensa_default_isa;
10686 bfd_boolean from_wide_insn = FALSE;
10688 bfd_boolean is_loop;
10690 gas_assert (fr_opcode != NULL);
10692 xg_clear_vinsn (&cur_vinsn);
10694 vinsn_from_chars (&cur_vinsn, fr_opcode);
10695 if (cur_vinsn.num_slots > 1)
10696 from_wide_insn = TRUE;
10698 orig_tinsn = cur_vinsn.slots[slot];
10699 tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
10701 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
10703 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10704 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
10706 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
10708 /* Conversion just inserts a NOP and marks the fix as completed. */
10709 bytes = xtensa_format_length (isa, fmt);
10712 cur_vinsn.slots[slot].opcode =
10713 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
10714 cur_vinsn.slots[slot].ntok = 0;
10718 bytes += fragP->tc_frag_data.text_expansion[0];
10719 gas_assert (bytes == 2 || bytes == 3);
10720 build_nop (&cur_vinsn.slots[0], bytes);
10721 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
10723 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
10724 xtensa_insnbuf_to_chars
10725 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
10730 /* Here is the fun stuff: Get the immediate field from this
10731 instruction. If it fits, we're done. If not, find the next
10732 instruction sequence that fits. */
10736 symbolS *lit_sym = NULL;
10737 int total_size = 0;
10738 int target_offset = 0;
10741 symbolS *gen_label = NULL;
10742 offsetT frag_offset;
10743 bfd_boolean first = TRUE;
10745 /* It does not fit. Find something that does and
10746 convert immediately. */
10747 frag_offset = fr_opcode - fragP->fr_literal;
10748 istack_init (&istack);
10749 xg_assembly_relax (&istack, &orig_tinsn,
10750 segP, fragP, frag_offset, min_steps, 0);
10752 old_size = xtensa_format_length (isa, fmt);
10754 /* Assemble this right inline. */
10756 /* First, create the mapping from a label name to the REAL label. */
10758 for (i = 0; i < istack.ninsn; i++)
10760 TInsn *tinsn = &istack.insn[i];
10763 switch (tinsn->insn_type)
10765 case ITYPE_LITERAL:
10766 if (lit_sym != NULL)
10767 as_bad (_("multiple literals in expansion"));
10768 /* First find the appropriate space in the literal pool. */
10769 lit_frag = fragP->tc_frag_data.literal_frags[slot];
10770 if (lit_frag == NULL)
10771 as_bad (_("no registered fragment for literal"));
10772 if (tinsn->ntok != 1)
10773 as_bad (_("number of literal tokens != 1"));
10775 /* Set the literal symbol and add a fixup. */
10776 lit_sym = lit_frag->fr_symbol;
10780 if (align_targets && !is_loop)
10782 fragS *unreach = fragP->fr_next;
10783 while (!(unreach->fr_type == rs_machine_dependent
10784 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10785 || unreach->fr_subtype == RELAX_UNREACHABLE)))
10787 unreach = unreach->fr_next;
10790 gas_assert (unreach->fr_type == rs_machine_dependent
10791 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10792 || unreach->fr_subtype == RELAX_UNREACHABLE));
10794 target_offset += unreach->tc_frag_data.text_expansion[0];
10796 gas_assert (gen_label == NULL);
10797 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
10798 fr_opcode - fragP->fr_literal
10799 + target_offset, fragP);
10803 if (first && from_wide_insn)
10805 target_offset += xtensa_format_length (isa, fmt);
10807 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10808 target_offset += xg_get_single_size (tinsn->opcode);
10811 target_offset += xg_get_single_size (tinsn->opcode);
10818 for (i = 0; i < istack.ninsn; i++)
10820 TInsn *tinsn = &istack.insn[i];
10824 bfd_reloc_code_real_type reloc_type;
10826 switch (tinsn->insn_type)
10828 case ITYPE_LITERAL:
10829 lit_frag = fragP->tc_frag_data.literal_frags[slot];
10830 /* Already checked. */
10831 gas_assert (lit_frag != NULL);
10832 gas_assert (lit_sym != NULL);
10833 gas_assert (tinsn->ntok == 1);
10835 target_seg = S_GET_SEGMENT (lit_sym);
10836 gas_assert (target_seg);
10837 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE);
10838 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
10839 &tinsn->tok[0], FALSE, reloc_type);
10846 xg_resolve_labels (tinsn, gen_label);
10847 xg_resolve_literals (tinsn, lit_sym);
10848 if (from_wide_insn && first)
10851 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10853 cur_vinsn.slots[slot] = *tinsn;
10857 cur_vinsn.slots[slot].opcode =
10858 xtensa_format_slot_nop_opcode (isa, fmt, slot);
10859 cur_vinsn.slots[slot].ntok = 0;
10861 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
10862 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
10863 (unsigned char *) immed_instr, 0);
10864 fragP->tc_frag_data.is_insn = TRUE;
10865 size = xtensa_format_length (isa, fmt);
10866 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10868 xg_emit_insn_to_buf
10869 (tinsn, immed_instr + size, fragP,
10870 immed_instr - fragP->fr_literal + size, TRUE);
10871 size += xg_get_single_size (tinsn->opcode);
10876 size = xg_get_single_size (tinsn->opcode);
10877 xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
10878 immed_instr - fragP->fr_literal, TRUE);
10880 immed_instr += size;
10881 total_size += size;
10886 diff = total_size - old_size;
10887 gas_assert (diff >= 0);
10890 gas_assert (diff <= fragP->fr_var);
10891 fragP->fr_var -= diff;
10892 fragP->fr_fix += diff;
10895 /* Check for undefined immediates in LOOP instructions. */
10899 sym = orig_tinsn.tok[1].X_add_symbol;
10900 if (sym != NULL && !S_IS_DEFINED (sym))
10902 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10905 sym = orig_tinsn.tok[1].X_op_symbol;
10906 if (sym != NULL && !S_IS_DEFINED (sym))
10908 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10913 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
10914 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
10916 if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
10918 /* Add an expansion note on the expanded instruction. */
10919 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
10920 &orig_tinsn.tok[0], TRUE,
10921 BFD_RELOC_XTENSA_ASM_EXPAND);
10926 /* Add a new fix expression into the desired segment. We have to
10927 switch to that segment to do this. */
10930 fix_new_exp_in_seg (segT new_seg,
10931 subsegT new_subseg,
10937 bfd_reloc_code_real_type r_type)
10940 segT seg = now_seg;
10941 subsegT subseg = now_subseg;
10943 gas_assert (new_seg != 0);
10944 subseg_set (new_seg, new_subseg);
10946 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
10947 subseg_set (seg, subseg);
10952 /* Relax a loop instruction so that it can span loop >256 bytes.
10958 addi as, as, lo8 (label-.L1)
10959 addmi as, as, mid8 (label-.L1)
10970 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
10975 unsigned long target;
10976 static xtensa_insnbuf insnbuf = NULL;
10977 unsigned int loop_length, loop_length_hi, loop_length_lo;
10978 xtensa_isa isa = xtensa_default_isa;
10979 addressT loop_offset;
10980 addressT addi_offset = 9;
10981 addressT addmi_offset = 12;
10986 insnbuf = xtensa_insnbuf_alloc (isa);
10988 /* Get the loop offset. */
10989 loop_offset = get_expanded_loop_offset (tinsn->opcode);
10991 /* Validate that there really is a LOOP at the loop_offset. Because
10992 loops are not bundleable, we can assume that the instruction will be
10994 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
10995 tinsn_immed_from_frag (&loop_insn, fragP, 0);
10997 gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
10998 addi_offset += loop_offset;
10999 addmi_offset += loop_offset;
11001 gas_assert (tinsn->ntok == 2);
11002 if (tinsn->tok[1].X_op == O_constant)
11003 target = tinsn->tok[1].X_add_number;
11004 else if (tinsn->tok[1].X_op == O_symbol)
11006 /* Find the fragment. */
11007 symbolS *sym = tinsn->tok[1].X_add_symbol;
11008 gas_assert (S_GET_SEGMENT (sym) == segP
11009 || S_GET_SEGMENT (sym) == absolute_section);
11010 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
11014 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
11018 loop_length = target - (fragP->fr_address + fragP->fr_fix);
11019 loop_length_hi = loop_length & ~0x0ff;
11020 loop_length_lo = loop_length & 0x0ff;
11021 if (loop_length_lo >= 128)
11023 loop_length_lo -= 256;
11024 loop_length_hi += 256;
11027 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
11028 32512. If the loop is larger than that, then we just fail. */
11029 if (loop_length_hi > 32512)
11030 as_bad_where (fragP->fr_file, fragP->fr_line,
11031 _("loop too long for LOOP instruction"));
11033 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
11034 gas_assert (addi_insn.opcode == xtensa_addi_opcode);
11036 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
11037 gas_assert (addmi_insn.opcode == xtensa_addmi_opcode);
11039 set_expr_const (&addi_insn.tok[2], loop_length_lo);
11040 tinsn_to_insnbuf (&addi_insn, insnbuf);
11042 fragP->tc_frag_data.is_insn = TRUE;
11043 xtensa_insnbuf_to_chars
11044 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
11046 set_expr_const (&addmi_insn.tok[2], loop_length_hi);
11047 tinsn_to_insnbuf (&addmi_insn, insnbuf);
11048 xtensa_insnbuf_to_chars
11049 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
11051 /* Walk through all of the frags from here to the loop end
11052 and mark them as no_transform to keep them from being modified
11053 by the linker. If we ever have a relocation for the
11054 addi/addmi of the difference of two symbols we can remove this. */
11057 for (next_fragP = fragP; next_fragP != NULL;
11058 next_fragP = next_fragP->fr_next)
11060 next_fragP->tc_frag_data.is_no_transform = TRUE;
11061 if (next_fragP->tc_frag_data.is_loop_target)
11063 if (target_count == 2)
11069 /* A map that keeps information on a per-subsegment basis. This is
11070 maintained during initial assembly, but is invalid once the
11071 subsegments are smashed together. I.E., it cannot be used during
11074 typedef struct subseg_map_struct
11082 float total_freq; /* fall-through + branch target frequency */
11083 float target_freq; /* branch target frequency alone */
11085 struct subseg_map_struct *next;
11089 static subseg_map *sseg_map = NULL;
11091 static subseg_map *
11092 get_subseg_info (segT seg, subsegT subseg)
11094 subseg_map *subseg_e;
11096 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
11098 if (seg == subseg_e->seg && subseg == subseg_e->subseg)
11105 static subseg_map *
11106 add_subseg_info (segT seg, subsegT subseg)
11108 subseg_map *subseg_e = XNEW (subseg_map);
11109 memset (subseg_e, 0, sizeof (subseg_map));
11110 subseg_e->seg = seg;
11111 subseg_e->subseg = subseg;
11112 subseg_e->flags = 0;
11113 /* Start off considering every branch target very important. */
11114 subseg_e->target_freq = 1.0;
11115 subseg_e->total_freq = 1.0;
11116 subseg_e->next = sseg_map;
11117 sseg_map = subseg_e;
11123 get_last_insn_flags (segT seg, subsegT subseg)
11125 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11127 return subseg_e->flags;
11133 set_last_insn_flags (segT seg,
11138 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11140 subseg_e = add_subseg_info (seg, subseg);
11142 subseg_e->flags |= fl;
11144 subseg_e->flags &= ~fl;
11149 get_subseg_total_freq (segT seg, subsegT subseg)
11151 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11153 return subseg_e->total_freq;
11159 get_subseg_target_freq (segT seg, subsegT subseg)
11161 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11163 return subseg_e->target_freq;
11169 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
11171 subseg_map *subseg_e = get_subseg_info (seg, subseg);
11173 subseg_e = add_subseg_info (seg, subseg);
11174 subseg_e->total_freq = total_f;
11175 subseg_e->target_freq = target_f;
11179 /* Segment Lists and emit_state Stuff. */
11182 xtensa_move_seg_list_to_beginning (seg_list *head)
11187 segT literal_section = head->seg;
11189 /* Move the literal section to the front of the section list. */
11190 gas_assert (literal_section);
11191 if (literal_section != stdoutput->sections)
11193 bfd_section_list_remove (stdoutput, literal_section);
11194 bfd_section_list_prepend (stdoutput, literal_section);
11201 static void mark_literal_frags (seg_list *);
11204 xg_promote_candidate_litpool (struct litpool_seg *lps,
11205 struct litpool_frag *lp)
11210 char label[10 + 2 * sizeof (fragS *)];
11212 poolbeg = lp->fragP;
11214 poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN;
11215 poolend = poolbeg->fr_next;
11216 gas_assert (poolend->fr_type == rs_machine_dependent &&
11217 poolend->fr_subtype == RELAX_LITERAL_POOL_END);
11218 /* Create a local symbol pointing to the
11219 end of the pool. */
11220 sprintf (label, ".L0_LT_%p", poolbeg);
11221 lsym = (symbolS *)local_symbol_make (label, lps->seg,
11223 poolbeg->fr_symbol = lsym;
11224 /* Rest is done in xtensa_relax_frag. */
11227 static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps,
11228 struct litpool_frag *lpf,
11231 struct litpool_frag *lp = lpf->prev;
11233 gas_assert (lp->fragP);
11235 while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11238 if (lp->fragP == NULL)
11240 /* End of list; have to bite the bullet.
11241 Take the nearest. */
11245 /* Does it (conservatively) reach? */
11246 if (addr - lp->addr <= 128 * 1024)
11248 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
11249 lp->literal_count < MAX_POOL_LITERALS)
11251 /* Found a good one. */
11254 else if (lp->prev->fragP &&
11255 addr - lp->prev->addr > 128 * 1024 &&
11256 lp->prev->literal_count < MAX_POOL_LITERALS)
11258 /* This is still a "candidate" but the next one
11259 will be too far away, so revert to the nearest
11260 one, convert it and add the jump around. */
11267 if (lp->literal_count >= MAX_POOL_LITERALS)
11270 while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS)
11277 gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS);
11278 ++lp->literal_count;
11280 /* Convert candidate and add the jump around. */
11281 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11282 xg_promote_candidate_litpool (lps, lp);
11287 static bfd_boolean xtensa_is_init_fini (segT seg)
11291 return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0
11292 || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0;
11296 xtensa_move_literals (void)
11299 frchainS *frchain_from, *frchain_to;
11300 fragS *search_frag, *next_frag, *literal_pool, *insert_after;
11301 fragS **frag_splice;
11304 fixS *fix, *next_fix, **fix_splice;
11306 struct litpool_seg *lps;
11307 const char *init_name = INIT_SECTION_NAME;
11308 const char *fini_name = FINI_SECTION_NAME;
11309 int init_name_len = strlen(init_name);
11310 int fini_name_len = strlen(fini_name);
11312 mark_literal_frags (literal_head->next);
11314 if (use_literal_section)
11317 /* Assign addresses (rough estimates) to the potential literal pool locations
11318 and create new ones if the gaps are too large. */
11320 for (lps = litpool_seg_list.next; lps; lps = lps->next)
11322 frchainS *frchP = seg_info (lps->seg)->frchainP;
11323 struct litpool_frag *lpf = lps->frag_list.next;
11326 if (xtensa_is_init_fini (lps->seg))
11329 for ( ; frchP; frchP = frchP->frch_next)
11332 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
11334 if (lpf && fragP == lpf->fragP)
11336 gas_assert(fragP->fr_type == rs_machine_dependent &&
11337 (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN ||
11338 fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN));
11339 /* Found a litpool location. */
11343 if (fragP->fr_type == rs_machine_dependent &&
11344 fragP->fr_subtype == RELAX_SLOTS)
11347 for (slot = 0; slot < MAX_SLOTS; slot++)
11349 fragS *litfrag = fragP->tc_frag_data.literal_frags[slot];
11352 && litfrag->tc_frag_data.is_literal
11353 && !litfrag->tc_frag_data.literal_frag)
11355 /* L32R referring .literal or generated as a result
11356 of relaxation. Point its literal to the nearest
11357 litpool preferring non-"candidate" positions to
11358 avoid the jump-around. */
11360 struct litpool_frag *lp;
11362 lp = xg_find_litpool (lps, lpf, addr);
11363 /* Take earliest use of this literal to avoid
11365 litfrag->tc_frag_data.literal_frag = lp->fragP;
11369 addr += fragP->fr_fix;
11370 if (fragP->fr_type == rs_fill)
11371 addr += fragP->fr_offset;
11376 for (segment = literal_head->next; segment; segment = segment->next)
11378 const char *seg_name = segment_name (segment->seg);
11380 /* Keep the literals for .init and .fini in separate sections. */
11381 if ((!memcmp (seg_name, init_name, init_name_len) &&
11382 !strcmp (seg_name + init_name_len, ".literal")) ||
11383 (!memcmp (seg_name, fini_name, fini_name_len) &&
11384 !strcmp (seg_name + fini_name_len, ".literal")))
11387 frchain_from = seg_info (segment->seg)->frchainP;
11388 search_frag = frchain_from->frch_root;
11389 literal_pool = NULL;
11391 frag_splice = &(frchain_from->frch_root);
11393 while (search_frag && !search_frag->tc_frag_data.literal_frag)
11395 gas_assert (search_frag->fr_fix == 0
11396 || search_frag->fr_type == rs_align);
11397 search_frag = search_frag->fr_next;
11402 search_frag = frchain_from->frch_root;
11403 as_bad_where (search_frag->fr_file, search_frag->fr_line,
11404 _("literal pool location required for text-section-literals; specify with .literal_position"));
11408 gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype
11409 == RELAX_LITERAL_POOL_BEGIN);
11410 xtensa_switch_section_emit_state (&state, segment->seg, 0);
11412 /* Make sure that all the frags in this series are closed, and
11413 that there is at least one left over of zero-size. This
11414 prevents us from making a segment with an frchain without any
11416 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11417 xtensa_set_frag_assembly_state (frag_now);
11418 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11419 xtensa_set_frag_assembly_state (frag_now);
11421 while (search_frag != frag_now)
11423 next_frag = search_frag->fr_next;
11424 if (search_frag->tc_frag_data.literal_frag)
11426 literal_pool = search_frag->tc_frag_data.literal_frag;
11427 gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
11428 frchain_to = literal_pool->tc_frag_data.lit_frchain;
11429 gas_assert (frchain_to);
11432 if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0)
11434 /* Skip empty fill frags. */
11435 *frag_splice = next_frag;
11436 search_frag = next_frag;
11440 if (search_frag->fr_type == rs_align)
11442 /* Skip alignment frags, because the pool as a whole will be
11443 aligned if used, and we don't want to force alignment if the
11445 *frag_splice = next_frag;
11446 search_frag = next_frag;
11450 /* First, move the frag out of the literal section and
11451 to the appropriate place. */
11453 /* Insert an alignment frag at start of pool. */
11454 if (literal_pool->fr_next->fr_type == rs_machine_dependent &&
11455 literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END)
11457 segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg;
11458 emit_state prev_state;
11461 xtensa_switch_section_emit_state (&prev_state, pool_seg, 0);
11462 prev_frag = frag_now;
11463 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11464 align_frag = frag_now;
11465 frag_align (2, 0, 0);
11466 /* Splice it into the right place. */
11467 prev_frag->fr_next = align_frag->fr_next;
11468 align_frag->fr_next = literal_pool->fr_next;
11469 literal_pool->fr_next = align_frag;
11470 /* Insert after this one. */
11471 literal_pool->tc_frag_data.literal_frag = align_frag;
11472 xtensa_restore_emit_state (&prev_state);
11474 insert_after = literal_pool->tc_frag_data.literal_frag;
11475 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
11476 /* Skip align frag. */
11477 if (insert_after->fr_next->fr_type == rs_align)
11479 insert_after = insert_after->fr_next;
11482 *frag_splice = next_frag;
11483 search_frag->fr_next = insert_after->fr_next;
11484 insert_after->fr_next = search_frag;
11485 search_frag->tc_frag_data.lit_seg = dest_seg;
11486 literal_pool->tc_frag_data.literal_frag = search_frag;
11488 /* Now move any fixups associated with this frag to the
11490 fix = frchain_from->fix_root;
11491 fix_splice = &(frchain_from->fix_root);
11494 next_fix = fix->fx_next;
11495 if (fix->fx_frag == search_frag)
11497 *fix_splice = next_fix;
11498 fix->fx_next = frchain_to->fix_root;
11499 frchain_to->fix_root = fix;
11500 if (frchain_to->fix_tail == NULL)
11501 frchain_to->fix_tail = fix;
11504 fix_splice = &(fix->fx_next);
11507 search_frag = next_frag;
11510 if (frchain_from->fix_root != NULL)
11512 frchain_from = seg_info (segment->seg)->frchainP;
11513 as_warn (_("fixes not all moved from %s"), segment->seg->name);
11515 gas_assert (frchain_from->fix_root == NULL);
11517 frchain_from->fix_tail = NULL;
11518 xtensa_restore_emit_state (&state);
11521 /* Now fix up the SEGMENT value for all the literal symbols. */
11522 for (lit = literal_syms; lit; lit = lit->next)
11524 symbolS *lit_sym = lit->sym;
11525 segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
11527 S_SET_SEGMENT (lit_sym, dseg);
11532 /* Walk over all the frags for segments in a list and mark them as
11533 containing literals. As clunky as this is, we can't rely on frag_var
11534 and frag_variant to get called in all situations. */
11537 mark_literal_frags (seg_list *segment)
11539 frchainS *frchain_from;
11540 fragS *search_frag;
11544 frchain_from = seg_info (segment->seg)->frchainP;
11545 search_frag = frchain_from->frch_root;
11546 while (search_frag)
11548 search_frag->tc_frag_data.is_literal = TRUE;
11549 search_frag = search_frag->fr_next;
11551 segment = segment->next;
11557 xtensa_reorder_seg_list (seg_list *head, segT after)
11559 /* Move all of the sections in the section list to come
11560 after "after" in the gnu segment list. */
11565 segT literal_section = head->seg;
11567 /* Move the literal section after "after". */
11568 gas_assert (literal_section);
11569 if (literal_section != after)
11571 bfd_section_list_remove (stdoutput, literal_section);
11572 bfd_section_list_insert_after (stdoutput, after, literal_section);
11580 /* Push all the literal segments to the end of the gnu list. */
11583 xtensa_reorder_segments (void)
11590 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11596 /* Now that we have the last section, push all the literal
11597 sections to the end. */
11598 xtensa_reorder_seg_list (literal_head, last_sec);
11600 /* Now perform the final error check. */
11601 for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11603 gas_assert (new_count == old_count);
11607 /* Change the emit state (seg, subseg, and frag related stuff) to the
11608 correct location. Return a emit_state which can be passed to
11609 xtensa_restore_emit_state to return to current fragment. */
11612 xtensa_switch_to_literal_fragment (emit_state *result)
11614 if (directive_state[directive_absolute_literals])
11616 segT lit4_seg = cache_literal_section (TRUE);
11617 xtensa_switch_section_emit_state (result, lit4_seg, 0);
11620 xtensa_switch_to_non_abs_literal_fragment (result);
11622 /* Do a 4-byte align here. */
11623 frag_align (2, 0, 0);
11624 record_alignment (now_seg, 2);
11629 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
11631 fragS *pool_location = get_literal_pool_location (now_seg);
11633 bfd_boolean is_init_fini = xtensa_is_init_fini (now_seg);
11635 if (pool_location == NULL
11636 && !use_literal_section
11639 if (!auto_litpools)
11641 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11643 xtensa_maybe_create_literal_pool_frag (TRUE, TRUE);
11644 pool_location = get_literal_pool_location (now_seg);
11647 lit_seg = cache_literal_section (FALSE);
11648 xtensa_switch_section_emit_state (result, lit_seg, 0);
11650 if (!use_literal_section
11652 && get_literal_pool_location (now_seg) != pool_location)
11654 /* Close whatever frag is there. */
11655 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11656 xtensa_set_frag_assembly_state (frag_now);
11657 frag_now->tc_frag_data.literal_frag = pool_location;
11658 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11659 xtensa_set_frag_assembly_state (frag_now);
11664 /* Call this function before emitting data into the literal section.
11665 This is a helper function for xtensa_switch_to_literal_fragment.
11666 This is similar to a .section new_now_seg subseg. */
11669 xtensa_switch_section_emit_state (emit_state *state,
11671 subsegT new_now_subseg)
11673 state->name = now_seg->name;
11674 state->now_seg = now_seg;
11675 state->now_subseg = now_subseg;
11676 state->generating_literals = generating_literals;
11677 generating_literals++;
11678 subseg_set (new_now_seg, new_now_subseg);
11682 /* Use to restore the emitting into the normal place. */
11685 xtensa_restore_emit_state (emit_state *state)
11687 generating_literals = state->generating_literals;
11688 subseg_set (state->now_seg, state->now_subseg);
11692 /* Predicate function used to look up a section in a particular group. */
11695 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
11697 const char *gname = inf;
11698 const char *group_name = elf_group_name (sec);
11700 return (group_name == gname
11701 || (group_name != NULL
11703 && strcmp (group_name, gname) == 0));
11707 /* Get the literal section to be used for the current text section.
11708 The result may be cached in the default_lit_sections structure. */
11711 cache_literal_section (bfd_boolean use_abs_literals)
11713 const char *text_name, *group_name = 0;
11714 const char *base_name, *suffix;
11717 segT seg, current_section;
11718 int current_subsec;
11719 bfd_boolean linkonce = FALSE;
11721 /* Save the current section/subsection. */
11722 current_section = now_seg;
11723 current_subsec = now_subseg;
11725 /* Clear the cached values if they are no longer valid. */
11726 if (now_seg != default_lit_sections.current_text_seg)
11728 default_lit_sections.current_text_seg = now_seg;
11729 default_lit_sections.lit_seg = NULL;
11730 default_lit_sections.lit4_seg = NULL;
11733 /* Check if the literal section is already cached. */
11734 if (use_abs_literals)
11735 pcached = &default_lit_sections.lit4_seg;
11737 pcached = &default_lit_sections.lit_seg;
11742 text_name = default_lit_sections.lit_prefix;
11743 if (! text_name || ! *text_name)
11745 text_name = segment_name (current_section);
11746 group_name = elf_group_name (current_section);
11747 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
11750 base_name = use_abs_literals ? ".lit4" : ".literal";
11753 name = concat (base_name, ".", group_name, (char *) NULL);
11755 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
11757 suffix = strchr (text_name + linkonce_len, '.');
11759 name = concat (".gnu.linkonce", base_name, suffix ? suffix : "",
11765 /* If the section name begins or ends with ".text", then replace
11766 that portion instead of appending an additional suffix. */
11767 size_t len = strlen (text_name);
11769 && (strcmp (text_name + len - 5, ".text") == 0
11770 || strncmp (text_name, ".text", 5) == 0))
11773 name = XNEWVEC (char, len + strlen (base_name) + 1);
11774 if (strncmp (text_name, ".text", 5) == 0)
11776 strcpy (name, base_name);
11777 strcat (name, text_name + 5);
11781 strcpy (name, text_name);
11782 strcpy (name + len, base_name);
11786 /* Canonicalize section names to allow renaming literal sections.
11787 The group name, if any, came from the current text section and
11788 has already been canonicalized. */
11789 name = tc_canonicalize_symbol_name (name);
11791 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
11792 (void *) group_name);
11797 seg = subseg_force_new (name, 0);
11799 if (! use_abs_literals)
11801 /* Add the newly created literal segment to the list. */
11802 seg_list *n = XNEW (seg_list);
11804 n->next = literal_head->next;
11805 literal_head->next = n;
11808 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
11809 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
11810 | (use_abs_literals ? SEC_DATA : SEC_CODE));
11812 elf_group_name (seg) = group_name;
11814 bfd_set_section_flags (stdoutput, seg, flags);
11815 bfd_set_section_alignment (stdoutput, seg, 2);
11819 subseg_set (current_section, current_subsec);
11824 /* Property Tables Stuff. */
11826 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11827 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11828 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11830 typedef bfd_boolean (*frag_predicate) (const fragS *);
11831 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
11833 static bfd_boolean get_frag_is_literal (const fragS *);
11834 static void xtensa_create_property_segments
11835 (frag_predicate, frag_predicate, const char *, xt_section_type);
11836 static void xtensa_create_xproperty_segments
11837 (frag_flags_fn, const char *, xt_section_type);
11838 static bfd_boolean exclude_section_from_property_tables (segT);
11839 static bfd_boolean section_has_property (segT, frag_predicate);
11840 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
11841 static void add_xt_block_frags
11842 (segT, xtensa_block_info **, frag_predicate, frag_predicate);
11843 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
11844 static void xtensa_frag_flags_init (frag_flags *);
11845 static void get_frag_property_flags (const fragS *, frag_flags *);
11846 static flagword frag_flags_to_number (const frag_flags *);
11847 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn);
11849 /* Set up property tables after relaxation. */
11852 xtensa_post_relax_hook (void)
11854 xtensa_move_seg_list_to_beginning (literal_head);
11856 xtensa_find_unmarked_state_frags ();
11857 xtensa_mark_frags_for_org ();
11858 xtensa_mark_difference_of_two_symbols ();
11860 xtensa_create_property_segments (get_frag_is_literal,
11862 XTENSA_LIT_SEC_NAME,
11864 xtensa_create_xproperty_segments (get_frag_property_flags,
11865 XTENSA_PROP_SEC_NAME,
11868 if (warn_unaligned_branch_targets)
11869 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
11870 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
11874 /* This function is only meaningful after xtensa_move_literals. */
11877 get_frag_is_literal (const fragS *fragP)
11879 gas_assert (fragP != NULL);
11880 return fragP->tc_frag_data.is_literal;
11885 xtensa_create_property_segments (frag_predicate property_function,
11886 frag_predicate end_property_function,
11887 const char *section_name_base,
11888 xt_section_type sec_type)
11892 /* Walk over all of the current segments.
11893 Walk over each fragment
11894 For each non-empty fragment,
11895 Build a property record (append where possible). */
11897 for (seclist = &stdoutput->sections;
11898 seclist && *seclist;
11899 seclist = &(*seclist)->next)
11901 segT sec = *seclist;
11903 if (exclude_section_from_property_tables (sec))
11906 if (section_has_property (sec, property_function))
11908 segment_info_type *xt_seg_info;
11909 xtensa_block_info **xt_blocks;
11910 segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11912 prop_sec->output_section = prop_sec;
11913 subseg_set (prop_sec, 0);
11914 xt_seg_info = seg_info (prop_sec);
11915 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11917 /* Walk over all of the frchains here and add new sections. */
11918 add_xt_block_frags (sec, xt_blocks, property_function,
11919 end_property_function);
11923 /* Now we fill them out.... */
11925 for (seclist = &stdoutput->sections;
11926 seclist && *seclist;
11927 seclist = &(*seclist)->next)
11929 segment_info_type *seginfo;
11930 xtensa_block_info *block;
11931 segT sec = *seclist;
11933 seginfo = seg_info (sec);
11934 block = seginfo->tc_segment_info_data.blocks[sec_type];
11938 xtensa_block_info *cur_block;
11940 bfd_size_type rec_size;
11942 for (cur_block = block; cur_block; cur_block = cur_block->next)
11945 rec_size = num_recs * 8;
11946 bfd_set_section_size (stdoutput, sec, rec_size);
11953 subseg_set (sec, 0);
11954 frag_data = frag_more (rec_size);
11956 for (i = 0; i < num_recs; i++)
11960 /* Write the fixup. */
11961 gas_assert (cur_block);
11962 fix = fix_new (frag_now, i * 8, 4,
11963 section_symbol (cur_block->sec),
11965 FALSE, BFD_RELOC_32);
11966 fix->fx_file = "<internal>";
11969 /* Write the length. */
11970 md_number_to_chars (&frag_data[4 + i * 8],
11971 cur_block->size, 4);
11972 cur_block = cur_block->next;
11974 frag_wane (frag_now);
11976 frag_wane (frag_now);
11984 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
11985 const char *section_name_base,
11986 xt_section_type sec_type)
11990 /* Walk over all of the current segments.
11991 Walk over each fragment.
11992 For each fragment that has instructions,
11993 build an instruction record (append where possible). */
11995 for (seclist = &stdoutput->sections;
11996 seclist && *seclist;
11997 seclist = &(*seclist)->next)
11999 segT sec = *seclist;
12001 if (exclude_section_from_property_tables (sec))
12004 if (section_has_xproperty (sec, flag_fn))
12006 segment_info_type *xt_seg_info;
12007 xtensa_block_info **xt_blocks;
12008 segT prop_sec = xtensa_make_property_section (sec, section_name_base);
12010 prop_sec->output_section = prop_sec;
12011 subseg_set (prop_sec, 0);
12012 xt_seg_info = seg_info (prop_sec);
12013 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
12015 /* Walk over all of the frchains here and add new sections. */
12016 add_xt_prop_frags (sec, xt_blocks, flag_fn);
12020 /* Now we fill them out.... */
12022 for (seclist = &stdoutput->sections;
12023 seclist && *seclist;
12024 seclist = &(*seclist)->next)
12026 segment_info_type *seginfo;
12027 xtensa_block_info *block;
12028 segT sec = *seclist;
12030 seginfo = seg_info (sec);
12031 block = seginfo->tc_segment_info_data.blocks[sec_type];
12035 xtensa_block_info *cur_block;
12037 bfd_size_type rec_size;
12039 for (cur_block = block; cur_block; cur_block = cur_block->next)
12042 rec_size = num_recs * (8 + 4);
12043 bfd_set_section_size (stdoutput, sec, rec_size);
12044 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
12051 subseg_set (sec, 0);
12052 frag_data = frag_more (rec_size);
12054 for (i = 0; i < num_recs; i++)
12058 /* Write the fixup. */
12059 gas_assert (cur_block);
12060 fix = fix_new (frag_now, i * 12, 4,
12061 section_symbol (cur_block->sec),
12063 FALSE, BFD_RELOC_32);
12064 fix->fx_file = "<internal>";
12067 /* Write the length. */
12068 md_number_to_chars (&frag_data[4 + i * 12],
12069 cur_block->size, 4);
12070 md_number_to_chars (&frag_data[8 + i * 12],
12071 frag_flags_to_number (&cur_block->flags),
12072 sizeof (flagword));
12073 cur_block = cur_block->next;
12075 frag_wane (frag_now);
12077 frag_wane (frag_now);
12085 exclude_section_from_property_tables (segT sec)
12087 flagword flags = bfd_get_section_flags (stdoutput, sec);
12089 /* Sections that don't contribute to the memory footprint are excluded. */
12090 if ((flags & SEC_DEBUGGING)
12091 || !(flags & SEC_ALLOC)
12092 || (flags & SEC_MERGE))
12095 /* Linker cie and fde optimizations mess up property entries for
12096 eh_frame sections, but there is nothing inside them relevant to
12097 property tables anyway. */
12098 if (strcmp (sec->name, ".eh_frame") == 0)
12106 section_has_property (segT sec, frag_predicate property_function)
12108 segment_info_type *seginfo = seg_info (sec);
12111 if (seginfo && seginfo->frchainP)
12113 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
12115 if (property_function (fragP)
12116 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
12125 section_has_xproperty (segT sec, frag_flags_fn property_function)
12127 segment_info_type *seginfo = seg_info (sec);
12130 if (seginfo && seginfo->frchainP)
12132 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
12134 frag_flags prop_flags;
12135 property_function (fragP, &prop_flags);
12136 if (!xtensa_frag_flags_is_empty (&prop_flags))
12144 /* Two types of block sections exist right now: literal and insns. */
12147 add_xt_block_frags (segT sec,
12148 xtensa_block_info **xt_block,
12149 frag_predicate property_function,
12150 frag_predicate end_property_function)
12154 /* Build it if needed. */
12155 while (*xt_block != NULL)
12156 xt_block = &(*xt_block)->next;
12157 /* We are either at NULL at the beginning or at the end. */
12159 /* Walk through the frags. */
12160 if (seg_info (sec)->frchainP)
12162 for (fragP = seg_info (sec)->frchainP->frch_root;
12164 fragP = fragP->fr_next)
12166 if (property_function (fragP)
12167 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
12169 if (*xt_block != NULL)
12171 if ((*xt_block)->offset + (*xt_block)->size
12172 == fragP->fr_address)
12173 (*xt_block)->size += fragP->fr_fix;
12175 xt_block = &((*xt_block)->next);
12177 if (*xt_block == NULL)
12179 xtensa_block_info *new_block = XNEW (xtensa_block_info);
12180 new_block->sec = sec;
12181 new_block->offset = fragP->fr_address;
12182 new_block->size = fragP->fr_fix;
12183 new_block->next = NULL;
12184 xtensa_frag_flags_init (&new_block->flags);
12185 *xt_block = new_block;
12187 if (end_property_function
12188 && end_property_function (fragP))
12190 xt_block = &((*xt_block)->next);
12198 /* Break the encapsulation of add_xt_prop_frags here. */
12201 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
12203 if (prop_flags->is_literal
12204 || prop_flags->is_insn
12205 || prop_flags->is_data
12206 || prop_flags->is_unreachable)
12213 xtensa_frag_flags_init (frag_flags *prop_flags)
12215 memset (prop_flags, 0, sizeof (frag_flags));
12220 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
12222 xtensa_frag_flags_init (prop_flags);
12223 if (fragP->tc_frag_data.is_literal)
12224 prop_flags->is_literal = TRUE;
12225 if (fragP->tc_frag_data.is_specific_opcode
12226 || fragP->tc_frag_data.is_no_transform)
12228 prop_flags->is_no_transform = TRUE;
12229 if (xtensa_frag_flags_is_empty (prop_flags))
12230 prop_flags->is_data = TRUE;
12232 if (fragP->tc_frag_data.is_unreachable)
12233 prop_flags->is_unreachable = TRUE;
12234 else if (fragP->tc_frag_data.is_insn)
12236 prop_flags->is_insn = TRUE;
12237 if (fragP->tc_frag_data.is_loop_target)
12238 prop_flags->insn.is_loop_target = TRUE;
12239 if (fragP->tc_frag_data.is_branch_target)
12240 prop_flags->insn.is_branch_target = TRUE;
12241 if (fragP->tc_frag_data.is_no_density)
12242 prop_flags->insn.is_no_density = TRUE;
12243 if (fragP->tc_frag_data.use_absolute_literals)
12244 prop_flags->insn.is_abslit = TRUE;
12246 if (fragP->tc_frag_data.is_align)
12248 prop_flags->is_align = TRUE;
12249 prop_flags->alignment = fragP->tc_frag_data.alignment;
12250 if (xtensa_frag_flags_is_empty (prop_flags))
12251 prop_flags->is_data = TRUE;
12257 frag_flags_to_number (const frag_flags *prop_flags)
12260 if (prop_flags->is_literal)
12261 num |= XTENSA_PROP_LITERAL;
12262 if (prop_flags->is_insn)
12263 num |= XTENSA_PROP_INSN;
12264 if (prop_flags->is_data)
12265 num |= XTENSA_PROP_DATA;
12266 if (prop_flags->is_unreachable)
12267 num |= XTENSA_PROP_UNREACHABLE;
12268 if (prop_flags->insn.is_loop_target)
12269 num |= XTENSA_PROP_INSN_LOOP_TARGET;
12270 if (prop_flags->insn.is_branch_target)
12272 num |= XTENSA_PROP_INSN_BRANCH_TARGET;
12273 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
12276 if (prop_flags->insn.is_no_density)
12277 num |= XTENSA_PROP_INSN_NO_DENSITY;
12278 if (prop_flags->is_no_transform)
12279 num |= XTENSA_PROP_NO_TRANSFORM;
12280 if (prop_flags->insn.is_no_reorder)
12281 num |= XTENSA_PROP_INSN_NO_REORDER;
12282 if (prop_flags->insn.is_abslit)
12283 num |= XTENSA_PROP_INSN_ABSLIT;
12285 if (prop_flags->is_align)
12287 num |= XTENSA_PROP_ALIGN;
12288 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
12296 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
12297 const frag_flags *prop_flags_2)
12299 /* Cannot combine with an end marker. */
12301 if (prop_flags_1->is_literal != prop_flags_2->is_literal)
12303 if (prop_flags_1->is_insn != prop_flags_2->is_insn)
12305 if (prop_flags_1->is_data != prop_flags_2->is_data)
12308 if (prop_flags_1->is_insn)
12310 /* Properties of the beginning of the frag. */
12311 if (prop_flags_2->insn.is_loop_target)
12313 if (prop_flags_2->insn.is_branch_target)
12315 if (prop_flags_1->insn.is_no_density !=
12316 prop_flags_2->insn.is_no_density)
12318 if (prop_flags_1->is_no_transform !=
12319 prop_flags_2->is_no_transform)
12321 if (prop_flags_1->insn.is_no_reorder !=
12322 prop_flags_2->insn.is_no_reorder)
12324 if (prop_flags_1->insn.is_abslit !=
12325 prop_flags_2->insn.is_abslit)
12329 if (prop_flags_1->is_align)
12337 xt_block_aligned_size (const xtensa_block_info *xt_block)
12340 unsigned align_bits;
12342 if (!xt_block->flags.is_align)
12343 return xt_block->size;
12345 end_addr = xt_block->offset + xt_block->size;
12346 align_bits = xt_block->flags.alignment;
12347 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
12348 return end_addr - xt_block->offset;
12353 xtensa_xt_block_combine (xtensa_block_info *xt_block,
12354 const xtensa_block_info *xt_block_2)
12356 if (xt_block->sec != xt_block_2->sec)
12358 if (xt_block->offset + xt_block_aligned_size (xt_block)
12359 != xt_block_2->offset)
12362 if (xt_block_2->size == 0
12363 && (!xt_block_2->flags.is_unreachable
12364 || xt_block->flags.is_unreachable))
12366 if (xt_block_2->flags.is_align
12367 && xt_block->flags.is_align)
12369 /* Nothing needed. */
12370 if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
12375 if (xt_block_2->flags.is_align)
12377 /* Push alignment to previous entry. */
12378 xt_block->flags.is_align = xt_block_2->flags.is_align;
12379 xt_block->flags.alignment = xt_block_2->flags.alignment;
12384 if (!xtensa_frag_flags_combinable (&xt_block->flags,
12385 &xt_block_2->flags))
12388 xt_block->size += xt_block_2->size;
12390 if (xt_block_2->flags.is_align)
12392 xt_block->flags.is_align = TRUE;
12393 xt_block->flags.alignment = xt_block_2->flags.alignment;
12401 add_xt_prop_frags (segT sec,
12402 xtensa_block_info **xt_block,
12403 frag_flags_fn property_function)
12407 /* Build it if needed. */
12408 while (*xt_block != NULL)
12410 xt_block = &(*xt_block)->next;
12412 /* We are either at NULL at the beginning or at the end. */
12414 /* Walk through the frags. */
12415 if (seg_info (sec)->frchainP)
12417 for (fragP = seg_info (sec)->frchainP->frch_root; fragP;
12418 fragP = fragP->fr_next)
12420 xtensa_block_info tmp_block;
12421 tmp_block.sec = sec;
12422 tmp_block.offset = fragP->fr_address;
12423 tmp_block.size = fragP->fr_fix;
12424 tmp_block.next = NULL;
12425 property_function (fragP, &tmp_block.flags);
12427 if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
12428 /* && fragP->fr_fix != 0) */
12430 if ((*xt_block) == NULL
12431 || !xtensa_xt_block_combine (*xt_block, &tmp_block))
12433 xtensa_block_info *new_block;
12434 if ((*xt_block) != NULL)
12435 xt_block = &(*xt_block)->next;
12436 new_block = XNEW (xtensa_block_info);
12437 *new_block = tmp_block;
12438 *xt_block = new_block;
12446 /* op_placement_info_table */
12448 /* op_placement_info makes it easier to determine which
12449 ops can go in which slots. */
12452 init_op_placement_info_table (void)
12454 xtensa_isa isa = xtensa_default_isa;
12455 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
12456 xtensa_opcode opcode;
12459 int num_opcodes = xtensa_isa_num_opcodes (isa);
12461 op_placement_table = XNEWVEC (op_placement_info, num_opcodes);
12462 gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
12464 for (opcode = 0; opcode < num_opcodes; opcode++)
12466 op_placement_info *opi = &op_placement_table[opcode];
12467 /* FIXME: Make tinsn allocation dynamic. */
12468 if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS)
12469 as_fatal (_("too many operands in instruction"));
12470 opi->narrowest = XTENSA_UNDEFINED;
12471 opi->narrowest_size = 0x7F;
12472 opi->narrowest_slot = 0;
12474 opi->num_formats = 0;
12476 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
12478 opi->slots[fmt] = 0;
12479 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
12481 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
12483 int fmt_length = xtensa_format_length (isa, fmt);
12485 set_bit (fmt, opi->formats);
12486 set_bit (slot, opi->slots[fmt]);
12487 if (fmt_length < opi->narrowest_size
12488 || (fmt_length == opi->narrowest_size
12489 && (xtensa_format_num_slots (isa, fmt)
12490 < xtensa_format_num_slots (isa,
12493 opi->narrowest = fmt;
12494 opi->narrowest_size = fmt_length;
12495 opi->narrowest_slot = slot;
12500 opi->num_formats++;
12503 xtensa_insnbuf_free (isa, ibuf);
12508 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
12510 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
12514 /* If the opcode is available in a single slot format, return its size. */
12517 xg_get_single_size (xtensa_opcode opcode)
12519 return op_placement_table[opcode].narrowest_size;
12523 static xtensa_format
12524 xg_get_single_format (xtensa_opcode opcode)
12526 return op_placement_table[opcode].narrowest;
12531 xg_get_single_slot (xtensa_opcode opcode)
12533 return op_placement_table[opcode].narrowest_slot;
12537 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12540 istack_init (IStack *stack)
12547 istack_empty (IStack *stack)
12549 return (stack->ninsn == 0);
12554 istack_full (IStack *stack)
12556 return (stack->ninsn == MAX_ISTACK);
12560 /* Return a pointer to the top IStack entry.
12561 It is an error to call this if istack_empty () is TRUE. */
12564 istack_top (IStack *stack)
12566 int rec = stack->ninsn - 1;
12567 gas_assert (!istack_empty (stack));
12568 return &stack->insn[rec];
12572 /* Add a new TInsn to an IStack.
12573 It is an error to call this if istack_full () is TRUE. */
12576 istack_push (IStack *stack, TInsn *insn)
12578 int rec = stack->ninsn;
12579 gas_assert (!istack_full (stack));
12580 stack->insn[rec] = *insn;
12585 /* Clear space for the next TInsn on the IStack and return a pointer
12586 to it. It is an error to call this if istack_full () is TRUE. */
12589 istack_push_space (IStack *stack)
12591 int rec = stack->ninsn;
12593 gas_assert (!istack_full (stack));
12594 insn = &stack->insn[rec];
12601 /* Remove the last pushed instruction. It is an error to call this if
12602 istack_empty () returns TRUE. */
12605 istack_pop (IStack *stack)
12607 int rec = stack->ninsn - 1;
12608 gas_assert (!istack_empty (stack));
12610 tinsn_init (&stack->insn[rec]);
12614 /* TInsn functions. */
12617 tinsn_init (TInsn *dst)
12619 memset (dst, 0, sizeof (TInsn));
12623 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12626 tinsn_has_symbolic_operands (const TInsn *insn)
12629 int n = insn->ntok;
12631 gas_assert (insn->insn_type == ITYPE_INSN);
12633 for (i = 0; i < n; ++i)
12635 switch (insn->tok[i].X_op)
12649 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
12651 xtensa_isa isa = xtensa_default_isa;
12653 int n = insn->ntok;
12655 gas_assert (insn->insn_type == ITYPE_INSN);
12657 for (i = 0; i < n; ++i)
12659 switch (insn->tok[i].X_op)
12667 /* Errors for these types are caught later. */
12672 /* Symbolic immediates are only allowed on the last immediate
12673 operand. At this time, CONST16 is the only opcode where we
12674 support non-PC-relative relocations. */
12675 if (i != get_relaxable_immed (insn->opcode)
12676 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
12677 && insn->opcode != xtensa_const16_opcode))
12679 as_bad (_("invalid symbolic operand"));
12688 /* For assembly code with complex expressions (e.g. subtraction),
12689 we have to build them in the literal pool so that
12690 their results are calculated correctly after relaxation.
12691 The relaxation only handles expressions that
12692 boil down to SYMBOL + OFFSET. */
12695 tinsn_has_complex_operands (const TInsn *insn)
12698 int n = insn->ntok;
12699 gas_assert (insn->insn_type == ITYPE_INSN);
12700 for (i = 0; i < n; ++i)
12702 switch (insn->tok[i].X_op)
12718 /* Encode a TInsn opcode and its constant operands into slotbuf.
12719 Return TRUE if there is a symbol in the immediate field. This
12720 function assumes that:
12721 1) The number of operands are correct.
12722 2) The insn_type is ITYPE_INSN.
12723 3) The opcode can be encoded in the specified format and slot.
12724 4) Operands are either O_constant or O_symbol, and all constants fit. */
12727 tinsn_to_slotbuf (xtensa_format fmt,
12730 xtensa_insnbuf slotbuf)
12732 xtensa_isa isa = xtensa_default_isa;
12733 xtensa_opcode opcode = tinsn->opcode;
12734 bfd_boolean has_fixup = FALSE;
12735 int noperands = xtensa_opcode_num_operands (isa, opcode);
12738 gas_assert (tinsn->insn_type == ITYPE_INSN);
12739 if (noperands != tinsn->ntok)
12740 as_fatal (_("operand number mismatch"));
12742 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
12744 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12745 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
12749 for (i = 0; i < noperands; i++)
12751 expressionS *exp = &tinsn->tok[i];
12754 const char *file_name;
12760 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12762 /* The register number has already been checked in
12763 expression_maybe_register, so we don't need to check here. */
12764 opnd_value = exp->X_add_number;
12765 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12766 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
12769 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
12773 if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12775 file_name = as_where (&line);
12776 /* It is a constant and we called this function
12777 then we have to try to fit it. */
12778 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
12779 exp->X_add_number, file_name, line);
12792 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12793 into a multi-slot instruction, fill the other slots with NOPs.
12794 Return TRUE if there is a symbol in the immediate field. See also the
12795 assumptions listed for tinsn_to_slotbuf. */
12798 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
12800 static xtensa_insnbuf slotbuf = 0;
12801 static vliw_insn vinsn;
12802 xtensa_isa isa = xtensa_default_isa;
12803 bfd_boolean has_fixup = FALSE;
12808 slotbuf = xtensa_insnbuf_alloc (isa);
12809 xg_init_vinsn (&vinsn);
12812 xg_clear_vinsn (&vinsn);
12814 bundle_tinsn (tinsn, &vinsn);
12816 xtensa_format_encode (isa, vinsn.format, insnbuf);
12818 for (i = 0; i < vinsn.num_slots; i++)
12820 /* Only one slot may have a fix-up because the rest contains NOPs. */
12822 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
12823 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
12830 /* Check the instruction arguments. Return TRUE on failure. */
12833 tinsn_check_arguments (const TInsn *insn)
12835 xtensa_isa isa = xtensa_default_isa;
12836 xtensa_opcode opcode = insn->opcode;
12837 xtensa_regfile t1_regfile, t2_regfile;
12838 int t1_reg, t2_reg;
12839 int t1_base_reg, t1_last_reg;
12840 int t2_base_reg, t2_last_reg;
12841 char t1_inout, t2_inout;
12844 if (opcode == XTENSA_UNDEFINED)
12846 as_bad (_("invalid opcode"));
12850 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
12852 as_bad (_("too few operands"));
12856 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
12858 as_bad (_("too many operands"));
12862 /* Check registers. */
12863 for (j = 0; j < insn->ntok; j++)
12865 if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
12868 t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
12869 t2_base_reg = insn->tok[j].X_add_number;
12871 = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
12873 for (i = 0; i < insn->ntok; i++)
12878 if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
12881 t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
12883 if (t1_regfile != t2_regfile)
12886 t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
12887 t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
12889 t1_base_reg = insn->tok[i].X_add_number;
12890 t1_last_reg = (t1_base_reg
12891 + xtensa_operand_num_regs (isa, insn->opcode, i));
12893 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
12895 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
12897 if (t1_reg != t2_reg)
12900 if (t1_inout != 'i' && t2_inout != 'i')
12902 as_bad (_("multiple writes to the same register"));
12913 /* Load an instruction from its encoded form. */
12916 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
12920 xg_init_vinsn (&vinsn);
12921 vinsn_from_chars (&vinsn, f);
12923 *tinsn = vinsn.slots[slot];
12924 xg_free_vinsn (&vinsn);
12929 tinsn_from_insnbuf (TInsn *tinsn,
12930 xtensa_insnbuf slotbuf,
12935 xtensa_isa isa = xtensa_default_isa;
12937 /* Find the immed. */
12938 tinsn_init (tinsn);
12939 tinsn->insn_type = ITYPE_INSN;
12940 tinsn->is_specific_opcode = FALSE; /* must not be specific */
12941 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
12942 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
12943 for (i = 0; i < tinsn->ntok; i++)
12945 set_expr_const (&tinsn->tok[i],
12946 xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
12947 tinsn->opcode, i));
12952 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12955 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
12957 xtensa_opcode opcode = tinsn->opcode;
12960 if (fragP->tc_frag_data.slot_symbols[slot])
12962 opnum = get_relaxable_immed (opcode);
12963 gas_assert (opnum >= 0);
12964 set_expr_symbol_offset (&tinsn->tok[opnum],
12965 fragP->tc_frag_data.slot_symbols[slot],
12966 fragP->tc_frag_data.slot_offsets[slot]);
12968 tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
12973 get_num_stack_text_bytes (IStack *istack)
12976 int text_bytes = 0;
12978 for (i = 0; i < istack->ninsn; i++)
12980 TInsn *tinsn = &istack->insn[i];
12981 if (tinsn->insn_type == ITYPE_INSN)
12982 text_bytes += xg_get_single_size (tinsn->opcode);
12989 get_num_stack_literal_bytes (IStack *istack)
12994 for (i = 0; i < istack->ninsn; i++)
12996 TInsn *tinsn = &istack->insn[i];
12997 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
13004 /* vliw_insn functions. */
13007 xg_init_vinsn (vliw_insn *v)
13010 xtensa_isa isa = xtensa_default_isa;
13012 xg_clear_vinsn (v);
13014 v->insnbuf = xtensa_insnbuf_alloc (isa);
13015 if (v->insnbuf == NULL)
13016 as_fatal (_("out of memory"));
13018 for (i = 0; i < config_max_slots; i++)
13020 v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
13021 if (v->slotbuf[i] == NULL)
13022 as_fatal (_("out of memory"));
13028 xg_clear_vinsn (vliw_insn *v)
13032 memset (v, 0, offsetof (vliw_insn, slots)
13033 + sizeof(TInsn) * config_max_slots);
13035 v->format = XTENSA_UNDEFINED;
13037 v->inside_bundle = FALSE;
13039 if (xt_saved_debug_type != DEBUG_NONE)
13040 debug_type = xt_saved_debug_type;
13042 for (i = 0; i < config_max_slots; i++)
13043 v->slots[i].opcode = XTENSA_UNDEFINED;
13048 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
13051 offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
13052 dst->insnbuf = src->insnbuf;
13053 memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
13058 vinsn_has_specific_opcodes (vliw_insn *v)
13062 for (i = 0; i < v->num_slots; i++)
13064 if (v->slots[i].is_specific_opcode)
13072 xg_free_vinsn (vliw_insn *v)
13075 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
13076 for (i = 0; i < config_max_slots; i++)
13077 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
13081 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
13082 operands. See also the assumptions listed for tinsn_to_slotbuf. */
13085 vinsn_to_insnbuf (vliw_insn *vinsn,
13088 bfd_boolean record_fixup)
13090 xtensa_isa isa = xtensa_default_isa;
13091 xtensa_format fmt = vinsn->format;
13092 xtensa_insnbuf insnbuf = vinsn->insnbuf;
13094 bfd_boolean has_fixup = FALSE;
13096 xtensa_format_encode (isa, fmt, insnbuf);
13098 for (slot = 0; slot < vinsn->num_slots; slot++)
13100 TInsn *tinsn = &vinsn->slots[slot];
13101 expressionS *extra_arg = &tinsn->extra_arg;
13102 bfd_boolean tinsn_has_fixup =
13103 tinsn_to_slotbuf (vinsn->format, slot, tinsn,
13104 vinsn->slotbuf[slot]);
13106 xtensa_format_set_slot (isa, fmt, slot,
13107 insnbuf, vinsn->slotbuf[slot]);
13108 if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
13110 if (vinsn->num_slots != 1)
13111 as_bad (_("TLS relocation not allowed in FLIX bundle"));
13112 else if (record_fixup)
13113 /* Instructions that generate TLS relocations should always be
13114 relaxed in the front-end. If "record_fixup" is set, then this
13115 function is being called during back-end relaxation, so flag
13116 the unexpected behavior as an error. */
13117 as_bad (_("unexpected TLS relocation"));
13119 fix_new (fragP, frag_offset - fragP->fr_literal,
13120 xtensa_format_length (isa, fmt),
13121 extra_arg->X_add_symbol, extra_arg->X_add_number,
13122 FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE));
13124 if (tinsn_has_fixup)
13127 xtensa_opcode opcode = tinsn->opcode;
13128 int noperands = xtensa_opcode_num_operands (isa, opcode);
13131 for (i = 0; i < noperands; i++)
13133 expressionS* exp = &tinsn->tok[i];
13139 if (get_relaxable_immed (opcode) == i)
13141 /* Add a fix record for the instruction, except if this
13142 function is being called prior to relaxation, i.e.,
13143 if record_fixup is false, and the instruction might
13144 be relaxed later. */
13146 || tinsn->is_specific_opcode
13147 || !xg_is_relaxable_insn (tinsn, 0))
13149 xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP,
13150 frag_offset - fragP->fr_literal);
13154 if (exp->X_op != O_symbol)
13155 as_bad (_("invalid operand"));
13156 tinsn->symbol = exp->X_add_symbol;
13157 tinsn->offset = exp->X_add_number;
13161 as_bad (_("symbolic operand not allowed"));
13169 as_bad (_("expression too complex"));
13181 vinsn_from_chars (vliw_insn *vinsn, char *f)
13183 static xtensa_insnbuf insnbuf = NULL;
13184 static xtensa_insnbuf slotbuf = NULL;
13187 xtensa_isa isa = xtensa_default_isa;
13191 insnbuf = xtensa_insnbuf_alloc (isa);
13192 slotbuf = xtensa_insnbuf_alloc (isa);
13195 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
13196 fmt = xtensa_format_decode (isa, insnbuf);
13197 if (fmt == XTENSA_UNDEFINED)
13198 as_fatal (_("cannot decode instruction format"));
13199 vinsn->format = fmt;
13200 vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
13202 for (i = 0; i < vinsn->num_slots; i++)
13204 TInsn *tinsn = &vinsn->slots[i];
13205 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
13206 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
13211 /* Expression utilities. */
13213 /* Return TRUE if the expression is an integer constant. */
13216 expr_is_const (const expressionS *s)
13218 return (s->X_op == O_constant);
13222 /* Get the expression constant.
13223 Calling this is illegal if expr_is_const () returns TRUE. */
13226 get_expr_const (const expressionS *s)
13228 gas_assert (expr_is_const (s));
13229 return s->X_add_number;
13233 /* Set the expression to a constant value. */
13236 set_expr_const (expressionS *s, offsetT val)
13238 s->X_op = O_constant;
13239 s->X_add_number = val;
13240 s->X_add_symbol = NULL;
13241 s->X_op_symbol = NULL;
13246 expr_is_register (const expressionS *s)
13248 return (s->X_op == O_register);
13252 /* Get the expression constant.
13253 Calling this is illegal if expr_is_const () returns TRUE. */
13256 get_expr_register (const expressionS *s)
13258 gas_assert (expr_is_register (s));
13259 return s->X_add_number;
13263 /* Set the expression to a symbol + constant offset. */
13266 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
13268 s->X_op = O_symbol;
13269 s->X_add_symbol = sym;
13270 s->X_op_symbol = NULL; /* unused */
13271 s->X_add_number = offset;
13275 /* Return TRUE if the two expressions are equal. */
13278 expr_is_equal (expressionS *s1, expressionS *s2)
13280 if (s1->X_op != s2->X_op)
13282 if (s1->X_add_symbol != s2->X_add_symbol)
13284 if (s1->X_op_symbol != s2->X_op_symbol)
13286 if (s1->X_add_number != s2->X_add_number)
13293 copy_expr (expressionS *dst, const expressionS *src)
13295 memcpy (dst, src, sizeof (expressionS));
13299 /* Support for the "--rename-section" option. */
13301 struct rename_section_struct
13303 const char *old_name;
13305 struct rename_section_struct *next;
13308 static struct rename_section_struct *section_rename;
13311 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13312 entries to the section_rename list. Note: Specifying multiple
13313 renamings separated by colons is not documented and is retained only
13314 for backward compatibility. */
13317 build_section_rename (const char *arg)
13319 struct rename_section_struct *r;
13320 char *this_arg = NULL;
13321 char *next_arg = NULL;
13323 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
13325 char *old_name, *new_name;
13329 next_arg = strchr (this_arg, ':');
13337 old_name = this_arg;
13338 new_name = strchr (this_arg, '=');
13340 if (*old_name == '\0')
13342 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13345 if (!new_name || new_name[1] == '\0')
13347 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13354 /* Check for invalid section renaming. */
13355 for (r = section_rename; r != NULL; r = r->next)
13357 if (strcmp (r->old_name, old_name) == 0)
13358 as_bad (_("section %s renamed multiple times"), old_name);
13359 if (strcmp (r->new_name, new_name) == 0)
13360 as_bad (_("multiple sections remapped to output section %s"),
13365 r = XNEW (struct rename_section_struct);
13366 r->old_name = xstrdup (old_name);
13367 r->new_name = xstrdup (new_name);
13368 r->next = section_rename;
13369 section_rename = r;
13375 xtensa_section_rename (const char *name)
13377 struct rename_section_struct *r = section_rename;
13379 for (r = section_rename; r != NULL; r = r->next)
13381 if (strcmp (r->old_name, name) == 0)
13382 return r->new_name;
13385 return (char *) name;