1 /* This is the machine dependent code of the Visium Assembler.
3 Copyright (C) 2005-2015 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 #include "safe-ctype.h"
27 #include "opcode/visium.h"
28 #include "elf/visium.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 /* Relocations and fixups:
34 There are two different cases where an instruction or data
35 directive operand requires relocation, or fixup.
37 1. Relative branch instructions, take an 16-bit signed word
38 offset. The formula for computing the offset is this:
40 offset = (destination - pc) / 4
42 Branch instructions never branch to a label not declared
43 locally, so the actual offset can always be computed by the assembler.
44 However, we provide a relocation type to support this.
46 2. Load literal instructions, such as MOVIU, which take a 16-bit
47 literal operand. The literal may be the top or bottom half of
48 a 32-bit value computed by the assembler, or by the linker. We provide
49 two relocation types here.
51 3. Data items (long, word and byte) preset with a value computed by
55 /* This string holds the chars that always start a comment. If the
56 pre-processor is disabled, these aren't very useful. The macro
57 tc_comment_chars points to this. */
58 const char *visium_comment_chars = "!;";
60 /* This array holds the chars that only start a comment at the beginning
61 of a line. If the line seems to have the form '# 123 filename' .line
62 and .file directives will appear in the pre-processed output. Note that
63 input_file.c hand checks for '#' at the beginning of the first line of
64 the input file. This is because the compiler outputs #NO_APP at the
65 beginning of its output. Also note that comments like this one will
67 const char line_comment_chars[] = "#!;";
68 const char line_separator_chars[] = "";
70 /* Chars that can be used to separate mantissa from exponent in floating point
72 const char EXP_CHARS[] = "eE";
74 /* Chars that mean this number is a floating point constant, as in
75 "0f12.456" or "0d1.2345e12".
77 ...Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
78 changed in read.c. Ideally it shouldn't have to know about it at all,
79 but nothing is ideal around here. */
80 const char FLT_CHARS[] = "rRsSfFdDxXeE";
82 /* The size of a relocation record. */
83 const int md_reloc_size = 8;
85 /* The architecture for which we are assembling. */
94 static enum visium_arch_val visium_arch = VISIUM_ARCH_DEF;
96 /* The opcode architecture for which we are assembling. In contrast to the
97 previous one, this only determines which instructions are supported. */
98 static enum visium_opcode_arch_val visium_opcode_arch = VISIUM_OPCODE_ARCH_DEF;
100 /* Flags to set in the ELF header e_flags field. */
101 static flagword visium_flags = 0;
103 /* More than this number of nops in an alignment op gets a branch instead. */
104 static unsigned int nop_limit = 5;
107 /* Translate internal representation of relocation info to BFD target
110 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
113 bfd_reloc_code_real_type code;
115 reloc = (arelent *) xmalloc (sizeof (arelent));
117 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
118 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
119 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
121 switch (fixp->fx_r_type)
126 case BFD_RELOC_8_PCREL:
127 case BFD_RELOC_16_PCREL:
128 case BFD_RELOC_32_PCREL:
129 case BFD_RELOC_VISIUM_HI16:
130 case BFD_RELOC_VISIUM_LO16:
131 case BFD_RELOC_VISIUM_IM16:
132 case BFD_RELOC_VISIUM_REL16:
133 case BFD_RELOC_VISIUM_HI16_PCREL:
134 case BFD_RELOC_VISIUM_LO16_PCREL:
135 case BFD_RELOC_VISIUM_IM16_PCREL:
136 case BFD_RELOC_VTABLE_INHERIT:
137 case BFD_RELOC_VTABLE_ENTRY:
138 code = fixp->fx_r_type;
141 as_bad_where (fixp->fx_file, fixp->fx_line,
142 "internal error: unknown relocation type %d (`%s')",
144 bfd_get_reloc_code_name (fixp->fx_r_type));
148 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
149 if (reloc->howto == 0)
151 as_bad_where (fixp->fx_file, fixp->fx_line,
152 "internal error: can't export reloc type %d (`%s')",
153 fixp->fx_r_type, bfd_get_reloc_code_name (code));
157 /* Write the addend. */
158 if (reloc->howto->pc_relative == 0)
159 reloc->addend = fixp->fx_addnumber;
161 reloc->addend = fixp->fx_offset;
166 extern char *input_line_pointer;
169 static void s_bss (int);
170 static void visium_rdata (int);
172 static void visium_update_parity_bit (char *);
173 static char *parse_exp (char *, expressionS *);
175 /* These are the back-ends for the various machine dependent pseudo-ops. */
176 void demand_empty_rest_of_line (void);
180 s_bss (int ignore ATTRIBUTE_UNUSED)
182 /* We don't support putting frags in the BSS segment, we fake it
183 by marking in_bss, then looking at s_skip for clues. */
185 subseg_set (bss_section, 0);
186 demand_empty_rest_of_line ();
190 /* This table describes all the machine specific pseudo-ops the assembler
191 has to support. The fields are:
193 1: Pseudo-op name without dot.
194 2: Function to call to execute this pseudo-op.
195 3: Integer arg to pass to the function. */
196 const pseudo_typeS md_pseudo_table[] =
199 {"skip", s_space, 0},
200 {"align", s_align_bytes, 0},
201 {"noopt", s_ignore, 0},
202 {"optim", s_ignore, 0},
203 {"rdata", visium_rdata, 0},
204 {"rodata", visium_rdata, 0},
210 visium_rdata (int xxx)
212 char *save_line = input_line_pointer;
213 static char section[] = ".rodata\n";
215 /* Just pretend this is .section .rodata */
216 input_line_pointer = section;
217 obj_elf_section (xxx);
218 input_line_pointer = save_line;
221 /* Align a section. */
223 md_section_align (asection *seg, valueT addr)
225 int align = bfd_get_section_alignment (stdoutput, seg);
227 return ((addr + (1 << align) - 1) & (-1 << align));
231 md_number_to_chars (char *buf, valueT val, int n)
233 number_to_chars_bigendian (buf, val, n);
237 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
242 /* The parse options. */
243 const char *md_shortopts = "m:";
245 struct option md_longopts[] =
247 {NULL, no_argument, NULL, 0}
250 size_t md_longopts_size = sizeof (md_longopts);
252 struct visium_option_table
254 char *option; /* Option name to match. */
255 char *help; /* Help information. */
256 int *var; /* Variable to change. */
257 int value; /* To what to change it. */
258 char *deprecated; /* If non-null, print this message. */
261 static struct visium_option_table visium_opts[] =
263 {NULL, NULL, NULL, 0, NULL}
266 struct visium_arch_option_table
269 enum visium_arch_val value;
272 static struct visium_arch_option_table visium_archs[] =
274 {"mcm24", VISIUM_ARCH_MCM24},
275 {"mcm", VISIUM_ARCH_MCM},
276 {"gr5", VISIUM_ARCH_MCM},
277 {"gr6", VISIUM_ARCH_GR6},
281 struct visium_long_option_table
283 char *option; /* Substring to match. */
284 char *help; /* Help information. */
285 int (*func) (char *subopt); /* Function to decode sub-option. */
286 char *deprecated; /* If non-null, print this message. */
290 visium_parse_arch (char *str)
292 struct visium_arch_option_table *opt;
294 if (strlen (str) == 0)
296 as_bad ("missing architecture name `%s'", str);
301 for (opt = visium_archs; opt->name != NULL; opt++)
302 if (strcmp (opt->name, str) == 0)
304 visium_arch = opt->value;
308 as_bad ("unknown architecture `%s'\n", str);
312 static struct visium_long_option_table visium_long_opts[] =
314 {"mtune=", "<arch_name>\t assemble for architecture <arch name>",
315 visium_parse_arch, NULL},
316 {NULL, NULL, NULL, NULL}
320 md_parse_option (int c, char *arg)
322 struct visium_option_table *opt;
323 struct visium_long_option_table *lopt;
328 /* Listing option. Just ignore these, we don't support additional
333 for (opt = visium_opts; opt->option != NULL; opt++)
335 if (c == opt->option[0]
336 && ((arg == NULL && opt->option[1] == 0)
337 || strcmp (arg, opt->option + 1) == 0))
339 /* If the option is deprecated, tell the user. */
340 if (opt->deprecated != NULL)
341 as_tsktsk ("option `-%c%s' is deprecated: %s", c,
342 arg ? arg : "", opt->deprecated);
344 if (opt->var != NULL)
345 *opt->var = opt->value;
351 for (lopt = visium_long_opts; lopt->option != NULL; lopt++)
353 /* These options are expected to have an argument. */
354 if (c == lopt->option[0]
356 && strncmp (arg, lopt->option + 1,
357 strlen (lopt->option + 1)) == 0)
359 /* If the option is deprecated, tell the user. */
360 if (lopt->deprecated != NULL)
361 as_tsktsk ("option `-%c%s' is deprecated: %s", c, arg,
364 /* Call the sup-option parser. */
365 return lopt->func (arg + strlen (lopt->option) - 1);
376 md_show_usage (FILE * fp)
378 struct visium_option_table *opt;
379 struct visium_long_option_table *lopt;
381 fprintf (fp, " Visium-specific assembler options:\n");
383 for (opt = visium_opts; opt->option != NULL; opt++)
384 if (opt->help != NULL)
385 fprintf (fp, " -%-23s%s\n", opt->option, opt->help);
387 for (lopt = visium_long_opts; lopt->option != NULL; lopt++)
388 if (lopt->help != NULL)
389 fprintf (fp, " -%s%s\n", lopt->option, lopt->help);
393 /* Interface to relax_segment. */
395 /* Return the estimate of the size of a machine dependent frag
396 before any relaxing is done. It may also create any necessary
399 md_estimate_size_before_relax (fragS * fragP,
400 segT segment ATTRIBUTE_UNUSED)
406 /* Get the address of a symbol during relaxation. From tc-arm.c. */
408 relaxed_symbol_addr (fragS *fragp, long stretch)
414 sym = fragp->fr_symbol;
415 sym_frag = symbol_get_frag (sym);
416 know (S_GET_SEGMENT (sym) != absolute_section
417 || sym_frag == &zero_address_frag);
418 addr = S_GET_VALUE (sym) + fragp->fr_offset;
420 /* If frag has yet to be reached on this pass, assume it will
421 move by STRETCH just as we did. If this is not so, it will
422 be because some frag between grows, and that will force
425 && sym_frag->relax_marker != fragp->relax_marker)
429 /* Adjust stretch for any alignment frag. Note that if have
430 been expanding the earlier code, the symbol may be
431 defined in what appears to be an earlier frag. FIXME:
432 This doesn't handle the fr_subtype field, which specifies
433 a maximum number of bytes to skip when doing an
435 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
437 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
440 stretch = - ((- stretch)
441 & ~ ((1 << (int) f->fr_offset) - 1));
443 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
455 /* Relax a machine dependent frag. This returns the amount by which
456 the current size of the frag should change. */
458 visium_relax_frag (asection *sec, fragS *fragP, long stretch)
460 int old_size, new_size;
463 /* We only handle relaxation for the BRR instruction. */
464 gas_assert (fragP->fr_subtype == mode_ci);
466 if (!S_IS_DEFINED (fragP->fr_symbol)
467 || sec != S_GET_SEGMENT (fragP->fr_symbol)
468 || S_IS_WEAK (fragP->fr_symbol))
471 old_size = fragP->fr_var;
472 addr = relaxed_symbol_addr (fragP, stretch);
474 /* If the target is the address of the instruction, we'll insert a NOP. */
475 if (addr == fragP->fr_address + fragP->fr_fix)
480 fragP->fr_var = new_size;
481 return new_size - old_size;
484 /* Convert a machine dependent frag. */
486 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
489 char *buf = fragP->fr_literal + fragP->fr_fix;
493 /* We only handle relaxation for the BRR instruction. */
494 gas_assert (fragP->fr_subtype == mode_ci);
496 /* Insert the NOP if requested. */
497 if (fragP->fr_var == 8)
499 memcpy (buf + 4, buf, 4);
505 exp.X_add_symbol = fragP->fr_symbol;
506 exp.X_add_number = fragP->fr_offset;
508 /* Now we can create the relocation at the correct offset. */
509 fixP = fix_new_exp (fragP, fragP->fr_fix, 4, &exp, 1, BFD_RELOC_VISIUM_REL16);
510 fixP->fx_file = fragP->fr_file;
511 fixP->fx_line = fragP->fr_line;
516 /* The location from which a PC relative jump should be calculated,
517 given a PC relative jump reloc. */
519 visium_pcrel_from_section (fixS *fixP, segT sec)
521 if (fixP->fx_addsy != (symbolS *) NULL
522 && (!S_IS_DEFINED (fixP->fx_addsy)
523 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
525 /* The symbol is undefined (or is defined but not in this section).
526 Let the linker figure it out. */
530 /* Return the address of the instruction. */
531 return fixP->fx_where + fixP->fx_frag->fr_address;
534 /* Indicate whether a fixup against a locally defined
535 symbol should be adjusted to be against the section
538 visium_fix_adjustable (fixS *fix)
540 /* We need the symbol name for the VTABLE entries. */
541 return (fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
542 && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY);
545 /* Update the parity bit of the 4-byte instruction in BUF. */
547 visium_update_parity_bit (char *buf)
549 int p1 = (buf[0] & 0x7f) ^ buf[1] ^ buf[2] ^ buf[3];
553 for (i = 1; i <= 8; i++)
559 buf[0] = (buf[0] & 0x7f) | ((p2 << 7) & 0x80);
562 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
563 of an rs_align_code fragment. */
565 visium_handle_align (fragS *fragP)
568 = fragP->fr_next->fr_address - (fragP->fr_address + fragP->fr_fix);
569 valueT fix = count & 3;
570 char *p = fragP->fr_literal + fragP->fr_fix;
577 fragP->fr_fix += fix;
585 if (count > 4 * nop_limit && count <= 131068)
589 /* Make a branch, then follow with nops. Insert another
590 frag to handle the nops. */
591 md_number_to_chars (p, 0x78000000 + (count >> 2), 4);
592 visium_update_parity_bit (p);
594 rest = xmalloc (SIZEOF_STRUCT_FRAG + 4);
595 memcpy (rest, fragP, SIZEOF_STRUCT_FRAG);
596 fragP->fr_next = rest;
597 rest->fr_address += rest->fr_fix + 4;
599 /* If we leave the next frag as rs_align_code we'll come here
600 again, resulting in a bunch of branches rather than a
601 branch followed by nops. */
602 rest->fr_type = rs_align;
603 p = rest->fr_literal;
609 /* Apply a fixS to the frags, now that we know the value it ought to
612 md_apply_fix (fixS * fixP, valueT * value, segT segment)
614 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
620 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
622 /* Remember value for tc_gen_reloc. */
623 fixP->fx_addnumber = val;
625 /* Since DIFF_EXPR_OK is defined, .-foo gets turned into PC
626 relative relocs. If this has happened, a non-PC relative
627 reloc must be reinstalled with its PC relative version here. */
630 switch (fixP->fx_r_type)
633 fixP->fx_r_type = BFD_RELOC_8_PCREL;
636 fixP->fx_r_type = BFD_RELOC_16_PCREL;
639 fixP->fx_r_type = BFD_RELOC_32_PCREL;
641 case BFD_RELOC_VISIUM_HI16:
642 fixP->fx_r_type = BFD_RELOC_VISIUM_HI16_PCREL;
644 case BFD_RELOC_VISIUM_LO16:
645 fixP->fx_r_type = BFD_RELOC_VISIUM_LO16_PCREL;
647 case BFD_RELOC_VISIUM_IM16:
648 fixP->fx_r_type = BFD_RELOC_VISIUM_IM16_PCREL;
655 /* If this is a data relocation, just output VAL. */
656 switch (fixP->fx_r_type)
659 case BFD_RELOC_8_PCREL:
660 md_number_to_chars (buf, val, 1);
663 case BFD_RELOC_16_PCREL:
664 md_number_to_chars (buf, val, 2);
667 case BFD_RELOC_32_PCREL:
668 md_number_to_chars (buf, val, 4);
670 case BFD_RELOC_VTABLE_INHERIT:
671 case BFD_RELOC_VTABLE_ENTRY:
675 /* It's a relocation against an instruction. */
676 insn = bfd_getb32 ((unsigned char *) buf);
678 switch (fixP->fx_r_type)
680 case BFD_RELOC_VISIUM_REL16:
681 if (fixP->fx_addsy == NULL
682 || (S_IS_DEFINED (fixP->fx_addsy)
683 && S_GET_SEGMENT (fixP->fx_addsy) == segment))
685 if (val > 0x1fffc || val < -0x20000)
687 (fixP->fx_file, fixP->fx_line,
688 "16-bit word displacement out of range: value = %d",
692 insn = (insn & 0xffff0000) | (val & 0x0000ffff);
696 case BFD_RELOC_VISIUM_HI16:
697 case BFD_RELOC_VISIUM_HI16_PCREL:
698 if (fixP->fx_addsy == NULL)
699 insn = (insn & 0xffff0000) | ((val >> 16) & 0x0000ffff);
702 case BFD_RELOC_VISIUM_LO16:
703 case BFD_RELOC_VISIUM_LO16_PCREL:
704 if (fixP->fx_addsy == NULL)
705 insn = (insn & 0xffff0000) | (val & 0x0000ffff);
708 case BFD_RELOC_VISIUM_IM16:
709 case BFD_RELOC_VISIUM_IM16_PCREL:
710 if (fixP->fx_addsy == NULL)
712 if ((val & 0xffff0000) != 0)
713 as_bad_where (fixP->fx_file, fixP->fx_line,
714 "16-bit immediate out of range: value = %d",
717 insn = (insn & 0xffff0000) | val;
723 as_bad_where (fixP->fx_file, fixP->fx_line,
724 "bad or unhandled relocation type: 0x%02x",
729 bfd_putb32 (insn, (unsigned char *) buf);
730 visium_update_parity_bit (buf);
734 /* Are we finished with this relocation now? */
735 if (fixP->fx_addsy == NULL)
740 parse_exp (char *s, expressionS * op)
742 char *save = input_line_pointer;
750 input_line_pointer = s;
752 new = input_line_pointer;
753 input_line_pointer = save;
757 /* If the given string is a Visium opcode mnemonic return the code
758 otherwise return -1. Use binary chop to find matching entry. */
760 get_opcode (int *code, enum addressing_mode *mode, char *flags, char *mnem)
763 int r = sizeof (opcode_table) / sizeof (struct opcode_entry) - 1;
767 int mid = (l + r) / 2;
768 int ans = strcmp (mnem, opcode_table[mid].mnem);
776 *code = opcode_table[mid].code;
777 *mode = opcode_table[mid].mode;
778 *flags = opcode_table[mid].flags;
788 /* This function is called when the assembler starts up. It is called
789 after the options have been parsed and the output file has been
796 case VISIUM_ARCH_DEF:
798 case VISIUM_ARCH_MCM24:
799 visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5;
800 visium_flags |= EF_VISIUM_ARCH_MCM24;
802 case VISIUM_ARCH_MCM:
803 visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5;
804 visium_flags |= EF_VISIUM_ARCH_MCM;
806 case VISIUM_ARCH_GR6:
807 visium_opcode_arch = VISIUM_OPCODE_ARCH_GR6;
808 visium_flags |= EF_VISIUM_ARCH_MCM | EF_VISIUM_ARCH_GR6;
815 bfd_set_private_flags (stdoutput, visium_flags);
818 /* This is identical to the md_atof in m68k.c. I think this is right,
821 Turn a string in input_line_pointer into a floating point constant of type
822 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
823 emitted is stored in *sizeP . An error message is returned,
826 /* Equal to MAX_PRECISION in atof-ieee.c. */
827 #define MAX_LITTLENUMS 6
830 md_atof (int type, char *litP, int *sizeP)
833 LITTLENUM_TYPE words[MAX_LITTLENUMS];
864 return "Bad call to MD_ATOF()";
867 t = atof_ieee (input_line_pointer, type, words);
869 input_line_pointer = t;
870 *sizeP = prec * sizeof (LITTLENUM_TYPE);
872 if (target_big_endian)
874 for (i = 0; i < prec; i++)
876 md_number_to_chars (litP, (valueT) words[i],
877 sizeof (LITTLENUM_TYPE));
878 litP += sizeof (LITTLENUM_TYPE);
883 for (i = prec - 1; i >= 0; i--)
885 md_number_to_chars (litP, (valueT) words[i],
886 sizeof (LITTLENUM_TYPE));
887 litP += sizeof (LITTLENUM_TYPE);
897 while (*s == ' ' || *s == '\t')
904 parse_gen_reg (char **sptr, int *rptr)
906 char *s = skip_space (*sptr);
912 memset (buf, '\0', 10);
913 while ((ISALNUM (*s)) && cnt < 10)
914 buf[cnt++] = TOLOWER (*s++);
917 r = sizeof (gen_reg_table) / sizeof (struct reg_entry) - 1;
921 int mid = (l + r) / 2;
922 int ans = strcmp (buf, gen_reg_table[mid].name);
930 *rptr = gen_reg_table[mid].code;
941 parse_fp_reg (char **sptr, int *rptr)
943 char *s = skip_space (*sptr);
949 memset (buf, '\0', 10);
950 while ((ISALNUM (*s)) && cnt < 10)
951 buf[cnt++] = TOLOWER (*s++);
954 r = sizeof (fp_reg_table) / sizeof (struct reg_entry) - 1;
958 int mid = (l + r) / 2;
959 int ans = strcmp (buf, fp_reg_table[mid].name);
967 *rptr = fp_reg_table[mid].code;
978 parse_cc (char **sptr, int *rptr)
980 char *s = skip_space (*sptr);
986 memset (buf, '\0', 10);
987 while ((ISALNUM (*s)) && cnt < 10)
988 buf[cnt++] = TOLOWER (*s++);
991 r = sizeof (cc_table) / sizeof (struct cc_entry) - 1;
995 int mid = (l + r) / 2;
996 int ans = strcmp (buf, cc_table[mid].name);
1004 *rptr = cc_table[mid].code;
1014 /* Previous dest is the destination register number of the instruction
1015 before the current one. */
1016 static int previous_dest = 0;
1017 static int previous_mode = 0;
1018 static int condition_code = 0;
1019 static int this_dest = 0;
1020 static int this_mode = 0;
1023 /* This is the main function in this file. It takes a line of assembly language
1024 source code and assembles it. Note, labels and pseudo ops have already
1025 been removed, so too has leading white space. */
1027 md_assemble (char *str0)
1033 enum addressing_mode amode;
1039 relax_substateT relax = 0;
1045 /* Initialize the expression. */
1048 /* Initialize destination register.
1049 If the instruction we just looked at is in the delay slot of an
1050 unconditional branch, then there is no index hazard. */
1051 if ((previous_mode == mode_cad || previous_mode == mode_ci)
1052 && condition_code == 15)
1055 previous_dest = this_dest;
1056 previous_mode = this_mode;
1059 /* Drop leading whitespace (probably not required). */
1063 /* Get opcode mnemonic and make sure it's in lower case. */
1065 memset (mnem, '\0', 10);
1066 while ((ISALNUM (*str) || *str == '.' || *str == '_') && cnt < 10)
1067 mnem[cnt++] = TOLOWER (*str++);
1069 /* Look up mnemonic in opcode table, and get the code,
1070 the instruction format, and the flags that indicate
1071 which family members support this mnenonic. */
1072 if (get_opcode (&opcode, &amode, &arch_flags, mnem) < 0)
1074 as_bad ("Unknown instruction mnenonic `%s'", mnem);
1078 if ((VISIUM_OPCODE_ARCH_MASK (visium_opcode_arch) & arch_flags) == 0)
1080 as_bad ("Architecture mismatch on `%s'", mnem);
1092 ans = parse_gen_reg (&str, &r1);
1095 as_bad ("Dest register required");
1098 opcode |= (r1 << 10);
1105 ans = parse_gen_reg (&str, &r1);
1108 as_bad ("SourceA register required");
1111 opcode |= (r1 << 16);
1115 /* register * register
1118 ans = parse_gen_reg (&str, &r1);
1121 as_bad ("SourceA register required");
1124 str = skip_space (str);
1128 ans = parse_gen_reg (&str, &r2);
1131 as_bad ("SourceB register required");
1134 opcode |= (r1 << 16) | (r2 << 4);
1138 as_bad ("SourceB register required");
1144 /* register := register
1147 ans = parse_gen_reg (&str, &r1);
1150 as_bad ("Dest register required");
1153 str = skip_space (str);
1157 ans = parse_gen_reg (&str, &r2);
1160 as_bad ("SourceA register required");
1163 opcode |= (r1 << 10) | (r2 << 16);
1167 as_bad ("SourceB register required");
1174 /* register := register * register
1177 ans = parse_gen_reg (&str, &r1);
1180 as_bad ("Dest register required");
1183 str = skip_space (str);
1187 ans = parse_gen_reg (&str, &r2);
1190 as_bad ("SourceA register required");
1193 str = skip_space (str);
1197 ans = parse_gen_reg (&str, &r3);
1200 as_bad ("SourceB register required");
1204 /* Got three regs, assemble instruction. */
1205 opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
1209 as_bad ("SourceA register required");
1215 as_bad ("Dest register required");
1222 /* 5-bit immediate * register * register
1225 str = parse_exp (str, &e1);
1226 str = skip_space (str);
1227 if (e1.X_op != O_absent && *str == ',')
1229 int eam_op = e1.X_add_number;
1231 str = skip_space (str + 1);
1232 ans = parse_gen_reg (&str, &r2);
1235 as_bad ("SourceA register required");
1238 str = skip_space (str);
1242 ans = parse_gen_reg (&str, &r3);
1245 as_bad ("SourceB register required");
1249 /* Got three operands, assemble instruction. */
1250 if (eam_op < 0 || eam_op > 31)
1252 as_bad ("eam_op out of range");
1254 opcode |= ((eam_op & 0x1f) << 10) | (r2 << 16) | (r3 << 4);
1259 as_bad ("EAM_OP required");
1265 /* zero * register * register
1268 ans = parse_gen_reg (&str, &r1);
1271 as_bad ("SourceA register required");
1274 str = skip_space (str);
1278 ans = parse_gen_reg (&str, &r2);
1281 as_bad ("SourceB register required");
1284 opcode |= (r1 << 16) | (r2 << 4);
1288 as_bad ("SourceB register required");
1294 /* register * register * zero
1297 ans = parse_gen_reg (&str, &r1);
1300 as_bad ("Dest register required");
1303 str = skip_space (str);
1307 ans = parse_gen_reg (&str, &r2);
1310 as_bad ("SourceA register required");
1313 opcode |= (r1 << 10) | (r2 << 16);
1317 as_bad ("SourceA register required");
1324 /* condition * register * register
1327 ans = parse_cc (&str, &cc);
1330 as_bad ("condition code required");
1334 str = skip_space (str);
1337 str = skip_space (str + 1);
1338 ans = parse_gen_reg (&str, &r2);
1341 as_bad ("SourceA register required");
1344 str = skip_space (str);
1348 ans = parse_gen_reg (&str, &r3);
1351 as_bad ("Dest register required");
1355 /* Got three operands, assemble instruction. */
1356 opcode |= (cc << 27) | (r2 << 16) | (r3 << 10);
1360 as_bad ("Dest register required");
1366 as_bad ("SourceA register required");
1370 if (previous_mode == mode_cad || previous_mode == mode_ci)
1371 as_bad ("branch instruction in delay slot");
1374 condition_code = cc;
1378 /* register := register * 5-bit imediate/register shift count
1381 ans = parse_gen_reg (&str, &r1);
1384 as_bad ("Dest register required");
1387 str = skip_space (str);
1391 ans = parse_gen_reg (&str, &r2);
1394 as_bad ("SourceA register required");
1397 str = skip_space (str);
1401 ans = parse_gen_reg (&str, &r3);
1404 opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
1408 str = parse_exp (str, &e1);
1409 if (e1.X_op == O_constant)
1411 int imm = e1.X_add_number;
1413 if (imm < 0 || imm > 31)
1414 as_bad ("immediate value out of range");
1417 (r1 << 10) | (r2 << 16) | (1 << 9) | ((imm & 0x1f) <<
1422 as_bad ("immediate operand required");
1430 as_bad ("SourceA register required");
1437 /* register := 5-bit immediate
1440 ans = parse_gen_reg (&str, &r1);
1443 as_bad ("Dest register required");
1446 str = skip_space (str);
1450 str = parse_exp (str, &e1);
1451 if (e1.X_op == O_constant)
1453 int opnd2 = e1.X_add_number;
1455 if (opnd2 < 0 || opnd2 > 31)
1457 as_bad ("immediate operand out of range");
1460 opcode |= (r1 << 10) | ((opnd2 & 0x1f) << 4);
1464 as_bad ("immediate operand required");
1470 as_bad ("immediate operand required");
1477 /* 5-bit immediate * register, e.g. trace 1,r1 */
1478 str = parse_exp (str, &e1);
1479 str = skip_space (str);
1480 if (e1.X_op == O_constant && *str == ',')
1482 int opnd1 = e1.X_add_number;
1484 str = skip_space (str + 1);
1485 ans = parse_gen_reg (&str, &r2);
1488 as_bad ("SourceA register required");
1492 /* Got two operands, assemble instruction. */
1493 if (opnd1 < 0 || opnd1 > 31)
1495 as_bad ("1st operand out of range");
1497 opcode |= ((opnd1 & 0x1f) << 10) | (r2 << 16);
1501 as_bad ("Immediate operand required");
1507 /* register *= 16-bit unsigned immediate
1510 ans = parse_gen_reg (&str, &r1);
1513 as_bad ("Dest register required");
1516 opcode |= (r1 << 16);
1518 str = skip_space (str);
1521 as_bad ("immediate value missing");
1526 /* fall through... */
1529 /* MOVIL/WRTL traditionally get an implicit "%l" applied
1530 to their immediate value. For other opcodes, unless
1531 the immediate value is decorated with "%u" or "%l"
1532 it must be in the range 0 .. 65535. */
1533 if ((opcode & 0x7fe00000) == 0x04800000
1534 || (opcode & 0x7fe00000) == 0x05000000)
1535 reloc = BFD_RELOC_VISIUM_LO16;
1537 reloc = BFD_RELOC_VISIUM_IM16;
1539 str = skip_space (str + 1);
1544 reloc = BFD_RELOC_VISIUM_HI16;
1545 else if (str[1] == 'l')
1546 reloc = BFD_RELOC_VISIUM_LO16;
1549 as_bad ("bad char after %%");
1555 str = parse_exp (str, &e1);
1556 if (e1.X_op != O_absent)
1558 if (e1.X_op == O_constant)
1560 int imm = e1.X_add_number;
1562 if (reloc == BFD_RELOC_VISIUM_HI16)
1563 opcode |= ((imm >> 16) & 0xffff);
1564 else if (reloc == BFD_RELOC_VISIUM_LO16)
1565 opcode |= (imm & 0xffff);
1568 if (imm < 0 || imm > 0xffff)
1569 as_bad ("immediate value out of range");
1571 opcode |= (imm & 0xffff);
1573 /* No relocation is needed. */
1579 as_bad ("immediate value missing");
1585 /* register * register * 5-bit immediate,
1586 SourceB * SourceA * Index
1590 str = skip_space (str);
1595 str = parse_exp (str, &e1);
1596 if (e1.X_op == O_constant)
1598 indx = e1.X_add_number;
1600 if (indx < 0 || indx > 31)
1602 as_bad ("Index out of range");
1608 as_bad ("Index(SourceA) required");
1613 str = skip_space (str);
1617 as_bad ("Index(SourceA) required");
1621 str = skip_space (str + 1);
1623 ans = parse_gen_reg (&str, &r1);
1626 as_bad ("SourceA register required");
1629 str = skip_space (str);
1632 as_bad ("(SourceA) required");
1635 str = skip_space (str + 1);
1639 str = skip_space (str + 1);
1640 ans = parse_gen_reg (&str, &r2);
1643 as_bad ("SourceB register required");
1649 as_bad ("SourceB register required");
1653 opcode |= (r1 << 16) | (r2 << 4) | ((indx & 0x1f) << 10);
1655 if (indx != 0 && previous_mode == mode_cad)
1657 /* We're in a delay slot.
1658 If the base reg is the destination of the branch, then issue
1660 Otherwise it is safe to use the base and index. */
1661 if (previous_dest != 0 && r1 == previous_dest)
1663 as_bad ("base register not ready");
1667 else if (previous_dest != 0
1668 && r1 == previous_dest
1669 && (visium_arch == VISIUM_ARCH_MCM
1670 || visium_arch == VISIUM_ARCH_MCM24
1671 || (visium_arch == VISIUM_ARCH_DEF && indx != 0)))
1673 as_warn ("base register not ready, NOP inserted.");
1674 /* Insert a NOP before the write instruction. */
1675 output = frag_more (4);
1676 memset (output, 0, 4);
1681 /* register := register * 5-bit immediate
1685 ans = parse_gen_reg (&str, &r1);
1688 as_bad ("Dest register required");
1691 str = skip_space (str);
1694 as_bad ("SourceA required");
1697 str = skip_space (str + 1);
1702 str = parse_exp (str, &e1);
1703 if (e1.X_op == O_constant)
1705 indx = e1.X_add_number;
1707 if (indx < 0 || indx > 31)
1709 as_bad ("Index out of range");
1715 as_bad ("Immediate 0 to 31 required");
1721 as_bad ("(SourceA) required");
1725 ans = parse_gen_reg (&str, &r2);
1728 as_bad ("SourceA register required");
1731 str = skip_space (str);
1734 as_bad ("(SourceA) required");
1738 opcode |= (r1 << 10) | (r2 << 16) | ((indx & 0x1f) << 4);
1741 if (indx != 0 && previous_mode == mode_cad)
1743 /* We're in a delay slot.
1744 If the base reg is the destination of the branch, then issue
1746 Otherwise it is safe to use the base and index. */
1747 if (previous_dest != 0 && r2 == previous_dest)
1749 as_bad ("base register not ready");
1753 else if (previous_dest != 0
1754 && r2 == previous_dest
1755 && (visium_arch == VISIUM_ARCH_MCM
1756 || visium_arch == VISIUM_ARCH_MCM24
1757 || (visium_arch == VISIUM_ARCH_DEF && indx != 0)))
1759 as_warn ("base register not ready, NOP inserted.");
1760 /* Insert a NOP before the read instruction. */
1761 output = frag_more (4);
1762 memset (output, 0, 4);
1770 str = skip_space (str);
1774 /* condition * 16-bit signed word displacement
1777 ans = parse_cc (&str, &cc);
1780 as_bad ("condition code required");
1783 opcode |= (cc << 27);
1785 str = skip_space (str);
1788 str = skip_space (str + 1);
1789 str = parse_exp (str, &e1);
1790 if (e1.X_op != O_absent)
1792 if (e1.X_op == O_constant)
1794 int imm = e1.X_add_number;
1796 if (imm < -32768 || imm > 32767)
1797 as_bad ("immediate value out of range");
1799 /* The GR6 doesn't correctly handle a 0 displacement
1800 so we insert a NOP and change it to -1. */
1801 if (imm == 0 && cc != 0 && visium_arch == VISIUM_ARCH_GR6)
1803 output = frag_more (4);
1804 memset (output, 0, 4);
1808 opcode |= (imm & 0xffff);
1810 else if (e1.X_op == O_symbol)
1812 /* The GR6 doesn't correctly handle a 0 displacement
1813 so the instruction requires relaxation. */
1814 if (cc != 0 && visium_arch == VISIUM_ARCH_GR6)
1817 reloc = BFD_RELOC_VISIUM_REL16;
1821 as_bad ("immediate value missing");
1827 as_bad ("immediate value missing");
1833 as_bad ("immediate value missing");
1837 if (previous_mode == mode_cad || previous_mode == mode_ci)
1838 as_bad ("branch instruction in delay slot");
1840 condition_code = cc;
1844 /* float := float * float
1847 ans = parse_fp_reg (&str, &r1);
1850 as_bad ("floating point destination register required");
1853 str = skip_space (str);
1857 ans = parse_fp_reg (&str, &r2);
1860 as_bad ("floating point SourceA register required");
1863 str = skip_space (str);
1867 ans = parse_fp_reg (&str, &r3);
1870 as_bad ("floating point SourceB register required");
1874 /* Got 3 floating regs, assemble instruction. */
1875 opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
1879 as_bad ("floating point SourceB register required");
1885 as_bad ("floating point SourceA register required");
1891 /* 4-bit immediate * float * float * float
1893 fpinst 10,f1,f2,f3 */
1894 str = parse_exp (str, &e1);
1895 str = skip_space (str);
1896 if (e1.X_op != O_absent && *str == ',')
1898 int finst = e1.X_add_number;
1900 str = skip_space (str + 1);
1901 ans = parse_fp_reg (&str, &r1);
1904 as_bad ("floating point destination register required");
1907 str = skip_space (str);
1911 ans = parse_fp_reg (&str, &r2);
1914 as_bad ("floating point SourceA register required");
1917 str = skip_space (str);
1921 ans = parse_fp_reg (&str, &r3);
1924 as_bad ("floating point SourceB register required");
1928 /* Got immediate and 3 floating regs,
1929 assemble instruction. */
1930 if (finst < 0 || finst > 15)
1931 as_bad ("finst out of range");
1934 ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 <<
1939 as_bad ("floating point SourceB register required");
1945 as_bad ("floating point SourceA register required");
1951 as_bad ("finst missing");
1957 /* 4-bit immediate * register * float * float
1959 fpuread 4,r25,f2,f3 */
1960 str = parse_exp (str, &e1);
1961 str = skip_space (str);
1962 if (e1.X_op != O_absent && *str == ',')
1964 int finst = e1.X_add_number;
1966 str = skip_space (str + 1);
1967 ans = parse_gen_reg (&str, &r1);
1970 as_bad ("destination general register required");
1973 str = skip_space (str);
1977 ans = parse_fp_reg (&str, &r2);
1980 as_bad ("floating point SourceA register required");
1983 str = skip_space (str);
1987 ans = parse_fp_reg (&str, &r3);
1990 as_bad ("floating point SourceB register required");
1994 /* Got immediate and 3 floating regs,
1995 assemble instruction. */
1996 if (finst < 0 || finst > 15)
1997 as_bad ("finst out of range");
2000 ((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 <<
2005 as_bad ("floating point SourceB register required");
2011 as_bad ("floating point SourceA register required");
2017 as_bad ("finst missing");
2026 ans = parse_fp_reg (&str, &r1);
2029 as_bad ("floating point destination register required");
2032 str = skip_space (str);
2036 ans = parse_fp_reg (&str, &r2);
2039 as_bad ("floating point source register required");
2043 /* Got 2 floating regs, assemble instruction. */
2044 opcode |= (r1 << 10) | (r2 << 16);
2048 as_bad ("floating point source register required");
2054 /* float := register
2057 ans = parse_fp_reg (&str, &r1);
2060 as_bad ("floating point destination register required");
2063 str = skip_space (str);
2067 ans = parse_gen_reg (&str, &r2);
2070 as_bad ("SourceA general register required");
2074 /* Got 2 regs, assemble instruction. */
2075 opcode |= (r1 << 10) | (r2 << 16);
2079 as_bad ("SourceA general register required");
2085 /* register := float * float
2088 For the GR6, register must be r0 and can be omitted. */
2089 ans = parse_gen_reg (&str, &r1);
2092 if (visium_opcode_arch == VISIUM_OPCODE_ARCH_GR5)
2094 as_bad ("Dest general register required");
2101 if (r1 != 0 && visium_opcode_arch != VISIUM_OPCODE_ARCH_GR5)
2103 as_bad ("FCMP/FCMPE can only use r0 as Dest register");
2107 str = skip_space (str);
2112 as_bad ("floating point SourceA register required");
2117 ans = parse_fp_reg (&str, &r2);
2120 as_bad ("floating point SourceA register required");
2123 str = skip_space (str);
2127 ans = parse_fp_reg (&str, &r3);
2130 as_bad ("floating point SourceB register required");
2134 /* Got 3 regs, assemble instruction. */
2135 opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
2142 /* register := float
2145 ans = parse_gen_reg (&str, &r1);
2148 as_bad ("Dest general register required");
2151 str = skip_space (str);
2155 ans = parse_fp_reg (&str, &r2);
2158 as_bad ("floating point source register required");
2162 /* Got 2 regs, assemble instruction. */
2163 opcode |= (r1 << 10) | (r2 << 16);
2167 as_bad ("floating point source register required");
2175 /* register register register, all sources and destinations
2179 ans = parse_gen_reg (&str, &r1);
2182 as_bad ("destination address register required");
2185 str = skip_space (str);
2189 ans = parse_gen_reg (&str, &r2);
2192 as_bad ("source address register required");
2195 str = skip_space (str);
2199 ans = parse_gen_reg (&str, &r3);
2202 as_bad ("count register required");
2206 /* We insist on three registers but the opcode can only use
2208 if (r1 != 1 || r2 != 2 || r3 != 3)
2210 as_bad ("BMI/BMD can only use format op r1,r2,r3");
2214 /* Opcode is unmodified by what comes out of the table. */
2218 as_bad ("register required");
2224 as_bad ("register required");
2236 output = frag_var (rs_machine_dependent, 8, 4, relax, e1.X_add_symbol,
2237 e1.X_add_number, NULL);
2239 output = frag_more (4);
2241 /* Build the 32-bit instruction in a host-endian-neutral fashion. */
2242 output[0] = (opcode >> 24) & 0xff;
2243 output[1] = (opcode >> 16) & 0xff;
2244 output[2] = (opcode >> 8) & 0xff;
2245 output[3] = (opcode >> 0) & 0xff;
2248 /* The size of the instruction is unknown, so tie the debug info to the
2249 start of the instruction. */
2250 dwarf2_emit_insn (0);
2254 fix_new_exp (frag_now, output - frag_now->fr_literal, 4, &e1,
2255 reloc == BFD_RELOC_VISIUM_REL16, reloc);
2257 visium_update_parity_bit (output);
2259 dwarf2_emit_insn (4);
2263 as_bad ("junk after instruction");
2267 visium_cfi_frame_initial_instructions (void)
2269 /* The CFA is in SP on function entry. */
2270 cfi_add_CFA_def_cfa (23, 0);
2274 visium_regname_to_dw2regnum (char *regname)
2279 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
2282 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
2285 if (regname[0] == 'm' && regname[1] == 'd' && !regname[3])
2288 case 'b': return 32;
2289 case 'a': return 33;
2290 case 'c': return 34;
2291 default : return -1;
2294 if (regname[0] == 'f' || regname[0] == 'r')
2297 unsigned int regnum = strtoul (regname + 1, &p, 10);
2300 if (regnum >= (regname[0] == 'f' ? 16 : 32))
2302 if (regname[0] == 'f')