3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "dwarf2dbg.h"
24 #include "safe-ctype.h"
26 #include "opcode/tic6x.h"
27 #include "elf/tic6x.h"
28 #include "elf32-tic6x.h"
30 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit
31 host gives identical results to a 32-bit host. */
32 #define TRUNC(X) ((valueT) (X) & 0xffffffffU)
33 #define SEXT(X) ((TRUNC (X) ^ 0x80000000U) - 0x80000000U)
35 const char comment_chars[] = ";";
36 const char line_comment_chars[] = "#*;";
37 const char line_separator_chars[] = "@";
39 const char EXP_CHARS[] = "eE";
40 const char FLT_CHARS[] = "dDfF";
42 const char *md_shortopts = "";
46 OPTION_MARCH = OPTION_MD_BASE,
50 OPTION_MLITTLE_ENDIAN,
54 struct option md_longopts[] =
56 { "march", required_argument, NULL, OPTION_MARCH },
57 { "matomic", no_argument, NULL, OPTION_MATOMIC },
58 { "mno-atomic", no_argument, NULL, OPTION_MNO_ATOMIC },
59 { "mbig-endian", no_argument, NULL, OPTION_MBIG_ENDIAN },
60 { "mlittle-endian", no_argument, NULL, OPTION_MLITTLE_ENDIAN },
61 { "mgenerate-rel", no_argument, NULL, OPTION_MGENERATE_REL },
62 { NULL, no_argument, NULL, 0 }
64 size_t md_longopts_size = sizeof (md_longopts);
66 /* Whether to enable atomic instructions. 1 to enable them, 0 to
67 disable, -1 to default from architecture. */
68 static int tic6x_atomic = -1;
70 /* The instructions enabled based only on the selected architecture
71 (all instructions, if no architecture specified). Atomic
72 instructions may be enabled or disabled separately. */
73 static unsigned short tic6x_arch_enable = (TIC6X_INSN_C62X
81 /* The instructions enabled based on the current set of features
82 (architecture, as modified by other options). */
83 static unsigned short tic6x_features;
85 /* The architecture attribute value, or C6XABI_Tag_CPU_arch_none if
87 static int tic6x_arch_attribute = C6XABI_Tag_CPU_arch_none;
89 /* Whether any instructions at all have been seen. Once any
90 instructions have been seen, architecture attributes merge into the
91 previous attribute value rather than replacing it. */
92 static bfd_boolean tic6x_seen_insns = FALSE;
94 /* The number of registers in each register file supported by the
95 current architecture. */
96 static unsigned int tic6x_num_registers;
98 /* Whether predication on A0 is possible. */
99 static bfd_boolean tic6x_predicate_a0;
101 /* Whether execute packets can cross fetch packet boundaries. */
102 static bfd_boolean tic6x_can_cross_fp_boundary;
104 /* Whether there are constraints on simultaneous reads and writes of
106 static bfd_boolean tic6x_long_data_constraints;
108 /* Whether compact instructions are available. */
109 static bfd_boolean tic6x_compact_insns;
111 /* Whether to generate RELA relocations. */
112 static bfd_boolean tic6x_generate_rela = TRUE;
114 /* Table of supported architecture variants. */
119 unsigned short features;
121 static const tic6x_arch_table tic6x_arches[] =
123 { "c62x", C6XABI_Tag_CPU_arch_C62X, TIC6X_INSN_C62X },
124 { "c64x", C6XABI_Tag_CPU_arch_C64X, TIC6X_INSN_C62X | TIC6X_INSN_C64X },
125 { "c64x+", C6XABI_Tag_CPU_arch_C64XP, (TIC6X_INSN_C62X
127 | TIC6X_INSN_C64XP) },
128 { "c67x", C6XABI_Tag_CPU_arch_C67X, TIC6X_INSN_C62X | TIC6X_INSN_C67X },
129 { "c67x+", C6XABI_Tag_CPU_arch_C67XP, (TIC6X_INSN_C62X
131 | TIC6X_INSN_C67XP) },
132 { "c674x", C6XABI_Tag_CPU_arch_C674X, (TIC6X_INSN_C62X
137 | TIC6X_INSN_C674X) }
140 /* Update the selected architecture based on ARCH, giving an error if
141 ARCH is an invalid value. Does not call tic6x_update_features; the
142 caller must do that if necessary. */
145 tic6x_use_arch (const char *arch)
149 for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
150 if (strcmp (arch, tic6x_arches[i].arch) == 0)
152 tic6x_arch_enable = tic6x_arches[i].features;
153 if (tic6x_seen_insns)
155 = elf32_tic6x_merge_arch_attributes (tic6x_arch_attribute,
156 tic6x_arches[i].attr);
158 tic6x_arch_attribute = tic6x_arches[i].attr;
162 as_bad (_("unknown architecture '%s'"), arch);
165 /* Parse a target-specific option. */
168 md_parse_option (int c, char *arg)
173 tic6x_use_arch (arg);
180 case OPTION_MNO_ATOMIC:
184 case OPTION_MBIG_ENDIAN:
185 target_big_endian = 1;
188 case OPTION_MLITTLE_ENDIAN:
189 target_big_endian = 0;
192 case OPTION_MGENERATE_REL:
193 tic6x_generate_rela = FALSE;
203 md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
207 fputc ('\n', stream);
208 fprintf (stream, _("TMS320C6000 options:\n"));
209 fprintf (stream, _(" -march=ARCH enable instructions from architecture ARCH\n"));
210 fprintf (stream, _(" -matomic enable atomic operation instructions\n"));
211 fprintf (stream, _(" -mno-atomic disable atomic operation instructions\n"));
212 fprintf (stream, _(" -mbig-endian generate big-endian code\n"));
213 fprintf (stream, _(" -mlittle-endian generate little-endian code\n"));
214 /* -mgenerate-rel is only for testsuite use and is deliberately
217 fputc ('\n', stream);
218 fprintf (stream, _("Supported ARCH values are:"));
219 for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
220 fprintf (stream, " %s", tic6x_arches[i].arch);
221 fputc ('\n', stream);
224 /* Update enabled features based on the current architecture and
227 tic6x_update_features (void)
229 switch (tic6x_atomic)
232 tic6x_features = tic6x_arch_enable;
236 tic6x_features = tic6x_arch_enable & ~TIC6X_INSN_ATOMIC;
240 tic6x_features = tic6x_arch_enable | TIC6X_INSN_ATOMIC;
248 = (tic6x_arch_enable & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? 32 : 16;
250 tic6x_predicate_a0 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? TRUE : FALSE;
252 tic6x_can_cross_fp_boundary
254 & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? TRUE : FALSE;
256 tic6x_long_data_constraints
257 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? FALSE : TRUE;
259 tic6x_compact_insns = (tic6x_arch_enable & TIC6X_INSN_C64XP) ? TRUE : FALSE;
262 /* Do configuration after all options have been parsed. */
265 tic6x_after_parse_args (void)
267 tic6x_update_features ();
270 /* Parse a .arch directive. */
273 s_tic6x_arch (int ignored ATTRIBUTE_UNUSED)
278 arch = input_line_pointer;
279 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
280 input_line_pointer++;
281 c = *input_line_pointer;
282 *input_line_pointer = 0;
284 tic6x_use_arch (arch);
285 tic6x_update_features ();
286 *input_line_pointer = c;
287 demand_empty_rest_of_line ();
290 /* Parse a .atomic directive. */
293 s_tic6x_atomic (int ignored ATTRIBUTE_UNUSED)
296 tic6x_update_features ();
297 demand_empty_rest_of_line ();
300 /* Parse a .noatomic directive. */
303 s_tic6x_noatomic (int ignored ATTRIBUTE_UNUSED)
306 tic6x_update_features ();
307 demand_empty_rest_of_line ();
310 /* Parse a .nocmp directive. */
313 s_tic6x_nocmp (int ignored ATTRIBUTE_UNUSED)
315 seg_info (now_seg)->tc_segment_info_data.nocmp = TRUE;
316 demand_empty_rest_of_line ();
319 /* Track for each attribute whether it has been set explicitly (and so
320 should not have a default value set by the assembler). */
321 static bfd_boolean tic6x_attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
323 /* Parse a .c6xabi_attribute directive. */
326 s_tic6x_c6xabi_attribute (int ignored ATTRIBUTE_UNUSED)
328 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
330 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
331 tic6x_attributes_set_explicitly[tag] = TRUE;
338 } tic6x_attribute_table;
340 static const tic6x_attribute_table tic6x_attributes[] =
342 #define TAG(tag, value) { #tag, tag }
343 #include "elf/tic6x-attrs.h"
347 /* Convert an attribute name to a number. */
350 tic6x_convert_symbolic_attribute (const char *name)
354 for (i = 0; i < ARRAY_SIZE (tic6x_attributes); i++)
355 if (strcmp (name, tic6x_attributes[i].name) == 0)
356 return tic6x_attributes[i].tag;
361 const pseudo_typeS md_pseudo_table[] =
363 { "arch", s_tic6x_arch, 0 },
364 { "atomic", s_tic6x_atomic, 0 },
365 { "c6xabi_attribute", s_tic6x_c6xabi_attribute, 0 },
366 { "noatomic", s_tic6x_noatomic, 0 },
367 { "nocmp", s_tic6x_nocmp, 0 },
372 /* Hash table of opcodes. For each opcode name, this stores a pointer
373 to a tic6x_opcode_list listing (in an arbitrary order) all opcode
374 table entries with that name. */
375 static struct hash_control *opcode_hash;
377 /* Initialize the assembler (called once at assembler startup). */
384 bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
386 /* Insert opcodes into the hash table. */
387 opcode_hash = hash_new ();
388 for (id = 0; id < tic6x_opcode_max; id++)
391 tic6x_opcode_list *opc = xmalloc (sizeof (tic6x_opcode_list));
394 opc->next = hash_find (opcode_hash, tic6x_opcode_table[id].name);
395 if ((errmsg = hash_jam (opcode_hash, tic6x_opcode_table[id].name, opc))
397 as_fatal ("%s", _(errmsg));
401 /* Whether the current line being parsed had the "||" parallel bars. */
402 static bfd_boolean tic6x_line_parallel;
404 /* Whether the current line being parsed started "||^" to indicate an
405 SPMASKed parallel instruction. */
406 static bfd_boolean tic6x_line_spmask;
408 /* If the current line being parsed had an instruction predicate, the
409 creg value for that predicate (which must be nonzero); otherwise
411 static unsigned int tic6x_line_creg;
413 /* If the current line being parsed had an instruction predicate, the
414 z value for that predicate; otherwise 0. */
415 static unsigned int tic6x_line_z;
417 /* Return 1 (updating input_line_pointer as appropriate) if the line
418 starting with C (immediately before input_line_pointer) starts with
419 pre-opcode text appropriate for this target, 0 otherwise. */
422 tic6x_unrecognized_line (int c)
427 bfd_boolean bad_predicate;
432 if (input_line_pointer[0] == '|')
434 if (input_line_pointer[1] == '^')
436 tic6x_line_spmask = TRUE;
437 input_line_pointer += 2;
440 input_line_pointer += 1;
441 if (tic6x_line_parallel)
442 as_bad (_("multiple '||' on same line"));
443 tic6x_line_parallel = TRUE;
445 as_bad (_("'||' after predicate"));
451 /* If it doesn't look like a predicate at all, just return 0.
452 If it looks like one but not a valid one, give a better
454 p = input_line_pointer;
455 while (*p != ']' && !is_end_of_line[(unsigned char) *p])
460 p = input_line_pointer;
462 bad_predicate = FALSE;
468 if (*p == 'A' || *p == 'a')
470 else if (*p == 'B' || *p == 'b')
474 areg = TRUE; /* Avoid uninitialized warning. */
475 bad_predicate = TRUE;
480 if (*p != '0' && *p != '1' && *p != '2')
481 bad_predicate = TRUE;
482 else if (p[1] != ']')
483 bad_predicate = TRUE;
485 input_line_pointer = p + 2;
489 as_bad (_("multiple predicates on same line"));
495 as_bad (_("bad predicate '%s'"), input_line_pointer - 1);
497 input_line_pointer = endp;
504 tic6x_line_creg = (areg ? 6 : 1);
505 if (areg && !tic6x_predicate_a0)
506 as_bad (_("predication on A0 not supported on this architecture"));
510 tic6x_line_creg = (areg ? 4 : 2);
514 tic6x_line_creg = (areg ? 5 : 3);
529 /* Do any target-specific handling of a label required. */
532 tic6x_frob_label (symbolS *sym)
534 segment_info_type *si;
535 tic6x_label_list *list;
537 if (tic6x_line_parallel)
539 as_bad (_("label after '||'"));
540 tic6x_line_parallel = FALSE;
541 tic6x_line_spmask = FALSE;
545 as_bad (_("label after predicate"));
550 si = seg_info (now_seg);
551 list = si->tc_segment_info_data.label_list;
552 si->tc_segment_info_data.label_list = xmalloc (sizeof (tic6x_label_list));
553 si->tc_segment_info_data.label_list->next = list;
554 si->tc_segment_info_data.label_list->label = sym;
556 /* Defining tc_frob_label overrides the ELF definition of
557 obj_frob_label, so we need to apply its effects here. */
558 dwarf2_emit_label (sym);
561 /* At end-of-line, give errors for start-of-line decorations that
562 needed an instruction but were not followed by one. */
565 tic6x_end_of_line (void)
567 if (tic6x_line_parallel)
569 as_bad (_("'||' not followed by instruction"));
570 tic6x_line_parallel = FALSE;
571 tic6x_line_spmask = FALSE;
575 as_bad (_("predicate not followed by instruction"));
581 /* Do any target-specific handling of the start of a logical line. */
584 tic6x_start_line_hook (void)
586 tic6x_end_of_line ();
589 /* Do target-specific handling immediately after an input file from
590 the command line, and any other inputs it includes, have been
596 tic6x_end_of_line ();
599 /* Do target-specific initialization after arguments have been
600 processed and the output file created. */
603 tic6x_init_after_args (void)
605 elf32_tic6x_set_use_rela_p (stdoutput, tic6x_generate_rela);
608 /* Free LIST of labels (possibly NULL). */
611 tic6x_free_label_list (tic6x_label_list *list)
615 tic6x_label_list *old = list;
622 /* Handle a data alignment of N bytes. */
625 tic6x_cons_align (int n ATTRIBUTE_UNUSED)
627 segment_info_type *seginfo = seg_info (now_seg);
629 /* Data means there is no current execute packet, and that any label
630 applies to that data rather than a subsequent instruction. */
631 tic6x_free_label_list (seginfo->tc_segment_info_data.label_list);
632 seginfo->tc_segment_info_data.label_list = NULL;
633 seginfo->tc_segment_info_data.execute_packet_frag = NULL;
634 seginfo->tc_segment_info_data.last_insn_lsb = NULL;
635 seginfo->tc_segment_info_data.spmask_addr = NULL;
638 /* Handle an alignment directive. Return TRUE if the
639 machine-independent frag generation should be skipped. */
642 tic6x_do_align (int n, char *fill, int len ATTRIBUTE_UNUSED, int max)
644 /* Given code alignments of 4, 8, 16 or 32 bytes, we try to handle
645 them in the md_end pass by inserting NOPs in parallel with
646 previous instructions. We only do this in sections containing
647 nothing but instructions. Code alignments of 1 or 2 bytes have
648 no effect in such sections (but we record them with
649 machine-dependent frags anyway so they can be skipped or
650 converted to machine-independent), while those of more than 64
651 bytes cannot reliably be handled in this way. */
657 && subseg_text_p (now_seg))
665 /* Machine-independent code would generate a frag here, but we
666 wish to handle it in a machine-dependent way. */
667 if (frag_now_fix () != 0)
669 if (frag_now->fr_type != rs_machine_dependent)
670 frag_wane (frag_now);
675 align_frag = frag_now;
676 p = frag_var (rs_machine_dependent, 32, 32, max, NULL, n, NULL);
677 /* This must be the same as the frag to which a pointer was just
679 if (p != align_frag->fr_literal)
681 align_frag->tc_frag_data.is_insns = FALSE;
688 /* Types of operand for parsing purposes. These are used as bit-masks
689 to tell tic6x_parse_operand what forms of operand are
691 #define TIC6X_OP_EXP 0x0001u
692 #define TIC6X_OP_REG 0x0002u
693 #define TIC6X_OP_REGPAIR 0x0004u
694 #define TIC6X_OP_IRP 0x0008u
695 #define TIC6X_OP_NRP 0x0010u
696 /* With TIC6X_OP_MEM_NOUNREG, the contents of a () offset are always
697 interpreted as an expression, which may be a symbol with the same
698 name as a register that ends up being implicitly DP-relative. With
699 TIC6X_OP_MEM_UNREG, the contents of a () offset are interpreted as
700 a register if they match one, and failing that as an expression,
701 which must be constant. */
702 #define TIC6X_OP_MEM_NOUNREG 0x0020u
703 #define TIC6X_OP_MEM_UNREG 0x0040u
704 #define TIC6X_OP_CTRL 0x0080u
705 #define TIC6X_OP_FUNC_UNIT 0x0100u
707 /* A register or register pair read by the assembler. */
710 /* The side the register is on (1 or 2). */
712 /* The register number (0 to 31). */
716 /* Types of modification of a base address. */
722 tic6x_mem_mod_preinc,
723 tic6x_mem_mod_predec,
724 tic6x_mem_mod_postinc,
725 tic6x_mem_mod_postdec
728 /* Scaled [] or unscaled () nature of an offset. */
733 tic6x_offset_unscaled
736 /* A memory operand read by the assembler. */
739 /* The base register. */
740 tic6x_register base_reg;
741 /* How the base register is modified. */
743 /* Whether there is an offset (required with plain "+" and "-"), and
744 whether it is scaled or unscaled if so. */
745 tic6x_mem_scaling scaled;
746 /* Whether the offset is a register (TRUE) or an expression
748 bfd_boolean offset_is_reg;
757 /* A functional unit in SPMASK operands read by the assembler. */
760 /* The basic unit. */
761 tic6x_func_unit_base base;
762 /* The side (1 or 2). */
764 } tic6x_func_unit_operand;
766 /* An operand read by the assembler. */
769 /* The syntactic form of the operand, as one of the bit-masks
772 /* The operand value. */
775 /* An expression: TIC6X_OP_EXP. */
777 /* A register: TIC6X_OP_REG, TIC6X_OP_REGPAIR. */
779 /* A memory reference: TIC6X_OP_MEM_NOUNREG,
780 TIC6X_OP_MEM_UNREG. */
782 /* A control register: TIC6X_OP_CTRL. */
784 /* A functional unit: TIC6X_OP_FUNC_UNIT. */
785 tic6x_func_unit_operand func_unit;
789 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
791 /* Parse a register operand, or part of an operand, starting at *P.
792 If syntactically OK (including that the number is in the range 0 to
793 31, but not necessarily in range for this architecture), return
794 TRUE, putting the register side and number in *REG and update *P to
795 point immediately after the register number; otherwise return FALSE
796 without changing *P (but possibly changing *REG). Do not print any
800 tic6x_parse_register (char **p, tic6x_register *reg)
821 if (*r >= '0' && *r <= '9')
829 if (reg->num > 0 && *r >= '0' && *r <= '9')
831 reg->num = reg->num * 10 + (*r - '0');
835 if (*r >= '0' && *r <= '9')
844 /* Parse the initial two characters of a functional unit name starting
845 at *P. If OK, set *BASE and *SIDE and return TRUE; otherwise,
849 tic6x_parse_func_unit_base (char *p, tic6x_func_unit_base *base,
852 bfd_boolean good_func_unit = TRUE;
853 tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
854 unsigned int maybe_side = 0;
860 maybe_base = tic6x_func_unit_d;
865 maybe_base = tic6x_func_unit_l;
870 maybe_base = tic6x_func_unit_m;
875 maybe_base = tic6x_func_unit_s;
879 good_func_unit = FALSE;
895 good_func_unit = FALSE;
905 return good_func_unit;
908 /* Parse an operand starting at *P. If the operand parses OK, return
909 TRUE and store the value in *OP; otherwise return FALSE (possibly
910 changing *OP). In any case, update *P to point to the following
911 comma or end of line. The possible operand forms are given by
912 OP_FORMS. For diagnostics, this is operand OPNO of an opcode
913 starting at STR, length OPC_LEN. */
916 tic6x_parse_operand (char **p, tic6x_operand *op, unsigned int op_forms,
917 char *str, int opc_len, unsigned int opno)
919 bfd_boolean operand_parsed = FALSE;
922 if ((op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
923 == (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
926 /* Check for functional unit names for SPMASK and SPMASKR. */
927 if (!operand_parsed && (op_forms & TIC6X_OP_FUNC_UNIT))
929 tic6x_func_unit_base base = tic6x_func_unit_nfu;
930 unsigned int side = 0;
932 if (tic6x_parse_func_unit_base (q, &base, &side))
936 skip_whitespace (rq);
937 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
939 op->form = TIC6X_OP_FUNC_UNIT;
940 op->value.func_unit.base = base;
941 op->value.func_unit.side = side;
942 operand_parsed = TRUE;
948 /* Check for literal "irp". */
949 if (!operand_parsed && (op_forms & TIC6X_OP_IRP))
951 if ((q[0] == 'i' || q[0] == 'I')
952 && (q[1] == 'r' || q[1] == 'R')
953 && (q[2] == 'p' || q[2] == 'P'))
957 skip_whitespace (rq);
958 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
960 op->form = TIC6X_OP_IRP;
961 operand_parsed = TRUE;
967 /* Check for literal "nrp". */
968 if (!operand_parsed && (op_forms & TIC6X_OP_NRP))
970 if ((q[0] == 'n' || q[0] == 'N')
971 && (q[1] == 'r' || q[1] == 'R')
972 && (q[2] == 'p' || q[2] == 'P'))
976 skip_whitespace (rq);
977 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
979 op->form = TIC6X_OP_NRP;
980 operand_parsed = TRUE;
986 /* Check for control register names. */
987 if (!operand_parsed && (op_forms & TIC6X_OP_CTRL))
991 for (crid = 0; crid < tic6x_ctrl_max; crid++)
993 size_t len = strlen (tic6x_ctrl_table[crid].name);
995 if (strncasecmp (tic6x_ctrl_table[crid].name, q, len) == 0)
999 skip_whitespace (rq);
1000 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1002 op->form = TIC6X_OP_CTRL;
1003 op->value.ctrl = crid;
1004 operand_parsed = TRUE;
1006 if (!(tic6x_ctrl_table[crid].isa_variants & tic6x_features))
1007 as_bad (_("control register '%s' not supported "
1008 "on this architecture"),
1009 tic6x_ctrl_table[crid].name);
1015 /* See if this looks like a memory reference. */
1017 && (op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG)))
1019 bfd_boolean mem_ok = TRUE;
1021 tic6x_mem_mod mem_mod = tic6x_mem_mod_none;
1022 tic6x_register base_reg;
1023 bfd_boolean require_offset, permit_offset;
1024 tic6x_mem_scaling scaled;
1025 bfd_boolean offset_is_reg;
1026 expressionS offset_exp;
1027 tic6x_register offset_reg;
1036 skip_whitespace (mq);
1042 mem_mod = tic6x_mem_mod_preinc;
1047 mem_mod = tic6x_mem_mod_plus;
1055 mem_mod = tic6x_mem_mod_predec;
1060 mem_mod = tic6x_mem_mod_minus;
1072 skip_whitespace (mq);
1073 mem_ok = tic6x_parse_register (&mq, &base_reg);
1076 if (mem_ok && mem_mod == tic6x_mem_mod_none)
1078 skip_whitespace (mq);
1079 if (mq[0] == '+' && mq[1] == '+')
1081 mem_mod = tic6x_mem_mod_postinc;
1084 else if (mq[0] == '-' && mq[1] == '-')
1086 mem_mod = tic6x_mem_mod_postdec;
1091 if (mem_mod == tic6x_mem_mod_none)
1092 permit_offset = FALSE;
1094 permit_offset = TRUE;
1095 if (mem_mod == tic6x_mem_mod_plus || mem_mod == tic6x_mem_mod_minus)
1096 require_offset = TRUE;
1098 require_offset = FALSE;
1099 scaled = tic6x_offset_none;
1100 offset_is_reg = FALSE;
1102 if (mem_ok && permit_offset)
1106 skip_whitespace (mq);
1110 scaled = tic6x_offset_scaled;
1116 scaled = tic6x_offset_unscaled;
1124 if (scaled != tic6x_offset_none)
1126 skip_whitespace (mq);
1127 if (scaled == tic6x_offset_scaled
1128 || (op_forms & TIC6X_OP_MEM_UNREG))
1133 reg_ok = tic6x_parse_register (&rq, &offset_reg);
1136 skip_whitespace (rq);
1140 offset_is_reg = TRUE;
1146 char *save_input_line_pointer;
1148 save_input_line_pointer = input_line_pointer;
1149 input_line_pointer = mq;
1150 expression (&offset_exp);
1151 mq = input_line_pointer;
1152 input_line_pointer = save_input_line_pointer;
1154 skip_whitespace (mq);
1162 if (mem_ok && require_offset && scaled == tic6x_offset_none)
1167 skip_whitespace (mq);
1168 if (!is_end_of_line[(unsigned char) *mq] && *mq != ',')
1174 op->form = op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG);
1175 op->value.mem.base_reg = base_reg;
1176 op->value.mem.mod = mem_mod;
1177 op->value.mem.scaled = scaled;
1178 op->value.mem.offset_is_reg = offset_is_reg;
1180 op->value.mem.offset.reg = offset_reg;
1182 op->value.mem.offset.exp = offset_exp;
1183 operand_parsed = TRUE;
1185 if (base_reg.num >= tic6x_num_registers)
1186 as_bad (_("register number %u not supported on this architecture"),
1188 if (offset_is_reg && offset_reg.num >= tic6x_num_registers)
1189 as_bad (_("register number %u not supported on this architecture"),
1194 /* See if this looks like a register or register pair. */
1195 if (!operand_parsed && (op_forms & (TIC6X_OP_REG | TIC6X_OP_REGPAIR)))
1197 tic6x_register first_reg, second_reg;
1201 reg_ok = tic6x_parse_register (&rq, &first_reg);
1205 if (*rq == ':' && (op_forms & TIC6X_OP_REGPAIR))
1208 reg_ok = tic6x_parse_register (&rq, &second_reg);
1211 skip_whitespace (rq);
1212 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1214 if ((second_reg.num & 1)
1215 || (first_reg.num != second_reg.num + 1)
1216 || (first_reg.side != second_reg.side))
1217 as_bad (_("register pair for operand %u of '%.*s'"
1218 " not a valid even/odd pair"), opno,
1220 op->form = TIC6X_OP_REGPAIR;
1221 op->value.reg = second_reg;
1222 operand_parsed = TRUE;
1227 else if (op_forms & TIC6X_OP_REG)
1229 skip_whitespace (rq);
1230 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1232 op->form = TIC6X_OP_REG;
1233 op->value.reg = first_reg;
1234 operand_parsed = TRUE;
1241 if (first_reg.num >= tic6x_num_registers)
1242 as_bad (_("register number %u not supported on this architecture"),
1244 if (op->form == TIC6X_OP_REGPAIR
1245 && second_reg.num >= tic6x_num_registers)
1246 as_bad (_("register number %u not supported on this architecture"),
1251 /* Otherwise, parse it as an expression. */
1252 if (!operand_parsed && (op_forms & TIC6X_OP_EXP))
1254 char *save_input_line_pointer;
1256 save_input_line_pointer = input_line_pointer;
1257 input_line_pointer = q;
1258 op->form = TIC6X_OP_EXP;
1259 expression (&op->value.exp);
1260 q = input_line_pointer;
1261 input_line_pointer = save_input_line_pointer;
1262 operand_parsed = TRUE;
1267 /* Now the operand has been parsed, there must be nothing more
1268 before the comma or end of line. */
1269 skip_whitespace (q);
1270 if (!is_end_of_line[(unsigned char) *q] && *q != ',')
1272 operand_parsed = FALSE;
1273 as_bad (_("junk after operand %u of '%.*s'"), opno,
1275 while (!is_end_of_line[(unsigned char) *q] && *q != ',')
1281 /* This could not be parsed as any acceptable form of
1285 case TIC6X_OP_REG | TIC6X_OP_REGPAIR:
1286 as_bad (_("bad register or register pair for operand %u of '%.*s'"),
1287 opno, opc_len, str);
1290 case TIC6X_OP_REG | TIC6X_OP_CTRL:
1292 as_bad (_("bad register for operand %u of '%.*s'"),
1293 opno, opc_len, str);
1296 case TIC6X_OP_REGPAIR:
1297 as_bad (_("bad register pair for operand %u of '%.*s'"),
1298 opno, opc_len, str);
1301 case TIC6X_OP_FUNC_UNIT:
1302 as_bad (_("bad functional unit for operand %u of '%.*s'"),
1303 opno, opc_len, str);
1307 as_bad (_("bad operand %u of '%.*s'"),
1308 opno, opc_len, str);
1312 while (!is_end_of_line[(unsigned char) *q] && *q != ',')
1316 return operand_parsed;
1319 /* Table of assembler operators and associated O_* values. */
1324 } tic6x_operator_table;
1325 static const tic6x_operator_table tic6x_operators[] = {
1326 #define O_dsbt_index O_md1
1327 { "dsbt_index", O_dsbt_index },
1330 #define O_dpr_got O_md3
1331 { "dpr_got", O_dpr_got },
1332 #define O_dpr_byte O_md4
1333 { "dpr_byte", O_dpr_byte },
1334 #define O_dpr_hword O_md5
1335 { "dpr_hword", O_dpr_hword },
1336 #define O_dpr_word O_md6
1337 { "dpr_word", O_dpr_word },
1340 /* Parse a name in some machine-specific way. Used on C6X to handle
1341 assembler operators. */
1344 tic6x_parse_name (const char *name, expressionS *exprP,
1345 enum expr_mode mode ATTRIBUTE_UNUSED, char *nextchar)
1347 char *p = input_line_pointer;
1348 char c, *name_start, *name_end;
1349 const char *inner_name;
1351 operatorT op = O_illegal;
1357 for (i = 0; i < ARRAY_SIZE (tic6x_operators); i++)
1358 if (strcasecmp (name + 1, tic6x_operators[i].name) == 0)
1360 op = tic6x_operators[i].op;
1364 if (op == O_illegal)
1367 *input_line_pointer = *nextchar;
1368 skip_whitespace (p);
1372 *input_line_pointer = 0;
1376 skip_whitespace (p);
1378 if (!is_name_beginner (*p))
1380 *input_line_pointer = 0;
1386 while (is_part_of_name (*p))
1389 skip_whitespace (p);
1393 *input_line_pointer = 0;
1397 input_line_pointer = p + 1;
1398 *nextchar = *input_line_pointer;
1399 *input_line_pointer = 0;
1403 inner_name = name_start;
1404 if (op == O_dsbt_index && strcmp (inner_name, "__c6xabi_DSBT_BASE") != 0)
1406 as_bad (_("$DSBT_INDEX must be used with __c6xabi_DSBT_BASE"));
1407 inner_name = "__c6xabi_DSBT_BASE";
1409 sym = symbol_find_or_make (inner_name);
1413 exprP->X_add_symbol = sym;
1414 exprP->X_add_number = 0;
1415 exprP->X_op_symbol = NULL;
1421 /* Create a fixup for an expression. Same arguments as fix_new_exp,
1422 plus FIX_ADDA which is TRUE for ADDA instructions (to indicate that
1423 fixes resolving to constants should have those constants implicitly
1424 shifted) and FALSE otherwise, but look for C6X-specific expression
1425 types and adjust the relocations or give errors accordingly. */
1428 tic6x_fix_new_exp (fragS *frag, int where, int size, expressionS *exp,
1429 int pcrel, bfd_reloc_code_real_type r_type,
1430 bfd_boolean fix_adda)
1432 bfd_reloc_code_real_type new_reloc = BFD_RELOC_UNUSED;
1440 case BFD_RELOC_C6000_SBR_U15_W:
1441 new_reloc = BFD_RELOC_C6000_DSBT_INDEX;
1445 as_bad (_("$DSBT_INDEX not supported in this context"));
1453 case BFD_RELOC_C6000_SBR_U15_W:
1454 new_reloc = BFD_RELOC_C6000_SBR_GOT_U15_W;
1458 as_bad (_("$GOT not supported in this context"));
1466 case BFD_RELOC_C6000_ABS_L16:
1467 new_reloc = BFD_RELOC_C6000_SBR_GOT_L16_W;
1470 case BFD_RELOC_C6000_ABS_H16:
1471 new_reloc = BFD_RELOC_C6000_SBR_GOT_H16_W;
1475 as_bad (_("$DPR_GOT not supported in this context"));
1483 case BFD_RELOC_C6000_ABS_S16:
1484 new_reloc = BFD_RELOC_C6000_SBR_S16;
1487 case BFD_RELOC_C6000_ABS_L16:
1488 new_reloc = BFD_RELOC_C6000_SBR_L16_B;
1491 case BFD_RELOC_C6000_ABS_H16:
1492 new_reloc = BFD_RELOC_C6000_SBR_H16_B;
1496 as_bad (_("$DPR_BYTE not supported in this context"));
1504 case BFD_RELOC_C6000_ABS_L16:
1505 new_reloc = BFD_RELOC_C6000_SBR_L16_H;
1508 case BFD_RELOC_C6000_ABS_H16:
1509 new_reloc = BFD_RELOC_C6000_SBR_H16_H;
1513 as_bad (_("$DPR_HWORD not supported in this context"));
1521 case BFD_RELOC_C6000_ABS_L16:
1522 new_reloc = BFD_RELOC_C6000_SBR_L16_W;
1525 case BFD_RELOC_C6000_ABS_H16:
1526 new_reloc = BFD_RELOC_C6000_SBR_H16_W;
1530 as_bad (_("$DPR_WORD not supported in this context"));
1541 as_bad (_("invalid PC-relative operand"));
1547 if (new_reloc == BFD_RELOC_UNUSED)
1548 fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
1550 fix = fix_new (frag, where, size, exp->X_add_symbol, exp->X_add_number,
1552 fix->tc_fix_data.fix_adda = fix_adda;
1555 /* Generate a fix for a constant (.word etc.). Needed to ensure these
1556 go through the error checking in tic6x_fix_new_exp. */
1559 tic6x_cons_fix_new (fragS *frag, int where, int size, expressionS *exp)
1561 bfd_reloc_code_real_type r_type;
1566 r_type = BFD_RELOC_8;
1570 r_type = BFD_RELOC_16;
1574 r_type = BFD_RELOC_32;
1578 as_bad (_("no %d-byte relocations available"), size);
1582 tic6x_fix_new_exp (frag, where, size, exp, 0, r_type, FALSE);
1585 /* Initialize target-specific fix data. */
1588 tic6x_init_fix_data (fixS *fixP)
1590 fixP->tc_fix_data.fix_adda = FALSE;
1593 /* Given the fine-grained form of an operand, return the coarse
1597 tic6x_coarse_operand_form (tic6x_operand_form form)
1601 case tic6x_operand_asm_const:
1602 case tic6x_operand_link_const:
1603 return TIC6X_OP_EXP;
1605 case tic6x_operand_reg:
1606 case tic6x_operand_xreg:
1607 case tic6x_operand_dreg:
1608 case tic6x_operand_areg:
1609 case tic6x_operand_retreg:
1610 return TIC6X_OP_REG;
1612 case tic6x_operand_regpair:
1613 case tic6x_operand_xregpair:
1614 case tic6x_operand_dregpair:
1615 return TIC6X_OP_REGPAIR;
1617 case tic6x_operand_irp:
1618 return TIC6X_OP_IRP;
1620 case tic6x_operand_nrp:
1621 return TIC6X_OP_NRP;
1623 case tic6x_operand_ctrl:
1624 return TIC6X_OP_CTRL;
1626 case tic6x_operand_mem_short:
1627 case tic6x_operand_mem_long:
1628 case tic6x_operand_mem_deref:
1629 return TIC6X_OP_MEM_NOUNREG;
1631 case tic6x_operand_mem_ndw:
1632 return TIC6X_OP_MEM_UNREG;
1634 case tic6x_operand_func_unit:
1635 return TIC6X_OP_FUNC_UNIT;
1642 /* How an operand may match or not match a desired form. If different
1643 instruction alternatives fail in different ways, the first failure
1644 in this list determines the diagnostic. */
1648 tic6x_match_matches,
1649 /* Bad coarse form. */
1652 tic6x_match_non_const,
1653 /* Register on wrong side. */
1654 tic6x_match_wrong_side,
1655 /* Not a valid address register. */
1656 tic6x_match_bad_address,
1657 /* Not a valid return address register. */
1658 tic6x_match_bad_return,
1659 /* Control register not readable. */
1660 tic6x_match_ctrl_write_only,
1661 /* Control register not writable. */
1662 tic6x_match_ctrl_read_only,
1663 /* Not a valid memory reference for this instruction. */
1665 } tic6x_operand_match;
1667 /* Return whether an operand matches the given fine-grained form and
1668 read/write usage, and, if it does not match, how it fails to match.
1669 The main functional unit side is SIDE; the cross-path side is CROSS
1670 (the same as SIDE if a cross path not used); the data side is
1672 static tic6x_operand_match
1673 tic6x_operand_matches_form (const tic6x_operand *op, tic6x_operand_form form,
1674 tic6x_rw rw, unsigned int side, unsigned int cross,
1675 unsigned int data_side)
1677 unsigned int coarse = tic6x_coarse_operand_form (form);
1679 if (coarse != op->form)
1680 return tic6x_match_coarse;
1684 case tic6x_operand_asm_const:
1685 if (op->value.exp.X_op == O_constant)
1686 return tic6x_match_matches;
1688 return tic6x_match_non_const;
1690 case tic6x_operand_link_const:
1691 case tic6x_operand_irp:
1692 case tic6x_operand_nrp:
1693 case tic6x_operand_func_unit:
1694 /* All expressions are link-time constants, although there may
1695 not be relocations to express them in the output file. "irp"
1696 and "nrp" are unique operand values. All parsed functional
1697 unit names are valid. */
1698 return tic6x_match_matches;
1700 case tic6x_operand_reg:
1701 case tic6x_operand_regpair:
1702 if (op->value.reg.side == side)
1703 return tic6x_match_matches;
1705 return tic6x_match_wrong_side;
1707 case tic6x_operand_xreg:
1708 case tic6x_operand_xregpair:
1709 if (op->value.reg.side == cross)
1710 return tic6x_match_matches;
1712 return tic6x_match_wrong_side;
1714 case tic6x_operand_dreg:
1715 case tic6x_operand_dregpair:
1716 if (op->value.reg.side == data_side)
1717 return tic6x_match_matches;
1719 return tic6x_match_wrong_side;
1721 case tic6x_operand_areg:
1722 if (op->value.reg.side != cross)
1723 return tic6x_match_wrong_side;
1724 else if (op->value.reg.side == 2
1725 && (op->value.reg.num == 14 || op->value.reg.num == 15))
1726 return tic6x_match_matches;
1728 return tic6x_match_bad_address;
1730 case tic6x_operand_retreg:
1731 if (op->value.reg.side != side)
1732 return tic6x_match_wrong_side;
1733 else if (op->value.reg.num != 3)
1734 return tic6x_match_bad_return;
1736 return tic6x_match_matches;
1738 case tic6x_operand_ctrl:
1742 if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read
1743 || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
1744 return tic6x_match_matches;
1746 return tic6x_match_ctrl_write_only;
1748 case tic6x_rw_write:
1749 if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_write
1750 || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
1751 return tic6x_match_matches;
1753 return tic6x_match_ctrl_read_only;
1759 case tic6x_operand_mem_deref:
1760 if (op->value.mem.mod != tic6x_mem_mod_none)
1761 return tic6x_match_bad_mem;
1762 else if (op->value.mem.scaled != tic6x_offset_none)
1764 else if (op->value.mem.base_reg.side != side)
1765 return tic6x_match_bad_mem;
1767 return tic6x_match_matches;
1769 case tic6x_operand_mem_short:
1770 case tic6x_operand_mem_ndw:
1771 if (op->value.mem.base_reg.side != side)
1772 return tic6x_match_bad_mem;
1773 if (op->value.mem.mod == tic6x_mem_mod_none)
1775 if (op->value.mem.scaled != tic6x_offset_none)
1777 return tic6x_match_matches;
1779 if (op->value.mem.scaled == tic6x_offset_none)
1781 if (op->value.mem.mod == tic6x_mem_mod_plus
1782 || op->value.mem.mod == tic6x_mem_mod_minus)
1784 return tic6x_match_matches;
1786 if (op->value.mem.offset_is_reg)
1788 if (op->value.mem.scaled == tic6x_offset_unscaled
1789 && form != tic6x_operand_mem_ndw)
1791 if (op->value.mem.offset.reg.side == side)
1792 return tic6x_match_matches;
1794 return tic6x_match_bad_mem;
1798 if (op->value.mem.offset.exp.X_op == O_constant)
1799 return tic6x_match_matches;
1801 return tic6x_match_bad_mem;
1804 case tic6x_operand_mem_long:
1805 if (op->value.mem.base_reg.side == 2
1806 && (op->value.mem.base_reg.num == 14
1807 || op->value.mem.base_reg.num == 15))
1809 switch (op->value.mem.mod)
1811 case tic6x_mem_mod_none:
1812 if (op->value.mem.scaled != tic6x_offset_none)
1814 return tic6x_match_matches;
1816 case tic6x_mem_mod_plus:
1817 if (op->value.mem.scaled == tic6x_offset_none)
1819 if (op->value.mem.offset_is_reg)
1820 return tic6x_match_bad_mem;
1821 else if (op->value.mem.scaled == tic6x_offset_scaled
1822 && op->value.mem.offset.exp.X_op != O_constant)
1823 return tic6x_match_bad_mem;
1825 return tic6x_match_matches;
1827 case tic6x_mem_mod_minus:
1828 case tic6x_mem_mod_preinc:
1829 case tic6x_mem_mod_predec:
1830 case tic6x_mem_mod_postinc:
1831 case tic6x_mem_mod_postdec:
1832 return tic6x_match_bad_mem;
1840 return tic6x_match_bad_mem;
1847 /* Return the number of bits shift used with DP-relative coding method
1851 tic6x_dpr_shift (tic6x_coding_method coding)
1855 case tic6x_coding_ulcst_dpr_byte:
1858 case tic6x_coding_ulcst_dpr_half:
1861 case tic6x_coding_ulcst_dpr_word:
1869 /* Return the relocation used with DP-relative coding method
1872 static bfd_reloc_code_real_type
1873 tic6x_dpr_reloc (tic6x_coding_method coding)
1877 case tic6x_coding_ulcst_dpr_byte:
1878 return BFD_RELOC_C6000_SBR_U15_B;
1880 case tic6x_coding_ulcst_dpr_half:
1881 return BFD_RELOC_C6000_SBR_U15_H;
1883 case tic6x_coding_ulcst_dpr_word:
1884 return BFD_RELOC_C6000_SBR_U15_W;
1891 /* Given a memory reference *MEM_REF as originally parsed, fill in
1892 defaults for missing offsets. */
1895 tic6x_default_mem_ref (tic6x_mem_ref *mem_ref)
1897 switch (mem_ref->mod)
1899 case tic6x_mem_mod_none:
1900 if (mem_ref->scaled != tic6x_offset_none)
1902 mem_ref->mod = tic6x_mem_mod_plus;
1903 mem_ref->scaled = tic6x_offset_unscaled;
1904 mem_ref->offset_is_reg = FALSE;
1905 memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
1906 mem_ref->offset.exp.X_op = O_constant;
1907 mem_ref->offset.exp.X_add_number = 0;
1908 mem_ref->offset.exp.X_unsigned = 0;
1911 case tic6x_mem_mod_plus:
1912 case tic6x_mem_mod_minus:
1913 if (mem_ref->scaled == tic6x_offset_none)
1917 case tic6x_mem_mod_preinc:
1918 case tic6x_mem_mod_predec:
1919 case tic6x_mem_mod_postinc:
1920 case tic6x_mem_mod_postdec:
1921 if (mem_ref->scaled != tic6x_offset_none)
1923 mem_ref->scaled = tic6x_offset_scaled;
1924 mem_ref->offset_is_reg = FALSE;
1925 memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
1926 mem_ref->offset.exp.X_op = O_constant;
1927 mem_ref->offset.exp.X_add_number = 1;
1928 mem_ref->offset.exp.X_unsigned = 0;
1936 /* Return the encoding in the 8-bit field of an SPMASK or SPMASKR
1937 instruction of the specified UNIT, side SIDE. */
1940 tic6x_encode_spmask (tic6x_func_unit_base unit, unsigned int side)
1944 case tic6x_func_unit_l:
1945 return 1 << (side - 1);
1947 case tic6x_func_unit_s:
1948 return 1 << (side + 1);
1950 case tic6x_func_unit_d:
1951 return 1 << (side + 3);
1953 case tic6x_func_unit_m:
1954 return 1 << (side + 5);
1961 /* Try to encode the instruction with opcode number ID and operands
1962 OPERANDS (number NUM_OPERANDS), creg value THIS_LINE_CREG and z
1963 value THIS_LINE_Z; FUNC_UNIT_SIDE, FUNC_UNIT_CROSS and
1964 FUNC_UNIT_DATA_SIDE describe the functional unit specification;
1965 SPLOOP_II is the ii value from the previous SPLOOP-family
1966 instruction, or 0 if not in such a loop; the only possible problems
1967 are operands being out of range (they already match the
1968 fine-grained form), and inappropriate predication. If this
1969 succeeds, return the encoding and set *OK to TRUE; otherwise return
1970 0 and set *OK to FALSE. If a fix is needed, set *FIX_NEEDED to
1971 true and fill in *FIX_EXP, *FIX_PCREL, *FX_R_TYPE and *FIX_ADDA.
1972 Print error messages for failure if PRINT_ERRORS is TRUE; the
1973 opcode starts at STR and has length OPC_LEN. */
1976 tic6x_try_encode (tic6x_opcode_id id, tic6x_operand *operands,
1977 unsigned int num_operands, unsigned int this_line_creg,
1978 unsigned int this_line_z, unsigned int func_unit_side,
1979 unsigned int func_unit_cross,
1980 unsigned int func_unit_data_side, int sploop_ii,
1981 expressionS **fix_exp, int *fix_pcrel,
1982 bfd_reloc_code_real_type *fx_r_type, bfd_boolean *fix_adda,
1983 bfd_boolean *fix_needed, bfd_boolean *ok,
1984 bfd_boolean print_errors, char *str, int opc_len)
1986 const tic6x_opcode *opct;
1987 const tic6x_insn_format *fmt;
1988 unsigned int opcode_value;
1991 opct = &tic6x_opcode_table[id];
1992 fmt = &tic6x_insn_format_table[opct->format];
1993 opcode_value = fmt->cst_bits;
1995 for (fld = 0; fld < opct->num_fixed_fields; fld++)
1997 if (opct->fixed_fields[fld].min_val == opct->fixed_fields[fld].max_val)
1999 const tic6x_insn_field *fldd;
2000 fldd = tic6x_field_from_fmt (fmt, opct->fixed_fields[fld].field_id);
2003 opcode_value |= opct->fixed_fields[fld].min_val << fldd->low_pos;
2007 for (fld = 0; fld < opct->num_variable_fields; fld++)
2009 const tic6x_insn_field *fldd;
2015 unsigned int fcyc_bits;
2020 fldd = tic6x_field_from_fmt (fmt, opct->variable_fields[fld].field_id);
2023 opno = opct->variable_fields[fld].operand_num;
2024 switch (opct->variable_fields[fld].coding_method)
2026 case tic6x_coding_ucst:
2027 if (operands[opno].form != TIC6X_OP_EXP)
2029 if (operands[opno].value.exp.X_op != O_constant)
2031 ucexp = operands[opno].value.exp;
2033 if (ucexp.X_add_number < 0
2034 || ucexp.X_add_number >= (1 << fldd->width))
2037 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2042 value = ucexp.X_add_number;
2045 case tic6x_coding_scst:
2046 if (operands[opno].form != TIC6X_OP_EXP)
2048 if (operands[opno].value.exp.X_op != O_constant)
2051 /* Opcode table should not permit non-constants without
2052 a known relocation for them. */
2053 if (fldd->low_pos != 7 || fldd->width != 16)
2056 *fix_exp = &operands[opno].value.exp;
2058 *fx_r_type = BFD_RELOC_C6000_ABS_S16;
2062 sign_value = SEXT (operands[opno].value.exp.X_add_number);
2064 if (sign_value < -(1 << (fldd->width - 1))
2065 || (sign_value >= (1 << (fldd->width - 1))))
2068 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2073 value = sign_value + (1 << (fldd->width - 1));
2074 value ^= (1 << (fldd->width - 1));
2077 case tic6x_coding_ucst_minus_one:
2078 if (operands[opno].form != TIC6X_OP_EXP)
2080 if (operands[opno].value.exp.X_op != O_constant)
2082 if (operands[opno].value.exp.X_add_number <= 0
2083 || operands[opno].value.exp.X_add_number > (1 << fldd->width))
2086 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2091 value = operands[opno].value.exp.X_add_number - 1;
2094 case tic6x_coding_scst_negate:
2095 if (operands[opno].form != TIC6X_OP_EXP)
2097 if (operands[opno].value.exp.X_op != O_constant)
2099 sign_value = SEXT (-operands[opno].value.exp.X_add_number);
2100 goto signed_constant;
2102 case tic6x_coding_ulcst_dpr_byte:
2103 case tic6x_coding_ulcst_dpr_half:
2104 case tic6x_coding_ulcst_dpr_word:
2105 bits = tic6x_dpr_shift (opct->variable_fields[fld].coding_method);
2106 switch (operands[opno].form)
2109 if (operands[opno].value.exp.X_op == O_constant)
2111 ucexp = operands[opno].value.exp;
2112 goto unsigned_constant;
2114 expp = &operands[opno].value.exp;
2117 case TIC6X_OP_MEM_NOUNREG:
2118 mem = operands[opno].value.mem;
2119 tic6x_default_mem_ref (&mem);
2120 if (mem.offset_is_reg)
2122 if (mem.offset.exp.X_op == O_constant)
2124 ucexp = mem.offset.exp;
2125 if (mem.scaled == tic6x_offset_unscaled)
2127 if (ucexp.X_add_number & ((1 << bits) - 1))
2130 as_bad (_("offset in operand %u of '%.*s' not "
2131 "divisible by %u"), opno + 1, opc_len,
2136 ucexp.X_add_number >>= bits;
2138 goto unsigned_constant;
2140 if (mem.scaled != tic6x_offset_unscaled)
2142 if (operands[opno].value.mem.mod == tic6x_mem_mod_none
2143 || operands[opno].value.mem.scaled != tic6x_offset_unscaled
2144 || operands[opno].value.mem.offset_is_reg)
2146 expp = &operands[opno].value.mem.offset.exp;
2153 /* Opcode table should not use this encoding without a known
2155 if (fldd->low_pos != 8 || fldd->width != 15)
2157 /* We do not check for offset divisibility here; such a
2158 check is not needed at this point to encode the value,
2159 and if there is eventually a problem it will be detected
2160 either in md_apply_fix or at link time. */
2165 = tic6x_dpr_reloc (opct->variable_fields[fld].coding_method);
2166 if (operands[opno].form == TIC6X_OP_EXP)
2172 case tic6x_coding_lcst_low16:
2173 if (operands[opno].form != TIC6X_OP_EXP)
2175 if (operands[opno].value.exp.X_op == O_constant)
2176 value = operands[opno].value.exp.X_add_number & 0xffff;
2180 /* Opcode table should not use this encoding without a
2181 known relocation. */
2182 if (fldd->low_pos != 7 || fldd->width != 16)
2185 *fix_exp = &operands[opno].value.exp;
2187 *fx_r_type = BFD_RELOC_C6000_ABS_L16;
2192 case tic6x_coding_lcst_high16:
2193 if (operands[opno].form != TIC6X_OP_EXP)
2195 if (operands[opno].value.exp.X_op == O_constant)
2196 value = (operands[opno].value.exp.X_add_number >> 16) & 0xffff;
2200 /* Opcode table should not use this encoding without a
2201 known relocation. */
2202 if (fldd->low_pos != 7 || fldd->width != 16)
2205 *fix_exp = &operands[opno].value.exp;
2207 *fx_r_type = BFD_RELOC_C6000_ABS_H16;
2212 case tic6x_coding_pcrel:
2213 case tic6x_coding_pcrel_half:
2214 if (operands[opno].form != TIC6X_OP_EXP)
2218 *fix_exp = &operands[opno].value.exp;
2220 if (fldd->low_pos == 7 && fldd->width == 21)
2221 *fx_r_type = BFD_RELOC_C6000_PCR_S21;
2222 else if (fldd->low_pos == 16 && fldd->width == 12)
2223 *fx_r_type = BFD_RELOC_C6000_PCR_S12;
2224 else if (fldd->low_pos == 13 && fldd->width == 10)
2225 *fx_r_type = BFD_RELOC_C6000_PCR_S10;
2226 else if (fldd->low_pos == 16 && fldd->width == 7)
2227 *fx_r_type = BFD_RELOC_C6000_PCR_S7;
2229 /* Opcode table should not use this encoding without a
2230 known relocation. */
2235 case tic6x_coding_reg:
2236 switch (operands[opno].form)
2239 case TIC6X_OP_REGPAIR:
2240 value = operands[opno].value.reg.num;
2243 case TIC6X_OP_MEM_NOUNREG:
2244 case TIC6X_OP_MEM_UNREG:
2245 value = operands[opno].value.mem.base_reg.num;
2253 case tic6x_coding_areg:
2254 switch (operands[opno].form)
2257 value = (operands[opno].value.reg.num == 15 ? 1 : 0);
2260 case TIC6X_OP_MEM_NOUNREG:
2261 value = (operands[opno].value.mem.base_reg.num == 15 ? 1 : 0);
2269 case tic6x_coding_crlo:
2270 if (operands[opno].form != TIC6X_OP_CTRL)
2272 value = tic6x_ctrl_table[operands[opno].value.ctrl].crlo;
2275 case tic6x_coding_crhi:
2276 if (operands[opno].form != TIC6X_OP_CTRL)
2281 case tic6x_coding_reg_shift:
2282 if (operands[opno].form != TIC6X_OP_REGPAIR)
2284 value = operands[opno].value.reg.num >> 1;
2287 case tic6x_coding_mem_offset:
2288 if (operands[opno].form != TIC6X_OP_MEM_NOUNREG)
2290 mem = operands[opno].value.mem;
2291 tic6x_default_mem_ref (&mem);
2292 if (mem.offset_is_reg)
2294 if (mem.scaled != tic6x_offset_scaled)
2296 value = mem.offset.reg.num;
2302 if (mem.offset.exp.X_op != O_constant)
2306 case tic6x_offset_scaled:
2310 case tic6x_offset_unscaled:
2311 scale = opct->operand_info[opno].size;
2312 if (scale != 1 && scale != 2 && scale != 4 && scale != 8)
2319 if (mem.offset.exp.X_add_number < 0
2320 || mem.offset.exp.X_add_number >= (1 << fldd->width) * scale)
2323 as_bad (_("offset in operand %u of '%.*s' out of range"),
2324 opno + 1, opc_len, str);
2328 if (mem.offset.exp.X_add_number % scale)
2331 as_bad (_("offset in operand %u of '%.*s' not "
2333 opno + 1, opc_len, str, scale);
2337 value = mem.offset.exp.X_add_number / scale;
2341 case tic6x_coding_mem_offset_noscale:
2342 if (operands[opno].form != TIC6X_OP_MEM_UNREG)
2344 mem = operands[opno].value.mem;
2345 tic6x_default_mem_ref (&mem);
2346 if (mem.offset_is_reg)
2347 value = mem.offset.reg.num;
2350 if (mem.offset.exp.X_op != O_constant)
2352 if (mem.offset.exp.X_add_number < 0
2353 || mem.offset.exp.X_add_number >= (1 << fldd->width))
2356 as_bad (_("offset in operand %u of '%.*s' out of range"),
2357 opno + 1, opc_len, str);
2361 value = mem.offset.exp.X_add_number;
2365 case tic6x_coding_mem_mode:
2366 if (operands[opno].form != TIC6X_OP_MEM_NOUNREG
2367 && operands[opno].form != TIC6X_OP_MEM_UNREG)
2369 mem = operands[opno].value.mem;
2370 tic6x_default_mem_ref (&mem);
2373 case tic6x_mem_mod_plus:
2377 case tic6x_mem_mod_minus:
2381 case tic6x_mem_mod_preinc:
2385 case tic6x_mem_mod_predec:
2389 case tic6x_mem_mod_postinc:
2393 case tic6x_mem_mod_postdec:
2400 value += (mem.offset_is_reg ? 4 : 0);
2403 case tic6x_coding_scaled:
2404 if (operands[opno].form != TIC6X_OP_MEM_UNREG)
2406 mem = operands[opno].value.mem;
2407 tic6x_default_mem_ref (&mem);
2410 case tic6x_offset_unscaled:
2414 case tic6x_offset_scaled:
2423 case tic6x_coding_spmask:
2424 /* The position of such a field is hardcoded in the handling
2426 if (fldd->low_pos != 18)
2429 for (opno = 0; opno < num_operands; opno++)
2433 v = tic6x_encode_spmask (operands[opno].value.func_unit.base,
2434 operands[opno].value.func_unit.side);
2438 as_bad (_("functional unit already masked for operand "
2439 "%u of '%.*s'"), opno + 1, opc_len, str);
2447 case tic6x_coding_reg_unused:
2448 /* This is a placeholder; correct handling goes along with
2449 resource constraint checks. */
2453 case tic6x_coding_fstg:
2454 case tic6x_coding_fcyc:
2455 if (operands[opno].form != TIC6X_OP_EXP)
2457 if (operands[opno].value.exp.X_op != O_constant)
2462 as_bad (_("'%.*s' instruction not in a software "
2471 else if (sploop_ii <= 2)
2473 else if (sploop_ii <= 4)
2475 else if (sploop_ii <= 8)
2477 else if (sploop_ii <= 14)
2481 if (fcyc_bits > fldd->width)
2484 if (opct->variable_fields[fld].coding_method == tic6x_coding_fstg)
2486 if (operands[opno].value.exp.X_add_number < 0
2487 || (operands[opno].value.exp.X_add_number
2488 >= (1 << (fldd->width - fcyc_bits))))
2491 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2496 value = operands[opno].value.exp.X_add_number << fcyc_bits;
2500 if (operands[opno].value.exp.X_add_number < 0
2501 || (operands[opno].value.exp.X_add_number >= sploop_ii))
2504 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2509 value = operands[opno].value.exp.X_add_number;
2513 case tic6x_coding_fu:
2514 value = func_unit_side == 2 ? 1 : 0;
2517 case tic6x_coding_data_fu:
2518 value = func_unit_data_side == 2 ? 1 : 0;
2521 case tic6x_coding_xpath:
2522 value = func_unit_cross;
2529 for (ffld = 0; ffld < opct->num_fixed_fields; ffld++)
2530 if ((opct->fixed_fields[ffld].field_id
2531 == opct->variable_fields[fld].field_id)
2532 && (value < opct->fixed_fields[ffld].min_val
2533 || value > opct->fixed_fields[ffld].max_val))
2536 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2542 opcode_value |= value << fldd->low_pos;
2547 const tic6x_insn_field *creg;
2548 const tic6x_insn_field *z;
2550 creg = tic6x_field_from_fmt (fmt, tic6x_field_creg);
2554 as_bad (_("instruction '%.*s' cannot be predicated"),
2559 z = tic6x_field_from_fmt (fmt, tic6x_field_z);
2560 /* If there is a creg field, there must be a z field; otherwise
2561 there is an error in the format table. */
2565 opcode_value |= this_line_creg << creg->low_pos;
2566 opcode_value |= this_line_z << z->low_pos;
2570 return opcode_value;
2573 /* Convert the target integer stored in N bytes in BUF to a host
2574 integer, returning that value. */
2577 md_chars_to_number (char *buf, int n)
2580 unsigned char *p = (unsigned char *) buf;
2582 if (target_big_endian)
2587 result |= (*p++ & 0xff);
2595 result |= (p[n] & 0xff);
2602 /* Assemble the instruction starting at STR (an opcode, with the
2603 opcode name all-lowercase). */
2606 md_assemble (char *str)
2610 bfd_boolean this_line_parallel;
2611 bfd_boolean this_line_spmask;
2612 unsigned int this_line_creg;
2613 unsigned int this_line_z;
2614 tic6x_label_list *this_insn_label_list;
2615 segment_info_type *seginfo;
2616 tic6x_opcode_list *opc_list, *opc;
2617 tic6x_func_unit_base func_unit_base = tic6x_func_unit_nfu;
2618 unsigned int func_unit_side = 0;
2619 unsigned int func_unit_cross = 0;
2620 unsigned int cross_side = 0;
2621 unsigned int func_unit_data_side = 0;
2622 unsigned int max_matching_opcodes, num_matching_opcodes;
2623 tic6x_opcode_id *opcm = NULL;
2624 unsigned int opc_rank[TIC6X_NUM_PREFER];
2625 const tic6x_opcode *opct = NULL;
2626 int min_rank, try_rank, max_rank;
2627 bfd_boolean num_operands_permitted[TIC6X_MAX_SOURCE_OPERANDS + 1]
2629 unsigned int operand_forms[TIC6X_MAX_SOURCE_OPERANDS] = { 0 };
2630 tic6x_operand operands[TIC6X_MAX_SOURCE_OPERANDS];
2631 unsigned int max_num_operands;
2632 unsigned int num_operands_read;
2633 bfd_boolean ok_this_arch, ok_this_fu, ok_this_arch_fu;
2634 bfd_boolean bad_operands = FALSE;
2635 unsigned int opcode_value;
2636 bfd_boolean encoded_ok;
2637 bfd_boolean fix_needed = FALSE;
2638 expressionS *fix_exp = NULL;
2640 bfd_reloc_code_real_type fx_r_type = BFD_RELOC_UNUSED;
2641 bfd_boolean fix_adda = FALSE;
2646 while (*p && !is_end_of_line[(unsigned char) *p] && *p != ' ')
2649 /* This function should only have been called when there is actually
2650 an instruction to assemble. */
2654 /* Now an instruction has been seen, architecture attributes from
2655 .arch directives merge with rather than overriding the previous
2657 tic6x_seen_insns = TRUE;
2658 /* If no .arch directives or -march options have been seen, we are
2659 assessing instruction validity based on the C674X default, so set
2660 the attribute accordingly. */
2661 if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
2662 tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
2664 /* Reset global settings for parallel bars and predicates now to
2665 avoid extra errors if there are problems with this opcode. */
2666 this_line_parallel = tic6x_line_parallel;
2667 this_line_spmask = tic6x_line_spmask;
2668 this_line_creg = tic6x_line_creg;
2669 this_line_z = tic6x_line_z;
2670 tic6x_line_parallel = FALSE;
2671 tic6x_line_spmask = FALSE;
2672 tic6x_line_creg = 0;
2674 seginfo = seg_info (now_seg);
2675 this_insn_label_list = seginfo->tc_segment_info_data.label_list;
2676 seginfo->tc_segment_info_data.label_list = NULL;
2678 opc_list = hash_find_n (opcode_hash, str, p - str);
2679 if (opc_list == NULL)
2683 as_bad (_("unknown opcode '%s'"), str);
2689 skip_whitespace (p);
2691 /* See if there is something that looks like a functional unit
2695 bfd_boolean good_func_unit;
2696 tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
2697 unsigned int maybe_side = 0;
2698 unsigned int maybe_cross = 0;
2699 unsigned int maybe_data_side = 0;
2701 good_func_unit = tic6x_parse_func_unit_base (p + 1, &maybe_base,
2706 if (p[3] == ' ' || is_end_of_line[(unsigned char) p[3]])
2708 else if ((p[3] == 'x' || p[3] == 'X')
2709 && (p[4] == ' ' || is_end_of_line[(unsigned char) p[4]]))
2714 else if (maybe_base == tic6x_func_unit_d
2715 && (p[3] == 't' || p[3] == 'T')
2716 && (p[4] == '1' || p[4] == '2')
2717 && (p[5] == ' ' || is_end_of_line[(unsigned char) p[5]]))
2719 maybe_data_side = p[4] - '0';
2723 good_func_unit = FALSE;
2728 func_unit_base = maybe_base;
2729 func_unit_side = maybe_side;
2730 func_unit_cross = maybe_cross;
2731 cross_side = (func_unit_cross ? 3 - func_unit_side : func_unit_side);
2732 func_unit_data_side = maybe_data_side;
2735 skip_whitespace (p);
2738 /* Determine which entries in the opcode table match, and the
2739 associated permitted forms of operands. */
2740 max_matching_opcodes = 0;
2741 for (opc = opc_list; opc; opc = opc->next)
2742 max_matching_opcodes++;
2743 num_matching_opcodes = 0;
2744 opcm = xmalloc (max_matching_opcodes * sizeof (*opcm));
2745 max_num_operands = 0;
2746 ok_this_arch = FALSE;
2748 ok_this_arch_fu = FALSE;
2749 for (opc = opc_list; opc; opc = opc->next)
2751 unsigned int num_operands;
2753 bfd_boolean this_opc_arch_ok = TRUE;
2754 bfd_boolean this_opc_fu_ok = TRUE;
2756 if (tic6x_insn_format_table[tic6x_opcode_table[opc->id].format].num_bits
2759 if (!(tic6x_opcode_table[opc->id].isa_variants & tic6x_features))
2760 this_opc_arch_ok = FALSE;
2761 if (tic6x_opcode_table[opc->id].func_unit != func_unit_base)
2762 this_opc_fu_ok = FALSE;
2763 if (func_unit_side == 1
2764 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_B_ONLY))
2765 this_opc_fu_ok = FALSE;
2767 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_NO_CROSS))
2768 this_opc_fu_ok = FALSE;
2769 if (!func_unit_data_side
2770 && (tic6x_opcode_table[opc->id].flags
2771 & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
2772 this_opc_fu_ok = FALSE;
2773 if (func_unit_data_side
2774 && !(tic6x_opcode_table[opc->id].flags
2775 & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
2776 this_opc_fu_ok = FALSE;
2777 if (func_unit_data_side == 1
2778 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_T2_ONLY))
2779 this_opc_fu_ok = FALSE;
2780 if (this_opc_arch_ok)
2781 ok_this_arch = TRUE;
2784 if (!this_opc_arch_ok || !this_opc_fu_ok)
2786 ok_this_arch_fu = TRUE;
2787 opcm[num_matching_opcodes] = opc->id;
2788 num_matching_opcodes++;
2789 num_operands = tic6x_opcode_table[opc->id].num_operands;
2791 if (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SPMASK)
2793 if (num_operands != 1
2794 || (tic6x_opcode_table[opc->id].operand_info[0].form
2795 != tic6x_operand_func_unit))
2798 for (i = 0; i < num_operands; i++)
2801 |= tic6x_coarse_operand_form (tic6x_operand_func_unit);
2802 num_operands_permitted[i] = TRUE;
2807 for (i = 0; i < num_operands; i++)
2809 tic6x_operand_form f
2810 = tic6x_opcode_table[opc->id].operand_info[i].form;
2812 operand_forms[i] |= tic6x_coarse_operand_form (f);
2815 num_operands_permitted[num_operands] = TRUE;
2816 if (num_operands > max_num_operands)
2817 max_num_operands = num_operands;
2822 as_bad (_("'%.*s' instruction not supported on this architecture"),
2830 as_bad (_("'%.*s' instruction not supported on this functional unit"),
2836 if (!ok_this_arch_fu)
2838 as_bad (_("'%.*s' instruction not supported on this functional unit"
2839 " for this architecture"),
2845 /* If there were no instructions matching the above availability
2846 checks, we should now have given an error and returned. */
2847 if (num_matching_opcodes == 0)
2850 num_operands_read = 0;
2853 skip_whitespace (p);
2854 if (is_end_of_line[(unsigned char) *p])
2856 if (num_operands_read > 0)
2858 as_bad (_("missing operand after comma"));
2859 bad_operands = TRUE;
2864 if (max_num_operands == 0)
2866 as_bad (_("too many operands to '%.*s'"), opc_len, str);
2867 bad_operands = TRUE;
2871 if (!tic6x_parse_operand (&p, &operands[num_operands_read],
2872 operand_forms[num_operands_read], str, opc_len,
2873 num_operands_read + 1))
2874 bad_operands = TRUE;
2875 num_operands_read++;
2877 if (is_end_of_line[(unsigned char) *p])
2882 if (num_operands_read == max_num_operands)
2884 as_bad (_("too many operands to '%.*s'"), opc_len, str);
2885 bad_operands = TRUE;
2891 /* Operand parsing should consume whole operands. */
2895 if (!bad_operands && !num_operands_permitted[num_operands_read])
2897 as_bad (_("bad number of operands to '%.*s'"), opc_len, str);
2898 bad_operands = TRUE;
2903 /* Each operand is of the right syntactic form for some opcode
2904 choice, and the number of operands is valid. Check that each
2905 operand is OK in detail for some opcode choice with the right
2906 number of operands. */
2909 for (i = 0; i < num_operands_read; i++)
2911 bfd_boolean coarse_ok = FALSE;
2912 bfd_boolean fine_ok = FALSE;
2913 tic6x_operand_match fine_failure = tic6x_match_matches;
2916 for (j = 0; j < num_matching_opcodes; j++)
2918 tic6x_operand_form f;
2921 tic6x_operand_match this_fine_failure;
2923 if (tic6x_opcode_table[opcm[j]].flags & TIC6X_FLAG_SPMASK)
2925 f = tic6x_operand_func_unit;
2930 if (tic6x_opcode_table[opcm[j]].num_operands
2931 != num_operands_read)
2934 f = tic6x_opcode_table[opcm[j]].operand_info[i].form;
2935 rw = tic6x_opcode_table[opcm[j]].operand_info[i].rw;
2937 cf = tic6x_coarse_operand_form (f);
2939 if (operands[i].form != cf)
2944 = tic6x_operand_matches_form (&operands[i], f, rw,
2947 func_unit_data_side);
2948 if (this_fine_failure == tic6x_match_matches)
2953 if (fine_failure == tic6x_match_matches
2954 || fine_failure > this_fine_failure)
2955 fine_failure = this_fine_failure;
2958 /* No instructions should have operand syntactic forms only
2959 acceptable with certain numbers of operands, so no
2960 diagnostic for this case. */
2966 switch (fine_failure)
2968 case tic6x_match_non_const:
2969 as_bad (_("operand %u of '%.*s' not constant"),
2970 i + 1, opc_len, str);
2973 case tic6x_match_wrong_side:
2974 as_bad (_("operand %u of '%.*s' on wrong side"),
2975 i + 1, opc_len, str);
2978 case tic6x_match_bad_return:
2979 as_bad (_("operand %u of '%.*s' not a valid return "
2980 "address register"),
2981 i + 1, opc_len, str);
2984 case tic6x_match_ctrl_write_only:
2985 as_bad (_("operand %u of '%.*s' is write-only"),
2986 i + 1, opc_len, str);
2989 case tic6x_match_ctrl_read_only:
2990 as_bad (_("operand %u of '%.*s' is read-only"),
2991 i + 1, opc_len, str);
2994 case tic6x_match_bad_mem:
2995 as_bad (_("operand %u of '%.*s' not a valid memory "
2997 i + 1, opc_len, str);
3000 case tic6x_match_bad_address:
3001 as_bad (_("operand %u of '%.*s' not a valid base "
3002 "address register"),
3003 i + 1, opc_len, str);
3009 bad_operands = TRUE;
3017 /* Each operand is OK for some opcode choice, and the number of
3018 operands is valid. Check whether there is an opcode choice
3019 for which all operands are simultaneously valid. */
3021 bfd_boolean found_match = FALSE;
3023 for (i = 0; i < TIC6X_NUM_PREFER; i++)
3024 opc_rank[i] = (unsigned int) -1;
3026 min_rank = TIC6X_NUM_PREFER - 1;
3029 for (i = 0; i < num_matching_opcodes; i++)
3032 bfd_boolean this_matches = TRUE;
3034 if (!(tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
3035 && tic6x_opcode_table[opcm[i]].num_operands != num_operands_read)
3038 for (j = 0; j < num_operands_read; j++)
3040 tic6x_operand_form f;
3043 if (tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
3045 f = tic6x_operand_func_unit;
3050 f = tic6x_opcode_table[opcm[i]].operand_info[j].form;
3051 rw = tic6x_opcode_table[opcm[i]].operand_info[j].rw;
3053 if (tic6x_operand_matches_form (&operands[j], f, rw,
3056 func_unit_data_side)
3057 != tic6x_match_matches)
3059 this_matches = FALSE;
3066 int rank = TIC6X_PREFER_VAL (tic6x_opcode_table[opcm[i]].flags);
3068 if (rank < min_rank)
3070 if (rank > max_rank)
3073 if (opc_rank[rank] == (unsigned int) -1)
3076 /* The opcode table should provide a total ordering
3077 for all cases where multiple matches may get
3087 as_bad (_("bad operand combination for '%.*s'"), opc_len, str);
3088 bad_operands = TRUE;
3100 for (try_rank = max_rank; try_rank >= min_rank; try_rank--)
3104 if (opc_rank[try_rank] == (unsigned int) -1)
3107 opcode_value = tic6x_try_encode (opcm[opc_rank[try_rank]], operands,
3108 num_operands_read, this_line_creg,
3109 this_line_z, func_unit_side,
3110 func_unit_cross, func_unit_data_side,
3111 seginfo->tc_segment_info_data.sploop_ii,
3112 &fix_exp, &fix_pcrel, &fx_r_type,
3113 &fix_adda, &fix_needed, &encoded_ok,
3114 (try_rank == min_rank ? TRUE : FALSE),
3118 opct = &tic6x_opcode_table[opcm[opc_rank[try_rank]]];
3128 if (this_line_parallel)
3130 insn_frag = seginfo->tc_segment_info_data.execute_packet_frag;
3131 if (insn_frag == NULL)
3133 as_bad (_("parallel instruction not following another instruction"));
3137 if (insn_frag->fr_fix >= 32)
3139 as_bad (_("too many instructions in execute packet"));
3143 if (this_insn_label_list != NULL)
3144 as_bad (_("label not at start of execute packet"));
3146 if (opct->flags & TIC6X_FLAG_FIRST)
3147 as_bad (_("'%.*s' instruction not at start of execute packet"),
3150 *seginfo->tc_segment_info_data.last_insn_lsb |= 0x1;
3151 output = insn_frag->fr_literal + insn_frag->fr_fix;
3155 tic6x_label_list *l;
3157 seginfo->tc_segment_info_data.spmask_addr = NULL;
3159 /* Start a new frag for this execute packet. */
3160 if (frag_now_fix () != 0)
3162 if (frag_now->fr_type != rs_machine_dependent)
3163 frag_wane (frag_now);
3168 insn_frag = seginfo->tc_segment_info_data.execute_packet_frag = frag_now;
3169 for (l = this_insn_label_list; l; l = l->next)
3171 symbol_set_frag (l->label, frag_now);
3172 S_SET_VALUE (l->label, 0);
3173 S_SET_SEGMENT (l->label, now_seg);
3175 tic6x_free_label_list (this_insn_label_list);
3176 dwarf2_emit_insn (0);
3177 output = frag_var (rs_machine_dependent, 32, 32, 0, NULL, 0, NULL);
3178 /* This must be the same as the frag to which a pointer was just
3180 if (output != insn_frag->fr_literal)
3182 insn_frag->tc_frag_data.is_insns = TRUE;
3183 insn_frag->tc_frag_data.can_cross_fp_boundary
3184 = tic6x_can_cross_fp_boundary;
3187 if (opct->flags & TIC6X_FLAG_SPLOOP)
3189 if (seginfo->tc_segment_info_data.sploop_ii)
3190 as_bad (_("nested software pipelined loop"));
3191 if (num_operands_read != 1
3192 || operands[0].form != TIC6X_OP_EXP
3193 || operands[0].value.exp.X_op != O_constant)
3195 seginfo->tc_segment_info_data.sploop_ii
3196 = operands[0].value.exp.X_add_number;
3198 else if (opct->flags & TIC6X_FLAG_SPKERNEL)
3200 if (!seginfo->tc_segment_info_data.sploop_ii)
3201 as_bad (_("'%.*s' instruction not in a software pipelined loop"),
3203 seginfo->tc_segment_info_data.sploop_ii = 0;
3206 if (this_line_spmask)
3208 if (seginfo->tc_segment_info_data.spmask_addr == NULL)
3209 as_bad (_("'||^' without previous SPMASK"));
3210 else if (func_unit_base == tic6x_func_unit_nfu)
3211 as_bad (_("cannot mask instruction using no functional unit"));
3214 unsigned int spmask_opcode;
3215 unsigned int mask_bit;
3218 = md_chars_to_number (seginfo->tc_segment_info_data.spmask_addr,
3220 mask_bit = tic6x_encode_spmask (func_unit_base, func_unit_side);
3222 if (spmask_opcode & mask_bit)
3223 as_bad (_("functional unit already masked"));
3224 spmask_opcode |= mask_bit;
3225 md_number_to_chars (seginfo->tc_segment_info_data.spmask_addr,
3230 record_alignment (now_seg, 5);
3231 md_number_to_chars (output, opcode_value, 4);
3233 tic6x_fix_new_exp (insn_frag, output - insn_frag->fr_literal, 4, fix_exp,
3234 fix_pcrel, fx_r_type, fix_adda);
3235 insn_frag->fr_fix += 4;
3236 insn_frag->fr_var -= 4;
3237 seginfo->tc_segment_info_data.last_insn_lsb
3238 = (target_big_endian ? output + 3 : output);
3239 if (opct->flags & TIC6X_FLAG_SPMASK)
3240 seginfo->tc_segment_info_data.spmask_addr = output;
3243 /* Modify NEWVAL (32-bit) by inserting VALUE, shifted right by SHIFT
3244 and the least significant BITS bits taken, at position POS. */
3245 #define MODIFY_VALUE(NEWVAL, VALUE, SHIFT, POS, BITS) \
3247 (NEWVAL) &= 0xffffffffU & ~(((1U << (BITS)) - 1) << (POS)); \
3248 (NEWVAL) |= (((VALUE) >> (SHIFT)) & ((1U << (BITS)) - 1)) << (POS); \
3251 /* Apply a fixup to the object file. */
3254 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
3256 offsetT value = *valP;
3257 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3259 value = SEXT (value);
3262 fixP->fx_offset = SEXT (fixP->fx_offset);
3264 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3267 /* We do our own overflow checks. */
3268 fixP->fx_no_overflow = 1;
3270 switch (fixP->fx_r_type)
3272 case BFD_RELOC_NONE:
3273 /* Force output to the object file. */
3278 if (fixP->fx_done || !seg->use_rela_p)
3279 md_number_to_chars (buf, value, 4);
3283 if (fixP->fx_done || !seg->use_rela_p)
3285 if (value < -0x8000 || value > 0xffff)
3286 as_bad_where (fixP->fx_file, fixP->fx_line,
3287 _("value too large for 2-byte field"));
3288 md_number_to_chars (buf, value, 2);
3293 if (fixP->fx_done || !seg->use_rela_p)
3295 if (value < -0x80 || value > 0xff)
3296 as_bad_where (fixP->fx_file, fixP->fx_line,
3297 _("value too large for 1-byte field"));
3298 md_number_to_chars (buf, value, 1);
3302 case BFD_RELOC_C6000_ABS_S16:
3303 case BFD_RELOC_C6000_ABS_L16:
3304 case BFD_RELOC_C6000_SBR_S16:
3305 case BFD_RELOC_C6000_SBR_L16_B:
3306 case BFD_RELOC_C6000_SBR_L16_H:
3307 case BFD_RELOC_C6000_SBR_L16_W:
3308 case BFD_RELOC_C6000_SBR_GOT_L16_W:
3309 if (fixP->fx_done || !seg->use_rela_p)
3311 offsetT newval = md_chars_to_number (buf, 4);
3314 switch (fixP->fx_r_type)
3316 case BFD_RELOC_C6000_SBR_L16_H:
3320 case BFD_RELOC_C6000_SBR_L16_W:
3321 case BFD_RELOC_C6000_SBR_GOT_L16_W:
3330 MODIFY_VALUE (newval, value, shift, 7, 16);
3331 if ((value < -0x8000 || value > 0x7fff)
3332 && (fixP->fx_r_type == BFD_RELOC_C6000_ABS_S16
3333 || fixP->fx_r_type == BFD_RELOC_C6000_SBR_S16))
3334 as_bad_where (fixP->fx_file, fixP->fx_line,
3335 _("immediate offset out of range"));
3337 md_number_to_chars (buf, newval, 4);
3340 && fixP->fx_r_type != BFD_RELOC_C6000_ABS_S16
3341 && fixP->fx_r_type != BFD_RELOC_C6000_ABS_L16)
3345 case BFD_RELOC_C6000_ABS_H16:
3346 case BFD_RELOC_C6000_SBR_H16_B:
3347 case BFD_RELOC_C6000_SBR_H16_H:
3348 case BFD_RELOC_C6000_SBR_H16_W:
3349 case BFD_RELOC_C6000_SBR_GOT_H16_W:
3350 if (fixP->fx_done || !seg->use_rela_p)
3352 offsetT newval = md_chars_to_number (buf, 4);
3355 switch (fixP->fx_r_type)
3357 case BFD_RELOC_C6000_SBR_H16_H:
3361 case BFD_RELOC_C6000_SBR_H16_W:
3362 case BFD_RELOC_C6000_SBR_GOT_H16_W:
3371 MODIFY_VALUE (newval, value, shift, 7, 16);
3373 md_number_to_chars (buf, newval, 4);
3375 if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_ABS_H16)
3379 case BFD_RELOC_C6000_SBR_U15_B:
3380 if (fixP->fx_done || !seg->use_rela_p)
3382 offsetT newval = md_chars_to_number (buf, 4);
3384 MODIFY_VALUE (newval, value, 0, 8, 15);
3385 if (value < 0 || value > 0x7fff)
3386 as_bad_where (fixP->fx_file, fixP->fx_line,
3387 _("immediate offset out of range"));
3389 md_number_to_chars (buf, newval, 4);
3393 case BFD_RELOC_C6000_SBR_U15_H:
3394 if (fixP->fx_done || !seg->use_rela_p)
3396 offsetT newval = md_chars_to_number (buf, 4);
3398 /* Constant ADDA operands, processed as constant when the
3399 instruction is parsed, are encoded as-is rather than
3400 shifted. If the operand of an ADDA instruction is now
3401 constant (for example, the difference between two labels
3402 found after the instruction), ensure it is encoded the
3403 same way it would have been if the constant value had
3404 been known when the instruction was parsed. */
3405 if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
3408 MODIFY_VALUE (newval, value, 1, 8, 15);
3410 as_bad_where (fixP->fx_file, fixP->fx_line,
3411 _("immediate offset not 2-byte-aligned"));
3412 if (value < 0 || value > 0xfffe)
3413 as_bad_where (fixP->fx_file, fixP->fx_line,
3414 _("immediate offset out of range"));
3416 md_number_to_chars (buf, newval, 4);
3420 case BFD_RELOC_C6000_SBR_U15_W:
3421 case BFD_RELOC_C6000_SBR_GOT_U15_W:
3422 if (fixP->fx_done || !seg->use_rela_p)
3424 offsetT newval = md_chars_to_number (buf, 4);
3426 /* Constant ADDA operands, processed as constant when the
3427 instruction is parsed, are encoded as-is rather than
3428 shifted. If the operand of an ADDA instruction is now
3429 constant (for example, the difference between two labels
3430 found after the instruction), ensure it is encoded the
3431 same way it would have been if the constant value had
3432 been known when the instruction was parsed. */
3433 if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
3436 MODIFY_VALUE (newval, value, 2, 8, 15);
3438 as_bad_where (fixP->fx_file, fixP->fx_line,
3439 _("immediate offset not 4-byte-aligned"));
3440 if (value < 0 || value > 0x1fffc)
3441 as_bad_where (fixP->fx_file, fixP->fx_line,
3442 _("immediate offset out of range"));
3444 md_number_to_chars (buf, newval, 4);
3446 if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_SBR_U15_W)
3450 case BFD_RELOC_C6000_DSBT_INDEX:
3452 as_bad_where (fixP->fx_file, fixP->fx_line,
3453 _("addend used with $DSBT_INDEX"));
3458 case BFD_RELOC_C6000_PCR_S21:
3459 if (fixP->fx_done || !seg->use_rela_p)
3461 offsetT newval = md_chars_to_number (buf, 4);
3463 MODIFY_VALUE (newval, value, 2, 7, 21);
3466 as_bad_where (fixP->fx_file, fixP->fx_line,
3467 _("PC-relative offset not 4-byte-aligned"));
3468 if (value < -0x400000 || value > 0x3ffffc)
3469 as_bad_where (fixP->fx_file, fixP->fx_line,
3470 _("PC-relative offset out of range"));
3472 md_number_to_chars (buf, newval, 4);
3476 case BFD_RELOC_C6000_PCR_S12:
3477 if (fixP->fx_done || !seg->use_rela_p)
3479 offsetT newval = md_chars_to_number (buf, 4);
3481 MODIFY_VALUE (newval, value, 2, 16, 12);
3484 as_bad_where (fixP->fx_file, fixP->fx_line,
3485 _("PC-relative offset not 4-byte-aligned"));
3486 if (value < -0x2000 || value > 0x1ffc)
3487 as_bad_where (fixP->fx_file, fixP->fx_line,
3488 _("PC-relative offset out of range"));
3490 md_number_to_chars (buf, newval, 4);
3494 case BFD_RELOC_C6000_PCR_S10:
3495 if (fixP->fx_done || !seg->use_rela_p)
3497 offsetT newval = md_chars_to_number (buf, 4);
3499 MODIFY_VALUE (newval, value, 2, 13, 10);
3502 as_bad_where (fixP->fx_file, fixP->fx_line,
3503 _("PC-relative offset not 4-byte-aligned"));
3504 if (value < -0x800 || value > 0x7fc)
3505 as_bad_where (fixP->fx_file, fixP->fx_line,
3506 _("PC-relative offset out of range"));
3508 md_number_to_chars (buf, newval, 4);
3512 case BFD_RELOC_C6000_PCR_S7:
3513 if (fixP->fx_done || !seg->use_rela_p)
3515 offsetT newval = md_chars_to_number (buf, 4);
3517 MODIFY_VALUE (newval, value, 2, 16, 7);
3520 as_bad_where (fixP->fx_file, fixP->fx_line,
3521 _("PC-relative offset not 4-byte-aligned"));
3522 if (value < -0x100 || value > 0xfc)
3523 as_bad_where (fixP->fx_file, fixP->fx_line,
3524 _("PC-relative offset out of range"));
3526 md_number_to_chars (buf, newval, 4);
3535 /* Convert a floating-point number to target (IEEE) format. */
3538 md_atof (int type, char *litP, int *sizeP)
3540 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3543 /* Adjust the frags in SECTION (see tic6x_end). */
3546 tic6x_adjust_section (bfd *abfd ATTRIBUTE_UNUSED, segT section,
3547 void *dummy ATTRIBUTE_UNUSED)
3549 segment_info_type *info;
3552 bfd_boolean have_code = FALSE;
3553 bfd_boolean have_non_code = FALSE;
3555 info = seg_info (section);
3559 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3560 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3561 switch (fragp->fr_type)
3563 case rs_machine_dependent:
3564 if (fragp->tc_frag_data.is_insns)
3570 if (fragp->fr_fix > 0)
3571 have_non_code = TRUE;
3575 have_non_code = TRUE;
3579 /* Process alignment requirements in a code-only section. */
3580 if (have_code && !have_non_code)
3582 /* If we need to insert an odd number of instructions to meet an
3583 alignment requirement, there must have been an odd number of
3584 instructions since the last 8-byte-aligned execute packet
3585 boundary. So there must have been an execute packet with an
3586 odd number (and so a number fewer than 8) of instructions
3587 into which we can insert a NOP without breaking any previous
3590 If then we need to insert a number 2 mod 4 of instructions,
3591 the number of instructions since the last 16-byte-aligned
3592 execute packet boundary must be 2 mod 4. So between that
3593 boundary and the following 8-byte-aligned boundary there must
3594 either be at least one execute packet with 2-mod-4
3595 instructions, or at least two with an odd number of
3596 instructions; again, greedily inserting NOPs as soon as
3597 possible suffices to meet the alignment requirement.
3599 If then we need to insert 4 instructions, we look between the
3600 last 32-byte-aligned boundary and the following
3601 16-byte-aligned boundary. The sizes of the execute packets
3602 in this range total 4 instructions mod 8, so again there is
3603 room for greedy insertion of NOPs to meet the alignment
3604 requirement, and before any intermediate point with 8-byte
3605 (2-instruction) alignment requirement the sizes of execute
3606 packets (and so the room for NOPs) will total 2 instructions
3607 mod 4 so greedy insertion will not break such alignments.
3609 So we can always meet these alignment requirements by
3610 inserting NOPs in parallel with existing execute packets, and
3611 by induction the approach described above inserts the minimum
3612 number of such NOPs. */
3614 /* The number of NOPs we are currently looking to insert, if we
3615 have gone back to insert NOPs. */
3616 unsigned int want_insert = 0;
3618 /* Out of that number, the number inserted so far in the current
3619 stage of the above algorithm. */
3620 unsigned int want_insert_done_so_far = 0;
3622 /* The position mod 32 at the start of the current frag. */
3623 unsigned int pos = 0;
3625 /* The locations in the frag chain of the most recent frags at
3626 the start of which there is the given alignment. */
3627 frchainS *frchp_last32, *frchp_last16, *frchp_last8;
3628 fragS *fragp_last32, *fragp_last16, *fragp_last8;
3629 unsigned int pos_last32, pos_last16, pos_last8;
3631 frchp_last32 = frchp_last16 = frchp_last8 = info->frchainP;
3632 fragp_last32 = fragp_last16 = fragp_last8 = info->frchainP->frch_root;
3633 pos_last32 = pos_last16 = pos_last8 = 0;
3635 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3636 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3639 bfd_boolean go_back = FALSE;
3640 frchainS *frchp_next;
3643 if (fragp->fr_type != rs_machine_dependent)
3646 if (fragp->tc_frag_data.is_insns
3647 && pos + fragp->fr_fix > 32
3648 && !fragp->tc_frag_data.can_cross_fp_boundary)
3650 /* As described above, we should always have met an
3651 alignment requirement by the time we come back to
3658 want_insert = (32 - pos) >> 2;
3659 if (want_insert > 7)
3661 want_insert_done_so_far = 0;
3665 if (!fragp->tc_frag_data.is_insns)
3667 unsigned int would_insert_bytes;
3669 if (!(pos & ((1 << fragp->fr_offset) - 1)))
3670 /* This alignment requirement is already met. */
3673 /* As described above, we should always have met an
3674 alignment requirement by the time we come back to
3679 /* We may not be able to meet this requirement within
3680 the given number of characters. */
3682 = ((1 << fragp->fr_offset)
3683 - (pos & ((1 << fragp->fr_offset) - 1)));
3685 if (fragp->fr_subtype != 0
3686 && would_insert_bytes > fragp->fr_subtype)
3689 /* An unmet alignment must be 8, 16 or 32 bytes;
3690 smaller ones must always be met within code-only
3691 sections and larger ones cause the section not to
3693 if (fragp->fr_offset != 3
3694 && fragp->fr_offset != 4
3695 && fragp->fr_offset != 5)
3698 if (would_insert_bytes & 3)
3700 want_insert = would_insert_bytes >> 2;
3701 if (want_insert > 7)
3703 want_insert_done_so_far = 0;
3706 else if (want_insert && !go_back)
3708 unsigned int num_insns = fragp->fr_fix >> 2;
3709 unsigned int max_poss_nops = 8 - num_insns;
3713 unsigned int cur_want_nops, max_want_nops, do_nops, i;
3715 if (want_insert & 1)
3717 else if (want_insert & 2)
3719 else if (want_insert & 4)
3724 max_want_nops = cur_want_nops - want_insert_done_so_far;
3726 do_nops = (max_poss_nops < max_want_nops
3729 for (i = 0; i < do_nops; i++)
3731 md_number_to_chars (fragp->fr_literal + fragp->fr_fix,
3733 if (target_big_endian)
3734 fragp->fr_literal[fragp->fr_fix - 1] |= 0x1;
3736 fragp->fr_literal[fragp->fr_fix - 4] |= 0x1;
3740 want_insert_done_so_far += do_nops;
3741 if (want_insert_done_so_far == cur_want_nops)
3743 want_insert -= want_insert_done_so_far;
3744 want_insert_done_so_far = 0;
3752 if (want_insert & 1)
3754 frchp = frchp_last8;
3755 fragp = fragp_last8;
3758 else if (want_insert & 2)
3760 frchp = frchp_last8 = frchp_last16;
3761 fragp = fragp_last8 = fragp_last16;
3762 pos = pos_last8 = pos_last16;
3764 else if (want_insert & 4)
3766 frchp = frchp_last8 = frchp_last16 = frchp_last32;
3767 fragp = fragp_last8 = fragp_last16 = fragp_last32;
3768 pos = pos_last8 = pos_last16 = pos_last32;
3776 /* Update current position for moving past a code
3778 pos += fragp->fr_fix;
3781 fragp_next = fragp->fr_next;
3782 if (fragp_next == NULL)
3784 frchp_next = frchp->frch_next;
3785 if (frchp_next != NULL)
3786 fragp_next = frchp_next->frch_root;
3790 frchp_last8 = frchp_next;
3791 fragp_last8 = fragp_next;
3796 frchp_last16 = frchp_next;
3797 fragp_last16 = fragp_next;
3802 frchp_last32 = frchp_next;
3803 fragp_last32 = fragp_next;
3809 /* Now convert the machine-dependent frags to machine-independent
3811 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3812 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3814 if (fragp->fr_type == rs_machine_dependent)
3816 if (fragp->tc_frag_data.is_insns)
3820 fragp->fr_type = rs_align_code;
3822 *fragp->fr_literal = 0;
3828 /* Initialize the machine-dependent parts of a frag. */
3831 tic6x_frag_init (fragS *fragp)
3833 fragp->tc_frag_data.is_insns = FALSE;
3834 fragp->tc_frag_data.can_cross_fp_boundary = FALSE;
3837 /* Set an attribute if it has not already been set by the user. */
3840 tic6x_set_attribute_int (int tag, int value)
3843 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES)
3845 if (!tic6x_attributes_set_explicitly[tag])
3846 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
3849 /* Set object attributes deduced from the input file and command line
3850 rather than given explicitly. */
3852 tic6x_set_attributes (void)
3854 if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
3855 tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
3857 tic6x_set_attribute_int (Tag_C6XABI_Tag_CPU_arch, tic6x_arch_attribute);
3860 /* Do machine-dependent manipulations of the frag chains after all
3861 input has been read and before the machine-independent sizing and
3867 /* Set object attributes at this point if not explicitly set. */
3868 tic6x_set_attributes ();
3870 /* Meeting alignment requirements may require inserting NOPs in
3871 parallel in execute packets earlier in the segment. Future
3872 16-bit instruction generation involves whole-segment optimization
3873 to determine the best choice and ordering of 32-bit or 16-bit
3874 instructions. This doesn't fit will in the general relaxation
3875 framework, so handle alignment and 16-bit instruction generation
3877 bfd_map_over_sections (stdoutput, tic6x_adjust_section, NULL);
3880 /* No machine-dependent frags at this stage; all converted in
3884 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3885 fragS *fragp ATTRIBUTE_UNUSED)
3890 /* No machine-dependent frags at this stage; all converted in
3894 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
3895 segT seg ATTRIBUTE_UNUSED)
3900 /* Put a number into target byte order. */
3903 md_number_to_chars (char *buf, valueT val, int n)
3905 if (target_big_endian)
3906 number_to_chars_bigendian (buf, val, n);
3908 number_to_chars_littleendian (buf, val, n);
3911 /* Machine-dependent operand parsing not currently needed. */
3914 md_operand (expressionS *op ATTRIBUTE_UNUSED)
3918 /* PC-relative operands are relative to the start of the fetch
3922 tic6x_pcrel_from_section (fixS *fixp, segT sec)
3924 if (fixp->fx_addsy != NULL
3925 && (!S_IS_DEFINED (fixp->fx_addsy)
3926 || S_GET_SEGMENT (fixp->fx_addsy) != sec))
3928 return (fixp->fx_where + fixp->fx_frag->fr_address) & ~(long) 0x1f;
3931 /* Round up a section size to the appropriate boundary. */
3934 md_section_align (segT segment ATTRIBUTE_UNUSED,
3937 /* Round up section sizes to ensure that text sections consist of
3938 whole fetch packets. */
3939 int align = bfd_get_section_alignment (stdoutput, segment);
3940 return ((size + (1 << align) - 1) & ((valueT) -1 << align));
3943 /* No special undefined symbol handling needed for now. */
3946 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3951 /* Translate internal representation of relocation info to BFD target
3955 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3958 bfd_reloc_code_real_type r_type;
3960 reloc = xmalloc (sizeof (arelent));
3961 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3962 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3963 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3964 reloc->addend = (tic6x_generate_rela ? fixp->fx_offset : 0);
3965 r_type = fixp->fx_r_type;
3966 reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);
3968 if (reloc->howto == NULL)
3970 as_bad_where (fixp->fx_file, fixp->fx_line,
3971 _("Cannot represent relocation type %s"),
3972 bfd_get_reloc_code_name (r_type));
3976 /* Correct for adjustments bfd_install_relocation will make. */
3977 if (reloc->howto->pcrel_offset && reloc->howto->partial_inplace)
3978 reloc->addend += reloc->address;