3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "dwarf2dbg.h"
24 #include "safe-ctype.h"
26 #include "opcode/tic6x.h"
27 #include "elf/tic6x.h"
28 #include "elf32-tic6x.h"
30 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit
31 host gives identical results to a 32-bit host. */
32 #define TRUNC(X) ((valueT) (X) & 0xffffffffU)
33 #define SEXT(X) ((TRUNC (X) ^ 0x80000000U) - 0x80000000U)
35 const char comment_chars[] = ";";
36 const char line_comment_chars[] = "#*;";
37 const char line_separator_chars[] = "@";
39 const char EXP_CHARS[] = "eE";
40 const char FLT_CHARS[] = "dDfF";
42 const char *md_shortopts = "";
46 OPTION_MARCH = OPTION_MD_BASE,
50 OPTION_MLITTLE_ENDIAN,
54 struct option md_longopts[] =
56 { "march", required_argument, NULL, OPTION_MARCH },
57 { "matomic", no_argument, NULL, OPTION_MATOMIC },
58 { "mno-atomic", no_argument, NULL, OPTION_MNO_ATOMIC },
59 { "mbig-endian", no_argument, NULL, OPTION_MBIG_ENDIAN },
60 { "mlittle-endian", no_argument, NULL, OPTION_MLITTLE_ENDIAN },
61 { "mgenerate-rel", no_argument, NULL, OPTION_MGENERATE_REL },
62 { NULL, no_argument, NULL, 0 }
64 size_t md_longopts_size = sizeof (md_longopts);
66 /* Whether to enable atomic instructions. 1 to enable them, 0 to
67 disable, -1 to default from architecture. */
68 static int tic6x_atomic = -1;
70 /* The instructions enabled based only on the selected architecture
71 (all instructions, if no architecture specified). Atomic
72 instructions may be enabled or disabled separately. */
73 static unsigned short tic6x_arch_enable = (TIC6X_INSN_C62X
81 /* The instructions enabled based on the current set of features
82 (architecture, as modified by other options). */
83 static unsigned short tic6x_features;
85 /* The architecture attribute value, or C6XABI_Tag_CPU_arch_none if
87 static int tic6x_arch_attribute = C6XABI_Tag_CPU_arch_none;
89 /* Whether any instructions at all have been seen. Once any
90 instructions have been seen, architecture attributes merge into the
91 previous attribute value rather than replacing it. */
92 static bfd_boolean tic6x_seen_insns = FALSE;
94 /* The number of registers in each register file supported by the
95 current architecture. */
96 static unsigned int tic6x_num_registers;
98 /* Whether predication on A0 is possible. */
99 static bfd_boolean tic6x_predicate_a0;
101 /* Whether execute packets can cross fetch packet boundaries. */
102 static bfd_boolean tic6x_can_cross_fp_boundary;
104 /* Whether there are constraints on simultaneous reads and writes of
106 static bfd_boolean tic6x_long_data_constraints;
108 /* Whether compact instructions are available. */
109 static bfd_boolean tic6x_compact_insns;
111 /* Whether to generate RELA relocations. */
112 static bfd_boolean tic6x_generate_rela = TRUE;
114 /* Table of supported architecture variants. */
119 unsigned short features;
121 static const tic6x_arch_table tic6x_arches[] =
123 { "c62x", C6XABI_Tag_CPU_arch_C62X, TIC6X_INSN_C62X },
124 { "c64x", C6XABI_Tag_CPU_arch_C64X, TIC6X_INSN_C62X | TIC6X_INSN_C64X },
125 { "c64x+", C6XABI_Tag_CPU_arch_C64XP, (TIC6X_INSN_C62X
127 | TIC6X_INSN_C64XP) },
128 { "c67x", C6XABI_Tag_CPU_arch_C67X, TIC6X_INSN_C62X | TIC6X_INSN_C67X },
129 { "c67x+", C6XABI_Tag_CPU_arch_C67XP, (TIC6X_INSN_C62X
131 | TIC6X_INSN_C67XP) },
132 { "c674x", C6XABI_Tag_CPU_arch_C674X, (TIC6X_INSN_C62X
137 | TIC6X_INSN_C674X) }
140 /* Update the selected architecture based on ARCH, giving an error if
141 ARCH is an invalid value. Does not call tic6x_update_features; the
142 caller must do that if necessary. */
145 tic6x_use_arch (const char *arch)
149 for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
150 if (strcmp (arch, tic6x_arches[i].arch) == 0)
152 tic6x_arch_enable = tic6x_arches[i].features;
153 if (tic6x_seen_insns)
155 = elf32_tic6x_merge_arch_attributes (tic6x_arch_attribute,
156 tic6x_arches[i].attr);
158 tic6x_arch_attribute = tic6x_arches[i].attr;
162 as_bad (_("unknown architecture '%s'"), arch);
165 /* Parse a target-specific option. */
168 md_parse_option (int c, char *arg)
173 tic6x_use_arch (arg);
180 case OPTION_MNO_ATOMIC:
184 case OPTION_MBIG_ENDIAN:
185 target_big_endian = 1;
188 case OPTION_MLITTLE_ENDIAN:
189 target_big_endian = 0;
192 case OPTION_MGENERATE_REL:
193 tic6x_generate_rela = FALSE;
203 md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
207 fputc ('\n', stream);
208 fprintf (stream, _("TMS320C6000 options:\n"));
209 fprintf (stream, _(" -march=ARCH enable instructions from architecture ARCH\n"));
210 fprintf (stream, _(" -matomic enable atomic operation instructions\n"));
211 fprintf (stream, _(" -mno-atomic disable atomic operation instructions\n"));
212 fprintf (stream, _(" -mbig-endian generate big-endian code\n"));
213 fprintf (stream, _(" -mlittle-endian generate little-endian code\n"));
214 /* -mgenerate-rel is only for testsuite use and is deliberately
217 fputc ('\n', stream);
218 fprintf (stream, _("Supported ARCH values are:"));
219 for (i = 0; i < ARRAY_SIZE (tic6x_arches); i++)
220 fprintf (stream, " %s", tic6x_arches[i].arch);
221 fputc ('\n', stream);
224 /* Update enabled features based on the current architecture and
227 tic6x_update_features (void)
229 switch (tic6x_atomic)
232 tic6x_features = tic6x_arch_enable;
236 tic6x_features = tic6x_arch_enable & ~TIC6X_INSN_ATOMIC;
240 tic6x_features = tic6x_arch_enable | TIC6X_INSN_ATOMIC;
248 = (tic6x_arch_enable & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? 32 : 16;
250 tic6x_predicate_a0 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? TRUE : FALSE;
252 tic6x_can_cross_fp_boundary
254 & (TIC6X_INSN_C64X | TIC6X_INSN_C67XP)) ? TRUE : FALSE;
256 tic6x_long_data_constraints
257 = (tic6x_arch_enable & TIC6X_INSN_C64X) ? FALSE : TRUE;
259 tic6x_compact_insns = (tic6x_arch_enable & TIC6X_INSN_C64XP) ? TRUE : FALSE;
262 /* Do configuration after all options have been parsed. */
265 tic6x_after_parse_args (void)
267 tic6x_update_features ();
270 /* Parse a .arch directive. */
273 s_tic6x_arch (int ignored ATTRIBUTE_UNUSED)
278 arch = input_line_pointer;
279 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
280 input_line_pointer++;
281 c = *input_line_pointer;
282 *input_line_pointer = 0;
284 tic6x_use_arch (arch);
285 tic6x_update_features ();
286 *input_line_pointer = c;
287 demand_empty_rest_of_line ();
290 /* Parse a .atomic directive. */
293 s_tic6x_atomic (int ignored ATTRIBUTE_UNUSED)
296 tic6x_update_features ();
297 demand_empty_rest_of_line ();
300 /* Parse a .noatomic directive. */
303 s_tic6x_noatomic (int ignored ATTRIBUTE_UNUSED)
306 tic6x_update_features ();
307 demand_empty_rest_of_line ();
310 /* Parse a .nocmp directive. */
313 s_tic6x_nocmp (int ignored ATTRIBUTE_UNUSED)
315 seg_info (now_seg)->tc_segment_info_data.nocmp = TRUE;
316 demand_empty_rest_of_line ();
319 /* Track for each attribute whether it has been set explicitly (and so
320 should not have a default value set by the assembler). */
321 static bfd_boolean tic6x_attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
323 /* Parse a .c6xabi_attribute directive. */
326 s_tic6x_c6xabi_attribute (int ignored ATTRIBUTE_UNUSED)
328 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
330 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
331 tic6x_attributes_set_explicitly[tag] = TRUE;
338 } tic6x_attribute_table;
340 static const tic6x_attribute_table tic6x_attributes[] =
342 #define TAG(tag, value) { #tag, tag }
343 #include "elf/tic6x-attrs.h"
347 /* Convert an attribute name to a number. */
350 tic6x_convert_symbolic_attribute (const char *name)
354 for (i = 0; i < ARRAY_SIZE (tic6x_attributes); i++)
355 if (strcmp (name, tic6x_attributes[i].name) == 0)
356 return tic6x_attributes[i].tag;
361 const pseudo_typeS md_pseudo_table[] =
363 { "arch", s_tic6x_arch, 0 },
364 { "atomic", s_tic6x_atomic, 0 },
365 { "c6xabi_attribute", s_tic6x_c6xabi_attribute, 0 },
366 { "noatomic", s_tic6x_noatomic, 0 },
367 { "nocmp", s_tic6x_nocmp, 0 },
372 /* Hash table of opcodes. For each opcode name, this stores a pointer
373 to a tic6x_opcode_list listing (in an arbitrary order) all opcode
374 table entries with that name. */
375 static struct hash_control *opcode_hash;
377 /* Initialize the assembler (called once at assembler startup). */
384 bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
386 /* Insert opcodes into the hash table. */
387 opcode_hash = hash_new ();
388 for (id = 0; id < tic6x_opcode_max; id++)
391 tic6x_opcode_list *opc = xmalloc (sizeof (tic6x_opcode_list));
394 opc->next = hash_find (opcode_hash, tic6x_opcode_table[id].name);
395 if ((errmsg = hash_jam (opcode_hash, tic6x_opcode_table[id].name, opc))
397 as_fatal ("%s", _(errmsg));
401 /* Whether the current line being parsed had the "||" parallel bars. */
402 static bfd_boolean tic6x_line_parallel;
404 /* Whether the current line being parsed started "||^" to indicate an
405 SPMASKed parallel instruction. */
406 static bfd_boolean tic6x_line_spmask;
408 /* If the current line being parsed had an instruction predicate, the
409 creg value for that predicate (which must be nonzero); otherwise
411 static unsigned int tic6x_line_creg;
413 /* If the current line being parsed had an instruction predicate, the
414 z value for that predicate; otherwise 0. */
415 static unsigned int tic6x_line_z;
417 /* Return 1 (updating input_line_pointer as appropriate) if the line
418 starting with C (immediately before input_line_pointer) starts with
419 pre-opcode text appropriate for this target, 0 otherwise. */
422 tic6x_unrecognized_line (int c)
427 bfd_boolean bad_predicate;
432 if (input_line_pointer[0] == '|')
434 if (input_line_pointer[1] == '^')
436 tic6x_line_spmask = TRUE;
437 input_line_pointer += 2;
440 input_line_pointer += 1;
441 if (tic6x_line_parallel)
442 as_bad (_("multiple '||' on same line"));
443 tic6x_line_parallel = TRUE;
445 as_bad (_("'||' after predicate"));
451 /* If it doesn't look like a predicate at all, just return 0.
452 If it looks like one but not a valid one, give a better
454 p = input_line_pointer;
455 while (*p != ']' && !is_end_of_line[(unsigned char) *p])
460 p = input_line_pointer;
462 bad_predicate = FALSE;
468 if (*p == 'A' || *p == 'a')
470 else if (*p == 'B' || *p == 'b')
474 areg = TRUE; /* Avoid uninitialized warning. */
475 bad_predicate = TRUE;
480 if (*p != '0' && *p != '1' && *p != '2')
481 bad_predicate = TRUE;
482 else if (p[1] != ']')
483 bad_predicate = TRUE;
485 input_line_pointer = p + 2;
489 as_bad (_("multiple predicates on same line"));
495 as_bad (_("bad predicate '%s'"), input_line_pointer - 1);
497 input_line_pointer = endp;
504 tic6x_line_creg = (areg ? 6 : 1);
505 if (areg && !tic6x_predicate_a0)
506 as_bad (_("predication on A0 not supported on this architecture"));
510 tic6x_line_creg = (areg ? 4 : 2);
514 tic6x_line_creg = (areg ? 5 : 3);
529 /* Do any target-specific handling of a label required. */
532 tic6x_frob_label (symbolS *sym)
534 segment_info_type *si;
535 tic6x_label_list *list;
537 if (tic6x_line_parallel)
539 as_bad (_("label after '||'"));
540 tic6x_line_parallel = FALSE;
541 tic6x_line_spmask = FALSE;
545 as_bad (_("label after predicate"));
550 si = seg_info (now_seg);
551 list = si->tc_segment_info_data.label_list;
552 si->tc_segment_info_data.label_list = xmalloc (sizeof (tic6x_label_list));
553 si->tc_segment_info_data.label_list->next = list;
554 si->tc_segment_info_data.label_list->label = sym;
556 /* Defining tc_frob_label overrides the ELF definition of
557 obj_frob_label, so we need to apply its effects here. */
558 dwarf2_emit_label (sym);
561 /* At end-of-line, give errors for start-of-line decorations that
562 needed an instruction but were not followed by one. */
565 tic6x_end_of_line (void)
567 if (tic6x_line_parallel)
569 as_bad (_("'||' not followed by instruction"));
570 tic6x_line_parallel = FALSE;
571 tic6x_line_spmask = FALSE;
575 as_bad (_("predicate not followed by instruction"));
581 /* Do any target-specific handling of the start of a logical line. */
584 tic6x_start_line_hook (void)
586 tic6x_end_of_line ();
589 /* Do target-specific handling immediately after an input file from
590 the command line, and any other inputs it includes, have been
596 tic6x_end_of_line ();
599 /* Do target-specific initialization after arguments have been
600 processed and the output file created. */
603 tic6x_init_after_args (void)
605 elf32_tic6x_set_use_rela_p (stdoutput, tic6x_generate_rela);
608 /* Free LIST of labels (possibly NULL). */
611 tic6x_free_label_list (tic6x_label_list *list)
615 tic6x_label_list *old = list;
622 /* Handle a data alignment of N bytes. */
625 tic6x_cons_align (int n ATTRIBUTE_UNUSED)
627 segment_info_type *seginfo = seg_info (now_seg);
629 /* Data means there is no current execute packet, and that any label
630 applies to that data rather than a subsequent instruction. */
631 tic6x_free_label_list (seginfo->tc_segment_info_data.label_list);
632 seginfo->tc_segment_info_data.label_list = NULL;
633 seginfo->tc_segment_info_data.execute_packet_frag = NULL;
634 seginfo->tc_segment_info_data.last_insn_lsb = NULL;
635 seginfo->tc_segment_info_data.spmask_addr = NULL;
636 seginfo->tc_segment_info_data.func_units_used = 0;
639 /* Handle an alignment directive. Return TRUE if the
640 machine-independent frag generation should be skipped. */
643 tic6x_do_align (int n, char *fill, int len ATTRIBUTE_UNUSED, int max)
645 /* Given code alignments of 4, 8, 16 or 32 bytes, we try to handle
646 them in the md_end pass by inserting NOPs in parallel with
647 previous instructions. We only do this in sections containing
648 nothing but instructions. Code alignments of 1 or 2 bytes have
649 no effect in such sections (but we record them with
650 machine-dependent frags anyway so they can be skipped or
651 converted to machine-independent), while those of more than 64
652 bytes cannot reliably be handled in this way. */
658 && subseg_text_p (now_seg))
666 /* Machine-independent code would generate a frag here, but we
667 wish to handle it in a machine-dependent way. */
668 if (frag_now_fix () != 0)
670 if (frag_now->fr_type != rs_machine_dependent)
671 frag_wane (frag_now);
676 align_frag = frag_now;
677 p = frag_var (rs_machine_dependent, 32, 32, max, NULL, n, NULL);
678 /* This must be the same as the frag to which a pointer was just
680 if (p != align_frag->fr_literal)
682 align_frag->tc_frag_data.is_insns = FALSE;
689 /* Types of operand for parsing purposes. These are used as bit-masks
690 to tell tic6x_parse_operand what forms of operand are
692 #define TIC6X_OP_EXP 0x0001u
693 #define TIC6X_OP_REG 0x0002u
694 #define TIC6X_OP_REGPAIR 0x0004u
695 #define TIC6X_OP_IRP 0x0008u
696 #define TIC6X_OP_NRP 0x0010u
697 /* With TIC6X_OP_MEM_NOUNREG, the contents of a () offset are always
698 interpreted as an expression, which may be a symbol with the same
699 name as a register that ends up being implicitly DP-relative. With
700 TIC6X_OP_MEM_UNREG, the contents of a () offset are interpreted as
701 a register if they match one, and failing that as an expression,
702 which must be constant. */
703 #define TIC6X_OP_MEM_NOUNREG 0x0020u
704 #define TIC6X_OP_MEM_UNREG 0x0040u
705 #define TIC6X_OP_CTRL 0x0080u
706 #define TIC6X_OP_FUNC_UNIT 0x0100u
708 /* A register or register pair read by the assembler. */
711 /* The side the register is on (1 or 2). */
713 /* The register number (0 to 31). */
717 /* Types of modification of a base address. */
723 tic6x_mem_mod_preinc,
724 tic6x_mem_mod_predec,
725 tic6x_mem_mod_postinc,
726 tic6x_mem_mod_postdec
729 /* Scaled [] or unscaled () nature of an offset. */
734 tic6x_offset_unscaled
737 /* A memory operand read by the assembler. */
740 /* The base register. */
741 tic6x_register base_reg;
742 /* How the base register is modified. */
744 /* Whether there is an offset (required with plain "+" and "-"), and
745 whether it is scaled or unscaled if so. */
746 tic6x_mem_scaling scaled;
747 /* Whether the offset is a register (TRUE) or an expression
749 bfd_boolean offset_is_reg;
758 /* A functional unit in SPMASK operands read by the assembler. */
761 /* The basic unit. */
762 tic6x_func_unit_base base;
763 /* The side (1 or 2). */
765 } tic6x_func_unit_operand;
767 /* An operand read by the assembler. */
770 /* The syntactic form of the operand, as one of the bit-masks
773 /* The operand value. */
776 /* An expression: TIC6X_OP_EXP. */
778 /* A register: TIC6X_OP_REG, TIC6X_OP_REGPAIR. */
780 /* A memory reference: TIC6X_OP_MEM_NOUNREG,
781 TIC6X_OP_MEM_UNREG. */
783 /* A control register: TIC6X_OP_CTRL. */
785 /* A functional unit: TIC6X_OP_FUNC_UNIT. */
786 tic6x_func_unit_operand func_unit;
790 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
792 /* Parse a register operand, or part of an operand, starting at *P.
793 If syntactically OK (including that the number is in the range 0 to
794 31, but not necessarily in range for this architecture), return
795 TRUE, putting the register side and number in *REG and update *P to
796 point immediately after the register number; otherwise return FALSE
797 without changing *P (but possibly changing *REG). Do not print any
801 tic6x_parse_register (char **p, tic6x_register *reg)
822 if (*r >= '0' && *r <= '9')
830 if (reg->num > 0 && *r >= '0' && *r <= '9')
832 reg->num = reg->num * 10 + (*r - '0');
836 if (*r >= '0' && *r <= '9')
845 /* Parse the initial two characters of a functional unit name starting
846 at *P. If OK, set *BASE and *SIDE and return TRUE; otherwise,
850 tic6x_parse_func_unit_base (char *p, tic6x_func_unit_base *base,
853 bfd_boolean good_func_unit = TRUE;
854 tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
855 unsigned int maybe_side = 0;
861 maybe_base = tic6x_func_unit_d;
866 maybe_base = tic6x_func_unit_l;
871 maybe_base = tic6x_func_unit_m;
876 maybe_base = tic6x_func_unit_s;
880 good_func_unit = FALSE;
896 good_func_unit = FALSE;
906 return good_func_unit;
909 /* Parse an operand starting at *P. If the operand parses OK, return
910 TRUE and store the value in *OP; otherwise return FALSE (possibly
911 changing *OP). In any case, update *P to point to the following
912 comma or end of line. The possible operand forms are given by
913 OP_FORMS. For diagnostics, this is operand OPNO of an opcode
914 starting at STR, length OPC_LEN. */
917 tic6x_parse_operand (char **p, tic6x_operand *op, unsigned int op_forms,
918 char *str, int opc_len, unsigned int opno)
920 bfd_boolean operand_parsed = FALSE;
923 if ((op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
924 == (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG))
927 /* Check for functional unit names for SPMASK and SPMASKR. */
928 if (!operand_parsed && (op_forms & TIC6X_OP_FUNC_UNIT))
930 tic6x_func_unit_base base = tic6x_func_unit_nfu;
931 unsigned int side = 0;
933 if (tic6x_parse_func_unit_base (q, &base, &side))
937 skip_whitespace (rq);
938 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
940 op->form = TIC6X_OP_FUNC_UNIT;
941 op->value.func_unit.base = base;
942 op->value.func_unit.side = side;
943 operand_parsed = TRUE;
949 /* Check for literal "irp". */
950 if (!operand_parsed && (op_forms & TIC6X_OP_IRP))
952 if ((q[0] == 'i' || q[0] == 'I')
953 && (q[1] == 'r' || q[1] == 'R')
954 && (q[2] == 'p' || q[2] == 'P'))
958 skip_whitespace (rq);
959 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
961 op->form = TIC6X_OP_IRP;
962 operand_parsed = TRUE;
968 /* Check for literal "nrp". */
969 if (!operand_parsed && (op_forms & TIC6X_OP_NRP))
971 if ((q[0] == 'n' || q[0] == 'N')
972 && (q[1] == 'r' || q[1] == 'R')
973 && (q[2] == 'p' || q[2] == 'P'))
977 skip_whitespace (rq);
978 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
980 op->form = TIC6X_OP_NRP;
981 operand_parsed = TRUE;
987 /* Check for control register names. */
988 if (!operand_parsed && (op_forms & TIC6X_OP_CTRL))
992 for (crid = 0; crid < tic6x_ctrl_max; crid++)
994 size_t len = strlen (tic6x_ctrl_table[crid].name);
996 if (strncasecmp (tic6x_ctrl_table[crid].name, q, len) == 0)
1000 skip_whitespace (rq);
1001 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1003 op->form = TIC6X_OP_CTRL;
1004 op->value.ctrl = crid;
1005 operand_parsed = TRUE;
1007 if (!(tic6x_ctrl_table[crid].isa_variants & tic6x_features))
1008 as_bad (_("control register '%s' not supported "
1009 "on this architecture"),
1010 tic6x_ctrl_table[crid].name);
1016 /* See if this looks like a memory reference. */
1018 && (op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG)))
1020 bfd_boolean mem_ok = TRUE;
1022 tic6x_mem_mod mem_mod = tic6x_mem_mod_none;
1023 tic6x_register base_reg;
1024 bfd_boolean require_offset, permit_offset;
1025 tic6x_mem_scaling scaled;
1026 bfd_boolean offset_is_reg;
1027 expressionS offset_exp;
1028 tic6x_register offset_reg;
1037 skip_whitespace (mq);
1043 mem_mod = tic6x_mem_mod_preinc;
1048 mem_mod = tic6x_mem_mod_plus;
1056 mem_mod = tic6x_mem_mod_predec;
1061 mem_mod = tic6x_mem_mod_minus;
1073 skip_whitespace (mq);
1074 mem_ok = tic6x_parse_register (&mq, &base_reg);
1077 if (mem_ok && mem_mod == tic6x_mem_mod_none)
1079 skip_whitespace (mq);
1080 if (mq[0] == '+' && mq[1] == '+')
1082 mem_mod = tic6x_mem_mod_postinc;
1085 else if (mq[0] == '-' && mq[1] == '-')
1087 mem_mod = tic6x_mem_mod_postdec;
1092 if (mem_mod == tic6x_mem_mod_none)
1093 permit_offset = FALSE;
1095 permit_offset = TRUE;
1096 if (mem_mod == tic6x_mem_mod_plus || mem_mod == tic6x_mem_mod_minus)
1097 require_offset = TRUE;
1099 require_offset = FALSE;
1100 scaled = tic6x_offset_none;
1101 offset_is_reg = FALSE;
1103 if (mem_ok && permit_offset)
1107 skip_whitespace (mq);
1111 scaled = tic6x_offset_scaled;
1117 scaled = tic6x_offset_unscaled;
1125 if (scaled != tic6x_offset_none)
1127 skip_whitespace (mq);
1128 if (scaled == tic6x_offset_scaled
1129 || (op_forms & TIC6X_OP_MEM_UNREG))
1134 reg_ok = tic6x_parse_register (&rq, &offset_reg);
1137 skip_whitespace (rq);
1141 offset_is_reg = TRUE;
1147 char *save_input_line_pointer;
1149 save_input_line_pointer = input_line_pointer;
1150 input_line_pointer = mq;
1151 expression (&offset_exp);
1152 mq = input_line_pointer;
1153 input_line_pointer = save_input_line_pointer;
1155 skip_whitespace (mq);
1163 if (mem_ok && require_offset && scaled == tic6x_offset_none)
1168 skip_whitespace (mq);
1169 if (!is_end_of_line[(unsigned char) *mq] && *mq != ',')
1175 op->form = op_forms & (TIC6X_OP_MEM_NOUNREG | TIC6X_OP_MEM_UNREG);
1176 op->value.mem.base_reg = base_reg;
1177 op->value.mem.mod = mem_mod;
1178 op->value.mem.scaled = scaled;
1179 op->value.mem.offset_is_reg = offset_is_reg;
1181 op->value.mem.offset.reg = offset_reg;
1183 op->value.mem.offset.exp = offset_exp;
1184 operand_parsed = TRUE;
1186 if (base_reg.num >= tic6x_num_registers)
1187 as_bad (_("register number %u not supported on this architecture"),
1189 if (offset_is_reg && offset_reg.num >= tic6x_num_registers)
1190 as_bad (_("register number %u not supported on this architecture"),
1195 /* See if this looks like a register or register pair. */
1196 if (!operand_parsed && (op_forms & (TIC6X_OP_REG | TIC6X_OP_REGPAIR)))
1198 tic6x_register first_reg, second_reg;
1202 reg_ok = tic6x_parse_register (&rq, &first_reg);
1206 if (*rq == ':' && (op_forms & TIC6X_OP_REGPAIR))
1209 reg_ok = tic6x_parse_register (&rq, &second_reg);
1212 skip_whitespace (rq);
1213 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1215 if ((second_reg.num & 1)
1216 || (first_reg.num != second_reg.num + 1)
1217 || (first_reg.side != second_reg.side))
1218 as_bad (_("register pair for operand %u of '%.*s'"
1219 " not a valid even/odd pair"), opno,
1221 op->form = TIC6X_OP_REGPAIR;
1222 op->value.reg = second_reg;
1223 operand_parsed = TRUE;
1228 else if (op_forms & TIC6X_OP_REG)
1230 skip_whitespace (rq);
1231 if (is_end_of_line[(unsigned char) *rq] || *rq == ',')
1233 op->form = TIC6X_OP_REG;
1234 op->value.reg = first_reg;
1235 operand_parsed = TRUE;
1242 if (first_reg.num >= tic6x_num_registers)
1243 as_bad (_("register number %u not supported on this architecture"),
1245 if (op->form == TIC6X_OP_REGPAIR
1246 && second_reg.num >= tic6x_num_registers)
1247 as_bad (_("register number %u not supported on this architecture"),
1252 /* Otherwise, parse it as an expression. */
1253 if (!operand_parsed && (op_forms & TIC6X_OP_EXP))
1255 char *save_input_line_pointer;
1257 save_input_line_pointer = input_line_pointer;
1258 input_line_pointer = q;
1259 op->form = TIC6X_OP_EXP;
1260 expression (&op->value.exp);
1261 q = input_line_pointer;
1262 input_line_pointer = save_input_line_pointer;
1263 operand_parsed = TRUE;
1268 /* Now the operand has been parsed, there must be nothing more
1269 before the comma or end of line. */
1270 skip_whitespace (q);
1271 if (!is_end_of_line[(unsigned char) *q] && *q != ',')
1273 operand_parsed = FALSE;
1274 as_bad (_("junk after operand %u of '%.*s'"), opno,
1276 while (!is_end_of_line[(unsigned char) *q] && *q != ',')
1282 /* This could not be parsed as any acceptable form of
1286 case TIC6X_OP_REG | TIC6X_OP_REGPAIR:
1287 as_bad (_("bad register or register pair for operand %u of '%.*s'"),
1288 opno, opc_len, str);
1291 case TIC6X_OP_REG | TIC6X_OP_CTRL:
1293 as_bad (_("bad register for operand %u of '%.*s'"),
1294 opno, opc_len, str);
1297 case TIC6X_OP_REGPAIR:
1298 as_bad (_("bad register pair for operand %u of '%.*s'"),
1299 opno, opc_len, str);
1302 case TIC6X_OP_FUNC_UNIT:
1303 as_bad (_("bad functional unit for operand %u of '%.*s'"),
1304 opno, opc_len, str);
1308 as_bad (_("bad operand %u of '%.*s'"),
1309 opno, opc_len, str);
1313 while (!is_end_of_line[(unsigned char) *q] && *q != ',')
1317 return operand_parsed;
1320 /* Table of assembler operators and associated O_* values. */
1325 } tic6x_operator_table;
1326 static const tic6x_operator_table tic6x_operators[] = {
1327 #define O_dsbt_index O_md1
1328 { "dsbt_index", O_dsbt_index },
1331 #define O_dpr_got O_md3
1332 { "dpr_got", O_dpr_got },
1333 #define O_dpr_byte O_md4
1334 { "dpr_byte", O_dpr_byte },
1335 #define O_dpr_hword O_md5
1336 { "dpr_hword", O_dpr_hword },
1337 #define O_dpr_word O_md6
1338 { "dpr_word", O_dpr_word },
1341 /* Parse a name in some machine-specific way. Used on C6X to handle
1342 assembler operators. */
1345 tic6x_parse_name (const char *name, expressionS *exprP,
1346 enum expr_mode mode ATTRIBUTE_UNUSED, char *nextchar)
1348 char *p = input_line_pointer;
1349 char c, *name_start, *name_end;
1350 const char *inner_name;
1352 operatorT op = O_illegal;
1358 for (i = 0; i < ARRAY_SIZE (tic6x_operators); i++)
1359 if (strcasecmp (name + 1, tic6x_operators[i].name) == 0)
1361 op = tic6x_operators[i].op;
1365 if (op == O_illegal)
1368 *input_line_pointer = *nextchar;
1369 skip_whitespace (p);
1373 *input_line_pointer = 0;
1377 skip_whitespace (p);
1379 if (!is_name_beginner (*p))
1381 *input_line_pointer = 0;
1387 while (is_part_of_name (*p))
1390 skip_whitespace (p);
1394 *input_line_pointer = 0;
1398 input_line_pointer = p + 1;
1399 *nextchar = *input_line_pointer;
1400 *input_line_pointer = 0;
1404 inner_name = name_start;
1405 if (op == O_dsbt_index && strcmp (inner_name, "__c6xabi_DSBT_BASE") != 0)
1407 as_bad (_("$DSBT_INDEX must be used with __c6xabi_DSBT_BASE"));
1408 inner_name = "__c6xabi_DSBT_BASE";
1410 sym = symbol_find_or_make (inner_name);
1414 exprP->X_add_symbol = sym;
1415 exprP->X_add_number = 0;
1416 exprP->X_op_symbol = NULL;
1422 /* Create a fixup for an expression. Same arguments as fix_new_exp,
1423 plus FIX_ADDA which is TRUE for ADDA instructions (to indicate that
1424 fixes resolving to constants should have those constants implicitly
1425 shifted) and FALSE otherwise, but look for C6X-specific expression
1426 types and adjust the relocations or give errors accordingly. */
1429 tic6x_fix_new_exp (fragS *frag, int where, int size, expressionS *exp,
1430 int pcrel, bfd_reloc_code_real_type r_type,
1431 bfd_boolean fix_adda)
1433 bfd_reloc_code_real_type new_reloc = BFD_RELOC_UNUSED;
1441 case BFD_RELOC_C6000_SBR_U15_W:
1442 new_reloc = BFD_RELOC_C6000_DSBT_INDEX;
1446 as_bad (_("$DSBT_INDEX not supported in this context"));
1454 case BFD_RELOC_C6000_SBR_U15_W:
1455 new_reloc = BFD_RELOC_C6000_SBR_GOT_U15_W;
1459 as_bad (_("$GOT not supported in this context"));
1467 case BFD_RELOC_C6000_ABS_L16:
1468 new_reloc = BFD_RELOC_C6000_SBR_GOT_L16_W;
1471 case BFD_RELOC_C6000_ABS_H16:
1472 new_reloc = BFD_RELOC_C6000_SBR_GOT_H16_W;
1476 as_bad (_("$DPR_GOT not supported in this context"));
1484 case BFD_RELOC_C6000_ABS_S16:
1485 new_reloc = BFD_RELOC_C6000_SBR_S16;
1488 case BFD_RELOC_C6000_ABS_L16:
1489 new_reloc = BFD_RELOC_C6000_SBR_L16_B;
1492 case BFD_RELOC_C6000_ABS_H16:
1493 new_reloc = BFD_RELOC_C6000_SBR_H16_B;
1497 as_bad (_("$DPR_BYTE not supported in this context"));
1505 case BFD_RELOC_C6000_ABS_L16:
1506 new_reloc = BFD_RELOC_C6000_SBR_L16_H;
1509 case BFD_RELOC_C6000_ABS_H16:
1510 new_reloc = BFD_RELOC_C6000_SBR_H16_H;
1514 as_bad (_("$DPR_HWORD not supported in this context"));
1522 case BFD_RELOC_C6000_ABS_L16:
1523 new_reloc = BFD_RELOC_C6000_SBR_L16_W;
1526 case BFD_RELOC_C6000_ABS_H16:
1527 new_reloc = BFD_RELOC_C6000_SBR_H16_W;
1531 as_bad (_("$DPR_WORD not supported in this context"));
1542 as_bad (_("invalid PC-relative operand"));
1548 if (new_reloc == BFD_RELOC_UNUSED)
1549 fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
1551 fix = fix_new (frag, where, size, exp->X_add_symbol, exp->X_add_number,
1553 fix->tc_fix_data.fix_adda = fix_adda;
1556 /* Generate a fix for a constant (.word etc.). Needed to ensure these
1557 go through the error checking in tic6x_fix_new_exp. */
1560 tic6x_cons_fix_new (fragS *frag, int where, int size, expressionS *exp)
1562 bfd_reloc_code_real_type r_type;
1567 r_type = BFD_RELOC_8;
1571 r_type = BFD_RELOC_16;
1575 r_type = BFD_RELOC_32;
1579 as_bad (_("no %d-byte relocations available"), size);
1583 tic6x_fix_new_exp (frag, where, size, exp, 0, r_type, FALSE);
1586 /* Initialize target-specific fix data. */
1589 tic6x_init_fix_data (fixS *fixP)
1591 fixP->tc_fix_data.fix_adda = FALSE;
1594 /* Return true if the fix can be handled by GAS, false if it must
1595 be passed through to the linker. */
1598 tic6x_fix_adjustable (fixS *fixP)
1600 switch (fixP->fx_r_type)
1602 /* Adjust_reloc_syms doesn't know about the GOT. */
1603 case BFD_RELOC_C6000_SBR_GOT_U15_W:
1604 case BFD_RELOC_C6000_SBR_GOT_H16_W:
1605 case BFD_RELOC_C6000_SBR_GOT_L16_W:
1613 /* Given the fine-grained form of an operand, return the coarse
1617 tic6x_coarse_operand_form (tic6x_operand_form form)
1621 case tic6x_operand_asm_const:
1622 case tic6x_operand_link_const:
1623 return TIC6X_OP_EXP;
1625 case tic6x_operand_reg:
1626 case tic6x_operand_xreg:
1627 case tic6x_operand_dreg:
1628 case tic6x_operand_areg:
1629 case tic6x_operand_retreg:
1630 return TIC6X_OP_REG;
1632 case tic6x_operand_regpair:
1633 case tic6x_operand_xregpair:
1634 case tic6x_operand_dregpair:
1635 return TIC6X_OP_REGPAIR;
1637 case tic6x_operand_irp:
1638 return TIC6X_OP_IRP;
1640 case tic6x_operand_nrp:
1641 return TIC6X_OP_NRP;
1643 case tic6x_operand_ctrl:
1644 return TIC6X_OP_CTRL;
1646 case tic6x_operand_mem_short:
1647 case tic6x_operand_mem_long:
1648 case tic6x_operand_mem_deref:
1649 return TIC6X_OP_MEM_NOUNREG;
1651 case tic6x_operand_mem_ndw:
1652 return TIC6X_OP_MEM_UNREG;
1654 case tic6x_operand_func_unit:
1655 return TIC6X_OP_FUNC_UNIT;
1662 /* How an operand may match or not match a desired form. If different
1663 instruction alternatives fail in different ways, the first failure
1664 in this list determines the diagnostic. */
1668 tic6x_match_matches,
1669 /* Bad coarse form. */
1672 tic6x_match_non_const,
1673 /* Register on wrong side. */
1674 tic6x_match_wrong_side,
1675 /* Not a valid address register. */
1676 tic6x_match_bad_address,
1677 /* Not a valid return address register. */
1678 tic6x_match_bad_return,
1679 /* Control register not readable. */
1680 tic6x_match_ctrl_write_only,
1681 /* Control register not writable. */
1682 tic6x_match_ctrl_read_only,
1683 /* Not a valid memory reference for this instruction. */
1685 } tic6x_operand_match;
1687 /* Return whether an operand matches the given fine-grained form and
1688 read/write usage, and, if it does not match, how it fails to match.
1689 The main functional unit side is SIDE; the cross-path side is CROSS
1690 (the same as SIDE if a cross path not used); the data side is
1692 static tic6x_operand_match
1693 tic6x_operand_matches_form (const tic6x_operand *op, tic6x_operand_form form,
1694 tic6x_rw rw, unsigned int side, unsigned int cross,
1695 unsigned int data_side)
1697 unsigned int coarse = tic6x_coarse_operand_form (form);
1699 if (coarse != op->form)
1700 return tic6x_match_coarse;
1704 case tic6x_operand_asm_const:
1705 if (op->value.exp.X_op == O_constant)
1706 return tic6x_match_matches;
1708 return tic6x_match_non_const;
1710 case tic6x_operand_link_const:
1711 case tic6x_operand_irp:
1712 case tic6x_operand_nrp:
1713 case tic6x_operand_func_unit:
1714 /* All expressions are link-time constants, although there may
1715 not be relocations to express them in the output file. "irp"
1716 and "nrp" are unique operand values. All parsed functional
1717 unit names are valid. */
1718 return tic6x_match_matches;
1720 case tic6x_operand_reg:
1721 case tic6x_operand_regpair:
1722 if (op->value.reg.side == side)
1723 return tic6x_match_matches;
1725 return tic6x_match_wrong_side;
1727 case tic6x_operand_xreg:
1728 case tic6x_operand_xregpair:
1729 if (op->value.reg.side == cross)
1730 return tic6x_match_matches;
1732 return tic6x_match_wrong_side;
1734 case tic6x_operand_dreg:
1735 case tic6x_operand_dregpair:
1736 if (op->value.reg.side == data_side)
1737 return tic6x_match_matches;
1739 return tic6x_match_wrong_side;
1741 case tic6x_operand_areg:
1742 if (op->value.reg.side != cross)
1743 return tic6x_match_wrong_side;
1744 else if (op->value.reg.side == 2
1745 && (op->value.reg.num == 14 || op->value.reg.num == 15))
1746 return tic6x_match_matches;
1748 return tic6x_match_bad_address;
1750 case tic6x_operand_retreg:
1751 if (op->value.reg.side != side)
1752 return tic6x_match_wrong_side;
1753 else if (op->value.reg.num != 3)
1754 return tic6x_match_bad_return;
1756 return tic6x_match_matches;
1758 case tic6x_operand_ctrl:
1762 if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read
1763 || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
1764 return tic6x_match_matches;
1766 return tic6x_match_ctrl_write_only;
1768 case tic6x_rw_write:
1769 if (tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_write
1770 || tic6x_ctrl_table[op->value.ctrl].rw == tic6x_rw_read_write)
1771 return tic6x_match_matches;
1773 return tic6x_match_ctrl_read_only;
1779 case tic6x_operand_mem_deref:
1780 if (op->value.mem.mod != tic6x_mem_mod_none)
1781 return tic6x_match_bad_mem;
1782 else if (op->value.mem.scaled != tic6x_offset_none)
1784 else if (op->value.mem.base_reg.side != side)
1785 return tic6x_match_bad_mem;
1787 return tic6x_match_matches;
1789 case tic6x_operand_mem_short:
1790 case tic6x_operand_mem_ndw:
1791 if (op->value.mem.base_reg.side != side)
1792 return tic6x_match_bad_mem;
1793 if (op->value.mem.mod == tic6x_mem_mod_none)
1795 if (op->value.mem.scaled != tic6x_offset_none)
1797 return tic6x_match_matches;
1799 if (op->value.mem.scaled == tic6x_offset_none)
1801 if (op->value.mem.mod == tic6x_mem_mod_plus
1802 || op->value.mem.mod == tic6x_mem_mod_minus)
1804 return tic6x_match_matches;
1806 if (op->value.mem.offset_is_reg)
1808 if (op->value.mem.scaled == tic6x_offset_unscaled
1809 && form != tic6x_operand_mem_ndw)
1811 if (op->value.mem.offset.reg.side == side)
1812 return tic6x_match_matches;
1814 return tic6x_match_bad_mem;
1818 if (op->value.mem.offset.exp.X_op == O_constant)
1819 return tic6x_match_matches;
1821 return tic6x_match_bad_mem;
1824 case tic6x_operand_mem_long:
1825 if (op->value.mem.base_reg.side == 2
1826 && (op->value.mem.base_reg.num == 14
1827 || op->value.mem.base_reg.num == 15))
1829 switch (op->value.mem.mod)
1831 case tic6x_mem_mod_none:
1832 if (op->value.mem.scaled != tic6x_offset_none)
1834 return tic6x_match_matches;
1836 case tic6x_mem_mod_plus:
1837 if (op->value.mem.scaled == tic6x_offset_none)
1839 if (op->value.mem.offset_is_reg)
1840 return tic6x_match_bad_mem;
1841 else if (op->value.mem.scaled == tic6x_offset_scaled
1842 && op->value.mem.offset.exp.X_op != O_constant)
1843 return tic6x_match_bad_mem;
1845 return tic6x_match_matches;
1847 case tic6x_mem_mod_minus:
1848 case tic6x_mem_mod_preinc:
1849 case tic6x_mem_mod_predec:
1850 case tic6x_mem_mod_postinc:
1851 case tic6x_mem_mod_postdec:
1852 return tic6x_match_bad_mem;
1860 return tic6x_match_bad_mem;
1867 /* Return the number of bits shift used with DP-relative coding method
1871 tic6x_dpr_shift (tic6x_coding_method coding)
1875 case tic6x_coding_ulcst_dpr_byte:
1878 case tic6x_coding_ulcst_dpr_half:
1881 case tic6x_coding_ulcst_dpr_word:
1889 /* Return the relocation used with DP-relative coding method
1892 static bfd_reloc_code_real_type
1893 tic6x_dpr_reloc (tic6x_coding_method coding)
1897 case tic6x_coding_ulcst_dpr_byte:
1898 return BFD_RELOC_C6000_SBR_U15_B;
1900 case tic6x_coding_ulcst_dpr_half:
1901 return BFD_RELOC_C6000_SBR_U15_H;
1903 case tic6x_coding_ulcst_dpr_word:
1904 return BFD_RELOC_C6000_SBR_U15_W;
1911 /* Given a memory reference *MEM_REF as originally parsed, fill in
1912 defaults for missing offsets. */
1915 tic6x_default_mem_ref (tic6x_mem_ref *mem_ref)
1917 switch (mem_ref->mod)
1919 case tic6x_mem_mod_none:
1920 if (mem_ref->scaled != tic6x_offset_none)
1922 mem_ref->mod = tic6x_mem_mod_plus;
1923 mem_ref->scaled = tic6x_offset_unscaled;
1924 mem_ref->offset_is_reg = FALSE;
1925 memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
1926 mem_ref->offset.exp.X_op = O_constant;
1927 mem_ref->offset.exp.X_add_number = 0;
1928 mem_ref->offset.exp.X_unsigned = 0;
1931 case tic6x_mem_mod_plus:
1932 case tic6x_mem_mod_minus:
1933 if (mem_ref->scaled == tic6x_offset_none)
1937 case tic6x_mem_mod_preinc:
1938 case tic6x_mem_mod_predec:
1939 case tic6x_mem_mod_postinc:
1940 case tic6x_mem_mod_postdec:
1941 if (mem_ref->scaled != tic6x_offset_none)
1943 mem_ref->scaled = tic6x_offset_scaled;
1944 mem_ref->offset_is_reg = FALSE;
1945 memset (&mem_ref->offset.exp, 0, sizeof mem_ref->offset.exp);
1946 mem_ref->offset.exp.X_op = O_constant;
1947 mem_ref->offset.exp.X_add_number = 1;
1948 mem_ref->offset.exp.X_unsigned = 0;
1956 /* Return the encoding in the 8-bit field of an SPMASK or SPMASKR
1957 instruction of the specified UNIT, side SIDE. */
1960 tic6x_encode_spmask (tic6x_func_unit_base unit, unsigned int side)
1964 case tic6x_func_unit_l:
1965 return 1 << (side - 1);
1967 case tic6x_func_unit_s:
1968 return 1 << (side + 1);
1970 case tic6x_func_unit_d:
1971 return 1 << (side + 3);
1973 case tic6x_func_unit_m:
1974 return 1 << (side + 5);
1981 /* Try to encode the instruction with opcode number ID and operands
1982 OPERANDS (number NUM_OPERANDS), creg value THIS_LINE_CREG and z
1983 value THIS_LINE_Z; FUNC_UNIT_SIDE, FUNC_UNIT_CROSS and
1984 FUNC_UNIT_DATA_SIDE describe the functional unit specification;
1985 SPLOOP_II is the ii value from the previous SPLOOP-family
1986 instruction, or 0 if not in such a loop; the only possible problems
1987 are operands being out of range (they already match the
1988 fine-grained form), and inappropriate predication. If this
1989 succeeds, return the encoding and set *OK to TRUE; otherwise return
1990 0 and set *OK to FALSE. If a fix is needed, set *FIX_NEEDED to
1991 true and fill in *FIX_EXP, *FIX_PCREL, *FX_R_TYPE and *FIX_ADDA.
1992 Print error messages for failure if PRINT_ERRORS is TRUE; the
1993 opcode starts at STR and has length OPC_LEN. */
1996 tic6x_try_encode (tic6x_opcode_id id, tic6x_operand *operands,
1997 unsigned int num_operands, unsigned int this_line_creg,
1998 unsigned int this_line_z, unsigned int func_unit_side,
1999 unsigned int func_unit_cross,
2000 unsigned int func_unit_data_side, int sploop_ii,
2001 expressionS **fix_exp, int *fix_pcrel,
2002 bfd_reloc_code_real_type *fx_r_type, bfd_boolean *fix_adda,
2003 bfd_boolean *fix_needed, bfd_boolean *ok,
2004 bfd_boolean print_errors, char *str, int opc_len)
2006 const tic6x_opcode *opct;
2007 const tic6x_insn_format *fmt;
2008 unsigned int opcode_value;
2011 opct = &tic6x_opcode_table[id];
2012 fmt = &tic6x_insn_format_table[opct->format];
2013 opcode_value = fmt->cst_bits;
2015 for (fld = 0; fld < opct->num_fixed_fields; fld++)
2017 if (opct->fixed_fields[fld].min_val == opct->fixed_fields[fld].max_val)
2019 const tic6x_insn_field *fldd;
2020 fldd = tic6x_field_from_fmt (fmt, opct->fixed_fields[fld].field_id);
2023 opcode_value |= opct->fixed_fields[fld].min_val << fldd->low_pos;
2027 for (fld = 0; fld < opct->num_variable_fields; fld++)
2029 const tic6x_insn_field *fldd;
2035 unsigned int fcyc_bits;
2040 fldd = tic6x_field_from_fmt (fmt, opct->variable_fields[fld].field_id);
2043 opno = opct->variable_fields[fld].operand_num;
2044 switch (opct->variable_fields[fld].coding_method)
2046 case tic6x_coding_ucst:
2047 if (operands[opno].form != TIC6X_OP_EXP)
2049 if (operands[opno].value.exp.X_op != O_constant)
2051 ucexp = operands[opno].value.exp;
2053 if (ucexp.X_add_number < 0
2054 || ucexp.X_add_number >= (1 << fldd->width))
2057 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2062 value = ucexp.X_add_number;
2065 case tic6x_coding_scst:
2066 if (operands[opno].form != TIC6X_OP_EXP)
2068 if (operands[opno].value.exp.X_op != O_constant)
2071 /* Opcode table should not permit non-constants without
2072 a known relocation for them. */
2073 if (fldd->low_pos != 7 || fldd->width != 16)
2076 *fix_exp = &operands[opno].value.exp;
2078 *fx_r_type = BFD_RELOC_C6000_ABS_S16;
2082 sign_value = SEXT (operands[opno].value.exp.X_add_number);
2084 if (sign_value < -(1 << (fldd->width - 1))
2085 || (sign_value >= (1 << (fldd->width - 1))))
2088 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2093 value = sign_value + (1 << (fldd->width - 1));
2094 value ^= (1 << (fldd->width - 1));
2097 case tic6x_coding_ucst_minus_one:
2098 if (operands[opno].form != TIC6X_OP_EXP)
2100 if (operands[opno].value.exp.X_op != O_constant)
2102 if (operands[opno].value.exp.X_add_number <= 0
2103 || operands[opno].value.exp.X_add_number > (1 << fldd->width))
2106 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2111 value = operands[opno].value.exp.X_add_number - 1;
2114 case tic6x_coding_scst_negate:
2115 if (operands[opno].form != TIC6X_OP_EXP)
2117 if (operands[opno].value.exp.X_op != O_constant)
2119 sign_value = SEXT (-operands[opno].value.exp.X_add_number);
2120 goto signed_constant;
2122 case tic6x_coding_ulcst_dpr_byte:
2123 case tic6x_coding_ulcst_dpr_half:
2124 case tic6x_coding_ulcst_dpr_word:
2125 bits = tic6x_dpr_shift (opct->variable_fields[fld].coding_method);
2126 switch (operands[opno].form)
2129 if (operands[opno].value.exp.X_op == O_constant)
2131 ucexp = operands[opno].value.exp;
2132 goto unsigned_constant;
2134 expp = &operands[opno].value.exp;
2137 case TIC6X_OP_MEM_NOUNREG:
2138 mem = operands[opno].value.mem;
2139 tic6x_default_mem_ref (&mem);
2140 if (mem.offset_is_reg)
2142 if (mem.offset.exp.X_op == O_constant)
2144 ucexp = mem.offset.exp;
2145 if (mem.scaled == tic6x_offset_unscaled)
2147 if (ucexp.X_add_number & ((1 << bits) - 1))
2150 as_bad (_("offset in operand %u of '%.*s' not "
2151 "divisible by %u"), opno + 1, opc_len,
2156 ucexp.X_add_number >>= bits;
2158 goto unsigned_constant;
2160 if (mem.scaled != tic6x_offset_unscaled)
2162 if (operands[opno].value.mem.mod == tic6x_mem_mod_none
2163 || operands[opno].value.mem.scaled != tic6x_offset_unscaled
2164 || operands[opno].value.mem.offset_is_reg)
2166 expp = &operands[opno].value.mem.offset.exp;
2173 /* Opcode table should not use this encoding without a known
2175 if (fldd->low_pos != 8 || fldd->width != 15)
2177 /* We do not check for offset divisibility here; such a
2178 check is not needed at this point to encode the value,
2179 and if there is eventually a problem it will be detected
2180 either in md_apply_fix or at link time. */
2185 = tic6x_dpr_reloc (opct->variable_fields[fld].coding_method);
2186 if (operands[opno].form == TIC6X_OP_EXP)
2192 case tic6x_coding_lcst_low16:
2193 if (operands[opno].form != TIC6X_OP_EXP)
2195 if (operands[opno].value.exp.X_op == O_constant)
2196 value = operands[opno].value.exp.X_add_number & 0xffff;
2200 /* Opcode table should not use this encoding without a
2201 known relocation. */
2202 if (fldd->low_pos != 7 || fldd->width != 16)
2205 *fix_exp = &operands[opno].value.exp;
2207 *fx_r_type = BFD_RELOC_C6000_ABS_L16;
2212 case tic6x_coding_lcst_high16:
2213 if (operands[opno].form != TIC6X_OP_EXP)
2215 if (operands[opno].value.exp.X_op == O_constant)
2216 value = (operands[opno].value.exp.X_add_number >> 16) & 0xffff;
2220 /* Opcode table should not use this encoding without a
2221 known relocation. */
2222 if (fldd->low_pos != 7 || fldd->width != 16)
2225 *fix_exp = &operands[opno].value.exp;
2227 *fx_r_type = BFD_RELOC_C6000_ABS_H16;
2232 case tic6x_coding_pcrel:
2233 case tic6x_coding_pcrel_half:
2234 if (operands[opno].form != TIC6X_OP_EXP)
2238 *fix_exp = &operands[opno].value.exp;
2240 if (fldd->low_pos == 7 && fldd->width == 21)
2241 *fx_r_type = BFD_RELOC_C6000_PCR_S21;
2242 else if (fldd->low_pos == 16 && fldd->width == 12)
2243 *fx_r_type = BFD_RELOC_C6000_PCR_S12;
2244 else if (fldd->low_pos == 13 && fldd->width == 10)
2245 *fx_r_type = BFD_RELOC_C6000_PCR_S10;
2246 else if (fldd->low_pos == 16 && fldd->width == 7)
2247 *fx_r_type = BFD_RELOC_C6000_PCR_S7;
2249 /* Opcode table should not use this encoding without a
2250 known relocation. */
2255 case tic6x_coding_reg:
2256 switch (operands[opno].form)
2259 case TIC6X_OP_REGPAIR:
2260 value = operands[opno].value.reg.num;
2263 case TIC6X_OP_MEM_NOUNREG:
2264 case TIC6X_OP_MEM_UNREG:
2265 value = operands[opno].value.mem.base_reg.num;
2273 case tic6x_coding_areg:
2274 switch (operands[opno].form)
2277 value = (operands[opno].value.reg.num == 15 ? 1 : 0);
2280 case TIC6X_OP_MEM_NOUNREG:
2281 value = (operands[opno].value.mem.base_reg.num == 15 ? 1 : 0);
2289 case tic6x_coding_crlo:
2290 if (operands[opno].form != TIC6X_OP_CTRL)
2292 value = tic6x_ctrl_table[operands[opno].value.ctrl].crlo;
2295 case tic6x_coding_crhi:
2296 if (operands[opno].form != TIC6X_OP_CTRL)
2301 case tic6x_coding_reg_shift:
2302 if (operands[opno].form != TIC6X_OP_REGPAIR)
2304 value = operands[opno].value.reg.num >> 1;
2307 case tic6x_coding_mem_offset:
2308 if (operands[opno].form != TIC6X_OP_MEM_NOUNREG)
2310 mem = operands[opno].value.mem;
2311 tic6x_default_mem_ref (&mem);
2312 if (mem.offset_is_reg)
2314 if (mem.scaled != tic6x_offset_scaled)
2316 value = mem.offset.reg.num;
2322 if (mem.offset.exp.X_op != O_constant)
2326 case tic6x_offset_scaled:
2330 case tic6x_offset_unscaled:
2331 scale = opct->operand_info[opno].size;
2332 if (scale != 1 && scale != 2 && scale != 4 && scale != 8)
2339 if (mem.offset.exp.X_add_number < 0
2340 || mem.offset.exp.X_add_number >= (1 << fldd->width) * scale)
2343 as_bad (_("offset in operand %u of '%.*s' out of range"),
2344 opno + 1, opc_len, str);
2348 if (mem.offset.exp.X_add_number % scale)
2351 as_bad (_("offset in operand %u of '%.*s' not "
2353 opno + 1, opc_len, str, scale);
2357 value = mem.offset.exp.X_add_number / scale;
2361 case tic6x_coding_mem_offset_noscale:
2362 if (operands[opno].form != TIC6X_OP_MEM_UNREG)
2364 mem = operands[opno].value.mem;
2365 tic6x_default_mem_ref (&mem);
2366 if (mem.offset_is_reg)
2367 value = mem.offset.reg.num;
2370 if (mem.offset.exp.X_op != O_constant)
2372 if (mem.offset.exp.X_add_number < 0
2373 || mem.offset.exp.X_add_number >= (1 << fldd->width))
2376 as_bad (_("offset in operand %u of '%.*s' out of range"),
2377 opno + 1, opc_len, str);
2381 value = mem.offset.exp.X_add_number;
2385 case tic6x_coding_mem_mode:
2386 if (operands[opno].form != TIC6X_OP_MEM_NOUNREG
2387 && operands[opno].form != TIC6X_OP_MEM_UNREG)
2389 mem = operands[opno].value.mem;
2390 tic6x_default_mem_ref (&mem);
2393 case tic6x_mem_mod_plus:
2397 case tic6x_mem_mod_minus:
2401 case tic6x_mem_mod_preinc:
2405 case tic6x_mem_mod_predec:
2409 case tic6x_mem_mod_postinc:
2413 case tic6x_mem_mod_postdec:
2420 value += (mem.offset_is_reg ? 4 : 0);
2423 case tic6x_coding_scaled:
2424 if (operands[opno].form != TIC6X_OP_MEM_UNREG)
2426 mem = operands[opno].value.mem;
2427 tic6x_default_mem_ref (&mem);
2430 case tic6x_offset_unscaled:
2434 case tic6x_offset_scaled:
2443 case tic6x_coding_spmask:
2444 /* The position of such a field is hardcoded in the handling
2446 if (fldd->low_pos != 18)
2449 for (opno = 0; opno < num_operands; opno++)
2453 v = tic6x_encode_spmask (operands[opno].value.func_unit.base,
2454 operands[opno].value.func_unit.side);
2458 as_bad (_("functional unit already masked for operand "
2459 "%u of '%.*s'"), opno + 1, opc_len, str);
2467 case tic6x_coding_reg_unused:
2468 /* This is a placeholder; correct handling goes along with
2469 resource constraint checks. */
2473 case tic6x_coding_fstg:
2474 case tic6x_coding_fcyc:
2475 if (operands[opno].form != TIC6X_OP_EXP)
2477 if (operands[opno].value.exp.X_op != O_constant)
2482 as_bad (_("'%.*s' instruction not in a software "
2491 else if (sploop_ii <= 2)
2493 else if (sploop_ii <= 4)
2495 else if (sploop_ii <= 8)
2497 else if (sploop_ii <= 14)
2501 if (fcyc_bits > fldd->width)
2504 if (opct->variable_fields[fld].coding_method == tic6x_coding_fstg)
2506 if (operands[opno].value.exp.X_add_number < 0
2507 || (operands[opno].value.exp.X_add_number
2508 >= (1 << (fldd->width - fcyc_bits))))
2511 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2516 value = operands[opno].value.exp.X_add_number << fcyc_bits;
2520 if (operands[opno].value.exp.X_add_number < 0
2521 || (operands[opno].value.exp.X_add_number >= sploop_ii))
2524 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2529 value = operands[opno].value.exp.X_add_number;
2533 case tic6x_coding_fu:
2534 value = func_unit_side == 2 ? 1 : 0;
2537 case tic6x_coding_data_fu:
2538 value = func_unit_data_side == 2 ? 1 : 0;
2541 case tic6x_coding_xpath:
2542 value = func_unit_cross;
2549 for (ffld = 0; ffld < opct->num_fixed_fields; ffld++)
2550 if ((opct->fixed_fields[ffld].field_id
2551 == opct->variable_fields[fld].field_id)
2552 && (value < opct->fixed_fields[ffld].min_val
2553 || value > opct->fixed_fields[ffld].max_val))
2556 as_bad (_("operand %u of '%.*s' out of range"), opno + 1,
2562 opcode_value |= value << fldd->low_pos;
2567 const tic6x_insn_field *creg;
2568 const tic6x_insn_field *z;
2570 creg = tic6x_field_from_fmt (fmt, tic6x_field_creg);
2574 as_bad (_("instruction '%.*s' cannot be predicated"),
2579 z = tic6x_field_from_fmt (fmt, tic6x_field_z);
2580 /* If there is a creg field, there must be a z field; otherwise
2581 there is an error in the format table. */
2585 opcode_value |= this_line_creg << creg->low_pos;
2586 opcode_value |= this_line_z << z->low_pos;
2590 return opcode_value;
2593 /* Convert the target integer stored in N bytes in BUF to a host
2594 integer, returning that value. */
2597 md_chars_to_number (char *buf, int n)
2600 unsigned char *p = (unsigned char *) buf;
2602 if (target_big_endian)
2607 result |= (*p++ & 0xff);
2615 result |= (p[n] & 0xff);
2622 /* Assemble the instruction starting at STR (an opcode, with the
2623 opcode name all-lowercase). */
2626 md_assemble (char *str)
2630 bfd_boolean this_line_parallel;
2631 bfd_boolean this_line_spmask;
2632 unsigned int this_line_creg;
2633 unsigned int this_line_z;
2634 tic6x_label_list *this_insn_label_list;
2635 segment_info_type *seginfo;
2636 tic6x_opcode_list *opc_list, *opc;
2637 tic6x_func_unit_base func_unit_base = tic6x_func_unit_nfu;
2638 unsigned int func_unit_side = 0;
2639 unsigned int func_unit_cross = 0;
2640 unsigned int cross_side = 0;
2641 unsigned int func_unit_data_side = 0;
2642 unsigned int max_matching_opcodes, num_matching_opcodes;
2643 tic6x_opcode_id *opcm = NULL;
2644 unsigned int opc_rank[TIC6X_NUM_PREFER];
2645 const tic6x_opcode *opct = NULL;
2646 int min_rank, try_rank, max_rank;
2647 bfd_boolean num_operands_permitted[TIC6X_MAX_SOURCE_OPERANDS + 1]
2649 unsigned int operand_forms[TIC6X_MAX_SOURCE_OPERANDS] = { 0 };
2650 tic6x_operand operands[TIC6X_MAX_SOURCE_OPERANDS];
2651 unsigned int max_num_operands;
2652 unsigned int num_operands_read;
2653 bfd_boolean ok_this_arch, ok_this_fu, ok_this_arch_fu;
2654 bfd_boolean bad_operands = FALSE;
2655 unsigned int opcode_value;
2656 bfd_boolean encoded_ok;
2657 bfd_boolean fix_needed = FALSE;
2658 expressionS *fix_exp = NULL;
2660 bfd_reloc_code_real_type fx_r_type = BFD_RELOC_UNUSED;
2661 bfd_boolean fix_adda = FALSE;
2666 while (*p && !is_end_of_line[(unsigned char) *p] && *p != ' ')
2669 /* This function should only have been called when there is actually
2670 an instruction to assemble. */
2674 /* Now an instruction has been seen, architecture attributes from
2675 .arch directives merge with rather than overriding the previous
2677 tic6x_seen_insns = TRUE;
2678 /* If no .arch directives or -march options have been seen, we are
2679 assessing instruction validity based on the C674X default, so set
2680 the attribute accordingly. */
2681 if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
2682 tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
2684 /* Reset global settings for parallel bars and predicates now to
2685 avoid extra errors if there are problems with this opcode. */
2686 this_line_parallel = tic6x_line_parallel;
2687 this_line_spmask = tic6x_line_spmask;
2688 this_line_creg = tic6x_line_creg;
2689 this_line_z = tic6x_line_z;
2690 tic6x_line_parallel = FALSE;
2691 tic6x_line_spmask = FALSE;
2692 tic6x_line_creg = 0;
2694 seginfo = seg_info (now_seg);
2695 this_insn_label_list = seginfo->tc_segment_info_data.label_list;
2696 seginfo->tc_segment_info_data.label_list = NULL;
2698 opc_list = hash_find_n (opcode_hash, str, p - str);
2699 if (opc_list == NULL)
2703 as_bad (_("unknown opcode '%s'"), str);
2709 skip_whitespace (p);
2711 /* See if there is something that looks like a functional unit
2715 bfd_boolean good_func_unit;
2716 tic6x_func_unit_base maybe_base = tic6x_func_unit_nfu;
2717 unsigned int maybe_side = 0;
2718 unsigned int maybe_cross = 0;
2719 unsigned int maybe_data_side = 0;
2721 good_func_unit = tic6x_parse_func_unit_base (p + 1, &maybe_base,
2726 if (p[3] == ' ' || is_end_of_line[(unsigned char) p[3]])
2728 else if ((p[3] == 'x' || p[3] == 'X')
2729 && (p[4] == ' ' || is_end_of_line[(unsigned char) p[4]]))
2734 else if (maybe_base == tic6x_func_unit_d
2735 && (p[3] == 't' || p[3] == 'T')
2736 && (p[4] == '1' || p[4] == '2')
2737 && (p[5] == ' ' || is_end_of_line[(unsigned char) p[5]]))
2739 maybe_data_side = p[4] - '0';
2743 good_func_unit = FALSE;
2748 func_unit_base = maybe_base;
2749 func_unit_side = maybe_side;
2750 func_unit_cross = maybe_cross;
2751 cross_side = (func_unit_cross ? 3 - func_unit_side : func_unit_side);
2752 func_unit_data_side = maybe_data_side;
2755 skip_whitespace (p);
2758 /* Determine which entries in the opcode table match, and the
2759 associated permitted forms of operands. */
2760 max_matching_opcodes = 0;
2761 for (opc = opc_list; opc; opc = opc->next)
2762 max_matching_opcodes++;
2763 num_matching_opcodes = 0;
2764 opcm = xmalloc (max_matching_opcodes * sizeof (*opcm));
2765 max_num_operands = 0;
2766 ok_this_arch = FALSE;
2768 ok_this_arch_fu = FALSE;
2769 for (opc = opc_list; opc; opc = opc->next)
2771 unsigned int num_operands;
2773 bfd_boolean this_opc_arch_ok = TRUE;
2774 bfd_boolean this_opc_fu_ok = TRUE;
2776 if (tic6x_insn_format_table[tic6x_opcode_table[opc->id].format].num_bits
2779 if (!(tic6x_opcode_table[opc->id].isa_variants & tic6x_features))
2780 this_opc_arch_ok = FALSE;
2781 if (tic6x_opcode_table[opc->id].func_unit != func_unit_base)
2782 this_opc_fu_ok = FALSE;
2783 if (func_unit_side == 1
2784 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_B_ONLY))
2785 this_opc_fu_ok = FALSE;
2787 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_NO_CROSS))
2788 this_opc_fu_ok = FALSE;
2789 if (!func_unit_data_side
2790 && (tic6x_opcode_table[opc->id].flags
2791 & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
2792 this_opc_fu_ok = FALSE;
2793 if (func_unit_data_side
2794 && !(tic6x_opcode_table[opc->id].flags
2795 & (TIC6X_FLAG_LOAD | TIC6X_FLAG_STORE)))
2796 this_opc_fu_ok = FALSE;
2797 if (func_unit_data_side == 1
2798 && (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SIDE_T2_ONLY))
2799 this_opc_fu_ok = FALSE;
2800 if (this_opc_arch_ok)
2801 ok_this_arch = TRUE;
2804 if (!this_opc_arch_ok || !this_opc_fu_ok)
2806 ok_this_arch_fu = TRUE;
2807 opcm[num_matching_opcodes] = opc->id;
2808 num_matching_opcodes++;
2809 num_operands = tic6x_opcode_table[opc->id].num_operands;
2811 if (tic6x_opcode_table[opc->id].flags & TIC6X_FLAG_SPMASK)
2813 if (num_operands != 1
2814 || (tic6x_opcode_table[opc->id].operand_info[0].form
2815 != tic6x_operand_func_unit))
2818 for (i = 0; i < num_operands; i++)
2821 |= tic6x_coarse_operand_form (tic6x_operand_func_unit);
2822 num_operands_permitted[i] = TRUE;
2827 for (i = 0; i < num_operands; i++)
2829 tic6x_operand_form f
2830 = tic6x_opcode_table[opc->id].operand_info[i].form;
2832 operand_forms[i] |= tic6x_coarse_operand_form (f);
2835 num_operands_permitted[num_operands] = TRUE;
2836 if (num_operands > max_num_operands)
2837 max_num_operands = num_operands;
2842 as_bad (_("'%.*s' instruction not supported on this architecture"),
2850 as_bad (_("'%.*s' instruction not supported on this functional unit"),
2856 if (!ok_this_arch_fu)
2858 as_bad (_("'%.*s' instruction not supported on this functional unit"
2859 " for this architecture"),
2865 /* If there were no instructions matching the above availability
2866 checks, we should now have given an error and returned. */
2867 if (num_matching_opcodes == 0)
2870 num_operands_read = 0;
2873 skip_whitespace (p);
2874 if (is_end_of_line[(unsigned char) *p])
2876 if (num_operands_read > 0)
2878 as_bad (_("missing operand after comma"));
2879 bad_operands = TRUE;
2884 if (max_num_operands == 0)
2886 as_bad (_("too many operands to '%.*s'"), opc_len, str);
2887 bad_operands = TRUE;
2891 if (!tic6x_parse_operand (&p, &operands[num_operands_read],
2892 operand_forms[num_operands_read], str, opc_len,
2893 num_operands_read + 1))
2894 bad_operands = TRUE;
2895 num_operands_read++;
2897 if (is_end_of_line[(unsigned char) *p])
2902 if (num_operands_read == max_num_operands)
2904 as_bad (_("too many operands to '%.*s'"), opc_len, str);
2905 bad_operands = TRUE;
2911 /* Operand parsing should consume whole operands. */
2915 if (!bad_operands && !num_operands_permitted[num_operands_read])
2917 as_bad (_("bad number of operands to '%.*s'"), opc_len, str);
2918 bad_operands = TRUE;
2923 /* Each operand is of the right syntactic form for some opcode
2924 choice, and the number of operands is valid. Check that each
2925 operand is OK in detail for some opcode choice with the right
2926 number of operands. */
2929 for (i = 0; i < num_operands_read; i++)
2931 bfd_boolean coarse_ok = FALSE;
2932 bfd_boolean fine_ok = FALSE;
2933 tic6x_operand_match fine_failure = tic6x_match_matches;
2936 for (j = 0; j < num_matching_opcodes; j++)
2938 tic6x_operand_form f;
2941 tic6x_operand_match this_fine_failure;
2943 if (tic6x_opcode_table[opcm[j]].flags & TIC6X_FLAG_SPMASK)
2945 f = tic6x_operand_func_unit;
2950 if (tic6x_opcode_table[opcm[j]].num_operands
2951 != num_operands_read)
2954 f = tic6x_opcode_table[opcm[j]].operand_info[i].form;
2955 rw = tic6x_opcode_table[opcm[j]].operand_info[i].rw;
2957 cf = tic6x_coarse_operand_form (f);
2959 if (operands[i].form != cf)
2964 = tic6x_operand_matches_form (&operands[i], f, rw,
2967 func_unit_data_side);
2968 if (this_fine_failure == tic6x_match_matches)
2973 if (fine_failure == tic6x_match_matches
2974 || fine_failure > this_fine_failure)
2975 fine_failure = this_fine_failure;
2978 /* No instructions should have operand syntactic forms only
2979 acceptable with certain numbers of operands, so no
2980 diagnostic for this case. */
2986 switch (fine_failure)
2988 case tic6x_match_non_const:
2989 as_bad (_("operand %u of '%.*s' not constant"),
2990 i + 1, opc_len, str);
2993 case tic6x_match_wrong_side:
2994 as_bad (_("operand %u of '%.*s' on wrong side"),
2995 i + 1, opc_len, str);
2998 case tic6x_match_bad_return:
2999 as_bad (_("operand %u of '%.*s' not a valid return "
3000 "address register"),
3001 i + 1, opc_len, str);
3004 case tic6x_match_ctrl_write_only:
3005 as_bad (_("operand %u of '%.*s' is write-only"),
3006 i + 1, opc_len, str);
3009 case tic6x_match_ctrl_read_only:
3010 as_bad (_("operand %u of '%.*s' is read-only"),
3011 i + 1, opc_len, str);
3014 case tic6x_match_bad_mem:
3015 as_bad (_("operand %u of '%.*s' not a valid memory "
3017 i + 1, opc_len, str);
3020 case tic6x_match_bad_address:
3021 as_bad (_("operand %u of '%.*s' not a valid base "
3022 "address register"),
3023 i + 1, opc_len, str);
3029 bad_operands = TRUE;
3037 /* Each operand is OK for some opcode choice, and the number of
3038 operands is valid. Check whether there is an opcode choice
3039 for which all operands are simultaneously valid. */
3041 bfd_boolean found_match = FALSE;
3043 for (i = 0; i < TIC6X_NUM_PREFER; i++)
3044 opc_rank[i] = (unsigned int) -1;
3046 min_rank = TIC6X_NUM_PREFER - 1;
3049 for (i = 0; i < num_matching_opcodes; i++)
3052 bfd_boolean this_matches = TRUE;
3054 if (!(tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
3055 && tic6x_opcode_table[opcm[i]].num_operands != num_operands_read)
3058 for (j = 0; j < num_operands_read; j++)
3060 tic6x_operand_form f;
3063 if (tic6x_opcode_table[opcm[i]].flags & TIC6X_FLAG_SPMASK)
3065 f = tic6x_operand_func_unit;
3070 f = tic6x_opcode_table[opcm[i]].operand_info[j].form;
3071 rw = tic6x_opcode_table[opcm[i]].operand_info[j].rw;
3073 if (tic6x_operand_matches_form (&operands[j], f, rw,
3076 func_unit_data_side)
3077 != tic6x_match_matches)
3079 this_matches = FALSE;
3086 int rank = TIC6X_PREFER_VAL (tic6x_opcode_table[opcm[i]].flags);
3088 if (rank < min_rank)
3090 if (rank > max_rank)
3093 if (opc_rank[rank] == (unsigned int) -1)
3096 /* The opcode table should provide a total ordering
3097 for all cases where multiple matches may get
3107 as_bad (_("bad operand combination for '%.*s'"), opc_len, str);
3108 bad_operands = TRUE;
3120 for (try_rank = max_rank; try_rank >= min_rank; try_rank--)
3124 if (opc_rank[try_rank] == (unsigned int) -1)
3127 opcode_value = tic6x_try_encode (opcm[opc_rank[try_rank]], operands,
3128 num_operands_read, this_line_creg,
3129 this_line_z, func_unit_side,
3130 func_unit_cross, func_unit_data_side,
3131 seginfo->tc_segment_info_data.sploop_ii,
3132 &fix_exp, &fix_pcrel, &fx_r_type,
3133 &fix_adda, &fix_needed, &encoded_ok,
3134 (try_rank == min_rank ? TRUE : FALSE),
3138 opct = &tic6x_opcode_table[opcm[opc_rank[try_rank]]];
3148 if (this_line_parallel)
3150 insn_frag = seginfo->tc_segment_info_data.execute_packet_frag;
3151 if (insn_frag == NULL)
3153 as_bad (_("parallel instruction not following another instruction"));
3157 if (insn_frag->fr_fix >= 32)
3159 as_bad (_("too many instructions in execute packet"));
3163 if (this_insn_label_list != NULL)
3164 as_bad (_("label not at start of execute packet"));
3166 if (opct->flags & TIC6X_FLAG_FIRST)
3167 as_bad (_("'%.*s' instruction not at start of execute packet"),
3170 *seginfo->tc_segment_info_data.last_insn_lsb |= 0x1;
3171 output = insn_frag->fr_literal + insn_frag->fr_fix;
3175 tic6x_label_list *l;
3177 seginfo->tc_segment_info_data.spmask_addr = NULL;
3178 seginfo->tc_segment_info_data.func_units_used = 0;
3180 /* Start a new frag for this execute packet. */
3181 if (frag_now_fix () != 0)
3183 if (frag_now->fr_type != rs_machine_dependent)
3184 frag_wane (frag_now);
3189 insn_frag = seginfo->tc_segment_info_data.execute_packet_frag = frag_now;
3190 for (l = this_insn_label_list; l; l = l->next)
3192 symbol_set_frag (l->label, frag_now);
3193 S_SET_VALUE (l->label, 0);
3194 S_SET_SEGMENT (l->label, now_seg);
3196 tic6x_free_label_list (this_insn_label_list);
3197 dwarf2_emit_insn (0);
3198 output = frag_var (rs_machine_dependent, 32, 32, 0, NULL, 0, NULL);
3199 /* This must be the same as the frag to which a pointer was just
3201 if (output != insn_frag->fr_literal)
3203 insn_frag->tc_frag_data.is_insns = TRUE;
3204 insn_frag->tc_frag_data.can_cross_fp_boundary
3205 = tic6x_can_cross_fp_boundary;
3208 if (func_unit_base != tic6x_func_unit_nfu)
3210 unsigned int func_unit_enc;
3212 func_unit_enc = tic6x_encode_spmask (func_unit_base, func_unit_side);
3214 if (seginfo->tc_segment_info_data.func_units_used & func_unit_enc)
3215 as_bad (_("functional unit already used in this execute packet"));
3217 seginfo->tc_segment_info_data.func_units_used |= func_unit_enc;
3220 if (opct->flags & TIC6X_FLAG_SPLOOP)
3222 if (seginfo->tc_segment_info_data.sploop_ii)
3223 as_bad (_("nested software pipelined loop"));
3224 if (num_operands_read != 1
3225 || operands[0].form != TIC6X_OP_EXP
3226 || operands[0].value.exp.X_op != O_constant)
3228 seginfo->tc_segment_info_data.sploop_ii
3229 = operands[0].value.exp.X_add_number;
3231 else if (opct->flags & TIC6X_FLAG_SPKERNEL)
3233 if (!seginfo->tc_segment_info_data.sploop_ii)
3234 as_bad (_("'%.*s' instruction not in a software pipelined loop"),
3236 seginfo->tc_segment_info_data.sploop_ii = 0;
3239 if (this_line_spmask)
3241 if (seginfo->tc_segment_info_data.spmask_addr == NULL)
3242 as_bad (_("'||^' without previous SPMASK"));
3243 else if (func_unit_base == tic6x_func_unit_nfu)
3244 as_bad (_("cannot mask instruction using no functional unit"));
3247 unsigned int spmask_opcode;
3248 unsigned int mask_bit;
3251 = md_chars_to_number (seginfo->tc_segment_info_data.spmask_addr,
3253 mask_bit = tic6x_encode_spmask (func_unit_base, func_unit_side);
3255 if (spmask_opcode & mask_bit)
3256 as_bad (_("functional unit already masked"));
3257 spmask_opcode |= mask_bit;
3258 md_number_to_chars (seginfo->tc_segment_info_data.spmask_addr,
3263 record_alignment (now_seg, 5);
3264 md_number_to_chars (output, opcode_value, 4);
3266 tic6x_fix_new_exp (insn_frag, output - insn_frag->fr_literal, 4, fix_exp,
3267 fix_pcrel, fx_r_type, fix_adda);
3268 insn_frag->fr_fix += 4;
3269 insn_frag->fr_var -= 4;
3270 seginfo->tc_segment_info_data.last_insn_lsb
3271 = (target_big_endian ? output + 3 : output);
3272 if (opct->flags & TIC6X_FLAG_SPMASK)
3273 seginfo->tc_segment_info_data.spmask_addr = output;
3276 /* Modify NEWVAL (32-bit) by inserting VALUE, shifted right by SHIFT
3277 and the least significant BITS bits taken, at position POS. */
3278 #define MODIFY_VALUE(NEWVAL, VALUE, SHIFT, POS, BITS) \
3280 (NEWVAL) &= 0xffffffffU & ~(((1U << (BITS)) - 1) << (POS)); \
3281 (NEWVAL) |= (((VALUE) >> (SHIFT)) & ((1U << (BITS)) - 1)) << (POS); \
3284 /* Apply a fixup to the object file. */
3287 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
3289 offsetT value = *valP;
3290 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3292 value = SEXT (value);
3295 fixP->fx_offset = SEXT (fixP->fx_offset);
3297 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3300 /* We do our own overflow checks. */
3301 fixP->fx_no_overflow = 1;
3303 switch (fixP->fx_r_type)
3305 case BFD_RELOC_NONE:
3306 /* Force output to the object file. */
3311 if (fixP->fx_done || !seg->use_rela_p)
3312 md_number_to_chars (buf, value, 4);
3316 if (fixP->fx_done || !seg->use_rela_p)
3318 if (value < -0x8000 || value > 0xffff)
3319 as_bad_where (fixP->fx_file, fixP->fx_line,
3320 _("value too large for 2-byte field"));
3321 md_number_to_chars (buf, value, 2);
3326 if (fixP->fx_done || !seg->use_rela_p)
3328 if (value < -0x80 || value > 0xff)
3329 as_bad_where (fixP->fx_file, fixP->fx_line,
3330 _("value too large for 1-byte field"));
3331 md_number_to_chars (buf, value, 1);
3335 case BFD_RELOC_C6000_ABS_S16:
3336 case BFD_RELOC_C6000_ABS_L16:
3337 case BFD_RELOC_C6000_SBR_S16:
3338 case BFD_RELOC_C6000_SBR_L16_B:
3339 case BFD_RELOC_C6000_SBR_L16_H:
3340 case BFD_RELOC_C6000_SBR_L16_W:
3341 case BFD_RELOC_C6000_SBR_GOT_L16_W:
3342 if (fixP->fx_done || !seg->use_rela_p)
3344 offsetT newval = md_chars_to_number (buf, 4);
3347 switch (fixP->fx_r_type)
3349 case BFD_RELOC_C6000_SBR_L16_H:
3353 case BFD_RELOC_C6000_SBR_L16_W:
3354 case BFD_RELOC_C6000_SBR_GOT_L16_W:
3363 MODIFY_VALUE (newval, value, shift, 7, 16);
3364 if ((value < -0x8000 || value > 0x7fff)
3365 && (fixP->fx_r_type == BFD_RELOC_C6000_ABS_S16
3366 || fixP->fx_r_type == BFD_RELOC_C6000_SBR_S16))
3367 as_bad_where (fixP->fx_file, fixP->fx_line,
3368 _("immediate offset out of range"));
3370 md_number_to_chars (buf, newval, 4);
3373 && fixP->fx_r_type != BFD_RELOC_C6000_ABS_S16
3374 && fixP->fx_r_type != BFD_RELOC_C6000_ABS_L16)
3378 case BFD_RELOC_C6000_ABS_H16:
3379 case BFD_RELOC_C6000_SBR_H16_B:
3380 case BFD_RELOC_C6000_SBR_H16_H:
3381 case BFD_RELOC_C6000_SBR_H16_W:
3382 case BFD_RELOC_C6000_SBR_GOT_H16_W:
3383 if (fixP->fx_done || !seg->use_rela_p)
3385 offsetT newval = md_chars_to_number (buf, 4);
3388 switch (fixP->fx_r_type)
3390 case BFD_RELOC_C6000_SBR_H16_H:
3394 case BFD_RELOC_C6000_SBR_H16_W:
3395 case BFD_RELOC_C6000_SBR_GOT_H16_W:
3404 MODIFY_VALUE (newval, value, shift, 7, 16);
3406 md_number_to_chars (buf, newval, 4);
3408 if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_ABS_H16)
3412 case BFD_RELOC_C6000_SBR_U15_B:
3413 if (fixP->fx_done || !seg->use_rela_p)
3415 offsetT newval = md_chars_to_number (buf, 4);
3417 MODIFY_VALUE (newval, value, 0, 8, 15);
3418 if (value < 0 || value > 0x7fff)
3419 as_bad_where (fixP->fx_file, fixP->fx_line,
3420 _("immediate offset out of range"));
3422 md_number_to_chars (buf, newval, 4);
3426 case BFD_RELOC_C6000_SBR_U15_H:
3427 if (fixP->fx_done || !seg->use_rela_p)
3429 offsetT newval = md_chars_to_number (buf, 4);
3431 /* Constant ADDA operands, processed as constant when the
3432 instruction is parsed, are encoded as-is rather than
3433 shifted. If the operand of an ADDA instruction is now
3434 constant (for example, the difference between two labels
3435 found after the instruction), ensure it is encoded the
3436 same way it would have been if the constant value had
3437 been known when the instruction was parsed. */
3438 if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
3441 MODIFY_VALUE (newval, value, 1, 8, 15);
3443 as_bad_where (fixP->fx_file, fixP->fx_line,
3444 _("immediate offset not 2-byte-aligned"));
3445 if (value < 0 || value > 0xfffe)
3446 as_bad_where (fixP->fx_file, fixP->fx_line,
3447 _("immediate offset out of range"));
3449 md_number_to_chars (buf, newval, 4);
3453 case BFD_RELOC_C6000_SBR_U15_W:
3454 case BFD_RELOC_C6000_SBR_GOT_U15_W:
3455 if (fixP->fx_done || !seg->use_rela_p)
3457 offsetT newval = md_chars_to_number (buf, 4);
3459 /* Constant ADDA operands, processed as constant when the
3460 instruction is parsed, are encoded as-is rather than
3461 shifted. If the operand of an ADDA instruction is now
3462 constant (for example, the difference between two labels
3463 found after the instruction), ensure it is encoded the
3464 same way it would have been if the constant value had
3465 been known when the instruction was parsed. */
3466 if (fixP->tc_fix_data.fix_adda && fixP->fx_done)
3469 MODIFY_VALUE (newval, value, 2, 8, 15);
3471 as_bad_where (fixP->fx_file, fixP->fx_line,
3472 _("immediate offset not 4-byte-aligned"));
3473 if (value < 0 || value > 0x1fffc)
3474 as_bad_where (fixP->fx_file, fixP->fx_line,
3475 _("immediate offset out of range"));
3477 md_number_to_chars (buf, newval, 4);
3479 if (fixP->fx_done && fixP->fx_r_type != BFD_RELOC_C6000_SBR_U15_W)
3483 case BFD_RELOC_C6000_DSBT_INDEX:
3485 as_bad_where (fixP->fx_file, fixP->fx_line,
3486 _("addend used with $DSBT_INDEX"));
3491 case BFD_RELOC_C6000_PCR_S21:
3492 if (fixP->fx_done || !seg->use_rela_p)
3494 offsetT newval = md_chars_to_number (buf, 4);
3496 MODIFY_VALUE (newval, value, 2, 7, 21);
3499 as_bad_where (fixP->fx_file, fixP->fx_line,
3500 _("PC-relative offset not 4-byte-aligned"));
3501 if (value < -0x400000 || value > 0x3ffffc)
3502 as_bad_where (fixP->fx_file, fixP->fx_line,
3503 _("PC-relative offset out of range"));
3505 md_number_to_chars (buf, newval, 4);
3509 case BFD_RELOC_C6000_PCR_S12:
3510 if (fixP->fx_done || !seg->use_rela_p)
3512 offsetT newval = md_chars_to_number (buf, 4);
3514 MODIFY_VALUE (newval, value, 2, 16, 12);
3517 as_bad_where (fixP->fx_file, fixP->fx_line,
3518 _("PC-relative offset not 4-byte-aligned"));
3519 if (value < -0x2000 || value > 0x1ffc)
3520 as_bad_where (fixP->fx_file, fixP->fx_line,
3521 _("PC-relative offset out of range"));
3523 md_number_to_chars (buf, newval, 4);
3527 case BFD_RELOC_C6000_PCR_S10:
3528 if (fixP->fx_done || !seg->use_rela_p)
3530 offsetT newval = md_chars_to_number (buf, 4);
3532 MODIFY_VALUE (newval, value, 2, 13, 10);
3535 as_bad_where (fixP->fx_file, fixP->fx_line,
3536 _("PC-relative offset not 4-byte-aligned"));
3537 if (value < -0x800 || value > 0x7fc)
3538 as_bad_where (fixP->fx_file, fixP->fx_line,
3539 _("PC-relative offset out of range"));
3541 md_number_to_chars (buf, newval, 4);
3545 case BFD_RELOC_C6000_PCR_S7:
3546 if (fixP->fx_done || !seg->use_rela_p)
3548 offsetT newval = md_chars_to_number (buf, 4);
3550 MODIFY_VALUE (newval, value, 2, 16, 7);
3553 as_bad_where (fixP->fx_file, fixP->fx_line,
3554 _("PC-relative offset not 4-byte-aligned"));
3555 if (value < -0x100 || value > 0xfc)
3556 as_bad_where (fixP->fx_file, fixP->fx_line,
3557 _("PC-relative offset out of range"));
3559 md_number_to_chars (buf, newval, 4);
3568 /* Convert a floating-point number to target (IEEE) format. */
3571 md_atof (int type, char *litP, int *sizeP)
3573 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3576 /* Adjust the frags in SECTION (see tic6x_end). */
3579 tic6x_adjust_section (bfd *abfd ATTRIBUTE_UNUSED, segT section,
3580 void *dummy ATTRIBUTE_UNUSED)
3582 segment_info_type *info;
3585 bfd_boolean have_code = FALSE;
3586 bfd_boolean have_non_code = FALSE;
3588 info = seg_info (section);
3592 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3593 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3594 switch (fragp->fr_type)
3596 case rs_machine_dependent:
3597 if (fragp->tc_frag_data.is_insns)
3603 if (fragp->fr_fix > 0)
3604 have_non_code = TRUE;
3608 have_non_code = TRUE;
3612 /* Process alignment requirements in a code-only section. */
3613 if (have_code && !have_non_code)
3615 /* If we need to insert an odd number of instructions to meet an
3616 alignment requirement, there must have been an odd number of
3617 instructions since the last 8-byte-aligned execute packet
3618 boundary. So there must have been an execute packet with an
3619 odd number (and so a number fewer than 8) of instructions
3620 into which we can insert a NOP without breaking any previous
3623 If then we need to insert a number 2 mod 4 of instructions,
3624 the number of instructions since the last 16-byte-aligned
3625 execute packet boundary must be 2 mod 4. So between that
3626 boundary and the following 8-byte-aligned boundary there must
3627 either be at least one execute packet with 2-mod-4
3628 instructions, or at least two with an odd number of
3629 instructions; again, greedily inserting NOPs as soon as
3630 possible suffices to meet the alignment requirement.
3632 If then we need to insert 4 instructions, we look between the
3633 last 32-byte-aligned boundary and the following
3634 16-byte-aligned boundary. The sizes of the execute packets
3635 in this range total 4 instructions mod 8, so again there is
3636 room for greedy insertion of NOPs to meet the alignment
3637 requirement, and before any intermediate point with 8-byte
3638 (2-instruction) alignment requirement the sizes of execute
3639 packets (and so the room for NOPs) will total 2 instructions
3640 mod 4 so greedy insertion will not break such alignments.
3642 So we can always meet these alignment requirements by
3643 inserting NOPs in parallel with existing execute packets, and
3644 by induction the approach described above inserts the minimum
3645 number of such NOPs. */
3647 /* The number of NOPs we are currently looking to insert, if we
3648 have gone back to insert NOPs. */
3649 unsigned int want_insert = 0;
3651 /* Out of that number, the number inserted so far in the current
3652 stage of the above algorithm. */
3653 unsigned int want_insert_done_so_far = 0;
3655 /* The position mod 32 at the start of the current frag. */
3656 unsigned int pos = 0;
3658 /* The locations in the frag chain of the most recent frags at
3659 the start of which there is the given alignment. */
3660 frchainS *frchp_last32, *frchp_last16, *frchp_last8;
3661 fragS *fragp_last32, *fragp_last16, *fragp_last8;
3662 unsigned int pos_last32, pos_last16, pos_last8;
3664 frchp_last32 = frchp_last16 = frchp_last8 = info->frchainP;
3665 fragp_last32 = fragp_last16 = fragp_last8 = info->frchainP->frch_root;
3666 pos_last32 = pos_last16 = pos_last8 = 0;
3668 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3669 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3672 bfd_boolean go_back = FALSE;
3673 frchainS *frchp_next;
3676 if (fragp->fr_type != rs_machine_dependent)
3679 if (fragp->tc_frag_data.is_insns
3680 && pos + fragp->fr_fix > 32
3681 && !fragp->tc_frag_data.can_cross_fp_boundary)
3683 /* As described above, we should always have met an
3684 alignment requirement by the time we come back to
3691 want_insert = (32 - pos) >> 2;
3692 if (want_insert > 7)
3694 want_insert_done_so_far = 0;
3698 if (!fragp->tc_frag_data.is_insns)
3700 unsigned int would_insert_bytes;
3702 if (!(pos & ((1 << fragp->fr_offset) - 1)))
3703 /* This alignment requirement is already met. */
3706 /* As described above, we should always have met an
3707 alignment requirement by the time we come back to
3712 /* We may not be able to meet this requirement within
3713 the given number of characters. */
3715 = ((1 << fragp->fr_offset)
3716 - (pos & ((1 << fragp->fr_offset) - 1)));
3718 if (fragp->fr_subtype != 0
3719 && would_insert_bytes > fragp->fr_subtype)
3722 /* An unmet alignment must be 8, 16 or 32 bytes;
3723 smaller ones must always be met within code-only
3724 sections and larger ones cause the section not to
3726 if (fragp->fr_offset != 3
3727 && fragp->fr_offset != 4
3728 && fragp->fr_offset != 5)
3731 if (would_insert_bytes & 3)
3733 want_insert = would_insert_bytes >> 2;
3734 if (want_insert > 7)
3736 want_insert_done_so_far = 0;
3739 else if (want_insert && !go_back)
3741 unsigned int num_insns = fragp->fr_fix >> 2;
3742 unsigned int max_poss_nops = 8 - num_insns;
3746 unsigned int cur_want_nops, max_want_nops, do_nops, i;
3748 if (want_insert & 1)
3750 else if (want_insert & 2)
3752 else if (want_insert & 4)
3757 max_want_nops = cur_want_nops - want_insert_done_so_far;
3759 do_nops = (max_poss_nops < max_want_nops
3762 for (i = 0; i < do_nops; i++)
3764 md_number_to_chars (fragp->fr_literal + fragp->fr_fix,
3766 if (target_big_endian)
3767 fragp->fr_literal[fragp->fr_fix - 1] |= 0x1;
3769 fragp->fr_literal[fragp->fr_fix - 4] |= 0x1;
3773 want_insert_done_so_far += do_nops;
3774 if (want_insert_done_so_far == cur_want_nops)
3776 want_insert -= want_insert_done_so_far;
3777 want_insert_done_so_far = 0;
3785 if (want_insert & 1)
3787 frchp = frchp_last8;
3788 fragp = fragp_last8;
3791 else if (want_insert & 2)
3793 frchp = frchp_last8 = frchp_last16;
3794 fragp = fragp_last8 = fragp_last16;
3795 pos = pos_last8 = pos_last16;
3797 else if (want_insert & 4)
3799 frchp = frchp_last8 = frchp_last16 = frchp_last32;
3800 fragp = fragp_last8 = fragp_last16 = fragp_last32;
3801 pos = pos_last8 = pos_last16 = pos_last32;
3809 /* Update current position for moving past a code
3811 pos += fragp->fr_fix;
3814 fragp_next = fragp->fr_next;
3815 if (fragp_next == NULL)
3817 frchp_next = frchp->frch_next;
3818 if (frchp_next != NULL)
3819 fragp_next = frchp_next->frch_root;
3823 frchp_last8 = frchp_next;
3824 fragp_last8 = fragp_next;
3829 frchp_last16 = frchp_next;
3830 fragp_last16 = fragp_next;
3835 frchp_last32 = frchp_next;
3836 fragp_last32 = fragp_next;
3842 /* Now convert the machine-dependent frags to machine-independent
3844 for (frchp = info->frchainP; frchp; frchp = frchp->frch_next)
3845 for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
3847 if (fragp->fr_type == rs_machine_dependent)
3849 if (fragp->tc_frag_data.is_insns)
3853 fragp->fr_type = rs_align_code;
3855 *fragp->fr_literal = 0;
3861 /* Initialize the machine-dependent parts of a frag. */
3864 tic6x_frag_init (fragS *fragp)
3866 fragp->tc_frag_data.is_insns = FALSE;
3867 fragp->tc_frag_data.can_cross_fp_boundary = FALSE;
3870 /* Set an attribute if it has not already been set by the user. */
3873 tic6x_set_attribute_int (int tag, int value)
3876 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES)
3878 if (!tic6x_attributes_set_explicitly[tag])
3879 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
3882 /* Set object attributes deduced from the input file and command line
3883 rather than given explicitly. */
3885 tic6x_set_attributes (void)
3887 if (tic6x_arch_attribute == C6XABI_Tag_CPU_arch_none)
3888 tic6x_arch_attribute = C6XABI_Tag_CPU_arch_C674X;
3890 tic6x_set_attribute_int (Tag_C6XABI_Tag_CPU_arch, tic6x_arch_attribute);
3893 /* Do machine-dependent manipulations of the frag chains after all
3894 input has been read and before the machine-independent sizing and
3900 /* Set object attributes at this point if not explicitly set. */
3901 tic6x_set_attributes ();
3903 /* Meeting alignment requirements may require inserting NOPs in
3904 parallel in execute packets earlier in the segment. Future
3905 16-bit instruction generation involves whole-segment optimization
3906 to determine the best choice and ordering of 32-bit or 16-bit
3907 instructions. This doesn't fit will in the general relaxation
3908 framework, so handle alignment and 16-bit instruction generation
3910 bfd_map_over_sections (stdoutput, tic6x_adjust_section, NULL);
3913 /* No machine-dependent frags at this stage; all converted in
3917 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3918 fragS *fragp ATTRIBUTE_UNUSED)
3923 /* No machine-dependent frags at this stage; all converted in
3927 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
3928 segT seg ATTRIBUTE_UNUSED)
3933 /* Put a number into target byte order. */
3936 md_number_to_chars (char *buf, valueT val, int n)
3938 if (target_big_endian)
3939 number_to_chars_bigendian (buf, val, n);
3941 number_to_chars_littleendian (buf, val, n);
3944 /* Machine-dependent operand parsing not currently needed. */
3947 md_operand (expressionS *op ATTRIBUTE_UNUSED)
3951 /* PC-relative operands are relative to the start of the fetch
3955 tic6x_pcrel_from_section (fixS *fixp, segT sec)
3957 if (fixp->fx_addsy != NULL
3958 && (!S_IS_DEFINED (fixp->fx_addsy)
3959 || S_GET_SEGMENT (fixp->fx_addsy) != sec))
3961 return (fixp->fx_where + fixp->fx_frag->fr_address) & ~(long) 0x1f;
3964 /* Round up a section size to the appropriate boundary. */
3967 md_section_align (segT segment ATTRIBUTE_UNUSED,
3970 /* Round up section sizes to ensure that text sections consist of
3971 whole fetch packets. */
3972 int align = bfd_get_section_alignment (stdoutput, segment);
3973 return ((size + (1 << align) - 1) & ((valueT) -1 << align));
3976 /* No special undefined symbol handling needed for now. */
3979 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3984 /* Translate internal representation of relocation info to BFD target
3988 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3991 bfd_reloc_code_real_type r_type;
3993 reloc = xmalloc (sizeof (arelent));
3994 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3995 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3996 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3997 reloc->addend = (tic6x_generate_rela ? fixp->fx_offset : 0);
3998 r_type = fixp->fx_r_type;
3999 reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);
4001 if (reloc->howto == NULL)
4003 as_bad_where (fixp->fx_file, fixp->fx_line,
4004 _("Cannot represent relocation type %s"),
4005 bfd_get_reloc_code_name (r_type));
4009 /* Correct for adjustments bfd_install_relocation will make. */
4010 if (reloc->howto->pcrel_offset && reloc->howto->partial_inplace)
4011 reloc->addend += reloc->address;