1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "opcode/sparc.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 static struct sparc_arch *lookup_arch PARAMS ((char *));
36 static void init_default_arch PARAMS ((void));
37 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
38 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
40 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
41 static int sparc_ffs PARAMS ((unsigned int));
42 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
43 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
44 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
45 static bfd_vma BSR PARAMS ((bfd_vma, int));
46 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
47 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
48 static int parse_const_expr_arg PARAMS ((char **, int *));
49 static int get_expression PARAMS ((char *str));
51 /* Default architecture. */
52 /* ??? The default value should be V8, but sparclite support was added
53 by making it the default. GCC now passes -Asparclite, so maybe sometime in
54 the future we can set this to V8. */
56 #define DEFAULT_ARCH "sparclite"
58 static char *default_arch = DEFAULT_ARCH;
60 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
62 static int default_init_p;
64 /* Current architecture. We don't bump up unless necessary. */
65 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
67 /* The maximum architecture level we can bump up to.
68 In a 32 bit environment, don't allow bumping up to v9 by default.
69 The native assembler works this way. The user is required to pass
70 an explicit argument before we'll create v9 object files. However, if
71 we don't see any v9 insns, a v8plus object file is not created. */
72 static enum sparc_opcode_arch_val max_architecture;
74 /* Either 32 or 64, selects file format. */
75 static int sparc_arch_size;
76 /* Initial (default) value, recorded separately in case a user option
77 changes the value before md_show_usage is called. */
78 static int default_arch_size;
81 /* The currently selected v9 memory model. Currently only used for
83 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
86 static int architecture_requested;
87 static int warn_on_bump;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data;
106 extern int target_big_endian;
108 static int target_little_endian_data;
110 /* Symbols for global registers on v9. */
111 static symbolS *globals[8];
113 /* V9 and 86x have big and little endian data, but instructions are always big
114 endian. The sparclet has bi-endian support but both data and insns have
115 the same endianness. Global `target_big_endian' is used for data.
116 The following macro is used for instructions. */
117 #ifndef INSN_BIG_ENDIAN
118 #define INSN_BIG_ENDIAN (target_big_endian \
119 || default_arch_type == sparc86x \
120 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
123 /* Handle of the OPCODE hash table. */
124 static struct hash_control *op_hash;
126 static int log2 PARAMS ((int));
127 static void s_data1 PARAMS ((void));
128 static void s_seg PARAMS ((int));
129 static void s_proc PARAMS ((int));
130 static void s_reserve PARAMS ((int));
131 static void s_common PARAMS ((int));
132 static void s_empty PARAMS ((int));
133 static void s_uacons PARAMS ((int));
134 static void s_ncons PARAMS ((int));
135 static void s_register PARAMS ((int));
137 const pseudo_typeS md_pseudo_table[] =
139 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
140 {"common", s_common, 0},
141 {"empty", s_empty, 0},
142 {"global", s_globl, 0},
144 {"nword", s_ncons, 0},
145 {"optim", s_ignore, 0},
147 {"reserve", s_reserve, 0},
149 {"skip", s_space, 0},
152 {"uahalf", s_uacons, 2},
153 {"uaword", s_uacons, 4},
154 {"uaxword", s_uacons, 8},
156 {"file", dwarf2_directive_file, 0},
157 {"loc", dwarf2_directive_loc, 0},
158 /* These are specific to sparc/svr4. */
159 {"2byte", s_uacons, 2},
160 {"4byte", s_uacons, 4},
161 {"8byte", s_uacons, 8},
162 {"register", s_register, 0},
167 /* Size of relocation record. */
168 const int md_reloc_size = 12;
170 /* This array holds the chars that always start a comment. If the
171 pre-processor is disabled, these aren't very useful. */
172 const char comment_chars[] = "!"; /* JF removed '|' from
175 /* This array holds the chars that only start a comment at the beginning of
176 a line. If the line seems to have the form '# 123 filename'
177 .line and .file directives will appear in the pre-processed output. */
178 /* Note that input_file.c hand checks for '#' at the beginning of the
179 first line of the input file. This is because the compiler outputs
180 #NO_APP at the beginning of its output. */
181 /* Also note that comments started like this one will always
182 work if '/' isn't otherwise defined. */
183 const char line_comment_chars[] = "#";
185 const char line_separator_chars[] = ";";
187 /* Chars that can be used to separate mant from exp in floating point
189 const char EXP_CHARS[] = "eE";
191 /* Chars that mean this number is a floating point constant.
194 const char FLT_CHARS[] = "rRsSfFdDxXpP";
196 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
197 changed in read.c. Ideally it shouldn't have to know about it at all,
198 but nothing is ideal around here. */
200 #define isoctal(c) ((unsigned) ((c) - '0') < '8')
205 unsigned long opcode;
206 struct nlist *nlistp;
210 bfd_reloc_code_real_type reloc;
213 struct sparc_it the_insn, set_insn;
215 static void output_insn
216 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
218 /* Table of arguments to -A.
219 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
220 for this use. That table is for opcodes only. This table is for opcodes
223 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
224 v8plusa, v9, v9a, v9b, v9_64};
226 static struct sparc_arch {
229 enum sparc_arch_types arch_type;
230 /* Default word size, as specified during configuration.
231 A value of zero means can't be used to specify default architecture. */
232 int default_arch_size;
233 /* Allowable arg to -A? */
235 } sparc_arch_table[] = {
236 { "v6", "v6", v6, 0, 1 },
237 { "v7", "v7", v7, 0, 1 },
238 { "v8", "v8", v8, 32, 1 },
239 { "sparclet", "sparclet", sparclet, 32, 1 },
240 { "sparclite", "sparclite", sparclite, 32, 1 },
241 { "sparc86x", "sparclite", sparc86x, 32, 1 },
242 { "v8plus", "v9", v9, 0, 1 },
243 { "v8plusa", "v9a", v9, 0, 1 },
244 { "v8plusb", "v9b", v9, 0, 1 },
245 { "v9", "v9", v9, 0, 1 },
246 { "v9a", "v9a", v9, 0, 1 },
247 { "v9b", "v9b", v9, 0, 1 },
248 /* This exists to allow configure.in/Makefile.in to pass one
249 value to specify both the default machine and default word size. */
250 { "v9-64", "v9", v9, 64, 0 },
251 { NULL, NULL, v8, 0, 0 }
254 /* Variant of default_arch */
255 static enum sparc_arch_types default_arch_type;
257 static struct sparc_arch *
261 struct sparc_arch *sa;
263 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
264 if (strcmp (sa->name, name) == 0)
266 if (sa->name == NULL)
271 /* Initialize the default opcode arch and word size from the default
272 architecture name. */
277 struct sparc_arch *sa = lookup_arch (default_arch);
280 || sa->default_arch_size == 0)
281 as_fatal (_("Invalid default architecture, broken assembler."));
283 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
284 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
285 as_fatal (_("Bad opcode table, broken assembler."));
286 default_arch_size = sparc_arch_size = sa->default_arch_size;
288 default_arch_type = sa->arch_type;
291 /* Called by TARGET_FORMAT. */
294 sparc_target_format ()
296 /* We don't get a chance to initialize anything before we're called,
297 so handle that now. */
298 if (! default_init_p)
299 init_default_arch ();
303 return "a.out-sparc-netbsd";
306 if (target_big_endian)
307 return "a.out-sunos-big";
308 else if (default_arch_type == sparc86x && target_little_endian_data)
309 return "a.out-sunos-big";
311 return "a.out-sparc-little";
313 return "a.out-sunos-big";
324 return "coff-sparc-lynx";
331 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
338 * Invocation line includes a switch not recognized by the base assembler.
339 * See if it's a processor-specific option. These are:
342 * Warn on architecture bumps. See also -A.
344 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
345 * Standard 32 bit architectures.
347 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
348 * This used to only mean 64 bits, but properly specifying it
349 * complicated gcc's ASM_SPECs, so now opcode selection is
350 * specified orthogonally to word size (except when specifying
351 * the default, but that is an internal implementation detail).
352 * -Av8plus, -Av8plusa, -Av8plusb
353 * Same as -Av9{,a,b}.
354 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
355 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
357 * -xarch=v9, -xarch=v9a, -xarch=v9b
358 * Same as -Av9{,a,b} -64, for compatibility with Sun's
361 * Select the architecture and possibly the file format.
362 * Instructions or features not supported by the selected
363 * architecture cause fatal errors.
365 * The default is to start at v6, and bump the architecture up
366 * whenever an instruction is seen at a higher level. In 32 bit
367 * environments, v9 is not bumped up to, the user must pass
370 * If -bump is specified, a warning is printing when bumping to
373 * If an architecture is specified, all instructions must match
374 * that architecture. Any higher level instructions are flagged
375 * as errors. Note that in the 32 bit environment specifying
376 * -Av8plus does not automatically create a v8plus object file, a
377 * v9 insn must be seen.
379 * If both an architecture and -bump are specified, the
380 * architecture starts at the specified level, but bumps are
381 * warnings. Note that we can't set `current_architecture' to
382 * the requested level in this case: in the 32 bit environment,
383 * we still must avoid creating v8plus object files unless v9
387 * Bumping between incompatible architectures is always an
388 * error. For example, from sparclite to v9.
392 CONST char *md_shortopts = "A:K:VQ:sq";
395 CONST char *md_shortopts = "A:k";
397 CONST char *md_shortopts = "A:";
400 struct option md_longopts[] = {
401 #define OPTION_BUMP (OPTION_MD_BASE)
402 {"bump", no_argument, NULL, OPTION_BUMP},
403 #define OPTION_SPARC (OPTION_MD_BASE + 1)
404 {"sparc", no_argument, NULL, OPTION_SPARC},
405 #define OPTION_XARCH (OPTION_MD_BASE + 2)
406 {"xarch", required_argument, NULL, OPTION_XARCH},
408 #define OPTION_32 (OPTION_MD_BASE + 3)
409 {"32", no_argument, NULL, OPTION_32},
410 #define OPTION_64 (OPTION_MD_BASE + 4)
411 {"64", no_argument, NULL, OPTION_64},
412 #define OPTION_TSO (OPTION_MD_BASE + 5)
413 {"TSO", no_argument, NULL, OPTION_TSO},
414 #define OPTION_PSO (OPTION_MD_BASE + 6)
415 {"PSO", no_argument, NULL, OPTION_PSO},
416 #define OPTION_RMO (OPTION_MD_BASE + 7)
417 {"RMO", no_argument, NULL, OPTION_RMO},
419 #ifdef SPARC_BIENDIAN
420 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
421 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
422 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
423 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
425 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
426 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
427 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
428 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
430 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
431 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
432 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
433 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
435 #define OPTION_RELAX (OPTION_MD_BASE + 14)
436 {"relax", no_argument, NULL, OPTION_RELAX},
437 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
438 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
439 {NULL, no_argument, NULL, 0}
442 size_t md_longopts_size = sizeof (md_longopts);
445 md_parse_option (c, arg)
449 /* We don't get a chance to initialize anything before we're called,
450 so handle that now. */
451 if (! default_init_p)
452 init_default_arch ();
458 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
463 if (strncmp (arg, "v9", 2) != 0)
464 md_parse_option (OPTION_32, NULL);
466 md_parse_option (OPTION_64, NULL);
472 struct sparc_arch *sa;
473 enum sparc_opcode_arch_val opcode_arch;
475 sa = lookup_arch (arg);
477 || ! sa->user_option_p)
479 if (c == OPTION_XARCH)
480 as_bad (_("invalid architecture -xarch=%s"), arg);
482 as_bad (_("invalid architecture -A%s"), arg);
486 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
487 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
488 as_fatal (_("Bad opcode table, broken assembler."));
490 max_architecture = opcode_arch;
491 architecture_requested = 1;
496 /* Ignore -sparc, used by SunOS make default .s.o rule. */
499 case OPTION_ENFORCE_ALIGNED_DATA:
500 enforce_aligned_data = 1;
503 #ifdef SPARC_BIENDIAN
504 case OPTION_LITTLE_ENDIAN:
505 target_big_endian = 0;
506 if (default_arch_type != sparclet)
507 as_fatal ("This target does not support -EL");
509 case OPTION_LITTLE_ENDIAN_DATA:
510 target_little_endian_data = 1;
511 target_big_endian = 0;
512 if (default_arch_type != sparc86x
513 && default_arch_type != v9)
514 as_fatal ("This target does not support --little-endian-data");
516 case OPTION_BIG_ENDIAN:
517 target_big_endian = 1;
531 const char **list, **l;
533 sparc_arch_size = c == OPTION_32 ? 32 : 64;
534 list = bfd_target_list ();
535 for (l = list; *l != NULL; l++)
537 if (sparc_arch_size == 32)
539 if (strcmp (*l, "elf32-sparc") == 0)
544 if (strcmp (*l, "elf64-sparc") == 0)
549 as_fatal (_("No compiled in support for %d bit object file format"),
556 sparc_memory_model = MM_TSO;
560 sparc_memory_model = MM_PSO;
564 sparc_memory_model = MM_RMO;
572 /* Qy - do emit .comment
573 Qn - do not emit .comment. */
577 /* Use .stab instead of .stab.excl. */
581 /* quick -- Native assembler does fewer checks. */
585 if (strcmp (arg, "PIC") != 0)
586 as_warn (_("Unrecognized option following -K"));
591 case OPTION_NO_UNDECLARED_REGS:
592 no_undeclared_regs = 1;
595 case OPTION_UNDECLARED_REGS:
596 no_undeclared_regs = 0;
604 case OPTION_NO_RELAX:
616 md_show_usage (stream)
619 const struct sparc_arch *arch;
622 /* We don't get a chance to initialize anything before we're called,
623 so handle that now. */
624 if (! default_init_p)
625 init_default_arch ();
627 fprintf (stream, _("SPARC options:\n"));
629 for (arch = &sparc_arch_table[0]; arch->name; arch++)
631 if (!arch->user_option_p)
633 if (arch != &sparc_arch_table[0])
634 fprintf (stream, " | ");
635 if (column + strlen(arch->name) > 70)
638 fputc ('\n', stream);
640 column += 5 + 2 + strlen(arch->name);
641 fprintf (stream, "-A%s", arch->name);
643 for (arch = &sparc_arch_table[0]; arch->name; arch++)
645 if (!arch->user_option_p)
647 fprintf (stream, " | ");
648 if (column + strlen(arch->name) > 65)
651 fputc ('\n', stream);
653 column += 5 + 7 + strlen(arch->name);
654 fprintf (stream, "-xarch=%s", arch->name);
656 fprintf (stream, _("\n\
657 specify variant of SPARC architecture\n\
658 -bump warn when assembler switches architectures\n\
660 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
661 -relax relax jumps and branches (default)\n\
662 -no-relax avoid changing any jumps and branches\n"));
664 fprintf (stream, _("\
665 -k generate PIC\n"));
668 fprintf (stream, _("\
669 -32 create 32 bit object file\n\
670 -64 create 64 bit object file\n"));
671 fprintf (stream, _("\
672 [default is %d]\n"), default_arch_size);
673 fprintf (stream, _("\
674 -TSO use Total Store Ordering\n\
675 -PSO use Partial Store Ordering\n\
676 -RMO use Relaxed Memory Ordering\n"));
677 fprintf (stream, _("\
678 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
679 fprintf (stream, _("\
680 -KPIC generate PIC\n\
681 -V print assembler version number\n\
682 -undeclared-regs ignore application global register usage without\n\
683 appropriate .register directive (default)\n\
684 -no-undeclared-regs force error on application global register usage\n\
685 without appropriate .register directive\n\
690 #ifdef SPARC_BIENDIAN
691 fprintf (stream, _("\
692 -EL generate code for a little endian machine\n\
693 -EB generate code for a big endian machine\n\
694 --little-endian-data generate code for a machine having big endian\n\
695 instructions and little endian data.\n"));
699 /* Native operand size opcode translation. */
705 } native_op_table[] =
707 {"ldn", "ld", "ldx"},
708 {"ldna", "lda", "ldxa"},
709 {"stn", "st", "stx"},
710 {"stna", "sta", "stxa"},
711 {"slln", "sll", "sllx"},
712 {"srln", "srl", "srlx"},
713 {"sran", "sra", "srax"},
714 {"casn", "cas", "casx"},
715 {"casna", "casa", "casxa"},
716 {"clrn", "clr", "clrx"},
720 /* sparc64 priviledged registers. */
722 struct priv_reg_entry
728 struct priv_reg_entry priv_reg_table[] =
747 {"", -1}, /* End marker. */
750 /* v9a specific asrs. */
752 struct priv_reg_entry v9a_asr_table[] =
755 {"sys_tick_cmpr", 25},
763 {"clear_softint", 21},
764 {"", -1}, /* End marker. */
768 cmp_reg_entry (parg, qarg)
772 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
773 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
775 return strcmp (q->name, p->name);
778 /* This function is called once, at assembler startup time. It should
779 set up all the tables, etc. that the MD part of the assembler will
785 register const char *retval = NULL;
787 register unsigned int i = 0;
789 /* We don't get a chance to initialize anything before md_parse_option
790 is called, and it may not be called, so handle default initialization
791 now if not already done. */
792 if (! default_init_p)
793 init_default_arch ();
795 op_hash = hash_new ();
797 while (i < (unsigned int) sparc_num_opcodes)
799 const char *name = sparc_opcodes[i].name;
800 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
803 as_bad (_("Internal error: can't hash `%s': %s\n"),
804 sparc_opcodes[i].name, retval);
809 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
811 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
812 sparc_opcodes[i].name, sparc_opcodes[i].args);
817 while (i < (unsigned int) sparc_num_opcodes
818 && !strcmp (sparc_opcodes[i].name, name));
821 for (i = 0; native_op_table[i].name; i++)
823 const struct sparc_opcode *insn;
824 char *name = ((sparc_arch_size == 32)
825 ? native_op_table[i].name32
826 : native_op_table[i].name64);
827 insn = (struct sparc_opcode *) hash_find (op_hash, name);
830 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
831 name, native_op_table[i].name);
836 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
839 as_bad (_("Internal error: can't hash `%s': %s\n"),
840 sparc_opcodes[i].name, retval);
847 as_fatal (_("Broken assembler. No assembly attempted."));
849 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
850 sizeof (priv_reg_table[0]), cmp_reg_entry);
852 /* If -bump, record the architecture level at which we start issuing
853 warnings. The behaviour is different depending upon whether an
854 architecture was explicitly specified. If it wasn't, we issue warnings
855 for all upwards bumps. If it was, we don't start issuing warnings until
856 we need to bump beyond the requested architecture or when we bump between
857 conflicting architectures. */
860 && architecture_requested)
862 /* `max_architecture' records the requested architecture.
863 Issue warnings if we go above it. */
864 warn_after_architecture = max_architecture;
866 /* Find the highest architecture level that doesn't conflict with
867 the requested one. */
868 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
869 max_architecture > warn_after_architecture;
871 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
872 warn_after_architecture))
877 /* Called after all assembly has been done. */
882 unsigned long mach = bfd_mach_sparc;
884 if (sparc_arch_size == 64)
885 switch (current_architecture)
887 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
888 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
889 default: mach = bfd_mach_sparc_v9; break;
892 switch (current_architecture)
894 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
895 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
896 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
897 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
898 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
899 be but for now it is (since that's the way it's always been
903 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
906 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
909 in_signed_range (val, max)
910 bfd_signed_vma val, max;
914 /* Sign-extend the value from the architecture word size, so that
915 0xffffffff is always considered -1 on sparc32. */
916 if (sparc_arch_size == 32)
918 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
919 val = ((val & 0xffffffff) ^ sign) - sign;
928 /* Return non-zero if VAL is in the range 0 to MAX. */
931 in_unsigned_range (val, max)
939 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
940 (e.g. -15 to +31). */
943 in_bitfield_range (val, max)
944 bfd_signed_vma val, max;
950 if (val < ~(max >> 1))
964 for (i = 0; (mask & 1) == 0; ++i)
969 /* Implement big shift right. */
975 if (sizeof (bfd_vma) <= 4 && amount >= 32)
976 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
977 return val >> amount;
980 /* For communication between sparc_ip and get_expression. */
981 static char *expr_end;
983 /* Values for `special_case'.
984 Instructions that require wierd handling because they're longer than
986 #define SPECIAL_CASE_NONE 0
987 #define SPECIAL_CASE_SET 1
988 #define SPECIAL_CASE_SETSW 2
989 #define SPECIAL_CASE_SETX 3
990 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
991 #define SPECIAL_CASE_FDIV 4
993 /* Bit masks of various insns. */
994 #define NOP_INSN 0x01000000
995 #define OR_INSN 0x80100000
996 #define XOR_INSN 0x80180000
997 #define FMOVS_INSN 0x81A00020
998 #define SETHI_INSN 0x01000000
999 #define SLLX_INSN 0x81281000
1000 #define SRA_INSN 0x81380000
1002 /* The last instruction to be assembled. */
1003 static const struct sparc_opcode *last_insn;
1004 /* The assembled opcode of `last_insn'. */
1005 static unsigned long last_opcode;
1007 /* Handle the set and setuw synthetic instructions. */
1010 synthetize_setuw (insn)
1011 const struct sparc_opcode *insn;
1013 int need_hi22_p = 0;
1014 int rd = (the_insn.opcode & RD (~0)) >> 25;
1016 if (the_insn.exp.X_op == O_constant)
1018 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1020 if (sizeof (offsetT) > 4
1021 && (the_insn.exp.X_add_number < 0
1022 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1023 as_warn (_("set: number not in 0..4294967295 range"));
1027 if (sizeof (offsetT) > 4
1028 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1029 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1030 as_warn (_("set: number not in -2147483648..4294967295 range"));
1031 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1035 /* See if operand is absolute and small; skip sethi if so. */
1036 if (the_insn.exp.X_op != O_constant
1037 || the_insn.exp.X_add_number >= (1 << 12)
1038 || the_insn.exp.X_add_number < -(1 << 12))
1040 the_insn.opcode = (SETHI_INSN | RD (rd)
1041 | ((the_insn.exp.X_add_number >> 10)
1042 & (the_insn.exp.X_op == O_constant
1044 the_insn.reloc = (the_insn.exp.X_op != O_constant
1045 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1046 output_insn (insn, &the_insn);
1050 /* See if operand has no low-order bits; skip OR if so. */
1051 if (the_insn.exp.X_op != O_constant
1052 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1055 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1057 | (the_insn.exp.X_add_number
1058 & (the_insn.exp.X_op != O_constant
1059 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1060 the_insn.reloc = (the_insn.exp.X_op != O_constant
1061 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1062 output_insn (insn, &the_insn);
1066 /* Handle the setsw synthetic instruction. */
1069 synthetize_setsw (insn)
1070 const struct sparc_opcode *insn;
1074 rd = (the_insn.opcode & RD (~0)) >> 25;
1076 if (the_insn.exp.X_op != O_constant)
1078 synthetize_setuw (insn);
1080 /* Need to sign extend it. */
1081 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1082 the_insn.reloc = BFD_RELOC_NONE;
1083 output_insn (insn, &the_insn);
1087 if (sizeof (offsetT) > 4
1088 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1089 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1090 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1092 low32 = the_insn.exp.X_add_number;
1096 synthetize_setuw (insn);
1102 the_insn.reloc = BFD_RELOC_NONE;
1103 /* See if operand is absolute and small; skip sethi if so. */
1104 if (low32 < -(1 << 12))
1106 the_insn.opcode = (SETHI_INSN | RD (rd)
1107 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1108 output_insn (insn, &the_insn);
1109 low32 = 0x1c00 | (low32 & 0x3ff);
1110 opc = RS1 (rd) | XOR_INSN;
1113 the_insn.opcode = (opc | RD (rd) | IMMED
1114 | (low32 & 0x1fff));
1115 output_insn (insn, &the_insn);
1118 /* Handle the setsw synthetic instruction. */
1121 synthetize_setx (insn)
1122 const struct sparc_opcode *insn;
1124 int upper32, lower32;
1125 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1126 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1128 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1129 int need_xor10_p = 0;
1131 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1132 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1133 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1136 upper_dstreg = tmpreg;
1137 /* The tmp reg should not be the dst reg. */
1138 if (tmpreg == dstreg)
1139 as_warn (_("setx: temporary register same as destination register"));
1141 /* ??? Obviously there are other optimizations we can do
1142 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1143 doing some of these. Later. If you do change things, try to
1144 change all of this to be table driven as well. */
1145 /* What to output depends on the number if it's constant.
1146 Compute that first, then output what we've decided upon. */
1147 if (the_insn.exp.X_op != O_constant)
1149 if (sparc_arch_size == 32)
1151 /* When arch size is 32, we want setx to be equivalent
1152 to setuw for anything but constants. */
1153 the_insn.exp.X_add_number &= 0xffffffff;
1154 synthetize_setuw (insn);
1157 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1163 /* Reset X_add_number, we've extracted it as upper32/lower32.
1164 Otherwise fixup_segment will complain about not being able to
1165 write an 8 byte number in a 4 byte field. */
1166 the_insn.exp.X_add_number = 0;
1168 /* Only need hh22 if `or' insn can't handle constant. */
1169 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1172 /* Does bottom part (after sethi) have bits? */
1173 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1174 /* No hh22, but does upper32 still have bits we can't set
1176 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1179 /* If the lower half is all zero, we build the upper half directly
1180 into the dst reg. */
1182 /* Need lower half if number is zero or 0xffffffff00000000. */
1183 || (! need_hh22_p && ! need_hm10_p))
1185 /* No need for sethi if `or' insn can handle constant. */
1186 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1187 /* Note that we can't use a negative constant in the `or'
1188 insn unless the upper 32 bits are all ones. */
1189 || (lower32 < 0 && upper32 != -1)
1190 || (lower32 >= 0 && upper32 == -1))
1193 if (need_hi22_p && upper32 == -1)
1196 /* Does bottom part (after sethi) have bits? */
1197 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1199 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1200 /* Need `or' if we didn't set anything else. */
1201 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1205 /* Output directly to dst reg if lower 32 bits are all zero. */
1206 upper_dstreg = dstreg;
1209 if (!upper_dstreg && dstreg)
1210 as_warn (_("setx: illegal temporary register g0"));
1214 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1215 | ((upper32 >> 10) & 0x3fffff));
1216 the_insn.reloc = (the_insn.exp.X_op != O_constant
1217 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1218 output_insn (insn, &the_insn);
1223 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1224 | (((need_xor10_p ? ~lower32 : lower32)
1225 >> 10) & 0x3fffff));
1226 the_insn.reloc = (the_insn.exp.X_op != O_constant
1227 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1228 output_insn (insn, &the_insn);
1233 the_insn.opcode = (OR_INSN
1234 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1237 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1238 the_insn.reloc = (the_insn.exp.X_op != O_constant
1239 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1240 output_insn (insn, &the_insn);
1245 /* FIXME: One nice optimization to do here is to OR the low part
1246 with the highpart if hi22 isn't needed and the low part is
1248 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1251 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1252 the_insn.reloc = (the_insn.exp.X_op != O_constant
1253 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1254 output_insn (insn, &the_insn);
1257 /* If we needed to build the upper part, shift it into place. */
1258 if (need_hh22_p || need_hm10_p)
1260 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1262 the_insn.reloc = BFD_RELOC_NONE;
1263 output_insn (insn, &the_insn);
1266 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1269 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1270 | 0x1c00 | (lower32 & 0x3ff));
1271 the_insn.reloc = BFD_RELOC_NONE;
1272 output_insn (insn, &the_insn);
1275 /* If we needed to build both upper and lower parts, OR them together. */
1276 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1278 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1280 the_insn.reloc = BFD_RELOC_NONE;
1281 output_insn (insn, &the_insn);
1285 /* Main entry point to assemble one instruction. */
1291 const struct sparc_opcode *insn;
1295 special_case = sparc_ip (str, &insn);
1297 /* We warn about attempts to put a floating point branch in a delay slot,
1298 unless the delay slot has been annulled. */
1300 && last_insn != NULL
1301 && (insn->flags & F_FBR) != 0
1302 && (last_insn->flags & F_DELAYED) != 0
1303 /* ??? This test isn't completely accurate. We assume anything with
1304 F_{UNBR,CONDBR,FBR} set is annullable. */
1305 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1306 || (last_opcode & ANNUL) == 0))
1307 as_warn (_("FP branch in delay slot"));
1309 /* SPARC before v9 requires a nop instruction between a floating
1310 point instruction and a floating point branch. We insert one
1311 automatically, with a warning. */
1312 if (max_architecture < SPARC_OPCODE_ARCH_V9
1314 && last_insn != NULL
1315 && (insn->flags & F_FBR) != 0
1316 && (last_insn->flags & F_FLOAT) != 0)
1318 struct sparc_it nop_insn;
1320 nop_insn.opcode = NOP_INSN;
1321 nop_insn.reloc = BFD_RELOC_NONE;
1322 output_insn (insn, &nop_insn);
1323 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1326 switch (special_case)
1328 case SPECIAL_CASE_NONE:
1330 output_insn (insn, &the_insn);
1333 case SPECIAL_CASE_SETSW:
1334 synthetize_setsw (insn);
1337 case SPECIAL_CASE_SET:
1338 synthetize_setuw (insn);
1341 case SPECIAL_CASE_SETX:
1342 synthetize_setx (insn);
1345 case SPECIAL_CASE_FDIV:
1347 int rd = (the_insn.opcode >> 25) & 0x1f;
1349 output_insn (insn, &the_insn);
1351 /* According to information leaked from Sun, the "fdiv" instructions
1352 on early SPARC machines would produce incorrect results sometimes.
1353 The workaround is to add an fmovs of the destination register to
1354 itself just after the instruction. This was true on machines
1355 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1356 assert (the_insn.reloc == BFD_RELOC_NONE);
1357 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1358 output_insn (insn, &the_insn);
1363 as_fatal (_("failed special case insn sanity check"));
1367 /* Subroutine of md_assemble to do the actual parsing. */
1370 sparc_ip (str, pinsn)
1372 const struct sparc_opcode **pinsn;
1374 char *error_message = "";
1378 const struct sparc_opcode *insn;
1380 unsigned long opcode;
1381 unsigned int mask = 0;
1385 int special_case = SPECIAL_CASE_NONE;
1388 if (islower ((unsigned char) *s))
1392 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1409 as_fatal (_("Unknown opcode: `%s'"), str);
1411 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1415 as_bad (_("Unknown opcode: `%s'"), str);
1416 return special_case;
1426 opcode = insn->match;
1427 memset (&the_insn, '\0', sizeof (the_insn));
1428 the_insn.reloc = BFD_RELOC_NONE;
1431 /* Build the opcode, checking as we go to make sure that the
1433 for (args = insn->args;; ++args)
1441 /* Parse a series of masks. */
1448 if (! parse_keyword_arg (sparc_encode_membar, &s,
1451 error_message = _(": invalid membar mask name");
1457 if (*s == '|' || *s == '+')
1465 if (! parse_const_expr_arg (&s, &kmask))
1467 error_message = _(": invalid membar mask expression");
1470 if (kmask < 0 || kmask > 127)
1472 error_message = _(": invalid membar mask number");
1477 opcode |= MEMBAR (kmask);
1485 if (! parse_const_expr_arg (&s, &smask))
1487 error_message = _(": invalid siam mode expression");
1490 if (smask < 0 || smask > 7)
1492 error_message = _(": invalid siam mode number");
1503 /* Parse a prefetch function. */
1506 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1508 error_message = _(": invalid prefetch function name");
1514 if (! parse_const_expr_arg (&s, &fcn))
1516 error_message = _(": invalid prefetch function expression");
1519 if (fcn < 0 || fcn > 31)
1521 error_message = _(": invalid prefetch function number");
1531 /* Parse a sparc64 privileged register. */
1534 struct priv_reg_entry *p = priv_reg_table;
1535 unsigned int len = 9999999; /* Init to make gcc happy. */
1538 while (p->name[0] > s[0])
1540 while (p->name[0] == s[0])
1542 len = strlen (p->name);
1543 if (strncmp (p->name, s, len) == 0)
1547 if (p->name[0] != s[0])
1549 error_message = _(": unrecognizable privileged register");
1553 opcode |= (p->regnum << 14);
1555 opcode |= (p->regnum << 25);
1561 error_message = _(": unrecognizable privileged register");
1567 /* Parse a v9a/v9b ancillary state register. */
1570 struct priv_reg_entry *p = v9a_asr_table;
1571 unsigned int len = 9999999; /* Init to make gcc happy. */
1574 while (p->name[0] > s[0])
1576 while (p->name[0] == s[0])
1578 len = strlen (p->name);
1579 if (strncmp (p->name, s, len) == 0)
1583 if (p->name[0] != s[0])
1585 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1588 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1590 error_message = _(": rd on write only ancillary state register");
1594 && (insn->architecture
1595 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1597 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1598 error_message = _(": unrecognizable v9a ancillary state register");
1602 opcode |= (p->regnum << 14);
1604 opcode |= (p->regnum << 25);
1610 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1616 if (strncmp (s, "%asr", 4) == 0)
1620 if (isdigit ((unsigned char) *s))
1624 while (isdigit ((unsigned char) *s))
1626 num = num * 10 + *s - '0';
1630 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1632 if (num < 16 || 31 < num)
1634 error_message = _(": asr number must be between 16 and 31");
1640 if (num < 0 || 31 < num)
1642 error_message = _(": asr number must be between 0 and 31");
1647 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1652 error_message = _(": expecting %asrN");
1659 the_insn.reloc = BFD_RELOC_SPARC_11;
1663 the_insn.reloc = BFD_RELOC_SPARC_10;
1667 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1668 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1669 the_insn.reloc = BFD_RELOC_SPARC_5;
1671 the_insn.reloc = BFD_RELOC_SPARC13;
1672 /* These fields are unsigned, but for upward compatibility,
1673 allow negative values as well. */
1677 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1678 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1679 the_insn.reloc = BFD_RELOC_SPARC_6;
1681 the_insn.reloc = BFD_RELOC_SPARC13;
1682 /* These fields are unsigned, but for upward compatibility,
1683 allow negative values as well. */
1687 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1692 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1697 if (*s == 'p' && s[1] == 'n')
1705 if (*s == 'p' && s[1] == 't')
1717 if (strncmp (s, "%icc", 4) == 0)
1729 if (strncmp (s, "%xcc", 4) == 0)
1741 if (strncmp (s, "%fcc0", 5) == 0)
1753 if (strncmp (s, "%fcc1", 5) == 0)
1765 if (strncmp (s, "%fcc2", 5) == 0)
1777 if (strncmp (s, "%fcc3", 5) == 0)
1785 if (strncmp (s, "%pc", 3) == 0)
1793 if (strncmp (s, "%tick", 5) == 0)
1800 case '\0': /* End of args. */
1819 case '[': /* These must match exactly. */
1827 case '#': /* Must be at least one digit. */
1828 if (isdigit ((unsigned char) *s++))
1830 while (isdigit ((unsigned char) *s))
1838 case 'C': /* Coprocessor state register. */
1839 if (strncmp (s, "%csr", 4) == 0)
1846 case 'b': /* Next operand is a coprocessor register. */
1849 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1852 if (isdigit ((unsigned char) *s))
1854 mask = 10 * (mask - '0') + (*s++ - '0');
1868 opcode |= mask << 14;
1876 opcode |= mask << 25;
1882 case 'r': /* next operand must be a register */
1892 case 'f': /* frame pointer */
1900 case 'g': /* global register */
1909 case 'i': /* in register */
1913 mask = c - '0' + 24;
1918 case 'l': /* local register */
1922 mask = (c - '0' + 16);
1927 case 'o': /* out register */
1931 mask = (c - '0' + 8);
1936 case 's': /* stack pointer */
1944 case 'r': /* any register */
1945 if (!isdigit ((unsigned char) (c = *s++)))
1960 if (isdigit ((unsigned char) *s))
1962 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1978 if ((mask & ~1) == 2 && sparc_arch_size == 64
1979 && no_undeclared_regs && ! globals[mask])
1980 as_bad (_("detected global register use not covered by .register pseudo-op"));
1982 /* Got the register, now figure out where
1983 it goes in the opcode. */
1987 opcode |= mask << 14;
1995 opcode |= mask << 25;
1999 opcode |= (mask << 25) | (mask << 14);
2003 opcode |= (mask << 25) | (mask << 0);
2009 case 'e': /* next operand is a floating point register */
2024 && ((format = *s) == 'f')
2025 && isdigit ((unsigned char) *++s))
2027 for (mask = 0; isdigit ((unsigned char) *s); ++s)
2029 mask = 10 * mask + (*s - '0');
2030 } /* read the number */
2038 } /* register must be even numbered */
2046 } /* register must be multiple of 4 */
2050 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2051 error_message = _(": There are only 64 f registers; [0-63]");
2053 error_message = _(": There are only 32 f registers; [0-31]");
2056 else if (mask >= 32)
2058 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2061 mask -= 31; /* wrap high bit */
2065 error_message = _(": There are only 32 f registers; [0-31]");
2073 } /* if not an 'f' register. */
2080 opcode |= RS1 (mask);
2086 opcode |= RS2 (mask);
2092 opcode |= RD (mask);
2101 if (strncmp (s, "%fsr", 4) == 0)
2108 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2109 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2112 case 'l': /* 22 bit PC relative immediate */
2113 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2117 case 'L': /* 30 bit immediate */
2118 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2123 case 'n': /* 22 bit immediate */
2124 the_insn.reloc = BFD_RELOC_SPARC22;
2127 case 'i': /* 13 bit immediate */
2128 the_insn.reloc = BFD_RELOC_SPARC13;
2138 char *op_arg = NULL;
2140 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2142 /* Check for %hi, etc. */
2145 static const struct ops {
2146 /* The name as it appears in assembler. */
2148 /* strlen (name), precomputed for speed */
2150 /* The reloc this pseudo-op translates to. */
2152 /* Non-zero if for v9 only. */
2154 /* Non-zero if can be used in pc-relative contexts. */
2155 int pcrel_p;/*FIXME:wip*/
2157 /* hix/lox must appear before hi/lo so %hix won't be
2158 mistaken for %hi. */
2159 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2160 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2161 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2162 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2163 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2164 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2165 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2166 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2167 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2168 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2169 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2170 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2171 { NULL, 0, 0, 0, 0 }
2173 const struct ops *o;
2175 for (o = ops; o->name; o++)
2176 if (strncmp (s + 1, o->name, o->len) == 0)
2178 if (o->name == NULL)
2181 if (s[o->len + 1] != '(')
2183 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2184 return special_case;
2188 the_insn.reloc = o->reloc;
2193 /* Note that if the get_expression() fails, we will still
2194 have created U entries in the symbol table for the
2195 'symbols' in the input string. Try not to create U
2196 symbols for registers, etc. */
2198 /* This stuff checks to see if the expression ends in
2199 +%reg. If it does, it removes the register from
2200 the expression, and re-sets 's' to point to the
2207 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2210 else if (*s1 == ')')
2219 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2220 return special_case;
2224 (void) get_expression (s);
2227 if (*s == ',' || *s == ']' || !*s)
2229 if (*s != '+' && *s != '-')
2231 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2232 return special_case;
2236 op_exp = the_insn.exp;
2237 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2240 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2243 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2245 if (s1[-2] == '%' && s1[-3] == '+')
2247 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2254 if (op_arg && s1 == s + 1)
2255 the_insn.exp.X_op = O_absent;
2257 (void) get_expression (s);
2269 (void) get_expression (s);
2277 the_insn.exp2 = the_insn.exp;
2278 the_insn.exp = op_exp;
2279 if (the_insn.exp2.X_op == O_absent)
2280 the_insn.exp2.X_op = O_illegal;
2281 else if (the_insn.exp.X_op == O_absent)
2283 the_insn.exp = the_insn.exp2;
2284 the_insn.exp2.X_op = O_illegal;
2286 else if (the_insn.exp.X_op == O_constant)
2288 valueT val = the_insn.exp.X_add_number;
2289 switch (the_insn.reloc)
2294 case BFD_RELOC_SPARC_HH22:
2295 val = BSR (val, 32);
2298 case BFD_RELOC_SPARC_LM22:
2299 case BFD_RELOC_HI22:
2300 val = (val >> 10) & 0x3fffff;
2303 case BFD_RELOC_SPARC_HM10:
2304 val = BSR (val, 32);
2307 case BFD_RELOC_LO10:
2311 case BFD_RELOC_SPARC_H44:
2316 case BFD_RELOC_SPARC_M44:
2321 case BFD_RELOC_SPARC_L44:
2325 case BFD_RELOC_SPARC_HIX22:
2327 val = (val >> 10) & 0x3fffff;
2330 case BFD_RELOC_SPARC_LOX10:
2331 val = (val & 0x3ff) | 0x1c00;
2334 the_insn.exp = the_insn.exp2;
2335 the_insn.exp.X_add_number += val;
2336 the_insn.exp2.X_op = O_illegal;
2337 the_insn.reloc = old_reloc;
2339 else if (the_insn.exp2.X_op != O_constant)
2341 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2342 return special_case;
2346 if (old_reloc != BFD_RELOC_SPARC13
2347 || the_insn.reloc != BFD_RELOC_LO10
2348 || sparc_arch_size != 64
2351 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2352 return special_case;
2354 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2358 /* Check for constants that don't require emitting a reloc. */
2359 if (the_insn.exp.X_op == O_constant
2360 && the_insn.exp.X_add_symbol == 0
2361 && the_insn.exp.X_op_symbol == 0)
2363 /* For pc-relative call instructions, we reject
2364 constants to get better code. */
2366 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2367 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2369 error_message = _(": PC-relative operand can't be a constant");
2373 /* Constants that won't fit are checked in md_apply_fix3
2374 and bfd_install_relocation.
2375 ??? It would be preferable to install the constants
2376 into the insn here and save having to create a fixS
2377 for each one. There already exists code to handle
2378 all the various cases (e.g. in md_apply_fix3 and
2379 bfd_install_relocation) so duplicating all that code
2380 here isn't right. */
2400 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2402 error_message = _(": invalid ASI name");
2408 if (! parse_const_expr_arg (&s, &asi))
2410 error_message = _(": invalid ASI expression");
2413 if (asi < 0 || asi > 255)
2415 error_message = _(": invalid ASI number");
2419 opcode |= ASI (asi);
2421 } /* Alternate space. */
2424 if (strncmp (s, "%psr", 4) == 0)
2431 case 'q': /* Floating point queue. */
2432 if (strncmp (s, "%fq", 3) == 0)
2439 case 'Q': /* Coprocessor queue. */
2440 if (strncmp (s, "%cq", 3) == 0)
2448 if (strcmp (str, "set") == 0
2449 || strcmp (str, "setuw") == 0)
2451 special_case = SPECIAL_CASE_SET;
2454 else if (strcmp (str, "setsw") == 0)
2456 special_case = SPECIAL_CASE_SETSW;
2459 else if (strcmp (str, "setx") == 0)
2461 special_case = SPECIAL_CASE_SETX;
2464 else if (strncmp (str, "fdiv", 4) == 0)
2466 special_case = SPECIAL_CASE_FDIV;
2472 if (strncmp (s, "%asi", 4) != 0)
2478 if (strncmp (s, "%fprs", 5) != 0)
2484 if (strncmp (s, "%ccr", 4) != 0)
2490 if (strncmp (s, "%tbr", 4) != 0)
2496 if (strncmp (s, "%wim", 4) != 0)
2503 char *push = input_line_pointer;
2506 input_line_pointer = s;
2508 if (e.X_op == O_constant)
2510 int n = e.X_add_number;
2511 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2512 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2514 opcode |= e.X_add_number << 5;
2517 as_bad (_("non-immediate OPF operand, ignored"));
2518 s = input_line_pointer;
2519 input_line_pointer = push;
2524 if (strncmp (s, "%y", 2) != 0)
2532 /* Parse a sparclet cpreg. */
2534 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2536 error_message = _(": invalid cpreg name");
2539 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2544 as_fatal (_("failed sanity check."));
2545 } /* switch on arg code. */
2547 /* Break out of for() loop. */
2549 } /* For each arg that we expect. */
2554 /* Args don't match. */
2555 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2556 && (insn->name == insn[1].name
2557 || !strcmp (insn->name, insn[1].name)))
2565 as_bad (_("Illegal operands%s"), error_message);
2566 return special_case;
2571 /* We have a match. Now see if the architecture is OK. */
2572 int needed_arch_mask = insn->architecture;
2577 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2578 if (! needed_arch_mask)
2580 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2583 if (needed_arch_mask
2584 & SPARC_OPCODE_SUPPORTED (current_architecture))
2587 /* Can we bump up the architecture? */
2588 else if (needed_arch_mask
2589 & SPARC_OPCODE_SUPPORTED (max_architecture))
2591 enum sparc_opcode_arch_val needed_architecture =
2592 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2593 & needed_arch_mask);
2595 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2597 && needed_architecture > warn_after_architecture)
2599 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2600 sparc_opcode_archs[current_architecture].name,
2601 sparc_opcode_archs[needed_architecture].name,
2603 warn_after_architecture = needed_architecture;
2605 current_architecture = needed_architecture;
2608 /* ??? This seems to be a bit fragile. What if the next entry in
2609 the opcode table is the one we want and it is supported?
2610 It is possible to arrange the table today so that this can't
2611 happen but what about tomorrow? */
2614 int arch, printed_one_p = 0;
2616 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2618 /* Create a list of the architectures that support the insn. */
2619 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2621 arch = sparc_ffs (needed_arch_mask);
2622 while ((1 << arch) <= needed_arch_mask)
2624 if ((1 << arch) & needed_arch_mask)
2628 strcpy (p, sparc_opcode_archs[arch].name);
2635 as_bad (_("Architecture mismatch on \"%s\"."), str);
2636 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2638 sparc_opcode_archs[max_architecture].name);
2639 return special_case;
2641 } /* If no match. */
2644 } /* Forever looking for a match. */
2646 the_insn.opcode = opcode;
2647 return special_case;
2650 /* Parse an argument that can be expressed as a keyword.
2651 (eg: #StoreStore or %ccfr).
2652 The result is a boolean indicating success.
2653 If successful, INPUT_POINTER is updated. */
2656 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2657 int (*lookup_fn) PARAMS ((const char *));
2658 char **input_pointerP;
2664 p = *input_pointerP;
2665 for (q = p + (*p == '#' || *p == '%');
2666 isalnum ((unsigned char) *q) || *q == '_';
2671 value = (*lookup_fn) (p);
2676 *input_pointerP = q;
2680 /* Parse an argument that is a constant expression.
2681 The result is a boolean indicating success. */
2684 parse_const_expr_arg (input_pointerP, valueP)
2685 char **input_pointerP;
2688 char *save = input_line_pointer;
2691 input_line_pointer = *input_pointerP;
2692 /* The next expression may be something other than a constant
2693 (say if we're not processing the right variant of the insn).
2694 Don't call expression unless we're sure it will succeed as it will
2695 signal an error (which we want to defer until later). */
2696 /* FIXME: It might be better to define md_operand and have it recognize
2697 things like %asi, etc. but continuing that route through to the end
2698 is a lot of work. */
2699 if (*input_line_pointer == '%')
2701 input_line_pointer = save;
2705 *input_pointerP = input_line_pointer;
2706 input_line_pointer = save;
2707 if (exp.X_op != O_constant)
2709 *valueP = exp.X_add_number;
2713 /* Subroutine of sparc_ip to parse an expression. */
2716 get_expression (str)
2722 save_in = input_line_pointer;
2723 input_line_pointer = str;
2724 seg = expression (&the_insn.exp);
2725 if (seg != absolute_section
2726 && seg != text_section
2727 && seg != data_section
2728 && seg != bss_section
2729 && seg != undefined_section)
2731 the_insn.error = _("bad segment");
2732 expr_end = input_line_pointer;
2733 input_line_pointer = save_in;
2736 expr_end = input_line_pointer;
2737 input_line_pointer = save_in;
2741 /* Subroutine of md_assemble to output one insn. */
2744 output_insn (insn, the_insn)
2745 const struct sparc_opcode *insn;
2746 struct sparc_it *the_insn;
2748 char *toP = frag_more (4);
2750 /* Put out the opcode. */
2751 if (INSN_BIG_ENDIAN)
2752 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2754 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2756 /* Put out the symbol-dependent stuff. */
2757 if (the_insn->reloc != BFD_RELOC_NONE)
2759 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2760 (toP - frag_now->fr_literal), /* Where. */
2765 /* Turn off overflow checking in fixup_segment. We'll do our
2766 own overflow checking in md_apply_fix3. This is necessary because
2767 the insn size is 4 and fixup_segment will signal an overflow for
2768 large 8 byte quantities. */
2769 fixP->fx_no_overflow = 1;
2770 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2771 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2775 last_opcode = the_insn->opcode;
2778 dwarf2_emit_insn (4);
2782 /* This is identical to the md_atof in m68k.c. I think this is right,
2785 Turn a string in input_line_pointer into a floating point constant
2786 of type TYPE, and store the appropriate bytes in *LITP. The number
2787 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2788 returned, or NULL on OK. */
2790 /* Equal to MAX_PRECISION in atof-ieee.c. */
2791 #define MAX_LITTLENUMS 6
2794 md_atof (type, litP, sizeP)
2800 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2831 return _("Bad call to MD_ATOF()");
2834 t = atof_ieee (input_line_pointer, type, words);
2836 input_line_pointer = t;
2837 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2839 if (target_big_endian)
2841 for (i = 0; i < prec; i++)
2843 md_number_to_chars (litP, (valueT) words[i],
2844 sizeof (LITTLENUM_TYPE));
2845 litP += sizeof (LITTLENUM_TYPE);
2850 for (i = prec - 1; i >= 0; i--)
2852 md_number_to_chars (litP, (valueT) words[i],
2853 sizeof (LITTLENUM_TYPE));
2854 litP += sizeof (LITTLENUM_TYPE);
2861 /* Write a value out to the object file, using the appropriate
2865 md_number_to_chars (buf, val, n)
2870 if (target_big_endian)
2871 number_to_chars_bigendian (buf, val, n);
2872 else if (target_little_endian_data
2873 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2874 /* Output debug words, which are not in allocated sections, as big
2876 number_to_chars_bigendian (buf, val, n);
2877 else if (target_little_endian_data || ! target_big_endian)
2878 number_to_chars_littleendian (buf, val, n);
2881 /* Apply a fixS to the frags, now that we know the value it ought to
2885 md_apply_fix3 (fixP, value, segment)
2890 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2896 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2898 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2901 /* FIXME: SPARC ELF relocations don't use an addend in the data
2902 field itself. This whole approach should be somehow combined
2903 with the calls to bfd_install_relocation. Also, the value passed
2904 in by fixup_segment includes the value of a defined symbol. We
2905 don't want to include the value of an externally visible symbol. */
2906 if (fixP->fx_addsy != NULL)
2908 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2909 && (S_IS_EXTERNAL (fixP->fx_addsy)
2910 || S_IS_WEAK (fixP->fx_addsy)
2911 || (sparc_pic_code && ! fixP->fx_pcrel)
2912 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2913 && ((bfd_get_section_flags (stdoutput,
2914 S_GET_SEGMENT (fixP->fx_addsy))
2915 & SEC_LINK_ONCE) != 0
2916 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2918 sizeof ".gnu.linkonce" - 1) == 0)))
2919 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2920 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2921 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2922 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2927 /* This is a hack. There should be a better way to
2928 handle this. Probably in terms of howto fields, once
2929 we can look at these fixups in terms of howtos. */
2930 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2931 val += fixP->fx_where + fixP->fx_frag->fr_address;
2934 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2935 generate a reloc, then we just want to let the reloc addend set
2936 the value. We do not want to also stuff the addend into the
2937 object file. Including the addend in the object file works when
2938 doing a static link, because the linker will ignore the object
2939 file contents. However, the dynamic linker does not ignore the
2940 object file contents. */
2941 if (fixP->fx_addsy != NULL
2942 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2945 /* When generating PIC code, we do not want an addend for a reloc
2946 against a local symbol. We adjust fx_addnumber to cancel out the
2947 value already included in val, and to also cancel out the
2948 adjustment which bfd_install_relocation will create. */
2950 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2951 && fixP->fx_addsy != NULL
2952 && ! S_IS_COMMON (fixP->fx_addsy)
2953 && symbol_section_p (fixP->fx_addsy))
2954 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2956 /* When generating PIC code, we need to fiddle to get
2957 bfd_install_relocation to do the right thing for a PC relative
2958 reloc against a local symbol which we are going to keep. */
2960 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2961 && fixP->fx_addsy != NULL
2962 && (S_IS_EXTERNAL (fixP->fx_addsy)
2963 || S_IS_WEAK (fixP->fx_addsy))
2964 && S_IS_DEFINED (fixP->fx_addsy)
2965 && ! S_IS_COMMON (fixP->fx_addsy))
2968 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2972 /* If this is a data relocation, just output VAL. */
2974 if (fixP->fx_r_type == BFD_RELOC_16)
2976 md_number_to_chars (buf, val, 2);
2978 else if (fixP->fx_r_type == BFD_RELOC_32
2979 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2981 md_number_to_chars (buf, val, 4);
2983 else if (fixP->fx_r_type == BFD_RELOC_64)
2985 md_number_to_chars (buf, val, 8);
2987 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2988 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2995 /* It's a relocation against an instruction. */
2997 if (INSN_BIG_ENDIAN)
2998 insn = bfd_getb32 ((unsigned char *) buf);
3000 insn = bfd_getl32 ((unsigned char *) buf);
3002 switch (fixP->fx_r_type)
3004 case BFD_RELOC_32_PCREL_S2:
3006 /* FIXME: This increment-by-one deserves a comment of why it's
3008 if (! sparc_pic_code
3009 || fixP->fx_addsy == NULL
3010 || symbol_section_p (fixP->fx_addsy))
3013 insn |= val & 0x3fffffff;
3015 /* See if we have a delay slot. */
3016 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3020 #define XCC (2 << 20)
3021 #define COND(x) (((x)&0xf)<<25)
3022 #define CONDA COND(0x8)
3023 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3024 #define INSN_BA (F2(0,2) | CONDA)
3025 #define INSN_OR F3(2, 0x2, 0)
3026 #define INSN_NOP F2(0,4)
3030 /* If the instruction is a call with either:
3032 arithmetic instruction with rd == %o7
3033 where rs1 != %o7 and rs2 if it is register != %o7
3034 then we can optimize if the call destination is near
3035 by changing the call into a branch always. */
3036 if (INSN_BIG_ENDIAN)
3037 delay = bfd_getb32 ((unsigned char *) buf + 4);
3039 delay = bfd_getl32 ((unsigned char *) buf + 4);
3040 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3042 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3043 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3044 || ((delay & RD (~0)) != RD (O7))))
3046 if ((delay & RS1 (~0)) == RS1 (O7)
3047 || ((delay & F3I (~0)) == 0
3048 && (delay & RS2 (~0)) == RS2 (O7)))
3050 /* Ensure the branch will fit into simm22. */
3051 if ((val & 0x3fe00000)
3052 && (val & 0x3fe00000) != 0x3fe00000)
3054 /* Check if the arch is v9 and branch will fit
3056 if (((val & 0x3c0000) == 0
3057 || (val & 0x3c0000) == 0x3c0000)
3058 && (sparc_arch_size == 64
3059 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3061 insn = INSN_BPA | (val & 0x7ffff);
3064 insn = INSN_BA | (val & 0x3fffff);
3065 if (fixP->fx_where >= 4
3066 && ((delay & (0xffffffff ^ RS1 (~0)))
3067 == (INSN_OR | RD (O7) | RS2 (G0))))
3072 if (INSN_BIG_ENDIAN)
3073 setter = bfd_getb32 ((unsigned char *) buf - 4);
3075 setter = bfd_getl32 ((unsigned char *) buf - 4);
3076 if ((setter & (0xffffffff ^ RD (~0)))
3077 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3084 If call foo was replaced with ba, replace
3085 or %rN, %g0, %o7 with nop. */
3086 reg = (delay & RS1 (~0)) >> 14;
3087 if (reg != ((setter & RD (~0)) >> 25)
3088 || reg == G0 || reg == O7)
3091 if (INSN_BIG_ENDIAN)
3092 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3094 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3099 case BFD_RELOC_SPARC_11:
3100 if (! in_signed_range (val, 0x7ff))
3101 as_bad_where (fixP->fx_file, fixP->fx_line,
3102 _("relocation overflow"));
3103 insn |= val & 0x7ff;
3106 case BFD_RELOC_SPARC_10:
3107 if (! in_signed_range (val, 0x3ff))
3108 as_bad_where (fixP->fx_file, fixP->fx_line,
3109 _("relocation overflow"));
3110 insn |= val & 0x3ff;
3113 case BFD_RELOC_SPARC_7:
3114 if (! in_bitfield_range (val, 0x7f))
3115 as_bad_where (fixP->fx_file, fixP->fx_line,
3116 _("relocation overflow"));
3120 case BFD_RELOC_SPARC_6:
3121 if (! in_bitfield_range (val, 0x3f))
3122 as_bad_where (fixP->fx_file, fixP->fx_line,
3123 _("relocation overflow"));
3127 case BFD_RELOC_SPARC_5:
3128 if (! in_bitfield_range (val, 0x1f))
3129 as_bad_where (fixP->fx_file, fixP->fx_line,
3130 _("relocation overflow"));
3134 case BFD_RELOC_SPARC_WDISP16:
3135 /* FIXME: simplify. */
3136 if (((val > 0) && (val & ~0x3fffc))
3137 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3138 as_bad_where (fixP->fx_file, fixP->fx_line,
3139 _("relocation overflow"));
3140 /* FIXME: The +1 deserves a comment. */
3141 val = (val >> 2) + 1;
3142 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3145 case BFD_RELOC_SPARC_WDISP19:
3146 /* FIXME: simplify. */
3147 if (((val > 0) && (val & ~0x1ffffc))
3148 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3149 as_bad_where (fixP->fx_file, fixP->fx_line,
3150 _("relocation overflow"));
3151 /* FIXME: The +1 deserves a comment. */
3152 val = (val >> 2) + 1;
3153 insn |= val & 0x7ffff;
3156 case BFD_RELOC_SPARC_HH22:
3157 val = BSR (val, 32);
3160 case BFD_RELOC_SPARC_LM22:
3161 case BFD_RELOC_HI22:
3162 if (!fixP->fx_addsy)
3164 insn |= (val >> 10) & 0x3fffff;
3168 /* FIXME: Need comment explaining why we do this. */
3173 case BFD_RELOC_SPARC22:
3174 if (val & ~0x003fffff)
3175 as_bad_where (fixP->fx_file, fixP->fx_line,
3176 _("relocation overflow"));
3177 insn |= (val & 0x3fffff);
3180 case BFD_RELOC_SPARC_HM10:
3181 val = BSR (val, 32);
3184 case BFD_RELOC_LO10:
3185 if (!fixP->fx_addsy)
3187 insn |= val & 0x3ff;
3191 /* FIXME: Need comment explaining why we do this. */
3196 case BFD_RELOC_SPARC_OLO10:
3198 val += fixP->tc_fix_data;
3201 case BFD_RELOC_SPARC13:
3202 if (! in_signed_range (val, 0x1fff))
3203 as_bad_where (fixP->fx_file, fixP->fx_line,
3204 _("relocation overflow"));
3205 insn |= val & 0x1fff;
3208 case BFD_RELOC_SPARC_WDISP22:
3209 val = (val >> 2) + 1;
3211 case BFD_RELOC_SPARC_BASE22:
3212 insn |= val & 0x3fffff;
3215 case BFD_RELOC_SPARC_H44:
3216 if (!fixP->fx_addsy)
3220 insn |= tval & 0x3fffff;
3224 case BFD_RELOC_SPARC_M44:
3225 if (!fixP->fx_addsy)
3226 insn |= (val >> 12) & 0x3ff;
3229 case BFD_RELOC_SPARC_L44:
3230 if (!fixP->fx_addsy)
3231 insn |= val & 0xfff;
3234 case BFD_RELOC_SPARC_HIX22:
3235 if (!fixP->fx_addsy)
3237 val ^= ~(offsetT) 0;
3238 insn |= (val >> 10) & 0x3fffff;
3242 case BFD_RELOC_SPARC_LOX10:
3243 if (!fixP->fx_addsy)
3244 insn |= 0x1c00 | (val & 0x3ff);
3247 case BFD_RELOC_NONE:
3249 as_bad_where (fixP->fx_file, fixP->fx_line,
3250 _("bad or unhandled relocation type: 0x%02x"),
3255 if (INSN_BIG_ENDIAN)
3256 bfd_putb32 (insn, (unsigned char *) buf);
3258 bfd_putl32 (insn, (unsigned char *) buf);
3261 /* Are we finished with this relocation now? */
3262 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3268 /* Translate internal representation of relocation info to BFD target
3272 tc_gen_reloc (section, fixp)
3276 static arelent *relocs[3];
3278 bfd_reloc_code_real_type code;
3280 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3283 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3284 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3285 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3287 switch (fixp->fx_r_type)
3291 case BFD_RELOC_HI22:
3292 case BFD_RELOC_LO10:
3293 case BFD_RELOC_32_PCREL_S2:
3294 case BFD_RELOC_SPARC13:
3295 case BFD_RELOC_SPARC22:
3296 case BFD_RELOC_SPARC_BASE13:
3297 case BFD_RELOC_SPARC_WDISP16:
3298 case BFD_RELOC_SPARC_WDISP19:
3299 case BFD_RELOC_SPARC_WDISP22:
3301 case BFD_RELOC_SPARC_5:
3302 case BFD_RELOC_SPARC_6:
3303 case BFD_RELOC_SPARC_7:
3304 case BFD_RELOC_SPARC_10:
3305 case BFD_RELOC_SPARC_11:
3306 case BFD_RELOC_SPARC_HH22:
3307 case BFD_RELOC_SPARC_HM10:
3308 case BFD_RELOC_SPARC_LM22:
3309 case BFD_RELOC_SPARC_PC_HH22:
3310 case BFD_RELOC_SPARC_PC_HM10:
3311 case BFD_RELOC_SPARC_PC_LM22:
3312 case BFD_RELOC_SPARC_H44:
3313 case BFD_RELOC_SPARC_M44:
3314 case BFD_RELOC_SPARC_L44:
3315 case BFD_RELOC_SPARC_HIX22:
3316 case BFD_RELOC_SPARC_LOX10:
3317 case BFD_RELOC_SPARC_REV32:
3318 case BFD_RELOC_SPARC_OLO10:
3319 case BFD_RELOC_VTABLE_ENTRY:
3320 case BFD_RELOC_VTABLE_INHERIT:
3321 code = fixp->fx_r_type;
3328 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3329 /* If we are generating PIC code, we need to generate a different
3333 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3335 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3338 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3344 case BFD_RELOC_32_PCREL_S2:
3345 if (! S_IS_DEFINED (fixp->fx_addsy)
3346 || S_IS_COMMON (fixp->fx_addsy)
3347 || S_IS_EXTERNAL (fixp->fx_addsy)
3348 || S_IS_WEAK (fixp->fx_addsy))
3349 code = BFD_RELOC_SPARC_WPLT30;
3351 case BFD_RELOC_HI22:
3352 if (fixp->fx_addsy != NULL
3353 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3354 code = BFD_RELOC_SPARC_PC22;
3356 code = BFD_RELOC_SPARC_GOT22;
3358 case BFD_RELOC_LO10:
3359 if (fixp->fx_addsy != NULL
3360 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3361 code = BFD_RELOC_SPARC_PC10;
3363 code = BFD_RELOC_SPARC_GOT10;
3365 case BFD_RELOC_SPARC13:
3366 code = BFD_RELOC_SPARC_GOT13;
3372 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3374 if (code == BFD_RELOC_SPARC_OLO10)
3375 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3377 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3378 if (reloc->howto == 0)
3380 as_bad_where (fixp->fx_file, fixp->fx_line,
3381 _("internal error: can't export reloc type %d (`%s')"),
3382 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3388 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3391 if (reloc->howto->pc_relative == 0
3392 || code == BFD_RELOC_SPARC_PC10
3393 || code == BFD_RELOC_SPARC_PC22)
3394 reloc->addend = fixp->fx_addnumber;
3395 else if (sparc_pic_code
3396 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3397 && fixp->fx_addsy != NULL
3398 && (S_IS_EXTERNAL (fixp->fx_addsy)
3399 || S_IS_WEAK (fixp->fx_addsy))
3400 && S_IS_DEFINED (fixp->fx_addsy)
3401 && ! S_IS_COMMON (fixp->fx_addsy))
3402 reloc->addend = fixp->fx_addnumber;
3404 reloc->addend = fixp->fx_offset - reloc->address;
3406 #else /* elf or coff */
3408 if (reloc->howto->pc_relative == 0
3409 || code == BFD_RELOC_SPARC_PC10
3410 || code == BFD_RELOC_SPARC_PC22)
3411 reloc->addend = fixp->fx_addnumber;
3412 else if (symbol_section_p (fixp->fx_addsy))
3413 reloc->addend = (section->vma
3414 + fixp->fx_addnumber
3415 + md_pcrel_from (fixp));
3417 reloc->addend = fixp->fx_offset;
3420 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3421 on the same location. */
3422 if (code == BFD_RELOC_SPARC_OLO10)
3424 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3427 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3429 = symbol_get_bfdsym (section_symbol (absolute_section));
3430 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3431 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3432 reloc->addend = fixp->tc_fix_data;
3438 /* We have no need to default values of symbols. */
3441 md_undefined_symbol (name)
3442 char *name ATTRIBUTE_UNUSED;
3447 /* Round up a section size to the appropriate boundary. */
3450 md_section_align (segment, size)
3451 segT segment ATTRIBUTE_UNUSED;
3455 /* This is not right for ELF; a.out wants it, and COFF will force
3456 the alignment anyways. */
3457 valueT align = ((valueT) 1
3458 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3461 /* Turn alignment value into a mask. */
3463 newsize = (size + align) & ~align;
3470 /* Exactly what point is a PC-relative offset relative TO?
3471 On the sparc, they're relative to the address of the offset, plus
3472 its size. This gets us to the following instruction.
3473 (??? Is this right? FIXME-SOON) */
3475 md_pcrel_from (fixP)
3480 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3481 if (! sparc_pic_code
3482 || fixP->fx_addsy == NULL
3483 || symbol_section_p (fixP->fx_addsy))
3484 ret += fixP->fx_size;
3488 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3500 for (shift = 0; (value & 1) == 0; value >>= 1)
3503 return (value == 1) ? shift : -1;
3506 /* Sort of like s_lcomm. */
3509 static int max_alignment = 15;
3514 int ignore ATTRIBUTE_UNUSED;
3524 name = input_line_pointer;
3525 c = get_symbol_end ();
3526 p = input_line_pointer;
3530 if (*input_line_pointer != ',')
3532 as_bad (_("Expected comma after name"));
3533 ignore_rest_of_line ();
3537 ++input_line_pointer;
3539 if ((size = get_absolute_expression ()) < 0)
3541 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3542 ignore_rest_of_line ();
3547 symbolP = symbol_find_or_make (name);
3550 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3551 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3553 as_bad (_("bad .reserve segment -- expected BSS segment"));
3557 if (input_line_pointer[2] == '.')
3558 input_line_pointer += 7;
3560 input_line_pointer += 6;
3563 if (*input_line_pointer == ',')
3565 ++input_line_pointer;
3568 if (*input_line_pointer == '\n')
3570 as_bad (_("missing alignment"));
3571 ignore_rest_of_line ();
3575 align = (int) get_absolute_expression ();
3578 if (align > max_alignment)
3580 align = max_alignment;
3581 as_warn (_("alignment too large; assuming %d"), align);
3587 as_bad (_("negative alignment"));
3588 ignore_rest_of_line ();
3594 temp = log2 (align);
3597 as_bad (_("alignment not a power of 2"));
3598 ignore_rest_of_line ();
3605 record_alignment (bss_section, align);
3610 if (!S_IS_DEFINED (symbolP)
3612 && S_GET_OTHER (symbolP) == 0
3613 && S_GET_DESC (symbolP) == 0
3620 segT current_seg = now_seg;
3621 subsegT current_subseg = now_subseg;
3623 /* Switch to bss. */
3624 subseg_set (bss_section, 1);
3628 frag_align (align, 0, 0);
3630 /* Detach from old frag. */
3631 if (S_GET_SEGMENT (symbolP) == bss_section)
3632 symbol_get_frag (symbolP)->fr_symbol = NULL;
3634 symbol_set_frag (symbolP, frag_now);
3635 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3636 (offsetT) size, (char *) 0);
3639 S_SET_SEGMENT (symbolP, bss_section);
3641 subseg_set (current_seg, current_subseg);
3644 S_SET_SIZE (symbolP, size);
3650 as_warn ("Ignoring attempt to re-define symbol %s",
3651 S_GET_NAME (symbolP));
3652 } /* if not redefining. */
3654 demand_empty_rest_of_line ();
3659 int ignore ATTRIBUTE_UNUSED;
3667 name = input_line_pointer;
3668 c = get_symbol_end ();
3669 /* Just after name is now '\0'. */
3670 p = input_line_pointer;
3673 if (*input_line_pointer != ',')
3675 as_bad (_("Expected comma after symbol-name"));
3676 ignore_rest_of_line ();
3681 input_line_pointer++;
3683 if ((temp = get_absolute_expression ()) < 0)
3685 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3686 ignore_rest_of_line ();
3691 symbolP = symbol_find_or_make (name);
3693 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3695 as_bad (_("Ignoring attempt to re-define symbol"));
3696 ignore_rest_of_line ();
3699 if (S_GET_VALUE (symbolP) != 0)
3701 if (S_GET_VALUE (symbolP) != (valueT) size)
3703 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3704 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3710 S_SET_VALUE (symbolP, (valueT) size);
3711 S_SET_EXTERNAL (symbolP);
3714 know (symbol_get_frag (symbolP) == &zero_address_frag);
3715 if (*input_line_pointer != ',')
3717 as_bad (_("Expected comma after common length"));
3718 ignore_rest_of_line ();
3721 input_line_pointer++;
3723 if (*input_line_pointer != '"')
3725 temp = get_absolute_expression ();
3728 if (temp > max_alignment)
3730 temp = max_alignment;
3731 as_warn (_("alignment too large; assuming %d"), temp);
3737 as_bad (_("negative alignment"));
3738 ignore_rest_of_line ();
3743 if (symbol_get_obj (symbolP)->local)
3751 old_subsec = now_subseg;
3756 align = log2 (temp);
3760 as_bad (_("alignment not a power of 2"));
3761 ignore_rest_of_line ();
3765 record_alignment (bss_section, align);
3766 subseg_set (bss_section, 0);
3768 frag_align (align, 0, 0);
3769 if (S_GET_SEGMENT (symbolP) == bss_section)
3770 symbol_get_frag (symbolP)->fr_symbol = 0;
3771 symbol_set_frag (symbolP, frag_now);
3772 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3773 (offsetT) size, (char *) 0);
3775 S_SET_SEGMENT (symbolP, bss_section);
3776 S_CLEAR_EXTERNAL (symbolP);
3777 S_SET_SIZE (symbolP, size);
3778 subseg_set (old_sec, old_subsec);
3781 #endif /* OBJ_ELF */
3784 S_SET_VALUE (symbolP, (valueT) size);
3786 S_SET_ALIGN (symbolP, temp);
3787 S_SET_SIZE (symbolP, size);
3789 S_SET_EXTERNAL (symbolP);
3790 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3795 input_line_pointer++;
3796 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3797 if (*input_line_pointer == '.')
3798 input_line_pointer++;
3799 /* @@ Some say data, some say bss. */
3800 if (strncmp (input_line_pointer, "bss\"", 4)
3801 && strncmp (input_line_pointer, "data\"", 5))
3803 while (*--input_line_pointer != '"')
3805 input_line_pointer--;
3806 goto bad_common_segment;
3808 while (*input_line_pointer++ != '"')
3810 goto allocate_common;
3813 #ifdef BFD_ASSEMBLER
3814 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3817 demand_empty_rest_of_line ();
3822 p = input_line_pointer;
3823 while (*p && *p != '\n')
3827 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3829 input_line_pointer = p;
3830 ignore_rest_of_line ();
3835 /* Handle the .empty pseudo-op. This supresses the warnings about
3836 invalid delay slot usage. */
3840 int ignore ATTRIBUTE_UNUSED;
3842 /* The easy way to implement is to just forget about the last
3849 int ignore ATTRIBUTE_UNUSED;
3852 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3854 input_line_pointer += 6;
3858 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3860 input_line_pointer += 6;
3864 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3866 input_line_pointer += 7;
3870 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3872 input_line_pointer += 5;
3873 /* We only support 2 segments -- text and data -- for now, so
3874 things in the "bss segment" will have to go into data for now.
3875 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3876 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3879 as_bad (_("Unknown segment type"));
3880 demand_empty_rest_of_line ();
3886 subseg_set (data_section, 1);
3887 demand_empty_rest_of_line ();
3892 int ignore ATTRIBUTE_UNUSED;
3894 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3896 ++input_line_pointer;
3898 ++input_line_pointer;
3901 /* This static variable is set by s_uacons to tell sparc_cons_align
3902 that the expession does not need to be aligned. */
3904 static int sparc_no_align_cons = 0;
3906 /* This handles the unaligned space allocation pseudo-ops, such as
3907 .uaword. .uaword is just like .word, but the value does not need
3914 /* Tell sparc_cons_align not to align this value. */
3915 sparc_no_align_cons = 1;
3919 /* This handles the native word allocation pseudo-op .nword.
3920 For sparc_arch_size 32 it is equivalent to .word, for
3921 sparc_arch_size 64 it is equivalent to .xword. */
3925 int bytes ATTRIBUTE_UNUSED;
3927 cons (sparc_arch_size == 32 ? 4 : 8);
3931 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3935 .register %g[2367],{#scratch|symbolname|#ignore}
3940 int ignore ATTRIBUTE_UNUSED;
3945 const char *regname;
3947 if (input_line_pointer[0] != '%'
3948 || input_line_pointer[1] != 'g'
3949 || ((input_line_pointer[2] & ~1) != '2'
3950 && (input_line_pointer[2] & ~1) != '6')
3951 || input_line_pointer[3] != ',')
3952 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3953 reg = input_line_pointer[2] - '0';
3954 input_line_pointer += 4;
3956 if (*input_line_pointer == '#')
3958 ++input_line_pointer;
3959 regname = input_line_pointer;
3960 c = get_symbol_end ();
3961 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3962 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3963 if (regname[0] == 'i')
3970 regname = input_line_pointer;
3971 c = get_symbol_end ();
3973 if (sparc_arch_size == 64)
3977 if ((regname && globals[reg] != (symbolS *) 1
3978 && strcmp (S_GET_NAME (globals[reg]), regname))
3979 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3980 as_bad (_("redefinition of global register"));
3984 if (regname == NULL)
3985 globals[reg] = (symbolS *) 1;
3990 if (symbol_find (regname))
3991 as_bad (_("Register symbol %s already defined."),
3994 globals[reg] = symbol_make (regname);
3995 flags = symbol_get_bfdsym (globals[reg])->flags;
3997 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3998 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3999 flags |= BSF_GLOBAL;
4000 symbol_get_bfdsym (globals[reg])->flags = flags;
4001 S_SET_VALUE (globals[reg], (valueT) reg);
4002 S_SET_ALIGN (globals[reg], reg);
4003 S_SET_SIZE (globals[reg], 0);
4004 /* Although we actually want undefined_section here,
4005 we have to use absolute_section, because otherwise
4006 generic as code will make it a COM section.
4007 We fix this up in sparc_adjust_symtab. */
4008 S_SET_SEGMENT (globals[reg], absolute_section);
4009 S_SET_OTHER (globals[reg], 0);
4010 elf_symbol (symbol_get_bfdsym (globals[reg]))
4011 ->internal_elf_sym.st_info =
4012 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4013 elf_symbol (symbol_get_bfdsym (globals[reg]))
4014 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4019 *input_line_pointer = c;
4021 demand_empty_rest_of_line ();
4024 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4025 symbols which need it. */
4028 sparc_adjust_symtab ()
4032 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4034 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4035 ->internal_elf_sym.st_info) != STT_REGISTER)
4038 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4039 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4042 S_SET_SEGMENT (sym, undefined_section);
4047 /* If the --enforce-aligned-data option is used, we require .word,
4048 et. al., to be aligned correctly. We do it by setting up an
4049 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4050 no unexpected alignment was introduced.
4052 The SunOS and Solaris native assemblers enforce aligned data by
4053 default. We don't want to do that, because gcc can deliberately
4054 generate misaligned data if the packed attribute is used. Instead,
4055 we permit misaligned data by default, and permit the user to set an
4056 option to check for it. */
4059 sparc_cons_align (nbytes)
4065 /* Only do this if we are enforcing aligned data. */
4066 if (! enforce_aligned_data)
4069 if (sparc_no_align_cons)
4071 /* This is an unaligned pseudo-op. */
4072 sparc_no_align_cons = 0;
4076 nalign = log2 (nbytes);
4080 assert (nalign > 0);
4082 if (now_seg == absolute_section)
4084 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4085 as_bad (_("misaligned data"));
4089 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4090 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4092 record_alignment (now_seg, nalign);
4095 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4098 sparc_handle_align (fragp)
4104 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4106 switch (fragp->fr_type)
4110 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4114 p = fragp->fr_literal + fragp->fr_fix;
4125 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4127 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4128 if (INSN_BIG_ENDIAN)
4129 number_to_chars_bigendian (p, wval, 4);
4131 number_to_chars_littleendian (p, wval, 4);
4137 if (INSN_BIG_ENDIAN)
4138 number_to_chars_bigendian (p, 0x01000000, 4);
4140 number_to_chars_littleendian (p, 0x01000000, 4);
4142 fragp->fr_fix += fix;
4152 /* Some special processing for a Sparc ELF file. */
4155 sparc_elf_final_processing ()
4157 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4158 sort of BFD interface for this. */
4159 if (sparc_arch_size == 64)
4161 switch (sparc_memory_model)
4164 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4167 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4173 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4174 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4175 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4176 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4177 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4178 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4182 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4183 reloc for a cons. We could use the definition there, except that
4184 we want to handle little endian relocs specially. */
4187 cons_fix_new_sparc (frag, where, nbytes, exp)
4190 unsigned int nbytes;
4193 bfd_reloc_code_real_type r;
4195 r = (nbytes == 1 ? BFD_RELOC_8 :
4196 (nbytes == 2 ? BFD_RELOC_16 :
4197 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4199 if (target_little_endian_data && nbytes == 4
4200 && now_seg->flags & SEC_ALLOC)
4201 r = BFD_RELOC_SPARC_REV32;
4202 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4207 elf32_sparc_force_relocation (fixp)
4210 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4211 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)