1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch *lookup_arch PARAMS ((char *));
33 static void init_default_arch PARAMS ((void));
34 static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
35 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
36 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
37 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38 static int sparc_ffs PARAMS ((unsigned int));
39 static bfd_vma BSR PARAMS ((bfd_vma, int));
40 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
41 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
42 static int parse_const_expr_arg PARAMS ((char **, int *));
43 static int get_expression PARAMS ((char *str));
45 /* Default architecture. */
46 /* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
50 #define DEFAULT_ARCH "sparclite"
52 static char *default_arch = DEFAULT_ARCH;
54 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 static int default_init_p;
58 /* Current architecture. We don't bump up unless necessary. */
59 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61 /* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
63 The native assembler works this way. The user is required to pass
64 an explicit argument before we'll create v9 object files. However, if
65 we don't see any v9 insns, a v8plus object file is not created. */
66 static enum sparc_opcode_arch_val max_architecture;
68 /* Either 32 or 64, selects file format. */
69 static int sparc_arch_size;
70 /* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72 static int default_arch_size;
75 /* The currently selected v9 memory model. Currently only used for
77 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
80 static int architecture_requested;
81 static int warn_on_bump;
83 /* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85 static enum sparc_opcode_arch_val warn_after_architecture;
87 /* Non-zero if we are generating PIC code. */
90 /* Non-zero if we should give an error when misaligned data is seen. */
91 static int enforce_aligned_data;
93 extern int target_big_endian;
95 static int target_little_endian_data;
97 /* V9 and 86x have big and little endian data, but instructions are always big
98 endian. The sparclet has bi-endian support but both data and insns have
99 the same endianness. Global `target_big_endian' is used for data.
100 The following macro is used for instructions. */
101 #ifndef INSN_BIG_ENDIAN
102 #define INSN_BIG_ENDIAN (target_big_endian \
103 || default_arch_type == sparc86x \
104 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
107 /* handle of the OPCODE hash table */
108 static struct hash_control *op_hash;
110 static int log2 PARAMS ((int));
111 static void s_data1 PARAMS ((void));
112 static void s_seg PARAMS ((int));
113 static void s_proc PARAMS ((int));
114 static void s_reserve PARAMS ((int));
115 static void s_common PARAMS ((int));
116 static void s_empty PARAMS ((int));
117 static void s_uacons PARAMS ((int));
119 const pseudo_typeS md_pseudo_table[] =
121 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
122 {"common", s_common, 0},
123 {"empty", s_empty, 0},
124 {"global", s_globl, 0},
126 {"optim", s_ignore, 0},
128 {"reserve", s_reserve, 0},
130 {"skip", s_space, 0},
133 {"uahalf", s_uacons, 2},
134 {"uaword", s_uacons, 4},
135 {"uaxword", s_uacons, 8},
137 /* these are specific to sparc/svr4 */
138 {"pushsection", obj_elf_section, 0},
139 {"popsection", obj_elf_previous, 0},
140 {"2byte", s_uacons, 2},
141 {"4byte", s_uacons, 4},
142 {"8byte", s_uacons, 8},
147 const int md_reloc_size = 12; /* Size of relocation record */
149 /* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
151 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
153 /* This array holds the chars that only start a comment at the beginning of
154 a line. If the line seems to have the form '# 123 filename'
155 .line and .file directives will appear in the pre-processed output */
156 /* Note that input_file.c hand checks for '#' at the beginning of the
157 first line of the input file. This is because the compiler outputs
158 #NO_APP at the beginning of its output. */
159 /* Also note that comments started like this one will always
160 work if '/' isn't otherwise defined. */
161 const char line_comment_chars[] = "#";
163 const char line_separator_chars[] = "";
165 /* Chars that can be used to separate mant from exp in floating point nums */
166 const char EXP_CHARS[] = "eE";
168 /* Chars that mean this number is a floating point constant */
171 const char FLT_CHARS[] = "rRsSfFdDxXpP";
173 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
174 changed in read.c. Ideally it shouldn't have to know about it at all,
175 but nothing is ideal around here. */
177 static unsigned char octal[256];
178 #define isoctal(c) octal[(unsigned char) (c)]
179 static unsigned char toHex[256];
184 unsigned long opcode;
185 struct nlist *nlistp;
188 bfd_reloc_code_real_type reloc;
191 struct sparc_it the_insn, set_insn;
193 static void output_insn
194 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
196 /* Table of arguments to -A.
197 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
198 for this use. That table is for opcodes only. This table is for opcodes
201 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
202 v8plusa, v9, v9a, v9_64};
204 static struct sparc_arch {
207 enum sparc_arch_types arch_type;
208 /* Default word size, as specified during configuration.
209 A value of zero means can't be used to specify default architecture. */
210 int default_arch_size;
211 /* Allowable arg to -A? */
213 } sparc_arch_table[] = {
214 { "v6", "v6", v6, 0, 1 },
215 { "v7", "v7", v7, 0, 1 },
216 { "v8", "v8", v8, 32, 1 },
217 { "sparclet", "sparclet", sparclet, 32, 1 },
218 { "sparclite", "sparclite", sparclite, 32, 1 },
219 { "sparc86x", "sparclite", sparc86x, 32, 1 },
220 { "v8plus", "v9", v9, 0, 1 },
221 { "v8plusa", "v9a", v9, 0, 1 },
222 { "v9", "v9", v9, 0, 1 },
223 { "v9a", "v9a", v9, 0, 1 },
224 /* This exists to allow configure.in/Makefile.in to pass one
225 value to specify both the default machine and default word size. */
226 { "v9-64", "v9", v9, 64, 0 },
227 { NULL, NULL, v8, 0, 0 }
230 /* Variant of default_arch */
231 static enum sparc_arch_types default_arch_type;
233 static struct sparc_arch *
237 struct sparc_arch *sa;
239 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
240 if (strcmp (sa->name, name) == 0)
242 if (sa->name == NULL)
247 /* Initialize the default opcode arch and word size from the default
248 architecture name. */
253 struct sparc_arch *sa = lookup_arch (default_arch);
256 || sa->default_arch_size == 0)
257 as_fatal (_("Invalid default architecture, broken assembler."));
259 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
260 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
261 as_fatal (_("Bad opcode table, broken assembler."));
262 default_arch_size = sparc_arch_size = sa->default_arch_size;
264 default_arch_type = sa->arch_type;
267 /* Called by TARGET_FORMAT. */
270 sparc_target_format ()
272 /* We don't get a chance to initialize anything before we're called,
273 so handle that now. */
274 if (! default_init_p)
275 init_default_arch ();
279 return "a.out-sparc-netbsd";
282 if (target_big_endian)
283 return "a.out-sunos-big";
284 else if (default_arch_type == sparc86x && target_little_endian_data)
285 return "a.out-sunos-big";
286 else return "a.out-sparc-little";
288 return "a.out-sunos-big";
299 return "coff-sparc-lynx";
306 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
314 * Invocation line includes a switch not recognized by the base assembler.
315 * See if it's a processor-specific option. These are:
318 * Warn on architecture bumps. See also -A.
320 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
321 * Standard 32 bit architectures.
322 * -Av8plus, -Av8plusa
323 * Sparc64 in a 32 bit world.
325 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
326 * This used to only mean 64 bits, but properly specifying it
327 * complicated gcc's ASM_SPECs, so now opcode selection is
328 * specified orthogonally to word size (except when specifying
329 * the default, but that is an internal implementation detail).
330 * -xarch=v8plus, -xarch=v8plusa
331 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
333 * Select the architecture and possibly the file format.
334 * Instructions or features not supported by the selected
335 * architecture cause fatal errors.
337 * The default is to start at v6, and bump the architecture up
338 * whenever an instruction is seen at a higher level. In 32 bit
339 * environments, v9 is not bumped up to, the user must pass
342 * If -bump is specified, a warning is printing when bumping to
345 * If an architecture is specified, all instructions must match
346 * that architecture. Any higher level instructions are flagged
347 * as errors. Note that in the 32 bit environment specifying
348 * -Av8plus does not automatically create a v8plus object file, a
349 * v9 insn must be seen.
351 * If both an architecture and -bump are specified, the
352 * architecture starts at the specified level, but bumps are
353 * warnings. Note that we can't set `current_architecture' to
354 * the requested level in this case: in the 32 bit environment,
355 * we still must avoid creating v8plus object files unless v9
359 * Bumping between incompatible architectures is always an
360 * error. For example, from sparclite to v9.
364 CONST char *md_shortopts = "A:K:VQ:sq";
367 CONST char *md_shortopts = "A:k";
369 CONST char *md_shortopts = "A:";
372 struct option md_longopts[] = {
373 #define OPTION_BUMP (OPTION_MD_BASE)
374 {"bump", no_argument, NULL, OPTION_BUMP},
375 #define OPTION_SPARC (OPTION_MD_BASE + 1)
376 {"sparc", no_argument, NULL, OPTION_SPARC},
377 #define OPTION_XARCH (OPTION_MD_BASE + 2)
378 {"xarch", required_argument, NULL, OPTION_XARCH},
380 #define OPTION_32 (OPTION_MD_BASE + 3)
381 {"32", no_argument, NULL, OPTION_32},
382 #define OPTION_64 (OPTION_MD_BASE + 4)
383 {"64", no_argument, NULL, OPTION_64},
384 #define OPTION_TSO (OPTION_MD_BASE + 5)
385 {"TSO", no_argument, NULL, OPTION_TSO},
386 #define OPTION_PSO (OPTION_MD_BASE + 6)
387 {"PSO", no_argument, NULL, OPTION_PSO},
388 #define OPTION_RMO (OPTION_MD_BASE + 7)
389 {"RMO", no_argument, NULL, OPTION_RMO},
391 #ifdef SPARC_BIENDIAN
392 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
393 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
394 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
395 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
397 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
398 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
399 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
400 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
401 {NULL, no_argument, NULL, 0}
403 size_t md_longopts_size = sizeof(md_longopts);
406 md_parse_option (c, arg)
410 /* We don't get a chance to initialize anything before we're called,
411 so handle that now. */
412 if (! default_init_p)
413 init_default_arch ();
419 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
423 /* This is for compatibility with Sun's assembler. */
424 if (strcmp (arg, "v8plus") != 0
425 && strcmp (arg, "v8plusa") != 0)
427 as_bad (_("invalid architecture -xarch=%s"), arg);
435 struct sparc_arch *sa;
436 enum sparc_opcode_arch_val opcode_arch;
438 sa = lookup_arch (arg);
440 || ! sa->user_option_p)
442 as_bad (_("invalid architecture -A%s"), arg);
446 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
447 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
448 as_fatal (_("Bad opcode table, broken assembler."));
450 max_architecture = opcode_arch;
451 architecture_requested = 1;
456 /* Ignore -sparc, used by SunOS make default .s.o rule. */
459 case OPTION_ENFORCE_ALIGNED_DATA:
460 enforce_aligned_data = 1;
463 #ifdef SPARC_BIENDIAN
464 case OPTION_LITTLE_ENDIAN:
465 target_big_endian = 0;
466 if (default_arch_type != sparclet)
467 as_fatal ("This target does not support -EL");
469 case OPTION_LITTLE_ENDIAN_DATA:
470 target_little_endian_data = 1;
471 target_big_endian = 0;
472 if (default_arch_type != sparc86x
473 && default_arch_type != v9)
474 as_fatal ("This target does not support --little-endian-data");
476 case OPTION_BIG_ENDIAN:
477 target_big_endian = 1;
491 const char **list, **l;
493 sparc_arch_size = c == OPTION_32 ? 32 : 64;
494 list = bfd_target_list ();
495 for (l = list; *l != NULL; l++)
497 if (sparc_arch_size == 32)
499 if (strcmp (*l, "elf32-sparc") == 0)
504 if (strcmp (*l, "elf64-sparc") == 0)
509 as_fatal (_("No compiled in support for %d bit object file format"),
516 sparc_memory_model = MM_TSO;
520 sparc_memory_model = MM_PSO;
524 sparc_memory_model = MM_RMO;
532 /* Qy - do emit .comment
533 Qn - do not emit .comment */
537 /* use .stab instead of .stab.excl */
541 /* quick -- native assembler does fewer checks */
545 if (strcmp (arg, "PIC") != 0)
546 as_warn (_("Unrecognized option following -K"));
560 md_show_usage (stream)
563 const struct sparc_arch *arch;
565 /* We don't get a chance to initialize anything before we're called,
566 so handle that now. */
567 if (! default_init_p)
568 init_default_arch ();
570 fprintf(stream, _("SPARC options:\n"));
571 for (arch = &sparc_arch_table[0]; arch->name; arch++)
573 if (arch != &sparc_arch_table[0])
574 fprintf (stream, " | ");
575 if (arch->user_option_p)
576 fprintf (stream, "-A%s", arch->name);
578 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
579 fprintf (stream, _("\
580 specify variant of SPARC architecture\n\
581 -bump warn when assembler switches architectures\n\
583 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
585 fprintf (stream, _("\
586 -k generate PIC\n"));
589 fprintf (stream, _("\
590 -32 create 32 bit object file\n\
591 -64 create 64 bit object file\n"));
592 fprintf (stream, _("\
593 [default is %d]\n"), default_arch_size);
594 fprintf (stream, _("\
595 -TSO use Total Store Ordering\n\
596 -PSO use Partial Store Ordering\n\
597 -RMO use Relaxed Memory Ordering\n"));
598 fprintf (stream, _("\
599 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
600 fprintf (stream, _("\
601 -KPIC generate PIC\n\
602 -V print assembler version number\n\
607 #ifdef SPARC_BIENDIAN
608 fprintf (stream, _("\
609 -EL generate code for a little endian machine\n\
610 -EB generate code for a big endian machine\n\
611 --little-endian-data generate code for a machine having big endian\n\
612 instructions and little endian data."));
616 /* sparc64 priviledged registers */
618 struct priv_reg_entry
624 struct priv_reg_entry priv_reg_table[] =
643 {"", -1}, /* end marker */
646 /* v9a specific asrs */
648 struct priv_reg_entry v9a_asr_table[] =
657 {"clear_softint", 21},
658 {"", -1}, /* end marker */
662 cmp_reg_entry (parg, qarg)
666 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
667 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
669 return strcmp (q->name, p->name);
672 /* This function is called once, at assembler startup time. It should
673 set up all the tables, etc. that the MD part of the assembler will need. */
678 register const char *retval = NULL;
680 register unsigned int i = 0;
682 /* We don't get a chance to initialize anything before md_parse_option
683 is called, and it may not be called, so handle default initialization
684 now if not already done. */
685 if (! default_init_p)
686 init_default_arch ();
688 op_hash = hash_new ();
690 while (i < (unsigned int) sparc_num_opcodes)
692 const char *name = sparc_opcodes[i].name;
693 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
696 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
697 sparc_opcodes[i].name, retval);
702 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
704 fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
705 sparc_opcodes[i].name, sparc_opcodes[i].args);
710 while (i < (unsigned int) sparc_num_opcodes
711 && !strcmp (sparc_opcodes[i].name, name));
715 as_fatal (_("Broken assembler. No assembly attempted."));
717 for (i = '0'; i < '8'; ++i)
719 for (i = '0'; i <= '9'; ++i)
721 for (i = 'a'; i <= 'f'; ++i)
722 toHex[i] = i + 10 - 'a';
723 for (i = 'A'; i <= 'F'; ++i)
724 toHex[i] = i + 10 - 'A';
726 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
727 sizeof (priv_reg_table[0]), cmp_reg_entry);
729 /* If -bump, record the architecture level at which we start issuing
730 warnings. The behaviour is different depending upon whether an
731 architecture was explicitly specified. If it wasn't, we issue warnings
732 for all upwards bumps. If it was, we don't start issuing warnings until
733 we need to bump beyond the requested architecture or when we bump between
734 conflicting architectures. */
737 && architecture_requested)
739 /* `max_architecture' records the requested architecture.
740 Issue warnings if we go above it. */
741 warn_after_architecture = max_architecture;
743 /* Find the highest architecture level that doesn't conflict with
744 the requested one. */
745 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
746 max_architecture > warn_after_architecture;
748 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
749 warn_after_architecture))
754 /* Called after all assembly has been done. */
759 if (sparc_arch_size == 64)
761 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
762 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
764 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
768 if (current_architecture == SPARC_OPCODE_ARCH_V9)
769 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
770 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
771 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
772 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
773 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
774 else if (default_arch_type == sparc86x && target_little_endian_data)
775 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
778 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
779 be but for now it is (since that's the way it's always been
781 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
786 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
789 in_signed_range (val, max)
790 bfd_signed_vma val, max;
801 /* Return non-zero if VAL is in the range 0 to MAX. */
804 in_unsigned_range (val, max)
812 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
813 (e.g. -15 to +31). */
816 in_bitfield_range (val, max)
817 bfd_signed_vma val, max;
823 if (val < ~(max >> 1))
837 for (i = 0; (mask & 1) == 0; ++i)
842 /* Implement big shift right. */
848 if (sizeof (bfd_vma) <= 4 && amount >= 32)
849 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
850 return val >> amount;
853 /* For communication between sparc_ip and get_expression. */
854 static char *expr_end;
856 /* For communication between md_assemble and sparc_ip. */
857 static int special_case;
859 /* Values for `special_case'.
860 Instructions that require wierd handling because they're longer than
862 #define SPECIAL_CASE_NONE 0
863 #define SPECIAL_CASE_SET 1
864 #define SPECIAL_CASE_SETSW 2
865 #define SPECIAL_CASE_SETX 3
866 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
867 #define SPECIAL_CASE_FDIV 4
869 /* Bit masks of various insns. */
870 #define NOP_INSN 0x01000000
871 #define OR_INSN 0x80100000
872 #define FMOVS_INSN 0x81A00020
873 #define SETHI_INSN 0x01000000
874 #define SLLX_INSN 0x81281000
875 #define SRA_INSN 0x81380000
877 /* The last instruction to be assembled. */
878 static const struct sparc_opcode *last_insn;
879 /* The assembled opcode of `last_insn'. */
880 static unsigned long last_opcode;
882 /* Main entry point to assemble one instruction. */
888 const struct sparc_opcode *insn;
891 special_case = SPECIAL_CASE_NONE;
892 sparc_ip (str, &insn);
894 /* We warn about attempts to put a floating point branch in a delay slot,
895 unless the delay slot has been annulled. */
898 && (insn->flags & F_FBR) != 0
899 && (last_insn->flags & F_DELAYED) != 0
900 /* ??? This test isn't completely accurate. We assume anything with
901 F_{UNBR,CONDBR,FBR} set is annullable. */
902 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
903 || (last_opcode & ANNUL) == 0))
904 as_warn (_("FP branch in delay slot"));
906 /* SPARC before v9 requires a nop instruction between a floating
907 point instruction and a floating point branch. We insert one
908 automatically, with a warning. */
909 if (max_architecture < SPARC_OPCODE_ARCH_V9
912 && (insn->flags & F_FBR) != 0
913 && (last_insn->flags & F_FLOAT) != 0)
915 struct sparc_it nop_insn;
917 nop_insn.opcode = NOP_INSN;
918 nop_insn.reloc = BFD_RELOC_NONE;
919 output_insn (insn, &nop_insn);
920 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
923 switch (special_case)
925 case SPECIAL_CASE_NONE:
927 output_insn (insn, &the_insn);
930 case SPECIAL_CASE_SET:
934 /* "set" is not defined for negative numbers in v9: it doesn't yield
935 what you expect it to. */
936 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
937 && the_insn.exp.X_op == O_constant)
939 if (the_insn.exp.X_add_number < 0)
940 as_warn (_("set: used with negative number"));
941 else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff)
942 as_warn (_("set: number larger than 4294967295"));
945 /* See if operand is absolute and small; skip sethi if so. */
946 if (the_insn.exp.X_op != O_constant
947 || the_insn.exp.X_add_number >= (1 << 12)
948 || the_insn.exp.X_add_number < -(1 << 12))
950 output_insn (insn, &the_insn);
953 /* See if operand has no low-order bits; skip OR if so. */
954 if (the_insn.exp.X_op != O_constant
955 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
958 int rd = (the_insn.opcode & RD (~0)) >> 25;
959 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
962 | (the_insn.exp.X_add_number
963 & (need_hi22_p ? 0x3ff : 0x1fff)));
964 the_insn.reloc = (the_insn.exp.X_op != O_constant
967 output_insn (insn, &the_insn);
972 case SPECIAL_CASE_SETSW:
974 /* FIXME: Not finished. */
978 case SPECIAL_CASE_SETX:
980 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
981 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
982 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
984 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
985 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
986 /* Output directly to dst reg if lower 32 bits are all zero. */
987 int upper_dstreg = (the_insn.exp.X_op == O_constant
988 && lower32 == 0) ? dstreg : tmpreg;
989 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
991 /* The tmp reg should not be the dst reg. */
992 if (tmpreg == dstreg)
993 as_warn (_("setx: temporary register same as destination register"));
995 /* Reset X_add_number, we've extracted it as upper32/lower32.
996 Otherwise fixup_segment will complain about not being able to
997 write an 8 byte number in a 4 byte field. */
998 the_insn.exp.X_add_number = 0;
1000 /* ??? Obviously there are other optimizations we can do
1001 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1002 doing some of these. Later. If you do change things, try to
1003 change all of this to be table driven as well. */
1005 /* What to output depends on the number if it's constant.
1006 Compute that first, then output what we've decided upon. */
1007 if (the_insn.exp.X_op != O_constant)
1008 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1011 /* Only need hh22 if `or' insn can't handle constant. */
1012 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1015 /* Does bottom part (after sethi) have bits? */
1016 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1017 /* No hh22, but does upper32 still have bits we can't set
1021 && (upper32 != -1 || lower32 >= 0)))
1024 /* If the lower half is all zero, we build the upper half directly
1025 into the dst reg. */
1027 /* Need lower half if number is zero. */
1028 || (! need_hh22_p && ! need_hm10_p))
1030 /* No need for sethi if `or' insn can handle constant. */
1031 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1032 /* Note that we can't use a negative constant in the `or'
1033 insn unless the upper 32 bits are all ones. */
1034 || (lower32 < 0 && upper32 != -1))
1037 /* Does bottom part (after sethi) have bits? */
1038 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1040 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1041 /* Need `or' if we didn't set anything else. */
1042 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1049 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1050 | ((upper32 >> 10) & 0x3fffff));
1051 the_insn.reloc = (the_insn.exp.X_op != O_constant
1052 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1053 output_insn (insn, &the_insn);
1058 the_insn.opcode = (OR_INSN
1059 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1063 & (need_hh22_p ? 0x3ff : 0x1fff)));
1064 the_insn.reloc = (the_insn.exp.X_op != O_constant
1065 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1066 output_insn (insn, &the_insn);
1071 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1072 | ((lower32 >> 10) & 0x3fffff));
1073 the_insn.reloc = BFD_RELOC_HI22;
1074 output_insn (insn, &the_insn);
1079 /* FIXME: One nice optimization to do here is to OR the low part
1080 with the highpart if hi22 isn't needed and the low part is
1082 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1086 & (need_hi22_p ? 0x3ff : 0x1fff)));
1087 the_insn.reloc = BFD_RELOC_LO10;
1088 output_insn (insn, &the_insn);
1091 /* If we needed to build the upper part, shift it into place. */
1092 if (need_hh22_p || need_hm10_p)
1094 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1096 the_insn.reloc = BFD_RELOC_NONE;
1097 output_insn (insn, &the_insn);
1100 /* If we needed to build both upper and lower parts, OR them together. */
1101 if ((need_hh22_p || need_hm10_p)
1102 && (need_hi22_p || need_lo10_p))
1104 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1106 the_insn.reloc = BFD_RELOC_NONE;
1107 output_insn (insn, &the_insn);
1109 /* We didn't need both regs, but we may have to sign extend lower32. */
1110 else if (need_hi22_p && upper32 == -1)
1112 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1114 the_insn.reloc = BFD_RELOC_NONE;
1115 output_insn (insn, &the_insn);
1120 case SPECIAL_CASE_FDIV:
1122 int rd = (the_insn.opcode >> 25) & 0x1f;
1124 output_insn (insn, &the_insn);
1126 /* According to information leaked from Sun, the "fdiv" instructions
1127 on early SPARC machines would produce incorrect results sometimes.
1128 The workaround is to add an fmovs of the destination register to
1129 itself just after the instruction. This was true on machines
1130 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1131 assert (the_insn.reloc == BFD_RELOC_NONE);
1132 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1133 output_insn (insn, &the_insn);
1138 as_fatal (_("failed special case insn sanity check"));
1142 /* Subroutine of md_assemble to do the actual parsing. */
1145 sparc_ip (str, pinsn)
1147 const struct sparc_opcode **pinsn;
1149 char *error_message = "";
1153 const struct sparc_opcode *insn;
1155 unsigned long opcode;
1156 unsigned int mask = 0;
1162 if (islower ((unsigned char) *s))
1166 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1184 as_fatal (_("Unknown opcode: `%s'"), str);
1186 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1190 as_bad (_("Unknown opcode: `%s'"), str);
1201 opcode = insn->match;
1202 memset (&the_insn, '\0', sizeof (the_insn));
1203 the_insn.reloc = BFD_RELOC_NONE;
1207 * Build the opcode, checking as we go to make
1208 * sure that the operands match
1210 for (args = insn->args;; ++args)
1218 /* Parse a series of masks. */
1225 if (! parse_keyword_arg (sparc_encode_membar, &s,
1228 error_message = _(": invalid membar mask name");
1232 while (*s == ' ') { ++s; continue; }
1233 if (*s == '|' || *s == '+')
1235 while (*s == ' ') { ++s; continue; }
1240 if (! parse_const_expr_arg (&s, &kmask))
1242 error_message = _(": invalid membar mask expression");
1245 if (kmask < 0 || kmask > 127)
1247 error_message = _(": invalid membar mask number");
1252 opcode |= MEMBAR (kmask);
1260 /* Parse a prefetch function. */
1263 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1265 error_message = _(": invalid prefetch function name");
1271 if (! parse_const_expr_arg (&s, &fcn))
1273 error_message = _(": invalid prefetch function expression");
1276 if (fcn < 0 || fcn > 31)
1278 error_message = _(": invalid prefetch function number");
1288 /* Parse a sparc64 privileged register. */
1291 struct priv_reg_entry *p = priv_reg_table;
1292 unsigned int len = 9999999; /* init to make gcc happy */
1295 while (p->name[0] > s[0])
1297 while (p->name[0] == s[0])
1299 len = strlen (p->name);
1300 if (strncmp (p->name, s, len) == 0)
1304 if (p->name[0] != s[0])
1306 error_message = _(": unrecognizable privileged register");
1310 opcode |= (p->regnum << 14);
1312 opcode |= (p->regnum << 25);
1318 error_message = _(": unrecognizable privileged register");
1324 /* Parse a v9a ancillary state register. */
1327 struct priv_reg_entry *p = v9a_asr_table;
1328 unsigned int len = 9999999; /* init to make gcc happy */
1331 while (p->name[0] > s[0])
1333 while (p->name[0] == s[0])
1335 len = strlen (p->name);
1336 if (strncmp (p->name, s, len) == 0)
1340 if (p->name[0] != s[0])
1342 error_message = _(": unrecognizable v9a ancillary state register");
1345 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1347 error_message = _(": rd on write only ancillary state register");
1351 opcode |= (p->regnum << 14);
1353 opcode |= (p->regnum << 25);
1359 error_message = _(": unrecognizable v9a ancillary state register");
1365 if (strncmp (s, "%asr", 4) == 0)
1369 if (isdigit ((unsigned char) *s))
1373 while (isdigit ((unsigned char) *s))
1375 num = num * 10 + *s - '0';
1379 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1381 if (num < 16 || 31 < num)
1383 error_message = _(": asr number must be between 16 and 31");
1389 if (num < 0 || 31 < num)
1391 error_message = _(": asr number must be between 0 and 31");
1396 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1401 error_message = _(": expecting %asrN");
1408 the_insn.reloc = BFD_RELOC_SPARC_11;
1412 the_insn.reloc = BFD_RELOC_SPARC_10;
1416 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1417 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1418 the_insn.reloc = BFD_RELOC_SPARC_5;
1420 the_insn.reloc = BFD_RELOC_SPARC13;
1421 /* These fields are unsigned, but for upward compatibility,
1422 allow negative values as well. */
1426 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1427 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1428 the_insn.reloc = BFD_RELOC_SPARC_6;
1430 the_insn.reloc = BFD_RELOC_SPARC13;
1431 /* These fields are unsigned, but for upward compatibility,
1432 allow negative values as well. */
1436 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1441 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1446 if (*s == 'p' && s[1] == 'n')
1454 if (*s == 'p' && s[1] == 't')
1466 if (strncmp (s, "%icc", 4) == 0)
1478 if (strncmp (s, "%xcc", 4) == 0)
1490 if (strncmp (s, "%fcc0", 5) == 0)
1502 if (strncmp (s, "%fcc1", 5) == 0)
1514 if (strncmp (s, "%fcc2", 5) == 0)
1526 if (strncmp (s, "%fcc3", 5) == 0)
1534 if (strncmp (s, "%pc", 3) == 0)
1542 if (strncmp (s, "%tick", 5) == 0)
1549 case '\0': /* end of args */
1568 case '[': /* these must match exactly */
1576 case '#': /* must be at least one digit */
1577 if (isdigit ((unsigned char) *s++))
1579 while (isdigit ((unsigned char) *s))
1587 case 'C': /* coprocessor state register */
1588 if (strncmp (s, "%csr", 4) == 0)
1595 case 'b': /* next operand is a coprocessor register */
1598 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1601 if (isdigit ((unsigned char) *s))
1603 mask = 10 * (mask - '0') + (*s++ - '0');
1617 opcode |= mask << 14;
1625 opcode |= mask << 25;
1631 case 'r': /* next operand must be a register */
1641 case 'f': /* frame pointer */
1649 case 'g': /* global register */
1650 if (isoctal (c = *s++))
1657 case 'i': /* in register */
1658 if (isoctal (c = *s++))
1660 mask = c - '0' + 24;
1665 case 'l': /* local register */
1666 if (isoctal (c = *s++))
1668 mask = (c - '0' + 16);
1673 case 'o': /* out register */
1674 if (isoctal (c = *s++))
1676 mask = (c - '0' + 8);
1681 case 's': /* stack pointer */
1689 case 'r': /* any register */
1690 if (!isdigit ((unsigned char) (c = *s++)))
1705 if (isdigit ((unsigned char) *s))
1707 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1723 /* Got the register, now figure out where
1724 it goes in the opcode. */
1728 opcode |= mask << 14;
1736 opcode |= mask << 25;
1740 opcode |= (mask << 25) | (mask << 14);
1744 opcode |= (mask << 25) | (mask << 0);
1750 case 'e': /* next operand is a floating point register */
1765 && ((format = *s) == 'f')
1766 && isdigit ((unsigned char) *++s))
1768 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1770 mask = 10 * mask + (*s - '0');
1771 } /* read the number */
1779 } /* register must be even numbered */
1787 } /* register must be multiple of 4 */
1791 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1792 error_message = _(": There are only 64 f registers; [0-63]");
1794 error_message = _(": There are only 32 f registers; [0-31]");
1797 else if (mask >= 32)
1799 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1802 mask -= 31; /* wrap high bit */
1806 error_message = _(": There are only 32 f registers; [0-31]");
1814 } /* if not an 'f' register. */
1821 opcode |= RS1 (mask);
1828 opcode |= RS2 (mask);
1834 opcode |= RD (mask);
1843 if (strncmp (s, "%fsr", 4) == 0)
1850 case '0': /* 64 bit immediate (setx insn) */
1851 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1854 case 'h': /* high 22 bits */
1855 the_insn.reloc = BFD_RELOC_HI22;
1858 case 'l': /* 22 bit PC relative immediate */
1859 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
1863 case 'L': /* 30 bit immediate */
1864 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
1868 case 'n': /* 22 bit immediate */
1869 the_insn.reloc = BFD_RELOC_SPARC22;
1872 case 'i': /* 13 bit immediate */
1873 the_insn.reloc = BFD_RELOC_SPARC13;
1881 /* Check for %hi, etc. */
1885 /* The name as it appears in assembler. */
1887 /* strlen (name), precomputed for speed */
1889 /* The reloc this pseudo-op translates to. */
1891 /* Non-zero if for v9 only. */
1893 /* Non-zero if can be used in pc-relative contexts. */
1894 int pcrel_p;/*FIXME:wip*/
1896 /* hix/lox must appear before hi/lo so %hix won't be
1897 mistaken for %hi. */
1898 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
1899 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
1900 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
1901 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
1902 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
1903 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
1904 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
1905 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
1906 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
1907 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
1908 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
1909 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
1914 for (o = ops; o->name; o++)
1915 if (strncmp (s + 1, o->name, o->len) == 0)
1917 if (o->name == NULL)
1920 the_insn.reloc = o->reloc;
1925 /* Note that if the get_expression() fails, we will still
1926 have created U entries in the symbol table for the
1927 'symbols' in the input string. Try not to create U
1928 symbols for registers, etc. */
1930 /* This stuff checks to see if the expression ends in
1931 +%reg. If it does, it removes the register from
1932 the expression, and re-sets 's' to point to the
1937 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
1939 if (s1 != s && isdigit ((unsigned char) s1[-1]))
1941 if (s1[-2] == '%' && s1[-3] == '+')
1945 (void) get_expression (s);
1950 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1954 (void) get_expression (s);
1961 (void) get_expression (s);
1964 /* Check for constants that don't require emitting a reloc. */
1965 if (the_insn.exp.X_op == O_constant
1966 && the_insn.exp.X_add_symbol == 0
1967 && the_insn.exp.X_op_symbol == 0)
1969 /* For pc-relative call instructions, we reject
1970 constants to get better code. */
1972 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
1973 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
1975 error_message = _(": PC-relative operand can't be a constant");
1979 /* Constants that won't fit are checked in md_apply_fix3
1980 and bfd_install_relocation.
1981 ??? It would be preferable to install the constants
1982 into the insn here and save having to create a fixS
1983 for each one. There already exists code to handle
1984 all the various cases (e.g. in md_apply_fix3 and
1985 bfd_install_relocation) so duplicating all that code
1986 here isn't right. */
2006 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2008 error_message = _(": invalid ASI name");
2014 if (! parse_const_expr_arg (&s, &asi))
2016 error_message = _(": invalid ASI expression");
2019 if (asi < 0 || asi > 255)
2021 error_message = _(": invalid ASI number");
2025 opcode |= ASI (asi);
2027 } /* alternate space */
2030 if (strncmp (s, "%psr", 4) == 0)
2037 case 'q': /* floating point queue */
2038 if (strncmp (s, "%fq", 3) == 0)
2045 case 'Q': /* coprocessor queue */
2046 if (strncmp (s, "%cq", 3) == 0)
2054 if (strcmp (str, "set") == 0
2055 || strcmp (str, "setuw") == 0)
2057 special_case = SPECIAL_CASE_SET;
2060 else if (strcmp (str, "setsw") == 0)
2062 special_case = SPECIAL_CASE_SETSW;
2065 else if (strcmp (str, "setx") == 0)
2067 special_case = SPECIAL_CASE_SETX;
2070 else if (strncmp (str, "fdiv", 4) == 0)
2072 special_case = SPECIAL_CASE_FDIV;
2078 if (strncmp (s, "%asi", 4) != 0)
2084 if (strncmp (s, "%fprs", 5) != 0)
2090 if (strncmp (s, "%ccr", 4) != 0)
2096 if (strncmp (s, "%tbr", 4) != 0)
2102 if (strncmp (s, "%wim", 4) != 0)
2109 char *push = input_line_pointer;
2112 input_line_pointer = s;
2114 if (e.X_op == O_constant)
2116 int n = e.X_add_number;
2117 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2118 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2120 opcode |= e.X_add_number << 5;
2123 as_bad (_("non-immediate OPF operand, ignored"));
2124 s = input_line_pointer;
2125 input_line_pointer = push;
2130 if (strncmp (s, "%y", 2) != 0)
2138 /* Parse a sparclet cpreg. */
2140 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2142 error_message = _(": invalid cpreg name");
2145 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2150 as_fatal (_("failed sanity check."));
2151 } /* switch on arg code */
2153 /* Break out of for() loop. */
2155 } /* for each arg that we expect */
2160 /* Args don't match. */
2161 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2162 && (insn->name == insn[1].name
2163 || !strcmp (insn->name, insn[1].name)))
2171 as_bad (_("Illegal operands%s"), error_message);
2177 /* We have a match. Now see if the architecture is ok. */
2178 int needed_arch_mask = insn->architecture;
2182 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2183 | (1 << SPARC_OPCODE_ARCH_V9A));
2184 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2187 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2189 /* Can we bump up the architecture? */
2190 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2192 enum sparc_opcode_arch_val needed_architecture =
2193 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2194 & needed_arch_mask);
2196 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2198 && needed_architecture > warn_after_architecture)
2200 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2201 sparc_opcode_archs[current_architecture].name,
2202 sparc_opcode_archs[needed_architecture].name,
2204 warn_after_architecture = needed_architecture;
2206 current_architecture = needed_architecture;
2209 /* ??? This seems to be a bit fragile. What if the next entry in
2210 the opcode table is the one we want and it is supported?
2211 It is possible to arrange the table today so that this can't
2212 happen but what about tomorrow? */
2215 int arch,printed_one_p = 0;
2217 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2219 /* Create a list of the architectures that support the insn. */
2220 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2222 arch = sparc_ffs (needed_arch_mask);
2223 while ((1 << arch) <= needed_arch_mask)
2225 if ((1 << arch) & needed_arch_mask)
2229 strcpy (p, sparc_opcode_archs[arch].name);
2236 as_bad (_("Architecture mismatch on \"%s\"."), str);
2237 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2239 sparc_opcode_archs[max_architecture].name);
2245 } /* forever looking for a match */
2247 the_insn.opcode = opcode;
2250 /* Parse an argument that can be expressed as a keyword.
2251 (eg: #StoreStore or %ccfr).
2252 The result is a boolean indicating success.
2253 If successful, INPUT_POINTER is updated. */
2256 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2257 int (*lookup_fn) PARAMS ((const char *));
2258 char **input_pointerP;
2264 p = *input_pointerP;
2265 for (q = p + (*p == '#' || *p == '%');
2266 isalnum ((unsigned char) *q) || *q == '_';
2271 value = (*lookup_fn) (p);
2276 *input_pointerP = q;
2280 /* Parse an argument that is a constant expression.
2281 The result is a boolean indicating success. */
2284 parse_const_expr_arg (input_pointerP, valueP)
2285 char **input_pointerP;
2288 char *save = input_line_pointer;
2291 input_line_pointer = *input_pointerP;
2292 /* The next expression may be something other than a constant
2293 (say if we're not processing the right variant of the insn).
2294 Don't call expression unless we're sure it will succeed as it will
2295 signal an error (which we want to defer until later). */
2296 /* FIXME: It might be better to define md_operand and have it recognize
2297 things like %asi, etc. but continuing that route through to the end
2298 is a lot of work. */
2299 if (*input_line_pointer == '%')
2301 input_line_pointer = save;
2305 *input_pointerP = input_line_pointer;
2306 input_line_pointer = save;
2307 if (exp.X_op != O_constant)
2309 *valueP = exp.X_add_number;
2313 /* Subroutine of sparc_ip to parse an expression. */
2316 get_expression (str)
2322 save_in = input_line_pointer;
2323 input_line_pointer = str;
2324 seg = expression (&the_insn.exp);
2325 if (seg != absolute_section
2326 && seg != text_section
2327 && seg != data_section
2328 && seg != bss_section
2329 && seg != undefined_section)
2331 the_insn.error = _("bad segment");
2332 expr_end = input_line_pointer;
2333 input_line_pointer = save_in;
2336 expr_end = input_line_pointer;
2337 input_line_pointer = save_in;
2341 /* Subroutine of md_assemble to output one insn. */
2344 output_insn (insn, the_insn)
2345 const struct sparc_opcode *insn;
2346 struct sparc_it *the_insn;
2348 char *toP = frag_more (4);
2350 /* put out the opcode */
2351 if (INSN_BIG_ENDIAN)
2352 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2354 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2356 /* put out the symbol-dependent stuff */
2357 if (the_insn->reloc != BFD_RELOC_NONE)
2359 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2360 (toP - frag_now->fr_literal), /* where */
2365 /* Turn off overflow checking in fixup_segment. We'll do our
2366 own overflow checking in md_apply_fix3. This is necessary because
2367 the insn size is 4 and fixup_segment will signal an overflow for
2368 large 8 byte quantities. */
2369 fixP->fx_no_overflow = 1;
2373 last_opcode = the_insn->opcode;
2377 This is identical to the md_atof in m68k.c. I think this is right,
2380 Turn a string in input_line_pointer into a floating point constant of type
2381 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2382 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2385 /* Equal to MAX_PRECISION in atof-ieee.c */
2386 #define MAX_LITTLENUMS 6
2389 md_atof (type, litP, sizeP)
2395 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2426 return _("Bad call to MD_ATOF()");
2429 t = atof_ieee (input_line_pointer, type, words);
2431 input_line_pointer = t;
2432 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2434 if (target_big_endian)
2436 for (i = 0; i < prec; i++)
2438 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2439 litP += sizeof (LITTLENUM_TYPE);
2444 for (i = prec - 1; i >= 0; i--)
2446 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2447 litP += sizeof (LITTLENUM_TYPE);
2454 /* Write a value out to the object file, using the appropriate
2458 md_number_to_chars (buf, val, n)
2463 if (target_big_endian)
2464 number_to_chars_bigendian (buf, val, n);
2465 else if (target_little_endian_data
2466 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2467 /* Output debug words, which are not in allocated sections, as big endian */
2468 number_to_chars_bigendian (buf, val, n);
2469 else if (target_little_endian_data || ! target_big_endian)
2470 number_to_chars_littleendian (buf, val, n);
2473 /* Apply a fixS to the frags, now that we know the value it ought to
2477 md_apply_fix3 (fixP, value, segment)
2482 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2488 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2490 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2493 /* FIXME: SPARC ELF relocations don't use an addend in the data
2494 field itself. This whole approach should be somehow combined
2495 with the calls to bfd_install_relocation. Also, the value passed
2496 in by fixup_segment includes the value of a defined symbol. We
2497 don't want to include the value of an externally visible symbol. */
2498 if (fixP->fx_addsy != NULL)
2500 if (fixP->fx_addsy->sy_used_in_reloc
2501 && (S_IS_EXTERNAL (fixP->fx_addsy)
2502 || S_IS_WEAK (fixP->fx_addsy)
2503 || (sparc_pic_code && ! fixP->fx_pcrel)
2504 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2505 && ((bfd_get_section_flags (stdoutput,
2506 S_GET_SEGMENT (fixP->fx_addsy))
2507 & SEC_LINK_ONCE) != 0
2508 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2510 sizeof ".gnu.linkonce" - 1) == 0)))
2511 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2512 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2513 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2514 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2519 /* This is a hack. There should be a better way to
2520 handle this. Probably in terms of howto fields, once
2521 we can look at these fixups in terms of howtos. */
2522 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2523 val += fixP->fx_where + fixP->fx_frag->fr_address;
2526 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2527 generate a reloc, then we just want to let the reloc addend set
2528 the value. We do not want to also stuff the addend into the
2529 object file. Including the addend in the object file works when
2530 doing a static link, because the linker will ignore the object
2531 file contents. However, the dynamic linker does not ignore the
2532 object file contents. */
2533 if (fixP->fx_addsy != NULL
2534 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2537 /* When generating PIC code, we do not want an addend for a reloc
2538 against a local symbol. We adjust fx_addnumber to cancel out the
2539 value already included in val, and to also cancel out the
2540 adjustment which bfd_install_relocation will create. */
2542 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2543 && fixP->fx_addsy != NULL
2544 && ! S_IS_COMMON (fixP->fx_addsy)
2545 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2546 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2548 /* When generating PIC code, we need to fiddle to get
2549 bfd_install_relocation to do the right thing for a PC relative
2550 reloc against a local symbol which we are going to keep. */
2552 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2553 && fixP->fx_addsy != NULL
2554 && (S_IS_EXTERNAL (fixP->fx_addsy)
2555 || S_IS_WEAK (fixP->fx_addsy))
2556 && S_IS_DEFINED (fixP->fx_addsy)
2557 && ! S_IS_COMMON (fixP->fx_addsy))
2560 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2564 /* If this is a data relocation, just output VAL. */
2566 if (fixP->fx_r_type == BFD_RELOC_16)
2568 md_number_to_chars (buf, val, 2);
2570 else if (fixP->fx_r_type == BFD_RELOC_32
2571 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2573 md_number_to_chars (buf, val, 4);
2575 else if (fixP->fx_r_type == BFD_RELOC_64)
2577 md_number_to_chars (buf, val, 8);
2581 /* It's a relocation against an instruction. */
2583 if (INSN_BIG_ENDIAN)
2584 insn = bfd_getb32 ((unsigned char *) buf);
2586 insn = bfd_getl32 ((unsigned char *) buf);
2588 switch (fixP->fx_r_type)
2590 case BFD_RELOC_32_PCREL_S2:
2592 /* FIXME: This increment-by-one deserves a comment of why it's
2594 if (! sparc_pic_code
2595 || fixP->fx_addsy == NULL
2596 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2598 insn |= val & 0x3fffffff;
2601 case BFD_RELOC_SPARC_11:
2602 if (! in_signed_range (val, 0x7ff))
2603 as_bad_where (fixP->fx_file, fixP->fx_line,
2604 _("relocation overflow"));
2605 insn |= val & 0x7ff;
2608 case BFD_RELOC_SPARC_10:
2609 if (! in_signed_range (val, 0x3ff))
2610 as_bad_where (fixP->fx_file, fixP->fx_line,
2611 _("relocation overflow"));
2612 insn |= val & 0x3ff;
2615 case BFD_RELOC_SPARC_7:
2616 if (! in_bitfield_range (val, 0x7f))
2617 as_bad_where (fixP->fx_file, fixP->fx_line,
2618 _("relocation overflow"));
2622 case BFD_RELOC_SPARC_6:
2623 if (! in_bitfield_range (val, 0x3f))
2624 as_bad_where (fixP->fx_file, fixP->fx_line,
2625 _("relocation overflow"));
2629 case BFD_RELOC_SPARC_5:
2630 if (! in_bitfield_range (val, 0x1f))
2631 as_bad_where (fixP->fx_file, fixP->fx_line,
2632 _("relocation overflow"));
2636 case BFD_RELOC_SPARC_WDISP16:
2637 /* FIXME: simplify */
2638 if (((val > 0) && (val & ~0x3fffc))
2639 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2640 as_bad_where (fixP->fx_file, fixP->fx_line,
2641 _("relocation overflow"));
2642 /* FIXME: The +1 deserves a comment. */
2643 val = (val >> 2) + 1;
2644 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2647 case BFD_RELOC_SPARC_WDISP19:
2648 /* FIXME: simplify */
2649 if (((val > 0) && (val & ~0x1ffffc))
2650 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2651 as_bad_where (fixP->fx_file, fixP->fx_line,
2652 _("relocation overflow"));
2653 /* FIXME: The +1 deserves a comment. */
2654 val = (val >> 2) + 1;
2655 insn |= val & 0x7ffff;
2658 case BFD_RELOC_SPARC_HH22:
2659 val = BSR (val, 32);
2660 /* intentional fallthrough */
2662 case BFD_RELOC_SPARC_LM22:
2663 case BFD_RELOC_HI22:
2664 if (!fixP->fx_addsy)
2666 insn |= (val >> 10) & 0x3fffff;
2670 /* FIXME: Need comment explaining why we do this. */
2675 case BFD_RELOC_SPARC22:
2676 if (val & ~0x003fffff)
2677 as_bad_where (fixP->fx_file, fixP->fx_line,
2678 _("relocation overflow"));
2679 insn |= (val & 0x3fffff);
2682 case BFD_RELOC_SPARC_HM10:
2683 val = BSR (val, 32);
2684 /* intentional fallthrough */
2686 case BFD_RELOC_LO10:
2687 if (!fixP->fx_addsy)
2689 insn |= val & 0x3ff;
2693 /* FIXME: Need comment explaining why we do this. */
2698 case BFD_RELOC_SPARC13:
2699 if (! in_signed_range (val, 0x1fff))
2700 as_bad_where (fixP->fx_file, fixP->fx_line,
2701 _("relocation overflow"));
2702 insn |= val & 0x1fff;
2705 case BFD_RELOC_SPARC_WDISP22:
2706 val = (val >> 2) + 1;
2708 case BFD_RELOC_SPARC_BASE22:
2709 insn |= val & 0x3fffff;
2712 case BFD_RELOC_SPARC_H44:
2713 if (!fixP->fx_addsy)
2717 insn |= tval & 0x3fffff;
2721 case BFD_RELOC_SPARC_M44:
2722 if (!fixP->fx_addsy)
2723 insn |= (val >> 12) & 0x3ff;
2726 case BFD_RELOC_SPARC_L44:
2727 if (!fixP->fx_addsy)
2728 insn |= val & 0xfff;
2731 case BFD_RELOC_SPARC_HIX22:
2732 if (!fixP->fx_addsy)
2734 val ^= ~ (offsetT) 0;
2735 insn |= (val >> 10) & 0x3fffff;
2739 case BFD_RELOC_SPARC_LOX10:
2740 if (!fixP->fx_addsy)
2741 insn |= 0x1c00 | (val & 0x3ff);
2744 case BFD_RELOC_NONE:
2746 as_bad_where (fixP->fx_file, fixP->fx_line,
2747 _("bad or unhandled relocation type: 0x%02x"),
2752 if (INSN_BIG_ENDIAN)
2753 bfd_putb32 (insn, (unsigned char *) buf);
2755 bfd_putl32 (insn, (unsigned char *) buf);
2758 /* Are we finished with this relocation now? */
2759 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2765 /* Translate internal representation of relocation info to BFD target
2768 tc_gen_reloc (section, fixp)
2773 bfd_reloc_code_real_type code;
2775 reloc = (arelent *) xmalloc (sizeof (arelent));
2777 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2778 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2780 switch (fixp->fx_r_type)
2784 case BFD_RELOC_HI22:
2785 case BFD_RELOC_LO10:
2786 case BFD_RELOC_32_PCREL_S2:
2787 case BFD_RELOC_SPARC13:
2788 case BFD_RELOC_SPARC_BASE13:
2789 case BFD_RELOC_SPARC_WDISP16:
2790 case BFD_RELOC_SPARC_WDISP19:
2791 case BFD_RELOC_SPARC_WDISP22:
2793 case BFD_RELOC_SPARC_5:
2794 case BFD_RELOC_SPARC_6:
2795 case BFD_RELOC_SPARC_7:
2796 case BFD_RELOC_SPARC_10:
2797 case BFD_RELOC_SPARC_11:
2798 case BFD_RELOC_SPARC_HH22:
2799 case BFD_RELOC_SPARC_HM10:
2800 case BFD_RELOC_SPARC_LM22:
2801 case BFD_RELOC_SPARC_PC_HH22:
2802 case BFD_RELOC_SPARC_PC_HM10:
2803 case BFD_RELOC_SPARC_PC_LM22:
2804 case BFD_RELOC_SPARC_H44:
2805 case BFD_RELOC_SPARC_M44:
2806 case BFD_RELOC_SPARC_L44:
2807 case BFD_RELOC_SPARC_HIX22:
2808 case BFD_RELOC_SPARC_LOX10:
2809 case BFD_RELOC_SPARC_REV32:
2810 code = fixp->fx_r_type;
2817 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2818 /* If we are generating PIC code, we need to generate a different
2822 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2824 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2831 case BFD_RELOC_32_PCREL_S2:
2832 if (! S_IS_DEFINED (fixp->fx_addsy)
2833 || S_IS_COMMON (fixp->fx_addsy)
2834 || S_IS_EXTERNAL (fixp->fx_addsy)
2835 || S_IS_WEAK (fixp->fx_addsy))
2836 code = BFD_RELOC_SPARC_WPLT30;
2838 case BFD_RELOC_HI22:
2839 if (fixp->fx_addsy != NULL
2840 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2841 code = BFD_RELOC_SPARC_PC22;
2843 code = BFD_RELOC_SPARC_GOT22;
2845 case BFD_RELOC_LO10:
2846 if (fixp->fx_addsy != NULL
2847 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2848 code = BFD_RELOC_SPARC_PC10;
2850 code = BFD_RELOC_SPARC_GOT10;
2852 case BFD_RELOC_SPARC13:
2853 code = BFD_RELOC_SPARC_GOT13;
2859 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2861 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2862 if (reloc->howto == 0)
2864 as_bad_where (fixp->fx_file, fixp->fx_line,
2865 _("internal error: can't export reloc type %d (`%s')"),
2866 fixp->fx_r_type, bfd_get_reloc_code_name (code));
2870 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2873 if (reloc->howto->pc_relative == 0
2874 || code == BFD_RELOC_SPARC_PC10
2875 || code == BFD_RELOC_SPARC_PC22)
2876 reloc->addend = fixp->fx_addnumber;
2877 else if (sparc_pic_code
2878 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
2879 && fixp->fx_addsy != NULL
2880 && (S_IS_EXTERNAL (fixp->fx_addsy)
2881 || S_IS_WEAK (fixp->fx_addsy))
2882 && S_IS_DEFINED (fixp->fx_addsy)
2883 && ! S_IS_COMMON (fixp->fx_addsy))
2884 reloc->addend = fixp->fx_addnumber;
2886 reloc->addend = fixp->fx_offset - reloc->address;
2888 #else /* elf or coff */
2890 if (reloc->howto->pc_relative == 0
2891 || code == BFD_RELOC_SPARC_PC10
2892 || code == BFD_RELOC_SPARC_PC22)
2893 reloc->addend = fixp->fx_addnumber;
2894 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2895 reloc->addend = (section->vma
2896 + fixp->fx_addnumber
2897 + md_pcrel_from (fixp));
2899 reloc->addend = fixp->fx_offset;
2905 /* We have no need to default values of symbols. */
2909 md_undefined_symbol (name)
2913 } /* md_undefined_symbol() */
2915 /* Round up a section size to the appropriate boundary. */
2917 md_section_align (segment, size)
2922 /* This is not right for ELF; a.out wants it, and COFF will force
2923 the alignment anyways. */
2924 valueT align = ((valueT) 1
2925 << (valueT) bfd_get_section_alignment (stdoutput, segment));
2927 /* turn alignment value into a mask */
2929 newsize = (size + align) & ~align;
2936 /* Exactly what point is a PC-relative offset relative TO?
2937 On the sparc, they're relative to the address of the offset, plus
2938 its size. This gets us to the following instruction.
2939 (??? Is this right? FIXME-SOON) */
2941 md_pcrel_from (fixP)
2946 ret = fixP->fx_where + fixP->fx_frag->fr_address;
2947 if (! sparc_pic_code
2948 || fixP->fx_addsy == NULL
2949 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2950 ret += fixP->fx_size;
2954 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
2966 for (shift = 0; (value & 1) == 0; value >>= 1)
2969 return (value == 1) ? shift : -1;
2973 * sort of like s_lcomm
2977 static int max_alignment = 15;
2992 name = input_line_pointer;
2993 c = get_symbol_end ();
2994 p = input_line_pointer;
2998 if (*input_line_pointer != ',')
3000 as_bad (_("Expected comma after name"));
3001 ignore_rest_of_line ();
3005 ++input_line_pointer;
3007 if ((size = get_absolute_expression ()) < 0)
3009 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3010 ignore_rest_of_line ();
3015 symbolP = symbol_find_or_make (name);
3018 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3019 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3021 as_bad (_("bad .reserve segment -- expected BSS segment"));
3025 if (input_line_pointer[2] == '.')
3026 input_line_pointer += 7;
3028 input_line_pointer += 6;
3031 if (*input_line_pointer == ',')
3033 ++input_line_pointer;
3036 if (*input_line_pointer == '\n')
3038 as_bad (_("missing alignment"));
3039 ignore_rest_of_line ();
3043 align = (int) get_absolute_expression ();
3046 if (align > max_alignment)
3048 align = max_alignment;
3049 as_warn (_("alignment too large; assuming %d"), align);
3055 as_bad (_("negative alignment"));
3056 ignore_rest_of_line ();
3062 temp = log2 (align);
3065 as_bad (_("alignment not a power of 2"));
3066 ignore_rest_of_line ();
3073 record_alignment (bss_section, align);
3078 if (!S_IS_DEFINED (symbolP)
3080 && S_GET_OTHER (symbolP) == 0
3081 && S_GET_DESC (symbolP) == 0
3088 segT current_seg = now_seg;
3089 subsegT current_subseg = now_subseg;
3091 subseg_set (bss_section, 1); /* switch to bss */
3094 frag_align (align, 0, 0); /* do alignment */
3096 /* detach from old frag */
3097 if (S_GET_SEGMENT(symbolP) == bss_section)
3098 symbolP->sy_frag->fr_symbol = NULL;
3100 symbolP->sy_frag = frag_now;
3101 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3102 (offsetT) size, (char *)0);
3105 S_SET_SEGMENT (symbolP, bss_section);
3107 subseg_set (current_seg, current_subseg);
3110 S_SET_SIZE (symbolP, size);
3116 as_warn("Ignoring attempt to re-define symbol %s",
3117 S_GET_NAME (symbolP));
3118 } /* if not redefining */
3120 demand_empty_rest_of_line ();
3133 name = input_line_pointer;
3134 c = get_symbol_end ();
3135 /* just after name is now '\0' */
3136 p = input_line_pointer;
3139 if (*input_line_pointer != ',')
3141 as_bad (_("Expected comma after symbol-name"));
3142 ignore_rest_of_line ();
3145 input_line_pointer++; /* skip ',' */
3146 if ((temp = get_absolute_expression ()) < 0)
3148 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3149 ignore_rest_of_line ();
3154 symbolP = symbol_find_or_make (name);
3156 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3158 as_bad (_("Ignoring attempt to re-define symbol"));
3159 ignore_rest_of_line ();
3162 if (S_GET_VALUE (symbolP) != 0)
3164 if (S_GET_VALUE (symbolP) != (valueT) size)
3166 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3167 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3173 S_SET_VALUE (symbolP, (valueT) size);
3174 S_SET_EXTERNAL (symbolP);
3177 know (symbolP->sy_frag == &zero_address_frag);
3178 if (*input_line_pointer != ',')
3180 as_bad (_("Expected comma after common length"));
3181 ignore_rest_of_line ();
3184 input_line_pointer++;
3186 if (*input_line_pointer != '"')
3188 temp = get_absolute_expression ();
3191 if (temp > max_alignment)
3193 temp = max_alignment;
3194 as_warn (_("alignment too large; assuming %d"), temp);
3200 as_bad (_("negative alignment"));
3201 ignore_rest_of_line ();
3214 old_subsec = now_subseg;
3219 align = log2 (temp);
3223 as_bad (_("alignment not a power of 2"));
3224 ignore_rest_of_line ();
3228 record_alignment (bss_section, align);
3229 subseg_set (bss_section, 0);
3231 frag_align (align, 0, 0);
3232 if (S_GET_SEGMENT (symbolP) == bss_section)
3233 symbolP->sy_frag->fr_symbol = 0;
3234 symbolP->sy_frag = frag_now;
3235 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3236 (offsetT) size, (char *) 0);
3238 S_SET_SEGMENT (symbolP, bss_section);
3239 S_CLEAR_EXTERNAL (symbolP);
3240 S_SET_SIZE (symbolP, size);
3241 subseg_set (old_sec, old_subsec);
3244 #endif /* OBJ_ELF */
3247 S_SET_VALUE (symbolP, (valueT) size);
3249 S_SET_ALIGN (symbolP, temp);
3250 S_SET_SIZE (symbolP, size);
3252 S_SET_EXTERNAL (symbolP);
3253 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3258 input_line_pointer++;
3259 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3260 if (*input_line_pointer == '.')
3261 input_line_pointer++;
3262 /* @@ Some say data, some say bss. */
3263 if (strncmp (input_line_pointer, "bss\"", 4)
3264 && strncmp (input_line_pointer, "data\"", 5))
3266 while (*--input_line_pointer != '"')
3268 input_line_pointer--;
3269 goto bad_common_segment;
3271 while (*input_line_pointer++ != '"')
3273 goto allocate_common;
3276 #ifdef BFD_ASSEMBLER
3277 symbolP->bsym->flags |= BSF_OBJECT;
3280 demand_empty_rest_of_line ();
3285 p = input_line_pointer;
3286 while (*p && *p != '\n')
3290 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3292 input_line_pointer = p;
3293 ignore_rest_of_line ();
3298 /* Handle the .empty pseudo-op. This supresses the warnings about
3299 invalid delay slot usage. */
3305 /* The easy way to implement is to just forget about the last
3315 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3317 input_line_pointer += 6;
3321 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3323 input_line_pointer += 6;
3327 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3329 input_line_pointer += 7;
3333 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3335 input_line_pointer += 5;
3336 /* We only support 2 segments -- text and data -- for now, so
3337 things in the "bss segment" will have to go into data for now.
3338 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3339 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3342 as_bad (_("Unknown segment type"));
3343 demand_empty_rest_of_line ();
3349 subseg_set (data_section, 1);
3350 demand_empty_rest_of_line ();
3357 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3359 ++input_line_pointer;
3361 ++input_line_pointer;
3364 /* This static variable is set by s_uacons to tell sparc_cons_align
3365 that the expession does not need to be aligned. */
3367 static int sparc_no_align_cons = 0;
3369 /* This handles the unaligned space allocation pseudo-ops, such as
3370 .uaword. .uaword is just like .word, but the value does not need
3377 /* Tell sparc_cons_align not to align this value. */
3378 sparc_no_align_cons = 1;
3382 /* If the --enforce-aligned-data option is used, we require .word,
3383 et. al., to be aligned correctly. We do it by setting up an
3384 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3385 no unexpected alignment was introduced.
3387 The SunOS and Solaris native assemblers enforce aligned data by
3388 default. We don't want to do that, because gcc can deliberately
3389 generate misaligned data if the packed attribute is used. Instead,
3390 we permit misaligned data by default, and permit the user to set an
3391 option to check for it. */
3394 sparc_cons_align (nbytes)
3400 /* Only do this if we are enforcing aligned data. */
3401 if (! enforce_aligned_data)
3404 if (sparc_no_align_cons)
3406 /* This is an unaligned pseudo-op. */
3407 sparc_no_align_cons = 0;
3411 nalign = log2 (nbytes);
3415 assert (nalign > 0);
3417 if (now_seg == absolute_section)
3419 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3420 as_bad (_("misaligned data"));
3424 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3425 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3427 record_alignment (now_seg, nalign);
3430 /* This is where we do the unexpected alignment check.
3431 This is called from HANDLE_ALIGN in tc-sparc.h. */
3434 sparc_handle_align (fragp)
3437 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
3438 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
3439 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
3440 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3442 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3447 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
3449 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3452 for (i = 0; i < count; i += 4, p++)
3453 if (INSN_BIG_ENDIAN)
3454 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3456 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3458 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
3460 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3461 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3462 if (INSN_BIG_ENDIAN)
3463 number_to_chars_bigendian (waddr, wval, 4);
3465 number_to_chars_littleendian (waddr, wval, 4);
3467 fragp->fr_var = count;
3473 /* Some special processing for a Sparc ELF file. */
3476 sparc_elf_final_processing ()
3478 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3479 sort of BFD interface for this. */
3480 if (sparc_arch_size == 64)
3482 switch (sparc_memory_model)
3485 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3488 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3494 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3495 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3496 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3497 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3501 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3502 reloc for a cons. We could use the definition there, except that
3503 we want to handle little endian relocs specially. */
3506 cons_fix_new_sparc (frag, where, nbytes, exp)
3509 unsigned int nbytes;
3512 bfd_reloc_code_real_type r;
3514 r = (nbytes == 1 ? BFD_RELOC_8 :
3515 (nbytes == 2 ? BFD_RELOC_16 :
3516 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
3518 if (target_little_endian_data && nbytes == 4
3519 && now_seg->flags & SEC_ALLOC)
3520 r = BFD_RELOC_SPARC_REV32;
3521 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);