1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 static struct sparc_arch *lookup_arch PARAMS ((char *));
35 static void init_default_arch PARAMS ((void));
36 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
37 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
39 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
40 static int sparc_ffs PARAMS ((unsigned int));
41 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
42 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
43 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
44 static bfd_vma BSR PARAMS ((bfd_vma, int));
45 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
46 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
47 static int parse_const_expr_arg PARAMS ((char **, int *));
48 static int get_expression PARAMS ((char *str));
50 /* Default architecture. */
51 /* ??? The default value should be V8, but sparclite support was added
52 by making it the default. GCC now passes -Asparclite, so maybe sometime in
53 the future we can set this to V8. */
55 #define DEFAULT_ARCH "sparclite"
57 static char *default_arch = DEFAULT_ARCH;
59 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
61 static int default_init_p;
63 /* Current architecture. We don't bump up unless necessary. */
64 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
66 /* The maximum architecture level we can bump up to.
67 In a 32 bit environment, don't allow bumping up to v9 by default.
68 The native assembler works this way. The user is required to pass
69 an explicit argument before we'll create v9 object files. However, if
70 we don't see any v9 insns, a v8plus object file is not created. */
71 static enum sparc_opcode_arch_val max_architecture;
73 /* Either 32 or 64, selects file format. */
74 static int sparc_arch_size;
75 /* Initial (default) value, recorded separately in case a user option
76 changes the value before md_show_usage is called. */
77 static int default_arch_size;
80 /* The currently selected v9 memory model. Currently only used for
82 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
85 static int architecture_requested;
86 static int warn_on_bump;
88 /* If warn_on_bump and the needed architecture is higher than this
89 architecture, issue a warning. */
90 static enum sparc_opcode_arch_val warn_after_architecture;
92 /* Non-zero if as should generate error if an undeclared g[23] register
93 has been used in -64. */
94 static int no_undeclared_regs;
96 /* Non-zero if we should try to relax jumps and calls. */
97 static int sparc_relax;
99 /* Non-zero if we are generating PIC code. */
102 /* Non-zero if we should give an error when misaligned data is seen. */
103 static int enforce_aligned_data;
105 extern int target_big_endian;
107 static int target_little_endian_data;
109 /* Symbols for global registers on v9. */
110 static symbolS *globals[8];
112 /* V9 and 86x have big and little endian data, but instructions are always big
113 endian. The sparclet has bi-endian support but both data and insns have
114 the same endianness. Global `target_big_endian' is used for data.
115 The following macro is used for instructions. */
116 #ifndef INSN_BIG_ENDIAN
117 #define INSN_BIG_ENDIAN (target_big_endian \
118 || default_arch_type == sparc86x \
119 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
122 /* Handle of the OPCODE hash table. */
123 static struct hash_control *op_hash;
125 static int log2 PARAMS ((int));
126 static void s_data1 PARAMS ((void));
127 static void s_seg PARAMS ((int));
128 static void s_proc PARAMS ((int));
129 static void s_reserve PARAMS ((int));
130 static void s_common PARAMS ((int));
131 static void s_empty PARAMS ((int));
132 static void s_uacons PARAMS ((int));
133 static void s_ncons PARAMS ((int));
134 static void s_register PARAMS ((int));
136 const pseudo_typeS md_pseudo_table[] =
138 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
139 {"common", s_common, 0},
140 {"empty", s_empty, 0},
141 {"global", s_globl, 0},
143 {"nword", s_ncons, 0},
144 {"optim", s_ignore, 0},
146 {"reserve", s_reserve, 0},
148 {"skip", s_space, 0},
151 {"uahalf", s_uacons, 2},
152 {"uaword", s_uacons, 4},
153 {"uaxword", s_uacons, 8},
155 {"file", dwarf2_directive_file, 0},
156 {"loc", dwarf2_directive_loc, 0},
157 /* These are specific to sparc/svr4. */
158 {"2byte", s_uacons, 2},
159 {"4byte", s_uacons, 4},
160 {"8byte", s_uacons, 8},
161 {"register", s_register, 0},
166 /* Size of relocation record. */
167 const int md_reloc_size = 12;
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars[] = "#";
184 const char line_separator_chars[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < '8')
204 unsigned long opcode;
205 struct nlist *nlistp;
209 bfd_reloc_code_real_type reloc;
212 struct sparc_it the_insn, set_insn;
214 static void output_insn
215 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
217 /* Table of arguments to -A.
218 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
219 for this use. That table is for opcodes only. This table is for opcodes
222 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
223 v8plusa, v9, v9a, v9b, v9_64};
225 static struct sparc_arch {
228 enum sparc_arch_types arch_type;
229 /* Default word size, as specified during configuration.
230 A value of zero means can't be used to specify default architecture. */
231 int default_arch_size;
232 /* Allowable arg to -A? */
234 } sparc_arch_table[] = {
235 { "v6", "v6", v6, 0, 1 },
236 { "v7", "v7", v7, 0, 1 },
237 { "v8", "v8", v8, 32, 1 },
238 { "sparclet", "sparclet", sparclet, 32, 1 },
239 { "sparclite", "sparclite", sparclite, 32, 1 },
240 { "sparc86x", "sparclite", sparc86x, 32, 1 },
241 { "v8plus", "v9", v9, 0, 1 },
242 { "v8plusa", "v9a", v9, 0, 1 },
243 { "v8plusb", "v9b", v9, 0, 1 },
244 { "v9", "v9", v9, 0, 1 },
245 { "v9a", "v9a", v9, 0, 1 },
246 { "v9b", "v9b", v9, 0, 1 },
247 /* This exists to allow configure.in/Makefile.in to pass one
248 value to specify both the default machine and default word size. */
249 { "v9-64", "v9", v9, 64, 0 },
250 { NULL, NULL, v8, 0, 0 }
253 /* Variant of default_arch */
254 static enum sparc_arch_types default_arch_type;
256 static struct sparc_arch *
260 struct sparc_arch *sa;
262 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
263 if (strcmp (sa->name, name) == 0)
265 if (sa->name == NULL)
270 /* Initialize the default opcode arch and word size from the default
271 architecture name. */
276 struct sparc_arch *sa = lookup_arch (default_arch);
279 || sa->default_arch_size == 0)
280 as_fatal (_("Invalid default architecture, broken assembler."));
282 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
283 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
284 as_fatal (_("Bad opcode table, broken assembler."));
285 default_arch_size = sparc_arch_size = sa->default_arch_size;
287 default_arch_type = sa->arch_type;
290 /* Called by TARGET_FORMAT. */
293 sparc_target_format ()
295 /* We don't get a chance to initialize anything before we're called,
296 so handle that now. */
297 if (! default_init_p)
298 init_default_arch ();
302 return "a.out-sparc-netbsd";
305 if (target_big_endian)
306 return "a.out-sunos-big";
307 else if (default_arch_type == sparc86x && target_little_endian_data)
308 return "a.out-sunos-big";
310 return "a.out-sparc-little";
312 return "a.out-sunos-big";
323 return "coff-sparc-lynx";
330 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
337 * Invocation line includes a switch not recognized by the base assembler.
338 * See if it's a processor-specific option. These are:
341 * Warn on architecture bumps. See also -A.
343 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
344 * Standard 32 bit architectures.
346 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
347 * This used to only mean 64 bits, but properly specifying it
348 * complicated gcc's ASM_SPECs, so now opcode selection is
349 * specified orthogonally to word size (except when specifying
350 * the default, but that is an internal implementation detail).
351 * -Av8plus, -Av8plusa, -Av8plusb
352 * Same as -Av9{,a,b}.
353 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
354 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
356 * -xarch=v9, -xarch=v9a, -xarch=v9b
357 * Same as -Av9{,a,b} -64, for compatibility with Sun's
360 * Select the architecture and possibly the file format.
361 * Instructions or features not supported by the selected
362 * architecture cause fatal errors.
364 * The default is to start at v6, and bump the architecture up
365 * whenever an instruction is seen at a higher level. In 32 bit
366 * environments, v9 is not bumped up to, the user must pass
369 * If -bump is specified, a warning is printing when bumping to
372 * If an architecture is specified, all instructions must match
373 * that architecture. Any higher level instructions are flagged
374 * as errors. Note that in the 32 bit environment specifying
375 * -Av8plus does not automatically create a v8plus object file, a
376 * v9 insn must be seen.
378 * If both an architecture and -bump are specified, the
379 * architecture starts at the specified level, but bumps are
380 * warnings. Note that we can't set `current_architecture' to
381 * the requested level in this case: in the 32 bit environment,
382 * we still must avoid creating v8plus object files unless v9
386 * Bumping between incompatible architectures is always an
387 * error. For example, from sparclite to v9.
391 CONST char *md_shortopts = "A:K:VQ:sq";
394 CONST char *md_shortopts = "A:k";
396 CONST char *md_shortopts = "A:";
399 struct option md_longopts[] = {
400 #define OPTION_BUMP (OPTION_MD_BASE)
401 {"bump", no_argument, NULL, OPTION_BUMP},
402 #define OPTION_SPARC (OPTION_MD_BASE + 1)
403 {"sparc", no_argument, NULL, OPTION_SPARC},
404 #define OPTION_XARCH (OPTION_MD_BASE + 2)
405 {"xarch", required_argument, NULL, OPTION_XARCH},
407 #define OPTION_32 (OPTION_MD_BASE + 3)
408 {"32", no_argument, NULL, OPTION_32},
409 #define OPTION_64 (OPTION_MD_BASE + 4)
410 {"64", no_argument, NULL, OPTION_64},
411 #define OPTION_TSO (OPTION_MD_BASE + 5)
412 {"TSO", no_argument, NULL, OPTION_TSO},
413 #define OPTION_PSO (OPTION_MD_BASE + 6)
414 {"PSO", no_argument, NULL, OPTION_PSO},
415 #define OPTION_RMO (OPTION_MD_BASE + 7)
416 {"RMO", no_argument, NULL, OPTION_RMO},
418 #ifdef SPARC_BIENDIAN
419 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
420 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
421 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
422 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
424 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
425 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
426 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
427 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
429 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
430 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
431 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
432 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
434 #define OPTION_RELAX (OPTION_MD_BASE + 14)
435 {"relax", no_argument, NULL, OPTION_RELAX},
436 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
437 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
438 {NULL, no_argument, NULL, 0}
441 size_t md_longopts_size = sizeof (md_longopts);
444 md_parse_option (c, arg)
448 /* We don't get a chance to initialize anything before we're called,
449 so handle that now. */
450 if (! default_init_p)
451 init_default_arch ();
457 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
462 if (strncmp (arg, "v9", 2) != 0)
463 md_parse_option (OPTION_32, NULL);
465 md_parse_option (OPTION_64, NULL);
471 struct sparc_arch *sa;
472 enum sparc_opcode_arch_val opcode_arch;
474 sa = lookup_arch (arg);
476 || ! sa->user_option_p)
478 if (c == OPTION_XARCH)
479 as_bad (_("invalid architecture -xarch=%s"), arg);
481 as_bad (_("invalid architecture -A%s"), arg);
485 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
486 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
487 as_fatal (_("Bad opcode table, broken assembler."));
489 max_architecture = opcode_arch;
490 architecture_requested = 1;
495 /* Ignore -sparc, used by SunOS make default .s.o rule. */
498 case OPTION_ENFORCE_ALIGNED_DATA:
499 enforce_aligned_data = 1;
502 #ifdef SPARC_BIENDIAN
503 case OPTION_LITTLE_ENDIAN:
504 target_big_endian = 0;
505 if (default_arch_type != sparclet)
506 as_fatal ("This target does not support -EL");
508 case OPTION_LITTLE_ENDIAN_DATA:
509 target_little_endian_data = 1;
510 target_big_endian = 0;
511 if (default_arch_type != sparc86x
512 && default_arch_type != v9)
513 as_fatal ("This target does not support --little-endian-data");
515 case OPTION_BIG_ENDIAN:
516 target_big_endian = 1;
530 const char **list, **l;
532 sparc_arch_size = c == OPTION_32 ? 32 : 64;
533 list = bfd_target_list ();
534 for (l = list; *l != NULL; l++)
536 if (sparc_arch_size == 32)
538 if (strcmp (*l, "elf32-sparc") == 0)
543 if (strcmp (*l, "elf64-sparc") == 0)
548 as_fatal (_("No compiled in support for %d bit object file format"),
555 sparc_memory_model = MM_TSO;
559 sparc_memory_model = MM_PSO;
563 sparc_memory_model = MM_RMO;
571 /* Qy - do emit .comment
572 Qn - do not emit .comment. */
576 /* Use .stab instead of .stab.excl. */
580 /* quick -- Native assembler does fewer checks. */
584 if (strcmp (arg, "PIC") != 0)
585 as_warn (_("Unrecognized option following -K"));
590 case OPTION_NO_UNDECLARED_REGS:
591 no_undeclared_regs = 1;
594 case OPTION_UNDECLARED_REGS:
595 no_undeclared_regs = 0;
603 case OPTION_NO_RELAX:
615 md_show_usage (stream)
618 const struct sparc_arch *arch;
621 /* We don't get a chance to initialize anything before we're called,
622 so handle that now. */
623 if (! default_init_p)
624 init_default_arch ();
626 fprintf (stream, _("SPARC options:\n"));
628 for (arch = &sparc_arch_table[0]; arch->name; arch++)
630 if (!arch->user_option_p)
632 if (arch != &sparc_arch_table[0])
633 fprintf (stream, " | ");
634 if (column + strlen(arch->name) > 70)
637 fputc ('\n', stream);
639 column += 5 + 2 + strlen(arch->name);
640 fprintf (stream, "-A%s", arch->name);
642 for (arch = &sparc_arch_table[0]; arch->name; arch++)
644 if (!arch->user_option_p)
646 fprintf (stream, " | ");
647 if (column + strlen(arch->name) > 65)
650 fputc ('\n', stream);
652 column += 5 + 7 + strlen(arch->name);
653 fprintf (stream, "-xarch=%s", arch->name);
655 fprintf (stream, _("\n\
656 specify variant of SPARC architecture\n\
657 -bump warn when assembler switches architectures\n\
659 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
660 -relax relax jumps and branches (default)\n\
661 -no-relax avoid changing any jumps and branches\n"));
663 fprintf (stream, _("\
664 -k generate PIC\n"));
667 fprintf (stream, _("\
668 -32 create 32 bit object file\n\
669 -64 create 64 bit object file\n"));
670 fprintf (stream, _("\
671 [default is %d]\n"), default_arch_size);
672 fprintf (stream, _("\
673 -TSO use Total Store Ordering\n\
674 -PSO use Partial Store Ordering\n\
675 -RMO use Relaxed Memory Ordering\n"));
676 fprintf (stream, _("\
677 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
678 fprintf (stream, _("\
679 -KPIC generate PIC\n\
680 -V print assembler version number\n\
681 -undeclared-regs ignore application global register usage without\n\
682 appropriate .register directive (default)\n\
683 -no-undeclared-regs force error on application global register usage\n\
684 without appropriate .register directive\n\
689 #ifdef SPARC_BIENDIAN
690 fprintf (stream, _("\
691 -EL generate code for a little endian machine\n\
692 -EB generate code for a big endian machine\n\
693 --little-endian-data generate code for a machine having big endian\n\
694 instructions and little endian data.\n"));
698 /* Native operand size opcode translation. */
704 } native_op_table[] =
706 {"ldn", "ld", "ldx"},
707 {"ldna", "lda", "ldxa"},
708 {"stn", "st", "stx"},
709 {"stna", "sta", "stxa"},
710 {"slln", "sll", "sllx"},
711 {"srln", "srl", "srlx"},
712 {"sran", "sra", "srax"},
713 {"casn", "cas", "casx"},
714 {"casna", "casa", "casxa"},
715 {"clrn", "clr", "clrx"},
719 /* sparc64 priviledged registers. */
721 struct priv_reg_entry
727 struct priv_reg_entry priv_reg_table[] =
746 {"", -1}, /* End marker. */
749 /* v9a specific asrs. */
751 struct priv_reg_entry v9a_asr_table[] =
754 {"sys_tick_cmpr", 25},
762 {"clear_softint", 21},
763 {"", -1}, /* End marker. */
767 cmp_reg_entry (parg, qarg)
771 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
772 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
774 return strcmp (q->name, p->name);
777 /* This function is called once, at assembler startup time. It should
778 set up all the tables, etc. that the MD part of the assembler will
784 register const char *retval = NULL;
786 register unsigned int i = 0;
788 /* We don't get a chance to initialize anything before md_parse_option
789 is called, and it may not be called, so handle default initialization
790 now if not already done. */
791 if (! default_init_p)
792 init_default_arch ();
794 op_hash = hash_new ();
796 while (i < (unsigned int) sparc_num_opcodes)
798 const char *name = sparc_opcodes[i].name;
799 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
802 as_bad (_("Internal error: can't hash `%s': %s\n"),
803 sparc_opcodes[i].name, retval);
808 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
810 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
811 sparc_opcodes[i].name, sparc_opcodes[i].args);
816 while (i < (unsigned int) sparc_num_opcodes
817 && !strcmp (sparc_opcodes[i].name, name));
820 for (i = 0; native_op_table[i].name; i++)
822 const struct sparc_opcode *insn;
823 char *name = ((sparc_arch_size == 32)
824 ? native_op_table[i].name32
825 : native_op_table[i].name64);
826 insn = (struct sparc_opcode *) hash_find (op_hash, name);
829 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
830 name, native_op_table[i].name);
835 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
838 as_bad (_("Internal error: can't hash `%s': %s\n"),
839 sparc_opcodes[i].name, retval);
846 as_fatal (_("Broken assembler. No assembly attempted."));
848 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
849 sizeof (priv_reg_table[0]), cmp_reg_entry);
851 /* If -bump, record the architecture level at which we start issuing
852 warnings. The behaviour is different depending upon whether an
853 architecture was explicitly specified. If it wasn't, we issue warnings
854 for all upwards bumps. If it was, we don't start issuing warnings until
855 we need to bump beyond the requested architecture or when we bump between
856 conflicting architectures. */
859 && architecture_requested)
861 /* `max_architecture' records the requested architecture.
862 Issue warnings if we go above it. */
863 warn_after_architecture = max_architecture;
865 /* Find the highest architecture level that doesn't conflict with
866 the requested one. */
867 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
868 max_architecture > warn_after_architecture;
870 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
871 warn_after_architecture))
876 /* Called after all assembly has been done. */
881 unsigned long mach = bfd_mach_sparc;
883 if (sparc_arch_size == 64)
884 switch (current_architecture)
886 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
887 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
888 default: mach = bfd_mach_sparc_v9; break;
891 switch (current_architecture)
893 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
894 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
895 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
896 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
897 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
898 be but for now it is (since that's the way it's always been
902 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
905 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
908 in_signed_range (val, max)
909 bfd_signed_vma val, max;
913 /* Sign-extend the value from the architecture word size, so that
914 0xffffffff is always considered -1 on sparc32. */
915 if (sparc_arch_size == 32)
917 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
918 val = ((val & 0xffffffff) ^ sign) - sign;
927 /* Return non-zero if VAL is in the range 0 to MAX. */
930 in_unsigned_range (val, max)
938 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
939 (e.g. -15 to +31). */
942 in_bitfield_range (val, max)
943 bfd_signed_vma val, max;
949 if (val < ~(max >> 1))
963 for (i = 0; (mask & 1) == 0; ++i)
968 /* Implement big shift right. */
974 if (sizeof (bfd_vma) <= 4 && amount >= 32)
975 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
976 return val >> amount;
979 /* For communication between sparc_ip and get_expression. */
980 static char *expr_end;
982 /* Values for `special_case'.
983 Instructions that require wierd handling because they're longer than
985 #define SPECIAL_CASE_NONE 0
986 #define SPECIAL_CASE_SET 1
987 #define SPECIAL_CASE_SETSW 2
988 #define SPECIAL_CASE_SETX 3
989 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
990 #define SPECIAL_CASE_FDIV 4
992 /* Bit masks of various insns. */
993 #define NOP_INSN 0x01000000
994 #define OR_INSN 0x80100000
995 #define XOR_INSN 0x80180000
996 #define FMOVS_INSN 0x81A00020
997 #define SETHI_INSN 0x01000000
998 #define SLLX_INSN 0x81281000
999 #define SRA_INSN 0x81380000
1001 /* The last instruction to be assembled. */
1002 static const struct sparc_opcode *last_insn;
1003 /* The assembled opcode of `last_insn'. */
1004 static unsigned long last_opcode;
1006 /* Handle the set and setuw synthetic instructions. */
1009 synthetize_setuw (insn)
1010 const struct sparc_opcode *insn;
1012 int need_hi22_p = 0;
1013 int rd = (the_insn.opcode & RD (~0)) >> 25;
1015 if (the_insn.exp.X_op == O_constant)
1017 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1019 if (sizeof (offsetT) > 4
1020 && (the_insn.exp.X_add_number < 0
1021 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1022 as_warn (_("set: number not in 0..4294967295 range"));
1026 if (sizeof (offsetT) > 4
1027 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1028 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1029 as_warn (_("set: number not in -2147483648..4294967295 range"));
1030 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1034 /* See if operand is absolute and small; skip sethi if so. */
1035 if (the_insn.exp.X_op != O_constant
1036 || the_insn.exp.X_add_number >= (1 << 12)
1037 || the_insn.exp.X_add_number < -(1 << 12))
1039 the_insn.opcode = (SETHI_INSN | RD (rd)
1040 | ((the_insn.exp.X_add_number >> 10)
1041 & (the_insn.exp.X_op == O_constant
1043 the_insn.reloc = (the_insn.exp.X_op != O_constant
1044 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1045 output_insn (insn, &the_insn);
1049 /* See if operand has no low-order bits; skip OR if so. */
1050 if (the_insn.exp.X_op != O_constant
1051 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1054 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1056 | (the_insn.exp.X_add_number
1057 & (the_insn.exp.X_op != O_constant
1058 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1059 the_insn.reloc = (the_insn.exp.X_op != O_constant
1060 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1061 output_insn (insn, &the_insn);
1065 /* Handle the setsw synthetic instruction. */
1068 synthetize_setsw (insn)
1069 const struct sparc_opcode *insn;
1073 rd = (the_insn.opcode & RD (~0)) >> 25;
1075 if (the_insn.exp.X_op != O_constant)
1077 synthetize_setuw (insn);
1079 /* Need to sign extend it. */
1080 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1081 the_insn.reloc = BFD_RELOC_NONE;
1082 output_insn (insn, &the_insn);
1086 if (sizeof (offsetT) > 4
1087 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1088 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1089 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1091 low32 = the_insn.exp.X_add_number;
1095 synthetize_setuw (insn);
1101 the_insn.reloc = BFD_RELOC_NONE;
1102 /* See if operand is absolute and small; skip sethi if so. */
1103 if (low32 < -(1 << 12))
1105 the_insn.opcode = (SETHI_INSN | RD (rd)
1106 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1107 output_insn (insn, &the_insn);
1108 low32 = 0x1c00 | (low32 & 0x3ff);
1109 opc = RS1 (rd) | XOR_INSN;
1112 the_insn.opcode = (opc | RD (rd) | IMMED
1113 | (low32 & 0x1fff));
1114 output_insn (insn, &the_insn);
1117 /* Handle the setsw synthetic instruction. */
1120 synthetize_setx (insn)
1121 const struct sparc_opcode *insn;
1123 int upper32, lower32;
1124 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1125 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1127 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1128 int need_xor10_p = 0;
1130 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1131 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1132 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1135 upper_dstreg = tmpreg;
1136 /* The tmp reg should not be the dst reg. */
1137 if (tmpreg == dstreg)
1138 as_warn (_("setx: temporary register same as destination register"));
1140 /* ??? Obviously there are other optimizations we can do
1141 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1142 doing some of these. Later. If you do change things, try to
1143 change all of this to be table driven as well. */
1144 /* What to output depends on the number if it's constant.
1145 Compute that first, then output what we've decided upon. */
1146 if (the_insn.exp.X_op != O_constant)
1148 if (sparc_arch_size == 32)
1150 /* When arch size is 32, we want setx to be equivalent
1151 to setuw for anything but constants. */
1152 the_insn.exp.X_add_number &= 0xffffffff;
1153 synthetize_setuw (insn);
1156 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1162 /* Reset X_add_number, we've extracted it as upper32/lower32.
1163 Otherwise fixup_segment will complain about not being able to
1164 write an 8 byte number in a 4 byte field. */
1165 the_insn.exp.X_add_number = 0;
1167 /* Only need hh22 if `or' insn can't handle constant. */
1168 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1171 /* Does bottom part (after sethi) have bits? */
1172 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1173 /* No hh22, but does upper32 still have bits we can't set
1175 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1178 /* If the lower half is all zero, we build the upper half directly
1179 into the dst reg. */
1181 /* Need lower half if number is zero or 0xffffffff00000000. */
1182 || (! need_hh22_p && ! need_hm10_p))
1184 /* No need for sethi if `or' insn can handle constant. */
1185 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1186 /* Note that we can't use a negative constant in the `or'
1187 insn unless the upper 32 bits are all ones. */
1188 || (lower32 < 0 && upper32 != -1)
1189 || (lower32 >= 0 && upper32 == -1))
1192 if (need_hi22_p && upper32 == -1)
1195 /* Does bottom part (after sethi) have bits? */
1196 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1198 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1199 /* Need `or' if we didn't set anything else. */
1200 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1204 /* Output directly to dst reg if lower 32 bits are all zero. */
1205 upper_dstreg = dstreg;
1208 if (!upper_dstreg && dstreg)
1209 as_warn (_("setx: illegal temporary register g0"));
1213 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1214 | ((upper32 >> 10) & 0x3fffff));
1215 the_insn.reloc = (the_insn.exp.X_op != O_constant
1216 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1217 output_insn (insn, &the_insn);
1222 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1223 | (((need_xor10_p ? ~lower32 : lower32)
1224 >> 10) & 0x3fffff));
1225 the_insn.reloc = (the_insn.exp.X_op != O_constant
1226 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1227 output_insn (insn, &the_insn);
1232 the_insn.opcode = (OR_INSN
1233 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1236 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1237 the_insn.reloc = (the_insn.exp.X_op != O_constant
1238 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1239 output_insn (insn, &the_insn);
1244 /* FIXME: One nice optimization to do here is to OR the low part
1245 with the highpart if hi22 isn't needed and the low part is
1247 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1250 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1251 the_insn.reloc = (the_insn.exp.X_op != O_constant
1252 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1253 output_insn (insn, &the_insn);
1256 /* If we needed to build the upper part, shift it into place. */
1257 if (need_hh22_p || need_hm10_p)
1259 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1261 the_insn.reloc = BFD_RELOC_NONE;
1262 output_insn (insn, &the_insn);
1265 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1268 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1269 | 0x1c00 | (lower32 & 0x3ff));
1270 the_insn.reloc = BFD_RELOC_NONE;
1271 output_insn (insn, &the_insn);
1274 /* If we needed to build both upper and lower parts, OR them together. */
1275 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1277 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1279 the_insn.reloc = BFD_RELOC_NONE;
1280 output_insn (insn, &the_insn);
1284 /* Main entry point to assemble one instruction. */
1290 const struct sparc_opcode *insn;
1294 special_case = sparc_ip (str, &insn);
1296 /* We warn about attempts to put a floating point branch in a delay slot,
1297 unless the delay slot has been annulled. */
1299 && last_insn != NULL
1300 && (insn->flags & F_FBR) != 0
1301 && (last_insn->flags & F_DELAYED) != 0
1302 /* ??? This test isn't completely accurate. We assume anything with
1303 F_{UNBR,CONDBR,FBR} set is annullable. */
1304 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1305 || (last_opcode & ANNUL) == 0))
1306 as_warn (_("FP branch in delay slot"));
1308 /* SPARC before v9 requires a nop instruction between a floating
1309 point instruction and a floating point branch. We insert one
1310 automatically, with a warning. */
1311 if (max_architecture < SPARC_OPCODE_ARCH_V9
1313 && last_insn != NULL
1314 && (insn->flags & F_FBR) != 0
1315 && (last_insn->flags & F_FLOAT) != 0)
1317 struct sparc_it nop_insn;
1319 nop_insn.opcode = NOP_INSN;
1320 nop_insn.reloc = BFD_RELOC_NONE;
1321 output_insn (insn, &nop_insn);
1322 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1325 switch (special_case)
1327 case SPECIAL_CASE_NONE:
1329 output_insn (insn, &the_insn);
1332 case SPECIAL_CASE_SETSW:
1333 synthetize_setsw (insn);
1336 case SPECIAL_CASE_SET:
1337 synthetize_setuw (insn);
1340 case SPECIAL_CASE_SETX:
1341 synthetize_setx (insn);
1344 case SPECIAL_CASE_FDIV:
1346 int rd = (the_insn.opcode >> 25) & 0x1f;
1348 output_insn (insn, &the_insn);
1350 /* According to information leaked from Sun, the "fdiv" instructions
1351 on early SPARC machines would produce incorrect results sometimes.
1352 The workaround is to add an fmovs of the destination register to
1353 itself just after the instruction. This was true on machines
1354 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1355 assert (the_insn.reloc == BFD_RELOC_NONE);
1356 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1357 output_insn (insn, &the_insn);
1362 as_fatal (_("failed special case insn sanity check"));
1366 /* Subroutine of md_assemble to do the actual parsing. */
1369 sparc_ip (str, pinsn)
1371 const struct sparc_opcode **pinsn;
1373 char *error_message = "";
1377 const struct sparc_opcode *insn;
1379 unsigned long opcode;
1380 unsigned int mask = 0;
1384 int special_case = SPECIAL_CASE_NONE;
1387 if (islower ((unsigned char) *s))
1391 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1408 as_fatal (_("Unknown opcode: `%s'"), str);
1410 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1414 as_bad (_("Unknown opcode: `%s'"), str);
1415 return special_case;
1425 opcode = insn->match;
1426 memset (&the_insn, '\0', sizeof (the_insn));
1427 the_insn.reloc = BFD_RELOC_NONE;
1430 /* Build the opcode, checking as we go to make sure that the
1432 for (args = insn->args;; ++args)
1440 /* Parse a series of masks. */
1447 if (! parse_keyword_arg (sparc_encode_membar, &s,
1450 error_message = _(": invalid membar mask name");
1456 if (*s == '|' || *s == '+')
1464 if (! parse_const_expr_arg (&s, &kmask))
1466 error_message = _(": invalid membar mask expression");
1469 if (kmask < 0 || kmask > 127)
1471 error_message = _(": invalid membar mask number");
1476 opcode |= MEMBAR (kmask);
1484 if (! parse_const_expr_arg (&s, &smask))
1486 error_message = _(": invalid siam mode expression");
1489 if (smask < 0 || smask > 7)
1491 error_message = _(": invalid siam mode number");
1502 /* Parse a prefetch function. */
1505 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1507 error_message = _(": invalid prefetch function name");
1513 if (! parse_const_expr_arg (&s, &fcn))
1515 error_message = _(": invalid prefetch function expression");
1518 if (fcn < 0 || fcn > 31)
1520 error_message = _(": invalid prefetch function number");
1530 /* Parse a sparc64 privileged register. */
1533 struct priv_reg_entry *p = priv_reg_table;
1534 unsigned int len = 9999999; /* Init to make gcc happy. */
1537 while (p->name[0] > s[0])
1539 while (p->name[0] == s[0])
1541 len = strlen (p->name);
1542 if (strncmp (p->name, s, len) == 0)
1546 if (p->name[0] != s[0])
1548 error_message = _(": unrecognizable privileged register");
1552 opcode |= (p->regnum << 14);
1554 opcode |= (p->regnum << 25);
1560 error_message = _(": unrecognizable privileged register");
1566 /* Parse a v9a/v9b ancillary state register. */
1569 struct priv_reg_entry *p = v9a_asr_table;
1570 unsigned int len = 9999999; /* Init to make gcc happy. */
1573 while (p->name[0] > s[0])
1575 while (p->name[0] == s[0])
1577 len = strlen (p->name);
1578 if (strncmp (p->name, s, len) == 0)
1582 if (p->name[0] != s[0])
1584 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1587 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1589 error_message = _(": rd on write only ancillary state register");
1593 && (insn->architecture
1594 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1596 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1597 error_message = _(": unrecognizable v9a ancillary state register");
1601 opcode |= (p->regnum << 14);
1603 opcode |= (p->regnum << 25);
1609 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1615 if (strncmp (s, "%asr", 4) == 0)
1619 if (isdigit ((unsigned char) *s))
1623 while (isdigit ((unsigned char) *s))
1625 num = num * 10 + *s - '0';
1629 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1631 if (num < 16 || 31 < num)
1633 error_message = _(": asr number must be between 16 and 31");
1639 if (num < 0 || 31 < num)
1641 error_message = _(": asr number must be between 0 and 31");
1646 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1651 error_message = _(": expecting %asrN");
1658 the_insn.reloc = BFD_RELOC_SPARC_11;
1662 the_insn.reloc = BFD_RELOC_SPARC_10;
1666 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1667 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1668 the_insn.reloc = BFD_RELOC_SPARC_5;
1670 the_insn.reloc = BFD_RELOC_SPARC13;
1671 /* These fields are unsigned, but for upward compatibility,
1672 allow negative values as well. */
1676 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1677 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1678 the_insn.reloc = BFD_RELOC_SPARC_6;
1680 the_insn.reloc = BFD_RELOC_SPARC13;
1681 /* These fields are unsigned, but for upward compatibility,
1682 allow negative values as well. */
1686 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1691 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1696 if (*s == 'p' && s[1] == 'n')
1704 if (*s == 'p' && s[1] == 't')
1716 if (strncmp (s, "%icc", 4) == 0)
1728 if (strncmp (s, "%xcc", 4) == 0)
1740 if (strncmp (s, "%fcc0", 5) == 0)
1752 if (strncmp (s, "%fcc1", 5) == 0)
1764 if (strncmp (s, "%fcc2", 5) == 0)
1776 if (strncmp (s, "%fcc3", 5) == 0)
1784 if (strncmp (s, "%pc", 3) == 0)
1792 if (strncmp (s, "%tick", 5) == 0)
1799 case '\0': /* End of args. */
1818 case '[': /* These must match exactly. */
1826 case '#': /* Must be at least one digit. */
1827 if (isdigit ((unsigned char) *s++))
1829 while (isdigit ((unsigned char) *s))
1837 case 'C': /* Coprocessor state register. */
1838 if (strncmp (s, "%csr", 4) == 0)
1845 case 'b': /* Next operand is a coprocessor register. */
1848 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1851 if (isdigit ((unsigned char) *s))
1853 mask = 10 * (mask - '0') + (*s++ - '0');
1867 opcode |= mask << 14;
1875 opcode |= mask << 25;
1881 case 'r': /* next operand must be a register */
1891 case 'f': /* frame pointer */
1899 case 'g': /* global register */
1908 case 'i': /* in register */
1912 mask = c - '0' + 24;
1917 case 'l': /* local register */
1921 mask = (c - '0' + 16);
1926 case 'o': /* out register */
1930 mask = (c - '0' + 8);
1935 case 's': /* stack pointer */
1943 case 'r': /* any register */
1944 if (!isdigit ((unsigned char) (c = *s++)))
1959 if (isdigit ((unsigned char) *s))
1961 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1977 if ((mask & ~1) == 2 && sparc_arch_size == 64
1978 && no_undeclared_regs && ! globals[mask])
1979 as_bad (_("detected global register use not covered by .register pseudo-op"));
1981 /* Got the register, now figure out where
1982 it goes in the opcode. */
1986 opcode |= mask << 14;
1994 opcode |= mask << 25;
1998 opcode |= (mask << 25) | (mask << 14);
2002 opcode |= (mask << 25) | (mask << 0);
2008 case 'e': /* next operand is a floating point register */
2023 && ((format = *s) == 'f')
2024 && isdigit ((unsigned char) *++s))
2026 for (mask = 0; isdigit ((unsigned char) *s); ++s)
2028 mask = 10 * mask + (*s - '0');
2029 } /* read the number */
2037 } /* register must be even numbered */
2045 } /* register must be multiple of 4 */
2049 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2050 error_message = _(": There are only 64 f registers; [0-63]");
2052 error_message = _(": There are only 32 f registers; [0-31]");
2055 else if (mask >= 32)
2057 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2060 mask -= 31; /* wrap high bit */
2064 error_message = _(": There are only 32 f registers; [0-31]");
2072 } /* if not an 'f' register. */
2079 opcode |= RS1 (mask);
2085 opcode |= RS2 (mask);
2091 opcode |= RD (mask);
2100 if (strncmp (s, "%fsr", 4) == 0)
2107 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2108 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2111 case 'l': /* 22 bit PC relative immediate */
2112 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2116 case 'L': /* 30 bit immediate */
2117 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2122 case 'n': /* 22 bit immediate */
2123 the_insn.reloc = BFD_RELOC_SPARC22;
2126 case 'i': /* 13 bit immediate */
2127 the_insn.reloc = BFD_RELOC_SPARC13;
2137 char *op_arg = NULL;
2139 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2141 /* Check for %hi, etc. */
2144 static const struct ops {
2145 /* The name as it appears in assembler. */
2147 /* strlen (name), precomputed for speed */
2149 /* The reloc this pseudo-op translates to. */
2151 /* Non-zero if for v9 only. */
2153 /* Non-zero if can be used in pc-relative contexts. */
2154 int pcrel_p;/*FIXME:wip*/
2156 /* hix/lox must appear before hi/lo so %hix won't be
2157 mistaken for %hi. */
2158 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2159 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2160 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2161 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2162 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2163 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2164 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2165 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2166 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2167 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2168 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2169 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2170 { NULL, 0, 0, 0, 0 }
2172 const struct ops *o;
2174 for (o = ops; o->name; o++)
2175 if (strncmp (s + 1, o->name, o->len) == 0)
2177 if (o->name == NULL)
2180 if (s[o->len + 1] != '(')
2182 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2183 return special_case;
2187 the_insn.reloc = o->reloc;
2192 /* Note that if the get_expression() fails, we will still
2193 have created U entries in the symbol table for the
2194 'symbols' in the input string. Try not to create U
2195 symbols for registers, etc. */
2197 /* This stuff checks to see if the expression ends in
2198 +%reg. If it does, it removes the register from
2199 the expression, and re-sets 's' to point to the
2206 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2209 else if (*s1 == ')')
2218 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2219 return special_case;
2223 (void) get_expression (s);
2226 if (*s == ',' || *s == ']' || !*s)
2228 if (*s != '+' && *s != '-')
2230 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2231 return special_case;
2235 op_exp = the_insn.exp;
2236 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2239 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2242 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2244 if (s1[-2] == '%' && s1[-3] == '+')
2246 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2253 if (op_arg && s1 == s + 1)
2254 the_insn.exp.X_op = O_absent;
2256 (void) get_expression (s);
2268 (void) get_expression (s);
2276 the_insn.exp2 = the_insn.exp;
2277 the_insn.exp = op_exp;
2278 if (the_insn.exp2.X_op == O_absent)
2279 the_insn.exp2.X_op = O_illegal;
2280 else if (the_insn.exp.X_op == O_absent)
2282 the_insn.exp = the_insn.exp2;
2283 the_insn.exp2.X_op = O_illegal;
2285 else if (the_insn.exp.X_op == O_constant)
2287 valueT val = the_insn.exp.X_add_number;
2288 switch (the_insn.reloc)
2293 case BFD_RELOC_SPARC_HH22:
2294 val = BSR (val, 32);
2297 case BFD_RELOC_SPARC_LM22:
2298 case BFD_RELOC_HI22:
2299 val = (val >> 10) & 0x3fffff;
2302 case BFD_RELOC_SPARC_HM10:
2303 val = BSR (val, 32);
2306 case BFD_RELOC_LO10:
2310 case BFD_RELOC_SPARC_H44:
2315 case BFD_RELOC_SPARC_M44:
2320 case BFD_RELOC_SPARC_L44:
2324 case BFD_RELOC_SPARC_HIX22:
2326 val = (val >> 10) & 0x3fffff;
2329 case BFD_RELOC_SPARC_LOX10:
2330 val = (val & 0x3ff) | 0x1c00;
2333 the_insn.exp = the_insn.exp2;
2334 the_insn.exp.X_add_number += val;
2335 the_insn.exp2.X_op = O_illegal;
2336 the_insn.reloc = old_reloc;
2338 else if (the_insn.exp2.X_op != O_constant)
2340 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2341 return special_case;
2345 if (old_reloc != BFD_RELOC_SPARC13
2346 || the_insn.reloc != BFD_RELOC_LO10
2347 || sparc_arch_size != 64
2350 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2351 return special_case;
2353 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2357 /* Check for constants that don't require emitting a reloc. */
2358 if (the_insn.exp.X_op == O_constant
2359 && the_insn.exp.X_add_symbol == 0
2360 && the_insn.exp.X_op_symbol == 0)
2362 /* For pc-relative call instructions, we reject
2363 constants to get better code. */
2365 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2366 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2368 error_message = _(": PC-relative operand can't be a constant");
2372 /* Constants that won't fit are checked in md_apply_fix3
2373 and bfd_install_relocation.
2374 ??? It would be preferable to install the constants
2375 into the insn here and save having to create a fixS
2376 for each one. There already exists code to handle
2377 all the various cases (e.g. in md_apply_fix3 and
2378 bfd_install_relocation) so duplicating all that code
2379 here isn't right. */
2399 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2401 error_message = _(": invalid ASI name");
2407 if (! parse_const_expr_arg (&s, &asi))
2409 error_message = _(": invalid ASI expression");
2412 if (asi < 0 || asi > 255)
2414 error_message = _(": invalid ASI number");
2418 opcode |= ASI (asi);
2420 } /* Alternate space. */
2423 if (strncmp (s, "%psr", 4) == 0)
2430 case 'q': /* Floating point queue. */
2431 if (strncmp (s, "%fq", 3) == 0)
2438 case 'Q': /* Coprocessor queue. */
2439 if (strncmp (s, "%cq", 3) == 0)
2447 if (strcmp (str, "set") == 0
2448 || strcmp (str, "setuw") == 0)
2450 special_case = SPECIAL_CASE_SET;
2453 else if (strcmp (str, "setsw") == 0)
2455 special_case = SPECIAL_CASE_SETSW;
2458 else if (strcmp (str, "setx") == 0)
2460 special_case = SPECIAL_CASE_SETX;
2463 else if (strncmp (str, "fdiv", 4) == 0)
2465 special_case = SPECIAL_CASE_FDIV;
2471 if (strncmp (s, "%asi", 4) != 0)
2477 if (strncmp (s, "%fprs", 5) != 0)
2483 if (strncmp (s, "%ccr", 4) != 0)
2489 if (strncmp (s, "%tbr", 4) != 0)
2495 if (strncmp (s, "%wim", 4) != 0)
2502 char *push = input_line_pointer;
2505 input_line_pointer = s;
2507 if (e.X_op == O_constant)
2509 int n = e.X_add_number;
2510 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2511 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2513 opcode |= e.X_add_number << 5;
2516 as_bad (_("non-immediate OPF operand, ignored"));
2517 s = input_line_pointer;
2518 input_line_pointer = push;
2523 if (strncmp (s, "%y", 2) != 0)
2531 /* Parse a sparclet cpreg. */
2533 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2535 error_message = _(": invalid cpreg name");
2538 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2543 as_fatal (_("failed sanity check."));
2544 } /* switch on arg code. */
2546 /* Break out of for() loop. */
2548 } /* For each arg that we expect. */
2553 /* Args don't match. */
2554 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2555 && (insn->name == insn[1].name
2556 || !strcmp (insn->name, insn[1].name)))
2564 as_bad (_("Illegal operands%s"), error_message);
2565 return special_case;
2570 /* We have a match. Now see if the architecture is OK. */
2571 int needed_arch_mask = insn->architecture;
2576 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2577 if (! needed_arch_mask)
2579 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2582 if (needed_arch_mask
2583 & SPARC_OPCODE_SUPPORTED (current_architecture))
2586 /* Can we bump up the architecture? */
2587 else if (needed_arch_mask
2588 & SPARC_OPCODE_SUPPORTED (max_architecture))
2590 enum sparc_opcode_arch_val needed_architecture =
2591 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2592 & needed_arch_mask);
2594 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2596 && needed_architecture > warn_after_architecture)
2598 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2599 sparc_opcode_archs[current_architecture].name,
2600 sparc_opcode_archs[needed_architecture].name,
2602 warn_after_architecture = needed_architecture;
2604 current_architecture = needed_architecture;
2607 /* ??? This seems to be a bit fragile. What if the next entry in
2608 the opcode table is the one we want and it is supported?
2609 It is possible to arrange the table today so that this can't
2610 happen but what about tomorrow? */
2613 int arch, printed_one_p = 0;
2615 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2617 /* Create a list of the architectures that support the insn. */
2618 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2620 arch = sparc_ffs (needed_arch_mask);
2621 while ((1 << arch) <= needed_arch_mask)
2623 if ((1 << arch) & needed_arch_mask)
2627 strcpy (p, sparc_opcode_archs[arch].name);
2634 as_bad (_("Architecture mismatch on \"%s\"."), str);
2635 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2637 sparc_opcode_archs[max_architecture].name);
2638 return special_case;
2640 } /* If no match. */
2643 } /* Forever looking for a match. */
2645 the_insn.opcode = opcode;
2646 return special_case;
2649 /* Parse an argument that can be expressed as a keyword.
2650 (eg: #StoreStore or %ccfr).
2651 The result is a boolean indicating success.
2652 If successful, INPUT_POINTER is updated. */
2655 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2656 int (*lookup_fn) PARAMS ((const char *));
2657 char **input_pointerP;
2663 p = *input_pointerP;
2664 for (q = p + (*p == '#' || *p == '%');
2665 isalnum ((unsigned char) *q) || *q == '_';
2670 value = (*lookup_fn) (p);
2675 *input_pointerP = q;
2679 /* Parse an argument that is a constant expression.
2680 The result is a boolean indicating success. */
2683 parse_const_expr_arg (input_pointerP, valueP)
2684 char **input_pointerP;
2687 char *save = input_line_pointer;
2690 input_line_pointer = *input_pointerP;
2691 /* The next expression may be something other than a constant
2692 (say if we're not processing the right variant of the insn).
2693 Don't call expression unless we're sure it will succeed as it will
2694 signal an error (which we want to defer until later). */
2695 /* FIXME: It might be better to define md_operand and have it recognize
2696 things like %asi, etc. but continuing that route through to the end
2697 is a lot of work. */
2698 if (*input_line_pointer == '%')
2700 input_line_pointer = save;
2704 *input_pointerP = input_line_pointer;
2705 input_line_pointer = save;
2706 if (exp.X_op != O_constant)
2708 *valueP = exp.X_add_number;
2712 /* Subroutine of sparc_ip to parse an expression. */
2715 get_expression (str)
2721 save_in = input_line_pointer;
2722 input_line_pointer = str;
2723 seg = expression (&the_insn.exp);
2724 if (seg != absolute_section
2725 && seg != text_section
2726 && seg != data_section
2727 && seg != bss_section
2728 && seg != undefined_section)
2730 the_insn.error = _("bad segment");
2731 expr_end = input_line_pointer;
2732 input_line_pointer = save_in;
2735 expr_end = input_line_pointer;
2736 input_line_pointer = save_in;
2740 /* Subroutine of md_assemble to output one insn. */
2743 output_insn (insn, the_insn)
2744 const struct sparc_opcode *insn;
2745 struct sparc_it *the_insn;
2747 char *toP = frag_more (4);
2749 /* Put out the opcode. */
2750 if (INSN_BIG_ENDIAN)
2751 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2753 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2755 /* Put out the symbol-dependent stuff. */
2756 if (the_insn->reloc != BFD_RELOC_NONE)
2758 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2759 (toP - frag_now->fr_literal), /* Where. */
2764 /* Turn off overflow checking in fixup_segment. We'll do our
2765 own overflow checking in md_apply_fix3. This is necessary because
2766 the insn size is 4 and fixup_segment will signal an overflow for
2767 large 8 byte quantities. */
2768 fixP->fx_no_overflow = 1;
2769 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2770 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2774 last_opcode = the_insn->opcode;
2777 dwarf2_emit_insn (4);
2781 /* This is identical to the md_atof in m68k.c. I think this is right,
2784 Turn a string in input_line_pointer into a floating point constant
2785 of type TYPE, and store the appropriate bytes in *LITP. The number
2786 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2787 returned, or NULL on OK. */
2789 /* Equal to MAX_PRECISION in atof-ieee.c. */
2790 #define MAX_LITTLENUMS 6
2793 md_atof (type, litP, sizeP)
2799 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2830 return _("Bad call to MD_ATOF()");
2833 t = atof_ieee (input_line_pointer, type, words);
2835 input_line_pointer = t;
2836 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2838 if (target_big_endian)
2840 for (i = 0; i < prec; i++)
2842 md_number_to_chars (litP, (valueT) words[i],
2843 sizeof (LITTLENUM_TYPE));
2844 litP += sizeof (LITTLENUM_TYPE);
2849 for (i = prec - 1; i >= 0; i--)
2851 md_number_to_chars (litP, (valueT) words[i],
2852 sizeof (LITTLENUM_TYPE));
2853 litP += sizeof (LITTLENUM_TYPE);
2860 /* Write a value out to the object file, using the appropriate
2864 md_number_to_chars (buf, val, n)
2869 if (target_big_endian)
2870 number_to_chars_bigendian (buf, val, n);
2871 else if (target_little_endian_data
2872 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2873 /* Output debug words, which are not in allocated sections, as big
2875 number_to_chars_bigendian (buf, val, n);
2876 else if (target_little_endian_data || ! target_big_endian)
2877 number_to_chars_littleendian (buf, val, n);
2880 /* Apply a fixS to the frags, now that we know the value it ought to
2884 md_apply_fix3 (fixP, value, segment)
2889 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2895 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2897 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2900 /* FIXME: SPARC ELF relocations don't use an addend in the data
2901 field itself. This whole approach should be somehow combined
2902 with the calls to bfd_install_relocation. Also, the value passed
2903 in by fixup_segment includes the value of a defined symbol. We
2904 don't want to include the value of an externally visible symbol. */
2905 if (fixP->fx_addsy != NULL)
2907 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2908 && (S_IS_EXTERNAL (fixP->fx_addsy)
2909 || S_IS_WEAK (fixP->fx_addsy)
2910 || (sparc_pic_code && ! fixP->fx_pcrel)
2911 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2912 && ((bfd_get_section_flags (stdoutput,
2913 S_GET_SEGMENT (fixP->fx_addsy))
2914 & SEC_LINK_ONCE) != 0
2915 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2917 sizeof ".gnu.linkonce" - 1) == 0)))
2918 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2919 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2920 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2921 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2926 /* This is a hack. There should be a better way to
2927 handle this. Probably in terms of howto fields, once
2928 we can look at these fixups in terms of howtos. */
2929 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2930 val += fixP->fx_where + fixP->fx_frag->fr_address;
2933 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2934 generate a reloc, then we just want to let the reloc addend set
2935 the value. We do not want to also stuff the addend into the
2936 object file. Including the addend in the object file works when
2937 doing a static link, because the linker will ignore the object
2938 file contents. However, the dynamic linker does not ignore the
2939 object file contents. */
2940 if (fixP->fx_addsy != NULL
2941 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2944 /* When generating PIC code, we do not want an addend for a reloc
2945 against a local symbol. We adjust fx_addnumber to cancel out the
2946 value already included in val, and to also cancel out the
2947 adjustment which bfd_install_relocation will create. */
2949 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2950 && fixP->fx_addsy != NULL
2951 && ! S_IS_COMMON (fixP->fx_addsy)
2952 && symbol_section_p (fixP->fx_addsy))
2953 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2955 /* When generating PIC code, we need to fiddle to get
2956 bfd_install_relocation to do the right thing for a PC relative
2957 reloc against a local symbol which we are going to keep. */
2959 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2960 && fixP->fx_addsy != NULL
2961 && (S_IS_EXTERNAL (fixP->fx_addsy)
2962 || S_IS_WEAK (fixP->fx_addsy))
2963 && S_IS_DEFINED (fixP->fx_addsy)
2964 && ! S_IS_COMMON (fixP->fx_addsy))
2967 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2971 /* If this is a data relocation, just output VAL. */
2973 if (fixP->fx_r_type == BFD_RELOC_16)
2975 md_number_to_chars (buf, val, 2);
2977 else if (fixP->fx_r_type == BFD_RELOC_32
2978 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2980 md_number_to_chars (buf, val, 4);
2982 else if (fixP->fx_r_type == BFD_RELOC_64)
2984 md_number_to_chars (buf, val, 8);
2986 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2987 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2994 /* It's a relocation against an instruction. */
2996 if (INSN_BIG_ENDIAN)
2997 insn = bfd_getb32 ((unsigned char *) buf);
2999 insn = bfd_getl32 ((unsigned char *) buf);
3001 switch (fixP->fx_r_type)
3003 case BFD_RELOC_32_PCREL_S2:
3005 /* FIXME: This increment-by-one deserves a comment of why it's
3007 if (! sparc_pic_code
3008 || fixP->fx_addsy == NULL
3009 || symbol_section_p (fixP->fx_addsy))
3012 insn |= val & 0x3fffffff;
3014 /* See if we have a delay slot. */
3015 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3019 #define XCC (2 << 20)
3020 #define COND(x) (((x)&0xf)<<25)
3021 #define CONDA COND(0x8)
3022 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3023 #define INSN_BA (F2(0,2) | CONDA)
3024 #define INSN_OR F3(2, 0x2, 0)
3025 #define INSN_NOP F2(0,4)
3029 /* If the instruction is a call with either:
3031 arithmetic instruction with rd == %o7
3032 where rs1 != %o7 and rs2 if it is register != %o7
3033 then we can optimize if the call destination is near
3034 by changing the call into a branch always. */
3035 if (INSN_BIG_ENDIAN)
3036 delay = bfd_getb32 ((unsigned char *) buf + 4);
3038 delay = bfd_getl32 ((unsigned char *) buf + 4);
3039 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3041 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3042 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3043 || ((delay & RD (~0)) != RD (O7))))
3045 if ((delay & RS1 (~0)) == RS1 (O7)
3046 || ((delay & F3I (~0)) == 0
3047 && (delay & RS2 (~0)) == RS2 (O7)))
3049 /* Ensure the branch will fit into simm22. */
3050 if ((val & 0x3fe00000)
3051 && (val & 0x3fe00000) != 0x3fe00000)
3053 /* Check if the arch is v9 and branch will fit
3055 if (((val & 0x3c0000) == 0
3056 || (val & 0x3c0000) == 0x3c0000)
3057 && (sparc_arch_size == 64
3058 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3060 insn = INSN_BPA | (val & 0x7ffff);
3063 insn = INSN_BA | (val & 0x3fffff);
3064 if (fixP->fx_where >= 4
3065 && ((delay & (0xffffffff ^ RS1 (~0)))
3066 == (INSN_OR | RD (O7) | RS2 (G0))))
3071 if (INSN_BIG_ENDIAN)
3072 setter = bfd_getb32 ((unsigned char *) buf - 4);
3074 setter = bfd_getl32 ((unsigned char *) buf - 4);
3075 if ((setter & (0xffffffff ^ RD (~0)))
3076 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3083 If call foo was replaced with ba, replace
3084 or %rN, %g0, %o7 with nop. */
3085 reg = (delay & RS1 (~0)) >> 14;
3086 if (reg != ((setter & RD (~0)) >> 25)
3087 || reg == G0 || reg == O7)
3090 if (INSN_BIG_ENDIAN)
3091 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3093 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3098 case BFD_RELOC_SPARC_11:
3099 if (! in_signed_range (val, 0x7ff))
3100 as_bad_where (fixP->fx_file, fixP->fx_line,
3101 _("relocation overflow"));
3102 insn |= val & 0x7ff;
3105 case BFD_RELOC_SPARC_10:
3106 if (! in_signed_range (val, 0x3ff))
3107 as_bad_where (fixP->fx_file, fixP->fx_line,
3108 _("relocation overflow"));
3109 insn |= val & 0x3ff;
3112 case BFD_RELOC_SPARC_7:
3113 if (! in_bitfield_range (val, 0x7f))
3114 as_bad_where (fixP->fx_file, fixP->fx_line,
3115 _("relocation overflow"));
3119 case BFD_RELOC_SPARC_6:
3120 if (! in_bitfield_range (val, 0x3f))
3121 as_bad_where (fixP->fx_file, fixP->fx_line,
3122 _("relocation overflow"));
3126 case BFD_RELOC_SPARC_5:
3127 if (! in_bitfield_range (val, 0x1f))
3128 as_bad_where (fixP->fx_file, fixP->fx_line,
3129 _("relocation overflow"));
3133 case BFD_RELOC_SPARC_WDISP16:
3134 /* FIXME: simplify. */
3135 if (((val > 0) && (val & ~0x3fffc))
3136 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3137 as_bad_where (fixP->fx_file, fixP->fx_line,
3138 _("relocation overflow"));
3139 /* FIXME: The +1 deserves a comment. */
3140 val = (val >> 2) + 1;
3141 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3144 case BFD_RELOC_SPARC_WDISP19:
3145 /* FIXME: simplify. */
3146 if (((val > 0) && (val & ~0x1ffffc))
3147 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3148 as_bad_where (fixP->fx_file, fixP->fx_line,
3149 _("relocation overflow"));
3150 /* FIXME: The +1 deserves a comment. */
3151 val = (val >> 2) + 1;
3152 insn |= val & 0x7ffff;
3155 case BFD_RELOC_SPARC_HH22:
3156 val = BSR (val, 32);
3159 case BFD_RELOC_SPARC_LM22:
3160 case BFD_RELOC_HI22:
3161 if (!fixP->fx_addsy)
3163 insn |= (val >> 10) & 0x3fffff;
3167 /* FIXME: Need comment explaining why we do this. */
3172 case BFD_RELOC_SPARC22:
3173 if (val & ~0x003fffff)
3174 as_bad_where (fixP->fx_file, fixP->fx_line,
3175 _("relocation overflow"));
3176 insn |= (val & 0x3fffff);
3179 case BFD_RELOC_SPARC_HM10:
3180 val = BSR (val, 32);
3183 case BFD_RELOC_LO10:
3184 if (!fixP->fx_addsy)
3186 insn |= val & 0x3ff;
3190 /* FIXME: Need comment explaining why we do this. */
3195 case BFD_RELOC_SPARC_OLO10:
3197 val += fixP->tc_fix_data;
3200 case BFD_RELOC_SPARC13:
3201 if (! in_signed_range (val, 0x1fff))
3202 as_bad_where (fixP->fx_file, fixP->fx_line,
3203 _("relocation overflow"));
3204 insn |= val & 0x1fff;
3207 case BFD_RELOC_SPARC_WDISP22:
3208 val = (val >> 2) + 1;
3210 case BFD_RELOC_SPARC_BASE22:
3211 insn |= val & 0x3fffff;
3214 case BFD_RELOC_SPARC_H44:
3215 if (!fixP->fx_addsy)
3219 insn |= tval & 0x3fffff;
3223 case BFD_RELOC_SPARC_M44:
3224 if (!fixP->fx_addsy)
3225 insn |= (val >> 12) & 0x3ff;
3228 case BFD_RELOC_SPARC_L44:
3229 if (!fixP->fx_addsy)
3230 insn |= val & 0xfff;
3233 case BFD_RELOC_SPARC_HIX22:
3234 if (!fixP->fx_addsy)
3236 val ^= ~(offsetT) 0;
3237 insn |= (val >> 10) & 0x3fffff;
3241 case BFD_RELOC_SPARC_LOX10:
3242 if (!fixP->fx_addsy)
3243 insn |= 0x1c00 | (val & 0x3ff);
3246 case BFD_RELOC_NONE:
3248 as_bad_where (fixP->fx_file, fixP->fx_line,
3249 _("bad or unhandled relocation type: 0x%02x"),
3254 if (INSN_BIG_ENDIAN)
3255 bfd_putb32 (insn, (unsigned char *) buf);
3257 bfd_putl32 (insn, (unsigned char *) buf);
3260 /* Are we finished with this relocation now? */
3261 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3267 /* Translate internal representation of relocation info to BFD target
3271 tc_gen_reloc (section, fixp)
3275 static arelent *relocs[3];
3277 bfd_reloc_code_real_type code;
3279 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3282 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3283 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3284 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3286 switch (fixp->fx_r_type)
3290 case BFD_RELOC_HI22:
3291 case BFD_RELOC_LO10:
3292 case BFD_RELOC_32_PCREL_S2:
3293 case BFD_RELOC_SPARC13:
3294 case BFD_RELOC_SPARC22:
3295 case BFD_RELOC_SPARC_BASE13:
3296 case BFD_RELOC_SPARC_WDISP16:
3297 case BFD_RELOC_SPARC_WDISP19:
3298 case BFD_RELOC_SPARC_WDISP22:
3300 case BFD_RELOC_SPARC_5:
3301 case BFD_RELOC_SPARC_6:
3302 case BFD_RELOC_SPARC_7:
3303 case BFD_RELOC_SPARC_10:
3304 case BFD_RELOC_SPARC_11:
3305 case BFD_RELOC_SPARC_HH22:
3306 case BFD_RELOC_SPARC_HM10:
3307 case BFD_RELOC_SPARC_LM22:
3308 case BFD_RELOC_SPARC_PC_HH22:
3309 case BFD_RELOC_SPARC_PC_HM10:
3310 case BFD_RELOC_SPARC_PC_LM22:
3311 case BFD_RELOC_SPARC_H44:
3312 case BFD_RELOC_SPARC_M44:
3313 case BFD_RELOC_SPARC_L44:
3314 case BFD_RELOC_SPARC_HIX22:
3315 case BFD_RELOC_SPARC_LOX10:
3316 case BFD_RELOC_SPARC_REV32:
3317 case BFD_RELOC_SPARC_OLO10:
3318 case BFD_RELOC_VTABLE_ENTRY:
3319 case BFD_RELOC_VTABLE_INHERIT:
3320 code = fixp->fx_r_type;
3327 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3328 /* If we are generating PIC code, we need to generate a different
3332 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3334 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3337 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3343 case BFD_RELOC_32_PCREL_S2:
3344 if (! S_IS_DEFINED (fixp->fx_addsy)
3345 || S_IS_COMMON (fixp->fx_addsy)
3346 || S_IS_EXTERNAL (fixp->fx_addsy)
3347 || S_IS_WEAK (fixp->fx_addsy))
3348 code = BFD_RELOC_SPARC_WPLT30;
3350 case BFD_RELOC_HI22:
3351 if (fixp->fx_addsy != NULL
3352 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3353 code = BFD_RELOC_SPARC_PC22;
3355 code = BFD_RELOC_SPARC_GOT22;
3357 case BFD_RELOC_LO10:
3358 if (fixp->fx_addsy != NULL
3359 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3360 code = BFD_RELOC_SPARC_PC10;
3362 code = BFD_RELOC_SPARC_GOT10;
3364 case BFD_RELOC_SPARC13:
3365 code = BFD_RELOC_SPARC_GOT13;
3371 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3373 if (code == BFD_RELOC_SPARC_OLO10)
3374 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3376 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3377 if (reloc->howto == 0)
3379 as_bad_where (fixp->fx_file, fixp->fx_line,
3380 _("internal error: can't export reloc type %d (`%s')"),
3381 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3387 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3390 if (reloc->howto->pc_relative == 0
3391 || code == BFD_RELOC_SPARC_PC10
3392 || code == BFD_RELOC_SPARC_PC22)
3393 reloc->addend = fixp->fx_addnumber;
3394 else if (sparc_pic_code
3395 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3396 && fixp->fx_addsy != NULL
3397 && (S_IS_EXTERNAL (fixp->fx_addsy)
3398 || S_IS_WEAK (fixp->fx_addsy))
3399 && S_IS_DEFINED (fixp->fx_addsy)
3400 && ! S_IS_COMMON (fixp->fx_addsy))
3401 reloc->addend = fixp->fx_addnumber;
3403 reloc->addend = fixp->fx_offset - reloc->address;
3405 #else /* elf or coff */
3407 if (reloc->howto->pc_relative == 0
3408 || code == BFD_RELOC_SPARC_PC10
3409 || code == BFD_RELOC_SPARC_PC22)
3410 reloc->addend = fixp->fx_addnumber;
3411 else if (symbol_section_p (fixp->fx_addsy))
3412 reloc->addend = (section->vma
3413 + fixp->fx_addnumber
3414 + md_pcrel_from (fixp));
3416 reloc->addend = fixp->fx_offset;
3419 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3420 on the same location. */
3421 if (code == BFD_RELOC_SPARC_OLO10)
3423 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3426 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3428 = symbol_get_bfdsym (section_symbol (absolute_section));
3429 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3430 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3431 reloc->addend = fixp->tc_fix_data;
3437 /* We have no need to default values of symbols. */
3440 md_undefined_symbol (name)
3441 char *name ATTRIBUTE_UNUSED;
3446 /* Round up a section size to the appropriate boundary. */
3449 md_section_align (segment, size)
3450 segT segment ATTRIBUTE_UNUSED;
3454 /* This is not right for ELF; a.out wants it, and COFF will force
3455 the alignment anyways. */
3456 valueT align = ((valueT) 1
3457 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3460 /* Turn alignment value into a mask. */
3462 newsize = (size + align) & ~align;
3469 /* Exactly what point is a PC-relative offset relative TO?
3470 On the sparc, they're relative to the address of the offset, plus
3471 its size. This gets us to the following instruction.
3472 (??? Is this right? FIXME-SOON) */
3474 md_pcrel_from (fixP)
3479 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3480 if (! sparc_pic_code
3481 || fixP->fx_addsy == NULL
3482 || symbol_section_p (fixP->fx_addsy))
3483 ret += fixP->fx_size;
3487 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3499 for (shift = 0; (value & 1) == 0; value >>= 1)
3502 return (value == 1) ? shift : -1;
3505 /* Sort of like s_lcomm. */
3508 static int max_alignment = 15;
3513 int ignore ATTRIBUTE_UNUSED;
3523 name = input_line_pointer;
3524 c = get_symbol_end ();
3525 p = input_line_pointer;
3529 if (*input_line_pointer != ',')
3531 as_bad (_("Expected comma after name"));
3532 ignore_rest_of_line ();
3536 ++input_line_pointer;
3538 if ((size = get_absolute_expression ()) < 0)
3540 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3541 ignore_rest_of_line ();
3546 symbolP = symbol_find_or_make (name);
3549 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3550 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3552 as_bad (_("bad .reserve segment -- expected BSS segment"));
3556 if (input_line_pointer[2] == '.')
3557 input_line_pointer += 7;
3559 input_line_pointer += 6;
3562 if (*input_line_pointer == ',')
3564 ++input_line_pointer;
3567 if (*input_line_pointer == '\n')
3569 as_bad (_("missing alignment"));
3570 ignore_rest_of_line ();
3574 align = (int) get_absolute_expression ();
3577 if (align > max_alignment)
3579 align = max_alignment;
3580 as_warn (_("alignment too large; assuming %d"), align);
3586 as_bad (_("negative alignment"));
3587 ignore_rest_of_line ();
3593 temp = log2 (align);
3596 as_bad (_("alignment not a power of 2"));
3597 ignore_rest_of_line ();
3604 record_alignment (bss_section, align);
3609 if (!S_IS_DEFINED (symbolP)
3611 && S_GET_OTHER (symbolP) == 0
3612 && S_GET_DESC (symbolP) == 0
3619 segT current_seg = now_seg;
3620 subsegT current_subseg = now_subseg;
3622 /* Switch to bss. */
3623 subseg_set (bss_section, 1);
3627 frag_align (align, 0, 0);
3629 /* Detach from old frag. */
3630 if (S_GET_SEGMENT (symbolP) == bss_section)
3631 symbol_get_frag (symbolP)->fr_symbol = NULL;
3633 symbol_set_frag (symbolP, frag_now);
3634 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3635 (offsetT) size, (char *) 0);
3638 S_SET_SEGMENT (symbolP, bss_section);
3640 subseg_set (current_seg, current_subseg);
3643 S_SET_SIZE (symbolP, size);
3649 as_warn ("Ignoring attempt to re-define symbol %s",
3650 S_GET_NAME (symbolP));
3651 } /* if not redefining. */
3653 demand_empty_rest_of_line ();
3658 int ignore ATTRIBUTE_UNUSED;
3666 name = input_line_pointer;
3667 c = get_symbol_end ();
3668 /* Just after name is now '\0'. */
3669 p = input_line_pointer;
3672 if (*input_line_pointer != ',')
3674 as_bad (_("Expected comma after symbol-name"));
3675 ignore_rest_of_line ();
3680 input_line_pointer++;
3682 if ((temp = get_absolute_expression ()) < 0)
3684 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3685 ignore_rest_of_line ();
3690 symbolP = symbol_find_or_make (name);
3692 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3694 as_bad (_("Ignoring attempt to re-define symbol"));
3695 ignore_rest_of_line ();
3698 if (S_GET_VALUE (symbolP) != 0)
3700 if (S_GET_VALUE (symbolP) != (valueT) size)
3702 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3703 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3709 S_SET_VALUE (symbolP, (valueT) size);
3710 S_SET_EXTERNAL (symbolP);
3713 know (symbol_get_frag (symbolP) == &zero_address_frag);
3714 if (*input_line_pointer != ',')
3716 as_bad (_("Expected comma after common length"));
3717 ignore_rest_of_line ();
3720 input_line_pointer++;
3722 if (*input_line_pointer != '"')
3724 temp = get_absolute_expression ();
3727 if (temp > max_alignment)
3729 temp = max_alignment;
3730 as_warn (_("alignment too large; assuming %d"), temp);
3736 as_bad (_("negative alignment"));
3737 ignore_rest_of_line ();
3742 if (symbol_get_obj (symbolP)->local)
3750 old_subsec = now_subseg;
3755 align = log2 (temp);
3759 as_bad (_("alignment not a power of 2"));
3760 ignore_rest_of_line ();
3764 record_alignment (bss_section, align);
3765 subseg_set (bss_section, 0);
3767 frag_align (align, 0, 0);
3768 if (S_GET_SEGMENT (symbolP) == bss_section)
3769 symbol_get_frag (symbolP)->fr_symbol = 0;
3770 symbol_set_frag (symbolP, frag_now);
3771 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3772 (offsetT) size, (char *) 0);
3774 S_SET_SEGMENT (symbolP, bss_section);
3775 S_CLEAR_EXTERNAL (symbolP);
3776 S_SET_SIZE (symbolP, size);
3777 subseg_set (old_sec, old_subsec);
3780 #endif /* OBJ_ELF */
3783 S_SET_VALUE (symbolP, (valueT) size);
3785 S_SET_ALIGN (symbolP, temp);
3786 S_SET_SIZE (symbolP, size);
3788 S_SET_EXTERNAL (symbolP);
3789 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3794 input_line_pointer++;
3795 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3796 if (*input_line_pointer == '.')
3797 input_line_pointer++;
3798 /* @@ Some say data, some say bss. */
3799 if (strncmp (input_line_pointer, "bss\"", 4)
3800 && strncmp (input_line_pointer, "data\"", 5))
3802 while (*--input_line_pointer != '"')
3804 input_line_pointer--;
3805 goto bad_common_segment;
3807 while (*input_line_pointer++ != '"')
3809 goto allocate_common;
3812 #ifdef BFD_ASSEMBLER
3813 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3816 demand_empty_rest_of_line ();
3821 p = input_line_pointer;
3822 while (*p && *p != '\n')
3826 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3828 input_line_pointer = p;
3829 ignore_rest_of_line ();
3834 /* Handle the .empty pseudo-op. This supresses the warnings about
3835 invalid delay slot usage. */
3839 int ignore ATTRIBUTE_UNUSED;
3841 /* The easy way to implement is to just forget about the last
3848 int ignore ATTRIBUTE_UNUSED;
3851 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3853 input_line_pointer += 6;
3857 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3859 input_line_pointer += 6;
3863 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3865 input_line_pointer += 7;
3869 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3871 input_line_pointer += 5;
3872 /* We only support 2 segments -- text and data -- for now, so
3873 things in the "bss segment" will have to go into data for now.
3874 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3875 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3878 as_bad (_("Unknown segment type"));
3879 demand_empty_rest_of_line ();
3885 subseg_set (data_section, 1);
3886 demand_empty_rest_of_line ();
3891 int ignore ATTRIBUTE_UNUSED;
3893 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3895 ++input_line_pointer;
3897 ++input_line_pointer;
3900 /* This static variable is set by s_uacons to tell sparc_cons_align
3901 that the expession does not need to be aligned. */
3903 static int sparc_no_align_cons = 0;
3905 /* This handles the unaligned space allocation pseudo-ops, such as
3906 .uaword. .uaword is just like .word, but the value does not need
3913 /* Tell sparc_cons_align not to align this value. */
3914 sparc_no_align_cons = 1;
3918 /* This handles the native word allocation pseudo-op .nword.
3919 For sparc_arch_size 32 it is equivalent to .word, for
3920 sparc_arch_size 64 it is equivalent to .xword. */
3924 int bytes ATTRIBUTE_UNUSED;
3926 cons (sparc_arch_size == 32 ? 4 : 8);
3930 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3934 .register %g[2367],{#scratch|symbolname|#ignore}
3939 int ignore ATTRIBUTE_UNUSED;
3944 const char *regname;
3946 if (input_line_pointer[0] != '%'
3947 || input_line_pointer[1] != 'g'
3948 || ((input_line_pointer[2] & ~1) != '2'
3949 && (input_line_pointer[2] & ~1) != '6')
3950 || input_line_pointer[3] != ',')
3951 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3952 reg = input_line_pointer[2] - '0';
3953 input_line_pointer += 4;
3955 if (*input_line_pointer == '#')
3957 ++input_line_pointer;
3958 regname = input_line_pointer;
3959 c = get_symbol_end ();
3960 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3961 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3962 if (regname[0] == 'i')
3969 regname = input_line_pointer;
3970 c = get_symbol_end ();
3972 if (sparc_arch_size == 64)
3976 if ((regname && globals[reg] != (symbolS *) 1
3977 && strcmp (S_GET_NAME (globals[reg]), regname))
3978 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3979 as_bad (_("redefinition of global register"));
3983 if (regname == NULL)
3984 globals[reg] = (symbolS *) 1;
3989 if (symbol_find (regname))
3990 as_bad (_("Register symbol %s already defined."),
3993 globals[reg] = symbol_make (regname);
3994 flags = symbol_get_bfdsym (globals[reg])->flags;
3996 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3997 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3998 flags |= BSF_GLOBAL;
3999 symbol_get_bfdsym (globals[reg])->flags = flags;
4000 S_SET_VALUE (globals[reg], (valueT) reg);
4001 S_SET_ALIGN (globals[reg], reg);
4002 S_SET_SIZE (globals[reg], 0);
4003 /* Although we actually want undefined_section here,
4004 we have to use absolute_section, because otherwise
4005 generic as code will make it a COM section.
4006 We fix this up in sparc_adjust_symtab. */
4007 S_SET_SEGMENT (globals[reg], absolute_section);
4008 S_SET_OTHER (globals[reg], 0);
4009 elf_symbol (symbol_get_bfdsym (globals[reg]))
4010 ->internal_elf_sym.st_info =
4011 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4012 elf_symbol (symbol_get_bfdsym (globals[reg]))
4013 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4018 *input_line_pointer = c;
4020 demand_empty_rest_of_line ();
4023 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4024 symbols which need it. */
4027 sparc_adjust_symtab ()
4031 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4033 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4034 ->internal_elf_sym.st_info) != STT_REGISTER)
4037 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4038 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4041 S_SET_SEGMENT (sym, undefined_section);
4046 /* If the --enforce-aligned-data option is used, we require .word,
4047 et. al., to be aligned correctly. We do it by setting up an
4048 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4049 no unexpected alignment was introduced.
4051 The SunOS and Solaris native assemblers enforce aligned data by
4052 default. We don't want to do that, because gcc can deliberately
4053 generate misaligned data if the packed attribute is used. Instead,
4054 we permit misaligned data by default, and permit the user to set an
4055 option to check for it. */
4058 sparc_cons_align (nbytes)
4064 /* Only do this if we are enforcing aligned data. */
4065 if (! enforce_aligned_data)
4068 if (sparc_no_align_cons)
4070 /* This is an unaligned pseudo-op. */
4071 sparc_no_align_cons = 0;
4075 nalign = log2 (nbytes);
4079 assert (nalign > 0);
4081 if (now_seg == absolute_section)
4083 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4084 as_bad (_("misaligned data"));
4088 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4089 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4091 record_alignment (now_seg, nalign);
4094 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4097 sparc_handle_align (fragp)
4103 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4105 switch (fragp->fr_type)
4109 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4113 p = fragp->fr_literal + fragp->fr_fix;
4124 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4126 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4127 if (INSN_BIG_ENDIAN)
4128 number_to_chars_bigendian (p, wval, 4);
4130 number_to_chars_littleendian (p, wval, 4);
4136 if (INSN_BIG_ENDIAN)
4137 number_to_chars_bigendian (p, 0x01000000, 4);
4139 number_to_chars_littleendian (p, 0x01000000, 4);
4141 fragp->fr_fix += fix;
4151 /* Some special processing for a Sparc ELF file. */
4154 sparc_elf_final_processing ()
4156 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4157 sort of BFD interface for this. */
4158 if (sparc_arch_size == 64)
4160 switch (sparc_memory_model)
4163 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4166 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4172 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4173 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4174 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4175 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4176 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4177 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4181 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4182 reloc for a cons. We could use the definition there, except that
4183 we want to handle little endian relocs specially. */
4186 cons_fix_new_sparc (frag, where, nbytes, exp)
4189 unsigned int nbytes;
4192 bfd_reloc_code_real_type r;
4194 r = (nbytes == 1 ? BFD_RELOC_8 :
4195 (nbytes == 2 ? BFD_RELOC_16 :
4196 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4198 if (target_little_endian_data && nbytes == 4
4199 && now_seg->flags & SEC_ALLOC)
4200 r = BFD_RELOC_SPARC_REV32;
4201 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4206 elf32_sparc_force_relocation (fixp)
4209 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4210 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)