1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch *lookup_arch PARAMS ((char *));
33 static void init_default_arch PARAMS ((void));
34 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
35 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
36 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
37 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38 static int sparc_ffs PARAMS ((unsigned int));
39 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
40 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
41 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
42 static bfd_vma BSR PARAMS ((bfd_vma, int));
43 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
44 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
45 static int parse_const_expr_arg PARAMS ((char **, int *));
46 static int get_expression PARAMS ((char *str));
48 /* Default architecture. */
49 /* ??? The default value should be V8, but sparclite support was added
50 by making it the default. GCC now passes -Asparclite, so maybe sometime in
51 the future we can set this to V8. */
53 #define DEFAULT_ARCH "sparclite"
55 static char *default_arch = DEFAULT_ARCH;
57 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 static int default_init_p;
61 /* Current architecture. We don't bump up unless necessary. */
62 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
64 /* The maximum architecture level we can bump up to.
65 In a 32 bit environment, don't allow bumping up to v9 by default.
66 The native assembler works this way. The user is required to pass
67 an explicit argument before we'll create v9 object files. However, if
68 we don't see any v9 insns, a v8plus object file is not created. */
69 static enum sparc_opcode_arch_val max_architecture;
71 /* Either 32 or 64, selects file format. */
72 static int sparc_arch_size;
73 /* Initial (default) value, recorded separately in case a user option
74 changes the value before md_show_usage is called. */
75 static int default_arch_size;
78 /* The currently selected v9 memory model. Currently only used for
80 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
83 static int architecture_requested;
84 static int warn_on_bump;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture;
90 /* Non-zero if as should generate error if an undeclared g[23] register
91 has been used in -64. */
92 static int no_undeclared_regs;
94 /* Non-zero if we are generating PIC code. */
97 /* Non-zero if we should give an error when misaligned data is seen. */
98 static int enforce_aligned_data;
100 extern int target_big_endian;
102 static int target_little_endian_data;
104 /* Symbols for global registers on v9. */
105 static symbolS *globals[8];
107 /* V9 and 86x have big and little endian data, but instructions are always big
108 endian. The sparclet has bi-endian support but both data and insns have
109 the same endianness. Global `target_big_endian' is used for data.
110 The following macro is used for instructions. */
111 #ifndef INSN_BIG_ENDIAN
112 #define INSN_BIG_ENDIAN (target_big_endian \
113 || default_arch_type == sparc86x \
114 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
117 /* handle of the OPCODE hash table */
118 static struct hash_control *op_hash;
120 static int log2 PARAMS ((int));
121 static void s_data1 PARAMS ((void));
122 static void s_seg PARAMS ((int));
123 static void s_proc PARAMS ((int));
124 static void s_reserve PARAMS ((int));
125 static void s_common PARAMS ((int));
126 static void s_empty PARAMS ((int));
127 static void s_uacons PARAMS ((int));
128 static void s_ncons PARAMS ((int));
129 static void s_register PARAMS ((int));
131 const pseudo_typeS md_pseudo_table[] =
133 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
134 {"common", s_common, 0},
135 {"empty", s_empty, 0},
136 {"global", s_globl, 0},
138 {"nword", s_ncons, 0},
139 {"optim", s_ignore, 0},
141 {"reserve", s_reserve, 0},
143 {"skip", s_space, 0},
146 {"uahalf", s_uacons, 2},
147 {"uaword", s_uacons, 4},
148 {"uaxword", s_uacons, 8},
150 /* these are specific to sparc/svr4 */
151 {"2byte", s_uacons, 2},
152 {"4byte", s_uacons, 4},
153 {"8byte", s_uacons, 8},
154 {"register", s_register, 0},
159 const int md_reloc_size = 12; /* Size of relocation record */
161 /* This array holds the chars that always start a comment. If the
162 pre-processor is disabled, these aren't very useful */
163 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
165 /* This array holds the chars that only start a comment at the beginning of
166 a line. If the line seems to have the form '# 123 filename'
167 .line and .file directives will appear in the pre-processed output */
168 /* Note that input_file.c hand checks for '#' at the beginning of the
169 first line of the input file. This is because the compiler outputs
170 #NO_APP at the beginning of its output. */
171 /* Also note that comments started like this one will always
172 work if '/' isn't otherwise defined. */
173 const char line_comment_chars[] = "#";
175 const char line_separator_chars[] = "";
177 /* Chars that can be used to separate mant from exp in floating point nums */
178 const char EXP_CHARS[] = "eE";
180 /* Chars that mean this number is a floating point constant */
183 const char FLT_CHARS[] = "rRsSfFdDxXpP";
185 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
186 changed in read.c. Ideally it shouldn't have to know about it at all,
187 but nothing is ideal around here. */
189 #define isoctal(c) ((unsigned)((c) - '0') < '8')
194 unsigned long opcode;
195 struct nlist *nlistp;
199 bfd_reloc_code_real_type reloc;
202 struct sparc_it the_insn, set_insn;
204 static void output_insn
205 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
207 /* Table of arguments to -A.
208 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
209 for this use. That table is for opcodes only. This table is for opcodes
212 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
213 v8plusa, v9, v9a, v9_64};
215 static struct sparc_arch {
218 enum sparc_arch_types arch_type;
219 /* Default word size, as specified during configuration.
220 A value of zero means can't be used to specify default architecture. */
221 int default_arch_size;
222 /* Allowable arg to -A? */
224 } sparc_arch_table[] = {
225 { "v6", "v6", v6, 0, 1 },
226 { "v7", "v7", v7, 0, 1 },
227 { "v8", "v8", v8, 32, 1 },
228 { "sparclet", "sparclet", sparclet, 32, 1 },
229 { "sparclite", "sparclite", sparclite, 32, 1 },
230 { "sparc86x", "sparclite", sparc86x, 32, 1 },
231 { "v8plus", "v9", v9, 0, 1 },
232 { "v8plusa", "v9a", v9, 0, 1 },
233 { "v9", "v9", v9, 0, 1 },
234 { "v9a", "v9a", v9, 0, 1 },
235 /* This exists to allow configure.in/Makefile.in to pass one
236 value to specify both the default machine and default word size. */
237 { "v9-64", "v9", v9, 64, 0 },
238 { NULL, NULL, v8, 0, 0 }
241 /* Variant of default_arch */
242 static enum sparc_arch_types default_arch_type;
244 static struct sparc_arch *
248 struct sparc_arch *sa;
250 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
251 if (strcmp (sa->name, name) == 0)
253 if (sa->name == NULL)
258 /* Initialize the default opcode arch and word size from the default
259 architecture name. */
264 struct sparc_arch *sa = lookup_arch (default_arch);
267 || sa->default_arch_size == 0)
268 as_fatal (_("Invalid default architecture, broken assembler."));
270 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
271 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
272 as_fatal (_("Bad opcode table, broken assembler."));
273 default_arch_size = sparc_arch_size = sa->default_arch_size;
275 default_arch_type = sa->arch_type;
278 /* Called by TARGET_FORMAT. */
281 sparc_target_format ()
283 /* We don't get a chance to initialize anything before we're called,
284 so handle that now. */
285 if (! default_init_p)
286 init_default_arch ();
290 return "a.out-sparc-netbsd";
293 if (target_big_endian)
294 return "a.out-sunos-big";
295 else if (default_arch_type == sparc86x && target_little_endian_data)
296 return "a.out-sunos-big";
297 else return "a.out-sparc-little";
299 return "a.out-sunos-big";
310 return "coff-sparc-lynx";
317 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
325 * Invocation line includes a switch not recognized by the base assembler.
326 * See if it's a processor-specific option. These are:
329 * Warn on architecture bumps. See also -A.
331 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
332 * Standard 32 bit architectures.
333 * -Av8plus, -Av8plusa
334 * Sparc64 in a 32 bit world.
336 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
337 * This used to only mean 64 bits, but properly specifying it
338 * complicated gcc's ASM_SPECs, so now opcode selection is
339 * specified orthogonally to word size (except when specifying
340 * the default, but that is an internal implementation detail).
341 * -xarch=v8plus, -xarch=v8plusa
342 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
344 * Select the architecture and possibly the file format.
345 * Instructions or features not supported by the selected
346 * architecture cause fatal errors.
348 * The default is to start at v6, and bump the architecture up
349 * whenever an instruction is seen at a higher level. In 32 bit
350 * environments, v9 is not bumped up to, the user must pass
353 * If -bump is specified, a warning is printing when bumping to
356 * If an architecture is specified, all instructions must match
357 * that architecture. Any higher level instructions are flagged
358 * as errors. Note that in the 32 bit environment specifying
359 * -Av8plus does not automatically create a v8plus object file, a
360 * v9 insn must be seen.
362 * If both an architecture and -bump are specified, the
363 * architecture starts at the specified level, but bumps are
364 * warnings. Note that we can't set `current_architecture' to
365 * the requested level in this case: in the 32 bit environment,
366 * we still must avoid creating v8plus object files unless v9
370 * Bumping between incompatible architectures is always an
371 * error. For example, from sparclite to v9.
375 CONST char *md_shortopts = "A:K:VQ:sq";
378 CONST char *md_shortopts = "A:k";
380 CONST char *md_shortopts = "A:";
383 struct option md_longopts[] = {
384 #define OPTION_BUMP (OPTION_MD_BASE)
385 {"bump", no_argument, NULL, OPTION_BUMP},
386 #define OPTION_SPARC (OPTION_MD_BASE + 1)
387 {"sparc", no_argument, NULL, OPTION_SPARC},
388 #define OPTION_XARCH (OPTION_MD_BASE + 2)
389 {"xarch", required_argument, NULL, OPTION_XARCH},
391 #define OPTION_32 (OPTION_MD_BASE + 3)
392 {"32", no_argument, NULL, OPTION_32},
393 #define OPTION_64 (OPTION_MD_BASE + 4)
394 {"64", no_argument, NULL, OPTION_64},
395 #define OPTION_TSO (OPTION_MD_BASE + 5)
396 {"TSO", no_argument, NULL, OPTION_TSO},
397 #define OPTION_PSO (OPTION_MD_BASE + 6)
398 {"PSO", no_argument, NULL, OPTION_PSO},
399 #define OPTION_RMO (OPTION_MD_BASE + 7)
400 {"RMO", no_argument, NULL, OPTION_RMO},
402 #ifdef SPARC_BIENDIAN
403 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
404 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
405 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
406 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
408 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
409 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
410 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
411 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
413 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
414 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
415 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
416 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
418 {NULL, no_argument, NULL, 0}
420 size_t md_longopts_size = sizeof(md_longopts);
423 md_parse_option (c, arg)
427 /* We don't get a chance to initialize anything before we're called,
428 so handle that now. */
429 if (! default_init_p)
430 init_default_arch ();
436 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
440 /* This is for compatibility with Sun's assembler. */
441 if (strcmp (arg, "v8plus") != 0
442 && strcmp (arg, "v8plusa") != 0)
444 as_bad (_("invalid architecture -xarch=%s"), arg);
452 struct sparc_arch *sa;
453 enum sparc_opcode_arch_val opcode_arch;
455 sa = lookup_arch (arg);
457 || ! sa->user_option_p)
459 as_bad (_("invalid architecture -A%s"), arg);
463 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
464 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
465 as_fatal (_("Bad opcode table, broken assembler."));
467 max_architecture = opcode_arch;
468 architecture_requested = 1;
473 /* Ignore -sparc, used by SunOS make default .s.o rule. */
476 case OPTION_ENFORCE_ALIGNED_DATA:
477 enforce_aligned_data = 1;
480 #ifdef SPARC_BIENDIAN
481 case OPTION_LITTLE_ENDIAN:
482 target_big_endian = 0;
483 if (default_arch_type != sparclet)
484 as_fatal ("This target does not support -EL");
486 case OPTION_LITTLE_ENDIAN_DATA:
487 target_little_endian_data = 1;
488 target_big_endian = 0;
489 if (default_arch_type != sparc86x
490 && default_arch_type != v9)
491 as_fatal ("This target does not support --little-endian-data");
493 case OPTION_BIG_ENDIAN:
494 target_big_endian = 1;
508 const char **list, **l;
510 sparc_arch_size = c == OPTION_32 ? 32 : 64;
511 list = bfd_target_list ();
512 for (l = list; *l != NULL; l++)
514 if (sparc_arch_size == 32)
516 if (strcmp (*l, "elf32-sparc") == 0)
521 if (strcmp (*l, "elf64-sparc") == 0)
526 as_fatal (_("No compiled in support for %d bit object file format"),
533 sparc_memory_model = MM_TSO;
537 sparc_memory_model = MM_PSO;
541 sparc_memory_model = MM_RMO;
549 /* Qy - do emit .comment
550 Qn - do not emit .comment */
554 /* use .stab instead of .stab.excl */
558 /* quick -- native assembler does fewer checks */
562 if (strcmp (arg, "PIC") != 0)
563 as_warn (_("Unrecognized option following -K"));
568 case OPTION_NO_UNDECLARED_REGS:
569 no_undeclared_regs = 1;
572 case OPTION_UNDECLARED_REGS:
573 no_undeclared_regs = 0;
585 md_show_usage (stream)
588 const struct sparc_arch *arch;
590 /* We don't get a chance to initialize anything before we're called,
591 so handle that now. */
592 if (! default_init_p)
593 init_default_arch ();
595 fprintf(stream, _("SPARC options:\n"));
596 for (arch = &sparc_arch_table[0]; arch->name; arch++)
598 if (arch != &sparc_arch_table[0])
599 fprintf (stream, " | ");
600 if (arch->user_option_p)
601 fprintf (stream, "-A%s", arch->name);
603 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
604 fprintf (stream, _("\
605 specify variant of SPARC architecture\n\
606 -bump warn when assembler switches architectures\n\
608 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
610 fprintf (stream, _("\
611 -k generate PIC\n"));
614 fprintf (stream, _("\
615 -32 create 32 bit object file\n\
616 -64 create 64 bit object file\n"));
617 fprintf (stream, _("\
618 [default is %d]\n"), default_arch_size);
619 fprintf (stream, _("\
620 -TSO use Total Store Ordering\n\
621 -PSO use Partial Store Ordering\n\
622 -RMO use Relaxed Memory Ordering\n"));
623 fprintf (stream, _("\
624 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
625 fprintf (stream, _("\
626 -KPIC generate PIC\n\
627 -V print assembler version number\n\
628 -undeclared-regs ignore application global register usage without\n\
629 appropriate .register directive (default)\n\
630 -no-undeclared-regs force error on application global register usage\n\
631 without appropriate .register directive\n\
636 #ifdef SPARC_BIENDIAN
637 fprintf (stream, _("\
638 -EL generate code for a little endian machine\n\
639 -EB generate code for a big endian machine\n\
640 --little-endian-data generate code for a machine having big endian\n\
641 instructions and little endian data."));
645 /* native operand size opcode translation */
651 } native_op_table[] =
653 {"ldn", "ld", "ldx"},
654 {"ldna", "lda", "ldxa"},
655 {"stn", "st", "stx"},
656 {"stna", "sta", "stxa"},
657 {"slln", "sll", "sllx"},
658 {"srln", "srl", "srlx"},
659 {"sran", "sra", "srax"},
660 {"casn", "cas", "casx"},
661 {"casna", "casa", "casxa"},
662 {"clrn", "clr", "clrx"},
666 /* sparc64 priviledged registers */
668 struct priv_reg_entry
674 struct priv_reg_entry priv_reg_table[] =
693 {"", -1}, /* end marker */
696 /* v9a specific asrs */
698 struct priv_reg_entry v9a_asr_table[] =
707 {"clear_softint", 21},
708 {"", -1}, /* end marker */
712 cmp_reg_entry (parg, qarg)
716 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
717 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
719 return strcmp (q->name, p->name);
722 /* This function is called once, at assembler startup time. It should
723 set up all the tables, etc. that the MD part of the assembler will need. */
728 register const char *retval = NULL;
730 register unsigned int i = 0;
732 /* We don't get a chance to initialize anything before md_parse_option
733 is called, and it may not be called, so handle default initialization
734 now if not already done. */
735 if (! default_init_p)
736 init_default_arch ();
738 op_hash = hash_new ();
740 while (i < (unsigned int) sparc_num_opcodes)
742 const char *name = sparc_opcodes[i].name;
743 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
746 as_bad (_("Internal error: can't hash `%s': %s\n"),
747 sparc_opcodes[i].name, retval);
752 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
754 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
755 sparc_opcodes[i].name, sparc_opcodes[i].args);
760 while (i < (unsigned int) sparc_num_opcodes
761 && !strcmp (sparc_opcodes[i].name, name));
764 for (i = 0; native_op_table[i].name; i++)
766 const struct sparc_opcode *insn;
767 char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
768 native_op_table[i].name64;
769 insn = (struct sparc_opcode *)hash_find (op_hash, name);
772 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
773 name, native_op_table[i].name);
778 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
781 as_bad (_("Internal error: can't hash `%s': %s\n"),
782 sparc_opcodes[i].name, retval);
789 as_fatal (_("Broken assembler. No assembly attempted."));
791 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
792 sizeof (priv_reg_table[0]), cmp_reg_entry);
794 /* If -bump, record the architecture level at which we start issuing
795 warnings. The behaviour is different depending upon whether an
796 architecture was explicitly specified. If it wasn't, we issue warnings
797 for all upwards bumps. If it was, we don't start issuing warnings until
798 we need to bump beyond the requested architecture or when we bump between
799 conflicting architectures. */
802 && architecture_requested)
804 /* `max_architecture' records the requested architecture.
805 Issue warnings if we go above it. */
806 warn_after_architecture = max_architecture;
808 /* Find the highest architecture level that doesn't conflict with
809 the requested one. */
810 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
811 max_architecture > warn_after_architecture;
813 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
814 warn_after_architecture))
819 /* Called after all assembly has been done. */
824 if (sparc_arch_size == 64)
826 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
827 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
829 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
833 if (current_architecture == SPARC_OPCODE_ARCH_V9)
834 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
835 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
836 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
837 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
838 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
839 else if (default_arch_type == sparc86x && target_little_endian_data)
840 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
843 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
844 be but for now it is (since that's the way it's always been
846 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
851 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
854 in_signed_range (val, max)
855 bfd_signed_vma val, max;
859 /* Sign-extend the value from the architecture word size, so that
860 0xffffffff is always considered -1 on sparc32. */
861 if (sparc_arch_size == 32)
863 bfd_signed_vma sign = (bfd_signed_vma)1 << 31;
864 val = ((val & 0xffffffff) ^ sign) - sign;
873 /* Return non-zero if VAL is in the range 0 to MAX. */
876 in_unsigned_range (val, max)
884 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
885 (e.g. -15 to +31). */
888 in_bitfield_range (val, max)
889 bfd_signed_vma val, max;
895 if (val < ~(max >> 1))
909 for (i = 0; (mask & 1) == 0; ++i)
914 /* Implement big shift right. */
920 if (sizeof (bfd_vma) <= 4 && amount >= 32)
921 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
922 return val >> amount;
925 /* For communication between sparc_ip and get_expression. */
926 static char *expr_end;
928 /* Values for `special_case'.
929 Instructions that require wierd handling because they're longer than
931 #define SPECIAL_CASE_NONE 0
932 #define SPECIAL_CASE_SET 1
933 #define SPECIAL_CASE_SETSW 2
934 #define SPECIAL_CASE_SETX 3
935 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
936 #define SPECIAL_CASE_FDIV 4
938 /* Bit masks of various insns. */
939 #define NOP_INSN 0x01000000
940 #define OR_INSN 0x80100000
941 #define XOR_INSN 0x80180000
942 #define FMOVS_INSN 0x81A00020
943 #define SETHI_INSN 0x01000000
944 #define SLLX_INSN 0x81281000
945 #define SRA_INSN 0x81380000
947 /* The last instruction to be assembled. */
948 static const struct sparc_opcode *last_insn;
949 /* The assembled opcode of `last_insn'. */
950 static unsigned long last_opcode;
952 /* Handle the set and setuw synthetic instructions. */
954 synthetize_setuw (insn)
955 const struct sparc_opcode *insn;
958 int rd = (the_insn.opcode & RD (~0)) >> 25;
960 if (the_insn.exp.X_op == O_constant)
962 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
964 if (sizeof(offsetT) > 4
965 && (the_insn.exp.X_add_number < 0
966 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
967 as_warn (_("set: number not in 0..4294967295 range"));
971 if (sizeof(offsetT) > 4
972 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
973 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
974 as_warn (_("set: number not in -2147483648..4294967295 range"));
975 the_insn.exp.X_add_number = (int)the_insn.exp.X_add_number;
979 /* See if operand is absolute and small; skip sethi if so. */
980 if (the_insn.exp.X_op != O_constant
981 || the_insn.exp.X_add_number >= (1 << 12)
982 || the_insn.exp.X_add_number < -(1 << 12))
984 the_insn.opcode = (SETHI_INSN | RD (rd)
985 | ((the_insn.exp.X_add_number >> 10)
986 & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0)));
987 the_insn.reloc = (the_insn.exp.X_op != O_constant
990 output_insn (insn, &the_insn);
994 /* See if operand has no low-order bits; skip OR if so. */
995 if (the_insn.exp.X_op != O_constant
996 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
999 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1001 | (the_insn.exp.X_add_number
1002 & (the_insn.exp.X_op != O_constant ? 0 :
1003 need_hi22_p ? 0x3ff : 0x1fff)));
1004 the_insn.reloc = (the_insn.exp.X_op != O_constant
1007 output_insn (insn, &the_insn);
1011 /* Handle the setsw synthetic instruction. */
1013 synthetize_setsw (insn)
1014 const struct sparc_opcode *insn;
1018 rd = (the_insn.opcode & RD (~0)) >> 25;
1020 if (the_insn.exp.X_op != O_constant)
1022 synthetize_setuw (insn);
1024 /* Need to sign extend it. */
1025 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1026 the_insn.reloc = BFD_RELOC_NONE;
1027 output_insn (insn, &the_insn);
1031 if (sizeof(offsetT) > 4
1032 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1033 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1034 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1036 low32 = the_insn.exp.X_add_number;
1040 synthetize_setuw (insn);
1046 the_insn.reloc = BFD_RELOC_NONE;
1047 /* See if operand is absolute and small; skip sethi if so. */
1048 if (low32 < -(1 << 12))
1050 the_insn.opcode = (SETHI_INSN | RD (rd)
1051 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1052 output_insn (insn, &the_insn);
1053 low32 = 0x1c00 | (low32 & 0x3ff);
1054 opc = RS1 (rd) | XOR_INSN;
1057 the_insn.opcode = (opc | RD (rd) | IMMED
1058 | (low32 & 0x1fff));
1059 output_insn (insn, &the_insn);
1062 /* Handle the setsw synthetic instruction. */
1064 synthetize_setx (insn)
1065 const struct sparc_opcode *insn;
1067 int upper32, lower32;
1068 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1069 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1071 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1072 int need_xor10_p = 0;
1074 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1075 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1076 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1079 upper_dstreg = tmpreg;
1080 /* The tmp reg should not be the dst reg. */
1081 if (tmpreg == dstreg)
1082 as_warn (_("setx: temporary register same as destination register"));
1084 /* ??? Obviously there are other optimizations we can do
1085 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1086 doing some of these. Later. If you do change things, try to
1087 change all of this to be table driven as well. */
1088 /* What to output depends on the number if it's constant.
1089 Compute that first, then output what we've decided upon. */
1090 if (the_insn.exp.X_op != O_constant)
1092 if (sparc_arch_size == 32)
1094 /* When arch size is 32, we want setx to be equivalent
1095 to setuw for anything but constants. */
1096 the_insn.exp.X_add_number &= 0xffffffff;
1097 synthetize_setuw (insn);
1100 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1101 lower32 = 0; upper32 = 0;
1105 /* Reset X_add_number, we've extracted it as upper32/lower32.
1106 Otherwise fixup_segment will complain about not being able to
1107 write an 8 byte number in a 4 byte field. */
1108 the_insn.exp.X_add_number = 0;
1110 /* Only need hh22 if `or' insn can't handle constant. */
1111 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1114 /* Does bottom part (after sethi) have bits? */
1115 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1116 /* No hh22, but does upper32 still have bits we can't set
1118 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1121 /* If the lower half is all zero, we build the upper half directly
1122 into the dst reg. */
1124 /* Need lower half if number is zero or 0xffffffff00000000. */
1125 || (! need_hh22_p && ! need_hm10_p))
1127 /* No need for sethi if `or' insn can handle constant. */
1128 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1129 /* Note that we can't use a negative constant in the `or'
1130 insn unless the upper 32 bits are all ones. */
1131 || (lower32 < 0 && upper32 != -1)
1132 || (lower32 >= 0 && upper32 == -1))
1135 if (need_hi22_p && upper32 == -1)
1138 /* Does bottom part (after sethi) have bits? */
1139 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1141 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1142 /* Need `or' if we didn't set anything else. */
1143 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1147 /* Output directly to dst reg if lower 32 bits are all zero. */
1148 upper_dstreg = dstreg;
1151 if (!upper_dstreg && dstreg)
1152 as_warn (_("setx: illegal temporary register g0"));
1156 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1157 | ((upper32 >> 10) & 0x3fffff));
1158 the_insn.reloc = (the_insn.exp.X_op != O_constant
1159 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1160 output_insn (insn, &the_insn);
1165 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1166 | (((need_xor10_p ? ~lower32 : lower32)
1167 >> 10) & 0x3fffff));
1168 the_insn.reloc = (the_insn.exp.X_op != O_constant
1169 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1170 output_insn (insn, &the_insn);
1175 the_insn.opcode = (OR_INSN
1176 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1179 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1180 the_insn.reloc = (the_insn.exp.X_op != O_constant
1181 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1182 output_insn (insn, &the_insn);
1187 /* FIXME: One nice optimization to do here is to OR the low part
1188 with the highpart if hi22 isn't needed and the low part is
1190 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1193 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1194 the_insn.reloc = (the_insn.exp.X_op != O_constant
1195 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1196 output_insn (insn, &the_insn);
1199 /* If we needed to build the upper part, shift it into place. */
1200 if (need_hh22_p || need_hm10_p)
1202 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1204 the_insn.reloc = BFD_RELOC_NONE;
1205 output_insn (insn, &the_insn);
1208 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1211 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1212 | 0x1c00 | (lower32 & 0x3ff));
1213 the_insn.reloc = BFD_RELOC_NONE;
1214 output_insn (insn, &the_insn);
1217 /* If we needed to build both upper and lower parts, OR them together. */
1218 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1220 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1222 the_insn.reloc = BFD_RELOC_NONE;
1223 output_insn (insn, &the_insn);
1227 /* Main entry point to assemble one instruction. */
1233 const struct sparc_opcode *insn;
1237 special_case = sparc_ip (str, &insn);
1239 /* We warn about attempts to put a floating point branch in a delay slot,
1240 unless the delay slot has been annulled. */
1242 && last_insn != NULL
1243 && (insn->flags & F_FBR) != 0
1244 && (last_insn->flags & F_DELAYED) != 0
1245 /* ??? This test isn't completely accurate. We assume anything with
1246 F_{UNBR,CONDBR,FBR} set is annullable. */
1247 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1248 || (last_opcode & ANNUL) == 0))
1249 as_warn (_("FP branch in delay slot"));
1251 /* SPARC before v9 requires a nop instruction between a floating
1252 point instruction and a floating point branch. We insert one
1253 automatically, with a warning. */
1254 if (max_architecture < SPARC_OPCODE_ARCH_V9
1256 && last_insn != NULL
1257 && (insn->flags & F_FBR) != 0
1258 && (last_insn->flags & F_FLOAT) != 0)
1260 struct sparc_it nop_insn;
1262 nop_insn.opcode = NOP_INSN;
1263 nop_insn.reloc = BFD_RELOC_NONE;
1264 output_insn (insn, &nop_insn);
1265 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1268 switch (special_case)
1270 case SPECIAL_CASE_NONE:
1272 output_insn (insn, &the_insn);
1275 case SPECIAL_CASE_SETSW:
1276 synthetize_setsw (insn);
1279 case SPECIAL_CASE_SET:
1280 synthetize_setuw (insn);
1283 case SPECIAL_CASE_SETX:
1284 synthetize_setx (insn);
1287 case SPECIAL_CASE_FDIV:
1289 int rd = (the_insn.opcode >> 25) & 0x1f;
1291 output_insn (insn, &the_insn);
1293 /* According to information leaked from Sun, the "fdiv" instructions
1294 on early SPARC machines would produce incorrect results sometimes.
1295 The workaround is to add an fmovs of the destination register to
1296 itself just after the instruction. This was true on machines
1297 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1298 assert (the_insn.reloc == BFD_RELOC_NONE);
1299 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1300 output_insn (insn, &the_insn);
1305 as_fatal (_("failed special case insn sanity check"));
1309 /* Subroutine of md_assemble to do the actual parsing. */
1312 sparc_ip (str, pinsn)
1314 const struct sparc_opcode **pinsn;
1316 char *error_message = "";
1320 const struct sparc_opcode *insn;
1322 unsigned long opcode;
1323 unsigned int mask = 0;
1327 int special_case = SPECIAL_CASE_NONE;
1330 if (islower ((unsigned char) *s))
1334 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1352 as_fatal (_("Unknown opcode: `%s'"), str);
1354 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1358 as_bad (_("Unknown opcode: `%s'"), str);
1359 return special_case;
1369 opcode = insn->match;
1370 memset (&the_insn, '\0', sizeof (the_insn));
1371 the_insn.reloc = BFD_RELOC_NONE;
1375 * Build the opcode, checking as we go to make
1376 * sure that the operands match
1378 for (args = insn->args;; ++args)
1386 /* Parse a series of masks. */
1393 if (! parse_keyword_arg (sparc_encode_membar, &s,
1396 error_message = _(": invalid membar mask name");
1400 while (*s == ' ') { ++s; continue; }
1401 if (*s == '|' || *s == '+')
1403 while (*s == ' ') { ++s; continue; }
1408 if (! parse_const_expr_arg (&s, &kmask))
1410 error_message = _(": invalid membar mask expression");
1413 if (kmask < 0 || kmask > 127)
1415 error_message = _(": invalid membar mask number");
1420 opcode |= MEMBAR (kmask);
1428 /* Parse a prefetch function. */
1431 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1433 error_message = _(": invalid prefetch function name");
1439 if (! parse_const_expr_arg (&s, &fcn))
1441 error_message = _(": invalid prefetch function expression");
1444 if (fcn < 0 || fcn > 31)
1446 error_message = _(": invalid prefetch function number");
1456 /* Parse a sparc64 privileged register. */
1459 struct priv_reg_entry *p = priv_reg_table;
1460 unsigned int len = 9999999; /* init to make gcc happy */
1463 while (p->name[0] > s[0])
1465 while (p->name[0] == s[0])
1467 len = strlen (p->name);
1468 if (strncmp (p->name, s, len) == 0)
1472 if (p->name[0] != s[0])
1474 error_message = _(": unrecognizable privileged register");
1478 opcode |= (p->regnum << 14);
1480 opcode |= (p->regnum << 25);
1486 error_message = _(": unrecognizable privileged register");
1492 /* Parse a v9a ancillary state register. */
1495 struct priv_reg_entry *p = v9a_asr_table;
1496 unsigned int len = 9999999; /* init to make gcc happy */
1499 while (p->name[0] > s[0])
1501 while (p->name[0] == s[0])
1503 len = strlen (p->name);
1504 if (strncmp (p->name, s, len) == 0)
1508 if (p->name[0] != s[0])
1510 error_message = _(": unrecognizable v9a ancillary state register");
1513 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1515 error_message = _(": rd on write only ancillary state register");
1519 opcode |= (p->regnum << 14);
1521 opcode |= (p->regnum << 25);
1527 error_message = _(": unrecognizable v9a ancillary state register");
1533 if (strncmp (s, "%asr", 4) == 0)
1537 if (isdigit ((unsigned char) *s))
1541 while (isdigit ((unsigned char) *s))
1543 num = num * 10 + *s - '0';
1547 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1549 if (num < 16 || 31 < num)
1551 error_message = _(": asr number must be between 16 and 31");
1557 if (num < 0 || 31 < num)
1559 error_message = _(": asr number must be between 0 and 31");
1564 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1569 error_message = _(": expecting %asrN");
1576 the_insn.reloc = BFD_RELOC_SPARC_11;
1580 the_insn.reloc = BFD_RELOC_SPARC_10;
1584 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1585 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1586 the_insn.reloc = BFD_RELOC_SPARC_5;
1588 the_insn.reloc = BFD_RELOC_SPARC13;
1589 /* These fields are unsigned, but for upward compatibility,
1590 allow negative values as well. */
1594 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1595 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1596 the_insn.reloc = BFD_RELOC_SPARC_6;
1598 the_insn.reloc = BFD_RELOC_SPARC13;
1599 /* These fields are unsigned, but for upward compatibility,
1600 allow negative values as well. */
1604 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1609 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1614 if (*s == 'p' && s[1] == 'n')
1622 if (*s == 'p' && s[1] == 't')
1634 if (strncmp (s, "%icc", 4) == 0)
1646 if (strncmp (s, "%xcc", 4) == 0)
1658 if (strncmp (s, "%fcc0", 5) == 0)
1670 if (strncmp (s, "%fcc1", 5) == 0)
1682 if (strncmp (s, "%fcc2", 5) == 0)
1694 if (strncmp (s, "%fcc3", 5) == 0)
1702 if (strncmp (s, "%pc", 3) == 0)
1710 if (strncmp (s, "%tick", 5) == 0)
1717 case '\0': /* end of args */
1736 case '[': /* these must match exactly */
1744 case '#': /* must be at least one digit */
1745 if (isdigit ((unsigned char) *s++))
1747 while (isdigit ((unsigned char) *s))
1755 case 'C': /* coprocessor state register */
1756 if (strncmp (s, "%csr", 4) == 0)
1763 case 'b': /* next operand is a coprocessor register */
1766 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1769 if (isdigit ((unsigned char) *s))
1771 mask = 10 * (mask - '0') + (*s++ - '0');
1785 opcode |= mask << 14;
1793 opcode |= mask << 25;
1799 case 'r': /* next operand must be a register */
1809 case 'f': /* frame pointer */
1817 case 'g': /* global register */
1826 case 'i': /* in register */
1830 mask = c - '0' + 24;
1835 case 'l': /* local register */
1839 mask = (c - '0' + 16);
1844 case 'o': /* out register */
1848 mask = (c - '0' + 8);
1853 case 's': /* stack pointer */
1861 case 'r': /* any register */
1862 if (!isdigit ((unsigned char) (c = *s++)))
1877 if (isdigit ((unsigned char) *s))
1879 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1895 if ((mask & ~1) == 2 && sparc_arch_size == 64
1896 && no_undeclared_regs && ! globals [mask])
1897 as_bad (_("detected global register use not "
1898 "covered by .register pseudo-op"));
1900 /* Got the register, now figure out where
1901 it goes in the opcode. */
1905 opcode |= mask << 14;
1913 opcode |= mask << 25;
1917 opcode |= (mask << 25) | (mask << 14);
1921 opcode |= (mask << 25) | (mask << 0);
1927 case 'e': /* next operand is a floating point register */
1942 && ((format = *s) == 'f')
1943 && isdigit ((unsigned char) *++s))
1945 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1947 mask = 10 * mask + (*s - '0');
1948 } /* read the number */
1956 } /* register must be even numbered */
1964 } /* register must be multiple of 4 */
1968 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1969 error_message = _(": There are only 64 f registers; [0-63]");
1971 error_message = _(": There are only 32 f registers; [0-31]");
1974 else if (mask >= 32)
1976 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1979 mask -= 31; /* wrap high bit */
1983 error_message = _(": There are only 32 f registers; [0-31]");
1991 } /* if not an 'f' register. */
1998 opcode |= RS1 (mask);
2005 opcode |= RS2 (mask);
2011 opcode |= RD (mask);
2020 if (strncmp (s, "%fsr", 4) == 0)
2027 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2028 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2031 case 'l': /* 22 bit PC relative immediate */
2032 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2036 case 'L': /* 30 bit immediate */
2037 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2042 case 'n': /* 22 bit immediate */
2043 the_insn.reloc = BFD_RELOC_SPARC22;
2046 case 'i': /* 13 bit immediate */
2047 the_insn.reloc = BFD_RELOC_SPARC13;
2057 char *op_arg = NULL;
2059 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2061 /* Check for %hi, etc. */
2064 static const struct ops {
2065 /* The name as it appears in assembler. */
2067 /* strlen (name), precomputed for speed */
2069 /* The reloc this pseudo-op translates to. */
2071 /* Non-zero if for v9 only. */
2073 /* Non-zero if can be used in pc-relative contexts. */
2074 int pcrel_p;/*FIXME:wip*/
2076 /* hix/lox must appear before hi/lo so %hix won't be
2077 mistaken for %hi. */
2078 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2079 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2080 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2081 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2082 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2083 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2084 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2085 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2086 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2087 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2088 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2089 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2092 const struct ops *o;
2094 for (o = ops; o->name; o++)
2095 if (strncmp (s + 1, o->name, o->len) == 0)
2097 if (o->name == NULL)
2100 if (s[o->len + 1] != '(')
2102 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2103 return special_case;
2107 the_insn.reloc = o->reloc;
2112 /* Note that if the get_expression() fails, we will still
2113 have created U entries in the symbol table for the
2114 'symbols' in the input string. Try not to create U
2115 symbols for registers, etc. */
2117 /* This stuff checks to see if the expression ends in
2118 +%reg. If it does, it removes the register from
2119 the expression, and re-sets 's' to point to the
2126 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2129 else if (*s1 == ')')
2138 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2139 return special_case;
2143 (void) get_expression (s);
2146 if (*s == ',' || *s == ']' || !*s)
2148 if (*s != '+' && *s != '-')
2150 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2151 return special_case;
2155 op_exp = the_insn.exp;
2156 memset (&the_insn.exp, 0, sizeof(the_insn.exp));
2159 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
2161 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2163 if (s1[-2] == '%' && s1[-3] == '+')
2165 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2172 if (op_arg && s1 == s + 1)
2173 the_insn.exp.X_op = O_absent;
2175 (void) get_expression (s);
2187 (void) get_expression (s);
2195 the_insn.exp2 = the_insn.exp;
2196 the_insn.exp = op_exp;
2197 if (the_insn.exp2.X_op == O_absent)
2198 the_insn.exp2.X_op = O_illegal;
2199 else if (the_insn.exp.X_op == O_absent)
2201 the_insn.exp = the_insn.exp2;
2202 the_insn.exp2.X_op = O_illegal;
2204 else if (the_insn.exp.X_op == O_constant)
2206 valueT val = the_insn.exp.X_add_number;
2207 switch (the_insn.reloc)
2212 case BFD_RELOC_SPARC_HH22:
2213 val = BSR (val, 32);
2214 /* intentional fallthrough */
2216 case BFD_RELOC_SPARC_LM22:
2217 case BFD_RELOC_HI22:
2218 val = (val >> 10) & 0x3fffff;
2221 case BFD_RELOC_SPARC_HM10:
2222 val = BSR (val, 32);
2223 /* intentional fallthrough */
2225 case BFD_RELOC_LO10:
2229 case BFD_RELOC_SPARC_H44:
2234 case BFD_RELOC_SPARC_M44:
2239 case BFD_RELOC_SPARC_L44:
2243 case BFD_RELOC_SPARC_HIX22:
2245 val = (val >> 10) & 0x3fffff;
2248 case BFD_RELOC_SPARC_LOX10:
2249 val = (val & 0x3ff) | 0x1c00;
2252 the_insn.exp = the_insn.exp2;
2253 the_insn.exp.X_add_number += val;
2254 the_insn.exp2.X_op = O_illegal;
2255 the_insn.reloc = old_reloc;
2257 else if (the_insn.exp2.X_op != O_constant)
2259 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2260 return special_case;
2264 if (old_reloc != BFD_RELOC_SPARC13
2265 || the_insn.reloc != BFD_RELOC_LO10
2266 || sparc_arch_size != 64
2269 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2270 return special_case;
2272 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2276 /* Check for constants that don't require emitting a reloc. */
2277 if (the_insn.exp.X_op == O_constant
2278 && the_insn.exp.X_add_symbol == 0
2279 && the_insn.exp.X_op_symbol == 0)
2281 /* For pc-relative call instructions, we reject
2282 constants to get better code. */
2284 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2285 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2287 error_message = _(": PC-relative operand can't be a constant");
2291 /* Constants that won't fit are checked in md_apply_fix3
2292 and bfd_install_relocation.
2293 ??? It would be preferable to install the constants
2294 into the insn here and save having to create a fixS
2295 for each one. There already exists code to handle
2296 all the various cases (e.g. in md_apply_fix3 and
2297 bfd_install_relocation) so duplicating all that code
2298 here isn't right. */
2318 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2320 error_message = _(": invalid ASI name");
2326 if (! parse_const_expr_arg (&s, &asi))
2328 error_message = _(": invalid ASI expression");
2331 if (asi < 0 || asi > 255)
2333 error_message = _(": invalid ASI number");
2337 opcode |= ASI (asi);
2339 } /* alternate space */
2342 if (strncmp (s, "%psr", 4) == 0)
2349 case 'q': /* floating point queue */
2350 if (strncmp (s, "%fq", 3) == 0)
2357 case 'Q': /* coprocessor queue */
2358 if (strncmp (s, "%cq", 3) == 0)
2366 if (strcmp (str, "set") == 0
2367 || strcmp (str, "setuw") == 0)
2369 special_case = SPECIAL_CASE_SET;
2372 else if (strcmp (str, "setsw") == 0)
2374 special_case = SPECIAL_CASE_SETSW;
2377 else if (strcmp (str, "setx") == 0)
2379 special_case = SPECIAL_CASE_SETX;
2382 else if (strncmp (str, "fdiv", 4) == 0)
2384 special_case = SPECIAL_CASE_FDIV;
2390 if (strncmp (s, "%asi", 4) != 0)
2396 if (strncmp (s, "%fprs", 5) != 0)
2402 if (strncmp (s, "%ccr", 4) != 0)
2408 if (strncmp (s, "%tbr", 4) != 0)
2414 if (strncmp (s, "%wim", 4) != 0)
2421 char *push = input_line_pointer;
2424 input_line_pointer = s;
2426 if (e.X_op == O_constant)
2428 int n = e.X_add_number;
2429 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2430 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2432 opcode |= e.X_add_number << 5;
2435 as_bad (_("non-immediate OPF operand, ignored"));
2436 s = input_line_pointer;
2437 input_line_pointer = push;
2442 if (strncmp (s, "%y", 2) != 0)
2450 /* Parse a sparclet cpreg. */
2452 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2454 error_message = _(": invalid cpreg name");
2457 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2462 as_fatal (_("failed sanity check."));
2463 } /* switch on arg code */
2465 /* Break out of for() loop. */
2467 } /* for each arg that we expect */
2472 /* Args don't match. */
2473 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2474 && (insn->name == insn[1].name
2475 || !strcmp (insn->name, insn[1].name)))
2483 as_bad (_("Illegal operands%s"), error_message);
2484 return special_case;
2489 /* We have a match. Now see if the architecture is ok. */
2490 int needed_arch_mask = insn->architecture;
2494 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2495 | (1 << SPARC_OPCODE_ARCH_V9A));
2496 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2499 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2501 /* Can we bump up the architecture? */
2502 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2504 enum sparc_opcode_arch_val needed_architecture =
2505 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2506 & needed_arch_mask);
2508 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2510 && needed_architecture > warn_after_architecture)
2512 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2513 sparc_opcode_archs[current_architecture].name,
2514 sparc_opcode_archs[needed_architecture].name,
2516 warn_after_architecture = needed_architecture;
2518 current_architecture = needed_architecture;
2521 /* ??? This seems to be a bit fragile. What if the next entry in
2522 the opcode table is the one we want and it is supported?
2523 It is possible to arrange the table today so that this can't
2524 happen but what about tomorrow? */
2527 int arch,printed_one_p = 0;
2529 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2531 /* Create a list of the architectures that support the insn. */
2532 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2534 arch = sparc_ffs (needed_arch_mask);
2535 while ((1 << arch) <= needed_arch_mask)
2537 if ((1 << arch) & needed_arch_mask)
2541 strcpy (p, sparc_opcode_archs[arch].name);
2548 as_bad (_("Architecture mismatch on \"%s\"."), str);
2549 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2551 sparc_opcode_archs[max_architecture].name);
2552 return special_case;
2557 } /* forever looking for a match */
2559 the_insn.opcode = opcode;
2560 return special_case;
2563 /* Parse an argument that can be expressed as a keyword.
2564 (eg: #StoreStore or %ccfr).
2565 The result is a boolean indicating success.
2566 If successful, INPUT_POINTER is updated. */
2569 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2570 int (*lookup_fn) PARAMS ((const char *));
2571 char **input_pointerP;
2577 p = *input_pointerP;
2578 for (q = p + (*p == '#' || *p == '%');
2579 isalnum ((unsigned char) *q) || *q == '_';
2584 value = (*lookup_fn) (p);
2589 *input_pointerP = q;
2593 /* Parse an argument that is a constant expression.
2594 The result is a boolean indicating success. */
2597 parse_const_expr_arg (input_pointerP, valueP)
2598 char **input_pointerP;
2601 char *save = input_line_pointer;
2604 input_line_pointer = *input_pointerP;
2605 /* The next expression may be something other than a constant
2606 (say if we're not processing the right variant of the insn).
2607 Don't call expression unless we're sure it will succeed as it will
2608 signal an error (which we want to defer until later). */
2609 /* FIXME: It might be better to define md_operand and have it recognize
2610 things like %asi, etc. but continuing that route through to the end
2611 is a lot of work. */
2612 if (*input_line_pointer == '%')
2614 input_line_pointer = save;
2618 *input_pointerP = input_line_pointer;
2619 input_line_pointer = save;
2620 if (exp.X_op != O_constant)
2622 *valueP = exp.X_add_number;
2626 /* Subroutine of sparc_ip to parse an expression. */
2629 get_expression (str)
2635 save_in = input_line_pointer;
2636 input_line_pointer = str;
2637 seg = expression (&the_insn.exp);
2638 if (seg != absolute_section
2639 && seg != text_section
2640 && seg != data_section
2641 && seg != bss_section
2642 && seg != undefined_section)
2644 the_insn.error = _("bad segment");
2645 expr_end = input_line_pointer;
2646 input_line_pointer = save_in;
2649 expr_end = input_line_pointer;
2650 input_line_pointer = save_in;
2654 /* Subroutine of md_assemble to output one insn. */
2657 output_insn (insn, the_insn)
2658 const struct sparc_opcode *insn;
2659 struct sparc_it *the_insn;
2661 char *toP = frag_more (4);
2663 /* put out the opcode */
2664 if (INSN_BIG_ENDIAN)
2665 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2667 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2669 /* put out the symbol-dependent stuff */
2670 if (the_insn->reloc != BFD_RELOC_NONE)
2672 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2673 (toP - frag_now->fr_literal), /* where */
2678 /* Turn off overflow checking in fixup_segment. We'll do our
2679 own overflow checking in md_apply_fix3. This is necessary because
2680 the insn size is 4 and fixup_segment will signal an overflow for
2681 large 8 byte quantities. */
2682 fixP->fx_no_overflow = 1;
2683 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2684 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2688 last_opcode = the_insn->opcode;
2692 This is identical to the md_atof in m68k.c. I think this is right,
2695 Turn a string in input_line_pointer into a floating point constant of type
2696 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2697 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2700 /* Equal to MAX_PRECISION in atof-ieee.c */
2701 #define MAX_LITTLENUMS 6
2704 md_atof (type, litP, sizeP)
2710 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2741 return _("Bad call to MD_ATOF()");
2744 t = atof_ieee (input_line_pointer, type, words);
2746 input_line_pointer = t;
2747 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2749 if (target_big_endian)
2751 for (i = 0; i < prec; i++)
2753 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2754 litP += sizeof (LITTLENUM_TYPE);
2759 for (i = prec - 1; i >= 0; i--)
2761 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2762 litP += sizeof (LITTLENUM_TYPE);
2769 /* Write a value out to the object file, using the appropriate
2773 md_number_to_chars (buf, val, n)
2778 if (target_big_endian)
2779 number_to_chars_bigendian (buf, val, n);
2780 else if (target_little_endian_data
2781 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2782 /* Output debug words, which are not in allocated sections, as big endian */
2783 number_to_chars_bigendian (buf, val, n);
2784 else if (target_little_endian_data || ! target_big_endian)
2785 number_to_chars_littleendian (buf, val, n);
2788 /* Apply a fixS to the frags, now that we know the value it ought to
2792 md_apply_fix3 (fixP, value, segment)
2797 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2803 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2805 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2808 /* FIXME: SPARC ELF relocations don't use an addend in the data
2809 field itself. This whole approach should be somehow combined
2810 with the calls to bfd_install_relocation. Also, the value passed
2811 in by fixup_segment includes the value of a defined symbol. We
2812 don't want to include the value of an externally visible symbol. */
2813 if (fixP->fx_addsy != NULL)
2815 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2816 && (S_IS_EXTERNAL (fixP->fx_addsy)
2817 || S_IS_WEAK (fixP->fx_addsy)
2818 || (sparc_pic_code && ! fixP->fx_pcrel)
2819 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2820 && ((bfd_get_section_flags (stdoutput,
2821 S_GET_SEGMENT (fixP->fx_addsy))
2822 & SEC_LINK_ONCE) != 0
2823 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2825 sizeof ".gnu.linkonce" - 1) == 0)))
2826 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2827 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2828 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2829 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2834 /* This is a hack. There should be a better way to
2835 handle this. Probably in terms of howto fields, once
2836 we can look at these fixups in terms of howtos. */
2837 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2838 val += fixP->fx_where + fixP->fx_frag->fr_address;
2841 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2842 generate a reloc, then we just want to let the reloc addend set
2843 the value. We do not want to also stuff the addend into the
2844 object file. Including the addend in the object file works when
2845 doing a static link, because the linker will ignore the object
2846 file contents. However, the dynamic linker does not ignore the
2847 object file contents. */
2848 if (fixP->fx_addsy != NULL
2849 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2852 /* When generating PIC code, we do not want an addend for a reloc
2853 against a local symbol. We adjust fx_addnumber to cancel out the
2854 value already included in val, and to also cancel out the
2855 adjustment which bfd_install_relocation will create. */
2857 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2858 && fixP->fx_addsy != NULL
2859 && ! S_IS_COMMON (fixP->fx_addsy)
2860 && symbol_section_p (fixP->fx_addsy))
2861 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2863 /* When generating PIC code, we need to fiddle to get
2864 bfd_install_relocation to do the right thing for a PC relative
2865 reloc against a local symbol which we are going to keep. */
2867 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2868 && fixP->fx_addsy != NULL
2869 && (S_IS_EXTERNAL (fixP->fx_addsy)
2870 || S_IS_WEAK (fixP->fx_addsy))
2871 && S_IS_DEFINED (fixP->fx_addsy)
2872 && ! S_IS_COMMON (fixP->fx_addsy))
2875 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2879 /* If this is a data relocation, just output VAL. */
2881 if (fixP->fx_r_type == BFD_RELOC_16)
2883 md_number_to_chars (buf, val, 2);
2885 else if (fixP->fx_r_type == BFD_RELOC_32
2886 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2888 md_number_to_chars (buf, val, 4);
2890 else if (fixP->fx_r_type == BFD_RELOC_64)
2892 md_number_to_chars (buf, val, 8);
2894 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2895 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2902 /* It's a relocation against an instruction. */
2904 if (INSN_BIG_ENDIAN)
2905 insn = bfd_getb32 ((unsigned char *) buf);
2907 insn = bfd_getl32 ((unsigned char *) buf);
2909 switch (fixP->fx_r_type)
2911 case BFD_RELOC_32_PCREL_S2:
2913 /* FIXME: This increment-by-one deserves a comment of why it's
2915 if (! sparc_pic_code
2916 || fixP->fx_addsy == NULL
2917 || symbol_section_p (fixP->fx_addsy))
2919 insn |= val & 0x3fffffff;
2922 case BFD_RELOC_SPARC_11:
2923 if (! in_signed_range (val, 0x7ff))
2924 as_bad_where (fixP->fx_file, fixP->fx_line,
2925 _("relocation overflow"));
2926 insn |= val & 0x7ff;
2929 case BFD_RELOC_SPARC_10:
2930 if (! in_signed_range (val, 0x3ff))
2931 as_bad_where (fixP->fx_file, fixP->fx_line,
2932 _("relocation overflow"));
2933 insn |= val & 0x3ff;
2936 case BFD_RELOC_SPARC_7:
2937 if (! in_bitfield_range (val, 0x7f))
2938 as_bad_where (fixP->fx_file, fixP->fx_line,
2939 _("relocation overflow"));
2943 case BFD_RELOC_SPARC_6:
2944 if (! in_bitfield_range (val, 0x3f))
2945 as_bad_where (fixP->fx_file, fixP->fx_line,
2946 _("relocation overflow"));
2950 case BFD_RELOC_SPARC_5:
2951 if (! in_bitfield_range (val, 0x1f))
2952 as_bad_where (fixP->fx_file, fixP->fx_line,
2953 _("relocation overflow"));
2957 case BFD_RELOC_SPARC_WDISP16:
2958 /* FIXME: simplify */
2959 if (((val > 0) && (val & ~0x3fffc))
2960 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2961 as_bad_where (fixP->fx_file, fixP->fx_line,
2962 _("relocation overflow"));
2963 /* FIXME: The +1 deserves a comment. */
2964 val = (val >> 2) + 1;
2965 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2968 case BFD_RELOC_SPARC_WDISP19:
2969 /* FIXME: simplify */
2970 if (((val > 0) && (val & ~0x1ffffc))
2971 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2972 as_bad_where (fixP->fx_file, fixP->fx_line,
2973 _("relocation overflow"));
2974 /* FIXME: The +1 deserves a comment. */
2975 val = (val >> 2) + 1;
2976 insn |= val & 0x7ffff;
2979 case BFD_RELOC_SPARC_HH22:
2980 val = BSR (val, 32);
2981 /* intentional fallthrough */
2983 case BFD_RELOC_SPARC_LM22:
2984 case BFD_RELOC_HI22:
2985 if (!fixP->fx_addsy)
2987 insn |= (val >> 10) & 0x3fffff;
2991 /* FIXME: Need comment explaining why we do this. */
2996 case BFD_RELOC_SPARC22:
2997 if (val & ~0x003fffff)
2998 as_bad_where (fixP->fx_file, fixP->fx_line,
2999 _("relocation overflow"));
3000 insn |= (val & 0x3fffff);
3003 case BFD_RELOC_SPARC_HM10:
3004 val = BSR (val, 32);
3005 /* intentional fallthrough */
3007 case BFD_RELOC_LO10:
3008 if (!fixP->fx_addsy)
3010 insn |= val & 0x3ff;
3014 /* FIXME: Need comment explaining why we do this. */
3019 case BFD_RELOC_SPARC_OLO10:
3021 val += fixP->tc_fix_data;
3022 /* intentional fallthrough */
3024 case BFD_RELOC_SPARC13:
3025 if (! in_signed_range (val, 0x1fff))
3026 as_bad_where (fixP->fx_file, fixP->fx_line,
3027 _("relocation overflow"));
3028 insn |= val & 0x1fff;
3031 case BFD_RELOC_SPARC_WDISP22:
3032 val = (val >> 2) + 1;
3034 case BFD_RELOC_SPARC_BASE22:
3035 insn |= val & 0x3fffff;
3038 case BFD_RELOC_SPARC_H44:
3039 if (!fixP->fx_addsy)
3043 insn |= tval & 0x3fffff;
3047 case BFD_RELOC_SPARC_M44:
3048 if (!fixP->fx_addsy)
3049 insn |= (val >> 12) & 0x3ff;
3052 case BFD_RELOC_SPARC_L44:
3053 if (!fixP->fx_addsy)
3054 insn |= val & 0xfff;
3057 case BFD_RELOC_SPARC_HIX22:
3058 if (!fixP->fx_addsy)
3060 val ^= ~ (offsetT) 0;
3061 insn |= (val >> 10) & 0x3fffff;
3065 case BFD_RELOC_SPARC_LOX10:
3066 if (!fixP->fx_addsy)
3067 insn |= 0x1c00 | (val & 0x3ff);
3070 case BFD_RELOC_NONE:
3072 as_bad_where (fixP->fx_file, fixP->fx_line,
3073 _("bad or unhandled relocation type: 0x%02x"),
3078 if (INSN_BIG_ENDIAN)
3079 bfd_putb32 (insn, (unsigned char *) buf);
3081 bfd_putl32 (insn, (unsigned char *) buf);
3084 /* Are we finished with this relocation now? */
3085 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3091 /* Translate internal representation of relocation info to BFD target
3094 tc_gen_reloc (section, fixp)
3098 static arelent *relocs[3];
3100 bfd_reloc_code_real_type code;
3102 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3105 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3106 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3107 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3109 switch (fixp->fx_r_type)
3113 case BFD_RELOC_HI22:
3114 case BFD_RELOC_LO10:
3115 case BFD_RELOC_32_PCREL_S2:
3116 case BFD_RELOC_SPARC13:
3117 case BFD_RELOC_SPARC22:
3118 case BFD_RELOC_SPARC_BASE13:
3119 case BFD_RELOC_SPARC_WDISP16:
3120 case BFD_RELOC_SPARC_WDISP19:
3121 case BFD_RELOC_SPARC_WDISP22:
3123 case BFD_RELOC_SPARC_5:
3124 case BFD_RELOC_SPARC_6:
3125 case BFD_RELOC_SPARC_7:
3126 case BFD_RELOC_SPARC_10:
3127 case BFD_RELOC_SPARC_11:
3128 case BFD_RELOC_SPARC_HH22:
3129 case BFD_RELOC_SPARC_HM10:
3130 case BFD_RELOC_SPARC_LM22:
3131 case BFD_RELOC_SPARC_PC_HH22:
3132 case BFD_RELOC_SPARC_PC_HM10:
3133 case BFD_RELOC_SPARC_PC_LM22:
3134 case BFD_RELOC_SPARC_H44:
3135 case BFD_RELOC_SPARC_M44:
3136 case BFD_RELOC_SPARC_L44:
3137 case BFD_RELOC_SPARC_HIX22:
3138 case BFD_RELOC_SPARC_LOX10:
3139 case BFD_RELOC_SPARC_REV32:
3140 case BFD_RELOC_SPARC_OLO10:
3141 case BFD_RELOC_VTABLE_ENTRY:
3142 case BFD_RELOC_VTABLE_INHERIT:
3143 code = fixp->fx_r_type;
3150 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3151 /* If we are generating PIC code, we need to generate a different
3155 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3157 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3160 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3166 case BFD_RELOC_32_PCREL_S2:
3167 if (! S_IS_DEFINED (fixp->fx_addsy)
3168 || S_IS_COMMON (fixp->fx_addsy)
3169 || S_IS_EXTERNAL (fixp->fx_addsy)
3170 || S_IS_WEAK (fixp->fx_addsy))
3171 code = BFD_RELOC_SPARC_WPLT30;
3173 case BFD_RELOC_HI22:
3174 if (fixp->fx_addsy != NULL
3175 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3176 code = BFD_RELOC_SPARC_PC22;
3178 code = BFD_RELOC_SPARC_GOT22;
3180 case BFD_RELOC_LO10:
3181 if (fixp->fx_addsy != NULL
3182 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3183 code = BFD_RELOC_SPARC_PC10;
3185 code = BFD_RELOC_SPARC_GOT10;
3187 case BFD_RELOC_SPARC13:
3188 code = BFD_RELOC_SPARC_GOT13;
3194 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3196 if (code == BFD_RELOC_SPARC_OLO10)
3197 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3199 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3200 if (reloc->howto == 0)
3202 as_bad_where (fixp->fx_file, fixp->fx_line,
3203 _("internal error: can't export reloc type %d (`%s')"),
3204 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3210 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3213 if (reloc->howto->pc_relative == 0
3214 || code == BFD_RELOC_SPARC_PC10
3215 || code == BFD_RELOC_SPARC_PC22)
3216 reloc->addend = fixp->fx_addnumber;
3217 else if (sparc_pic_code
3218 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3219 && fixp->fx_addsy != NULL
3220 && (S_IS_EXTERNAL (fixp->fx_addsy)
3221 || S_IS_WEAK (fixp->fx_addsy))
3222 && S_IS_DEFINED (fixp->fx_addsy)
3223 && ! S_IS_COMMON (fixp->fx_addsy))
3224 reloc->addend = fixp->fx_addnumber;
3226 reloc->addend = fixp->fx_offset - reloc->address;
3228 #else /* elf or coff */
3230 if (reloc->howto->pc_relative == 0
3231 || code == BFD_RELOC_SPARC_PC10
3232 || code == BFD_RELOC_SPARC_PC22)
3233 reloc->addend = fixp->fx_addnumber;
3234 else if (symbol_section_p (fixp->fx_addsy))
3235 reloc->addend = (section->vma
3236 + fixp->fx_addnumber
3237 + md_pcrel_from (fixp));
3239 reloc->addend = fixp->fx_offset;
3242 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3243 on the same location. */
3244 if (code == BFD_RELOC_SPARC_OLO10)
3246 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3249 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3250 *reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section));
3251 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3252 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3253 reloc->addend = fixp->tc_fix_data;
3259 /* We have no need to default values of symbols. */
3263 md_undefined_symbol (name)
3267 } /* md_undefined_symbol() */
3269 /* Round up a section size to the appropriate boundary. */
3271 md_section_align (segment, size)
3276 /* This is not right for ELF; a.out wants it, and COFF will force
3277 the alignment anyways. */
3278 valueT align = ((valueT) 1
3279 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3281 /* turn alignment value into a mask */
3283 newsize = (size + align) & ~align;
3290 /* Exactly what point is a PC-relative offset relative TO?
3291 On the sparc, they're relative to the address of the offset, plus
3292 its size. This gets us to the following instruction.
3293 (??? Is this right? FIXME-SOON) */
3295 md_pcrel_from (fixP)
3300 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3301 if (! sparc_pic_code
3302 || fixP->fx_addsy == NULL
3303 || symbol_section_p (fixP->fx_addsy))
3304 ret += fixP->fx_size;
3308 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3320 for (shift = 0; (value & 1) == 0; value >>= 1)
3323 return (value == 1) ? shift : -1;
3327 * sort of like s_lcomm
3331 static int max_alignment = 15;
3346 name = input_line_pointer;
3347 c = get_symbol_end ();
3348 p = input_line_pointer;
3352 if (*input_line_pointer != ',')
3354 as_bad (_("Expected comma after name"));
3355 ignore_rest_of_line ();
3359 ++input_line_pointer;
3361 if ((size = get_absolute_expression ()) < 0)
3363 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3364 ignore_rest_of_line ();
3369 symbolP = symbol_find_or_make (name);
3372 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3373 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3375 as_bad (_("bad .reserve segment -- expected BSS segment"));
3379 if (input_line_pointer[2] == '.')
3380 input_line_pointer += 7;
3382 input_line_pointer += 6;
3385 if (*input_line_pointer == ',')
3387 ++input_line_pointer;
3390 if (*input_line_pointer == '\n')
3392 as_bad (_("missing alignment"));
3393 ignore_rest_of_line ();
3397 align = (int) get_absolute_expression ();
3400 if (align > max_alignment)
3402 align = max_alignment;
3403 as_warn (_("alignment too large; assuming %d"), align);
3409 as_bad (_("negative alignment"));
3410 ignore_rest_of_line ();
3416 temp = log2 (align);
3419 as_bad (_("alignment not a power of 2"));
3420 ignore_rest_of_line ();
3427 record_alignment (bss_section, align);
3432 if (!S_IS_DEFINED (symbolP)
3434 && S_GET_OTHER (symbolP) == 0
3435 && S_GET_DESC (symbolP) == 0
3442 segT current_seg = now_seg;
3443 subsegT current_subseg = now_subseg;
3445 subseg_set (bss_section, 1); /* switch to bss */
3448 frag_align (align, 0, 0); /* do alignment */
3450 /* detach from old frag */
3451 if (S_GET_SEGMENT(symbolP) == bss_section)
3452 symbol_get_frag (symbolP)->fr_symbol = NULL;
3454 symbol_set_frag (symbolP, frag_now);
3455 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3456 (offsetT) size, (char *)0);
3459 S_SET_SEGMENT (symbolP, bss_section);
3461 subseg_set (current_seg, current_subseg);
3464 S_SET_SIZE (symbolP, size);
3470 as_warn("Ignoring attempt to re-define symbol %s",
3471 S_GET_NAME (symbolP));
3472 } /* if not redefining */
3474 demand_empty_rest_of_line ();
3487 name = input_line_pointer;
3488 c = get_symbol_end ();
3489 /* just after name is now '\0' */
3490 p = input_line_pointer;
3493 if (*input_line_pointer != ',')
3495 as_bad (_("Expected comma after symbol-name"));
3496 ignore_rest_of_line ();
3499 input_line_pointer++; /* skip ',' */
3500 if ((temp = get_absolute_expression ()) < 0)
3502 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3503 ignore_rest_of_line ();
3508 symbolP = symbol_find_or_make (name);
3510 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3512 as_bad (_("Ignoring attempt to re-define symbol"));
3513 ignore_rest_of_line ();
3516 if (S_GET_VALUE (symbolP) != 0)
3518 if (S_GET_VALUE (symbolP) != (valueT) size)
3520 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3521 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3527 S_SET_VALUE (symbolP, (valueT) size);
3528 S_SET_EXTERNAL (symbolP);
3531 know (symbol_get_frag (symbolP) == &zero_address_frag);
3532 if (*input_line_pointer != ',')
3534 as_bad (_("Expected comma after common length"));
3535 ignore_rest_of_line ();
3538 input_line_pointer++;
3540 if (*input_line_pointer != '"')
3542 temp = get_absolute_expression ();
3545 if (temp > max_alignment)
3547 temp = max_alignment;
3548 as_warn (_("alignment too large; assuming %d"), temp);
3554 as_bad (_("negative alignment"));
3555 ignore_rest_of_line ();
3560 if (symbol_get_obj (symbolP)->local)
3568 old_subsec = now_subseg;
3573 align = log2 (temp);
3577 as_bad (_("alignment not a power of 2"));
3578 ignore_rest_of_line ();
3582 record_alignment (bss_section, align);
3583 subseg_set (bss_section, 0);
3585 frag_align (align, 0, 0);
3586 if (S_GET_SEGMENT (symbolP) == bss_section)
3587 symbol_get_frag (symbolP)->fr_symbol = 0;
3588 symbol_set_frag (symbolP, frag_now);
3589 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3590 (offsetT) size, (char *) 0);
3592 S_SET_SEGMENT (symbolP, bss_section);
3593 S_CLEAR_EXTERNAL (symbolP);
3594 S_SET_SIZE (symbolP, size);
3595 subseg_set (old_sec, old_subsec);
3598 #endif /* OBJ_ELF */
3601 S_SET_VALUE (symbolP, (valueT) size);
3603 S_SET_ALIGN (symbolP, temp);
3604 S_SET_SIZE (symbolP, size);
3606 S_SET_EXTERNAL (symbolP);
3607 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3612 input_line_pointer++;
3613 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3614 if (*input_line_pointer == '.')
3615 input_line_pointer++;
3616 /* @@ Some say data, some say bss. */
3617 if (strncmp (input_line_pointer, "bss\"", 4)
3618 && strncmp (input_line_pointer, "data\"", 5))
3620 while (*--input_line_pointer != '"')
3622 input_line_pointer--;
3623 goto bad_common_segment;
3625 while (*input_line_pointer++ != '"')
3627 goto allocate_common;
3630 #ifdef BFD_ASSEMBLER
3631 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3634 demand_empty_rest_of_line ();
3639 p = input_line_pointer;
3640 while (*p && *p != '\n')
3644 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3646 input_line_pointer = p;
3647 ignore_rest_of_line ();
3652 /* Handle the .empty pseudo-op. This supresses the warnings about
3653 invalid delay slot usage. */
3659 /* The easy way to implement is to just forget about the last
3669 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3671 input_line_pointer += 6;
3675 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3677 input_line_pointer += 6;
3681 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3683 input_line_pointer += 7;
3687 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3689 input_line_pointer += 5;
3690 /* We only support 2 segments -- text and data -- for now, so
3691 things in the "bss segment" will have to go into data for now.
3692 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3693 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3696 as_bad (_("Unknown segment type"));
3697 demand_empty_rest_of_line ();
3703 subseg_set (data_section, 1);
3704 demand_empty_rest_of_line ();
3711 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3713 ++input_line_pointer;
3715 ++input_line_pointer;
3718 /* This static variable is set by s_uacons to tell sparc_cons_align
3719 that the expession does not need to be aligned. */
3721 static int sparc_no_align_cons = 0;
3723 /* This handles the unaligned space allocation pseudo-ops, such as
3724 .uaword. .uaword is just like .word, but the value does not need
3731 /* Tell sparc_cons_align not to align this value. */
3732 sparc_no_align_cons = 1;
3736 /* This handles the native word allocation pseudo-op .nword.
3737 For sparc_arch_size 32 it is equivalent to .word, for
3738 sparc_arch_size 64 it is equivalent to .xword. */
3744 cons (sparc_arch_size == 32 ? 4 : 8);
3748 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3752 .register %g[2367],{#scratch|symbolname|#ignore}
3762 const char *regname;
3764 if (input_line_pointer[0] != '%'
3765 || input_line_pointer[1] != 'g'
3766 || ((input_line_pointer[2] & ~1) != '2'
3767 && (input_line_pointer[2] & ~1) != '6')
3768 || input_line_pointer[3] != ',')
3769 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3770 reg = input_line_pointer[2] - '0';
3771 input_line_pointer += 4;
3773 if (*input_line_pointer == '#')
3775 ++input_line_pointer;
3776 regname = input_line_pointer;
3777 c = get_symbol_end ();
3778 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3779 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3780 if (regname [0] == 'i')
3787 regname = input_line_pointer;
3788 c = get_symbol_end ();
3790 if (sparc_arch_size == 64)
3794 if ((regname && globals [reg] != (symbolS *)1
3795 && strcmp (S_GET_NAME (globals [reg]), regname))
3796 || ((regname != NULL) ^ (globals [reg] != (symbolS *)1)))
3797 as_bad (_("redefinition of global register"));
3801 if (regname == NULL)
3802 globals [reg] = (symbolS *)1;
3807 if (symbol_find (regname))
3808 as_bad (_("Register symbol %s already defined."),
3811 globals [reg] = symbol_make (regname);
3812 flags = symbol_get_bfdsym (globals [reg])->flags;
3814 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3815 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3816 flags |= BSF_GLOBAL;
3817 symbol_get_bfdsym (globals [reg])->flags = flags;
3818 S_SET_VALUE (globals [reg], (valueT)reg);
3819 S_SET_ALIGN (globals [reg], reg);
3820 S_SET_SIZE (globals [reg], 0);
3821 /* Although we actually want undefined_section here,
3822 we have to use absolute_section, because otherwise
3823 generic as code will make it a COM section.
3824 We fix this up in sparc_adjust_symtab. */
3825 S_SET_SEGMENT (globals [reg], absolute_section);
3826 S_SET_OTHER (globals [reg], 0);
3827 elf_symbol (symbol_get_bfdsym (globals [reg]))
3828 ->internal_elf_sym.st_info =
3829 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
3830 elf_symbol (symbol_get_bfdsym (globals [reg]))
3831 ->internal_elf_sym.st_shndx = SHN_UNDEF;
3836 *input_line_pointer = c;
3838 demand_empty_rest_of_line ();
3841 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
3842 symbols which need it. */
3845 sparc_adjust_symtab ()
3849 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
3851 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3852 ->internal_elf_sym.st_info) != STT_REGISTER)
3855 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3856 ->internal_elf_sym.st_shndx != SHN_UNDEF))
3859 S_SET_SEGMENT (sym, undefined_section);
3864 /* If the --enforce-aligned-data option is used, we require .word,
3865 et. al., to be aligned correctly. We do it by setting up an
3866 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3867 no unexpected alignment was introduced.
3869 The SunOS and Solaris native assemblers enforce aligned data by
3870 default. We don't want to do that, because gcc can deliberately
3871 generate misaligned data if the packed attribute is used. Instead,
3872 we permit misaligned data by default, and permit the user to set an
3873 option to check for it. */
3876 sparc_cons_align (nbytes)
3882 /* Only do this if we are enforcing aligned data. */
3883 if (! enforce_aligned_data)
3886 if (sparc_no_align_cons)
3888 /* This is an unaligned pseudo-op. */
3889 sparc_no_align_cons = 0;
3893 nalign = log2 (nbytes);
3897 assert (nalign > 0);
3899 if (now_seg == absolute_section)
3901 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3902 as_bad (_("misaligned data"));
3906 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3907 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3909 record_alignment (now_seg, nalign);
3912 /* This is where we do the unexpected alignment check.
3913 This is called from HANDLE_ALIGN in tc-sparc.h. */
3916 sparc_handle_align (fragp)
3919 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
3920 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
3921 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
3922 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3924 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3929 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
3931 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3934 for (i = 0; i < count; i += 4, p++)
3935 if (INSN_BIG_ENDIAN)
3936 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3938 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3940 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
3942 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3943 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3944 if (INSN_BIG_ENDIAN)
3945 number_to_chars_bigendian (waddr, wval, 4);
3947 number_to_chars_littleendian (waddr, wval, 4);
3949 fragp->fr_var = count;
3955 /* Some special processing for a Sparc ELF file. */
3958 sparc_elf_final_processing ()
3960 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3961 sort of BFD interface for this. */
3962 if (sparc_arch_size == 64)
3964 switch (sparc_memory_model)
3967 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3970 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3976 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3977 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3978 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3979 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3983 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3984 reloc for a cons. We could use the definition there, except that
3985 we want to handle little endian relocs specially. */
3988 cons_fix_new_sparc (frag, where, nbytes, exp)
3991 unsigned int nbytes;
3994 bfd_reloc_code_real_type r;
3996 r = (nbytes == 1 ? BFD_RELOC_8 :
3997 (nbytes == 2 ? BFD_RELOC_16 :
3998 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4000 if (target_little_endian_data && nbytes == 4
4001 && now_seg->flags & SEC_ALLOC)
4002 r = BFD_RELOC_SPARC_REV32;
4003 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4008 elf32_sparc_force_relocation (fixp)
4011 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4012 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)