1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* careful, this file includes data *declarations* */
28 #include "opcode/sparc.h"
30 static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
31 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
32 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
33 static int sparc_ffs PARAMS ((unsigned int));
34 static bfd_vma BSR PARAMS ((bfd_vma, int));
35 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
36 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
37 static int parse_const_expr_arg PARAMS ((char **, int *));
39 /* Current architecture. We don't bump up unless necessary. */
40 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
42 /* The maximum architecture level we can bump up to.
43 In a 32 bit environment, don't allow bumping up to v9 by default.
44 The native assembler works this way. The user is required to pass
45 an explicit argument before we'll create v9 object files. However, if
46 we don't see any v9 insns, a v9 object file is not created. */
48 static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_V9;
50 /* ??? This should be V8, but sparclite support was added by making it the
51 default. GCC now passes -Asparclite, so maybe sometime in the future
52 we can set this to V8. */
53 static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_SPARCLITE;
56 static int architecture_requested;
57 static int warn_on_bump;
59 /* If warn_on_bump and the needed architecture is higher than this
60 architecture, issue a warning. */
61 static enum sparc_opcode_arch_val warn_after_architecture;
63 /* Non-zero if we are generating PIC code. */
66 /* Non-zero if we should give an error when misaligned data is seen. */
67 static int enforce_aligned_data;
69 extern int target_big_endian;
71 /* V9 has big and little endian data, but instructions are always big endian.
72 The sparclet has bi-endian support but both data and insns have the same
73 endianness. Global `target_big_endian' is used for data. The following
74 macro is used for instructions. */
75 #define INSN_BIG_ENDIAN (target_big_endian \
76 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
78 /* handle of the OPCODE hash table */
79 static struct hash_control *op_hash;
81 static void s_data1 PARAMS ((void));
82 static void s_seg PARAMS ((int));
83 static void s_proc PARAMS ((int));
84 static void s_reserve PARAMS ((int));
85 static void s_common PARAMS ((int));
86 static void s_empty PARAMS ((int));
87 static void s_uacons PARAMS ((int));
89 const pseudo_typeS md_pseudo_table[] =
91 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
92 {"common", s_common, 0},
93 {"empty", s_empty, 0},
94 {"global", s_globl, 0},
96 {"optim", s_ignore, 0},
98 {"reserve", s_reserve, 0},
100 {"skip", s_space, 0},
103 {"uahalf", s_uacons, 2},
104 {"uaword", s_uacons, 4},
105 {"uaxword", s_uacons, 8},
107 /* these are specific to sparc/svr4 */
108 {"pushsection", obj_elf_section, 0},
109 {"popsection", obj_elf_previous, 0},
110 {"2byte", s_uacons, 2},
111 {"4byte", s_uacons, 4},
112 {"8byte", s_uacons, 8},
117 const int md_reloc_size = 12; /* Size of relocation record */
119 /* This array holds the chars that always start a comment. If the
120 pre-processor is disabled, these aren't very useful */
121 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
123 /* This array holds the chars that only start a comment at the beginning of
124 a line. If the line seems to have the form '# 123 filename'
125 .line and .file directives will appear in the pre-processed output */
126 /* Note that input_file.c hand checks for '#' at the beginning of the
127 first line of the input file. This is because the compiler outputs
128 #NO_APP at the beginning of its output. */
129 /* Also note that comments started like this one will always
130 work if '/' isn't otherwise defined. */
131 const char line_comment_chars[] = "#";
133 const char line_separator_chars[] = "";
135 /* Chars that can be used to separate mant from exp in floating point nums */
136 const char EXP_CHARS[] = "eE";
138 /* Chars that mean this number is a floating point constant */
141 const char FLT_CHARS[] = "rRsSfFdDxXpP";
143 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
144 changed in read.c. Ideally it shouldn't have to know about it at all,
145 but nothing is ideal around here. */
147 static unsigned char octal[256];
148 #define isoctal(c) octal[(unsigned char) (c)]
149 static unsigned char toHex[256];
154 unsigned long opcode;
155 struct nlist *nlistp;
158 bfd_reloc_code_real_type reloc;
161 struct sparc_it the_insn, set_insn;
163 static void output_insn
164 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
166 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
169 in_signed_range (val, max)
170 bfd_signed_vma val, max;
181 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
182 (e.g. -15 to +31). */
185 in_bitfield_range (val, max)
186 bfd_signed_vma val, max;
192 if (val < ~(max >> 1))
206 for (i = 0; (mask & 1) == 0; ++i)
211 /* Implement big shift right. */
217 if (sizeof (bfd_vma) <= 4 && amount >= 32)
218 as_fatal ("Support for 64-bit arithmetic not compiled in.");
219 return val >> amount;
223 static void print_insn PARAMS ((struct sparc_it *insn));
225 static int getExpression PARAMS ((char *str));
227 static char *expr_end;
228 static int special_case;
231 * Instructions that require wierd handling because they're longer than
234 #define SPECIAL_CASE_SET 1
235 #define SPECIAL_CASE_SETSW 2
236 #define SPECIAL_CASE_SETX 3
237 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
238 #define SPECIAL_CASE_FDIV 4
240 /* Bit masks of various insns. */
241 #define NOP_INSN 0x01000000
242 #define OR_INSN 0x80100000
243 #define FMOVS_INSN 0x81A00020
244 #define SETHI_INSN 0x01000000
245 #define SLLX_INSN 0x81281000
246 #define SRA_INSN 0x81380000
248 /* The last instruction to be assembled. */
249 static const struct sparc_opcode *last_insn;
250 /* The assembled opcode of `last_insn'. */
251 static unsigned long last_opcode;
254 * sort of like s_lcomm
258 static int max_alignment = 15;
273 name = input_line_pointer;
274 c = get_symbol_end ();
275 p = input_line_pointer;
279 if (*input_line_pointer != ',')
281 as_bad ("Expected comma after name");
282 ignore_rest_of_line ();
286 ++input_line_pointer;
288 if ((size = get_absolute_expression ()) < 0)
290 as_bad ("BSS length (%d.) <0! Ignored.", size);
291 ignore_rest_of_line ();
296 symbolP = symbol_find_or_make (name);
299 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
300 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
302 as_bad ("bad .reserve segment -- expected BSS segment");
306 if (input_line_pointer[2] == '.')
307 input_line_pointer += 7;
309 input_line_pointer += 6;
312 if (*input_line_pointer == ',')
314 ++input_line_pointer;
317 if (*input_line_pointer == '\n')
319 as_bad ("Missing alignment");
323 align = get_absolute_expression ();
325 if (align > max_alignment)
327 align = max_alignment;
328 as_warn ("Alignment too large: %d. assumed.", align);
334 as_warn ("Alignment negative. 0 assumed.");
337 record_alignment (bss_section, align);
339 /* convert to a power of 2 alignment */
340 for (temp = 0; (align & 1) == 0; align >>= 1, ++temp);;
344 as_bad ("Alignment not a power of 2");
345 ignore_rest_of_line ();
347 } /* not a power of two */
350 } /* if has optional alignment */
354 if (!S_IS_DEFINED (symbolP)
356 && S_GET_OTHER (symbolP) == 0
357 && S_GET_DESC (symbolP) == 0
364 segT current_seg = now_seg;
365 subsegT current_subseg = now_subseg;
367 subseg_set (bss_section, 1); /* switch to bss */
370 frag_align (align, 0, 0); /* do alignment */
372 /* detach from old frag */
373 if (S_GET_SEGMENT(symbolP) == bss_section)
374 symbolP->sy_frag->fr_symbol = NULL;
376 symbolP->sy_frag = frag_now;
377 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
378 (offsetT) size, (char *)0);
381 S_SET_SEGMENT (symbolP, bss_section);
383 subseg_set (current_seg, current_subseg);
388 as_warn("Ignoring attempt to re-define symbol %s",
389 S_GET_NAME (symbolP));
390 } /* if not redefining */
392 demand_empty_rest_of_line ();
405 name = input_line_pointer;
406 c = get_symbol_end ();
407 /* just after name is now '\0' */
408 p = input_line_pointer;
411 if (*input_line_pointer != ',')
413 as_bad ("Expected comma after symbol-name");
414 ignore_rest_of_line ();
417 input_line_pointer++; /* skip ',' */
418 if ((temp = get_absolute_expression ()) < 0)
420 as_bad (".COMMon length (%d.) <0! Ignored.", temp);
421 ignore_rest_of_line ();
426 symbolP = symbol_find_or_make (name);
428 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
430 as_bad ("Ignoring attempt to re-define symbol");
431 ignore_rest_of_line ();
434 if (S_GET_VALUE (symbolP) != 0)
436 if (S_GET_VALUE (symbolP) != size)
438 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
439 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
445 S_SET_VALUE (symbolP, (valueT) size);
446 S_SET_EXTERNAL (symbolP);
449 know (symbolP->sy_frag == &zero_address_frag);
450 if (*input_line_pointer != ',')
452 as_bad ("Expected comma after common length");
453 ignore_rest_of_line ();
456 input_line_pointer++;
458 if (*input_line_pointer != '"')
460 temp = get_absolute_expression ();
462 if (temp > max_alignment)
464 temp = max_alignment;
465 as_warn ("Common alignment too large: %d. assumed", temp);
471 as_warn ("Common alignment negative; 0 assumed");
482 old_subsec = now_subseg;
484 record_alignment (bss_section, align);
485 subseg_set (bss_section, 0);
487 frag_align (align, 0, 0);
488 if (S_GET_SEGMENT (symbolP) == bss_section)
489 symbolP->sy_frag->fr_symbol = 0;
490 symbolP->sy_frag = frag_now;
491 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
492 (offsetT) size, (char *) 0);
494 S_SET_SEGMENT (symbolP, bss_section);
495 S_CLEAR_EXTERNAL (symbolP);
496 subseg_set (old_sec, old_subsec);
502 S_SET_VALUE (symbolP, (valueT) size);
504 S_SET_ALIGN (symbolP, temp);
506 S_SET_EXTERNAL (symbolP);
507 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
512 input_line_pointer++;
513 /* @@ Some use the dot, some don't. Can we get some consistency?? */
514 if (*input_line_pointer == '.')
515 input_line_pointer++;
516 /* @@ Some say data, some say bss. */
517 if (strncmp (input_line_pointer, "bss\"", 4)
518 && strncmp (input_line_pointer, "data\"", 5))
520 while (*--input_line_pointer != '"')
522 input_line_pointer--;
523 goto bad_common_segment;
525 while (*input_line_pointer++ != '"')
527 goto allocate_common;
531 symbolP->bsym->flags |= BSF_OBJECT;
534 demand_empty_rest_of_line ();
539 p = input_line_pointer;
540 while (*p && *p != '\n')
544 as_bad ("bad .common segment %s", input_line_pointer + 1);
546 input_line_pointer = p;
547 ignore_rest_of_line ();
552 /* Handle the .empty pseudo-op. This supresses the warnings about
553 invalid delay slot usage. */
559 /* The easy way to implement is to just forget about the last
569 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
571 input_line_pointer += 6;
575 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
577 input_line_pointer += 6;
581 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
583 input_line_pointer += 7;
587 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
589 input_line_pointer += 5;
590 /* We only support 2 segments -- text and data -- for now, so
591 things in the "bss segment" will have to go into data for now.
592 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
593 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
596 as_bad ("Unknown segment type");
597 demand_empty_rest_of_line ();
603 subseg_set (data_section, 1);
604 demand_empty_rest_of_line ();
611 while (!is_end_of_line[(unsigned char) *input_line_pointer])
613 ++input_line_pointer;
615 ++input_line_pointer;
618 /* This static variable is set by s_uacons to tell sparc_cons_align
619 that the expession does not need to be aligned. */
621 static int sparc_no_align_cons = 0;
623 /* This handles the unaligned space allocation pseudo-ops, such as
624 .uaword. .uaword is just like .word, but the value does not need
631 /* Tell sparc_cons_align not to align this value. */
632 sparc_no_align_cons = 1;
636 /* If the --enforce-aligned-data option is used, we require .word,
637 et. al., to be aligned correctly. We do it by setting up an
638 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
639 no unexpected alignment was introduced.
641 The SunOS and Solaris native assemblers enforce aligned data by
642 default. We don't want to do that, because gcc can deliberately
643 generate misaligned data if the packed attribute is used. Instead,
644 we permit misaligned data by default, and permit the user to set an
645 option to check for it. */
648 sparc_cons_align (nbytes)
654 /* Only do this if we are enforcing aligned data. */
655 if (! enforce_aligned_data)
658 if (sparc_no_align_cons)
660 /* This is an unaligned pseudo-op. */
661 sparc_no_align_cons = 0;
666 while ((nbytes & 1) == 0)
675 if (now_seg == absolute_section)
677 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
678 as_bad ("misaligned data");
682 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
683 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
685 record_alignment (now_seg, nalign);
688 /* This is where we do the unexpected alignment check. */
691 sparc_handle_align (fragp)
694 if (fragp->fr_type == rs_align_code
695 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
696 as_bad_where (fragp->fr_file, fragp->fr_line, "misaligned data");
699 /* sparc64 priviledged registers */
701 struct priv_reg_entry
707 struct priv_reg_entry priv_reg_table[] =
726 {"", -1}, /* end marker */
730 cmp_reg_entry (parg, qarg)
734 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
735 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
737 return strcmp (q->name, p->name);
740 /* This function is called once, at assembler startup time. It should
741 set up all the tables, etc. that the MD part of the assembler will need. */
746 register const char *retval = NULL;
748 register unsigned int i = 0;
750 op_hash = hash_new ();
752 while (i < sparc_num_opcodes)
754 const char *name = sparc_opcodes[i].name;
755 retval = hash_insert (op_hash, name, &sparc_opcodes[i]);
758 fprintf (stderr, "internal error: can't hash `%s': %s\n",
759 sparc_opcodes[i].name, retval);
764 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
766 fprintf (stderr, "internal error: losing opcode: `%s' \"%s\"\n",
767 sparc_opcodes[i].name, sparc_opcodes[i].args);
772 while (i < sparc_num_opcodes
773 && !strcmp (sparc_opcodes[i].name, name));
777 as_fatal ("Broken assembler. No assembly attempted.");
779 for (i = '0'; i < '8'; ++i)
781 for (i = '0'; i <= '9'; ++i)
783 for (i = 'a'; i <= 'f'; ++i)
784 toHex[i] = i + 10 - 'a';
785 for (i = 'A'; i <= 'F'; ++i)
786 toHex[i] = i + 10 - 'A';
788 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
789 sizeof (priv_reg_table[0]), cmp_reg_entry);
791 /* If -bump, record the architecture level at which we start issuing
792 warnings. The behaviour is different depending upon whether an
793 architecture was explicitly specified. If it wasn't, we issue warnings
794 for all upwards bumps. If it was, we don't start issuing warnings until
795 we need to bump beyond the requested architecture or when we bump between
796 conflicting architectures. */
799 && architecture_requested)
801 /* `max_architecture' records the requested architecture.
802 Issue warnings if we go above it. */
803 warn_after_architecture = max_architecture;
805 /* Find the highest architecture level that doesn't conflict with
806 the requested one. */
807 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
808 max_architecture > warn_after_architecture;
810 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
811 warn_after_architecture))
816 /* Called after all assembly has been done. */
822 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
823 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
825 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
827 if (current_architecture == SPARC_OPCODE_ARCH_V9)
828 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
829 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
830 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
831 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
832 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
835 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
836 be but for now it is (since that's the way it's always been
838 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
843 /* Utility to output one insn. */
846 output_insn (insn, the_insn)
847 const struct sparc_opcode *insn;
848 struct sparc_it *the_insn;
850 char *toP = frag_more (4);
852 /* put out the opcode */
854 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
856 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
858 /* put out the symbol-dependent stuff */
859 if (the_insn->reloc != BFD_RELOC_NONE)
861 fix_new_exp (frag_now, /* which frag */
862 (toP - frag_now->fr_literal), /* where */
870 last_opcode = the_insn->opcode;
877 const struct sparc_opcode *insn;
881 sparc_ip (str, &insn);
883 /* We warn about attempts to put a floating point branch in a delay slot,
884 unless the delay slot has been annulled. */
887 && (insn->flags & F_FBR) != 0
888 && (last_insn->flags & F_DELAYED) != 0
889 /* ??? This test isn't completely accurate. We assume anything with
890 F_{UNBR,CONDBR,FBR} set is annullable. */
891 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
892 || (last_opcode & ANNUL) == 0))
893 as_warn ("FP branch in delay slot");
895 /* SPARC before v9 requires a nop instruction between a floating
896 point instruction and a floating point branch. We insert one
897 automatically, with a warning. */
898 if (max_architecture < SPARC_OPCODE_ARCH_V9
901 && (insn->flags & F_FBR) != 0
902 && (last_insn->flags & F_FLOAT) != 0)
904 struct sparc_it nop_insn;
906 nop_insn.opcode = NOP_INSN;
907 nop_insn.reloc = BFD_RELOC_NONE;
908 output_insn (insn, &nop_insn);
909 as_warn ("FP branch preceded by FP instruction; NOP inserted");
912 switch (special_case)
916 output_insn (insn, &the_insn);
919 case SPECIAL_CASE_SET:
923 /* "set" is not defined for negative numbers in v9: it doesn't yield
924 what you expect it to. */
925 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
926 && the_insn.exp.X_op == O_constant)
928 if (the_insn.exp.X_add_number < 0)
929 as_warn ("set: used with negative number");
930 else if (the_insn.exp.X_add_number > 0xffffffff)
931 as_warn ("set: number larger than 4294967295");
934 /* See if operand is absolute and small; skip sethi if so. */
935 if (the_insn.exp.X_op != O_constant
936 || the_insn.exp.X_add_number >= (1 << 12)
937 || the_insn.exp.X_add_number < -(1 << 12))
939 output_insn (insn, &the_insn);
942 /* See if operand has no low-order bits; skip OR if so. */
943 if (the_insn.exp.X_op != O_constant
944 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
947 int rd = (the_insn.opcode & RD (~0)) >> 25;
948 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
951 | (the_insn.exp.X_add_number
952 & (need_hi22_p ? 0x3ff : 0x1fff)));
953 the_insn.reloc = (the_insn.exp.X_op != O_constant
956 output_insn (insn, &the_insn);
961 case SPECIAL_CASE_SETSW:
963 /* FIXME: Not finished. */
967 case SPECIAL_CASE_SETX:
969 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
970 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
971 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
973 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
974 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
975 /* Output directly to dst reg if lower 32 bits are all zero. */
976 int upper_dstreg = (the_insn.exp.X_op == O_constant
977 && lower32 == 0) ? dstreg : tmpreg;
978 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
980 /* The tmp reg should not be the dst reg. */
981 if (tmpreg == dstreg)
982 as_warn ("setx: temporary register same as destination register");
984 /* Reset X_add_number, we've extracted it as upper32/lower32.
985 Otherwise fixup_segment will complain about not being able to
986 write an 8 byte number in a 4 byte field. */
987 the_insn.exp.X_add_number = 0;
989 /* ??? Obviously there are other optimizations we can do
990 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
991 doing some of these. Later. If you do change things, try to
992 change all of this to be table driven as well. */
994 /* What to output depends on the number if it's constant.
995 Compute that first, then output what we've decided upon. */
996 if (the_insn.exp.X_op != O_constant)
997 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1000 /* Only need hh22 if `or' insn can't handle constant. */
1001 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1004 /* Does bottom part (after sethi) have bits? */
1005 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1006 /* No hh22, but does upper32 still have bits we can't set
1010 && (upper32 != -1 || lower32 >= 0)))
1013 /* If the lower half is all zero, we build the upper half directly
1014 into the dst reg. */
1016 /* Need lower half if number is zero. */
1017 || (! need_hh22_p && ! need_hm10_p))
1019 /* No need for sethi if `or' insn can handle constant. */
1020 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1021 /* Note that we can't use a negative constant in the `or'
1022 insn unless the upper 32 bits are all ones. */
1023 || (lower32 < 0 && upper32 != -1))
1026 /* Does bottom part (after sethi) have bits? */
1027 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1029 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1030 /* Need `or' if we didn't set anything else. */
1031 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1038 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1039 | ((upper32 >> 10) & 0x3fffff));
1040 the_insn.reloc = (the_insn.exp.X_op != O_constant
1041 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1042 output_insn (insn, &the_insn);
1047 the_insn.opcode = (OR_INSN
1048 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1052 & (need_hh22_p ? 0x3ff : 0x1fff)));
1053 the_insn.reloc = (the_insn.exp.X_op != O_constant
1054 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1055 output_insn (insn, &the_insn);
1060 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1061 | ((lower32 >> 10) & 0x3fffff));
1062 the_insn.reloc = BFD_RELOC_HI22;
1063 output_insn (insn, &the_insn);
1068 /* FIXME: One nice optimization to do here is to OR the low part
1069 with the highpart if hi22 isn't needed and the low part is
1071 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1075 & (need_hi22_p ? 0x3ff : 0x1fff)));
1076 the_insn.reloc = BFD_RELOC_LO10;
1077 output_insn (insn, &the_insn);
1080 /* If we needed to build the upper part, shift it into place. */
1081 if (need_hh22_p || need_hm10_p)
1083 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1085 the_insn.reloc = BFD_RELOC_NONE;
1086 output_insn (insn, &the_insn);
1089 /* If we needed to build both upper and lower parts, OR them together. */
1090 if ((need_hh22_p || need_hm10_p)
1091 && (need_hi22_p || need_lo10_p))
1093 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1095 the_insn.reloc = BFD_RELOC_NONE;
1096 output_insn (insn, &the_insn);
1098 /* We didn't need both regs, but we may have to sign extend lower32. */
1099 else if (need_hi22_p && upper32 == -1)
1101 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1103 the_insn.reloc = BFD_RELOC_NONE;
1104 output_insn (insn, &the_insn);
1109 case SPECIAL_CASE_FDIV:
1111 int rd = (the_insn.opcode >> 25) & 0x1f;
1113 output_insn (insn, &the_insn);
1115 /* According to information leaked from Sun, the "fdiv" instructions
1116 on early SPARC machines would produce incorrect results sometimes.
1117 The workaround is to add an fmovs of the destination register to
1118 itself just after the instruction. This was true on machines
1119 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1120 assert (the_insn.reloc == BFD_RELOC_NONE);
1121 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1122 output_insn (insn, &the_insn);
1127 as_fatal ("failed special case insn sanity check");
1131 /* Parse an argument that can be expressed as a keyword.
1132 (eg: #StoreStore or %ccfr).
1133 The result is a boolean indicating success.
1134 If successful, INPUT_POINTER is updated. */
1137 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
1138 int (*lookup_fn) PARAMS ((const char *));
1139 char **input_pointerP;
1145 p = *input_pointerP;
1146 for (q = p + (*p == '#' || *p == '%'); isalpha (*q) || *q == '_'; ++q)
1150 value = (*lookup_fn) (p);
1155 *input_pointerP = q;
1159 /* Parse an argument that is a constant expression.
1160 The result is a boolean indicating success. */
1163 parse_const_expr_arg (input_pointerP, valueP)
1164 char **input_pointerP;
1167 char *save = input_line_pointer;
1170 input_line_pointer = *input_pointerP;
1171 /* The next expression may be something other than a constant
1172 (say if we're not processing the right variant of the insn).
1173 Don't call expression unless we're sure it will succeed as it will
1174 signal an error (which we want to defer until later). */
1175 /* FIXME: It might be better to define md_operand and have it recognize
1176 things like %asi, etc. but continuing that route through to the end
1177 is a lot of work. */
1178 if (*input_line_pointer == '%')
1180 input_line_pointer = save;
1184 *input_pointerP = input_line_pointer;
1185 input_line_pointer = save;
1186 if (exp.X_op != O_constant)
1188 *valueP = exp.X_add_number;
1193 sparc_ip (str, pinsn)
1195 const struct sparc_opcode **pinsn;
1197 char *error_message = "";
1201 const struct sparc_opcode *insn;
1203 unsigned long opcode;
1204 unsigned int mask = 0;
1207 long immediate_max = 0;
1210 for (s = str; islower (*s) || (*s >= '0' && *s <= '3'); ++s)
1228 as_fatal ("Unknown opcode: `%s'", str);
1230 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1234 as_bad ("Unknown opcode: `%s'", str);
1245 opcode = insn->match;
1246 memset (&the_insn, '\0', sizeof (the_insn));
1247 the_insn.reloc = BFD_RELOC_NONE;
1251 * Build the opcode, checking as we go to make
1252 * sure that the operands match
1254 for (args = insn->args;; ++args)
1262 /* Parse a series of masks. */
1269 if (! parse_keyword_arg (sparc_encode_membar, &s,
1272 error_message = ": invalid membar mask name";
1276 while (*s == ' ') { ++s; continue; }
1277 if (*s == '|' || *s == '+')
1279 while (*s == ' ') { ++s; continue; }
1284 if (! parse_const_expr_arg (&s, &kmask))
1286 error_message = ": invalid membar mask expression";
1289 if (kmask < 0 || kmask > 127)
1291 error_message = ": invalid membar mask number";
1296 opcode |= MEMBAR (kmask);
1304 /* Parse a prefetch function. */
1307 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1309 error_message = ": invalid prefetch function name";
1315 if (! parse_const_expr_arg (&s, &fcn))
1317 error_message = ": invalid prefetch function expression";
1320 if (fcn < 0 || fcn > 31)
1322 error_message = ": invalid prefetch function number";
1332 /* Parse a sparc64 privileged register. */
1335 struct priv_reg_entry *p = priv_reg_table;
1336 unsigned int len = 9999999; /* init to make gcc happy */
1339 while (p->name[0] > s[0])
1341 while (p->name[0] == s[0])
1343 len = strlen (p->name);
1344 if (strncmp (p->name, s, len) == 0)
1348 if (p->name[0] != s[0])
1350 error_message = ": unrecognizable privileged register";
1354 opcode |= (p->regnum << 14);
1356 opcode |= (p->regnum << 25);
1362 error_message = ": unrecognizable privileged register";
1368 if (strncmp (s, "%asr", 4) == 0)
1376 while (isdigit (*s))
1378 num = num * 10 + *s - '0';
1382 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1384 if (num < 16 || 31 < num)
1386 error_message = ": asr number must be between 16 and 31";
1392 if (num < 0 || 31 < num)
1394 error_message = ": asr number must be between 0 and 31";
1399 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1404 error_message = ": expecting %asrN";
1411 the_insn.reloc = BFD_RELOC_SPARC_11;
1412 immediate_max = 0x03FF;
1416 the_insn.reloc = BFD_RELOC_SPARC_10;
1417 immediate_max = 0x01FF;
1421 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1422 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1423 the_insn.reloc = BFD_RELOC_SPARC_5;
1425 the_insn.reloc = BFD_RELOC_SPARC13;
1426 /* These fields are unsigned, but for upward compatibility,
1427 allow negative values as well. */
1428 immediate_max = 0x1f;
1432 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1433 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1434 the_insn.reloc = BFD_RELOC_SPARC_6;
1436 the_insn.reloc = BFD_RELOC_SPARC13;
1437 /* These fields are unsigned, but for upward compatibility,
1438 allow negative values as well. */
1439 immediate_max = 0x3f;
1443 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1448 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1453 if (*s == 'p' && s[1] == 'n')
1461 if (*s == 'p' && s[1] == 't')
1473 if (strncmp (s, "%icc", 4) == 0)
1485 if (strncmp (s, "%xcc", 4) == 0)
1497 if (strncmp (s, "%fcc0", 5) == 0)
1509 if (strncmp (s, "%fcc1", 5) == 0)
1521 if (strncmp (s, "%fcc2", 5) == 0)
1533 if (strncmp (s, "%fcc3", 5) == 0)
1541 if (strncmp (s, "%pc", 3) == 0)
1549 if (strncmp (s, "%tick", 5) == 0)
1556 case '\0': /* end of args */
1575 case '[': /* these must match exactly */
1583 case '#': /* must be at least one digit */
1586 while (isdigit (*s))
1594 case 'C': /* coprocessor state register */
1595 if (strncmp (s, "%csr", 4) == 0)
1602 case 'b': /* next operand is a coprocessor register */
1605 if (*s++ == '%' && *s++ == 'c' && isdigit (*s))
1610 mask = 10 * (mask - '0') + (*s++ - '0');
1624 opcode |= mask << 14;
1632 opcode |= mask << 25;
1638 case 'r': /* next operand must be a register */
1648 case 'f': /* frame pointer */
1656 case 'g': /* global register */
1657 if (isoctal (c = *s++))
1664 case 'i': /* in register */
1665 if (isoctal (c = *s++))
1667 mask = c - '0' + 24;
1672 case 'l': /* local register */
1673 if (isoctal (c = *s++))
1675 mask = (c - '0' + 16);
1680 case 'o': /* out register */
1681 if (isoctal (c = *s++))
1683 mask = (c - '0' + 8);
1688 case 's': /* stack pointer */
1696 case 'r': /* any register */
1697 if (!isdigit (c = *s++))
1714 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1730 /* Got the register, now figure out where
1731 it goes in the opcode. */
1735 opcode |= mask << 14;
1743 opcode |= mask << 25;
1747 opcode |= (mask << 25) | (mask << 14);
1751 opcode |= (mask << 25) | (mask << 0);
1757 case 'e': /* next operand is a floating point register */
1772 && ((format = *s) == 'f')
1775 for (mask = 0; isdigit (*s); ++s)
1777 mask = 10 * mask + (*s - '0');
1778 } /* read the number */
1786 } /* register must be even numbered */
1794 } /* register must be multiple of 4 */
1798 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1799 error_message = ": There are only 64 f registers; [0-63]";
1801 error_message = ": There are only 32 f registers; [0-31]";
1804 else if (mask >= 32)
1806 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1809 mask -= 31; /* wrap high bit */
1813 error_message = ": There are only 32 f registers; [0-31]";
1821 } /* if not an 'f' register. */
1828 opcode |= RS1 (mask);
1835 opcode |= RS2 (mask);
1841 opcode |= RD (mask);
1850 if (strncmp (s, "%fsr", 4) == 0)
1857 case '0': /* 64 bit immediate (setx insn) */
1858 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1861 case 'h': /* high 22 bits */
1862 the_insn.reloc = BFD_RELOC_HI22;
1865 case 'l': /* 22 bit PC relative immediate */
1866 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
1870 case 'L': /* 30 bit immediate */
1871 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
1875 case 'n': /* 22 bit immediate */
1876 the_insn.reloc = BFD_RELOC_SPARC22;
1879 case 'i': /* 13 bit immediate */
1880 the_insn.reloc = BFD_RELOC_SPARC13;
1881 immediate_max = 0x0FFF;
1890 if ((c = s[1]) == 'h' && s[2] == 'i')
1892 the_insn.reloc = BFD_RELOC_HI22;
1895 else if (c == 'l' && s[2] == 'o')
1897 the_insn.reloc = BFD_RELOC_LO10;
1904 the_insn.reloc = BFD_RELOC_SPARC_HH22;
1912 the_insn.reloc = BFD_RELOC_SPARC_HM10;
1919 /* Note that if the getExpression() fails, we will still
1920 have created U entries in the symbol table for the
1921 'symbols' in the input string. Try not to create U
1922 symbols for registers, etc. */
1924 /* This stuff checks to see if the expression ends in
1925 +%reg. If it does, it removes the register from
1926 the expression, and re-sets 's' to point to the
1931 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
1933 if (s1 != s && isdigit (s1[-1]))
1935 if (s1[-2] == '%' && s1[-3] == '+')
1939 (void) getExpression (s);
1944 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1948 (void) getExpression (s);
1955 (void) getExpression (s);
1958 if (the_insn.exp.X_op == O_constant
1959 && the_insn.exp.X_add_symbol == 0
1960 && the_insn.exp.X_op_symbol == 0)
1962 /* Handle %uhi/%ulo by moving the upper word to the lower
1963 one and pretending it's %hi/%lo. We also need to watch
1964 for %hi/%lo: the top word needs to be zeroed otherwise
1965 fixup_segment will complain the value is too big. */
1966 switch (the_insn.reloc)
1968 case BFD_RELOC_SPARC_HH22:
1969 the_insn.reloc = BFD_RELOC_HI22;
1970 the_insn.exp.X_add_number = BSR (the_insn.exp.X_add_number, 32);
1972 case BFD_RELOC_SPARC_HM10:
1973 the_insn.reloc = BFD_RELOC_LO10;
1974 the_insn.exp.X_add_number = BSR (the_insn.exp.X_add_number, 32);
1976 case BFD_RELOC_HI22:
1977 case BFD_RELOC_LO10:
1978 the_insn.exp.X_add_number &= 0xffffffff;
1984 /* For pc-relative call instructions, we reject
1985 constants to get better code. */
1987 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
1988 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)
1991 error_message = ": PC-relative operand can't be a constant";
1994 /* Check for invalid constant values. Don't warn if
1995 constant was inside %hi or %lo, since these
1996 truncate the constant to fit. */
1997 if (immediate_max != 0
1998 && the_insn.reloc != BFD_RELOC_LO10
1999 && the_insn.reloc != BFD_RELOC_HI22
2000 && !in_signed_range (the_insn.exp.X_add_number,
2005 /* Who knows? After relocation, we may be within
2006 range. Let the linker figure it out. */
2008 the_insn.exp.X_op = O_symbol;
2009 the_insn.exp.X_add_symbol = section_symbol (absolute_section);
2012 /* Immediate value is non-pcrel, and out of
2014 as_bad ("constant value %ld out of range (%ld .. %ld)",
2015 the_insn.exp.X_add_number,
2016 ~immediate_max, immediate_max);
2020 /* Reset to prevent extraneous range check. */
2040 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2042 error_message = ": invalid ASI name";
2048 if (! parse_const_expr_arg (&s, &asi))
2050 error_message = ": invalid ASI expression";
2053 if (asi < 0 || asi > 255)
2055 error_message = ": invalid ASI number";
2059 opcode |= ASI (asi);
2061 } /* alternate space */
2064 if (strncmp (s, "%psr", 4) == 0)
2071 case 'q': /* floating point queue */
2072 if (strncmp (s, "%fq", 3) == 0)
2079 case 'Q': /* coprocessor queue */
2080 if (strncmp (s, "%cq", 3) == 0)
2088 if (strcmp (str, "set") == 0
2089 || strcmp (str, "setuw") == 0)
2091 special_case = SPECIAL_CASE_SET;
2094 else if (strcmp (str, "setsw") == 0)
2096 special_case = SPECIAL_CASE_SETSW;
2099 else if (strcmp (str, "setx") == 0)
2101 special_case = SPECIAL_CASE_SETX;
2104 else if (strncmp (str, "fdiv", 4) == 0)
2106 special_case = SPECIAL_CASE_FDIV;
2112 if (strncmp (s, "%asi", 4) != 0)
2118 if (strncmp (s, "%fprs", 5) != 0)
2124 if (strncmp (s, "%ccr", 4) != 0)
2130 if (strncmp (s, "%tbr", 4) != 0)
2136 if (strncmp (s, "%wim", 4) != 0)
2143 char *push = input_line_pointer;
2146 input_line_pointer = s;
2148 if (e.X_op == O_constant)
2150 int n = e.X_add_number;
2151 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2152 as_bad ("OPF immediate operand out of range (0-0x1ff)");
2154 opcode |= e.X_add_number << 5;
2157 as_bad ("non-immediate OPF operand, ignored");
2158 s = input_line_pointer;
2159 input_line_pointer = push;
2164 if (strncmp (s, "%y", 2) != 0)
2172 /* Parse a sparclet cpreg. */
2174 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2176 error_message = ": invalid cpreg name";
2179 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2184 as_fatal ("failed sanity check.");
2185 } /* switch on arg code */
2187 /* Break out of for() loop. */
2189 } /* for each arg that we expect */
2194 /* Args don't match. */
2195 if (((unsigned) (&insn[1] - sparc_opcodes)) < sparc_num_opcodes
2196 && (insn->name == insn[1].name
2197 || !strcmp (insn->name, insn[1].name)))
2205 as_bad ("Illegal operands%s", error_message);
2211 /* We have a match. Now see if the architecture is ok. */
2212 int needed_arch_mask = insn->architecture;
2216 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2217 | (1 << SPARC_OPCODE_ARCH_V9A));
2218 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2221 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2223 /* Can we bump up the architecture? */
2224 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2226 enum sparc_opcode_arch_val needed_architecture =
2227 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2228 & needed_arch_mask);
2230 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2232 && needed_architecture > warn_after_architecture)
2234 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2235 sparc_opcode_archs[current_architecture].name,
2236 sparc_opcode_archs[needed_architecture].name,
2238 warn_after_architecture = needed_architecture;
2240 current_architecture = needed_architecture;
2243 /* ??? This seems to be a bit fragile. What if the next entry in
2244 the opcode table is the one we want and it is supported?
2245 It is possible to arrange the table today so that this can't
2246 happen but what about tomorrow? */
2249 int arch,printed_one_p = 0;
2251 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2253 /* Create a list of the architectures that support the insn. */
2254 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2256 arch = sparc_ffs (needed_arch_mask);
2257 while ((1 << arch) <= needed_arch_mask)
2259 if ((1 << arch) & needed_arch_mask)
2263 strcpy (p, sparc_opcode_archs[arch].name);
2270 as_bad ("Architecture mismatch on \"%s\".", str);
2271 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2273 sparc_opcode_archs[max_architecture].name);
2279 } /* forever looking for a match */
2281 the_insn.opcode = opcode;
2291 save_in = input_line_pointer;
2292 input_line_pointer = str;
2293 seg = expression (&the_insn.exp);
2294 if (seg != absolute_section
2295 && seg != text_section
2296 && seg != data_section
2297 && seg != bss_section
2298 && seg != undefined_section)
2300 the_insn.error = "bad segment";
2301 expr_end = input_line_pointer;
2302 input_line_pointer = save_in;
2305 expr_end = input_line_pointer;
2306 input_line_pointer = save_in;
2308 } /* getExpression() */
2312 This is identical to the md_atof in m68k.c. I think this is right,
2315 Turn a string in input_line_pointer into a floating point constant of type
2316 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2317 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2320 /* Equal to MAX_PRECISION in atof-ieee.c */
2321 #define MAX_LITTLENUMS 6
2324 md_atof (type, litP, sizeP)
2330 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2361 return "Bad call to MD_ATOF()";
2364 t = atof_ieee (input_line_pointer, type, words);
2366 input_line_pointer = t;
2367 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2369 if (target_big_endian)
2371 for (i = 0; i < prec; i++)
2373 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2374 litP += sizeof (LITTLENUM_TYPE);
2379 for (i = prec - 1; i >= 0; i--)
2381 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2382 litP += sizeof (LITTLENUM_TYPE);
2389 /* Write a value out to the object file, using the appropriate
2393 md_number_to_chars (buf, val, n)
2398 if (target_big_endian)
2399 number_to_chars_bigendian (buf, val, n);
2401 number_to_chars_littleendian (buf, val, n);
2404 /* Apply a fixS to the frags, now that we know the value it ought to
2408 md_apply_fix3 (fixP, value, segment)
2413 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2419 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2421 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2424 /* FIXME: SPARC ELF relocations don't use an addend in the data
2425 field itself. This whole approach should be somehow combined
2426 with the calls to bfd_install_relocation. Also, the value passed
2427 in by fixup_segment includes the value of a defined symbol. We
2428 don't want to include the value of an externally visible symbol. */
2429 if (fixP->fx_addsy != NULL)
2431 if (fixP->fx_addsy->sy_used_in_reloc
2432 && (S_IS_EXTERNAL (fixP->fx_addsy)
2433 || S_IS_WEAK (fixP->fx_addsy)
2434 || (sparc_pic_code && ! fixP->fx_pcrel)
2435 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2436 && ((bfd_get_section_flags (stdoutput,
2437 S_GET_SEGMENT (fixP->fx_addsy))
2438 & SEC_LINK_ONCE) != 0
2439 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2441 sizeof ".gnu.linkonce" - 1) == 0)))
2442 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2443 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2444 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2445 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2450 /* This is a hack. There should be a better way to
2451 handle this. Probably in terms of howto fields, once
2452 we can look at these fixups in terms of howtos. */
2453 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2454 val += fixP->fx_where + fixP->fx_frag->fr_address;
2457 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2458 generate a reloc, then we just want to let the reloc addend set
2459 the value. We do not want to also stuff the addend into the
2460 object file. Including the addend in the object file works when
2461 doing a static link, because the linker will ignore the object
2462 file contents. However, the dynamic linker does not ignore the
2463 object file contents. */
2464 if (fixP->fx_addsy != NULL
2465 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2468 /* When generating PIC code, we do not want an addend for a reloc
2469 against a local symbol. We adjust fx_addnumber to cancel out the
2470 value already included in val, and to also cancel out the
2471 adjustment which bfd_install_relocation will create. */
2473 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2474 && fixP->fx_addsy != NULL
2475 && ! S_IS_COMMON (fixP->fx_addsy)
2476 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2477 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2480 /* If this is a data relocation, just output VAL. */
2482 if (fixP->fx_r_type == BFD_RELOC_16)
2484 md_number_to_chars (buf, val, 2);
2486 else if (fixP->fx_r_type == BFD_RELOC_32)
2488 md_number_to_chars (buf, val, 4);
2490 else if (fixP->fx_r_type == BFD_RELOC_64)
2492 md_number_to_chars (buf, val, 8);
2496 /* It's a relocation against an instruction. */
2498 if (INSN_BIG_ENDIAN)
2499 insn = bfd_getb32 ((unsigned char *) buf);
2501 insn = bfd_getl32 ((unsigned char *) buf);
2503 switch (fixP->fx_r_type)
2505 case BFD_RELOC_32_PCREL_S2:
2507 /* FIXME: This increment-by-one deserves a comment of why it's
2509 if (! sparc_pic_code
2510 || fixP->fx_addsy == NULL
2511 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2513 insn |= val & 0x3fffffff;
2516 case BFD_RELOC_SPARC_11:
2517 if (! in_signed_range (val, 0x7ff))
2518 as_bad ("relocation overflow.");
2519 insn |= val & 0x7ff;
2522 case BFD_RELOC_SPARC_10:
2523 if (! in_signed_range (val, 0x3ff))
2524 as_bad ("relocation overflow.");
2525 insn |= val & 0x3ff;
2528 case BFD_RELOC_SPARC_6:
2529 if (! in_bitfield_range (val, 0x3f))
2530 as_bad ("relocation overflow.");
2534 case BFD_RELOC_SPARC_5:
2535 if (! in_bitfield_range (val, 0x1f))
2536 as_bad ("relocation overflow.");
2540 case BFD_RELOC_SPARC_WDISP16:
2541 /* FIXME: simplify */
2542 if (((val > 0) && (val & ~0x3fffc))
2543 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2544 as_bad ("relocation overflow.");
2545 /* FIXME: The +1 deserves a comment. */
2546 val = (val >> 2) + 1;
2547 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2550 case BFD_RELOC_SPARC_WDISP19:
2551 /* FIXME: simplify */
2552 if (((val > 0) && (val & ~0x1ffffc))
2553 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2554 as_bad ("relocation overflow.");
2555 /* FIXME: The +1 deserves a comment. */
2556 val = (val >> 2) + 1;
2557 insn |= val & 0x7ffff;
2560 case BFD_RELOC_SPARC_HH22:
2561 val = BSR (val, 32);
2562 /* intentional fallthrough */
2564 case BFD_RELOC_SPARC_LM22:
2565 case BFD_RELOC_HI22:
2566 if (!fixP->fx_addsy)
2568 insn |= (val >> 10) & 0x3fffff;
2572 /* FIXME: Need comment explaining why we do this. */
2577 case BFD_RELOC_SPARC22:
2578 if (val & ~0x003fffff)
2579 as_bad ("relocation overflow");
2580 insn |= (val & 0x3fffff);
2583 case BFD_RELOC_SPARC_HM10:
2584 val = BSR (val, 32);
2585 /* intentional fallthrough */
2587 case BFD_RELOC_LO10:
2588 if (!fixP->fx_addsy)
2590 insn |= val & 0x3ff;
2594 /* FIXME: Need comment explaining why we do this. */
2599 case BFD_RELOC_SPARC13:
2600 if (! in_signed_range (val, 0x1fff))
2601 as_bad ("relocation overflow");
2602 insn |= val & 0x1fff;
2605 case BFD_RELOC_SPARC_WDISP22:
2606 val = (val >> 2) + 1;
2608 case BFD_RELOC_SPARC_BASE22:
2609 insn |= val & 0x3fffff;
2612 case BFD_RELOC_NONE:
2614 as_bad ("bad or unhandled relocation type: 0x%02x", fixP->fx_r_type);
2618 if (INSN_BIG_ENDIAN)
2619 bfd_putb32 (insn, (unsigned char *) buf);
2621 bfd_putl32 (insn, (unsigned char *) buf);
2624 /* Are we finished with this relocation now? */
2625 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2631 /* Translate internal representation of relocation info to BFD target
2634 tc_gen_reloc (section, fixp)
2639 bfd_reloc_code_real_type code;
2641 reloc = (arelent *) xmalloc (sizeof (arelent));
2643 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2644 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2646 switch (fixp->fx_r_type)
2650 case BFD_RELOC_HI22:
2651 case BFD_RELOC_LO10:
2652 case BFD_RELOC_32_PCREL_S2:
2653 case BFD_RELOC_SPARC13:
2654 case BFD_RELOC_SPARC_BASE13:
2655 case BFD_RELOC_SPARC_WDISP16:
2656 case BFD_RELOC_SPARC_WDISP19:
2657 case BFD_RELOC_SPARC_WDISP22:
2659 case BFD_RELOC_SPARC_5:
2660 case BFD_RELOC_SPARC_6:
2661 case BFD_RELOC_SPARC_10:
2662 case BFD_RELOC_SPARC_11:
2663 case BFD_RELOC_SPARC_HH22:
2664 case BFD_RELOC_SPARC_HM10:
2665 case BFD_RELOC_SPARC_LM22:
2666 case BFD_RELOC_SPARC_PC_HH22:
2667 case BFD_RELOC_SPARC_PC_HM10:
2668 case BFD_RELOC_SPARC_PC_LM22:
2669 code = fixp->fx_r_type;
2675 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2676 /* If we are generating PIC code, we need to generate a different
2680 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2682 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2689 case BFD_RELOC_32_PCREL_S2:
2690 if (! S_IS_DEFINED (fixp->fx_addsy)
2691 || S_IS_COMMON (fixp->fx_addsy)
2692 || S_IS_EXTERNAL (fixp->fx_addsy)
2693 || S_IS_WEAK (fixp->fx_addsy))
2694 code = BFD_RELOC_SPARC_WPLT30;
2696 case BFD_RELOC_HI22:
2697 if (fixp->fx_addsy != NULL
2698 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2699 code = BFD_RELOC_SPARC_PC22;
2701 code = BFD_RELOC_SPARC_GOT22;
2703 case BFD_RELOC_LO10:
2704 if (fixp->fx_addsy != NULL
2705 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2706 code = BFD_RELOC_SPARC_PC10;
2708 code = BFD_RELOC_SPARC_GOT10;
2710 case BFD_RELOC_SPARC13:
2711 code = BFD_RELOC_SPARC_GOT13;
2717 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2719 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2720 if (reloc->howto == 0)
2722 as_bad_where (fixp->fx_file, fixp->fx_line,
2723 "internal error: can't export reloc type %d (`%s')",
2724 fixp->fx_r_type, bfd_get_reloc_code_name (code));
2728 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2731 if (reloc->howto->pc_relative == 0
2732 || code == BFD_RELOC_SPARC_PC10
2733 || code == BFD_RELOC_SPARC_PC22)
2734 reloc->addend = fixp->fx_addnumber;
2736 reloc->addend = fixp->fx_offset - reloc->address;
2738 #else /* elf or coff */
2740 if (reloc->howto->pc_relative == 0
2741 || code == BFD_RELOC_SPARC_PC10
2742 || code == BFD_RELOC_SPARC_PC22)
2743 reloc->addend = fixp->fx_addnumber;
2744 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2745 reloc->addend = (section->vma
2746 + fixp->fx_addnumber
2747 + md_pcrel_from (fixp));
2749 reloc->addend = fixp->fx_offset;
2757 /* for debugging only */
2760 struct sparc_it *insn;
2762 const char *const Reloc[] = {
2791 fprintf (stderr, "ERROR: %s\n");
2792 fprintf (stderr, "opcode=0x%08x\n", insn->opcode);
2793 fprintf (stderr, "reloc = %s\n", Reloc[insn->reloc]);
2794 fprintf (stderr, "exp = {\n");
2795 fprintf (stderr, "\t\tX_add_symbol = %s\n",
2796 ((insn->exp.X_add_symbol != NULL)
2797 ? ((S_GET_NAME (insn->exp.X_add_symbol) != NULL)
2798 ? S_GET_NAME (insn->exp.X_add_symbol)
2801 fprintf (stderr, "\t\tX_sub_symbol = %s\n",
2802 ((insn->exp.X_op_symbol != NULL)
2803 ? (S_GET_NAME (insn->exp.X_op_symbol)
2804 ? S_GET_NAME (insn->exp.X_op_symbol)
2807 fprintf (stderr, "\t\tX_add_number = %d\n",
2808 insn->exp.X_add_number);
2809 fprintf (stderr, "}\n");
2815 * Invocation line includes a switch not recognized by the base assembler.
2816 * See if it's a processor-specific option. These are:
2819 * Warn on architecture bumps. See also -A.
2821 * -Av6, -Av7, -Av8, -Av9, -Av9a, -Asparclite
2822 * -xarch=v8plus, -xarch=v8plusa
2823 * Select the architecture. Instructions or features not
2824 * supported by the selected architecture cause fatal errors.
2826 * The default is to start at v6, and bump the architecture up
2827 * whenever an instruction is seen at a higher level. If 32 bit
2828 * environments, v9 is not bumped up to, the user must pass -Av9.
2830 * -xarch=v8plus{,a} is for compatibility with the Sun assembler.
2832 * If -bump is specified, a warning is printing when bumping to
2835 * If an architecture is specified, all instructions must match
2836 * that architecture. Any higher level instructions are flagged
2837 * as errors. Note that in the 32 bit environment specifying
2838 * -Av9 does not automatically create a v9 object file, a v9
2839 * insn must be seen.
2841 * If both an architecture and -bump are specified, the
2842 * architecture starts at the specified level, but bumps are
2843 * warnings. Note that we can't set `current_architecture' to
2844 * the requested level in this case: in the 32 bit environment,
2845 * we still must avoid creating v9 object files unless v9 insns
2849 * Bumping between incompatible architectures is always an
2850 * error. For example, from sparclite to v9.
2854 CONST char *md_shortopts = "A:K:VQ:sq";
2857 CONST char *md_shortopts = "A:k";
2859 CONST char *md_shortopts = "A:";
2862 struct option md_longopts[] = {
2863 #define OPTION_BUMP (OPTION_MD_BASE)
2864 {"bump", no_argument, NULL, OPTION_BUMP},
2865 #define OPTION_SPARC (OPTION_MD_BASE + 1)
2866 {"sparc", no_argument, NULL, OPTION_SPARC},
2867 #define OPTION_XARCH (OPTION_MD_BASE + 2)
2868 {"xarch", required_argument, NULL, OPTION_XARCH},
2869 #ifdef SPARC_BIENDIAN
2870 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
2871 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
2872 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
2873 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
2875 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
2876 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
2877 {NULL, no_argument, NULL, 0}
2879 size_t md_longopts_size = sizeof(md_longopts);
2882 md_parse_option (c, arg)
2890 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
2894 /* ??? We could add v8plus and v8plusa to sparc_opcode_archs.
2895 But we might want v8plus to mean something different than v9
2896 someday, and we'd recognize more -xarch options than Sun's
2897 assembler does (which may lead to a conflict someday). */
2898 if (strcmp (arg, "v8plus") == 0)
2900 else if (strcmp (arg, "v8plusa") == 0)
2904 as_bad ("invalid architecture -xarch=%s", arg);
2912 enum sparc_opcode_arch_val new_arch = sparc_opcode_lookup_arch (arg);
2914 if (new_arch == SPARC_OPCODE_ARCH_BAD)
2916 as_bad ("invalid architecture -A%s", arg);
2921 max_architecture = new_arch;
2922 architecture_requested = 1;
2928 /* Ignore -sparc, used by SunOS make default .s.o rule. */
2931 case OPTION_ENFORCE_ALIGNED_DATA:
2932 enforce_aligned_data = 1;
2935 #ifdef SPARC_BIENDIAN
2936 case OPTION_LITTLE_ENDIAN:
2937 target_big_endian = 0;
2939 case OPTION_BIG_ENDIAN:
2940 target_big_endian = 1;
2952 print_version_id ();
2956 /* Qy - do emit .comment
2957 Qn - do not emit .comment */
2961 /* use .stab instead of .stab.excl */
2965 /* quick -- native assembler does fewer checks */
2969 if (strcmp (arg, "PIC") != 0)
2970 as_warn ("Unrecognized option following -K");
2984 md_show_usage (stream)
2987 const struct sparc_opcode_arch *arch;
2989 fprintf(stream, "SPARC options:\n");
2990 for (arch = &sparc_opcode_archs[0]; arch->name; arch++)
2992 if (arch != &sparc_opcode_archs[0])
2993 fprintf (stream, " | ");
2994 fprintf (stream, "-A%s", arch->name);
2996 fprintf (stream, "\n-xarch=v8plus | -xarch=v8plusa\n");
2998 specify variant of SPARC architecture\n\
2999 -bump warn when assembler switches architectures\n\
3001 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
3004 -k generate PIC\n");
3008 -KPIC generate PIC\n\
3009 -V print assembler version number\n\
3014 #ifdef SPARC_BIENDIAN
3016 -EL generate code for a little endian machine\n\
3017 -EB generate code for a big endian machine\n");
3021 /* We have no need to default values of symbols. */
3025 md_undefined_symbol (name)
3029 } /* md_undefined_symbol() */
3031 /* Round up a section size to the appropriate boundary. */
3033 md_section_align (segment, size)
3038 /* This is not right for ELF; a.out wants it, and COFF will force
3039 the alignment anyways. */
3040 valueT align = ((valueT) 1
3041 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3043 /* turn alignment value into a mask */
3045 newsize = (size + align) & ~align;
3052 /* Exactly what point is a PC-relative offset relative TO?
3053 On the sparc, they're relative to the address of the offset, plus
3054 its size. This gets us to the following instruction.
3055 (??? Is this right? FIXME-SOON) */
3057 md_pcrel_from (fixP)
3062 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3063 if (! sparc_pic_code
3064 || fixP->fx_addsy == NULL
3065 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
3066 ret += fixP->fx_size;
3070 /* end of tc-sparc.c */