1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
51 #define DEFAULT_ARCH "sparclite"
53 static char *default_arch = DEFAULT_ARCH;
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
57 static int default_init_p;
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
76 /* The currently selected v9 memory model. Currently only used for
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
87 static int hwcap_allowed;
89 static int architecture_requested;
90 static int warn_on_bump;
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
103 /* Non-zero if we are generating PIC code. */
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
109 extern int target_big_endian;
111 static int target_little_endian_data;
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
141 static void s_register (int);
144 const pseudo_typeS md_pseudo_table[] =
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
154 {"reserve", s_reserve, 0},
156 {"skip", s_space, 0},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
187 const char line_separator_chars[] = ";";
189 /* Chars that can be used to separate mant from exp in floating point
191 const char EXP_CHARS[] = "eE";
193 /* Chars that mean this number is a floating point constant.
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
207 unsigned long opcode;
208 struct nlist *nlistp;
212 bfd_reloc_code_real_type reloc;
215 struct sparc_it the_insn, set_insn;
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
224 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
227 static struct sparc_arch {
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
248 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
249 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
250 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
254 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
255 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
256 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
257 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
258 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
259 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
260 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
261 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
262 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
263 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
264 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
265 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
266 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
269 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
270 { NULL, NULL, v8, 0, 0, 0 }
273 /* Variant of default_arch */
274 static enum sparc_arch_types default_arch_type;
276 static struct sparc_arch *
277 lookup_arch (char *name)
279 struct sparc_arch *sa;
281 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
282 if (strcmp (sa->name, name) == 0)
284 if (sa->name == NULL)
289 /* Initialize the default opcode arch and word size from the default
290 architecture name. */
293 init_default_arch (void)
295 struct sparc_arch *sa = lookup_arch (default_arch);
298 || sa->default_arch_size == 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
301 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
302 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size = sparc_arch_size = sa->default_arch_size;
306 default_arch_type = sa->arch_type;
309 /* Called by TARGET_FORMAT. */
312 sparc_target_format (void)
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p)
317 init_default_arch ();
321 return "a.out-sparc-netbsd";
324 if (target_big_endian)
325 return "a.out-sunos-big";
326 else if (default_arch_type == sparc86x && target_little_endian_data)
327 return "a.out-sunos-big";
329 return "a.out-sparc-little";
331 return "a.out-sunos-big";
342 return "coff-sparc-lynx";
349 return "elf32-sparc-vxworks";
353 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
364 * Warn on architecture bumps. See also -A.
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
392 * If -bump is specified, a warning is printing when bumping to
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
414 const char *md_shortopts = "A:K:VQ:sq";
417 const char *md_shortopts = "A:k";
419 const char *md_shortopts = "A:";
422 struct option md_longopts[] = {
423 #define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument, NULL, OPTION_BUMP},
425 #define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument, NULL, OPTION_SPARC},
427 #define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument, NULL, OPTION_XARCH},
430 #define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument, NULL, OPTION_32},
432 #define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument, NULL, OPTION_64},
434 #define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument, NULL, OPTION_TSO},
436 #define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument, NULL, OPTION_PSO},
438 #define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument, NULL, OPTION_RMO},
441 #ifdef SPARC_BIENDIAN
442 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
444 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
447 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
449 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
452 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
454 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
457 #define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument, NULL, OPTION_RELAX},
459 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
461 {NULL, no_argument, NULL, 0}
464 size_t md_longopts_size = sizeof (md_longopts);
467 md_parse_option (int c, char *arg)
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p)
472 init_default_arch ();
478 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
483 if (strncmp (arg, "v9", 2) != 0)
484 md_parse_option (OPTION_32, NULL);
486 md_parse_option (OPTION_64, NULL);
492 struct sparc_arch *sa;
493 enum sparc_opcode_arch_val opcode_arch;
495 sa = lookup_arch (arg);
497 || ! sa->user_option_p)
499 if (c == OPTION_XARCH)
500 as_bad (_("invalid architecture -xarch=%s"), arg);
502 as_bad (_("invalid architecture -A%s"), arg);
506 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
507 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
508 as_fatal (_("Bad opcode table, broken assembler."));
510 if (!architecture_requested
511 || opcode_arch > max_architecture)
512 max_architecture = opcode_arch;
513 hwcap_allowed |= sa->hwcap_allowed;
514 architecture_requested = 1;
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
522 case OPTION_ENFORCE_ALIGNED_DATA:
523 enforce_aligned_data = 1;
526 #ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN:
528 target_big_endian = 0;
529 if (default_arch_type != sparclet)
530 as_fatal ("This target does not support -EL");
532 case OPTION_LITTLE_ENDIAN_DATA:
533 target_little_endian_data = 1;
534 target_big_endian = 0;
535 if (default_arch_type != sparc86x
536 && default_arch_type != v9)
537 as_fatal ("This target does not support --little-endian-data");
539 case OPTION_BIG_ENDIAN:
540 target_big_endian = 1;
554 const char **list, **l;
556 sparc_arch_size = c == OPTION_32 ? 32 : 64;
557 list = bfd_target_list ();
558 for (l = list; *l != NULL; l++)
560 if (sparc_arch_size == 32)
562 if (CONST_STRNEQ (*l, "elf32-sparc"))
567 if (CONST_STRNEQ (*l, "elf64-sparc"))
572 as_fatal (_("No compiled in support for %d bit object file format"),
576 if (sparc_arch_size == 64
577 && max_architecture < SPARC_OPCODE_ARCH_V9)
578 max_architecture = SPARC_OPCODE_ARCH_V9;
583 sparc_memory_model = MM_TSO;
587 sparc_memory_model = MM_PSO;
591 sparc_memory_model = MM_RMO;
599 /* Qy - do emit .comment
600 Qn - do not emit .comment. */
604 /* Use .stab instead of .stab.excl. */
608 /* quick -- Native assembler does fewer checks. */
612 if (strcmp (arg, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
618 case OPTION_NO_UNDECLARED_REGS:
619 no_undeclared_regs = 1;
622 case OPTION_UNDECLARED_REGS:
623 no_undeclared_regs = 0;
631 case OPTION_NO_RELAX:
643 md_show_usage (FILE *stream)
645 const struct sparc_arch *arch;
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p)
651 init_default_arch ();
653 fprintf (stream, _("SPARC options:\n"));
655 for (arch = &sparc_arch_table[0]; arch->name; arch++)
657 if (!arch->user_option_p)
659 if (arch != &sparc_arch_table[0])
660 fprintf (stream, " | ");
661 if (column + strlen (arch->name) > 70)
664 fputc ('\n', stream);
666 column += 5 + 2 + strlen (arch->name);
667 fprintf (stream, "-A%s", arch->name);
669 for (arch = &sparc_arch_table[0]; arch->name; arch++)
671 if (!arch->user_option_p)
673 fprintf (stream, " | ");
674 if (column + strlen (arch->name) > 65)
677 fputc ('\n', stream);
679 column += 5 + 7 + strlen (arch->name);
680 fprintf (stream, "-xarch=%s", arch->name);
682 fprintf (stream, _("\n\
683 specify variant of SPARC architecture\n\
684 -bump warn when assembler switches architectures\n\
686 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
687 -relax relax jumps and branches (default)\n\
688 -no-relax avoid changing any jumps and branches\n"));
690 fprintf (stream, _("\
691 -k generate PIC\n"));
694 fprintf (stream, _("\
695 -32 create 32 bit object file\n\
696 -64 create 64 bit object file\n"));
697 fprintf (stream, _("\
698 [default is %d]\n"), default_arch_size);
699 fprintf (stream, _("\
700 -TSO use Total Store Ordering\n\
701 -PSO use Partial Store Ordering\n\
702 -RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream, _("\
704 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
705 fprintf (stream, _("\
706 -KPIC generate PIC\n\
707 -V print assembler version number\n\
708 -undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710 -no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
716 #ifdef SPARC_BIENDIAN
717 fprintf (stream, _("\
718 -EL generate code for a little endian machine\n\
719 -EB generate code for a big endian machine\n\
720 --little-endian-data generate code for a machine having big endian\n\
721 instructions and little endian data.\n"));
725 /* Native operand size opcode translation. */
731 } native_op_table[] =
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
746 /* sparc64 privileged and hyperprivileged registers. */
748 struct priv_reg_entry
754 struct priv_reg_entry priv_reg_table[] =
774 {"", -1}, /* End marker. */
777 struct priv_reg_entry hpriv_reg_table[] =
785 {"", -1}, /* End marker. */
788 /* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
791 struct priv_reg_entry v9a_asr_table[] =
794 {"sys_tick_cmpr", 25},
798 {"softint_clear", 21},
807 {"clear_softint", 21},
808 {"", -1}, /* End marker. */
812 cmp_reg_entry (const void *parg, const void *qarg)
814 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
815 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
817 return strcmp (q->name, p->name);
820 /* This function is called once, at assembler startup time. It should
821 set up all the tables, etc. that the MD part of the assembler will
827 register const char *retval = NULL;
829 register unsigned int i = 0;
831 /* We don't get a chance to initialize anything before md_parse_option
832 is called, and it may not be called, so handle default initialization
833 now if not already done. */
834 if (! default_init_p)
835 init_default_arch ();
837 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
838 op_hash = hash_new ();
840 while (i < (unsigned int) sparc_num_opcodes)
842 const char *name = sparc_opcodes[i].name;
843 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
846 as_bad (_("Internal error: can't hash `%s': %s\n"),
847 sparc_opcodes[i].name, retval);
852 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
854 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
855 sparc_opcodes[i].name, sparc_opcodes[i].args);
860 while (i < (unsigned int) sparc_num_opcodes
861 && !strcmp (sparc_opcodes[i].name, name));
864 for (i = 0; native_op_table[i].name; i++)
866 const struct sparc_opcode *insn;
867 char *name = ((sparc_arch_size == 32)
868 ? native_op_table[i].name32
869 : native_op_table[i].name64);
870 insn = (struct sparc_opcode *) hash_find (op_hash, name);
873 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
874 name, native_op_table[i].name);
879 retval = hash_insert (op_hash, native_op_table[i].name,
883 as_bad (_("Internal error: can't hash `%s': %s\n"),
884 sparc_opcodes[i].name, retval);
891 as_fatal (_("Broken assembler. No assembly attempted."));
893 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
894 sizeof (priv_reg_table[0]), cmp_reg_entry);
896 /* If -bump, record the architecture level at which we start issuing
897 warnings. The behaviour is different depending upon whether an
898 architecture was explicitly specified. If it wasn't, we issue warnings
899 for all upwards bumps. If it was, we don't start issuing warnings until
900 we need to bump beyond the requested architecture or when we bump between
901 conflicting architectures. */
904 && architecture_requested)
906 /* `max_architecture' records the requested architecture.
907 Issue warnings if we go above it. */
908 warn_after_architecture = max_architecture;
910 /* Find the highest architecture level that doesn't conflict with
911 the requested one. */
912 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
913 max_architecture > warn_after_architecture;
915 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
916 warn_after_architecture))
921 /* Called after all assembly has been done. */
926 unsigned long mach = bfd_mach_sparc;
928 if (sparc_arch_size == 64)
929 switch (current_architecture)
931 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
932 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
933 default: mach = bfd_mach_sparc_v9; break;
936 switch (current_architecture)
938 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
939 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
940 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
941 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
942 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
943 be but for now it is (since that's the way it's always been
947 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
949 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
951 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
955 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
958 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
962 /* Sign-extend the value from the architecture word size, so that
963 0xffffffff is always considered -1 on sparc32. */
964 if (sparc_arch_size == 32)
966 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
967 val = ((val & U0xffffffff) ^ sign) - sign;
976 /* Return non-zero if VAL is in the range 0 to MAX. */
979 in_unsigned_range (bfd_vma val, bfd_vma max)
986 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
987 (e.g. -15 to +31). */
990 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
996 if (val < ~(max >> 1))
1002 sparc_ffs (unsigned int mask)
1009 for (i = 0; (mask & 1) == 0; ++i)
1014 /* Implement big shift right. */
1016 BSR (bfd_vma val, int amount)
1018 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1019 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1020 return val >> amount;
1023 /* For communication between sparc_ip and get_expression. */
1024 static char *expr_end;
1026 /* Values for `special_case'.
1027 Instructions that require wierd handling because they're longer than
1029 #define SPECIAL_CASE_NONE 0
1030 #define SPECIAL_CASE_SET 1
1031 #define SPECIAL_CASE_SETSW 2
1032 #define SPECIAL_CASE_SETX 3
1033 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1034 #define SPECIAL_CASE_FDIV 4
1036 /* Bit masks of various insns. */
1037 #define NOP_INSN 0x01000000
1038 #define OR_INSN 0x80100000
1039 #define XOR_INSN 0x80180000
1040 #define FMOVS_INSN 0x81A00020
1041 #define SETHI_INSN 0x01000000
1042 #define SLLX_INSN 0x81281000
1043 #define SRA_INSN 0x81380000
1045 /* The last instruction to be assembled. */
1046 static const struct sparc_opcode *last_insn;
1047 /* The assembled opcode of `last_insn'. */
1048 static unsigned long last_opcode;
1050 /* Handle the set and setuw synthetic instructions. */
1053 synthetize_setuw (const struct sparc_opcode *insn)
1055 int need_hi22_p = 0;
1056 int rd = (the_insn.opcode & RD (~0)) >> 25;
1058 if (the_insn.exp.X_op == O_constant)
1060 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1062 if (sizeof (offsetT) > 4
1063 && (the_insn.exp.X_add_number < 0
1064 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1065 as_warn (_("set: number not in 0..4294967295 range"));
1069 if (sizeof (offsetT) > 4
1070 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1071 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1072 as_warn (_("set: number not in -2147483648..4294967295 range"));
1073 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1077 /* See if operand is absolute and small; skip sethi if so. */
1078 if (the_insn.exp.X_op != O_constant
1079 || the_insn.exp.X_add_number >= (1 << 12)
1080 || the_insn.exp.X_add_number < -(1 << 12))
1082 the_insn.opcode = (SETHI_INSN | RD (rd)
1083 | ((the_insn.exp.X_add_number >> 10)
1084 & (the_insn.exp.X_op == O_constant
1086 the_insn.reloc = (the_insn.exp.X_op != O_constant
1087 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1088 output_insn (insn, &the_insn);
1092 /* See if operand has no low-order bits; skip OR if so. */
1093 if (the_insn.exp.X_op != O_constant
1094 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1097 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1099 | (the_insn.exp.X_add_number
1100 & (the_insn.exp.X_op != O_constant
1101 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1102 the_insn.reloc = (the_insn.exp.X_op != O_constant
1103 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1104 output_insn (insn, &the_insn);
1108 /* Handle the setsw synthetic instruction. */
1111 synthetize_setsw (const struct sparc_opcode *insn)
1115 rd = (the_insn.opcode & RD (~0)) >> 25;
1117 if (the_insn.exp.X_op != O_constant)
1119 synthetize_setuw (insn);
1121 /* Need to sign extend it. */
1122 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1123 the_insn.reloc = BFD_RELOC_NONE;
1124 output_insn (insn, &the_insn);
1128 if (sizeof (offsetT) > 4
1129 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1130 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1131 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1133 low32 = the_insn.exp.X_add_number;
1137 synthetize_setuw (insn);
1143 the_insn.reloc = BFD_RELOC_NONE;
1144 /* See if operand is absolute and small; skip sethi if so. */
1145 if (low32 < -(1 << 12))
1147 the_insn.opcode = (SETHI_INSN | RD (rd)
1148 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1149 output_insn (insn, &the_insn);
1150 low32 = 0x1c00 | (low32 & 0x3ff);
1151 opc = RS1 (rd) | XOR_INSN;
1154 the_insn.opcode = (opc | RD (rd) | IMMED
1155 | (low32 & 0x1fff));
1156 output_insn (insn, &the_insn);
1159 /* Handle the setsw synthetic instruction. */
1162 synthetize_setx (const struct sparc_opcode *insn)
1164 int upper32, lower32;
1165 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1166 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1168 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1169 int need_xor10_p = 0;
1171 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1172 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1173 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1176 upper_dstreg = tmpreg;
1177 /* The tmp reg should not be the dst reg. */
1178 if (tmpreg == dstreg)
1179 as_warn (_("setx: temporary register same as destination register"));
1181 /* ??? Obviously there are other optimizations we can do
1182 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1183 doing some of these. Later. If you do change things, try to
1184 change all of this to be table driven as well. */
1185 /* What to output depends on the number if it's constant.
1186 Compute that first, then output what we've decided upon. */
1187 if (the_insn.exp.X_op != O_constant)
1189 if (sparc_arch_size == 32)
1191 /* When arch size is 32, we want setx to be equivalent
1192 to setuw for anything but constants. */
1193 the_insn.exp.X_add_number &= 0xffffffff;
1194 synthetize_setuw (insn);
1197 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1203 /* Reset X_add_number, we've extracted it as upper32/lower32.
1204 Otherwise fixup_segment will complain about not being able to
1205 write an 8 byte number in a 4 byte field. */
1206 the_insn.exp.X_add_number = 0;
1208 /* Only need hh22 if `or' insn can't handle constant. */
1209 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1212 /* Does bottom part (after sethi) have bits? */
1213 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1214 /* No hh22, but does upper32 still have bits we can't set
1216 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1219 /* If the lower half is all zero, we build the upper half directly
1220 into the dst reg. */
1222 /* Need lower half if number is zero or 0xffffffff00000000. */
1223 || (! need_hh22_p && ! need_hm10_p))
1225 /* No need for sethi if `or' insn can handle constant. */
1226 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1227 /* Note that we can't use a negative constant in the `or'
1228 insn unless the upper 32 bits are all ones. */
1229 || (lower32 < 0 && upper32 != -1)
1230 || (lower32 >= 0 && upper32 == -1))
1233 if (need_hi22_p && upper32 == -1)
1236 /* Does bottom part (after sethi) have bits? */
1237 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1239 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1240 /* Need `or' if we didn't set anything else. */
1241 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1245 /* Output directly to dst reg if lower 32 bits are all zero. */
1246 upper_dstreg = dstreg;
1249 if (!upper_dstreg && dstreg)
1250 as_warn (_("setx: illegal temporary register g0"));
1254 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1255 | ((upper32 >> 10) & 0x3fffff));
1256 the_insn.reloc = (the_insn.exp.X_op != O_constant
1257 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1258 output_insn (insn, &the_insn);
1263 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1264 | (((need_xor10_p ? ~lower32 : lower32)
1265 >> 10) & 0x3fffff));
1266 the_insn.reloc = (the_insn.exp.X_op != O_constant
1267 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1268 output_insn (insn, &the_insn);
1273 the_insn.opcode = (OR_INSN
1274 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1277 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1278 the_insn.reloc = (the_insn.exp.X_op != O_constant
1279 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1280 output_insn (insn, &the_insn);
1285 /* FIXME: One nice optimization to do here is to OR the low part
1286 with the highpart if hi22 isn't needed and the low part is
1288 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1291 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1292 the_insn.reloc = (the_insn.exp.X_op != O_constant
1293 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1294 output_insn (insn, &the_insn);
1297 /* If we needed to build the upper part, shift it into place. */
1298 if (need_hh22_p || need_hm10_p)
1300 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1302 the_insn.reloc = BFD_RELOC_NONE;
1303 output_insn (insn, &the_insn);
1306 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1309 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1310 | 0x1c00 | (lower32 & 0x3ff));
1311 the_insn.reloc = BFD_RELOC_NONE;
1312 output_insn (insn, &the_insn);
1315 /* If we needed to build both upper and lower parts, OR them together. */
1316 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1318 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1320 the_insn.reloc = BFD_RELOC_NONE;
1321 output_insn (insn, &the_insn);
1325 /* Main entry point to assemble one instruction. */
1328 md_assemble (char *str)
1330 const struct sparc_opcode *insn;
1334 special_case = sparc_ip (str, &insn);
1338 /* We warn about attempts to put a floating point branch in a delay slot,
1339 unless the delay slot has been annulled. */
1340 if (last_insn != NULL
1341 && (insn->flags & F_FBR) != 0
1342 && (last_insn->flags & F_DELAYED) != 0
1343 /* ??? This test isn't completely accurate. We assume anything with
1344 F_{UNBR,CONDBR,FBR} set is annullable. */
1345 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1346 || (last_opcode & ANNUL) == 0))
1347 as_warn (_("FP branch in delay slot"));
1349 /* SPARC before v9 requires a nop instruction between a floating
1350 point instruction and a floating point branch. We insert one
1351 automatically, with a warning. */
1352 if (max_architecture < SPARC_OPCODE_ARCH_V9
1353 && last_insn != NULL
1354 && (insn->flags & F_FBR) != 0
1355 && (last_insn->flags & F_FLOAT) != 0)
1357 struct sparc_it nop_insn;
1359 nop_insn.opcode = NOP_INSN;
1360 nop_insn.reloc = BFD_RELOC_NONE;
1361 output_insn (insn, &nop_insn);
1362 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1365 switch (special_case)
1367 case SPECIAL_CASE_NONE:
1369 output_insn (insn, &the_insn);
1372 case SPECIAL_CASE_SETSW:
1373 synthetize_setsw (insn);
1376 case SPECIAL_CASE_SET:
1377 synthetize_setuw (insn);
1380 case SPECIAL_CASE_SETX:
1381 synthetize_setx (insn);
1384 case SPECIAL_CASE_FDIV:
1386 int rd = (the_insn.opcode >> 25) & 0x1f;
1388 output_insn (insn, &the_insn);
1390 /* According to information leaked from Sun, the "fdiv" instructions
1391 on early SPARC machines would produce incorrect results sometimes.
1392 The workaround is to add an fmovs of the destination register to
1393 itself just after the instruction. This was true on machines
1394 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1395 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1396 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1397 output_insn (insn, &the_insn);
1402 as_fatal (_("failed special case insn sanity check"));
1407 get_hwcap_name (int mask)
1409 if (mask & HWCAP_MUL32)
1411 if (mask & HWCAP_DIV32)
1413 if (mask & HWCAP_FSMULD)
1415 if (mask & HWCAP_V8PLUS)
1417 if (mask & HWCAP_POPC)
1419 if (mask & HWCAP_VIS)
1421 if (mask & HWCAP_VIS2)
1423 if (mask & HWCAP_ASI_BLK_INIT)
1424 return "ASIBlkInit";
1425 if (mask & HWCAP_FMAF)
1427 if (mask & HWCAP_VIS3)
1429 if (mask & HWCAP_HPC)
1431 if (mask & HWCAP_RANDOM)
1433 if (mask & HWCAP_TRANS)
1435 if (mask & HWCAP_FJFMAU)
1437 if (mask & HWCAP_IMA)
1439 if (mask & HWCAP_ASI_CACHE_SPARING)
1441 if (mask & HWCAP_AES)
1443 if (mask & HWCAP_DES)
1445 if (mask & HWCAP_KASUMI)
1447 if (mask & HWCAP_CAMELLIA)
1449 if (mask & HWCAP_MD5)
1451 if (mask & HWCAP_SHA1)
1453 if (mask & HWCAP_SHA256)
1455 if (mask & HWCAP_SHA512)
1457 if (mask & HWCAP_MPMUL)
1459 if (mask & HWCAP_MONT)
1461 if (mask & HWCAP_PAUSE)
1463 if (mask & HWCAP_CBCOND)
1465 if (mask & HWCAP_CRC32C)
1470 /* Subroutine of md_assemble to do the actual parsing. */
1473 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1475 char *error_message = "";
1479 const struct sparc_opcode *insn;
1481 unsigned long opcode;
1482 unsigned int mask = 0;
1486 int special_case = SPECIAL_CASE_NONE;
1493 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1510 as_bad (_("Unknown opcode: `%s'"), str);
1512 return special_case;
1514 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1518 as_bad (_("Unknown opcode: `%s'"), str);
1519 return special_case;
1529 opcode = insn->match;
1530 memset (&the_insn, '\0', sizeof (the_insn));
1531 the_insn.reloc = BFD_RELOC_NONE;
1534 /* Build the opcode, checking as we go to make sure that the
1536 for (args = insn->args;; ++args)
1544 /* Parse a series of masks. */
1551 if (! parse_keyword_arg (sparc_encode_membar, &s,
1554 error_message = _(": invalid membar mask name");
1560 if (*s == '|' || *s == '+')
1568 if (! parse_const_expr_arg (&s, &kmask))
1570 error_message = _(": invalid membar mask expression");
1573 if (kmask < 0 || kmask > 127)
1575 error_message = _(": invalid membar mask number");
1580 opcode |= MEMBAR (kmask);
1588 if (! parse_const_expr_arg (&s, &smask))
1590 error_message = _(": invalid siam mode expression");
1593 if (smask < 0 || smask > 7)
1595 error_message = _(": invalid siam mode number");
1606 /* Parse a prefetch function. */
1609 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1611 error_message = _(": invalid prefetch function name");
1617 if (! parse_const_expr_arg (&s, &fcn))
1619 error_message = _(": invalid prefetch function expression");
1622 if (fcn < 0 || fcn > 31)
1624 error_message = _(": invalid prefetch function number");
1634 /* Parse a sparc64 privileged register. */
1637 struct priv_reg_entry *p = priv_reg_table;
1638 unsigned int len = 9999999; /* Init to make gcc happy. */
1641 while (p->name[0] > s[0])
1643 while (p->name[0] == s[0])
1645 len = strlen (p->name);
1646 if (strncmp (p->name, s, len) == 0)
1650 if (p->name[0] != s[0])
1652 error_message = _(": unrecognizable privileged register");
1656 opcode |= (p->regnum << 14);
1658 opcode |= (p->regnum << 25);
1664 error_message = _(": unrecognizable privileged register");
1670 /* Parse a sparc64 hyperprivileged register. */
1673 struct priv_reg_entry *p = hpriv_reg_table;
1674 unsigned int len = 9999999; /* Init to make gcc happy. */
1677 while (p->name[0] > s[0])
1679 while (p->name[0] == s[0])
1681 len = strlen (p->name);
1682 if (strncmp (p->name, s, len) == 0)
1686 if (p->name[0] != s[0])
1688 error_message = _(": unrecognizable hyperprivileged register");
1692 opcode |= (p->regnum << 14);
1694 opcode |= (p->regnum << 25);
1700 error_message = _(": unrecognizable hyperprivileged register");
1706 /* Parse a v9a/v9b ancillary state register. */
1709 struct priv_reg_entry *p = v9a_asr_table;
1710 unsigned int len = 9999999; /* Init to make gcc happy. */
1713 while (p->name[0] > s[0])
1715 while (p->name[0] == s[0])
1717 len = strlen (p->name);
1718 if (strncmp (p->name, s, len) == 0)
1722 if (p->name[0] != s[0])
1724 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1727 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1729 error_message = _(": rd on write only ancillary state register");
1733 && (insn->architecture
1734 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1736 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1737 error_message = _(": unrecognizable v9a ancillary state register");
1741 opcode |= (p->regnum << 14);
1743 opcode |= (p->regnum << 25);
1749 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1755 if (strncmp (s, "%asr", 4) == 0)
1763 while (ISDIGIT (*s))
1765 num = num * 10 + *s - '0';
1769 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1771 if (num < 16 || 31 < num)
1773 error_message = _(": asr number must be between 16 and 31");
1779 if (num < 0 || 31 < num)
1781 error_message = _(": asr number must be between 0 and 31");
1786 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1791 error_message = _(": expecting %asrN");
1798 the_insn.reloc = BFD_RELOC_SPARC_11;
1802 the_insn.reloc = BFD_RELOC_SPARC_10;
1808 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1813 if (s[0] == '0' && s[1] == 'x')
1816 while (ISXDIGIT (*s))
1819 num |= hex_value (*s);
1825 while (ISDIGIT (*s))
1827 num = num * 10 + *s - '0';
1831 if (num < 0 || num > 31)
1833 error_message = _(": crypto immediate must be between 0 and 31");
1837 opcode |= RS3 (num);
1842 error_message = _(": expecting crypto immediate");
1847 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1848 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1849 the_insn.reloc = BFD_RELOC_SPARC_5;
1851 the_insn.reloc = BFD_RELOC_SPARC13;
1852 /* These fields are unsigned, but for upward compatibility,
1853 allow negative values as well. */
1857 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1858 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1859 the_insn.reloc = BFD_RELOC_SPARC_6;
1861 the_insn.reloc = BFD_RELOC_SPARC13;
1862 /* These fields are unsigned, but for upward compatibility,
1863 allow negative values as well. */
1867 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1872 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1877 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1882 if (*s == 'p' && s[1] == 'n')
1890 if (*s == 'p' && s[1] == 't')
1902 if (strncmp (s, "%icc", 4) == 0)
1914 if (strncmp (s, "%xcc", 4) == 0)
1926 if (strncmp (s, "%fcc0", 5) == 0)
1938 if (strncmp (s, "%fcc1", 5) == 0)
1950 if (strncmp (s, "%fcc2", 5) == 0)
1962 if (strncmp (s, "%fcc3", 5) == 0)
1970 if (strncmp (s, "%pc", 3) == 0)
1978 if (strncmp (s, "%tick", 5) == 0)
1985 case '\0': /* End of args. */
1986 if (s[0] == ',' && s[1] == '%')
1988 static const struct ops
1990 /* The name as it appears in assembler. */
1992 /* strlen (name), precomputed for speed */
1994 /* The reloc this pseudo-op translates to. */
1996 /* 1 if tls call. */
2001 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2002 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2003 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2004 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2005 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2006 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2007 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2008 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2009 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2012 const struct ops *o;
2016 for (o = ops; o->name; o++)
2017 if (strncmp (s + 2, o->name, o->len) == 0)
2019 if (o->name == NULL)
2022 if (s[o->len + 2] != '(')
2024 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2025 return special_case;
2028 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2030 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2032 return special_case;
2036 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2037 || the_insn.exp.X_add_number != 0
2038 || the_insn.exp.X_add_symbol
2039 != symbol_find_or_make ("__tls_get_addr")))
2041 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2043 return special_case;
2046 the_insn.reloc = o->reloc;
2047 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2050 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2053 else if (*s1 == ')')
2062 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2063 return special_case;
2067 (void) get_expression (s);
2087 case '[': /* These must match exactly. */
2095 case '#': /* Must be at least one digit. */
2098 while (ISDIGIT (*s))
2106 case 'C': /* Coprocessor state register. */
2107 if (strncmp (s, "%csr", 4) == 0)
2114 case 'b': /* Next operand is a coprocessor register. */
2117 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2122 mask = 10 * (mask - '0') + (*s++ - '0');
2136 opcode |= mask << 14;
2144 opcode |= mask << 25;
2150 case 'r': /* next operand must be a register */
2160 case 'f': /* frame pointer */
2168 case 'g': /* global register */
2177 case 'i': /* in register */
2181 mask = c - '0' + 24;
2186 case 'l': /* local register */
2190 mask = (c - '0' + 16);
2195 case 'o': /* out register */
2199 mask = (c - '0' + 8);
2204 case 's': /* stack pointer */
2212 case 'r': /* any register */
2213 if (!ISDIGIT ((c = *s++)))
2230 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2246 if ((mask & ~1) == 2 && sparc_arch_size == 64
2247 && no_undeclared_regs && ! globals[mask])
2248 as_bad (_("detected global register use not covered by .register pseudo-op"));
2250 /* Got the register, now figure out where
2251 it goes in the opcode. */
2255 opcode |= mask << 14;
2263 opcode |= mask << 25;
2267 opcode |= (mask << 25) | (mask << 14);
2271 opcode |= (mask << 25) | (mask << 0);
2277 case 'e': /* next operand is a floating point register */
2295 && ((format = *s) == 'f')
2298 for (mask = 0; ISDIGIT (*s); ++s)
2300 mask = 10 * mask + (*s - '0');
2301 } /* read the number */
2310 } /* register must be even numbered */
2318 } /* register must be multiple of 4 */
2322 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2323 error_message = _(": There are only 64 f registers; [0-63]");
2325 error_message = _(": There are only 32 f registers; [0-31]");
2328 else if (mask >= 32)
2330 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2332 if (*args == 'e' || *args == 'f' || *args == 'g')
2335 = _(": There are only 32 single precision f registers; [0-31]");
2339 mask -= 31; /* wrap high bit */
2343 error_message = _(": There are only 32 f registers; [0-31]");
2351 } /* if not an 'f' register. */
2358 opcode |= RS1 (mask);
2364 opcode |= RS2 (mask);
2369 opcode |= RS3 (mask);
2375 opcode |= RD (mask);
2384 if (strncmp (s, "%fsr", 4) == 0)
2392 if (strncmp (s, "%efsr", 5) == 0)
2399 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2400 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2403 case 'l': /* 22 bit PC relative immediate */
2404 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2408 case 'L': /* 30 bit immediate */
2409 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2414 case 'n': /* 22 bit immediate */
2415 the_insn.reloc = BFD_RELOC_SPARC22;
2418 case 'i': /* 13 bit immediate */
2419 the_insn.reloc = BFD_RELOC_SPARC13;
2429 char *op_arg = NULL;
2430 static expressionS op_exp;
2431 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2433 /* Check for %hi, etc. */
2436 static const struct ops {
2437 /* The name as it appears in assembler. */
2439 /* strlen (name), precomputed for speed */
2441 /* The reloc this pseudo-op translates to. */
2443 /* Non-zero if for v9 only. */
2445 /* Non-zero if can be used in pc-relative contexts. */
2446 int pcrel_p;/*FIXME:wip*/
2448 /* hix/lox must appear before hi/lo so %hix won't be
2449 mistaken for %hi. */
2450 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2451 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2452 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2453 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2454 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2455 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2456 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2457 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2458 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2459 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2460 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2461 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2462 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2463 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2464 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2465 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2466 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2467 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2468 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2469 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2470 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2472 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2474 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2475 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2476 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2477 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2478 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2480 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2482 { NULL, 0, 0, 0, 0 }
2484 const struct ops *o;
2486 for (o = ops; o->name; o++)
2487 if (strncmp (s + 1, o->name, o->len) == 0)
2489 if (o->name == NULL)
2492 if (s[o->len + 1] != '(')
2494 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2495 return special_case;
2499 the_insn.reloc = o->reloc;
2504 /* Note that if the get_expression() fails, we will still
2505 have created U entries in the symbol table for the
2506 'symbols' in the input string. Try not to create U
2507 symbols for registers, etc. */
2509 /* This stuff checks to see if the expression ends in
2510 +%reg. If it does, it removes the register from
2511 the expression, and re-sets 's' to point to the
2518 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2521 else if (*s1 == ')')
2530 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2531 return special_case;
2535 (void) get_expression (s);
2538 if (*s == ',' || *s == ']' || !*s)
2540 if (*s != '+' && *s != '-')
2542 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2543 return special_case;
2547 op_exp = the_insn.exp;
2548 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2551 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2554 if (s1 != s && ISDIGIT (s1[-1]))
2556 if (s1[-2] == '%' && s1[-3] == '+')
2558 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2560 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2567 if (op_arg && s1 == s + 1)
2568 the_insn.exp.X_op = O_absent;
2570 (void) get_expression (s);
2582 (void) get_expression (s);
2590 the_insn.exp2 = the_insn.exp;
2591 the_insn.exp = op_exp;
2592 if (the_insn.exp2.X_op == O_absent)
2593 the_insn.exp2.X_op = O_illegal;
2594 else if (the_insn.exp.X_op == O_absent)
2596 the_insn.exp = the_insn.exp2;
2597 the_insn.exp2.X_op = O_illegal;
2599 else if (the_insn.exp.X_op == O_constant)
2601 valueT val = the_insn.exp.X_add_number;
2602 switch (the_insn.reloc)
2607 case BFD_RELOC_SPARC_HH22:
2608 val = BSR (val, 32);
2611 case BFD_RELOC_SPARC_LM22:
2612 case BFD_RELOC_HI22:
2613 val = (val >> 10) & 0x3fffff;
2616 case BFD_RELOC_SPARC_HM10:
2617 val = BSR (val, 32);
2620 case BFD_RELOC_LO10:
2624 case BFD_RELOC_SPARC_H34:
2629 case BFD_RELOC_SPARC_H44:
2634 case BFD_RELOC_SPARC_M44:
2639 case BFD_RELOC_SPARC_L44:
2643 case BFD_RELOC_SPARC_HIX22:
2645 val = (val >> 10) & 0x3fffff;
2648 case BFD_RELOC_SPARC_LOX10:
2649 val = (val & 0x3ff) | 0x1c00;
2652 the_insn.exp = the_insn.exp2;
2653 the_insn.exp.X_add_number += val;
2654 the_insn.exp2.X_op = O_illegal;
2655 the_insn.reloc = old_reloc;
2657 else if (the_insn.exp2.X_op != O_constant)
2659 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2660 return special_case;
2664 if (old_reloc != BFD_RELOC_SPARC13
2665 || the_insn.reloc != BFD_RELOC_LO10
2666 || sparc_arch_size != 64
2669 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2670 return special_case;
2672 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2676 /* Check for constants that don't require emitting a reloc. */
2677 if (the_insn.exp.X_op == O_constant
2678 && the_insn.exp.X_add_symbol == 0
2679 && the_insn.exp.X_op_symbol == 0)
2681 /* For pc-relative call instructions, we reject
2682 constants to get better code. */
2684 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2685 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2687 error_message = _(": PC-relative operand can't be a constant");
2691 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2692 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2694 error_message = _(": TLS operand can't be a constant");
2698 /* Constants that won't fit are checked in md_apply_fix
2699 and bfd_install_relocation.
2700 ??? It would be preferable to install the constants
2701 into the insn here and save having to create a fixS
2702 for each one. There already exists code to handle
2703 all the various cases (e.g. in md_apply_fix and
2704 bfd_install_relocation) so duplicating all that code
2705 here isn't right. */
2707 /* This is a special case to handle cbcond instructions
2708 properly, which can need two relocations. The first
2709 one is for the 5-bit immediate field and the latter
2710 is going to be for the WDISP10 branch part. We
2711 handle the R_SPARC_5 immediate directly here so that
2712 we don't need to add support for multiple relocations
2713 in one instruction just yet. */
2714 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2716 valueT val = the_insn.exp.X_add_number;
2718 if (! in_bitfield_range (val, 0x1f))
2720 error_message = _(": Immediate value in cbcond is out of range.");
2723 opcode |= val & 0x1f;
2724 the_insn.reloc = BFD_RELOC_NONE;
2745 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2747 error_message = _(": invalid ASI name");
2753 if (! parse_const_expr_arg (&s, &asi))
2755 error_message = _(": invalid ASI expression");
2758 if (asi < 0 || asi > 255)
2760 error_message = _(": invalid ASI number");
2764 opcode |= ASI (asi);
2766 } /* Alternate space. */
2769 if (strncmp (s, "%psr", 4) == 0)
2776 case 'q': /* Floating point queue. */
2777 if (strncmp (s, "%fq", 3) == 0)
2784 case 'Q': /* Coprocessor queue. */
2785 if (strncmp (s, "%cq", 3) == 0)
2793 if (strcmp (str, "set") == 0
2794 || strcmp (str, "setuw") == 0)
2796 special_case = SPECIAL_CASE_SET;
2799 else if (strcmp (str, "setsw") == 0)
2801 special_case = SPECIAL_CASE_SETSW;
2804 else if (strcmp (str, "setx") == 0)
2806 special_case = SPECIAL_CASE_SETX;
2809 else if (strncmp (str, "fdiv", 4) == 0)
2811 special_case = SPECIAL_CASE_FDIV;
2817 if (strncmp (s, "%asi", 4) != 0)
2823 if (strncmp (s, "%fprs", 5) != 0)
2829 if (strncmp (s, "%ccr", 4) != 0)
2835 if (strncmp (s, "%tbr", 4) != 0)
2841 if (strncmp (s, "%wim", 4) != 0)
2848 char *push = input_line_pointer;
2851 input_line_pointer = s;
2853 if (e.X_op == O_constant)
2855 int n = e.X_add_number;
2856 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2857 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2859 opcode |= e.X_add_number << 5;
2862 as_bad (_("non-immediate OPF operand, ignored"));
2863 s = input_line_pointer;
2864 input_line_pointer = push;
2869 if (strncmp (s, "%y", 2) != 0)
2877 /* Parse a sparclet cpreg. */
2879 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2881 error_message = _(": invalid cpreg name");
2884 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2889 as_fatal (_("failed sanity check."));
2890 } /* switch on arg code. */
2892 /* Break out of for() loop. */
2894 } /* For each arg that we expect. */
2899 /* Args don't match. */
2900 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2901 && (insn->name == insn[1].name
2902 || !strcmp (insn->name, insn[1].name)))
2910 as_bad (_("Illegal operands%s"), error_message);
2911 return special_case;
2916 /* We have a match. Now see if the architecture is OK. */
2917 int needed_arch_mask = insn->architecture;
2918 int hwcaps = insn->hwcaps;
2920 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2922 hwcap_seen |= hwcaps;
2927 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2928 if (! needed_arch_mask)
2930 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2933 if (needed_arch_mask
2934 & SPARC_OPCODE_SUPPORTED (current_architecture))
2937 /* Can we bump up the architecture? */
2938 else if (needed_arch_mask
2939 & SPARC_OPCODE_SUPPORTED (max_architecture))
2941 enum sparc_opcode_arch_val needed_architecture =
2942 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2943 & needed_arch_mask);
2945 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2947 && needed_architecture > warn_after_architecture)
2949 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2950 sparc_opcode_archs[current_architecture].name,
2951 sparc_opcode_archs[needed_architecture].name,
2953 warn_after_architecture = needed_architecture;
2955 current_architecture = needed_architecture;
2958 /* ??? This seems to be a bit fragile. What if the next entry in
2959 the opcode table is the one we want and it is supported?
2960 It is possible to arrange the table today so that this can't
2961 happen but what about tomorrow? */
2964 int arch, printed_one_p = 0;
2966 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2968 /* Create a list of the architectures that support the insn. */
2969 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2971 arch = sparc_ffs (needed_arch_mask);
2972 while ((1 << arch) <= needed_arch_mask)
2974 if ((1 << arch) & needed_arch_mask)
2978 strcpy (p, sparc_opcode_archs[arch].name);
2985 as_bad (_("Architecture mismatch on \"%s\"."), str);
2986 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2988 sparc_opcode_archs[max_architecture].name);
2989 return special_case;
2992 /* Make sure the the hwcaps used by the instruction are
2993 currently enabled. */
2994 if (hwcaps & ~hwcap_allowed)
2996 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2998 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3000 return special_case;
3002 } /* If no match. */
3005 } /* Forever looking for a match. */
3007 the_insn.opcode = opcode;
3008 return special_case;
3011 /* Parse an argument that can be expressed as a keyword.
3012 (eg: #StoreStore or %ccfr).
3013 The result is a boolean indicating success.
3014 If successful, INPUT_POINTER is updated. */
3017 parse_keyword_arg (int (*lookup_fn) (const char *),
3018 char **input_pointerP,
3024 p = *input_pointerP;
3025 for (q = p + (*p == '#' || *p == '%');
3026 ISALNUM (*q) || *q == '_';
3031 value = (*lookup_fn) (p);
3036 *input_pointerP = q;
3040 /* Parse an argument that is a constant expression.
3041 The result is a boolean indicating success. */
3044 parse_const_expr_arg (char **input_pointerP, int *valueP)
3046 char *save = input_line_pointer;
3049 input_line_pointer = *input_pointerP;
3050 /* The next expression may be something other than a constant
3051 (say if we're not processing the right variant of the insn).
3052 Don't call expression unless we're sure it will succeed as it will
3053 signal an error (which we want to defer until later). */
3054 /* FIXME: It might be better to define md_operand and have it recognize
3055 things like %asi, etc. but continuing that route through to the end
3056 is a lot of work. */
3057 if (*input_line_pointer == '%')
3059 input_line_pointer = save;
3063 *input_pointerP = input_line_pointer;
3064 input_line_pointer = save;
3065 if (exp.X_op != O_constant)
3067 *valueP = exp.X_add_number;
3071 /* Subroutine of sparc_ip to parse an expression. */
3074 get_expression (char *str)
3079 save_in = input_line_pointer;
3080 input_line_pointer = str;
3081 seg = expression (&the_insn.exp);
3082 if (seg != absolute_section
3083 && seg != text_section
3084 && seg != data_section
3085 && seg != bss_section
3086 && seg != undefined_section)
3088 the_insn.error = _("bad segment");
3089 expr_end = input_line_pointer;
3090 input_line_pointer = save_in;
3093 expr_end = input_line_pointer;
3094 input_line_pointer = save_in;
3098 /* Subroutine of md_assemble to output one insn. */
3101 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3103 char *toP = frag_more (4);
3105 /* Put out the opcode. */
3106 if (INSN_BIG_ENDIAN)
3107 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3109 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3111 /* Put out the symbol-dependent stuff. */
3112 if (theinsn->reloc != BFD_RELOC_NONE)
3114 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3115 (toP - frag_now->fr_literal), /* Where. */
3120 /* Turn off overflow checking in fixup_segment. We'll do our
3121 own overflow checking in md_apply_fix. This is necessary because
3122 the insn size is 4 and fixup_segment will signal an overflow for
3123 large 8 byte quantities. */
3124 fixP->fx_no_overflow = 1;
3125 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3126 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3130 last_opcode = theinsn->opcode;
3133 dwarf2_emit_insn (4);
3138 md_atof (int type, char *litP, int *sizeP)
3140 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3143 /* Write a value out to the object file, using the appropriate
3147 md_number_to_chars (char *buf, valueT val, int n)
3149 if (target_big_endian)
3150 number_to_chars_bigendian (buf, val, n);
3151 else if (target_little_endian_data
3152 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3153 /* Output debug words, which are not in allocated sections, as big
3155 number_to_chars_bigendian (buf, val, n);
3156 else if (target_little_endian_data || ! target_big_endian)
3157 number_to_chars_littleendian (buf, val, n);
3160 /* Apply a fixS to the frags, now that we know the value it ought to
3164 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3166 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3167 offsetT val = * (offsetT *) valP;
3170 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3172 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3175 /* SPARC ELF relocations don't use an addend in the data field. */
3176 if (fixP->fx_addsy != NULL)
3178 switch (fixP->fx_r_type)
3180 case BFD_RELOC_SPARC_TLS_GD_HI22:
3181 case BFD_RELOC_SPARC_TLS_GD_LO10:
3182 case BFD_RELOC_SPARC_TLS_GD_ADD:
3183 case BFD_RELOC_SPARC_TLS_GD_CALL:
3184 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3185 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3186 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3187 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3188 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3189 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3190 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3191 case BFD_RELOC_SPARC_TLS_IE_HI22:
3192 case BFD_RELOC_SPARC_TLS_IE_LO10:
3193 case BFD_RELOC_SPARC_TLS_IE_LD:
3194 case BFD_RELOC_SPARC_TLS_IE_LDX:
3195 case BFD_RELOC_SPARC_TLS_IE_ADD:
3196 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3197 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3198 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3199 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3200 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3201 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3202 case BFD_RELOC_SPARC_TLS_TPOFF32:
3203 case BFD_RELOC_SPARC_TLS_TPOFF64:
3204 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3214 /* This is a hack. There should be a better way to
3215 handle this. Probably in terms of howto fields, once
3216 we can look at these fixups in terms of howtos. */
3217 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3218 val += fixP->fx_where + fixP->fx_frag->fr_address;
3221 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3222 generate a reloc, then we just want to let the reloc addend set
3223 the value. We do not want to also stuff the addend into the
3224 object file. Including the addend in the object file works when
3225 doing a static link, because the linker will ignore the object
3226 file contents. However, the dynamic linker does not ignore the
3227 object file contents. */
3228 if (fixP->fx_addsy != NULL
3229 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3232 /* When generating PIC code, we do not want an addend for a reloc
3233 against a local symbol. We adjust fx_addnumber to cancel out the
3234 value already included in val, and to also cancel out the
3235 adjustment which bfd_install_relocation will create. */
3237 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3238 && fixP->fx_addsy != NULL
3239 && ! S_IS_COMMON (fixP->fx_addsy)
3240 && symbol_section_p (fixP->fx_addsy))
3241 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3243 /* When generating PIC code, we need to fiddle to get
3244 bfd_install_relocation to do the right thing for a PC relative
3245 reloc against a local symbol which we are going to keep. */
3247 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3248 && fixP->fx_addsy != NULL
3249 && (S_IS_EXTERNAL (fixP->fx_addsy)
3250 || S_IS_WEAK (fixP->fx_addsy))
3251 && S_IS_DEFINED (fixP->fx_addsy)
3252 && ! S_IS_COMMON (fixP->fx_addsy))
3255 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3259 /* If this is a data relocation, just output VAL. */
3261 if (fixP->fx_r_type == BFD_RELOC_8)
3263 md_number_to_chars (buf, val, 1);
3265 else if (fixP->fx_r_type == BFD_RELOC_16
3266 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3268 md_number_to_chars (buf, val, 2);
3270 else if (fixP->fx_r_type == BFD_RELOC_32
3271 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3272 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3274 md_number_to_chars (buf, val, 4);
3276 else if (fixP->fx_r_type == BFD_RELOC_64
3277 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3279 md_number_to_chars (buf, val, 8);
3281 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3282 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3289 /* It's a relocation against an instruction. */
3291 if (INSN_BIG_ENDIAN)
3292 insn = bfd_getb32 ((unsigned char *) buf);
3294 insn = bfd_getl32 ((unsigned char *) buf);
3296 switch (fixP->fx_r_type)
3298 case BFD_RELOC_32_PCREL_S2:
3300 /* FIXME: This increment-by-one deserves a comment of why it's
3302 if (! sparc_pic_code
3303 || fixP->fx_addsy == NULL
3304 || symbol_section_p (fixP->fx_addsy))
3307 insn |= val & 0x3fffffff;
3309 /* See if we have a delay slot. */
3310 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3314 #define XCC (2 << 20)
3315 #define COND(x) (((x)&0xf)<<25)
3316 #define CONDA COND(0x8)
3317 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3318 #define INSN_BA (F2(0,2) | CONDA)
3319 #define INSN_OR F3(2, 0x2, 0)
3320 #define INSN_NOP F2(0,4)
3324 /* If the instruction is a call with either:
3326 arithmetic instruction with rd == %o7
3327 where rs1 != %o7 and rs2 if it is register != %o7
3328 then we can optimize if the call destination is near
3329 by changing the call into a branch always. */
3330 if (INSN_BIG_ENDIAN)
3331 delay = bfd_getb32 ((unsigned char *) buf + 4);
3333 delay = bfd_getl32 ((unsigned char *) buf + 4);
3334 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3336 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3337 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3338 || ((delay & RD (~0)) != RD (O7))))
3340 if ((delay & RS1 (~0)) == RS1 (O7)
3341 || ((delay & F3I (~0)) == 0
3342 && (delay & RS2 (~0)) == RS2 (O7)))
3344 /* Ensure the branch will fit into simm22. */
3345 if ((val & 0x3fe00000)
3346 && (val & 0x3fe00000) != 0x3fe00000)
3348 /* Check if the arch is v9 and branch will fit
3350 if (((val & 0x3c0000) == 0
3351 || (val & 0x3c0000) == 0x3c0000)
3352 && (sparc_arch_size == 64
3353 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3355 insn = INSN_BPA | (val & 0x7ffff);
3358 insn = INSN_BA | (val & 0x3fffff);
3359 if (fixP->fx_where >= 4
3360 && ((delay & (0xffffffff ^ RS1 (~0)))
3361 == (INSN_OR | RD (O7) | RS2 (G0))))
3366 if (INSN_BIG_ENDIAN)
3367 setter = bfd_getb32 ((unsigned char *) buf - 4);
3369 setter = bfd_getl32 ((unsigned char *) buf - 4);
3370 if ((setter & (0xffffffff ^ RD (~0)))
3371 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3378 If call foo was replaced with ba, replace
3379 or %rN, %g0, %o7 with nop. */
3380 reg = (delay & RS1 (~0)) >> 14;
3381 if (reg != ((setter & RD (~0)) >> 25)
3382 || reg == G0 || reg == O7)
3385 if (INSN_BIG_ENDIAN)
3386 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3388 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3393 case BFD_RELOC_SPARC_11:
3394 if (! in_signed_range (val, 0x7ff))
3395 as_bad_where (fixP->fx_file, fixP->fx_line,
3396 _("relocation overflow"));
3397 insn |= val & 0x7ff;
3400 case BFD_RELOC_SPARC_10:
3401 if (! in_signed_range (val, 0x3ff))
3402 as_bad_where (fixP->fx_file, fixP->fx_line,
3403 _("relocation overflow"));
3404 insn |= val & 0x3ff;
3407 case BFD_RELOC_SPARC_7:
3408 if (! in_bitfield_range (val, 0x7f))
3409 as_bad_where (fixP->fx_file, fixP->fx_line,
3410 _("relocation overflow"));
3414 case BFD_RELOC_SPARC_6:
3415 if (! in_bitfield_range (val, 0x3f))
3416 as_bad_where (fixP->fx_file, fixP->fx_line,
3417 _("relocation overflow"));
3421 case BFD_RELOC_SPARC_5:
3422 if (! in_bitfield_range (val, 0x1f))
3423 as_bad_where (fixP->fx_file, fixP->fx_line,
3424 _("relocation overflow"));
3428 case BFD_RELOC_SPARC_WDISP10:
3431 || val <= -(offsetT) 0x808)
3432 as_bad_where (fixP->fx_file, fixP->fx_line,
3433 _("relocation overflow"));
3434 /* FIXME: The +1 deserves a comment. */
3435 val = (val >> 2) + 1;
3436 insn |= ((val & 0x300) << 11)
3437 | ((val & 0xff) << 5);
3440 case BFD_RELOC_SPARC_WDISP16:
3443 || val <= -(offsetT) 0x20008)
3444 as_bad_where (fixP->fx_file, fixP->fx_line,
3445 _("relocation overflow"));
3446 /* FIXME: The +1 deserves a comment. */
3447 val = (val >> 2) + 1;
3448 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3451 case BFD_RELOC_SPARC_WDISP19:
3454 || val <= -(offsetT) 0x100008)
3455 as_bad_where (fixP->fx_file, fixP->fx_line,
3456 _("relocation overflow"));
3457 /* FIXME: The +1 deserves a comment. */
3458 val = (val >> 2) + 1;
3459 insn |= val & 0x7ffff;
3462 case BFD_RELOC_SPARC_HH22:
3463 val = BSR (val, 32);
3466 case BFD_RELOC_SPARC_LM22:
3467 case BFD_RELOC_HI22:
3468 if (!fixP->fx_addsy)
3469 insn |= (val >> 10) & 0x3fffff;
3471 /* FIXME: Need comment explaining why we do this. */
3475 case BFD_RELOC_SPARC22:
3476 if (val & ~0x003fffff)
3477 as_bad_where (fixP->fx_file, fixP->fx_line,
3478 _("relocation overflow"));
3479 insn |= (val & 0x3fffff);
3482 case BFD_RELOC_SPARC_HM10:
3483 val = BSR (val, 32);
3486 case BFD_RELOC_LO10:
3487 if (!fixP->fx_addsy)
3488 insn |= val & 0x3ff;
3490 /* FIXME: Need comment explaining why we do this. */
3494 case BFD_RELOC_SPARC_OLO10:
3496 val += fixP->tc_fix_data;
3499 case BFD_RELOC_SPARC13:
3500 if (! in_signed_range (val, 0x1fff))
3501 as_bad_where (fixP->fx_file, fixP->fx_line,
3502 _("relocation overflow"));
3503 insn |= val & 0x1fff;
3506 case BFD_RELOC_SPARC_WDISP22:
3507 val = (val >> 2) + 1;
3509 case BFD_RELOC_SPARC_BASE22:
3510 insn |= val & 0x3fffff;
3513 case BFD_RELOC_SPARC_H34:
3514 if (!fixP->fx_addsy)
3518 insn |= tval & 0x3fffff;
3522 case BFD_RELOC_SPARC_H44:
3523 if (!fixP->fx_addsy)
3527 insn |= tval & 0x3fffff;
3531 case BFD_RELOC_SPARC_M44:
3532 if (!fixP->fx_addsy)
3533 insn |= (val >> 12) & 0x3ff;
3536 case BFD_RELOC_SPARC_L44:
3537 if (!fixP->fx_addsy)
3538 insn |= val & 0xfff;
3541 case BFD_RELOC_SPARC_HIX22:
3542 if (!fixP->fx_addsy)
3544 val ^= ~(offsetT) 0;
3545 insn |= (val >> 10) & 0x3fffff;
3549 case BFD_RELOC_SPARC_LOX10:
3550 if (!fixP->fx_addsy)
3551 insn |= 0x1c00 | (val & 0x3ff);
3554 case BFD_RELOC_NONE:
3556 as_bad_where (fixP->fx_file, fixP->fx_line,
3557 _("bad or unhandled relocation type: 0x%02x"),
3562 if (INSN_BIG_ENDIAN)
3563 bfd_putb32 (insn, (unsigned char *) buf);
3565 bfd_putl32 (insn, (unsigned char *) buf);
3568 /* Are we finished with this relocation now? */
3569 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3573 /* Translate internal representation of relocation info to BFD target
3577 tc_gen_reloc (asection *section, fixS *fixp)
3579 static arelent *relocs[3];
3581 bfd_reloc_code_real_type code;
3583 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3586 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3587 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3588 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3590 switch (fixp->fx_r_type)
3594 case BFD_RELOC_HI22:
3595 case BFD_RELOC_LO10:
3596 case BFD_RELOC_32_PCREL_S2:
3597 case BFD_RELOC_SPARC13:
3598 case BFD_RELOC_SPARC22:
3599 case BFD_RELOC_SPARC_PC22:
3600 case BFD_RELOC_SPARC_PC10:
3601 case BFD_RELOC_SPARC_BASE13:
3602 case BFD_RELOC_SPARC_WDISP10:
3603 case BFD_RELOC_SPARC_WDISP16:
3604 case BFD_RELOC_SPARC_WDISP19:
3605 case BFD_RELOC_SPARC_WDISP22:
3607 case BFD_RELOC_SPARC_5:
3608 case BFD_RELOC_SPARC_6:
3609 case BFD_RELOC_SPARC_7:
3610 case BFD_RELOC_SPARC_10:
3611 case BFD_RELOC_SPARC_11:
3612 case BFD_RELOC_SPARC_HH22:
3613 case BFD_RELOC_SPARC_HM10:
3614 case BFD_RELOC_SPARC_LM22:
3615 case BFD_RELOC_SPARC_PC_HH22:
3616 case BFD_RELOC_SPARC_PC_HM10:
3617 case BFD_RELOC_SPARC_PC_LM22:
3618 case BFD_RELOC_SPARC_H34:
3619 case BFD_RELOC_SPARC_H44:
3620 case BFD_RELOC_SPARC_M44:
3621 case BFD_RELOC_SPARC_L44:
3622 case BFD_RELOC_SPARC_HIX22:
3623 case BFD_RELOC_SPARC_LOX10:
3624 case BFD_RELOC_SPARC_REV32:
3625 case BFD_RELOC_SPARC_OLO10:
3626 case BFD_RELOC_SPARC_UA16:
3627 case BFD_RELOC_SPARC_UA32:
3628 case BFD_RELOC_SPARC_UA64:
3629 case BFD_RELOC_8_PCREL:
3630 case BFD_RELOC_16_PCREL:
3631 case BFD_RELOC_32_PCREL:
3632 case BFD_RELOC_64_PCREL:
3633 case BFD_RELOC_SPARC_PLT32:
3634 case BFD_RELOC_SPARC_PLT64:
3635 case BFD_RELOC_VTABLE_ENTRY:
3636 case BFD_RELOC_VTABLE_INHERIT:
3637 case BFD_RELOC_SPARC_TLS_GD_HI22:
3638 case BFD_RELOC_SPARC_TLS_GD_LO10:
3639 case BFD_RELOC_SPARC_TLS_GD_ADD:
3640 case BFD_RELOC_SPARC_TLS_GD_CALL:
3641 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3642 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3643 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3644 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3645 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3646 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3647 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3648 case BFD_RELOC_SPARC_TLS_IE_HI22:
3649 case BFD_RELOC_SPARC_TLS_IE_LO10:
3650 case BFD_RELOC_SPARC_TLS_IE_LD:
3651 case BFD_RELOC_SPARC_TLS_IE_LDX:
3652 case BFD_RELOC_SPARC_TLS_IE_ADD:
3653 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3654 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3655 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3656 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3657 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3658 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3659 case BFD_RELOC_SPARC_GOTDATA_OP:
3660 code = fixp->fx_r_type;
3667 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3668 /* If we are generating PIC code, we need to generate a different
3672 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3674 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3677 #define GOTT_BASE "__GOTT_BASE__"
3678 #define GOTT_INDEX "__GOTT_INDEX__"
3681 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3687 case BFD_RELOC_32_PCREL_S2:
3688 if (generic_force_reloc (fixp))
3689 code = BFD_RELOC_SPARC_WPLT30;
3691 case BFD_RELOC_HI22:
3692 code = BFD_RELOC_SPARC_GOT22;
3693 if (fixp->fx_addsy != NULL)
3695 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3696 code = BFD_RELOC_SPARC_PC22;
3698 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3699 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3700 code = BFD_RELOC_HI22; /* Unchanged. */
3704 case BFD_RELOC_LO10:
3705 code = BFD_RELOC_SPARC_GOT10;
3706 if (fixp->fx_addsy != NULL)
3708 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3709 code = BFD_RELOC_SPARC_PC10;
3711 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3712 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3713 code = BFD_RELOC_LO10; /* Unchanged. */
3717 case BFD_RELOC_SPARC13:
3718 code = BFD_RELOC_SPARC_GOT13;
3724 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3726 /* Nothing is aligned in DWARF debugging sections. */
3727 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3730 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3731 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3732 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3736 if (code == BFD_RELOC_SPARC_OLO10)
3737 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3739 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3740 if (reloc->howto == 0)
3742 as_bad_where (fixp->fx_file, fixp->fx_line,
3743 _("internal error: can't export reloc type %d (`%s')"),
3744 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3750 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3753 if (reloc->howto->pc_relative == 0
3754 || code == BFD_RELOC_SPARC_PC10
3755 || code == BFD_RELOC_SPARC_PC22)
3756 reloc->addend = fixp->fx_addnumber;
3757 else if (sparc_pic_code
3758 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3759 && fixp->fx_addsy != NULL
3760 && (S_IS_EXTERNAL (fixp->fx_addsy)
3761 || S_IS_WEAK (fixp->fx_addsy))
3762 && S_IS_DEFINED (fixp->fx_addsy)
3763 && ! S_IS_COMMON (fixp->fx_addsy))
3764 reloc->addend = fixp->fx_addnumber;
3766 reloc->addend = fixp->fx_offset - reloc->address;
3768 #else /* elf or coff */
3770 if (code != BFD_RELOC_32_PCREL_S2
3771 && code != BFD_RELOC_SPARC_WDISP22
3772 && code != BFD_RELOC_SPARC_WDISP16
3773 && code != BFD_RELOC_SPARC_WDISP19
3774 && code != BFD_RELOC_SPARC_WDISP10
3775 && code != BFD_RELOC_SPARC_WPLT30
3776 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3777 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3778 reloc->addend = fixp->fx_addnumber;
3779 else if (symbol_section_p (fixp->fx_addsy))
3780 reloc->addend = (section->vma
3781 + fixp->fx_addnumber
3782 + md_pcrel_from (fixp));
3784 reloc->addend = fixp->fx_offset;
3787 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3788 on the same location. */
3789 if (code == BFD_RELOC_SPARC_OLO10)
3791 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3794 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3796 = symbol_get_bfdsym (section_symbol (absolute_section));
3797 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3798 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3799 reloc->addend = fixp->tc_fix_data;
3805 /* We have no need to default values of symbols. */
3808 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3813 /* Round up a section size to the appropriate boundary. */
3816 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3819 /* This is not right for ELF; a.out wants it, and COFF will force
3820 the alignment anyways. */
3821 valueT align = ((valueT) 1
3822 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3825 /* Turn alignment value into a mask. */
3827 newsize = (size + align) & ~align;
3834 /* Exactly what point is a PC-relative offset relative TO?
3835 On the sparc, they're relative to the address of the offset, plus
3836 its size. This gets us to the following instruction.
3837 (??? Is this right? FIXME-SOON) */
3839 md_pcrel_from (fixS *fixP)
3843 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3844 if (! sparc_pic_code
3845 || fixP->fx_addsy == NULL
3846 || symbol_section_p (fixP->fx_addsy))
3847 ret += fixP->fx_size;
3851 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3862 for (shift = 0; (value & 1) == 0; value >>= 1)
3865 return (value == 1) ? shift : -1;
3868 /* Sort of like s_lcomm. */
3871 static int max_alignment = 15;
3875 s_reserve (int ignore ATTRIBUTE_UNUSED)
3885 name = input_line_pointer;
3886 c = get_symbol_end ();
3887 p = input_line_pointer;
3891 if (*input_line_pointer != ',')
3893 as_bad (_("Expected comma after name"));
3894 ignore_rest_of_line ();
3898 ++input_line_pointer;
3900 if ((size = get_absolute_expression ()) < 0)
3902 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3903 ignore_rest_of_line ();
3908 symbolP = symbol_find_or_make (name);
3911 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3912 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3914 as_bad (_("bad .reserve segment -- expected BSS segment"));
3918 if (input_line_pointer[2] == '.')
3919 input_line_pointer += 7;
3921 input_line_pointer += 6;
3924 if (*input_line_pointer == ',')
3926 ++input_line_pointer;
3929 if (*input_line_pointer == '\n')
3931 as_bad (_("missing alignment"));
3932 ignore_rest_of_line ();
3936 align = (int) get_absolute_expression ();
3939 if (align > max_alignment)
3941 align = max_alignment;
3942 as_warn (_("alignment too large; assuming %d"), align);
3948 as_bad (_("negative alignment"));
3949 ignore_rest_of_line ();
3955 temp = mylog2 (align);
3958 as_bad (_("alignment not a power of 2"));
3959 ignore_rest_of_line ();
3966 record_alignment (bss_section, align);
3971 if (!S_IS_DEFINED (symbolP)
3973 && S_GET_OTHER (symbolP) == 0
3974 && S_GET_DESC (symbolP) == 0
3981 segT current_seg = now_seg;
3982 subsegT current_subseg = now_subseg;
3984 /* Switch to bss. */
3985 subseg_set (bss_section, 1);
3989 frag_align (align, 0, 0);
3991 /* Detach from old frag. */
3992 if (S_GET_SEGMENT (symbolP) == bss_section)
3993 symbol_get_frag (symbolP)->fr_symbol = NULL;
3995 symbol_set_frag (symbolP, frag_now);
3996 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3997 (offsetT) size, (char *) 0);
4000 S_SET_SEGMENT (symbolP, bss_section);
4002 subseg_set (current_seg, current_subseg);
4005 S_SET_SIZE (symbolP, size);
4011 as_warn (_("Ignoring attempt to re-define symbol %s"),
4012 S_GET_NAME (symbolP));
4015 demand_empty_rest_of_line ();
4019 s_common (int ignore ATTRIBUTE_UNUSED)
4027 name = input_line_pointer;
4028 c = get_symbol_end ();
4029 /* Just after name is now '\0'. */
4030 p = input_line_pointer;
4033 if (*input_line_pointer != ',')
4035 as_bad (_("Expected comma after symbol-name"));
4036 ignore_rest_of_line ();
4041 input_line_pointer++;
4043 if ((temp = get_absolute_expression ()) < 0)
4045 as_bad (_(".COMMon length (%lu) out of range ignored"),
4046 (unsigned long) temp);
4047 ignore_rest_of_line ();
4052 symbolP = symbol_find_or_make (name);
4054 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4056 as_bad (_("Ignoring attempt to re-define symbol"));
4057 ignore_rest_of_line ();
4060 if (S_GET_VALUE (symbolP) != 0)
4062 if (S_GET_VALUE (symbolP) != (valueT) size)
4064 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4065 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4071 S_SET_VALUE (symbolP, (valueT) size);
4072 S_SET_EXTERNAL (symbolP);
4075 know (symbol_get_frag (symbolP) == &zero_address_frag);
4076 if (*input_line_pointer != ',')
4078 as_bad (_("Expected comma after common length"));
4079 ignore_rest_of_line ();
4082 input_line_pointer++;
4084 if (*input_line_pointer != '"')
4086 temp = get_absolute_expression ();
4089 if (temp > max_alignment)
4091 temp = max_alignment;
4092 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4098 as_bad (_("negative alignment"));
4099 ignore_rest_of_line ();
4104 if (symbol_get_obj (symbolP)->local)
4111 old_subsec = now_subseg;
4116 align = mylog2 (temp);
4120 as_bad (_("alignment not a power of 2"));
4121 ignore_rest_of_line ();
4125 record_alignment (bss_section, align);
4126 subseg_set (bss_section, 0);
4128 frag_align (align, 0, 0);
4129 if (S_GET_SEGMENT (symbolP) == bss_section)
4130 symbol_get_frag (symbolP)->fr_symbol = 0;
4131 symbol_set_frag (symbolP, frag_now);
4132 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4133 (offsetT) size, (char *) 0);
4135 S_SET_SEGMENT (symbolP, bss_section);
4136 S_CLEAR_EXTERNAL (symbolP);
4137 S_SET_SIZE (symbolP, size);
4138 subseg_set (old_sec, old_subsec);
4141 #endif /* OBJ_ELF */
4144 S_SET_VALUE (symbolP, (valueT) size);
4146 S_SET_ALIGN (symbolP, temp);
4147 S_SET_SIZE (symbolP, size);
4149 S_SET_EXTERNAL (symbolP);
4150 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4155 input_line_pointer++;
4156 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4157 if (*input_line_pointer == '.')
4158 input_line_pointer++;
4159 /* @@ Some say data, some say bss. */
4160 if (strncmp (input_line_pointer, "bss\"", 4)
4161 && strncmp (input_line_pointer, "data\"", 5))
4163 while (*--input_line_pointer != '"')
4165 input_line_pointer--;
4166 goto bad_common_segment;
4168 while (*input_line_pointer++ != '"')
4170 goto allocate_common;
4173 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4175 demand_empty_rest_of_line ();
4180 p = input_line_pointer;
4181 while (*p && *p != '\n')
4185 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4187 input_line_pointer = p;
4188 ignore_rest_of_line ();
4193 /* Handle the .empty pseudo-op. This suppresses the warnings about
4194 invalid delay slot usage. */
4197 s_empty (int ignore ATTRIBUTE_UNUSED)
4199 /* The easy way to implement is to just forget about the last
4205 s_seg (int ignore ATTRIBUTE_UNUSED)
4208 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4210 input_line_pointer += 6;
4214 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4216 input_line_pointer += 6;
4220 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4222 input_line_pointer += 7;
4226 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4228 input_line_pointer += 5;
4229 /* We only support 2 segments -- text and data -- for now, so
4230 things in the "bss segment" will have to go into data for now.
4231 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4232 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4235 as_bad (_("Unknown segment type"));
4236 demand_empty_rest_of_line ();
4242 subseg_set (data_section, 1);
4243 demand_empty_rest_of_line ();
4247 s_proc (int ignore ATTRIBUTE_UNUSED)
4249 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4251 ++input_line_pointer;
4253 ++input_line_pointer;
4256 /* This static variable is set by s_uacons to tell sparc_cons_align
4257 that the expression does not need to be aligned. */
4259 static int sparc_no_align_cons = 0;
4261 /* This static variable is set by sparc_cons to emit requested types
4262 of relocations in cons_fix_new_sparc. */
4264 static const char *sparc_cons_special_reloc;
4266 /* This handles the unaligned space allocation pseudo-ops, such as
4267 .uaword. .uaword is just like .word, but the value does not need
4271 s_uacons (int bytes)
4273 /* Tell sparc_cons_align not to align this value. */
4274 sparc_no_align_cons = 1;
4276 sparc_no_align_cons = 0;
4279 /* This handles the native word allocation pseudo-op .nword.
4280 For sparc_arch_size 32 it is equivalent to .word, for
4281 sparc_arch_size 64 it is equivalent to .xword. */
4284 s_ncons (int bytes ATTRIBUTE_UNUSED)
4286 cons (sparc_arch_size == 32 ? 4 : 8);
4290 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4294 .register %g[2367],{#scratch|symbolname|#ignore}
4298 s_register (int ignore ATTRIBUTE_UNUSED)
4303 const char *regname;
4305 if (input_line_pointer[0] != '%'
4306 || input_line_pointer[1] != 'g'
4307 || ((input_line_pointer[2] & ~1) != '2'
4308 && (input_line_pointer[2] & ~1) != '6')
4309 || input_line_pointer[3] != ',')
4310 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4311 reg = input_line_pointer[2] - '0';
4312 input_line_pointer += 4;
4314 if (*input_line_pointer == '#')
4316 ++input_line_pointer;
4317 regname = input_line_pointer;
4318 c = get_symbol_end ();
4319 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4320 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4321 if (regname[0] == 'i')
4328 regname = input_line_pointer;
4329 c = get_symbol_end ();
4331 if (sparc_arch_size == 64)
4335 if ((regname && globals[reg] != (symbolS *) 1
4336 && strcmp (S_GET_NAME (globals[reg]), regname))
4337 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4338 as_bad (_("redefinition of global register"));
4342 if (regname == NULL)
4343 globals[reg] = (symbolS *) 1;
4348 if (symbol_find (regname))
4349 as_bad (_("Register symbol %s already defined."),
4352 globals[reg] = symbol_make (regname);
4353 flags = symbol_get_bfdsym (globals[reg])->flags;
4355 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4356 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4357 flags |= BSF_GLOBAL;
4358 symbol_get_bfdsym (globals[reg])->flags = flags;
4359 S_SET_VALUE (globals[reg], (valueT) reg);
4360 S_SET_ALIGN (globals[reg], reg);
4361 S_SET_SIZE (globals[reg], 0);
4362 /* Although we actually want undefined_section here,
4363 we have to use absolute_section, because otherwise
4364 generic as code will make it a COM section.
4365 We fix this up in sparc_adjust_symtab. */
4366 S_SET_SEGMENT (globals[reg], absolute_section);
4367 S_SET_OTHER (globals[reg], 0);
4368 elf_symbol (symbol_get_bfdsym (globals[reg]))
4369 ->internal_elf_sym.st_info =
4370 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4371 elf_symbol (symbol_get_bfdsym (globals[reg]))
4372 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4377 *input_line_pointer = c;
4379 demand_empty_rest_of_line ();
4382 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4383 symbols which need it. */
4386 sparc_adjust_symtab (void)
4390 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4392 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4393 ->internal_elf_sym.st_info) != STT_REGISTER)
4396 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4397 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4400 S_SET_SEGMENT (sym, undefined_section);
4405 /* If the --enforce-aligned-data option is used, we require .word,
4406 et. al., to be aligned correctly. We do it by setting up an
4407 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4408 no unexpected alignment was introduced.
4410 The SunOS and Solaris native assemblers enforce aligned data by
4411 default. We don't want to do that, because gcc can deliberately
4412 generate misaligned data if the packed attribute is used. Instead,
4413 we permit misaligned data by default, and permit the user to set an
4414 option to check for it. */
4417 sparc_cons_align (int nbytes)
4421 /* Only do this if we are enforcing aligned data. */
4422 if (! enforce_aligned_data)
4425 /* Don't align if this is an unaligned pseudo-op. */
4426 if (sparc_no_align_cons)
4429 nalign = mylog2 (nbytes);
4433 gas_assert (nalign > 0);
4435 if (now_seg == absolute_section)
4437 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4438 as_bad (_("misaligned data"));
4442 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4443 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4445 record_alignment (now_seg, nalign);
4448 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4451 sparc_handle_align (fragS *fragp)
4456 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4458 switch (fragp->fr_type)
4462 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4466 p = fragp->fr_literal + fragp->fr_fix;
4477 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4479 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4480 if (INSN_BIG_ENDIAN)
4481 number_to_chars_bigendian (p, wval, 4);
4483 number_to_chars_littleendian (p, wval, 4);
4489 if (INSN_BIG_ENDIAN)
4490 number_to_chars_bigendian (p, 0x01000000, 4);
4492 number_to_chars_littleendian (p, 0x01000000, 4);
4494 fragp->fr_fix += fix;
4504 /* Some special processing for a Sparc ELF file. */
4507 sparc_elf_final_processing (void)
4509 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4510 sort of BFD interface for this. */
4511 if (sparc_arch_size == 64)
4513 switch (sparc_memory_model)
4516 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4519 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4525 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4526 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4527 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4528 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4529 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4530 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4534 sparc_cons (expressionS *exp, int size)
4539 sparc_cons_special_reloc = NULL;
4540 save = input_line_pointer;
4541 if (input_line_pointer[0] == '%'
4542 && input_line_pointer[1] == 'r'
4543 && input_line_pointer[2] == '_')
4545 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4547 input_line_pointer += 7;
4548 sparc_cons_special_reloc = "disp";
4550 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4552 if (size != 4 && size != 8)
4553 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4556 input_line_pointer += 6;
4557 sparc_cons_special_reloc = "plt";
4560 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4562 if (size != 4 && size != 8)
4563 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4566 input_line_pointer += 13;
4567 sparc_cons_special_reloc = "tls_dtpoff";
4570 if (sparc_cons_special_reloc)
4577 if (*input_line_pointer != '8')
4579 input_line_pointer--;
4582 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4586 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4590 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4600 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4601 sparc_cons_special_reloc, size * 8, size);
4605 input_line_pointer += 2;
4606 if (*input_line_pointer != '(')
4608 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4609 sparc_cons_special_reloc, size * 8);
4616 input_line_pointer = save;
4617 sparc_cons_special_reloc = NULL;
4622 char *end = ++input_line_pointer;
4625 while (! is_end_of_line[(c = *end)])
4639 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4640 sparc_cons_special_reloc, size * 8);
4646 if (input_line_pointer != end)
4648 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4649 sparc_cons_special_reloc, size * 8);
4653 input_line_pointer++;
4655 c = *input_line_pointer;
4656 if (! is_end_of_line[c] && c != ',')
4657 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4658 sparc_cons_special_reloc, size * 8);
4664 if (sparc_cons_special_reloc == NULL)
4670 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4671 reloc for a cons. We could use the definition there, except that
4672 we want to handle little endian relocs specially. */
4675 cons_fix_new_sparc (fragS *frag,
4677 unsigned int nbytes,
4680 bfd_reloc_code_real_type r;
4682 r = (nbytes == 1 ? BFD_RELOC_8 :
4683 (nbytes == 2 ? BFD_RELOC_16 :
4684 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4686 if (target_little_endian_data
4688 && now_seg->flags & SEC_ALLOC)
4689 r = BFD_RELOC_SPARC_REV32;
4691 if (sparc_cons_special_reloc)
4693 if (*sparc_cons_special_reloc == 'd')
4696 case 1: r = BFD_RELOC_8_PCREL; break;
4697 case 2: r = BFD_RELOC_16_PCREL; break;
4698 case 4: r = BFD_RELOC_32_PCREL; break;
4699 case 8: r = BFD_RELOC_64_PCREL; break;
4702 else if (*sparc_cons_special_reloc == 'p')
4705 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4706 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4711 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4712 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4715 else if (sparc_no_align_cons)
4719 case 2: r = BFD_RELOC_SPARC_UA16; break;
4720 case 4: r = BFD_RELOC_SPARC_UA32; break;
4721 case 8: r = BFD_RELOC_SPARC_UA64; break;
4726 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4727 sparc_cons_special_reloc = NULL;
4731 sparc_cfi_frame_initial_instructions (void)
4733 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4737 sparc_regname_to_dw2regnum (char *regname)
4745 p = strchr (q, regname[0]);
4748 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4750 return (p - q) * 8 + regname[1] - '0';
4752 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4754 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4756 if (regname[0] == 'f' || regname[0] == 'r')
4758 unsigned int regnum;
4760 regnum = strtoul (regname + 1, &q, 10);
4763 if (regnum >= ((regname[0] == 'f'
4764 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4767 if (regname[0] == 'f')
4770 if (regnum >= 64 && (regnum & 1))
4779 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4781 sparc_cons_special_reloc = "disp";
4782 sparc_no_align_cons = 1;
4783 emit_expr (exp, nbytes);
4784 sparc_no_align_cons = 0;
4785 sparc_cons_special_reloc = NULL;