1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
51 #define DEFAULT_ARCH "sparclite"
53 static char *default_arch = DEFAULT_ARCH;
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
57 static int default_init_p;
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
76 /* The currently selected v9 memory model. Currently only used for
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
87 static int hwcap_allowed;
89 static int architecture_requested;
90 static int warn_on_bump;
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
103 /* Non-zero if we are generating PIC code. */
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
109 extern int target_big_endian;
111 static int target_little_endian_data;
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
141 static void s_register (int);
144 const pseudo_typeS md_pseudo_table[] =
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
154 {"reserve", s_reserve, 0},
156 {"skip", s_space, 0},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
187 const char line_separator_chars[] = ";";
189 /* Chars that can be used to separate mant from exp in floating point
191 const char EXP_CHARS[] = "eE";
193 /* Chars that mean this number is a floating point constant.
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
207 unsigned long opcode;
208 struct nlist *nlistp;
212 bfd_reloc_code_real_type reloc;
215 struct sparc_it the_insn, set_insn;
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
224 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
227 static struct sparc_arch {
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
248 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
249 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
250 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
254 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
255 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
256 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
257 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
258 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
259 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
260 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
261 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
262 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
263 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
264 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
265 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
266 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
269 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
270 { NULL, NULL, v8, 0, 0, 0 }
273 /* Variant of default_arch */
274 static enum sparc_arch_types default_arch_type;
276 static struct sparc_arch *
277 lookup_arch (char *name)
279 struct sparc_arch *sa;
281 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
282 if (strcmp (sa->name, name) == 0)
284 if (sa->name == NULL)
289 /* Initialize the default opcode arch and word size from the default
290 architecture name. */
293 init_default_arch (void)
295 struct sparc_arch *sa = lookup_arch (default_arch);
298 || sa->default_arch_size == 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
301 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
302 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size = sparc_arch_size = sa->default_arch_size;
306 default_arch_type = sa->arch_type;
309 /* Called by TARGET_FORMAT. */
312 sparc_target_format (void)
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p)
317 init_default_arch ();
321 return "a.out-sparc-netbsd";
324 if (target_big_endian)
325 return "a.out-sunos-big";
326 else if (default_arch_type == sparc86x && target_little_endian_data)
327 return "a.out-sunos-big";
329 return "a.out-sparc-little";
331 return "a.out-sunos-big";
342 return "coff-sparc-lynx";
349 return "elf32-sparc-vxworks";
353 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
364 * Warn on architecture bumps. See also -A.
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
392 * If -bump is specified, a warning is printing when bumping to
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
414 const char *md_shortopts = "A:K:VQ:sq";
417 const char *md_shortopts = "A:k";
419 const char *md_shortopts = "A:";
422 struct option md_longopts[] = {
423 #define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument, NULL, OPTION_BUMP},
425 #define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument, NULL, OPTION_SPARC},
427 #define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument, NULL, OPTION_XARCH},
430 #define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument, NULL, OPTION_32},
432 #define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument, NULL, OPTION_64},
434 #define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument, NULL, OPTION_TSO},
436 #define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument, NULL, OPTION_PSO},
438 #define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument, NULL, OPTION_RMO},
441 #ifdef SPARC_BIENDIAN
442 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
444 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
447 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
449 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
452 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
454 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
457 #define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument, NULL, OPTION_RELAX},
459 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
461 {NULL, no_argument, NULL, 0}
464 size_t md_longopts_size = sizeof (md_longopts);
467 md_parse_option (int c, char *arg)
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p)
472 init_default_arch ();
478 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
483 if (strncmp (arg, "v9", 2) != 0)
484 md_parse_option (OPTION_32, NULL);
486 md_parse_option (OPTION_64, NULL);
492 struct sparc_arch *sa;
493 enum sparc_opcode_arch_val opcode_arch;
495 sa = lookup_arch (arg);
497 || ! sa->user_option_p)
499 if (c == OPTION_XARCH)
500 as_bad (_("invalid architecture -xarch=%s"), arg);
502 as_bad (_("invalid architecture -A%s"), arg);
506 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
507 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
508 as_fatal (_("Bad opcode table, broken assembler."));
510 if (!architecture_requested
511 || opcode_arch > max_architecture)
512 max_architecture = opcode_arch;
513 hwcap_allowed |= sa->hwcap_allowed;
514 architecture_requested = 1;
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
522 case OPTION_ENFORCE_ALIGNED_DATA:
523 enforce_aligned_data = 1;
526 #ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN:
528 target_big_endian = 0;
529 if (default_arch_type != sparclet)
530 as_fatal ("This target does not support -EL");
532 case OPTION_LITTLE_ENDIAN_DATA:
533 target_little_endian_data = 1;
534 target_big_endian = 0;
535 if (default_arch_type != sparc86x
536 && default_arch_type != v9)
537 as_fatal ("This target does not support --little-endian-data");
539 case OPTION_BIG_ENDIAN:
540 target_big_endian = 1;
554 const char **list, **l;
556 sparc_arch_size = c == OPTION_32 ? 32 : 64;
557 list = bfd_target_list ();
558 for (l = list; *l != NULL; l++)
560 if (sparc_arch_size == 32)
562 if (CONST_STRNEQ (*l, "elf32-sparc"))
567 if (CONST_STRNEQ (*l, "elf64-sparc"))
572 as_fatal (_("No compiled in support for %d bit object file format"),
576 if (sparc_arch_size == 64
577 && max_architecture < SPARC_OPCODE_ARCH_V9)
578 max_architecture = SPARC_OPCODE_ARCH_V9;
583 sparc_memory_model = MM_TSO;
587 sparc_memory_model = MM_PSO;
591 sparc_memory_model = MM_RMO;
599 /* Qy - do emit .comment
600 Qn - do not emit .comment. */
604 /* Use .stab instead of .stab.excl. */
608 /* quick -- Native assembler does fewer checks. */
612 if (strcmp (arg, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
618 case OPTION_NO_UNDECLARED_REGS:
619 no_undeclared_regs = 1;
622 case OPTION_UNDECLARED_REGS:
623 no_undeclared_regs = 0;
631 case OPTION_NO_RELAX:
643 md_show_usage (FILE *stream)
645 const struct sparc_arch *arch;
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p)
651 init_default_arch ();
653 fprintf (stream, _("SPARC options:\n"));
655 for (arch = &sparc_arch_table[0]; arch->name; arch++)
657 if (!arch->user_option_p)
659 if (arch != &sparc_arch_table[0])
660 fprintf (stream, " | ");
661 if (column + strlen (arch->name) > 70)
664 fputc ('\n', stream);
666 column += 5 + 2 + strlen (arch->name);
667 fprintf (stream, "-A%s", arch->name);
669 for (arch = &sparc_arch_table[0]; arch->name; arch++)
671 if (!arch->user_option_p)
673 fprintf (stream, " | ");
674 if (column + strlen (arch->name) > 65)
677 fputc ('\n', stream);
679 column += 5 + 7 + strlen (arch->name);
680 fprintf (stream, "-xarch=%s", arch->name);
682 fprintf (stream, _("\n\
683 specify variant of SPARC architecture\n\
684 -bump warn when assembler switches architectures\n\
686 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
687 -relax relax jumps and branches (default)\n\
688 -no-relax avoid changing any jumps and branches\n"));
690 fprintf (stream, _("\
691 -k generate PIC\n"));
694 fprintf (stream, _("\
695 -32 create 32 bit object file\n\
696 -64 create 64 bit object file\n"));
697 fprintf (stream, _("\
698 [default is %d]\n"), default_arch_size);
699 fprintf (stream, _("\
700 -TSO use Total Store Ordering\n\
701 -PSO use Partial Store Ordering\n\
702 -RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream, _("\
704 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
705 fprintf (stream, _("\
706 -KPIC generate PIC\n\
707 -V print assembler version number\n\
708 -undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710 -no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
716 #ifdef SPARC_BIENDIAN
717 fprintf (stream, _("\
718 -EL generate code for a little endian machine\n\
719 -EB generate code for a big endian machine\n\
720 --little-endian-data generate code for a machine having big endian\n\
721 instructions and little endian data.\n"));
725 /* Native operand size opcode translation. */
731 } native_op_table[] =
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
746 /* sparc64 privileged and hyperprivileged registers. */
748 struct priv_reg_entry
754 struct priv_reg_entry priv_reg_table[] =
774 {"", -1}, /* End marker. */
777 struct priv_reg_entry hpriv_reg_table[] =
785 {"", -1}, /* End marker. */
788 /* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
791 struct priv_reg_entry v9a_asr_table[] =
794 {"sys_tick_cmpr", 25},
798 {"softint_clear", 21},
808 {"clear_softint", 21},
809 {"", -1}, /* End marker. */
813 cmp_reg_entry (const void *parg, const void *qarg)
815 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
816 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
818 return strcmp (q->name, p->name);
821 /* This function is called once, at assembler startup time. It should
822 set up all the tables, etc. that the MD part of the assembler will
828 register const char *retval = NULL;
830 register unsigned int i = 0;
832 /* We don't get a chance to initialize anything before md_parse_option
833 is called, and it may not be called, so handle default initialization
834 now if not already done. */
835 if (! default_init_p)
836 init_default_arch ();
838 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
839 op_hash = hash_new ();
841 while (i < (unsigned int) sparc_num_opcodes)
843 const char *name = sparc_opcodes[i].name;
844 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
847 as_bad (_("Internal error: can't hash `%s': %s\n"),
848 sparc_opcodes[i].name, retval);
853 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
855 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
856 sparc_opcodes[i].name, sparc_opcodes[i].args);
861 while (i < (unsigned int) sparc_num_opcodes
862 && !strcmp (sparc_opcodes[i].name, name));
865 for (i = 0; native_op_table[i].name; i++)
867 const struct sparc_opcode *insn;
868 char *name = ((sparc_arch_size == 32)
869 ? native_op_table[i].name32
870 : native_op_table[i].name64);
871 insn = (struct sparc_opcode *) hash_find (op_hash, name);
874 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
875 name, native_op_table[i].name);
880 retval = hash_insert (op_hash, native_op_table[i].name,
884 as_bad (_("Internal error: can't hash `%s': %s\n"),
885 sparc_opcodes[i].name, retval);
892 as_fatal (_("Broken assembler. No assembly attempted."));
894 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
895 sizeof (priv_reg_table[0]), cmp_reg_entry);
897 /* If -bump, record the architecture level at which we start issuing
898 warnings. The behaviour is different depending upon whether an
899 architecture was explicitly specified. If it wasn't, we issue warnings
900 for all upwards bumps. If it was, we don't start issuing warnings until
901 we need to bump beyond the requested architecture or when we bump between
902 conflicting architectures. */
905 && architecture_requested)
907 /* `max_architecture' records the requested architecture.
908 Issue warnings if we go above it. */
909 warn_after_architecture = max_architecture;
911 /* Find the highest architecture level that doesn't conflict with
912 the requested one. */
913 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
914 max_architecture > warn_after_architecture;
916 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
917 warn_after_architecture))
922 /* Called after all assembly has been done. */
927 unsigned long mach = bfd_mach_sparc;
929 if (sparc_arch_size == 64)
930 switch (current_architecture)
932 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
933 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
934 default: mach = bfd_mach_sparc_v9; break;
937 switch (current_architecture)
939 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
940 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
941 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
942 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
943 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
944 be but for now it is (since that's the way it's always been
948 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
950 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
952 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
956 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
959 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
963 /* Sign-extend the value from the architecture word size, so that
964 0xffffffff is always considered -1 on sparc32. */
965 if (sparc_arch_size == 32)
967 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
968 val = ((val & U0xffffffff) ^ sign) - sign;
977 /* Return non-zero if VAL is in the range 0 to MAX. */
980 in_unsigned_range (bfd_vma val, bfd_vma max)
987 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
988 (e.g. -15 to +31). */
991 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
997 if (val < ~(max >> 1))
1003 sparc_ffs (unsigned int mask)
1010 for (i = 0; (mask & 1) == 0; ++i)
1015 /* Implement big shift right. */
1017 BSR (bfd_vma val, int amount)
1019 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1020 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1021 return val >> amount;
1024 /* For communication between sparc_ip and get_expression. */
1025 static char *expr_end;
1027 /* Values for `special_case'.
1028 Instructions that require wierd handling because they're longer than
1030 #define SPECIAL_CASE_NONE 0
1031 #define SPECIAL_CASE_SET 1
1032 #define SPECIAL_CASE_SETSW 2
1033 #define SPECIAL_CASE_SETX 3
1034 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1035 #define SPECIAL_CASE_FDIV 4
1037 /* Bit masks of various insns. */
1038 #define NOP_INSN 0x01000000
1039 #define OR_INSN 0x80100000
1040 #define XOR_INSN 0x80180000
1041 #define FMOVS_INSN 0x81A00020
1042 #define SETHI_INSN 0x01000000
1043 #define SLLX_INSN 0x81281000
1044 #define SRA_INSN 0x81380000
1046 /* The last instruction to be assembled. */
1047 static const struct sparc_opcode *last_insn;
1048 /* The assembled opcode of `last_insn'. */
1049 static unsigned long last_opcode;
1051 /* Handle the set and setuw synthetic instructions. */
1054 synthetize_setuw (const struct sparc_opcode *insn)
1056 int need_hi22_p = 0;
1057 int rd = (the_insn.opcode & RD (~0)) >> 25;
1059 if (the_insn.exp.X_op == O_constant)
1061 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1063 if (sizeof (offsetT) > 4
1064 && (the_insn.exp.X_add_number < 0
1065 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1066 as_warn (_("set: number not in 0..4294967295 range"));
1070 if (sizeof (offsetT) > 4
1071 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1072 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1073 as_warn (_("set: number not in -2147483648..4294967295 range"));
1074 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1078 /* See if operand is absolute and small; skip sethi if so. */
1079 if (the_insn.exp.X_op != O_constant
1080 || the_insn.exp.X_add_number >= (1 << 12)
1081 || the_insn.exp.X_add_number < -(1 << 12))
1083 the_insn.opcode = (SETHI_INSN | RD (rd)
1084 | ((the_insn.exp.X_add_number >> 10)
1085 & (the_insn.exp.X_op == O_constant
1087 the_insn.reloc = (the_insn.exp.X_op != O_constant
1088 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1089 output_insn (insn, &the_insn);
1093 /* See if operand has no low-order bits; skip OR if so. */
1094 if (the_insn.exp.X_op != O_constant
1095 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1098 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1100 | (the_insn.exp.X_add_number
1101 & (the_insn.exp.X_op != O_constant
1102 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1103 the_insn.reloc = (the_insn.exp.X_op != O_constant
1104 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1105 output_insn (insn, &the_insn);
1109 /* Handle the setsw synthetic instruction. */
1112 synthetize_setsw (const struct sparc_opcode *insn)
1116 rd = (the_insn.opcode & RD (~0)) >> 25;
1118 if (the_insn.exp.X_op != O_constant)
1120 synthetize_setuw (insn);
1122 /* Need to sign extend it. */
1123 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1124 the_insn.reloc = BFD_RELOC_NONE;
1125 output_insn (insn, &the_insn);
1129 if (sizeof (offsetT) > 4
1130 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1131 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1132 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1134 low32 = the_insn.exp.X_add_number;
1138 synthetize_setuw (insn);
1144 the_insn.reloc = BFD_RELOC_NONE;
1145 /* See if operand is absolute and small; skip sethi if so. */
1146 if (low32 < -(1 << 12))
1148 the_insn.opcode = (SETHI_INSN | RD (rd)
1149 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1150 output_insn (insn, &the_insn);
1151 low32 = 0x1c00 | (low32 & 0x3ff);
1152 opc = RS1 (rd) | XOR_INSN;
1155 the_insn.opcode = (opc | RD (rd) | IMMED
1156 | (low32 & 0x1fff));
1157 output_insn (insn, &the_insn);
1160 /* Handle the setsw synthetic instruction. */
1163 synthetize_setx (const struct sparc_opcode *insn)
1165 int upper32, lower32;
1166 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1167 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1169 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1170 int need_xor10_p = 0;
1172 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1173 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1174 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1177 upper_dstreg = tmpreg;
1178 /* The tmp reg should not be the dst reg. */
1179 if (tmpreg == dstreg)
1180 as_warn (_("setx: temporary register same as destination register"));
1182 /* ??? Obviously there are other optimizations we can do
1183 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1184 doing some of these. Later. If you do change things, try to
1185 change all of this to be table driven as well. */
1186 /* What to output depends on the number if it's constant.
1187 Compute that first, then output what we've decided upon. */
1188 if (the_insn.exp.X_op != O_constant)
1190 if (sparc_arch_size == 32)
1192 /* When arch size is 32, we want setx to be equivalent
1193 to setuw for anything but constants. */
1194 the_insn.exp.X_add_number &= 0xffffffff;
1195 synthetize_setuw (insn);
1198 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1204 /* Reset X_add_number, we've extracted it as upper32/lower32.
1205 Otherwise fixup_segment will complain about not being able to
1206 write an 8 byte number in a 4 byte field. */
1207 the_insn.exp.X_add_number = 0;
1209 /* Only need hh22 if `or' insn can't handle constant. */
1210 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1213 /* Does bottom part (after sethi) have bits? */
1214 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1215 /* No hh22, but does upper32 still have bits we can't set
1217 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1220 /* If the lower half is all zero, we build the upper half directly
1221 into the dst reg. */
1223 /* Need lower half if number is zero or 0xffffffff00000000. */
1224 || (! need_hh22_p && ! need_hm10_p))
1226 /* No need for sethi if `or' insn can handle constant. */
1227 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1228 /* Note that we can't use a negative constant in the `or'
1229 insn unless the upper 32 bits are all ones. */
1230 || (lower32 < 0 && upper32 != -1)
1231 || (lower32 >= 0 && upper32 == -1))
1234 if (need_hi22_p && upper32 == -1)
1237 /* Does bottom part (after sethi) have bits? */
1238 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1240 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1241 /* Need `or' if we didn't set anything else. */
1242 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1246 /* Output directly to dst reg if lower 32 bits are all zero. */
1247 upper_dstreg = dstreg;
1250 if (!upper_dstreg && dstreg)
1251 as_warn (_("setx: illegal temporary register g0"));
1255 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1256 | ((upper32 >> 10) & 0x3fffff));
1257 the_insn.reloc = (the_insn.exp.X_op != O_constant
1258 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1259 output_insn (insn, &the_insn);
1264 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1265 | (((need_xor10_p ? ~lower32 : lower32)
1266 >> 10) & 0x3fffff));
1267 the_insn.reloc = (the_insn.exp.X_op != O_constant
1268 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1269 output_insn (insn, &the_insn);
1274 the_insn.opcode = (OR_INSN
1275 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1278 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1279 the_insn.reloc = (the_insn.exp.X_op != O_constant
1280 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1281 output_insn (insn, &the_insn);
1286 /* FIXME: One nice optimization to do here is to OR the low part
1287 with the highpart if hi22 isn't needed and the low part is
1289 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1292 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1293 the_insn.reloc = (the_insn.exp.X_op != O_constant
1294 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1295 output_insn (insn, &the_insn);
1298 /* If we needed to build the upper part, shift it into place. */
1299 if (need_hh22_p || need_hm10_p)
1301 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1303 the_insn.reloc = BFD_RELOC_NONE;
1304 output_insn (insn, &the_insn);
1307 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1310 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1311 | 0x1c00 | (lower32 & 0x3ff));
1312 the_insn.reloc = BFD_RELOC_NONE;
1313 output_insn (insn, &the_insn);
1316 /* If we needed to build both upper and lower parts, OR them together. */
1317 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1319 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1321 the_insn.reloc = BFD_RELOC_NONE;
1322 output_insn (insn, &the_insn);
1326 /* Main entry point to assemble one instruction. */
1329 md_assemble (char *str)
1331 const struct sparc_opcode *insn;
1335 special_case = sparc_ip (str, &insn);
1339 /* We warn about attempts to put a floating point branch in a delay slot,
1340 unless the delay slot has been annulled. */
1341 if (last_insn != NULL
1342 && (insn->flags & F_FBR) != 0
1343 && (last_insn->flags & F_DELAYED) != 0
1344 /* ??? This test isn't completely accurate. We assume anything with
1345 F_{UNBR,CONDBR,FBR} set is annullable. */
1346 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1347 || (last_opcode & ANNUL) == 0))
1348 as_warn (_("FP branch in delay slot"));
1350 /* SPARC before v9 requires a nop instruction between a floating
1351 point instruction and a floating point branch. We insert one
1352 automatically, with a warning. */
1353 if (max_architecture < SPARC_OPCODE_ARCH_V9
1354 && last_insn != NULL
1355 && (insn->flags & F_FBR) != 0
1356 && (last_insn->flags & F_FLOAT) != 0)
1358 struct sparc_it nop_insn;
1360 nop_insn.opcode = NOP_INSN;
1361 nop_insn.reloc = BFD_RELOC_NONE;
1362 output_insn (insn, &nop_insn);
1363 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1366 switch (special_case)
1368 case SPECIAL_CASE_NONE:
1370 output_insn (insn, &the_insn);
1373 case SPECIAL_CASE_SETSW:
1374 synthetize_setsw (insn);
1377 case SPECIAL_CASE_SET:
1378 synthetize_setuw (insn);
1381 case SPECIAL_CASE_SETX:
1382 synthetize_setx (insn);
1385 case SPECIAL_CASE_FDIV:
1387 int rd = (the_insn.opcode >> 25) & 0x1f;
1389 output_insn (insn, &the_insn);
1391 /* According to information leaked from Sun, the "fdiv" instructions
1392 on early SPARC machines would produce incorrect results sometimes.
1393 The workaround is to add an fmovs of the destination register to
1394 itself just after the instruction. This was true on machines
1395 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1396 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1397 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1398 output_insn (insn, &the_insn);
1403 as_fatal (_("failed special case insn sanity check"));
1408 get_hwcap_name (int mask)
1410 if (mask & HWCAP_MUL32)
1412 if (mask & HWCAP_DIV32)
1414 if (mask & HWCAP_FSMULD)
1416 if (mask & HWCAP_V8PLUS)
1418 if (mask & HWCAP_POPC)
1420 if (mask & HWCAP_VIS)
1422 if (mask & HWCAP_VIS2)
1424 if (mask & HWCAP_ASI_BLK_INIT)
1425 return "ASIBlkInit";
1426 if (mask & HWCAP_FMAF)
1428 if (mask & HWCAP_VIS3)
1430 if (mask & HWCAP_HPC)
1432 if (mask & HWCAP_RANDOM)
1434 if (mask & HWCAP_TRANS)
1436 if (mask & HWCAP_FJFMAU)
1438 if (mask & HWCAP_IMA)
1440 if (mask & HWCAP_ASI_CACHE_SPARING)
1442 if (mask & HWCAP_AES)
1444 if (mask & HWCAP_DES)
1446 if (mask & HWCAP_KASUMI)
1448 if (mask & HWCAP_CAMELLIA)
1450 if (mask & HWCAP_MD5)
1452 if (mask & HWCAP_SHA1)
1454 if (mask & HWCAP_SHA256)
1456 if (mask & HWCAP_SHA512)
1458 if (mask & HWCAP_MPMUL)
1460 if (mask & HWCAP_MONT)
1462 if (mask & HWCAP_PAUSE)
1464 if (mask & HWCAP_CBCOND)
1466 if (mask & HWCAP_CRC32C)
1471 /* Subroutine of md_assemble to do the actual parsing. */
1474 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1476 char *error_message = "";
1480 const struct sparc_opcode *insn;
1482 unsigned long opcode;
1483 unsigned int mask = 0;
1487 int special_case = SPECIAL_CASE_NONE;
1494 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1511 as_bad (_("Unknown opcode: `%s'"), str);
1513 return special_case;
1515 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1519 as_bad (_("Unknown opcode: `%s'"), str);
1520 return special_case;
1530 opcode = insn->match;
1531 memset (&the_insn, '\0', sizeof (the_insn));
1532 the_insn.reloc = BFD_RELOC_NONE;
1535 /* Build the opcode, checking as we go to make sure that the
1537 for (args = insn->args;; ++args)
1545 /* Parse a series of masks. */
1552 if (! parse_keyword_arg (sparc_encode_membar, &s,
1555 error_message = _(": invalid membar mask name");
1561 if (*s == '|' || *s == '+')
1569 if (! parse_const_expr_arg (&s, &kmask))
1571 error_message = _(": invalid membar mask expression");
1574 if (kmask < 0 || kmask > 127)
1576 error_message = _(": invalid membar mask number");
1581 opcode |= MEMBAR (kmask);
1589 if (! parse_const_expr_arg (&s, &smask))
1591 error_message = _(": invalid siam mode expression");
1594 if (smask < 0 || smask > 7)
1596 error_message = _(": invalid siam mode number");
1607 /* Parse a prefetch function. */
1610 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1612 error_message = _(": invalid prefetch function name");
1618 if (! parse_const_expr_arg (&s, &fcn))
1620 error_message = _(": invalid prefetch function expression");
1623 if (fcn < 0 || fcn > 31)
1625 error_message = _(": invalid prefetch function number");
1635 /* Parse a sparc64 privileged register. */
1638 struct priv_reg_entry *p = priv_reg_table;
1639 unsigned int len = 9999999; /* Init to make gcc happy. */
1642 while (p->name[0] > s[0])
1644 while (p->name[0] == s[0])
1646 len = strlen (p->name);
1647 if (strncmp (p->name, s, len) == 0)
1651 if (p->name[0] != s[0])
1653 error_message = _(": unrecognizable privileged register");
1657 opcode |= (p->regnum << 14);
1659 opcode |= (p->regnum << 25);
1665 error_message = _(": unrecognizable privileged register");
1671 /* Parse a sparc64 hyperprivileged register. */
1674 struct priv_reg_entry *p = hpriv_reg_table;
1675 unsigned int len = 9999999; /* Init to make gcc happy. */
1678 while (p->name[0] > s[0])
1680 while (p->name[0] == s[0])
1682 len = strlen (p->name);
1683 if (strncmp (p->name, s, len) == 0)
1687 if (p->name[0] != s[0])
1689 error_message = _(": unrecognizable hyperprivileged register");
1693 opcode |= (p->regnum << 14);
1695 opcode |= (p->regnum << 25);
1701 error_message = _(": unrecognizable hyperprivileged register");
1707 /* Parse a v9a/v9b ancillary state register. */
1710 struct priv_reg_entry *p = v9a_asr_table;
1711 unsigned int len = 9999999; /* Init to make gcc happy. */
1714 while (p->name[0] > s[0])
1716 while (p->name[0] == s[0])
1718 len = strlen (p->name);
1719 if (strncmp (p->name, s, len) == 0)
1723 if (p->name[0] != s[0])
1725 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1728 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1730 error_message = _(": rd on write only ancillary state register");
1734 && (insn->architecture
1735 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1737 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1738 error_message = _(": unrecognizable v9a ancillary state register");
1742 opcode |= (p->regnum << 14);
1744 opcode |= (p->regnum << 25);
1750 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1756 if (strncmp (s, "%asr", 4) == 0)
1764 while (ISDIGIT (*s))
1766 num = num * 10 + *s - '0';
1770 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1772 if (num < 16 || 31 < num)
1774 error_message = _(": asr number must be between 16 and 31");
1780 if (num < 0 || 31 < num)
1782 error_message = _(": asr number must be between 0 and 31");
1787 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1792 error_message = _(": expecting %asrN");
1799 the_insn.reloc = BFD_RELOC_SPARC_11;
1803 the_insn.reloc = BFD_RELOC_SPARC_10;
1809 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1814 if (s[0] == '0' && s[1] == 'x')
1817 while (ISXDIGIT (*s))
1820 num |= hex_value (*s);
1826 while (ISDIGIT (*s))
1828 num = num * 10 + *s - '0';
1832 if (num < 0 || num > 31)
1834 error_message = _(": crypto immediate must be between 0 and 31");
1838 opcode |= RS3 (num);
1843 error_message = _(": expecting crypto immediate");
1848 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1849 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1850 the_insn.reloc = BFD_RELOC_SPARC_5;
1852 the_insn.reloc = BFD_RELOC_SPARC13;
1853 /* These fields are unsigned, but for upward compatibility,
1854 allow negative values as well. */
1858 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1859 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1860 the_insn.reloc = BFD_RELOC_SPARC_6;
1862 the_insn.reloc = BFD_RELOC_SPARC13;
1863 /* These fields are unsigned, but for upward compatibility,
1864 allow negative values as well. */
1868 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1873 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1878 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1883 if (*s == 'p' && s[1] == 'n')
1891 if (*s == 'p' && s[1] == 't')
1903 if (strncmp (s, "%icc", 4) == 0)
1915 if (strncmp (s, "%xcc", 4) == 0)
1927 if (strncmp (s, "%fcc0", 5) == 0)
1939 if (strncmp (s, "%fcc1", 5) == 0)
1951 if (strncmp (s, "%fcc2", 5) == 0)
1963 if (strncmp (s, "%fcc3", 5) == 0)
1971 if (strncmp (s, "%pc", 3) == 0)
1979 if (strncmp (s, "%tick", 5) == 0)
1986 case '\0': /* End of args. */
1987 if (s[0] == ',' && s[1] == '%')
1989 static const struct ops
1991 /* The name as it appears in assembler. */
1993 /* strlen (name), precomputed for speed */
1995 /* The reloc this pseudo-op translates to. */
1997 /* 1 if tls call. */
2002 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2003 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2004 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2005 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2006 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2007 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2008 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2009 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2010 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2013 const struct ops *o;
2017 for (o = ops; o->name; o++)
2018 if (strncmp (s + 2, o->name, o->len) == 0)
2020 if (o->name == NULL)
2023 if (s[o->len + 2] != '(')
2025 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2026 return special_case;
2029 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2031 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2033 return special_case;
2037 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2038 || the_insn.exp.X_add_number != 0
2039 || the_insn.exp.X_add_symbol
2040 != symbol_find_or_make ("__tls_get_addr")))
2042 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2044 return special_case;
2047 the_insn.reloc = o->reloc;
2048 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2051 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2054 else if (*s1 == ')')
2063 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2064 return special_case;
2068 (void) get_expression (s);
2088 case '[': /* These must match exactly. */
2096 case '#': /* Must be at least one digit. */
2099 while (ISDIGIT (*s))
2107 case 'C': /* Coprocessor state register. */
2108 if (strncmp (s, "%csr", 4) == 0)
2115 case 'b': /* Next operand is a coprocessor register. */
2118 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2123 mask = 10 * (mask - '0') + (*s++ - '0');
2137 opcode |= mask << 14;
2145 opcode |= mask << 25;
2151 case 'r': /* next operand must be a register */
2161 case 'f': /* frame pointer */
2169 case 'g': /* global register */
2178 case 'i': /* in register */
2182 mask = c - '0' + 24;
2187 case 'l': /* local register */
2191 mask = (c - '0' + 16);
2196 case 'o': /* out register */
2200 mask = (c - '0' + 8);
2205 case 's': /* stack pointer */
2213 case 'r': /* any register */
2214 if (!ISDIGIT ((c = *s++)))
2231 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2247 if ((mask & ~1) == 2 && sparc_arch_size == 64
2248 && no_undeclared_regs && ! globals[mask])
2249 as_bad (_("detected global register use not covered by .register pseudo-op"));
2251 /* Got the register, now figure out where
2252 it goes in the opcode. */
2256 opcode |= mask << 14;
2264 opcode |= mask << 25;
2268 opcode |= (mask << 25) | (mask << 14);
2272 opcode |= (mask << 25) | (mask << 0);
2278 case 'e': /* next operand is a floating point register */
2296 && ((format = *s) == 'f')
2299 for (mask = 0; ISDIGIT (*s); ++s)
2301 mask = 10 * mask + (*s - '0');
2302 } /* read the number */
2311 } /* register must be even numbered */
2319 } /* register must be multiple of 4 */
2323 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2324 error_message = _(": There are only 64 f registers; [0-63]");
2326 error_message = _(": There are only 32 f registers; [0-31]");
2329 else if (mask >= 32)
2331 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2333 if (*args == 'e' || *args == 'f' || *args == 'g')
2336 = _(": There are only 32 single precision f registers; [0-31]");
2340 mask -= 31; /* wrap high bit */
2344 error_message = _(": There are only 32 f registers; [0-31]");
2352 } /* if not an 'f' register. */
2359 opcode |= RS1 (mask);
2365 opcode |= RS2 (mask);
2370 opcode |= RS3 (mask);
2376 opcode |= RD (mask);
2385 if (strncmp (s, "%fsr", 4) == 0)
2393 if (strncmp (s, "%efsr", 5) == 0)
2400 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2401 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2404 case 'l': /* 22 bit PC relative immediate */
2405 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2409 case 'L': /* 30 bit immediate */
2410 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2415 case 'n': /* 22 bit immediate */
2416 the_insn.reloc = BFD_RELOC_SPARC22;
2419 case 'i': /* 13 bit immediate */
2420 the_insn.reloc = BFD_RELOC_SPARC13;
2430 char *op_arg = NULL;
2431 static expressionS op_exp;
2432 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2434 /* Check for %hi, etc. */
2437 static const struct ops {
2438 /* The name as it appears in assembler. */
2440 /* strlen (name), precomputed for speed */
2442 /* The reloc this pseudo-op translates to. */
2444 /* Non-zero if for v9 only. */
2446 /* Non-zero if can be used in pc-relative contexts. */
2447 int pcrel_p;/*FIXME:wip*/
2449 /* hix/lox must appear before hi/lo so %hix won't be
2450 mistaken for %hi. */
2451 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2452 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2453 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2454 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2455 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2456 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2457 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2458 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2459 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2460 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2461 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2462 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2463 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2464 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2465 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2466 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2467 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2468 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2469 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2470 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2471 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2473 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2475 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2476 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2477 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2478 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2479 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2481 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2483 { NULL, 0, 0, 0, 0 }
2485 const struct ops *o;
2487 for (o = ops; o->name; o++)
2488 if (strncmp (s + 1, o->name, o->len) == 0)
2490 if (o->name == NULL)
2493 if (s[o->len + 1] != '(')
2495 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2496 return special_case;
2500 the_insn.reloc = o->reloc;
2505 /* Note that if the get_expression() fails, we will still
2506 have created U entries in the symbol table for the
2507 'symbols' in the input string. Try not to create U
2508 symbols for registers, etc. */
2510 /* This stuff checks to see if the expression ends in
2511 +%reg. If it does, it removes the register from
2512 the expression, and re-sets 's' to point to the
2519 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2522 else if (*s1 == ')')
2531 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2532 return special_case;
2536 (void) get_expression (s);
2539 if (*s == ',' || *s == ']' || !*s)
2541 if (*s != '+' && *s != '-')
2543 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2544 return special_case;
2548 op_exp = the_insn.exp;
2549 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2552 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2555 if (s1 != s && ISDIGIT (s1[-1]))
2557 if (s1[-2] == '%' && s1[-3] == '+')
2559 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2561 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2568 if (op_arg && s1 == s + 1)
2569 the_insn.exp.X_op = O_absent;
2571 (void) get_expression (s);
2583 (void) get_expression (s);
2591 the_insn.exp2 = the_insn.exp;
2592 the_insn.exp = op_exp;
2593 if (the_insn.exp2.X_op == O_absent)
2594 the_insn.exp2.X_op = O_illegal;
2595 else if (the_insn.exp.X_op == O_absent)
2597 the_insn.exp = the_insn.exp2;
2598 the_insn.exp2.X_op = O_illegal;
2600 else if (the_insn.exp.X_op == O_constant)
2602 valueT val = the_insn.exp.X_add_number;
2603 switch (the_insn.reloc)
2608 case BFD_RELOC_SPARC_HH22:
2609 val = BSR (val, 32);
2612 case BFD_RELOC_SPARC_LM22:
2613 case BFD_RELOC_HI22:
2614 val = (val >> 10) & 0x3fffff;
2617 case BFD_RELOC_SPARC_HM10:
2618 val = BSR (val, 32);
2621 case BFD_RELOC_LO10:
2625 case BFD_RELOC_SPARC_H34:
2630 case BFD_RELOC_SPARC_H44:
2635 case BFD_RELOC_SPARC_M44:
2640 case BFD_RELOC_SPARC_L44:
2644 case BFD_RELOC_SPARC_HIX22:
2646 val = (val >> 10) & 0x3fffff;
2649 case BFD_RELOC_SPARC_LOX10:
2650 val = (val & 0x3ff) | 0x1c00;
2653 the_insn.exp = the_insn.exp2;
2654 the_insn.exp.X_add_number += val;
2655 the_insn.exp2.X_op = O_illegal;
2656 the_insn.reloc = old_reloc;
2658 else if (the_insn.exp2.X_op != O_constant)
2660 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2661 return special_case;
2665 if (old_reloc != BFD_RELOC_SPARC13
2666 || the_insn.reloc != BFD_RELOC_LO10
2667 || sparc_arch_size != 64
2670 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2671 return special_case;
2673 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2677 /* Check for constants that don't require emitting a reloc. */
2678 if (the_insn.exp.X_op == O_constant
2679 && the_insn.exp.X_add_symbol == 0
2680 && the_insn.exp.X_op_symbol == 0)
2682 /* For pc-relative call instructions, we reject
2683 constants to get better code. */
2685 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2686 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2688 error_message = _(": PC-relative operand can't be a constant");
2692 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2693 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2695 error_message = _(": TLS operand can't be a constant");
2699 /* Constants that won't fit are checked in md_apply_fix
2700 and bfd_install_relocation.
2701 ??? It would be preferable to install the constants
2702 into the insn here and save having to create a fixS
2703 for each one. There already exists code to handle
2704 all the various cases (e.g. in md_apply_fix and
2705 bfd_install_relocation) so duplicating all that code
2706 here isn't right. */
2708 /* This is a special case to handle cbcond instructions
2709 properly, which can need two relocations. The first
2710 one is for the 5-bit immediate field and the latter
2711 is going to be for the WDISP10 branch part. We
2712 handle the R_SPARC_5 immediate directly here so that
2713 we don't need to add support for multiple relocations
2714 in one instruction just yet. */
2715 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2717 valueT val = the_insn.exp.X_add_number;
2719 if (! in_bitfield_range (val, 0x1f))
2721 error_message = _(": Immediate value in cbcond is out of range.");
2724 opcode |= val & 0x1f;
2725 the_insn.reloc = BFD_RELOC_NONE;
2746 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2748 error_message = _(": invalid ASI name");
2754 if (! parse_const_expr_arg (&s, &asi))
2756 error_message = _(": invalid ASI expression");
2759 if (asi < 0 || asi > 255)
2761 error_message = _(": invalid ASI number");
2765 opcode |= ASI (asi);
2767 } /* Alternate space. */
2770 if (strncmp (s, "%psr", 4) == 0)
2777 case 'q': /* Floating point queue. */
2778 if (strncmp (s, "%fq", 3) == 0)
2785 case 'Q': /* Coprocessor queue. */
2786 if (strncmp (s, "%cq", 3) == 0)
2794 if (strcmp (str, "set") == 0
2795 || strcmp (str, "setuw") == 0)
2797 special_case = SPECIAL_CASE_SET;
2800 else if (strcmp (str, "setsw") == 0)
2802 special_case = SPECIAL_CASE_SETSW;
2805 else if (strcmp (str, "setx") == 0)
2807 special_case = SPECIAL_CASE_SETX;
2810 else if (strncmp (str, "fdiv", 4) == 0)
2812 special_case = SPECIAL_CASE_FDIV;
2818 if (strncmp (s, "%asi", 4) != 0)
2824 if (strncmp (s, "%fprs", 5) != 0)
2830 if (strncmp (s, "%ccr", 4) != 0)
2836 if (strncmp (s, "%tbr", 4) != 0)
2842 if (strncmp (s, "%wim", 4) != 0)
2849 char *push = input_line_pointer;
2852 input_line_pointer = s;
2854 if (e.X_op == O_constant)
2856 int n = e.X_add_number;
2857 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2858 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2860 opcode |= e.X_add_number << 5;
2863 as_bad (_("non-immediate OPF operand, ignored"));
2864 s = input_line_pointer;
2865 input_line_pointer = push;
2870 if (strncmp (s, "%y", 2) != 0)
2878 /* Parse a sparclet cpreg. */
2880 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2882 error_message = _(": invalid cpreg name");
2885 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2890 as_fatal (_("failed sanity check."));
2891 } /* switch on arg code. */
2893 /* Break out of for() loop. */
2895 } /* For each arg that we expect. */
2900 /* Args don't match. */
2901 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2902 && (insn->name == insn[1].name
2903 || !strcmp (insn->name, insn[1].name)))
2911 as_bad (_("Illegal operands%s"), error_message);
2912 return special_case;
2917 /* We have a match. Now see if the architecture is OK. */
2918 int needed_arch_mask = insn->architecture;
2919 int hwcaps = insn->hwcaps;
2921 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2923 hwcap_seen |= hwcaps;
2928 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2929 if (! needed_arch_mask)
2931 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2934 if (needed_arch_mask
2935 & SPARC_OPCODE_SUPPORTED (current_architecture))
2938 /* Can we bump up the architecture? */
2939 else if (needed_arch_mask
2940 & SPARC_OPCODE_SUPPORTED (max_architecture))
2942 enum sparc_opcode_arch_val needed_architecture =
2943 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2944 & needed_arch_mask);
2946 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2948 && needed_architecture > warn_after_architecture)
2950 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2951 sparc_opcode_archs[current_architecture].name,
2952 sparc_opcode_archs[needed_architecture].name,
2954 warn_after_architecture = needed_architecture;
2956 current_architecture = needed_architecture;
2959 /* ??? This seems to be a bit fragile. What if the next entry in
2960 the opcode table is the one we want and it is supported?
2961 It is possible to arrange the table today so that this can't
2962 happen but what about tomorrow? */
2965 int arch, printed_one_p = 0;
2967 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2969 /* Create a list of the architectures that support the insn. */
2970 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2972 arch = sparc_ffs (needed_arch_mask);
2973 while ((1 << arch) <= needed_arch_mask)
2975 if ((1 << arch) & needed_arch_mask)
2979 strcpy (p, sparc_opcode_archs[arch].name);
2986 as_bad (_("Architecture mismatch on \"%s\"."), str);
2987 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2989 sparc_opcode_archs[max_architecture].name);
2990 return special_case;
2993 /* Make sure the the hwcaps used by the instruction are
2994 currently enabled. */
2995 if (hwcaps & ~hwcap_allowed)
2997 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2999 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3001 return special_case;
3003 } /* If no match. */
3006 } /* Forever looking for a match. */
3008 the_insn.opcode = opcode;
3009 return special_case;
3012 /* Parse an argument that can be expressed as a keyword.
3013 (eg: #StoreStore or %ccfr).
3014 The result is a boolean indicating success.
3015 If successful, INPUT_POINTER is updated. */
3018 parse_keyword_arg (int (*lookup_fn) (const char *),
3019 char **input_pointerP,
3025 p = *input_pointerP;
3026 for (q = p + (*p == '#' || *p == '%');
3027 ISALNUM (*q) || *q == '_';
3032 value = (*lookup_fn) (p);
3037 *input_pointerP = q;
3041 /* Parse an argument that is a constant expression.
3042 The result is a boolean indicating success. */
3045 parse_const_expr_arg (char **input_pointerP, int *valueP)
3047 char *save = input_line_pointer;
3050 input_line_pointer = *input_pointerP;
3051 /* The next expression may be something other than a constant
3052 (say if we're not processing the right variant of the insn).
3053 Don't call expression unless we're sure it will succeed as it will
3054 signal an error (which we want to defer until later). */
3055 /* FIXME: It might be better to define md_operand and have it recognize
3056 things like %asi, etc. but continuing that route through to the end
3057 is a lot of work. */
3058 if (*input_line_pointer == '%')
3060 input_line_pointer = save;
3064 *input_pointerP = input_line_pointer;
3065 input_line_pointer = save;
3066 if (exp.X_op != O_constant)
3068 *valueP = exp.X_add_number;
3072 /* Subroutine of sparc_ip to parse an expression. */
3075 get_expression (char *str)
3080 save_in = input_line_pointer;
3081 input_line_pointer = str;
3082 seg = expression (&the_insn.exp);
3083 if (seg != absolute_section
3084 && seg != text_section
3085 && seg != data_section
3086 && seg != bss_section
3087 && seg != undefined_section)
3089 the_insn.error = _("bad segment");
3090 expr_end = input_line_pointer;
3091 input_line_pointer = save_in;
3094 expr_end = input_line_pointer;
3095 input_line_pointer = save_in;
3099 /* Subroutine of md_assemble to output one insn. */
3102 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3104 char *toP = frag_more (4);
3106 /* Put out the opcode. */
3107 if (INSN_BIG_ENDIAN)
3108 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3110 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3112 /* Put out the symbol-dependent stuff. */
3113 if (theinsn->reloc != BFD_RELOC_NONE)
3115 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3116 (toP - frag_now->fr_literal), /* Where. */
3121 /* Turn off overflow checking in fixup_segment. We'll do our
3122 own overflow checking in md_apply_fix. This is necessary because
3123 the insn size is 4 and fixup_segment will signal an overflow for
3124 large 8 byte quantities. */
3125 fixP->fx_no_overflow = 1;
3126 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3127 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3131 last_opcode = theinsn->opcode;
3134 dwarf2_emit_insn (4);
3139 md_atof (int type, char *litP, int *sizeP)
3141 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3144 /* Write a value out to the object file, using the appropriate
3148 md_number_to_chars (char *buf, valueT val, int n)
3150 if (target_big_endian)
3151 number_to_chars_bigendian (buf, val, n);
3152 else if (target_little_endian_data
3153 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3154 /* Output debug words, which are not in allocated sections, as big
3156 number_to_chars_bigendian (buf, val, n);
3157 else if (target_little_endian_data || ! target_big_endian)
3158 number_to_chars_littleendian (buf, val, n);
3161 /* Apply a fixS to the frags, now that we know the value it ought to
3165 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3167 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3168 offsetT val = * (offsetT *) valP;
3171 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3173 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3176 /* SPARC ELF relocations don't use an addend in the data field. */
3177 if (fixP->fx_addsy != NULL)
3179 switch (fixP->fx_r_type)
3181 case BFD_RELOC_SPARC_TLS_GD_HI22:
3182 case BFD_RELOC_SPARC_TLS_GD_LO10:
3183 case BFD_RELOC_SPARC_TLS_GD_ADD:
3184 case BFD_RELOC_SPARC_TLS_GD_CALL:
3185 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3186 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3187 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3188 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3189 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3190 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3191 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3192 case BFD_RELOC_SPARC_TLS_IE_HI22:
3193 case BFD_RELOC_SPARC_TLS_IE_LO10:
3194 case BFD_RELOC_SPARC_TLS_IE_LD:
3195 case BFD_RELOC_SPARC_TLS_IE_LDX:
3196 case BFD_RELOC_SPARC_TLS_IE_ADD:
3197 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3198 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3199 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3200 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3201 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3202 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3203 case BFD_RELOC_SPARC_TLS_TPOFF32:
3204 case BFD_RELOC_SPARC_TLS_TPOFF64:
3205 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3215 /* This is a hack. There should be a better way to
3216 handle this. Probably in terms of howto fields, once
3217 we can look at these fixups in terms of howtos. */
3218 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3219 val += fixP->fx_where + fixP->fx_frag->fr_address;
3222 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3223 generate a reloc, then we just want to let the reloc addend set
3224 the value. We do not want to also stuff the addend into the
3225 object file. Including the addend in the object file works when
3226 doing a static link, because the linker will ignore the object
3227 file contents. However, the dynamic linker does not ignore the
3228 object file contents. */
3229 if (fixP->fx_addsy != NULL
3230 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3233 /* When generating PIC code, we do not want an addend for a reloc
3234 against a local symbol. We adjust fx_addnumber to cancel out the
3235 value already included in val, and to also cancel out the
3236 adjustment which bfd_install_relocation will create. */
3238 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3239 && fixP->fx_addsy != NULL
3240 && ! S_IS_COMMON (fixP->fx_addsy)
3241 && symbol_section_p (fixP->fx_addsy))
3242 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3244 /* When generating PIC code, we need to fiddle to get
3245 bfd_install_relocation to do the right thing for a PC relative
3246 reloc against a local symbol which we are going to keep. */
3248 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3249 && fixP->fx_addsy != NULL
3250 && (S_IS_EXTERNAL (fixP->fx_addsy)
3251 || S_IS_WEAK (fixP->fx_addsy))
3252 && S_IS_DEFINED (fixP->fx_addsy)
3253 && ! S_IS_COMMON (fixP->fx_addsy))
3256 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3260 /* If this is a data relocation, just output VAL. */
3262 if (fixP->fx_r_type == BFD_RELOC_8)
3264 md_number_to_chars (buf, val, 1);
3266 else if (fixP->fx_r_type == BFD_RELOC_16
3267 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3269 md_number_to_chars (buf, val, 2);
3271 else if (fixP->fx_r_type == BFD_RELOC_32
3272 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3273 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3275 md_number_to_chars (buf, val, 4);
3277 else if (fixP->fx_r_type == BFD_RELOC_64
3278 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3280 md_number_to_chars (buf, val, 8);
3282 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3283 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3290 /* It's a relocation against an instruction. */
3292 if (INSN_BIG_ENDIAN)
3293 insn = bfd_getb32 ((unsigned char *) buf);
3295 insn = bfd_getl32 ((unsigned char *) buf);
3297 switch (fixP->fx_r_type)
3299 case BFD_RELOC_32_PCREL_S2:
3301 /* FIXME: This increment-by-one deserves a comment of why it's
3303 if (! sparc_pic_code
3304 || fixP->fx_addsy == NULL
3305 || symbol_section_p (fixP->fx_addsy))
3308 insn |= val & 0x3fffffff;
3310 /* See if we have a delay slot. */
3311 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3315 #define XCC (2 << 20)
3316 #define COND(x) (((x)&0xf)<<25)
3317 #define CONDA COND(0x8)
3318 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3319 #define INSN_BA (F2(0,2) | CONDA)
3320 #define INSN_OR F3(2, 0x2, 0)
3321 #define INSN_NOP F2(0,4)
3325 /* If the instruction is a call with either:
3327 arithmetic instruction with rd == %o7
3328 where rs1 != %o7 and rs2 if it is register != %o7
3329 then we can optimize if the call destination is near
3330 by changing the call into a branch always. */
3331 if (INSN_BIG_ENDIAN)
3332 delay = bfd_getb32 ((unsigned char *) buf + 4);
3334 delay = bfd_getl32 ((unsigned char *) buf + 4);
3335 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3337 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3338 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3339 || ((delay & RD (~0)) != RD (O7))))
3341 if ((delay & RS1 (~0)) == RS1 (O7)
3342 || ((delay & F3I (~0)) == 0
3343 && (delay & RS2 (~0)) == RS2 (O7)))
3345 /* Ensure the branch will fit into simm22. */
3346 if ((val & 0x3fe00000)
3347 && (val & 0x3fe00000) != 0x3fe00000)
3349 /* Check if the arch is v9 and branch will fit
3351 if (((val & 0x3c0000) == 0
3352 || (val & 0x3c0000) == 0x3c0000)
3353 && (sparc_arch_size == 64
3354 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3356 insn = INSN_BPA | (val & 0x7ffff);
3359 insn = INSN_BA | (val & 0x3fffff);
3360 if (fixP->fx_where >= 4
3361 && ((delay & (0xffffffff ^ RS1 (~0)))
3362 == (INSN_OR | RD (O7) | RS2 (G0))))
3367 if (INSN_BIG_ENDIAN)
3368 setter = bfd_getb32 ((unsigned char *) buf - 4);
3370 setter = bfd_getl32 ((unsigned char *) buf - 4);
3371 if ((setter & (0xffffffff ^ RD (~0)))
3372 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3379 If call foo was replaced with ba, replace
3380 or %rN, %g0, %o7 with nop. */
3381 reg = (delay & RS1 (~0)) >> 14;
3382 if (reg != ((setter & RD (~0)) >> 25)
3383 || reg == G0 || reg == O7)
3386 if (INSN_BIG_ENDIAN)
3387 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3389 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3394 case BFD_RELOC_SPARC_11:
3395 if (! in_signed_range (val, 0x7ff))
3396 as_bad_where (fixP->fx_file, fixP->fx_line,
3397 _("relocation overflow"));
3398 insn |= val & 0x7ff;
3401 case BFD_RELOC_SPARC_10:
3402 if (! in_signed_range (val, 0x3ff))
3403 as_bad_where (fixP->fx_file, fixP->fx_line,
3404 _("relocation overflow"));
3405 insn |= val & 0x3ff;
3408 case BFD_RELOC_SPARC_7:
3409 if (! in_bitfield_range (val, 0x7f))
3410 as_bad_where (fixP->fx_file, fixP->fx_line,
3411 _("relocation overflow"));
3415 case BFD_RELOC_SPARC_6:
3416 if (! in_bitfield_range (val, 0x3f))
3417 as_bad_where (fixP->fx_file, fixP->fx_line,
3418 _("relocation overflow"));
3422 case BFD_RELOC_SPARC_5:
3423 if (! in_bitfield_range (val, 0x1f))
3424 as_bad_where (fixP->fx_file, fixP->fx_line,
3425 _("relocation overflow"));
3429 case BFD_RELOC_SPARC_WDISP10:
3432 || val <= -(offsetT) 0x808)
3433 as_bad_where (fixP->fx_file, fixP->fx_line,
3434 _("relocation overflow"));
3435 /* FIXME: The +1 deserves a comment. */
3436 val = (val >> 2) + 1;
3437 insn |= ((val & 0x300) << 11)
3438 | ((val & 0xff) << 5);
3441 case BFD_RELOC_SPARC_WDISP16:
3444 || val <= -(offsetT) 0x20008)
3445 as_bad_where (fixP->fx_file, fixP->fx_line,
3446 _("relocation overflow"));
3447 /* FIXME: The +1 deserves a comment. */
3448 val = (val >> 2) + 1;
3449 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3452 case BFD_RELOC_SPARC_WDISP19:
3455 || val <= -(offsetT) 0x100008)
3456 as_bad_where (fixP->fx_file, fixP->fx_line,
3457 _("relocation overflow"));
3458 /* FIXME: The +1 deserves a comment. */
3459 val = (val >> 2) + 1;
3460 insn |= val & 0x7ffff;
3463 case BFD_RELOC_SPARC_HH22:
3464 val = BSR (val, 32);
3467 case BFD_RELOC_SPARC_LM22:
3468 case BFD_RELOC_HI22:
3469 if (!fixP->fx_addsy)
3470 insn |= (val >> 10) & 0x3fffff;
3472 /* FIXME: Need comment explaining why we do this. */
3476 case BFD_RELOC_SPARC22:
3477 if (val & ~0x003fffff)
3478 as_bad_where (fixP->fx_file, fixP->fx_line,
3479 _("relocation overflow"));
3480 insn |= (val & 0x3fffff);
3483 case BFD_RELOC_SPARC_HM10:
3484 val = BSR (val, 32);
3487 case BFD_RELOC_LO10:
3488 if (!fixP->fx_addsy)
3489 insn |= val & 0x3ff;
3491 /* FIXME: Need comment explaining why we do this. */
3495 case BFD_RELOC_SPARC_OLO10:
3497 val += fixP->tc_fix_data;
3500 case BFD_RELOC_SPARC13:
3501 if (! in_signed_range (val, 0x1fff))
3502 as_bad_where (fixP->fx_file, fixP->fx_line,
3503 _("relocation overflow"));
3504 insn |= val & 0x1fff;
3507 case BFD_RELOC_SPARC_WDISP22:
3508 val = (val >> 2) + 1;
3510 case BFD_RELOC_SPARC_BASE22:
3511 insn |= val & 0x3fffff;
3514 case BFD_RELOC_SPARC_H34:
3515 if (!fixP->fx_addsy)
3519 insn |= tval & 0x3fffff;
3523 case BFD_RELOC_SPARC_H44:
3524 if (!fixP->fx_addsy)
3528 insn |= tval & 0x3fffff;
3532 case BFD_RELOC_SPARC_M44:
3533 if (!fixP->fx_addsy)
3534 insn |= (val >> 12) & 0x3ff;
3537 case BFD_RELOC_SPARC_L44:
3538 if (!fixP->fx_addsy)
3539 insn |= val & 0xfff;
3542 case BFD_RELOC_SPARC_HIX22:
3543 if (!fixP->fx_addsy)
3545 val ^= ~(offsetT) 0;
3546 insn |= (val >> 10) & 0x3fffff;
3550 case BFD_RELOC_SPARC_LOX10:
3551 if (!fixP->fx_addsy)
3552 insn |= 0x1c00 | (val & 0x3ff);
3555 case BFD_RELOC_NONE:
3557 as_bad_where (fixP->fx_file, fixP->fx_line,
3558 _("bad or unhandled relocation type: 0x%02x"),
3563 if (INSN_BIG_ENDIAN)
3564 bfd_putb32 (insn, (unsigned char *) buf);
3566 bfd_putl32 (insn, (unsigned char *) buf);
3569 /* Are we finished with this relocation now? */
3570 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3574 /* Translate internal representation of relocation info to BFD target
3578 tc_gen_reloc (asection *section, fixS *fixp)
3580 static arelent *relocs[3];
3582 bfd_reloc_code_real_type code;
3584 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3587 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3588 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3589 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3591 switch (fixp->fx_r_type)
3595 case BFD_RELOC_HI22:
3596 case BFD_RELOC_LO10:
3597 case BFD_RELOC_32_PCREL_S2:
3598 case BFD_RELOC_SPARC13:
3599 case BFD_RELOC_SPARC22:
3600 case BFD_RELOC_SPARC_PC22:
3601 case BFD_RELOC_SPARC_PC10:
3602 case BFD_RELOC_SPARC_BASE13:
3603 case BFD_RELOC_SPARC_WDISP10:
3604 case BFD_RELOC_SPARC_WDISP16:
3605 case BFD_RELOC_SPARC_WDISP19:
3606 case BFD_RELOC_SPARC_WDISP22:
3608 case BFD_RELOC_SPARC_5:
3609 case BFD_RELOC_SPARC_6:
3610 case BFD_RELOC_SPARC_7:
3611 case BFD_RELOC_SPARC_10:
3612 case BFD_RELOC_SPARC_11:
3613 case BFD_RELOC_SPARC_HH22:
3614 case BFD_RELOC_SPARC_HM10:
3615 case BFD_RELOC_SPARC_LM22:
3616 case BFD_RELOC_SPARC_PC_HH22:
3617 case BFD_RELOC_SPARC_PC_HM10:
3618 case BFD_RELOC_SPARC_PC_LM22:
3619 case BFD_RELOC_SPARC_H34:
3620 case BFD_RELOC_SPARC_H44:
3621 case BFD_RELOC_SPARC_M44:
3622 case BFD_RELOC_SPARC_L44:
3623 case BFD_RELOC_SPARC_HIX22:
3624 case BFD_RELOC_SPARC_LOX10:
3625 case BFD_RELOC_SPARC_REV32:
3626 case BFD_RELOC_SPARC_OLO10:
3627 case BFD_RELOC_SPARC_UA16:
3628 case BFD_RELOC_SPARC_UA32:
3629 case BFD_RELOC_SPARC_UA64:
3630 case BFD_RELOC_8_PCREL:
3631 case BFD_RELOC_16_PCREL:
3632 case BFD_RELOC_32_PCREL:
3633 case BFD_RELOC_64_PCREL:
3634 case BFD_RELOC_SPARC_PLT32:
3635 case BFD_RELOC_SPARC_PLT64:
3636 case BFD_RELOC_VTABLE_ENTRY:
3637 case BFD_RELOC_VTABLE_INHERIT:
3638 case BFD_RELOC_SPARC_TLS_GD_HI22:
3639 case BFD_RELOC_SPARC_TLS_GD_LO10:
3640 case BFD_RELOC_SPARC_TLS_GD_ADD:
3641 case BFD_RELOC_SPARC_TLS_GD_CALL:
3642 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3643 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3644 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3645 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3646 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3647 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3648 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3649 case BFD_RELOC_SPARC_TLS_IE_HI22:
3650 case BFD_RELOC_SPARC_TLS_IE_LO10:
3651 case BFD_RELOC_SPARC_TLS_IE_LD:
3652 case BFD_RELOC_SPARC_TLS_IE_LDX:
3653 case BFD_RELOC_SPARC_TLS_IE_ADD:
3654 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3655 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3656 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3657 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3658 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3659 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3660 case BFD_RELOC_SPARC_GOTDATA_OP:
3661 code = fixp->fx_r_type;
3668 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3669 /* If we are generating PIC code, we need to generate a different
3673 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3675 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3678 #define GOTT_BASE "__GOTT_BASE__"
3679 #define GOTT_INDEX "__GOTT_INDEX__"
3682 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3688 case BFD_RELOC_32_PCREL_S2:
3689 if (generic_force_reloc (fixp))
3690 code = BFD_RELOC_SPARC_WPLT30;
3692 case BFD_RELOC_HI22:
3693 code = BFD_RELOC_SPARC_GOT22;
3694 if (fixp->fx_addsy != NULL)
3696 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3697 code = BFD_RELOC_SPARC_PC22;
3699 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3700 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3701 code = BFD_RELOC_HI22; /* Unchanged. */
3705 case BFD_RELOC_LO10:
3706 code = BFD_RELOC_SPARC_GOT10;
3707 if (fixp->fx_addsy != NULL)
3709 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3710 code = BFD_RELOC_SPARC_PC10;
3712 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3713 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3714 code = BFD_RELOC_LO10; /* Unchanged. */
3718 case BFD_RELOC_SPARC13:
3719 code = BFD_RELOC_SPARC_GOT13;
3725 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3727 /* Nothing is aligned in DWARF debugging sections. */
3728 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3731 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3732 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3733 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3737 if (code == BFD_RELOC_SPARC_OLO10)
3738 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3740 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3741 if (reloc->howto == 0)
3743 as_bad_where (fixp->fx_file, fixp->fx_line,
3744 _("internal error: can't export reloc type %d (`%s')"),
3745 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3751 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3754 if (reloc->howto->pc_relative == 0
3755 || code == BFD_RELOC_SPARC_PC10
3756 || code == BFD_RELOC_SPARC_PC22)
3757 reloc->addend = fixp->fx_addnumber;
3758 else if (sparc_pic_code
3759 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3760 && fixp->fx_addsy != NULL
3761 && (S_IS_EXTERNAL (fixp->fx_addsy)
3762 || S_IS_WEAK (fixp->fx_addsy))
3763 && S_IS_DEFINED (fixp->fx_addsy)
3764 && ! S_IS_COMMON (fixp->fx_addsy))
3765 reloc->addend = fixp->fx_addnumber;
3767 reloc->addend = fixp->fx_offset - reloc->address;
3769 #else /* elf or coff */
3771 if (code != BFD_RELOC_32_PCREL_S2
3772 && code != BFD_RELOC_SPARC_WDISP22
3773 && code != BFD_RELOC_SPARC_WDISP16
3774 && code != BFD_RELOC_SPARC_WDISP19
3775 && code != BFD_RELOC_SPARC_WDISP10
3776 && code != BFD_RELOC_SPARC_WPLT30
3777 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3778 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3779 reloc->addend = fixp->fx_addnumber;
3780 else if (symbol_section_p (fixp->fx_addsy))
3781 reloc->addend = (section->vma
3782 + fixp->fx_addnumber
3783 + md_pcrel_from (fixp));
3785 reloc->addend = fixp->fx_offset;
3788 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3789 on the same location. */
3790 if (code == BFD_RELOC_SPARC_OLO10)
3792 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3795 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3797 = symbol_get_bfdsym (section_symbol (absolute_section));
3798 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3799 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3800 reloc->addend = fixp->tc_fix_data;
3806 /* We have no need to default values of symbols. */
3809 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3814 /* Round up a section size to the appropriate boundary. */
3817 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3820 /* This is not right for ELF; a.out wants it, and COFF will force
3821 the alignment anyways. */
3822 valueT align = ((valueT) 1
3823 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3826 /* Turn alignment value into a mask. */
3828 newsize = (size + align) & ~align;
3835 /* Exactly what point is a PC-relative offset relative TO?
3836 On the sparc, they're relative to the address of the offset, plus
3837 its size. This gets us to the following instruction.
3838 (??? Is this right? FIXME-SOON) */
3840 md_pcrel_from (fixS *fixP)
3844 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3845 if (! sparc_pic_code
3846 || fixP->fx_addsy == NULL
3847 || symbol_section_p (fixP->fx_addsy))
3848 ret += fixP->fx_size;
3852 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3863 for (shift = 0; (value & 1) == 0; value >>= 1)
3866 return (value == 1) ? shift : -1;
3869 /* Sort of like s_lcomm. */
3872 static int max_alignment = 15;
3876 s_reserve (int ignore ATTRIBUTE_UNUSED)
3886 name = input_line_pointer;
3887 c = get_symbol_end ();
3888 p = input_line_pointer;
3892 if (*input_line_pointer != ',')
3894 as_bad (_("Expected comma after name"));
3895 ignore_rest_of_line ();
3899 ++input_line_pointer;
3901 if ((size = get_absolute_expression ()) < 0)
3903 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3904 ignore_rest_of_line ();
3909 symbolP = symbol_find_or_make (name);
3912 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3913 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3915 as_bad (_("bad .reserve segment -- expected BSS segment"));
3919 if (input_line_pointer[2] == '.')
3920 input_line_pointer += 7;
3922 input_line_pointer += 6;
3925 if (*input_line_pointer == ',')
3927 ++input_line_pointer;
3930 if (*input_line_pointer == '\n')
3932 as_bad (_("missing alignment"));
3933 ignore_rest_of_line ();
3937 align = (int) get_absolute_expression ();
3940 if (align > max_alignment)
3942 align = max_alignment;
3943 as_warn (_("alignment too large; assuming %d"), align);
3949 as_bad (_("negative alignment"));
3950 ignore_rest_of_line ();
3956 temp = mylog2 (align);
3959 as_bad (_("alignment not a power of 2"));
3960 ignore_rest_of_line ();
3967 record_alignment (bss_section, align);
3972 if (!S_IS_DEFINED (symbolP)
3974 && S_GET_OTHER (symbolP) == 0
3975 && S_GET_DESC (symbolP) == 0
3982 segT current_seg = now_seg;
3983 subsegT current_subseg = now_subseg;
3985 /* Switch to bss. */
3986 subseg_set (bss_section, 1);
3990 frag_align (align, 0, 0);
3992 /* Detach from old frag. */
3993 if (S_GET_SEGMENT (symbolP) == bss_section)
3994 symbol_get_frag (symbolP)->fr_symbol = NULL;
3996 symbol_set_frag (symbolP, frag_now);
3997 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3998 (offsetT) size, (char *) 0);
4001 S_SET_SEGMENT (symbolP, bss_section);
4003 subseg_set (current_seg, current_subseg);
4006 S_SET_SIZE (symbolP, size);
4012 as_warn (_("Ignoring attempt to re-define symbol %s"),
4013 S_GET_NAME (symbolP));
4016 demand_empty_rest_of_line ();
4020 s_common (int ignore ATTRIBUTE_UNUSED)
4028 name = input_line_pointer;
4029 c = get_symbol_end ();
4030 /* Just after name is now '\0'. */
4031 p = input_line_pointer;
4034 if (*input_line_pointer != ',')
4036 as_bad (_("Expected comma after symbol-name"));
4037 ignore_rest_of_line ();
4042 input_line_pointer++;
4044 if ((temp = get_absolute_expression ()) < 0)
4046 as_bad (_(".COMMon length (%lu) out of range ignored"),
4047 (unsigned long) temp);
4048 ignore_rest_of_line ();
4053 symbolP = symbol_find_or_make (name);
4055 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4057 as_bad (_("Ignoring attempt to re-define symbol"));
4058 ignore_rest_of_line ();
4061 if (S_GET_VALUE (symbolP) != 0)
4063 if (S_GET_VALUE (symbolP) != (valueT) size)
4065 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4066 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4072 S_SET_VALUE (symbolP, (valueT) size);
4073 S_SET_EXTERNAL (symbolP);
4076 know (symbol_get_frag (symbolP) == &zero_address_frag);
4077 if (*input_line_pointer != ',')
4079 as_bad (_("Expected comma after common length"));
4080 ignore_rest_of_line ();
4083 input_line_pointer++;
4085 if (*input_line_pointer != '"')
4087 temp = get_absolute_expression ();
4090 if (temp > max_alignment)
4092 temp = max_alignment;
4093 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4099 as_bad (_("negative alignment"));
4100 ignore_rest_of_line ();
4105 if (symbol_get_obj (symbolP)->local)
4112 old_subsec = now_subseg;
4117 align = mylog2 (temp);
4121 as_bad (_("alignment not a power of 2"));
4122 ignore_rest_of_line ();
4126 record_alignment (bss_section, align);
4127 subseg_set (bss_section, 0);
4129 frag_align (align, 0, 0);
4130 if (S_GET_SEGMENT (symbolP) == bss_section)
4131 symbol_get_frag (symbolP)->fr_symbol = 0;
4132 symbol_set_frag (symbolP, frag_now);
4133 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4134 (offsetT) size, (char *) 0);
4136 S_SET_SEGMENT (symbolP, bss_section);
4137 S_CLEAR_EXTERNAL (symbolP);
4138 S_SET_SIZE (symbolP, size);
4139 subseg_set (old_sec, old_subsec);
4142 #endif /* OBJ_ELF */
4145 S_SET_VALUE (symbolP, (valueT) size);
4147 S_SET_ALIGN (symbolP, temp);
4148 S_SET_SIZE (symbolP, size);
4150 S_SET_EXTERNAL (symbolP);
4151 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4156 input_line_pointer++;
4157 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4158 if (*input_line_pointer == '.')
4159 input_line_pointer++;
4160 /* @@ Some say data, some say bss. */
4161 if (strncmp (input_line_pointer, "bss\"", 4)
4162 && strncmp (input_line_pointer, "data\"", 5))
4164 while (*--input_line_pointer != '"')
4166 input_line_pointer--;
4167 goto bad_common_segment;
4169 while (*input_line_pointer++ != '"')
4171 goto allocate_common;
4174 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4176 demand_empty_rest_of_line ();
4181 p = input_line_pointer;
4182 while (*p && *p != '\n')
4186 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4188 input_line_pointer = p;
4189 ignore_rest_of_line ();
4194 /* Handle the .empty pseudo-op. This suppresses the warnings about
4195 invalid delay slot usage. */
4198 s_empty (int ignore ATTRIBUTE_UNUSED)
4200 /* The easy way to implement is to just forget about the last
4206 s_seg (int ignore ATTRIBUTE_UNUSED)
4209 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4211 input_line_pointer += 6;
4215 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4217 input_line_pointer += 6;
4221 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4223 input_line_pointer += 7;
4227 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4229 input_line_pointer += 5;
4230 /* We only support 2 segments -- text and data -- for now, so
4231 things in the "bss segment" will have to go into data for now.
4232 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4233 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4236 as_bad (_("Unknown segment type"));
4237 demand_empty_rest_of_line ();
4243 subseg_set (data_section, 1);
4244 demand_empty_rest_of_line ();
4248 s_proc (int ignore ATTRIBUTE_UNUSED)
4250 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4252 ++input_line_pointer;
4254 ++input_line_pointer;
4257 /* This static variable is set by s_uacons to tell sparc_cons_align
4258 that the expression does not need to be aligned. */
4260 static int sparc_no_align_cons = 0;
4262 /* This static variable is set by sparc_cons to emit requested types
4263 of relocations in cons_fix_new_sparc. */
4265 static const char *sparc_cons_special_reloc;
4267 /* This handles the unaligned space allocation pseudo-ops, such as
4268 .uaword. .uaword is just like .word, but the value does not need
4272 s_uacons (int bytes)
4274 /* Tell sparc_cons_align not to align this value. */
4275 sparc_no_align_cons = 1;
4277 sparc_no_align_cons = 0;
4280 /* This handles the native word allocation pseudo-op .nword.
4281 For sparc_arch_size 32 it is equivalent to .word, for
4282 sparc_arch_size 64 it is equivalent to .xword. */
4285 s_ncons (int bytes ATTRIBUTE_UNUSED)
4287 cons (sparc_arch_size == 32 ? 4 : 8);
4291 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4295 .register %g[2367],{#scratch|symbolname|#ignore}
4299 s_register (int ignore ATTRIBUTE_UNUSED)
4304 const char *regname;
4306 if (input_line_pointer[0] != '%'
4307 || input_line_pointer[1] != 'g'
4308 || ((input_line_pointer[2] & ~1) != '2'
4309 && (input_line_pointer[2] & ~1) != '6')
4310 || input_line_pointer[3] != ',')
4311 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4312 reg = input_line_pointer[2] - '0';
4313 input_line_pointer += 4;
4315 if (*input_line_pointer == '#')
4317 ++input_line_pointer;
4318 regname = input_line_pointer;
4319 c = get_symbol_end ();
4320 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4321 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4322 if (regname[0] == 'i')
4329 regname = input_line_pointer;
4330 c = get_symbol_end ();
4332 if (sparc_arch_size == 64)
4336 if ((regname && globals[reg] != (symbolS *) 1
4337 && strcmp (S_GET_NAME (globals[reg]), regname))
4338 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4339 as_bad (_("redefinition of global register"));
4343 if (regname == NULL)
4344 globals[reg] = (symbolS *) 1;
4349 if (symbol_find (regname))
4350 as_bad (_("Register symbol %s already defined."),
4353 globals[reg] = symbol_make (regname);
4354 flags = symbol_get_bfdsym (globals[reg])->flags;
4356 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4357 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4358 flags |= BSF_GLOBAL;
4359 symbol_get_bfdsym (globals[reg])->flags = flags;
4360 S_SET_VALUE (globals[reg], (valueT) reg);
4361 S_SET_ALIGN (globals[reg], reg);
4362 S_SET_SIZE (globals[reg], 0);
4363 /* Although we actually want undefined_section here,
4364 we have to use absolute_section, because otherwise
4365 generic as code will make it a COM section.
4366 We fix this up in sparc_adjust_symtab. */
4367 S_SET_SEGMENT (globals[reg], absolute_section);
4368 S_SET_OTHER (globals[reg], 0);
4369 elf_symbol (symbol_get_bfdsym (globals[reg]))
4370 ->internal_elf_sym.st_info =
4371 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4372 elf_symbol (symbol_get_bfdsym (globals[reg]))
4373 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4378 *input_line_pointer = c;
4380 demand_empty_rest_of_line ();
4383 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4384 symbols which need it. */
4387 sparc_adjust_symtab (void)
4391 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4393 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4394 ->internal_elf_sym.st_info) != STT_REGISTER)
4397 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4398 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4401 S_SET_SEGMENT (sym, undefined_section);
4406 /* If the --enforce-aligned-data option is used, we require .word,
4407 et. al., to be aligned correctly. We do it by setting up an
4408 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4409 no unexpected alignment was introduced.
4411 The SunOS and Solaris native assemblers enforce aligned data by
4412 default. We don't want to do that, because gcc can deliberately
4413 generate misaligned data if the packed attribute is used. Instead,
4414 we permit misaligned data by default, and permit the user to set an
4415 option to check for it. */
4418 sparc_cons_align (int nbytes)
4422 /* Only do this if we are enforcing aligned data. */
4423 if (! enforce_aligned_data)
4426 /* Don't align if this is an unaligned pseudo-op. */
4427 if (sparc_no_align_cons)
4430 nalign = mylog2 (nbytes);
4434 gas_assert (nalign > 0);
4436 if (now_seg == absolute_section)
4438 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4439 as_bad (_("misaligned data"));
4443 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4444 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4446 record_alignment (now_seg, nalign);
4449 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4452 sparc_handle_align (fragS *fragp)
4457 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4459 switch (fragp->fr_type)
4463 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4467 p = fragp->fr_literal + fragp->fr_fix;
4478 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4480 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4481 if (INSN_BIG_ENDIAN)
4482 number_to_chars_bigendian (p, wval, 4);
4484 number_to_chars_littleendian (p, wval, 4);
4490 if (INSN_BIG_ENDIAN)
4491 number_to_chars_bigendian (p, 0x01000000, 4);
4493 number_to_chars_littleendian (p, 0x01000000, 4);
4495 fragp->fr_fix += fix;
4505 /* Some special processing for a Sparc ELF file. */
4508 sparc_elf_final_processing (void)
4510 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4511 sort of BFD interface for this. */
4512 if (sparc_arch_size == 64)
4514 switch (sparc_memory_model)
4517 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4520 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4526 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4527 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4528 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4529 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4530 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4531 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4535 sparc_cons (expressionS *exp, int size)
4540 sparc_cons_special_reloc = NULL;
4541 save = input_line_pointer;
4542 if (input_line_pointer[0] == '%'
4543 && input_line_pointer[1] == 'r'
4544 && input_line_pointer[2] == '_')
4546 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4548 input_line_pointer += 7;
4549 sparc_cons_special_reloc = "disp";
4551 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4553 if (size != 4 && size != 8)
4554 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4557 input_line_pointer += 6;
4558 sparc_cons_special_reloc = "plt";
4561 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4563 if (size != 4 && size != 8)
4564 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4567 input_line_pointer += 13;
4568 sparc_cons_special_reloc = "tls_dtpoff";
4571 if (sparc_cons_special_reloc)
4578 if (*input_line_pointer != '8')
4580 input_line_pointer--;
4583 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4587 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4591 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4601 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4602 sparc_cons_special_reloc, size * 8, size);
4606 input_line_pointer += 2;
4607 if (*input_line_pointer != '(')
4609 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4610 sparc_cons_special_reloc, size * 8);
4617 input_line_pointer = save;
4618 sparc_cons_special_reloc = NULL;
4623 char *end = ++input_line_pointer;
4626 while (! is_end_of_line[(c = *end)])
4640 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4641 sparc_cons_special_reloc, size * 8);
4647 if (input_line_pointer != end)
4649 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4650 sparc_cons_special_reloc, size * 8);
4654 input_line_pointer++;
4656 c = *input_line_pointer;
4657 if (! is_end_of_line[c] && c != ',')
4658 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4659 sparc_cons_special_reloc, size * 8);
4665 if (sparc_cons_special_reloc == NULL)
4671 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4672 reloc for a cons. We could use the definition there, except that
4673 we want to handle little endian relocs specially. */
4676 cons_fix_new_sparc (fragS *frag,
4678 unsigned int nbytes,
4681 bfd_reloc_code_real_type r;
4683 r = (nbytes == 1 ? BFD_RELOC_8 :
4684 (nbytes == 2 ? BFD_RELOC_16 :
4685 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4687 if (target_little_endian_data
4689 && now_seg->flags & SEC_ALLOC)
4690 r = BFD_RELOC_SPARC_REV32;
4692 if (sparc_cons_special_reloc)
4694 if (*sparc_cons_special_reloc == 'd')
4697 case 1: r = BFD_RELOC_8_PCREL; break;
4698 case 2: r = BFD_RELOC_16_PCREL; break;
4699 case 4: r = BFD_RELOC_32_PCREL; break;
4700 case 8: r = BFD_RELOC_64_PCREL; break;
4703 else if (*sparc_cons_special_reloc == 'p')
4706 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4707 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4712 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4713 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4716 else if (sparc_no_align_cons)
4720 case 2: r = BFD_RELOC_SPARC_UA16; break;
4721 case 4: r = BFD_RELOC_SPARC_UA32; break;
4722 case 8: r = BFD_RELOC_SPARC_UA64; break;
4727 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4728 sparc_cons_special_reloc = NULL;
4732 sparc_cfi_frame_initial_instructions (void)
4734 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4738 sparc_regname_to_dw2regnum (char *regname)
4746 p = strchr (q, regname[0]);
4749 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4751 return (p - q) * 8 + regname[1] - '0';
4753 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4755 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4757 if (regname[0] == 'f' || regname[0] == 'r')
4759 unsigned int regnum;
4761 regnum = strtoul (regname + 1, &q, 10);
4764 if (regnum >= ((regname[0] == 'f'
4765 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4768 if (regname[0] == 'f')
4771 if (regnum >= 64 && (regnum & 1))
4780 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4782 sparc_cons_special_reloc = "disp";
4783 sparc_no_align_cons = 1;
4784 emit_expr (exp, nbytes);
4785 sparc_no_align_cons = 0;
4786 sparc_cons_special_reloc = NULL;