1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch *lookup_arch PARAMS ((char *));
33 static void init_default_arch PARAMS ((void));
34 static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
35 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
36 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
37 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
38 static int sparc_ffs PARAMS ((unsigned int));
39 static bfd_vma BSR PARAMS ((bfd_vma, int));
40 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
41 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
42 static int parse_const_expr_arg PARAMS ((char **, int *));
43 static int get_expression PARAMS ((char *str));
45 /* Default architecture. */
46 /* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
50 #define DEFAULT_ARCH "sparclite"
52 static char *default_arch = DEFAULT_ARCH;
54 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 static int default_init_p;
58 /* Current architecture. We don't bump up unless necessary. */
59 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61 /* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
63 The native assembler works this way. The user is required to pass
64 an explicit argument before we'll create v9 object files. However, if
65 we don't see any v9 insns, a v8plus object file is not created. */
66 static enum sparc_opcode_arch_val max_architecture;
68 /* Either 32 or 64, selects file format. */
69 static int sparc_arch_size;
70 /* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72 static int default_arch_size;
75 /* The currently selected v9 memory model. Currently only used for
77 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
80 static int architecture_requested;
81 static int warn_on_bump;
83 /* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85 static enum sparc_opcode_arch_val warn_after_architecture;
87 /* Non-zero if we are generating PIC code. */
90 /* Non-zero if we should give an error when misaligned data is seen. */
91 static int enforce_aligned_data;
93 extern int target_big_endian;
95 static int target_little_endian_data;
97 /* V9 and 86x have big and little endian data, but instructions are always big
98 endian. The sparclet has bi-endian support but both data and insns have
99 the same endianness. Global `target_big_endian' is used for data.
100 The following macro is used for instructions. */
101 #ifndef INSN_BIG_ENDIAN
102 #define INSN_BIG_ENDIAN (target_big_endian \
103 || default_arch_type == sparc86x \
104 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
107 /* handle of the OPCODE hash table */
108 static struct hash_control *op_hash;
110 static int log2 PARAMS ((int));
111 static void s_data1 PARAMS ((void));
112 static void s_seg PARAMS ((int));
113 static void s_proc PARAMS ((int));
114 static void s_reserve PARAMS ((int));
115 static void s_common PARAMS ((int));
116 static void s_empty PARAMS ((int));
117 static void s_uacons PARAMS ((int));
119 const pseudo_typeS md_pseudo_table[] =
121 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
122 {"common", s_common, 0},
123 {"empty", s_empty, 0},
124 {"global", s_globl, 0},
126 {"optim", s_ignore, 0},
128 {"reserve", s_reserve, 0},
130 {"skip", s_space, 0},
133 {"uahalf", s_uacons, 2},
134 {"uaword", s_uacons, 4},
135 {"uaxword", s_uacons, 8},
137 /* these are specific to sparc/svr4 */
138 {"pushsection", obj_elf_section, 0},
139 {"popsection", obj_elf_previous, 0},
140 {"2byte", s_uacons, 2},
141 {"4byte", s_uacons, 4},
142 {"8byte", s_uacons, 8},
147 const int md_reloc_size = 12; /* Size of relocation record */
149 /* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
151 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
153 /* This array holds the chars that only start a comment at the beginning of
154 a line. If the line seems to have the form '# 123 filename'
155 .line and .file directives will appear in the pre-processed output */
156 /* Note that input_file.c hand checks for '#' at the beginning of the
157 first line of the input file. This is because the compiler outputs
158 #NO_APP at the beginning of its output. */
159 /* Also note that comments started like this one will always
160 work if '/' isn't otherwise defined. */
161 const char line_comment_chars[] = "#";
163 const char line_separator_chars[] = "";
165 /* Chars that can be used to separate mant from exp in floating point nums */
166 const char EXP_CHARS[] = "eE";
168 /* Chars that mean this number is a floating point constant */
171 const char FLT_CHARS[] = "rRsSfFdDxXpP";
173 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
174 changed in read.c. Ideally it shouldn't have to know about it at all,
175 but nothing is ideal around here. */
177 static unsigned char octal[256];
178 #define isoctal(c) octal[(unsigned char) (c)]
179 static unsigned char toHex[256];
184 unsigned long opcode;
185 struct nlist *nlistp;
188 bfd_reloc_code_real_type reloc;
191 struct sparc_it the_insn, set_insn;
193 static void output_insn
194 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
196 /* Table of arguments to -A.
197 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
198 for this use. That table is for opcodes only. This table is for opcodes
201 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
202 v8plusa, v9, v9a, v9_64};
204 static struct sparc_arch {
207 enum sparc_arch_types arch_type;
208 /* Default word size, as specified during configuration.
209 A value of zero means can't be used to specify default architecture. */
210 int default_arch_size;
211 /* Allowable arg to -A? */
213 } sparc_arch_table[] = {
214 { "v6", "v6", v6, 0, 1 },
215 { "v7", "v7", v7, 0, 1 },
216 { "v8", "v8", v8, 32, 1 },
217 { "sparclet", "sparclet", sparclet, 32, 1 },
218 { "sparclite", "sparclite", sparclite, 32, 1 },
219 { "sparc86x", "sparclite", sparc86x, 32, 1 },
220 { "v8plus", "v9", v9, 0, 1 },
221 { "v8plusa", "v9a", v9, 0, 1 },
222 { "v9", "v9", v9, 0, 1 },
223 { "v9a", "v9a", v9, 0, 1 },
224 /* This exists to allow configure.in/Makefile.in to pass one
225 value to specify both the default machine and default word size. */
226 { "v9-64", "v9", v9, 64, 0 },
227 { NULL, NULL, v8, 0, 0 }
230 /* Variant of default_arch */
231 static enum sparc_arch_types default_arch_type;
233 static struct sparc_arch *
237 struct sparc_arch *sa;
239 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
240 if (strcmp (sa->name, name) == 0)
242 if (sa->name == NULL)
247 /* Initialize the default opcode arch and word size from the default
248 architecture name. */
253 struct sparc_arch *sa = lookup_arch (default_arch);
256 || sa->default_arch_size == 0)
257 as_fatal (_("Invalid default architecture, broken assembler."));
259 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
260 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
261 as_fatal (_("Bad opcode table, broken assembler."));
262 default_arch_size = sparc_arch_size = sa->default_arch_size;
264 default_arch_type = sa->arch_type;
267 /* Called by TARGET_FORMAT. */
270 sparc_target_format ()
272 /* We don't get a chance to initialize anything before we're called,
273 so handle that now. */
274 if (! default_init_p)
275 init_default_arch ();
279 return "a.out-sparc-netbsd";
282 return target_big_endian ? "a.out-sunos-big" : "a.out-sparc-little";
284 return "a.out-sunos-big";
295 return "coff-sparc-lynx";
302 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
310 * Invocation line includes a switch not recognized by the base assembler.
311 * See if it's a processor-specific option. These are:
314 * Warn on architecture bumps. See also -A.
316 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
317 * Standard 32 bit architectures.
318 * -Av8plus, -Av8plusa
319 * Sparc64 in a 32 bit world.
321 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
322 * This used to only mean 64 bits, but properly specifying it
323 * complicated gcc's ASM_SPECs, so now opcode selection is
324 * specified orthogonally to word size (except when specifying
325 * the default, but that is an internal implementation detail).
326 * -xarch=v8plus, -xarch=v8plusa
327 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
329 * Select the architecture and possibly the file format.
330 * Instructions or features not supported by the selected
331 * architecture cause fatal errors.
333 * The default is to start at v6, and bump the architecture up
334 * whenever an instruction is seen at a higher level. In 32 bit
335 * environments, v9 is not bumped up to, the user must pass
338 * If -bump is specified, a warning is printing when bumping to
341 * If an architecture is specified, all instructions must match
342 * that architecture. Any higher level instructions are flagged
343 * as errors. Note that in the 32 bit environment specifying
344 * -Av8plus does not automatically create a v8plus object file, a
345 * v9 insn must be seen.
347 * If both an architecture and -bump are specified, the
348 * architecture starts at the specified level, but bumps are
349 * warnings. Note that we can't set `current_architecture' to
350 * the requested level in this case: in the 32 bit environment,
351 * we still must avoid creating v8plus object files unless v9
355 * Bumping between incompatible architectures is always an
356 * error. For example, from sparclite to v9.
360 CONST char *md_shortopts = "A:K:VQ:sq";
363 CONST char *md_shortopts = "A:k";
365 CONST char *md_shortopts = "A:";
368 struct option md_longopts[] = {
369 #define OPTION_BUMP (OPTION_MD_BASE)
370 {"bump", no_argument, NULL, OPTION_BUMP},
371 #define OPTION_SPARC (OPTION_MD_BASE + 1)
372 {"sparc", no_argument, NULL, OPTION_SPARC},
373 #define OPTION_XARCH (OPTION_MD_BASE + 2)
374 {"xarch", required_argument, NULL, OPTION_XARCH},
376 #define OPTION_32 (OPTION_MD_BASE + 3)
377 {"32", no_argument, NULL, OPTION_32},
378 #define OPTION_64 (OPTION_MD_BASE + 4)
379 {"64", no_argument, NULL, OPTION_64},
380 #define OPTION_TSO (OPTION_MD_BASE + 5)
381 {"TSO", no_argument, NULL, OPTION_TSO},
382 #define OPTION_PSO (OPTION_MD_BASE + 6)
383 {"PSO", no_argument, NULL, OPTION_PSO},
384 #define OPTION_RMO (OPTION_MD_BASE + 7)
385 {"RMO", no_argument, NULL, OPTION_RMO},
387 #ifdef SPARC_BIENDIAN
388 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
389 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
390 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
391 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
393 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
394 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
395 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
396 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
397 {NULL, no_argument, NULL, 0}
399 size_t md_longopts_size = sizeof(md_longopts);
402 md_parse_option (c, arg)
406 /* We don't get a chance to initialize anything before we're called,
407 so handle that now. */
408 if (! default_init_p)
409 init_default_arch ();
415 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
419 /* This is for compatibility with Sun's assembler. */
420 if (strcmp (arg, "v8plus") != 0
421 && strcmp (arg, "v8plusa") != 0)
423 as_bad (_("invalid architecture -xarch=%s"), arg);
431 struct sparc_arch *sa;
432 enum sparc_opcode_arch_val opcode_arch;
434 sa = lookup_arch (arg);
436 || ! sa->user_option_p)
438 as_bad (_("invalid architecture -A%s"), arg);
442 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
443 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
444 as_fatal (_("Bad opcode table, broken assembler."));
446 max_architecture = opcode_arch;
447 architecture_requested = 1;
452 /* Ignore -sparc, used by SunOS make default .s.o rule. */
455 case OPTION_ENFORCE_ALIGNED_DATA:
456 enforce_aligned_data = 1;
459 #ifdef SPARC_BIENDIAN
460 case OPTION_LITTLE_ENDIAN:
461 target_big_endian = 0;
462 if (default_arch_type != sparclet)
463 as_fatal ("This target does not support -EL");
465 case OPTION_LITTLE_ENDIAN_DATA:
466 target_little_endian_data = 1;
467 target_big_endian = 0;
468 if (default_arch_type != sparc86x
469 && default_arch_type != v9)
470 as_fatal ("This target does not support --little-endian-data");
472 case OPTION_BIG_ENDIAN:
473 target_big_endian = 1;
487 const char **list, **l;
489 sparc_arch_size = c == OPTION_32 ? 32 : 64;
490 list = bfd_target_list ();
491 for (l = list; *l != NULL; l++)
493 if (sparc_arch_size == 32)
495 if (strcmp (*l, "elf32-sparc") == 0)
500 if (strcmp (*l, "elf64-sparc") == 0)
505 as_fatal (_("No compiled in support for %d bit object file format"),
512 sparc_memory_model = MM_TSO;
516 sparc_memory_model = MM_PSO;
520 sparc_memory_model = MM_RMO;
528 /* Qy - do emit .comment
529 Qn - do not emit .comment */
533 /* use .stab instead of .stab.excl */
537 /* quick -- native assembler does fewer checks */
541 if (strcmp (arg, "PIC") != 0)
542 as_warn (_("Unrecognized option following -K"));
556 md_show_usage (stream)
559 const struct sparc_arch *arch;
561 /* We don't get a chance to initialize anything before we're called,
562 so handle that now. */
563 if (! default_init_p)
564 init_default_arch ();
566 fprintf(stream, _("SPARC options:\n"));
567 for (arch = &sparc_arch_table[0]; arch->name; arch++)
569 if (arch != &sparc_arch_table[0])
570 fprintf (stream, " | ");
571 if (arch->user_option_p)
572 fprintf (stream, "-A%s", arch->name);
574 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
575 fprintf (stream, _("\
576 specify variant of SPARC architecture\n\
577 -bump warn when assembler switches architectures\n\
579 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
581 fprintf (stream, _("\
582 -k generate PIC\n"));
585 fprintf (stream, _("\
586 -32 create 32 bit object file\n\
587 -64 create 64 bit object file\n"));
588 fprintf (stream, _("\
589 [default is %d]\n"), default_arch_size);
590 fprintf (stream, _("\
591 -TSO use Total Store Ordering\n\
592 -PSO use Partial Store Ordering\n\
593 -RMO use Relaxed Memory Ordering\n"));
594 fprintf (stream, _("\
595 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
596 fprintf (stream, _("\
597 -KPIC generate PIC\n\
598 -V print assembler version number\n\
603 #ifdef SPARC_BIENDIAN
604 fprintf (stream, _("\
605 -EL generate code for a little endian machine\n\
606 -EB generate code for a big endian machine\n\
607 --little-endian-data generate code for a machine having big endian\n\
608 instructions and little endian data."));
612 /* sparc64 priviledged registers */
614 struct priv_reg_entry
620 struct priv_reg_entry priv_reg_table[] =
639 {"", -1}, /* end marker */
642 /* v9a specific asrs */
644 struct priv_reg_entry v9a_asr_table[] =
653 {"clear_softint", 21},
654 {"", -1}, /* end marker */
658 cmp_reg_entry (parg, qarg)
662 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
663 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
665 return strcmp (q->name, p->name);
668 /* This function is called once, at assembler startup time. It should
669 set up all the tables, etc. that the MD part of the assembler will need. */
674 register const char *retval = NULL;
676 register unsigned int i = 0;
678 /* We don't get a chance to initialize anything before md_parse_option
679 is called, and it may not be called, so handle default initialization
680 now if not already done. */
681 if (! default_init_p)
682 init_default_arch ();
684 op_hash = hash_new ();
686 while (i < (unsigned int) sparc_num_opcodes)
688 const char *name = sparc_opcodes[i].name;
689 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
692 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
693 sparc_opcodes[i].name, retval);
698 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
700 fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
701 sparc_opcodes[i].name, sparc_opcodes[i].args);
706 while (i < (unsigned int) sparc_num_opcodes
707 && !strcmp (sparc_opcodes[i].name, name));
711 as_fatal (_("Broken assembler. No assembly attempted."));
713 for (i = '0'; i < '8'; ++i)
715 for (i = '0'; i <= '9'; ++i)
717 for (i = 'a'; i <= 'f'; ++i)
718 toHex[i] = i + 10 - 'a';
719 for (i = 'A'; i <= 'F'; ++i)
720 toHex[i] = i + 10 - 'A';
722 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
723 sizeof (priv_reg_table[0]), cmp_reg_entry);
725 /* If -bump, record the architecture level at which we start issuing
726 warnings. The behaviour is different depending upon whether an
727 architecture was explicitly specified. If it wasn't, we issue warnings
728 for all upwards bumps. If it was, we don't start issuing warnings until
729 we need to bump beyond the requested architecture or when we bump between
730 conflicting architectures. */
733 && architecture_requested)
735 /* `max_architecture' records the requested architecture.
736 Issue warnings if we go above it. */
737 warn_after_architecture = max_architecture;
739 /* Find the highest architecture level that doesn't conflict with
740 the requested one. */
741 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
742 max_architecture > warn_after_architecture;
744 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
745 warn_after_architecture))
750 /* Called after all assembly has been done. */
755 if (sparc_arch_size == 64)
757 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
758 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
760 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
764 if (current_architecture == SPARC_OPCODE_ARCH_V9)
765 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
766 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
767 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
768 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
769 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
770 else if (default_arch_type == sparc86x && target_little_endian_data)
771 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
774 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
775 be but for now it is (since that's the way it's always been
777 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
782 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
785 in_signed_range (val, max)
786 bfd_signed_vma val, max;
797 /* Return non-zero if VAL is in the range 0 to MAX. */
800 in_unsigned_range (val, max)
808 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
809 (e.g. -15 to +31). */
812 in_bitfield_range (val, max)
813 bfd_signed_vma val, max;
819 if (val < ~(max >> 1))
833 for (i = 0; (mask & 1) == 0; ++i)
838 /* Implement big shift right. */
844 if (sizeof (bfd_vma) <= 4 && amount >= 32)
845 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
846 return val >> amount;
849 /* For communication between sparc_ip and get_expression. */
850 static char *expr_end;
852 /* For communication between md_assemble and sparc_ip. */
853 static int special_case;
855 /* Values for `special_case'.
856 Instructions that require wierd handling because they're longer than
858 #define SPECIAL_CASE_NONE 0
859 #define SPECIAL_CASE_SET 1
860 #define SPECIAL_CASE_SETSW 2
861 #define SPECIAL_CASE_SETX 3
862 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
863 #define SPECIAL_CASE_FDIV 4
865 /* Bit masks of various insns. */
866 #define NOP_INSN 0x01000000
867 #define OR_INSN 0x80100000
868 #define FMOVS_INSN 0x81A00020
869 #define SETHI_INSN 0x01000000
870 #define SLLX_INSN 0x81281000
871 #define SRA_INSN 0x81380000
873 /* The last instruction to be assembled. */
874 static const struct sparc_opcode *last_insn;
875 /* The assembled opcode of `last_insn'. */
876 static unsigned long last_opcode;
878 /* Main entry point to assemble one instruction. */
884 const struct sparc_opcode *insn;
887 special_case = SPECIAL_CASE_NONE;
888 sparc_ip (str, &insn);
890 /* We warn about attempts to put a floating point branch in a delay slot,
891 unless the delay slot has been annulled. */
894 && (insn->flags & F_FBR) != 0
895 && (last_insn->flags & F_DELAYED) != 0
896 /* ??? This test isn't completely accurate. We assume anything with
897 F_{UNBR,CONDBR,FBR} set is annullable. */
898 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
899 || (last_opcode & ANNUL) == 0))
900 as_warn (_("FP branch in delay slot"));
902 /* SPARC before v9 requires a nop instruction between a floating
903 point instruction and a floating point branch. We insert one
904 automatically, with a warning. */
905 if (max_architecture < SPARC_OPCODE_ARCH_V9
908 && (insn->flags & F_FBR) != 0
909 && (last_insn->flags & F_FLOAT) != 0)
911 struct sparc_it nop_insn;
913 nop_insn.opcode = NOP_INSN;
914 nop_insn.reloc = BFD_RELOC_NONE;
915 output_insn (insn, &nop_insn);
916 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
919 switch (special_case)
921 case SPECIAL_CASE_NONE:
923 output_insn (insn, &the_insn);
926 case SPECIAL_CASE_SET:
930 /* "set" is not defined for negative numbers in v9: it doesn't yield
931 what you expect it to. */
932 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
933 && the_insn.exp.X_op == O_constant)
935 if (the_insn.exp.X_add_number < 0)
936 as_warn (_("set: used with negative number"));
937 else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff)
938 as_warn (_("set: number larger than 4294967295"));
941 /* See if operand is absolute and small; skip sethi if so. */
942 if (the_insn.exp.X_op != O_constant
943 || the_insn.exp.X_add_number >= (1 << 12)
944 || the_insn.exp.X_add_number < -(1 << 12))
946 output_insn (insn, &the_insn);
949 /* See if operand has no low-order bits; skip OR if so. */
950 if (the_insn.exp.X_op != O_constant
951 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
954 int rd = (the_insn.opcode & RD (~0)) >> 25;
955 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
958 | (the_insn.exp.X_add_number
959 & (need_hi22_p ? 0x3ff : 0x1fff)));
960 the_insn.reloc = (the_insn.exp.X_op != O_constant
963 output_insn (insn, &the_insn);
968 case SPECIAL_CASE_SETSW:
970 /* FIXME: Not finished. */
974 case SPECIAL_CASE_SETX:
976 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
977 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
978 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
980 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
981 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
982 /* Output directly to dst reg if lower 32 bits are all zero. */
983 int upper_dstreg = (the_insn.exp.X_op == O_constant
984 && lower32 == 0) ? dstreg : tmpreg;
985 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
987 /* The tmp reg should not be the dst reg. */
988 if (tmpreg == dstreg)
989 as_warn (_("setx: temporary register same as destination register"));
991 /* Reset X_add_number, we've extracted it as upper32/lower32.
992 Otherwise fixup_segment will complain about not being able to
993 write an 8 byte number in a 4 byte field. */
994 the_insn.exp.X_add_number = 0;
996 /* ??? Obviously there are other optimizations we can do
997 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
998 doing some of these. Later. If you do change things, try to
999 change all of this to be table driven as well. */
1001 /* What to output depends on the number if it's constant.
1002 Compute that first, then output what we've decided upon. */
1003 if (the_insn.exp.X_op != O_constant)
1004 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1007 /* Only need hh22 if `or' insn can't handle constant. */
1008 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1011 /* Does bottom part (after sethi) have bits? */
1012 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1013 /* No hh22, but does upper32 still have bits we can't set
1017 && (upper32 != -1 || lower32 >= 0)))
1020 /* If the lower half is all zero, we build the upper half directly
1021 into the dst reg. */
1023 /* Need lower half if number is zero. */
1024 || (! need_hh22_p && ! need_hm10_p))
1026 /* No need for sethi if `or' insn can handle constant. */
1027 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1028 /* Note that we can't use a negative constant in the `or'
1029 insn unless the upper 32 bits are all ones. */
1030 || (lower32 < 0 && upper32 != -1))
1033 /* Does bottom part (after sethi) have bits? */
1034 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1036 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1037 /* Need `or' if we didn't set anything else. */
1038 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1045 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1046 | ((upper32 >> 10) & 0x3fffff));
1047 the_insn.reloc = (the_insn.exp.X_op != O_constant
1048 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1049 output_insn (insn, &the_insn);
1054 the_insn.opcode = (OR_INSN
1055 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1059 & (need_hh22_p ? 0x3ff : 0x1fff)));
1060 the_insn.reloc = (the_insn.exp.X_op != O_constant
1061 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1062 output_insn (insn, &the_insn);
1067 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1068 | ((lower32 >> 10) & 0x3fffff));
1069 the_insn.reloc = BFD_RELOC_HI22;
1070 output_insn (insn, &the_insn);
1075 /* FIXME: One nice optimization to do here is to OR the low part
1076 with the highpart if hi22 isn't needed and the low part is
1078 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1082 & (need_hi22_p ? 0x3ff : 0x1fff)));
1083 the_insn.reloc = BFD_RELOC_LO10;
1084 output_insn (insn, &the_insn);
1087 /* If we needed to build the upper part, shift it into place. */
1088 if (need_hh22_p || need_hm10_p)
1090 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1092 the_insn.reloc = BFD_RELOC_NONE;
1093 output_insn (insn, &the_insn);
1096 /* If we needed to build both upper and lower parts, OR them together. */
1097 if ((need_hh22_p || need_hm10_p)
1098 && (need_hi22_p || need_lo10_p))
1100 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1102 the_insn.reloc = BFD_RELOC_NONE;
1103 output_insn (insn, &the_insn);
1105 /* We didn't need both regs, but we may have to sign extend lower32. */
1106 else if (need_hi22_p && upper32 == -1)
1108 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1110 the_insn.reloc = BFD_RELOC_NONE;
1111 output_insn (insn, &the_insn);
1116 case SPECIAL_CASE_FDIV:
1118 int rd = (the_insn.opcode >> 25) & 0x1f;
1120 output_insn (insn, &the_insn);
1122 /* According to information leaked from Sun, the "fdiv" instructions
1123 on early SPARC machines would produce incorrect results sometimes.
1124 The workaround is to add an fmovs of the destination register to
1125 itself just after the instruction. This was true on machines
1126 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1127 assert (the_insn.reloc == BFD_RELOC_NONE);
1128 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1129 output_insn (insn, &the_insn);
1134 as_fatal (_("failed special case insn sanity check"));
1138 /* Subroutine of md_assemble to do the actual parsing. */
1141 sparc_ip (str, pinsn)
1143 const struct sparc_opcode **pinsn;
1145 char *error_message = "";
1149 const struct sparc_opcode *insn;
1151 unsigned long opcode;
1152 unsigned int mask = 0;
1157 for (s = str; islower ((unsigned char) *s) || (*s >= '0' && *s <= '3'); ++s)
1175 as_fatal (_("Unknown opcode: `%s'"), str);
1177 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1181 as_bad (_("Unknown opcode: `%s'"), str);
1192 opcode = insn->match;
1193 memset (&the_insn, '\0', sizeof (the_insn));
1194 the_insn.reloc = BFD_RELOC_NONE;
1198 * Build the opcode, checking as we go to make
1199 * sure that the operands match
1201 for (args = insn->args;; ++args)
1209 /* Parse a series of masks. */
1216 if (! parse_keyword_arg (sparc_encode_membar, &s,
1219 error_message = _(": invalid membar mask name");
1223 while (*s == ' ') { ++s; continue; }
1224 if (*s == '|' || *s == '+')
1226 while (*s == ' ') { ++s; continue; }
1231 if (! parse_const_expr_arg (&s, &kmask))
1233 error_message = _(": invalid membar mask expression");
1236 if (kmask < 0 || kmask > 127)
1238 error_message = _(": invalid membar mask number");
1243 opcode |= MEMBAR (kmask);
1251 /* Parse a prefetch function. */
1254 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1256 error_message = _(": invalid prefetch function name");
1262 if (! parse_const_expr_arg (&s, &fcn))
1264 error_message = _(": invalid prefetch function expression");
1267 if (fcn < 0 || fcn > 31)
1269 error_message = _(": invalid prefetch function number");
1279 /* Parse a sparc64 privileged register. */
1282 struct priv_reg_entry *p = priv_reg_table;
1283 unsigned int len = 9999999; /* init to make gcc happy */
1286 while (p->name[0] > s[0])
1288 while (p->name[0] == s[0])
1290 len = strlen (p->name);
1291 if (strncmp (p->name, s, len) == 0)
1295 if (p->name[0] != s[0])
1297 error_message = _(": unrecognizable privileged register");
1301 opcode |= (p->regnum << 14);
1303 opcode |= (p->regnum << 25);
1309 error_message = _(": unrecognizable privileged register");
1315 /* Parse a v9a ancillary state register. */
1318 struct priv_reg_entry *p = v9a_asr_table;
1319 unsigned int len = 9999999; /* init to make gcc happy */
1322 while (p->name[0] > s[0])
1324 while (p->name[0] == s[0])
1326 len = strlen (p->name);
1327 if (strncmp (p->name, s, len) == 0)
1331 if (p->name[0] != s[0])
1333 error_message = _(": unrecognizable v9a ancillary state register");
1336 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1338 error_message = _(": rd on write only ancillary state register");
1342 opcode |= (p->regnum << 14);
1344 opcode |= (p->regnum << 25);
1350 error_message = _(": unrecognizable v9a ancillary state register");
1356 if (strncmp (s, "%asr", 4) == 0)
1360 if (isdigit ((unsigned char) *s))
1364 while (isdigit ((unsigned char) *s))
1366 num = num * 10 + *s - '0';
1370 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1372 if (num < 16 || 31 < num)
1374 error_message = _(": asr number must be between 16 and 31");
1380 if (num < 0 || 31 < num)
1382 error_message = _(": asr number must be between 0 and 31");
1387 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1392 error_message = _(": expecting %asrN");
1399 the_insn.reloc = BFD_RELOC_SPARC_11;
1403 the_insn.reloc = BFD_RELOC_SPARC_10;
1407 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1408 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1409 the_insn.reloc = BFD_RELOC_SPARC_5;
1411 the_insn.reloc = BFD_RELOC_SPARC13;
1412 /* These fields are unsigned, but for upward compatibility,
1413 allow negative values as well. */
1417 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1418 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1419 the_insn.reloc = BFD_RELOC_SPARC_6;
1421 the_insn.reloc = BFD_RELOC_SPARC13;
1422 /* These fields are unsigned, but for upward compatibility,
1423 allow negative values as well. */
1427 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1432 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1437 if (*s == 'p' && s[1] == 'n')
1445 if (*s == 'p' && s[1] == 't')
1457 if (strncmp (s, "%icc", 4) == 0)
1469 if (strncmp (s, "%xcc", 4) == 0)
1481 if (strncmp (s, "%fcc0", 5) == 0)
1493 if (strncmp (s, "%fcc1", 5) == 0)
1505 if (strncmp (s, "%fcc2", 5) == 0)
1517 if (strncmp (s, "%fcc3", 5) == 0)
1525 if (strncmp (s, "%pc", 3) == 0)
1533 if (strncmp (s, "%tick", 5) == 0)
1540 case '\0': /* end of args */
1559 case '[': /* these must match exactly */
1567 case '#': /* must be at least one digit */
1568 if (isdigit ((unsigned char) *s++))
1570 while (isdigit ((unsigned char) *s))
1578 case 'C': /* coprocessor state register */
1579 if (strncmp (s, "%csr", 4) == 0)
1586 case 'b': /* next operand is a coprocessor register */
1589 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1592 if (isdigit ((unsigned char) *s))
1594 mask = 10 * (mask - '0') + (*s++ - '0');
1608 opcode |= mask << 14;
1616 opcode |= mask << 25;
1622 case 'r': /* next operand must be a register */
1632 case 'f': /* frame pointer */
1640 case 'g': /* global register */
1641 if (isoctal (c = *s++))
1648 case 'i': /* in register */
1649 if (isoctal (c = *s++))
1651 mask = c - '0' + 24;
1656 case 'l': /* local register */
1657 if (isoctal (c = *s++))
1659 mask = (c - '0' + 16);
1664 case 'o': /* out register */
1665 if (isoctal (c = *s++))
1667 mask = (c - '0' + 8);
1672 case 's': /* stack pointer */
1680 case 'r': /* any register */
1681 if (!isdigit ((unsigned char) (c = *s++)))
1696 if (isdigit ((unsigned char) *s))
1698 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1714 /* Got the register, now figure out where
1715 it goes in the opcode. */
1719 opcode |= mask << 14;
1727 opcode |= mask << 25;
1731 opcode |= (mask << 25) | (mask << 14);
1735 opcode |= (mask << 25) | (mask << 0);
1741 case 'e': /* next operand is a floating point register */
1756 && ((format = *s) == 'f')
1757 && isdigit ((unsigned char) *++s))
1759 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1761 mask = 10 * mask + (*s - '0');
1762 } /* read the number */
1770 } /* register must be even numbered */
1778 } /* register must be multiple of 4 */
1782 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1783 error_message = _(": There are only 64 f registers; [0-63]");
1785 error_message = _(": There are only 32 f registers; [0-31]");
1788 else if (mask >= 32)
1790 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1793 mask -= 31; /* wrap high bit */
1797 error_message = _(": There are only 32 f registers; [0-31]");
1805 } /* if not an 'f' register. */
1812 opcode |= RS1 (mask);
1819 opcode |= RS2 (mask);
1825 opcode |= RD (mask);
1834 if (strncmp (s, "%fsr", 4) == 0)
1841 case '0': /* 64 bit immediate (setx insn) */
1842 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1845 case 'h': /* high 22 bits */
1846 the_insn.reloc = BFD_RELOC_HI22;
1849 case 'l': /* 22 bit PC relative immediate */
1850 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
1854 case 'L': /* 30 bit immediate */
1855 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
1859 case 'n': /* 22 bit immediate */
1860 the_insn.reloc = BFD_RELOC_SPARC22;
1863 case 'i': /* 13 bit immediate */
1864 the_insn.reloc = BFD_RELOC_SPARC13;
1872 /* Check for %hi, etc. */
1876 /* The name as it appears in assembler. */
1878 /* strlen (name), precomputed for speed */
1880 /* The reloc this pseudo-op translates to. */
1882 /* Non-zero if for v9 only. */
1884 /* Non-zero if can be used in pc-relative contexts. */
1885 int pcrel_p;/*FIXME:wip*/
1887 /* hix/lox must appear before hi/lo so %hix won't be
1888 mistaken for %hi. */
1889 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
1890 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
1891 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
1892 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
1893 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
1894 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
1895 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
1896 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
1897 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
1898 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
1899 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
1900 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
1905 for (o = ops; o->name; o++)
1906 if (strncmp (s + 1, o->name, o->len) == 0)
1908 if (o->name == NULL)
1911 the_insn.reloc = o->reloc;
1916 /* Note that if the get_expression() fails, we will still
1917 have created U entries in the symbol table for the
1918 'symbols' in the input string. Try not to create U
1919 symbols for registers, etc. */
1921 /* This stuff checks to see if the expression ends in
1922 +%reg. If it does, it removes the register from
1923 the expression, and re-sets 's' to point to the
1928 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
1930 if (s1 != s && isdigit ((unsigned char) s1[-1]))
1932 if (s1[-2] == '%' && s1[-3] == '+')
1936 (void) get_expression (s);
1941 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1945 (void) get_expression (s);
1952 (void) get_expression (s);
1955 /* Check for constants that don't require emitting a reloc. */
1956 if (the_insn.exp.X_op == O_constant
1957 && the_insn.exp.X_add_symbol == 0
1958 && the_insn.exp.X_op_symbol == 0)
1960 /* For pc-relative call instructions, we reject
1961 constants to get better code. */
1963 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
1964 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
1966 error_message = _(": PC-relative operand can't be a constant");
1970 /* Constants that won't fit are checked in md_apply_fix3
1971 and bfd_install_relocation.
1972 ??? It would be preferable to install the constants
1973 into the insn here and save having to create a fixS
1974 for each one. There already exists code to handle
1975 all the various cases (e.g. in md_apply_fix3 and
1976 bfd_install_relocation) so duplicating all that code
1977 here isn't right. */
1997 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
1999 error_message = _(": invalid ASI name");
2005 if (! parse_const_expr_arg (&s, &asi))
2007 error_message = _(": invalid ASI expression");
2010 if (asi < 0 || asi > 255)
2012 error_message = _(": invalid ASI number");
2016 opcode |= ASI (asi);
2018 } /* alternate space */
2021 if (strncmp (s, "%psr", 4) == 0)
2028 case 'q': /* floating point queue */
2029 if (strncmp (s, "%fq", 3) == 0)
2036 case 'Q': /* coprocessor queue */
2037 if (strncmp (s, "%cq", 3) == 0)
2045 if (strcmp (str, "set") == 0
2046 || strcmp (str, "setuw") == 0)
2048 special_case = SPECIAL_CASE_SET;
2051 else if (strcmp (str, "setsw") == 0)
2053 special_case = SPECIAL_CASE_SETSW;
2056 else if (strcmp (str, "setx") == 0)
2058 special_case = SPECIAL_CASE_SETX;
2061 else if (strncmp (str, "fdiv", 4) == 0)
2063 special_case = SPECIAL_CASE_FDIV;
2069 if (strncmp (s, "%asi", 4) != 0)
2075 if (strncmp (s, "%fprs", 5) != 0)
2081 if (strncmp (s, "%ccr", 4) != 0)
2087 if (strncmp (s, "%tbr", 4) != 0)
2093 if (strncmp (s, "%wim", 4) != 0)
2100 char *push = input_line_pointer;
2103 input_line_pointer = s;
2105 if (e.X_op == O_constant)
2107 int n = e.X_add_number;
2108 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2109 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2111 opcode |= e.X_add_number << 5;
2114 as_bad (_("non-immediate OPF operand, ignored"));
2115 s = input_line_pointer;
2116 input_line_pointer = push;
2121 if (strncmp (s, "%y", 2) != 0)
2129 /* Parse a sparclet cpreg. */
2131 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2133 error_message = _(": invalid cpreg name");
2136 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2141 as_fatal (_("failed sanity check."));
2142 } /* switch on arg code */
2144 /* Break out of for() loop. */
2146 } /* for each arg that we expect */
2151 /* Args don't match. */
2152 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2153 && (insn->name == insn[1].name
2154 || !strcmp (insn->name, insn[1].name)))
2162 as_bad (_("Illegal operands%s"), error_message);
2168 /* We have a match. Now see if the architecture is ok. */
2169 int needed_arch_mask = insn->architecture;
2173 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2174 | (1 << SPARC_OPCODE_ARCH_V9A));
2175 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2178 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2180 /* Can we bump up the architecture? */
2181 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2183 enum sparc_opcode_arch_val needed_architecture =
2184 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2185 & needed_arch_mask);
2187 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2189 && needed_architecture > warn_after_architecture)
2191 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2192 sparc_opcode_archs[current_architecture].name,
2193 sparc_opcode_archs[needed_architecture].name,
2195 warn_after_architecture = needed_architecture;
2197 current_architecture = needed_architecture;
2200 /* ??? This seems to be a bit fragile. What if the next entry in
2201 the opcode table is the one we want and it is supported?
2202 It is possible to arrange the table today so that this can't
2203 happen but what about tomorrow? */
2206 int arch,printed_one_p = 0;
2208 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2210 /* Create a list of the architectures that support the insn. */
2211 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2213 arch = sparc_ffs (needed_arch_mask);
2214 while ((1 << arch) <= needed_arch_mask)
2216 if ((1 << arch) & needed_arch_mask)
2220 strcpy (p, sparc_opcode_archs[arch].name);
2227 as_bad (_("Architecture mismatch on \"%s\"."), str);
2228 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2230 sparc_opcode_archs[max_architecture].name);
2236 } /* forever looking for a match */
2238 the_insn.opcode = opcode;
2241 /* Parse an argument that can be expressed as a keyword.
2242 (eg: #StoreStore or %ccfr).
2243 The result is a boolean indicating success.
2244 If successful, INPUT_POINTER is updated. */
2247 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2248 int (*lookup_fn) PARAMS ((const char *));
2249 char **input_pointerP;
2255 p = *input_pointerP;
2256 for (q = p + (*p == '#' || *p == '%');
2257 isalnum ((unsigned char) *q) || *q == '_';
2262 value = (*lookup_fn) (p);
2267 *input_pointerP = q;
2271 /* Parse an argument that is a constant expression.
2272 The result is a boolean indicating success. */
2275 parse_const_expr_arg (input_pointerP, valueP)
2276 char **input_pointerP;
2279 char *save = input_line_pointer;
2282 input_line_pointer = *input_pointerP;
2283 /* The next expression may be something other than a constant
2284 (say if we're not processing the right variant of the insn).
2285 Don't call expression unless we're sure it will succeed as it will
2286 signal an error (which we want to defer until later). */
2287 /* FIXME: It might be better to define md_operand and have it recognize
2288 things like %asi, etc. but continuing that route through to the end
2289 is a lot of work. */
2290 if (*input_line_pointer == '%')
2292 input_line_pointer = save;
2296 *input_pointerP = input_line_pointer;
2297 input_line_pointer = save;
2298 if (exp.X_op != O_constant)
2300 *valueP = exp.X_add_number;
2304 /* Subroutine of sparc_ip to parse an expression. */
2307 get_expression (str)
2313 save_in = input_line_pointer;
2314 input_line_pointer = str;
2315 seg = expression (&the_insn.exp);
2316 if (seg != absolute_section
2317 && seg != text_section
2318 && seg != data_section
2319 && seg != bss_section
2320 && seg != undefined_section)
2322 the_insn.error = _("bad segment");
2323 expr_end = input_line_pointer;
2324 input_line_pointer = save_in;
2327 expr_end = input_line_pointer;
2328 input_line_pointer = save_in;
2332 /* Subroutine of md_assemble to output one insn. */
2335 output_insn (insn, the_insn)
2336 const struct sparc_opcode *insn;
2337 struct sparc_it *the_insn;
2339 char *toP = frag_more (4);
2341 /* put out the opcode */
2342 if (INSN_BIG_ENDIAN)
2343 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2345 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2347 /* put out the symbol-dependent stuff */
2348 if (the_insn->reloc != BFD_RELOC_NONE)
2350 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2351 (toP - frag_now->fr_literal), /* where */
2356 /* Turn off overflow checking in fixup_segment. We'll do our
2357 own overflow checking in md_apply_fix3. This is necessary because
2358 the insn size is 4 and fixup_segment will signal an overflow for
2359 large 8 byte quantities. */
2360 fixP->fx_no_overflow = 1;
2364 last_opcode = the_insn->opcode;
2368 This is identical to the md_atof in m68k.c. I think this is right,
2371 Turn a string in input_line_pointer into a floating point constant of type
2372 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2373 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2376 /* Equal to MAX_PRECISION in atof-ieee.c */
2377 #define MAX_LITTLENUMS 6
2380 md_atof (type, litP, sizeP)
2386 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2417 return _("Bad call to MD_ATOF()");
2420 t = atof_ieee (input_line_pointer, type, words);
2422 input_line_pointer = t;
2423 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2425 if (target_big_endian)
2427 for (i = 0; i < prec; i++)
2429 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2430 litP += sizeof (LITTLENUM_TYPE);
2435 for (i = prec - 1; i >= 0; i--)
2437 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2438 litP += sizeof (LITTLENUM_TYPE);
2445 /* Write a value out to the object file, using the appropriate
2449 md_number_to_chars (buf, val, n)
2454 if (target_big_endian)
2455 number_to_chars_bigendian (buf, val, n);
2457 number_to_chars_littleendian (buf, val, n);
2460 /* Apply a fixS to the frags, now that we know the value it ought to
2464 md_apply_fix3 (fixP, value, segment)
2469 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2475 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2477 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2480 /* FIXME: SPARC ELF relocations don't use an addend in the data
2481 field itself. This whole approach should be somehow combined
2482 with the calls to bfd_install_relocation. Also, the value passed
2483 in by fixup_segment includes the value of a defined symbol. We
2484 don't want to include the value of an externally visible symbol. */
2485 if (fixP->fx_addsy != NULL)
2487 if (fixP->fx_addsy->sy_used_in_reloc
2488 && (S_IS_EXTERNAL (fixP->fx_addsy)
2489 || S_IS_WEAK (fixP->fx_addsy)
2490 || (sparc_pic_code && ! fixP->fx_pcrel)
2491 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2492 && ((bfd_get_section_flags (stdoutput,
2493 S_GET_SEGMENT (fixP->fx_addsy))
2494 & SEC_LINK_ONCE) != 0
2495 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2497 sizeof ".gnu.linkonce" - 1) == 0)))
2498 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2499 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2500 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2501 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2506 /* This is a hack. There should be a better way to
2507 handle this. Probably in terms of howto fields, once
2508 we can look at these fixups in terms of howtos. */
2509 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2510 val += fixP->fx_where + fixP->fx_frag->fr_address;
2513 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2514 generate a reloc, then we just want to let the reloc addend set
2515 the value. We do not want to also stuff the addend into the
2516 object file. Including the addend in the object file works when
2517 doing a static link, because the linker will ignore the object
2518 file contents. However, the dynamic linker does not ignore the
2519 object file contents. */
2520 if (fixP->fx_addsy != NULL
2521 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2524 /* When generating PIC code, we do not want an addend for a reloc
2525 against a local symbol. We adjust fx_addnumber to cancel out the
2526 value already included in val, and to also cancel out the
2527 adjustment which bfd_install_relocation will create. */
2529 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2530 && fixP->fx_addsy != NULL
2531 && ! S_IS_COMMON (fixP->fx_addsy)
2532 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2533 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2535 /* When generating PIC code, we need to fiddle to get
2536 bfd_install_relocation to do the right thing for a PC relative
2537 reloc against a local symbol which we are going to keep. */
2539 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2540 && fixP->fx_addsy != NULL
2541 && (S_IS_EXTERNAL (fixP->fx_addsy)
2542 || S_IS_WEAK (fixP->fx_addsy))
2543 && S_IS_DEFINED (fixP->fx_addsy)
2544 && ! S_IS_COMMON (fixP->fx_addsy))
2547 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2551 /* If this is a data relocation, just output VAL. */
2553 if (fixP->fx_r_type == BFD_RELOC_16)
2555 md_number_to_chars (buf, val, 2);
2557 else if (fixP->fx_r_type == BFD_RELOC_32
2558 || fixP->fx_r_type == BFD_RELOC_SPARC_32LE)
2560 md_number_to_chars (buf, val, 4);
2562 else if (fixP->fx_r_type == BFD_RELOC_64)
2564 md_number_to_chars (buf, val, 8);
2568 /* It's a relocation against an instruction. */
2570 if (INSN_BIG_ENDIAN)
2571 insn = bfd_getb32 ((unsigned char *) buf);
2573 insn = bfd_getl32 ((unsigned char *) buf);
2575 switch (fixP->fx_r_type)
2577 case BFD_RELOC_32_PCREL_S2:
2579 /* FIXME: This increment-by-one deserves a comment of why it's
2581 if (! sparc_pic_code
2582 || fixP->fx_addsy == NULL
2583 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2585 insn |= val & 0x3fffffff;
2588 case BFD_RELOC_SPARC_11:
2589 if (! in_signed_range (val, 0x7ff))
2590 as_bad_where (fixP->fx_file, fixP->fx_line,
2591 _("relocation overflow"));
2592 insn |= val & 0x7ff;
2595 case BFD_RELOC_SPARC_10:
2596 if (! in_signed_range (val, 0x3ff))
2597 as_bad_where (fixP->fx_file, fixP->fx_line,
2598 _("relocation overflow"));
2599 insn |= val & 0x3ff;
2602 case BFD_RELOC_SPARC_7:
2603 if (! in_bitfield_range (val, 0x7f))
2604 as_bad_where (fixP->fx_file, fixP->fx_line,
2605 _("relocation overflow"));
2609 case BFD_RELOC_SPARC_6:
2610 if (! in_bitfield_range (val, 0x3f))
2611 as_bad_where (fixP->fx_file, fixP->fx_line,
2612 _("relocation overflow"));
2616 case BFD_RELOC_SPARC_5:
2617 if (! in_bitfield_range (val, 0x1f))
2618 as_bad_where (fixP->fx_file, fixP->fx_line,
2619 _("relocation overflow"));
2623 case BFD_RELOC_SPARC_WDISP16:
2624 /* FIXME: simplify */
2625 if (((val > 0) && (val & ~0x3fffc))
2626 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2627 as_bad_where (fixP->fx_file, fixP->fx_line,
2628 _("relocation overflow"));
2629 /* FIXME: The +1 deserves a comment. */
2630 val = (val >> 2) + 1;
2631 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2634 case BFD_RELOC_SPARC_WDISP19:
2635 /* FIXME: simplify */
2636 if (((val > 0) && (val & ~0x1ffffc))
2637 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2638 as_bad_where (fixP->fx_file, fixP->fx_line,
2639 _("relocation overflow"));
2640 /* FIXME: The +1 deserves a comment. */
2641 val = (val >> 2) + 1;
2642 insn |= val & 0x7ffff;
2645 case BFD_RELOC_SPARC_HH22:
2646 val = BSR (val, 32);
2647 /* intentional fallthrough */
2649 case BFD_RELOC_SPARC_LM22:
2650 case BFD_RELOC_HI22:
2651 if (!fixP->fx_addsy)
2653 insn |= (val >> 10) & 0x3fffff;
2657 /* FIXME: Need comment explaining why we do this. */
2662 case BFD_RELOC_SPARC22:
2663 if (val & ~0x003fffff)
2664 as_bad_where (fixP->fx_file, fixP->fx_line,
2665 _("relocation overflow"));
2666 insn |= (val & 0x3fffff);
2669 case BFD_RELOC_SPARC_HM10:
2670 val = BSR (val, 32);
2671 /* intentional fallthrough */
2673 case BFD_RELOC_LO10:
2674 if (!fixP->fx_addsy)
2676 insn |= val & 0x3ff;
2680 /* FIXME: Need comment explaining why we do this. */
2685 case BFD_RELOC_SPARC13:
2686 if (! in_signed_range (val, 0x1fff))
2687 as_bad_where (fixP->fx_file, fixP->fx_line,
2688 _("relocation overflow"));
2689 insn |= val & 0x1fff;
2692 case BFD_RELOC_SPARC_WDISP22:
2693 val = (val >> 2) + 1;
2695 case BFD_RELOC_SPARC_BASE22:
2696 insn |= val & 0x3fffff;
2699 case BFD_RELOC_SPARC_H44:
2700 if (!fixP->fx_addsy)
2704 insn |= tval & 0x3fffff;
2708 case BFD_RELOC_SPARC_M44:
2709 if (!fixP->fx_addsy)
2710 insn |= (val >> 12) & 0x3ff;
2713 case BFD_RELOC_SPARC_L44:
2714 if (!fixP->fx_addsy)
2715 insn |= val & 0xfff;
2718 case BFD_RELOC_SPARC_HIX22:
2719 if (!fixP->fx_addsy)
2721 val ^= ~ (offsetT) 0;
2722 insn |= (val >> 10) & 0x3fffff;
2726 case BFD_RELOC_SPARC_LOX10:
2727 if (!fixP->fx_addsy)
2728 insn |= 0x1c00 | (val & 0x3ff);
2731 case BFD_RELOC_NONE:
2733 as_bad_where (fixP->fx_file, fixP->fx_line,
2734 _("bad or unhandled relocation type: 0x%02x"),
2739 if (INSN_BIG_ENDIAN)
2740 bfd_putb32 (insn, (unsigned char *) buf);
2742 bfd_putl32 (insn, (unsigned char *) buf);
2745 /* Are we finished with this relocation now? */
2746 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2752 /* Translate internal representation of relocation info to BFD target
2755 tc_gen_reloc (section, fixp)
2760 bfd_reloc_code_real_type code;
2762 reloc = (arelent *) xmalloc (sizeof (arelent));
2764 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2765 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2767 switch (fixp->fx_r_type)
2771 case BFD_RELOC_HI22:
2772 case BFD_RELOC_LO10:
2773 case BFD_RELOC_32_PCREL_S2:
2774 case BFD_RELOC_SPARC13:
2775 case BFD_RELOC_SPARC_BASE13:
2776 case BFD_RELOC_SPARC_WDISP16:
2777 case BFD_RELOC_SPARC_WDISP19:
2778 case BFD_RELOC_SPARC_WDISP22:
2780 case BFD_RELOC_SPARC_5:
2781 case BFD_RELOC_SPARC_6:
2782 case BFD_RELOC_SPARC_7:
2783 case BFD_RELOC_SPARC_10:
2784 case BFD_RELOC_SPARC_11:
2785 case BFD_RELOC_SPARC_HH22:
2786 case BFD_RELOC_SPARC_HM10:
2787 case BFD_RELOC_SPARC_LM22:
2788 case BFD_RELOC_SPARC_PC_HH22:
2789 case BFD_RELOC_SPARC_PC_HM10:
2790 case BFD_RELOC_SPARC_PC_LM22:
2791 case BFD_RELOC_SPARC_H44:
2792 case BFD_RELOC_SPARC_M44:
2793 case BFD_RELOC_SPARC_L44:
2794 case BFD_RELOC_SPARC_HIX22:
2795 case BFD_RELOC_SPARC_LOX10:
2796 case BFD_RELOC_SPARC_32LE:
2797 code = fixp->fx_r_type;
2804 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2805 /* If we are generating PIC code, we need to generate a different
2809 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2811 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2818 case BFD_RELOC_32_PCREL_S2:
2819 if (! S_IS_DEFINED (fixp->fx_addsy)
2820 || S_IS_COMMON (fixp->fx_addsy)
2821 || S_IS_EXTERNAL (fixp->fx_addsy)
2822 || S_IS_WEAK (fixp->fx_addsy))
2823 code = BFD_RELOC_SPARC_WPLT30;
2825 case BFD_RELOC_HI22:
2826 if (fixp->fx_addsy != NULL
2827 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2828 code = BFD_RELOC_SPARC_PC22;
2830 code = BFD_RELOC_SPARC_GOT22;
2832 case BFD_RELOC_LO10:
2833 if (fixp->fx_addsy != NULL
2834 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2835 code = BFD_RELOC_SPARC_PC10;
2837 code = BFD_RELOC_SPARC_GOT10;
2839 case BFD_RELOC_SPARC13:
2840 code = BFD_RELOC_SPARC_GOT13;
2846 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2848 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2849 if (reloc->howto == 0)
2851 as_bad_where (fixp->fx_file, fixp->fx_line,
2852 _("internal error: can't export reloc type %d (`%s')"),
2853 fixp->fx_r_type, bfd_get_reloc_code_name (code));
2857 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2860 if (reloc->howto->pc_relative == 0
2861 || code == BFD_RELOC_SPARC_PC10
2862 || code == BFD_RELOC_SPARC_PC22)
2863 reloc->addend = fixp->fx_addnumber;
2864 else if (sparc_pic_code
2865 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
2866 && fixp->fx_addsy != NULL
2867 && (S_IS_EXTERNAL (fixp->fx_addsy)
2868 || S_IS_WEAK (fixp->fx_addsy))
2869 && S_IS_DEFINED (fixp->fx_addsy)
2870 && ! S_IS_COMMON (fixp->fx_addsy))
2871 reloc->addend = fixp->fx_addnumber;
2873 reloc->addend = fixp->fx_offset - reloc->address;
2875 #else /* elf or coff */
2877 if (reloc->howto->pc_relative == 0
2878 || code == BFD_RELOC_SPARC_PC10
2879 || code == BFD_RELOC_SPARC_PC22)
2880 reloc->addend = fixp->fx_addnumber;
2881 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2882 reloc->addend = (section->vma
2883 + fixp->fx_addnumber
2884 + md_pcrel_from (fixp));
2886 reloc->addend = fixp->fx_offset;
2892 /* We have no need to default values of symbols. */
2896 md_undefined_symbol (name)
2900 } /* md_undefined_symbol() */
2902 /* Round up a section size to the appropriate boundary. */
2904 md_section_align (segment, size)
2909 /* This is not right for ELF; a.out wants it, and COFF will force
2910 the alignment anyways. */
2911 valueT align = ((valueT) 1
2912 << (valueT) bfd_get_section_alignment (stdoutput, segment));
2914 /* turn alignment value into a mask */
2916 newsize = (size + align) & ~align;
2923 /* Exactly what point is a PC-relative offset relative TO?
2924 On the sparc, they're relative to the address of the offset, plus
2925 its size. This gets us to the following instruction.
2926 (??? Is this right? FIXME-SOON) */
2928 md_pcrel_from (fixP)
2933 ret = fixP->fx_where + fixP->fx_frag->fr_address;
2934 if (! sparc_pic_code
2935 || fixP->fx_addsy == NULL
2936 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2937 ret += fixP->fx_size;
2941 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
2953 for (shift = 0; (value & 1) == 0; value >>= 1)
2956 return (value == 1) ? shift : -1;
2960 * sort of like s_lcomm
2964 static int max_alignment = 15;
2979 name = input_line_pointer;
2980 c = get_symbol_end ();
2981 p = input_line_pointer;
2985 if (*input_line_pointer != ',')
2987 as_bad (_("Expected comma after name"));
2988 ignore_rest_of_line ();
2992 ++input_line_pointer;
2994 if ((size = get_absolute_expression ()) < 0)
2996 as_bad (_("BSS length (%d.) <0! Ignored."), size);
2997 ignore_rest_of_line ();
3002 symbolP = symbol_find_or_make (name);
3005 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3006 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3008 as_bad (_("bad .reserve segment -- expected BSS segment"));
3012 if (input_line_pointer[2] == '.')
3013 input_line_pointer += 7;
3015 input_line_pointer += 6;
3018 if (*input_line_pointer == ',')
3020 ++input_line_pointer;
3023 if (*input_line_pointer == '\n')
3025 as_bad (_("missing alignment"));
3026 ignore_rest_of_line ();
3030 align = (int) get_absolute_expression ();
3033 if (align > max_alignment)
3035 align = max_alignment;
3036 as_warn (_("alignment too large; assuming %d"), align);
3042 as_bad (_("negative alignment"));
3043 ignore_rest_of_line ();
3049 temp = log2 (align);
3052 as_bad (_("alignment not a power of 2"));
3053 ignore_rest_of_line ();
3060 record_alignment (bss_section, align);
3065 if (!S_IS_DEFINED (symbolP)
3067 && S_GET_OTHER (symbolP) == 0
3068 && S_GET_DESC (symbolP) == 0
3075 segT current_seg = now_seg;
3076 subsegT current_subseg = now_subseg;
3078 subseg_set (bss_section, 1); /* switch to bss */
3081 frag_align (align, 0, 0); /* do alignment */
3083 /* detach from old frag */
3084 if (S_GET_SEGMENT(symbolP) == bss_section)
3085 symbolP->sy_frag->fr_symbol = NULL;
3087 symbolP->sy_frag = frag_now;
3088 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
3089 (offsetT) size, (char *)0);
3092 S_SET_SEGMENT (symbolP, bss_section);
3094 subseg_set (current_seg, current_subseg);
3099 as_warn("Ignoring attempt to re-define symbol %s",
3100 S_GET_NAME (symbolP));
3101 } /* if not redefining */
3103 demand_empty_rest_of_line ();
3116 name = input_line_pointer;
3117 c = get_symbol_end ();
3118 /* just after name is now '\0' */
3119 p = input_line_pointer;
3122 if (*input_line_pointer != ',')
3124 as_bad (_("Expected comma after symbol-name"));
3125 ignore_rest_of_line ();
3128 input_line_pointer++; /* skip ',' */
3129 if ((temp = get_absolute_expression ()) < 0)
3131 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3132 ignore_rest_of_line ();
3137 symbolP = symbol_find_or_make (name);
3139 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3141 as_bad (_("Ignoring attempt to re-define symbol"));
3142 ignore_rest_of_line ();
3145 if (S_GET_VALUE (symbolP) != 0)
3147 if (S_GET_VALUE (symbolP) != (valueT) size)
3149 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3150 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3156 S_SET_VALUE (symbolP, (valueT) size);
3157 S_SET_EXTERNAL (symbolP);
3160 know (symbolP->sy_frag == &zero_address_frag);
3161 if (*input_line_pointer != ',')
3163 as_bad (_("Expected comma after common length"));
3164 ignore_rest_of_line ();
3167 input_line_pointer++;
3169 if (*input_line_pointer != '"')
3171 temp = get_absolute_expression ();
3174 if (temp > max_alignment)
3176 temp = max_alignment;
3177 as_warn (_("alignment too large; assuming %d"), temp);
3183 as_bad (_("negative alignment"));
3184 ignore_rest_of_line ();
3197 old_subsec = now_subseg;
3202 align = log2 (temp);
3206 as_bad (_("alignment not a power of 2"));
3207 ignore_rest_of_line ();
3211 record_alignment (bss_section, align);
3212 subseg_set (bss_section, 0);
3214 frag_align (align, 0, 0);
3215 if (S_GET_SEGMENT (symbolP) == bss_section)
3216 symbolP->sy_frag->fr_symbol = 0;
3217 symbolP->sy_frag = frag_now;
3218 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3219 (offsetT) size, (char *) 0);
3221 S_SET_SEGMENT (symbolP, bss_section);
3222 S_CLEAR_EXTERNAL (symbolP);
3223 subseg_set (old_sec, old_subsec);
3226 #endif /* OBJ_ELF */
3229 S_SET_VALUE (symbolP, (valueT) size);
3231 S_SET_ALIGN (symbolP, temp);
3233 S_SET_EXTERNAL (symbolP);
3234 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3239 input_line_pointer++;
3240 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3241 if (*input_line_pointer == '.')
3242 input_line_pointer++;
3243 /* @@ Some say data, some say bss. */
3244 if (strncmp (input_line_pointer, "bss\"", 4)
3245 && strncmp (input_line_pointer, "data\"", 5))
3247 while (*--input_line_pointer != '"')
3249 input_line_pointer--;
3250 goto bad_common_segment;
3252 while (*input_line_pointer++ != '"')
3254 goto allocate_common;
3257 #ifdef BFD_ASSEMBLER
3258 symbolP->bsym->flags |= BSF_OBJECT;
3261 demand_empty_rest_of_line ();
3266 p = input_line_pointer;
3267 while (*p && *p != '\n')
3271 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3273 input_line_pointer = p;
3274 ignore_rest_of_line ();
3279 /* Handle the .empty pseudo-op. This supresses the warnings about
3280 invalid delay slot usage. */
3286 /* The easy way to implement is to just forget about the last
3296 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3298 input_line_pointer += 6;
3302 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3304 input_line_pointer += 6;
3308 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3310 input_line_pointer += 7;
3314 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3316 input_line_pointer += 5;
3317 /* We only support 2 segments -- text and data -- for now, so
3318 things in the "bss segment" will have to go into data for now.
3319 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3320 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3323 as_bad (_("Unknown segment type"));
3324 demand_empty_rest_of_line ();
3330 subseg_set (data_section, 1);
3331 demand_empty_rest_of_line ();
3338 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3340 ++input_line_pointer;
3342 ++input_line_pointer;
3345 /* This static variable is set by s_uacons to tell sparc_cons_align
3346 that the expession does not need to be aligned. */
3348 static int sparc_no_align_cons = 0;
3350 /* This handles the unaligned space allocation pseudo-ops, such as
3351 .uaword. .uaword is just like .word, but the value does not need
3358 /* Tell sparc_cons_align not to align this value. */
3359 sparc_no_align_cons = 1;
3363 /* If the --enforce-aligned-data option is used, we require .word,
3364 et. al., to be aligned correctly. We do it by setting up an
3365 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3366 no unexpected alignment was introduced.
3368 The SunOS and Solaris native assemblers enforce aligned data by
3369 default. We don't want to do that, because gcc can deliberately
3370 generate misaligned data if the packed attribute is used. Instead,
3371 we permit misaligned data by default, and permit the user to set an
3372 option to check for it. */
3375 sparc_cons_align (nbytes)
3381 /* Only do this if we are enforcing aligned data. */
3382 if (! enforce_aligned_data)
3385 if (sparc_no_align_cons)
3387 /* This is an unaligned pseudo-op. */
3388 sparc_no_align_cons = 0;
3392 nalign = log2 (nbytes);
3396 assert (nalign > 0);
3398 if (now_seg == absolute_section)
3400 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3401 as_bad (_("misaligned data"));
3405 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3406 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3408 record_alignment (now_seg, nalign);
3411 /* This is where we do the unexpected alignment check.
3412 This is called from HANDLE_ALIGN in tc-sparc.h. */
3415 sparc_handle_align (fragp)
3418 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
3419 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
3420 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
3421 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
3423 int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
3428 && !((long)(fragp->fr_literal + fragp->fr_fix) & 3))
3430 unsigned *p = (unsigned *)(fragp->fr_literal + fragp->fr_fix);
3433 for (i = 0; i < count; i += 4, p++)
3434 if (INSN_BIG_ENDIAN)
3435 number_to_chars_bigendian ((char *)p, 0x01000000, 4); /* emit nops */
3437 number_to_chars_littleendian ((char *)p, 0x10000000, 4);
3439 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
3441 char *waddr = &fragp->fr_literal[fragp->fr_fix];
3442 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
3443 if (INSN_BIG_ENDIAN)
3444 number_to_chars_bigendian (waddr, wval, 4);
3446 number_to_chars_littleendian (waddr, wval, 4);
3448 fragp->fr_var = count;
3454 /* Some special processing for a Sparc ELF file. */
3457 sparc_elf_final_processing ()
3459 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3460 sort of BFD interface for this. */
3461 if (sparc_arch_size == 64)
3463 switch (sparc_memory_model)
3466 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
3469 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
3475 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
3476 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
3477 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
3478 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
3482 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3483 reloc for a cons. We could use the definition there, except that
3484 we want to handle little endian relocs specially. */
3487 cons_fix_new_sparc (frag, where, nbytes, exp)
3490 unsigned int nbytes;
3493 bfd_reloc_code_real_type r;
3495 r = (nbytes == 1 ? BFD_RELOC_8 :
3496 (nbytes == 2 ? BFD_RELOC_16 :
3497 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
3500 if (target_little_endian_data && nbytes == 4)
3501 r = BFD_RELOC_SPARC_32LE;
3503 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);