1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
30 #include "elf/sparc.h"
33 static struct sparc_arch *lookup_arch PARAMS ((char *));
34 static void init_default_arch PARAMS ((void));
35 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
36 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
37 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
38 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39 static int sparc_ffs PARAMS ((unsigned int));
40 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
41 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
42 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
43 static bfd_vma BSR PARAMS ((bfd_vma, int));
44 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
45 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
46 static int parse_const_expr_arg PARAMS ((char **, int *));
47 static int get_expression PARAMS ((char *str));
49 /* Default architecture. */
50 /* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
54 #define DEFAULT_ARCH "sparclite"
56 static char *default_arch = DEFAULT_ARCH;
58 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
60 static int default_init_p;
62 /* Current architecture. We don't bump up unless necessary. */
63 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
65 /* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70 static enum sparc_opcode_arch_val max_architecture;
72 /* Either 32 or 64, selects file format. */
73 static int sparc_arch_size;
74 /* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76 static int default_arch_size;
79 /* The currently selected v9 memory model. Currently only used for
81 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
84 static int architecture_requested;
85 static int warn_on_bump;
87 /* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89 static enum sparc_opcode_arch_val warn_after_architecture;
91 /* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93 static int no_undeclared_regs;
95 /* Non-zero if we should try to relax jumps and calls. */
96 static int sparc_relax;
98 /* Non-zero if we are generating PIC code. */
101 /* Non-zero if we should give an error when misaligned data is seen. */
102 static int enforce_aligned_data;
104 extern int target_big_endian;
106 static int target_little_endian_data;
108 /* Symbols for global registers on v9. */
109 static symbolS *globals[8];
111 /* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115 #ifndef INSN_BIG_ENDIAN
116 #define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
121 /* Handle of the OPCODE hash table. */
122 static struct hash_control *op_hash;
124 static int log2 PARAMS ((int));
125 static void s_data1 PARAMS ((void));
126 static void s_seg PARAMS ((int));
127 static void s_proc PARAMS ((int));
128 static void s_reserve PARAMS ((int));
129 static void s_common PARAMS ((int));
130 static void s_empty PARAMS ((int));
131 static void s_uacons PARAMS ((int));
132 static void s_ncons PARAMS ((int));
133 static void s_register PARAMS ((int));
135 const pseudo_typeS md_pseudo_table[] =
137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
142 {"nword", s_ncons, 0},
143 {"optim", s_ignore, 0},
145 {"reserve", s_reserve, 0},
147 {"skip", s_space, 0},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
158 {"register", s_register, 0},
163 /* Size of relocation record. */
164 const int md_reloc_size = 12;
166 /* This array holds the chars that always start a comment. If the
167 pre-processor is disabled, these aren't very useful. */
168 const char comment_chars[] = "!"; /* JF removed '|' from
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output. */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that comments started like this one will always
178 work if '/' isn't otherwise defined. */
179 const char line_comment_chars[] = "#";
181 const char line_separator_chars[] = ";";
183 /* Chars that can be used to separate mant from exp in floating point
185 const char EXP_CHARS[] = "eE";
187 /* Chars that mean this number is a floating point constant.
190 const char FLT_CHARS[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
196 #define isoctal(c) ((unsigned)((c) - '0') < '8')
201 unsigned long opcode;
202 struct nlist *nlistp;
206 bfd_reloc_code_real_type reloc;
209 struct sparc_it the_insn, set_insn;
211 static void output_insn
212 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
220 v8plusa, v9, v9a, v9_64};
222 static struct sparc_arch {
225 enum sparc_arch_types arch_type;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size;
229 /* Allowable arg to -A? */
231 } sparc_arch_table[] = {
232 { "v6", "v6", v6, 0, 1 },
233 { "v7", "v7", v7, 0, 1 },
234 { "v8", "v8", v8, 32, 1 },
235 { "sparclet", "sparclet", sparclet, 32, 1 },
236 { "sparclite", "sparclite", sparclite, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x, 32, 1 },
238 { "v8plus", "v9", v9, 0, 1 },
239 { "v8plusa", "v9a", v9, 0, 1 },
240 { "v9", "v9", v9, 0, 1 },
241 { "v9a", "v9a", v9, 0, 1 },
242 /* This exists to allow configure.in/Makefile.in to pass one
243 value to specify both the default machine and default word size. */
244 { "v9-64", "v9", v9, 64, 0 },
245 { NULL, NULL, v8, 0, 0 }
248 /* Variant of default_arch */
249 static enum sparc_arch_types default_arch_type;
251 static struct sparc_arch *
255 struct sparc_arch *sa;
257 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
258 if (strcmp (sa->name, name) == 0)
260 if (sa->name == NULL)
265 /* Initialize the default opcode arch and word size from the default
266 architecture name. */
271 struct sparc_arch *sa = lookup_arch (default_arch);
274 || sa->default_arch_size == 0)
275 as_fatal (_("Invalid default architecture, broken assembler."));
277 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
278 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
279 as_fatal (_("Bad opcode table, broken assembler."));
280 default_arch_size = sparc_arch_size = sa->default_arch_size;
282 default_arch_type = sa->arch_type;
285 /* Called by TARGET_FORMAT. */
288 sparc_target_format ()
290 /* We don't get a chance to initialize anything before we're called,
291 so handle that now. */
292 if (! default_init_p)
293 init_default_arch ();
297 return "a.out-sparc-netbsd";
300 if (target_big_endian)
301 return "a.out-sunos-big";
302 else if (default_arch_type == sparc86x && target_little_endian_data)
303 return "a.out-sunos-big";
305 return "a.out-sparc-little";
307 return "a.out-sunos-big";
318 return "coff-sparc-lynx";
325 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
332 * Invocation line includes a switch not recognized by the base assembler.
333 * See if it's a processor-specific option. These are:
336 * Warn on architecture bumps. See also -A.
338 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
339 * Standard 32 bit architectures.
340 * -Av8plus, -Av8plusa
341 * Sparc64 in a 32 bit world.
343 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
344 * This used to only mean 64 bits, but properly specifying it
345 * complicated gcc's ASM_SPECs, so now opcode selection is
346 * specified orthogonally to word size (except when specifying
347 * the default, but that is an internal implementation detail).
348 * -xarch=v8plus, -xarch=v8plusa
349 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
351 * Select the architecture and possibly the file format.
352 * Instructions or features not supported by the selected
353 * architecture cause fatal errors.
355 * The default is to start at v6, and bump the architecture up
356 * whenever an instruction is seen at a higher level. In 32 bit
357 * environments, v9 is not bumped up to, the user must pass
360 * If -bump is specified, a warning is printing when bumping to
363 * If an architecture is specified, all instructions must match
364 * that architecture. Any higher level instructions are flagged
365 * as errors. Note that in the 32 bit environment specifying
366 * -Av8plus does not automatically create a v8plus object file, a
367 * v9 insn must be seen.
369 * If both an architecture and -bump are specified, the
370 * architecture starts at the specified level, but bumps are
371 * warnings. Note that we can't set `current_architecture' to
372 * the requested level in this case: in the 32 bit environment,
373 * we still must avoid creating v8plus object files unless v9
377 * Bumping between incompatible architectures is always an
378 * error. For example, from sparclite to v9.
382 CONST char *md_shortopts = "A:K:VQ:sq";
385 CONST char *md_shortopts = "A:k";
387 CONST char *md_shortopts = "A:";
390 struct option md_longopts[] = {
391 #define OPTION_BUMP (OPTION_MD_BASE)
392 {"bump", no_argument, NULL, OPTION_BUMP},
393 #define OPTION_SPARC (OPTION_MD_BASE + 1)
394 {"sparc", no_argument, NULL, OPTION_SPARC},
395 #define OPTION_XARCH (OPTION_MD_BASE + 2)
396 {"xarch", required_argument, NULL, OPTION_XARCH},
398 #define OPTION_32 (OPTION_MD_BASE + 3)
399 {"32", no_argument, NULL, OPTION_32},
400 #define OPTION_64 (OPTION_MD_BASE + 4)
401 {"64", no_argument, NULL, OPTION_64},
402 #define OPTION_TSO (OPTION_MD_BASE + 5)
403 {"TSO", no_argument, NULL, OPTION_TSO},
404 #define OPTION_PSO (OPTION_MD_BASE + 6)
405 {"PSO", no_argument, NULL, OPTION_PSO},
406 #define OPTION_RMO (OPTION_MD_BASE + 7)
407 {"RMO", no_argument, NULL, OPTION_RMO},
409 #ifdef SPARC_BIENDIAN
410 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
411 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
412 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
413 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
415 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
416 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
417 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
418 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
420 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
421 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
422 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
423 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
425 #define OPTION_RELAX (OPTION_MD_BASE + 14)
426 {"relax", no_argument, NULL, OPTION_RELAX},
427 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
428 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
429 {NULL, no_argument, NULL, 0}
432 size_t md_longopts_size = sizeof (md_longopts);
435 md_parse_option (c, arg)
439 /* We don't get a chance to initialize anything before we're called,
440 so handle that now. */
441 if (! default_init_p)
442 init_default_arch ();
448 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
452 /* This is for compatibility with Sun's assembler. */
453 if (strcmp (arg, "v8plus") != 0
454 && strcmp (arg, "v8plusa") != 0)
456 as_bad (_("invalid architecture -xarch=%s"), arg);
463 struct sparc_arch *sa;
464 enum sparc_opcode_arch_val opcode_arch;
466 sa = lookup_arch (arg);
468 || ! sa->user_option_p)
470 as_bad (_("invalid architecture -A%s"), arg);
474 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
475 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
476 as_fatal (_("Bad opcode table, broken assembler."));
478 max_architecture = opcode_arch;
479 architecture_requested = 1;
484 /* Ignore -sparc, used by SunOS make default .s.o rule. */
487 case OPTION_ENFORCE_ALIGNED_DATA:
488 enforce_aligned_data = 1;
491 #ifdef SPARC_BIENDIAN
492 case OPTION_LITTLE_ENDIAN:
493 target_big_endian = 0;
494 if (default_arch_type != sparclet)
495 as_fatal ("This target does not support -EL");
497 case OPTION_LITTLE_ENDIAN_DATA:
498 target_little_endian_data = 1;
499 target_big_endian = 0;
500 if (default_arch_type != sparc86x
501 && default_arch_type != v9)
502 as_fatal ("This target does not support --little-endian-data");
504 case OPTION_BIG_ENDIAN:
505 target_big_endian = 1;
519 const char **list, **l;
521 sparc_arch_size = c == OPTION_32 ? 32 : 64;
522 list = bfd_target_list ();
523 for (l = list; *l != NULL; l++)
525 if (sparc_arch_size == 32)
527 if (strcmp (*l, "elf32-sparc") == 0)
532 if (strcmp (*l, "elf64-sparc") == 0)
537 as_fatal (_("No compiled in support for %d bit object file format"),
544 sparc_memory_model = MM_TSO;
548 sparc_memory_model = MM_PSO;
552 sparc_memory_model = MM_RMO;
560 /* Qy - do emit .comment
561 Qn - do not emit .comment. */
565 /* Use .stab instead of .stab.excl. */
569 /* quick -- Native assembler does fewer checks. */
573 if (strcmp (arg, "PIC") != 0)
574 as_warn (_("Unrecognized option following -K"));
579 case OPTION_NO_UNDECLARED_REGS:
580 no_undeclared_regs = 1;
583 case OPTION_UNDECLARED_REGS:
584 no_undeclared_regs = 0;
592 case OPTION_NO_RELAX:
604 md_show_usage (stream)
607 const struct sparc_arch *arch;
609 /* We don't get a chance to initialize anything before we're called,
610 so handle that now. */
611 if (! default_init_p)
612 init_default_arch ();
614 fprintf (stream, _("SPARC options:\n"));
615 for (arch = &sparc_arch_table[0]; arch->name; arch++)
617 if (arch != &sparc_arch_table[0])
618 fprintf (stream, " | ");
619 if (arch->user_option_p)
620 fprintf (stream, "-A%s", arch->name);
622 fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
623 fprintf (stream, _("\
624 specify variant of SPARC architecture\n\
625 -bump warn when assembler switches architectures\n\
627 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
628 -relax relax jumps and branches (default)\n\
629 -no-relax avoid changing any jumps and branches\n"));
631 fprintf (stream, _("\
632 -k generate PIC\n"));
635 fprintf (stream, _("\
636 -32 create 32 bit object file\n\
637 -64 create 64 bit object file\n"));
638 fprintf (stream, _("\
639 [default is %d]\n"), default_arch_size);
640 fprintf (stream, _("\
641 -TSO use Total Store Ordering\n\
642 -PSO use Partial Store Ordering\n\
643 -RMO use Relaxed Memory Ordering\n"));
644 fprintf (stream, _("\
645 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
646 fprintf (stream, _("\
647 -KPIC generate PIC\n\
648 -V print assembler version number\n\
649 -undeclared-regs ignore application global register usage without\n\
650 appropriate .register directive (default)\n\
651 -no-undeclared-regs force error on application global register usage\n\
652 without appropriate .register directive\n\
657 #ifdef SPARC_BIENDIAN
658 fprintf (stream, _("\
659 -EL generate code for a little endian machine\n\
660 -EB generate code for a big endian machine\n\
661 --little-endian-data generate code for a machine having big endian\n\
662 instructions and little endian data.\n"));
666 /* Native operand size opcode translation. */
672 } native_op_table[] =
674 {"ldn", "ld", "ldx"},
675 {"ldna", "lda", "ldxa"},
676 {"stn", "st", "stx"},
677 {"stna", "sta", "stxa"},
678 {"slln", "sll", "sllx"},
679 {"srln", "srl", "srlx"},
680 {"sran", "sra", "srax"},
681 {"casn", "cas", "casx"},
682 {"casna", "casa", "casxa"},
683 {"clrn", "clr", "clrx"},
687 /* sparc64 priviledged registers. */
689 struct priv_reg_entry
695 struct priv_reg_entry priv_reg_table[] =
714 {"", -1}, /* End marker. */
717 /* v9a specific asrs. */
719 struct priv_reg_entry v9a_asr_table[] =
728 {"clear_softint", 21},
729 {"", -1}, /* End marker. */
733 cmp_reg_entry (parg, qarg)
737 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
738 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
740 return strcmp (q->name, p->name);
743 /* This function is called once, at assembler startup time. It should
744 set up all the tables, etc. that the MD part of the assembler will
750 register const char *retval = NULL;
752 register unsigned int i = 0;
754 /* We don't get a chance to initialize anything before md_parse_option
755 is called, and it may not be called, so handle default initialization
756 now if not already done. */
757 if (! default_init_p)
758 init_default_arch ();
760 op_hash = hash_new ();
762 while (i < (unsigned int) sparc_num_opcodes)
764 const char *name = sparc_opcodes[i].name;
765 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
768 as_bad (_("Internal error: can't hash `%s': %s\n"),
769 sparc_opcodes[i].name, retval);
774 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
776 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
777 sparc_opcodes[i].name, sparc_opcodes[i].args);
782 while (i < (unsigned int) sparc_num_opcodes
783 && !strcmp (sparc_opcodes[i].name, name));
786 for (i = 0; native_op_table[i].name; i++)
788 const struct sparc_opcode *insn;
789 char *name = ((sparc_arch_size == 32)
790 ? native_op_table[i].name32
791 : native_op_table[i].name64);
792 insn = (struct sparc_opcode *) hash_find (op_hash, name);
795 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
796 name, native_op_table[i].name);
801 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
804 as_bad (_("Internal error: can't hash `%s': %s\n"),
805 sparc_opcodes[i].name, retval);
812 as_fatal (_("Broken assembler. No assembly attempted."));
814 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
815 sizeof (priv_reg_table[0]), cmp_reg_entry);
817 /* If -bump, record the architecture level at which we start issuing
818 warnings. The behaviour is different depending upon whether an
819 architecture was explicitly specified. If it wasn't, we issue warnings
820 for all upwards bumps. If it was, we don't start issuing warnings until
821 we need to bump beyond the requested architecture or when we bump between
822 conflicting architectures. */
825 && architecture_requested)
827 /* `max_architecture' records the requested architecture.
828 Issue warnings if we go above it. */
829 warn_after_architecture = max_architecture;
831 /* Find the highest architecture level that doesn't conflict with
832 the requested one. */
833 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
834 max_architecture > warn_after_architecture;
836 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
837 warn_after_architecture))
842 /* Called after all assembly has been done. */
847 if (sparc_arch_size == 64)
849 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
850 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
852 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
856 if (current_architecture == SPARC_OPCODE_ARCH_V9)
857 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
858 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
859 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
860 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
861 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
862 else if (default_arch_type == sparc86x && target_little_endian_data)
863 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
866 /* The sparclite is treated like a normal sparc. Perhaps it
867 shouldn't be but for now it is (since that's the way it's
868 always been treated). */
869 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
874 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
877 in_signed_range (val, max)
878 bfd_signed_vma val, max;
882 /* Sign-extend the value from the architecture word size, so that
883 0xffffffff is always considered -1 on sparc32. */
884 if (sparc_arch_size == 32)
886 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
887 val = ((val & 0xffffffff) ^ sign) - sign;
896 /* Return non-zero if VAL is in the range 0 to MAX. */
899 in_unsigned_range (val, max)
907 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
908 (e.g. -15 to +31). */
911 in_bitfield_range (val, max)
912 bfd_signed_vma val, max;
918 if (val < ~(max >> 1))
932 for (i = 0; (mask & 1) == 0; ++i)
937 /* Implement big shift right. */
943 if (sizeof (bfd_vma) <= 4 && amount >= 32)
944 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
945 return val >> amount;
948 /* For communication between sparc_ip and get_expression. */
949 static char *expr_end;
951 /* Values for `special_case'.
952 Instructions that require wierd handling because they're longer than
954 #define SPECIAL_CASE_NONE 0
955 #define SPECIAL_CASE_SET 1
956 #define SPECIAL_CASE_SETSW 2
957 #define SPECIAL_CASE_SETX 3
958 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
959 #define SPECIAL_CASE_FDIV 4
961 /* Bit masks of various insns. */
962 #define NOP_INSN 0x01000000
963 #define OR_INSN 0x80100000
964 #define XOR_INSN 0x80180000
965 #define FMOVS_INSN 0x81A00020
966 #define SETHI_INSN 0x01000000
967 #define SLLX_INSN 0x81281000
968 #define SRA_INSN 0x81380000
970 /* The last instruction to be assembled. */
971 static const struct sparc_opcode *last_insn;
972 /* The assembled opcode of `last_insn'. */
973 static unsigned long last_opcode;
975 /* Handle the set and setuw synthetic instructions. */
978 synthetize_setuw (insn)
979 const struct sparc_opcode *insn;
982 int rd = (the_insn.opcode & RD (~0)) >> 25;
984 if (the_insn.exp.X_op == O_constant)
986 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
988 if (sizeof (offsetT) > 4
989 && (the_insn.exp.X_add_number < 0
990 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
991 as_warn (_("set: number not in 0..4294967295 range"));
995 if (sizeof (offsetT) > 4
996 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
997 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
998 as_warn (_("set: number not in -2147483648..4294967295 range"));
999 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1003 /* See if operand is absolute and small; skip sethi if so. */
1004 if (the_insn.exp.X_op != O_constant
1005 || the_insn.exp.X_add_number >= (1 << 12)
1006 || the_insn.exp.X_add_number < -(1 << 12))
1008 the_insn.opcode = (SETHI_INSN | RD (rd)
1009 | ((the_insn.exp.X_add_number >> 10)
1010 & (the_insn.exp.X_op == O_constant
1012 the_insn.reloc = (the_insn.exp.X_op != O_constant
1013 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1014 output_insn (insn, &the_insn);
1018 /* See if operand has no low-order bits; skip OR if so. */
1019 if (the_insn.exp.X_op != O_constant
1020 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1023 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1025 | (the_insn.exp.X_add_number
1026 & (the_insn.exp.X_op != O_constant
1027 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1028 the_insn.reloc = (the_insn.exp.X_op != O_constant
1029 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1030 output_insn (insn, &the_insn);
1034 /* Handle the setsw synthetic instruction. */
1037 synthetize_setsw (insn)
1038 const struct sparc_opcode *insn;
1042 rd = (the_insn.opcode & RD (~0)) >> 25;
1044 if (the_insn.exp.X_op != O_constant)
1046 synthetize_setuw (insn);
1048 /* Need to sign extend it. */
1049 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1050 the_insn.reloc = BFD_RELOC_NONE;
1051 output_insn (insn, &the_insn);
1055 if (sizeof (offsetT) > 4
1056 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1057 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1058 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1060 low32 = the_insn.exp.X_add_number;
1064 synthetize_setuw (insn);
1070 the_insn.reloc = BFD_RELOC_NONE;
1071 /* See if operand is absolute and small; skip sethi if so. */
1072 if (low32 < -(1 << 12))
1074 the_insn.opcode = (SETHI_INSN | RD (rd)
1075 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1076 output_insn (insn, &the_insn);
1077 low32 = 0x1c00 | (low32 & 0x3ff);
1078 opc = RS1 (rd) | XOR_INSN;
1081 the_insn.opcode = (opc | RD (rd) | IMMED
1082 | (low32 & 0x1fff));
1083 output_insn (insn, &the_insn);
1086 /* Handle the setsw synthetic instruction. */
1089 synthetize_setx (insn)
1090 const struct sparc_opcode *insn;
1092 int upper32, lower32;
1093 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1094 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1096 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1097 int need_xor10_p = 0;
1099 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1100 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1101 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1104 upper_dstreg = tmpreg;
1105 /* The tmp reg should not be the dst reg. */
1106 if (tmpreg == dstreg)
1107 as_warn (_("setx: temporary register same as destination register"));
1109 /* ??? Obviously there are other optimizations we can do
1110 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1111 doing some of these. Later. If you do change things, try to
1112 change all of this to be table driven as well. */
1113 /* What to output depends on the number if it's constant.
1114 Compute that first, then output what we've decided upon. */
1115 if (the_insn.exp.X_op != O_constant)
1117 if (sparc_arch_size == 32)
1119 /* When arch size is 32, we want setx to be equivalent
1120 to setuw for anything but constants. */
1121 the_insn.exp.X_add_number &= 0xffffffff;
1122 synthetize_setuw (insn);
1125 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1131 /* Reset X_add_number, we've extracted it as upper32/lower32.
1132 Otherwise fixup_segment will complain about not being able to
1133 write an 8 byte number in a 4 byte field. */
1134 the_insn.exp.X_add_number = 0;
1136 /* Only need hh22 if `or' insn can't handle constant. */
1137 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1140 /* Does bottom part (after sethi) have bits? */
1141 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1142 /* No hh22, but does upper32 still have bits we can't set
1144 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1147 /* If the lower half is all zero, we build the upper half directly
1148 into the dst reg. */
1150 /* Need lower half if number is zero or 0xffffffff00000000. */
1151 || (! need_hh22_p && ! need_hm10_p))
1153 /* No need for sethi if `or' insn can handle constant. */
1154 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1155 /* Note that we can't use a negative constant in the `or'
1156 insn unless the upper 32 bits are all ones. */
1157 || (lower32 < 0 && upper32 != -1)
1158 || (lower32 >= 0 && upper32 == -1))
1161 if (need_hi22_p && upper32 == -1)
1164 /* Does bottom part (after sethi) have bits? */
1165 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1167 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1168 /* Need `or' if we didn't set anything else. */
1169 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1173 /* Output directly to dst reg if lower 32 bits are all zero. */
1174 upper_dstreg = dstreg;
1177 if (!upper_dstreg && dstreg)
1178 as_warn (_("setx: illegal temporary register g0"));
1182 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1183 | ((upper32 >> 10) & 0x3fffff));
1184 the_insn.reloc = (the_insn.exp.X_op != O_constant
1185 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1186 output_insn (insn, &the_insn);
1191 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1192 | (((need_xor10_p ? ~lower32 : lower32)
1193 >> 10) & 0x3fffff));
1194 the_insn.reloc = (the_insn.exp.X_op != O_constant
1195 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1196 output_insn (insn, &the_insn);
1201 the_insn.opcode = (OR_INSN
1202 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1205 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1206 the_insn.reloc = (the_insn.exp.X_op != O_constant
1207 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1208 output_insn (insn, &the_insn);
1213 /* FIXME: One nice optimization to do here is to OR the low part
1214 with the highpart if hi22 isn't needed and the low part is
1216 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1219 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1220 the_insn.reloc = (the_insn.exp.X_op != O_constant
1221 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1222 output_insn (insn, &the_insn);
1225 /* If we needed to build the upper part, shift it into place. */
1226 if (need_hh22_p || need_hm10_p)
1228 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1230 the_insn.reloc = BFD_RELOC_NONE;
1231 output_insn (insn, &the_insn);
1234 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1237 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1238 | 0x1c00 | (lower32 & 0x3ff));
1239 the_insn.reloc = BFD_RELOC_NONE;
1240 output_insn (insn, &the_insn);
1243 /* If we needed to build both upper and lower parts, OR them together. */
1244 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1246 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1248 the_insn.reloc = BFD_RELOC_NONE;
1249 output_insn (insn, &the_insn);
1253 /* Main entry point to assemble one instruction. */
1259 const struct sparc_opcode *insn;
1263 special_case = sparc_ip (str, &insn);
1265 /* We warn about attempts to put a floating point branch in a delay slot,
1266 unless the delay slot has been annulled. */
1268 && last_insn != NULL
1269 && (insn->flags & F_FBR) != 0
1270 && (last_insn->flags & F_DELAYED) != 0
1271 /* ??? This test isn't completely accurate. We assume anything with
1272 F_{UNBR,CONDBR,FBR} set is annullable. */
1273 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1274 || (last_opcode & ANNUL) == 0))
1275 as_warn (_("FP branch in delay slot"));
1277 /* SPARC before v9 requires a nop instruction between a floating
1278 point instruction and a floating point branch. We insert one
1279 automatically, with a warning. */
1280 if (max_architecture < SPARC_OPCODE_ARCH_V9
1282 && last_insn != NULL
1283 && (insn->flags & F_FBR) != 0
1284 && (last_insn->flags & F_FLOAT) != 0)
1286 struct sparc_it nop_insn;
1288 nop_insn.opcode = NOP_INSN;
1289 nop_insn.reloc = BFD_RELOC_NONE;
1290 output_insn (insn, &nop_insn);
1291 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1294 switch (special_case)
1296 case SPECIAL_CASE_NONE:
1298 output_insn (insn, &the_insn);
1301 case SPECIAL_CASE_SETSW:
1302 synthetize_setsw (insn);
1305 case SPECIAL_CASE_SET:
1306 synthetize_setuw (insn);
1309 case SPECIAL_CASE_SETX:
1310 synthetize_setx (insn);
1313 case SPECIAL_CASE_FDIV:
1315 int rd = (the_insn.opcode >> 25) & 0x1f;
1317 output_insn (insn, &the_insn);
1319 /* According to information leaked from Sun, the "fdiv" instructions
1320 on early SPARC machines would produce incorrect results sometimes.
1321 The workaround is to add an fmovs of the destination register to
1322 itself just after the instruction. This was true on machines
1323 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1324 assert (the_insn.reloc == BFD_RELOC_NONE);
1325 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1326 output_insn (insn, &the_insn);
1331 as_fatal (_("failed special case insn sanity check"));
1335 /* Subroutine of md_assemble to do the actual parsing. */
1338 sparc_ip (str, pinsn)
1340 const struct sparc_opcode **pinsn;
1342 char *error_message = "";
1346 const struct sparc_opcode *insn;
1348 unsigned long opcode;
1349 unsigned int mask = 0;
1353 int special_case = SPECIAL_CASE_NONE;
1356 if (islower ((unsigned char) *s))
1360 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1377 as_fatal (_("Unknown opcode: `%s'"), str);
1379 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1383 as_bad (_("Unknown opcode: `%s'"), str);
1384 return special_case;
1394 opcode = insn->match;
1395 memset (&the_insn, '\0', sizeof (the_insn));
1396 the_insn.reloc = BFD_RELOC_NONE;
1399 /* Build the opcode, checking as we go to make sure that the
1401 for (args = insn->args;; ++args)
1409 /* Parse a series of masks. */
1416 if (! parse_keyword_arg (sparc_encode_membar, &s,
1419 error_message = _(": invalid membar mask name");
1425 if (*s == '|' || *s == '+')
1433 if (! parse_const_expr_arg (&s, &kmask))
1435 error_message = _(": invalid membar mask expression");
1438 if (kmask < 0 || kmask > 127)
1440 error_message = _(": invalid membar mask number");
1445 opcode |= MEMBAR (kmask);
1453 /* Parse a prefetch function. */
1456 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1458 error_message = _(": invalid prefetch function name");
1464 if (! parse_const_expr_arg (&s, &fcn))
1466 error_message = _(": invalid prefetch function expression");
1469 if (fcn < 0 || fcn > 31)
1471 error_message = _(": invalid prefetch function number");
1481 /* Parse a sparc64 privileged register. */
1484 struct priv_reg_entry *p = priv_reg_table;
1485 unsigned int len = 9999999; /* Init to make gcc happy. */
1488 while (p->name[0] > s[0])
1490 while (p->name[0] == s[0])
1492 len = strlen (p->name);
1493 if (strncmp (p->name, s, len) == 0)
1497 if (p->name[0] != s[0])
1499 error_message = _(": unrecognizable privileged register");
1503 opcode |= (p->regnum << 14);
1505 opcode |= (p->regnum << 25);
1511 error_message = _(": unrecognizable privileged register");
1517 /* Parse a v9a ancillary state register. */
1520 struct priv_reg_entry *p = v9a_asr_table;
1521 unsigned int len = 9999999; /* Init to make gcc happy. */
1524 while (p->name[0] > s[0])
1526 while (p->name[0] == s[0])
1528 len = strlen (p->name);
1529 if (strncmp (p->name, s, len) == 0)
1533 if (p->name[0] != s[0])
1535 error_message = _(": unrecognizable v9a ancillary state register");
1538 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1540 error_message = _(": rd on write only ancillary state register");
1544 opcode |= (p->regnum << 14);
1546 opcode |= (p->regnum << 25);
1552 error_message = _(": unrecognizable v9a ancillary state register");
1558 if (strncmp (s, "%asr", 4) == 0)
1562 if (isdigit ((unsigned char) *s))
1566 while (isdigit ((unsigned char) *s))
1568 num = num * 10 + *s - '0';
1572 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1574 if (num < 16 || 31 < num)
1576 error_message = _(": asr number must be between 16 and 31");
1582 if (num < 0 || 31 < num)
1584 error_message = _(": asr number must be between 0 and 31");
1589 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1594 error_message = _(": expecting %asrN");
1601 the_insn.reloc = BFD_RELOC_SPARC_11;
1605 the_insn.reloc = BFD_RELOC_SPARC_10;
1609 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1610 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1611 the_insn.reloc = BFD_RELOC_SPARC_5;
1613 the_insn.reloc = BFD_RELOC_SPARC13;
1614 /* These fields are unsigned, but for upward compatibility,
1615 allow negative values as well. */
1619 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1620 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1621 the_insn.reloc = BFD_RELOC_SPARC_6;
1623 the_insn.reloc = BFD_RELOC_SPARC13;
1624 /* These fields are unsigned, but for upward compatibility,
1625 allow negative values as well. */
1629 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1634 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1639 if (*s == 'p' && s[1] == 'n')
1647 if (*s == 'p' && s[1] == 't')
1659 if (strncmp (s, "%icc", 4) == 0)
1671 if (strncmp (s, "%xcc", 4) == 0)
1683 if (strncmp (s, "%fcc0", 5) == 0)
1695 if (strncmp (s, "%fcc1", 5) == 0)
1707 if (strncmp (s, "%fcc2", 5) == 0)
1719 if (strncmp (s, "%fcc3", 5) == 0)
1727 if (strncmp (s, "%pc", 3) == 0)
1735 if (strncmp (s, "%tick", 5) == 0)
1742 case '\0': /* End of args. */
1761 case '[': /* These must match exactly. */
1769 case '#': /* Must be at least one digit. */
1770 if (isdigit ((unsigned char) *s++))
1772 while (isdigit ((unsigned char) *s))
1780 case 'C': /* Coprocessor state register. */
1781 if (strncmp (s, "%csr", 4) == 0)
1788 case 'b': /* Next operand is a coprocessor register. */
1791 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1794 if (isdigit ((unsigned char) *s))
1796 mask = 10 * (mask - '0') + (*s++ - '0');
1810 opcode |= mask << 14;
1818 opcode |= mask << 25;
1824 case 'r': /* next operand must be a register */
1834 case 'f': /* frame pointer */
1842 case 'g': /* global register */
1851 case 'i': /* in register */
1855 mask = c - '0' + 24;
1860 case 'l': /* local register */
1864 mask = (c - '0' + 16);
1869 case 'o': /* out register */
1873 mask = (c - '0' + 8);
1878 case 's': /* stack pointer */
1886 case 'r': /* any register */
1887 if (!isdigit ((unsigned char) (c = *s++)))
1902 if (isdigit ((unsigned char) *s))
1904 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1920 if ((mask & ~1) == 2 && sparc_arch_size == 64
1921 && no_undeclared_regs && ! globals[mask])
1922 as_bad (_("detected global register use not covered by .register pseudo-op"));
1924 /* Got the register, now figure out where
1925 it goes in the opcode. */
1929 opcode |= mask << 14;
1937 opcode |= mask << 25;
1941 opcode |= (mask << 25) | (mask << 14);
1945 opcode |= (mask << 25) | (mask << 0);
1951 case 'e': /* next operand is a floating point register */
1966 && ((format = *s) == 'f')
1967 && isdigit ((unsigned char) *++s))
1969 for (mask = 0; isdigit ((unsigned char) *s); ++s)
1971 mask = 10 * mask + (*s - '0');
1972 } /* read the number */
1980 } /* register must be even numbered */
1988 } /* register must be multiple of 4 */
1992 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1993 error_message = _(": There are only 64 f registers; [0-63]");
1995 error_message = _(": There are only 32 f registers; [0-31]");
1998 else if (mask >= 32)
2000 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2003 mask -= 31; /* wrap high bit */
2007 error_message = _(": There are only 32 f registers; [0-31]");
2015 } /* if not an 'f' register. */
2022 opcode |= RS1 (mask);
2028 opcode |= RS2 (mask);
2034 opcode |= RD (mask);
2043 if (strncmp (s, "%fsr", 4) == 0)
2050 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2051 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2054 case 'l': /* 22 bit PC relative immediate */
2055 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2059 case 'L': /* 30 bit immediate */
2060 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2065 case 'n': /* 22 bit immediate */
2066 the_insn.reloc = BFD_RELOC_SPARC22;
2069 case 'i': /* 13 bit immediate */
2070 the_insn.reloc = BFD_RELOC_SPARC13;
2080 char *op_arg = NULL;
2082 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2084 /* Check for %hi, etc. */
2087 static const struct ops {
2088 /* The name as it appears in assembler. */
2090 /* strlen (name), precomputed for speed */
2092 /* The reloc this pseudo-op translates to. */
2094 /* Non-zero if for v9 only. */
2096 /* Non-zero if can be used in pc-relative contexts. */
2097 int pcrel_p;/*FIXME:wip*/
2099 /* hix/lox must appear before hi/lo so %hix won't be
2100 mistaken for %hi. */
2101 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2102 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2103 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2104 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2105 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2106 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2107 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2108 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2109 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2110 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2111 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2112 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2115 const struct ops *o;
2117 for (o = ops; o->name; o++)
2118 if (strncmp (s + 1, o->name, o->len) == 0)
2120 if (o->name == NULL)
2123 if (s[o->len + 1] != '(')
2125 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2126 return special_case;
2130 the_insn.reloc = o->reloc;
2135 /* Note that if the get_expression() fails, we will still
2136 have created U entries in the symbol table for the
2137 'symbols' in the input string. Try not to create U
2138 symbols for registers, etc. */
2140 /* This stuff checks to see if the expression ends in
2141 +%reg. If it does, it removes the register from
2142 the expression, and re-sets 's' to point to the
2149 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2152 else if (*s1 == ')')
2161 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2162 return special_case;
2166 (void) get_expression (s);
2169 if (*s == ',' || *s == ']' || !*s)
2171 if (*s != '+' && *s != '-')
2173 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2174 return special_case;
2178 op_exp = the_insn.exp;
2179 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2182 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2185 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2187 if (s1[-2] == '%' && s1[-3] == '+')
2189 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2196 if (op_arg && s1 == s + 1)
2197 the_insn.exp.X_op = O_absent;
2199 (void) get_expression (s);
2211 (void) get_expression (s);
2219 the_insn.exp2 = the_insn.exp;
2220 the_insn.exp = op_exp;
2221 if (the_insn.exp2.X_op == O_absent)
2222 the_insn.exp2.X_op = O_illegal;
2223 else if (the_insn.exp.X_op == O_absent)
2225 the_insn.exp = the_insn.exp2;
2226 the_insn.exp2.X_op = O_illegal;
2228 else if (the_insn.exp.X_op == O_constant)
2230 valueT val = the_insn.exp.X_add_number;
2231 switch (the_insn.reloc)
2236 case BFD_RELOC_SPARC_HH22:
2237 val = BSR (val, 32);
2240 case BFD_RELOC_SPARC_LM22:
2241 case BFD_RELOC_HI22:
2242 val = (val >> 10) & 0x3fffff;
2245 case BFD_RELOC_SPARC_HM10:
2246 val = BSR (val, 32);
2249 case BFD_RELOC_LO10:
2253 case BFD_RELOC_SPARC_H44:
2258 case BFD_RELOC_SPARC_M44:
2263 case BFD_RELOC_SPARC_L44:
2267 case BFD_RELOC_SPARC_HIX22:
2269 val = (val >> 10) & 0x3fffff;
2272 case BFD_RELOC_SPARC_LOX10:
2273 val = (val & 0x3ff) | 0x1c00;
2276 the_insn.exp = the_insn.exp2;
2277 the_insn.exp.X_add_number += val;
2278 the_insn.exp2.X_op = O_illegal;
2279 the_insn.reloc = old_reloc;
2281 else if (the_insn.exp2.X_op != O_constant)
2283 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2284 return special_case;
2288 if (old_reloc != BFD_RELOC_SPARC13
2289 || the_insn.reloc != BFD_RELOC_LO10
2290 || sparc_arch_size != 64
2293 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2294 return special_case;
2296 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2300 /* Check for constants that don't require emitting a reloc. */
2301 if (the_insn.exp.X_op == O_constant
2302 && the_insn.exp.X_add_symbol == 0
2303 && the_insn.exp.X_op_symbol == 0)
2305 /* For pc-relative call instructions, we reject
2306 constants to get better code. */
2308 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2309 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2311 error_message = _(": PC-relative operand can't be a constant");
2315 /* Constants that won't fit are checked in md_apply_fix3
2316 and bfd_install_relocation.
2317 ??? It would be preferable to install the constants
2318 into the insn here and save having to create a fixS
2319 for each one. There already exists code to handle
2320 all the various cases (e.g. in md_apply_fix3 and
2321 bfd_install_relocation) so duplicating all that code
2322 here isn't right. */
2342 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2344 error_message = _(": invalid ASI name");
2350 if (! parse_const_expr_arg (&s, &asi))
2352 error_message = _(": invalid ASI expression");
2355 if (asi < 0 || asi > 255)
2357 error_message = _(": invalid ASI number");
2361 opcode |= ASI (asi);
2363 } /* Alternate space. */
2366 if (strncmp (s, "%psr", 4) == 0)
2373 case 'q': /* Floating point queue. */
2374 if (strncmp (s, "%fq", 3) == 0)
2381 case 'Q': /* Coprocessor queue. */
2382 if (strncmp (s, "%cq", 3) == 0)
2390 if (strcmp (str, "set") == 0
2391 || strcmp (str, "setuw") == 0)
2393 special_case = SPECIAL_CASE_SET;
2396 else if (strcmp (str, "setsw") == 0)
2398 special_case = SPECIAL_CASE_SETSW;
2401 else if (strcmp (str, "setx") == 0)
2403 special_case = SPECIAL_CASE_SETX;
2406 else if (strncmp (str, "fdiv", 4) == 0)
2408 special_case = SPECIAL_CASE_FDIV;
2414 if (strncmp (s, "%asi", 4) != 0)
2420 if (strncmp (s, "%fprs", 5) != 0)
2426 if (strncmp (s, "%ccr", 4) != 0)
2432 if (strncmp (s, "%tbr", 4) != 0)
2438 if (strncmp (s, "%wim", 4) != 0)
2445 char *push = input_line_pointer;
2448 input_line_pointer = s;
2450 if (e.X_op == O_constant)
2452 int n = e.X_add_number;
2453 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2454 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2456 opcode |= e.X_add_number << 5;
2459 as_bad (_("non-immediate OPF operand, ignored"));
2460 s = input_line_pointer;
2461 input_line_pointer = push;
2466 if (strncmp (s, "%y", 2) != 0)
2474 /* Parse a sparclet cpreg. */
2476 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2478 error_message = _(": invalid cpreg name");
2481 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2486 as_fatal (_("failed sanity check."));
2487 } /* switch on arg code. */
2489 /* Break out of for() loop. */
2491 } /* For each arg that we expect. */
2496 /* Args don't match. */
2497 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2498 && (insn->name == insn[1].name
2499 || !strcmp (insn->name, insn[1].name)))
2507 as_bad (_("Illegal operands%s"), error_message);
2508 return special_case;
2513 /* We have a match. Now see if the architecture is OK. */
2514 int needed_arch_mask = insn->architecture;
2518 needed_arch_mask &= ~((1 << SPARC_OPCODE_ARCH_V9)
2519 | (1 << SPARC_OPCODE_ARCH_V9A));
2520 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2523 if (needed_arch_mask
2524 & SPARC_OPCODE_SUPPORTED (current_architecture))
2527 /* Can we bump up the architecture? */
2528 else if (needed_arch_mask
2529 & SPARC_OPCODE_SUPPORTED (max_architecture))
2531 enum sparc_opcode_arch_val needed_architecture =
2532 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2533 & needed_arch_mask);
2535 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2537 && needed_architecture > warn_after_architecture)
2539 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2540 sparc_opcode_archs[current_architecture].name,
2541 sparc_opcode_archs[needed_architecture].name,
2543 warn_after_architecture = needed_architecture;
2545 current_architecture = needed_architecture;
2548 /* ??? This seems to be a bit fragile. What if the next entry in
2549 the opcode table is the one we want and it is supported?
2550 It is possible to arrange the table today so that this can't
2551 happen but what about tomorrow? */
2554 int arch, printed_one_p = 0;
2556 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2558 /* Create a list of the architectures that support the insn. */
2559 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2561 arch = sparc_ffs (needed_arch_mask);
2562 while ((1 << arch) <= needed_arch_mask)
2564 if ((1 << arch) & needed_arch_mask)
2568 strcpy (p, sparc_opcode_archs[arch].name);
2575 as_bad (_("Architecture mismatch on \"%s\"."), str);
2576 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2578 sparc_opcode_archs[max_architecture].name);
2579 return special_case;
2581 } /* If no match. */
2584 } /* Forever looking for a match. */
2586 the_insn.opcode = opcode;
2587 return special_case;
2590 /* Parse an argument that can be expressed as a keyword.
2591 (eg: #StoreStore or %ccfr).
2592 The result is a boolean indicating success.
2593 If successful, INPUT_POINTER is updated. */
2596 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2597 int (*lookup_fn) PARAMS ((const char *));
2598 char **input_pointerP;
2604 p = *input_pointerP;
2605 for (q = p + (*p == '#' || *p == '%');
2606 isalnum ((unsigned char) *q) || *q == '_';
2611 value = (*lookup_fn) (p);
2616 *input_pointerP = q;
2620 /* Parse an argument that is a constant expression.
2621 The result is a boolean indicating success. */
2624 parse_const_expr_arg (input_pointerP, valueP)
2625 char **input_pointerP;
2628 char *save = input_line_pointer;
2631 input_line_pointer = *input_pointerP;
2632 /* The next expression may be something other than a constant
2633 (say if we're not processing the right variant of the insn).
2634 Don't call expression unless we're sure it will succeed as it will
2635 signal an error (which we want to defer until later). */
2636 /* FIXME: It might be better to define md_operand and have it recognize
2637 things like %asi, etc. but continuing that route through to the end
2638 is a lot of work. */
2639 if (*input_line_pointer == '%')
2641 input_line_pointer = save;
2645 *input_pointerP = input_line_pointer;
2646 input_line_pointer = save;
2647 if (exp.X_op != O_constant)
2649 *valueP = exp.X_add_number;
2653 /* Subroutine of sparc_ip to parse an expression. */
2656 get_expression (str)
2662 save_in = input_line_pointer;
2663 input_line_pointer = str;
2664 seg = expression (&the_insn.exp);
2665 if (seg != absolute_section
2666 && seg != text_section
2667 && seg != data_section
2668 && seg != bss_section
2669 && seg != undefined_section)
2671 the_insn.error = _("bad segment");
2672 expr_end = input_line_pointer;
2673 input_line_pointer = save_in;
2676 expr_end = input_line_pointer;
2677 input_line_pointer = save_in;
2681 /* Subroutine of md_assemble to output one insn. */
2684 output_insn (insn, the_insn)
2685 const struct sparc_opcode *insn;
2686 struct sparc_it *the_insn;
2688 char *toP = frag_more (4);
2690 /* Put out the opcode. */
2691 if (INSN_BIG_ENDIAN)
2692 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2694 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2696 /* Put out the symbol-dependent stuff. */
2697 if (the_insn->reloc != BFD_RELOC_NONE)
2699 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2700 (toP - frag_now->fr_literal), /* Where. */
2705 /* Turn off overflow checking in fixup_segment. We'll do our
2706 own overflow checking in md_apply_fix3. This is necessary because
2707 the insn size is 4 and fixup_segment will signal an overflow for
2708 large 8 byte quantities. */
2709 fixP->fx_no_overflow = 1;
2710 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2711 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2715 last_opcode = the_insn->opcode;
2718 /* This is identical to the md_atof in m68k.c. I think this is right,
2721 Turn a string in input_line_pointer into a floating point constant
2722 of type TYPE, and store the appropriate bytes in *LITP. The number
2723 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2724 returned, or NULL on OK. */
2726 /* Equal to MAX_PRECISION in atof-ieee.c. */
2727 #define MAX_LITTLENUMS 6
2730 md_atof (type, litP, sizeP)
2736 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2767 return _("Bad call to MD_ATOF()");
2770 t = atof_ieee (input_line_pointer, type, words);
2772 input_line_pointer = t;
2773 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2775 if (target_big_endian)
2777 for (i = 0; i < prec; i++)
2779 md_number_to_chars (litP, (valueT) words[i],
2780 sizeof (LITTLENUM_TYPE));
2781 litP += sizeof (LITTLENUM_TYPE);
2786 for (i = prec - 1; i >= 0; i--)
2788 md_number_to_chars (litP, (valueT) words[i],
2789 sizeof (LITTLENUM_TYPE));
2790 litP += sizeof (LITTLENUM_TYPE);
2797 /* Write a value out to the object file, using the appropriate
2801 md_number_to_chars (buf, val, n)
2806 if (target_big_endian)
2807 number_to_chars_bigendian (buf, val, n);
2808 else if (target_little_endian_data
2809 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2810 /* Output debug words, which are not in allocated sections, as big
2812 number_to_chars_bigendian (buf, val, n);
2813 else if (target_little_endian_data || ! target_big_endian)
2814 number_to_chars_littleendian (buf, val, n);
2817 /* Apply a fixS to the frags, now that we know the value it ought to
2821 md_apply_fix3 (fixP, value, segment)
2826 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2832 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2834 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2837 /* FIXME: SPARC ELF relocations don't use an addend in the data
2838 field itself. This whole approach should be somehow combined
2839 with the calls to bfd_install_relocation. Also, the value passed
2840 in by fixup_segment includes the value of a defined symbol. We
2841 don't want to include the value of an externally visible symbol. */
2842 if (fixP->fx_addsy != NULL)
2844 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2845 && (S_IS_EXTERNAL (fixP->fx_addsy)
2846 || S_IS_WEAK (fixP->fx_addsy)
2847 || (sparc_pic_code && ! fixP->fx_pcrel)
2848 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2849 && ((bfd_get_section_flags (stdoutput,
2850 S_GET_SEGMENT (fixP->fx_addsy))
2851 & SEC_LINK_ONCE) != 0
2852 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2854 sizeof ".gnu.linkonce" - 1) == 0)))
2855 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2856 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2857 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2858 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2863 /* This is a hack. There should be a better way to
2864 handle this. Probably in terms of howto fields, once
2865 we can look at these fixups in terms of howtos. */
2866 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2867 val += fixP->fx_where + fixP->fx_frag->fr_address;
2870 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2871 generate a reloc, then we just want to let the reloc addend set
2872 the value. We do not want to also stuff the addend into the
2873 object file. Including the addend in the object file works when
2874 doing a static link, because the linker will ignore the object
2875 file contents. However, the dynamic linker does not ignore the
2876 object file contents. */
2877 if (fixP->fx_addsy != NULL
2878 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2881 /* When generating PIC code, we do not want an addend for a reloc
2882 against a local symbol. We adjust fx_addnumber to cancel out the
2883 value already included in val, and to also cancel out the
2884 adjustment which bfd_install_relocation will create. */
2886 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2887 && fixP->fx_addsy != NULL
2888 && ! S_IS_COMMON (fixP->fx_addsy)
2889 && symbol_section_p (fixP->fx_addsy))
2890 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2892 /* When generating PIC code, we need to fiddle to get
2893 bfd_install_relocation to do the right thing for a PC relative
2894 reloc against a local symbol which we are going to keep. */
2896 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2897 && fixP->fx_addsy != NULL
2898 && (S_IS_EXTERNAL (fixP->fx_addsy)
2899 || S_IS_WEAK (fixP->fx_addsy))
2900 && S_IS_DEFINED (fixP->fx_addsy)
2901 && ! S_IS_COMMON (fixP->fx_addsy))
2904 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2908 /* If this is a data relocation, just output VAL. */
2910 if (fixP->fx_r_type == BFD_RELOC_16)
2912 md_number_to_chars (buf, val, 2);
2914 else if (fixP->fx_r_type == BFD_RELOC_32
2915 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2917 md_number_to_chars (buf, val, 4);
2919 else if (fixP->fx_r_type == BFD_RELOC_64)
2921 md_number_to_chars (buf, val, 8);
2923 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2924 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2931 /* It's a relocation against an instruction. */
2933 if (INSN_BIG_ENDIAN)
2934 insn = bfd_getb32 ((unsigned char *) buf);
2936 insn = bfd_getl32 ((unsigned char *) buf);
2938 switch (fixP->fx_r_type)
2940 case BFD_RELOC_32_PCREL_S2:
2942 /* FIXME: This increment-by-one deserves a comment of why it's
2944 if (! sparc_pic_code
2945 || fixP->fx_addsy == NULL
2946 || symbol_section_p (fixP->fx_addsy))
2949 insn |= val & 0x3fffffff;
2951 /* See if we have a delay slot. */
2952 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
2956 #define XCC (2 << 20)
2957 #define COND(x) (((x)&0xf)<<25)
2958 #define CONDA COND(0x8)
2959 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
2960 #define INSN_BA (F2(0,2) | CONDA)
2961 #define INSN_OR F3(2, 0x2, 0)
2962 #define INSN_NOP F2(0,4)
2966 /* If the instruction is a call with either:
2968 arithmetic instruction with rd == %o7
2969 where rs1 != %o7 and rs2 if it is register != %o7
2970 then we can optimize if the call destination is near
2971 by changing the call into a branch always. */
2972 if (INSN_BIG_ENDIAN)
2973 delay = bfd_getb32 ((unsigned char *) buf + 4);
2975 delay = bfd_getl32 ((unsigned char *) buf + 4);
2976 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
2978 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
2979 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
2980 || ((delay & RD (~0)) != RD (O7))))
2982 if ((delay & RS1 (~0)) == RS1 (O7)
2983 || ((delay & F3I (~0)) == 0
2984 && (delay & RS2 (~0)) == RS2 (O7)))
2986 /* Ensure the branch will fit into simm22. */
2987 if ((val & 0x3fe00000)
2988 && (val & 0x3fe00000) != 0x3fe00000)
2990 /* Check if the arch is v9 and branch will fit
2992 if (((val & 0x3c0000) == 0
2993 || (val & 0x3c0000) == 0x3c0000)
2994 && (sparc_arch_size == 64
2995 || current_architecture >= SPARC_OPCODE_ARCH_V9))
2997 insn = INSN_BPA | (val & 0x7ffff);
3000 insn = INSN_BA | (val & 0x3fffff);
3001 if (fixP->fx_where >= 4
3002 && ((delay & (0xffffffff ^ RS1 (~0)))
3003 == (INSN_OR | RD (O7) | RS2 (G0))))
3008 if (INSN_BIG_ENDIAN)
3009 setter = bfd_getb32 ((unsigned char *) buf - 4);
3011 setter = bfd_getl32 ((unsigned char *) buf - 4);
3012 if ((setter & (0xffffffff ^ RD (~0)))
3013 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3020 If call foo was replaced with ba, replace
3021 or %rN, %g0, %o7 with nop. */
3022 reg = (delay & RS1 (~0)) >> 14;
3023 if (reg != ((setter & RD (~0)) >> 25)
3024 || reg == G0 || reg == O7)
3027 if (INSN_BIG_ENDIAN)
3028 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3030 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3035 case BFD_RELOC_SPARC_11:
3036 if (! in_signed_range (val, 0x7ff))
3037 as_bad_where (fixP->fx_file, fixP->fx_line,
3038 _("relocation overflow"));
3039 insn |= val & 0x7ff;
3042 case BFD_RELOC_SPARC_10:
3043 if (! in_signed_range (val, 0x3ff))
3044 as_bad_where (fixP->fx_file, fixP->fx_line,
3045 _("relocation overflow"));
3046 insn |= val & 0x3ff;
3049 case BFD_RELOC_SPARC_7:
3050 if (! in_bitfield_range (val, 0x7f))
3051 as_bad_where (fixP->fx_file, fixP->fx_line,
3052 _("relocation overflow"));
3056 case BFD_RELOC_SPARC_6:
3057 if (! in_bitfield_range (val, 0x3f))
3058 as_bad_where (fixP->fx_file, fixP->fx_line,
3059 _("relocation overflow"));
3063 case BFD_RELOC_SPARC_5:
3064 if (! in_bitfield_range (val, 0x1f))
3065 as_bad_where (fixP->fx_file, fixP->fx_line,
3066 _("relocation overflow"));
3070 case BFD_RELOC_SPARC_WDISP16:
3071 /* FIXME: simplify. */
3072 if (((val > 0) && (val & ~0x3fffc))
3073 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3074 as_bad_where (fixP->fx_file, fixP->fx_line,
3075 _("relocation overflow"));
3076 /* FIXME: The +1 deserves a comment. */
3077 val = (val >> 2) + 1;
3078 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3081 case BFD_RELOC_SPARC_WDISP19:
3082 /* FIXME: simplify. */
3083 if (((val > 0) && (val & ~0x1ffffc))
3084 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3085 as_bad_where (fixP->fx_file, fixP->fx_line,
3086 _("relocation overflow"));
3087 /* FIXME: The +1 deserves a comment. */
3088 val = (val >> 2) + 1;
3089 insn |= val & 0x7ffff;
3092 case BFD_RELOC_SPARC_HH22:
3093 val = BSR (val, 32);
3096 case BFD_RELOC_SPARC_LM22:
3097 case BFD_RELOC_HI22:
3098 if (!fixP->fx_addsy)
3100 insn |= (val >> 10) & 0x3fffff;
3104 /* FIXME: Need comment explaining why we do this. */
3109 case BFD_RELOC_SPARC22:
3110 if (val & ~0x003fffff)
3111 as_bad_where (fixP->fx_file, fixP->fx_line,
3112 _("relocation overflow"));
3113 insn |= (val & 0x3fffff);
3116 case BFD_RELOC_SPARC_HM10:
3117 val = BSR (val, 32);
3120 case BFD_RELOC_LO10:
3121 if (!fixP->fx_addsy)
3123 insn |= val & 0x3ff;
3127 /* FIXME: Need comment explaining why we do this. */
3132 case BFD_RELOC_SPARC_OLO10:
3134 val += fixP->tc_fix_data;
3137 case BFD_RELOC_SPARC13:
3138 if (! in_signed_range (val, 0x1fff))
3139 as_bad_where (fixP->fx_file, fixP->fx_line,
3140 _("relocation overflow"));
3141 insn |= val & 0x1fff;
3144 case BFD_RELOC_SPARC_WDISP22:
3145 val = (val >> 2) + 1;
3147 case BFD_RELOC_SPARC_BASE22:
3148 insn |= val & 0x3fffff;
3151 case BFD_RELOC_SPARC_H44:
3152 if (!fixP->fx_addsy)
3156 insn |= tval & 0x3fffff;
3160 case BFD_RELOC_SPARC_M44:
3161 if (!fixP->fx_addsy)
3162 insn |= (val >> 12) & 0x3ff;
3165 case BFD_RELOC_SPARC_L44:
3166 if (!fixP->fx_addsy)
3167 insn |= val & 0xfff;
3170 case BFD_RELOC_SPARC_HIX22:
3171 if (!fixP->fx_addsy)
3173 val ^= ~(offsetT) 0;
3174 insn |= (val >> 10) & 0x3fffff;
3178 case BFD_RELOC_SPARC_LOX10:
3179 if (!fixP->fx_addsy)
3180 insn |= 0x1c00 | (val & 0x3ff);
3183 case BFD_RELOC_NONE:
3185 as_bad_where (fixP->fx_file, fixP->fx_line,
3186 _("bad or unhandled relocation type: 0x%02x"),
3191 if (INSN_BIG_ENDIAN)
3192 bfd_putb32 (insn, (unsigned char *) buf);
3194 bfd_putl32 (insn, (unsigned char *) buf);
3197 /* Are we finished with this relocation now? */
3198 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3204 /* Translate internal representation of relocation info to BFD target
3208 tc_gen_reloc (section, fixp)
3212 static arelent *relocs[3];
3214 bfd_reloc_code_real_type code;
3216 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3219 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3220 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3221 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3223 switch (fixp->fx_r_type)
3227 case BFD_RELOC_HI22:
3228 case BFD_RELOC_LO10:
3229 case BFD_RELOC_32_PCREL_S2:
3230 case BFD_RELOC_SPARC13:
3231 case BFD_RELOC_SPARC22:
3232 case BFD_RELOC_SPARC_BASE13:
3233 case BFD_RELOC_SPARC_WDISP16:
3234 case BFD_RELOC_SPARC_WDISP19:
3235 case BFD_RELOC_SPARC_WDISP22:
3237 case BFD_RELOC_SPARC_5:
3238 case BFD_RELOC_SPARC_6:
3239 case BFD_RELOC_SPARC_7:
3240 case BFD_RELOC_SPARC_10:
3241 case BFD_RELOC_SPARC_11:
3242 case BFD_RELOC_SPARC_HH22:
3243 case BFD_RELOC_SPARC_HM10:
3244 case BFD_RELOC_SPARC_LM22:
3245 case BFD_RELOC_SPARC_PC_HH22:
3246 case BFD_RELOC_SPARC_PC_HM10:
3247 case BFD_RELOC_SPARC_PC_LM22:
3248 case BFD_RELOC_SPARC_H44:
3249 case BFD_RELOC_SPARC_M44:
3250 case BFD_RELOC_SPARC_L44:
3251 case BFD_RELOC_SPARC_HIX22:
3252 case BFD_RELOC_SPARC_LOX10:
3253 case BFD_RELOC_SPARC_REV32:
3254 case BFD_RELOC_SPARC_OLO10:
3255 case BFD_RELOC_VTABLE_ENTRY:
3256 case BFD_RELOC_VTABLE_INHERIT:
3257 code = fixp->fx_r_type;
3264 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3265 /* If we are generating PIC code, we need to generate a different
3269 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3271 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3274 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3280 case BFD_RELOC_32_PCREL_S2:
3281 if (! S_IS_DEFINED (fixp->fx_addsy)
3282 || S_IS_COMMON (fixp->fx_addsy)
3283 || S_IS_EXTERNAL (fixp->fx_addsy)
3284 || S_IS_WEAK (fixp->fx_addsy))
3285 code = BFD_RELOC_SPARC_WPLT30;
3287 case BFD_RELOC_HI22:
3288 if (fixp->fx_addsy != NULL
3289 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3290 code = BFD_RELOC_SPARC_PC22;
3292 code = BFD_RELOC_SPARC_GOT22;
3294 case BFD_RELOC_LO10:
3295 if (fixp->fx_addsy != NULL
3296 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3297 code = BFD_RELOC_SPARC_PC10;
3299 code = BFD_RELOC_SPARC_GOT10;
3301 case BFD_RELOC_SPARC13:
3302 code = BFD_RELOC_SPARC_GOT13;
3308 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3310 if (code == BFD_RELOC_SPARC_OLO10)
3311 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3313 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3314 if (reloc->howto == 0)
3316 as_bad_where (fixp->fx_file, fixp->fx_line,
3317 _("internal error: can't export reloc type %d (`%s')"),
3318 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3324 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3327 if (reloc->howto->pc_relative == 0
3328 || code == BFD_RELOC_SPARC_PC10
3329 || code == BFD_RELOC_SPARC_PC22)
3330 reloc->addend = fixp->fx_addnumber;
3331 else if (sparc_pic_code
3332 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3333 && fixp->fx_addsy != NULL
3334 && (S_IS_EXTERNAL (fixp->fx_addsy)
3335 || S_IS_WEAK (fixp->fx_addsy))
3336 && S_IS_DEFINED (fixp->fx_addsy)
3337 && ! S_IS_COMMON (fixp->fx_addsy))
3338 reloc->addend = fixp->fx_addnumber;
3340 reloc->addend = fixp->fx_offset - reloc->address;
3342 #else /* elf or coff */
3344 if (reloc->howto->pc_relative == 0
3345 || code == BFD_RELOC_SPARC_PC10
3346 || code == BFD_RELOC_SPARC_PC22)
3347 reloc->addend = fixp->fx_addnumber;
3348 else if (symbol_section_p (fixp->fx_addsy))
3349 reloc->addend = (section->vma
3350 + fixp->fx_addnumber
3351 + md_pcrel_from (fixp));
3353 reloc->addend = fixp->fx_offset;
3356 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3357 on the same location. */
3358 if (code == BFD_RELOC_SPARC_OLO10)
3360 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3363 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3365 = symbol_get_bfdsym (section_symbol (absolute_section));
3366 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3367 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3368 reloc->addend = fixp->tc_fix_data;
3374 /* We have no need to default values of symbols. */
3377 md_undefined_symbol (name)
3383 /* Round up a section size to the appropriate boundary. */
3386 md_section_align (segment, size)
3391 /* This is not right for ELF; a.out wants it, and COFF will force
3392 the alignment anyways. */
3393 valueT align = ((valueT) 1
3394 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3397 /* Turn alignment value into a mask. */
3399 newsize = (size + align) & ~align;
3406 /* Exactly what point is a PC-relative offset relative TO?
3407 On the sparc, they're relative to the address of the offset, plus
3408 its size. This gets us to the following instruction.
3409 (??? Is this right? FIXME-SOON) */
3411 md_pcrel_from (fixP)
3416 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3417 if (! sparc_pic_code
3418 || fixP->fx_addsy == NULL
3419 || symbol_section_p (fixP->fx_addsy))
3420 ret += fixP->fx_size;
3424 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3436 for (shift = 0; (value & 1) == 0; value >>= 1)
3439 return (value == 1) ? shift : -1;
3442 /* Sort of like s_lcomm. */
3445 static int max_alignment = 15;
3460 name = input_line_pointer;
3461 c = get_symbol_end ();
3462 p = input_line_pointer;
3466 if (*input_line_pointer != ',')
3468 as_bad (_("Expected comma after name"));
3469 ignore_rest_of_line ();
3473 ++input_line_pointer;
3475 if ((size = get_absolute_expression ()) < 0)
3477 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3478 ignore_rest_of_line ();
3483 symbolP = symbol_find_or_make (name);
3486 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3487 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3489 as_bad (_("bad .reserve segment -- expected BSS segment"));
3493 if (input_line_pointer[2] == '.')
3494 input_line_pointer += 7;
3496 input_line_pointer += 6;
3499 if (*input_line_pointer == ',')
3501 ++input_line_pointer;
3504 if (*input_line_pointer == '\n')
3506 as_bad (_("missing alignment"));
3507 ignore_rest_of_line ();
3511 align = (int) get_absolute_expression ();
3514 if (align > max_alignment)
3516 align = max_alignment;
3517 as_warn (_("alignment too large; assuming %d"), align);
3523 as_bad (_("negative alignment"));
3524 ignore_rest_of_line ();
3530 temp = log2 (align);
3533 as_bad (_("alignment not a power of 2"));
3534 ignore_rest_of_line ();
3541 record_alignment (bss_section, align);
3546 if (!S_IS_DEFINED (symbolP)
3548 && S_GET_OTHER (symbolP) == 0
3549 && S_GET_DESC (symbolP) == 0
3556 segT current_seg = now_seg;
3557 subsegT current_subseg = now_subseg;
3559 /* Switch to bss. */
3560 subseg_set (bss_section, 1);
3564 frag_align (align, 0, 0);
3566 /* Detach from old frag. */
3567 if (S_GET_SEGMENT (symbolP) == bss_section)
3568 symbol_get_frag (symbolP)->fr_symbol = NULL;
3570 symbol_set_frag (symbolP, frag_now);
3571 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3572 (offsetT) size, (char *) 0);
3575 S_SET_SEGMENT (symbolP, bss_section);
3577 subseg_set (current_seg, current_subseg);
3580 S_SET_SIZE (symbolP, size);
3586 as_warn ("Ignoring attempt to re-define symbol %s",
3587 S_GET_NAME (symbolP));
3588 } /* if not redefining. */
3590 demand_empty_rest_of_line ();
3603 name = input_line_pointer;
3604 c = get_symbol_end ();
3605 /* Just after name is now '\0'. */
3606 p = input_line_pointer;
3609 if (*input_line_pointer != ',')
3611 as_bad (_("Expected comma after symbol-name"));
3612 ignore_rest_of_line ();
3617 input_line_pointer++;
3619 if ((temp = get_absolute_expression ()) < 0)
3621 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3622 ignore_rest_of_line ();
3627 symbolP = symbol_find_or_make (name);
3629 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3631 as_bad (_("Ignoring attempt to re-define symbol"));
3632 ignore_rest_of_line ();
3635 if (S_GET_VALUE (symbolP) != 0)
3637 if (S_GET_VALUE (symbolP) != (valueT) size)
3639 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3640 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3646 S_SET_VALUE (symbolP, (valueT) size);
3647 S_SET_EXTERNAL (symbolP);
3650 know (symbol_get_frag (symbolP) == &zero_address_frag);
3651 if (*input_line_pointer != ',')
3653 as_bad (_("Expected comma after common length"));
3654 ignore_rest_of_line ();
3657 input_line_pointer++;
3659 if (*input_line_pointer != '"')
3661 temp = get_absolute_expression ();
3664 if (temp > max_alignment)
3666 temp = max_alignment;
3667 as_warn (_("alignment too large; assuming %d"), temp);
3673 as_bad (_("negative alignment"));
3674 ignore_rest_of_line ();
3679 if (symbol_get_obj (symbolP)->local)
3687 old_subsec = now_subseg;
3692 align = log2 (temp);
3696 as_bad (_("alignment not a power of 2"));
3697 ignore_rest_of_line ();
3701 record_alignment (bss_section, align);
3702 subseg_set (bss_section, 0);
3704 frag_align (align, 0, 0);
3705 if (S_GET_SEGMENT (symbolP) == bss_section)
3706 symbol_get_frag (symbolP)->fr_symbol = 0;
3707 symbol_set_frag (symbolP, frag_now);
3708 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3709 (offsetT) size, (char *) 0);
3711 S_SET_SEGMENT (symbolP, bss_section);
3712 S_CLEAR_EXTERNAL (symbolP);
3713 S_SET_SIZE (symbolP, size);
3714 subseg_set (old_sec, old_subsec);
3717 #endif /* OBJ_ELF */
3720 S_SET_VALUE (symbolP, (valueT) size);
3722 S_SET_ALIGN (symbolP, temp);
3723 S_SET_SIZE (symbolP, size);
3725 S_SET_EXTERNAL (symbolP);
3726 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3731 input_line_pointer++;
3732 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3733 if (*input_line_pointer == '.')
3734 input_line_pointer++;
3735 /* @@ Some say data, some say bss. */
3736 if (strncmp (input_line_pointer, "bss\"", 4)
3737 && strncmp (input_line_pointer, "data\"", 5))
3739 while (*--input_line_pointer != '"')
3741 input_line_pointer--;
3742 goto bad_common_segment;
3744 while (*input_line_pointer++ != '"')
3746 goto allocate_common;
3749 #ifdef BFD_ASSEMBLER
3750 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3753 demand_empty_rest_of_line ();
3758 p = input_line_pointer;
3759 while (*p && *p != '\n')
3763 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3765 input_line_pointer = p;
3766 ignore_rest_of_line ();
3771 /* Handle the .empty pseudo-op. This supresses the warnings about
3772 invalid delay slot usage. */
3778 /* The easy way to implement is to just forget about the last
3788 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3790 input_line_pointer += 6;
3794 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3796 input_line_pointer += 6;
3800 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3802 input_line_pointer += 7;
3806 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3808 input_line_pointer += 5;
3809 /* We only support 2 segments -- text and data -- for now, so
3810 things in the "bss segment" will have to go into data for now.
3811 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3812 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3815 as_bad (_("Unknown segment type"));
3816 demand_empty_rest_of_line ();
3822 subseg_set (data_section, 1);
3823 demand_empty_rest_of_line ();
3830 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3832 ++input_line_pointer;
3834 ++input_line_pointer;
3837 /* This static variable is set by s_uacons to tell sparc_cons_align
3838 that the expession does not need to be aligned. */
3840 static int sparc_no_align_cons = 0;
3842 /* This handles the unaligned space allocation pseudo-ops, such as
3843 .uaword. .uaword is just like .word, but the value does not need
3850 /* Tell sparc_cons_align not to align this value. */
3851 sparc_no_align_cons = 1;
3855 /* This handles the native word allocation pseudo-op .nword.
3856 For sparc_arch_size 32 it is equivalent to .word, for
3857 sparc_arch_size 64 it is equivalent to .xword. */
3863 cons (sparc_arch_size == 32 ? 4 : 8);
3867 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3871 .register %g[2367],{#scratch|symbolname|#ignore}
3881 const char *regname;
3883 if (input_line_pointer[0] != '%'
3884 || input_line_pointer[1] != 'g'
3885 || ((input_line_pointer[2] & ~1) != '2'
3886 && (input_line_pointer[2] & ~1) != '6')
3887 || input_line_pointer[3] != ',')
3888 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3889 reg = input_line_pointer[2] - '0';
3890 input_line_pointer += 4;
3892 if (*input_line_pointer == '#')
3894 ++input_line_pointer;
3895 regname = input_line_pointer;
3896 c = get_symbol_end ();
3897 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3898 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3899 if (regname[0] == 'i')
3906 regname = input_line_pointer;
3907 c = get_symbol_end ();
3909 if (sparc_arch_size == 64)
3913 if ((regname && globals[reg] != (symbolS *) 1
3914 && strcmp (S_GET_NAME (globals[reg]), regname))
3915 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3916 as_bad (_("redefinition of global register"));
3920 if (regname == NULL)
3921 globals[reg] = (symbolS *) 1;
3926 if (symbol_find (regname))
3927 as_bad (_("Register symbol %s already defined."),
3930 globals[reg] = symbol_make (regname);
3931 flags = symbol_get_bfdsym (globals[reg])->flags;
3933 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3934 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3935 flags |= BSF_GLOBAL;
3936 symbol_get_bfdsym (globals[reg])->flags = flags;
3937 S_SET_VALUE (globals[reg], (valueT) reg);
3938 S_SET_ALIGN (globals[reg], reg);
3939 S_SET_SIZE (globals[reg], 0);
3940 /* Although we actually want undefined_section here,
3941 we have to use absolute_section, because otherwise
3942 generic as code will make it a COM section.
3943 We fix this up in sparc_adjust_symtab. */
3944 S_SET_SEGMENT (globals[reg], absolute_section);
3945 S_SET_OTHER (globals[reg], 0);
3946 elf_symbol (symbol_get_bfdsym (globals[reg]))
3947 ->internal_elf_sym.st_info =
3948 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
3949 elf_symbol (symbol_get_bfdsym (globals[reg]))
3950 ->internal_elf_sym.st_shndx = SHN_UNDEF;
3955 *input_line_pointer = c;
3957 demand_empty_rest_of_line ();
3960 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
3961 symbols which need it. */
3964 sparc_adjust_symtab ()
3968 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
3970 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3971 ->internal_elf_sym.st_info) != STT_REGISTER)
3974 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
3975 ->internal_elf_sym.st_shndx != SHN_UNDEF))
3978 S_SET_SEGMENT (sym, undefined_section);
3983 /* If the --enforce-aligned-data option is used, we require .word,
3984 et. al., to be aligned correctly. We do it by setting up an
3985 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3986 no unexpected alignment was introduced.
3988 The SunOS and Solaris native assemblers enforce aligned data by
3989 default. We don't want to do that, because gcc can deliberately
3990 generate misaligned data if the packed attribute is used. Instead,
3991 we permit misaligned data by default, and permit the user to set an
3992 option to check for it. */
3995 sparc_cons_align (nbytes)
4001 /* Only do this if we are enforcing aligned data. */
4002 if (! enforce_aligned_data)
4005 if (sparc_no_align_cons)
4007 /* This is an unaligned pseudo-op. */
4008 sparc_no_align_cons = 0;
4012 nalign = log2 (nbytes);
4016 assert (nalign > 0);
4018 if (now_seg == absolute_section)
4020 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4021 as_bad (_("misaligned data"));
4025 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
4026 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4028 record_alignment (now_seg, nalign);
4031 /* This is where we do the unexpected alignment check.
4032 This is called from HANDLE_ALIGN in tc-sparc.h. */
4035 sparc_handle_align (fragp)
4038 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
4039 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
4040 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4041 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
4044 fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4049 && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
4051 unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
4054 for (i = 0; i < count; i += 4, p++)
4055 if (INSN_BIG_ENDIAN)
4057 number_to_chars_bigendian ((char *) p, 0x01000000, 4);
4059 number_to_chars_littleendian ((char *) p, 0x10000000, 4);
4061 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4063 char *waddr = &fragp->fr_literal[fragp->fr_fix];
4064 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4065 if (INSN_BIG_ENDIAN)
4066 number_to_chars_bigendian (waddr, wval, 4);
4068 number_to_chars_littleendian (waddr, wval, 4);
4070 fragp->fr_var = count;
4076 /* Some special processing for a Sparc ELF file. */
4079 sparc_elf_final_processing ()
4081 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4082 sort of BFD interface for this. */
4083 if (sparc_arch_size == 64)
4085 switch (sparc_memory_model)
4088 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4091 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4097 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4098 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4099 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4100 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4104 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4105 reloc for a cons. We could use the definition there, except that
4106 we want to handle little endian relocs specially. */
4109 cons_fix_new_sparc (frag, where, nbytes, exp)
4112 unsigned int nbytes;
4115 bfd_reloc_code_real_type r;
4117 r = (nbytes == 1 ? BFD_RELOC_8 :
4118 (nbytes == 2 ? BFD_RELOC_16 :
4119 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4121 if (target_little_endian_data && nbytes == 4
4122 && now_seg->flags & SEC_ALLOC)
4123 r = BFD_RELOC_SPARC_REV32;
4124 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4129 elf32_sparc_force_relocation (fixp)
4132 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4133 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)