1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-95, 1996 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* careful, this file includes data *declarations* */
28 #include "opcode/sparc.h"
30 static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
32 /* Current architecture. We don't bump up unless necessary. */
33 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
35 /* The maximum architecture level we can bump up to.
36 In a 32 bit environment, don't allow bumping up to v9 by default.
37 The native assembler works this way. The user is required to pass
38 an explicit argument before we'll create v9 object files. However, if
39 we don't see any v9 insns, a v9 object file is not created. */
41 static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_V9;
43 /* ??? This should be V8, but sparclite support was added by making it the
44 default. GCC now passes -Asparclite, so maybe sometime in the future
45 we can set this to V8. */
46 static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_SPARCLITE;
49 static int architecture_requested;
50 static int warn_on_bump;
52 /* If warn_on_bump and the needed architecture is higher than this
53 architecture, issue a warning. */
54 static enum sparc_opcode_arch_val warn_after_architecture;
56 /* Non-zero if we are generating PIC code. */
59 /* Non-zero if we should give an error when misaligned data is seen. */
60 static int enforce_aligned_data;
62 extern int target_big_endian;
64 /* V9 has big and little endian data, but instructions are always big endian.
65 The sparclet has bi-endian support but both data and insns have the same
66 endianness. Global `target_big_endian' is used for data. The following
67 macro is used for instructions. */
68 #define INSN_BIG_ENDIAN (target_big_endian \
69 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
71 /* handle of the OPCODE hash table */
72 static struct hash_control *op_hash;
74 static void s_data1 PARAMS ((void));
75 static void s_seg PARAMS ((int));
76 static void s_proc PARAMS ((int));
77 static void s_reserve PARAMS ((int));
78 static void s_common PARAMS ((int));
79 static void s_empty PARAMS ((int));
80 static void s_uacons PARAMS ((int));
82 const pseudo_typeS md_pseudo_table[] =
84 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
85 {"common", s_common, 0},
86 {"empty", s_empty, 0},
87 {"global", s_globl, 0},
89 {"optim", s_ignore, 0},
91 {"reserve", s_reserve, 0},
96 {"uahalf", s_uacons, 2},
97 {"uaword", s_uacons, 4},
98 {"uaxword", s_uacons, 8},
100 /* these are specific to sparc/svr4 */
101 {"pushsection", obj_elf_section, 0},
102 {"popsection", obj_elf_previous, 0},
103 {"2byte", s_uacons, 2},
104 {"4byte", s_uacons, 4},
105 {"8byte", s_uacons, 8},
110 const int md_reloc_size = 12; /* Size of relocation record */
112 /* This array holds the chars that always start a comment. If the
113 pre-processor is disabled, these aren't very useful */
114 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
116 /* This array holds the chars that only start a comment at the beginning of
117 a line. If the line seems to have the form '# 123 filename'
118 .line and .file directives will appear in the pre-processed output */
119 /* Note that input_file.c hand checks for '#' at the beginning of the
120 first line of the input file. This is because the compiler outputs
121 #NO_APP at the beginning of its output. */
122 /* Also note that comments started like this one will always
123 work if '/' isn't otherwise defined. */
124 const char line_comment_chars[] = "#";
126 const char line_separator_chars[] = "";
128 /* Chars that can be used to separate mant from exp in floating point nums */
129 const char EXP_CHARS[] = "eE";
131 /* Chars that mean this number is a floating point constant */
134 const char FLT_CHARS[] = "rRsSfFdDxXpP";
136 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
137 changed in read.c. Ideally it shouldn't have to know about it at all,
138 but nothing is ideal around here. */
140 static unsigned char octal[256];
141 #define isoctal(c) octal[(unsigned char) (c)]
142 static unsigned char toHex[256];
147 unsigned long opcode;
148 struct nlist *nlistp;
151 bfd_reloc_code_real_type reloc;
154 struct sparc_it the_insn, set_insn;
156 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
159 in_signed_range (val, max)
160 bfd_signed_vma val, max;
171 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
172 (e.g. -15 to +31). */
175 in_bitfield_range (val, max)
176 bfd_signed_vma val, max;
182 if (val < ~(max >> 1))
196 for (i = 0; (mask & 1) == 0; ++i)
201 /* Implement big shift right. */
207 if (sizeof (bfd_vma) <= 4 && amount >= 32)
208 as_fatal ("Support for 64-bit arithmetic not compiled in.");
209 return val >> amount;
213 static void print_insn PARAMS ((struct sparc_it *insn));
215 static int getExpression PARAMS ((char *str));
217 static char *expr_end;
218 static int special_case;
221 * Instructions that require wierd handling because they're longer than
224 #define SPECIAL_CASE_SET 1
225 #define SPECIAL_CASE_SETSW 2
226 #define SPECIAL_CASE_SETX 3
227 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
228 #define SPECIAL_CASE_FDIV 4
230 /* Bit masks of various insns. */
231 #define NOP_INSN 0x01000000
232 #define OR_INSN 0x80100000
233 #define FMOVS_INSN 0x81A00020
234 #define SETHI_INSN 0x01000000
235 #define SLLX_INSN 0x81281000
236 #define SRA_INSN 0x81380000
238 /* The last instruction to be assembled. */
239 static const struct sparc_opcode *last_insn;
242 * sort of like s_lcomm
246 static int max_alignment = 15;
261 name = input_line_pointer;
262 c = get_symbol_end ();
263 p = input_line_pointer;
267 if (*input_line_pointer != ',')
269 as_bad ("Expected comma after name");
270 ignore_rest_of_line ();
274 ++input_line_pointer;
276 if ((size = get_absolute_expression ()) < 0)
278 as_bad ("BSS length (%d.) <0! Ignored.", size);
279 ignore_rest_of_line ();
284 symbolP = symbol_find_or_make (name);
287 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
288 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
290 as_bad ("bad .reserve segment -- expected BSS segment");
294 if (input_line_pointer[2] == '.')
295 input_line_pointer += 7;
297 input_line_pointer += 6;
300 if (*input_line_pointer == ',')
302 ++input_line_pointer;
305 if (*input_line_pointer == '\n')
307 as_bad ("Missing alignment");
311 align = get_absolute_expression ();
313 if (align > max_alignment)
315 align = max_alignment;
316 as_warn ("Alignment too large: %d. assumed.", align);
322 as_warn ("Alignment negative. 0 assumed.");
325 record_alignment (bss_section, align);
327 /* convert to a power of 2 alignment */
328 for (temp = 0; (align & 1) == 0; align >>= 1, ++temp);;
332 as_bad ("Alignment not a power of 2");
333 ignore_rest_of_line ();
335 } /* not a power of two */
338 } /* if has optional alignment */
342 if (!S_IS_DEFINED (symbolP)
344 && S_GET_OTHER (symbolP) == 0
345 && S_GET_DESC (symbolP) == 0
352 segT current_seg = now_seg;
353 subsegT current_subseg = now_subseg;
355 subseg_set (bss_section, 1); /* switch to bss */
358 frag_align (align, 0); /* do alignment */
360 /* detach from old frag */
361 if (S_GET_SEGMENT(symbolP) == bss_section)
362 symbolP->sy_frag->fr_symbol = NULL;
364 symbolP->sy_frag = frag_now;
365 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
369 S_SET_SEGMENT (symbolP, bss_section);
371 subseg_set (current_seg, current_subseg);
376 as_warn("Ignoring attempt to re-define symbol %s",
377 S_GET_NAME (symbolP));
378 } /* if not redefining */
380 demand_empty_rest_of_line ();
393 name = input_line_pointer;
394 c = get_symbol_end ();
395 /* just after name is now '\0' */
396 p = input_line_pointer;
399 if (*input_line_pointer != ',')
401 as_bad ("Expected comma after symbol-name");
402 ignore_rest_of_line ();
405 input_line_pointer++; /* skip ',' */
406 if ((temp = get_absolute_expression ()) < 0)
408 as_bad (".COMMon length (%d.) <0! Ignored.", temp);
409 ignore_rest_of_line ();
414 symbolP = symbol_find_or_make (name);
416 if (S_IS_DEFINED (symbolP))
418 as_bad ("Ignoring attempt to re-define symbol");
419 ignore_rest_of_line ();
422 if (S_GET_VALUE (symbolP) != 0)
424 if (S_GET_VALUE (symbolP) != size)
426 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
427 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
433 S_SET_VALUE (symbolP, (valueT) size);
434 S_SET_EXTERNAL (symbolP);
437 know (symbolP->sy_frag == &zero_address_frag);
438 if (*input_line_pointer != ',')
440 as_bad ("Expected comma after common length");
441 ignore_rest_of_line ();
444 input_line_pointer++;
446 if (*input_line_pointer != '"')
448 temp = get_absolute_expression ();
450 if (temp > max_alignment)
452 temp = max_alignment;
453 as_warn ("Common alignment too large: %d. assumed", temp);
459 as_warn ("Common alignment negative; 0 assumed");
470 old_subsec = now_subseg;
472 record_alignment (bss_section, align);
473 subseg_set (bss_section, 0);
475 frag_align (align, 0);
476 if (S_GET_SEGMENT (symbolP) == bss_section)
477 symbolP->sy_frag->fr_symbol = 0;
478 symbolP->sy_frag = frag_now;
479 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
482 S_SET_SEGMENT (symbolP, bss_section);
483 S_CLEAR_EXTERNAL (symbolP);
484 subseg_set (old_sec, old_subsec);
490 S_SET_VALUE (symbolP, (valueT) size);
492 S_SET_ALIGN (symbolP, temp);
494 S_SET_EXTERNAL (symbolP);
495 /* should be common, but this is how gas does it for now */
496 S_SET_SEGMENT (symbolP, bfd_und_section_ptr);
501 input_line_pointer++;
502 /* @@ Some use the dot, some don't. Can we get some consistency?? */
503 if (*input_line_pointer == '.')
504 input_line_pointer++;
505 /* @@ Some say data, some say bss. */
506 if (strncmp (input_line_pointer, "bss\"", 4)
507 && strncmp (input_line_pointer, "data\"", 5))
509 while (*--input_line_pointer != '"')
511 input_line_pointer--;
512 goto bad_common_segment;
514 while (*input_line_pointer++ != '"')
516 goto allocate_common;
518 demand_empty_rest_of_line ();
523 p = input_line_pointer;
524 while (*p && *p != '\n')
528 as_bad ("bad .common segment %s", input_line_pointer + 1);
530 input_line_pointer = p;
531 ignore_rest_of_line ();
536 /* Handle the .empty pseudo-op. This supresses the warnings about
537 invalid delay slot usage. */
543 /* The easy way to implement is to just forget about the last
553 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
555 input_line_pointer += 6;
559 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
561 input_line_pointer += 6;
565 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
567 input_line_pointer += 7;
571 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
573 input_line_pointer += 5;
574 /* We only support 2 segments -- text and data -- for now, so
575 things in the "bss segment" will have to go into data for now.
576 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
577 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
580 as_bad ("Unknown segment type");
581 demand_empty_rest_of_line ();
587 subseg_set (data_section, 1);
588 demand_empty_rest_of_line ();
595 while (!is_end_of_line[(unsigned char) *input_line_pointer])
597 ++input_line_pointer;
599 ++input_line_pointer;
602 /* This static variable is set by s_uacons to tell sparc_cons_align
603 that the expession does not need to be aligned. */
605 static int sparc_no_align_cons = 0;
607 /* This handles the unaligned space allocation pseudo-ops, such as
608 .uaword. .uaword is just like .word, but the value does not need
615 /* Tell sparc_cons_align not to align this value. */
616 sparc_no_align_cons = 1;
620 /* If the --enforce-aligned-data option is used, we require .word,
621 et. al., to be aligned correctly. We do it by setting up an
622 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
623 no unexpected alignment was introduced.
625 The SunOS and Solaris native assemblers enforce aligned data by
626 default. We don't want to do that, because gcc can deliberately
627 generate misaligned data if the packed attribute is used. Instead,
628 we permit misaligned data by default, and permit the user to set an
629 option to check for it. */
632 sparc_cons_align (nbytes)
638 /* Only do this if we are enforcing aligned data. */
639 if (! enforce_aligned_data)
642 if (sparc_no_align_cons)
644 /* This is an unaligned pseudo-op. */
645 sparc_no_align_cons = 0;
650 while ((nbytes & 1) == 0)
659 if (now_seg == absolute_section)
661 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
662 as_bad ("misaligned data");
666 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
667 (symbolS *) NULL, (long) nalign, (char *) NULL);
669 record_alignment (now_seg, nalign);
672 /* This is where we do the unexpected alignment check. */
675 sparc_handle_align (fragp)
678 if (fragp->fr_type == rs_align_code
679 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
680 as_bad_where (fragp->fr_file, fragp->fr_line, "misaligned data");
683 /* sparc64 priviledged registers */
685 struct priv_reg_entry
691 struct priv_reg_entry priv_reg_table[] =
710 {"", -1}, /* end marker */
715 struct priv_reg_entry *p, *q;
717 return strcmp (q->name, p->name);
720 /* This function is called once, at assembler startup time. It should
721 set up all the tables, etc. that the MD part of the assembler will need. */
726 register const char *retval = NULL;
728 register unsigned int i = 0;
730 op_hash = hash_new ();
732 while (i < sparc_num_opcodes)
734 const char *name = sparc_opcodes[i].name;
735 retval = hash_insert (op_hash, name, &sparc_opcodes[i]);
738 fprintf (stderr, "internal error: can't hash `%s': %s\n",
739 sparc_opcodes[i].name, retval);
744 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
746 fprintf (stderr, "internal error: losing opcode: `%s' \"%s\"\n",
747 sparc_opcodes[i].name, sparc_opcodes[i].args);
752 while (i < sparc_num_opcodes
753 && !strcmp (sparc_opcodes[i].name, name));
757 as_fatal ("Broken assembler. No assembly attempted.");
759 for (i = '0'; i < '8'; ++i)
761 for (i = '0'; i <= '9'; ++i)
763 for (i = 'a'; i <= 'f'; ++i)
764 toHex[i] = i + 10 - 'a';
765 for (i = 'A'; i <= 'F'; ++i)
766 toHex[i] = i + 10 - 'A';
768 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
769 sizeof (priv_reg_table[0]), cmp_reg_entry);
771 /* If -bump, record the architecture level at which we start issuing
772 warnings. The behaviour is different depending upon whether an
773 architecture was explicitly specified. If it wasn't, we issue warnings
774 for all upwards bumps. If it was, we don't start issuing warnings until
775 we need to bump beyond the requested architecture or when we bump between
776 conflicting architectures. */
779 && architecture_requested)
781 /* `max_architecture' records the requested architecture.
782 Issue warnings if we go above it. */
783 warn_after_architecture = max_architecture;
785 /* Find the highest architecture level that doesn't conflict with
786 the requested one. */
787 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
788 max_architecture > warn_after_architecture;
790 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
791 warn_after_architecture))
796 /* Called after all assembly has been done. */
802 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
803 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
805 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
807 if (current_architecture == SPARC_OPCODE_ARCH_V9)
808 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
809 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
810 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
811 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
812 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
815 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
816 be but for now it is (since that's the way it's always been
818 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
823 /* Utility to output one insn. */
826 output_insn (insn, the_insn)
827 const struct sparc_opcode *insn;
828 struct sparc_it *the_insn;
830 char *toP = frag_more (4);
832 /* put out the opcode */
834 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
836 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
838 /* put out the symbol-dependent stuff */
839 if (the_insn->reloc != BFD_RELOC_NONE)
841 fix_new_exp (frag_now, /* which frag */
842 (toP - frag_now->fr_literal), /* where */
856 const struct sparc_opcode *insn;
860 sparc_ip (str, &insn);
862 /* We warn about attempts to put a floating point branch in a delay slot. */
865 && (insn->flags & F_FBR) != 0
866 && (last_insn->flags & F_DELAYED) != 0)
867 as_warn ("FP branch in delay slot");
869 /* SPARC before v9 requires a nop instruction between a floating
870 point instruction and a floating point branch. We insert one
871 automatically, with a warning. */
872 if (max_architecture < SPARC_OPCODE_ARCH_V9
875 && (insn->flags & F_FBR) != 0
876 && (last_insn->flags & F_FLOAT) != 0)
878 struct sparc_it nop_insn;
880 nop_insn.opcode = NOP_INSN;
881 nop_insn.reloc = BFD_RELOC_NONE;
882 output_insn (insn, &nop_insn);
883 as_warn ("FP branch preceded by FP instruction; NOP inserted");
886 switch (special_case)
890 output_insn (insn, &the_insn);
893 case SPECIAL_CASE_SET:
897 /* "set" is not defined for negative numbers in v9: it doesn't yield
898 what you expect it to. */
899 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
900 && the_insn.exp.X_op == O_constant)
902 if (the_insn.exp.X_add_number < 0)
903 as_warn ("set: used with negative number");
904 else if (the_insn.exp.X_add_number > 0xffffffff)
905 as_warn ("set: number larger than 4294967295");
908 /* See if operand is absolute and small; skip sethi if so. */
909 if (the_insn.exp.X_op != O_constant
910 || the_insn.exp.X_add_number >= (1 << 12)
911 || the_insn.exp.X_add_number < -(1 << 12))
913 output_insn (insn, &the_insn);
916 /* See if operand has no low-order bits; skip OR if so. */
917 if (the_insn.exp.X_op != O_constant
918 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
921 int rd = (the_insn.opcode & RD (~0)) >> 25;
922 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
925 | (the_insn.exp.X_add_number
926 & (need_hi22_p ? 0x3ff : 0x1fff)));
927 the_insn.reloc = (the_insn.exp.X_op != O_constant
930 output_insn (insn, &the_insn);
935 case SPECIAL_CASE_SETSW:
937 /* FIXME: Not finished. */
941 case SPECIAL_CASE_SETX:
943 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
944 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
945 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
947 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
948 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
949 /* Output directly to dst reg if lower 32 bits are all zero. */
950 int upper_dstreg = (the_insn.exp.X_op == O_constant
951 && lower32 == 0) ? dstreg : tmpreg;
952 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
954 /* The tmp reg should not be the dst reg. */
955 if (tmpreg == dstreg)
956 as_warn ("setx: temporary register same as destination register");
958 /* Reset X_add_number, we've extracted it as upper32/lower32.
959 Otherwise fixup_segment will complain about not being able to
960 write an 8 byte number in a 4 byte field. */
961 the_insn.exp.X_add_number = 0;
963 /* ??? Obviously there are other optimizations we can do
964 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
965 doing some of these. Later. If you do change things, try to
966 change all of this to be table driven as well. */
968 /* What to output depends on the number if it's constant.
969 Compute that first, then output what we've decided upon. */
970 if (the_insn.exp.X_op != O_constant)
971 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
974 /* Only need hh22 if `or' insn can't handle constant. */
975 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
978 /* Does bottom part (after sethi) have bits? */
979 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
980 /* No hh22, but does upper32 still have bits we can't set
984 && (upper32 != -1 || lower32 >= 0)))
987 /* If the lower half is all zero, we build the upper half directly
990 /* Need lower half if number is zero. */
991 || (! need_hh22_p && ! need_hm10_p))
993 /* No need for sethi if `or' insn can handle constant. */
994 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
995 /* Note that we can't use a negative constant in the `or'
996 insn unless the upper 32 bits are all ones. */
997 || (lower32 < 0 && upper32 != -1))
1000 /* Does bottom part (after sethi) have bits? */
1001 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1003 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1004 /* Need `or' if we didn't set anything else. */
1005 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1012 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1013 | ((upper32 >> 10) & 0x3fffff));
1014 the_insn.reloc = (the_insn.exp.X_op != O_constant
1015 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1016 output_insn (insn, &the_insn);
1021 the_insn.opcode = (OR_INSN
1022 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1026 & (need_hh22_p ? 0x3ff : 0x1fff)));
1027 the_insn.reloc = (the_insn.exp.X_op != O_constant
1028 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1029 output_insn (insn, &the_insn);
1034 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1035 | ((lower32 >> 10) & 0x3fffff));
1036 the_insn.reloc = BFD_RELOC_HI22;
1037 output_insn (insn, &the_insn);
1042 /* FIXME: One nice optimization to do here is to OR the low part
1043 with the highpart if hi22 isn't needed and the low part is
1045 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1049 & (need_hi22_p ? 0x3ff : 0x1fff)));
1050 the_insn.reloc = BFD_RELOC_LO10;
1051 output_insn (insn, &the_insn);
1054 /* If we needed to build the upper part, shift it into place. */
1055 if (need_hh22_p || need_hm10_p)
1057 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1059 the_insn.reloc = BFD_RELOC_NONE;
1060 output_insn (insn, &the_insn);
1063 /* If we needed to build both upper and lower parts, OR them together. */
1064 if ((need_hh22_p || need_hm10_p)
1065 && (need_hi22_p || need_lo10_p))
1067 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1069 the_insn.reloc = BFD_RELOC_NONE;
1070 output_insn (insn, &the_insn);
1072 /* We didn't need both regs, but we may have to sign extend lower32. */
1073 else if (need_hi22_p && upper32 == -1)
1075 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1077 the_insn.reloc = BFD_RELOC_NONE;
1078 output_insn (insn, &the_insn);
1083 case SPECIAL_CASE_FDIV:
1085 int rd = (the_insn.opcode >> 25) & 0x1f;
1087 output_insn (insn, &the_insn);
1089 /* According to information leaked from Sun, the "fdiv" instructions
1090 on early SPARC machines would produce incorrect results sometimes.
1091 The workaround is to add an fmovs of the destination register to
1092 itself just after the instruction. This was true on machines
1093 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1094 assert (the_insn.reloc == BFD_RELOC_NONE);
1095 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1096 output_insn (insn, &the_insn);
1101 as_fatal ("failed special case insn sanity check");
1105 /* Parse an argument that can be expressed as a keyword.
1106 (eg: #StoreStore or %ccfr).
1107 The result is a boolean indicating success.
1108 If successful, INPUT_POINTER is updated. */
1111 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
1112 int (*lookup_fn) ();
1113 char **input_pointerP;
1119 p = *input_pointerP;
1120 for (q = p + (*p == '#' || *p == '%'); isalpha (*q) || *q == '_'; ++q)
1124 value = (*lookup_fn) (p);
1129 *input_pointerP = q;
1133 /* Parse an argument that is a constant expression.
1134 The result is a boolean indicating success. */
1137 parse_const_expr_arg (input_pointerP, valueP)
1138 char **input_pointerP;
1141 char *save = input_line_pointer;
1144 input_line_pointer = *input_pointerP;
1145 /* The next expression may be something other than a constant
1146 (say if we're not processing the right variant of the insn).
1147 Don't call expression unless we're sure it will succeed as it will
1148 signal an error (which we want to defer until later). */
1149 /* FIXME: It might be better to define md_operand and have it recognize
1150 things like %asi, etc. but continuing that route through to the end
1151 is a lot of work. */
1152 if (*input_line_pointer == '%')
1154 input_line_pointer = save;
1158 *input_pointerP = input_line_pointer;
1159 input_line_pointer = save;
1160 if (exp.X_op != O_constant)
1162 *valueP = exp.X_add_number;
1167 sparc_ip (str, pinsn)
1169 const struct sparc_opcode **pinsn;
1171 char *error_message = "";
1175 const struct sparc_opcode *insn;
1177 unsigned long opcode;
1178 unsigned int mask = 0;
1181 long immediate_max = 0;
1184 for (s = str; islower (*s) || (*s >= '0' && *s <= '3'); ++s)
1202 as_fatal ("Unknown opcode: `%s'", str);
1204 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1208 as_bad ("Unknown opcode: `%s'", str);
1219 opcode = insn->match;
1220 memset (&the_insn, '\0', sizeof (the_insn));
1221 the_insn.reloc = BFD_RELOC_NONE;
1225 * Build the opcode, checking as we go to make
1226 * sure that the operands match
1228 for (args = insn->args;; ++args)
1236 /* Parse a series of masks. */
1243 if (! parse_keyword_arg (sparc_encode_membar, &s,
1246 error_message = ": invalid membar mask name";
1250 while (*s == ' ') { ++s; continue; }
1251 if (*s == '|' || *s == '+')
1253 while (*s == ' ') { ++s; continue; }
1258 if (! parse_const_expr_arg (&s, &kmask))
1260 error_message = ": invalid membar mask expression";
1263 if (kmask < 0 || kmask > 127)
1265 error_message = ": invalid membar mask number";
1270 opcode |= MEMBAR (kmask);
1278 /* Parse a prefetch function. */
1281 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1283 error_message = ": invalid prefetch function name";
1289 if (! parse_const_expr_arg (&s, &fcn))
1291 error_message = ": invalid prefetch function expression";
1294 if (fcn < 0 || fcn > 31)
1296 error_message = ": invalid prefetch function number";
1306 /* Parse a sparc64 privileged register. */
1309 struct priv_reg_entry *p = priv_reg_table;
1310 unsigned int len = 9999999; /* init to make gcc happy */
1313 while (p->name[0] > s[0])
1315 while (p->name[0] == s[0])
1317 len = strlen (p->name);
1318 if (strncmp (p->name, s, len) == 0)
1322 if (p->name[0] != s[0])
1324 error_message = ": unrecognizable privileged register";
1328 opcode |= (p->regnum << 14);
1330 opcode |= (p->regnum << 25);
1336 error_message = ": unrecognizable privileged register";
1342 if (strncmp (s, "%asr", 4) == 0)
1350 while (isdigit (*s))
1352 num = num * 10 + *s - '0';
1356 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1358 if (num < 16 || 31 < num)
1360 error_message = ": asr number must be between 16 and 31";
1366 if (num < 0 || 31 < num)
1368 error_message = ": asr number must be between 0 and 31";
1373 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1378 error_message = ": expecting %asrN";
1385 the_insn.reloc = BFD_RELOC_SPARC_11;
1386 immediate_max = 0x03FF;
1390 the_insn.reloc = BFD_RELOC_SPARC_10;
1391 immediate_max = 0x01FF;
1395 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1396 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1397 the_insn.reloc = BFD_RELOC_SPARC_5;
1399 the_insn.reloc = BFD_RELOC_SPARC13;
1400 /* These fields are unsigned, but for upward compatibility,
1401 allow negative values as well. */
1402 immediate_max = 0x1f;
1406 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1407 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1408 the_insn.reloc = BFD_RELOC_SPARC_6;
1410 the_insn.reloc = BFD_RELOC_SPARC13;
1411 /* These fields are unsigned, but for upward compatibility,
1412 allow negative values as well. */
1413 immediate_max = 0x3f;
1417 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1422 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1427 if (*s == 'p' && s[1] == 'n')
1435 if (*s == 'p' && s[1] == 't')
1447 if (strncmp (s, "%icc", 4) == 0)
1459 if (strncmp (s, "%xcc", 4) == 0)
1471 if (strncmp (s, "%fcc0", 5) == 0)
1483 if (strncmp (s, "%fcc1", 5) == 0)
1495 if (strncmp (s, "%fcc2", 5) == 0)
1507 if (strncmp (s, "%fcc3", 5) == 0)
1515 if (strncmp (s, "%pc", 3) == 0)
1523 if (strncmp (s, "%tick", 5) == 0)
1530 case '\0': /* end of args */
1549 case '[': /* these must match exactly */
1557 case '#': /* must be at least one digit */
1560 while (isdigit (*s))
1568 case 'C': /* coprocessor state register */
1569 if (strncmp (s, "%csr", 4) == 0)
1576 case 'b': /* next operand is a coprocessor register */
1579 if (*s++ == '%' && *s++ == 'c' && isdigit (*s))
1584 mask = 10 * (mask - '0') + (*s++ - '0');
1598 opcode |= mask << 14;
1606 opcode |= mask << 25;
1612 case 'r': /* next operand must be a register */
1622 case 'f': /* frame pointer */
1630 case 'g': /* global register */
1631 if (isoctal (c = *s++))
1638 case 'i': /* in register */
1639 if (isoctal (c = *s++))
1641 mask = c - '0' + 24;
1646 case 'l': /* local register */
1647 if (isoctal (c = *s++))
1649 mask = (c - '0' + 16);
1654 case 'o': /* out register */
1655 if (isoctal (c = *s++))
1657 mask = (c - '0' + 8);
1662 case 's': /* stack pointer */
1670 case 'r': /* any register */
1671 if (!isdigit (c = *s++))
1688 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1704 /* Got the register, now figure out where
1705 it goes in the opcode. */
1709 opcode |= mask << 14;
1717 opcode |= mask << 25;
1721 opcode |= (mask << 25) | (mask << 14);
1725 opcode |= (mask << 25) | (mask << 0);
1731 case 'e': /* next operand is a floating point register */
1746 && ((format = *s) == 'f')
1749 for (mask = 0; isdigit (*s); ++s)
1751 mask = 10 * mask + (*s - '0');
1752 } /* read the number */
1760 } /* register must be even numbered */
1768 } /* register must be multiple of 4 */
1772 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1773 error_message = ": There are only 64 f registers; [0-63]";
1775 error_message = ": There are only 32 f registers; [0-31]";
1778 else if (mask >= 32)
1780 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1783 mask -= 31; /* wrap high bit */
1787 error_message = ": There are only 32 f registers; [0-31]";
1795 } /* if not an 'f' register. */
1802 opcode |= RS1 (mask);
1809 opcode |= RS2 (mask);
1815 opcode |= RD (mask);
1824 if (strncmp (s, "%fsr", 4) == 0)
1831 case '0': /* 64 bit immediate (setx insn) */
1832 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1835 case 'h': /* high 22 bits */
1836 the_insn.reloc = BFD_RELOC_HI22;
1839 case 'l': /* 22 bit PC relative immediate */
1840 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
1844 case 'L': /* 30 bit immediate */
1845 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
1849 case 'n': /* 22 bit immediate */
1850 the_insn.reloc = BFD_RELOC_SPARC22;
1853 case 'i': /* 13 bit immediate */
1854 the_insn.reloc = BFD_RELOC_SPARC13;
1855 immediate_max = 0x0FFF;
1864 if ((c = s[1]) == 'h' && s[2] == 'i')
1866 the_insn.reloc = BFD_RELOC_HI22;
1869 else if (c == 'l' && s[2] == 'o')
1871 the_insn.reloc = BFD_RELOC_LO10;
1878 the_insn.reloc = BFD_RELOC_SPARC_HH22;
1886 the_insn.reloc = BFD_RELOC_SPARC_HM10;
1893 /* Note that if the getExpression() fails, we will still
1894 have created U entries in the symbol table for the
1895 'symbols' in the input string. Try not to create U
1896 symbols for registers, etc. */
1898 /* This stuff checks to see if the expression ends in
1899 +%reg. If it does, it removes the register from
1900 the expression, and re-sets 's' to point to the
1905 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
1907 if (s1 != s && isdigit (s1[-1]))
1909 if (s1[-2] == '%' && s1[-3] == '+')
1913 (void) getExpression (s);
1918 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1922 (void) getExpression (s);
1929 (void) getExpression (s);
1932 if (the_insn.exp.X_op == O_constant
1933 && the_insn.exp.X_add_symbol == 0
1934 && the_insn.exp.X_op_symbol == 0)
1936 /* Handle %uhi/%ulo by moving the upper word to the lower
1937 one and pretending it's %hi/%lo. We also need to watch
1938 for %hi/%lo: the top word needs to be zeroed otherwise
1939 fixup_segment will complain the value is too big. */
1940 switch (the_insn.reloc)
1942 case BFD_RELOC_SPARC_HH22:
1943 the_insn.reloc = BFD_RELOC_HI22;
1944 the_insn.exp.X_add_number = BSR (the_insn.exp.X_add_number, 32);
1946 case BFD_RELOC_SPARC_HM10:
1947 the_insn.reloc = BFD_RELOC_LO10;
1948 the_insn.exp.X_add_number = BSR (the_insn.exp.X_add_number, 32);
1950 case BFD_RELOC_HI22:
1951 case BFD_RELOC_LO10:
1952 the_insn.exp.X_add_number &= 0xffffffff;
1958 /* For pc-relative call instructions, we reject
1959 constants to get better code. */
1961 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
1962 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)
1965 error_message = ": PC-relative operand can't be a constant";
1968 /* Check for invalid constant values. Don't warn if
1969 constant was inside %hi or %lo, since these
1970 truncate the constant to fit. */
1971 if (immediate_max != 0
1972 && the_insn.reloc != BFD_RELOC_LO10
1973 && the_insn.reloc != BFD_RELOC_HI22
1974 && !in_signed_range (the_insn.exp.X_add_number,
1979 /* Who knows? After relocation, we may be within
1980 range. Let the linker figure it out. */
1982 the_insn.exp.X_op = O_symbol;
1983 the_insn.exp.X_add_symbol = section_symbol (absolute_section);
1986 /* Immediate value is non-pcrel, and out of
1988 as_bad ("constant value %ld out of range (%ld .. %ld)",
1989 the_insn.exp.X_add_number,
1990 ~immediate_max, immediate_max);
1994 /* Reset to prevent extraneous range check. */
2014 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2016 error_message = ": invalid ASI name";
2022 if (! parse_const_expr_arg (&s, &asi))
2024 error_message = ": invalid ASI expression";
2027 if (asi < 0 || asi > 255)
2029 error_message = ": invalid ASI number";
2033 opcode |= ASI (asi);
2035 } /* alternate space */
2038 if (strncmp (s, "%psr", 4) == 0)
2045 case 'q': /* floating point queue */
2046 if (strncmp (s, "%fq", 3) == 0)
2053 case 'Q': /* coprocessor queue */
2054 if (strncmp (s, "%cq", 3) == 0)
2062 if (strcmp (str, "set") == 0
2063 || strcmp (str, "setuw") == 0)
2065 special_case = SPECIAL_CASE_SET;
2068 else if (strcmp (str, "setsw") == 0)
2070 special_case = SPECIAL_CASE_SETSW;
2073 else if (strcmp (str, "setx") == 0)
2075 special_case = SPECIAL_CASE_SETX;
2078 else if (strncmp (str, "fdiv", 4) == 0)
2080 special_case = SPECIAL_CASE_FDIV;
2086 if (strncmp (s, "%asi", 4) != 0)
2092 if (strncmp (s, "%fprs", 5) != 0)
2098 if (strncmp (s, "%ccr", 4) != 0)
2104 if (strncmp (s, "%tbr", 4) != 0)
2110 if (strncmp (s, "%wim", 4) != 0)
2117 char *push = input_line_pointer;
2120 input_line_pointer = s;
2122 if (e.X_op == O_constant)
2124 int n = e.X_add_number;
2125 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2126 as_bad ("OPF immediate operand out of range (0-0x1ff)");
2128 opcode |= e.X_add_number << 5;
2131 as_bad ("non-immediate OPF operand, ignored");
2132 s = input_line_pointer;
2133 input_line_pointer = push;
2138 if (strncmp (s, "%y", 2) != 0)
2146 /* Parse a sparclet cpreg. */
2148 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2150 error_message = ": invalid cpreg name";
2153 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2158 as_fatal ("failed sanity check.");
2159 } /* switch on arg code */
2161 /* Break out of for() loop. */
2163 } /* for each arg that we expect */
2168 /* Args don't match. */
2169 if (((unsigned) (&insn[1] - sparc_opcodes)) < sparc_num_opcodes
2170 && (insn->name == insn[1].name
2171 || !strcmp (insn->name, insn[1].name)))
2179 as_bad ("Illegal operands%s", error_message);
2185 /* We have a match. Now see if the architecture is ok. */
2186 int needed_arch_mask = insn->architecture;
2190 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2191 | (1 << SPARC_OPCODE_ARCH_V9A));
2192 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2195 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2197 /* Can we bump up the architecture? */
2198 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2200 enum sparc_opcode_arch_val needed_architecture =
2201 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2202 & needed_arch_mask);
2204 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2206 && needed_architecture > warn_after_architecture)
2208 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2209 sparc_opcode_archs[current_architecture].name,
2210 sparc_opcode_archs[needed_architecture].name,
2212 warn_after_architecture = needed_architecture;
2214 current_architecture = needed_architecture;
2217 /* ??? This seems to be a bit fragile. What if the next entry in
2218 the opcode table is the one we want and it is supported?
2219 It is possible to arrange the table today so that this can't
2220 happen but what about tomorrow? */
2223 int arch,printed_one_p = 0;
2225 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2227 /* Create a list of the architectures that support the insn. */
2228 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2230 arch = sparc_ffs (needed_arch_mask);
2231 while ((1 << arch) <= needed_arch_mask)
2233 if ((1 << arch) & needed_arch_mask)
2237 strcpy (p, sparc_opcode_archs[arch].name);
2244 as_bad ("Architecture mismatch on \"%s\".", str);
2245 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2247 sparc_opcode_archs[max_architecture].name);
2253 } /* forever looking for a match */
2255 the_insn.opcode = opcode;
2265 save_in = input_line_pointer;
2266 input_line_pointer = str;
2267 seg = expression (&the_insn.exp);
2268 if (seg != absolute_section
2269 && seg != text_section
2270 && seg != data_section
2271 && seg != bss_section
2272 && seg != undefined_section)
2274 the_insn.error = "bad segment";
2275 expr_end = input_line_pointer;
2276 input_line_pointer = save_in;
2279 expr_end = input_line_pointer;
2280 input_line_pointer = save_in;
2282 } /* getExpression() */
2286 This is identical to the md_atof in m68k.c. I think this is right,
2289 Turn a string in input_line_pointer into a floating point constant of type
2290 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2291 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2294 /* Equal to MAX_PRECISION in atof-ieee.c */
2295 #define MAX_LITTLENUMS 6
2298 md_atof (type, litP, sizeP)
2304 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2336 return "Bad call to MD_ATOF()";
2339 t = atof_ieee (input_line_pointer, type, words);
2341 input_line_pointer = t;
2342 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2344 if (target_big_endian)
2346 for (i = 0; i < prec; i++)
2348 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2349 litP += sizeof (LITTLENUM_TYPE);
2354 for (i = prec - 1; i >= 0; i--)
2356 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2357 litP += sizeof (LITTLENUM_TYPE);
2364 /* Write a value out to the object file, using the appropriate
2368 md_number_to_chars (buf, val, n)
2373 if (target_big_endian)
2374 number_to_chars_bigendian (buf, val, n);
2376 number_to_chars_littleendian (buf, val, n);
2379 /* Apply a fixS to the frags, now that we know the value it ought to
2383 md_apply_fix3 (fixP, value, segment)
2388 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2394 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2396 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2399 /* FIXME: SPARC ELF relocations don't use an addend in the data
2400 field itself. This whole approach should be somehow combined
2401 with the calls to bfd_perform_relocation. Also, the value passed
2402 in by fixup_segment includes the value of a defined symbol. We
2403 don't want to include the value of an externally visible symbol. */
2404 if (fixP->fx_addsy != NULL)
2406 if (fixP->fx_addsy->sy_used_in_reloc
2407 && (S_IS_EXTERNAL (fixP->fx_addsy)
2408 || S_IS_WEAK (fixP->fx_addsy)
2409 || (sparc_pic_code && ! fixP->fx_pcrel)
2410 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2411 && ((bfd_get_section_flags (stdoutput,
2412 S_GET_SEGMENT (fixP->fx_addsy))
2413 & SEC_LINK_ONCE) != 0
2414 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2416 sizeof ".gnu.linkonce" - 1) == 0)))
2417 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2418 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2419 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2420 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2425 /* This is a hack. There should be a better way to
2426 handle this. Probably in terms of howto fields, once
2427 we can look at these fixups in terms of howtos. */
2428 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2429 val += fixP->fx_where + fixP->fx_frag->fr_address;
2432 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2433 generate a reloc, then we just want to let the reloc addend set
2434 the value. We do not want to also stuff the addend into the
2435 object file. Including the addend in the object file works when
2436 doing a static link, because the linker will ignore the object
2437 file contents. However, the dynamic linker does not ignore the
2438 object file contents. */
2439 if (fixP->fx_addsy != NULL
2440 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2443 /* When generating PIC code, we do not want an addend for a reloc
2444 against a local symbol. We adjust fx_addnumber to cancel out the
2445 value already included in val, and to also cancel out the
2446 adjustment which bfd_install_relocation will create. */
2448 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2449 && fixP->fx_addsy != NULL
2450 && ! S_IS_COMMON (fixP->fx_addsy)
2451 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2452 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2455 /* If this is a data relocation, just output VAL. */
2457 if (fixP->fx_r_type == BFD_RELOC_16)
2459 md_number_to_chars (buf, val, 2);
2461 else if (fixP->fx_r_type == BFD_RELOC_32)
2463 md_number_to_chars (buf, val, 4);
2465 else if (fixP->fx_r_type == BFD_RELOC_64)
2467 md_number_to_chars (buf, val, 8);
2471 /* It's a relocation against an instruction. */
2473 if (INSN_BIG_ENDIAN)
2474 insn = bfd_getb32 ((unsigned char *) buf);
2476 insn = bfd_getl32 ((unsigned char *) buf);
2478 switch (fixP->fx_r_type)
2480 case BFD_RELOC_32_PCREL_S2:
2482 /* FIXME: This increment-by-one deserves a comment of why it's
2484 if (! sparc_pic_code
2485 || fixP->fx_addsy == NULL
2486 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2488 insn |= val & 0x3fffffff;
2491 case BFD_RELOC_SPARC_11:
2492 if (! in_signed_range (val, 0x7ff))
2493 as_bad ("relocation overflow.");
2494 insn |= val & 0x7ff;
2497 case BFD_RELOC_SPARC_10:
2498 if (! in_signed_range (val, 0x3ff))
2499 as_bad ("relocation overflow.");
2500 insn |= val & 0x3ff;
2503 case BFD_RELOC_SPARC_6:
2504 if (! in_bitfield_range (val, 0x3f))
2505 as_bad ("relocation overflow.");
2509 case BFD_RELOC_SPARC_5:
2510 if (! in_bitfield_range (val, 0x1f))
2511 as_bad ("relocation overflow.");
2515 case BFD_RELOC_SPARC_WDISP16:
2516 /* FIXME: simplify */
2517 if (((val > 0) && (val & ~0x3fffc))
2518 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2519 as_bad ("relocation overflow.");
2520 /* FIXME: The +1 deserves a comment. */
2521 val = (val >> 2) + 1;
2522 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2525 case BFD_RELOC_SPARC_WDISP19:
2526 /* FIXME: simplify */
2527 if (((val > 0) && (val & ~0x1ffffc))
2528 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2529 as_bad ("relocation overflow.");
2530 /* FIXME: The +1 deserves a comment. */
2531 val = (val >> 2) + 1;
2532 insn |= val & 0x7ffff;
2535 case BFD_RELOC_SPARC_HH22:
2536 val = BSR (val, 32);
2537 /* intentional fallthrough */
2539 case BFD_RELOC_SPARC_LM22:
2540 case BFD_RELOC_HI22:
2541 if (!fixP->fx_addsy)
2543 insn |= (val >> 10) & 0x3fffff;
2547 /* FIXME: Need comment explaining why we do this. */
2552 case BFD_RELOC_SPARC22:
2553 if (val & ~0x003fffff)
2554 as_bad ("relocation overflow");
2555 insn |= (val & 0x3fffff);
2558 case BFD_RELOC_SPARC_HM10:
2559 val = BSR (val, 32);
2560 /* intentional fallthrough */
2562 case BFD_RELOC_LO10:
2563 if (!fixP->fx_addsy)
2565 insn |= val & 0x3ff;
2569 /* FIXME: Need comment explaining why we do this. */
2574 case BFD_RELOC_SPARC13:
2575 if (! in_signed_range (val, 0x1fff))
2576 as_bad ("relocation overflow");
2577 insn |= val & 0x1fff;
2580 case BFD_RELOC_SPARC_WDISP22:
2581 val = (val >> 2) + 1;
2583 case BFD_RELOC_SPARC_BASE22:
2584 insn |= val & 0x3fffff;
2587 case BFD_RELOC_NONE:
2589 as_bad ("bad or unhandled relocation type: 0x%02x", fixP->fx_r_type);
2593 if (INSN_BIG_ENDIAN)
2594 bfd_putb32 (insn, (unsigned char *) buf);
2596 bfd_putl32 (insn, (unsigned char *) buf);
2599 /* Are we finished with this relocation now? */
2600 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2606 /* Translate internal representation of relocation info to BFD target
2609 tc_gen_reloc (section, fixp)
2614 bfd_reloc_code_real_type code;
2616 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
2617 assert (reloc != 0);
2619 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2620 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2622 switch (fixp->fx_r_type)
2626 case BFD_RELOC_HI22:
2627 case BFD_RELOC_LO10:
2628 case BFD_RELOC_32_PCREL_S2:
2629 case BFD_RELOC_SPARC13:
2630 case BFD_RELOC_SPARC_BASE13:
2631 case BFD_RELOC_SPARC_WDISP16:
2632 case BFD_RELOC_SPARC_WDISP19:
2633 case BFD_RELOC_SPARC_WDISP22:
2635 case BFD_RELOC_SPARC_5:
2636 case BFD_RELOC_SPARC_6:
2637 case BFD_RELOC_SPARC_10:
2638 case BFD_RELOC_SPARC_11:
2639 case BFD_RELOC_SPARC_HH22:
2640 case BFD_RELOC_SPARC_HM10:
2641 case BFD_RELOC_SPARC_LM22:
2642 case BFD_RELOC_SPARC_PC_HH22:
2643 case BFD_RELOC_SPARC_PC_HM10:
2644 case BFD_RELOC_SPARC_PC_LM22:
2645 code = fixp->fx_r_type;
2651 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2652 /* If we are generating PIC code, we need to generate a different
2656 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2658 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2665 case BFD_RELOC_32_PCREL_S2:
2666 if (! S_IS_DEFINED (fixp->fx_addsy)
2667 || S_IS_EXTERNAL (fixp->fx_addsy)
2668 || S_IS_WEAK (fixp->fx_addsy))
2669 code = BFD_RELOC_SPARC_WPLT30;
2671 case BFD_RELOC_HI22:
2672 if (fixp->fx_addsy != NULL
2673 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2674 code = BFD_RELOC_SPARC_PC22;
2676 code = BFD_RELOC_SPARC_GOT22;
2678 case BFD_RELOC_LO10:
2679 if (fixp->fx_addsy != NULL
2680 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2681 code = BFD_RELOC_SPARC_PC10;
2683 code = BFD_RELOC_SPARC_GOT10;
2685 case BFD_RELOC_SPARC13:
2686 code = BFD_RELOC_SPARC_GOT13;
2692 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2694 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2695 if (reloc->howto == 0)
2697 as_bad_where (fixp->fx_file, fixp->fx_line,
2698 "internal error: can't export reloc type %d (`%s')",
2699 fixp->fx_r_type, bfd_get_reloc_code_name (code));
2703 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2706 if (reloc->howto->pc_relative == 0
2707 || code == BFD_RELOC_SPARC_PC10
2708 || code == BFD_RELOC_SPARC_PC22)
2709 reloc->addend = fixp->fx_addnumber;
2711 reloc->addend = fixp->fx_offset - reloc->address;
2713 #else /* elf or coff */
2715 if (reloc->howto->pc_relative == 0
2716 || code == BFD_RELOC_SPARC_PC10
2717 || code == BFD_RELOC_SPARC_PC22)
2718 reloc->addend = fixp->fx_addnumber;
2719 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2720 reloc->addend = (section->vma
2721 + fixp->fx_addnumber
2722 + md_pcrel_from (fixp));
2724 reloc->addend = fixp->fx_offset;
2732 /* for debugging only */
2735 struct sparc_it *insn;
2737 const char *const Reloc[] = {
2766 fprintf (stderr, "ERROR: %s\n");
2767 fprintf (stderr, "opcode=0x%08x\n", insn->opcode);
2768 fprintf (stderr, "reloc = %s\n", Reloc[insn->reloc]);
2769 fprintf (stderr, "exp = {\n");
2770 fprintf (stderr, "\t\tX_add_symbol = %s\n",
2771 ((insn->exp.X_add_symbol != NULL)
2772 ? ((S_GET_NAME (insn->exp.X_add_symbol) != NULL)
2773 ? S_GET_NAME (insn->exp.X_add_symbol)
2776 fprintf (stderr, "\t\tX_sub_symbol = %s\n",
2777 ((insn->exp.X_op_symbol != NULL)
2778 ? (S_GET_NAME (insn->exp.X_op_symbol)
2779 ? S_GET_NAME (insn->exp.X_op_symbol)
2782 fprintf (stderr, "\t\tX_add_number = %d\n",
2783 insn->exp.X_add_number);
2784 fprintf (stderr, "}\n");
2790 * Invocation line includes a switch not recognized by the base assembler.
2791 * See if it's a processor-specific option. These are:
2794 * Warn on architecture bumps. See also -A.
2796 * -Av6, -Av7, -Av8, -Av9, -Av9a, -Asparclite
2797 * -xarch=v8plus, -xarch=v8plusa
2798 * Select the architecture. Instructions or features not
2799 * supported by the selected architecture cause fatal errors.
2801 * The default is to start at v6, and bump the architecture up
2802 * whenever an instruction is seen at a higher level. If 32 bit
2803 * environments, v9 is not bumped up to, the user must pass -Av9.
2805 * -xarch=v8plus{,a} is for compatibility with the Sun assembler.
2807 * If -bump is specified, a warning is printing when bumping to
2810 * If an architecture is specified, all instructions must match
2811 * that architecture. Any higher level instructions are flagged
2812 * as errors. Note that in the 32 bit environment specifying
2813 * -Av9 does not automatically create a v9 object file, a v9
2814 * insn must be seen.
2816 * If both an architecture and -bump are specified, the
2817 * architecture starts at the specified level, but bumps are
2818 * warnings. Note that we can't set `current_architecture' to
2819 * the requested level in this case: in the 32 bit environment,
2820 * we still must avoid creating v9 object files unless v9 insns
2824 * Bumping between incompatible architectures is always an
2825 * error. For example, from sparclite to v9.
2829 CONST char *md_shortopts = "A:K:VQ:sq";
2832 CONST char *md_shortopts = "A:k";
2834 CONST char *md_shortopts = "A:";
2837 struct option md_longopts[] = {
2838 #define OPTION_BUMP (OPTION_MD_BASE)
2839 {"bump", no_argument, NULL, OPTION_BUMP},
2840 #define OPTION_SPARC (OPTION_MD_BASE + 1)
2841 {"sparc", no_argument, NULL, OPTION_SPARC},
2842 #define OPTION_XARCH (OPTION_MD_BASE + 2)
2843 {"xarch", required_argument, NULL, OPTION_XARCH},
2844 #ifdef SPARC_BIENDIAN
2845 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
2846 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
2847 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
2848 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
2850 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
2851 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
2852 {NULL, no_argument, NULL, 0}
2854 size_t md_longopts_size = sizeof(md_longopts);
2857 md_parse_option (c, arg)
2865 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
2869 /* ??? We could add v8plus and v8plusa to sparc_opcode_archs.
2870 But we might want v8plus to mean something different than v9
2871 someday, and we'd recognize more -xarch options than Sun's
2872 assembler does (which may lead to a conflict someday). */
2873 if (strcmp (arg, "v8plus") == 0)
2875 else if (strcmp (arg, "v8plusa") == 0)
2879 as_bad ("invalid architecture -xarch=%s", arg);
2887 enum sparc_opcode_arch_val new_arch = sparc_opcode_lookup_arch (arg);
2889 if (new_arch == SPARC_OPCODE_ARCH_BAD)
2891 as_bad ("invalid architecture -A%s", arg);
2896 max_architecture = new_arch;
2897 architecture_requested = 1;
2903 /* Ignore -sparc, used by SunOS make default .s.o rule. */
2906 case OPTION_ENFORCE_ALIGNED_DATA:
2907 enforce_aligned_data = 1;
2910 #ifdef SPARC_BIENDIAN
2911 case OPTION_LITTLE_ENDIAN:
2912 target_big_endian = 0;
2914 case OPTION_BIG_ENDIAN:
2915 target_big_endian = 1;
2927 print_version_id ();
2931 /* Qy - do emit .comment
2932 Qn - do not emit .comment */
2936 /* use .stab instead of .stab.excl */
2940 /* quick -- native assembler does fewer checks */
2944 if (strcmp (arg, "PIC") != 0)
2945 as_warn ("Unrecognized option following -K");
2959 md_show_usage (stream)
2962 const struct sparc_opcode_arch *arch;
2964 fprintf(stream, "SPARC options:\n");
2965 for (arch = &sparc_opcode_archs[0]; arch->name; arch++)
2967 if (arch != &sparc_opcode_archs[0])
2968 fprintf (stream, " | ");
2969 fprintf (stream, "-A%s", arch->name);
2971 fprintf (stream, "\n-xarch=v8plus | -xarch=v8plusa\n");
2973 specify variant of SPARC architecture\n\
2974 -bump warn when assembler switches architectures\n\
2976 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
2979 -k generate PIC\n");
2983 -KPIC generate PIC\n\
2984 -V print assembler version number\n\
2989 #ifdef SPARC_BIENDIAN
2991 -EL generate code for a little endian machine\n\
2992 -EB generate code for a big endian machine\n");
2996 /* We have no need to default values of symbols. */
3000 md_undefined_symbol (name)
3004 } /* md_undefined_symbol() */
3006 /* Round up a section size to the appropriate boundary. */
3008 md_section_align (segment, size)
3013 /* This is not right for ELF; a.out wants it, and COFF will force
3014 the alignment anyways. */
3015 valueT align = ((valueT) 1
3016 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3018 /* turn alignment value into a mask */
3020 newsize = (size + align) & ~align;
3027 /* Exactly what point is a PC-relative offset relative TO?
3028 On the sparc, they're relative to the address of the offset, plus
3029 its size. This gets us to the following instruction.
3030 (??? Is this right? FIXME-SOON) */
3032 md_pcrel_from (fixP)
3037 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3038 if (! sparc_pic_code
3039 || fixP->fx_addsy == NULL
3040 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
3041 ret += fixP->fx_size;
3045 /* end of tc-sparc.c */