1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static struct sparc_arch *lookup_arch PARAMS ((char *));
41 static void init_default_arch PARAMS ((void));
42 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
43 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
44 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
45 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46 static int sparc_ffs PARAMS ((unsigned int));
47 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
48 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
49 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
50 static bfd_vma BSR PARAMS ((bfd_vma, int));
51 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
52 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
53 static int parse_const_expr_arg PARAMS ((char **, int *));
54 static int get_expression PARAMS ((char *str));
56 /* Default architecture. */
57 /* ??? The default value should be V8, but sparclite support was added
58 by making it the default. GCC now passes -Asparclite, so maybe sometime in
59 the future we can set this to V8. */
61 #define DEFAULT_ARCH "sparclite"
63 static char *default_arch = DEFAULT_ARCH;
65 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 static int default_init_p;
69 /* Current architecture. We don't bump up unless necessary. */
70 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
72 /* The maximum architecture level we can bump up to.
73 In a 32 bit environment, don't allow bumping up to v9 by default.
74 The native assembler works this way. The user is required to pass
75 an explicit argument before we'll create v9 object files. However, if
76 we don't see any v9 insns, a v8plus object file is not created. */
77 static enum sparc_opcode_arch_val max_architecture;
79 /* Either 32 or 64, selects file format. */
80 static int sparc_arch_size;
81 /* Initial (default) value, recorded separately in case a user option
82 changes the value before md_show_usage is called. */
83 static int default_arch_size;
86 /* The currently selected v9 memory model. Currently only used for
88 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
91 static int architecture_requested;
92 static int warn_on_bump;
94 /* If warn_on_bump and the needed architecture is higher than this
95 architecture, issue a warning. */
96 static enum sparc_opcode_arch_val warn_after_architecture;
98 /* Non-zero if as should generate error if an undeclared g[23] register
99 has been used in -64. */
100 static int no_undeclared_regs;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data;
111 extern int target_big_endian;
113 static int target_little_endian_data;
115 /* Symbols for global registers on v9. */
116 static symbolS *globals[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control *op_hash;
134 static int mylog2 PARAMS ((int));
135 static void s_data1 PARAMS ((void));
136 static void s_seg PARAMS ((int));
137 static void s_proc PARAMS ((int));
138 static void s_reserve PARAMS ((int));
139 static void s_common PARAMS ((int));
140 static void s_empty PARAMS ((int));
141 static void s_uacons PARAMS ((int));
142 static void s_ncons PARAMS ((int));
144 static void s_register PARAMS ((int));
147 const pseudo_typeS md_pseudo_table[] =
149 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common, 0},
151 {"empty", s_empty, 0},
152 {"global", s_globl, 0},
154 {"nword", s_ncons, 0},
155 {"optim", s_ignore, 0},
157 {"reserve", s_reserve, 0},
159 {"skip", s_space, 0},
162 {"uahalf", s_uacons, 2},
163 {"uaword", s_uacons, 4},
164 {"uaxword", s_uacons, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
170 {"register", s_register, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode;
211 struct nlist *nlistp;
215 bfd_reloc_code_real_type reloc;
218 struct sparc_it the_insn, set_insn;
220 static void output_insn
221 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
223 /* Table of arguments to -A.
224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225 for this use. That table is for opcodes only. This table is for opcodes
228 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
229 v8plusa, v9, v9a, v9b, v9_64};
231 static struct sparc_arch {
234 enum sparc_arch_types arch_type;
235 /* Default word size, as specified during configuration.
236 A value of zero means can't be used to specify default architecture. */
237 int default_arch_size;
238 /* Allowable arg to -A? */
240 } sparc_arch_table[] = {
241 { "v6", "v6", v6, 0, 1 },
242 { "v7", "v7", v7, 0, 1 },
243 { "v8", "v8", v8, 32, 1 },
244 { "sparclet", "sparclet", sparclet, 32, 1 },
245 { "sparclite", "sparclite", sparclite, 32, 1 },
246 { "sparc86x", "sparclite", sparc86x, 32, 1 },
247 { "v8plus", "v9", v9, 0, 1 },
248 { "v8plusa", "v9a", v9, 0, 1 },
249 { "v8plusb", "v9b", v9, 0, 1 },
250 { "v9", "v9", v9, 0, 1 },
251 { "v9a", "v9a", v9, 0, 1 },
252 { "v9b", "v9b", v9, 0, 1 },
253 /* This exists to allow configure.in/Makefile.in to pass one
254 value to specify both the default machine and default word size. */
255 { "v9-64", "v9", v9, 64, 0 },
256 { NULL, NULL, v8, 0, 0 }
259 /* Variant of default_arch */
260 static enum sparc_arch_types default_arch_type;
262 static struct sparc_arch *
266 struct sparc_arch *sa;
268 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
269 if (strcmp (sa->name, name) == 0)
271 if (sa->name == NULL)
276 /* Initialize the default opcode arch and word size from the default
277 architecture name. */
282 struct sparc_arch *sa = lookup_arch (default_arch);
285 || sa->default_arch_size == 0)
286 as_fatal (_("Invalid default architecture, broken assembler."));
288 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
289 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
290 as_fatal (_("Bad opcode table, broken assembler."));
291 default_arch_size = sparc_arch_size = sa->default_arch_size;
293 default_arch_type = sa->arch_type;
296 /* Called by TARGET_FORMAT. */
299 sparc_target_format ()
301 /* We don't get a chance to initialize anything before we're called,
302 so handle that now. */
303 if (! default_init_p)
304 init_default_arch ();
308 return "a.out-sparc-netbsd";
311 if (target_big_endian)
312 return "a.out-sunos-big";
313 else if (default_arch_type == sparc86x && target_little_endian_data)
314 return "a.out-sunos-big";
316 return "a.out-sparc-little";
318 return "a.out-sunos-big";
329 return "coff-sparc-lynx";
336 return "elf32-sparc-vxworks";
340 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
347 * Invocation line includes a switch not recognized by the base assembler.
348 * See if it's a processor-specific option. These are:
351 * Warn on architecture bumps. See also -A.
353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354 * Standard 32 bit architectures.
356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357 * This used to only mean 64 bits, but properly specifying it
358 * complicated gcc's ASM_SPECs, so now opcode selection is
359 * specified orthogonally to word size (except when specifying
360 * the default, but that is an internal implementation detail).
361 * -Av8plus, -Av8plusa, -Av8plusb
362 * Same as -Av9{,a,b}.
363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
366 * -xarch=v9, -xarch=v9a, -xarch=v9b
367 * Same as -Av9{,a,b} -64, for compatibility with Sun's
370 * Select the architecture and possibly the file format.
371 * Instructions or features not supported by the selected
372 * architecture cause fatal errors.
374 * The default is to start at v6, and bump the architecture up
375 * whenever an instruction is seen at a higher level. In 32 bit
376 * environments, v9 is not bumped up to, the user must pass
379 * If -bump is specified, a warning is printing when bumping to
382 * If an architecture is specified, all instructions must match
383 * that architecture. Any higher level instructions are flagged
384 * as errors. Note that in the 32 bit environment specifying
385 * -Av8plus does not automatically create a v8plus object file, a
386 * v9 insn must be seen.
388 * If both an architecture and -bump are specified, the
389 * architecture starts at the specified level, but bumps are
390 * warnings. Note that we can't set `current_architecture' to
391 * the requested level in this case: in the 32 bit environment,
392 * we still must avoid creating v8plus object files unless v9
396 * Bumping between incompatible architectures is always an
397 * error. For example, from sparclite to v9.
401 const char *md_shortopts = "A:K:VQ:sq";
404 const char *md_shortopts = "A:k";
406 const char *md_shortopts = "A:";
409 struct option md_longopts[] = {
410 #define OPTION_BUMP (OPTION_MD_BASE)
411 {"bump", no_argument, NULL, OPTION_BUMP},
412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
413 {"sparc", no_argument, NULL, OPTION_SPARC},
414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
415 {"xarch", required_argument, NULL, OPTION_XARCH},
417 #define OPTION_32 (OPTION_MD_BASE + 3)
418 {"32", no_argument, NULL, OPTION_32},
419 #define OPTION_64 (OPTION_MD_BASE + 4)
420 {"64", no_argument, NULL, OPTION_64},
421 #define OPTION_TSO (OPTION_MD_BASE + 5)
422 {"TSO", no_argument, NULL, OPTION_TSO},
423 #define OPTION_PSO (OPTION_MD_BASE + 6)
424 {"PSO", no_argument, NULL, OPTION_PSO},
425 #define OPTION_RMO (OPTION_MD_BASE + 7)
426 {"RMO", no_argument, NULL, OPTION_RMO},
428 #ifdef SPARC_BIENDIAN
429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
445 {"relax", no_argument, NULL, OPTION_RELAX},
446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
448 {NULL, no_argument, NULL, 0}
451 size_t md_longopts_size = sizeof (md_longopts);
454 md_parse_option (c, arg)
458 /* We don't get a chance to initialize anything before we're called,
459 so handle that now. */
460 if (! default_init_p)
461 init_default_arch ();
467 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
472 if (strncmp (arg, "v9", 2) != 0)
473 md_parse_option (OPTION_32, NULL);
475 md_parse_option (OPTION_64, NULL);
481 struct sparc_arch *sa;
482 enum sparc_opcode_arch_val opcode_arch;
484 sa = lookup_arch (arg);
486 || ! sa->user_option_p)
488 if (c == OPTION_XARCH)
489 as_bad (_("invalid architecture -xarch=%s"), arg);
491 as_bad (_("invalid architecture -A%s"), arg);
495 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
496 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
497 as_fatal (_("Bad opcode table, broken assembler."));
499 max_architecture = opcode_arch;
500 architecture_requested = 1;
505 /* Ignore -sparc, used by SunOS make default .s.o rule. */
508 case OPTION_ENFORCE_ALIGNED_DATA:
509 enforce_aligned_data = 1;
512 #ifdef SPARC_BIENDIAN
513 case OPTION_LITTLE_ENDIAN:
514 target_big_endian = 0;
515 if (default_arch_type != sparclet)
516 as_fatal ("This target does not support -EL");
518 case OPTION_LITTLE_ENDIAN_DATA:
519 target_little_endian_data = 1;
520 target_big_endian = 0;
521 if (default_arch_type != sparc86x
522 && default_arch_type != v9)
523 as_fatal ("This target does not support --little-endian-data");
525 case OPTION_BIG_ENDIAN:
526 target_big_endian = 1;
540 const char **list, **l;
542 sparc_arch_size = c == OPTION_32 ? 32 : 64;
543 list = bfd_target_list ();
544 for (l = list; *l != NULL; l++)
546 if (sparc_arch_size == 32)
548 if (CONST_STRNEQ (*l, "elf32-sparc"))
553 if (CONST_STRNEQ (*l, "elf64-sparc"))
558 as_fatal (_("No compiled in support for %d bit object file format"),
565 sparc_memory_model = MM_TSO;
569 sparc_memory_model = MM_PSO;
573 sparc_memory_model = MM_RMO;
581 /* Qy - do emit .comment
582 Qn - do not emit .comment. */
586 /* Use .stab instead of .stab.excl. */
590 /* quick -- Native assembler does fewer checks. */
594 if (strcmp (arg, "PIC") != 0)
595 as_warn (_("Unrecognized option following -K"));
600 case OPTION_NO_UNDECLARED_REGS:
601 no_undeclared_regs = 1;
604 case OPTION_UNDECLARED_REGS:
605 no_undeclared_regs = 0;
613 case OPTION_NO_RELAX:
625 md_show_usage (stream)
628 const struct sparc_arch *arch;
631 /* We don't get a chance to initialize anything before we're called,
632 so handle that now. */
633 if (! default_init_p)
634 init_default_arch ();
636 fprintf (stream, _("SPARC options:\n"));
638 for (arch = &sparc_arch_table[0]; arch->name; arch++)
640 if (!arch->user_option_p)
642 if (arch != &sparc_arch_table[0])
643 fprintf (stream, " | ");
644 if (column + strlen (arch->name) > 70)
647 fputc ('\n', stream);
649 column += 5 + 2 + strlen (arch->name);
650 fprintf (stream, "-A%s", arch->name);
652 for (arch = &sparc_arch_table[0]; arch->name; arch++)
654 if (!arch->user_option_p)
656 fprintf (stream, " | ");
657 if (column + strlen (arch->name) > 65)
660 fputc ('\n', stream);
662 column += 5 + 7 + strlen (arch->name);
663 fprintf (stream, "-xarch=%s", arch->name);
665 fprintf (stream, _("\n\
666 specify variant of SPARC architecture\n\
667 -bump warn when assembler switches architectures\n\
669 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
670 -relax relax jumps and branches (default)\n\
671 -no-relax avoid changing any jumps and branches\n"));
673 fprintf (stream, _("\
674 -k generate PIC\n"));
677 fprintf (stream, _("\
678 -32 create 32 bit object file\n\
679 -64 create 64 bit object file\n"));
680 fprintf (stream, _("\
681 [default is %d]\n"), default_arch_size);
682 fprintf (stream, _("\
683 -TSO use Total Store Ordering\n\
684 -PSO use Partial Store Ordering\n\
685 -RMO use Relaxed Memory Ordering\n"));
686 fprintf (stream, _("\
687 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
688 fprintf (stream, _("\
689 -KPIC generate PIC\n\
690 -V print assembler version number\n\
691 -undeclared-regs ignore application global register usage without\n\
692 appropriate .register directive (default)\n\
693 -no-undeclared-regs force error on application global register usage\n\
694 without appropriate .register directive\n\
699 #ifdef SPARC_BIENDIAN
700 fprintf (stream, _("\
701 -EL generate code for a little endian machine\n\
702 -EB generate code for a big endian machine\n\
703 --little-endian-data generate code for a machine having big endian\n\
704 instructions and little endian data.\n"));
708 /* Native operand size opcode translation. */
714 } native_op_table[] =
716 {"ldn", "ld", "ldx"},
717 {"ldna", "lda", "ldxa"},
718 {"stn", "st", "stx"},
719 {"stna", "sta", "stxa"},
720 {"slln", "sll", "sllx"},
721 {"srln", "srl", "srlx"},
722 {"sran", "sra", "srax"},
723 {"casn", "cas", "casx"},
724 {"casna", "casa", "casxa"},
725 {"clrn", "clr", "clrx"},
729 /* sparc64 privileged and hyperprivileged registers. */
731 struct priv_reg_entry
737 struct priv_reg_entry priv_reg_table[] =
757 {"", -1}, /* End marker. */
760 struct priv_reg_entry hpriv_reg_table[] =
768 {"", -1}, /* End marker. */
771 /* v9a specific asrs. This table is ordered by initial
772 letter, in reverse. */
774 struct priv_reg_entry v9a_asr_table[] =
777 {"sys_tick_cmpr", 25},
781 {"softint_clear", 21},
789 {"clear_softint", 21},
790 {"", -1}, /* End marker. */
794 cmp_reg_entry (parg, qarg)
798 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
799 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
801 return strcmp (q->name, p->name);
804 /* This function is called once, at assembler startup time. It should
805 set up all the tables, etc. that the MD part of the assembler will
811 register const char *retval = NULL;
813 register unsigned int i = 0;
815 /* We don't get a chance to initialize anything before md_parse_option
816 is called, and it may not be called, so handle default initialization
817 now if not already done. */
818 if (! default_init_p)
819 init_default_arch ();
821 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
822 op_hash = hash_new ();
824 while (i < (unsigned int) sparc_num_opcodes)
826 const char *name = sparc_opcodes[i].name;
827 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
830 as_bad (_("Internal error: can't hash `%s': %s\n"),
831 sparc_opcodes[i].name, retval);
836 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
838 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
839 sparc_opcodes[i].name, sparc_opcodes[i].args);
844 while (i < (unsigned int) sparc_num_opcodes
845 && !strcmp (sparc_opcodes[i].name, name));
848 for (i = 0; native_op_table[i].name; i++)
850 const struct sparc_opcode *insn;
851 char *name = ((sparc_arch_size == 32)
852 ? native_op_table[i].name32
853 : native_op_table[i].name64);
854 insn = (struct sparc_opcode *) hash_find (op_hash, name);
857 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
858 name, native_op_table[i].name);
863 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
866 as_bad (_("Internal error: can't hash `%s': %s\n"),
867 sparc_opcodes[i].name, retval);
874 as_fatal (_("Broken assembler. No assembly attempted."));
876 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
877 sizeof (priv_reg_table[0]), cmp_reg_entry);
879 /* If -bump, record the architecture level at which we start issuing
880 warnings. The behaviour is different depending upon whether an
881 architecture was explicitly specified. If it wasn't, we issue warnings
882 for all upwards bumps. If it was, we don't start issuing warnings until
883 we need to bump beyond the requested architecture or when we bump between
884 conflicting architectures. */
887 && architecture_requested)
889 /* `max_architecture' records the requested architecture.
890 Issue warnings if we go above it. */
891 warn_after_architecture = max_architecture;
893 /* Find the highest architecture level that doesn't conflict with
894 the requested one. */
895 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
896 max_architecture > warn_after_architecture;
898 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
899 warn_after_architecture))
904 /* Called after all assembly has been done. */
909 unsigned long mach = bfd_mach_sparc;
911 if (sparc_arch_size == 64)
912 switch (current_architecture)
914 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
915 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
916 default: mach = bfd_mach_sparc_v9; break;
919 switch (current_architecture)
921 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
922 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
923 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
924 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
925 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
926 be but for now it is (since that's the way it's always been
930 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
933 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
936 in_signed_range (val, max)
937 bfd_signed_vma val, max;
941 /* Sign-extend the value from the architecture word size, so that
942 0xffffffff is always considered -1 on sparc32. */
943 if (sparc_arch_size == 32)
945 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
946 val = ((val & U0xffffffff) ^ sign) - sign;
955 /* Return non-zero if VAL is in the range 0 to MAX. */
958 in_unsigned_range (val, max)
966 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
967 (e.g. -15 to +31). */
970 in_bitfield_range (val, max)
971 bfd_signed_vma val, max;
977 if (val < ~(max >> 1))
991 for (i = 0; (mask & 1) == 0; ++i)
996 /* Implement big shift right. */
1002 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1003 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1004 return val >> amount;
1007 /* For communication between sparc_ip and get_expression. */
1008 static char *expr_end;
1010 /* Values for `special_case'.
1011 Instructions that require wierd handling because they're longer than
1013 #define SPECIAL_CASE_NONE 0
1014 #define SPECIAL_CASE_SET 1
1015 #define SPECIAL_CASE_SETSW 2
1016 #define SPECIAL_CASE_SETX 3
1017 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1018 #define SPECIAL_CASE_FDIV 4
1020 /* Bit masks of various insns. */
1021 #define NOP_INSN 0x01000000
1022 #define OR_INSN 0x80100000
1023 #define XOR_INSN 0x80180000
1024 #define FMOVS_INSN 0x81A00020
1025 #define SETHI_INSN 0x01000000
1026 #define SLLX_INSN 0x81281000
1027 #define SRA_INSN 0x81380000
1029 /* The last instruction to be assembled. */
1030 static const struct sparc_opcode *last_insn;
1031 /* The assembled opcode of `last_insn'. */
1032 static unsigned long last_opcode;
1034 /* Handle the set and setuw synthetic instructions. */
1037 synthetize_setuw (insn)
1038 const struct sparc_opcode *insn;
1040 int need_hi22_p = 0;
1041 int rd = (the_insn.opcode & RD (~0)) >> 25;
1043 if (the_insn.exp.X_op == O_constant)
1045 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1047 if (sizeof (offsetT) > 4
1048 && (the_insn.exp.X_add_number < 0
1049 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1050 as_warn (_("set: number not in 0..4294967295 range"));
1054 if (sizeof (offsetT) > 4
1055 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1056 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1057 as_warn (_("set: number not in -2147483648..4294967295 range"));
1058 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1062 /* See if operand is absolute and small; skip sethi if so. */
1063 if (the_insn.exp.X_op != O_constant
1064 || the_insn.exp.X_add_number >= (1 << 12)
1065 || the_insn.exp.X_add_number < -(1 << 12))
1067 the_insn.opcode = (SETHI_INSN | RD (rd)
1068 | ((the_insn.exp.X_add_number >> 10)
1069 & (the_insn.exp.X_op == O_constant
1071 the_insn.reloc = (the_insn.exp.X_op != O_constant
1072 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1073 output_insn (insn, &the_insn);
1077 /* See if operand has no low-order bits; skip OR if so. */
1078 if (the_insn.exp.X_op != O_constant
1079 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1082 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1084 | (the_insn.exp.X_add_number
1085 & (the_insn.exp.X_op != O_constant
1086 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1087 the_insn.reloc = (the_insn.exp.X_op != O_constant
1088 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1089 output_insn (insn, &the_insn);
1093 /* Handle the setsw synthetic instruction. */
1096 synthetize_setsw (insn)
1097 const struct sparc_opcode *insn;
1101 rd = (the_insn.opcode & RD (~0)) >> 25;
1103 if (the_insn.exp.X_op != O_constant)
1105 synthetize_setuw (insn);
1107 /* Need to sign extend it. */
1108 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1109 the_insn.reloc = BFD_RELOC_NONE;
1110 output_insn (insn, &the_insn);
1114 if (sizeof (offsetT) > 4
1115 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1116 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1117 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1119 low32 = the_insn.exp.X_add_number;
1123 synthetize_setuw (insn);
1129 the_insn.reloc = BFD_RELOC_NONE;
1130 /* See if operand is absolute and small; skip sethi if so. */
1131 if (low32 < -(1 << 12))
1133 the_insn.opcode = (SETHI_INSN | RD (rd)
1134 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1135 output_insn (insn, &the_insn);
1136 low32 = 0x1c00 | (low32 & 0x3ff);
1137 opc = RS1 (rd) | XOR_INSN;
1140 the_insn.opcode = (opc | RD (rd) | IMMED
1141 | (low32 & 0x1fff));
1142 output_insn (insn, &the_insn);
1145 /* Handle the setsw synthetic instruction. */
1148 synthetize_setx (insn)
1149 const struct sparc_opcode *insn;
1151 int upper32, lower32;
1152 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1153 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1155 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1156 int need_xor10_p = 0;
1158 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1159 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1160 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1163 upper_dstreg = tmpreg;
1164 /* The tmp reg should not be the dst reg. */
1165 if (tmpreg == dstreg)
1166 as_warn (_("setx: temporary register same as destination register"));
1168 /* ??? Obviously there are other optimizations we can do
1169 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1170 doing some of these. Later. If you do change things, try to
1171 change all of this to be table driven as well. */
1172 /* What to output depends on the number if it's constant.
1173 Compute that first, then output what we've decided upon. */
1174 if (the_insn.exp.X_op != O_constant)
1176 if (sparc_arch_size == 32)
1178 /* When arch size is 32, we want setx to be equivalent
1179 to setuw for anything but constants. */
1180 the_insn.exp.X_add_number &= 0xffffffff;
1181 synthetize_setuw (insn);
1184 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1190 /* Reset X_add_number, we've extracted it as upper32/lower32.
1191 Otherwise fixup_segment will complain about not being able to
1192 write an 8 byte number in a 4 byte field. */
1193 the_insn.exp.X_add_number = 0;
1195 /* Only need hh22 if `or' insn can't handle constant. */
1196 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1199 /* Does bottom part (after sethi) have bits? */
1200 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1201 /* No hh22, but does upper32 still have bits we can't set
1203 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1206 /* If the lower half is all zero, we build the upper half directly
1207 into the dst reg. */
1209 /* Need lower half if number is zero or 0xffffffff00000000. */
1210 || (! need_hh22_p && ! need_hm10_p))
1212 /* No need for sethi if `or' insn can handle constant. */
1213 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1214 /* Note that we can't use a negative constant in the `or'
1215 insn unless the upper 32 bits are all ones. */
1216 || (lower32 < 0 && upper32 != -1)
1217 || (lower32 >= 0 && upper32 == -1))
1220 if (need_hi22_p && upper32 == -1)
1223 /* Does bottom part (after sethi) have bits? */
1224 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1226 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1227 /* Need `or' if we didn't set anything else. */
1228 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1232 /* Output directly to dst reg if lower 32 bits are all zero. */
1233 upper_dstreg = dstreg;
1236 if (!upper_dstreg && dstreg)
1237 as_warn (_("setx: illegal temporary register g0"));
1241 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1242 | ((upper32 >> 10) & 0x3fffff));
1243 the_insn.reloc = (the_insn.exp.X_op != O_constant
1244 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1245 output_insn (insn, &the_insn);
1250 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1251 | (((need_xor10_p ? ~lower32 : lower32)
1252 >> 10) & 0x3fffff));
1253 the_insn.reloc = (the_insn.exp.X_op != O_constant
1254 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1255 output_insn (insn, &the_insn);
1260 the_insn.opcode = (OR_INSN
1261 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1264 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1265 the_insn.reloc = (the_insn.exp.X_op != O_constant
1266 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1267 output_insn (insn, &the_insn);
1272 /* FIXME: One nice optimization to do here is to OR the low part
1273 with the highpart if hi22 isn't needed and the low part is
1275 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1278 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1279 the_insn.reloc = (the_insn.exp.X_op != O_constant
1280 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1281 output_insn (insn, &the_insn);
1284 /* If we needed to build the upper part, shift it into place. */
1285 if (need_hh22_p || need_hm10_p)
1287 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1289 the_insn.reloc = BFD_RELOC_NONE;
1290 output_insn (insn, &the_insn);
1293 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1296 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1297 | 0x1c00 | (lower32 & 0x3ff));
1298 the_insn.reloc = BFD_RELOC_NONE;
1299 output_insn (insn, &the_insn);
1302 /* If we needed to build both upper and lower parts, OR them together. */
1303 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1305 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1307 the_insn.reloc = BFD_RELOC_NONE;
1308 output_insn (insn, &the_insn);
1312 /* Main entry point to assemble one instruction. */
1318 const struct sparc_opcode *insn;
1322 special_case = sparc_ip (str, &insn);
1326 /* We warn about attempts to put a floating point branch in a delay slot,
1327 unless the delay slot has been annulled. */
1328 if (last_insn != NULL
1329 && (insn->flags & F_FBR) != 0
1330 && (last_insn->flags & F_DELAYED) != 0
1331 /* ??? This test isn't completely accurate. We assume anything with
1332 F_{UNBR,CONDBR,FBR} set is annullable. */
1333 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1334 || (last_opcode & ANNUL) == 0))
1335 as_warn (_("FP branch in delay slot"));
1337 /* SPARC before v9 requires a nop instruction between a floating
1338 point instruction and a floating point branch. We insert one
1339 automatically, with a warning. */
1340 if (max_architecture < SPARC_OPCODE_ARCH_V9
1341 && last_insn != NULL
1342 && (insn->flags & F_FBR) != 0
1343 && (last_insn->flags & F_FLOAT) != 0)
1345 struct sparc_it nop_insn;
1347 nop_insn.opcode = NOP_INSN;
1348 nop_insn.reloc = BFD_RELOC_NONE;
1349 output_insn (insn, &nop_insn);
1350 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1353 switch (special_case)
1355 case SPECIAL_CASE_NONE:
1357 output_insn (insn, &the_insn);
1360 case SPECIAL_CASE_SETSW:
1361 synthetize_setsw (insn);
1364 case SPECIAL_CASE_SET:
1365 synthetize_setuw (insn);
1368 case SPECIAL_CASE_SETX:
1369 synthetize_setx (insn);
1372 case SPECIAL_CASE_FDIV:
1374 int rd = (the_insn.opcode >> 25) & 0x1f;
1376 output_insn (insn, &the_insn);
1378 /* According to information leaked from Sun, the "fdiv" instructions
1379 on early SPARC machines would produce incorrect results sometimes.
1380 The workaround is to add an fmovs of the destination register to
1381 itself just after the instruction. This was true on machines
1382 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1383 assert (the_insn.reloc == BFD_RELOC_NONE);
1384 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1385 output_insn (insn, &the_insn);
1390 as_fatal (_("failed special case insn sanity check"));
1394 /* Subroutine of md_assemble to do the actual parsing. */
1397 sparc_ip (str, pinsn)
1399 const struct sparc_opcode **pinsn;
1401 char *error_message = "";
1405 const struct sparc_opcode *insn;
1407 unsigned long opcode;
1408 unsigned int mask = 0;
1412 int special_case = SPECIAL_CASE_NONE;
1419 while (ISLOWER (*s) || ISDIGIT (*s));
1436 as_bad (_("Unknown opcode: `%s'"), str);
1438 return special_case;
1440 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1444 as_bad (_("Unknown opcode: `%s'"), str);
1445 return special_case;
1455 opcode = insn->match;
1456 memset (&the_insn, '\0', sizeof (the_insn));
1457 the_insn.reloc = BFD_RELOC_NONE;
1460 /* Build the opcode, checking as we go to make sure that the
1462 for (args = insn->args;; ++args)
1470 /* Parse a series of masks. */
1477 if (! parse_keyword_arg (sparc_encode_membar, &s,
1480 error_message = _(": invalid membar mask name");
1486 if (*s == '|' || *s == '+')
1494 if (! parse_const_expr_arg (&s, &kmask))
1496 error_message = _(": invalid membar mask expression");
1499 if (kmask < 0 || kmask > 127)
1501 error_message = _(": invalid membar mask number");
1506 opcode |= MEMBAR (kmask);
1514 if (! parse_const_expr_arg (&s, &smask))
1516 error_message = _(": invalid siam mode expression");
1519 if (smask < 0 || smask > 7)
1521 error_message = _(": invalid siam mode number");
1532 /* Parse a prefetch function. */
1535 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1537 error_message = _(": invalid prefetch function name");
1543 if (! parse_const_expr_arg (&s, &fcn))
1545 error_message = _(": invalid prefetch function expression");
1548 if (fcn < 0 || fcn > 31)
1550 error_message = _(": invalid prefetch function number");
1560 /* Parse a sparc64 privileged register. */
1563 struct priv_reg_entry *p = priv_reg_table;
1564 unsigned int len = 9999999; /* Init to make gcc happy. */
1567 while (p->name[0] > s[0])
1569 while (p->name[0] == s[0])
1571 len = strlen (p->name);
1572 if (strncmp (p->name, s, len) == 0)
1576 if (p->name[0] != s[0])
1578 error_message = _(": unrecognizable privileged register");
1582 opcode |= (p->regnum << 14);
1584 opcode |= (p->regnum << 25);
1590 error_message = _(": unrecognizable privileged register");
1596 /* Parse a sparc64 hyperprivileged register. */
1599 struct priv_reg_entry *p = hpriv_reg_table;
1600 unsigned int len = 9999999; /* Init to make gcc happy. */
1603 while (p->name[0] > s[0])
1605 while (p->name[0] == s[0])
1607 len = strlen (p->name);
1608 if (strncmp (p->name, s, len) == 0)
1612 if (p->name[0] != s[0])
1614 error_message = _(": unrecognizable hyperprivileged register");
1618 opcode |= (p->regnum << 14);
1620 opcode |= (p->regnum << 25);
1626 error_message = _(": unrecognizable hyperprivileged register");
1632 /* Parse a v9a/v9b ancillary state register. */
1635 struct priv_reg_entry *p = v9a_asr_table;
1636 unsigned int len = 9999999; /* Init to make gcc happy. */
1639 while (p->name[0] > s[0])
1641 while (p->name[0] == s[0])
1643 len = strlen (p->name);
1644 if (strncmp (p->name, s, len) == 0)
1648 if (p->name[0] != s[0])
1650 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1653 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1655 error_message = _(": rd on write only ancillary state register");
1659 && (insn->architecture
1660 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1662 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1663 error_message = _(": unrecognizable v9a ancillary state register");
1667 opcode |= (p->regnum << 14);
1669 opcode |= (p->regnum << 25);
1675 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1681 if (strncmp (s, "%asr", 4) == 0)
1689 while (ISDIGIT (*s))
1691 num = num * 10 + *s - '0';
1695 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1697 if (num < 16 || 31 < num)
1699 error_message = _(": asr number must be between 16 and 31");
1705 if (num < 0 || 31 < num)
1707 error_message = _(": asr number must be between 0 and 31");
1712 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1717 error_message = _(": expecting %asrN");
1724 the_insn.reloc = BFD_RELOC_SPARC_11;
1728 the_insn.reloc = BFD_RELOC_SPARC_10;
1732 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1733 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1734 the_insn.reloc = BFD_RELOC_SPARC_5;
1736 the_insn.reloc = BFD_RELOC_SPARC13;
1737 /* These fields are unsigned, but for upward compatibility,
1738 allow negative values as well. */
1742 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1743 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1744 the_insn.reloc = BFD_RELOC_SPARC_6;
1746 the_insn.reloc = BFD_RELOC_SPARC13;
1747 /* These fields are unsigned, but for upward compatibility,
1748 allow negative values as well. */
1752 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1757 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1762 if (*s == 'p' && s[1] == 'n')
1770 if (*s == 'p' && s[1] == 't')
1782 if (strncmp (s, "%icc", 4) == 0)
1794 if (strncmp (s, "%xcc", 4) == 0)
1806 if (strncmp (s, "%fcc0", 5) == 0)
1818 if (strncmp (s, "%fcc1", 5) == 0)
1830 if (strncmp (s, "%fcc2", 5) == 0)
1842 if (strncmp (s, "%fcc3", 5) == 0)
1850 if (strncmp (s, "%pc", 3) == 0)
1858 if (strncmp (s, "%tick", 5) == 0)
1865 case '\0': /* End of args. */
1866 if (s[0] == ',' && s[1] == '%')
1868 static const struct ops
1870 /* The name as it appears in assembler. */
1872 /* strlen (name), precomputed for speed */
1874 /* The reloc this pseudo-op translates to. */
1876 /* 1 if tls call. */
1881 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1882 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1883 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1884 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1885 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1886 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1887 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1888 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1889 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
1892 const struct ops *o;
1896 for (o = ops; o->name; o++)
1897 if (strncmp (s + 2, o->name, o->len) == 0)
1899 if (o->name == NULL)
1902 if (s[o->len + 2] != '(')
1904 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1905 return special_case;
1908 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
1910 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1912 return special_case;
1916 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1917 || the_insn.exp.X_add_number != 0
1918 || the_insn.exp.X_add_symbol
1919 != symbol_find_or_make ("__tls_get_addr")))
1921 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1923 return special_case;
1926 the_insn.reloc = o->reloc;
1927 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1930 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1933 else if (*s1 == ')')
1942 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1943 return special_case;
1947 (void) get_expression (s);
1967 case '[': /* These must match exactly. */
1975 case '#': /* Must be at least one digit. */
1978 while (ISDIGIT (*s))
1986 case 'C': /* Coprocessor state register. */
1987 if (strncmp (s, "%csr", 4) == 0)
1994 case 'b': /* Next operand is a coprocessor register. */
1997 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2002 mask = 10 * (mask - '0') + (*s++ - '0');
2016 opcode |= mask << 14;
2024 opcode |= mask << 25;
2030 case 'r': /* next operand must be a register */
2040 case 'f': /* frame pointer */
2048 case 'g': /* global register */
2057 case 'i': /* in register */
2061 mask = c - '0' + 24;
2066 case 'l': /* local register */
2070 mask = (c - '0' + 16);
2075 case 'o': /* out register */
2079 mask = (c - '0' + 8);
2084 case 's': /* stack pointer */
2092 case 'r': /* any register */
2093 if (!ISDIGIT ((c = *s++)))
2110 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2126 if ((mask & ~1) == 2 && sparc_arch_size == 64
2127 && no_undeclared_regs && ! globals[mask])
2128 as_bad (_("detected global register use not covered by .register pseudo-op"));
2130 /* Got the register, now figure out where
2131 it goes in the opcode. */
2135 opcode |= mask << 14;
2143 opcode |= mask << 25;
2147 opcode |= (mask << 25) | (mask << 14);
2151 opcode |= (mask << 25) | (mask << 0);
2157 case 'e': /* next operand is a floating point register */
2172 && ((format = *s) == 'f')
2175 for (mask = 0; ISDIGIT (*s); ++s)
2177 mask = 10 * mask + (*s - '0');
2178 } /* read the number */
2186 } /* register must be even numbered */
2194 } /* register must be multiple of 4 */
2198 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2199 error_message = _(": There are only 64 f registers; [0-63]");
2201 error_message = _(": There are only 32 f registers; [0-31]");
2204 else if (mask >= 32)
2206 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2208 if (*args == 'e' || *args == 'f' || *args == 'g')
2211 = _(": There are only 32 single precision f registers; [0-31]");
2215 mask -= 31; /* wrap high bit */
2219 error_message = _(": There are only 32 f registers; [0-31]");
2227 } /* if not an 'f' register. */
2234 opcode |= RS1 (mask);
2240 opcode |= RS2 (mask);
2246 opcode |= RD (mask);
2255 if (strncmp (s, "%fsr", 4) == 0)
2262 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2263 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2266 case 'l': /* 22 bit PC relative immediate */
2267 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2271 case 'L': /* 30 bit immediate */
2272 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2277 case 'n': /* 22 bit immediate */
2278 the_insn.reloc = BFD_RELOC_SPARC22;
2281 case 'i': /* 13 bit immediate */
2282 the_insn.reloc = BFD_RELOC_SPARC13;
2292 char *op_arg = NULL;
2293 static expressionS op_exp;
2294 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2296 /* Check for %hi, etc. */
2299 static const struct ops {
2300 /* The name as it appears in assembler. */
2302 /* strlen (name), precomputed for speed */
2304 /* The reloc this pseudo-op translates to. */
2306 /* Non-zero if for v9 only. */
2308 /* Non-zero if can be used in pc-relative contexts. */
2309 int pcrel_p;/*FIXME:wip*/
2311 /* hix/lox must appear before hi/lo so %hix won't be
2312 mistaken for %hi. */
2313 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2314 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2315 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2316 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2317 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2318 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2319 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2320 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2321 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2322 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2323 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2324 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2325 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2326 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2327 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2328 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2329 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2330 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2331 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2333 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2335 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2336 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2337 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2338 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2339 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2341 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2343 { NULL, 0, 0, 0, 0 }
2345 const struct ops *o;
2347 for (o = ops; o->name; o++)
2348 if (strncmp (s + 1, o->name, o->len) == 0)
2350 if (o->name == NULL)
2353 if (s[o->len + 1] != '(')
2355 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2356 return special_case;
2360 the_insn.reloc = o->reloc;
2365 /* Note that if the get_expression() fails, we will still
2366 have created U entries in the symbol table for the
2367 'symbols' in the input string. Try not to create U
2368 symbols for registers, etc. */
2370 /* This stuff checks to see if the expression ends in
2371 +%reg. If it does, it removes the register from
2372 the expression, and re-sets 's' to point to the
2379 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2382 else if (*s1 == ')')
2391 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2392 return special_case;
2396 (void) get_expression (s);
2399 if (*s == ',' || *s == ']' || !*s)
2401 if (*s != '+' && *s != '-')
2403 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2404 return special_case;
2408 op_exp = the_insn.exp;
2409 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2412 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2415 if (s1 != s && ISDIGIT (s1[-1]))
2417 if (s1[-2] == '%' && s1[-3] == '+')
2419 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2426 if (op_arg && s1 == s + 1)
2427 the_insn.exp.X_op = O_absent;
2429 (void) get_expression (s);
2441 (void) get_expression (s);
2449 the_insn.exp2 = the_insn.exp;
2450 the_insn.exp = op_exp;
2451 if (the_insn.exp2.X_op == O_absent)
2452 the_insn.exp2.X_op = O_illegal;
2453 else if (the_insn.exp.X_op == O_absent)
2455 the_insn.exp = the_insn.exp2;
2456 the_insn.exp2.X_op = O_illegal;
2458 else if (the_insn.exp.X_op == O_constant)
2460 valueT val = the_insn.exp.X_add_number;
2461 switch (the_insn.reloc)
2466 case BFD_RELOC_SPARC_HH22:
2467 val = BSR (val, 32);
2470 case BFD_RELOC_SPARC_LM22:
2471 case BFD_RELOC_HI22:
2472 val = (val >> 10) & 0x3fffff;
2475 case BFD_RELOC_SPARC_HM10:
2476 val = BSR (val, 32);
2479 case BFD_RELOC_LO10:
2483 case BFD_RELOC_SPARC_H44:
2488 case BFD_RELOC_SPARC_M44:
2493 case BFD_RELOC_SPARC_L44:
2497 case BFD_RELOC_SPARC_HIX22:
2499 val = (val >> 10) & 0x3fffff;
2502 case BFD_RELOC_SPARC_LOX10:
2503 val = (val & 0x3ff) | 0x1c00;
2506 the_insn.exp = the_insn.exp2;
2507 the_insn.exp.X_add_number += val;
2508 the_insn.exp2.X_op = O_illegal;
2509 the_insn.reloc = old_reloc;
2511 else if (the_insn.exp2.X_op != O_constant)
2513 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2514 return special_case;
2518 if (old_reloc != BFD_RELOC_SPARC13
2519 || the_insn.reloc != BFD_RELOC_LO10
2520 || sparc_arch_size != 64
2523 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2524 return special_case;
2526 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2530 /* Check for constants that don't require emitting a reloc. */
2531 if (the_insn.exp.X_op == O_constant
2532 && the_insn.exp.X_add_symbol == 0
2533 && the_insn.exp.X_op_symbol == 0)
2535 /* For pc-relative call instructions, we reject
2536 constants to get better code. */
2538 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2539 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2541 error_message = _(": PC-relative operand can't be a constant");
2545 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2546 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2548 error_message = _(": TLS operand can't be a constant");
2552 /* Constants that won't fit are checked in md_apply_fix
2553 and bfd_install_relocation.
2554 ??? It would be preferable to install the constants
2555 into the insn here and save having to create a fixS
2556 for each one. There already exists code to handle
2557 all the various cases (e.g. in md_apply_fix and
2558 bfd_install_relocation) so duplicating all that code
2559 here isn't right. */
2579 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2581 error_message = _(": invalid ASI name");
2587 if (! parse_const_expr_arg (&s, &asi))
2589 error_message = _(": invalid ASI expression");
2592 if (asi < 0 || asi > 255)
2594 error_message = _(": invalid ASI number");
2598 opcode |= ASI (asi);
2600 } /* Alternate space. */
2603 if (strncmp (s, "%psr", 4) == 0)
2610 case 'q': /* Floating point queue. */
2611 if (strncmp (s, "%fq", 3) == 0)
2618 case 'Q': /* Coprocessor queue. */
2619 if (strncmp (s, "%cq", 3) == 0)
2627 if (strcmp (str, "set") == 0
2628 || strcmp (str, "setuw") == 0)
2630 special_case = SPECIAL_CASE_SET;
2633 else if (strcmp (str, "setsw") == 0)
2635 special_case = SPECIAL_CASE_SETSW;
2638 else if (strcmp (str, "setx") == 0)
2640 special_case = SPECIAL_CASE_SETX;
2643 else if (strncmp (str, "fdiv", 4) == 0)
2645 special_case = SPECIAL_CASE_FDIV;
2651 if (strncmp (s, "%asi", 4) != 0)
2657 if (strncmp (s, "%fprs", 5) != 0)
2663 if (strncmp (s, "%ccr", 4) != 0)
2669 if (strncmp (s, "%tbr", 4) != 0)
2675 if (strncmp (s, "%wim", 4) != 0)
2682 char *push = input_line_pointer;
2685 input_line_pointer = s;
2687 if (e.X_op == O_constant)
2689 int n = e.X_add_number;
2690 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2691 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2693 opcode |= e.X_add_number << 5;
2696 as_bad (_("non-immediate OPF operand, ignored"));
2697 s = input_line_pointer;
2698 input_line_pointer = push;
2703 if (strncmp (s, "%y", 2) != 0)
2711 /* Parse a sparclet cpreg. */
2713 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2715 error_message = _(": invalid cpreg name");
2718 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2723 as_fatal (_("failed sanity check."));
2724 } /* switch on arg code. */
2726 /* Break out of for() loop. */
2728 } /* For each arg that we expect. */
2733 /* Args don't match. */
2734 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2735 && (insn->name == insn[1].name
2736 || !strcmp (insn->name, insn[1].name)))
2744 as_bad (_("Illegal operands%s"), error_message);
2745 return special_case;
2750 /* We have a match. Now see if the architecture is OK. */
2751 int needed_arch_mask = insn->architecture;
2756 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2757 if (! needed_arch_mask)
2759 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2762 if (needed_arch_mask
2763 & SPARC_OPCODE_SUPPORTED (current_architecture))
2766 /* Can we bump up the architecture? */
2767 else if (needed_arch_mask
2768 & SPARC_OPCODE_SUPPORTED (max_architecture))
2770 enum sparc_opcode_arch_val needed_architecture =
2771 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2772 & needed_arch_mask);
2774 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2776 && needed_architecture > warn_after_architecture)
2778 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2779 sparc_opcode_archs[current_architecture].name,
2780 sparc_opcode_archs[needed_architecture].name,
2782 warn_after_architecture = needed_architecture;
2784 current_architecture = needed_architecture;
2787 /* ??? This seems to be a bit fragile. What if the next entry in
2788 the opcode table is the one we want and it is supported?
2789 It is possible to arrange the table today so that this can't
2790 happen but what about tomorrow? */
2793 int arch, printed_one_p = 0;
2795 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2797 /* Create a list of the architectures that support the insn. */
2798 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2800 arch = sparc_ffs (needed_arch_mask);
2801 while ((1 << arch) <= needed_arch_mask)
2803 if ((1 << arch) & needed_arch_mask)
2807 strcpy (p, sparc_opcode_archs[arch].name);
2814 as_bad (_("Architecture mismatch on \"%s\"."), str);
2815 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2817 sparc_opcode_archs[max_architecture].name);
2818 return special_case;
2820 } /* If no match. */
2823 } /* Forever looking for a match. */
2825 the_insn.opcode = opcode;
2826 return special_case;
2829 /* Parse an argument that can be expressed as a keyword.
2830 (eg: #StoreStore or %ccfr).
2831 The result is a boolean indicating success.
2832 If successful, INPUT_POINTER is updated. */
2835 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2836 int (*lookup_fn) PARAMS ((const char *));
2837 char **input_pointerP;
2843 p = *input_pointerP;
2844 for (q = p + (*p == '#' || *p == '%');
2845 ISALNUM (*q) || *q == '_';
2850 value = (*lookup_fn) (p);
2855 *input_pointerP = q;
2859 /* Parse an argument that is a constant expression.
2860 The result is a boolean indicating success. */
2863 parse_const_expr_arg (input_pointerP, valueP)
2864 char **input_pointerP;
2867 char *save = input_line_pointer;
2870 input_line_pointer = *input_pointerP;
2871 /* The next expression may be something other than a constant
2872 (say if we're not processing the right variant of the insn).
2873 Don't call expression unless we're sure it will succeed as it will
2874 signal an error (which we want to defer until later). */
2875 /* FIXME: It might be better to define md_operand and have it recognize
2876 things like %asi, etc. but continuing that route through to the end
2877 is a lot of work. */
2878 if (*input_line_pointer == '%')
2880 input_line_pointer = save;
2884 *input_pointerP = input_line_pointer;
2885 input_line_pointer = save;
2886 if (exp.X_op != O_constant)
2888 *valueP = exp.X_add_number;
2892 /* Subroutine of sparc_ip to parse an expression. */
2895 get_expression (str)
2901 save_in = input_line_pointer;
2902 input_line_pointer = str;
2903 seg = expression (&the_insn.exp);
2904 if (seg != absolute_section
2905 && seg != text_section
2906 && seg != data_section
2907 && seg != bss_section
2908 && seg != undefined_section)
2910 the_insn.error = _("bad segment");
2911 expr_end = input_line_pointer;
2912 input_line_pointer = save_in;
2915 expr_end = input_line_pointer;
2916 input_line_pointer = save_in;
2920 /* Subroutine of md_assemble to output one insn. */
2923 output_insn (insn, the_insn)
2924 const struct sparc_opcode *insn;
2925 struct sparc_it *the_insn;
2927 char *toP = frag_more (4);
2929 /* Put out the opcode. */
2930 if (INSN_BIG_ENDIAN)
2931 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2933 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2935 /* Put out the symbol-dependent stuff. */
2936 if (the_insn->reloc != BFD_RELOC_NONE)
2938 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2939 (toP - frag_now->fr_literal), /* Where. */
2944 /* Turn off overflow checking in fixup_segment. We'll do our
2945 own overflow checking in md_apply_fix. This is necessary because
2946 the insn size is 4 and fixup_segment will signal an overflow for
2947 large 8 byte quantities. */
2948 fixP->fx_no_overflow = 1;
2949 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2950 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2954 last_opcode = the_insn->opcode;
2957 dwarf2_emit_insn (4);
2962 md_atof (int type, char *litP, int *sizeP)
2964 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2967 /* Write a value out to the object file, using the appropriate
2971 md_number_to_chars (buf, val, n)
2976 if (target_big_endian)
2977 number_to_chars_bigendian (buf, val, n);
2978 else if (target_little_endian_data
2979 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2980 /* Output debug words, which are not in allocated sections, as big
2982 number_to_chars_bigendian (buf, val, n);
2983 else if (target_little_endian_data || ! target_big_endian)
2984 number_to_chars_littleendian (buf, val, n);
2987 /* Apply a fixS to the frags, now that we know the value it ought to
2991 md_apply_fix (fixP, valP, segment)
2994 segT segment ATTRIBUTE_UNUSED;
2996 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2997 offsetT val = * (offsetT *) valP;
3000 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3002 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3005 /* SPARC ELF relocations don't use an addend in the data field. */
3006 if (fixP->fx_addsy != NULL)
3008 switch (fixP->fx_r_type)
3010 case BFD_RELOC_SPARC_TLS_GD_HI22:
3011 case BFD_RELOC_SPARC_TLS_GD_LO10:
3012 case BFD_RELOC_SPARC_TLS_GD_ADD:
3013 case BFD_RELOC_SPARC_TLS_GD_CALL:
3014 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3015 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3016 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3017 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3018 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3019 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3020 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3021 case BFD_RELOC_SPARC_TLS_IE_HI22:
3022 case BFD_RELOC_SPARC_TLS_IE_LO10:
3023 case BFD_RELOC_SPARC_TLS_IE_LD:
3024 case BFD_RELOC_SPARC_TLS_IE_LDX:
3025 case BFD_RELOC_SPARC_TLS_IE_ADD:
3026 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3027 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3028 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3029 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3030 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3031 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3032 case BFD_RELOC_SPARC_TLS_TPOFF32:
3033 case BFD_RELOC_SPARC_TLS_TPOFF64:
3034 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3044 /* This is a hack. There should be a better way to
3045 handle this. Probably in terms of howto fields, once
3046 we can look at these fixups in terms of howtos. */
3047 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3048 val += fixP->fx_where + fixP->fx_frag->fr_address;
3051 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3052 generate a reloc, then we just want to let the reloc addend set
3053 the value. We do not want to also stuff the addend into the
3054 object file. Including the addend in the object file works when
3055 doing a static link, because the linker will ignore the object
3056 file contents. However, the dynamic linker does not ignore the
3057 object file contents. */
3058 if (fixP->fx_addsy != NULL
3059 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3062 /* When generating PIC code, we do not want an addend for a reloc
3063 against a local symbol. We adjust fx_addnumber to cancel out the
3064 value already included in val, and to also cancel out the
3065 adjustment which bfd_install_relocation will create. */
3067 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3068 && fixP->fx_addsy != NULL
3069 && ! S_IS_COMMON (fixP->fx_addsy)
3070 && symbol_section_p (fixP->fx_addsy))
3071 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3073 /* When generating PIC code, we need to fiddle to get
3074 bfd_install_relocation to do the right thing for a PC relative
3075 reloc against a local symbol which we are going to keep. */
3077 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3078 && fixP->fx_addsy != NULL
3079 && (S_IS_EXTERNAL (fixP->fx_addsy)
3080 || S_IS_WEAK (fixP->fx_addsy))
3081 && S_IS_DEFINED (fixP->fx_addsy)
3082 && ! S_IS_COMMON (fixP->fx_addsy))
3085 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3089 /* If this is a data relocation, just output VAL. */
3091 if (fixP->fx_r_type == BFD_RELOC_16
3092 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3094 md_number_to_chars (buf, val, 2);
3096 else if (fixP->fx_r_type == BFD_RELOC_32
3097 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3098 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3100 md_number_to_chars (buf, val, 4);
3102 else if (fixP->fx_r_type == BFD_RELOC_64
3103 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3105 md_number_to_chars (buf, val, 8);
3107 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3108 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3115 /* It's a relocation against an instruction. */
3117 if (INSN_BIG_ENDIAN)
3118 insn = bfd_getb32 ((unsigned char *) buf);
3120 insn = bfd_getl32 ((unsigned char *) buf);
3122 switch (fixP->fx_r_type)
3124 case BFD_RELOC_32_PCREL_S2:
3126 /* FIXME: This increment-by-one deserves a comment of why it's
3128 if (! sparc_pic_code
3129 || fixP->fx_addsy == NULL
3130 || symbol_section_p (fixP->fx_addsy))
3133 insn |= val & 0x3fffffff;
3135 /* See if we have a delay slot. */
3136 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3140 #define XCC (2 << 20)
3141 #define COND(x) (((x)&0xf)<<25)
3142 #define CONDA COND(0x8)
3143 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3144 #define INSN_BA (F2(0,2) | CONDA)
3145 #define INSN_OR F3(2, 0x2, 0)
3146 #define INSN_NOP F2(0,4)
3150 /* If the instruction is a call with either:
3152 arithmetic instruction with rd == %o7
3153 where rs1 != %o7 and rs2 if it is register != %o7
3154 then we can optimize if the call destination is near
3155 by changing the call into a branch always. */
3156 if (INSN_BIG_ENDIAN)
3157 delay = bfd_getb32 ((unsigned char *) buf + 4);
3159 delay = bfd_getl32 ((unsigned char *) buf + 4);
3160 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3162 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3163 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3164 || ((delay & RD (~0)) != RD (O7))))
3166 if ((delay & RS1 (~0)) == RS1 (O7)
3167 || ((delay & F3I (~0)) == 0
3168 && (delay & RS2 (~0)) == RS2 (O7)))
3170 /* Ensure the branch will fit into simm22. */
3171 if ((val & 0x3fe00000)
3172 && (val & 0x3fe00000) != 0x3fe00000)
3174 /* Check if the arch is v9 and branch will fit
3176 if (((val & 0x3c0000) == 0
3177 || (val & 0x3c0000) == 0x3c0000)
3178 && (sparc_arch_size == 64
3179 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3181 insn = INSN_BPA | (val & 0x7ffff);
3184 insn = INSN_BA | (val & 0x3fffff);
3185 if (fixP->fx_where >= 4
3186 && ((delay & (0xffffffff ^ RS1 (~0)))
3187 == (INSN_OR | RD (O7) | RS2 (G0))))
3192 if (INSN_BIG_ENDIAN)
3193 setter = bfd_getb32 ((unsigned char *) buf - 4);
3195 setter = bfd_getl32 ((unsigned char *) buf - 4);
3196 if ((setter & (0xffffffff ^ RD (~0)))
3197 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3204 If call foo was replaced with ba, replace
3205 or %rN, %g0, %o7 with nop. */
3206 reg = (delay & RS1 (~0)) >> 14;
3207 if (reg != ((setter & RD (~0)) >> 25)
3208 || reg == G0 || reg == O7)
3211 if (INSN_BIG_ENDIAN)
3212 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3214 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3219 case BFD_RELOC_SPARC_11:
3220 if (! in_signed_range (val, 0x7ff))
3221 as_bad_where (fixP->fx_file, fixP->fx_line,
3222 _("relocation overflow"));
3223 insn |= val & 0x7ff;
3226 case BFD_RELOC_SPARC_10:
3227 if (! in_signed_range (val, 0x3ff))
3228 as_bad_where (fixP->fx_file, fixP->fx_line,
3229 _("relocation overflow"));
3230 insn |= val & 0x3ff;
3233 case BFD_RELOC_SPARC_7:
3234 if (! in_bitfield_range (val, 0x7f))
3235 as_bad_where (fixP->fx_file, fixP->fx_line,
3236 _("relocation overflow"));
3240 case BFD_RELOC_SPARC_6:
3241 if (! in_bitfield_range (val, 0x3f))
3242 as_bad_where (fixP->fx_file, fixP->fx_line,
3243 _("relocation overflow"));
3247 case BFD_RELOC_SPARC_5:
3248 if (! in_bitfield_range (val, 0x1f))
3249 as_bad_where (fixP->fx_file, fixP->fx_line,
3250 _("relocation overflow"));
3254 case BFD_RELOC_SPARC_WDISP16:
3257 || val <= -(offsetT) 0x20008)
3258 as_bad_where (fixP->fx_file, fixP->fx_line,
3259 _("relocation overflow"));
3260 /* FIXME: The +1 deserves a comment. */
3261 val = (val >> 2) + 1;
3262 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3265 case BFD_RELOC_SPARC_WDISP19:
3268 || val <= -(offsetT) 0x100008)
3269 as_bad_where (fixP->fx_file, fixP->fx_line,
3270 _("relocation overflow"));
3271 /* FIXME: The +1 deserves a comment. */
3272 val = (val >> 2) + 1;
3273 insn |= val & 0x7ffff;
3276 case BFD_RELOC_SPARC_HH22:
3277 val = BSR (val, 32);
3280 case BFD_RELOC_SPARC_LM22:
3281 case BFD_RELOC_HI22:
3282 if (!fixP->fx_addsy)
3283 insn |= (val >> 10) & 0x3fffff;
3285 /* FIXME: Need comment explaining why we do this. */
3289 case BFD_RELOC_SPARC22:
3290 if (val & ~0x003fffff)
3291 as_bad_where (fixP->fx_file, fixP->fx_line,
3292 _("relocation overflow"));
3293 insn |= (val & 0x3fffff);
3296 case BFD_RELOC_SPARC_HM10:
3297 val = BSR (val, 32);
3300 case BFD_RELOC_LO10:
3301 if (!fixP->fx_addsy)
3302 insn |= val & 0x3ff;
3304 /* FIXME: Need comment explaining why we do this. */
3308 case BFD_RELOC_SPARC_OLO10:
3310 val += fixP->tc_fix_data;
3313 case BFD_RELOC_SPARC13:
3314 if (! in_signed_range (val, 0x1fff))
3315 as_bad_where (fixP->fx_file, fixP->fx_line,
3316 _("relocation overflow"));
3317 insn |= val & 0x1fff;
3320 case BFD_RELOC_SPARC_WDISP22:
3321 val = (val >> 2) + 1;
3323 case BFD_RELOC_SPARC_BASE22:
3324 insn |= val & 0x3fffff;
3327 case BFD_RELOC_SPARC_H44:
3328 if (!fixP->fx_addsy)
3332 insn |= tval & 0x3fffff;
3336 case BFD_RELOC_SPARC_M44:
3337 if (!fixP->fx_addsy)
3338 insn |= (val >> 12) & 0x3ff;
3341 case BFD_RELOC_SPARC_L44:
3342 if (!fixP->fx_addsy)
3343 insn |= val & 0xfff;
3346 case BFD_RELOC_SPARC_HIX22:
3347 if (!fixP->fx_addsy)
3349 val ^= ~(offsetT) 0;
3350 insn |= (val >> 10) & 0x3fffff;
3354 case BFD_RELOC_SPARC_LOX10:
3355 if (!fixP->fx_addsy)
3356 insn |= 0x1c00 | (val & 0x3ff);
3359 case BFD_RELOC_NONE:
3361 as_bad_where (fixP->fx_file, fixP->fx_line,
3362 _("bad or unhandled relocation type: 0x%02x"),
3367 if (INSN_BIG_ENDIAN)
3368 bfd_putb32 (insn, (unsigned char *) buf);
3370 bfd_putl32 (insn, (unsigned char *) buf);
3373 /* Are we finished with this relocation now? */
3374 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3378 /* Translate internal representation of relocation info to BFD target
3382 tc_gen_reloc (section, fixp)
3386 static arelent *relocs[3];
3388 bfd_reloc_code_real_type code;
3390 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3393 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3394 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3395 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3397 switch (fixp->fx_r_type)
3401 case BFD_RELOC_HI22:
3402 case BFD_RELOC_LO10:
3403 case BFD_RELOC_32_PCREL_S2:
3404 case BFD_RELOC_SPARC13:
3405 case BFD_RELOC_SPARC22:
3406 case BFD_RELOC_SPARC_PC22:
3407 case BFD_RELOC_SPARC_PC10:
3408 case BFD_RELOC_SPARC_BASE13:
3409 case BFD_RELOC_SPARC_WDISP16:
3410 case BFD_RELOC_SPARC_WDISP19:
3411 case BFD_RELOC_SPARC_WDISP22:
3413 case BFD_RELOC_SPARC_5:
3414 case BFD_RELOC_SPARC_6:
3415 case BFD_RELOC_SPARC_7:
3416 case BFD_RELOC_SPARC_10:
3417 case BFD_RELOC_SPARC_11:
3418 case BFD_RELOC_SPARC_HH22:
3419 case BFD_RELOC_SPARC_HM10:
3420 case BFD_RELOC_SPARC_LM22:
3421 case BFD_RELOC_SPARC_PC_HH22:
3422 case BFD_RELOC_SPARC_PC_HM10:
3423 case BFD_RELOC_SPARC_PC_LM22:
3424 case BFD_RELOC_SPARC_H44:
3425 case BFD_RELOC_SPARC_M44:
3426 case BFD_RELOC_SPARC_L44:
3427 case BFD_RELOC_SPARC_HIX22:
3428 case BFD_RELOC_SPARC_LOX10:
3429 case BFD_RELOC_SPARC_REV32:
3430 case BFD_RELOC_SPARC_OLO10:
3431 case BFD_RELOC_SPARC_UA16:
3432 case BFD_RELOC_SPARC_UA32:
3433 case BFD_RELOC_SPARC_UA64:
3434 case BFD_RELOC_8_PCREL:
3435 case BFD_RELOC_16_PCREL:
3436 case BFD_RELOC_32_PCREL:
3437 case BFD_RELOC_64_PCREL:
3438 case BFD_RELOC_SPARC_PLT32:
3439 case BFD_RELOC_SPARC_PLT64:
3440 case BFD_RELOC_VTABLE_ENTRY:
3441 case BFD_RELOC_VTABLE_INHERIT:
3442 case BFD_RELOC_SPARC_TLS_GD_HI22:
3443 case BFD_RELOC_SPARC_TLS_GD_LO10:
3444 case BFD_RELOC_SPARC_TLS_GD_ADD:
3445 case BFD_RELOC_SPARC_TLS_GD_CALL:
3446 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3447 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3448 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3449 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3450 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3451 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3452 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3453 case BFD_RELOC_SPARC_TLS_IE_HI22:
3454 case BFD_RELOC_SPARC_TLS_IE_LO10:
3455 case BFD_RELOC_SPARC_TLS_IE_LD:
3456 case BFD_RELOC_SPARC_TLS_IE_LDX:
3457 case BFD_RELOC_SPARC_TLS_IE_ADD:
3458 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3459 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3460 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3461 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3462 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3463 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3464 case BFD_RELOC_SPARC_GOTDATA_OP:
3465 code = fixp->fx_r_type;
3472 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3473 /* If we are generating PIC code, we need to generate a different
3477 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3479 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3482 #define GOTT_BASE "__GOTT_BASE__"
3483 #define GOTT_INDEX "__GOTT_INDEX__"
3486 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3492 case BFD_RELOC_32_PCREL_S2:
3493 if (generic_force_reloc (fixp))
3494 code = BFD_RELOC_SPARC_WPLT30;
3496 case BFD_RELOC_HI22:
3497 code = BFD_RELOC_SPARC_GOT22;
3498 if (fixp->fx_addsy != NULL)
3500 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3501 code = BFD_RELOC_SPARC_PC22;
3503 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3504 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3505 code = BFD_RELOC_HI22; /* Unchanged. */
3509 case BFD_RELOC_LO10:
3510 code = BFD_RELOC_SPARC_GOT10;
3511 if (fixp->fx_addsy != NULL)
3513 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3514 code = BFD_RELOC_SPARC_PC10;
3516 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3517 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3518 code = BFD_RELOC_LO10; /* Unchanged. */
3522 case BFD_RELOC_SPARC13:
3523 code = BFD_RELOC_SPARC_GOT13;
3529 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3531 /* Nothing is aligned in DWARF debugging sections. */
3532 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3535 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3536 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3537 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3541 if (code == BFD_RELOC_SPARC_OLO10)
3542 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3544 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3545 if (reloc->howto == 0)
3547 as_bad_where (fixp->fx_file, fixp->fx_line,
3548 _("internal error: can't export reloc type %d (`%s')"),
3549 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3555 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3558 if (reloc->howto->pc_relative == 0
3559 || code == BFD_RELOC_SPARC_PC10
3560 || code == BFD_RELOC_SPARC_PC22)
3561 reloc->addend = fixp->fx_addnumber;
3562 else if (sparc_pic_code
3563 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3564 && fixp->fx_addsy != NULL
3565 && (S_IS_EXTERNAL (fixp->fx_addsy)
3566 || S_IS_WEAK (fixp->fx_addsy))
3567 && S_IS_DEFINED (fixp->fx_addsy)
3568 && ! S_IS_COMMON (fixp->fx_addsy))
3569 reloc->addend = fixp->fx_addnumber;
3571 reloc->addend = fixp->fx_offset - reloc->address;
3573 #else /* elf or coff */
3575 if (code != BFD_RELOC_32_PCREL_S2
3576 && code != BFD_RELOC_SPARC_WDISP22
3577 && code != BFD_RELOC_SPARC_WDISP16
3578 && code != BFD_RELOC_SPARC_WDISP19
3579 && code != BFD_RELOC_SPARC_WPLT30
3580 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3581 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3582 reloc->addend = fixp->fx_addnumber;
3583 else if (symbol_section_p (fixp->fx_addsy))
3584 reloc->addend = (section->vma
3585 + fixp->fx_addnumber
3586 + md_pcrel_from (fixp));
3588 reloc->addend = fixp->fx_offset;
3591 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3592 on the same location. */
3593 if (code == BFD_RELOC_SPARC_OLO10)
3595 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3598 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3600 = symbol_get_bfdsym (section_symbol (absolute_section));
3601 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3602 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3603 reloc->addend = fixp->tc_fix_data;
3609 /* We have no need to default values of symbols. */
3612 md_undefined_symbol (name)
3613 char *name ATTRIBUTE_UNUSED;
3618 /* Round up a section size to the appropriate boundary. */
3621 md_section_align (segment, size)
3622 segT segment ATTRIBUTE_UNUSED;
3626 /* This is not right for ELF; a.out wants it, and COFF will force
3627 the alignment anyways. */
3628 valueT align = ((valueT) 1
3629 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3632 /* Turn alignment value into a mask. */
3634 newsize = (size + align) & ~align;
3641 /* Exactly what point is a PC-relative offset relative TO?
3642 On the sparc, they're relative to the address of the offset, plus
3643 its size. This gets us to the following instruction.
3644 (??? Is this right? FIXME-SOON) */
3646 md_pcrel_from (fixP)
3651 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3652 if (! sparc_pic_code
3653 || fixP->fx_addsy == NULL
3654 || symbol_section_p (fixP->fx_addsy))
3655 ret += fixP->fx_size;
3659 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3671 for (shift = 0; (value & 1) == 0; value >>= 1)
3674 return (value == 1) ? shift : -1;
3677 /* Sort of like s_lcomm. */
3680 static int max_alignment = 15;
3685 int ignore ATTRIBUTE_UNUSED;
3695 name = input_line_pointer;
3696 c = get_symbol_end ();
3697 p = input_line_pointer;
3701 if (*input_line_pointer != ',')
3703 as_bad (_("Expected comma after name"));
3704 ignore_rest_of_line ();
3708 ++input_line_pointer;
3710 if ((size = get_absolute_expression ()) < 0)
3712 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3713 ignore_rest_of_line ();
3718 symbolP = symbol_find_or_make (name);
3721 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3722 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3724 as_bad (_("bad .reserve segment -- expected BSS segment"));
3728 if (input_line_pointer[2] == '.')
3729 input_line_pointer += 7;
3731 input_line_pointer += 6;
3734 if (*input_line_pointer == ',')
3736 ++input_line_pointer;
3739 if (*input_line_pointer == '\n')
3741 as_bad (_("missing alignment"));
3742 ignore_rest_of_line ();
3746 align = (int) get_absolute_expression ();
3749 if (align > max_alignment)
3751 align = max_alignment;
3752 as_warn (_("alignment too large; assuming %d"), align);
3758 as_bad (_("negative alignment"));
3759 ignore_rest_of_line ();
3765 temp = mylog2 (align);
3768 as_bad (_("alignment not a power of 2"));
3769 ignore_rest_of_line ();
3776 record_alignment (bss_section, align);
3781 if (!S_IS_DEFINED (symbolP)
3783 && S_GET_OTHER (symbolP) == 0
3784 && S_GET_DESC (symbolP) == 0
3791 segT current_seg = now_seg;
3792 subsegT current_subseg = now_subseg;
3794 /* Switch to bss. */
3795 subseg_set (bss_section, 1);
3799 frag_align (align, 0, 0);
3801 /* Detach from old frag. */
3802 if (S_GET_SEGMENT (symbolP) == bss_section)
3803 symbol_get_frag (symbolP)->fr_symbol = NULL;
3805 symbol_set_frag (symbolP, frag_now);
3806 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3807 (offsetT) size, (char *) 0);
3810 S_SET_SEGMENT (symbolP, bss_section);
3812 subseg_set (current_seg, current_subseg);
3815 S_SET_SIZE (symbolP, size);
3821 as_warn ("Ignoring attempt to re-define symbol %s",
3822 S_GET_NAME (symbolP));
3823 } /* if not redefining. */
3825 demand_empty_rest_of_line ();
3830 int ignore ATTRIBUTE_UNUSED;
3838 name = input_line_pointer;
3839 c = get_symbol_end ();
3840 /* Just after name is now '\0'. */
3841 p = input_line_pointer;
3844 if (*input_line_pointer != ',')
3846 as_bad (_("Expected comma after symbol-name"));
3847 ignore_rest_of_line ();
3852 input_line_pointer++;
3854 if ((temp = get_absolute_expression ()) < 0)
3856 as_bad (_(".COMMon length (%lu) out of range ignored"),
3857 (unsigned long) temp);
3858 ignore_rest_of_line ();
3863 symbolP = symbol_find_or_make (name);
3865 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3867 as_bad (_("Ignoring attempt to re-define symbol"));
3868 ignore_rest_of_line ();
3871 if (S_GET_VALUE (symbolP) != 0)
3873 if (S_GET_VALUE (symbolP) != (valueT) size)
3875 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3876 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3882 S_SET_VALUE (symbolP, (valueT) size);
3883 S_SET_EXTERNAL (symbolP);
3886 know (symbol_get_frag (symbolP) == &zero_address_frag);
3887 if (*input_line_pointer != ',')
3889 as_bad (_("Expected comma after common length"));
3890 ignore_rest_of_line ();
3893 input_line_pointer++;
3895 if (*input_line_pointer != '"')
3897 temp = get_absolute_expression ();
3900 if (temp > max_alignment)
3902 temp = max_alignment;
3903 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3909 as_bad (_("negative alignment"));
3910 ignore_rest_of_line ();
3915 if (symbol_get_obj (symbolP)->local)
3923 old_subsec = now_subseg;
3928 align = mylog2 (temp);
3932 as_bad (_("alignment not a power of 2"));
3933 ignore_rest_of_line ();
3937 record_alignment (bss_section, align);
3938 subseg_set (bss_section, 0);
3940 frag_align (align, 0, 0);
3941 if (S_GET_SEGMENT (symbolP) == bss_section)
3942 symbol_get_frag (symbolP)->fr_symbol = 0;
3943 symbol_set_frag (symbolP, frag_now);
3944 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3945 (offsetT) size, (char *) 0);
3947 S_SET_SEGMENT (symbolP, bss_section);
3948 S_CLEAR_EXTERNAL (symbolP);
3949 S_SET_SIZE (symbolP, size);
3950 subseg_set (old_sec, old_subsec);
3953 #endif /* OBJ_ELF */
3956 S_SET_VALUE (symbolP, (valueT) size);
3958 S_SET_ALIGN (symbolP, temp);
3959 S_SET_SIZE (symbolP, size);
3961 S_SET_EXTERNAL (symbolP);
3962 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3967 input_line_pointer++;
3968 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3969 if (*input_line_pointer == '.')
3970 input_line_pointer++;
3971 /* @@ Some say data, some say bss. */
3972 if (strncmp (input_line_pointer, "bss\"", 4)
3973 && strncmp (input_line_pointer, "data\"", 5))
3975 while (*--input_line_pointer != '"')
3977 input_line_pointer--;
3978 goto bad_common_segment;
3980 while (*input_line_pointer++ != '"')
3982 goto allocate_common;
3985 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3987 demand_empty_rest_of_line ();
3992 p = input_line_pointer;
3993 while (*p && *p != '\n')
3997 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3999 input_line_pointer = p;
4000 ignore_rest_of_line ();
4005 /* Handle the .empty pseudo-op. This suppresses the warnings about
4006 invalid delay slot usage. */
4010 int ignore ATTRIBUTE_UNUSED;
4012 /* The easy way to implement is to just forget about the last
4019 int ignore ATTRIBUTE_UNUSED;
4022 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4024 input_line_pointer += 6;
4028 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4030 input_line_pointer += 6;
4034 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4036 input_line_pointer += 7;
4040 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4042 input_line_pointer += 5;
4043 /* We only support 2 segments -- text and data -- for now, so
4044 things in the "bss segment" will have to go into data for now.
4045 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4046 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4049 as_bad (_("Unknown segment type"));
4050 demand_empty_rest_of_line ();
4056 subseg_set (data_section, 1);
4057 demand_empty_rest_of_line ();
4062 int ignore ATTRIBUTE_UNUSED;
4064 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4066 ++input_line_pointer;
4068 ++input_line_pointer;
4071 /* This static variable is set by s_uacons to tell sparc_cons_align
4072 that the expression does not need to be aligned. */
4074 static int sparc_no_align_cons = 0;
4076 /* This static variable is set by sparc_cons to emit requested types
4077 of relocations in cons_fix_new_sparc. */
4079 static const char *sparc_cons_special_reloc;
4081 /* This handles the unaligned space allocation pseudo-ops, such as
4082 .uaword. .uaword is just like .word, but the value does not need
4089 /* Tell sparc_cons_align not to align this value. */
4090 sparc_no_align_cons = 1;
4092 sparc_no_align_cons = 0;
4095 /* This handles the native word allocation pseudo-op .nword.
4096 For sparc_arch_size 32 it is equivalent to .word, for
4097 sparc_arch_size 64 it is equivalent to .xword. */
4101 int bytes ATTRIBUTE_UNUSED;
4103 cons (sparc_arch_size == 32 ? 4 : 8);
4107 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4111 .register %g[2367],{#scratch|symbolname|#ignore}
4116 int ignore ATTRIBUTE_UNUSED;
4121 const char *regname;
4123 if (input_line_pointer[0] != '%'
4124 || input_line_pointer[1] != 'g'
4125 || ((input_line_pointer[2] & ~1) != '2'
4126 && (input_line_pointer[2] & ~1) != '6')
4127 || input_line_pointer[3] != ',')
4128 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4129 reg = input_line_pointer[2] - '0';
4130 input_line_pointer += 4;
4132 if (*input_line_pointer == '#')
4134 ++input_line_pointer;
4135 regname = input_line_pointer;
4136 c = get_symbol_end ();
4137 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4138 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4139 if (regname[0] == 'i')
4146 regname = input_line_pointer;
4147 c = get_symbol_end ();
4149 if (sparc_arch_size == 64)
4153 if ((regname && globals[reg] != (symbolS *) 1
4154 && strcmp (S_GET_NAME (globals[reg]), regname))
4155 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4156 as_bad (_("redefinition of global register"));
4160 if (regname == NULL)
4161 globals[reg] = (symbolS *) 1;
4166 if (symbol_find (regname))
4167 as_bad (_("Register symbol %s already defined."),
4170 globals[reg] = symbol_make (regname);
4171 flags = symbol_get_bfdsym (globals[reg])->flags;
4173 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4174 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4175 flags |= BSF_GLOBAL;
4176 symbol_get_bfdsym (globals[reg])->flags = flags;
4177 S_SET_VALUE (globals[reg], (valueT) reg);
4178 S_SET_ALIGN (globals[reg], reg);
4179 S_SET_SIZE (globals[reg], 0);
4180 /* Although we actually want undefined_section here,
4181 we have to use absolute_section, because otherwise
4182 generic as code will make it a COM section.
4183 We fix this up in sparc_adjust_symtab. */
4184 S_SET_SEGMENT (globals[reg], absolute_section);
4185 S_SET_OTHER (globals[reg], 0);
4186 elf_symbol (symbol_get_bfdsym (globals[reg]))
4187 ->internal_elf_sym.st_info =
4188 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4189 elf_symbol (symbol_get_bfdsym (globals[reg]))
4190 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4195 *input_line_pointer = c;
4197 demand_empty_rest_of_line ();
4200 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4201 symbols which need it. */
4204 sparc_adjust_symtab ()
4208 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4210 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4211 ->internal_elf_sym.st_info) != STT_REGISTER)
4214 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4215 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4218 S_SET_SEGMENT (sym, undefined_section);
4223 /* If the --enforce-aligned-data option is used, we require .word,
4224 et. al., to be aligned correctly. We do it by setting up an
4225 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4226 no unexpected alignment was introduced.
4228 The SunOS and Solaris native assemblers enforce aligned data by
4229 default. We don't want to do that, because gcc can deliberately
4230 generate misaligned data if the packed attribute is used. Instead,
4231 we permit misaligned data by default, and permit the user to set an
4232 option to check for it. */
4235 sparc_cons_align (nbytes)
4241 /* Only do this if we are enforcing aligned data. */
4242 if (! enforce_aligned_data)
4245 /* Don't align if this is an unaligned pseudo-op. */
4246 if (sparc_no_align_cons)
4249 nalign = mylog2 (nbytes);
4253 assert (nalign > 0);
4255 if (now_seg == absolute_section)
4257 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4258 as_bad (_("misaligned data"));
4262 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4263 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4265 record_alignment (now_seg, nalign);
4268 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4271 sparc_handle_align (fragp)
4277 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4279 switch (fragp->fr_type)
4283 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4287 p = fragp->fr_literal + fragp->fr_fix;
4298 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4300 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4301 if (INSN_BIG_ENDIAN)
4302 number_to_chars_bigendian (p, wval, 4);
4304 number_to_chars_littleendian (p, wval, 4);
4310 if (INSN_BIG_ENDIAN)
4311 number_to_chars_bigendian (p, 0x01000000, 4);
4313 number_to_chars_littleendian (p, 0x01000000, 4);
4315 fragp->fr_fix += fix;
4325 /* Some special processing for a Sparc ELF file. */
4328 sparc_elf_final_processing ()
4330 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4331 sort of BFD interface for this. */
4332 if (sparc_arch_size == 64)
4334 switch (sparc_memory_model)
4337 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4340 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4346 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4347 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4348 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4349 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4350 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4351 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4355 sparc_cons (exp, size)
4362 sparc_cons_special_reloc = NULL;
4363 save = input_line_pointer;
4364 if (input_line_pointer[0] == '%'
4365 && input_line_pointer[1] == 'r'
4366 && input_line_pointer[2] == '_')
4368 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4370 input_line_pointer += 7;
4371 sparc_cons_special_reloc = "disp";
4373 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4375 if (size != 4 && size != 8)
4376 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4379 input_line_pointer += 6;
4380 sparc_cons_special_reloc = "plt";
4383 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4385 if (size != 4 && size != 8)
4386 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4389 input_line_pointer += 13;
4390 sparc_cons_special_reloc = "tls_dtpoff";
4393 if (sparc_cons_special_reloc)
4400 if (*input_line_pointer != '8')
4402 input_line_pointer--;
4405 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4409 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4413 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4423 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4424 sparc_cons_special_reloc, size * 8, size);
4428 input_line_pointer += 2;
4429 if (*input_line_pointer != '(')
4431 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4432 sparc_cons_special_reloc, size * 8);
4439 input_line_pointer = save;
4440 sparc_cons_special_reloc = NULL;
4445 char *end = ++input_line_pointer;
4448 while (! is_end_of_line[(c = *end)])
4462 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4463 sparc_cons_special_reloc, size * 8);
4469 if (input_line_pointer != end)
4471 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4472 sparc_cons_special_reloc, size * 8);
4476 input_line_pointer++;
4478 c = *input_line_pointer;
4479 if (! is_end_of_line[c] && c != ',')
4480 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4481 sparc_cons_special_reloc, size * 8);
4487 if (sparc_cons_special_reloc == NULL)
4493 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4494 reloc for a cons. We could use the definition there, except that
4495 we want to handle little endian relocs specially. */
4498 cons_fix_new_sparc (frag, where, nbytes, exp)
4501 unsigned int nbytes;
4504 bfd_reloc_code_real_type r;
4506 r = (nbytes == 1 ? BFD_RELOC_8 :
4507 (nbytes == 2 ? BFD_RELOC_16 :
4508 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4510 if (target_little_endian_data
4512 && now_seg->flags & SEC_ALLOC)
4513 r = BFD_RELOC_SPARC_REV32;
4515 if (sparc_cons_special_reloc)
4517 if (*sparc_cons_special_reloc == 'd')
4520 case 1: r = BFD_RELOC_8_PCREL; break;
4521 case 2: r = BFD_RELOC_16_PCREL; break;
4522 case 4: r = BFD_RELOC_32_PCREL; break;
4523 case 8: r = BFD_RELOC_64_PCREL; break;
4526 else if (*sparc_cons_special_reloc == 'p')
4529 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4530 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4535 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4536 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4539 else if (sparc_no_align_cons)
4543 case 2: r = BFD_RELOC_SPARC_UA16; break;
4544 case 4: r = BFD_RELOC_SPARC_UA32; break;
4545 case 8: r = BFD_RELOC_SPARC_UA64; break;
4550 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4551 sparc_cons_special_reloc = NULL;
4555 sparc_cfi_frame_initial_instructions ()
4557 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4561 sparc_regname_to_dw2regnum (char *regname)
4569 p = strchr (q, regname[0]);
4572 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4574 return (p - q) * 8 + regname[1] - '0';
4576 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4578 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4580 if (regname[0] == 'f' || regname[0] == 'r')
4582 unsigned int regnum;
4584 regnum = strtoul (regname + 1, &q, 10);
4587 if (regnum >= ((regname[0] == 'f'
4588 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4591 if (regname[0] == 'f')
4594 if (regnum >= 64 && (regnum & 1))
4603 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4605 sparc_cons_special_reloc = "disp";
4606 sparc_no_align_cons = 1;
4607 emit_expr (exp, nbytes);
4608 sparc_no_align_cons = 0;
4609 sparc_cons_special_reloc = NULL;