1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static struct sparc_arch *lookup_arch PARAMS ((char *));
41 static void init_default_arch PARAMS ((void));
42 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
43 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
44 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
45 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46 static int sparc_ffs PARAMS ((unsigned int));
47 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
48 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
49 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
50 static bfd_vma BSR PARAMS ((bfd_vma, int));
51 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
52 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
53 static int parse_const_expr_arg PARAMS ((char **, int *));
54 static int get_expression PARAMS ((char *str));
56 /* Default architecture. */
57 /* ??? The default value should be V8, but sparclite support was added
58 by making it the default. GCC now passes -Asparclite, so maybe sometime in
59 the future we can set this to V8. */
61 #define DEFAULT_ARCH "sparclite"
63 static char *default_arch = DEFAULT_ARCH;
65 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 static int default_init_p;
69 /* Current architecture. We don't bump up unless necessary. */
70 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
72 /* The maximum architecture level we can bump up to.
73 In a 32 bit environment, don't allow bumping up to v9 by default.
74 The native assembler works this way. The user is required to pass
75 an explicit argument before we'll create v9 object files. However, if
76 we don't see any v9 insns, a v8plus object file is not created. */
77 static enum sparc_opcode_arch_val max_architecture;
79 /* Either 32 or 64, selects file format. */
80 static int sparc_arch_size;
81 /* Initial (default) value, recorded separately in case a user option
82 changes the value before md_show_usage is called. */
83 static int default_arch_size;
86 /* The currently selected v9 memory model. Currently only used for
88 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
91 static int architecture_requested;
92 static int warn_on_bump;
94 /* If warn_on_bump and the needed architecture is higher than this
95 architecture, issue a warning. */
96 static enum sparc_opcode_arch_val warn_after_architecture;
98 /* Non-zero if as should generate error if an undeclared g[23] register
99 has been used in -64. */
100 static int no_undeclared_regs;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data;
111 extern int target_big_endian;
113 static int target_little_endian_data;
115 /* Symbols for global registers on v9. */
116 static symbolS *globals[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control *op_hash;
134 static int mylog2 PARAMS ((int));
135 static void s_data1 PARAMS ((void));
136 static void s_seg PARAMS ((int));
137 static void s_proc PARAMS ((int));
138 static void s_reserve PARAMS ((int));
139 static void s_common PARAMS ((int));
140 static void s_empty PARAMS ((int));
141 static void s_uacons PARAMS ((int));
142 static void s_ncons PARAMS ((int));
144 static void s_register PARAMS ((int));
147 const pseudo_typeS md_pseudo_table[] =
149 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common, 0},
151 {"empty", s_empty, 0},
152 {"global", s_globl, 0},
154 {"nword", s_ncons, 0},
155 {"optim", s_ignore, 0},
157 {"reserve", s_reserve, 0},
159 {"skip", s_space, 0},
162 {"uahalf", s_uacons, 2},
163 {"uaword", s_uacons, 4},
164 {"uaxword", s_uacons, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
170 {"register", s_register, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode;
211 struct nlist *nlistp;
215 bfd_reloc_code_real_type reloc;
218 struct sparc_it the_insn, set_insn;
220 static void output_insn
221 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
223 /* Table of arguments to -A.
224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225 for this use. That table is for opcodes only. This table is for opcodes
228 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
229 v8plusa, v9, v9a, v9b, v9_64};
231 static struct sparc_arch {
234 enum sparc_arch_types arch_type;
235 /* Default word size, as specified during configuration.
236 A value of zero means can't be used to specify default architecture. */
237 int default_arch_size;
238 /* Allowable arg to -A? */
240 } sparc_arch_table[] = {
241 { "v6", "v6", v6, 0, 1 },
242 { "v7", "v7", v7, 0, 1 },
243 { "v8", "v8", v8, 32, 1 },
244 { "sparclet", "sparclet", sparclet, 32, 1 },
245 { "sparclite", "sparclite", sparclite, 32, 1 },
246 { "sparc86x", "sparclite", sparc86x, 32, 1 },
247 { "v8plus", "v9", v9, 0, 1 },
248 { "v8plusa", "v9a", v9, 0, 1 },
249 { "v8plusb", "v9b", v9, 0, 1 },
250 { "v9", "v9", v9, 0, 1 },
251 { "v9a", "v9a", v9, 0, 1 },
252 { "v9b", "v9b", v9, 0, 1 },
253 /* This exists to allow configure.in/Makefile.in to pass one
254 value to specify both the default machine and default word size. */
255 { "v9-64", "v9", v9, 64, 0 },
256 { NULL, NULL, v8, 0, 0 }
259 /* Variant of default_arch */
260 static enum sparc_arch_types default_arch_type;
262 static struct sparc_arch *
266 struct sparc_arch *sa;
268 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
269 if (strcmp (sa->name, name) == 0)
271 if (sa->name == NULL)
276 /* Initialize the default opcode arch and word size from the default
277 architecture name. */
282 struct sparc_arch *sa = lookup_arch (default_arch);
285 || sa->default_arch_size == 0)
286 as_fatal (_("Invalid default architecture, broken assembler."));
288 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
289 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
290 as_fatal (_("Bad opcode table, broken assembler."));
291 default_arch_size = sparc_arch_size = sa->default_arch_size;
293 default_arch_type = sa->arch_type;
296 /* Called by TARGET_FORMAT. */
299 sparc_target_format ()
301 /* We don't get a chance to initialize anything before we're called,
302 so handle that now. */
303 if (! default_init_p)
304 init_default_arch ();
308 return "a.out-sparc-netbsd";
311 if (target_big_endian)
312 return "a.out-sunos-big";
313 else if (default_arch_type == sparc86x && target_little_endian_data)
314 return "a.out-sunos-big";
316 return "a.out-sparc-little";
318 return "a.out-sunos-big";
329 return "coff-sparc-lynx";
336 return "elf32-sparc-vxworks";
340 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
347 * Invocation line includes a switch not recognized by the base assembler.
348 * See if it's a processor-specific option. These are:
351 * Warn on architecture bumps. See also -A.
353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354 * Standard 32 bit architectures.
356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357 * This used to only mean 64 bits, but properly specifying it
358 * complicated gcc's ASM_SPECs, so now opcode selection is
359 * specified orthogonally to word size (except when specifying
360 * the default, but that is an internal implementation detail).
361 * -Av8plus, -Av8plusa, -Av8plusb
362 * Same as -Av9{,a,b}.
363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
366 * -xarch=v9, -xarch=v9a, -xarch=v9b
367 * Same as -Av9{,a,b} -64, for compatibility with Sun's
370 * Select the architecture and possibly the file format.
371 * Instructions or features not supported by the selected
372 * architecture cause fatal errors.
374 * The default is to start at v6, and bump the architecture up
375 * whenever an instruction is seen at a higher level. In 32 bit
376 * environments, v9 is not bumped up to, the user must pass
379 * If -bump is specified, a warning is printing when bumping to
382 * If an architecture is specified, all instructions must match
383 * that architecture. Any higher level instructions are flagged
384 * as errors. Note that in the 32 bit environment specifying
385 * -Av8plus does not automatically create a v8plus object file, a
386 * v9 insn must be seen.
388 * If both an architecture and -bump are specified, the
389 * architecture starts at the specified level, but bumps are
390 * warnings. Note that we can't set `current_architecture' to
391 * the requested level in this case: in the 32 bit environment,
392 * we still must avoid creating v8plus object files unless v9
396 * Bumping between incompatible architectures is always an
397 * error. For example, from sparclite to v9.
401 const char *md_shortopts = "A:K:VQ:sq";
404 const char *md_shortopts = "A:k";
406 const char *md_shortopts = "A:";
409 struct option md_longopts[] = {
410 #define OPTION_BUMP (OPTION_MD_BASE)
411 {"bump", no_argument, NULL, OPTION_BUMP},
412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
413 {"sparc", no_argument, NULL, OPTION_SPARC},
414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
415 {"xarch", required_argument, NULL, OPTION_XARCH},
417 #define OPTION_32 (OPTION_MD_BASE + 3)
418 {"32", no_argument, NULL, OPTION_32},
419 #define OPTION_64 (OPTION_MD_BASE + 4)
420 {"64", no_argument, NULL, OPTION_64},
421 #define OPTION_TSO (OPTION_MD_BASE + 5)
422 {"TSO", no_argument, NULL, OPTION_TSO},
423 #define OPTION_PSO (OPTION_MD_BASE + 6)
424 {"PSO", no_argument, NULL, OPTION_PSO},
425 #define OPTION_RMO (OPTION_MD_BASE + 7)
426 {"RMO", no_argument, NULL, OPTION_RMO},
428 #ifdef SPARC_BIENDIAN
429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
445 {"relax", no_argument, NULL, OPTION_RELAX},
446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
448 {NULL, no_argument, NULL, 0}
451 size_t md_longopts_size = sizeof (md_longopts);
454 md_parse_option (c, arg)
458 /* We don't get a chance to initialize anything before we're called,
459 so handle that now. */
460 if (! default_init_p)
461 init_default_arch ();
467 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
472 if (strncmp (arg, "v9", 2) != 0)
473 md_parse_option (OPTION_32, NULL);
475 md_parse_option (OPTION_64, NULL);
481 struct sparc_arch *sa;
482 enum sparc_opcode_arch_val opcode_arch;
484 sa = lookup_arch (arg);
486 || ! sa->user_option_p)
488 if (c == OPTION_XARCH)
489 as_bad (_("invalid architecture -xarch=%s"), arg);
491 as_bad (_("invalid architecture -A%s"), arg);
495 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
496 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
497 as_fatal (_("Bad opcode table, broken assembler."));
499 max_architecture = opcode_arch;
500 architecture_requested = 1;
505 /* Ignore -sparc, used by SunOS make default .s.o rule. */
508 case OPTION_ENFORCE_ALIGNED_DATA:
509 enforce_aligned_data = 1;
512 #ifdef SPARC_BIENDIAN
513 case OPTION_LITTLE_ENDIAN:
514 target_big_endian = 0;
515 if (default_arch_type != sparclet)
516 as_fatal ("This target does not support -EL");
518 case OPTION_LITTLE_ENDIAN_DATA:
519 target_little_endian_data = 1;
520 target_big_endian = 0;
521 if (default_arch_type != sparc86x
522 && default_arch_type != v9)
523 as_fatal ("This target does not support --little-endian-data");
525 case OPTION_BIG_ENDIAN:
526 target_big_endian = 1;
540 const char **list, **l;
542 sparc_arch_size = c == OPTION_32 ? 32 : 64;
543 list = bfd_target_list ();
544 for (l = list; *l != NULL; l++)
546 if (sparc_arch_size == 32)
548 if (CONST_STRNEQ (*l, "elf32-sparc"))
553 if (CONST_STRNEQ (*l, "elf64-sparc"))
558 as_fatal (_("No compiled in support for %d bit object file format"),
565 sparc_memory_model = MM_TSO;
569 sparc_memory_model = MM_PSO;
573 sparc_memory_model = MM_RMO;
581 /* Qy - do emit .comment
582 Qn - do not emit .comment. */
586 /* Use .stab instead of .stab.excl. */
590 /* quick -- Native assembler does fewer checks. */
594 if (strcmp (arg, "PIC") != 0)
595 as_warn (_("Unrecognized option following -K"));
600 case OPTION_NO_UNDECLARED_REGS:
601 no_undeclared_regs = 1;
604 case OPTION_UNDECLARED_REGS:
605 no_undeclared_regs = 0;
613 case OPTION_NO_RELAX:
625 md_show_usage (stream)
628 const struct sparc_arch *arch;
631 /* We don't get a chance to initialize anything before we're called,
632 so handle that now. */
633 if (! default_init_p)
634 init_default_arch ();
636 fprintf (stream, _("SPARC options:\n"));
638 for (arch = &sparc_arch_table[0]; arch->name; arch++)
640 if (!arch->user_option_p)
642 if (arch != &sparc_arch_table[0])
643 fprintf (stream, " | ");
644 if (column + strlen (arch->name) > 70)
647 fputc ('\n', stream);
649 column += 5 + 2 + strlen (arch->name);
650 fprintf (stream, "-A%s", arch->name);
652 for (arch = &sparc_arch_table[0]; arch->name; arch++)
654 if (!arch->user_option_p)
656 fprintf (stream, " | ");
657 if (column + strlen (arch->name) > 65)
660 fputc ('\n', stream);
662 column += 5 + 7 + strlen (arch->name);
663 fprintf (stream, "-xarch=%s", arch->name);
665 fprintf (stream, _("\n\
666 specify variant of SPARC architecture\n\
667 -bump warn when assembler switches architectures\n\
669 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
670 -relax relax jumps and branches (default)\n\
671 -no-relax avoid changing any jumps and branches\n"));
673 fprintf (stream, _("\
674 -k generate PIC\n"));
677 fprintf (stream, _("\
678 -32 create 32 bit object file\n\
679 -64 create 64 bit object file\n"));
680 fprintf (stream, _("\
681 [default is %d]\n"), default_arch_size);
682 fprintf (stream, _("\
683 -TSO use Total Store Ordering\n\
684 -PSO use Partial Store Ordering\n\
685 -RMO use Relaxed Memory Ordering\n"));
686 fprintf (stream, _("\
687 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
688 fprintf (stream, _("\
689 -KPIC generate PIC\n\
690 -V print assembler version number\n\
691 -undeclared-regs ignore application global register usage without\n\
692 appropriate .register directive (default)\n\
693 -no-undeclared-regs force error on application global register usage\n\
694 without appropriate .register directive\n\
699 #ifdef SPARC_BIENDIAN
700 fprintf (stream, _("\
701 -EL generate code for a little endian machine\n\
702 -EB generate code for a big endian machine\n\
703 --little-endian-data generate code for a machine having big endian\n\
704 instructions and little endian data.\n"));
708 /* Native operand size opcode translation. */
714 } native_op_table[] =
716 {"ldn", "ld", "ldx"},
717 {"ldna", "lda", "ldxa"},
718 {"stn", "st", "stx"},
719 {"stna", "sta", "stxa"},
720 {"slln", "sll", "sllx"},
721 {"srln", "srl", "srlx"},
722 {"sran", "sra", "srax"},
723 {"casn", "cas", "casx"},
724 {"casna", "casa", "casxa"},
725 {"clrn", "clr", "clrx"},
729 /* sparc64 privileged and hyperprivileged registers. */
731 struct priv_reg_entry
737 struct priv_reg_entry priv_reg_table[] =
757 {"", -1}, /* End marker. */
760 struct priv_reg_entry hpriv_reg_table[] =
768 {"", -1}, /* End marker. */
771 /* v9a specific asrs. This table is ordered by initial
772 letter, in reverse. */
774 struct priv_reg_entry v9a_asr_table[] =
777 {"sys_tick_cmpr", 25},
787 {"clear_softint", 21},
788 {"", -1}, /* End marker. */
792 cmp_reg_entry (parg, qarg)
796 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
797 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
799 return strcmp (q->name, p->name);
802 /* This function is called once, at assembler startup time. It should
803 set up all the tables, etc. that the MD part of the assembler will
809 register const char *retval = NULL;
811 register unsigned int i = 0;
813 /* We don't get a chance to initialize anything before md_parse_option
814 is called, and it may not be called, so handle default initialization
815 now if not already done. */
816 if (! default_init_p)
817 init_default_arch ();
819 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
820 op_hash = hash_new ();
822 while (i < (unsigned int) sparc_num_opcodes)
824 const char *name = sparc_opcodes[i].name;
825 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
828 as_bad (_("Internal error: can't hash `%s': %s\n"),
829 sparc_opcodes[i].name, retval);
834 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
836 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
837 sparc_opcodes[i].name, sparc_opcodes[i].args);
842 while (i < (unsigned int) sparc_num_opcodes
843 && !strcmp (sparc_opcodes[i].name, name));
846 for (i = 0; native_op_table[i].name; i++)
848 const struct sparc_opcode *insn;
849 char *name = ((sparc_arch_size == 32)
850 ? native_op_table[i].name32
851 : native_op_table[i].name64);
852 insn = (struct sparc_opcode *) hash_find (op_hash, name);
855 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
856 name, native_op_table[i].name);
861 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
864 as_bad (_("Internal error: can't hash `%s': %s\n"),
865 sparc_opcodes[i].name, retval);
872 as_fatal (_("Broken assembler. No assembly attempted."));
874 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
875 sizeof (priv_reg_table[0]), cmp_reg_entry);
877 /* If -bump, record the architecture level at which we start issuing
878 warnings. The behaviour is different depending upon whether an
879 architecture was explicitly specified. If it wasn't, we issue warnings
880 for all upwards bumps. If it was, we don't start issuing warnings until
881 we need to bump beyond the requested architecture or when we bump between
882 conflicting architectures. */
885 && architecture_requested)
887 /* `max_architecture' records the requested architecture.
888 Issue warnings if we go above it. */
889 warn_after_architecture = max_architecture;
891 /* Find the highest architecture level that doesn't conflict with
892 the requested one. */
893 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
894 max_architecture > warn_after_architecture;
896 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
897 warn_after_architecture))
902 /* Called after all assembly has been done. */
907 unsigned long mach = bfd_mach_sparc;
909 if (sparc_arch_size == 64)
910 switch (current_architecture)
912 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
913 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
914 default: mach = bfd_mach_sparc_v9; break;
917 switch (current_architecture)
919 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
920 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
921 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
922 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
923 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
924 be but for now it is (since that's the way it's always been
928 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
931 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
934 in_signed_range (val, max)
935 bfd_signed_vma val, max;
939 /* Sign-extend the value from the architecture word size, so that
940 0xffffffff is always considered -1 on sparc32. */
941 if (sparc_arch_size == 32)
943 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
944 val = ((val & U0xffffffff) ^ sign) - sign;
953 /* Return non-zero if VAL is in the range 0 to MAX. */
956 in_unsigned_range (val, max)
964 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
965 (e.g. -15 to +31). */
968 in_bitfield_range (val, max)
969 bfd_signed_vma val, max;
975 if (val < ~(max >> 1))
989 for (i = 0; (mask & 1) == 0; ++i)
994 /* Implement big shift right. */
1000 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1001 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1002 return val >> amount;
1005 /* For communication between sparc_ip and get_expression. */
1006 static char *expr_end;
1008 /* Values for `special_case'.
1009 Instructions that require wierd handling because they're longer than
1011 #define SPECIAL_CASE_NONE 0
1012 #define SPECIAL_CASE_SET 1
1013 #define SPECIAL_CASE_SETSW 2
1014 #define SPECIAL_CASE_SETX 3
1015 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1016 #define SPECIAL_CASE_FDIV 4
1018 /* Bit masks of various insns. */
1019 #define NOP_INSN 0x01000000
1020 #define OR_INSN 0x80100000
1021 #define XOR_INSN 0x80180000
1022 #define FMOVS_INSN 0x81A00020
1023 #define SETHI_INSN 0x01000000
1024 #define SLLX_INSN 0x81281000
1025 #define SRA_INSN 0x81380000
1027 /* The last instruction to be assembled. */
1028 static const struct sparc_opcode *last_insn;
1029 /* The assembled opcode of `last_insn'. */
1030 static unsigned long last_opcode;
1032 /* Handle the set and setuw synthetic instructions. */
1035 synthetize_setuw (insn)
1036 const struct sparc_opcode *insn;
1038 int need_hi22_p = 0;
1039 int rd = (the_insn.opcode & RD (~0)) >> 25;
1041 if (the_insn.exp.X_op == O_constant)
1043 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1045 if (sizeof (offsetT) > 4
1046 && (the_insn.exp.X_add_number < 0
1047 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1048 as_warn (_("set: number not in 0..4294967295 range"));
1052 if (sizeof (offsetT) > 4
1053 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1054 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1055 as_warn (_("set: number not in -2147483648..4294967295 range"));
1056 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1060 /* See if operand is absolute and small; skip sethi if so. */
1061 if (the_insn.exp.X_op != O_constant
1062 || the_insn.exp.X_add_number >= (1 << 12)
1063 || the_insn.exp.X_add_number < -(1 << 12))
1065 the_insn.opcode = (SETHI_INSN | RD (rd)
1066 | ((the_insn.exp.X_add_number >> 10)
1067 & (the_insn.exp.X_op == O_constant
1069 the_insn.reloc = (the_insn.exp.X_op != O_constant
1070 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1071 output_insn (insn, &the_insn);
1075 /* See if operand has no low-order bits; skip OR if so. */
1076 if (the_insn.exp.X_op != O_constant
1077 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1080 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1082 | (the_insn.exp.X_add_number
1083 & (the_insn.exp.X_op != O_constant
1084 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1085 the_insn.reloc = (the_insn.exp.X_op != O_constant
1086 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1087 output_insn (insn, &the_insn);
1091 /* Handle the setsw synthetic instruction. */
1094 synthetize_setsw (insn)
1095 const struct sparc_opcode *insn;
1099 rd = (the_insn.opcode & RD (~0)) >> 25;
1101 if (the_insn.exp.X_op != O_constant)
1103 synthetize_setuw (insn);
1105 /* Need to sign extend it. */
1106 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1107 the_insn.reloc = BFD_RELOC_NONE;
1108 output_insn (insn, &the_insn);
1112 if (sizeof (offsetT) > 4
1113 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1114 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1115 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1117 low32 = the_insn.exp.X_add_number;
1121 synthetize_setuw (insn);
1127 the_insn.reloc = BFD_RELOC_NONE;
1128 /* See if operand is absolute and small; skip sethi if so. */
1129 if (low32 < -(1 << 12))
1131 the_insn.opcode = (SETHI_INSN | RD (rd)
1132 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1133 output_insn (insn, &the_insn);
1134 low32 = 0x1c00 | (low32 & 0x3ff);
1135 opc = RS1 (rd) | XOR_INSN;
1138 the_insn.opcode = (opc | RD (rd) | IMMED
1139 | (low32 & 0x1fff));
1140 output_insn (insn, &the_insn);
1143 /* Handle the setsw synthetic instruction. */
1146 synthetize_setx (insn)
1147 const struct sparc_opcode *insn;
1149 int upper32, lower32;
1150 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1151 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1153 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1154 int need_xor10_p = 0;
1156 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1157 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1158 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1161 upper_dstreg = tmpreg;
1162 /* The tmp reg should not be the dst reg. */
1163 if (tmpreg == dstreg)
1164 as_warn (_("setx: temporary register same as destination register"));
1166 /* ??? Obviously there are other optimizations we can do
1167 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1168 doing some of these. Later. If you do change things, try to
1169 change all of this to be table driven as well. */
1170 /* What to output depends on the number if it's constant.
1171 Compute that first, then output what we've decided upon. */
1172 if (the_insn.exp.X_op != O_constant)
1174 if (sparc_arch_size == 32)
1176 /* When arch size is 32, we want setx to be equivalent
1177 to setuw for anything but constants. */
1178 the_insn.exp.X_add_number &= 0xffffffff;
1179 synthetize_setuw (insn);
1182 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1188 /* Reset X_add_number, we've extracted it as upper32/lower32.
1189 Otherwise fixup_segment will complain about not being able to
1190 write an 8 byte number in a 4 byte field. */
1191 the_insn.exp.X_add_number = 0;
1193 /* Only need hh22 if `or' insn can't handle constant. */
1194 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1197 /* Does bottom part (after sethi) have bits? */
1198 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1199 /* No hh22, but does upper32 still have bits we can't set
1201 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1204 /* If the lower half is all zero, we build the upper half directly
1205 into the dst reg. */
1207 /* Need lower half if number is zero or 0xffffffff00000000. */
1208 || (! need_hh22_p && ! need_hm10_p))
1210 /* No need for sethi if `or' insn can handle constant. */
1211 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1212 /* Note that we can't use a negative constant in the `or'
1213 insn unless the upper 32 bits are all ones. */
1214 || (lower32 < 0 && upper32 != -1)
1215 || (lower32 >= 0 && upper32 == -1))
1218 if (need_hi22_p && upper32 == -1)
1221 /* Does bottom part (after sethi) have bits? */
1222 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1224 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1225 /* Need `or' if we didn't set anything else. */
1226 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1230 /* Output directly to dst reg if lower 32 bits are all zero. */
1231 upper_dstreg = dstreg;
1234 if (!upper_dstreg && dstreg)
1235 as_warn (_("setx: illegal temporary register g0"));
1239 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1240 | ((upper32 >> 10) & 0x3fffff));
1241 the_insn.reloc = (the_insn.exp.X_op != O_constant
1242 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1243 output_insn (insn, &the_insn);
1248 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1249 | (((need_xor10_p ? ~lower32 : lower32)
1250 >> 10) & 0x3fffff));
1251 the_insn.reloc = (the_insn.exp.X_op != O_constant
1252 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1253 output_insn (insn, &the_insn);
1258 the_insn.opcode = (OR_INSN
1259 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1262 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1263 the_insn.reloc = (the_insn.exp.X_op != O_constant
1264 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1265 output_insn (insn, &the_insn);
1270 /* FIXME: One nice optimization to do here is to OR the low part
1271 with the highpart if hi22 isn't needed and the low part is
1273 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1276 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1277 the_insn.reloc = (the_insn.exp.X_op != O_constant
1278 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1279 output_insn (insn, &the_insn);
1282 /* If we needed to build the upper part, shift it into place. */
1283 if (need_hh22_p || need_hm10_p)
1285 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1287 the_insn.reloc = BFD_RELOC_NONE;
1288 output_insn (insn, &the_insn);
1291 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1294 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1295 | 0x1c00 | (lower32 & 0x3ff));
1296 the_insn.reloc = BFD_RELOC_NONE;
1297 output_insn (insn, &the_insn);
1300 /* If we needed to build both upper and lower parts, OR them together. */
1301 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1303 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1305 the_insn.reloc = BFD_RELOC_NONE;
1306 output_insn (insn, &the_insn);
1310 /* Main entry point to assemble one instruction. */
1316 const struct sparc_opcode *insn;
1320 special_case = sparc_ip (str, &insn);
1324 /* We warn about attempts to put a floating point branch in a delay slot,
1325 unless the delay slot has been annulled. */
1326 if (last_insn != NULL
1327 && (insn->flags & F_FBR) != 0
1328 && (last_insn->flags & F_DELAYED) != 0
1329 /* ??? This test isn't completely accurate. We assume anything with
1330 F_{UNBR,CONDBR,FBR} set is annullable. */
1331 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1332 || (last_opcode & ANNUL) == 0))
1333 as_warn (_("FP branch in delay slot"));
1335 /* SPARC before v9 requires a nop instruction between a floating
1336 point instruction and a floating point branch. We insert one
1337 automatically, with a warning. */
1338 if (max_architecture < SPARC_OPCODE_ARCH_V9
1339 && last_insn != NULL
1340 && (insn->flags & F_FBR) != 0
1341 && (last_insn->flags & F_FLOAT) != 0)
1343 struct sparc_it nop_insn;
1345 nop_insn.opcode = NOP_INSN;
1346 nop_insn.reloc = BFD_RELOC_NONE;
1347 output_insn (insn, &nop_insn);
1348 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1351 switch (special_case)
1353 case SPECIAL_CASE_NONE:
1355 output_insn (insn, &the_insn);
1358 case SPECIAL_CASE_SETSW:
1359 synthetize_setsw (insn);
1362 case SPECIAL_CASE_SET:
1363 synthetize_setuw (insn);
1366 case SPECIAL_CASE_SETX:
1367 synthetize_setx (insn);
1370 case SPECIAL_CASE_FDIV:
1372 int rd = (the_insn.opcode >> 25) & 0x1f;
1374 output_insn (insn, &the_insn);
1376 /* According to information leaked from Sun, the "fdiv" instructions
1377 on early SPARC machines would produce incorrect results sometimes.
1378 The workaround is to add an fmovs of the destination register to
1379 itself just after the instruction. This was true on machines
1380 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1381 assert (the_insn.reloc == BFD_RELOC_NONE);
1382 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1383 output_insn (insn, &the_insn);
1388 as_fatal (_("failed special case insn sanity check"));
1392 /* Subroutine of md_assemble to do the actual parsing. */
1395 sparc_ip (str, pinsn)
1397 const struct sparc_opcode **pinsn;
1399 char *error_message = "";
1403 const struct sparc_opcode *insn;
1405 unsigned long opcode;
1406 unsigned int mask = 0;
1410 int special_case = SPECIAL_CASE_NONE;
1417 while (ISLOWER (*s) || ISDIGIT (*s));
1434 as_bad (_("Unknown opcode: `%s'"), str);
1436 return special_case;
1438 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1442 as_bad (_("Unknown opcode: `%s'"), str);
1443 return special_case;
1453 opcode = insn->match;
1454 memset (&the_insn, '\0', sizeof (the_insn));
1455 the_insn.reloc = BFD_RELOC_NONE;
1458 /* Build the opcode, checking as we go to make sure that the
1460 for (args = insn->args;; ++args)
1468 /* Parse a series of masks. */
1475 if (! parse_keyword_arg (sparc_encode_membar, &s,
1478 error_message = _(": invalid membar mask name");
1484 if (*s == '|' || *s == '+')
1492 if (! parse_const_expr_arg (&s, &kmask))
1494 error_message = _(": invalid membar mask expression");
1497 if (kmask < 0 || kmask > 127)
1499 error_message = _(": invalid membar mask number");
1504 opcode |= MEMBAR (kmask);
1512 if (! parse_const_expr_arg (&s, &smask))
1514 error_message = _(": invalid siam mode expression");
1517 if (smask < 0 || smask > 7)
1519 error_message = _(": invalid siam mode number");
1530 /* Parse a prefetch function. */
1533 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1535 error_message = _(": invalid prefetch function name");
1541 if (! parse_const_expr_arg (&s, &fcn))
1543 error_message = _(": invalid prefetch function expression");
1546 if (fcn < 0 || fcn > 31)
1548 error_message = _(": invalid prefetch function number");
1558 /* Parse a sparc64 privileged register. */
1561 struct priv_reg_entry *p = priv_reg_table;
1562 unsigned int len = 9999999; /* Init to make gcc happy. */
1565 while (p->name[0] > s[0])
1567 while (p->name[0] == s[0])
1569 len = strlen (p->name);
1570 if (strncmp (p->name, s, len) == 0)
1574 if (p->name[0] != s[0])
1576 error_message = _(": unrecognizable privileged register");
1580 opcode |= (p->regnum << 14);
1582 opcode |= (p->regnum << 25);
1588 error_message = _(": unrecognizable privileged register");
1594 /* Parse a sparc64 hyperprivileged register. */
1597 struct priv_reg_entry *p = hpriv_reg_table;
1598 unsigned int len = 9999999; /* Init to make gcc happy. */
1601 while (p->name[0] > s[0])
1603 while (p->name[0] == s[0])
1605 len = strlen (p->name);
1606 if (strncmp (p->name, s, len) == 0)
1610 if (p->name[0] != s[0])
1612 error_message = _(": unrecognizable hyperprivileged register");
1616 opcode |= (p->regnum << 14);
1618 opcode |= (p->regnum << 25);
1624 error_message = _(": unrecognizable hyperprivileged register");
1630 /* Parse a v9a/v9b ancillary state register. */
1633 struct priv_reg_entry *p = v9a_asr_table;
1634 unsigned int len = 9999999; /* Init to make gcc happy. */
1637 while (p->name[0] > s[0])
1639 while (p->name[0] == s[0])
1641 len = strlen (p->name);
1642 if (strncmp (p->name, s, len) == 0)
1646 if (p->name[0] != s[0])
1648 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1651 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1653 error_message = _(": rd on write only ancillary state register");
1657 && (insn->architecture
1658 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1660 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1661 error_message = _(": unrecognizable v9a ancillary state register");
1665 opcode |= (p->regnum << 14);
1667 opcode |= (p->regnum << 25);
1673 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1679 if (strncmp (s, "%asr", 4) == 0)
1687 while (ISDIGIT (*s))
1689 num = num * 10 + *s - '0';
1693 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1695 if (num < 16 || 31 < num)
1697 error_message = _(": asr number must be between 16 and 31");
1703 if (num < 0 || 31 < num)
1705 error_message = _(": asr number must be between 0 and 31");
1710 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1715 error_message = _(": expecting %asrN");
1722 the_insn.reloc = BFD_RELOC_SPARC_11;
1726 the_insn.reloc = BFD_RELOC_SPARC_10;
1730 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1731 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1732 the_insn.reloc = BFD_RELOC_SPARC_5;
1734 the_insn.reloc = BFD_RELOC_SPARC13;
1735 /* These fields are unsigned, but for upward compatibility,
1736 allow negative values as well. */
1740 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1741 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1742 the_insn.reloc = BFD_RELOC_SPARC_6;
1744 the_insn.reloc = BFD_RELOC_SPARC13;
1745 /* These fields are unsigned, but for upward compatibility,
1746 allow negative values as well. */
1750 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1755 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1760 if (*s == 'p' && s[1] == 'n')
1768 if (*s == 'p' && s[1] == 't')
1780 if (strncmp (s, "%icc", 4) == 0)
1792 if (strncmp (s, "%xcc", 4) == 0)
1804 if (strncmp (s, "%fcc0", 5) == 0)
1816 if (strncmp (s, "%fcc1", 5) == 0)
1828 if (strncmp (s, "%fcc2", 5) == 0)
1840 if (strncmp (s, "%fcc3", 5) == 0)
1848 if (strncmp (s, "%pc", 3) == 0)
1856 if (strncmp (s, "%tick", 5) == 0)
1863 case '\0': /* End of args. */
1864 if (s[0] == ',' && s[1] == '%')
1866 static const struct ops
1868 /* The name as it appears in assembler. */
1870 /* strlen (name), precomputed for speed */
1872 /* The reloc this pseudo-op translates to. */
1874 /* 1 if tls call. */
1879 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1880 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1881 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1882 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1883 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1884 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1885 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1886 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1887 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
1890 const struct ops *o;
1894 for (o = ops; o->name; o++)
1895 if (strncmp (s + 2, o->name, o->len) == 0)
1897 if (o->name == NULL)
1900 if (s[o->len + 2] != '(')
1902 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1903 return special_case;
1906 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
1908 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1910 return special_case;
1914 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1915 || the_insn.exp.X_add_number != 0
1916 || the_insn.exp.X_add_symbol
1917 != symbol_find_or_make ("__tls_get_addr")))
1919 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1921 return special_case;
1924 the_insn.reloc = o->reloc;
1925 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1928 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1931 else if (*s1 == ')')
1940 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1941 return special_case;
1945 (void) get_expression (s);
1965 case '[': /* These must match exactly. */
1973 case '#': /* Must be at least one digit. */
1976 while (ISDIGIT (*s))
1984 case 'C': /* Coprocessor state register. */
1985 if (strncmp (s, "%csr", 4) == 0)
1992 case 'b': /* Next operand is a coprocessor register. */
1995 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2000 mask = 10 * (mask - '0') + (*s++ - '0');
2014 opcode |= mask << 14;
2022 opcode |= mask << 25;
2028 case 'r': /* next operand must be a register */
2038 case 'f': /* frame pointer */
2046 case 'g': /* global register */
2055 case 'i': /* in register */
2059 mask = c - '0' + 24;
2064 case 'l': /* local register */
2068 mask = (c - '0' + 16);
2073 case 'o': /* out register */
2077 mask = (c - '0' + 8);
2082 case 's': /* stack pointer */
2090 case 'r': /* any register */
2091 if (!ISDIGIT ((c = *s++)))
2108 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2124 if ((mask & ~1) == 2 && sparc_arch_size == 64
2125 && no_undeclared_regs && ! globals[mask])
2126 as_bad (_("detected global register use not covered by .register pseudo-op"));
2128 /* Got the register, now figure out where
2129 it goes in the opcode. */
2133 opcode |= mask << 14;
2141 opcode |= mask << 25;
2145 opcode |= (mask << 25) | (mask << 14);
2149 opcode |= (mask << 25) | (mask << 0);
2155 case 'e': /* next operand is a floating point register */
2170 && ((format = *s) == 'f')
2173 for (mask = 0; ISDIGIT (*s); ++s)
2175 mask = 10 * mask + (*s - '0');
2176 } /* read the number */
2184 } /* register must be even numbered */
2192 } /* register must be multiple of 4 */
2196 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2197 error_message = _(": There are only 64 f registers; [0-63]");
2199 error_message = _(": There are only 32 f registers; [0-31]");
2202 else if (mask >= 32)
2204 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2206 if (*args == 'e' || *args == 'f' || *args == 'g')
2209 = _(": There are only 32 single precision f registers; [0-31]");
2213 mask -= 31; /* wrap high bit */
2217 error_message = _(": There are only 32 f registers; [0-31]");
2225 } /* if not an 'f' register. */
2232 opcode |= RS1 (mask);
2238 opcode |= RS2 (mask);
2244 opcode |= RD (mask);
2253 if (strncmp (s, "%fsr", 4) == 0)
2260 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2261 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2264 case 'l': /* 22 bit PC relative immediate */
2265 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2269 case 'L': /* 30 bit immediate */
2270 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2275 case 'n': /* 22 bit immediate */
2276 the_insn.reloc = BFD_RELOC_SPARC22;
2279 case 'i': /* 13 bit immediate */
2280 the_insn.reloc = BFD_RELOC_SPARC13;
2290 char *op_arg = NULL;
2291 static expressionS op_exp;
2292 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2294 /* Check for %hi, etc. */
2297 static const struct ops {
2298 /* The name as it appears in assembler. */
2300 /* strlen (name), precomputed for speed */
2302 /* The reloc this pseudo-op translates to. */
2304 /* Non-zero if for v9 only. */
2306 /* Non-zero if can be used in pc-relative contexts. */
2307 int pcrel_p;/*FIXME:wip*/
2309 /* hix/lox must appear before hi/lo so %hix won't be
2310 mistaken for %hi. */
2311 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2312 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2313 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2314 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2315 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2316 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2317 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2318 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2319 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2320 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2321 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2322 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2323 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2324 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2325 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2326 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2327 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2328 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2329 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2331 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2333 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2334 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2335 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2336 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2337 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2339 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2341 { NULL, 0, 0, 0, 0 }
2343 const struct ops *o;
2345 for (o = ops; o->name; o++)
2346 if (strncmp (s + 1, o->name, o->len) == 0)
2348 if (o->name == NULL)
2351 if (s[o->len + 1] != '(')
2353 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2354 return special_case;
2358 the_insn.reloc = o->reloc;
2363 /* Note that if the get_expression() fails, we will still
2364 have created U entries in the symbol table for the
2365 'symbols' in the input string. Try not to create U
2366 symbols for registers, etc. */
2368 /* This stuff checks to see if the expression ends in
2369 +%reg. If it does, it removes the register from
2370 the expression, and re-sets 's' to point to the
2377 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2380 else if (*s1 == ')')
2389 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2390 return special_case;
2394 (void) get_expression (s);
2397 if (*s == ',' || *s == ']' || !*s)
2399 if (*s != '+' && *s != '-')
2401 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2402 return special_case;
2406 op_exp = the_insn.exp;
2407 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2410 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2413 if (s1 != s && ISDIGIT (s1[-1]))
2415 if (s1[-2] == '%' && s1[-3] == '+')
2417 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2424 if (op_arg && s1 == s + 1)
2425 the_insn.exp.X_op = O_absent;
2427 (void) get_expression (s);
2439 (void) get_expression (s);
2447 the_insn.exp2 = the_insn.exp;
2448 the_insn.exp = op_exp;
2449 if (the_insn.exp2.X_op == O_absent)
2450 the_insn.exp2.X_op = O_illegal;
2451 else if (the_insn.exp.X_op == O_absent)
2453 the_insn.exp = the_insn.exp2;
2454 the_insn.exp2.X_op = O_illegal;
2456 else if (the_insn.exp.X_op == O_constant)
2458 valueT val = the_insn.exp.X_add_number;
2459 switch (the_insn.reloc)
2464 case BFD_RELOC_SPARC_HH22:
2465 val = BSR (val, 32);
2468 case BFD_RELOC_SPARC_LM22:
2469 case BFD_RELOC_HI22:
2470 val = (val >> 10) & 0x3fffff;
2473 case BFD_RELOC_SPARC_HM10:
2474 val = BSR (val, 32);
2477 case BFD_RELOC_LO10:
2481 case BFD_RELOC_SPARC_H44:
2486 case BFD_RELOC_SPARC_M44:
2491 case BFD_RELOC_SPARC_L44:
2495 case BFD_RELOC_SPARC_HIX22:
2497 val = (val >> 10) & 0x3fffff;
2500 case BFD_RELOC_SPARC_LOX10:
2501 val = (val & 0x3ff) | 0x1c00;
2504 the_insn.exp = the_insn.exp2;
2505 the_insn.exp.X_add_number += val;
2506 the_insn.exp2.X_op = O_illegal;
2507 the_insn.reloc = old_reloc;
2509 else if (the_insn.exp2.X_op != O_constant)
2511 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2512 return special_case;
2516 if (old_reloc != BFD_RELOC_SPARC13
2517 || the_insn.reloc != BFD_RELOC_LO10
2518 || sparc_arch_size != 64
2521 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2522 return special_case;
2524 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2528 /* Check for constants that don't require emitting a reloc. */
2529 if (the_insn.exp.X_op == O_constant
2530 && the_insn.exp.X_add_symbol == 0
2531 && the_insn.exp.X_op_symbol == 0)
2533 /* For pc-relative call instructions, we reject
2534 constants to get better code. */
2536 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2537 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2539 error_message = _(": PC-relative operand can't be a constant");
2543 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2544 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2546 error_message = _(": TLS operand can't be a constant");
2550 /* Constants that won't fit are checked in md_apply_fix
2551 and bfd_install_relocation.
2552 ??? It would be preferable to install the constants
2553 into the insn here and save having to create a fixS
2554 for each one. There already exists code to handle
2555 all the various cases (e.g. in md_apply_fix and
2556 bfd_install_relocation) so duplicating all that code
2557 here isn't right. */
2577 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2579 error_message = _(": invalid ASI name");
2585 if (! parse_const_expr_arg (&s, &asi))
2587 error_message = _(": invalid ASI expression");
2590 if (asi < 0 || asi > 255)
2592 error_message = _(": invalid ASI number");
2596 opcode |= ASI (asi);
2598 } /* Alternate space. */
2601 if (strncmp (s, "%psr", 4) == 0)
2608 case 'q': /* Floating point queue. */
2609 if (strncmp (s, "%fq", 3) == 0)
2616 case 'Q': /* Coprocessor queue. */
2617 if (strncmp (s, "%cq", 3) == 0)
2625 if (strcmp (str, "set") == 0
2626 || strcmp (str, "setuw") == 0)
2628 special_case = SPECIAL_CASE_SET;
2631 else if (strcmp (str, "setsw") == 0)
2633 special_case = SPECIAL_CASE_SETSW;
2636 else if (strcmp (str, "setx") == 0)
2638 special_case = SPECIAL_CASE_SETX;
2641 else if (strncmp (str, "fdiv", 4) == 0)
2643 special_case = SPECIAL_CASE_FDIV;
2649 if (strncmp (s, "%asi", 4) != 0)
2655 if (strncmp (s, "%fprs", 5) != 0)
2661 if (strncmp (s, "%ccr", 4) != 0)
2667 if (strncmp (s, "%tbr", 4) != 0)
2673 if (strncmp (s, "%wim", 4) != 0)
2680 char *push = input_line_pointer;
2683 input_line_pointer = s;
2685 if (e.X_op == O_constant)
2687 int n = e.X_add_number;
2688 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2689 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2691 opcode |= e.X_add_number << 5;
2694 as_bad (_("non-immediate OPF operand, ignored"));
2695 s = input_line_pointer;
2696 input_line_pointer = push;
2701 if (strncmp (s, "%y", 2) != 0)
2709 /* Parse a sparclet cpreg. */
2711 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2713 error_message = _(": invalid cpreg name");
2716 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2721 as_fatal (_("failed sanity check."));
2722 } /* switch on arg code. */
2724 /* Break out of for() loop. */
2726 } /* For each arg that we expect. */
2731 /* Args don't match. */
2732 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2733 && (insn->name == insn[1].name
2734 || !strcmp (insn->name, insn[1].name)))
2742 as_bad (_("Illegal operands%s"), error_message);
2743 return special_case;
2748 /* We have a match. Now see if the architecture is OK. */
2749 int needed_arch_mask = insn->architecture;
2754 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2755 if (! needed_arch_mask)
2757 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2760 if (needed_arch_mask
2761 & SPARC_OPCODE_SUPPORTED (current_architecture))
2764 /* Can we bump up the architecture? */
2765 else if (needed_arch_mask
2766 & SPARC_OPCODE_SUPPORTED (max_architecture))
2768 enum sparc_opcode_arch_val needed_architecture =
2769 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2770 & needed_arch_mask);
2772 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2774 && needed_architecture > warn_after_architecture)
2776 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2777 sparc_opcode_archs[current_architecture].name,
2778 sparc_opcode_archs[needed_architecture].name,
2780 warn_after_architecture = needed_architecture;
2782 current_architecture = needed_architecture;
2785 /* ??? This seems to be a bit fragile. What if the next entry in
2786 the opcode table is the one we want and it is supported?
2787 It is possible to arrange the table today so that this can't
2788 happen but what about tomorrow? */
2791 int arch, printed_one_p = 0;
2793 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2795 /* Create a list of the architectures that support the insn. */
2796 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2798 arch = sparc_ffs (needed_arch_mask);
2799 while ((1 << arch) <= needed_arch_mask)
2801 if ((1 << arch) & needed_arch_mask)
2805 strcpy (p, sparc_opcode_archs[arch].name);
2812 as_bad (_("Architecture mismatch on \"%s\"."), str);
2813 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2815 sparc_opcode_archs[max_architecture].name);
2816 return special_case;
2818 } /* If no match. */
2821 } /* Forever looking for a match. */
2823 the_insn.opcode = opcode;
2824 return special_case;
2827 /* Parse an argument that can be expressed as a keyword.
2828 (eg: #StoreStore or %ccfr).
2829 The result is a boolean indicating success.
2830 If successful, INPUT_POINTER is updated. */
2833 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2834 int (*lookup_fn) PARAMS ((const char *));
2835 char **input_pointerP;
2841 p = *input_pointerP;
2842 for (q = p + (*p == '#' || *p == '%');
2843 ISALNUM (*q) || *q == '_';
2848 value = (*lookup_fn) (p);
2853 *input_pointerP = q;
2857 /* Parse an argument that is a constant expression.
2858 The result is a boolean indicating success. */
2861 parse_const_expr_arg (input_pointerP, valueP)
2862 char **input_pointerP;
2865 char *save = input_line_pointer;
2868 input_line_pointer = *input_pointerP;
2869 /* The next expression may be something other than a constant
2870 (say if we're not processing the right variant of the insn).
2871 Don't call expression unless we're sure it will succeed as it will
2872 signal an error (which we want to defer until later). */
2873 /* FIXME: It might be better to define md_operand and have it recognize
2874 things like %asi, etc. but continuing that route through to the end
2875 is a lot of work. */
2876 if (*input_line_pointer == '%')
2878 input_line_pointer = save;
2882 *input_pointerP = input_line_pointer;
2883 input_line_pointer = save;
2884 if (exp.X_op != O_constant)
2886 *valueP = exp.X_add_number;
2890 /* Subroutine of sparc_ip to parse an expression. */
2893 get_expression (str)
2899 save_in = input_line_pointer;
2900 input_line_pointer = str;
2901 seg = expression (&the_insn.exp);
2902 if (seg != absolute_section
2903 && seg != text_section
2904 && seg != data_section
2905 && seg != bss_section
2906 && seg != undefined_section)
2908 the_insn.error = _("bad segment");
2909 expr_end = input_line_pointer;
2910 input_line_pointer = save_in;
2913 expr_end = input_line_pointer;
2914 input_line_pointer = save_in;
2918 /* Subroutine of md_assemble to output one insn. */
2921 output_insn (insn, the_insn)
2922 const struct sparc_opcode *insn;
2923 struct sparc_it *the_insn;
2925 char *toP = frag_more (4);
2927 /* Put out the opcode. */
2928 if (INSN_BIG_ENDIAN)
2929 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2931 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2933 /* Put out the symbol-dependent stuff. */
2934 if (the_insn->reloc != BFD_RELOC_NONE)
2936 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2937 (toP - frag_now->fr_literal), /* Where. */
2942 /* Turn off overflow checking in fixup_segment. We'll do our
2943 own overflow checking in md_apply_fix. This is necessary because
2944 the insn size is 4 and fixup_segment will signal an overflow for
2945 large 8 byte quantities. */
2946 fixP->fx_no_overflow = 1;
2947 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2948 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2952 last_opcode = the_insn->opcode;
2955 dwarf2_emit_insn (4);
2960 md_atof (int type, char *litP, int *sizeP)
2962 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2965 /* Write a value out to the object file, using the appropriate
2969 md_number_to_chars (buf, val, n)
2974 if (target_big_endian)
2975 number_to_chars_bigendian (buf, val, n);
2976 else if (target_little_endian_data
2977 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2978 /* Output debug words, which are not in allocated sections, as big
2980 number_to_chars_bigendian (buf, val, n);
2981 else if (target_little_endian_data || ! target_big_endian)
2982 number_to_chars_littleendian (buf, val, n);
2985 /* Apply a fixS to the frags, now that we know the value it ought to
2989 md_apply_fix (fixP, valP, segment)
2992 segT segment ATTRIBUTE_UNUSED;
2994 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2995 offsetT val = * (offsetT *) valP;
2998 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3000 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3003 /* SPARC ELF relocations don't use an addend in the data field. */
3004 if (fixP->fx_addsy != NULL)
3006 switch (fixP->fx_r_type)
3008 case BFD_RELOC_SPARC_TLS_GD_HI22:
3009 case BFD_RELOC_SPARC_TLS_GD_LO10:
3010 case BFD_RELOC_SPARC_TLS_GD_ADD:
3011 case BFD_RELOC_SPARC_TLS_GD_CALL:
3012 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3013 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3014 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3015 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3016 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3017 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3018 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3019 case BFD_RELOC_SPARC_TLS_IE_HI22:
3020 case BFD_RELOC_SPARC_TLS_IE_LO10:
3021 case BFD_RELOC_SPARC_TLS_IE_LD:
3022 case BFD_RELOC_SPARC_TLS_IE_LDX:
3023 case BFD_RELOC_SPARC_TLS_IE_ADD:
3024 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3025 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3026 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3027 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3028 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3029 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3030 case BFD_RELOC_SPARC_TLS_TPOFF32:
3031 case BFD_RELOC_SPARC_TLS_TPOFF64:
3032 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3042 /* This is a hack. There should be a better way to
3043 handle this. Probably in terms of howto fields, once
3044 we can look at these fixups in terms of howtos. */
3045 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3046 val += fixP->fx_where + fixP->fx_frag->fr_address;
3049 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3050 generate a reloc, then we just want to let the reloc addend set
3051 the value. We do not want to also stuff the addend into the
3052 object file. Including the addend in the object file works when
3053 doing a static link, because the linker will ignore the object
3054 file contents. However, the dynamic linker does not ignore the
3055 object file contents. */
3056 if (fixP->fx_addsy != NULL
3057 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3060 /* When generating PIC code, we do not want an addend for a reloc
3061 against a local symbol. We adjust fx_addnumber to cancel out the
3062 value already included in val, and to also cancel out the
3063 adjustment which bfd_install_relocation will create. */
3065 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3066 && fixP->fx_addsy != NULL
3067 && ! S_IS_COMMON (fixP->fx_addsy)
3068 && symbol_section_p (fixP->fx_addsy))
3069 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3071 /* When generating PIC code, we need to fiddle to get
3072 bfd_install_relocation to do the right thing for a PC relative
3073 reloc against a local symbol which we are going to keep. */
3075 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3076 && fixP->fx_addsy != NULL
3077 && (S_IS_EXTERNAL (fixP->fx_addsy)
3078 || S_IS_WEAK (fixP->fx_addsy))
3079 && S_IS_DEFINED (fixP->fx_addsy)
3080 && ! S_IS_COMMON (fixP->fx_addsy))
3083 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3087 /* If this is a data relocation, just output VAL. */
3089 if (fixP->fx_r_type == BFD_RELOC_16
3090 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3092 md_number_to_chars (buf, val, 2);
3094 else if (fixP->fx_r_type == BFD_RELOC_32
3095 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3096 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3098 md_number_to_chars (buf, val, 4);
3100 else if (fixP->fx_r_type == BFD_RELOC_64
3101 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3103 md_number_to_chars (buf, val, 8);
3105 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3106 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3113 /* It's a relocation against an instruction. */
3115 if (INSN_BIG_ENDIAN)
3116 insn = bfd_getb32 ((unsigned char *) buf);
3118 insn = bfd_getl32 ((unsigned char *) buf);
3120 switch (fixP->fx_r_type)
3122 case BFD_RELOC_32_PCREL_S2:
3124 /* FIXME: This increment-by-one deserves a comment of why it's
3126 if (! sparc_pic_code
3127 || fixP->fx_addsy == NULL
3128 || symbol_section_p (fixP->fx_addsy))
3131 insn |= val & 0x3fffffff;
3133 /* See if we have a delay slot. */
3134 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3138 #define XCC (2 << 20)
3139 #define COND(x) (((x)&0xf)<<25)
3140 #define CONDA COND(0x8)
3141 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3142 #define INSN_BA (F2(0,2) | CONDA)
3143 #define INSN_OR F3(2, 0x2, 0)
3144 #define INSN_NOP F2(0,4)
3148 /* If the instruction is a call with either:
3150 arithmetic instruction with rd == %o7
3151 where rs1 != %o7 and rs2 if it is register != %o7
3152 then we can optimize if the call destination is near
3153 by changing the call into a branch always. */
3154 if (INSN_BIG_ENDIAN)
3155 delay = bfd_getb32 ((unsigned char *) buf + 4);
3157 delay = bfd_getl32 ((unsigned char *) buf + 4);
3158 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3160 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3161 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3162 || ((delay & RD (~0)) != RD (O7))))
3164 if ((delay & RS1 (~0)) == RS1 (O7)
3165 || ((delay & F3I (~0)) == 0
3166 && (delay & RS2 (~0)) == RS2 (O7)))
3168 /* Ensure the branch will fit into simm22. */
3169 if ((val & 0x3fe00000)
3170 && (val & 0x3fe00000) != 0x3fe00000)
3172 /* Check if the arch is v9 and branch will fit
3174 if (((val & 0x3c0000) == 0
3175 || (val & 0x3c0000) == 0x3c0000)
3176 && (sparc_arch_size == 64
3177 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3179 insn = INSN_BPA | (val & 0x7ffff);
3182 insn = INSN_BA | (val & 0x3fffff);
3183 if (fixP->fx_where >= 4
3184 && ((delay & (0xffffffff ^ RS1 (~0)))
3185 == (INSN_OR | RD (O7) | RS2 (G0))))
3190 if (INSN_BIG_ENDIAN)
3191 setter = bfd_getb32 ((unsigned char *) buf - 4);
3193 setter = bfd_getl32 ((unsigned char *) buf - 4);
3194 if ((setter & (0xffffffff ^ RD (~0)))
3195 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3202 If call foo was replaced with ba, replace
3203 or %rN, %g0, %o7 with nop. */
3204 reg = (delay & RS1 (~0)) >> 14;
3205 if (reg != ((setter & RD (~0)) >> 25)
3206 || reg == G0 || reg == O7)
3209 if (INSN_BIG_ENDIAN)
3210 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3212 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3217 case BFD_RELOC_SPARC_11:
3218 if (! in_signed_range (val, 0x7ff))
3219 as_bad_where (fixP->fx_file, fixP->fx_line,
3220 _("relocation overflow"));
3221 insn |= val & 0x7ff;
3224 case BFD_RELOC_SPARC_10:
3225 if (! in_signed_range (val, 0x3ff))
3226 as_bad_where (fixP->fx_file, fixP->fx_line,
3227 _("relocation overflow"));
3228 insn |= val & 0x3ff;
3231 case BFD_RELOC_SPARC_7:
3232 if (! in_bitfield_range (val, 0x7f))
3233 as_bad_where (fixP->fx_file, fixP->fx_line,
3234 _("relocation overflow"));
3238 case BFD_RELOC_SPARC_6:
3239 if (! in_bitfield_range (val, 0x3f))
3240 as_bad_where (fixP->fx_file, fixP->fx_line,
3241 _("relocation overflow"));
3245 case BFD_RELOC_SPARC_5:
3246 if (! in_bitfield_range (val, 0x1f))
3247 as_bad_where (fixP->fx_file, fixP->fx_line,
3248 _("relocation overflow"));
3252 case BFD_RELOC_SPARC_WDISP16:
3255 || val <= -(offsetT) 0x20008)
3256 as_bad_where (fixP->fx_file, fixP->fx_line,
3257 _("relocation overflow"));
3258 /* FIXME: The +1 deserves a comment. */
3259 val = (val >> 2) + 1;
3260 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3263 case BFD_RELOC_SPARC_WDISP19:
3266 || val <= -(offsetT) 0x100008)
3267 as_bad_where (fixP->fx_file, fixP->fx_line,
3268 _("relocation overflow"));
3269 /* FIXME: The +1 deserves a comment. */
3270 val = (val >> 2) + 1;
3271 insn |= val & 0x7ffff;
3274 case BFD_RELOC_SPARC_HH22:
3275 val = BSR (val, 32);
3278 case BFD_RELOC_SPARC_LM22:
3279 case BFD_RELOC_HI22:
3280 if (!fixP->fx_addsy)
3281 insn |= (val >> 10) & 0x3fffff;
3283 /* FIXME: Need comment explaining why we do this. */
3287 case BFD_RELOC_SPARC22:
3288 if (val & ~0x003fffff)
3289 as_bad_where (fixP->fx_file, fixP->fx_line,
3290 _("relocation overflow"));
3291 insn |= (val & 0x3fffff);
3294 case BFD_RELOC_SPARC_HM10:
3295 val = BSR (val, 32);
3298 case BFD_RELOC_LO10:
3299 if (!fixP->fx_addsy)
3300 insn |= val & 0x3ff;
3302 /* FIXME: Need comment explaining why we do this. */
3306 case BFD_RELOC_SPARC_OLO10:
3308 val += fixP->tc_fix_data;
3311 case BFD_RELOC_SPARC13:
3312 if (! in_signed_range (val, 0x1fff))
3313 as_bad_where (fixP->fx_file, fixP->fx_line,
3314 _("relocation overflow"));
3315 insn |= val & 0x1fff;
3318 case BFD_RELOC_SPARC_WDISP22:
3319 val = (val >> 2) + 1;
3321 case BFD_RELOC_SPARC_BASE22:
3322 insn |= val & 0x3fffff;
3325 case BFD_RELOC_SPARC_H44:
3326 if (!fixP->fx_addsy)
3330 insn |= tval & 0x3fffff;
3334 case BFD_RELOC_SPARC_M44:
3335 if (!fixP->fx_addsy)
3336 insn |= (val >> 12) & 0x3ff;
3339 case BFD_RELOC_SPARC_L44:
3340 if (!fixP->fx_addsy)
3341 insn |= val & 0xfff;
3344 case BFD_RELOC_SPARC_HIX22:
3345 if (!fixP->fx_addsy)
3347 val ^= ~(offsetT) 0;
3348 insn |= (val >> 10) & 0x3fffff;
3352 case BFD_RELOC_SPARC_LOX10:
3353 if (!fixP->fx_addsy)
3354 insn |= 0x1c00 | (val & 0x3ff);
3357 case BFD_RELOC_NONE:
3359 as_bad_where (fixP->fx_file, fixP->fx_line,
3360 _("bad or unhandled relocation type: 0x%02x"),
3365 if (INSN_BIG_ENDIAN)
3366 bfd_putb32 (insn, (unsigned char *) buf);
3368 bfd_putl32 (insn, (unsigned char *) buf);
3371 /* Are we finished with this relocation now? */
3372 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3376 /* Translate internal representation of relocation info to BFD target
3380 tc_gen_reloc (section, fixp)
3384 static arelent *relocs[3];
3386 bfd_reloc_code_real_type code;
3388 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3391 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3392 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3393 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3395 switch (fixp->fx_r_type)
3399 case BFD_RELOC_HI22:
3400 case BFD_RELOC_LO10:
3401 case BFD_RELOC_32_PCREL_S2:
3402 case BFD_RELOC_SPARC13:
3403 case BFD_RELOC_SPARC22:
3404 case BFD_RELOC_SPARC_PC22:
3405 case BFD_RELOC_SPARC_PC10:
3406 case BFD_RELOC_SPARC_BASE13:
3407 case BFD_RELOC_SPARC_WDISP16:
3408 case BFD_RELOC_SPARC_WDISP19:
3409 case BFD_RELOC_SPARC_WDISP22:
3411 case BFD_RELOC_SPARC_5:
3412 case BFD_RELOC_SPARC_6:
3413 case BFD_RELOC_SPARC_7:
3414 case BFD_RELOC_SPARC_10:
3415 case BFD_RELOC_SPARC_11:
3416 case BFD_RELOC_SPARC_HH22:
3417 case BFD_RELOC_SPARC_HM10:
3418 case BFD_RELOC_SPARC_LM22:
3419 case BFD_RELOC_SPARC_PC_HH22:
3420 case BFD_RELOC_SPARC_PC_HM10:
3421 case BFD_RELOC_SPARC_PC_LM22:
3422 case BFD_RELOC_SPARC_H44:
3423 case BFD_RELOC_SPARC_M44:
3424 case BFD_RELOC_SPARC_L44:
3425 case BFD_RELOC_SPARC_HIX22:
3426 case BFD_RELOC_SPARC_LOX10:
3427 case BFD_RELOC_SPARC_REV32:
3428 case BFD_RELOC_SPARC_OLO10:
3429 case BFD_RELOC_SPARC_UA16:
3430 case BFD_RELOC_SPARC_UA32:
3431 case BFD_RELOC_SPARC_UA64:
3432 case BFD_RELOC_8_PCREL:
3433 case BFD_RELOC_16_PCREL:
3434 case BFD_RELOC_32_PCREL:
3435 case BFD_RELOC_64_PCREL:
3436 case BFD_RELOC_SPARC_PLT32:
3437 case BFD_RELOC_SPARC_PLT64:
3438 case BFD_RELOC_VTABLE_ENTRY:
3439 case BFD_RELOC_VTABLE_INHERIT:
3440 case BFD_RELOC_SPARC_TLS_GD_HI22:
3441 case BFD_RELOC_SPARC_TLS_GD_LO10:
3442 case BFD_RELOC_SPARC_TLS_GD_ADD:
3443 case BFD_RELOC_SPARC_TLS_GD_CALL:
3444 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3445 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3446 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3447 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3448 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3449 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3450 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3451 case BFD_RELOC_SPARC_TLS_IE_HI22:
3452 case BFD_RELOC_SPARC_TLS_IE_LO10:
3453 case BFD_RELOC_SPARC_TLS_IE_LD:
3454 case BFD_RELOC_SPARC_TLS_IE_LDX:
3455 case BFD_RELOC_SPARC_TLS_IE_ADD:
3456 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3457 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3458 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3459 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3460 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3461 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3462 case BFD_RELOC_SPARC_GOTDATA_OP:
3463 code = fixp->fx_r_type;
3470 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3471 /* If we are generating PIC code, we need to generate a different
3475 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3477 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3480 #define GOTT_BASE "__GOTT_BASE__"
3481 #define GOTT_INDEX "__GOTT_INDEX__"
3484 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3490 case BFD_RELOC_32_PCREL_S2:
3491 if (generic_force_reloc (fixp))
3492 code = BFD_RELOC_SPARC_WPLT30;
3494 case BFD_RELOC_HI22:
3495 code = BFD_RELOC_SPARC_GOT22;
3496 if (fixp->fx_addsy != NULL)
3498 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3499 code = BFD_RELOC_SPARC_PC22;
3501 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3502 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3503 code = BFD_RELOC_HI22; /* Unchanged. */
3507 case BFD_RELOC_LO10:
3508 code = BFD_RELOC_SPARC_GOT10;
3509 if (fixp->fx_addsy != NULL)
3511 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3512 code = BFD_RELOC_SPARC_PC10;
3514 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3515 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3516 code = BFD_RELOC_LO10; /* Unchanged. */
3520 case BFD_RELOC_SPARC13:
3521 code = BFD_RELOC_SPARC_GOT13;
3527 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3529 /* Nothing is aligned in DWARF debugging sections. */
3530 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3533 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3534 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3535 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3539 if (code == BFD_RELOC_SPARC_OLO10)
3540 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3542 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3543 if (reloc->howto == 0)
3545 as_bad_where (fixp->fx_file, fixp->fx_line,
3546 _("internal error: can't export reloc type %d (`%s')"),
3547 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3553 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3556 if (reloc->howto->pc_relative == 0
3557 || code == BFD_RELOC_SPARC_PC10
3558 || code == BFD_RELOC_SPARC_PC22)
3559 reloc->addend = fixp->fx_addnumber;
3560 else if (sparc_pic_code
3561 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3562 && fixp->fx_addsy != NULL
3563 && (S_IS_EXTERNAL (fixp->fx_addsy)
3564 || S_IS_WEAK (fixp->fx_addsy))
3565 && S_IS_DEFINED (fixp->fx_addsy)
3566 && ! S_IS_COMMON (fixp->fx_addsy))
3567 reloc->addend = fixp->fx_addnumber;
3569 reloc->addend = fixp->fx_offset - reloc->address;
3571 #else /* elf or coff */
3573 if (code != BFD_RELOC_32_PCREL_S2
3574 && code != BFD_RELOC_SPARC_WDISP22
3575 && code != BFD_RELOC_SPARC_WDISP16
3576 && code != BFD_RELOC_SPARC_WDISP19
3577 && code != BFD_RELOC_SPARC_WPLT30
3578 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3579 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3580 reloc->addend = fixp->fx_addnumber;
3581 else if (symbol_section_p (fixp->fx_addsy))
3582 reloc->addend = (section->vma
3583 + fixp->fx_addnumber
3584 + md_pcrel_from (fixp));
3586 reloc->addend = fixp->fx_offset;
3589 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3590 on the same location. */
3591 if (code == BFD_RELOC_SPARC_OLO10)
3593 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3596 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3598 = symbol_get_bfdsym (section_symbol (absolute_section));
3599 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3600 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3601 reloc->addend = fixp->tc_fix_data;
3607 /* We have no need to default values of symbols. */
3610 md_undefined_symbol (name)
3611 char *name ATTRIBUTE_UNUSED;
3616 /* Round up a section size to the appropriate boundary. */
3619 md_section_align (segment, size)
3620 segT segment ATTRIBUTE_UNUSED;
3624 /* This is not right for ELF; a.out wants it, and COFF will force
3625 the alignment anyways. */
3626 valueT align = ((valueT) 1
3627 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3630 /* Turn alignment value into a mask. */
3632 newsize = (size + align) & ~align;
3639 /* Exactly what point is a PC-relative offset relative TO?
3640 On the sparc, they're relative to the address of the offset, plus
3641 its size. This gets us to the following instruction.
3642 (??? Is this right? FIXME-SOON) */
3644 md_pcrel_from (fixP)
3649 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3650 if (! sparc_pic_code
3651 || fixP->fx_addsy == NULL
3652 || symbol_section_p (fixP->fx_addsy))
3653 ret += fixP->fx_size;
3657 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3669 for (shift = 0; (value & 1) == 0; value >>= 1)
3672 return (value == 1) ? shift : -1;
3675 /* Sort of like s_lcomm. */
3678 static int max_alignment = 15;
3683 int ignore ATTRIBUTE_UNUSED;
3693 name = input_line_pointer;
3694 c = get_symbol_end ();
3695 p = input_line_pointer;
3699 if (*input_line_pointer != ',')
3701 as_bad (_("Expected comma after name"));
3702 ignore_rest_of_line ();
3706 ++input_line_pointer;
3708 if ((size = get_absolute_expression ()) < 0)
3710 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3711 ignore_rest_of_line ();
3716 symbolP = symbol_find_or_make (name);
3719 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3720 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3722 as_bad (_("bad .reserve segment -- expected BSS segment"));
3726 if (input_line_pointer[2] == '.')
3727 input_line_pointer += 7;
3729 input_line_pointer += 6;
3732 if (*input_line_pointer == ',')
3734 ++input_line_pointer;
3737 if (*input_line_pointer == '\n')
3739 as_bad (_("missing alignment"));
3740 ignore_rest_of_line ();
3744 align = (int) get_absolute_expression ();
3747 if (align > max_alignment)
3749 align = max_alignment;
3750 as_warn (_("alignment too large; assuming %d"), align);
3756 as_bad (_("negative alignment"));
3757 ignore_rest_of_line ();
3763 temp = mylog2 (align);
3766 as_bad (_("alignment not a power of 2"));
3767 ignore_rest_of_line ();
3774 record_alignment (bss_section, align);
3779 if (!S_IS_DEFINED (symbolP)
3781 && S_GET_OTHER (symbolP) == 0
3782 && S_GET_DESC (symbolP) == 0
3789 segT current_seg = now_seg;
3790 subsegT current_subseg = now_subseg;
3792 /* Switch to bss. */
3793 subseg_set (bss_section, 1);
3797 frag_align (align, 0, 0);
3799 /* Detach from old frag. */
3800 if (S_GET_SEGMENT (symbolP) == bss_section)
3801 symbol_get_frag (symbolP)->fr_symbol = NULL;
3803 symbol_set_frag (symbolP, frag_now);
3804 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3805 (offsetT) size, (char *) 0);
3808 S_SET_SEGMENT (symbolP, bss_section);
3810 subseg_set (current_seg, current_subseg);
3813 S_SET_SIZE (symbolP, size);
3819 as_warn ("Ignoring attempt to re-define symbol %s",
3820 S_GET_NAME (symbolP));
3821 } /* if not redefining. */
3823 demand_empty_rest_of_line ();
3828 int ignore ATTRIBUTE_UNUSED;
3836 name = input_line_pointer;
3837 c = get_symbol_end ();
3838 /* Just after name is now '\0'. */
3839 p = input_line_pointer;
3842 if (*input_line_pointer != ',')
3844 as_bad (_("Expected comma after symbol-name"));
3845 ignore_rest_of_line ();
3850 input_line_pointer++;
3852 if ((temp = get_absolute_expression ()) < 0)
3854 as_bad (_(".COMMon length (%lu) out of range ignored"),
3855 (unsigned long) temp);
3856 ignore_rest_of_line ();
3861 symbolP = symbol_find_or_make (name);
3863 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3865 as_bad (_("Ignoring attempt to re-define symbol"));
3866 ignore_rest_of_line ();
3869 if (S_GET_VALUE (symbolP) != 0)
3871 if (S_GET_VALUE (symbolP) != (valueT) size)
3873 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3874 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3880 S_SET_VALUE (symbolP, (valueT) size);
3881 S_SET_EXTERNAL (symbolP);
3884 know (symbol_get_frag (symbolP) == &zero_address_frag);
3885 if (*input_line_pointer != ',')
3887 as_bad (_("Expected comma after common length"));
3888 ignore_rest_of_line ();
3891 input_line_pointer++;
3893 if (*input_line_pointer != '"')
3895 temp = get_absolute_expression ();
3898 if (temp > max_alignment)
3900 temp = max_alignment;
3901 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3907 as_bad (_("negative alignment"));
3908 ignore_rest_of_line ();
3913 if (symbol_get_obj (symbolP)->local)
3921 old_subsec = now_subseg;
3926 align = mylog2 (temp);
3930 as_bad (_("alignment not a power of 2"));
3931 ignore_rest_of_line ();
3935 record_alignment (bss_section, align);
3936 subseg_set (bss_section, 0);
3938 frag_align (align, 0, 0);
3939 if (S_GET_SEGMENT (symbolP) == bss_section)
3940 symbol_get_frag (symbolP)->fr_symbol = 0;
3941 symbol_set_frag (symbolP, frag_now);
3942 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3943 (offsetT) size, (char *) 0);
3945 S_SET_SEGMENT (symbolP, bss_section);
3946 S_CLEAR_EXTERNAL (symbolP);
3947 S_SET_SIZE (symbolP, size);
3948 subseg_set (old_sec, old_subsec);
3951 #endif /* OBJ_ELF */
3954 S_SET_VALUE (symbolP, (valueT) size);
3956 S_SET_ALIGN (symbolP, temp);
3957 S_SET_SIZE (symbolP, size);
3959 S_SET_EXTERNAL (symbolP);
3960 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3965 input_line_pointer++;
3966 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3967 if (*input_line_pointer == '.')
3968 input_line_pointer++;
3969 /* @@ Some say data, some say bss. */
3970 if (strncmp (input_line_pointer, "bss\"", 4)
3971 && strncmp (input_line_pointer, "data\"", 5))
3973 while (*--input_line_pointer != '"')
3975 input_line_pointer--;
3976 goto bad_common_segment;
3978 while (*input_line_pointer++ != '"')
3980 goto allocate_common;
3983 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3985 demand_empty_rest_of_line ();
3990 p = input_line_pointer;
3991 while (*p && *p != '\n')
3995 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3997 input_line_pointer = p;
3998 ignore_rest_of_line ();
4003 /* Handle the .empty pseudo-op. This suppresses the warnings about
4004 invalid delay slot usage. */
4008 int ignore ATTRIBUTE_UNUSED;
4010 /* The easy way to implement is to just forget about the last
4017 int ignore ATTRIBUTE_UNUSED;
4020 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4022 input_line_pointer += 6;
4026 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4028 input_line_pointer += 6;
4032 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4034 input_line_pointer += 7;
4038 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4040 input_line_pointer += 5;
4041 /* We only support 2 segments -- text and data -- for now, so
4042 things in the "bss segment" will have to go into data for now.
4043 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4044 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4047 as_bad (_("Unknown segment type"));
4048 demand_empty_rest_of_line ();
4054 subseg_set (data_section, 1);
4055 demand_empty_rest_of_line ();
4060 int ignore ATTRIBUTE_UNUSED;
4062 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4064 ++input_line_pointer;
4066 ++input_line_pointer;
4069 /* This static variable is set by s_uacons to tell sparc_cons_align
4070 that the expression does not need to be aligned. */
4072 static int sparc_no_align_cons = 0;
4074 /* This static variable is set by sparc_cons to emit requested types
4075 of relocations in cons_fix_new_sparc. */
4077 static const char *sparc_cons_special_reloc;
4079 /* This handles the unaligned space allocation pseudo-ops, such as
4080 .uaword. .uaword is just like .word, but the value does not need
4087 /* Tell sparc_cons_align not to align this value. */
4088 sparc_no_align_cons = 1;
4090 sparc_no_align_cons = 0;
4093 /* This handles the native word allocation pseudo-op .nword.
4094 For sparc_arch_size 32 it is equivalent to .word, for
4095 sparc_arch_size 64 it is equivalent to .xword. */
4099 int bytes ATTRIBUTE_UNUSED;
4101 cons (sparc_arch_size == 32 ? 4 : 8);
4105 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4109 .register %g[2367],{#scratch|symbolname|#ignore}
4114 int ignore ATTRIBUTE_UNUSED;
4119 const char *regname;
4121 if (input_line_pointer[0] != '%'
4122 || input_line_pointer[1] != 'g'
4123 || ((input_line_pointer[2] & ~1) != '2'
4124 && (input_line_pointer[2] & ~1) != '6')
4125 || input_line_pointer[3] != ',')
4126 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4127 reg = input_line_pointer[2] - '0';
4128 input_line_pointer += 4;
4130 if (*input_line_pointer == '#')
4132 ++input_line_pointer;
4133 regname = input_line_pointer;
4134 c = get_symbol_end ();
4135 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4136 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4137 if (regname[0] == 'i')
4144 regname = input_line_pointer;
4145 c = get_symbol_end ();
4147 if (sparc_arch_size == 64)
4151 if ((regname && globals[reg] != (symbolS *) 1
4152 && strcmp (S_GET_NAME (globals[reg]), regname))
4153 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4154 as_bad (_("redefinition of global register"));
4158 if (regname == NULL)
4159 globals[reg] = (symbolS *) 1;
4164 if (symbol_find (regname))
4165 as_bad (_("Register symbol %s already defined."),
4168 globals[reg] = symbol_make (regname);
4169 flags = symbol_get_bfdsym (globals[reg])->flags;
4171 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4172 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4173 flags |= BSF_GLOBAL;
4174 symbol_get_bfdsym (globals[reg])->flags = flags;
4175 S_SET_VALUE (globals[reg], (valueT) reg);
4176 S_SET_ALIGN (globals[reg], reg);
4177 S_SET_SIZE (globals[reg], 0);
4178 /* Although we actually want undefined_section here,
4179 we have to use absolute_section, because otherwise
4180 generic as code will make it a COM section.
4181 We fix this up in sparc_adjust_symtab. */
4182 S_SET_SEGMENT (globals[reg], absolute_section);
4183 S_SET_OTHER (globals[reg], 0);
4184 elf_symbol (symbol_get_bfdsym (globals[reg]))
4185 ->internal_elf_sym.st_info =
4186 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4187 elf_symbol (symbol_get_bfdsym (globals[reg]))
4188 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4193 *input_line_pointer = c;
4195 demand_empty_rest_of_line ();
4198 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4199 symbols which need it. */
4202 sparc_adjust_symtab ()
4206 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4208 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4209 ->internal_elf_sym.st_info) != STT_REGISTER)
4212 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4213 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4216 S_SET_SEGMENT (sym, undefined_section);
4221 /* If the --enforce-aligned-data option is used, we require .word,
4222 et. al., to be aligned correctly. We do it by setting up an
4223 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4224 no unexpected alignment was introduced.
4226 The SunOS and Solaris native assemblers enforce aligned data by
4227 default. We don't want to do that, because gcc can deliberately
4228 generate misaligned data if the packed attribute is used. Instead,
4229 we permit misaligned data by default, and permit the user to set an
4230 option to check for it. */
4233 sparc_cons_align (nbytes)
4239 /* Only do this if we are enforcing aligned data. */
4240 if (! enforce_aligned_data)
4243 /* Don't align if this is an unaligned pseudo-op. */
4244 if (sparc_no_align_cons)
4247 nalign = mylog2 (nbytes);
4251 assert (nalign > 0);
4253 if (now_seg == absolute_section)
4255 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4256 as_bad (_("misaligned data"));
4260 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4261 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4263 record_alignment (now_seg, nalign);
4266 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4269 sparc_handle_align (fragp)
4275 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4277 switch (fragp->fr_type)
4281 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4285 p = fragp->fr_literal + fragp->fr_fix;
4296 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4298 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4299 if (INSN_BIG_ENDIAN)
4300 number_to_chars_bigendian (p, wval, 4);
4302 number_to_chars_littleendian (p, wval, 4);
4308 if (INSN_BIG_ENDIAN)
4309 number_to_chars_bigendian (p, 0x01000000, 4);
4311 number_to_chars_littleendian (p, 0x01000000, 4);
4313 fragp->fr_fix += fix;
4323 /* Some special processing for a Sparc ELF file. */
4326 sparc_elf_final_processing ()
4328 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4329 sort of BFD interface for this. */
4330 if (sparc_arch_size == 64)
4332 switch (sparc_memory_model)
4335 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4338 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4344 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4345 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4346 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4347 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4348 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4349 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4353 sparc_cons (exp, size)
4360 sparc_cons_special_reloc = NULL;
4361 save = input_line_pointer;
4362 if (input_line_pointer[0] == '%'
4363 && input_line_pointer[1] == 'r'
4364 && input_line_pointer[2] == '_')
4366 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4368 input_line_pointer += 7;
4369 sparc_cons_special_reloc = "disp";
4371 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4373 if (size != 4 && size != 8)
4374 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4377 input_line_pointer += 6;
4378 sparc_cons_special_reloc = "plt";
4381 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4383 if (size != 4 && size != 8)
4384 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4387 input_line_pointer += 13;
4388 sparc_cons_special_reloc = "tls_dtpoff";
4391 if (sparc_cons_special_reloc)
4398 if (*input_line_pointer != '8')
4400 input_line_pointer--;
4403 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4407 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4411 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4421 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4422 sparc_cons_special_reloc, size * 8, size);
4426 input_line_pointer += 2;
4427 if (*input_line_pointer != '(')
4429 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4430 sparc_cons_special_reloc, size * 8);
4437 input_line_pointer = save;
4438 sparc_cons_special_reloc = NULL;
4443 char *end = ++input_line_pointer;
4446 while (! is_end_of_line[(c = *end)])
4460 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4461 sparc_cons_special_reloc, size * 8);
4467 if (input_line_pointer != end)
4469 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4470 sparc_cons_special_reloc, size * 8);
4474 input_line_pointer++;
4476 c = *input_line_pointer;
4477 if (! is_end_of_line[c] && c != ',')
4478 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4479 sparc_cons_special_reloc, size * 8);
4485 if (sparc_cons_special_reloc == NULL)
4491 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4492 reloc for a cons. We could use the definition there, except that
4493 we want to handle little endian relocs specially. */
4496 cons_fix_new_sparc (frag, where, nbytes, exp)
4499 unsigned int nbytes;
4502 bfd_reloc_code_real_type r;
4504 r = (nbytes == 1 ? BFD_RELOC_8 :
4505 (nbytes == 2 ? BFD_RELOC_16 :
4506 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4508 if (target_little_endian_data
4510 && now_seg->flags & SEC_ALLOC)
4511 r = BFD_RELOC_SPARC_REV32;
4513 if (sparc_cons_special_reloc)
4515 if (*sparc_cons_special_reloc == 'd')
4518 case 1: r = BFD_RELOC_8_PCREL; break;
4519 case 2: r = BFD_RELOC_16_PCREL; break;
4520 case 4: r = BFD_RELOC_32_PCREL; break;
4521 case 8: r = BFD_RELOC_64_PCREL; break;
4524 else if (*sparc_cons_special_reloc == 'p')
4527 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4528 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4533 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4534 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4537 else if (sparc_no_align_cons)
4541 case 2: r = BFD_RELOC_SPARC_UA16; break;
4542 case 4: r = BFD_RELOC_SPARC_UA32; break;
4543 case 8: r = BFD_RELOC_SPARC_UA64; break;
4548 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4549 sparc_cons_special_reloc = NULL;
4553 sparc_cfi_frame_initial_instructions ()
4555 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4559 sparc_regname_to_dw2regnum (char *regname)
4567 p = strchr (q, regname[0]);
4570 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4572 return (p - q) * 8 + regname[1] - '0';
4574 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4576 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4578 if (regname[0] == 'f' || regname[0] == 'r')
4580 unsigned int regnum;
4582 regnum = strtoul (regname + 1, &q, 10);
4585 if (regnum >= ((regname[0] == 'f'
4586 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4589 if (regname[0] == 'f')
4592 if (regnum >= 64 && (regnum & 1))
4601 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4603 sparc_cons_special_reloc = "disp";
4604 sparc_no_align_cons = 1;
4605 emit_expr (exp, nbytes);
4606 sparc_no_align_cons = 0;
4607 sparc_cons_special_reloc = NULL;