1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
30 #include "elf/sparc.h"
33 static struct sparc_arch *lookup_arch PARAMS ((char *));
34 static void init_default_arch PARAMS ((void));
35 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
36 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
37 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
38 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39 static int sparc_ffs PARAMS ((unsigned int));
40 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
41 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
42 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
43 static bfd_vma BSR PARAMS ((bfd_vma, int));
44 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
45 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
46 static int parse_const_expr_arg PARAMS ((char **, int *));
47 static int get_expression PARAMS ((char *str));
49 /* Default architecture. */
50 /* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
54 #define DEFAULT_ARCH "sparclite"
56 static char *default_arch = DEFAULT_ARCH;
58 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
60 static int default_init_p;
62 /* Current architecture. We don't bump up unless necessary. */
63 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
65 /* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70 static enum sparc_opcode_arch_val max_architecture;
72 /* Either 32 or 64, selects file format. */
73 static int sparc_arch_size;
74 /* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76 static int default_arch_size;
79 /* The currently selected v9 memory model. Currently only used for
81 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
84 static int architecture_requested;
85 static int warn_on_bump;
87 /* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89 static enum sparc_opcode_arch_val warn_after_architecture;
91 /* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93 static int no_undeclared_regs;
95 /* Non-zero if we should try to relax jumps and calls. */
96 static int sparc_relax;
98 /* Non-zero if we are generating PIC code. */
101 /* Non-zero if we should give an error when misaligned data is seen. */
102 static int enforce_aligned_data;
104 extern int target_big_endian;
106 static int target_little_endian_data;
108 /* Symbols for global registers on v9. */
109 static symbolS *globals[8];
111 /* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115 #ifndef INSN_BIG_ENDIAN
116 #define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
121 /* Handle of the OPCODE hash table. */
122 static struct hash_control *op_hash;
124 static int log2 PARAMS ((int));
125 static void s_data1 PARAMS ((void));
126 static void s_seg PARAMS ((int));
127 static void s_proc PARAMS ((int));
128 static void s_reserve PARAMS ((int));
129 static void s_common PARAMS ((int));
130 static void s_empty PARAMS ((int));
131 static void s_uacons PARAMS ((int));
132 static void s_ncons PARAMS ((int));
133 static void s_register PARAMS ((int));
135 const pseudo_typeS md_pseudo_table[] =
137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
142 {"nword", s_ncons, 0},
143 {"optim", s_ignore, 0},
145 {"reserve", s_reserve, 0},
147 {"skip", s_space, 0},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
158 {"register", s_register, 0},
163 /* Size of relocation record. */
164 const int md_reloc_size = 12;
166 /* This array holds the chars that always start a comment. If the
167 pre-processor is disabled, these aren't very useful. */
168 const char comment_chars[] = "!"; /* JF removed '|' from
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output. */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that comments started like this one will always
178 work if '/' isn't otherwise defined. */
179 const char line_comment_chars[] = "#";
181 const char line_separator_chars[] = ";";
183 /* Chars that can be used to separate mant from exp in floating point
185 const char EXP_CHARS[] = "eE";
187 /* Chars that mean this number is a floating point constant.
190 const char FLT_CHARS[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
196 #define isoctal(c) ((unsigned)((c) - '0') < '8')
201 unsigned long opcode;
202 struct nlist *nlistp;
206 bfd_reloc_code_real_type reloc;
209 struct sparc_it the_insn, set_insn;
211 static void output_insn
212 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
220 v8plusa, v9, v9a, v9b, v9_64};
222 static struct sparc_arch {
225 enum sparc_arch_types arch_type;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size;
229 /* Allowable arg to -A? */
231 } sparc_arch_table[] = {
232 { "v6", "v6", v6, 0, 1 },
233 { "v7", "v7", v7, 0, 1 },
234 { "v8", "v8", v8, 32, 1 },
235 { "sparclet", "sparclet", sparclet, 32, 1 },
236 { "sparclite", "sparclite", sparclite, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x, 32, 1 },
238 { "v8plus", "v9", v9, 0, 1 },
239 { "v8plusa", "v9a", v9, 0, 1 },
240 { "v8plusb", "v9b", v9, 0, 1 },
241 { "v9", "v9", v9, 0, 1 },
242 { "v9a", "v9a", v9, 0, 1 },
243 { "v9b", "v9b", v9, 0, 1 },
244 /* This exists to allow configure.in/Makefile.in to pass one
245 value to specify both the default machine and default word size. */
246 { "v9-64", "v9", v9, 64, 0 },
247 { NULL, NULL, v8, 0, 0 }
250 /* Variant of default_arch */
251 static enum sparc_arch_types default_arch_type;
253 static struct sparc_arch *
257 struct sparc_arch *sa;
259 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
260 if (strcmp (sa->name, name) == 0)
262 if (sa->name == NULL)
267 /* Initialize the default opcode arch and word size from the default
268 architecture name. */
273 struct sparc_arch *sa = lookup_arch (default_arch);
276 || sa->default_arch_size == 0)
277 as_fatal (_("Invalid default architecture, broken assembler."));
279 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
280 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
281 as_fatal (_("Bad opcode table, broken assembler."));
282 default_arch_size = sparc_arch_size = sa->default_arch_size;
284 default_arch_type = sa->arch_type;
287 /* Called by TARGET_FORMAT. */
290 sparc_target_format ()
292 /* We don't get a chance to initialize anything before we're called,
293 so handle that now. */
294 if (! default_init_p)
295 init_default_arch ();
299 return "a.out-sparc-netbsd";
302 if (target_big_endian)
303 return "a.out-sunos-big";
304 else if (default_arch_type == sparc86x && target_little_endian_data)
305 return "a.out-sunos-big";
307 return "a.out-sparc-little";
309 return "a.out-sunos-big";
320 return "coff-sparc-lynx";
327 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
334 * Invocation line includes a switch not recognized by the base assembler.
335 * See if it's a processor-specific option. These are:
338 * Warn on architecture bumps. See also -A.
340 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
341 * Standard 32 bit architectures.
343 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
344 * This used to only mean 64 bits, but properly specifying it
345 * complicated gcc's ASM_SPECs, so now opcode selection is
346 * specified orthogonally to word size (except when specifying
347 * the default, but that is an internal implementation detail).
348 * -Av8plus, -Av8plusa, -Av8plusb
349 * Same as -Av9{,a,b}.
350 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
351 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
353 * -xarch=v9, -xarch=v9a, -xarch=v9b
354 * Same as -Av9{,a,b} -64, for compatibility with Sun's
357 * Select the architecture and possibly the file format.
358 * Instructions or features not supported by the selected
359 * architecture cause fatal errors.
361 * The default is to start at v6, and bump the architecture up
362 * whenever an instruction is seen at a higher level. In 32 bit
363 * environments, v9 is not bumped up to, the user must pass
366 * If -bump is specified, a warning is printing when bumping to
369 * If an architecture is specified, all instructions must match
370 * that architecture. Any higher level instructions are flagged
371 * as errors. Note that in the 32 bit environment specifying
372 * -Av8plus does not automatically create a v8plus object file, a
373 * v9 insn must be seen.
375 * If both an architecture and -bump are specified, the
376 * architecture starts at the specified level, but bumps are
377 * warnings. Note that we can't set `current_architecture' to
378 * the requested level in this case: in the 32 bit environment,
379 * we still must avoid creating v8plus object files unless v9
383 * Bumping between incompatible architectures is always an
384 * error. For example, from sparclite to v9.
388 CONST char *md_shortopts = "A:K:VQ:sq";
391 CONST char *md_shortopts = "A:k";
393 CONST char *md_shortopts = "A:";
396 struct option md_longopts[] = {
397 #define OPTION_BUMP (OPTION_MD_BASE)
398 {"bump", no_argument, NULL, OPTION_BUMP},
399 #define OPTION_SPARC (OPTION_MD_BASE + 1)
400 {"sparc", no_argument, NULL, OPTION_SPARC},
401 #define OPTION_XARCH (OPTION_MD_BASE + 2)
402 {"xarch", required_argument, NULL, OPTION_XARCH},
404 #define OPTION_32 (OPTION_MD_BASE + 3)
405 {"32", no_argument, NULL, OPTION_32},
406 #define OPTION_64 (OPTION_MD_BASE + 4)
407 {"64", no_argument, NULL, OPTION_64},
408 #define OPTION_TSO (OPTION_MD_BASE + 5)
409 {"TSO", no_argument, NULL, OPTION_TSO},
410 #define OPTION_PSO (OPTION_MD_BASE + 6)
411 {"PSO", no_argument, NULL, OPTION_PSO},
412 #define OPTION_RMO (OPTION_MD_BASE + 7)
413 {"RMO", no_argument, NULL, OPTION_RMO},
415 #ifdef SPARC_BIENDIAN
416 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
417 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
418 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
419 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
421 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
422 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
423 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
424 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
426 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
427 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
428 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
429 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
431 #define OPTION_RELAX (OPTION_MD_BASE + 14)
432 {"relax", no_argument, NULL, OPTION_RELAX},
433 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
434 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
435 {NULL, no_argument, NULL, 0}
438 size_t md_longopts_size = sizeof (md_longopts);
441 md_parse_option (c, arg)
445 /* We don't get a chance to initialize anything before we're called,
446 so handle that now. */
447 if (! default_init_p)
448 init_default_arch ();
454 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
459 if (strncmp (arg, "v9", 2) != 0)
460 md_parse_option (OPTION_32, NULL);
462 md_parse_option (OPTION_64, NULL);
468 struct sparc_arch *sa;
469 enum sparc_opcode_arch_val opcode_arch;
471 sa = lookup_arch (arg);
473 || ! sa->user_option_p)
475 if (c == OPTION_XARCH)
476 as_bad (_("invalid architecture -xarch=%s"), arg);
478 as_bad (_("invalid architecture -A%s"), arg);
482 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
483 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
484 as_fatal (_("Bad opcode table, broken assembler."));
486 max_architecture = opcode_arch;
487 architecture_requested = 1;
492 /* Ignore -sparc, used by SunOS make default .s.o rule. */
495 case OPTION_ENFORCE_ALIGNED_DATA:
496 enforce_aligned_data = 1;
499 #ifdef SPARC_BIENDIAN
500 case OPTION_LITTLE_ENDIAN:
501 target_big_endian = 0;
502 if (default_arch_type != sparclet)
503 as_fatal ("This target does not support -EL");
505 case OPTION_LITTLE_ENDIAN_DATA:
506 target_little_endian_data = 1;
507 target_big_endian = 0;
508 if (default_arch_type != sparc86x
509 && default_arch_type != v9)
510 as_fatal ("This target does not support --little-endian-data");
512 case OPTION_BIG_ENDIAN:
513 target_big_endian = 1;
527 const char **list, **l;
529 sparc_arch_size = c == OPTION_32 ? 32 : 64;
530 list = bfd_target_list ();
531 for (l = list; *l != NULL; l++)
533 if (sparc_arch_size == 32)
535 if (strcmp (*l, "elf32-sparc") == 0)
540 if (strcmp (*l, "elf64-sparc") == 0)
545 as_fatal (_("No compiled in support for %d bit object file format"),
552 sparc_memory_model = MM_TSO;
556 sparc_memory_model = MM_PSO;
560 sparc_memory_model = MM_RMO;
568 /* Qy - do emit .comment
569 Qn - do not emit .comment. */
573 /* Use .stab instead of .stab.excl. */
577 /* quick -- Native assembler does fewer checks. */
581 if (strcmp (arg, "PIC") != 0)
582 as_warn (_("Unrecognized option following -K"));
587 case OPTION_NO_UNDECLARED_REGS:
588 no_undeclared_regs = 1;
591 case OPTION_UNDECLARED_REGS:
592 no_undeclared_regs = 0;
600 case OPTION_NO_RELAX:
612 md_show_usage (stream)
615 const struct sparc_arch *arch;
618 /* We don't get a chance to initialize anything before we're called,
619 so handle that now. */
620 if (! default_init_p)
621 init_default_arch ();
623 fprintf (stream, _("SPARC options:\n"));
625 for (arch = &sparc_arch_table[0]; arch->name; arch++)
627 if (!arch->user_option_p)
629 if (arch != &sparc_arch_table[0])
630 fprintf (stream, " | ");
631 if (column + strlen(arch->name) > 70)
634 fputc ('\n', stream);
636 column += 5 + 2 + strlen(arch->name);
637 fprintf (stream, "-A%s", arch->name);
639 for (arch = &sparc_arch_table[0]; arch->name; arch++)
641 if (!arch->user_option_p)
643 fprintf (stream, " | ");
644 if (column + strlen(arch->name) > 65)
647 fputc ('\n', stream);
649 column += 5 + 7 + strlen(arch->name);
650 fprintf (stream, "-xarch=%s", arch->name);
652 fprintf (stream, _("\n\
653 specify variant of SPARC architecture\n\
654 -bump warn when assembler switches architectures\n\
656 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
657 -relax relax jumps and branches (default)\n\
658 -no-relax avoid changing any jumps and branches\n"));
660 fprintf (stream, _("\
661 -k generate PIC\n"));
664 fprintf (stream, _("\
665 -32 create 32 bit object file\n\
666 -64 create 64 bit object file\n"));
667 fprintf (stream, _("\
668 [default is %d]\n"), default_arch_size);
669 fprintf (stream, _("\
670 -TSO use Total Store Ordering\n\
671 -PSO use Partial Store Ordering\n\
672 -RMO use Relaxed Memory Ordering\n"));
673 fprintf (stream, _("\
674 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
675 fprintf (stream, _("\
676 -KPIC generate PIC\n\
677 -V print assembler version number\n\
678 -undeclared-regs ignore application global register usage without\n\
679 appropriate .register directive (default)\n\
680 -no-undeclared-regs force error on application global register usage\n\
681 without appropriate .register directive\n\
686 #ifdef SPARC_BIENDIAN
687 fprintf (stream, _("\
688 -EL generate code for a little endian machine\n\
689 -EB generate code for a big endian machine\n\
690 --little-endian-data generate code for a machine having big endian\n\
691 instructions and little endian data.\n"));
695 /* Native operand size opcode translation. */
701 } native_op_table[] =
703 {"ldn", "ld", "ldx"},
704 {"ldna", "lda", "ldxa"},
705 {"stn", "st", "stx"},
706 {"stna", "sta", "stxa"},
707 {"slln", "sll", "sllx"},
708 {"srln", "srl", "srlx"},
709 {"sran", "sra", "srax"},
710 {"casn", "cas", "casx"},
711 {"casna", "casa", "casxa"},
712 {"clrn", "clr", "clrx"},
716 /* sparc64 priviledged registers. */
718 struct priv_reg_entry
724 struct priv_reg_entry priv_reg_table[] =
743 {"", -1}, /* End marker. */
746 /* v9a specific asrs. */
748 struct priv_reg_entry v9a_asr_table[] =
751 {"sys_tick_cmpr", 25},
759 {"clear_softint", 21},
760 {"", -1}, /* End marker. */
764 cmp_reg_entry (parg, qarg)
768 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
769 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
771 return strcmp (q->name, p->name);
774 /* This function is called once, at assembler startup time. It should
775 set up all the tables, etc. that the MD part of the assembler will
781 register const char *retval = NULL;
783 register unsigned int i = 0;
785 /* We don't get a chance to initialize anything before md_parse_option
786 is called, and it may not be called, so handle default initialization
787 now if not already done. */
788 if (! default_init_p)
789 init_default_arch ();
791 op_hash = hash_new ();
793 while (i < (unsigned int) sparc_num_opcodes)
795 const char *name = sparc_opcodes[i].name;
796 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
799 as_bad (_("Internal error: can't hash `%s': %s\n"),
800 sparc_opcodes[i].name, retval);
805 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
807 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
808 sparc_opcodes[i].name, sparc_opcodes[i].args);
813 while (i < (unsigned int) sparc_num_opcodes
814 && !strcmp (sparc_opcodes[i].name, name));
817 for (i = 0; native_op_table[i].name; i++)
819 const struct sparc_opcode *insn;
820 char *name = ((sparc_arch_size == 32)
821 ? native_op_table[i].name32
822 : native_op_table[i].name64);
823 insn = (struct sparc_opcode *) hash_find (op_hash, name);
826 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
827 name, native_op_table[i].name);
832 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
835 as_bad (_("Internal error: can't hash `%s': %s\n"),
836 sparc_opcodes[i].name, retval);
843 as_fatal (_("Broken assembler. No assembly attempted."));
845 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
846 sizeof (priv_reg_table[0]), cmp_reg_entry);
848 /* If -bump, record the architecture level at which we start issuing
849 warnings. The behaviour is different depending upon whether an
850 architecture was explicitly specified. If it wasn't, we issue warnings
851 for all upwards bumps. If it was, we don't start issuing warnings until
852 we need to bump beyond the requested architecture or when we bump between
853 conflicting architectures. */
856 && architecture_requested)
858 /* `max_architecture' records the requested architecture.
859 Issue warnings if we go above it. */
860 warn_after_architecture = max_architecture;
862 /* Find the highest architecture level that doesn't conflict with
863 the requested one. */
864 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
865 max_architecture > warn_after_architecture;
867 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
868 warn_after_architecture))
873 /* Called after all assembly has been done. */
878 unsigned long mach = bfd_mach_sparc;
880 if (sparc_arch_size == 64)
881 switch (current_architecture)
883 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
884 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
885 default: mach = bfd_mach_sparc_v9; break;
888 switch (current_architecture)
890 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
891 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
892 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
893 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
894 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
895 be but for now it is (since that's the way it's always been
899 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
902 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
905 in_signed_range (val, max)
906 bfd_signed_vma val, max;
910 /* Sign-extend the value from the architecture word size, so that
911 0xffffffff is always considered -1 on sparc32. */
912 if (sparc_arch_size == 32)
914 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
915 val = ((val & 0xffffffff) ^ sign) - sign;
924 /* Return non-zero if VAL is in the range 0 to MAX. */
927 in_unsigned_range (val, max)
935 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
936 (e.g. -15 to +31). */
939 in_bitfield_range (val, max)
940 bfd_signed_vma val, max;
946 if (val < ~(max >> 1))
960 for (i = 0; (mask & 1) == 0; ++i)
965 /* Implement big shift right. */
971 if (sizeof (bfd_vma) <= 4 && amount >= 32)
972 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
973 return val >> amount;
976 /* For communication between sparc_ip and get_expression. */
977 static char *expr_end;
979 /* Values for `special_case'.
980 Instructions that require wierd handling because they're longer than
982 #define SPECIAL_CASE_NONE 0
983 #define SPECIAL_CASE_SET 1
984 #define SPECIAL_CASE_SETSW 2
985 #define SPECIAL_CASE_SETX 3
986 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
987 #define SPECIAL_CASE_FDIV 4
989 /* Bit masks of various insns. */
990 #define NOP_INSN 0x01000000
991 #define OR_INSN 0x80100000
992 #define XOR_INSN 0x80180000
993 #define FMOVS_INSN 0x81A00020
994 #define SETHI_INSN 0x01000000
995 #define SLLX_INSN 0x81281000
996 #define SRA_INSN 0x81380000
998 /* The last instruction to be assembled. */
999 static const struct sparc_opcode *last_insn;
1000 /* The assembled opcode of `last_insn'. */
1001 static unsigned long last_opcode;
1003 /* Handle the set and setuw synthetic instructions. */
1006 synthetize_setuw (insn)
1007 const struct sparc_opcode *insn;
1009 int need_hi22_p = 0;
1010 int rd = (the_insn.opcode & RD (~0)) >> 25;
1012 if (the_insn.exp.X_op == O_constant)
1014 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1016 if (sizeof (offsetT) > 4
1017 && (the_insn.exp.X_add_number < 0
1018 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1019 as_warn (_("set: number not in 0..4294967295 range"));
1023 if (sizeof (offsetT) > 4
1024 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1025 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1026 as_warn (_("set: number not in -2147483648..4294967295 range"));
1027 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1031 /* See if operand is absolute and small; skip sethi if so. */
1032 if (the_insn.exp.X_op != O_constant
1033 || the_insn.exp.X_add_number >= (1 << 12)
1034 || the_insn.exp.X_add_number < -(1 << 12))
1036 the_insn.opcode = (SETHI_INSN | RD (rd)
1037 | ((the_insn.exp.X_add_number >> 10)
1038 & (the_insn.exp.X_op == O_constant
1040 the_insn.reloc = (the_insn.exp.X_op != O_constant
1041 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1042 output_insn (insn, &the_insn);
1046 /* See if operand has no low-order bits; skip OR if so. */
1047 if (the_insn.exp.X_op != O_constant
1048 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1051 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1053 | (the_insn.exp.X_add_number
1054 & (the_insn.exp.X_op != O_constant
1055 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1056 the_insn.reloc = (the_insn.exp.X_op != O_constant
1057 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1058 output_insn (insn, &the_insn);
1062 /* Handle the setsw synthetic instruction. */
1065 synthetize_setsw (insn)
1066 const struct sparc_opcode *insn;
1070 rd = (the_insn.opcode & RD (~0)) >> 25;
1072 if (the_insn.exp.X_op != O_constant)
1074 synthetize_setuw (insn);
1076 /* Need to sign extend it. */
1077 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1078 the_insn.reloc = BFD_RELOC_NONE;
1079 output_insn (insn, &the_insn);
1083 if (sizeof (offsetT) > 4
1084 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1085 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1086 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1088 low32 = the_insn.exp.X_add_number;
1092 synthetize_setuw (insn);
1098 the_insn.reloc = BFD_RELOC_NONE;
1099 /* See if operand is absolute and small; skip sethi if so. */
1100 if (low32 < -(1 << 12))
1102 the_insn.opcode = (SETHI_INSN | RD (rd)
1103 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1104 output_insn (insn, &the_insn);
1105 low32 = 0x1c00 | (low32 & 0x3ff);
1106 opc = RS1 (rd) | XOR_INSN;
1109 the_insn.opcode = (opc | RD (rd) | IMMED
1110 | (low32 & 0x1fff));
1111 output_insn (insn, &the_insn);
1114 /* Handle the setsw synthetic instruction. */
1117 synthetize_setx (insn)
1118 const struct sparc_opcode *insn;
1120 int upper32, lower32;
1121 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1122 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1124 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1125 int need_xor10_p = 0;
1127 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1128 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1129 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1132 upper_dstreg = tmpreg;
1133 /* The tmp reg should not be the dst reg. */
1134 if (tmpreg == dstreg)
1135 as_warn (_("setx: temporary register same as destination register"));
1137 /* ??? Obviously there are other optimizations we can do
1138 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1139 doing some of these. Later. If you do change things, try to
1140 change all of this to be table driven as well. */
1141 /* What to output depends on the number if it's constant.
1142 Compute that first, then output what we've decided upon. */
1143 if (the_insn.exp.X_op != O_constant)
1145 if (sparc_arch_size == 32)
1147 /* When arch size is 32, we want setx to be equivalent
1148 to setuw for anything but constants. */
1149 the_insn.exp.X_add_number &= 0xffffffff;
1150 synthetize_setuw (insn);
1153 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1159 /* Reset X_add_number, we've extracted it as upper32/lower32.
1160 Otherwise fixup_segment will complain about not being able to
1161 write an 8 byte number in a 4 byte field. */
1162 the_insn.exp.X_add_number = 0;
1164 /* Only need hh22 if `or' insn can't handle constant. */
1165 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1168 /* Does bottom part (after sethi) have bits? */
1169 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1170 /* No hh22, but does upper32 still have bits we can't set
1172 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1175 /* If the lower half is all zero, we build the upper half directly
1176 into the dst reg. */
1178 /* Need lower half if number is zero or 0xffffffff00000000. */
1179 || (! need_hh22_p && ! need_hm10_p))
1181 /* No need for sethi if `or' insn can handle constant. */
1182 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1183 /* Note that we can't use a negative constant in the `or'
1184 insn unless the upper 32 bits are all ones. */
1185 || (lower32 < 0 && upper32 != -1)
1186 || (lower32 >= 0 && upper32 == -1))
1189 if (need_hi22_p && upper32 == -1)
1192 /* Does bottom part (after sethi) have bits? */
1193 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1195 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1196 /* Need `or' if we didn't set anything else. */
1197 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1201 /* Output directly to dst reg if lower 32 bits are all zero. */
1202 upper_dstreg = dstreg;
1205 if (!upper_dstreg && dstreg)
1206 as_warn (_("setx: illegal temporary register g0"));
1210 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1211 | ((upper32 >> 10) & 0x3fffff));
1212 the_insn.reloc = (the_insn.exp.X_op != O_constant
1213 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1214 output_insn (insn, &the_insn);
1219 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1220 | (((need_xor10_p ? ~lower32 : lower32)
1221 >> 10) & 0x3fffff));
1222 the_insn.reloc = (the_insn.exp.X_op != O_constant
1223 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1224 output_insn (insn, &the_insn);
1229 the_insn.opcode = (OR_INSN
1230 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1233 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1234 the_insn.reloc = (the_insn.exp.X_op != O_constant
1235 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1236 output_insn (insn, &the_insn);
1241 /* FIXME: One nice optimization to do here is to OR the low part
1242 with the highpart if hi22 isn't needed and the low part is
1244 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1247 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1248 the_insn.reloc = (the_insn.exp.X_op != O_constant
1249 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1250 output_insn (insn, &the_insn);
1253 /* If we needed to build the upper part, shift it into place. */
1254 if (need_hh22_p || need_hm10_p)
1256 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1258 the_insn.reloc = BFD_RELOC_NONE;
1259 output_insn (insn, &the_insn);
1262 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1265 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1266 | 0x1c00 | (lower32 & 0x3ff));
1267 the_insn.reloc = BFD_RELOC_NONE;
1268 output_insn (insn, &the_insn);
1271 /* If we needed to build both upper and lower parts, OR them together. */
1272 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1274 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1276 the_insn.reloc = BFD_RELOC_NONE;
1277 output_insn (insn, &the_insn);
1281 /* Main entry point to assemble one instruction. */
1287 const struct sparc_opcode *insn;
1291 special_case = sparc_ip (str, &insn);
1293 /* We warn about attempts to put a floating point branch in a delay slot,
1294 unless the delay slot has been annulled. */
1296 && last_insn != NULL
1297 && (insn->flags & F_FBR) != 0
1298 && (last_insn->flags & F_DELAYED) != 0
1299 /* ??? This test isn't completely accurate. We assume anything with
1300 F_{UNBR,CONDBR,FBR} set is annullable. */
1301 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1302 || (last_opcode & ANNUL) == 0))
1303 as_warn (_("FP branch in delay slot"));
1305 /* SPARC before v9 requires a nop instruction between a floating
1306 point instruction and a floating point branch. We insert one
1307 automatically, with a warning. */
1308 if (max_architecture < SPARC_OPCODE_ARCH_V9
1310 && last_insn != NULL
1311 && (insn->flags & F_FBR) != 0
1312 && (last_insn->flags & F_FLOAT) != 0)
1314 struct sparc_it nop_insn;
1316 nop_insn.opcode = NOP_INSN;
1317 nop_insn.reloc = BFD_RELOC_NONE;
1318 output_insn (insn, &nop_insn);
1319 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1322 switch (special_case)
1324 case SPECIAL_CASE_NONE:
1326 output_insn (insn, &the_insn);
1329 case SPECIAL_CASE_SETSW:
1330 synthetize_setsw (insn);
1333 case SPECIAL_CASE_SET:
1334 synthetize_setuw (insn);
1337 case SPECIAL_CASE_SETX:
1338 synthetize_setx (insn);
1341 case SPECIAL_CASE_FDIV:
1343 int rd = (the_insn.opcode >> 25) & 0x1f;
1345 output_insn (insn, &the_insn);
1347 /* According to information leaked from Sun, the "fdiv" instructions
1348 on early SPARC machines would produce incorrect results sometimes.
1349 The workaround is to add an fmovs of the destination register to
1350 itself just after the instruction. This was true on machines
1351 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1352 assert (the_insn.reloc == BFD_RELOC_NONE);
1353 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1354 output_insn (insn, &the_insn);
1359 as_fatal (_("failed special case insn sanity check"));
1363 /* Subroutine of md_assemble to do the actual parsing. */
1366 sparc_ip (str, pinsn)
1368 const struct sparc_opcode **pinsn;
1370 char *error_message = "";
1374 const struct sparc_opcode *insn;
1376 unsigned long opcode;
1377 unsigned int mask = 0;
1381 int special_case = SPECIAL_CASE_NONE;
1384 if (islower ((unsigned char) *s))
1388 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1405 as_fatal (_("Unknown opcode: `%s'"), str);
1407 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1411 as_bad (_("Unknown opcode: `%s'"), str);
1412 return special_case;
1422 opcode = insn->match;
1423 memset (&the_insn, '\0', sizeof (the_insn));
1424 the_insn.reloc = BFD_RELOC_NONE;
1427 /* Build the opcode, checking as we go to make sure that the
1429 for (args = insn->args;; ++args)
1437 /* Parse a series of masks. */
1444 if (! parse_keyword_arg (sparc_encode_membar, &s,
1447 error_message = _(": invalid membar mask name");
1453 if (*s == '|' || *s == '+')
1461 if (! parse_const_expr_arg (&s, &kmask))
1463 error_message = _(": invalid membar mask expression");
1466 if (kmask < 0 || kmask > 127)
1468 error_message = _(": invalid membar mask number");
1473 opcode |= MEMBAR (kmask);
1481 if (! parse_const_expr_arg (&s, &smask))
1483 error_message = _(": invalid siam mode expression");
1486 if (smask < 0 || smask > 7)
1488 error_message = _(": invalid siam mode number");
1499 /* Parse a prefetch function. */
1502 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1504 error_message = _(": invalid prefetch function name");
1510 if (! parse_const_expr_arg (&s, &fcn))
1512 error_message = _(": invalid prefetch function expression");
1515 if (fcn < 0 || fcn > 31)
1517 error_message = _(": invalid prefetch function number");
1527 /* Parse a sparc64 privileged register. */
1530 struct priv_reg_entry *p = priv_reg_table;
1531 unsigned int len = 9999999; /* Init to make gcc happy. */
1534 while (p->name[0] > s[0])
1536 while (p->name[0] == s[0])
1538 len = strlen (p->name);
1539 if (strncmp (p->name, s, len) == 0)
1543 if (p->name[0] != s[0])
1545 error_message = _(": unrecognizable privileged register");
1549 opcode |= (p->regnum << 14);
1551 opcode |= (p->regnum << 25);
1557 error_message = _(": unrecognizable privileged register");
1563 /* Parse a v9a/v9b ancillary state register. */
1566 struct priv_reg_entry *p = v9a_asr_table;
1567 unsigned int len = 9999999; /* Init to make gcc happy. */
1570 while (p->name[0] > s[0])
1572 while (p->name[0] == s[0])
1574 len = strlen (p->name);
1575 if (strncmp (p->name, s, len) == 0)
1579 if (p->name[0] != s[0])
1581 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1584 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1586 error_message = _(": rd on write only ancillary state register");
1590 && (insn->architecture
1591 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1593 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1594 error_message = _(": unrecognizable v9a ancillary state register");
1598 opcode |= (p->regnum << 14);
1600 opcode |= (p->regnum << 25);
1606 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1612 if (strncmp (s, "%asr", 4) == 0)
1616 if (isdigit ((unsigned char) *s))
1620 while (isdigit ((unsigned char) *s))
1622 num = num * 10 + *s - '0';
1626 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1628 if (num < 16 || 31 < num)
1630 error_message = _(": asr number must be between 16 and 31");
1636 if (num < 0 || 31 < num)
1638 error_message = _(": asr number must be between 0 and 31");
1643 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1648 error_message = _(": expecting %asrN");
1655 the_insn.reloc = BFD_RELOC_SPARC_11;
1659 the_insn.reloc = BFD_RELOC_SPARC_10;
1663 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1664 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1665 the_insn.reloc = BFD_RELOC_SPARC_5;
1667 the_insn.reloc = BFD_RELOC_SPARC13;
1668 /* These fields are unsigned, but for upward compatibility,
1669 allow negative values as well. */
1673 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1674 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1675 the_insn.reloc = BFD_RELOC_SPARC_6;
1677 the_insn.reloc = BFD_RELOC_SPARC13;
1678 /* These fields are unsigned, but for upward compatibility,
1679 allow negative values as well. */
1683 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1688 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1693 if (*s == 'p' && s[1] == 'n')
1701 if (*s == 'p' && s[1] == 't')
1713 if (strncmp (s, "%icc", 4) == 0)
1725 if (strncmp (s, "%xcc", 4) == 0)
1737 if (strncmp (s, "%fcc0", 5) == 0)
1749 if (strncmp (s, "%fcc1", 5) == 0)
1761 if (strncmp (s, "%fcc2", 5) == 0)
1773 if (strncmp (s, "%fcc3", 5) == 0)
1781 if (strncmp (s, "%pc", 3) == 0)
1789 if (strncmp (s, "%tick", 5) == 0)
1796 case '\0': /* End of args. */
1815 case '[': /* These must match exactly. */
1823 case '#': /* Must be at least one digit. */
1824 if (isdigit ((unsigned char) *s++))
1826 while (isdigit ((unsigned char) *s))
1834 case 'C': /* Coprocessor state register. */
1835 if (strncmp (s, "%csr", 4) == 0)
1842 case 'b': /* Next operand is a coprocessor register. */
1845 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1848 if (isdigit ((unsigned char) *s))
1850 mask = 10 * (mask - '0') + (*s++ - '0');
1864 opcode |= mask << 14;
1872 opcode |= mask << 25;
1878 case 'r': /* next operand must be a register */
1888 case 'f': /* frame pointer */
1896 case 'g': /* global register */
1905 case 'i': /* in register */
1909 mask = c - '0' + 24;
1914 case 'l': /* local register */
1918 mask = (c - '0' + 16);
1923 case 'o': /* out register */
1927 mask = (c - '0' + 8);
1932 case 's': /* stack pointer */
1940 case 'r': /* any register */
1941 if (!isdigit ((unsigned char) (c = *s++)))
1956 if (isdigit ((unsigned char) *s))
1958 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1974 if ((mask & ~1) == 2 && sparc_arch_size == 64
1975 && no_undeclared_regs && ! globals[mask])
1976 as_bad (_("detected global register use not covered by .register pseudo-op"));
1978 /* Got the register, now figure out where
1979 it goes in the opcode. */
1983 opcode |= mask << 14;
1991 opcode |= mask << 25;
1995 opcode |= (mask << 25) | (mask << 14);
1999 opcode |= (mask << 25) | (mask << 0);
2005 case 'e': /* next operand is a floating point register */
2020 && ((format = *s) == 'f')
2021 && isdigit ((unsigned char) *++s))
2023 for (mask = 0; isdigit ((unsigned char) *s); ++s)
2025 mask = 10 * mask + (*s - '0');
2026 } /* read the number */
2034 } /* register must be even numbered */
2042 } /* register must be multiple of 4 */
2046 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2047 error_message = _(": There are only 64 f registers; [0-63]");
2049 error_message = _(": There are only 32 f registers; [0-31]");
2052 else if (mask >= 32)
2054 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2057 mask -= 31; /* wrap high bit */
2061 error_message = _(": There are only 32 f registers; [0-31]");
2069 } /* if not an 'f' register. */
2076 opcode |= RS1 (mask);
2082 opcode |= RS2 (mask);
2088 opcode |= RD (mask);
2097 if (strncmp (s, "%fsr", 4) == 0)
2104 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2105 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2108 case 'l': /* 22 bit PC relative immediate */
2109 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2113 case 'L': /* 30 bit immediate */
2114 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2119 case 'n': /* 22 bit immediate */
2120 the_insn.reloc = BFD_RELOC_SPARC22;
2123 case 'i': /* 13 bit immediate */
2124 the_insn.reloc = BFD_RELOC_SPARC13;
2134 char *op_arg = NULL;
2136 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2138 /* Check for %hi, etc. */
2141 static const struct ops {
2142 /* The name as it appears in assembler. */
2144 /* strlen (name), precomputed for speed */
2146 /* The reloc this pseudo-op translates to. */
2148 /* Non-zero if for v9 only. */
2150 /* Non-zero if can be used in pc-relative contexts. */
2151 int pcrel_p;/*FIXME:wip*/
2153 /* hix/lox must appear before hi/lo so %hix won't be
2154 mistaken for %hi. */
2155 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2156 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2157 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2158 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2159 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2160 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2161 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2162 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2163 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2164 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2165 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2166 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2167 { NULL, 0, 0, 0, 0 }
2169 const struct ops *o;
2171 for (o = ops; o->name; o++)
2172 if (strncmp (s + 1, o->name, o->len) == 0)
2174 if (o->name == NULL)
2177 if (s[o->len + 1] != '(')
2179 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2180 return special_case;
2184 the_insn.reloc = o->reloc;
2189 /* Note that if the get_expression() fails, we will still
2190 have created U entries in the symbol table for the
2191 'symbols' in the input string. Try not to create U
2192 symbols for registers, etc. */
2194 /* This stuff checks to see if the expression ends in
2195 +%reg. If it does, it removes the register from
2196 the expression, and re-sets 's' to point to the
2203 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2206 else if (*s1 == ')')
2215 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2216 return special_case;
2220 (void) get_expression (s);
2223 if (*s == ',' || *s == ']' || !*s)
2225 if (*s != '+' && *s != '-')
2227 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2228 return special_case;
2232 op_exp = the_insn.exp;
2233 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2236 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2239 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2241 if (s1[-2] == '%' && s1[-3] == '+')
2243 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2250 if (op_arg && s1 == s + 1)
2251 the_insn.exp.X_op = O_absent;
2253 (void) get_expression (s);
2265 (void) get_expression (s);
2273 the_insn.exp2 = the_insn.exp;
2274 the_insn.exp = op_exp;
2275 if (the_insn.exp2.X_op == O_absent)
2276 the_insn.exp2.X_op = O_illegal;
2277 else if (the_insn.exp.X_op == O_absent)
2279 the_insn.exp = the_insn.exp2;
2280 the_insn.exp2.X_op = O_illegal;
2282 else if (the_insn.exp.X_op == O_constant)
2284 valueT val = the_insn.exp.X_add_number;
2285 switch (the_insn.reloc)
2290 case BFD_RELOC_SPARC_HH22:
2291 val = BSR (val, 32);
2294 case BFD_RELOC_SPARC_LM22:
2295 case BFD_RELOC_HI22:
2296 val = (val >> 10) & 0x3fffff;
2299 case BFD_RELOC_SPARC_HM10:
2300 val = BSR (val, 32);
2303 case BFD_RELOC_LO10:
2307 case BFD_RELOC_SPARC_H44:
2312 case BFD_RELOC_SPARC_M44:
2317 case BFD_RELOC_SPARC_L44:
2321 case BFD_RELOC_SPARC_HIX22:
2323 val = (val >> 10) & 0x3fffff;
2326 case BFD_RELOC_SPARC_LOX10:
2327 val = (val & 0x3ff) | 0x1c00;
2330 the_insn.exp = the_insn.exp2;
2331 the_insn.exp.X_add_number += val;
2332 the_insn.exp2.X_op = O_illegal;
2333 the_insn.reloc = old_reloc;
2335 else if (the_insn.exp2.X_op != O_constant)
2337 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2338 return special_case;
2342 if (old_reloc != BFD_RELOC_SPARC13
2343 || the_insn.reloc != BFD_RELOC_LO10
2344 || sparc_arch_size != 64
2347 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2348 return special_case;
2350 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2354 /* Check for constants that don't require emitting a reloc. */
2355 if (the_insn.exp.X_op == O_constant
2356 && the_insn.exp.X_add_symbol == 0
2357 && the_insn.exp.X_op_symbol == 0)
2359 /* For pc-relative call instructions, we reject
2360 constants to get better code. */
2362 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2363 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2365 error_message = _(": PC-relative operand can't be a constant");
2369 /* Constants that won't fit are checked in md_apply_fix3
2370 and bfd_install_relocation.
2371 ??? It would be preferable to install the constants
2372 into the insn here and save having to create a fixS
2373 for each one. There already exists code to handle
2374 all the various cases (e.g. in md_apply_fix3 and
2375 bfd_install_relocation) so duplicating all that code
2376 here isn't right. */
2396 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2398 error_message = _(": invalid ASI name");
2404 if (! parse_const_expr_arg (&s, &asi))
2406 error_message = _(": invalid ASI expression");
2409 if (asi < 0 || asi > 255)
2411 error_message = _(": invalid ASI number");
2415 opcode |= ASI (asi);
2417 } /* Alternate space. */
2420 if (strncmp (s, "%psr", 4) == 0)
2427 case 'q': /* Floating point queue. */
2428 if (strncmp (s, "%fq", 3) == 0)
2435 case 'Q': /* Coprocessor queue. */
2436 if (strncmp (s, "%cq", 3) == 0)
2444 if (strcmp (str, "set") == 0
2445 || strcmp (str, "setuw") == 0)
2447 special_case = SPECIAL_CASE_SET;
2450 else if (strcmp (str, "setsw") == 0)
2452 special_case = SPECIAL_CASE_SETSW;
2455 else if (strcmp (str, "setx") == 0)
2457 special_case = SPECIAL_CASE_SETX;
2460 else if (strncmp (str, "fdiv", 4) == 0)
2462 special_case = SPECIAL_CASE_FDIV;
2468 if (strncmp (s, "%asi", 4) != 0)
2474 if (strncmp (s, "%fprs", 5) != 0)
2480 if (strncmp (s, "%ccr", 4) != 0)
2486 if (strncmp (s, "%tbr", 4) != 0)
2492 if (strncmp (s, "%wim", 4) != 0)
2499 char *push = input_line_pointer;
2502 input_line_pointer = s;
2504 if (e.X_op == O_constant)
2506 int n = e.X_add_number;
2507 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2508 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2510 opcode |= e.X_add_number << 5;
2513 as_bad (_("non-immediate OPF operand, ignored"));
2514 s = input_line_pointer;
2515 input_line_pointer = push;
2520 if (strncmp (s, "%y", 2) != 0)
2528 /* Parse a sparclet cpreg. */
2530 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2532 error_message = _(": invalid cpreg name");
2535 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2540 as_fatal (_("failed sanity check."));
2541 } /* switch on arg code. */
2543 /* Break out of for() loop. */
2545 } /* For each arg that we expect. */
2550 /* Args don't match. */
2551 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2552 && (insn->name == insn[1].name
2553 || !strcmp (insn->name, insn[1].name)))
2561 as_bad (_("Illegal operands%s"), error_message);
2562 return special_case;
2567 /* We have a match. Now see if the architecture is OK. */
2568 int needed_arch_mask = insn->architecture;
2573 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2574 if (! needed_arch_mask)
2576 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2579 if (needed_arch_mask
2580 & SPARC_OPCODE_SUPPORTED (current_architecture))
2583 /* Can we bump up the architecture? */
2584 else if (needed_arch_mask
2585 & SPARC_OPCODE_SUPPORTED (max_architecture))
2587 enum sparc_opcode_arch_val needed_architecture =
2588 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2589 & needed_arch_mask);
2591 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2593 && needed_architecture > warn_after_architecture)
2595 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2596 sparc_opcode_archs[current_architecture].name,
2597 sparc_opcode_archs[needed_architecture].name,
2599 warn_after_architecture = needed_architecture;
2601 current_architecture = needed_architecture;
2604 /* ??? This seems to be a bit fragile. What if the next entry in
2605 the opcode table is the one we want and it is supported?
2606 It is possible to arrange the table today so that this can't
2607 happen but what about tomorrow? */
2610 int arch, printed_one_p = 0;
2612 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2614 /* Create a list of the architectures that support the insn. */
2615 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2617 arch = sparc_ffs (needed_arch_mask);
2618 while ((1 << arch) <= needed_arch_mask)
2620 if ((1 << arch) & needed_arch_mask)
2624 strcpy (p, sparc_opcode_archs[arch].name);
2631 as_bad (_("Architecture mismatch on \"%s\"."), str);
2632 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2634 sparc_opcode_archs[max_architecture].name);
2635 return special_case;
2637 } /* If no match. */
2640 } /* Forever looking for a match. */
2642 the_insn.opcode = opcode;
2643 return special_case;
2646 /* Parse an argument that can be expressed as a keyword.
2647 (eg: #StoreStore or %ccfr).
2648 The result is a boolean indicating success.
2649 If successful, INPUT_POINTER is updated. */
2652 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2653 int (*lookup_fn) PARAMS ((const char *));
2654 char **input_pointerP;
2660 p = *input_pointerP;
2661 for (q = p + (*p == '#' || *p == '%');
2662 isalnum ((unsigned char) *q) || *q == '_';
2667 value = (*lookup_fn) (p);
2672 *input_pointerP = q;
2676 /* Parse an argument that is a constant expression.
2677 The result is a boolean indicating success. */
2680 parse_const_expr_arg (input_pointerP, valueP)
2681 char **input_pointerP;
2684 char *save = input_line_pointer;
2687 input_line_pointer = *input_pointerP;
2688 /* The next expression may be something other than a constant
2689 (say if we're not processing the right variant of the insn).
2690 Don't call expression unless we're sure it will succeed as it will
2691 signal an error (which we want to defer until later). */
2692 /* FIXME: It might be better to define md_operand and have it recognize
2693 things like %asi, etc. but continuing that route through to the end
2694 is a lot of work. */
2695 if (*input_line_pointer == '%')
2697 input_line_pointer = save;
2701 *input_pointerP = input_line_pointer;
2702 input_line_pointer = save;
2703 if (exp.X_op != O_constant)
2705 *valueP = exp.X_add_number;
2709 /* Subroutine of sparc_ip to parse an expression. */
2712 get_expression (str)
2718 save_in = input_line_pointer;
2719 input_line_pointer = str;
2720 seg = expression (&the_insn.exp);
2721 if (seg != absolute_section
2722 && seg != text_section
2723 && seg != data_section
2724 && seg != bss_section
2725 && seg != undefined_section)
2727 the_insn.error = _("bad segment");
2728 expr_end = input_line_pointer;
2729 input_line_pointer = save_in;
2732 expr_end = input_line_pointer;
2733 input_line_pointer = save_in;
2737 /* Subroutine of md_assemble to output one insn. */
2740 output_insn (insn, the_insn)
2741 const struct sparc_opcode *insn;
2742 struct sparc_it *the_insn;
2744 char *toP = frag_more (4);
2746 /* Put out the opcode. */
2747 if (INSN_BIG_ENDIAN)
2748 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2750 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2752 /* Put out the symbol-dependent stuff. */
2753 if (the_insn->reloc != BFD_RELOC_NONE)
2755 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2756 (toP - frag_now->fr_literal), /* Where. */
2761 /* Turn off overflow checking in fixup_segment. We'll do our
2762 own overflow checking in md_apply_fix3. This is necessary because
2763 the insn size is 4 and fixup_segment will signal an overflow for
2764 large 8 byte quantities. */
2765 fixP->fx_no_overflow = 1;
2766 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2767 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2771 last_opcode = the_insn->opcode;
2774 /* This is identical to the md_atof in m68k.c. I think this is right,
2777 Turn a string in input_line_pointer into a floating point constant
2778 of type TYPE, and store the appropriate bytes in *LITP. The number
2779 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2780 returned, or NULL on OK. */
2782 /* Equal to MAX_PRECISION in atof-ieee.c. */
2783 #define MAX_LITTLENUMS 6
2786 md_atof (type, litP, sizeP)
2792 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2823 return _("Bad call to MD_ATOF()");
2826 t = atof_ieee (input_line_pointer, type, words);
2828 input_line_pointer = t;
2829 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2831 if (target_big_endian)
2833 for (i = 0; i < prec; i++)
2835 md_number_to_chars (litP, (valueT) words[i],
2836 sizeof (LITTLENUM_TYPE));
2837 litP += sizeof (LITTLENUM_TYPE);
2842 for (i = prec - 1; i >= 0; i--)
2844 md_number_to_chars (litP, (valueT) words[i],
2845 sizeof (LITTLENUM_TYPE));
2846 litP += sizeof (LITTLENUM_TYPE);
2853 /* Write a value out to the object file, using the appropriate
2857 md_number_to_chars (buf, val, n)
2862 if (target_big_endian)
2863 number_to_chars_bigendian (buf, val, n);
2864 else if (target_little_endian_data
2865 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2866 /* Output debug words, which are not in allocated sections, as big
2868 number_to_chars_bigendian (buf, val, n);
2869 else if (target_little_endian_data || ! target_big_endian)
2870 number_to_chars_littleendian (buf, val, n);
2873 /* Apply a fixS to the frags, now that we know the value it ought to
2877 md_apply_fix3 (fixP, value, segment)
2882 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2888 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2890 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2893 /* FIXME: SPARC ELF relocations don't use an addend in the data
2894 field itself. This whole approach should be somehow combined
2895 with the calls to bfd_install_relocation. Also, the value passed
2896 in by fixup_segment includes the value of a defined symbol. We
2897 don't want to include the value of an externally visible symbol. */
2898 if (fixP->fx_addsy != NULL)
2900 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2901 && (S_IS_EXTERNAL (fixP->fx_addsy)
2902 || S_IS_WEAK (fixP->fx_addsy)
2903 || (sparc_pic_code && ! fixP->fx_pcrel)
2904 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2905 && ((bfd_get_section_flags (stdoutput,
2906 S_GET_SEGMENT (fixP->fx_addsy))
2907 & SEC_LINK_ONCE) != 0
2908 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2910 sizeof ".gnu.linkonce" - 1) == 0)))
2911 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2912 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2913 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2914 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2919 /* This is a hack. There should be a better way to
2920 handle this. Probably in terms of howto fields, once
2921 we can look at these fixups in terms of howtos. */
2922 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2923 val += fixP->fx_where + fixP->fx_frag->fr_address;
2926 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2927 generate a reloc, then we just want to let the reloc addend set
2928 the value. We do not want to also stuff the addend into the
2929 object file. Including the addend in the object file works when
2930 doing a static link, because the linker will ignore the object
2931 file contents. However, the dynamic linker does not ignore the
2932 object file contents. */
2933 if (fixP->fx_addsy != NULL
2934 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2937 /* When generating PIC code, we do not want an addend for a reloc
2938 against a local symbol. We adjust fx_addnumber to cancel out the
2939 value already included in val, and to also cancel out the
2940 adjustment which bfd_install_relocation will create. */
2942 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2943 && fixP->fx_addsy != NULL
2944 && ! S_IS_COMMON (fixP->fx_addsy)
2945 && symbol_section_p (fixP->fx_addsy))
2946 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2948 /* When generating PIC code, we need to fiddle to get
2949 bfd_install_relocation to do the right thing for a PC relative
2950 reloc against a local symbol which we are going to keep. */
2952 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2953 && fixP->fx_addsy != NULL
2954 && (S_IS_EXTERNAL (fixP->fx_addsy)
2955 || S_IS_WEAK (fixP->fx_addsy))
2956 && S_IS_DEFINED (fixP->fx_addsy)
2957 && ! S_IS_COMMON (fixP->fx_addsy))
2960 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2964 /* If this is a data relocation, just output VAL. */
2966 if (fixP->fx_r_type == BFD_RELOC_16)
2968 md_number_to_chars (buf, val, 2);
2970 else if (fixP->fx_r_type == BFD_RELOC_32
2971 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2973 md_number_to_chars (buf, val, 4);
2975 else if (fixP->fx_r_type == BFD_RELOC_64)
2977 md_number_to_chars (buf, val, 8);
2979 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2980 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2987 /* It's a relocation against an instruction. */
2989 if (INSN_BIG_ENDIAN)
2990 insn = bfd_getb32 ((unsigned char *) buf);
2992 insn = bfd_getl32 ((unsigned char *) buf);
2994 switch (fixP->fx_r_type)
2996 case BFD_RELOC_32_PCREL_S2:
2998 /* FIXME: This increment-by-one deserves a comment of why it's
3000 if (! sparc_pic_code
3001 || fixP->fx_addsy == NULL
3002 || symbol_section_p (fixP->fx_addsy))
3005 insn |= val & 0x3fffffff;
3007 /* See if we have a delay slot. */
3008 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3012 #define XCC (2 << 20)
3013 #define COND(x) (((x)&0xf)<<25)
3014 #define CONDA COND(0x8)
3015 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3016 #define INSN_BA (F2(0,2) | CONDA)
3017 #define INSN_OR F3(2, 0x2, 0)
3018 #define INSN_NOP F2(0,4)
3022 /* If the instruction is a call with either:
3024 arithmetic instruction with rd == %o7
3025 where rs1 != %o7 and rs2 if it is register != %o7
3026 then we can optimize if the call destination is near
3027 by changing the call into a branch always. */
3028 if (INSN_BIG_ENDIAN)
3029 delay = bfd_getb32 ((unsigned char *) buf + 4);
3031 delay = bfd_getl32 ((unsigned char *) buf + 4);
3032 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3034 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3035 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3036 || ((delay & RD (~0)) != RD (O7))))
3038 if ((delay & RS1 (~0)) == RS1 (O7)
3039 || ((delay & F3I (~0)) == 0
3040 && (delay & RS2 (~0)) == RS2 (O7)))
3042 /* Ensure the branch will fit into simm22. */
3043 if ((val & 0x3fe00000)
3044 && (val & 0x3fe00000) != 0x3fe00000)
3046 /* Check if the arch is v9 and branch will fit
3048 if (((val & 0x3c0000) == 0
3049 || (val & 0x3c0000) == 0x3c0000)
3050 && (sparc_arch_size == 64
3051 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3053 insn = INSN_BPA | (val & 0x7ffff);
3056 insn = INSN_BA | (val & 0x3fffff);
3057 if (fixP->fx_where >= 4
3058 && ((delay & (0xffffffff ^ RS1 (~0)))
3059 == (INSN_OR | RD (O7) | RS2 (G0))))
3064 if (INSN_BIG_ENDIAN)
3065 setter = bfd_getb32 ((unsigned char *) buf - 4);
3067 setter = bfd_getl32 ((unsigned char *) buf - 4);
3068 if ((setter & (0xffffffff ^ RD (~0)))
3069 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3076 If call foo was replaced with ba, replace
3077 or %rN, %g0, %o7 with nop. */
3078 reg = (delay & RS1 (~0)) >> 14;
3079 if (reg != ((setter & RD (~0)) >> 25)
3080 || reg == G0 || reg == O7)
3083 if (INSN_BIG_ENDIAN)
3084 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3086 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3091 case BFD_RELOC_SPARC_11:
3092 if (! in_signed_range (val, 0x7ff))
3093 as_bad_where (fixP->fx_file, fixP->fx_line,
3094 _("relocation overflow"));
3095 insn |= val & 0x7ff;
3098 case BFD_RELOC_SPARC_10:
3099 if (! in_signed_range (val, 0x3ff))
3100 as_bad_where (fixP->fx_file, fixP->fx_line,
3101 _("relocation overflow"));
3102 insn |= val & 0x3ff;
3105 case BFD_RELOC_SPARC_7:
3106 if (! in_bitfield_range (val, 0x7f))
3107 as_bad_where (fixP->fx_file, fixP->fx_line,
3108 _("relocation overflow"));
3112 case BFD_RELOC_SPARC_6:
3113 if (! in_bitfield_range (val, 0x3f))
3114 as_bad_where (fixP->fx_file, fixP->fx_line,
3115 _("relocation overflow"));
3119 case BFD_RELOC_SPARC_5:
3120 if (! in_bitfield_range (val, 0x1f))
3121 as_bad_where (fixP->fx_file, fixP->fx_line,
3122 _("relocation overflow"));
3126 case BFD_RELOC_SPARC_WDISP16:
3127 /* FIXME: simplify. */
3128 if (((val > 0) && (val & ~0x3fffc))
3129 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3130 as_bad_where (fixP->fx_file, fixP->fx_line,
3131 _("relocation overflow"));
3132 /* FIXME: The +1 deserves a comment. */
3133 val = (val >> 2) + 1;
3134 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3137 case BFD_RELOC_SPARC_WDISP19:
3138 /* FIXME: simplify. */
3139 if (((val > 0) && (val & ~0x1ffffc))
3140 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3141 as_bad_where (fixP->fx_file, fixP->fx_line,
3142 _("relocation overflow"));
3143 /* FIXME: The +1 deserves a comment. */
3144 val = (val >> 2) + 1;
3145 insn |= val & 0x7ffff;
3148 case BFD_RELOC_SPARC_HH22:
3149 val = BSR (val, 32);
3152 case BFD_RELOC_SPARC_LM22:
3153 case BFD_RELOC_HI22:
3154 if (!fixP->fx_addsy)
3156 insn |= (val >> 10) & 0x3fffff;
3160 /* FIXME: Need comment explaining why we do this. */
3165 case BFD_RELOC_SPARC22:
3166 if (val & ~0x003fffff)
3167 as_bad_where (fixP->fx_file, fixP->fx_line,
3168 _("relocation overflow"));
3169 insn |= (val & 0x3fffff);
3172 case BFD_RELOC_SPARC_HM10:
3173 val = BSR (val, 32);
3176 case BFD_RELOC_LO10:
3177 if (!fixP->fx_addsy)
3179 insn |= val & 0x3ff;
3183 /* FIXME: Need comment explaining why we do this. */
3188 case BFD_RELOC_SPARC_OLO10:
3190 val += fixP->tc_fix_data;
3193 case BFD_RELOC_SPARC13:
3194 if (! in_signed_range (val, 0x1fff))
3195 as_bad_where (fixP->fx_file, fixP->fx_line,
3196 _("relocation overflow"));
3197 insn |= val & 0x1fff;
3200 case BFD_RELOC_SPARC_WDISP22:
3201 val = (val >> 2) + 1;
3203 case BFD_RELOC_SPARC_BASE22:
3204 insn |= val & 0x3fffff;
3207 case BFD_RELOC_SPARC_H44:
3208 if (!fixP->fx_addsy)
3212 insn |= tval & 0x3fffff;
3216 case BFD_RELOC_SPARC_M44:
3217 if (!fixP->fx_addsy)
3218 insn |= (val >> 12) & 0x3ff;
3221 case BFD_RELOC_SPARC_L44:
3222 if (!fixP->fx_addsy)
3223 insn |= val & 0xfff;
3226 case BFD_RELOC_SPARC_HIX22:
3227 if (!fixP->fx_addsy)
3229 val ^= ~(offsetT) 0;
3230 insn |= (val >> 10) & 0x3fffff;
3234 case BFD_RELOC_SPARC_LOX10:
3235 if (!fixP->fx_addsy)
3236 insn |= 0x1c00 | (val & 0x3ff);
3239 case BFD_RELOC_NONE:
3241 as_bad_where (fixP->fx_file, fixP->fx_line,
3242 _("bad or unhandled relocation type: 0x%02x"),
3247 if (INSN_BIG_ENDIAN)
3248 bfd_putb32 (insn, (unsigned char *) buf);
3250 bfd_putl32 (insn, (unsigned char *) buf);
3253 /* Are we finished with this relocation now? */
3254 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3260 /* Translate internal representation of relocation info to BFD target
3264 tc_gen_reloc (section, fixp)
3268 static arelent *relocs[3];
3270 bfd_reloc_code_real_type code;
3272 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3275 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3276 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3277 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3279 switch (fixp->fx_r_type)
3283 case BFD_RELOC_HI22:
3284 case BFD_RELOC_LO10:
3285 case BFD_RELOC_32_PCREL_S2:
3286 case BFD_RELOC_SPARC13:
3287 case BFD_RELOC_SPARC22:
3288 case BFD_RELOC_SPARC_BASE13:
3289 case BFD_RELOC_SPARC_WDISP16:
3290 case BFD_RELOC_SPARC_WDISP19:
3291 case BFD_RELOC_SPARC_WDISP22:
3293 case BFD_RELOC_SPARC_5:
3294 case BFD_RELOC_SPARC_6:
3295 case BFD_RELOC_SPARC_7:
3296 case BFD_RELOC_SPARC_10:
3297 case BFD_RELOC_SPARC_11:
3298 case BFD_RELOC_SPARC_HH22:
3299 case BFD_RELOC_SPARC_HM10:
3300 case BFD_RELOC_SPARC_LM22:
3301 case BFD_RELOC_SPARC_PC_HH22:
3302 case BFD_RELOC_SPARC_PC_HM10:
3303 case BFD_RELOC_SPARC_PC_LM22:
3304 case BFD_RELOC_SPARC_H44:
3305 case BFD_RELOC_SPARC_M44:
3306 case BFD_RELOC_SPARC_L44:
3307 case BFD_RELOC_SPARC_HIX22:
3308 case BFD_RELOC_SPARC_LOX10:
3309 case BFD_RELOC_SPARC_REV32:
3310 case BFD_RELOC_SPARC_OLO10:
3311 case BFD_RELOC_VTABLE_ENTRY:
3312 case BFD_RELOC_VTABLE_INHERIT:
3313 code = fixp->fx_r_type;
3320 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3321 /* If we are generating PIC code, we need to generate a different
3325 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3327 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3330 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3336 case BFD_RELOC_32_PCREL_S2:
3337 if (! S_IS_DEFINED (fixp->fx_addsy)
3338 || S_IS_COMMON (fixp->fx_addsy)
3339 || S_IS_EXTERNAL (fixp->fx_addsy)
3340 || S_IS_WEAK (fixp->fx_addsy))
3341 code = BFD_RELOC_SPARC_WPLT30;
3343 case BFD_RELOC_HI22:
3344 if (fixp->fx_addsy != NULL
3345 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3346 code = BFD_RELOC_SPARC_PC22;
3348 code = BFD_RELOC_SPARC_GOT22;
3350 case BFD_RELOC_LO10:
3351 if (fixp->fx_addsy != NULL
3352 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3353 code = BFD_RELOC_SPARC_PC10;
3355 code = BFD_RELOC_SPARC_GOT10;
3357 case BFD_RELOC_SPARC13:
3358 code = BFD_RELOC_SPARC_GOT13;
3364 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3366 if (code == BFD_RELOC_SPARC_OLO10)
3367 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3369 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3370 if (reloc->howto == 0)
3372 as_bad_where (fixp->fx_file, fixp->fx_line,
3373 _("internal error: can't export reloc type %d (`%s')"),
3374 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3380 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3383 if (reloc->howto->pc_relative == 0
3384 || code == BFD_RELOC_SPARC_PC10
3385 || code == BFD_RELOC_SPARC_PC22)
3386 reloc->addend = fixp->fx_addnumber;
3387 else if (sparc_pic_code
3388 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3389 && fixp->fx_addsy != NULL
3390 && (S_IS_EXTERNAL (fixp->fx_addsy)
3391 || S_IS_WEAK (fixp->fx_addsy))
3392 && S_IS_DEFINED (fixp->fx_addsy)
3393 && ! S_IS_COMMON (fixp->fx_addsy))
3394 reloc->addend = fixp->fx_addnumber;
3396 reloc->addend = fixp->fx_offset - reloc->address;
3398 #else /* elf or coff */
3400 if (reloc->howto->pc_relative == 0
3401 || code == BFD_RELOC_SPARC_PC10
3402 || code == BFD_RELOC_SPARC_PC22)
3403 reloc->addend = fixp->fx_addnumber;
3404 else if (symbol_section_p (fixp->fx_addsy))
3405 reloc->addend = (section->vma
3406 + fixp->fx_addnumber
3407 + md_pcrel_from (fixp));
3409 reloc->addend = fixp->fx_offset;
3412 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3413 on the same location. */
3414 if (code == BFD_RELOC_SPARC_OLO10)
3416 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3419 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3421 = symbol_get_bfdsym (section_symbol (absolute_section));
3422 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3423 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3424 reloc->addend = fixp->tc_fix_data;
3430 /* We have no need to default values of symbols. */
3433 md_undefined_symbol (name)
3434 char *name ATTRIBUTE_UNUSED;
3439 /* Round up a section size to the appropriate boundary. */
3442 md_section_align (segment, size)
3443 segT segment ATTRIBUTE_UNUSED;
3447 /* This is not right for ELF; a.out wants it, and COFF will force
3448 the alignment anyways. */
3449 valueT align = ((valueT) 1
3450 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3453 /* Turn alignment value into a mask. */
3455 newsize = (size + align) & ~align;
3462 /* Exactly what point is a PC-relative offset relative TO?
3463 On the sparc, they're relative to the address of the offset, plus
3464 its size. This gets us to the following instruction.
3465 (??? Is this right? FIXME-SOON) */
3467 md_pcrel_from (fixP)
3472 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3473 if (! sparc_pic_code
3474 || fixP->fx_addsy == NULL
3475 || symbol_section_p (fixP->fx_addsy))
3476 ret += fixP->fx_size;
3480 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3492 for (shift = 0; (value & 1) == 0; value >>= 1)
3495 return (value == 1) ? shift : -1;
3498 /* Sort of like s_lcomm. */
3501 static int max_alignment = 15;
3506 int ignore ATTRIBUTE_UNUSED;
3516 name = input_line_pointer;
3517 c = get_symbol_end ();
3518 p = input_line_pointer;
3522 if (*input_line_pointer != ',')
3524 as_bad (_("Expected comma after name"));
3525 ignore_rest_of_line ();
3529 ++input_line_pointer;
3531 if ((size = get_absolute_expression ()) < 0)
3533 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3534 ignore_rest_of_line ();
3539 symbolP = symbol_find_or_make (name);
3542 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3543 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3545 as_bad (_("bad .reserve segment -- expected BSS segment"));
3549 if (input_line_pointer[2] == '.')
3550 input_line_pointer += 7;
3552 input_line_pointer += 6;
3555 if (*input_line_pointer == ',')
3557 ++input_line_pointer;
3560 if (*input_line_pointer == '\n')
3562 as_bad (_("missing alignment"));
3563 ignore_rest_of_line ();
3567 align = (int) get_absolute_expression ();
3570 if (align > max_alignment)
3572 align = max_alignment;
3573 as_warn (_("alignment too large; assuming %d"), align);
3579 as_bad (_("negative alignment"));
3580 ignore_rest_of_line ();
3586 temp = log2 (align);
3589 as_bad (_("alignment not a power of 2"));
3590 ignore_rest_of_line ();
3597 record_alignment (bss_section, align);
3602 if (!S_IS_DEFINED (symbolP)
3604 && S_GET_OTHER (symbolP) == 0
3605 && S_GET_DESC (symbolP) == 0
3612 segT current_seg = now_seg;
3613 subsegT current_subseg = now_subseg;
3615 /* Switch to bss. */
3616 subseg_set (bss_section, 1);
3620 frag_align (align, 0, 0);
3622 /* Detach from old frag. */
3623 if (S_GET_SEGMENT (symbolP) == bss_section)
3624 symbol_get_frag (symbolP)->fr_symbol = NULL;
3626 symbol_set_frag (symbolP, frag_now);
3627 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3628 (offsetT) size, (char *) 0);
3631 S_SET_SEGMENT (symbolP, bss_section);
3633 subseg_set (current_seg, current_subseg);
3636 S_SET_SIZE (symbolP, size);
3642 as_warn ("Ignoring attempt to re-define symbol %s",
3643 S_GET_NAME (symbolP));
3644 } /* if not redefining. */
3646 demand_empty_rest_of_line ();
3651 int ignore ATTRIBUTE_UNUSED;
3659 name = input_line_pointer;
3660 c = get_symbol_end ();
3661 /* Just after name is now '\0'. */
3662 p = input_line_pointer;
3665 if (*input_line_pointer != ',')
3667 as_bad (_("Expected comma after symbol-name"));
3668 ignore_rest_of_line ();
3673 input_line_pointer++;
3675 if ((temp = get_absolute_expression ()) < 0)
3677 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3678 ignore_rest_of_line ();
3683 symbolP = symbol_find_or_make (name);
3685 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3687 as_bad (_("Ignoring attempt to re-define symbol"));
3688 ignore_rest_of_line ();
3691 if (S_GET_VALUE (symbolP) != 0)
3693 if (S_GET_VALUE (symbolP) != (valueT) size)
3695 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3696 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3702 S_SET_VALUE (symbolP, (valueT) size);
3703 S_SET_EXTERNAL (symbolP);
3706 know (symbol_get_frag (symbolP) == &zero_address_frag);
3707 if (*input_line_pointer != ',')
3709 as_bad (_("Expected comma after common length"));
3710 ignore_rest_of_line ();
3713 input_line_pointer++;
3715 if (*input_line_pointer != '"')
3717 temp = get_absolute_expression ();
3720 if (temp > max_alignment)
3722 temp = max_alignment;
3723 as_warn (_("alignment too large; assuming %d"), temp);
3729 as_bad (_("negative alignment"));
3730 ignore_rest_of_line ();
3735 if (symbol_get_obj (symbolP)->local)
3743 old_subsec = now_subseg;
3748 align = log2 (temp);
3752 as_bad (_("alignment not a power of 2"));
3753 ignore_rest_of_line ();
3757 record_alignment (bss_section, align);
3758 subseg_set (bss_section, 0);
3760 frag_align (align, 0, 0);
3761 if (S_GET_SEGMENT (symbolP) == bss_section)
3762 symbol_get_frag (symbolP)->fr_symbol = 0;
3763 symbol_set_frag (symbolP, frag_now);
3764 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3765 (offsetT) size, (char *) 0);
3767 S_SET_SEGMENT (symbolP, bss_section);
3768 S_CLEAR_EXTERNAL (symbolP);
3769 S_SET_SIZE (symbolP, size);
3770 subseg_set (old_sec, old_subsec);
3773 #endif /* OBJ_ELF */
3776 S_SET_VALUE (symbolP, (valueT) size);
3778 S_SET_ALIGN (symbolP, temp);
3779 S_SET_SIZE (symbolP, size);
3781 S_SET_EXTERNAL (symbolP);
3782 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3787 input_line_pointer++;
3788 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3789 if (*input_line_pointer == '.')
3790 input_line_pointer++;
3791 /* @@ Some say data, some say bss. */
3792 if (strncmp (input_line_pointer, "bss\"", 4)
3793 && strncmp (input_line_pointer, "data\"", 5))
3795 while (*--input_line_pointer != '"')
3797 input_line_pointer--;
3798 goto bad_common_segment;
3800 while (*input_line_pointer++ != '"')
3802 goto allocate_common;
3805 #ifdef BFD_ASSEMBLER
3806 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3809 demand_empty_rest_of_line ();
3814 p = input_line_pointer;
3815 while (*p && *p != '\n')
3819 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3821 input_line_pointer = p;
3822 ignore_rest_of_line ();
3827 /* Handle the .empty pseudo-op. This supresses the warnings about
3828 invalid delay slot usage. */
3832 int ignore ATTRIBUTE_UNUSED;
3834 /* The easy way to implement is to just forget about the last
3841 int ignore ATTRIBUTE_UNUSED;
3844 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3846 input_line_pointer += 6;
3850 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3852 input_line_pointer += 6;
3856 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3858 input_line_pointer += 7;
3862 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3864 input_line_pointer += 5;
3865 /* We only support 2 segments -- text and data -- for now, so
3866 things in the "bss segment" will have to go into data for now.
3867 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3868 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3871 as_bad (_("Unknown segment type"));
3872 demand_empty_rest_of_line ();
3878 subseg_set (data_section, 1);
3879 demand_empty_rest_of_line ();
3884 int ignore ATTRIBUTE_UNUSED;
3886 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3888 ++input_line_pointer;
3890 ++input_line_pointer;
3893 /* This static variable is set by s_uacons to tell sparc_cons_align
3894 that the expession does not need to be aligned. */
3896 static int sparc_no_align_cons = 0;
3898 /* This handles the unaligned space allocation pseudo-ops, such as
3899 .uaword. .uaword is just like .word, but the value does not need
3906 /* Tell sparc_cons_align not to align this value. */
3907 sparc_no_align_cons = 1;
3911 /* This handles the native word allocation pseudo-op .nword.
3912 For sparc_arch_size 32 it is equivalent to .word, for
3913 sparc_arch_size 64 it is equivalent to .xword. */
3917 int bytes ATTRIBUTE_UNUSED;
3919 cons (sparc_arch_size == 32 ? 4 : 8);
3923 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3927 .register %g[2367],{#scratch|symbolname|#ignore}
3932 int ignore ATTRIBUTE_UNUSED;
3937 const char *regname;
3939 if (input_line_pointer[0] != '%'
3940 || input_line_pointer[1] != 'g'
3941 || ((input_line_pointer[2] & ~1) != '2'
3942 && (input_line_pointer[2] & ~1) != '6')
3943 || input_line_pointer[3] != ',')
3944 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3945 reg = input_line_pointer[2] - '0';
3946 input_line_pointer += 4;
3948 if (*input_line_pointer == '#')
3950 ++input_line_pointer;
3951 regname = input_line_pointer;
3952 c = get_symbol_end ();
3953 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3954 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3955 if (regname[0] == 'i')
3962 regname = input_line_pointer;
3963 c = get_symbol_end ();
3965 if (sparc_arch_size == 64)
3969 if ((regname && globals[reg] != (symbolS *) 1
3970 && strcmp (S_GET_NAME (globals[reg]), regname))
3971 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3972 as_bad (_("redefinition of global register"));
3976 if (regname == NULL)
3977 globals[reg] = (symbolS *) 1;
3982 if (symbol_find (regname))
3983 as_bad (_("Register symbol %s already defined."),
3986 globals[reg] = symbol_make (regname);
3987 flags = symbol_get_bfdsym (globals[reg])->flags;
3989 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3990 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3991 flags |= BSF_GLOBAL;
3992 symbol_get_bfdsym (globals[reg])->flags = flags;
3993 S_SET_VALUE (globals[reg], (valueT) reg);
3994 S_SET_ALIGN (globals[reg], reg);
3995 S_SET_SIZE (globals[reg], 0);
3996 /* Although we actually want undefined_section here,
3997 we have to use absolute_section, because otherwise
3998 generic as code will make it a COM section.
3999 We fix this up in sparc_adjust_symtab. */
4000 S_SET_SEGMENT (globals[reg], absolute_section);
4001 S_SET_OTHER (globals[reg], 0);
4002 elf_symbol (symbol_get_bfdsym (globals[reg]))
4003 ->internal_elf_sym.st_info =
4004 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4005 elf_symbol (symbol_get_bfdsym (globals[reg]))
4006 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4011 *input_line_pointer = c;
4013 demand_empty_rest_of_line ();
4016 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4017 symbols which need it. */
4020 sparc_adjust_symtab ()
4024 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4026 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4027 ->internal_elf_sym.st_info) != STT_REGISTER)
4030 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4031 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4034 S_SET_SEGMENT (sym, undefined_section);
4039 /* If the --enforce-aligned-data option is used, we require .word,
4040 et. al., to be aligned correctly. We do it by setting up an
4041 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4042 no unexpected alignment was introduced.
4044 The SunOS and Solaris native assemblers enforce aligned data by
4045 default. We don't want to do that, because gcc can deliberately
4046 generate misaligned data if the packed attribute is used. Instead,
4047 we permit misaligned data by default, and permit the user to set an
4048 option to check for it. */
4051 sparc_cons_align (nbytes)
4057 /* Only do this if we are enforcing aligned data. */
4058 if (! enforce_aligned_data)
4061 if (sparc_no_align_cons)
4063 /* This is an unaligned pseudo-op. */
4064 sparc_no_align_cons = 0;
4068 nalign = log2 (nbytes);
4072 assert (nalign > 0);
4074 if (now_seg == absolute_section)
4076 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4077 as_bad (_("misaligned data"));
4081 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
4082 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4084 record_alignment (now_seg, nalign);
4087 /* This is where we do the unexpected alignment check.
4088 This is called from HANDLE_ALIGN in tc-sparc.h. */
4091 sparc_handle_align (fragp)
4094 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
4095 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
4096 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4097 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
4100 fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4105 && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
4107 unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
4110 for (i = 0; i < count; i += 4, p++)
4111 if (INSN_BIG_ENDIAN)
4113 number_to_chars_bigendian ((char *) p, 0x01000000, 4);
4115 number_to_chars_littleendian ((char *) p, 0x10000000, 4);
4117 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4119 char *waddr = &fragp->fr_literal[fragp->fr_fix];
4120 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4121 if (INSN_BIG_ENDIAN)
4122 number_to_chars_bigendian (waddr, wval, 4);
4124 number_to_chars_littleendian (waddr, wval, 4);
4126 fragp->fr_var = count;
4132 /* Some special processing for a Sparc ELF file. */
4135 sparc_elf_final_processing ()
4137 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4138 sort of BFD interface for this. */
4139 if (sparc_arch_size == 64)
4141 switch (sparc_memory_model)
4144 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4147 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4153 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4154 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4155 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4156 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4157 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4158 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4162 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4163 reloc for a cons. We could use the definition there, except that
4164 we want to handle little endian relocs specially. */
4167 cons_fix_new_sparc (frag, where, nbytes, exp)
4170 unsigned int nbytes;
4173 bfd_reloc_code_real_type r;
4175 r = (nbytes == 1 ? BFD_RELOC_8 :
4176 (nbytes == 2 ? BFD_RELOC_16 :
4177 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4179 if (target_little_endian_data && nbytes == 4
4180 && now_seg->flags & SEC_ALLOC)
4181 r = BFD_RELOC_SPARC_REV32;
4182 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4187 elf32_sparc_force_relocation (fixp)
4190 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4191 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)