1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static struct sparc_arch *lookup_arch PARAMS ((char *));
41 static void init_default_arch PARAMS ((void));
42 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
43 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
44 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
45 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
46 static int sparc_ffs PARAMS ((unsigned int));
47 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
48 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
49 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
50 static bfd_vma BSR PARAMS ((bfd_vma, int));
51 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
52 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
53 static int parse_const_expr_arg PARAMS ((char **, int *));
54 static int get_expression PARAMS ((char *str));
56 /* Default architecture. */
57 /* ??? The default value should be V8, but sparclite support was added
58 by making it the default. GCC now passes -Asparclite, so maybe sometime in
59 the future we can set this to V8. */
61 #define DEFAULT_ARCH "sparclite"
63 static char *default_arch = DEFAULT_ARCH;
65 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
67 static int default_init_p;
69 /* Current architecture. We don't bump up unless necessary. */
70 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
72 /* The maximum architecture level we can bump up to.
73 In a 32 bit environment, don't allow bumping up to v9 by default.
74 The native assembler works this way. The user is required to pass
75 an explicit argument before we'll create v9 object files. However, if
76 we don't see any v9 insns, a v8plus object file is not created. */
77 static enum sparc_opcode_arch_val max_architecture;
79 /* Either 32 or 64, selects file format. */
80 static int sparc_arch_size;
81 /* Initial (default) value, recorded separately in case a user option
82 changes the value before md_show_usage is called. */
83 static int default_arch_size;
86 /* The currently selected v9 memory model. Currently only used for
88 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
91 static int architecture_requested;
92 static int warn_on_bump;
94 /* If warn_on_bump and the needed architecture is higher than this
95 architecture, issue a warning. */
96 static enum sparc_opcode_arch_val warn_after_architecture;
98 /* Non-zero if as should generate error if an undeclared g[23] register
99 has been used in -64. */
100 static int no_undeclared_regs;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data;
111 extern int target_big_endian;
113 static int target_little_endian_data;
115 /* Symbols for global registers on v9. */
116 static symbolS *globals[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control *op_hash;
134 static int mylog2 PARAMS ((int));
135 static void s_data1 PARAMS ((void));
136 static void s_seg PARAMS ((int));
137 static void s_proc PARAMS ((int));
138 static void s_reserve PARAMS ((int));
139 static void s_common PARAMS ((int));
140 static void s_empty PARAMS ((int));
141 static void s_uacons PARAMS ((int));
142 static void s_ncons PARAMS ((int));
144 static void s_register PARAMS ((int));
147 const pseudo_typeS md_pseudo_table[] =
149 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common, 0},
151 {"empty", s_empty, 0},
152 {"global", s_globl, 0},
154 {"nword", s_ncons, 0},
155 {"optim", s_ignore, 0},
157 {"reserve", s_reserve, 0},
159 {"skip", s_space, 0},
162 {"uahalf", s_uacons, 2},
163 {"uaword", s_uacons, 4},
164 {"uaxword", s_uacons, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
170 {"register", s_register, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode;
211 struct nlist *nlistp;
215 bfd_reloc_code_real_type reloc;
218 struct sparc_it the_insn, set_insn;
220 static void output_insn
221 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
223 /* Table of arguments to -A.
224 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
225 for this use. That table is for opcodes only. This table is for opcodes
228 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
229 v8plusa, v9, v9a, v9b, v9_64};
231 static struct sparc_arch {
234 enum sparc_arch_types arch_type;
235 /* Default word size, as specified during configuration.
236 A value of zero means can't be used to specify default architecture. */
237 int default_arch_size;
238 /* Allowable arg to -A? */
240 } sparc_arch_table[] = {
241 { "v6", "v6", v6, 0, 1 },
242 { "v7", "v7", v7, 0, 1 },
243 { "v8", "v8", v8, 32, 1 },
244 { "sparclet", "sparclet", sparclet, 32, 1 },
245 { "sparclite", "sparclite", sparclite, 32, 1 },
246 { "sparc86x", "sparclite", sparc86x, 32, 1 },
247 { "v8plus", "v9", v9, 0, 1 },
248 { "v8plusa", "v9a", v9, 0, 1 },
249 { "v8plusb", "v9b", v9, 0, 1 },
250 { "v9", "v9", v9, 0, 1 },
251 { "v9a", "v9a", v9, 0, 1 },
252 { "v9b", "v9b", v9, 0, 1 },
253 /* This exists to allow configure.in/Makefile.in to pass one
254 value to specify both the default machine and default word size. */
255 { "v9-64", "v9", v9, 64, 0 },
256 { NULL, NULL, v8, 0, 0 }
259 /* Variant of default_arch */
260 static enum sparc_arch_types default_arch_type;
262 static struct sparc_arch *
266 struct sparc_arch *sa;
268 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
269 if (strcmp (sa->name, name) == 0)
271 if (sa->name == NULL)
276 /* Initialize the default opcode arch and word size from the default
277 architecture name. */
282 struct sparc_arch *sa = lookup_arch (default_arch);
285 || sa->default_arch_size == 0)
286 as_fatal (_("Invalid default architecture, broken assembler."));
288 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
289 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
290 as_fatal (_("Bad opcode table, broken assembler."));
291 default_arch_size = sparc_arch_size = sa->default_arch_size;
293 default_arch_type = sa->arch_type;
296 /* Called by TARGET_FORMAT. */
299 sparc_target_format ()
301 /* We don't get a chance to initialize anything before we're called,
302 so handle that now. */
303 if (! default_init_p)
304 init_default_arch ();
308 return "a.out-sparc-netbsd";
311 if (target_big_endian)
312 return "a.out-sunos-big";
313 else if (default_arch_type == sparc86x && target_little_endian_data)
314 return "a.out-sunos-big";
316 return "a.out-sparc-little";
318 return "a.out-sunos-big";
329 return "coff-sparc-lynx";
336 return "elf32-sparc-vxworks";
340 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
347 * Invocation line includes a switch not recognized by the base assembler.
348 * See if it's a processor-specific option. These are:
351 * Warn on architecture bumps. See also -A.
353 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
354 * Standard 32 bit architectures.
356 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
357 * This used to only mean 64 bits, but properly specifying it
358 * complicated gcc's ASM_SPECs, so now opcode selection is
359 * specified orthogonally to word size (except when specifying
360 * the default, but that is an internal implementation detail).
361 * -Av8plus, -Av8plusa, -Av8plusb
362 * Same as -Av9{,a,b}.
363 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
364 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
366 * -xarch=v9, -xarch=v9a, -xarch=v9b
367 * Same as -Av9{,a,b} -64, for compatibility with Sun's
370 * Select the architecture and possibly the file format.
371 * Instructions or features not supported by the selected
372 * architecture cause fatal errors.
374 * The default is to start at v6, and bump the architecture up
375 * whenever an instruction is seen at a higher level. In 32 bit
376 * environments, v9 is not bumped up to, the user must pass
379 * If -bump is specified, a warning is printing when bumping to
382 * If an architecture is specified, all instructions must match
383 * that architecture. Any higher level instructions are flagged
384 * as errors. Note that in the 32 bit environment specifying
385 * -Av8plus does not automatically create a v8plus object file, a
386 * v9 insn must be seen.
388 * If both an architecture and -bump are specified, the
389 * architecture starts at the specified level, but bumps are
390 * warnings. Note that we can't set `current_architecture' to
391 * the requested level in this case: in the 32 bit environment,
392 * we still must avoid creating v8plus object files unless v9
396 * Bumping between incompatible architectures is always an
397 * error. For example, from sparclite to v9.
401 const char *md_shortopts = "A:K:VQ:sq";
404 const char *md_shortopts = "A:k";
406 const char *md_shortopts = "A:";
409 struct option md_longopts[] = {
410 #define OPTION_BUMP (OPTION_MD_BASE)
411 {"bump", no_argument, NULL, OPTION_BUMP},
412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
413 {"sparc", no_argument, NULL, OPTION_SPARC},
414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
415 {"xarch", required_argument, NULL, OPTION_XARCH},
417 #define OPTION_32 (OPTION_MD_BASE + 3)
418 {"32", no_argument, NULL, OPTION_32},
419 #define OPTION_64 (OPTION_MD_BASE + 4)
420 {"64", no_argument, NULL, OPTION_64},
421 #define OPTION_TSO (OPTION_MD_BASE + 5)
422 {"TSO", no_argument, NULL, OPTION_TSO},
423 #define OPTION_PSO (OPTION_MD_BASE + 6)
424 {"PSO", no_argument, NULL, OPTION_PSO},
425 #define OPTION_RMO (OPTION_MD_BASE + 7)
426 {"RMO", no_argument, NULL, OPTION_RMO},
428 #ifdef SPARC_BIENDIAN
429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
430 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
432 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
435 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
437 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
440 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
442 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
445 {"relax", no_argument, NULL, OPTION_RELAX},
446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
447 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
448 {NULL, no_argument, NULL, 0}
451 size_t md_longopts_size = sizeof (md_longopts);
454 md_parse_option (c, arg)
458 /* We don't get a chance to initialize anything before we're called,
459 so handle that now. */
460 if (! default_init_p)
461 init_default_arch ();
467 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
472 if (strncmp (arg, "v9", 2) != 0)
473 md_parse_option (OPTION_32, NULL);
475 md_parse_option (OPTION_64, NULL);
481 struct sparc_arch *sa;
482 enum sparc_opcode_arch_val opcode_arch;
484 sa = lookup_arch (arg);
486 || ! sa->user_option_p)
488 if (c == OPTION_XARCH)
489 as_bad (_("invalid architecture -xarch=%s"), arg);
491 as_bad (_("invalid architecture -A%s"), arg);
495 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
496 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
497 as_fatal (_("Bad opcode table, broken assembler."));
499 max_architecture = opcode_arch;
500 architecture_requested = 1;
505 /* Ignore -sparc, used by SunOS make default .s.o rule. */
508 case OPTION_ENFORCE_ALIGNED_DATA:
509 enforce_aligned_data = 1;
512 #ifdef SPARC_BIENDIAN
513 case OPTION_LITTLE_ENDIAN:
514 target_big_endian = 0;
515 if (default_arch_type != sparclet)
516 as_fatal ("This target does not support -EL");
518 case OPTION_LITTLE_ENDIAN_DATA:
519 target_little_endian_data = 1;
520 target_big_endian = 0;
521 if (default_arch_type != sparc86x
522 && default_arch_type != v9)
523 as_fatal ("This target does not support --little-endian-data");
525 case OPTION_BIG_ENDIAN:
526 target_big_endian = 1;
540 const char **list, **l;
542 sparc_arch_size = c == OPTION_32 ? 32 : 64;
543 list = bfd_target_list ();
544 for (l = list; *l != NULL; l++)
546 if (sparc_arch_size == 32)
548 if (CONST_STRNEQ (*l, "elf32-sparc"))
553 if (CONST_STRNEQ (*l, "elf64-sparc"))
558 as_fatal (_("No compiled in support for %d bit object file format"),
565 sparc_memory_model = MM_TSO;
569 sparc_memory_model = MM_PSO;
573 sparc_memory_model = MM_RMO;
581 /* Qy - do emit .comment
582 Qn - do not emit .comment. */
586 /* Use .stab instead of .stab.excl. */
590 /* quick -- Native assembler does fewer checks. */
594 if (strcmp (arg, "PIC") != 0)
595 as_warn (_("Unrecognized option following -K"));
600 case OPTION_NO_UNDECLARED_REGS:
601 no_undeclared_regs = 1;
604 case OPTION_UNDECLARED_REGS:
605 no_undeclared_regs = 0;
613 case OPTION_NO_RELAX:
625 md_show_usage (stream)
628 const struct sparc_arch *arch;
631 /* We don't get a chance to initialize anything before we're called,
632 so handle that now. */
633 if (! default_init_p)
634 init_default_arch ();
636 fprintf (stream, _("SPARC options:\n"));
638 for (arch = &sparc_arch_table[0]; arch->name; arch++)
640 if (!arch->user_option_p)
642 if (arch != &sparc_arch_table[0])
643 fprintf (stream, " | ");
644 if (column + strlen (arch->name) > 70)
647 fputc ('\n', stream);
649 column += 5 + 2 + strlen (arch->name);
650 fprintf (stream, "-A%s", arch->name);
652 for (arch = &sparc_arch_table[0]; arch->name; arch++)
654 if (!arch->user_option_p)
656 fprintf (stream, " | ");
657 if (column + strlen (arch->name) > 65)
660 fputc ('\n', stream);
662 column += 5 + 7 + strlen (arch->name);
663 fprintf (stream, "-xarch=%s", arch->name);
665 fprintf (stream, _("\n\
666 specify variant of SPARC architecture\n\
667 -bump warn when assembler switches architectures\n\
669 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
670 -relax relax jumps and branches (default)\n\
671 -no-relax avoid changing any jumps and branches\n"));
673 fprintf (stream, _("\
674 -k generate PIC\n"));
677 fprintf (stream, _("\
678 -32 create 32 bit object file\n\
679 -64 create 64 bit object file\n"));
680 fprintf (stream, _("\
681 [default is %d]\n"), default_arch_size);
682 fprintf (stream, _("\
683 -TSO use Total Store Ordering\n\
684 -PSO use Partial Store Ordering\n\
685 -RMO use Relaxed Memory Ordering\n"));
686 fprintf (stream, _("\
687 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
688 fprintf (stream, _("\
689 -KPIC generate PIC\n\
690 -V print assembler version number\n\
691 -undeclared-regs ignore application global register usage without\n\
692 appropriate .register directive (default)\n\
693 -no-undeclared-regs force error on application global register usage\n\
694 without appropriate .register directive\n\
699 #ifdef SPARC_BIENDIAN
700 fprintf (stream, _("\
701 -EL generate code for a little endian machine\n\
702 -EB generate code for a big endian machine\n\
703 --little-endian-data generate code for a machine having big endian\n\
704 instructions and little endian data.\n"));
708 /* Native operand size opcode translation. */
714 } native_op_table[] =
716 {"ldn", "ld", "ldx"},
717 {"ldna", "lda", "ldxa"},
718 {"stn", "st", "stx"},
719 {"stna", "sta", "stxa"},
720 {"slln", "sll", "sllx"},
721 {"srln", "srl", "srlx"},
722 {"sran", "sra", "srax"},
723 {"casn", "cas", "casx"},
724 {"casna", "casa", "casxa"},
725 {"clrn", "clr", "clrx"},
729 /* sparc64 privileged and hyperprivileged registers. */
731 struct priv_reg_entry
737 struct priv_reg_entry priv_reg_table[] =
757 {"", -1}, /* End marker. */
760 struct priv_reg_entry hpriv_reg_table[] =
768 {"", -1}, /* End marker. */
771 /* v9a specific asrs. */
773 struct priv_reg_entry v9a_asr_table[] =
776 {"sys_tick_cmpr", 25},
784 {"clear_softint", 21},
785 {"", -1}, /* End marker. */
789 cmp_reg_entry (parg, qarg)
793 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
794 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
796 return strcmp (q->name, p->name);
799 /* This function is called once, at assembler startup time. It should
800 set up all the tables, etc. that the MD part of the assembler will
806 register const char *retval = NULL;
808 register unsigned int i = 0;
810 /* We don't get a chance to initialize anything before md_parse_option
811 is called, and it may not be called, so handle default initialization
812 now if not already done. */
813 if (! default_init_p)
814 init_default_arch ();
816 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
817 op_hash = hash_new ();
819 while (i < (unsigned int) sparc_num_opcodes)
821 const char *name = sparc_opcodes[i].name;
822 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
825 as_bad (_("Internal error: can't hash `%s': %s\n"),
826 sparc_opcodes[i].name, retval);
831 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
833 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
834 sparc_opcodes[i].name, sparc_opcodes[i].args);
839 while (i < (unsigned int) sparc_num_opcodes
840 && !strcmp (sparc_opcodes[i].name, name));
843 for (i = 0; native_op_table[i].name; i++)
845 const struct sparc_opcode *insn;
846 char *name = ((sparc_arch_size == 32)
847 ? native_op_table[i].name32
848 : native_op_table[i].name64);
849 insn = (struct sparc_opcode *) hash_find (op_hash, name);
852 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
853 name, native_op_table[i].name);
858 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
861 as_bad (_("Internal error: can't hash `%s': %s\n"),
862 sparc_opcodes[i].name, retval);
869 as_fatal (_("Broken assembler. No assembly attempted."));
871 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
872 sizeof (priv_reg_table[0]), cmp_reg_entry);
874 /* If -bump, record the architecture level at which we start issuing
875 warnings. The behaviour is different depending upon whether an
876 architecture was explicitly specified. If it wasn't, we issue warnings
877 for all upwards bumps. If it was, we don't start issuing warnings until
878 we need to bump beyond the requested architecture or when we bump between
879 conflicting architectures. */
882 && architecture_requested)
884 /* `max_architecture' records the requested architecture.
885 Issue warnings if we go above it. */
886 warn_after_architecture = max_architecture;
888 /* Find the highest architecture level that doesn't conflict with
889 the requested one. */
890 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
891 max_architecture > warn_after_architecture;
893 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
894 warn_after_architecture))
899 /* Called after all assembly has been done. */
904 unsigned long mach = bfd_mach_sparc;
906 if (sparc_arch_size == 64)
907 switch (current_architecture)
909 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
910 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
911 default: mach = bfd_mach_sparc_v9; break;
914 switch (current_architecture)
916 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
917 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
918 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
919 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
920 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
921 be but for now it is (since that's the way it's always been
925 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
928 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
931 in_signed_range (val, max)
932 bfd_signed_vma val, max;
936 /* Sign-extend the value from the architecture word size, so that
937 0xffffffff is always considered -1 on sparc32. */
938 if (sparc_arch_size == 32)
940 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
941 val = ((val & U0xffffffff) ^ sign) - sign;
950 /* Return non-zero if VAL is in the range 0 to MAX. */
953 in_unsigned_range (val, max)
961 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
962 (e.g. -15 to +31). */
965 in_bitfield_range (val, max)
966 bfd_signed_vma val, max;
972 if (val < ~(max >> 1))
986 for (i = 0; (mask & 1) == 0; ++i)
991 /* Implement big shift right. */
997 if (sizeof (bfd_vma) <= 4 && amount >= 32)
998 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
999 return val >> amount;
1002 /* For communication between sparc_ip and get_expression. */
1003 static char *expr_end;
1005 /* Values for `special_case'.
1006 Instructions that require wierd handling because they're longer than
1008 #define SPECIAL_CASE_NONE 0
1009 #define SPECIAL_CASE_SET 1
1010 #define SPECIAL_CASE_SETSW 2
1011 #define SPECIAL_CASE_SETX 3
1012 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1013 #define SPECIAL_CASE_FDIV 4
1015 /* Bit masks of various insns. */
1016 #define NOP_INSN 0x01000000
1017 #define OR_INSN 0x80100000
1018 #define XOR_INSN 0x80180000
1019 #define FMOVS_INSN 0x81A00020
1020 #define SETHI_INSN 0x01000000
1021 #define SLLX_INSN 0x81281000
1022 #define SRA_INSN 0x81380000
1024 /* The last instruction to be assembled. */
1025 static const struct sparc_opcode *last_insn;
1026 /* The assembled opcode of `last_insn'. */
1027 static unsigned long last_opcode;
1029 /* Handle the set and setuw synthetic instructions. */
1032 synthetize_setuw (insn)
1033 const struct sparc_opcode *insn;
1035 int need_hi22_p = 0;
1036 int rd = (the_insn.opcode & RD (~0)) >> 25;
1038 if (the_insn.exp.X_op == O_constant)
1040 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1042 if (sizeof (offsetT) > 4
1043 && (the_insn.exp.X_add_number < 0
1044 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1045 as_warn (_("set: number not in 0..4294967295 range"));
1049 if (sizeof (offsetT) > 4
1050 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1051 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1052 as_warn (_("set: number not in -2147483648..4294967295 range"));
1053 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1057 /* See if operand is absolute and small; skip sethi if so. */
1058 if (the_insn.exp.X_op != O_constant
1059 || the_insn.exp.X_add_number >= (1 << 12)
1060 || the_insn.exp.X_add_number < -(1 << 12))
1062 the_insn.opcode = (SETHI_INSN | RD (rd)
1063 | ((the_insn.exp.X_add_number >> 10)
1064 & (the_insn.exp.X_op == O_constant
1066 the_insn.reloc = (the_insn.exp.X_op != O_constant
1067 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1068 output_insn (insn, &the_insn);
1072 /* See if operand has no low-order bits; skip OR if so. */
1073 if (the_insn.exp.X_op != O_constant
1074 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1077 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1079 | (the_insn.exp.X_add_number
1080 & (the_insn.exp.X_op != O_constant
1081 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1082 the_insn.reloc = (the_insn.exp.X_op != O_constant
1083 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1084 output_insn (insn, &the_insn);
1088 /* Handle the setsw synthetic instruction. */
1091 synthetize_setsw (insn)
1092 const struct sparc_opcode *insn;
1096 rd = (the_insn.opcode & RD (~0)) >> 25;
1098 if (the_insn.exp.X_op != O_constant)
1100 synthetize_setuw (insn);
1102 /* Need to sign extend it. */
1103 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1104 the_insn.reloc = BFD_RELOC_NONE;
1105 output_insn (insn, &the_insn);
1109 if (sizeof (offsetT) > 4
1110 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1111 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1112 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1114 low32 = the_insn.exp.X_add_number;
1118 synthetize_setuw (insn);
1124 the_insn.reloc = BFD_RELOC_NONE;
1125 /* See if operand is absolute and small; skip sethi if so. */
1126 if (low32 < -(1 << 12))
1128 the_insn.opcode = (SETHI_INSN | RD (rd)
1129 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1130 output_insn (insn, &the_insn);
1131 low32 = 0x1c00 | (low32 & 0x3ff);
1132 opc = RS1 (rd) | XOR_INSN;
1135 the_insn.opcode = (opc | RD (rd) | IMMED
1136 | (low32 & 0x1fff));
1137 output_insn (insn, &the_insn);
1140 /* Handle the setsw synthetic instruction. */
1143 synthetize_setx (insn)
1144 const struct sparc_opcode *insn;
1146 int upper32, lower32;
1147 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1148 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1150 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1151 int need_xor10_p = 0;
1153 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1154 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1155 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1158 upper_dstreg = tmpreg;
1159 /* The tmp reg should not be the dst reg. */
1160 if (tmpreg == dstreg)
1161 as_warn (_("setx: temporary register same as destination register"));
1163 /* ??? Obviously there are other optimizations we can do
1164 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1165 doing some of these. Later. If you do change things, try to
1166 change all of this to be table driven as well. */
1167 /* What to output depends on the number if it's constant.
1168 Compute that first, then output what we've decided upon. */
1169 if (the_insn.exp.X_op != O_constant)
1171 if (sparc_arch_size == 32)
1173 /* When arch size is 32, we want setx to be equivalent
1174 to setuw for anything but constants. */
1175 the_insn.exp.X_add_number &= 0xffffffff;
1176 synthetize_setuw (insn);
1179 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1185 /* Reset X_add_number, we've extracted it as upper32/lower32.
1186 Otherwise fixup_segment will complain about not being able to
1187 write an 8 byte number in a 4 byte field. */
1188 the_insn.exp.X_add_number = 0;
1190 /* Only need hh22 if `or' insn can't handle constant. */
1191 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1194 /* Does bottom part (after sethi) have bits? */
1195 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1196 /* No hh22, but does upper32 still have bits we can't set
1198 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1201 /* If the lower half is all zero, we build the upper half directly
1202 into the dst reg. */
1204 /* Need lower half if number is zero or 0xffffffff00000000. */
1205 || (! need_hh22_p && ! need_hm10_p))
1207 /* No need for sethi if `or' insn can handle constant. */
1208 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1209 /* Note that we can't use a negative constant in the `or'
1210 insn unless the upper 32 bits are all ones. */
1211 || (lower32 < 0 && upper32 != -1)
1212 || (lower32 >= 0 && upper32 == -1))
1215 if (need_hi22_p && upper32 == -1)
1218 /* Does bottom part (after sethi) have bits? */
1219 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1221 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1222 /* Need `or' if we didn't set anything else. */
1223 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1227 /* Output directly to dst reg if lower 32 bits are all zero. */
1228 upper_dstreg = dstreg;
1231 if (!upper_dstreg && dstreg)
1232 as_warn (_("setx: illegal temporary register g0"));
1236 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1237 | ((upper32 >> 10) & 0x3fffff));
1238 the_insn.reloc = (the_insn.exp.X_op != O_constant
1239 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1240 output_insn (insn, &the_insn);
1245 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1246 | (((need_xor10_p ? ~lower32 : lower32)
1247 >> 10) & 0x3fffff));
1248 the_insn.reloc = (the_insn.exp.X_op != O_constant
1249 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1250 output_insn (insn, &the_insn);
1255 the_insn.opcode = (OR_INSN
1256 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1259 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1260 the_insn.reloc = (the_insn.exp.X_op != O_constant
1261 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1262 output_insn (insn, &the_insn);
1267 /* FIXME: One nice optimization to do here is to OR the low part
1268 with the highpart if hi22 isn't needed and the low part is
1270 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1273 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1274 the_insn.reloc = (the_insn.exp.X_op != O_constant
1275 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1276 output_insn (insn, &the_insn);
1279 /* If we needed to build the upper part, shift it into place. */
1280 if (need_hh22_p || need_hm10_p)
1282 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1284 the_insn.reloc = BFD_RELOC_NONE;
1285 output_insn (insn, &the_insn);
1288 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1291 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1292 | 0x1c00 | (lower32 & 0x3ff));
1293 the_insn.reloc = BFD_RELOC_NONE;
1294 output_insn (insn, &the_insn);
1297 /* If we needed to build both upper and lower parts, OR them together. */
1298 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1300 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1302 the_insn.reloc = BFD_RELOC_NONE;
1303 output_insn (insn, &the_insn);
1307 /* Main entry point to assemble one instruction. */
1313 const struct sparc_opcode *insn;
1317 special_case = sparc_ip (str, &insn);
1321 /* We warn about attempts to put a floating point branch in a delay slot,
1322 unless the delay slot has been annulled. */
1323 if (last_insn != NULL
1324 && (insn->flags & F_FBR) != 0
1325 && (last_insn->flags & F_DELAYED) != 0
1326 /* ??? This test isn't completely accurate. We assume anything with
1327 F_{UNBR,CONDBR,FBR} set is annullable. */
1328 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1329 || (last_opcode & ANNUL) == 0))
1330 as_warn (_("FP branch in delay slot"));
1332 /* SPARC before v9 requires a nop instruction between a floating
1333 point instruction and a floating point branch. We insert one
1334 automatically, with a warning. */
1335 if (max_architecture < SPARC_OPCODE_ARCH_V9
1336 && last_insn != NULL
1337 && (insn->flags & F_FBR) != 0
1338 && (last_insn->flags & F_FLOAT) != 0)
1340 struct sparc_it nop_insn;
1342 nop_insn.opcode = NOP_INSN;
1343 nop_insn.reloc = BFD_RELOC_NONE;
1344 output_insn (insn, &nop_insn);
1345 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1348 switch (special_case)
1350 case SPECIAL_CASE_NONE:
1352 output_insn (insn, &the_insn);
1355 case SPECIAL_CASE_SETSW:
1356 synthetize_setsw (insn);
1359 case SPECIAL_CASE_SET:
1360 synthetize_setuw (insn);
1363 case SPECIAL_CASE_SETX:
1364 synthetize_setx (insn);
1367 case SPECIAL_CASE_FDIV:
1369 int rd = (the_insn.opcode >> 25) & 0x1f;
1371 output_insn (insn, &the_insn);
1373 /* According to information leaked from Sun, the "fdiv" instructions
1374 on early SPARC machines would produce incorrect results sometimes.
1375 The workaround is to add an fmovs of the destination register to
1376 itself just after the instruction. This was true on machines
1377 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1378 assert (the_insn.reloc == BFD_RELOC_NONE);
1379 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1380 output_insn (insn, &the_insn);
1385 as_fatal (_("failed special case insn sanity check"));
1389 /* Subroutine of md_assemble to do the actual parsing. */
1392 sparc_ip (str, pinsn)
1394 const struct sparc_opcode **pinsn;
1396 char *error_message = "";
1400 const struct sparc_opcode *insn;
1402 unsigned long opcode;
1403 unsigned int mask = 0;
1407 int special_case = SPECIAL_CASE_NONE;
1414 while (ISLOWER (*s) || ISDIGIT (*s));
1431 as_bad (_("Unknown opcode: `%s'"), str);
1433 return special_case;
1435 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1439 as_bad (_("Unknown opcode: `%s'"), str);
1440 return special_case;
1450 opcode = insn->match;
1451 memset (&the_insn, '\0', sizeof (the_insn));
1452 the_insn.reloc = BFD_RELOC_NONE;
1455 /* Build the opcode, checking as we go to make sure that the
1457 for (args = insn->args;; ++args)
1465 /* Parse a series of masks. */
1472 if (! parse_keyword_arg (sparc_encode_membar, &s,
1475 error_message = _(": invalid membar mask name");
1481 if (*s == '|' || *s == '+')
1489 if (! parse_const_expr_arg (&s, &kmask))
1491 error_message = _(": invalid membar mask expression");
1494 if (kmask < 0 || kmask > 127)
1496 error_message = _(": invalid membar mask number");
1501 opcode |= MEMBAR (kmask);
1509 if (! parse_const_expr_arg (&s, &smask))
1511 error_message = _(": invalid siam mode expression");
1514 if (smask < 0 || smask > 7)
1516 error_message = _(": invalid siam mode number");
1527 /* Parse a prefetch function. */
1530 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1532 error_message = _(": invalid prefetch function name");
1538 if (! parse_const_expr_arg (&s, &fcn))
1540 error_message = _(": invalid prefetch function expression");
1543 if (fcn < 0 || fcn > 31)
1545 error_message = _(": invalid prefetch function number");
1555 /* Parse a sparc64 privileged register. */
1558 struct priv_reg_entry *p = priv_reg_table;
1559 unsigned int len = 9999999; /* Init to make gcc happy. */
1562 while (p->name[0] > s[0])
1564 while (p->name[0] == s[0])
1566 len = strlen (p->name);
1567 if (strncmp (p->name, s, len) == 0)
1571 if (p->name[0] != s[0])
1573 error_message = _(": unrecognizable privileged register");
1577 opcode |= (p->regnum << 14);
1579 opcode |= (p->regnum << 25);
1585 error_message = _(": unrecognizable privileged register");
1591 /* Parse a sparc64 hyperprivileged register. */
1594 struct priv_reg_entry *p = hpriv_reg_table;
1595 unsigned int len = 9999999; /* Init to make gcc happy. */
1598 while (p->name[0] > s[0])
1600 while (p->name[0] == s[0])
1602 len = strlen (p->name);
1603 if (strncmp (p->name, s, len) == 0)
1607 if (p->name[0] != s[0])
1609 error_message = _(": unrecognizable hyperprivileged register");
1613 opcode |= (p->regnum << 14);
1615 opcode |= (p->regnum << 25);
1621 error_message = _(": unrecognizable hyperprivileged register");
1627 /* Parse a v9a/v9b ancillary state register. */
1630 struct priv_reg_entry *p = v9a_asr_table;
1631 unsigned int len = 9999999; /* Init to make gcc happy. */
1634 while (p->name[0] > s[0])
1636 while (p->name[0] == s[0])
1638 len = strlen (p->name);
1639 if (strncmp (p->name, s, len) == 0)
1643 if (p->name[0] != s[0])
1645 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1648 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1650 error_message = _(": rd on write only ancillary state register");
1654 && (insn->architecture
1655 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1657 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1658 error_message = _(": unrecognizable v9a ancillary state register");
1662 opcode |= (p->regnum << 14);
1664 opcode |= (p->regnum << 25);
1670 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1676 if (strncmp (s, "%asr", 4) == 0)
1684 while (ISDIGIT (*s))
1686 num = num * 10 + *s - '0';
1690 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1692 if (num < 16 || 31 < num)
1694 error_message = _(": asr number must be between 16 and 31");
1700 if (num < 0 || 31 < num)
1702 error_message = _(": asr number must be between 0 and 31");
1707 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1712 error_message = _(": expecting %asrN");
1719 the_insn.reloc = BFD_RELOC_SPARC_11;
1723 the_insn.reloc = BFD_RELOC_SPARC_10;
1727 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1728 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1729 the_insn.reloc = BFD_RELOC_SPARC_5;
1731 the_insn.reloc = BFD_RELOC_SPARC13;
1732 /* These fields are unsigned, but for upward compatibility,
1733 allow negative values as well. */
1737 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1738 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1739 the_insn.reloc = BFD_RELOC_SPARC_6;
1741 the_insn.reloc = BFD_RELOC_SPARC13;
1742 /* These fields are unsigned, but for upward compatibility,
1743 allow negative values as well. */
1747 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1752 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1757 if (*s == 'p' && s[1] == 'n')
1765 if (*s == 'p' && s[1] == 't')
1777 if (strncmp (s, "%icc", 4) == 0)
1789 if (strncmp (s, "%xcc", 4) == 0)
1801 if (strncmp (s, "%fcc0", 5) == 0)
1813 if (strncmp (s, "%fcc1", 5) == 0)
1825 if (strncmp (s, "%fcc2", 5) == 0)
1837 if (strncmp (s, "%fcc3", 5) == 0)
1845 if (strncmp (s, "%pc", 3) == 0)
1853 if (strncmp (s, "%tick", 5) == 0)
1860 case '\0': /* End of args. */
1861 if (s[0] == ',' && s[1] == '%')
1863 static const struct tls_ops
1865 /* The name as it appears in assembler. */
1867 /* strlen (name), precomputed for speed */
1869 /* The reloc this pseudo-op translates to. */
1876 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1877 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1878 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1879 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1880 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1881 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1882 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1883 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1886 const struct tls_ops *o;
1890 for (o = tls_ops; o->name; o++)
1891 if (strncmp (s + 2, o->name, o->len) == 0)
1893 if (o->name == NULL)
1896 if (s[o->len + 2] != '(')
1898 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1899 return special_case;
1902 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
1904 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1906 return special_case;
1910 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
1911 || the_insn.exp.X_add_number != 0
1912 || the_insn.exp.X_add_symbol
1913 != symbol_find_or_make ("__tls_get_addr")))
1915 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1917 return special_case;
1920 the_insn.reloc = o->reloc;
1921 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
1924 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
1927 else if (*s1 == ')')
1936 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1937 return special_case;
1941 (void) get_expression (s);
1961 case '[': /* These must match exactly. */
1969 case '#': /* Must be at least one digit. */
1972 while (ISDIGIT (*s))
1980 case 'C': /* Coprocessor state register. */
1981 if (strncmp (s, "%csr", 4) == 0)
1988 case 'b': /* Next operand is a coprocessor register. */
1991 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
1996 mask = 10 * (mask - '0') + (*s++ - '0');
2010 opcode |= mask << 14;
2018 opcode |= mask << 25;
2024 case 'r': /* next operand must be a register */
2034 case 'f': /* frame pointer */
2042 case 'g': /* global register */
2051 case 'i': /* in register */
2055 mask = c - '0' + 24;
2060 case 'l': /* local register */
2064 mask = (c - '0' + 16);
2069 case 'o': /* out register */
2073 mask = (c - '0' + 8);
2078 case 's': /* stack pointer */
2086 case 'r': /* any register */
2087 if (!ISDIGIT ((c = *s++)))
2104 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2120 if ((mask & ~1) == 2 && sparc_arch_size == 64
2121 && no_undeclared_regs && ! globals[mask])
2122 as_bad (_("detected global register use not covered by .register pseudo-op"));
2124 /* Got the register, now figure out where
2125 it goes in the opcode. */
2129 opcode |= mask << 14;
2137 opcode |= mask << 25;
2141 opcode |= (mask << 25) | (mask << 14);
2145 opcode |= (mask << 25) | (mask << 0);
2151 case 'e': /* next operand is a floating point register */
2166 && ((format = *s) == 'f')
2169 for (mask = 0; ISDIGIT (*s); ++s)
2171 mask = 10 * mask + (*s - '0');
2172 } /* read the number */
2180 } /* register must be even numbered */
2188 } /* register must be multiple of 4 */
2192 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2193 error_message = _(": There are only 64 f registers; [0-63]");
2195 error_message = _(": There are only 32 f registers; [0-31]");
2198 else if (mask >= 32)
2200 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2202 if (*args == 'e' || *args == 'f' || *args == 'g')
2205 = _(": There are only 32 single precision f registers; [0-31]");
2209 mask -= 31; /* wrap high bit */
2213 error_message = _(": There are only 32 f registers; [0-31]");
2221 } /* if not an 'f' register. */
2228 opcode |= RS1 (mask);
2234 opcode |= RS2 (mask);
2240 opcode |= RD (mask);
2249 if (strncmp (s, "%fsr", 4) == 0)
2256 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2257 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2260 case 'l': /* 22 bit PC relative immediate */
2261 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2265 case 'L': /* 30 bit immediate */
2266 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2271 case 'n': /* 22 bit immediate */
2272 the_insn.reloc = BFD_RELOC_SPARC22;
2275 case 'i': /* 13 bit immediate */
2276 the_insn.reloc = BFD_RELOC_SPARC13;
2286 char *op_arg = NULL;
2287 static expressionS op_exp;
2288 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2290 /* Check for %hi, etc. */
2293 static const struct ops {
2294 /* The name as it appears in assembler. */
2296 /* strlen (name), precomputed for speed */
2298 /* The reloc this pseudo-op translates to. */
2300 /* Non-zero if for v9 only. */
2302 /* Non-zero if can be used in pc-relative contexts. */
2303 int pcrel_p;/*FIXME:wip*/
2305 /* hix/lox must appear before hi/lo so %hix won't be
2306 mistaken for %hi. */
2307 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2308 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2309 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2310 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2311 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2312 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2313 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2314 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2315 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2316 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2317 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2318 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2331 { NULL, 0, 0, 0, 0 }
2333 const struct ops *o;
2335 for (o = ops; o->name; o++)
2336 if (strncmp (s + 1, o->name, o->len) == 0)
2338 if (o->name == NULL)
2341 if (s[o->len + 1] != '(')
2343 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2344 return special_case;
2348 the_insn.reloc = o->reloc;
2353 /* Note that if the get_expression() fails, we will still
2354 have created U entries in the symbol table for the
2355 'symbols' in the input string. Try not to create U
2356 symbols for registers, etc. */
2358 /* This stuff checks to see if the expression ends in
2359 +%reg. If it does, it removes the register from
2360 the expression, and re-sets 's' to point to the
2367 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2370 else if (*s1 == ')')
2379 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2380 return special_case;
2384 (void) get_expression (s);
2387 if (*s == ',' || *s == ']' || !*s)
2389 if (*s != '+' && *s != '-')
2391 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2392 return special_case;
2396 op_exp = the_insn.exp;
2397 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2400 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2403 if (s1 != s && ISDIGIT (s1[-1]))
2405 if (s1[-2] == '%' && s1[-3] == '+')
2407 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2414 if (op_arg && s1 == s + 1)
2415 the_insn.exp.X_op = O_absent;
2417 (void) get_expression (s);
2429 (void) get_expression (s);
2437 the_insn.exp2 = the_insn.exp;
2438 the_insn.exp = op_exp;
2439 if (the_insn.exp2.X_op == O_absent)
2440 the_insn.exp2.X_op = O_illegal;
2441 else if (the_insn.exp.X_op == O_absent)
2443 the_insn.exp = the_insn.exp2;
2444 the_insn.exp2.X_op = O_illegal;
2446 else if (the_insn.exp.X_op == O_constant)
2448 valueT val = the_insn.exp.X_add_number;
2449 switch (the_insn.reloc)
2454 case BFD_RELOC_SPARC_HH22:
2455 val = BSR (val, 32);
2458 case BFD_RELOC_SPARC_LM22:
2459 case BFD_RELOC_HI22:
2460 val = (val >> 10) & 0x3fffff;
2463 case BFD_RELOC_SPARC_HM10:
2464 val = BSR (val, 32);
2467 case BFD_RELOC_LO10:
2471 case BFD_RELOC_SPARC_H44:
2476 case BFD_RELOC_SPARC_M44:
2481 case BFD_RELOC_SPARC_L44:
2485 case BFD_RELOC_SPARC_HIX22:
2487 val = (val >> 10) & 0x3fffff;
2490 case BFD_RELOC_SPARC_LOX10:
2491 val = (val & 0x3ff) | 0x1c00;
2494 the_insn.exp = the_insn.exp2;
2495 the_insn.exp.X_add_number += val;
2496 the_insn.exp2.X_op = O_illegal;
2497 the_insn.reloc = old_reloc;
2499 else if (the_insn.exp2.X_op != O_constant)
2501 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2502 return special_case;
2506 if (old_reloc != BFD_RELOC_SPARC13
2507 || the_insn.reloc != BFD_RELOC_LO10
2508 || sparc_arch_size != 64
2511 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2512 return special_case;
2514 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2518 /* Check for constants that don't require emitting a reloc. */
2519 if (the_insn.exp.X_op == O_constant
2520 && the_insn.exp.X_add_symbol == 0
2521 && the_insn.exp.X_op_symbol == 0)
2523 /* For pc-relative call instructions, we reject
2524 constants to get better code. */
2526 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2527 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2529 error_message = _(": PC-relative operand can't be a constant");
2533 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2534 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2536 error_message = _(": TLS operand can't be a constant");
2540 /* Constants that won't fit are checked in md_apply_fix
2541 and bfd_install_relocation.
2542 ??? It would be preferable to install the constants
2543 into the insn here and save having to create a fixS
2544 for each one. There already exists code to handle
2545 all the various cases (e.g. in md_apply_fix and
2546 bfd_install_relocation) so duplicating all that code
2547 here isn't right. */
2567 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2569 error_message = _(": invalid ASI name");
2575 if (! parse_const_expr_arg (&s, &asi))
2577 error_message = _(": invalid ASI expression");
2580 if (asi < 0 || asi > 255)
2582 error_message = _(": invalid ASI number");
2586 opcode |= ASI (asi);
2588 } /* Alternate space. */
2591 if (strncmp (s, "%psr", 4) == 0)
2598 case 'q': /* Floating point queue. */
2599 if (strncmp (s, "%fq", 3) == 0)
2606 case 'Q': /* Coprocessor queue. */
2607 if (strncmp (s, "%cq", 3) == 0)
2615 if (strcmp (str, "set") == 0
2616 || strcmp (str, "setuw") == 0)
2618 special_case = SPECIAL_CASE_SET;
2621 else if (strcmp (str, "setsw") == 0)
2623 special_case = SPECIAL_CASE_SETSW;
2626 else if (strcmp (str, "setx") == 0)
2628 special_case = SPECIAL_CASE_SETX;
2631 else if (strncmp (str, "fdiv", 4) == 0)
2633 special_case = SPECIAL_CASE_FDIV;
2639 if (strncmp (s, "%asi", 4) != 0)
2645 if (strncmp (s, "%fprs", 5) != 0)
2651 if (strncmp (s, "%ccr", 4) != 0)
2657 if (strncmp (s, "%tbr", 4) != 0)
2663 if (strncmp (s, "%wim", 4) != 0)
2670 char *push = input_line_pointer;
2673 input_line_pointer = s;
2675 if (e.X_op == O_constant)
2677 int n = e.X_add_number;
2678 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2679 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2681 opcode |= e.X_add_number << 5;
2684 as_bad (_("non-immediate OPF operand, ignored"));
2685 s = input_line_pointer;
2686 input_line_pointer = push;
2691 if (strncmp (s, "%y", 2) != 0)
2699 /* Parse a sparclet cpreg. */
2701 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2703 error_message = _(": invalid cpreg name");
2706 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2711 as_fatal (_("failed sanity check."));
2712 } /* switch on arg code. */
2714 /* Break out of for() loop. */
2716 } /* For each arg that we expect. */
2721 /* Args don't match. */
2722 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2723 && (insn->name == insn[1].name
2724 || !strcmp (insn->name, insn[1].name)))
2732 as_bad (_("Illegal operands%s"), error_message);
2733 return special_case;
2738 /* We have a match. Now see if the architecture is OK. */
2739 int needed_arch_mask = insn->architecture;
2744 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2745 if (! needed_arch_mask)
2747 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2750 if (needed_arch_mask
2751 & SPARC_OPCODE_SUPPORTED (current_architecture))
2754 /* Can we bump up the architecture? */
2755 else if (needed_arch_mask
2756 & SPARC_OPCODE_SUPPORTED (max_architecture))
2758 enum sparc_opcode_arch_val needed_architecture =
2759 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2760 & needed_arch_mask);
2762 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2764 && needed_architecture > warn_after_architecture)
2766 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2767 sparc_opcode_archs[current_architecture].name,
2768 sparc_opcode_archs[needed_architecture].name,
2770 warn_after_architecture = needed_architecture;
2772 current_architecture = needed_architecture;
2775 /* ??? This seems to be a bit fragile. What if the next entry in
2776 the opcode table is the one we want and it is supported?
2777 It is possible to arrange the table today so that this can't
2778 happen but what about tomorrow? */
2781 int arch, printed_one_p = 0;
2783 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2785 /* Create a list of the architectures that support the insn. */
2786 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2788 arch = sparc_ffs (needed_arch_mask);
2789 while ((1 << arch) <= needed_arch_mask)
2791 if ((1 << arch) & needed_arch_mask)
2795 strcpy (p, sparc_opcode_archs[arch].name);
2802 as_bad (_("Architecture mismatch on \"%s\"."), str);
2803 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2805 sparc_opcode_archs[max_architecture].name);
2806 return special_case;
2808 } /* If no match. */
2811 } /* Forever looking for a match. */
2813 the_insn.opcode = opcode;
2814 return special_case;
2817 /* Parse an argument that can be expressed as a keyword.
2818 (eg: #StoreStore or %ccfr).
2819 The result is a boolean indicating success.
2820 If successful, INPUT_POINTER is updated. */
2823 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2824 int (*lookup_fn) PARAMS ((const char *));
2825 char **input_pointerP;
2831 p = *input_pointerP;
2832 for (q = p + (*p == '#' || *p == '%');
2833 ISALNUM (*q) || *q == '_';
2838 value = (*lookup_fn) (p);
2843 *input_pointerP = q;
2847 /* Parse an argument that is a constant expression.
2848 The result is a boolean indicating success. */
2851 parse_const_expr_arg (input_pointerP, valueP)
2852 char **input_pointerP;
2855 char *save = input_line_pointer;
2858 input_line_pointer = *input_pointerP;
2859 /* The next expression may be something other than a constant
2860 (say if we're not processing the right variant of the insn).
2861 Don't call expression unless we're sure it will succeed as it will
2862 signal an error (which we want to defer until later). */
2863 /* FIXME: It might be better to define md_operand and have it recognize
2864 things like %asi, etc. but continuing that route through to the end
2865 is a lot of work. */
2866 if (*input_line_pointer == '%')
2868 input_line_pointer = save;
2872 *input_pointerP = input_line_pointer;
2873 input_line_pointer = save;
2874 if (exp.X_op != O_constant)
2876 *valueP = exp.X_add_number;
2880 /* Subroutine of sparc_ip to parse an expression. */
2883 get_expression (str)
2889 save_in = input_line_pointer;
2890 input_line_pointer = str;
2891 seg = expression (&the_insn.exp);
2892 if (seg != absolute_section
2893 && seg != text_section
2894 && seg != data_section
2895 && seg != bss_section
2896 && seg != undefined_section)
2898 the_insn.error = _("bad segment");
2899 expr_end = input_line_pointer;
2900 input_line_pointer = save_in;
2903 expr_end = input_line_pointer;
2904 input_line_pointer = save_in;
2908 /* Subroutine of md_assemble to output one insn. */
2911 output_insn (insn, the_insn)
2912 const struct sparc_opcode *insn;
2913 struct sparc_it *the_insn;
2915 char *toP = frag_more (4);
2917 /* Put out the opcode. */
2918 if (INSN_BIG_ENDIAN)
2919 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2921 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2923 /* Put out the symbol-dependent stuff. */
2924 if (the_insn->reloc != BFD_RELOC_NONE)
2926 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2927 (toP - frag_now->fr_literal), /* Where. */
2932 /* Turn off overflow checking in fixup_segment. We'll do our
2933 own overflow checking in md_apply_fix. This is necessary because
2934 the insn size is 4 and fixup_segment will signal an overflow for
2935 large 8 byte quantities. */
2936 fixP->fx_no_overflow = 1;
2937 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2938 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2942 last_opcode = the_insn->opcode;
2945 dwarf2_emit_insn (4);
2950 md_atof (int type, char *litP, int *sizeP)
2952 return ieee_md_atof (type, litP, sizeP, target_big_endian);
2955 /* Write a value out to the object file, using the appropriate
2959 md_number_to_chars (buf, val, n)
2964 if (target_big_endian)
2965 number_to_chars_bigendian (buf, val, n);
2966 else if (target_little_endian_data
2967 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2968 /* Output debug words, which are not in allocated sections, as big
2970 number_to_chars_bigendian (buf, val, n);
2971 else if (target_little_endian_data || ! target_big_endian)
2972 number_to_chars_littleendian (buf, val, n);
2975 /* Apply a fixS to the frags, now that we know the value it ought to
2979 md_apply_fix (fixP, valP, segment)
2982 segT segment ATTRIBUTE_UNUSED;
2984 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2985 offsetT val = * (offsetT *) valP;
2988 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2990 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2993 /* SPARC ELF relocations don't use an addend in the data field. */
2994 if (fixP->fx_addsy != NULL)
2996 switch (fixP->fx_r_type)
2998 case BFD_RELOC_SPARC_TLS_GD_HI22:
2999 case BFD_RELOC_SPARC_TLS_GD_LO10:
3000 case BFD_RELOC_SPARC_TLS_GD_ADD:
3001 case BFD_RELOC_SPARC_TLS_GD_CALL:
3002 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3003 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3004 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3005 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3006 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3007 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3008 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3009 case BFD_RELOC_SPARC_TLS_IE_HI22:
3010 case BFD_RELOC_SPARC_TLS_IE_LO10:
3011 case BFD_RELOC_SPARC_TLS_IE_LD:
3012 case BFD_RELOC_SPARC_TLS_IE_LDX:
3013 case BFD_RELOC_SPARC_TLS_IE_ADD:
3014 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3015 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3016 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3017 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3018 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3019 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3020 case BFD_RELOC_SPARC_TLS_TPOFF32:
3021 case BFD_RELOC_SPARC_TLS_TPOFF64:
3022 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3032 /* This is a hack. There should be a better way to
3033 handle this. Probably in terms of howto fields, once
3034 we can look at these fixups in terms of howtos. */
3035 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3036 val += fixP->fx_where + fixP->fx_frag->fr_address;
3039 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3040 generate a reloc, then we just want to let the reloc addend set
3041 the value. We do not want to also stuff the addend into the
3042 object file. Including the addend in the object file works when
3043 doing a static link, because the linker will ignore the object
3044 file contents. However, the dynamic linker does not ignore the
3045 object file contents. */
3046 if (fixP->fx_addsy != NULL
3047 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3050 /* When generating PIC code, we do not want an addend for a reloc
3051 against a local symbol. We adjust fx_addnumber to cancel out the
3052 value already included in val, and to also cancel out the
3053 adjustment which bfd_install_relocation will create. */
3055 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3056 && fixP->fx_addsy != NULL
3057 && ! S_IS_COMMON (fixP->fx_addsy)
3058 && symbol_section_p (fixP->fx_addsy))
3059 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3061 /* When generating PIC code, we need to fiddle to get
3062 bfd_install_relocation to do the right thing for a PC relative
3063 reloc against a local symbol which we are going to keep. */
3065 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3066 && fixP->fx_addsy != NULL
3067 && (S_IS_EXTERNAL (fixP->fx_addsy)
3068 || S_IS_WEAK (fixP->fx_addsy))
3069 && S_IS_DEFINED (fixP->fx_addsy)
3070 && ! S_IS_COMMON (fixP->fx_addsy))
3073 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3077 /* If this is a data relocation, just output VAL. */
3079 if (fixP->fx_r_type == BFD_RELOC_16
3080 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3082 md_number_to_chars (buf, val, 2);
3084 else if (fixP->fx_r_type == BFD_RELOC_32
3085 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3086 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3088 md_number_to_chars (buf, val, 4);
3090 else if (fixP->fx_r_type == BFD_RELOC_64
3091 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3093 md_number_to_chars (buf, val, 8);
3095 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3096 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3103 /* It's a relocation against an instruction. */
3105 if (INSN_BIG_ENDIAN)
3106 insn = bfd_getb32 ((unsigned char *) buf);
3108 insn = bfd_getl32 ((unsigned char *) buf);
3110 switch (fixP->fx_r_type)
3112 case BFD_RELOC_32_PCREL_S2:
3114 /* FIXME: This increment-by-one deserves a comment of why it's
3116 if (! sparc_pic_code
3117 || fixP->fx_addsy == NULL
3118 || symbol_section_p (fixP->fx_addsy))
3121 insn |= val & 0x3fffffff;
3123 /* See if we have a delay slot. */
3124 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3128 #define XCC (2 << 20)
3129 #define COND(x) (((x)&0xf)<<25)
3130 #define CONDA COND(0x8)
3131 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3132 #define INSN_BA (F2(0,2) | CONDA)
3133 #define INSN_OR F3(2, 0x2, 0)
3134 #define INSN_NOP F2(0,4)
3138 /* If the instruction is a call with either:
3140 arithmetic instruction with rd == %o7
3141 where rs1 != %o7 and rs2 if it is register != %o7
3142 then we can optimize if the call destination is near
3143 by changing the call into a branch always. */
3144 if (INSN_BIG_ENDIAN)
3145 delay = bfd_getb32 ((unsigned char *) buf + 4);
3147 delay = bfd_getl32 ((unsigned char *) buf + 4);
3148 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3150 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3151 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3152 || ((delay & RD (~0)) != RD (O7))))
3154 if ((delay & RS1 (~0)) == RS1 (O7)
3155 || ((delay & F3I (~0)) == 0
3156 && (delay & RS2 (~0)) == RS2 (O7)))
3158 /* Ensure the branch will fit into simm22. */
3159 if ((val & 0x3fe00000)
3160 && (val & 0x3fe00000) != 0x3fe00000)
3162 /* Check if the arch is v9 and branch will fit
3164 if (((val & 0x3c0000) == 0
3165 || (val & 0x3c0000) == 0x3c0000)
3166 && (sparc_arch_size == 64
3167 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3169 insn = INSN_BPA | (val & 0x7ffff);
3172 insn = INSN_BA | (val & 0x3fffff);
3173 if (fixP->fx_where >= 4
3174 && ((delay & (0xffffffff ^ RS1 (~0)))
3175 == (INSN_OR | RD (O7) | RS2 (G0))))
3180 if (INSN_BIG_ENDIAN)
3181 setter = bfd_getb32 ((unsigned char *) buf - 4);
3183 setter = bfd_getl32 ((unsigned char *) buf - 4);
3184 if ((setter & (0xffffffff ^ RD (~0)))
3185 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3192 If call foo was replaced with ba, replace
3193 or %rN, %g0, %o7 with nop. */
3194 reg = (delay & RS1 (~0)) >> 14;
3195 if (reg != ((setter & RD (~0)) >> 25)
3196 || reg == G0 || reg == O7)
3199 if (INSN_BIG_ENDIAN)
3200 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3202 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3207 case BFD_RELOC_SPARC_11:
3208 if (! in_signed_range (val, 0x7ff))
3209 as_bad_where (fixP->fx_file, fixP->fx_line,
3210 _("relocation overflow"));
3211 insn |= val & 0x7ff;
3214 case BFD_RELOC_SPARC_10:
3215 if (! in_signed_range (val, 0x3ff))
3216 as_bad_where (fixP->fx_file, fixP->fx_line,
3217 _("relocation overflow"));
3218 insn |= val & 0x3ff;
3221 case BFD_RELOC_SPARC_7:
3222 if (! in_bitfield_range (val, 0x7f))
3223 as_bad_where (fixP->fx_file, fixP->fx_line,
3224 _("relocation overflow"));
3228 case BFD_RELOC_SPARC_6:
3229 if (! in_bitfield_range (val, 0x3f))
3230 as_bad_where (fixP->fx_file, fixP->fx_line,
3231 _("relocation overflow"));
3235 case BFD_RELOC_SPARC_5:
3236 if (! in_bitfield_range (val, 0x1f))
3237 as_bad_where (fixP->fx_file, fixP->fx_line,
3238 _("relocation overflow"));
3242 case BFD_RELOC_SPARC_WDISP16:
3245 || val <= -(offsetT) 0x20008)
3246 as_bad_where (fixP->fx_file, fixP->fx_line,
3247 _("relocation overflow"));
3248 /* FIXME: The +1 deserves a comment. */
3249 val = (val >> 2) + 1;
3250 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3253 case BFD_RELOC_SPARC_WDISP19:
3256 || val <= -(offsetT) 0x100008)
3257 as_bad_where (fixP->fx_file, fixP->fx_line,
3258 _("relocation overflow"));
3259 /* FIXME: The +1 deserves a comment. */
3260 val = (val >> 2) + 1;
3261 insn |= val & 0x7ffff;
3264 case BFD_RELOC_SPARC_HH22:
3265 val = BSR (val, 32);
3268 case BFD_RELOC_SPARC_LM22:
3269 case BFD_RELOC_HI22:
3270 if (!fixP->fx_addsy)
3271 insn |= (val >> 10) & 0x3fffff;
3273 /* FIXME: Need comment explaining why we do this. */
3277 case BFD_RELOC_SPARC22:
3278 if (val & ~0x003fffff)
3279 as_bad_where (fixP->fx_file, fixP->fx_line,
3280 _("relocation overflow"));
3281 insn |= (val & 0x3fffff);
3284 case BFD_RELOC_SPARC_HM10:
3285 val = BSR (val, 32);
3288 case BFD_RELOC_LO10:
3289 if (!fixP->fx_addsy)
3290 insn |= val & 0x3ff;
3292 /* FIXME: Need comment explaining why we do this. */
3296 case BFD_RELOC_SPARC_OLO10:
3298 val += fixP->tc_fix_data;
3301 case BFD_RELOC_SPARC13:
3302 if (! in_signed_range (val, 0x1fff))
3303 as_bad_where (fixP->fx_file, fixP->fx_line,
3304 _("relocation overflow"));
3305 insn |= val & 0x1fff;
3308 case BFD_RELOC_SPARC_WDISP22:
3309 val = (val >> 2) + 1;
3311 case BFD_RELOC_SPARC_BASE22:
3312 insn |= val & 0x3fffff;
3315 case BFD_RELOC_SPARC_H44:
3316 if (!fixP->fx_addsy)
3320 insn |= tval & 0x3fffff;
3324 case BFD_RELOC_SPARC_M44:
3325 if (!fixP->fx_addsy)
3326 insn |= (val >> 12) & 0x3ff;
3329 case BFD_RELOC_SPARC_L44:
3330 if (!fixP->fx_addsy)
3331 insn |= val & 0xfff;
3334 case BFD_RELOC_SPARC_HIX22:
3335 if (!fixP->fx_addsy)
3337 val ^= ~(offsetT) 0;
3338 insn |= (val >> 10) & 0x3fffff;
3342 case BFD_RELOC_SPARC_LOX10:
3343 if (!fixP->fx_addsy)
3344 insn |= 0x1c00 | (val & 0x3ff);
3347 case BFD_RELOC_NONE:
3349 as_bad_where (fixP->fx_file, fixP->fx_line,
3350 _("bad or unhandled relocation type: 0x%02x"),
3355 if (INSN_BIG_ENDIAN)
3356 bfd_putb32 (insn, (unsigned char *) buf);
3358 bfd_putl32 (insn, (unsigned char *) buf);
3361 /* Are we finished with this relocation now? */
3362 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3366 /* Translate internal representation of relocation info to BFD target
3370 tc_gen_reloc (section, fixp)
3374 static arelent *relocs[3];
3376 bfd_reloc_code_real_type code;
3378 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3381 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3382 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3383 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3385 switch (fixp->fx_r_type)
3389 case BFD_RELOC_HI22:
3390 case BFD_RELOC_LO10:
3391 case BFD_RELOC_32_PCREL_S2:
3392 case BFD_RELOC_SPARC13:
3393 case BFD_RELOC_SPARC22:
3394 case BFD_RELOC_SPARC_BASE13:
3395 case BFD_RELOC_SPARC_WDISP16:
3396 case BFD_RELOC_SPARC_WDISP19:
3397 case BFD_RELOC_SPARC_WDISP22:
3399 case BFD_RELOC_SPARC_5:
3400 case BFD_RELOC_SPARC_6:
3401 case BFD_RELOC_SPARC_7:
3402 case BFD_RELOC_SPARC_10:
3403 case BFD_RELOC_SPARC_11:
3404 case BFD_RELOC_SPARC_HH22:
3405 case BFD_RELOC_SPARC_HM10:
3406 case BFD_RELOC_SPARC_LM22:
3407 case BFD_RELOC_SPARC_PC_HH22:
3408 case BFD_RELOC_SPARC_PC_HM10:
3409 case BFD_RELOC_SPARC_PC_LM22:
3410 case BFD_RELOC_SPARC_H44:
3411 case BFD_RELOC_SPARC_M44:
3412 case BFD_RELOC_SPARC_L44:
3413 case BFD_RELOC_SPARC_HIX22:
3414 case BFD_RELOC_SPARC_LOX10:
3415 case BFD_RELOC_SPARC_REV32:
3416 case BFD_RELOC_SPARC_OLO10:
3417 case BFD_RELOC_SPARC_UA16:
3418 case BFD_RELOC_SPARC_UA32:
3419 case BFD_RELOC_SPARC_UA64:
3420 case BFD_RELOC_8_PCREL:
3421 case BFD_RELOC_16_PCREL:
3422 case BFD_RELOC_32_PCREL:
3423 case BFD_RELOC_64_PCREL:
3424 case BFD_RELOC_SPARC_PLT32:
3425 case BFD_RELOC_SPARC_PLT64:
3426 case BFD_RELOC_VTABLE_ENTRY:
3427 case BFD_RELOC_VTABLE_INHERIT:
3428 case BFD_RELOC_SPARC_TLS_GD_HI22:
3429 case BFD_RELOC_SPARC_TLS_GD_LO10:
3430 case BFD_RELOC_SPARC_TLS_GD_ADD:
3431 case BFD_RELOC_SPARC_TLS_GD_CALL:
3432 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3433 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3434 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3435 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3436 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3437 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3438 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3439 case BFD_RELOC_SPARC_TLS_IE_HI22:
3440 case BFD_RELOC_SPARC_TLS_IE_LO10:
3441 case BFD_RELOC_SPARC_TLS_IE_LD:
3442 case BFD_RELOC_SPARC_TLS_IE_LDX:
3443 case BFD_RELOC_SPARC_TLS_IE_ADD:
3444 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3445 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3446 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3447 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3448 code = fixp->fx_r_type;
3455 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3456 /* If we are generating PIC code, we need to generate a different
3460 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3462 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3465 #define GOTT_BASE "__GOTT_BASE__"
3466 #define GOTT_INDEX "__GOTT_INDEX__"
3469 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3475 case BFD_RELOC_32_PCREL_S2:
3476 if (generic_force_reloc (fixp))
3477 code = BFD_RELOC_SPARC_WPLT30;
3479 case BFD_RELOC_HI22:
3480 code = BFD_RELOC_SPARC_GOT22;
3481 if (fixp->fx_addsy != NULL)
3483 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3484 code = BFD_RELOC_SPARC_PC22;
3486 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3487 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3488 code = BFD_RELOC_HI22; /* Unchanged. */
3492 case BFD_RELOC_LO10:
3493 code = BFD_RELOC_SPARC_GOT10;
3494 if (fixp->fx_addsy != NULL)
3496 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3497 code = BFD_RELOC_SPARC_PC10;
3499 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3500 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3501 code = BFD_RELOC_LO10; /* Unchanged. */
3505 case BFD_RELOC_SPARC13:
3506 code = BFD_RELOC_SPARC_GOT13;
3512 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3514 /* Nothing is aligned in DWARF debugging sections. */
3515 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3518 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3519 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3520 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3524 if (code == BFD_RELOC_SPARC_OLO10)
3525 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3527 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3528 if (reloc->howto == 0)
3530 as_bad_where (fixp->fx_file, fixp->fx_line,
3531 _("internal error: can't export reloc type %d (`%s')"),
3532 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3538 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3541 if (reloc->howto->pc_relative == 0
3542 || code == BFD_RELOC_SPARC_PC10
3543 || code == BFD_RELOC_SPARC_PC22)
3544 reloc->addend = fixp->fx_addnumber;
3545 else if (sparc_pic_code
3546 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3547 && fixp->fx_addsy != NULL
3548 && (S_IS_EXTERNAL (fixp->fx_addsy)
3549 || S_IS_WEAK (fixp->fx_addsy))
3550 && S_IS_DEFINED (fixp->fx_addsy)
3551 && ! S_IS_COMMON (fixp->fx_addsy))
3552 reloc->addend = fixp->fx_addnumber;
3554 reloc->addend = fixp->fx_offset - reloc->address;
3556 #else /* elf or coff */
3558 if (code != BFD_RELOC_32_PCREL_S2
3559 && code != BFD_RELOC_SPARC_WDISP22
3560 && code != BFD_RELOC_SPARC_WDISP16
3561 && code != BFD_RELOC_SPARC_WDISP19
3562 && code != BFD_RELOC_SPARC_WPLT30
3563 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3564 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3565 reloc->addend = fixp->fx_addnumber;
3566 else if (symbol_section_p (fixp->fx_addsy))
3567 reloc->addend = (section->vma
3568 + fixp->fx_addnumber
3569 + md_pcrel_from (fixp));
3571 reloc->addend = fixp->fx_offset;
3574 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3575 on the same location. */
3576 if (code == BFD_RELOC_SPARC_OLO10)
3578 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3581 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3583 = symbol_get_bfdsym (section_symbol (absolute_section));
3584 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3585 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3586 reloc->addend = fixp->tc_fix_data;
3592 /* We have no need to default values of symbols. */
3595 md_undefined_symbol (name)
3596 char *name ATTRIBUTE_UNUSED;
3601 /* Round up a section size to the appropriate boundary. */
3604 md_section_align (segment, size)
3605 segT segment ATTRIBUTE_UNUSED;
3609 /* This is not right for ELF; a.out wants it, and COFF will force
3610 the alignment anyways. */
3611 valueT align = ((valueT) 1
3612 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3615 /* Turn alignment value into a mask. */
3617 newsize = (size + align) & ~align;
3624 /* Exactly what point is a PC-relative offset relative TO?
3625 On the sparc, they're relative to the address of the offset, plus
3626 its size. This gets us to the following instruction.
3627 (??? Is this right? FIXME-SOON) */
3629 md_pcrel_from (fixP)
3634 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3635 if (! sparc_pic_code
3636 || fixP->fx_addsy == NULL
3637 || symbol_section_p (fixP->fx_addsy))
3638 ret += fixP->fx_size;
3642 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3654 for (shift = 0; (value & 1) == 0; value >>= 1)
3657 return (value == 1) ? shift : -1;
3660 /* Sort of like s_lcomm. */
3663 static int max_alignment = 15;
3668 int ignore ATTRIBUTE_UNUSED;
3678 name = input_line_pointer;
3679 c = get_symbol_end ();
3680 p = input_line_pointer;
3684 if (*input_line_pointer != ',')
3686 as_bad (_("Expected comma after name"));
3687 ignore_rest_of_line ();
3691 ++input_line_pointer;
3693 if ((size = get_absolute_expression ()) < 0)
3695 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3696 ignore_rest_of_line ();
3701 symbolP = symbol_find_or_make (name);
3704 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3705 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3707 as_bad (_("bad .reserve segment -- expected BSS segment"));
3711 if (input_line_pointer[2] == '.')
3712 input_line_pointer += 7;
3714 input_line_pointer += 6;
3717 if (*input_line_pointer == ',')
3719 ++input_line_pointer;
3722 if (*input_line_pointer == '\n')
3724 as_bad (_("missing alignment"));
3725 ignore_rest_of_line ();
3729 align = (int) get_absolute_expression ();
3732 if (align > max_alignment)
3734 align = max_alignment;
3735 as_warn (_("alignment too large; assuming %d"), align);
3741 as_bad (_("negative alignment"));
3742 ignore_rest_of_line ();
3748 temp = mylog2 (align);
3751 as_bad (_("alignment not a power of 2"));
3752 ignore_rest_of_line ();
3759 record_alignment (bss_section, align);
3764 if (!S_IS_DEFINED (symbolP)
3766 && S_GET_OTHER (symbolP) == 0
3767 && S_GET_DESC (symbolP) == 0
3774 segT current_seg = now_seg;
3775 subsegT current_subseg = now_subseg;
3777 /* Switch to bss. */
3778 subseg_set (bss_section, 1);
3782 frag_align (align, 0, 0);
3784 /* Detach from old frag. */
3785 if (S_GET_SEGMENT (symbolP) == bss_section)
3786 symbol_get_frag (symbolP)->fr_symbol = NULL;
3788 symbol_set_frag (symbolP, frag_now);
3789 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3790 (offsetT) size, (char *) 0);
3793 S_SET_SEGMENT (symbolP, bss_section);
3795 subseg_set (current_seg, current_subseg);
3798 S_SET_SIZE (symbolP, size);
3804 as_warn ("Ignoring attempt to re-define symbol %s",
3805 S_GET_NAME (symbolP));
3806 } /* if not redefining. */
3808 demand_empty_rest_of_line ();
3813 int ignore ATTRIBUTE_UNUSED;
3821 name = input_line_pointer;
3822 c = get_symbol_end ();
3823 /* Just after name is now '\0'. */
3824 p = input_line_pointer;
3827 if (*input_line_pointer != ',')
3829 as_bad (_("Expected comma after symbol-name"));
3830 ignore_rest_of_line ();
3835 input_line_pointer++;
3837 if ((temp = get_absolute_expression ()) < 0)
3839 as_bad (_(".COMMon length (%lu) out of range ignored"),
3840 (unsigned long) temp);
3841 ignore_rest_of_line ();
3846 symbolP = symbol_find_or_make (name);
3848 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3850 as_bad (_("Ignoring attempt to re-define symbol"));
3851 ignore_rest_of_line ();
3854 if (S_GET_VALUE (symbolP) != 0)
3856 if (S_GET_VALUE (symbolP) != (valueT) size)
3858 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3859 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
3865 S_SET_VALUE (symbolP, (valueT) size);
3866 S_SET_EXTERNAL (symbolP);
3869 know (symbol_get_frag (symbolP) == &zero_address_frag);
3870 if (*input_line_pointer != ',')
3872 as_bad (_("Expected comma after common length"));
3873 ignore_rest_of_line ();
3876 input_line_pointer++;
3878 if (*input_line_pointer != '"')
3880 temp = get_absolute_expression ();
3883 if (temp > max_alignment)
3885 temp = max_alignment;
3886 as_warn (_("alignment too large; assuming %ld"), (long) temp);
3892 as_bad (_("negative alignment"));
3893 ignore_rest_of_line ();
3898 if (symbol_get_obj (symbolP)->local)
3906 old_subsec = now_subseg;
3911 align = mylog2 (temp);
3915 as_bad (_("alignment not a power of 2"));
3916 ignore_rest_of_line ();
3920 record_alignment (bss_section, align);
3921 subseg_set (bss_section, 0);
3923 frag_align (align, 0, 0);
3924 if (S_GET_SEGMENT (symbolP) == bss_section)
3925 symbol_get_frag (symbolP)->fr_symbol = 0;
3926 symbol_set_frag (symbolP, frag_now);
3927 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3928 (offsetT) size, (char *) 0);
3930 S_SET_SEGMENT (symbolP, bss_section);
3931 S_CLEAR_EXTERNAL (symbolP);
3932 S_SET_SIZE (symbolP, size);
3933 subseg_set (old_sec, old_subsec);
3936 #endif /* OBJ_ELF */
3939 S_SET_VALUE (symbolP, (valueT) size);
3941 S_SET_ALIGN (symbolP, temp);
3942 S_SET_SIZE (symbolP, size);
3944 S_SET_EXTERNAL (symbolP);
3945 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3950 input_line_pointer++;
3951 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3952 if (*input_line_pointer == '.')
3953 input_line_pointer++;
3954 /* @@ Some say data, some say bss. */
3955 if (strncmp (input_line_pointer, "bss\"", 4)
3956 && strncmp (input_line_pointer, "data\"", 5))
3958 while (*--input_line_pointer != '"')
3960 input_line_pointer--;
3961 goto bad_common_segment;
3963 while (*input_line_pointer++ != '"')
3965 goto allocate_common;
3968 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3970 demand_empty_rest_of_line ();
3975 p = input_line_pointer;
3976 while (*p && *p != '\n')
3980 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3982 input_line_pointer = p;
3983 ignore_rest_of_line ();
3988 /* Handle the .empty pseudo-op. This suppresses the warnings about
3989 invalid delay slot usage. */
3993 int ignore ATTRIBUTE_UNUSED;
3995 /* The easy way to implement is to just forget about the last
4002 int ignore ATTRIBUTE_UNUSED;
4005 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4007 input_line_pointer += 6;
4011 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4013 input_line_pointer += 6;
4017 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4019 input_line_pointer += 7;
4023 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4025 input_line_pointer += 5;
4026 /* We only support 2 segments -- text and data -- for now, so
4027 things in the "bss segment" will have to go into data for now.
4028 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4029 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4032 as_bad (_("Unknown segment type"));
4033 demand_empty_rest_of_line ();
4039 subseg_set (data_section, 1);
4040 demand_empty_rest_of_line ();
4045 int ignore ATTRIBUTE_UNUSED;
4047 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4049 ++input_line_pointer;
4051 ++input_line_pointer;
4054 /* This static variable is set by s_uacons to tell sparc_cons_align
4055 that the expression does not need to be aligned. */
4057 static int sparc_no_align_cons = 0;
4059 /* This static variable is set by sparc_cons to emit requested types
4060 of relocations in cons_fix_new_sparc. */
4062 static const char *sparc_cons_special_reloc;
4064 /* This handles the unaligned space allocation pseudo-ops, such as
4065 .uaword. .uaword is just like .word, but the value does not need
4072 /* Tell sparc_cons_align not to align this value. */
4073 sparc_no_align_cons = 1;
4075 sparc_no_align_cons = 0;
4078 /* This handles the native word allocation pseudo-op .nword.
4079 For sparc_arch_size 32 it is equivalent to .word, for
4080 sparc_arch_size 64 it is equivalent to .xword. */
4084 int bytes ATTRIBUTE_UNUSED;
4086 cons (sparc_arch_size == 32 ? 4 : 8);
4090 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4094 .register %g[2367],{#scratch|symbolname|#ignore}
4099 int ignore ATTRIBUTE_UNUSED;
4104 const char *regname;
4106 if (input_line_pointer[0] != '%'
4107 || input_line_pointer[1] != 'g'
4108 || ((input_line_pointer[2] & ~1) != '2'
4109 && (input_line_pointer[2] & ~1) != '6')
4110 || input_line_pointer[3] != ',')
4111 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4112 reg = input_line_pointer[2] - '0';
4113 input_line_pointer += 4;
4115 if (*input_line_pointer == '#')
4117 ++input_line_pointer;
4118 regname = input_line_pointer;
4119 c = get_symbol_end ();
4120 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4121 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4122 if (regname[0] == 'i')
4129 regname = input_line_pointer;
4130 c = get_symbol_end ();
4132 if (sparc_arch_size == 64)
4136 if ((regname && globals[reg] != (symbolS *) 1
4137 && strcmp (S_GET_NAME (globals[reg]), regname))
4138 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4139 as_bad (_("redefinition of global register"));
4143 if (regname == NULL)
4144 globals[reg] = (symbolS *) 1;
4149 if (symbol_find (regname))
4150 as_bad (_("Register symbol %s already defined."),
4153 globals[reg] = symbol_make (regname);
4154 flags = symbol_get_bfdsym (globals[reg])->flags;
4156 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4157 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4158 flags |= BSF_GLOBAL;
4159 symbol_get_bfdsym (globals[reg])->flags = flags;
4160 S_SET_VALUE (globals[reg], (valueT) reg);
4161 S_SET_ALIGN (globals[reg], reg);
4162 S_SET_SIZE (globals[reg], 0);
4163 /* Although we actually want undefined_section here,
4164 we have to use absolute_section, because otherwise
4165 generic as code will make it a COM section.
4166 We fix this up in sparc_adjust_symtab. */
4167 S_SET_SEGMENT (globals[reg], absolute_section);
4168 S_SET_OTHER (globals[reg], 0);
4169 elf_symbol (symbol_get_bfdsym (globals[reg]))
4170 ->internal_elf_sym.st_info =
4171 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4172 elf_symbol (symbol_get_bfdsym (globals[reg]))
4173 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4178 *input_line_pointer = c;
4180 demand_empty_rest_of_line ();
4183 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4184 symbols which need it. */
4187 sparc_adjust_symtab ()
4191 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4193 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4194 ->internal_elf_sym.st_info) != STT_REGISTER)
4197 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4198 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4201 S_SET_SEGMENT (sym, undefined_section);
4206 /* If the --enforce-aligned-data option is used, we require .word,
4207 et. al., to be aligned correctly. We do it by setting up an
4208 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4209 no unexpected alignment was introduced.
4211 The SunOS and Solaris native assemblers enforce aligned data by
4212 default. We don't want to do that, because gcc can deliberately
4213 generate misaligned data if the packed attribute is used. Instead,
4214 we permit misaligned data by default, and permit the user to set an
4215 option to check for it. */
4218 sparc_cons_align (nbytes)
4224 /* Only do this if we are enforcing aligned data. */
4225 if (! enforce_aligned_data)
4228 /* Don't align if this is an unaligned pseudo-op. */
4229 if (sparc_no_align_cons)
4232 nalign = mylog2 (nbytes);
4236 assert (nalign > 0);
4238 if (now_seg == absolute_section)
4240 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4241 as_bad (_("misaligned data"));
4245 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4246 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4248 record_alignment (now_seg, nalign);
4251 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4254 sparc_handle_align (fragp)
4260 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4262 switch (fragp->fr_type)
4266 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4270 p = fragp->fr_literal + fragp->fr_fix;
4281 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4283 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4284 if (INSN_BIG_ENDIAN)
4285 number_to_chars_bigendian (p, wval, 4);
4287 number_to_chars_littleendian (p, wval, 4);
4293 if (INSN_BIG_ENDIAN)
4294 number_to_chars_bigendian (p, 0x01000000, 4);
4296 number_to_chars_littleendian (p, 0x01000000, 4);
4298 fragp->fr_fix += fix;
4308 /* Some special processing for a Sparc ELF file. */
4311 sparc_elf_final_processing ()
4313 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4314 sort of BFD interface for this. */
4315 if (sparc_arch_size == 64)
4317 switch (sparc_memory_model)
4320 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4323 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4329 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4330 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4331 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4332 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4333 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4334 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4338 sparc_cons (exp, size)
4345 sparc_cons_special_reloc = NULL;
4346 save = input_line_pointer;
4347 if (input_line_pointer[0] == '%'
4348 && input_line_pointer[1] == 'r'
4349 && input_line_pointer[2] == '_')
4351 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4353 input_line_pointer += 7;
4354 sparc_cons_special_reloc = "disp";
4356 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4358 if (size != 4 && size != 8)
4359 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4362 input_line_pointer += 6;
4363 sparc_cons_special_reloc = "plt";
4366 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4368 if (size != 4 && size != 8)
4369 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4372 input_line_pointer += 13;
4373 sparc_cons_special_reloc = "tls_dtpoff";
4376 if (sparc_cons_special_reloc)
4383 if (*input_line_pointer != '8')
4385 input_line_pointer--;
4388 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4392 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4396 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4406 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4407 sparc_cons_special_reloc, size * 8, size);
4411 input_line_pointer += 2;
4412 if (*input_line_pointer != '(')
4414 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4415 sparc_cons_special_reloc, size * 8);
4422 input_line_pointer = save;
4423 sparc_cons_special_reloc = NULL;
4428 char *end = ++input_line_pointer;
4431 while (! is_end_of_line[(c = *end)])
4445 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4446 sparc_cons_special_reloc, size * 8);
4452 if (input_line_pointer != end)
4454 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4455 sparc_cons_special_reloc, size * 8);
4459 input_line_pointer++;
4461 c = *input_line_pointer;
4462 if (! is_end_of_line[c] && c != ',')
4463 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4464 sparc_cons_special_reloc, size * 8);
4470 if (sparc_cons_special_reloc == NULL)
4476 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4477 reloc for a cons. We could use the definition there, except that
4478 we want to handle little endian relocs specially. */
4481 cons_fix_new_sparc (frag, where, nbytes, exp)
4484 unsigned int nbytes;
4487 bfd_reloc_code_real_type r;
4489 r = (nbytes == 1 ? BFD_RELOC_8 :
4490 (nbytes == 2 ? BFD_RELOC_16 :
4491 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4493 if (target_little_endian_data
4495 && now_seg->flags & SEC_ALLOC)
4496 r = BFD_RELOC_SPARC_REV32;
4498 if (sparc_cons_special_reloc)
4500 if (*sparc_cons_special_reloc == 'd')
4503 case 1: r = BFD_RELOC_8_PCREL; break;
4504 case 2: r = BFD_RELOC_16_PCREL; break;
4505 case 4: r = BFD_RELOC_32_PCREL; break;
4506 case 8: r = BFD_RELOC_64_PCREL; break;
4509 else if (*sparc_cons_special_reloc == 'p')
4512 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4513 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4518 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4519 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4522 else if (sparc_no_align_cons)
4526 case 2: r = BFD_RELOC_SPARC_UA16; break;
4527 case 4: r = BFD_RELOC_SPARC_UA32; break;
4528 case 8: r = BFD_RELOC_SPARC_UA64; break;
4533 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4534 sparc_cons_special_reloc = NULL;
4538 sparc_cfi_frame_initial_instructions ()
4540 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4544 sparc_regname_to_dw2regnum (char *regname)
4552 p = strchr (q, regname[0]);
4555 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4557 return (p - q) * 8 + regname[1] - '0';
4559 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4561 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4563 if (regname[0] == 'f' || regname[0] == 'r')
4565 unsigned int regnum;
4567 regnum = strtoul (regname + 1, &q, 10);
4570 if (regnum >= ((regname[0] == 'f'
4571 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4574 if (regname[0] == 'f')
4577 if (regnum >= 64 && (regnum & 1))
4586 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4588 sparc_cons_special_reloc = "disp";
4589 sparc_no_align_cons = 1;
4590 emit_expr (exp, nbytes);
4591 sparc_no_align_cons = 0;
4592 sparc_cons_special_reloc = NULL;