1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
51 #define DEFAULT_ARCH "sparclite"
53 static char *default_arch = DEFAULT_ARCH;
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
57 static int default_init_p;
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
76 /* The currently selected v9 memory model. Currently only used for
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
87 static int hwcap_allowed;
89 static int architecture_requested;
90 static int warn_on_bump;
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
103 /* Non-zero if we are generating PIC code. */
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
109 extern int target_big_endian;
111 static int target_little_endian_data;
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
141 static void s_register (int);
144 const pseudo_typeS md_pseudo_table[] =
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
154 {"reserve", s_reserve, 0},
156 {"skip", s_space, 0},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
187 const char line_separator_chars[] = ";";
189 /* Chars that can be used to separate mant from exp in floating point
191 const char EXP_CHARS[] = "eE";
193 /* Chars that mean this number is a floating point constant.
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
207 unsigned long opcode;
208 struct nlist *nlistp;
212 bfd_reloc_code_real_type reloc;
215 struct sparc_it the_insn, set_insn;
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
224 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
227 static struct sparc_arch {
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
248 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
249 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
250 { "leon", "leon", leon, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
254 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
255 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
256 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
257 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
258 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
259 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
260 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
261 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
262 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
263 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
264 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
265 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
266 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
267 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
268 /* This exists to allow configure.in/Makefile.in to pass one
269 value to specify both the default machine and default word size. */
270 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
271 { NULL, NULL, v8, 0, 0, 0 }
274 /* Variant of default_arch */
275 static enum sparc_arch_types default_arch_type;
277 static struct sparc_arch *
278 lookup_arch (char *name)
280 struct sparc_arch *sa;
282 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
283 if (strcmp (sa->name, name) == 0)
285 if (sa->name == NULL)
290 /* Initialize the default opcode arch and word size from the default
291 architecture name. */
294 init_default_arch (void)
296 struct sparc_arch *sa = lookup_arch (default_arch);
299 || sa->default_arch_size == 0)
300 as_fatal (_("Invalid default architecture, broken assembler."));
302 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
303 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
304 as_fatal (_("Bad opcode table, broken assembler."));
305 default_arch_size = sparc_arch_size = sa->default_arch_size;
307 default_arch_type = sa->arch_type;
310 /* Called by TARGET_FORMAT. */
313 sparc_target_format (void)
315 /* We don't get a chance to initialize anything before we're called,
316 so handle that now. */
317 if (! default_init_p)
318 init_default_arch ();
322 return "a.out-sparc-netbsd";
325 if (target_big_endian)
326 return "a.out-sunos-big";
327 else if (default_arch_type == sparc86x && target_little_endian_data)
328 return "a.out-sunos-big";
330 return "a.out-sparc-little";
332 return "a.out-sunos-big";
343 return "coff-sparc-lynx";
350 return "elf32-sparc-vxworks";
354 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
361 * Invocation line includes a switch not recognized by the base assembler.
362 * See if it's a processor-specific option. These are:
365 * Warn on architecture bumps. See also -A.
367 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
368 * Standard 32 bit architectures.
370 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
371 * This used to only mean 64 bits, but properly specifying it
372 * complicated gcc's ASM_SPECs, so now opcode selection is
373 * specified orthogonally to word size (except when specifying
374 * the default, but that is an internal implementation detail).
375 * -Av8plus, -Av8plusa, -Av8plusb
376 * Same as -Av9{,a,b}.
377 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
378 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
380 * -xarch=v9, -xarch=v9a, -xarch=v9b
381 * Same as -Av9{,a,b} -64, for compatibility with Sun's
384 * Select the architecture and possibly the file format.
385 * Instructions or features not supported by the selected
386 * architecture cause fatal errors.
388 * The default is to start at v6, and bump the architecture up
389 * whenever an instruction is seen at a higher level. In 32 bit
390 * environments, v9 is not bumped up to, the user must pass
393 * If -bump is specified, a warning is printing when bumping to
396 * If an architecture is specified, all instructions must match
397 * that architecture. Any higher level instructions are flagged
398 * as errors. Note that in the 32 bit environment specifying
399 * -Av8plus does not automatically create a v8plus object file, a
400 * v9 insn must be seen.
402 * If both an architecture and -bump are specified, the
403 * architecture starts at the specified level, but bumps are
404 * warnings. Note that we can't set `current_architecture' to
405 * the requested level in this case: in the 32 bit environment,
406 * we still must avoid creating v8plus object files unless v9
410 * Bumping between incompatible architectures is always an
411 * error. For example, from sparclite to v9.
415 const char *md_shortopts = "A:K:VQ:sq";
418 const char *md_shortopts = "A:k";
420 const char *md_shortopts = "A:";
423 struct option md_longopts[] = {
424 #define OPTION_BUMP (OPTION_MD_BASE)
425 {"bump", no_argument, NULL, OPTION_BUMP},
426 #define OPTION_SPARC (OPTION_MD_BASE + 1)
427 {"sparc", no_argument, NULL, OPTION_SPARC},
428 #define OPTION_XARCH (OPTION_MD_BASE + 2)
429 {"xarch", required_argument, NULL, OPTION_XARCH},
431 #define OPTION_32 (OPTION_MD_BASE + 3)
432 {"32", no_argument, NULL, OPTION_32},
433 #define OPTION_64 (OPTION_MD_BASE + 4)
434 {"64", no_argument, NULL, OPTION_64},
435 #define OPTION_TSO (OPTION_MD_BASE + 5)
436 {"TSO", no_argument, NULL, OPTION_TSO},
437 #define OPTION_PSO (OPTION_MD_BASE + 6)
438 {"PSO", no_argument, NULL, OPTION_PSO},
439 #define OPTION_RMO (OPTION_MD_BASE + 7)
440 {"RMO", no_argument, NULL, OPTION_RMO},
442 #ifdef SPARC_BIENDIAN
443 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
444 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
445 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
446 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
448 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
449 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
450 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
451 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
453 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
454 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
455 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
456 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
458 #define OPTION_RELAX (OPTION_MD_BASE + 14)
459 {"relax", no_argument, NULL, OPTION_RELAX},
460 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
461 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
462 {NULL, no_argument, NULL, 0}
465 size_t md_longopts_size = sizeof (md_longopts);
468 md_parse_option (int c, char *arg)
470 /* We don't get a chance to initialize anything before we're called,
471 so handle that now. */
472 if (! default_init_p)
473 init_default_arch ();
479 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
484 if (!strncmp (arg, "v9", 2))
485 md_parse_option (OPTION_64, NULL);
488 if (!strncmp (arg, "v8", 2)
489 || !strncmp (arg, "v7", 2)
490 || !strncmp (arg, "v6", 2)
491 || !strcmp (arg, "sparclet")
492 || !strcmp (arg, "sparclite")
493 || !strcmp (arg, "sparc86x"))
494 md_parse_option (OPTION_32, NULL);
501 struct sparc_arch *sa;
502 enum sparc_opcode_arch_val opcode_arch;
504 sa = lookup_arch (arg);
506 || ! sa->user_option_p)
508 if (c == OPTION_XARCH)
509 as_bad (_("invalid architecture -xarch=%s"), arg);
511 as_bad (_("invalid architecture -A%s"), arg);
515 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
516 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
517 as_fatal (_("Bad opcode table, broken assembler."));
519 if (!architecture_requested
520 || opcode_arch > max_architecture)
521 max_architecture = opcode_arch;
522 hwcap_allowed |= sa->hwcap_allowed;
523 architecture_requested = 1;
528 /* Ignore -sparc, used by SunOS make default .s.o rule. */
531 case OPTION_ENFORCE_ALIGNED_DATA:
532 enforce_aligned_data = 1;
535 #ifdef SPARC_BIENDIAN
536 case OPTION_LITTLE_ENDIAN:
537 target_big_endian = 0;
538 if (default_arch_type != sparclet)
539 as_fatal ("This target does not support -EL");
541 case OPTION_LITTLE_ENDIAN_DATA:
542 target_little_endian_data = 1;
543 target_big_endian = 0;
544 if (default_arch_type != sparc86x
545 && default_arch_type != v9)
546 as_fatal ("This target does not support --little-endian-data");
548 case OPTION_BIG_ENDIAN:
549 target_big_endian = 1;
563 const char **list, **l;
565 sparc_arch_size = c == OPTION_32 ? 32 : 64;
566 list = bfd_target_list ();
567 for (l = list; *l != NULL; l++)
569 if (sparc_arch_size == 32)
571 if (CONST_STRNEQ (*l, "elf32-sparc"))
576 if (CONST_STRNEQ (*l, "elf64-sparc"))
581 as_fatal (_("No compiled in support for %d bit object file format"),
585 if (sparc_arch_size == 64
586 && max_architecture < SPARC_OPCODE_ARCH_V9)
587 max_architecture = SPARC_OPCODE_ARCH_V9;
592 sparc_memory_model = MM_TSO;
596 sparc_memory_model = MM_PSO;
600 sparc_memory_model = MM_RMO;
608 /* Qy - do emit .comment
609 Qn - do not emit .comment. */
613 /* Use .stab instead of .stab.excl. */
617 /* quick -- Native assembler does fewer checks. */
621 if (strcmp (arg, "PIC") != 0)
622 as_warn (_("Unrecognized option following -K"));
627 case OPTION_NO_UNDECLARED_REGS:
628 no_undeclared_regs = 1;
631 case OPTION_UNDECLARED_REGS:
632 no_undeclared_regs = 0;
640 case OPTION_NO_RELAX:
652 md_show_usage (FILE *stream)
654 const struct sparc_arch *arch;
657 /* We don't get a chance to initialize anything before we're called,
658 so handle that now. */
659 if (! default_init_p)
660 init_default_arch ();
662 fprintf (stream, _("SPARC options:\n"));
664 for (arch = &sparc_arch_table[0]; arch->name; arch++)
666 if (!arch->user_option_p)
668 if (arch != &sparc_arch_table[0])
669 fprintf (stream, " | ");
670 if (column + strlen (arch->name) > 70)
673 fputc ('\n', stream);
675 column += 5 + 2 + strlen (arch->name);
676 fprintf (stream, "-A%s", arch->name);
678 for (arch = &sparc_arch_table[0]; arch->name; arch++)
680 if (!arch->user_option_p)
682 fprintf (stream, " | ");
683 if (column + strlen (arch->name) > 65)
686 fputc ('\n', stream);
688 column += 5 + 7 + strlen (arch->name);
689 fprintf (stream, "-xarch=%s", arch->name);
691 fprintf (stream, _("\n\
692 specify variant of SPARC architecture\n\
693 -bump warn when assembler switches architectures\n\
695 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
696 -relax relax jumps and branches (default)\n\
697 -no-relax avoid changing any jumps and branches\n"));
699 fprintf (stream, _("\
700 -k generate PIC\n"));
703 fprintf (stream, _("\
704 -32 create 32 bit object file\n\
705 -64 create 64 bit object file\n"));
706 fprintf (stream, _("\
707 [default is %d]\n"), default_arch_size);
708 fprintf (stream, _("\
709 -TSO use Total Store Ordering\n\
710 -PSO use Partial Store Ordering\n\
711 -RMO use Relaxed Memory Ordering\n"));
712 fprintf (stream, _("\
713 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
714 fprintf (stream, _("\
715 -KPIC generate PIC\n\
716 -V print assembler version number\n\
717 -undeclared-regs ignore application global register usage without\n\
718 appropriate .register directive (default)\n\
719 -no-undeclared-regs force error on application global register usage\n\
720 without appropriate .register directive\n\
725 #ifdef SPARC_BIENDIAN
726 fprintf (stream, _("\
727 -EL generate code for a little endian machine\n\
728 -EB generate code for a big endian machine\n\
729 --little-endian-data generate code for a machine having big endian\n\
730 instructions and little endian data.\n"));
734 /* Native operand size opcode translation. */
740 } native_op_table[] =
742 {"ldn", "ld", "ldx"},
743 {"ldna", "lda", "ldxa"},
744 {"stn", "st", "stx"},
745 {"stna", "sta", "stxa"},
746 {"slln", "sll", "sllx"},
747 {"srln", "srl", "srlx"},
748 {"sran", "sra", "srax"},
749 {"casn", "cas", "casx"},
750 {"casna", "casa", "casxa"},
751 {"clrn", "clr", "clrx"},
755 /* sparc64 privileged and hyperprivileged registers. */
757 struct priv_reg_entry
763 struct priv_reg_entry priv_reg_table[] =
783 {"", -1}, /* End marker. */
786 struct priv_reg_entry hpriv_reg_table[] =
794 {"", -1}, /* End marker. */
797 /* v9a specific asrs. This table is ordered by initial
798 letter, in reverse. */
800 struct priv_reg_entry v9a_asr_table[] =
803 {"sys_tick_cmpr", 25},
807 {"softint_clear", 21},
818 {"clear_softint", 21},
819 {"", -1}, /* End marker. */
823 cmp_reg_entry (const void *parg, const void *qarg)
825 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
826 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
828 return strcmp (q->name, p->name);
831 /* This function is called once, at assembler startup time. It should
832 set up all the tables, etc. that the MD part of the assembler will
838 register const char *retval = NULL;
840 register unsigned int i = 0;
842 /* We don't get a chance to initialize anything before md_parse_option
843 is called, and it may not be called, so handle default initialization
844 now if not already done. */
845 if (! default_init_p)
846 init_default_arch ();
848 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
849 op_hash = hash_new ();
851 while (i < (unsigned int) sparc_num_opcodes)
853 const char *name = sparc_opcodes[i].name;
854 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
857 as_bad (_("Internal error: can't hash `%s': %s\n"),
858 sparc_opcodes[i].name, retval);
863 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
865 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
866 sparc_opcodes[i].name, sparc_opcodes[i].args);
871 while (i < (unsigned int) sparc_num_opcodes
872 && !strcmp (sparc_opcodes[i].name, name));
875 for (i = 0; native_op_table[i].name; i++)
877 const struct sparc_opcode *insn;
878 char *name = ((sparc_arch_size == 32)
879 ? native_op_table[i].name32
880 : native_op_table[i].name64);
881 insn = (struct sparc_opcode *) hash_find (op_hash, name);
884 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
885 name, native_op_table[i].name);
890 retval = hash_insert (op_hash, native_op_table[i].name,
894 as_bad (_("Internal error: can't hash `%s': %s\n"),
895 sparc_opcodes[i].name, retval);
902 as_fatal (_("Broken assembler. No assembly attempted."));
904 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
905 sizeof (priv_reg_table[0]), cmp_reg_entry);
907 /* If -bump, record the architecture level at which we start issuing
908 warnings. The behaviour is different depending upon whether an
909 architecture was explicitly specified. If it wasn't, we issue warnings
910 for all upwards bumps. If it was, we don't start issuing warnings until
911 we need to bump beyond the requested architecture or when we bump between
912 conflicting architectures. */
915 && architecture_requested)
917 /* `max_architecture' records the requested architecture.
918 Issue warnings if we go above it. */
919 warn_after_architecture = max_architecture;
921 /* Find the highest architecture level that doesn't conflict with
922 the requested one. */
923 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
924 max_architecture > warn_after_architecture;
926 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
927 warn_after_architecture))
932 /* Called after all assembly has been done. */
937 unsigned long mach = bfd_mach_sparc;
939 if (sparc_arch_size == 64)
940 switch (current_architecture)
942 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
943 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
944 default: mach = bfd_mach_sparc_v9; break;
947 switch (current_architecture)
949 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
950 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
951 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
952 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
953 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
954 be but for now it is (since that's the way it's always been
958 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
960 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
962 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
966 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
969 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
973 /* Sign-extend the value from the architecture word size, so that
974 0xffffffff is always considered -1 on sparc32. */
975 if (sparc_arch_size == 32)
977 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
978 val = ((val & U0xffffffff) ^ sign) - sign;
987 /* Return non-zero if VAL is in the range 0 to MAX. */
990 in_unsigned_range (bfd_vma val, bfd_vma max)
997 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
998 (e.g. -15 to +31). */
1001 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
1007 if (val < ~(max >> 1))
1013 sparc_ffs (unsigned int mask)
1020 for (i = 0; (mask & 1) == 0; ++i)
1025 /* Implement big shift right. */
1027 BSR (bfd_vma val, int amount)
1029 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1030 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1031 return val >> amount;
1034 /* For communication between sparc_ip and get_expression. */
1035 static char *expr_end;
1037 /* Values for `special_case'.
1038 Instructions that require wierd handling because they're longer than
1040 #define SPECIAL_CASE_NONE 0
1041 #define SPECIAL_CASE_SET 1
1042 #define SPECIAL_CASE_SETSW 2
1043 #define SPECIAL_CASE_SETX 3
1044 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1045 #define SPECIAL_CASE_FDIV 4
1047 /* Bit masks of various insns. */
1048 #define NOP_INSN 0x01000000
1049 #define OR_INSN 0x80100000
1050 #define XOR_INSN 0x80180000
1051 #define FMOVS_INSN 0x81A00020
1052 #define SETHI_INSN 0x01000000
1053 #define SLLX_INSN 0x81281000
1054 #define SRA_INSN 0x81380000
1056 /* The last instruction to be assembled. */
1057 static const struct sparc_opcode *last_insn;
1058 /* The assembled opcode of `last_insn'. */
1059 static unsigned long last_opcode;
1061 /* Handle the set and setuw synthetic instructions. */
1064 synthetize_setuw (const struct sparc_opcode *insn)
1066 int need_hi22_p = 0;
1067 int rd = (the_insn.opcode & RD (~0)) >> 25;
1069 if (the_insn.exp.X_op == O_constant)
1071 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1073 if (sizeof (offsetT) > 4
1074 && (the_insn.exp.X_add_number < 0
1075 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1076 as_warn (_("set: number not in 0..4294967295 range"));
1080 if (sizeof (offsetT) > 4
1081 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1082 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1083 as_warn (_("set: number not in -2147483648..4294967295 range"));
1084 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1088 /* See if operand is absolute and small; skip sethi if so. */
1089 if (the_insn.exp.X_op != O_constant
1090 || the_insn.exp.X_add_number >= (1 << 12)
1091 || the_insn.exp.X_add_number < -(1 << 12))
1093 the_insn.opcode = (SETHI_INSN | RD (rd)
1094 | ((the_insn.exp.X_add_number >> 10)
1095 & (the_insn.exp.X_op == O_constant
1097 the_insn.reloc = (the_insn.exp.X_op != O_constant
1098 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1099 output_insn (insn, &the_insn);
1103 /* See if operand has no low-order bits; skip OR if so. */
1104 if (the_insn.exp.X_op != O_constant
1105 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1108 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1110 | (the_insn.exp.X_add_number
1111 & (the_insn.exp.X_op != O_constant
1112 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1113 the_insn.reloc = (the_insn.exp.X_op != O_constant
1114 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1115 output_insn (insn, &the_insn);
1119 /* Handle the setsw synthetic instruction. */
1122 synthetize_setsw (const struct sparc_opcode *insn)
1126 rd = (the_insn.opcode & RD (~0)) >> 25;
1128 if (the_insn.exp.X_op != O_constant)
1130 synthetize_setuw (insn);
1132 /* Need to sign extend it. */
1133 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1134 the_insn.reloc = BFD_RELOC_NONE;
1135 output_insn (insn, &the_insn);
1139 if (sizeof (offsetT) > 4
1140 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1141 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1142 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1144 low32 = the_insn.exp.X_add_number;
1148 synthetize_setuw (insn);
1154 the_insn.reloc = BFD_RELOC_NONE;
1155 /* See if operand is absolute and small; skip sethi if so. */
1156 if (low32 < -(1 << 12))
1158 the_insn.opcode = (SETHI_INSN | RD (rd)
1159 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1160 output_insn (insn, &the_insn);
1161 low32 = 0x1c00 | (low32 & 0x3ff);
1162 opc = RS1 (rd) | XOR_INSN;
1165 the_insn.opcode = (opc | RD (rd) | IMMED
1166 | (low32 & 0x1fff));
1167 output_insn (insn, &the_insn);
1170 /* Handle the setsw synthetic instruction. */
1173 synthetize_setx (const struct sparc_opcode *insn)
1175 int upper32, lower32;
1176 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1177 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1179 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1180 int need_xor10_p = 0;
1182 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1183 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1184 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1187 upper_dstreg = tmpreg;
1188 /* The tmp reg should not be the dst reg. */
1189 if (tmpreg == dstreg)
1190 as_warn (_("setx: temporary register same as destination register"));
1192 /* ??? Obviously there are other optimizations we can do
1193 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1194 doing some of these. Later. If you do change things, try to
1195 change all of this to be table driven as well. */
1196 /* What to output depends on the number if it's constant.
1197 Compute that first, then output what we've decided upon. */
1198 if (the_insn.exp.X_op != O_constant)
1200 if (sparc_arch_size == 32)
1202 /* When arch size is 32, we want setx to be equivalent
1203 to setuw for anything but constants. */
1204 the_insn.exp.X_add_number &= 0xffffffff;
1205 synthetize_setuw (insn);
1208 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1214 /* Reset X_add_number, we've extracted it as upper32/lower32.
1215 Otherwise fixup_segment will complain about not being able to
1216 write an 8 byte number in a 4 byte field. */
1217 the_insn.exp.X_add_number = 0;
1219 /* Only need hh22 if `or' insn can't handle constant. */
1220 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1223 /* Does bottom part (after sethi) have bits? */
1224 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1225 /* No hh22, but does upper32 still have bits we can't set
1227 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1230 /* If the lower half is all zero, we build the upper half directly
1231 into the dst reg. */
1233 /* Need lower half if number is zero or 0xffffffff00000000. */
1234 || (! need_hh22_p && ! need_hm10_p))
1236 /* No need for sethi if `or' insn can handle constant. */
1237 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1238 /* Note that we can't use a negative constant in the `or'
1239 insn unless the upper 32 bits are all ones. */
1240 || (lower32 < 0 && upper32 != -1)
1241 || (lower32 >= 0 && upper32 == -1))
1244 if (need_hi22_p && upper32 == -1)
1247 /* Does bottom part (after sethi) have bits? */
1248 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1250 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1251 /* Need `or' if we didn't set anything else. */
1252 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1256 /* Output directly to dst reg if lower 32 bits are all zero. */
1257 upper_dstreg = dstreg;
1260 if (!upper_dstreg && dstreg)
1261 as_warn (_("setx: illegal temporary register g0"));
1265 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1266 | ((upper32 >> 10) & 0x3fffff));
1267 the_insn.reloc = (the_insn.exp.X_op != O_constant
1268 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1269 output_insn (insn, &the_insn);
1274 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1275 | (((need_xor10_p ? ~lower32 : lower32)
1276 >> 10) & 0x3fffff));
1277 the_insn.reloc = (the_insn.exp.X_op != O_constant
1278 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1279 output_insn (insn, &the_insn);
1284 the_insn.opcode = (OR_INSN
1285 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1288 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1289 the_insn.reloc = (the_insn.exp.X_op != O_constant
1290 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1291 output_insn (insn, &the_insn);
1296 /* FIXME: One nice optimization to do here is to OR the low part
1297 with the highpart if hi22 isn't needed and the low part is
1299 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1302 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1303 the_insn.reloc = (the_insn.exp.X_op != O_constant
1304 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1305 output_insn (insn, &the_insn);
1308 /* If we needed to build the upper part, shift it into place. */
1309 if (need_hh22_p || need_hm10_p)
1311 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1313 the_insn.reloc = BFD_RELOC_NONE;
1314 output_insn (insn, &the_insn);
1317 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1320 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1321 | 0x1c00 | (lower32 & 0x3ff));
1322 the_insn.reloc = BFD_RELOC_NONE;
1323 output_insn (insn, &the_insn);
1326 /* If we needed to build both upper and lower parts, OR them together. */
1327 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1329 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1331 the_insn.reloc = BFD_RELOC_NONE;
1332 output_insn (insn, &the_insn);
1336 /* Main entry point to assemble one instruction. */
1339 md_assemble (char *str)
1341 const struct sparc_opcode *insn;
1345 special_case = sparc_ip (str, &insn);
1349 /* We warn about attempts to put a floating point branch in a delay slot,
1350 unless the delay slot has been annulled. */
1351 if (last_insn != NULL
1352 && (insn->flags & F_FBR) != 0
1353 && (last_insn->flags & F_DELAYED) != 0
1354 /* ??? This test isn't completely accurate. We assume anything with
1355 F_{UNBR,CONDBR,FBR} set is annullable. */
1356 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1357 || (last_opcode & ANNUL) == 0))
1358 as_warn (_("FP branch in delay slot"));
1360 /* SPARC before v9 requires a nop instruction between a floating
1361 point instruction and a floating point branch. We insert one
1362 automatically, with a warning. */
1363 if (max_architecture < SPARC_OPCODE_ARCH_V9
1364 && last_insn != NULL
1365 && (insn->flags & F_FBR) != 0
1366 && (last_insn->flags & F_FLOAT) != 0)
1368 struct sparc_it nop_insn;
1370 nop_insn.opcode = NOP_INSN;
1371 nop_insn.reloc = BFD_RELOC_NONE;
1372 output_insn (insn, &nop_insn);
1373 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1376 switch (special_case)
1378 case SPECIAL_CASE_NONE:
1380 output_insn (insn, &the_insn);
1383 case SPECIAL_CASE_SETSW:
1384 synthetize_setsw (insn);
1387 case SPECIAL_CASE_SET:
1388 synthetize_setuw (insn);
1391 case SPECIAL_CASE_SETX:
1392 synthetize_setx (insn);
1395 case SPECIAL_CASE_FDIV:
1397 int rd = (the_insn.opcode >> 25) & 0x1f;
1399 output_insn (insn, &the_insn);
1401 /* According to information leaked from Sun, the "fdiv" instructions
1402 on early SPARC machines would produce incorrect results sometimes.
1403 The workaround is to add an fmovs of the destination register to
1404 itself just after the instruction. This was true on machines
1405 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1406 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1407 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1408 output_insn (insn, &the_insn);
1413 as_fatal (_("failed special case insn sanity check"));
1418 get_hwcap_name (int mask)
1420 if (mask & HWCAP_MUL32)
1422 if (mask & HWCAP_DIV32)
1424 if (mask & HWCAP_FSMULD)
1426 if (mask & HWCAP_V8PLUS)
1428 if (mask & HWCAP_POPC)
1430 if (mask & HWCAP_VIS)
1432 if (mask & HWCAP_VIS2)
1434 if (mask & HWCAP_ASI_BLK_INIT)
1435 return "ASIBlkInit";
1436 if (mask & HWCAP_FMAF)
1438 if (mask & HWCAP_VIS3)
1440 if (mask & HWCAP_HPC)
1442 if (mask & HWCAP_RANDOM)
1444 if (mask & HWCAP_TRANS)
1446 if (mask & HWCAP_FJFMAU)
1448 if (mask & HWCAP_IMA)
1450 if (mask & HWCAP_ASI_CACHE_SPARING)
1452 if (mask & HWCAP_AES)
1454 if (mask & HWCAP_DES)
1456 if (mask & HWCAP_KASUMI)
1458 if (mask & HWCAP_CAMELLIA)
1460 if (mask & HWCAP_MD5)
1462 if (mask & HWCAP_SHA1)
1464 if (mask & HWCAP_SHA256)
1466 if (mask & HWCAP_SHA512)
1468 if (mask & HWCAP_MPMUL)
1470 if (mask & HWCAP_MONT)
1472 if (mask & HWCAP_PAUSE)
1474 if (mask & HWCAP_CBCOND)
1476 if (mask & HWCAP_CRC32C)
1481 /* Subroutine of md_assemble to do the actual parsing. */
1484 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1486 char *error_message = "";
1490 const struct sparc_opcode *insn;
1492 unsigned long opcode;
1493 unsigned int mask = 0;
1497 int special_case = SPECIAL_CASE_NONE;
1504 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1521 as_bad (_("Unknown opcode: `%s'"), str);
1523 return special_case;
1525 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1529 as_bad (_("Unknown opcode: `%s'"), str);
1530 return special_case;
1540 opcode = insn->match;
1541 memset (&the_insn, '\0', sizeof (the_insn));
1542 the_insn.reloc = BFD_RELOC_NONE;
1545 /* Build the opcode, checking as we go to make sure that the
1547 for (args = insn->args;; ++args)
1555 /* Parse a series of masks. */
1562 if (! parse_keyword_arg (sparc_encode_membar, &s,
1565 error_message = _(": invalid membar mask name");
1571 if (*s == '|' || *s == '+')
1579 if (! parse_const_expr_arg (&s, &kmask))
1581 error_message = _(": invalid membar mask expression");
1584 if (kmask < 0 || kmask > 127)
1586 error_message = _(": invalid membar mask number");
1591 opcode |= MEMBAR (kmask);
1599 if (! parse_const_expr_arg (&s, &smask))
1601 error_message = _(": invalid siam mode expression");
1604 if (smask < 0 || smask > 7)
1606 error_message = _(": invalid siam mode number");
1617 /* Parse a prefetch function. */
1620 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1622 error_message = _(": invalid prefetch function name");
1628 if (! parse_const_expr_arg (&s, &fcn))
1630 error_message = _(": invalid prefetch function expression");
1633 if (fcn < 0 || fcn > 31)
1635 error_message = _(": invalid prefetch function number");
1645 /* Parse a sparc64 privileged register. */
1648 struct priv_reg_entry *p = priv_reg_table;
1649 unsigned int len = 9999999; /* Init to make gcc happy. */
1652 while (p->name[0] > s[0])
1654 while (p->name[0] == s[0])
1656 len = strlen (p->name);
1657 if (strncmp (p->name, s, len) == 0)
1661 if (p->name[0] != s[0])
1663 error_message = _(": unrecognizable privileged register");
1667 opcode |= (p->regnum << 14);
1669 opcode |= (p->regnum << 25);
1675 error_message = _(": unrecognizable privileged register");
1681 /* Parse a sparc64 hyperprivileged register. */
1684 struct priv_reg_entry *p = hpriv_reg_table;
1685 unsigned int len = 9999999; /* Init to make gcc happy. */
1688 while (p->name[0] > s[0])
1690 while (p->name[0] == s[0])
1692 len = strlen (p->name);
1693 if (strncmp (p->name, s, len) == 0)
1697 if (p->name[0] != s[0])
1699 error_message = _(": unrecognizable hyperprivileged register");
1703 opcode |= (p->regnum << 14);
1705 opcode |= (p->regnum << 25);
1711 error_message = _(": unrecognizable hyperprivileged register");
1717 /* Parse a v9a/v9b ancillary state register. */
1720 struct priv_reg_entry *p = v9a_asr_table;
1721 unsigned int len = 9999999; /* Init to make gcc happy. */
1724 while (p->name[0] > s[0])
1726 while (p->name[0] == s[0])
1728 len = strlen (p->name);
1729 if (strncmp (p->name, s, len) == 0)
1733 if (p->name[0] != s[0])
1735 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1738 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1740 error_message = _(": rd on write only ancillary state register");
1744 && (insn->architecture
1745 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1747 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1748 error_message = _(": unrecognizable v9a ancillary state register");
1752 opcode |= (p->regnum << 14);
1754 opcode |= (p->regnum << 25);
1760 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1766 if (strncmp (s, "%asr", 4) == 0)
1774 while (ISDIGIT (*s))
1776 num = num * 10 + *s - '0';
1780 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1782 if (num < 16 || 31 < num)
1784 error_message = _(": asr number must be between 16 and 31");
1790 if (num < 0 || 31 < num)
1792 error_message = _(": asr number must be between 0 and 31");
1797 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1802 error_message = _(": expecting %asrN");
1809 the_insn.reloc = BFD_RELOC_SPARC_11;
1813 the_insn.reloc = BFD_RELOC_SPARC_10;
1819 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1824 if (s[0] == '0' && s[1] == 'x')
1827 while (ISXDIGIT (*s))
1830 num |= hex_value (*s);
1836 while (ISDIGIT (*s))
1838 num = num * 10 + *s - '0';
1842 if (num < 0 || num > 31)
1844 error_message = _(": crypto immediate must be between 0 and 31");
1848 opcode |= RS3 (num);
1853 error_message = _(": expecting crypto immediate");
1858 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1859 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1860 the_insn.reloc = BFD_RELOC_SPARC_5;
1862 the_insn.reloc = BFD_RELOC_SPARC13;
1863 /* These fields are unsigned, but for upward compatibility,
1864 allow negative values as well. */
1868 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1869 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1870 the_insn.reloc = BFD_RELOC_SPARC_6;
1872 the_insn.reloc = BFD_RELOC_SPARC13;
1873 /* These fields are unsigned, but for upward compatibility,
1874 allow negative values as well. */
1878 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1883 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1888 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1893 if (*s == 'p' && s[1] == 'n')
1901 if (*s == 'p' && s[1] == 't')
1913 if (strncmp (s, "%icc", 4) == 0)
1925 if (strncmp (s, "%xcc", 4) == 0)
1937 if (strncmp (s, "%fcc0", 5) == 0)
1949 if (strncmp (s, "%fcc1", 5) == 0)
1961 if (strncmp (s, "%fcc2", 5) == 0)
1973 if (strncmp (s, "%fcc3", 5) == 0)
1981 if (strncmp (s, "%pc", 3) == 0)
1989 if (strncmp (s, "%tick", 5) == 0)
1996 case '\0': /* End of args. */
1997 if (s[0] == ',' && s[1] == '%')
1999 static const struct ops
2001 /* The name as it appears in assembler. */
2003 /* strlen (name), precomputed for speed */
2005 /* The reloc this pseudo-op translates to. */
2007 /* 1 if tls call. */
2012 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2013 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2014 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2015 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2016 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2017 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2018 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2019 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2020 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2023 const struct ops *o;
2027 for (o = ops; o->name; o++)
2028 if (strncmp (s + 2, o->name, o->len) == 0)
2030 if (o->name == NULL)
2033 if (s[o->len + 2] != '(')
2035 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2036 return special_case;
2039 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2041 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2043 return special_case;
2047 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2048 || the_insn.exp.X_add_number != 0
2049 || the_insn.exp.X_add_symbol
2050 != symbol_find_or_make ("__tls_get_addr")))
2052 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2054 return special_case;
2057 the_insn.reloc = o->reloc;
2058 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2061 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2064 else if (*s1 == ')')
2073 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2074 return special_case;
2078 (void) get_expression (s);
2098 case '[': /* These must match exactly. */
2106 case '#': /* Must be at least one digit. */
2109 while (ISDIGIT (*s))
2117 case 'C': /* Coprocessor state register. */
2118 if (strncmp (s, "%csr", 4) == 0)
2125 case 'b': /* Next operand is a coprocessor register. */
2128 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2133 mask = 10 * (mask - '0') + (*s++ - '0');
2147 opcode |= mask << 14;
2155 opcode |= mask << 25;
2161 case 'r': /* next operand must be a register */
2171 case 'f': /* frame pointer */
2179 case 'g': /* global register */
2188 case 'i': /* in register */
2192 mask = c - '0' + 24;
2197 case 'l': /* local register */
2201 mask = (c - '0' + 16);
2206 case 'o': /* out register */
2210 mask = (c - '0' + 8);
2215 case 's': /* stack pointer */
2223 case 'r': /* any register */
2224 if (!ISDIGIT ((c = *s++)))
2241 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2257 if ((mask & ~1) == 2 && sparc_arch_size == 64
2258 && no_undeclared_regs && ! globals[mask])
2259 as_bad (_("detected global register use not covered by .register pseudo-op"));
2261 /* Got the register, now figure out where
2262 it goes in the opcode. */
2266 opcode |= mask << 14;
2274 opcode |= mask << 25;
2278 opcode |= (mask << 25) | (mask << 14);
2282 opcode |= (mask << 25) | (mask << 0);
2288 case 'e': /* next operand is a floating point register */
2306 && ((format = *s) == 'f')
2309 for (mask = 0; ISDIGIT (*s); ++s)
2311 mask = 10 * mask + (*s - '0');
2312 } /* read the number */
2321 } /* register must be even numbered */
2329 } /* register must be multiple of 4 */
2333 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2334 error_message = _(": There are only 64 f registers; [0-63]");
2336 error_message = _(": There are only 32 f registers; [0-31]");
2339 else if (mask >= 32)
2341 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2343 if (*args == 'e' || *args == 'f' || *args == 'g')
2346 = _(": There are only 32 single precision f registers; [0-31]");
2350 mask -= 31; /* wrap high bit */
2354 error_message = _(": There are only 32 f registers; [0-31]");
2362 } /* if not an 'f' register. */
2369 opcode |= RS1 (mask);
2375 opcode |= RS2 (mask);
2380 opcode |= RS3 (mask);
2386 opcode |= RD (mask);
2395 if (strncmp (s, "%fsr", 4) == 0)
2403 if (strncmp (s, "%efsr", 5) == 0)
2410 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2411 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2414 case 'l': /* 22 bit PC relative immediate */
2415 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2419 case 'L': /* 30 bit immediate */
2420 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2425 case 'n': /* 22 bit immediate */
2426 the_insn.reloc = BFD_RELOC_SPARC22;
2429 case 'i': /* 13 bit immediate */
2430 the_insn.reloc = BFD_RELOC_SPARC13;
2440 char *op_arg = NULL;
2441 static expressionS op_exp;
2442 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2444 /* Check for %hi, etc. */
2447 static const struct ops {
2448 /* The name as it appears in assembler. */
2450 /* strlen (name), precomputed for speed */
2452 /* The reloc this pseudo-op translates to. */
2454 /* Non-zero if for v9 only. */
2456 /* Non-zero if can be used in pc-relative contexts. */
2457 int pcrel_p;/*FIXME:wip*/
2459 /* hix/lox must appear before hi/lo so %hix won't be
2460 mistaken for %hi. */
2461 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2462 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2463 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2464 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2465 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2466 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2467 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2468 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2469 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2470 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2471 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2472 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2473 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2474 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2475 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2476 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2477 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2478 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2479 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2480 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2481 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2483 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2485 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2486 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2487 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2488 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2489 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2491 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2493 { NULL, 0, 0, 0, 0 }
2495 const struct ops *o;
2497 for (o = ops; o->name; o++)
2498 if (strncmp (s + 1, o->name, o->len) == 0)
2500 if (o->name == NULL)
2503 if (s[o->len + 1] != '(')
2505 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2506 return special_case;
2510 the_insn.reloc = o->reloc;
2515 /* Note that if the get_expression() fails, we will still
2516 have created U entries in the symbol table for the
2517 'symbols' in the input string. Try not to create U
2518 symbols for registers, etc. */
2520 /* This stuff checks to see if the expression ends in
2521 +%reg. If it does, it removes the register from
2522 the expression, and re-sets 's' to point to the
2529 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2532 else if (*s1 == ')')
2541 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2542 return special_case;
2546 (void) get_expression (s);
2549 if (*s == ',' || *s == ']' || !*s)
2551 if (*s != '+' && *s != '-')
2553 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2554 return special_case;
2558 op_exp = the_insn.exp;
2559 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2562 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2565 if (s1 != s && ISDIGIT (s1[-1]))
2567 if (s1[-2] == '%' && s1[-3] == '+')
2569 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2571 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2578 if (op_arg && s1 == s + 1)
2579 the_insn.exp.X_op = O_absent;
2581 (void) get_expression (s);
2593 (void) get_expression (s);
2601 the_insn.exp2 = the_insn.exp;
2602 the_insn.exp = op_exp;
2603 if (the_insn.exp2.X_op == O_absent)
2604 the_insn.exp2.X_op = O_illegal;
2605 else if (the_insn.exp.X_op == O_absent)
2607 the_insn.exp = the_insn.exp2;
2608 the_insn.exp2.X_op = O_illegal;
2610 else if (the_insn.exp.X_op == O_constant)
2612 valueT val = the_insn.exp.X_add_number;
2613 switch (the_insn.reloc)
2618 case BFD_RELOC_SPARC_HH22:
2619 val = BSR (val, 32);
2622 case BFD_RELOC_SPARC_LM22:
2623 case BFD_RELOC_HI22:
2624 val = (val >> 10) & 0x3fffff;
2627 case BFD_RELOC_SPARC_HM10:
2628 val = BSR (val, 32);
2631 case BFD_RELOC_LO10:
2635 case BFD_RELOC_SPARC_H34:
2640 case BFD_RELOC_SPARC_H44:
2645 case BFD_RELOC_SPARC_M44:
2650 case BFD_RELOC_SPARC_L44:
2654 case BFD_RELOC_SPARC_HIX22:
2656 val = (val >> 10) & 0x3fffff;
2659 case BFD_RELOC_SPARC_LOX10:
2660 val = (val & 0x3ff) | 0x1c00;
2663 the_insn.exp = the_insn.exp2;
2664 the_insn.exp.X_add_number += val;
2665 the_insn.exp2.X_op = O_illegal;
2666 the_insn.reloc = old_reloc;
2668 else if (the_insn.exp2.X_op != O_constant)
2670 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2671 return special_case;
2675 if (old_reloc != BFD_RELOC_SPARC13
2676 || the_insn.reloc != BFD_RELOC_LO10
2677 || sparc_arch_size != 64
2680 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2681 return special_case;
2683 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2687 /* Check for constants that don't require emitting a reloc. */
2688 if (the_insn.exp.X_op == O_constant
2689 && the_insn.exp.X_add_symbol == 0
2690 && the_insn.exp.X_op_symbol == 0)
2692 /* For pc-relative call instructions, we reject
2693 constants to get better code. */
2695 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2696 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2698 error_message = _(": PC-relative operand can't be a constant");
2702 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2703 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2705 error_message = _(": TLS operand can't be a constant");
2709 /* Constants that won't fit are checked in md_apply_fix
2710 and bfd_install_relocation.
2711 ??? It would be preferable to install the constants
2712 into the insn here and save having to create a fixS
2713 for each one. There already exists code to handle
2714 all the various cases (e.g. in md_apply_fix and
2715 bfd_install_relocation) so duplicating all that code
2716 here isn't right. */
2718 /* This is a special case to handle cbcond instructions
2719 properly, which can need two relocations. The first
2720 one is for the 5-bit immediate field and the latter
2721 is going to be for the WDISP10 branch part. We
2722 handle the R_SPARC_5 immediate directly here so that
2723 we don't need to add support for multiple relocations
2724 in one instruction just yet. */
2725 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2727 valueT val = the_insn.exp.X_add_number;
2729 if (! in_bitfield_range (val, 0x1f))
2731 error_message = _(": Immediate value in cbcond is out of range.");
2734 opcode |= val & 0x1f;
2735 the_insn.reloc = BFD_RELOC_NONE;
2756 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2758 error_message = _(": invalid ASI name");
2764 if (! parse_const_expr_arg (&s, &asi))
2766 error_message = _(": invalid ASI expression");
2769 if (asi < 0 || asi > 255)
2771 error_message = _(": invalid ASI number");
2775 opcode |= ASI (asi);
2777 } /* Alternate space. */
2780 if (strncmp (s, "%psr", 4) == 0)
2787 case 'q': /* Floating point queue. */
2788 if (strncmp (s, "%fq", 3) == 0)
2795 case 'Q': /* Coprocessor queue. */
2796 if (strncmp (s, "%cq", 3) == 0)
2804 if (strcmp (str, "set") == 0
2805 || strcmp (str, "setuw") == 0)
2807 special_case = SPECIAL_CASE_SET;
2810 else if (strcmp (str, "setsw") == 0)
2812 special_case = SPECIAL_CASE_SETSW;
2815 else if (strcmp (str, "setx") == 0)
2817 special_case = SPECIAL_CASE_SETX;
2820 else if (strncmp (str, "fdiv", 4) == 0)
2822 special_case = SPECIAL_CASE_FDIV;
2828 if (strncmp (s, "%asi", 4) != 0)
2834 if (strncmp (s, "%fprs", 5) != 0)
2840 if (strncmp (s, "%ccr", 4) != 0)
2846 if (strncmp (s, "%tbr", 4) != 0)
2852 if (strncmp (s, "%wim", 4) != 0)
2859 char *push = input_line_pointer;
2862 input_line_pointer = s;
2864 if (e.X_op == O_constant)
2866 int n = e.X_add_number;
2867 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2868 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2870 opcode |= e.X_add_number << 5;
2873 as_bad (_("non-immediate OPF operand, ignored"));
2874 s = input_line_pointer;
2875 input_line_pointer = push;
2880 if (strncmp (s, "%y", 2) != 0)
2888 /* Parse a sparclet cpreg. */
2890 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2892 error_message = _(": invalid cpreg name");
2895 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2900 as_fatal (_("failed sanity check."));
2901 } /* switch on arg code. */
2903 /* Break out of for() loop. */
2905 } /* For each arg that we expect. */
2910 /* Args don't match. */
2911 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2912 && (insn->name == insn[1].name
2913 || !strcmp (insn->name, insn[1].name)))
2921 as_bad (_("Illegal operands%s"), error_message);
2922 return special_case;
2927 /* We have a match. Now see if the architecture is OK. */
2928 int needed_arch_mask = insn->architecture;
2929 int hwcaps = insn->hwcaps;
2931 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2933 hwcap_seen |= hwcaps;
2938 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2939 if (! needed_arch_mask)
2941 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2944 if (needed_arch_mask
2945 & SPARC_OPCODE_SUPPORTED (current_architecture))
2948 /* Can we bump up the architecture? */
2949 else if (needed_arch_mask
2950 & SPARC_OPCODE_SUPPORTED (max_architecture))
2952 enum sparc_opcode_arch_val needed_architecture =
2953 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2954 & needed_arch_mask);
2956 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2958 && needed_architecture > warn_after_architecture)
2960 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2961 sparc_opcode_archs[current_architecture].name,
2962 sparc_opcode_archs[needed_architecture].name,
2964 warn_after_architecture = needed_architecture;
2966 current_architecture = needed_architecture;
2969 /* ??? This seems to be a bit fragile. What if the next entry in
2970 the opcode table is the one we want and it is supported?
2971 It is possible to arrange the table today so that this can't
2972 happen but what about tomorrow? */
2975 int arch, printed_one_p = 0;
2977 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2979 /* Create a list of the architectures that support the insn. */
2980 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2982 arch = sparc_ffs (needed_arch_mask);
2983 while ((1 << arch) <= needed_arch_mask)
2985 if ((1 << arch) & needed_arch_mask)
2989 strcpy (p, sparc_opcode_archs[arch].name);
2996 as_bad (_("Architecture mismatch on \"%s\"."), str);
2997 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2999 sparc_opcode_archs[max_architecture].name);
3000 return special_case;
3003 /* Make sure the the hwcaps used by the instruction are
3004 currently enabled. */
3005 if (hwcaps & ~hwcap_allowed)
3007 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
3009 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3011 return special_case;
3013 } /* If no match. */
3016 } /* Forever looking for a match. */
3018 the_insn.opcode = opcode;
3019 return special_case;
3022 /* Parse an argument that can be expressed as a keyword.
3023 (eg: #StoreStore or %ccfr).
3024 The result is a boolean indicating success.
3025 If successful, INPUT_POINTER is updated. */
3028 parse_keyword_arg (int (*lookup_fn) (const char *),
3029 char **input_pointerP,
3035 p = *input_pointerP;
3036 for (q = p + (*p == '#' || *p == '%');
3037 ISALNUM (*q) || *q == '_';
3042 value = (*lookup_fn) (p);
3047 *input_pointerP = q;
3051 /* Parse an argument that is a constant expression.
3052 The result is a boolean indicating success. */
3055 parse_const_expr_arg (char **input_pointerP, int *valueP)
3057 char *save = input_line_pointer;
3060 input_line_pointer = *input_pointerP;
3061 /* The next expression may be something other than a constant
3062 (say if we're not processing the right variant of the insn).
3063 Don't call expression unless we're sure it will succeed as it will
3064 signal an error (which we want to defer until later). */
3065 /* FIXME: It might be better to define md_operand and have it recognize
3066 things like %asi, etc. but continuing that route through to the end
3067 is a lot of work. */
3068 if (*input_line_pointer == '%')
3070 input_line_pointer = save;
3074 *input_pointerP = input_line_pointer;
3075 input_line_pointer = save;
3076 if (exp.X_op != O_constant)
3078 *valueP = exp.X_add_number;
3082 /* Subroutine of sparc_ip to parse an expression. */
3085 get_expression (char *str)
3090 save_in = input_line_pointer;
3091 input_line_pointer = str;
3092 seg = expression (&the_insn.exp);
3093 if (seg != absolute_section
3094 && seg != text_section
3095 && seg != data_section
3096 && seg != bss_section
3097 && seg != undefined_section)
3099 the_insn.error = _("bad segment");
3100 expr_end = input_line_pointer;
3101 input_line_pointer = save_in;
3104 expr_end = input_line_pointer;
3105 input_line_pointer = save_in;
3109 /* Subroutine of md_assemble to output one insn. */
3112 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3114 char *toP = frag_more (4);
3116 /* Put out the opcode. */
3117 if (INSN_BIG_ENDIAN)
3118 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3120 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3122 /* Put out the symbol-dependent stuff. */
3123 if (theinsn->reloc != BFD_RELOC_NONE)
3125 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3126 (toP - frag_now->fr_literal), /* Where. */
3131 /* Turn off overflow checking in fixup_segment. We'll do our
3132 own overflow checking in md_apply_fix. This is necessary because
3133 the insn size is 4 and fixup_segment will signal an overflow for
3134 large 8 byte quantities. */
3135 fixP->fx_no_overflow = 1;
3136 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3137 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3141 last_opcode = theinsn->opcode;
3144 dwarf2_emit_insn (4);
3149 md_atof (int type, char *litP, int *sizeP)
3151 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3154 /* Write a value out to the object file, using the appropriate
3158 md_number_to_chars (char *buf, valueT val, int n)
3160 if (target_big_endian)
3161 number_to_chars_bigendian (buf, val, n);
3162 else if (target_little_endian_data
3163 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3164 /* Output debug words, which are not in allocated sections, as big
3166 number_to_chars_bigendian (buf, val, n);
3167 else if (target_little_endian_data || ! target_big_endian)
3168 number_to_chars_littleendian (buf, val, n);
3171 /* Apply a fixS to the frags, now that we know the value it ought to
3175 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3177 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3178 offsetT val = * (offsetT *) valP;
3181 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3183 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3186 /* SPARC ELF relocations don't use an addend in the data field. */
3187 if (fixP->fx_addsy != NULL)
3189 switch (fixP->fx_r_type)
3191 case BFD_RELOC_SPARC_TLS_GD_HI22:
3192 case BFD_RELOC_SPARC_TLS_GD_LO10:
3193 case BFD_RELOC_SPARC_TLS_GD_ADD:
3194 case BFD_RELOC_SPARC_TLS_GD_CALL:
3195 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3196 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3197 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3198 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3199 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3200 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3201 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3202 case BFD_RELOC_SPARC_TLS_IE_HI22:
3203 case BFD_RELOC_SPARC_TLS_IE_LO10:
3204 case BFD_RELOC_SPARC_TLS_IE_LD:
3205 case BFD_RELOC_SPARC_TLS_IE_LDX:
3206 case BFD_RELOC_SPARC_TLS_IE_ADD:
3207 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3208 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3209 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3210 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3211 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3212 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3213 case BFD_RELOC_SPARC_TLS_TPOFF32:
3214 case BFD_RELOC_SPARC_TLS_TPOFF64:
3215 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3225 /* This is a hack. There should be a better way to
3226 handle this. Probably in terms of howto fields, once
3227 we can look at these fixups in terms of howtos. */
3228 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3229 val += fixP->fx_where + fixP->fx_frag->fr_address;
3232 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3233 generate a reloc, then we just want to let the reloc addend set
3234 the value. We do not want to also stuff the addend into the
3235 object file. Including the addend in the object file works when
3236 doing a static link, because the linker will ignore the object
3237 file contents. However, the dynamic linker does not ignore the
3238 object file contents. */
3239 if (fixP->fx_addsy != NULL
3240 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3243 /* When generating PIC code, we do not want an addend for a reloc
3244 against a local symbol. We adjust fx_addnumber to cancel out the
3245 value already included in val, and to also cancel out the
3246 adjustment which bfd_install_relocation will create. */
3248 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3249 && fixP->fx_addsy != NULL
3250 && ! S_IS_COMMON (fixP->fx_addsy)
3251 && symbol_section_p (fixP->fx_addsy))
3252 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3254 /* When generating PIC code, we need to fiddle to get
3255 bfd_install_relocation to do the right thing for a PC relative
3256 reloc against a local symbol which we are going to keep. */
3258 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3259 && fixP->fx_addsy != NULL
3260 && (S_IS_EXTERNAL (fixP->fx_addsy)
3261 || S_IS_WEAK (fixP->fx_addsy))
3262 && S_IS_DEFINED (fixP->fx_addsy)
3263 && ! S_IS_COMMON (fixP->fx_addsy))
3266 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3270 /* If this is a data relocation, just output VAL. */
3272 if (fixP->fx_r_type == BFD_RELOC_8)
3274 md_number_to_chars (buf, val, 1);
3276 else if (fixP->fx_r_type == BFD_RELOC_16
3277 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3279 md_number_to_chars (buf, val, 2);
3281 else if (fixP->fx_r_type == BFD_RELOC_32
3282 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3283 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3285 md_number_to_chars (buf, val, 4);
3287 else if (fixP->fx_r_type == BFD_RELOC_64
3288 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3290 md_number_to_chars (buf, val, 8);
3292 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3293 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3300 /* It's a relocation against an instruction. */
3302 if (INSN_BIG_ENDIAN)
3303 insn = bfd_getb32 ((unsigned char *) buf);
3305 insn = bfd_getl32 ((unsigned char *) buf);
3307 switch (fixP->fx_r_type)
3309 case BFD_RELOC_32_PCREL_S2:
3311 /* FIXME: This increment-by-one deserves a comment of why it's
3313 if (! sparc_pic_code
3314 || fixP->fx_addsy == NULL
3315 || symbol_section_p (fixP->fx_addsy))
3318 insn |= val & 0x3fffffff;
3320 /* See if we have a delay slot. */
3321 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3325 #define XCC (2 << 20)
3326 #define COND(x) (((x)&0xf)<<25)
3327 #define CONDA COND(0x8)
3328 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3329 #define INSN_BA (F2(0,2) | CONDA)
3330 #define INSN_OR F3(2, 0x2, 0)
3331 #define INSN_NOP F2(0,4)
3335 /* If the instruction is a call with either:
3337 arithmetic instruction with rd == %o7
3338 where rs1 != %o7 and rs2 if it is register != %o7
3339 then we can optimize if the call destination is near
3340 by changing the call into a branch always. */
3341 if (INSN_BIG_ENDIAN)
3342 delay = bfd_getb32 ((unsigned char *) buf + 4);
3344 delay = bfd_getl32 ((unsigned char *) buf + 4);
3345 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3347 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3348 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3349 || ((delay & RD (~0)) != RD (O7))))
3351 if ((delay & RS1 (~0)) == RS1 (O7)
3352 || ((delay & F3I (~0)) == 0
3353 && (delay & RS2 (~0)) == RS2 (O7)))
3355 /* Ensure the branch will fit into simm22. */
3356 if ((val & 0x3fe00000)
3357 && (val & 0x3fe00000) != 0x3fe00000)
3359 /* Check if the arch is v9 and branch will fit
3361 if (((val & 0x3c0000) == 0
3362 || (val & 0x3c0000) == 0x3c0000)
3363 && (sparc_arch_size == 64
3364 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3366 insn = INSN_BPA | (val & 0x7ffff);
3369 insn = INSN_BA | (val & 0x3fffff);
3370 if (fixP->fx_where >= 4
3371 && ((delay & (0xffffffff ^ RS1 (~0)))
3372 == (INSN_OR | RD (O7) | RS2 (G0))))
3377 if (INSN_BIG_ENDIAN)
3378 setter = bfd_getb32 ((unsigned char *) buf - 4);
3380 setter = bfd_getl32 ((unsigned char *) buf - 4);
3381 if ((setter & (0xffffffff ^ RD (~0)))
3382 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3389 If call foo was replaced with ba, replace
3390 or %rN, %g0, %o7 with nop. */
3391 reg = (delay & RS1 (~0)) >> 14;
3392 if (reg != ((setter & RD (~0)) >> 25)
3393 || reg == G0 || reg == O7)
3396 if (INSN_BIG_ENDIAN)
3397 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3399 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3404 case BFD_RELOC_SPARC_11:
3405 if (! in_signed_range (val, 0x7ff))
3406 as_bad_where (fixP->fx_file, fixP->fx_line,
3407 _("relocation overflow"));
3408 insn |= val & 0x7ff;
3411 case BFD_RELOC_SPARC_10:
3412 if (! in_signed_range (val, 0x3ff))
3413 as_bad_where (fixP->fx_file, fixP->fx_line,
3414 _("relocation overflow"));
3415 insn |= val & 0x3ff;
3418 case BFD_RELOC_SPARC_7:
3419 if (! in_bitfield_range (val, 0x7f))
3420 as_bad_where (fixP->fx_file, fixP->fx_line,
3421 _("relocation overflow"));
3425 case BFD_RELOC_SPARC_6:
3426 if (! in_bitfield_range (val, 0x3f))
3427 as_bad_where (fixP->fx_file, fixP->fx_line,
3428 _("relocation overflow"));
3432 case BFD_RELOC_SPARC_5:
3433 if (! in_bitfield_range (val, 0x1f))
3434 as_bad_where (fixP->fx_file, fixP->fx_line,
3435 _("relocation overflow"));
3439 case BFD_RELOC_SPARC_WDISP10:
3442 || val <= -(offsetT) 0x808)
3443 as_bad_where (fixP->fx_file, fixP->fx_line,
3444 _("relocation overflow"));
3445 /* FIXME: The +1 deserves a comment. */
3446 val = (val >> 2) + 1;
3447 insn |= ((val & 0x300) << 11)
3448 | ((val & 0xff) << 5);
3451 case BFD_RELOC_SPARC_WDISP16:
3454 || val <= -(offsetT) 0x20008)
3455 as_bad_where (fixP->fx_file, fixP->fx_line,
3456 _("relocation overflow"));
3457 /* FIXME: The +1 deserves a comment. */
3458 val = (val >> 2) + 1;
3459 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3462 case BFD_RELOC_SPARC_WDISP19:
3465 || val <= -(offsetT) 0x100008)
3466 as_bad_where (fixP->fx_file, fixP->fx_line,
3467 _("relocation overflow"));
3468 /* FIXME: The +1 deserves a comment. */
3469 val = (val >> 2) + 1;
3470 insn |= val & 0x7ffff;
3473 case BFD_RELOC_SPARC_HH22:
3474 val = BSR (val, 32);
3477 case BFD_RELOC_SPARC_LM22:
3478 case BFD_RELOC_HI22:
3479 if (!fixP->fx_addsy)
3480 insn |= (val >> 10) & 0x3fffff;
3482 /* FIXME: Need comment explaining why we do this. */
3486 case BFD_RELOC_SPARC22:
3487 if (val & ~0x003fffff)
3488 as_bad_where (fixP->fx_file, fixP->fx_line,
3489 _("relocation overflow"));
3490 insn |= (val & 0x3fffff);
3493 case BFD_RELOC_SPARC_HM10:
3494 val = BSR (val, 32);
3497 case BFD_RELOC_LO10:
3498 if (!fixP->fx_addsy)
3499 insn |= val & 0x3ff;
3501 /* FIXME: Need comment explaining why we do this. */
3505 case BFD_RELOC_SPARC_OLO10:
3507 val += fixP->tc_fix_data;
3510 case BFD_RELOC_SPARC13:
3511 if (! in_signed_range (val, 0x1fff))
3512 as_bad_where (fixP->fx_file, fixP->fx_line,
3513 _("relocation overflow"));
3514 insn |= val & 0x1fff;
3517 case BFD_RELOC_SPARC_WDISP22:
3518 val = (val >> 2) + 1;
3520 case BFD_RELOC_SPARC_BASE22:
3521 insn |= val & 0x3fffff;
3524 case BFD_RELOC_SPARC_H34:
3525 if (!fixP->fx_addsy)
3529 insn |= tval & 0x3fffff;
3533 case BFD_RELOC_SPARC_H44:
3534 if (!fixP->fx_addsy)
3538 insn |= tval & 0x3fffff;
3542 case BFD_RELOC_SPARC_M44:
3543 if (!fixP->fx_addsy)
3544 insn |= (val >> 12) & 0x3ff;
3547 case BFD_RELOC_SPARC_L44:
3548 if (!fixP->fx_addsy)
3549 insn |= val & 0xfff;
3552 case BFD_RELOC_SPARC_HIX22:
3553 if (!fixP->fx_addsy)
3555 val ^= ~(offsetT) 0;
3556 insn |= (val >> 10) & 0x3fffff;
3560 case BFD_RELOC_SPARC_LOX10:
3561 if (!fixP->fx_addsy)
3562 insn |= 0x1c00 | (val & 0x3ff);
3565 case BFD_RELOC_NONE:
3567 as_bad_where (fixP->fx_file, fixP->fx_line,
3568 _("bad or unhandled relocation type: 0x%02x"),
3573 if (INSN_BIG_ENDIAN)
3574 bfd_putb32 (insn, (unsigned char *) buf);
3576 bfd_putl32 (insn, (unsigned char *) buf);
3579 /* Are we finished with this relocation now? */
3580 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3584 /* Translate internal representation of relocation info to BFD target
3588 tc_gen_reloc (asection *section, fixS *fixp)
3590 static arelent *relocs[3];
3592 bfd_reloc_code_real_type code;
3594 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3597 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3598 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3599 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3601 switch (fixp->fx_r_type)
3605 case BFD_RELOC_HI22:
3606 case BFD_RELOC_LO10:
3607 case BFD_RELOC_32_PCREL_S2:
3608 case BFD_RELOC_SPARC13:
3609 case BFD_RELOC_SPARC22:
3610 case BFD_RELOC_SPARC_PC22:
3611 case BFD_RELOC_SPARC_PC10:
3612 case BFD_RELOC_SPARC_BASE13:
3613 case BFD_RELOC_SPARC_WDISP10:
3614 case BFD_RELOC_SPARC_WDISP16:
3615 case BFD_RELOC_SPARC_WDISP19:
3616 case BFD_RELOC_SPARC_WDISP22:
3618 case BFD_RELOC_SPARC_5:
3619 case BFD_RELOC_SPARC_6:
3620 case BFD_RELOC_SPARC_7:
3621 case BFD_RELOC_SPARC_10:
3622 case BFD_RELOC_SPARC_11:
3623 case BFD_RELOC_SPARC_HH22:
3624 case BFD_RELOC_SPARC_HM10:
3625 case BFD_RELOC_SPARC_LM22:
3626 case BFD_RELOC_SPARC_PC_HH22:
3627 case BFD_RELOC_SPARC_PC_HM10:
3628 case BFD_RELOC_SPARC_PC_LM22:
3629 case BFD_RELOC_SPARC_H34:
3630 case BFD_RELOC_SPARC_H44:
3631 case BFD_RELOC_SPARC_M44:
3632 case BFD_RELOC_SPARC_L44:
3633 case BFD_RELOC_SPARC_HIX22:
3634 case BFD_RELOC_SPARC_LOX10:
3635 case BFD_RELOC_SPARC_REV32:
3636 case BFD_RELOC_SPARC_OLO10:
3637 case BFD_RELOC_SPARC_UA16:
3638 case BFD_RELOC_SPARC_UA32:
3639 case BFD_RELOC_SPARC_UA64:
3640 case BFD_RELOC_8_PCREL:
3641 case BFD_RELOC_16_PCREL:
3642 case BFD_RELOC_32_PCREL:
3643 case BFD_RELOC_64_PCREL:
3644 case BFD_RELOC_SPARC_PLT32:
3645 case BFD_RELOC_SPARC_PLT64:
3646 case BFD_RELOC_VTABLE_ENTRY:
3647 case BFD_RELOC_VTABLE_INHERIT:
3648 case BFD_RELOC_SPARC_TLS_GD_HI22:
3649 case BFD_RELOC_SPARC_TLS_GD_LO10:
3650 case BFD_RELOC_SPARC_TLS_GD_ADD:
3651 case BFD_RELOC_SPARC_TLS_GD_CALL:
3652 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3653 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3654 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3655 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3656 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3657 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3658 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3659 case BFD_RELOC_SPARC_TLS_IE_HI22:
3660 case BFD_RELOC_SPARC_TLS_IE_LO10:
3661 case BFD_RELOC_SPARC_TLS_IE_LD:
3662 case BFD_RELOC_SPARC_TLS_IE_LDX:
3663 case BFD_RELOC_SPARC_TLS_IE_ADD:
3664 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3665 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3666 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3667 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3668 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3669 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3670 case BFD_RELOC_SPARC_GOTDATA_OP:
3671 code = fixp->fx_r_type;
3678 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3679 /* If we are generating PIC code, we need to generate a different
3683 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3685 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3688 #define GOTT_BASE "__GOTT_BASE__"
3689 #define GOTT_INDEX "__GOTT_INDEX__"
3692 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3698 case BFD_RELOC_32_PCREL_S2:
3699 if (generic_force_reloc (fixp))
3700 code = BFD_RELOC_SPARC_WPLT30;
3702 case BFD_RELOC_HI22:
3703 code = BFD_RELOC_SPARC_GOT22;
3704 if (fixp->fx_addsy != NULL)
3706 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3707 code = BFD_RELOC_SPARC_PC22;
3709 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3710 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3711 code = BFD_RELOC_HI22; /* Unchanged. */
3715 case BFD_RELOC_LO10:
3716 code = BFD_RELOC_SPARC_GOT10;
3717 if (fixp->fx_addsy != NULL)
3719 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3720 code = BFD_RELOC_SPARC_PC10;
3722 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3723 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3724 code = BFD_RELOC_LO10; /* Unchanged. */
3728 case BFD_RELOC_SPARC13:
3729 code = BFD_RELOC_SPARC_GOT13;
3735 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3737 /* Nothing is aligned in DWARF debugging sections. */
3738 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3741 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3742 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3743 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3747 if (code == BFD_RELOC_SPARC_OLO10)
3748 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3750 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3751 if (reloc->howto == 0)
3753 as_bad_where (fixp->fx_file, fixp->fx_line,
3754 _("internal error: can't export reloc type %d (`%s')"),
3755 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3761 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3764 if (reloc->howto->pc_relative == 0
3765 || code == BFD_RELOC_SPARC_PC10
3766 || code == BFD_RELOC_SPARC_PC22)
3767 reloc->addend = fixp->fx_addnumber;
3768 else if (sparc_pic_code
3769 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3770 && fixp->fx_addsy != NULL
3771 && (S_IS_EXTERNAL (fixp->fx_addsy)
3772 || S_IS_WEAK (fixp->fx_addsy))
3773 && S_IS_DEFINED (fixp->fx_addsy)
3774 && ! S_IS_COMMON (fixp->fx_addsy))
3775 reloc->addend = fixp->fx_addnumber;
3777 reloc->addend = fixp->fx_offset - reloc->address;
3779 #else /* elf or coff */
3781 if (code != BFD_RELOC_32_PCREL_S2
3782 && code != BFD_RELOC_SPARC_WDISP22
3783 && code != BFD_RELOC_SPARC_WDISP16
3784 && code != BFD_RELOC_SPARC_WDISP19
3785 && code != BFD_RELOC_SPARC_WDISP10
3786 && code != BFD_RELOC_SPARC_WPLT30
3787 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3788 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3789 reloc->addend = fixp->fx_addnumber;
3790 else if (symbol_section_p (fixp->fx_addsy))
3791 reloc->addend = (section->vma
3792 + fixp->fx_addnumber
3793 + md_pcrel_from (fixp));
3795 reloc->addend = fixp->fx_offset;
3798 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3799 on the same location. */
3800 if (code == BFD_RELOC_SPARC_OLO10)
3802 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3805 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3807 = symbol_get_bfdsym (section_symbol (absolute_section));
3808 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3809 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3810 reloc->addend = fixp->tc_fix_data;
3816 /* We have no need to default values of symbols. */
3819 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3824 /* Round up a section size to the appropriate boundary. */
3827 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3830 /* This is not right for ELF; a.out wants it, and COFF will force
3831 the alignment anyways. */
3832 valueT align = ((valueT) 1
3833 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3836 /* Turn alignment value into a mask. */
3838 newsize = (size + align) & ~align;
3845 /* Exactly what point is a PC-relative offset relative TO?
3846 On the sparc, they're relative to the address of the offset, plus
3847 its size. This gets us to the following instruction.
3848 (??? Is this right? FIXME-SOON) */
3850 md_pcrel_from (fixS *fixP)
3854 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3855 if (! sparc_pic_code
3856 || fixP->fx_addsy == NULL
3857 || symbol_section_p (fixP->fx_addsy))
3858 ret += fixP->fx_size;
3862 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3873 for (shift = 0; (value & 1) == 0; value >>= 1)
3876 return (value == 1) ? shift : -1;
3879 /* Sort of like s_lcomm. */
3882 static int max_alignment = 15;
3886 s_reserve (int ignore ATTRIBUTE_UNUSED)
3896 name = input_line_pointer;
3897 c = get_symbol_end ();
3898 p = input_line_pointer;
3902 if (*input_line_pointer != ',')
3904 as_bad (_("Expected comma after name"));
3905 ignore_rest_of_line ();
3909 ++input_line_pointer;
3911 if ((size = get_absolute_expression ()) < 0)
3913 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3914 ignore_rest_of_line ();
3919 symbolP = symbol_find_or_make (name);
3922 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3923 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3925 as_bad (_("bad .reserve segment -- expected BSS segment"));
3929 if (input_line_pointer[2] == '.')
3930 input_line_pointer += 7;
3932 input_line_pointer += 6;
3935 if (*input_line_pointer == ',')
3937 ++input_line_pointer;
3940 if (*input_line_pointer == '\n')
3942 as_bad (_("missing alignment"));
3943 ignore_rest_of_line ();
3947 align = (int) get_absolute_expression ();
3950 if (align > max_alignment)
3952 align = max_alignment;
3953 as_warn (_("alignment too large; assuming %d"), align);
3959 as_bad (_("negative alignment"));
3960 ignore_rest_of_line ();
3966 temp = mylog2 (align);
3969 as_bad (_("alignment not a power of 2"));
3970 ignore_rest_of_line ();
3977 record_alignment (bss_section, align);
3982 if (!S_IS_DEFINED (symbolP)
3984 && S_GET_OTHER (symbolP) == 0
3985 && S_GET_DESC (symbolP) == 0
3992 segT current_seg = now_seg;
3993 subsegT current_subseg = now_subseg;
3995 /* Switch to bss. */
3996 subseg_set (bss_section, 1);
4000 frag_align (align, 0, 0);
4002 /* Detach from old frag. */
4003 if (S_GET_SEGMENT (symbolP) == bss_section)
4004 symbol_get_frag (symbolP)->fr_symbol = NULL;
4006 symbol_set_frag (symbolP, frag_now);
4007 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4008 (offsetT) size, (char *) 0);
4011 S_SET_SEGMENT (symbolP, bss_section);
4013 subseg_set (current_seg, current_subseg);
4016 S_SET_SIZE (symbolP, size);
4022 as_warn (_("Ignoring attempt to re-define symbol %s"),
4023 S_GET_NAME (symbolP));
4026 demand_empty_rest_of_line ();
4030 s_common (int ignore ATTRIBUTE_UNUSED)
4038 name = input_line_pointer;
4039 c = get_symbol_end ();
4040 /* Just after name is now '\0'. */
4041 p = input_line_pointer;
4044 if (*input_line_pointer != ',')
4046 as_bad (_("Expected comma after symbol-name"));
4047 ignore_rest_of_line ();
4052 input_line_pointer++;
4054 if ((temp = get_absolute_expression ()) < 0)
4056 as_bad (_(".COMMon length (%lu) out of range ignored"),
4057 (unsigned long) temp);
4058 ignore_rest_of_line ();
4063 symbolP = symbol_find_or_make (name);
4065 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4067 as_bad (_("Ignoring attempt to re-define symbol"));
4068 ignore_rest_of_line ();
4071 if (S_GET_VALUE (symbolP) != 0)
4073 if (S_GET_VALUE (symbolP) != (valueT) size)
4075 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4076 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4082 S_SET_VALUE (symbolP, (valueT) size);
4083 S_SET_EXTERNAL (symbolP);
4086 know (symbol_get_frag (symbolP) == &zero_address_frag);
4087 if (*input_line_pointer != ',')
4089 as_bad (_("Expected comma after common length"));
4090 ignore_rest_of_line ();
4093 input_line_pointer++;
4095 if (*input_line_pointer != '"')
4097 temp = get_absolute_expression ();
4100 if (temp > max_alignment)
4102 temp = max_alignment;
4103 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4109 as_bad (_("negative alignment"));
4110 ignore_rest_of_line ();
4115 if (symbol_get_obj (symbolP)->local)
4122 old_subsec = now_subseg;
4127 align = mylog2 (temp);
4131 as_bad (_("alignment not a power of 2"));
4132 ignore_rest_of_line ();
4136 record_alignment (bss_section, align);
4137 subseg_set (bss_section, 0);
4139 frag_align (align, 0, 0);
4140 if (S_GET_SEGMENT (symbolP) == bss_section)
4141 symbol_get_frag (symbolP)->fr_symbol = 0;
4142 symbol_set_frag (symbolP, frag_now);
4143 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4144 (offsetT) size, (char *) 0);
4146 S_SET_SEGMENT (symbolP, bss_section);
4147 S_CLEAR_EXTERNAL (symbolP);
4148 S_SET_SIZE (symbolP, size);
4149 subseg_set (old_sec, old_subsec);
4152 #endif /* OBJ_ELF */
4155 S_SET_VALUE (symbolP, (valueT) size);
4157 S_SET_ALIGN (symbolP, temp);
4158 S_SET_SIZE (symbolP, size);
4160 S_SET_EXTERNAL (symbolP);
4161 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4166 input_line_pointer++;
4167 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4168 if (*input_line_pointer == '.')
4169 input_line_pointer++;
4170 /* @@ Some say data, some say bss. */
4171 if (strncmp (input_line_pointer, "bss\"", 4)
4172 && strncmp (input_line_pointer, "data\"", 5))
4174 while (*--input_line_pointer != '"')
4176 input_line_pointer--;
4177 goto bad_common_segment;
4179 while (*input_line_pointer++ != '"')
4181 goto allocate_common;
4184 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4186 demand_empty_rest_of_line ();
4191 p = input_line_pointer;
4192 while (*p && *p != '\n')
4196 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4198 input_line_pointer = p;
4199 ignore_rest_of_line ();
4204 /* Handle the .empty pseudo-op. This suppresses the warnings about
4205 invalid delay slot usage. */
4208 s_empty (int ignore ATTRIBUTE_UNUSED)
4210 /* The easy way to implement is to just forget about the last
4216 s_seg (int ignore ATTRIBUTE_UNUSED)
4219 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4221 input_line_pointer += 6;
4225 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4227 input_line_pointer += 6;
4231 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4233 input_line_pointer += 7;
4237 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4239 input_line_pointer += 5;
4240 /* We only support 2 segments -- text and data -- for now, so
4241 things in the "bss segment" will have to go into data for now.
4242 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4243 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4246 as_bad (_("Unknown segment type"));
4247 demand_empty_rest_of_line ();
4253 subseg_set (data_section, 1);
4254 demand_empty_rest_of_line ();
4258 s_proc (int ignore ATTRIBUTE_UNUSED)
4260 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4262 ++input_line_pointer;
4264 ++input_line_pointer;
4267 /* This static variable is set by s_uacons to tell sparc_cons_align
4268 that the expression does not need to be aligned. */
4270 static int sparc_no_align_cons = 0;
4272 /* This static variable is set by sparc_cons to emit requested types
4273 of relocations in cons_fix_new_sparc. */
4275 static const char *sparc_cons_special_reloc;
4277 /* This handles the unaligned space allocation pseudo-ops, such as
4278 .uaword. .uaword is just like .word, but the value does not need
4282 s_uacons (int bytes)
4284 /* Tell sparc_cons_align not to align this value. */
4285 sparc_no_align_cons = 1;
4287 sparc_no_align_cons = 0;
4290 /* This handles the native word allocation pseudo-op .nword.
4291 For sparc_arch_size 32 it is equivalent to .word, for
4292 sparc_arch_size 64 it is equivalent to .xword. */
4295 s_ncons (int bytes ATTRIBUTE_UNUSED)
4297 cons (sparc_arch_size == 32 ? 4 : 8);
4301 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4305 .register %g[2367],{#scratch|symbolname|#ignore}
4309 s_register (int ignore ATTRIBUTE_UNUSED)
4314 const char *regname;
4316 if (input_line_pointer[0] != '%'
4317 || input_line_pointer[1] != 'g'
4318 || ((input_line_pointer[2] & ~1) != '2'
4319 && (input_line_pointer[2] & ~1) != '6')
4320 || input_line_pointer[3] != ',')
4321 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4322 reg = input_line_pointer[2] - '0';
4323 input_line_pointer += 4;
4325 if (*input_line_pointer == '#')
4327 ++input_line_pointer;
4328 regname = input_line_pointer;
4329 c = get_symbol_end ();
4330 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4331 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4332 if (regname[0] == 'i')
4339 regname = input_line_pointer;
4340 c = get_symbol_end ();
4342 if (sparc_arch_size == 64)
4346 if ((regname && globals[reg] != (symbolS *) 1
4347 && strcmp (S_GET_NAME (globals[reg]), regname))
4348 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4349 as_bad (_("redefinition of global register"));
4353 if (regname == NULL)
4354 globals[reg] = (symbolS *) 1;
4359 if (symbol_find (regname))
4360 as_bad (_("Register symbol %s already defined."),
4363 globals[reg] = symbol_make (regname);
4364 flags = symbol_get_bfdsym (globals[reg])->flags;
4366 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4367 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4368 flags |= BSF_GLOBAL;
4369 symbol_get_bfdsym (globals[reg])->flags = flags;
4370 S_SET_VALUE (globals[reg], (valueT) reg);
4371 S_SET_ALIGN (globals[reg], reg);
4372 S_SET_SIZE (globals[reg], 0);
4373 /* Although we actually want undefined_section here,
4374 we have to use absolute_section, because otherwise
4375 generic as code will make it a COM section.
4376 We fix this up in sparc_adjust_symtab. */
4377 S_SET_SEGMENT (globals[reg], absolute_section);
4378 S_SET_OTHER (globals[reg], 0);
4379 elf_symbol (symbol_get_bfdsym (globals[reg]))
4380 ->internal_elf_sym.st_info =
4381 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4382 elf_symbol (symbol_get_bfdsym (globals[reg]))
4383 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4388 *input_line_pointer = c;
4390 demand_empty_rest_of_line ();
4393 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4394 symbols which need it. */
4397 sparc_adjust_symtab (void)
4401 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4403 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4404 ->internal_elf_sym.st_info) != STT_REGISTER)
4407 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4408 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4411 S_SET_SEGMENT (sym, undefined_section);
4416 /* If the --enforce-aligned-data option is used, we require .word,
4417 et. al., to be aligned correctly. We do it by setting up an
4418 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4419 no unexpected alignment was introduced.
4421 The SunOS and Solaris native assemblers enforce aligned data by
4422 default. We don't want to do that, because gcc can deliberately
4423 generate misaligned data if the packed attribute is used. Instead,
4424 we permit misaligned data by default, and permit the user to set an
4425 option to check for it. */
4428 sparc_cons_align (int nbytes)
4432 /* Only do this if we are enforcing aligned data. */
4433 if (! enforce_aligned_data)
4436 /* Don't align if this is an unaligned pseudo-op. */
4437 if (sparc_no_align_cons)
4440 nalign = mylog2 (nbytes);
4444 gas_assert (nalign > 0);
4446 if (now_seg == absolute_section)
4448 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4449 as_bad (_("misaligned data"));
4453 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4454 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4456 record_alignment (now_seg, nalign);
4459 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4462 sparc_handle_align (fragS *fragp)
4467 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4469 switch (fragp->fr_type)
4473 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4477 p = fragp->fr_literal + fragp->fr_fix;
4488 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4490 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4491 if (INSN_BIG_ENDIAN)
4492 number_to_chars_bigendian (p, wval, 4);
4494 number_to_chars_littleendian (p, wval, 4);
4500 if (INSN_BIG_ENDIAN)
4501 number_to_chars_bigendian (p, 0x01000000, 4);
4503 number_to_chars_littleendian (p, 0x01000000, 4);
4505 fragp->fr_fix += fix;
4515 /* Some special processing for a Sparc ELF file. */
4518 sparc_elf_final_processing (void)
4520 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4521 sort of BFD interface for this. */
4522 if (sparc_arch_size == 64)
4524 switch (sparc_memory_model)
4527 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4530 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4536 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4537 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4538 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4539 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4540 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4541 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4545 sparc_cons (expressionS *exp, int size)
4550 sparc_cons_special_reloc = NULL;
4551 save = input_line_pointer;
4552 if (input_line_pointer[0] == '%'
4553 && input_line_pointer[1] == 'r'
4554 && input_line_pointer[2] == '_')
4556 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4558 input_line_pointer += 7;
4559 sparc_cons_special_reloc = "disp";
4561 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4563 if (size != 4 && size != 8)
4564 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4567 input_line_pointer += 6;
4568 sparc_cons_special_reloc = "plt";
4571 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4573 if (size != 4 && size != 8)
4574 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4577 input_line_pointer += 13;
4578 sparc_cons_special_reloc = "tls_dtpoff";
4581 if (sparc_cons_special_reloc)
4588 if (*input_line_pointer != '8')
4590 input_line_pointer--;
4593 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4597 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4601 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4611 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4612 sparc_cons_special_reloc, size * 8, size);
4616 input_line_pointer += 2;
4617 if (*input_line_pointer != '(')
4619 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4620 sparc_cons_special_reloc, size * 8);
4627 input_line_pointer = save;
4628 sparc_cons_special_reloc = NULL;
4633 char *end = ++input_line_pointer;
4636 while (! is_end_of_line[(c = *end)])
4650 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4651 sparc_cons_special_reloc, size * 8);
4657 if (input_line_pointer != end)
4659 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4660 sparc_cons_special_reloc, size * 8);
4664 input_line_pointer++;
4666 c = *input_line_pointer;
4667 if (! is_end_of_line[c] && c != ',')
4668 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4669 sparc_cons_special_reloc, size * 8);
4675 if (sparc_cons_special_reloc == NULL)
4681 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4682 reloc for a cons. We could use the definition there, except that
4683 we want to handle little endian relocs specially. */
4686 cons_fix_new_sparc (fragS *frag,
4688 unsigned int nbytes,
4691 bfd_reloc_code_real_type r;
4693 r = (nbytes == 1 ? BFD_RELOC_8 :
4694 (nbytes == 2 ? BFD_RELOC_16 :
4695 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4697 if (target_little_endian_data
4699 && now_seg->flags & SEC_ALLOC)
4700 r = BFD_RELOC_SPARC_REV32;
4702 if (sparc_cons_special_reloc)
4704 if (*sparc_cons_special_reloc == 'd')
4707 case 1: r = BFD_RELOC_8_PCREL; break;
4708 case 2: r = BFD_RELOC_16_PCREL; break;
4709 case 4: r = BFD_RELOC_32_PCREL; break;
4710 case 8: r = BFD_RELOC_64_PCREL; break;
4713 else if (*sparc_cons_special_reloc == 'p')
4716 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4717 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4722 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4723 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4726 else if (sparc_no_align_cons)
4730 case 2: r = BFD_RELOC_SPARC_UA16; break;
4731 case 4: r = BFD_RELOC_SPARC_UA32; break;
4732 case 8: r = BFD_RELOC_SPARC_UA64; break;
4737 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4738 sparc_cons_special_reloc = NULL;
4742 sparc_cfi_frame_initial_instructions (void)
4744 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4748 sparc_regname_to_dw2regnum (char *regname)
4756 p = strchr (q, regname[0]);
4759 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4761 return (p - q) * 8 + regname[1] - '0';
4763 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4765 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4767 if (regname[0] == 'f' || regname[0] == 'r')
4769 unsigned int regnum;
4771 regnum = strtoul (regname + 1, &q, 10);
4774 if (regnum >= ((regname[0] == 'f'
4775 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4778 if (regname[0] == 'f')
4781 if (regnum >= 64 && (regnum & 1))
4790 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4792 sparc_cons_special_reloc = "disp";
4793 sparc_no_align_cons = 1;
4794 emit_expr (exp, nbytes);
4795 sparc_no_align_cons = 0;
4796 sparc_cons_special_reloc = NULL;