1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
29 static struct sparc_arch *lookup_arch PARAMS ((char *));
30 static void init_default_arch PARAMS ((void));
31 static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
32 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
33 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
34 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
35 static int sparc_ffs PARAMS ((unsigned int));
36 static bfd_vma BSR PARAMS ((bfd_vma, int));
37 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
38 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
39 static int parse_const_expr_arg PARAMS ((char **, int *));
40 static int get_expression PARAMS ((char *str));
42 /* Default architecture. */
43 /* ??? The default value should be V8, but sparclite support was added
44 by making it the default. GCC now passes -Asparclite, so maybe sometime in
45 the future we can set this to V8. */
47 #define DEFAULT_ARCH "sparclite"
49 static char *default_arch = DEFAULT_ARCH;
51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
53 static int default_init_p;
55 /* Current architecture. We don't bump up unless necessary. */
56 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
58 /* The maximum architecture level we can bump up to.
59 In a 32 bit environment, don't allow bumping up to v9 by default.
60 The native assembler works this way. The user is required to pass
61 an explicit argument before we'll create v9 object files. However, if
62 we don't see any v9 insns, a v8plus object file is not created. */
63 static enum sparc_opcode_arch_val max_architecture;
65 /* Either 32 or 64, selects file format. */
66 static int sparc_arch_size;
67 /* Initial (default) value, recorded separately in case a user option
68 changes the value before md_show_usage is called. */
69 static int default_arch_size;
71 static int architecture_requested;
72 static int warn_on_bump;
74 /* If warn_on_bump and the needed architecture is higher than this
75 architecture, issue a warning. */
76 static enum sparc_opcode_arch_val warn_after_architecture;
78 /* Non-zero if we are generating PIC code. */
81 /* Non-zero if we should give an error when misaligned data is seen. */
82 static int enforce_aligned_data;
84 extern int target_big_endian;
86 /* V9 has big and little endian data, but instructions are always big endian.
87 The sparclet has bi-endian support but both data and insns have the same
88 endianness. Global `target_big_endian' is used for data. The following
89 macro is used for instructions. */
90 #define INSN_BIG_ENDIAN (target_big_endian \
91 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
93 /* handle of the OPCODE hash table */
94 static struct hash_control *op_hash;
96 static void s_data1 PARAMS ((void));
97 static void s_seg PARAMS ((int));
98 static void s_proc PARAMS ((int));
99 static void s_reserve PARAMS ((int));
100 static void s_common PARAMS ((int));
101 static void s_empty PARAMS ((int));
102 static void s_uacons PARAMS ((int));
104 const pseudo_typeS md_pseudo_table[] =
106 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
107 {"common", s_common, 0},
108 {"empty", s_empty, 0},
109 {"global", s_globl, 0},
111 {"optim", s_ignore, 0},
113 {"reserve", s_reserve, 0},
115 {"skip", s_space, 0},
118 {"uahalf", s_uacons, 2},
119 {"uaword", s_uacons, 4},
120 {"uaxword", s_uacons, 8},
122 /* these are specific to sparc/svr4 */
123 {"pushsection", obj_elf_section, 0},
124 {"popsection", obj_elf_previous, 0},
125 {"2byte", s_uacons, 2},
126 {"4byte", s_uacons, 4},
127 {"8byte", s_uacons, 8},
132 const int md_reloc_size = 12; /* Size of relocation record */
134 /* This array holds the chars that always start a comment. If the
135 pre-processor is disabled, these aren't very useful */
136 const char comment_chars[] = "!"; /* JF removed '|' from comment_chars */
138 /* This array holds the chars that only start a comment at the beginning of
139 a line. If the line seems to have the form '# 123 filename'
140 .line and .file directives will appear in the pre-processed output */
141 /* Note that input_file.c hand checks for '#' at the beginning of the
142 first line of the input file. This is because the compiler outputs
143 #NO_APP at the beginning of its output. */
144 /* Also note that comments started like this one will always
145 work if '/' isn't otherwise defined. */
146 const char line_comment_chars[] = "#";
148 const char line_separator_chars[] = "";
150 /* Chars that can be used to separate mant from exp in floating point nums */
151 const char EXP_CHARS[] = "eE";
153 /* Chars that mean this number is a floating point constant */
156 const char FLT_CHARS[] = "rRsSfFdDxXpP";
158 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
159 changed in read.c. Ideally it shouldn't have to know about it at all,
160 but nothing is ideal around here. */
162 static unsigned char octal[256];
163 #define isoctal(c) octal[(unsigned char) (c)]
164 static unsigned char toHex[256];
169 unsigned long opcode;
170 struct nlist *nlistp;
173 bfd_reloc_code_real_type reloc;
176 struct sparc_it the_insn, set_insn;
178 static void output_insn
179 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
181 /* Table of arguments to -A.
182 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
183 for this use. That table is for opcodes only. This table is for opcodes
186 static struct sparc_arch {
189 /* Default word size, as specified during configuration.
190 A value of zero means can't be used to specify default architecture. */
191 int default_arch_size;
192 /* Allowable arg to -A? */
194 } sparc_arch_table[] = {
195 { "v6", "v6", 0, 1 },
196 { "v7", "v7", 0, 1 },
197 { "v8", "v8", 32, 1 },
198 { "sparclet", "sparclet", 32, 1 },
199 { "sparclite", "sparclite", 32, 1 },
200 { "v8plus", "v9", 0, 1 },
201 { "v8plusa", "v9a", 0, 1 },
202 { "v9", "v9", 0, 1 },
203 { "v9a", "v9a", 0, 1 },
204 /* This exists to allow configure.in/Makefile.in to pass one
205 value to specify both the default machine and default word size. */
206 { "v9-64", "v9", 64, 0 },
210 static struct sparc_arch *
214 struct sparc_arch *sa;
216 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
217 if (strcmp (sa->name, name) == 0)
219 if (sa->name == NULL)
224 /* Initialize the default opcode arch and word size from the default
225 architecture name. */
230 struct sparc_arch *sa = lookup_arch (default_arch);
233 || sa->default_arch_size == 0)
234 as_fatal ("Invalid default architecture, broken assembler.");
236 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
237 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
238 as_fatal ("Bad opcode table, broken assembler.");
239 default_arch_size = sparc_arch_size = sa->default_arch_size;
243 /* Called by TARGET_FORMAT. */
246 sparc_target_format ()
248 /* We don't get a chance to initialize anything before we're called,
249 so handle that now. */
250 if (! default_init_p)
251 init_default_arch ();
255 return "a.out-sparc-netbsd";
258 return target_big_endian ? "a.out-sunos-big" : "a.out-sparc-little";
260 return "a.out-sunos-big";
271 return "coff-sparc-lynx";
278 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
286 * Invocation line includes a switch not recognized by the base assembler.
287 * See if it's a processor-specific option. These are:
290 * Warn on architecture bumps. See also -A.
292 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
293 * Standard 32 bit architectures.
294 * -Av8plus, -Av8plusa
295 * Sparc64 in a 32 bit world.
297 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
298 * This used to only mean 64 bits, but properly specifying it
299 * complicated gcc's ASM_SPECs, so now opcode selection is
300 * specified orthogonally to word size (except when specifying
301 * the default, but that is an internal implementation detail).
302 * -xarch=v8plus, -xarch=v8plusa
303 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
305 * Select the architecture and possibly the file format.
306 * Instructions or features not supported by the selected
307 * architecture cause fatal errors.
309 * The default is to start at v6, and bump the architecture up
310 * whenever an instruction is seen at a higher level. In 32 bit
311 * environments, v9 is not bumped up to, the user must pass
314 * If -bump is specified, a warning is printing when bumping to
317 * If an architecture is specified, all instructions must match
318 * that architecture. Any higher level instructions are flagged
319 * as errors. Note that in the 32 bit environment specifying
320 * -Av8plus does not automatically create a v8plus object file, a
321 * v9 insn must be seen.
323 * If both an architecture and -bump are specified, the
324 * architecture starts at the specified level, but bumps are
325 * warnings. Note that we can't set `current_architecture' to
326 * the requested level in this case: in the 32 bit environment,
327 * we still must avoid creating v8plus object files unless v9
331 * Bumping between incompatible architectures is always an
332 * error. For example, from sparclite to v9.
336 CONST char *md_shortopts = "A:K:VQ:sq";
339 CONST char *md_shortopts = "A:k";
341 CONST char *md_shortopts = "A:";
344 struct option md_longopts[] = {
345 #define OPTION_BUMP (OPTION_MD_BASE)
346 {"bump", no_argument, NULL, OPTION_BUMP},
347 #define OPTION_SPARC (OPTION_MD_BASE + 1)
348 {"sparc", no_argument, NULL, OPTION_SPARC},
349 #define OPTION_XARCH (OPTION_MD_BASE + 2)
350 {"xarch", required_argument, NULL, OPTION_XARCH},
352 #define OPTION_32 (OPTION_MD_BASE + 3)
353 {"32", no_argument, NULL, OPTION_32},
354 #define OPTION_64 (OPTION_MD_BASE + 4)
355 {"64", no_argument, NULL, OPTION_64},
357 #ifdef SPARC_BIENDIAN
358 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 5)
359 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
360 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 6)
361 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
363 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 7)
364 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
365 {NULL, no_argument, NULL, 0}
367 size_t md_longopts_size = sizeof(md_longopts);
370 md_parse_option (c, arg)
374 /* We don't get a chance to initialize anything before we're called,
375 so handle that now. */
376 if (! default_init_p)
377 init_default_arch ();
383 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
387 /* This is for compatibility with Sun's assembler. */
388 if (strcmp (arg, "v8plus") != 0
389 && strcmp (arg, "v8plusa") != 0)
391 as_bad ("invalid architecture -xarch=%s", arg);
399 struct sparc_arch *sa;
400 enum sparc_opcode_arch_val opcode_arch;
402 sa = lookup_arch (arg);
404 || ! sa->user_option_p)
406 as_bad ("invalid architecture -A%s", arg);
410 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
411 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
412 as_fatal ("Bad opcode table, broken assembler.");
414 max_architecture = opcode_arch;
415 architecture_requested = 1;
420 /* Ignore -sparc, used by SunOS make default .s.o rule. */
423 case OPTION_ENFORCE_ALIGNED_DATA:
424 enforce_aligned_data = 1;
427 #ifdef SPARC_BIENDIAN
428 case OPTION_LITTLE_ENDIAN:
429 target_big_endian = 0;
431 case OPTION_BIG_ENDIAN:
432 target_big_endian = 1;
446 const char **list, **l;
448 sparc_arch_size = c == OPTION_32 ? 32 : 64;
449 list = bfd_target_list ();
450 for (l = list; *l != NULL; l++)
452 if (sparc_arch_size == 32)
454 if (strcmp (*l, "elf32-sparc") == 0)
459 if (strcmp (*l, "elf64-sparc") == 0)
464 as_fatal ("No compiled in support for %d bit object file format",
475 /* Qy - do emit .comment
476 Qn - do not emit .comment */
480 /* use .stab instead of .stab.excl */
484 /* quick -- native assembler does fewer checks */
488 if (strcmp (arg, "PIC") != 0)
489 as_warn ("Unrecognized option following -K");
503 md_show_usage (stream)
506 const struct sparc_arch *arch;
508 /* We don't get a chance to initialize anything before we're called,
509 so handle that now. */
510 if (! default_init_p)
511 init_default_arch ();
513 fprintf(stream, "SPARC options:\n");
514 for (arch = &sparc_arch_table[0]; arch->name; arch++)
516 if (arch != &sparc_arch_table[0])
517 fprintf (stream, " | ");
518 if (arch->user_option_p)
519 fprintf (stream, "-A%s", arch->name);
521 fprintf (stream, "\n-xarch=v8plus | -xarch=v8plusa\n");
523 specify variant of SPARC architecture\n\
524 -bump warn when assembler switches architectures\n\
526 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
533 -32 create 32 bit object file\n\
534 -64 create 64 bit object file\n");
536 [default is %d]\n", default_arch_size);
538 -KPIC generate PIC\n\
539 -V print assembler version number\n\
544 #ifdef SPARC_BIENDIAN
546 -EL generate code for a little endian machine\n\
547 -EB generate code for a big endian machine\n");
551 /* sparc64 priviledged registers */
553 struct priv_reg_entry
559 struct priv_reg_entry priv_reg_table[] =
578 {"", -1}, /* end marker */
582 cmp_reg_entry (parg, qarg)
586 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
587 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
589 return strcmp (q->name, p->name);
592 /* This function is called once, at assembler startup time. It should
593 set up all the tables, etc. that the MD part of the assembler will need. */
598 register const char *retval = NULL;
600 register unsigned int i = 0;
602 /* We don't get a chance to initialize anything before md_parse_option
603 is called, and it may not be called, so handle default initialization
604 now if not already done. */
605 if (! default_init_p)
606 init_default_arch ();
608 op_hash = hash_new ();
610 while (i < sparc_num_opcodes)
612 const char *name = sparc_opcodes[i].name;
613 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
616 fprintf (stderr, "internal error: can't hash `%s': %s\n",
617 sparc_opcodes[i].name, retval);
622 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
624 fprintf (stderr, "internal error: losing opcode: `%s' \"%s\"\n",
625 sparc_opcodes[i].name, sparc_opcodes[i].args);
630 while (i < sparc_num_opcodes
631 && !strcmp (sparc_opcodes[i].name, name));
635 as_fatal ("Broken assembler. No assembly attempted.");
637 for (i = '0'; i < '8'; ++i)
639 for (i = '0'; i <= '9'; ++i)
641 for (i = 'a'; i <= 'f'; ++i)
642 toHex[i] = i + 10 - 'a';
643 for (i = 'A'; i <= 'F'; ++i)
644 toHex[i] = i + 10 - 'A';
646 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
647 sizeof (priv_reg_table[0]), cmp_reg_entry);
649 /* If -bump, record the architecture level at which we start issuing
650 warnings. The behaviour is different depending upon whether an
651 architecture was explicitly specified. If it wasn't, we issue warnings
652 for all upwards bumps. If it was, we don't start issuing warnings until
653 we need to bump beyond the requested architecture or when we bump between
654 conflicting architectures. */
657 && architecture_requested)
659 /* `max_architecture' records the requested architecture.
660 Issue warnings if we go above it. */
661 warn_after_architecture = max_architecture;
663 /* Find the highest architecture level that doesn't conflict with
664 the requested one. */
665 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
666 max_architecture > warn_after_architecture;
668 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
669 warn_after_architecture))
674 /* Called after all assembly has been done. */
679 if (sparc_arch_size == 64)
681 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
682 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
684 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
688 if (current_architecture == SPARC_OPCODE_ARCH_V9)
689 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
690 else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
691 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
692 else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
693 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
696 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
697 be but for now it is (since that's the way it's always been
699 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
704 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
707 in_signed_range (val, max)
708 bfd_signed_vma val, max;
719 /* Return non-zero if VAL is in the range 0 to MAX. */
722 in_unsigned_range (val, max)
730 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
731 (e.g. -15 to +31). */
734 in_bitfield_range (val, max)
735 bfd_signed_vma val, max;
741 if (val < ~(max >> 1))
755 for (i = 0; (mask & 1) == 0; ++i)
760 /* Implement big shift right. */
766 if (sizeof (bfd_vma) <= 4 && amount >= 32)
767 as_fatal ("Support for 64-bit arithmetic not compiled in.");
768 return val >> amount;
771 /* For communication between sparc_ip and get_expression. */
772 static char *expr_end;
774 /* For communication between md_assemble and sparc_ip. */
775 static int special_case;
777 /* Values for `special_case'.
778 Instructions that require wierd handling because they're longer than
780 #define SPECIAL_CASE_NONE 0
781 #define SPECIAL_CASE_SET 1
782 #define SPECIAL_CASE_SETSW 2
783 #define SPECIAL_CASE_SETX 3
784 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
785 #define SPECIAL_CASE_FDIV 4
787 /* Bit masks of various insns. */
788 #define NOP_INSN 0x01000000
789 #define OR_INSN 0x80100000
790 #define FMOVS_INSN 0x81A00020
791 #define SETHI_INSN 0x01000000
792 #define SLLX_INSN 0x81281000
793 #define SRA_INSN 0x81380000
795 /* The last instruction to be assembled. */
796 static const struct sparc_opcode *last_insn;
797 /* The assembled opcode of `last_insn'. */
798 static unsigned long last_opcode;
800 /* Main entry point to assemble one instruction. */
806 const struct sparc_opcode *insn;
809 special_case = SPECIAL_CASE_NONE;
810 sparc_ip (str, &insn);
812 /* We warn about attempts to put a floating point branch in a delay slot,
813 unless the delay slot has been annulled. */
816 && (insn->flags & F_FBR) != 0
817 && (last_insn->flags & F_DELAYED) != 0
818 /* ??? This test isn't completely accurate. We assume anything with
819 F_{UNBR,CONDBR,FBR} set is annullable. */
820 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
821 || (last_opcode & ANNUL) == 0))
822 as_warn ("FP branch in delay slot");
824 /* SPARC before v9 requires a nop instruction between a floating
825 point instruction and a floating point branch. We insert one
826 automatically, with a warning. */
827 if (max_architecture < SPARC_OPCODE_ARCH_V9
830 && (insn->flags & F_FBR) != 0
831 && (last_insn->flags & F_FLOAT) != 0)
833 struct sparc_it nop_insn;
835 nop_insn.opcode = NOP_INSN;
836 nop_insn.reloc = BFD_RELOC_NONE;
837 output_insn (insn, &nop_insn);
838 as_warn ("FP branch preceded by FP instruction; NOP inserted");
841 switch (special_case)
843 case SPECIAL_CASE_NONE:
845 output_insn (insn, &the_insn);
848 case SPECIAL_CASE_SET:
852 /* "set" is not defined for negative numbers in v9: it doesn't yield
853 what you expect it to. */
854 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
855 && the_insn.exp.X_op == O_constant)
857 if (the_insn.exp.X_add_number < 0)
858 as_warn ("set: used with negative number");
859 else if (the_insn.exp.X_add_number > 0xffffffff)
860 as_warn ("set: number larger than 4294967295");
863 /* See if operand is absolute and small; skip sethi if so. */
864 if (the_insn.exp.X_op != O_constant
865 || the_insn.exp.X_add_number >= (1 << 12)
866 || the_insn.exp.X_add_number < -(1 << 12))
868 output_insn (insn, &the_insn);
871 /* See if operand has no low-order bits; skip OR if so. */
872 if (the_insn.exp.X_op != O_constant
873 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
876 int rd = (the_insn.opcode & RD (~0)) >> 25;
877 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
880 | (the_insn.exp.X_add_number
881 & (need_hi22_p ? 0x3ff : 0x1fff)));
882 the_insn.reloc = (the_insn.exp.X_op != O_constant
885 output_insn (insn, &the_insn);
890 case SPECIAL_CASE_SETSW:
892 /* FIXME: Not finished. */
896 case SPECIAL_CASE_SETX:
898 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
899 int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
900 int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
902 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
903 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
904 /* Output directly to dst reg if lower 32 bits are all zero. */
905 int upper_dstreg = (the_insn.exp.X_op == O_constant
906 && lower32 == 0) ? dstreg : tmpreg;
907 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
909 /* The tmp reg should not be the dst reg. */
910 if (tmpreg == dstreg)
911 as_warn ("setx: temporary register same as destination register");
913 /* Reset X_add_number, we've extracted it as upper32/lower32.
914 Otherwise fixup_segment will complain about not being able to
915 write an 8 byte number in a 4 byte field. */
916 the_insn.exp.X_add_number = 0;
918 /* ??? Obviously there are other optimizations we can do
919 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
920 doing some of these. Later. If you do change things, try to
921 change all of this to be table driven as well. */
923 /* What to output depends on the number if it's constant.
924 Compute that first, then output what we've decided upon. */
925 if (the_insn.exp.X_op != O_constant)
926 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
929 /* Only need hh22 if `or' insn can't handle constant. */
930 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
933 /* Does bottom part (after sethi) have bits? */
934 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
935 /* No hh22, but does upper32 still have bits we can't set
939 && (upper32 != -1 || lower32 >= 0)))
942 /* If the lower half is all zero, we build the upper half directly
945 /* Need lower half if number is zero. */
946 || (! need_hh22_p && ! need_hm10_p))
948 /* No need for sethi if `or' insn can handle constant. */
949 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
950 /* Note that we can't use a negative constant in the `or'
951 insn unless the upper 32 bits are all ones. */
952 || (lower32 < 0 && upper32 != -1))
955 /* Does bottom part (after sethi) have bits? */
956 if ((need_hi22_p && (lower32 & 0x3ff) != 0)
958 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
959 /* Need `or' if we didn't set anything else. */
960 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
967 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
968 | ((upper32 >> 10) & 0x3fffff));
969 the_insn.reloc = (the_insn.exp.X_op != O_constant
970 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
971 output_insn (insn, &the_insn);
976 the_insn.opcode = (OR_INSN
977 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
981 & (need_hh22_p ? 0x3ff : 0x1fff)));
982 the_insn.reloc = (the_insn.exp.X_op != O_constant
983 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
984 output_insn (insn, &the_insn);
989 the_insn.opcode = (SETHI_INSN | RD (dstreg)
990 | ((lower32 >> 10) & 0x3fffff));
991 the_insn.reloc = BFD_RELOC_HI22;
992 output_insn (insn, &the_insn);
997 /* FIXME: One nice optimization to do here is to OR the low part
998 with the highpart if hi22 isn't needed and the low part is
1000 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1004 & (need_hi22_p ? 0x3ff : 0x1fff)));
1005 the_insn.reloc = BFD_RELOC_LO10;
1006 output_insn (insn, &the_insn);
1009 /* If we needed to build the upper part, shift it into place. */
1010 if (need_hh22_p || need_hm10_p)
1012 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1014 the_insn.reloc = BFD_RELOC_NONE;
1015 output_insn (insn, &the_insn);
1018 /* If we needed to build both upper and lower parts, OR them together. */
1019 if ((need_hh22_p || need_hm10_p)
1020 && (need_hi22_p || need_lo10_p))
1022 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1024 the_insn.reloc = BFD_RELOC_NONE;
1025 output_insn (insn, &the_insn);
1027 /* We didn't need both regs, but we may have to sign extend lower32. */
1028 else if (need_hi22_p && upper32 == -1)
1030 the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
1032 the_insn.reloc = BFD_RELOC_NONE;
1033 output_insn (insn, &the_insn);
1038 case SPECIAL_CASE_FDIV:
1040 int rd = (the_insn.opcode >> 25) & 0x1f;
1042 output_insn (insn, &the_insn);
1044 /* According to information leaked from Sun, the "fdiv" instructions
1045 on early SPARC machines would produce incorrect results sometimes.
1046 The workaround is to add an fmovs of the destination register to
1047 itself just after the instruction. This was true on machines
1048 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1049 assert (the_insn.reloc == BFD_RELOC_NONE);
1050 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1051 output_insn (insn, &the_insn);
1056 as_fatal ("failed special case insn sanity check");
1060 /* Subroutine of md_assemble to do the actual parsing. */
1063 sparc_ip (str, pinsn)
1065 const struct sparc_opcode **pinsn;
1067 char *error_message = "";
1071 const struct sparc_opcode *insn;
1073 unsigned long opcode;
1074 unsigned int mask = 0;
1079 for (s = str; islower (*s) || (*s >= '0' && *s <= '3'); ++s)
1097 as_fatal ("Unknown opcode: `%s'", str);
1099 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1103 as_bad ("Unknown opcode: `%s'", str);
1114 opcode = insn->match;
1115 memset (&the_insn, '\0', sizeof (the_insn));
1116 the_insn.reloc = BFD_RELOC_NONE;
1120 * Build the opcode, checking as we go to make
1121 * sure that the operands match
1123 for (args = insn->args;; ++args)
1131 /* Parse a series of masks. */
1138 if (! parse_keyword_arg (sparc_encode_membar, &s,
1141 error_message = ": invalid membar mask name";
1145 while (*s == ' ') { ++s; continue; }
1146 if (*s == '|' || *s == '+')
1148 while (*s == ' ') { ++s; continue; }
1153 if (! parse_const_expr_arg (&s, &kmask))
1155 error_message = ": invalid membar mask expression";
1158 if (kmask < 0 || kmask > 127)
1160 error_message = ": invalid membar mask number";
1165 opcode |= MEMBAR (kmask);
1173 /* Parse a prefetch function. */
1176 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1178 error_message = ": invalid prefetch function name";
1184 if (! parse_const_expr_arg (&s, &fcn))
1186 error_message = ": invalid prefetch function expression";
1189 if (fcn < 0 || fcn > 31)
1191 error_message = ": invalid prefetch function number";
1201 /* Parse a sparc64 privileged register. */
1204 struct priv_reg_entry *p = priv_reg_table;
1205 unsigned int len = 9999999; /* init to make gcc happy */
1208 while (p->name[0] > s[0])
1210 while (p->name[0] == s[0])
1212 len = strlen (p->name);
1213 if (strncmp (p->name, s, len) == 0)
1217 if (p->name[0] != s[0])
1219 error_message = ": unrecognizable privileged register";
1223 opcode |= (p->regnum << 14);
1225 opcode |= (p->regnum << 25);
1231 error_message = ": unrecognizable privileged register";
1237 if (strncmp (s, "%asr", 4) == 0)
1245 while (isdigit (*s))
1247 num = num * 10 + *s - '0';
1251 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1253 if (num < 16 || 31 < num)
1255 error_message = ": asr number must be between 16 and 31";
1261 if (num < 0 || 31 < num)
1263 error_message = ": asr number must be between 0 and 31";
1268 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1273 error_message = ": expecting %asrN";
1280 the_insn.reloc = BFD_RELOC_SPARC_11;
1284 the_insn.reloc = BFD_RELOC_SPARC_10;
1288 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1289 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1290 the_insn.reloc = BFD_RELOC_SPARC_5;
1292 the_insn.reloc = BFD_RELOC_SPARC13;
1293 /* These fields are unsigned, but for upward compatibility,
1294 allow negative values as well. */
1298 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1299 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1300 the_insn.reloc = BFD_RELOC_SPARC_6;
1302 the_insn.reloc = BFD_RELOC_SPARC13;
1303 /* These fields are unsigned, but for upward compatibility,
1304 allow negative values as well. */
1308 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1313 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1318 if (*s == 'p' && s[1] == 'n')
1326 if (*s == 'p' && s[1] == 't')
1338 if (strncmp (s, "%icc", 4) == 0)
1350 if (strncmp (s, "%xcc", 4) == 0)
1362 if (strncmp (s, "%fcc0", 5) == 0)
1374 if (strncmp (s, "%fcc1", 5) == 0)
1386 if (strncmp (s, "%fcc2", 5) == 0)
1398 if (strncmp (s, "%fcc3", 5) == 0)
1406 if (strncmp (s, "%pc", 3) == 0)
1414 if (strncmp (s, "%tick", 5) == 0)
1421 case '\0': /* end of args */
1440 case '[': /* these must match exactly */
1448 case '#': /* must be at least one digit */
1451 while (isdigit (*s))
1459 case 'C': /* coprocessor state register */
1460 if (strncmp (s, "%csr", 4) == 0)
1467 case 'b': /* next operand is a coprocessor register */
1470 if (*s++ == '%' && *s++ == 'c' && isdigit (*s))
1475 mask = 10 * (mask - '0') + (*s++ - '0');
1489 opcode |= mask << 14;
1497 opcode |= mask << 25;
1503 case 'r': /* next operand must be a register */
1513 case 'f': /* frame pointer */
1521 case 'g': /* global register */
1522 if (isoctal (c = *s++))
1529 case 'i': /* in register */
1530 if (isoctal (c = *s++))
1532 mask = c - '0' + 24;
1537 case 'l': /* local register */
1538 if (isoctal (c = *s++))
1540 mask = (c - '0' + 16);
1545 case 'o': /* out register */
1546 if (isoctal (c = *s++))
1548 mask = (c - '0' + 8);
1553 case 's': /* stack pointer */
1561 case 'r': /* any register */
1562 if (!isdigit (c = *s++))
1579 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1595 /* Got the register, now figure out where
1596 it goes in the opcode. */
1600 opcode |= mask << 14;
1608 opcode |= mask << 25;
1612 opcode |= (mask << 25) | (mask << 14);
1616 opcode |= (mask << 25) | (mask << 0);
1622 case 'e': /* next operand is a floating point register */
1637 && ((format = *s) == 'f')
1640 for (mask = 0; isdigit (*s); ++s)
1642 mask = 10 * mask + (*s - '0');
1643 } /* read the number */
1651 } /* register must be even numbered */
1659 } /* register must be multiple of 4 */
1663 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1664 error_message = ": There are only 64 f registers; [0-63]";
1666 error_message = ": There are only 32 f registers; [0-31]";
1669 else if (mask >= 32)
1671 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1674 mask -= 31; /* wrap high bit */
1678 error_message = ": There are only 32 f registers; [0-31]";
1686 } /* if not an 'f' register. */
1693 opcode |= RS1 (mask);
1700 opcode |= RS2 (mask);
1706 opcode |= RD (mask);
1715 if (strncmp (s, "%fsr", 4) == 0)
1722 case '0': /* 64 bit immediate (setx insn) */
1723 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
1726 case 'h': /* high 22 bits */
1727 the_insn.reloc = BFD_RELOC_HI22;
1730 case 'l': /* 22 bit PC relative immediate */
1731 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
1735 case 'L': /* 30 bit immediate */
1736 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
1740 case 'n': /* 22 bit immediate */
1741 the_insn.reloc = BFD_RELOC_SPARC22;
1744 case 'i': /* 13 bit immediate */
1745 the_insn.reloc = BFD_RELOC_SPARC13;
1753 /* Check for %hi, etc. */
1757 /* The name as it appears in assembler. */
1759 /* strlen (name), precomputed for speed */
1761 /* The reloc this pseudo-op translates to. */
1763 /* Non-zero if for v9 only. */
1765 /* Non-zero if can be used in pc-relative contexts. */
1766 int pcrel_p;/*FIXME:wip*/
1768 /* hix/lox must appear before hi/lo so %hix won't be
1769 mistaken for %hi. */
1770 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
1771 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
1772 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
1773 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
1774 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
1775 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
1776 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
1777 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
1778 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
1779 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
1780 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
1781 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
1786 for (o = ops; o->name; o++)
1787 if (strncmp (s + 1, o->name, o->len) == 0)
1789 if (o->name == NULL)
1792 the_insn.reloc = o->reloc;
1797 /* Note that if the get_expression() fails, we will still
1798 have created U entries in the symbol table for the
1799 'symbols' in the input string. Try not to create U
1800 symbols for registers, etc. */
1802 /* This stuff checks to see if the expression ends in
1803 +%reg. If it does, it removes the register from
1804 the expression, and re-sets 's' to point to the
1809 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
1811 if (s1 != s && isdigit (s1[-1]))
1813 if (s1[-2] == '%' && s1[-3] == '+')
1817 (void) get_expression (s);
1822 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
1826 (void) get_expression (s);
1833 (void) get_expression (s);
1836 /* Check for constants that don't require emitting a reloc. */
1837 if (the_insn.exp.X_op == O_constant
1838 && the_insn.exp.X_add_symbol == 0
1839 && the_insn.exp.X_op_symbol == 0)
1841 /* For pc-relative call instructions, we reject
1842 constants to get better code. */
1844 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
1845 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
1847 error_message = ": PC-relative operand can't be a constant";
1851 /* Constants that won't fit are checked in md_apply_fix3
1852 and bfd_install_relocation.
1853 ??? It would be preferable to install the constants
1854 into the insn here and save having to create a fixS
1855 for each one. There already exists code to handle
1856 all the various cases (e.g. in md_apply_fix3 and
1857 bfd_install_relocation) so duplicating all that code
1858 here isn't right. */
1878 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
1880 error_message = ": invalid ASI name";
1886 if (! parse_const_expr_arg (&s, &asi))
1888 error_message = ": invalid ASI expression";
1891 if (asi < 0 || asi > 255)
1893 error_message = ": invalid ASI number";
1897 opcode |= ASI (asi);
1899 } /* alternate space */
1902 if (strncmp (s, "%psr", 4) == 0)
1909 case 'q': /* floating point queue */
1910 if (strncmp (s, "%fq", 3) == 0)
1917 case 'Q': /* coprocessor queue */
1918 if (strncmp (s, "%cq", 3) == 0)
1926 if (strcmp (str, "set") == 0
1927 || strcmp (str, "setuw") == 0)
1929 special_case = SPECIAL_CASE_SET;
1932 else if (strcmp (str, "setsw") == 0)
1934 special_case = SPECIAL_CASE_SETSW;
1937 else if (strcmp (str, "setx") == 0)
1939 special_case = SPECIAL_CASE_SETX;
1942 else if (strncmp (str, "fdiv", 4) == 0)
1944 special_case = SPECIAL_CASE_FDIV;
1950 if (strncmp (s, "%asi", 4) != 0)
1956 if (strncmp (s, "%fprs", 5) != 0)
1962 if (strncmp (s, "%ccr", 4) != 0)
1968 if (strncmp (s, "%tbr", 4) != 0)
1974 if (strncmp (s, "%wim", 4) != 0)
1981 char *push = input_line_pointer;
1984 input_line_pointer = s;
1986 if (e.X_op == O_constant)
1988 int n = e.X_add_number;
1989 if (n != e.X_add_number || (n & ~0x1ff) != 0)
1990 as_bad ("OPF immediate operand out of range (0-0x1ff)");
1992 opcode |= e.X_add_number << 5;
1995 as_bad ("non-immediate OPF operand, ignored");
1996 s = input_line_pointer;
1997 input_line_pointer = push;
2002 if (strncmp (s, "%y", 2) != 0)
2010 /* Parse a sparclet cpreg. */
2012 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2014 error_message = ": invalid cpreg name";
2017 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2022 as_fatal ("failed sanity check.");
2023 } /* switch on arg code */
2025 /* Break out of for() loop. */
2027 } /* for each arg that we expect */
2032 /* Args don't match. */
2033 if (((unsigned) (&insn[1] - sparc_opcodes)) < sparc_num_opcodes
2034 && (insn->name == insn[1].name
2035 || !strcmp (insn->name, insn[1].name)))
2043 as_bad ("Illegal operands%s", error_message);
2049 /* We have a match. Now see if the architecture is ok. */
2050 int needed_arch_mask = insn->architecture;
2054 needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
2055 | (1 << SPARC_OPCODE_ARCH_V9A));
2056 needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
2059 if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
2061 /* Can we bump up the architecture? */
2062 else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
2064 enum sparc_opcode_arch_val needed_architecture =
2065 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2066 & needed_arch_mask);
2068 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2070 && needed_architecture > warn_after_architecture)
2072 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2073 sparc_opcode_archs[current_architecture].name,
2074 sparc_opcode_archs[needed_architecture].name,
2076 warn_after_architecture = needed_architecture;
2078 current_architecture = needed_architecture;
2081 /* ??? This seems to be a bit fragile. What if the next entry in
2082 the opcode table is the one we want and it is supported?
2083 It is possible to arrange the table today so that this can't
2084 happen but what about tomorrow? */
2087 int arch,printed_one_p = 0;
2089 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2091 /* Create a list of the architectures that support the insn. */
2092 needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
2094 arch = sparc_ffs (needed_arch_mask);
2095 while ((1 << arch) <= needed_arch_mask)
2097 if ((1 << arch) & needed_arch_mask)
2101 strcpy (p, sparc_opcode_archs[arch].name);
2108 as_bad ("Architecture mismatch on \"%s\".", str);
2109 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2111 sparc_opcode_archs[max_architecture].name);
2117 } /* forever looking for a match */
2119 the_insn.opcode = opcode;
2122 /* Parse an argument that can be expressed as a keyword.
2123 (eg: #StoreStore or %ccfr).
2124 The result is a boolean indicating success.
2125 If successful, INPUT_POINTER is updated. */
2128 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2129 int (*lookup_fn) PARAMS ((const char *));
2130 char **input_pointerP;
2136 p = *input_pointerP;
2137 for (q = p + (*p == '#' || *p == '%'); isalnum (*q) || *q == '_'; ++q)
2141 value = (*lookup_fn) (p);
2146 *input_pointerP = q;
2150 /* Parse an argument that is a constant expression.
2151 The result is a boolean indicating success. */
2154 parse_const_expr_arg (input_pointerP, valueP)
2155 char **input_pointerP;
2158 char *save = input_line_pointer;
2161 input_line_pointer = *input_pointerP;
2162 /* The next expression may be something other than a constant
2163 (say if we're not processing the right variant of the insn).
2164 Don't call expression unless we're sure it will succeed as it will
2165 signal an error (which we want to defer until later). */
2166 /* FIXME: It might be better to define md_operand and have it recognize
2167 things like %asi, etc. but continuing that route through to the end
2168 is a lot of work. */
2169 if (*input_line_pointer == '%')
2171 input_line_pointer = save;
2175 *input_pointerP = input_line_pointer;
2176 input_line_pointer = save;
2177 if (exp.X_op != O_constant)
2179 *valueP = exp.X_add_number;
2183 /* Subroutine of sparc_ip to parse an expression. */
2186 get_expression (str)
2192 save_in = input_line_pointer;
2193 input_line_pointer = str;
2194 seg = expression (&the_insn.exp);
2195 if (seg != absolute_section
2196 && seg != text_section
2197 && seg != data_section
2198 && seg != bss_section
2199 && seg != undefined_section)
2201 the_insn.error = "bad segment";
2202 expr_end = input_line_pointer;
2203 input_line_pointer = save_in;
2206 expr_end = input_line_pointer;
2207 input_line_pointer = save_in;
2211 /* Subroutine of md_assemble to output one insn. */
2214 output_insn (insn, the_insn)
2215 const struct sparc_opcode *insn;
2216 struct sparc_it *the_insn;
2218 char *toP = frag_more (4);
2220 /* put out the opcode */
2221 if (INSN_BIG_ENDIAN)
2222 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2224 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2226 /* put out the symbol-dependent stuff */
2227 if (the_insn->reloc != BFD_RELOC_NONE)
2229 fixS *fixP = fix_new_exp (frag_now, /* which frag */
2230 (toP - frag_now->fr_literal), /* where */
2235 /* Turn off overflow checking in fixup_segment. We'll do our
2236 own overflow checking in md_apply_fix3. This is necessary because
2237 the insn size is 4 and fixup_segment will signal an overflow for
2238 large 8 byte quantities. */
2239 fixP->fx_no_overflow = 1;
2243 last_opcode = the_insn->opcode;
2247 This is identical to the md_atof in m68k.c. I think this is right,
2250 Turn a string in input_line_pointer into a floating point constant of type
2251 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2252 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2255 /* Equal to MAX_PRECISION in atof-ieee.c */
2256 #define MAX_LITTLENUMS 6
2259 md_atof (type, litP, sizeP)
2265 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2296 return "Bad call to MD_ATOF()";
2299 t = atof_ieee (input_line_pointer, type, words);
2301 input_line_pointer = t;
2302 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2304 if (target_big_endian)
2306 for (i = 0; i < prec; i++)
2308 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2309 litP += sizeof (LITTLENUM_TYPE);
2314 for (i = prec - 1; i >= 0; i--)
2316 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
2317 litP += sizeof (LITTLENUM_TYPE);
2324 /* Write a value out to the object file, using the appropriate
2328 md_number_to_chars (buf, val, n)
2333 if (target_big_endian)
2334 number_to_chars_bigendian (buf, val, n);
2336 number_to_chars_littleendian (buf, val, n);
2339 /* Apply a fixS to the frags, now that we know the value it ought to
2343 md_apply_fix3 (fixP, value, segment)
2348 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2354 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2356 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
2359 /* FIXME: SPARC ELF relocations don't use an addend in the data
2360 field itself. This whole approach should be somehow combined
2361 with the calls to bfd_install_relocation. Also, the value passed
2362 in by fixup_segment includes the value of a defined symbol. We
2363 don't want to include the value of an externally visible symbol. */
2364 if (fixP->fx_addsy != NULL)
2366 if (fixP->fx_addsy->sy_used_in_reloc
2367 && (S_IS_EXTERNAL (fixP->fx_addsy)
2368 || S_IS_WEAK (fixP->fx_addsy)
2369 || (sparc_pic_code && ! fixP->fx_pcrel)
2370 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2371 && ((bfd_get_section_flags (stdoutput,
2372 S_GET_SEGMENT (fixP->fx_addsy))
2373 & SEC_LINK_ONCE) != 0
2374 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2376 sizeof ".gnu.linkonce" - 1) == 0)))
2377 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2378 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2379 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2380 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2385 /* This is a hack. There should be a better way to
2386 handle this. Probably in terms of howto fields, once
2387 we can look at these fixups in terms of howtos. */
2388 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2389 val += fixP->fx_where + fixP->fx_frag->fr_address;
2392 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2393 generate a reloc, then we just want to let the reloc addend set
2394 the value. We do not want to also stuff the addend into the
2395 object file. Including the addend in the object file works when
2396 doing a static link, because the linker will ignore the object
2397 file contents. However, the dynamic linker does not ignore the
2398 object file contents. */
2399 if (fixP->fx_addsy != NULL
2400 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2403 /* When generating PIC code, we do not want an addend for a reloc
2404 against a local symbol. We adjust fx_addnumber to cancel out the
2405 value already included in val, and to also cancel out the
2406 adjustment which bfd_install_relocation will create. */
2408 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2409 && fixP->fx_addsy != NULL
2410 && ! S_IS_COMMON (fixP->fx_addsy)
2411 && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
2412 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2415 /* If this is a data relocation, just output VAL. */
2417 if (fixP->fx_r_type == BFD_RELOC_16)
2419 md_number_to_chars (buf, val, 2);
2421 else if (fixP->fx_r_type == BFD_RELOC_32)
2423 md_number_to_chars (buf, val, 4);
2425 else if (fixP->fx_r_type == BFD_RELOC_64)
2427 md_number_to_chars (buf, val, 8);
2431 /* It's a relocation against an instruction. */
2433 if (INSN_BIG_ENDIAN)
2434 insn = bfd_getb32 ((unsigned char *) buf);
2436 insn = bfd_getl32 ((unsigned char *) buf);
2438 switch (fixP->fx_r_type)
2440 case BFD_RELOC_32_PCREL_S2:
2442 /* FIXME: This increment-by-one deserves a comment of why it's
2444 if (! sparc_pic_code
2445 || fixP->fx_addsy == NULL
2446 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2448 insn |= val & 0x3fffffff;
2451 case BFD_RELOC_SPARC_11:
2452 if (! in_signed_range (val, 0x7ff))
2453 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2454 insn |= val & 0x7ff;
2457 case BFD_RELOC_SPARC_10:
2458 if (! in_signed_range (val, 0x3ff))
2459 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2460 insn |= val & 0x3ff;
2463 case BFD_RELOC_SPARC_7:
2464 if (! in_bitfield_range (val, 0x7f))
2465 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2469 case BFD_RELOC_SPARC_6:
2470 if (! in_bitfield_range (val, 0x3f))
2471 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2475 case BFD_RELOC_SPARC_5:
2476 if (! in_bitfield_range (val, 0x1f))
2477 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2481 case BFD_RELOC_SPARC_WDISP16:
2482 /* FIXME: simplify */
2483 if (((val > 0) && (val & ~0x3fffc))
2484 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
2485 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2486 /* FIXME: The +1 deserves a comment. */
2487 val = (val >> 2) + 1;
2488 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
2491 case BFD_RELOC_SPARC_WDISP19:
2492 /* FIXME: simplify */
2493 if (((val > 0) && (val & ~0x1ffffc))
2494 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
2495 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2496 /* FIXME: The +1 deserves a comment. */
2497 val = (val >> 2) + 1;
2498 insn |= val & 0x7ffff;
2501 case BFD_RELOC_SPARC_HH22:
2502 val = BSR (val, 32);
2503 /* intentional fallthrough */
2505 case BFD_RELOC_SPARC_LM22:
2506 case BFD_RELOC_HI22:
2507 if (!fixP->fx_addsy)
2509 insn |= (val >> 10) & 0x3fffff;
2513 /* FIXME: Need comment explaining why we do this. */
2518 case BFD_RELOC_SPARC22:
2519 if (val & ~0x003fffff)
2520 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2521 insn |= (val & 0x3fffff);
2524 case BFD_RELOC_SPARC_HM10:
2525 val = BSR (val, 32);
2526 /* intentional fallthrough */
2528 case BFD_RELOC_LO10:
2529 if (!fixP->fx_addsy)
2531 insn |= val & 0x3ff;
2535 /* FIXME: Need comment explaining why we do this. */
2540 case BFD_RELOC_SPARC13:
2541 if (! in_signed_range (val, 0x1fff))
2542 as_bad_where (fixP->fx_file, fixP->fx_line, "relocation overflow");
2543 insn |= val & 0x1fff;
2546 case BFD_RELOC_SPARC_WDISP22:
2547 val = (val >> 2) + 1;
2549 case BFD_RELOC_SPARC_BASE22:
2550 insn |= val & 0x3fffff;
2553 case BFD_RELOC_SPARC_H44:
2554 if (!fixP->fx_addsy)
2558 insn |= tval & 0x3fffff;
2562 case BFD_RELOC_SPARC_M44:
2563 if (!fixP->fx_addsy)
2564 insn |= (val >> 12) & 0x3ff;
2567 case BFD_RELOC_SPARC_L44:
2568 if (!fixP->fx_addsy)
2569 insn |= val & 0xfff;
2572 case BFD_RELOC_SPARC_HIX22:
2573 if (!fixP->fx_addsy)
2575 val ^= ~ (offsetT) 0;
2576 insn |= (val >> 10) & 0x3fffff;
2580 case BFD_RELOC_SPARC_LOX10:
2581 if (!fixP->fx_addsy)
2582 insn |= 0x1c00 | (val & 0x3ff);
2585 case BFD_RELOC_NONE:
2587 as_bad_where (fixP->fx_file, fixP->fx_line,
2588 "bad or unhandled relocation type: 0x%02x",
2593 if (INSN_BIG_ENDIAN)
2594 bfd_putb32 (insn, (unsigned char *) buf);
2596 bfd_putl32 (insn, (unsigned char *) buf);
2599 /* Are we finished with this relocation now? */
2600 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
2606 /* Translate internal representation of relocation info to BFD target
2609 tc_gen_reloc (section, fixp)
2614 bfd_reloc_code_real_type code;
2616 reloc = (arelent *) xmalloc (sizeof (arelent));
2618 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
2619 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2621 switch (fixp->fx_r_type)
2625 case BFD_RELOC_HI22:
2626 case BFD_RELOC_LO10:
2627 case BFD_RELOC_32_PCREL_S2:
2628 case BFD_RELOC_SPARC13:
2629 case BFD_RELOC_SPARC_BASE13:
2630 case BFD_RELOC_SPARC_WDISP16:
2631 case BFD_RELOC_SPARC_WDISP19:
2632 case BFD_RELOC_SPARC_WDISP22:
2634 case BFD_RELOC_SPARC_5:
2635 case BFD_RELOC_SPARC_6:
2636 case BFD_RELOC_SPARC_7:
2637 case BFD_RELOC_SPARC_10:
2638 case BFD_RELOC_SPARC_11:
2639 case BFD_RELOC_SPARC_HH22:
2640 case BFD_RELOC_SPARC_HM10:
2641 case BFD_RELOC_SPARC_LM22:
2642 case BFD_RELOC_SPARC_PC_HH22:
2643 case BFD_RELOC_SPARC_PC_HM10:
2644 case BFD_RELOC_SPARC_PC_LM22:
2645 case BFD_RELOC_SPARC_H44:
2646 case BFD_RELOC_SPARC_M44:
2647 case BFD_RELOC_SPARC_L44:
2648 case BFD_RELOC_SPARC_HIX22:
2649 case BFD_RELOC_SPARC_LOX10:
2650 code = fixp->fx_r_type;
2656 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2657 /* If we are generating PIC code, we need to generate a different
2661 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2663 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2670 case BFD_RELOC_32_PCREL_S2:
2671 if (! S_IS_DEFINED (fixp->fx_addsy)
2672 || S_IS_COMMON (fixp->fx_addsy)
2673 || S_IS_EXTERNAL (fixp->fx_addsy)
2674 || S_IS_WEAK (fixp->fx_addsy))
2675 code = BFD_RELOC_SPARC_WPLT30;
2677 case BFD_RELOC_HI22:
2678 if (fixp->fx_addsy != NULL
2679 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2680 code = BFD_RELOC_SPARC_PC22;
2682 code = BFD_RELOC_SPARC_GOT22;
2684 case BFD_RELOC_LO10:
2685 if (fixp->fx_addsy != NULL
2686 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
2687 code = BFD_RELOC_SPARC_PC10;
2689 code = BFD_RELOC_SPARC_GOT10;
2691 case BFD_RELOC_SPARC13:
2692 code = BFD_RELOC_SPARC_GOT13;
2698 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2700 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2701 if (reloc->howto == 0)
2703 as_bad_where (fixp->fx_file, fixp->fx_line,
2704 "internal error: can't export reloc type %d (`%s')",
2705 fixp->fx_r_type, bfd_get_reloc_code_name (code));
2709 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2712 if (reloc->howto->pc_relative == 0
2713 || code == BFD_RELOC_SPARC_PC10
2714 || code == BFD_RELOC_SPARC_PC22)
2715 reloc->addend = fixp->fx_addnumber;
2717 reloc->addend = fixp->fx_offset - reloc->address;
2719 #else /* elf or coff */
2721 if (reloc->howto->pc_relative == 0
2722 || code == BFD_RELOC_SPARC_PC10
2723 || code == BFD_RELOC_SPARC_PC22)
2724 reloc->addend = fixp->fx_addnumber;
2725 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2726 reloc->addend = (section->vma
2727 + fixp->fx_addnumber
2728 + md_pcrel_from (fixp));
2730 reloc->addend = fixp->fx_offset;
2736 /* We have no need to default values of symbols. */
2740 md_undefined_symbol (name)
2744 } /* md_undefined_symbol() */
2746 /* Round up a section size to the appropriate boundary. */
2748 md_section_align (segment, size)
2753 /* This is not right for ELF; a.out wants it, and COFF will force
2754 the alignment anyways. */
2755 valueT align = ((valueT) 1
2756 << (valueT) bfd_get_section_alignment (stdoutput, segment));
2758 /* turn alignment value into a mask */
2760 newsize = (size + align) & ~align;
2767 /* Exactly what point is a PC-relative offset relative TO?
2768 On the sparc, they're relative to the address of the offset, plus
2769 its size. This gets us to the following instruction.
2770 (??? Is this right? FIXME-SOON) */
2772 md_pcrel_from (fixP)
2777 ret = fixP->fx_where + fixP->fx_frag->fr_address;
2778 if (! sparc_pic_code
2779 || fixP->fx_addsy == NULL
2780 || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
2781 ret += fixP->fx_size;
2786 * sort of like s_lcomm
2790 static int max_alignment = 15;
2805 name = input_line_pointer;
2806 c = get_symbol_end ();
2807 p = input_line_pointer;
2811 if (*input_line_pointer != ',')
2813 as_bad ("Expected comma after name");
2814 ignore_rest_of_line ();
2818 ++input_line_pointer;
2820 if ((size = get_absolute_expression ()) < 0)
2822 as_bad ("BSS length (%d.) <0! Ignored.", size);
2823 ignore_rest_of_line ();
2828 symbolP = symbol_find_or_make (name);
2831 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
2832 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
2834 as_bad ("bad .reserve segment -- expected BSS segment");
2838 if (input_line_pointer[2] == '.')
2839 input_line_pointer += 7;
2841 input_line_pointer += 6;
2844 if (*input_line_pointer == ',')
2846 ++input_line_pointer;
2849 if (*input_line_pointer == '\n')
2851 as_bad ("Missing alignment");
2855 align = get_absolute_expression ();
2857 if (align > max_alignment)
2859 align = max_alignment;
2860 as_warn ("Alignment too large: %d. assumed.", align);
2866 as_warn ("Alignment negative. 0 assumed.");
2869 record_alignment (bss_section, align);
2871 /* convert to a power of 2 alignment */
2872 for (temp = 0; (align & 1) == 0; align >>= 1, ++temp);;
2876 as_bad ("Alignment not a power of 2");
2877 ignore_rest_of_line ();
2879 } /* not a power of two */
2882 } /* if has optional alignment */
2886 if (!S_IS_DEFINED (symbolP)
2888 && S_GET_OTHER (symbolP) == 0
2889 && S_GET_DESC (symbolP) == 0
2896 segT current_seg = now_seg;
2897 subsegT current_subseg = now_subseg;
2899 subseg_set (bss_section, 1); /* switch to bss */
2902 frag_align (align, 0, 0); /* do alignment */
2904 /* detach from old frag */
2905 if (S_GET_SEGMENT(symbolP) == bss_section)
2906 symbolP->sy_frag->fr_symbol = NULL;
2908 symbolP->sy_frag = frag_now;
2909 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
2910 (offsetT) size, (char *)0);
2913 S_SET_SEGMENT (symbolP, bss_section);
2915 subseg_set (current_seg, current_subseg);
2920 as_warn("Ignoring attempt to re-define symbol %s",
2921 S_GET_NAME (symbolP));
2922 } /* if not redefining */
2924 demand_empty_rest_of_line ();
2937 name = input_line_pointer;
2938 c = get_symbol_end ();
2939 /* just after name is now '\0' */
2940 p = input_line_pointer;
2943 if (*input_line_pointer != ',')
2945 as_bad ("Expected comma after symbol-name");
2946 ignore_rest_of_line ();
2949 input_line_pointer++; /* skip ',' */
2950 if ((temp = get_absolute_expression ()) < 0)
2952 as_bad (".COMMon length (%d.) <0! Ignored.", temp);
2953 ignore_rest_of_line ();
2958 symbolP = symbol_find_or_make (name);
2960 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
2962 as_bad ("Ignoring attempt to re-define symbol");
2963 ignore_rest_of_line ();
2966 if (S_GET_VALUE (symbolP) != 0)
2968 if (S_GET_VALUE (symbolP) != size)
2970 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
2971 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
2977 S_SET_VALUE (symbolP, (valueT) size);
2978 S_SET_EXTERNAL (symbolP);
2981 know (symbolP->sy_frag == &zero_address_frag);
2982 if (*input_line_pointer != ',')
2984 as_bad ("Expected comma after common length");
2985 ignore_rest_of_line ();
2988 input_line_pointer++;
2990 if (*input_line_pointer != '"')
2992 temp = get_absolute_expression ();
2994 if (temp > max_alignment)
2996 temp = max_alignment;
2997 as_warn ("Common alignment too large: %d. assumed", temp);
3003 as_warn ("Common alignment negative; 0 assumed");
3014 old_subsec = now_subseg;
3016 record_alignment (bss_section, align);
3017 subseg_set (bss_section, 0);
3019 frag_align (align, 0, 0);
3020 if (S_GET_SEGMENT (symbolP) == bss_section)
3021 symbolP->sy_frag->fr_symbol = 0;
3022 symbolP->sy_frag = frag_now;
3023 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3024 (offsetT) size, (char *) 0);
3026 S_SET_SEGMENT (symbolP, bss_section);
3027 S_CLEAR_EXTERNAL (symbolP);
3028 subseg_set (old_sec, old_subsec);
3034 S_SET_VALUE (symbolP, (valueT) size);
3036 S_SET_ALIGN (symbolP, temp);
3038 S_SET_EXTERNAL (symbolP);
3039 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3044 input_line_pointer++;
3045 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3046 if (*input_line_pointer == '.')
3047 input_line_pointer++;
3048 /* @@ Some say data, some say bss. */
3049 if (strncmp (input_line_pointer, "bss\"", 4)
3050 && strncmp (input_line_pointer, "data\"", 5))
3052 while (*--input_line_pointer != '"')
3054 input_line_pointer--;
3055 goto bad_common_segment;
3057 while (*input_line_pointer++ != '"')
3059 goto allocate_common;
3062 #ifdef BFD_ASSEMBLER
3063 symbolP->bsym->flags |= BSF_OBJECT;
3066 demand_empty_rest_of_line ();
3071 p = input_line_pointer;
3072 while (*p && *p != '\n')
3076 as_bad ("bad .common segment %s", input_line_pointer + 1);
3078 input_line_pointer = p;
3079 ignore_rest_of_line ();
3084 /* Handle the .empty pseudo-op. This supresses the warnings about
3085 invalid delay slot usage. */
3091 /* The easy way to implement is to just forget about the last
3101 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3103 input_line_pointer += 6;
3107 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3109 input_line_pointer += 6;
3113 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3115 input_line_pointer += 7;
3119 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3121 input_line_pointer += 5;
3122 /* We only support 2 segments -- text and data -- for now, so
3123 things in the "bss segment" will have to go into data for now.
3124 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3125 subseg_set (data_section, 255); /* FIXME-SOMEDAY */
3128 as_bad ("Unknown segment type");
3129 demand_empty_rest_of_line ();
3135 subseg_set (data_section, 1);
3136 demand_empty_rest_of_line ();
3143 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3145 ++input_line_pointer;
3147 ++input_line_pointer;
3150 /* This static variable is set by s_uacons to tell sparc_cons_align
3151 that the expession does not need to be aligned. */
3153 static int sparc_no_align_cons = 0;
3155 /* This handles the unaligned space allocation pseudo-ops, such as
3156 .uaword. .uaword is just like .word, but the value does not need
3163 /* Tell sparc_cons_align not to align this value. */
3164 sparc_no_align_cons = 1;
3168 /* If the --enforce-aligned-data option is used, we require .word,
3169 et. al., to be aligned correctly. We do it by setting up an
3170 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3171 no unexpected alignment was introduced.
3173 The SunOS and Solaris native assemblers enforce aligned data by
3174 default. We don't want to do that, because gcc can deliberately
3175 generate misaligned data if the packed attribute is used. Instead,
3176 we permit misaligned data by default, and permit the user to set an
3177 option to check for it. */
3180 sparc_cons_align (nbytes)
3186 /* Only do this if we are enforcing aligned data. */
3187 if (! enforce_aligned_data)
3190 if (sparc_no_align_cons)
3192 /* This is an unaligned pseudo-op. */
3193 sparc_no_align_cons = 0;
3198 while ((nbytes & 1) == 0)
3207 if (now_seg == absolute_section)
3209 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
3210 as_bad ("misaligned data");
3214 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
3215 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
3217 record_alignment (now_seg, nalign);
3220 /* This is where we do the unexpected alignment check.
3221 This is called from HANDLE_ALIGN in tc-sparc.h. */
3224 sparc_handle_align (fragp)
3227 if (fragp->fr_type == rs_align_code
3228 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
3229 as_bad_where (fragp->fr_file, fragp->fr_line, "misaligned data");