1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode **);
39 static int parse_sparc_asi (char **, const sparc_asi **);
40 static int parse_keyword_arg (int (*) (const char *), char **, int *);
41 static int parse_const_expr_arg (char **, int *);
42 static int get_expression (char *);
44 /* Default architecture. */
45 /* ??? The default value should be V8, but sparclite support was added
46 by making it the default. GCC now passes -Asparclite, so maybe sometime in
47 the future we can set this to V8. */
49 #define DEFAULT_ARCH "sparclite"
51 static const char *default_arch = DEFAULT_ARCH;
53 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 static int default_init_p;
57 /* Current architecture. We don't bump up unless necessary. */
58 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
60 /* The maximum architecture level we can bump up to.
61 In a 32 bit environment, don't allow bumping up to v9 by default.
62 The native assembler works this way. The user is required to pass
63 an explicit argument before we'll create v9 object files. However, if
64 we don't see any v9 insns, a v8plus object file is not created. */
65 static enum sparc_opcode_arch_val max_architecture;
67 /* Either 32 or 64, selects file format. */
68 static int sparc_arch_size;
69 /* Initial (default) value, recorded separately in case a user option
70 changes the value before md_show_usage is called. */
71 static int default_arch_size;
74 /* The currently selected v9 memory model. Currently only used for
76 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
79 /* Bitmask of instruction types seen so far, used to populate the
80 GNU attributes section with hwcap information. */
81 static bfd_uint64_t hwcap_seen;
85 static bfd_uint64_t hwcap_allowed;
87 static int architecture_requested;
88 static int warn_on_bump;
90 /* If warn_on_bump and the needed architecture is higher than this
91 architecture, issue a warning. */
92 static enum sparc_opcode_arch_val warn_after_architecture;
94 /* Non-zero if the assembler should generate error if an undeclared
95 g[23] register has been used in -64. */
96 static int no_undeclared_regs;
98 /* Non-zero if the assembler should generate a warning if an
99 unpredictable DCTI (delayed control transfer instruction) couple is
101 static int dcti_couples_detect;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax;
106 /* Non-zero if we are generating PIC code. */
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data;
112 extern int target_big_endian;
114 static int target_little_endian_data;
116 /* Symbols for global registers on v9. */
117 static symbolS *globals[8];
119 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
120 int sparc_cie_data_alignment;
122 /* V9 and 86x have big and little endian data, but instructions are always big
123 endian. The sparclet has bi-endian support but both data and insns have
124 the same endianness. Global `target_big_endian' is used for data.
125 The following macro is used for instructions. */
126 #ifndef INSN_BIG_ENDIAN
127 #define INSN_BIG_ENDIAN (target_big_endian \
128 || default_arch_type == sparc86x \
129 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
132 /* Handle of the OPCODE hash table. */
133 static struct hash_control *op_hash;
135 static void s_data1 (void);
136 static void s_seg (int);
137 static void s_proc (int);
138 static void s_reserve (int);
139 static void s_common (int);
140 static void s_empty (int);
141 static void s_uacons (int);
142 static void s_ncons (int);
144 static void s_register (int);
147 const pseudo_typeS md_pseudo_table[] =
149 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common, 0},
151 {"empty", s_empty, 0},
152 {"global", s_globl, 0},
154 {"nword", s_ncons, 0},
155 {"optim", s_ignore, 0},
157 {"reserve", s_reserve, 0},
159 {"skip", s_space, 0},
162 {"uahalf", s_uacons, 2},
163 {"uaword", s_uacons, 4},
164 {"uaxword", s_uacons, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons, 2},
168 {"4byte", s_uacons, 4},
169 {"8byte", s_uacons, 8},
170 {"register", s_register, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode;
211 struct nlist *nlistp;
215 bfd_reloc_code_real_type reloc;
218 struct sparc_it the_insn, set_insn;
220 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
222 /* Table of arguments to -A.
223 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
224 for this use. That table is for opcodes only. This table is for opcodes
227 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
228 v8plusa, v9, v9a, v9b, v9_64};
230 static struct sparc_arch {
232 const char *opcode_arch;
233 enum sparc_arch_types arch_type;
234 /* Default word size, as specified during configuration.
235 A value of zero means can't be used to specify default architecture. */
236 int default_arch_size;
237 /* Allowable arg to -A? */
239 /* Extra hardware capabilities allowed. These are added to the
240 hardware capabilities associated with the opcode
244 } sparc_arch_table[] = {
245 { "v6", "v6", v6, 0, 1, 0, 0 },
246 { "v7", "v7", v7, 0, 1, 0, 0 },
247 { "v8", "v8", v8, 32, 1, 0, 0 },
248 { "v8a", "v8", v8, 32, 1, 0, 0 },
249 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 },
250 { "sparcvis", "v9a", v9, 0, 1, 0, 0 },
251 { "sparcvis2", "v9b", v9, 0, 1, 0, 0 },
252 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 },
253 { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 },
254 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
255 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
257 { "sparc4", "v9v", v9, 0, 1, 0, 0 },
258 { "sparc5", "v9m", v9, 0, 1, 0, 0 },
259 { "sparc6", "m8", v9, 0, 1, 0, 0 },
261 { "leon", "leon", leon, 32, 1, 0, 0 },
262 { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 },
263 { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 },
264 { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 },
266 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 },
267 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 },
268 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 },
269 { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 },
270 { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 },
271 { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 },
272 { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 },
273 { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 },
274 { "v8plusm8", "m8", v9, 0, 1, HWCAP_V8PLUS, 0 },
276 { "v9", "v9", v9, 0, 1, 0, 0 },
277 { "v9a", "v9a", v9, 0, 1, 0, 0 },
278 { "v9b", "v9b", v9, 0, 1, 0, 0 },
279 { "v9c", "v9c", v9, 0, 1, 0, 0 },
280 { "v9d", "v9d", v9, 0, 1, 0, 0 },
281 { "v9e", "v9e", v9, 0, 1, 0, 0 },
282 { "v9v", "v9v", v9, 0, 1, 0, 0 },
283 { "v9m", "v9m", v9, 0, 1, 0, 0 },
284 { "v9m8", "m8", v9, 0, 1, 0, 0 },
286 /* This exists to allow configure.tgt to pass one
287 value to specify both the default machine and default word size. */
288 { "v9-64", "v9", v9, 64, 0, 0, 0 },
289 { NULL, NULL, v8, 0, 0, 0, 0 }
292 /* Variant of default_arch */
293 static enum sparc_arch_types default_arch_type;
295 static struct sparc_arch *
296 lookup_arch (const char *name)
298 struct sparc_arch *sa;
300 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
301 if (strcmp (sa->name, name) == 0)
303 if (sa->name == NULL)
308 /* Initialize the default opcode arch and word size from the default
309 architecture name. */
312 init_default_arch (void)
314 struct sparc_arch *sa = lookup_arch (default_arch);
317 || sa->default_arch_size == 0)
318 as_fatal (_("Invalid default architecture, broken assembler."));
320 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
321 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
322 as_fatal (_("Bad opcode table, broken assembler."));
323 default_arch_size = sparc_arch_size = sa->default_arch_size;
325 default_arch_type = sa->arch_type;
328 /* Called by TARGET_FORMAT. */
331 sparc_target_format (void)
333 /* We don't get a chance to initialize anything before we're called,
334 so handle that now. */
335 if (! default_init_p)
336 init_default_arch ();
340 return "a.out-sparc-netbsd";
343 if (target_big_endian)
344 return "a.out-sunos-big";
345 else if (default_arch_type == sparc86x && target_little_endian_data)
346 return "a.out-sunos-big";
348 return "a.out-sparc-little";
350 return "a.out-sunos-big";
361 return "coff-sparc-lynx";
368 return "elf32-sparc-vxworks";
372 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
379 * Invocation line includes a switch not recognized by the base assembler.
380 * See if it's a processor-specific option. These are:
383 * Warn on architecture bumps. See also -A.
385 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
386 * Standard 32 bit architectures.
388 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
389 * This used to only mean 64 bits, but properly specifying it
390 * complicated gcc's ASM_SPECs, so now opcode selection is
391 * specified orthogonally to word size (except when specifying
392 * the default, but that is an internal implementation detail).
393 * -Av8plus, -Av8plusa, -Av8plusb
394 * Same as -Av9{,a,b}.
395 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
396 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
398 * -xarch=v9, -xarch=v9a, -xarch=v9b
399 * Same as -Av9{,a,b} -64, for compatibility with Sun's
402 * Select the architecture and possibly the file format.
403 * Instructions or features not supported by the selected
404 * architecture cause fatal errors.
406 * The default is to start at v6, and bump the architecture up
407 * whenever an instruction is seen at a higher level. In 32 bit
408 * environments, v9 is not bumped up to, the user must pass
411 * If -bump is specified, a warning is printing when bumping to
414 * If an architecture is specified, all instructions must match
415 * that architecture. Any higher level instructions are flagged
416 * as errors. Note that in the 32 bit environment specifying
417 * -Av8plus does not automatically create a v8plus object file, a
418 * v9 insn must be seen.
420 * If both an architecture and -bump are specified, the
421 * architecture starts at the specified level, but bumps are
422 * warnings. Note that we can't set `current_architecture' to
423 * the requested level in this case: in the 32 bit environment,
424 * we still must avoid creating v8plus object files unless v9
428 * Bumping between incompatible architectures is always an
429 * error. For example, from sparclite to v9.
433 const char *md_shortopts = "A:K:VQ:sq";
436 const char *md_shortopts = "A:k";
438 const char *md_shortopts = "A:";
441 struct option md_longopts[] = {
442 #define OPTION_BUMP (OPTION_MD_BASE)
443 {"bump", no_argument, NULL, OPTION_BUMP},
444 #define OPTION_SPARC (OPTION_MD_BASE + 1)
445 {"sparc", no_argument, NULL, OPTION_SPARC},
446 #define OPTION_XARCH (OPTION_MD_BASE + 2)
447 {"xarch", required_argument, NULL, OPTION_XARCH},
449 #define OPTION_32 (OPTION_MD_BASE + 3)
450 {"32", no_argument, NULL, OPTION_32},
451 #define OPTION_64 (OPTION_MD_BASE + 4)
452 {"64", no_argument, NULL, OPTION_64},
453 #define OPTION_TSO (OPTION_MD_BASE + 5)
454 {"TSO", no_argument, NULL, OPTION_TSO},
455 #define OPTION_PSO (OPTION_MD_BASE + 6)
456 {"PSO", no_argument, NULL, OPTION_PSO},
457 #define OPTION_RMO (OPTION_MD_BASE + 7)
458 {"RMO", no_argument, NULL, OPTION_RMO},
460 #ifdef SPARC_BIENDIAN
461 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
462 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
463 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
464 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
466 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
467 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
468 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
469 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
471 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
472 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
473 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
474 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
476 #define OPTION_RELAX (OPTION_MD_BASE + 14)
477 {"relax", no_argument, NULL, OPTION_RELAX},
478 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
479 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
480 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
481 {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT},
482 {NULL, no_argument, NULL, 0}
485 size_t md_longopts_size = sizeof (md_longopts);
488 md_parse_option (int c, const char *arg)
490 /* We don't get a chance to initialize anything before we're called,
491 so handle that now. */
492 if (! default_init_p)
493 init_default_arch ();
499 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
504 if (!strncmp (arg, "v9", 2))
505 md_parse_option (OPTION_64, NULL);
508 if (!strncmp (arg, "v8", 2)
509 || !strncmp (arg, "v7", 2)
510 || !strncmp (arg, "v6", 2)
511 || !strcmp (arg, "sparclet")
512 || !strcmp (arg, "sparclite")
513 || !strcmp (arg, "sparc86x"))
514 md_parse_option (OPTION_32, NULL);
521 struct sparc_arch *sa;
522 enum sparc_opcode_arch_val opcode_arch;
524 sa = lookup_arch (arg);
526 || ! sa->user_option_p)
528 if (c == OPTION_XARCH)
529 as_bad (_("invalid architecture -xarch=%s"), arg);
531 as_bad (_("invalid architecture -A%s"), arg);
535 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
536 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
537 as_fatal (_("Bad opcode table, broken assembler."));
539 if (!architecture_requested
540 || opcode_arch > max_architecture)
541 max_architecture = opcode_arch;
543 /* The allowed hardware capabilities are the implied by the
544 opcodes arch plus any extra capabilities defined in the GAS
548 | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32)
549 | (((bfd_uint64_t) sa->hwcap2_allowed) << 32)
550 | sparc_opcode_archs[opcode_arch].hwcaps
551 | sa->hwcap_allowed);
552 architecture_requested = 1;
557 /* Ignore -sparc, used by SunOS make default .s.o rule. */
560 case OPTION_ENFORCE_ALIGNED_DATA:
561 enforce_aligned_data = 1;
564 #ifdef SPARC_BIENDIAN
565 case OPTION_LITTLE_ENDIAN:
566 target_big_endian = 0;
567 if (default_arch_type != sparclet)
568 as_fatal ("This target does not support -EL");
570 case OPTION_LITTLE_ENDIAN_DATA:
571 target_little_endian_data = 1;
572 target_big_endian = 0;
573 if (default_arch_type != sparc86x
574 && default_arch_type != v9)
575 as_fatal ("This target does not support --little-endian-data");
577 case OPTION_BIG_ENDIAN:
578 target_big_endian = 1;
592 const char **list, **l;
594 sparc_arch_size = c == OPTION_32 ? 32 : 64;
595 list = bfd_target_list ();
596 for (l = list; *l != NULL; l++)
598 if (sparc_arch_size == 32)
600 if (CONST_STRNEQ (*l, "elf32-sparc"))
605 if (CONST_STRNEQ (*l, "elf64-sparc"))
610 as_fatal (_("No compiled in support for %d bit object file format"),
614 if (sparc_arch_size == 64
615 && max_architecture < SPARC_OPCODE_ARCH_V9)
616 max_architecture = SPARC_OPCODE_ARCH_V9;
621 sparc_memory_model = MM_TSO;
625 sparc_memory_model = MM_PSO;
629 sparc_memory_model = MM_RMO;
637 /* Qy - do emit .comment
638 Qn - do not emit .comment. */
642 /* Use .stab instead of .stab.excl. */
646 /* quick -- Native assembler does fewer checks. */
650 if (strcmp (arg, "PIC") != 0)
651 as_warn (_("Unrecognized option following -K"));
656 case OPTION_NO_UNDECLARED_REGS:
657 no_undeclared_regs = 1;
660 case OPTION_UNDECLARED_REGS:
661 no_undeclared_regs = 0;
669 case OPTION_NO_RELAX:
673 case OPTION_DCTI_COUPLES_DETECT:
674 dcti_couples_detect = 1;
685 md_show_usage (FILE *stream)
687 const struct sparc_arch *arch;
690 /* We don't get a chance to initialize anything before we're called,
691 so handle that now. */
692 if (! default_init_p)
693 init_default_arch ();
695 fprintf (stream, _("SPARC options:\n"));
697 for (arch = &sparc_arch_table[0]; arch->name; arch++)
699 if (!arch->user_option_p)
701 if (arch != &sparc_arch_table[0])
702 fprintf (stream, " | ");
703 if (column + strlen (arch->name) > 70)
706 fputc ('\n', stream);
708 column += 5 + 2 + strlen (arch->name);
709 fprintf (stream, "-A%s", arch->name);
711 for (arch = &sparc_arch_table[0]; arch->name; arch++)
713 if (!arch->user_option_p)
715 fprintf (stream, " | ");
716 if (column + strlen (arch->name) > 65)
719 fputc ('\n', stream);
721 column += 5 + 7 + strlen (arch->name);
722 fprintf (stream, "-xarch=%s", arch->name);
724 fprintf (stream, _("\n\
725 specify variant of SPARC architecture\n\
726 -bump warn when assembler switches architectures\n\
728 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
729 -relax relax jumps and branches (default)\n\
730 -no-relax avoid changing any jumps and branches\n"));
732 fprintf (stream, _("\
733 -k generate PIC\n"));
736 fprintf (stream, _("\
737 -32 create 32 bit object file\n\
738 -64 create 64 bit object file\n"));
739 fprintf (stream, _("\
740 [default is %d]\n"), default_arch_size);
741 fprintf (stream, _("\
742 -TSO use Total Store Ordering\n\
743 -PSO use Partial Store Ordering\n\
744 -RMO use Relaxed Memory Ordering\n"));
745 fprintf (stream, _("\
746 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
747 fprintf (stream, _("\
748 -KPIC generate PIC\n\
749 -V print assembler version number\n\
750 -undeclared-regs ignore application global register usage without\n\
751 appropriate .register directive (default)\n\
752 -no-undeclared-regs force error on application global register usage\n\
753 without appropriate .register directive\n\
754 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
759 #ifdef SPARC_BIENDIAN
760 fprintf (stream, _("\
761 -EL generate code for a little endian machine\n\
762 -EB generate code for a big endian machine\n\
763 --little-endian-data generate code for a machine having big endian\n\
764 instructions and little endian data.\n"));
768 /* Native operand size opcode translation. */
774 } native_op_table[] =
776 {"ldn", "ld", "ldx"},
777 {"ldna", "lda", "ldxa"},
778 {"stn", "st", "stx"},
779 {"stna", "sta", "stxa"},
780 {"slln", "sll", "sllx"},
781 {"srln", "srl", "srlx"},
782 {"sran", "sra", "srax"},
783 {"casn", "cas", "casx"},
784 {"casna", "casa", "casxa"},
785 {"clrn", "clr", "clrx"},
789 /* sparc64 privileged and hyperprivileged registers. */
791 struct priv_reg_entry
797 struct priv_reg_entry priv_reg_table[] =
818 {NULL, -1}, /* End marker. */
821 struct priv_reg_entry hpriv_reg_table[] =
831 {"hstick_offset", 28},
832 {"hstick_enable", 29},
834 {NULL, -1}, /* End marker. */
837 /* v9a or later specific ancillary state registers. */
839 struct priv_reg_entry v9a_asr_table[] =
842 {"sys_tick_cmpr", 25},
846 {"softint_clear", 21},
857 {"clear_softint", 21},
858 {NULL, -1}, /* End marker. */
862 cmp_reg_entry (const void *parg, const void *qarg)
864 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
865 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
867 if (p->name == q->name)
869 else if (p->name == NULL)
871 else if (q->name == NULL)
874 return strcmp (q->name, p->name);
877 /* sparc %-pseudo-operations. */
880 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
881 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
883 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
884 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
886 instruction. (Generally they can appear
887 anywhere an immediate operand is
891 /* The name as it appears in assembler. */
893 /* The reloc this pseudo-op translates to. */
894 bfd_reloc_code_real_type reloc;
895 /* Flags. See F_POP_* above. */
899 struct pop_entry pop_table[] =
901 { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 },
902 { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 },
903 { "hi", BFD_RELOC_HI22, F_POP_PCREL },
904 { "lo", BFD_RELOC_LO10, F_POP_PCREL },
905 { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL },
906 { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL },
907 { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL },
908 { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL },
909 { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL },
910 { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 },
911 { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 },
912 { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 },
913 { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 },
914 { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 },
915 { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 },
916 { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 },
917 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 },
918 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 },
919 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 },
920 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 },
921 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 },
922 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 },
923 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 },
924 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 },
925 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 },
926 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 },
927 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 },
928 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 },
929 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX },
930 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL },
931 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX },
932 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL },
933 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX },
934 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX },
935 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX },
936 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX },
937 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX }
940 /* Table of %-names that can appear in a sparc assembly program. This
941 table is initialized in md_begin and contains entries for each
942 privileged/hyperprivileged/alternate register and %-pseudo-op. */
955 enum perc_entry_type type;
956 /* Name of the %-entity. */
960 /* Value. Either a pop or a reg depending on type.*/
963 struct pop_entry *pop;
964 struct priv_reg_entry *reg;
968 #define NUM_PERC_ENTRIES \
969 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
970 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
971 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
972 + ARRAY_SIZE (pop_table) \
975 struct perc_entry perc_table[NUM_PERC_ENTRIES];
978 cmp_perc_entry (const void *parg, const void *qarg)
980 const struct perc_entry *p = (const struct perc_entry *) parg;
981 const struct perc_entry *q = (const struct perc_entry *) qarg;
983 if (p->name == q->name)
985 else if (p->name == NULL)
987 else if (q->name == NULL)
990 return strcmp (q->name, p->name);
993 /* This function is called once, at assembler startup time. It should
994 set up all the tables, etc. that the MD part of the assembler will
1000 const char *retval = NULL;
1004 /* We don't get a chance to initialize anything before md_parse_option
1005 is called, and it may not be called, so handle default initialization
1006 now if not already done. */
1007 if (! default_init_p)
1008 init_default_arch ();
1010 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
1011 op_hash = hash_new ();
1013 while (i < (unsigned int) sparc_num_opcodes)
1015 const char *name = sparc_opcodes[i].name;
1016 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
1019 as_bad (_("Internal error: can't hash `%s': %s\n"),
1020 sparc_opcodes[i].name, retval);
1025 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
1027 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1028 sparc_opcodes[i].name, sparc_opcodes[i].args);
1033 while (i < (unsigned int) sparc_num_opcodes
1034 && !strcmp (sparc_opcodes[i].name, name));
1037 for (i = 0; native_op_table[i].name; i++)
1039 const struct sparc_opcode *insn;
1040 const char *name = ((sparc_arch_size == 32)
1041 ? native_op_table[i].name32
1042 : native_op_table[i].name64);
1043 insn = (struct sparc_opcode *) hash_find (op_hash, name);
1046 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1047 name, native_op_table[i].name);
1052 retval = hash_insert (op_hash, native_op_table[i].name,
1056 as_bad (_("Internal error: can't hash `%s': %s\n"),
1057 sparc_opcodes[i].name, retval);
1064 as_fatal (_("Broken assembler. No assembly attempted."));
1066 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
1067 sizeof (priv_reg_table[0]), cmp_reg_entry);
1068 qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]),
1069 sizeof (hpriv_reg_table[0]), cmp_reg_entry);
1070 qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]),
1071 sizeof (v9a_asr_table[0]), cmp_reg_entry);
1073 /* If -bump, record the architecture level at which we start issuing
1074 warnings. The behaviour is different depending upon whether an
1075 architecture was explicitly specified. If it wasn't, we issue warnings
1076 for all upwards bumps. If it was, we don't start issuing warnings until
1077 we need to bump beyond the requested architecture or when we bump between
1078 conflicting architectures. */
1081 && architecture_requested)
1083 /* `max_architecture' records the requested architecture.
1084 Issue warnings if we go above it. */
1085 warn_after_architecture = max_architecture;
1088 /* Find the highest architecture level that doesn't conflict with
1089 the requested one. */
1092 || !architecture_requested)
1094 enum sparc_opcode_arch_val current_max_architecture
1097 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
1098 max_architecture > warn_after_architecture;
1100 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
1101 current_max_architecture))
1105 /* Prepare the tables of %-pseudo-ops. */
1107 struct priv_reg_entry *reg_tables[]
1108 = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL};
1109 struct priv_reg_entry **reg_table;
1112 /* Add registers. */
1113 for (reg_table = reg_tables; reg_table[0]; reg_table++)
1115 struct priv_reg_entry *reg;
1116 for (reg = *reg_table; reg->name; reg++)
1118 struct perc_entry *p = &perc_table[entry++];
1119 p->type = perc_entry_reg;
1120 p->name = reg->name;
1121 p->len = strlen (reg->name);
1126 /* Add %-pseudo-ops. */
1127 for (i = 0; i < ARRAY_SIZE (pop_table); i++)
1129 struct perc_entry *p = &perc_table[entry++];
1130 p->type = (pop_table[i].flags & F_POP_POSTFIX
1131 ? perc_entry_post_pop : perc_entry_imm_pop);
1132 p->name = pop_table[i].name;
1133 p->len = strlen (pop_table[i].name);
1134 p->pop = &pop_table[i];
1137 /* Last entry is the sentinel. */
1138 perc_table[entry].type = perc_entry_none;
1140 qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]),
1141 sizeof (perc_table[0]), cmp_perc_entry);
1146 /* Called after all assembly has been done. */
1151 unsigned long mach = bfd_mach_sparc;
1152 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1153 int hwcaps, hwcaps2;
1156 if (sparc_arch_size == 64)
1157 switch (current_architecture)
1159 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
1160 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
1161 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break;
1162 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break;
1163 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break;
1164 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break;
1165 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break;
1166 case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v9m8; break;
1167 default: mach = bfd_mach_sparc_v9; break;
1170 switch (current_architecture)
1172 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
1173 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
1174 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
1175 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
1176 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break;
1177 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break;
1178 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break;
1179 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break;
1180 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break;
1181 case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v8plusm8; break;
1182 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1183 be but for now it is (since that's the way it's always been
1187 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
1189 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1190 hwcaps = hwcap_seen & U0xffffffff;
1191 hwcaps2 = hwcap_seen >> 32;
1194 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps);
1196 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2);
1200 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1203 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
1207 /* Sign-extend the value from the architecture word size, so that
1208 0xffffffff is always considered -1 on sparc32. */
1209 if (sparc_arch_size == 32)
1211 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
1212 val = ((val & U0xffffffff) ^ sign) - sign;
1221 /* Return non-zero if VAL is in the range 0 to MAX. */
1224 in_unsigned_range (bfd_vma val, bfd_vma max)
1231 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1232 (e.g. -15 to +31). */
1235 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
1241 if (val < ~(max >> 1))
1247 sparc_ffs (unsigned int mask)
1254 for (i = 0; (mask & 1) == 0; ++i)
1259 /* Implement big shift right. */
1261 BSR (bfd_vma val, int amount)
1263 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1264 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1265 return val >> amount;
1268 /* For communication between sparc_ip and get_expression. */
1269 static char *expr_end;
1271 /* Values for `special_case'.
1272 Instructions that require weird handling because they're longer than
1274 #define SPECIAL_CASE_NONE 0
1275 #define SPECIAL_CASE_SET 1
1276 #define SPECIAL_CASE_SETSW 2
1277 #define SPECIAL_CASE_SETX 3
1278 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1279 #define SPECIAL_CASE_FDIV 4
1281 /* Bit masks of various insns. */
1282 #define NOP_INSN 0x01000000
1283 #define OR_INSN 0x80100000
1284 #define XOR_INSN 0x80180000
1285 #define FMOVS_INSN 0x81A00020
1286 #define SETHI_INSN 0x01000000
1287 #define SLLX_INSN 0x81281000
1288 #define SRA_INSN 0x81380000
1290 /* The last instruction to be assembled. */
1291 static const struct sparc_opcode *last_insn;
1292 /* The assembled opcode of `last_insn'. */
1293 static unsigned long last_opcode;
1295 /* Handle the set and setuw synthetic instructions. */
1298 synthetize_setuw (const struct sparc_opcode *insn)
1300 int need_hi22_p = 0;
1301 int rd = (the_insn.opcode & RD (~0)) >> 25;
1303 if (the_insn.exp.X_op == O_constant)
1305 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1307 if (sizeof (offsetT) > 4
1308 && (the_insn.exp.X_add_number < 0
1309 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1310 as_warn (_("set: number not in 0..4294967295 range"));
1314 if (sizeof (offsetT) > 4
1315 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1316 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1317 as_warn (_("set: number not in -2147483648..4294967295 range"));
1318 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1322 /* See if operand is absolute and small; skip sethi if so. */
1323 if (the_insn.exp.X_op != O_constant
1324 || the_insn.exp.X_add_number >= (1 << 12)
1325 || the_insn.exp.X_add_number < -(1 << 12))
1327 the_insn.opcode = (SETHI_INSN | RD (rd)
1328 | ((the_insn.exp.X_add_number >> 10)
1329 & (the_insn.exp.X_op == O_constant
1331 the_insn.reloc = (the_insn.exp.X_op != O_constant
1332 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1333 output_insn (insn, &the_insn);
1337 /* See if operand has no low-order bits; skip OR if so. */
1338 if (the_insn.exp.X_op != O_constant
1339 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1342 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1344 | (the_insn.exp.X_add_number
1345 & (the_insn.exp.X_op != O_constant
1346 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1347 the_insn.reloc = (the_insn.exp.X_op != O_constant
1348 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1349 output_insn (insn, &the_insn);
1353 /* Handle the setsw synthetic instruction. */
1356 synthetize_setsw (const struct sparc_opcode *insn)
1360 rd = (the_insn.opcode & RD (~0)) >> 25;
1362 if (the_insn.exp.X_op != O_constant)
1364 synthetize_setuw (insn);
1366 /* Need to sign extend it. */
1367 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1368 the_insn.reloc = BFD_RELOC_NONE;
1369 output_insn (insn, &the_insn);
1373 if (sizeof (offsetT) > 4
1374 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1375 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1376 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1378 low32 = the_insn.exp.X_add_number;
1382 synthetize_setuw (insn);
1388 the_insn.reloc = BFD_RELOC_NONE;
1389 /* See if operand is absolute and small; skip sethi if so. */
1390 if (low32 < -(1 << 12))
1392 the_insn.opcode = (SETHI_INSN | RD (rd)
1393 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1394 output_insn (insn, &the_insn);
1395 low32 = 0x1c00 | (low32 & 0x3ff);
1396 opc = RS1 (rd) | XOR_INSN;
1399 the_insn.opcode = (opc | RD (rd) | IMMED
1400 | (low32 & 0x1fff));
1401 output_insn (insn, &the_insn);
1404 /* Handle the setx synthetic instruction. */
1407 synthetize_setx (const struct sparc_opcode *insn)
1409 int upper32, lower32;
1410 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1411 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1413 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1414 int need_xor10_p = 0;
1416 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1417 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1418 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1421 upper_dstreg = tmpreg;
1422 /* The tmp reg should not be the dst reg. */
1423 if (tmpreg == dstreg)
1424 as_warn (_("setx: temporary register same as destination register"));
1426 /* ??? Obviously there are other optimizations we can do
1427 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1428 doing some of these. Later. If you do change things, try to
1429 change all of this to be table driven as well. */
1430 /* What to output depends on the number if it's constant.
1431 Compute that first, then output what we've decided upon. */
1432 if (the_insn.exp.X_op != O_constant)
1434 if (sparc_arch_size == 32)
1436 /* When arch size is 32, we want setx to be equivalent
1437 to setuw for anything but constants. */
1438 the_insn.exp.X_add_number &= 0xffffffff;
1439 synthetize_setuw (insn);
1442 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1448 /* Reset X_add_number, we've extracted it as upper32/lower32.
1449 Otherwise fixup_segment will complain about not being able to
1450 write an 8 byte number in a 4 byte field. */
1451 the_insn.exp.X_add_number = 0;
1453 /* Only need hh22 if `or' insn can't handle constant. */
1454 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1457 /* Does bottom part (after sethi) have bits? */
1458 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1459 /* No hh22, but does upper32 still have bits we can't set
1461 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1464 /* If the lower half is all zero, we build the upper half directly
1465 into the dst reg. */
1467 /* Need lower half if number is zero or 0xffffffff00000000. */
1468 || (! need_hh22_p && ! need_hm10_p))
1470 /* No need for sethi if `or' insn can handle constant. */
1471 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1472 /* Note that we can't use a negative constant in the `or'
1473 insn unless the upper 32 bits are all ones. */
1474 || (lower32 < 0 && upper32 != -1)
1475 || (lower32 >= 0 && upper32 == -1))
1478 if (need_hi22_p && upper32 == -1)
1481 /* Does bottom part (after sethi) have bits? */
1482 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1484 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1485 /* Need `or' if we didn't set anything else. */
1486 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1490 /* Output directly to dst reg if lower 32 bits are all zero. */
1491 upper_dstreg = dstreg;
1494 if (!upper_dstreg && dstreg)
1495 as_warn (_("setx: illegal temporary register g0"));
1499 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1500 | ((upper32 >> 10) & 0x3fffff));
1501 the_insn.reloc = (the_insn.exp.X_op != O_constant
1502 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1503 output_insn (insn, &the_insn);
1508 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1509 | (((need_xor10_p ? ~lower32 : lower32)
1510 >> 10) & 0x3fffff));
1511 the_insn.reloc = (the_insn.exp.X_op != O_constant
1512 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1513 output_insn (insn, &the_insn);
1518 the_insn.opcode = (OR_INSN
1519 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1522 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1523 the_insn.reloc = (the_insn.exp.X_op != O_constant
1524 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1525 output_insn (insn, &the_insn);
1530 /* FIXME: One nice optimization to do here is to OR the low part
1531 with the highpart if hi22 isn't needed and the low part is
1533 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1536 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1537 the_insn.reloc = (the_insn.exp.X_op != O_constant
1538 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1539 output_insn (insn, &the_insn);
1542 /* If we needed to build the upper part, shift it into place. */
1543 if (need_hh22_p || need_hm10_p)
1545 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1547 the_insn.reloc = BFD_RELOC_NONE;
1548 output_insn (insn, &the_insn);
1551 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1554 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1555 | 0x1c00 | (lower32 & 0x3ff));
1556 the_insn.reloc = BFD_RELOC_NONE;
1557 output_insn (insn, &the_insn);
1560 /* If we needed to build both upper and lower parts, OR them together. */
1561 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1563 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1565 the_insn.reloc = BFD_RELOC_NONE;
1566 output_insn (insn, &the_insn);
1570 /* Main entry point to assemble one instruction. */
1573 md_assemble (char *str)
1575 const struct sparc_opcode *insn;
1579 special_case = sparc_ip (str, &insn);
1583 /* Certain instructions may not appear on delay slots. Check for
1584 these situations. */
1585 if (last_insn != NULL
1586 && (last_insn->flags & F_DELAYED) != 0)
1588 /* Before SPARC V9 the effect of having a delayed branch
1589 instruction in the delay slot of a conditional delayed branch
1592 In SPARC V9 DCTI couples are well defined.
1594 However, starting with the UltraSPARC Architecture 2005, DCTI
1595 couples (of all kind) are deprecated and should not be used,
1596 as they may be slow or behave differently to what the
1597 programmer expects. */
1598 if (dcti_couples_detect
1599 && (insn->flags & F_DELAYED) != 0
1600 && ((max_architecture < SPARC_OPCODE_ARCH_V9
1601 && (last_insn->flags & F_CONDBR) != 0)
1602 || max_architecture >= SPARC_OPCODE_ARCH_V9C))
1603 as_warn (_("unpredictable DCTI couple"));
1606 /* We warn about attempts to put a floating point branch in a
1607 delay slot, unless the delay slot has been annulled. */
1608 if ((insn->flags & F_FBR) != 0
1609 /* ??? This test isn't completely accurate. We assume anything with
1610 F_{UNBR,CONDBR,FBR} set is annullable. */
1611 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1612 || (last_opcode & ANNUL) == 0))
1613 as_warn (_("FP branch in delay slot"));
1616 /* SPARC before v9 requires a nop instruction between a floating
1617 point instruction and a floating point branch. We insert one
1618 automatically, with a warning. */
1619 if (max_architecture < SPARC_OPCODE_ARCH_V9
1620 && last_insn != NULL
1621 && (insn->flags & F_FBR) != 0
1622 && (last_insn->flags & F_FLOAT) != 0)
1624 struct sparc_it nop_insn;
1626 nop_insn.opcode = NOP_INSN;
1627 nop_insn.reloc = BFD_RELOC_NONE;
1628 output_insn (insn, &nop_insn);
1629 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1632 switch (special_case)
1634 case SPECIAL_CASE_NONE:
1636 output_insn (insn, &the_insn);
1639 case SPECIAL_CASE_SETSW:
1640 synthetize_setsw (insn);
1643 case SPECIAL_CASE_SET:
1644 synthetize_setuw (insn);
1647 case SPECIAL_CASE_SETX:
1648 synthetize_setx (insn);
1651 case SPECIAL_CASE_FDIV:
1653 int rd = (the_insn.opcode >> 25) & 0x1f;
1655 output_insn (insn, &the_insn);
1657 /* According to information leaked from Sun, the "fdiv" instructions
1658 on early SPARC machines would produce incorrect results sometimes.
1659 The workaround is to add an fmovs of the destination register to
1660 itself just after the instruction. This was true on machines
1661 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1662 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1663 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1664 output_insn (insn, &the_insn);
1669 as_fatal (_("failed special case insn sanity check"));
1674 get_hwcap_name (bfd_uint64_t mask)
1676 if (mask & HWCAP_MUL32)
1678 if (mask & HWCAP_DIV32)
1680 if (mask & HWCAP_FSMULD)
1682 if (mask & HWCAP_V8PLUS)
1684 if (mask & HWCAP_POPC)
1686 if (mask & HWCAP_VIS)
1688 if (mask & HWCAP_VIS2)
1690 if (mask & HWCAP_ASI_BLK_INIT)
1691 return "ASIBlkInit";
1692 if (mask & HWCAP_FMAF)
1694 if (mask & HWCAP_VIS3)
1696 if (mask & HWCAP_HPC)
1698 if (mask & HWCAP_RANDOM)
1700 if (mask & HWCAP_TRANS)
1702 if (mask & HWCAP_FJFMAU)
1704 if (mask & HWCAP_IMA)
1706 if (mask & HWCAP_ASI_CACHE_SPARING)
1708 if (mask & HWCAP_AES)
1710 if (mask & HWCAP_DES)
1712 if (mask & HWCAP_KASUMI)
1714 if (mask & HWCAP_CAMELLIA)
1716 if (mask & HWCAP_MD5)
1718 if (mask & HWCAP_SHA1)
1720 if (mask & HWCAP_SHA256)
1722 if (mask & HWCAP_SHA512)
1724 if (mask & HWCAP_MPMUL)
1726 if (mask & HWCAP_MONT)
1728 if (mask & HWCAP_PAUSE)
1730 if (mask & HWCAP_CBCOND)
1732 if (mask & HWCAP_CRC32C)
1736 if (mask & HWCAP2_FJATHPLUS)
1738 if (mask & HWCAP2_VIS3B)
1740 if (mask & HWCAP2_ADP)
1742 if (mask & HWCAP2_SPARC5)
1744 if (mask & HWCAP2_MWAIT)
1746 if (mask & HWCAP2_XMPMUL)
1748 if (mask & HWCAP2_XMONT)
1750 if (mask & HWCAP2_NSEC)
1752 if (mask & HWCAP2_SPARC6)
1754 if (mask & HWCAP2_ONADDSUB)
1756 if (mask & HWCAP2_ONMUL)
1758 if (mask & HWCAP2_ONDIV)
1760 if (mask & HWCAP2_DICTUNP)
1762 if (mask & HWCAP2_FPCMPSHL)
1764 if (mask & HWCAP2_RLE)
1766 if (mask & HWCAP2_SHA3)
1772 /* Subroutine of md_assemble to do the actual parsing. */
1775 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1777 const char *error_message = "";
1781 const struct sparc_opcode *insn;
1783 unsigned long opcode;
1784 unsigned int mask = 0;
1788 int special_case = SPECIAL_CASE_NONE;
1789 const sparc_asi *sasi = NULL;
1796 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1813 as_bad (_("Unknown opcode: `%s'"), str);
1815 return special_case;
1817 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1821 as_bad (_("Unknown opcode: `%s'"), str);
1822 return special_case;
1832 opcode = insn->match;
1833 memset (&the_insn, '\0', sizeof (the_insn));
1834 the_insn.reloc = BFD_RELOC_NONE;
1837 /* Build the opcode, checking as we go to make sure that the
1839 for (args = insn->args;; ++args)
1847 /* Parse a series of masks. */
1854 if (! parse_keyword_arg (sparc_encode_membar, &s,
1857 error_message = _(": invalid membar mask name");
1863 if (*s == '|' || *s == '+')
1871 if (! parse_const_expr_arg (&s, &kmask))
1873 error_message = _(": invalid membar mask expression");
1876 if (kmask < 0 || kmask > 127)
1878 error_message = _(": invalid membar mask number");
1883 opcode |= MEMBAR (kmask);
1891 if (! parse_const_expr_arg (&s, &smask))
1893 error_message = _(": invalid siam mode expression");
1896 if (smask < 0 || smask > 7)
1898 error_message = _(": invalid siam mode number");
1909 /* Parse a prefetch function. */
1912 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1914 error_message = _(": invalid prefetch function name");
1920 if (! parse_const_expr_arg (&s, &fcn))
1922 error_message = _(": invalid prefetch function expression");
1925 if (fcn < 0 || fcn > 31)
1927 error_message = _(": invalid prefetch function number");
1937 /* Parse a sparc64 privileged register. */
1940 struct priv_reg_entry *p;
1941 unsigned int len = 9999999; /* Init to make gcc happy. */
1944 for (p = priv_reg_table; p->name; p++)
1945 if (p->name[0] == s[0])
1947 len = strlen (p->name);
1948 if (strncmp (p->name, s, len) == 0)
1954 error_message = _(": unrecognizable privileged register");
1958 if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum)
1960 error_message = _(": unrecognizable privileged register");
1969 error_message = _(": unrecognizable privileged register");
1975 /* Parse a sparc64 hyperprivileged register. */
1978 struct priv_reg_entry *p;
1979 unsigned int len = 9999999; /* Init to make gcc happy. */
1982 for (p = hpriv_reg_table; p->name; p++)
1983 if (p->name[0] == s[0])
1985 len = strlen (p->name);
1986 if (strncmp (p->name, s, len) == 0)
1992 error_message = _(": unrecognizable hyperprivileged register");
1996 if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum)
1998 error_message = _(": unrecognizable hyperprivileged register");
2007 error_message = _(": unrecognizable hyperprivileged register");
2013 /* Parse a v9a or later ancillary state register. */
2016 struct priv_reg_entry *p;
2017 unsigned int len = 9999999; /* Init to make gcc happy. */
2020 for (p = v9a_asr_table; p->name; p++)
2021 if (p->name[0] == s[0])
2023 len = strlen (p->name);
2024 if (strncmp (p->name, s, len) == 0)
2030 error_message = _(": unrecognizable ancillary state register");
2034 if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum)
2036 error_message = _(": unrecognizable ancillary state register");
2045 error_message = _(": unrecognizable ancillary state register");
2051 if (strncmp (s, "%asr", 4) == 0)
2059 while (ISDIGIT (*s))
2061 num = num * 10 + *s - '0';
2065 /* We used to check here for the asr number to
2066 be between 16 and 31 in V9 and later, as
2067 mandated by the section C.1.1 "Register
2068 Names" in the SPARC spec. However, we
2069 decided to remove this restriction as a) it
2070 introduces problems when new V9 asr registers
2071 are introduced, b) the Solaris assembler
2072 doesn't implement this restriction and c) the
2073 restriction will go away in future revisions
2074 of the Oracle SPARC Architecture. */
2076 if (num < 0 || 31 < num)
2078 error_message = _(": asr number must be between 0 and 31");
2082 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
2087 error_message = _(": expecting %asrN");
2094 the_insn.reloc = BFD_RELOC_SPARC_11;
2098 the_insn.reloc = BFD_RELOC_SPARC_10;
2104 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
2109 if (s[0] == '0' && s[1] == 'x')
2112 while (ISXDIGIT (*s))
2115 num |= hex_value (*s);
2121 while (ISDIGIT (*s))
2123 num = num * 10 + *s - '0';
2127 if (num < 0 || num > 31)
2129 error_message = _(": crypto immediate must be between 0 and 31");
2133 opcode |= RS3 (num);
2138 error_message = _(": expecting crypto immediate");
2143 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2144 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2145 the_insn.reloc = BFD_RELOC_SPARC_5;
2147 the_insn.reloc = BFD_RELOC_SPARC13;
2148 /* These fields are unsigned, but for upward compatibility,
2149 allow negative values as well. */
2153 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2154 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2155 the_insn.reloc = BFD_RELOC_SPARC_6;
2157 the_insn.reloc = BFD_RELOC_SPARC13;
2158 /* These fields are unsigned, but for upward compatibility,
2159 allow negative values as well. */
2163 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
2168 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
2173 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
2178 if (*s == 'p' && s[1] == 'n')
2186 if (*s == 'p' && s[1] == 't')
2198 if ((strncmp (s, "%icc", 4) == 0)
2199 || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0))
2211 if ((strncmp (s, "%xcc", 4) == 0)
2212 || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0))
2224 if (strncmp (s, "%fcc0", 5) == 0)
2236 if (strncmp (s, "%fcc1", 5) == 0)
2248 if (strncmp (s, "%fcc2", 5) == 0)
2260 if (strncmp (s, "%fcc3", 5) == 0)
2268 if (strncmp (s, "%pc", 3) == 0)
2276 if (strncmp (s, "%tick", 5) == 0)
2283 case '\0': /* End of args. */
2284 if (s[0] == ',' && s[1] == '%')
2288 const struct perc_entry *p;
2290 for (p = perc_table; p->type != perc_entry_none; p++)
2291 if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg)
2292 && strncmp (s + 2, p->name, p->len) == 0)
2294 if (p->type == perc_entry_none || p->type == perc_entry_reg)
2297 if (s[p->len + 2] != '(')
2299 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name);
2300 return special_case;
2303 if (! (p->pop->flags & F_POP_TLS_CALL)
2304 && the_insn.reloc != BFD_RELOC_NONE)
2306 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2308 return special_case;
2311 if ((p->pop->flags & F_POP_TLS_CALL)
2312 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2313 || the_insn.exp.X_add_number != 0
2314 || the_insn.exp.X_add_symbol
2315 != symbol_find_or_make ("__tls_get_addr")))
2317 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2319 return special_case;
2322 the_insn.reloc = p->pop->reloc;
2323 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2326 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2329 else if (*s1 == ')')
2338 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name);
2339 return special_case;
2343 (void) get_expression (s);
2363 case '[': /* These must match exactly. */
2371 case '#': /* Must be at least one digit. */
2374 while (ISDIGIT (*s))
2382 case 'C': /* Coprocessor state register. */
2383 if (strncmp (s, "%csr", 4) == 0)
2390 case 'b': /* Next operand is a coprocessor register. */
2393 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2398 mask = 10 * (mask - '0') + (*s++ - '0');
2412 opcode |= mask << 14;
2420 opcode |= mask << 25;
2426 case 'r': /* next operand must be a register */
2436 case 'f': /* frame pointer */
2444 case 'g': /* global register */
2453 case 'i': /* in register */
2457 mask = c - '0' + 24;
2462 case 'l': /* local register */
2466 mask = (c - '0' + 16);
2471 case 'o': /* out register */
2475 mask = (c - '0' + 8);
2480 case 's': /* stack pointer */
2488 case 'r': /* any register */
2489 if (!ISDIGIT ((c = *s++)))
2506 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2522 if ((mask & ~1) == 2 && sparc_arch_size == 64
2523 && no_undeclared_regs && ! globals[mask])
2524 as_bad (_("detected global register use not covered by .register pseudo-op"));
2526 /* Got the register, now figure out where
2527 it goes in the opcode. */
2531 opcode |= mask << 14;
2539 opcode |= mask << 25;
2543 opcode |= (mask << 25) | (mask << 14);
2547 opcode |= (mask << 25) | (mask << 0);
2553 case 'e': /* next operand is a floating point register */
2576 && ((format = *s) == 'f'
2581 for (mask = 0; ISDIGIT (*s); ++s)
2583 mask = 10 * mask + (*s - '0');
2584 } /* read the number */
2594 /* register must be even numbered */
2604 /* register must be multiple of 4 */
2613 /* register must be multiple of 8 */
2617 if (*args == '\'' && mask < 48)
2619 /* register must be higher or equal than %f48 */
2625 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2626 error_message = _(": There are only 64 f registers; [0-63]");
2628 error_message = _(": There are only 32 f registers; [0-31]");
2631 else if (mask >= 32)
2633 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2635 if (*args == 'e' || *args == 'f' || *args == 'g')
2638 = _(": There are only 32 single precision f registers; [0-31]");
2642 mask -= 31; /* wrap high bit */
2646 error_message = _(": There are only 32 f registers; [0-31]");
2654 } /* if not an 'f' register. */
2656 if (*args == '}' && mask != RS2 (opcode))
2659 = _(": Instruction requires frs2 and frsd must be the same register");
2669 opcode |= RS1 (mask);
2676 opcode |= RS2 (mask);
2680 opcode |= RS2 (mask & 0xe);
2685 opcode |= RS3 (mask);
2693 opcode |= RD (mask);
2702 if (strncmp (s, "%fsr", 4) == 0)
2710 if (strncmp (s, "%efsr", 5) == 0)
2717 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2718 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2721 case 'l': /* 22 bit PC relative immediate */
2722 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2726 case 'L': /* 30 bit immediate */
2727 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2732 case 'n': /* 22 bit immediate */
2733 the_insn.reloc = BFD_RELOC_SPARC22;
2736 case 'i': /* 13 bit immediate */
2737 the_insn.reloc = BFD_RELOC_SPARC13;
2747 const char *op_arg = NULL;
2748 static expressionS op_exp;
2749 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2751 /* Check for %hi, etc. */
2754 const struct perc_entry *p;
2756 for (p = perc_table; p->type != perc_entry_none; p++)
2757 if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg)
2758 && strncmp (s + 1, p->name, p->len) == 0)
2760 if (p->type == perc_entry_none || p->type == perc_entry_reg)
2763 if (s[p->len + 1] != '(')
2765 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name);
2766 return special_case;
2770 the_insn.reloc = p->pop->reloc;
2772 v9_arg_p = p->pop->flags & F_POP_V9;
2775 /* Note that if the get_expression() fails, we will still
2776 have created U entries in the symbol table for the
2777 'symbols' in the input string. Try not to create U
2778 symbols for registers, etc. */
2780 /* This stuff checks to see if the expression ends in
2781 +%reg. If it does, it removes the register from
2782 the expression, and re-sets 's' to point to the
2789 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2792 else if (*s1 == ')')
2801 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2802 return special_case;
2806 (void) get_expression (s);
2810 as_bad (_("Expression inside %%%s could not be parsed"), op_arg);
2811 return special_case;
2814 if (*s == ',' || *s == ']' || !*s)
2816 if (*s != '+' && *s != '-')
2818 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2819 return special_case;
2823 op_exp = the_insn.exp;
2824 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2827 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2830 if (s1 != s && ISDIGIT (s1[-1]))
2832 if (s1[-2] == '%' && s1[-3] == '+')
2834 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2836 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2843 if (op_arg && s1 == s + 1)
2844 the_insn.exp.X_op = O_absent;
2846 (void) get_expression (s);
2858 (void) get_expression (s);
2866 the_insn.exp2 = the_insn.exp;
2867 the_insn.exp = op_exp;
2868 if (the_insn.exp2.X_op == O_absent)
2869 the_insn.exp2.X_op = O_illegal;
2870 else if (the_insn.exp.X_op == O_absent)
2872 the_insn.exp = the_insn.exp2;
2873 the_insn.exp2.X_op = O_illegal;
2875 else if (the_insn.exp.X_op == O_constant)
2877 valueT val = the_insn.exp.X_add_number;
2878 switch (the_insn.reloc)
2883 case BFD_RELOC_SPARC_HH22:
2884 val = BSR (val, 32);
2887 case BFD_RELOC_SPARC_LM22:
2888 case BFD_RELOC_HI22:
2889 val = (val >> 10) & 0x3fffff;
2892 case BFD_RELOC_SPARC_HM10:
2893 val = BSR (val, 32);
2896 case BFD_RELOC_LO10:
2900 case BFD_RELOC_SPARC_H34:
2905 case BFD_RELOC_SPARC_H44:
2910 case BFD_RELOC_SPARC_M44:
2915 case BFD_RELOC_SPARC_L44:
2919 case BFD_RELOC_SPARC_HIX22:
2921 val = (val >> 10) & 0x3fffff;
2924 case BFD_RELOC_SPARC_LOX10:
2925 val = (val & 0x3ff) | 0x1c00;
2928 the_insn.exp = the_insn.exp2;
2929 the_insn.exp.X_add_number += val;
2930 the_insn.exp2.X_op = O_illegal;
2931 the_insn.reloc = old_reloc;
2933 else if (the_insn.exp2.X_op != O_constant)
2935 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2936 return special_case;
2940 if (old_reloc != BFD_RELOC_SPARC13
2941 || the_insn.reloc != BFD_RELOC_LO10
2942 || sparc_arch_size != 64
2945 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2946 return special_case;
2948 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2952 /* Check for constants that don't require emitting a reloc. */
2953 if (the_insn.exp.X_op == O_constant
2954 && the_insn.exp.X_add_symbol == 0
2955 && the_insn.exp.X_op_symbol == 0)
2957 /* For pc-relative call instructions, we reject
2958 constants to get better code. */
2960 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2961 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2963 error_message = _(": PC-relative operand can't be a constant");
2967 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2968 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2970 error_message = _(": TLS operand can't be a constant");
2974 /* Constants that won't fit are checked in md_apply_fix
2975 and bfd_install_relocation.
2976 ??? It would be preferable to install the constants
2977 into the insn here and save having to create a fixS
2978 for each one. There already exists code to handle
2979 all the various cases (e.g. in md_apply_fix and
2980 bfd_install_relocation) so duplicating all that code
2981 here isn't right. */
2983 /* This is a special case to handle cbcond instructions
2984 properly, which can need two relocations. The first
2985 one is for the 5-bit immediate field and the latter
2986 is going to be for the WDISP10 branch part. We
2987 handle the R_SPARC_5 immediate directly here so that
2988 we don't need to add support for multiple relocations
2989 in one instruction just yet. */
2990 if (the_insn.reloc == BFD_RELOC_SPARC_5
2991 && ((insn->match & OP(0x3)) == 0))
2993 valueT val = the_insn.exp.X_add_number;
2995 the_insn.reloc = BFD_RELOC_NONE;
2996 if (! in_bitfield_range (val, 0x1f))
2998 error_message = _(": Immediate value in cbcond is out of range.");
3001 opcode |= val & 0x1f;
3022 if (! parse_sparc_asi (&s, &sasi))
3024 error_message = _(": invalid ASI name");
3031 if (! parse_const_expr_arg (&s, &asi))
3033 error_message = _(": invalid ASI expression");
3036 if (asi < 0 || asi > 255)
3038 error_message = _(": invalid ASI number");
3042 opcode |= ASI (asi);
3044 } /* Alternate space. */
3047 if (strncmp (s, "%psr", 4) == 0)
3054 case 'q': /* Floating point queue. */
3055 if (strncmp (s, "%fq", 3) == 0)
3062 case 'Q': /* Coprocessor queue. */
3063 if (strncmp (s, "%cq", 3) == 0)
3071 if (strcmp (str, "set") == 0
3072 || strcmp (str, "setuw") == 0)
3074 special_case = SPECIAL_CASE_SET;
3077 else if (strcmp (str, "setsw") == 0)
3079 special_case = SPECIAL_CASE_SETSW;
3082 else if (strcmp (str, "setx") == 0)
3084 special_case = SPECIAL_CASE_SETX;
3087 else if (strncmp (str, "fdiv", 4) == 0)
3089 special_case = SPECIAL_CASE_FDIV;
3095 if (strncmp (s, "%asi", 4) != 0)
3101 if (strncmp (s, "%fprs", 5) != 0)
3107 if (strncmp (s, "%mcdper",7) != 0)
3113 if (strncmp (s, "%entropy", 8) != 0)
3119 if (strncmp (s, "%ccr", 4) != 0)
3125 if (strncmp (s, "%tbr", 4) != 0)
3131 if (strncmp (s, "%wim", 4) != 0)
3140 /* Parse a 2-bit immediate. */
3141 if (! parse_const_expr_arg (&s, &imm2))
3143 error_message = _(": non-immdiate imm2 operand");
3146 if ((imm2 & ~0x3) != 0)
3148 error_message = _(": imm2 immediate operand out of range (0-3)");
3152 opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1);
3158 char *push = input_line_pointer;
3161 input_line_pointer = s;
3163 if (e.X_op == O_constant)
3165 int n = e.X_add_number;
3166 if (n != e.X_add_number || (n & ~0x1ff) != 0)
3167 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3169 opcode |= e.X_add_number << 5;
3172 as_bad (_("non-immediate OPF operand, ignored"));
3173 s = input_line_pointer;
3174 input_line_pointer = push;
3179 if (strncmp (s, "%y", 2) != 0)
3187 /* Parse a sparclet cpreg. */
3189 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
3191 error_message = _(": invalid cpreg name");
3194 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
3199 as_fatal (_("failed sanity check."));
3200 } /* switch on arg code. */
3202 /* Break out of for() loop. */
3204 } /* For each arg that we expect. */
3209 /* Args don't match. */
3210 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
3211 && (insn->name == insn[1].name
3212 || !strcmp (insn->name, insn[1].name)))
3220 as_bad (_("Illegal operands%s"), error_message);
3221 return special_case;
3226 /* We have a match. Now see if the architecture is OK. */
3227 /* String to use in case of architecture warning. */
3228 const char *msg_str = str;
3229 int needed_arch_mask = insn->architecture;
3231 /* Include the ASI architecture needed as well */
3232 if (sasi && needed_arch_mask > sasi->architecture)
3234 needed_arch_mask = sasi->architecture;
3235 msg_str = sasi->name;
3239 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps;
3241 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3243 hwcap_seen |= hwcaps;
3248 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
3249 if (! needed_arch_mask)
3251 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
3254 if (needed_arch_mask
3255 & SPARC_OPCODE_SUPPORTED (current_architecture))
3258 /* Can we bump up the architecture? */
3259 else if (needed_arch_mask
3260 & SPARC_OPCODE_SUPPORTED (max_architecture))
3262 enum sparc_opcode_arch_val needed_architecture =
3263 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
3264 & needed_arch_mask);
3266 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
3268 && needed_architecture > warn_after_architecture)
3270 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3271 sparc_opcode_archs[current_architecture].name,
3272 sparc_opcode_archs[needed_architecture].name,
3274 warn_after_architecture = needed_architecture;
3276 current_architecture = needed_architecture;
3280 | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32)
3281 | sparc_opcode_archs[current_architecture].hwcaps);
3284 /* ??? This seems to be a bit fragile. What if the next entry in
3285 the opcode table is the one we want and it is supported?
3286 It is possible to arrange the table today so that this can't
3287 happen but what about tomorrow? */
3290 int arch, printed_one_p = 0;
3292 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
3294 /* Create a list of the architectures that support the insn. */
3295 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
3297 arch = sparc_ffs (needed_arch_mask);
3298 while ((1 << arch) <= needed_arch_mask)
3300 if ((1 << arch) & needed_arch_mask)
3304 strcpy (p, sparc_opcode_archs[arch].name);
3311 as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart);
3312 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3314 sparc_opcode_archs[max_architecture].name);
3315 return special_case;
3318 /* Make sure the hwcaps used by the instruction are
3319 currently enabled. */
3320 if (hwcaps & ~hwcap_allowed)
3322 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
3324 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3326 return special_case;
3328 } /* If no match. */
3331 } /* Forever looking for a match. */
3333 the_insn.opcode = opcode;
3334 return special_case;
3338 skip_over_keyword (char *q)
3340 for (q = q + (*q == '#' || *q == '%');
3341 ISALNUM (*q) || *q == '_';
3348 parse_sparc_asi (char **input_pointer_p, const sparc_asi **value_p)
3350 const sparc_asi *value;
3353 p = *input_pointer_p;
3354 q = skip_over_keyword(p);
3357 value = sparc_encode_asi (p);
3362 *input_pointer_p = q;
3366 /* Parse an argument that can be expressed as a keyword.
3367 (eg: #StoreStore or %ccfr).
3368 The result is a boolean indicating success.
3369 If successful, INPUT_POINTER is updated. */
3372 parse_keyword_arg (int (*lookup_fn) (const char *),
3373 char **input_pointerP,
3379 p = *input_pointerP;
3380 q = skip_over_keyword(p);
3383 value = (*lookup_fn) (p);
3388 *input_pointerP = q;
3392 /* Parse an argument that is a constant expression.
3393 The result is a boolean indicating success. */
3396 parse_const_expr_arg (char **input_pointerP, int *valueP)
3398 char *save = input_line_pointer;
3401 input_line_pointer = *input_pointerP;
3402 /* The next expression may be something other than a constant
3403 (say if we're not processing the right variant of the insn).
3404 Don't call expression unless we're sure it will succeed as it will
3405 signal an error (which we want to defer until later). */
3406 /* FIXME: It might be better to define md_operand and have it recognize
3407 things like %asi, etc. but continuing that route through to the end
3408 is a lot of work. */
3409 if (*input_line_pointer == '%')
3411 input_line_pointer = save;
3415 *input_pointerP = input_line_pointer;
3416 input_line_pointer = save;
3417 if (exp.X_op != O_constant)
3419 *valueP = exp.X_add_number;
3423 /* Subroutine of sparc_ip to parse an expression. */
3426 get_expression (char *str)
3431 save_in = input_line_pointer;
3432 input_line_pointer = str;
3433 seg = expression (&the_insn.exp);
3434 if (seg != absolute_section
3435 && seg != text_section
3436 && seg != data_section
3437 && seg != bss_section
3438 && seg != undefined_section)
3440 the_insn.error = _("bad segment");
3441 expr_end = input_line_pointer;
3442 input_line_pointer = save_in;
3445 expr_end = input_line_pointer;
3446 input_line_pointer = save_in;
3450 /* Subroutine of md_assemble to output one insn. */
3453 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3455 char *toP = frag_more (4);
3457 /* Put out the opcode. */
3458 if (INSN_BIG_ENDIAN)
3459 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3461 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3463 /* Put out the symbol-dependent stuff. */
3464 if (theinsn->reloc != BFD_RELOC_NONE)
3466 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3467 (toP - frag_now->fr_literal), /* Where. */
3472 /* Turn off overflow checking in fixup_segment. We'll do our
3473 own overflow checking in md_apply_fix. This is necessary because
3474 the insn size is 4 and fixup_segment will signal an overflow for
3475 large 8 byte quantities. */
3476 fixP->fx_no_overflow = 1;
3477 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3478 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3482 last_opcode = theinsn->opcode;
3485 dwarf2_emit_insn (4);
3490 md_atof (int type, char *litP, int *sizeP)
3492 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3495 /* Write a value out to the object file, using the appropriate
3499 md_number_to_chars (char *buf, valueT val, int n)
3501 if (target_big_endian)
3502 number_to_chars_bigendian (buf, val, n);
3503 else if (target_little_endian_data
3504 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3505 /* Output debug words, which are not in allocated sections, as big
3507 number_to_chars_bigendian (buf, val, n);
3508 else if (target_little_endian_data || ! target_big_endian)
3509 number_to_chars_littleendian (buf, val, n);
3512 /* Apply a fixS to the frags, now that we know the value it ought to
3516 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3518 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3519 offsetT val = * (offsetT *) valP;
3522 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3524 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3527 /* SPARC ELF relocations don't use an addend in the data field. */
3528 if (fixP->fx_addsy != NULL)
3530 switch (fixP->fx_r_type)
3532 case BFD_RELOC_SPARC_TLS_GD_HI22:
3533 case BFD_RELOC_SPARC_TLS_GD_LO10:
3534 case BFD_RELOC_SPARC_TLS_GD_ADD:
3535 case BFD_RELOC_SPARC_TLS_GD_CALL:
3536 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3537 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3538 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3539 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3540 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3541 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3542 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3543 case BFD_RELOC_SPARC_TLS_IE_HI22:
3544 case BFD_RELOC_SPARC_TLS_IE_LO10:
3545 case BFD_RELOC_SPARC_TLS_IE_LD:
3546 case BFD_RELOC_SPARC_TLS_IE_LDX:
3547 case BFD_RELOC_SPARC_TLS_IE_ADD:
3548 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3549 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3550 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3551 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3552 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3553 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3554 case BFD_RELOC_SPARC_TLS_TPOFF32:
3555 case BFD_RELOC_SPARC_TLS_TPOFF64:
3556 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3566 /* This is a hack. There should be a better way to
3567 handle this. Probably in terms of howto fields, once
3568 we can look at these fixups in terms of howtos. */
3569 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3570 val += fixP->fx_where + fixP->fx_frag->fr_address;
3573 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3574 generate a reloc, then we just want to let the reloc addend set
3575 the value. We do not want to also stuff the addend into the
3576 object file. Including the addend in the object file works when
3577 doing a static link, because the linker will ignore the object
3578 file contents. However, the dynamic linker does not ignore the
3579 object file contents. */
3580 if (fixP->fx_addsy != NULL
3581 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3584 /* When generating PIC code, we do not want an addend for a reloc
3585 against a local symbol. We adjust fx_addnumber to cancel out the
3586 value already included in val, and to also cancel out the
3587 adjustment which bfd_install_relocation will create. */
3589 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3590 && fixP->fx_addsy != NULL
3591 && ! S_IS_COMMON (fixP->fx_addsy)
3592 && symbol_section_p (fixP->fx_addsy))
3593 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3595 /* When generating PIC code, we need to fiddle to get
3596 bfd_install_relocation to do the right thing for a PC relative
3597 reloc against a local symbol which we are going to keep. */
3599 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3600 && fixP->fx_addsy != NULL
3601 && (S_IS_EXTERNAL (fixP->fx_addsy)
3602 || S_IS_WEAK (fixP->fx_addsy))
3603 && S_IS_DEFINED (fixP->fx_addsy)
3604 && ! S_IS_COMMON (fixP->fx_addsy))
3607 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3611 /* If this is a data relocation, just output VAL. */
3613 if (fixP->fx_r_type == BFD_RELOC_8)
3615 md_number_to_chars (buf, val, 1);
3617 else if (fixP->fx_r_type == BFD_RELOC_16
3618 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3620 md_number_to_chars (buf, val, 2);
3622 else if (fixP->fx_r_type == BFD_RELOC_32
3623 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3624 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3626 md_number_to_chars (buf, val, 4);
3628 else if (fixP->fx_r_type == BFD_RELOC_64
3629 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3631 md_number_to_chars (buf, val, 8);
3633 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3634 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3641 /* It's a relocation against an instruction. */
3643 if (INSN_BIG_ENDIAN)
3644 insn = bfd_getb32 ((unsigned char *) buf);
3646 insn = bfd_getl32 ((unsigned char *) buf);
3648 switch (fixP->fx_r_type)
3650 case BFD_RELOC_32_PCREL_S2:
3652 /* FIXME: This increment-by-one deserves a comment of why it's
3654 if (! sparc_pic_code
3655 || fixP->fx_addsy == NULL
3656 || symbol_section_p (fixP->fx_addsy))
3659 insn |= val & 0x3fffffff;
3661 /* See if we have a delay slot. In that case we attempt to
3662 optimize several cases transforming CALL instructions
3663 into branches. But we can only do that if the relocation
3664 can be completely resolved here, i.e. if no undefined
3665 symbol is associated with it. */
3666 if (sparc_relax && fixP->fx_addsy == NULL
3667 && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3671 #define XCC (2 << 20)
3672 #define COND(x) (((x)&0xf)<<25)
3673 #define CONDA COND(0x8)
3674 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3675 #define INSN_BA (F2(0,2) | CONDA)
3676 #define INSN_OR F3(2, 0x2, 0)
3677 #define INSN_NOP F2(0,4)
3681 /* If the instruction is a call with either:
3683 arithmetic instruction with rd == %o7
3684 where rs1 != %o7 and rs2 if it is register != %o7
3685 then we can optimize if the call destination is near
3686 by changing the call into a branch always. */
3687 if (INSN_BIG_ENDIAN)
3688 delay = bfd_getb32 ((unsigned char *) buf + 4);
3690 delay = bfd_getl32 ((unsigned char *) buf + 4);
3691 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3693 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3694 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3695 || ((delay & RD (~0)) != RD (O7))))
3697 if ((delay & RS1 (~0)) == RS1 (O7)
3698 || ((delay & F3I (~0)) == 0
3699 && (delay & RS2 (~0)) == RS2 (O7)))
3701 /* Ensure the branch will fit into simm22. */
3702 if ((val & 0x3fe00000)
3703 && (val & 0x3fe00000) != 0x3fe00000)
3705 /* Check if the arch is v9 and branch will fit
3707 if (((val & 0x3c0000) == 0
3708 || (val & 0x3c0000) == 0x3c0000)
3709 && (sparc_arch_size == 64
3710 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3712 insn = INSN_BPA | (val & 0x7ffff);
3715 insn = INSN_BA | (val & 0x3fffff);
3716 if (fixP->fx_where >= 4
3717 && ((delay & (0xffffffff ^ RS1 (~0)))
3718 == (INSN_OR | RD (O7) | RS2 (G0))))
3723 if (INSN_BIG_ENDIAN)
3724 setter = bfd_getb32 ((unsigned char *) buf - 4);
3726 setter = bfd_getl32 ((unsigned char *) buf - 4);
3727 if ((setter & (0xffffffff ^ RD (~0)))
3728 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3735 If call foo was replaced with ba, replace
3736 or %rN, %g0, %o7 with nop. */
3737 reg = (delay & RS1 (~0)) >> 14;
3738 if (reg != ((setter & RD (~0)) >> 25)
3739 || reg == G0 || reg == O7)
3742 if (INSN_BIG_ENDIAN)
3743 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3745 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3750 case BFD_RELOC_SPARC_11:
3751 if (! in_signed_range (val, 0x7ff))
3752 as_bad_where (fixP->fx_file, fixP->fx_line,
3753 _("relocation overflow"));
3754 insn |= val & 0x7ff;
3757 case BFD_RELOC_SPARC_10:
3758 if (! in_signed_range (val, 0x3ff))
3759 as_bad_where (fixP->fx_file, fixP->fx_line,
3760 _("relocation overflow"));
3761 insn |= val & 0x3ff;
3764 case BFD_RELOC_SPARC_7:
3765 if (! in_bitfield_range (val, 0x7f))
3766 as_bad_where (fixP->fx_file, fixP->fx_line,
3767 _("relocation overflow"));
3771 case BFD_RELOC_SPARC_6:
3772 if (! in_bitfield_range (val, 0x3f))
3773 as_bad_where (fixP->fx_file, fixP->fx_line,
3774 _("relocation overflow"));
3778 case BFD_RELOC_SPARC_5:
3779 if (! in_bitfield_range (val, 0x1f))
3780 as_bad_where (fixP->fx_file, fixP->fx_line,
3781 _("relocation overflow"));
3785 case BFD_RELOC_SPARC_WDISP10:
3788 || val <= -(offsetT) 0x808)
3789 as_bad_where (fixP->fx_file, fixP->fx_line,
3790 _("relocation overflow"));
3791 /* FIXME: The +1 deserves a comment. */
3792 val = (val >> 2) + 1;
3793 insn |= ((val & 0x300) << 11)
3794 | ((val & 0xff) << 5);
3797 case BFD_RELOC_SPARC_WDISP16:
3800 || val <= -(offsetT) 0x20008)
3801 as_bad_where (fixP->fx_file, fixP->fx_line,
3802 _("relocation overflow"));
3803 /* FIXME: The +1 deserves a comment. */
3804 val = (val >> 2) + 1;
3805 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3808 case BFD_RELOC_SPARC_WDISP19:
3811 || val <= -(offsetT) 0x100008)
3812 as_bad_where (fixP->fx_file, fixP->fx_line,
3813 _("relocation overflow"));
3814 /* FIXME: The +1 deserves a comment. */
3815 val = (val >> 2) + 1;
3816 insn |= val & 0x7ffff;
3819 case BFD_RELOC_SPARC_HH22:
3820 val = BSR (val, 32);
3823 case BFD_RELOC_SPARC_LM22:
3824 case BFD_RELOC_HI22:
3825 if (!fixP->fx_addsy)
3826 insn |= (val >> 10) & 0x3fffff;
3828 /* FIXME: Need comment explaining why we do this. */
3832 case BFD_RELOC_SPARC22:
3833 if (val & ~0x003fffff)
3834 as_bad_where (fixP->fx_file, fixP->fx_line,
3835 _("relocation overflow"));
3836 insn |= (val & 0x3fffff);
3839 case BFD_RELOC_SPARC_HM10:
3840 val = BSR (val, 32);
3843 case BFD_RELOC_LO10:
3844 if (!fixP->fx_addsy)
3845 insn |= val & 0x3ff;
3847 /* FIXME: Need comment explaining why we do this. */
3851 case BFD_RELOC_SPARC_OLO10:
3853 val += fixP->tc_fix_data;
3856 case BFD_RELOC_SPARC13:
3857 if (! in_signed_range (val, 0x1fff))
3858 as_bad_where (fixP->fx_file, fixP->fx_line,
3859 _("relocation overflow"));
3860 insn |= val & 0x1fff;
3863 case BFD_RELOC_SPARC_WDISP22:
3864 val = (val >> 2) + 1;
3866 case BFD_RELOC_SPARC_BASE22:
3867 insn |= val & 0x3fffff;
3870 case BFD_RELOC_SPARC_H34:
3871 if (!fixP->fx_addsy)
3875 insn |= tval & 0x3fffff;
3879 case BFD_RELOC_SPARC_H44:
3880 if (!fixP->fx_addsy)
3884 insn |= tval & 0x3fffff;
3888 case BFD_RELOC_SPARC_M44:
3889 if (!fixP->fx_addsy)
3890 insn |= (val >> 12) & 0x3ff;
3893 case BFD_RELOC_SPARC_L44:
3894 if (!fixP->fx_addsy)
3895 insn |= val & 0xfff;
3898 case BFD_RELOC_SPARC_HIX22:
3899 if (!fixP->fx_addsy)
3901 val ^= ~(offsetT) 0;
3902 insn |= (val >> 10) & 0x3fffff;
3906 case BFD_RELOC_SPARC_LOX10:
3907 if (!fixP->fx_addsy)
3908 insn |= 0x1c00 | (val & 0x3ff);
3911 case BFD_RELOC_NONE:
3913 as_bad_where (fixP->fx_file, fixP->fx_line,
3914 _("bad or unhandled relocation type: 0x%02x"),
3919 if (INSN_BIG_ENDIAN)
3920 bfd_putb32 (insn, (unsigned char *) buf);
3922 bfd_putl32 (insn, (unsigned char *) buf);
3925 /* Are we finished with this relocation now? */
3926 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3930 /* Translate internal representation of relocation info to BFD target
3934 tc_gen_reloc (asection *section, fixS *fixp)
3936 static arelent *relocs[3];
3938 bfd_reloc_code_real_type code;
3940 relocs[0] = reloc = XNEW (arelent);
3943 reloc->sym_ptr_ptr = XNEW (asymbol *);
3944 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3945 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3947 switch (fixp->fx_r_type)
3955 switch (fixp->fx_size)
3958 as_bad_where (fixp->fx_file, fixp->fx_line,
3959 _("can not do %d byte pc-relative relocation"),
3961 code = fixp->fx_r_type;
3964 case 1: code = BFD_RELOC_8_PCREL; break;
3965 case 2: code = BFD_RELOC_16_PCREL; break;
3966 case 4: code = BFD_RELOC_32_PCREL; break;
3968 case 8: code = BFD_RELOC_64_PCREL; break;
3972 fixp->fx_addnumber = fixp->fx_offset;
3976 case BFD_RELOC_HI22:
3977 case BFD_RELOC_LO10:
3978 case BFD_RELOC_32_PCREL_S2:
3979 case BFD_RELOC_SPARC13:
3980 case BFD_RELOC_SPARC22:
3981 case BFD_RELOC_SPARC_PC22:
3982 case BFD_RELOC_SPARC_PC10:
3983 case BFD_RELOC_SPARC_BASE13:
3984 case BFD_RELOC_SPARC_WDISP10:
3985 case BFD_RELOC_SPARC_WDISP16:
3986 case BFD_RELOC_SPARC_WDISP19:
3987 case BFD_RELOC_SPARC_WDISP22:
3988 case BFD_RELOC_SPARC_5:
3989 case BFD_RELOC_SPARC_6:
3990 case BFD_RELOC_SPARC_7:
3991 case BFD_RELOC_SPARC_10:
3992 case BFD_RELOC_SPARC_11:
3993 case BFD_RELOC_SPARC_HH22:
3994 case BFD_RELOC_SPARC_HM10:
3995 case BFD_RELOC_SPARC_LM22:
3996 case BFD_RELOC_SPARC_PC_HH22:
3997 case BFD_RELOC_SPARC_PC_HM10:
3998 case BFD_RELOC_SPARC_PC_LM22:
3999 case BFD_RELOC_SPARC_H34:
4000 case BFD_RELOC_SPARC_H44:
4001 case BFD_RELOC_SPARC_M44:
4002 case BFD_RELOC_SPARC_L44:
4003 case BFD_RELOC_SPARC_HIX22:
4004 case BFD_RELOC_SPARC_LOX10:
4005 case BFD_RELOC_SPARC_REV32:
4006 case BFD_RELOC_SPARC_OLO10:
4007 case BFD_RELOC_SPARC_UA16:
4008 case BFD_RELOC_SPARC_UA32:
4009 case BFD_RELOC_SPARC_UA64:
4010 case BFD_RELOC_8_PCREL:
4011 case BFD_RELOC_16_PCREL:
4012 case BFD_RELOC_32_PCREL:
4013 case BFD_RELOC_64_PCREL:
4014 case BFD_RELOC_SPARC_PLT32:
4015 case BFD_RELOC_SPARC_PLT64:
4016 case BFD_RELOC_VTABLE_ENTRY:
4017 case BFD_RELOC_VTABLE_INHERIT:
4018 case BFD_RELOC_SPARC_TLS_GD_HI22:
4019 case BFD_RELOC_SPARC_TLS_GD_LO10:
4020 case BFD_RELOC_SPARC_TLS_GD_ADD:
4021 case BFD_RELOC_SPARC_TLS_GD_CALL:
4022 case BFD_RELOC_SPARC_TLS_LDM_HI22:
4023 case BFD_RELOC_SPARC_TLS_LDM_LO10:
4024 case BFD_RELOC_SPARC_TLS_LDM_ADD:
4025 case BFD_RELOC_SPARC_TLS_LDM_CALL:
4026 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
4027 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
4028 case BFD_RELOC_SPARC_TLS_LDO_ADD:
4029 case BFD_RELOC_SPARC_TLS_IE_HI22:
4030 case BFD_RELOC_SPARC_TLS_IE_LO10:
4031 case BFD_RELOC_SPARC_TLS_IE_LD:
4032 case BFD_RELOC_SPARC_TLS_IE_LDX:
4033 case BFD_RELOC_SPARC_TLS_IE_ADD:
4034 case BFD_RELOC_SPARC_TLS_LE_HIX22:
4035 case BFD_RELOC_SPARC_TLS_LE_LOX10:
4036 case BFD_RELOC_SPARC_TLS_DTPOFF32:
4037 case BFD_RELOC_SPARC_TLS_DTPOFF64:
4038 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
4039 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
4040 case BFD_RELOC_SPARC_GOTDATA_OP:
4041 code = fixp->fx_r_type;
4048 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
4049 /* If we are generating PIC code, we need to generate a different
4053 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
4055 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
4058 #define GOTT_BASE "__GOTT_BASE__"
4059 #define GOTT_INDEX "__GOTT_INDEX__"
4062 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
4068 case BFD_RELOC_32_PCREL_S2:
4069 if (generic_force_reloc (fixp))
4070 code = BFD_RELOC_SPARC_WPLT30;
4072 case BFD_RELOC_HI22:
4073 code = BFD_RELOC_SPARC_GOT22;
4074 if (fixp->fx_addsy != NULL)
4076 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
4077 code = BFD_RELOC_SPARC_PC22;
4079 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
4080 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
4081 code = BFD_RELOC_HI22; /* Unchanged. */
4085 case BFD_RELOC_LO10:
4086 code = BFD_RELOC_SPARC_GOT10;
4087 if (fixp->fx_addsy != NULL)
4089 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
4090 code = BFD_RELOC_SPARC_PC10;
4092 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
4093 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
4094 code = BFD_RELOC_LO10; /* Unchanged. */
4098 case BFD_RELOC_SPARC13:
4099 code = BFD_RELOC_SPARC_GOT13;
4105 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
4107 /* Nothing is aligned in DWARF debugging sections. */
4108 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
4111 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
4112 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
4113 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
4117 if (code == BFD_RELOC_SPARC_OLO10)
4118 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
4120 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
4121 if (reloc->howto == 0)
4123 as_bad_where (fixp->fx_file, fixp->fx_line,
4124 _("internal error: can't export reloc type %d (`%s')"),
4125 fixp->fx_r_type, bfd_get_reloc_code_name (code));
4131 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4134 if (reloc->howto->pc_relative == 0
4135 || code == BFD_RELOC_SPARC_PC10
4136 || code == BFD_RELOC_SPARC_PC22)
4137 reloc->addend = fixp->fx_addnumber;
4138 else if (sparc_pic_code
4139 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
4140 && fixp->fx_addsy != NULL
4141 && (S_IS_EXTERNAL (fixp->fx_addsy)
4142 || S_IS_WEAK (fixp->fx_addsy))
4143 && S_IS_DEFINED (fixp->fx_addsy)
4144 && ! S_IS_COMMON (fixp->fx_addsy))
4145 reloc->addend = fixp->fx_addnumber;
4147 reloc->addend = fixp->fx_offset - reloc->address;
4149 #else /* elf or coff */
4151 if (code != BFD_RELOC_32_PCREL_S2
4152 && code != BFD_RELOC_SPARC_WDISP22
4153 && code != BFD_RELOC_SPARC_WDISP16
4154 && code != BFD_RELOC_SPARC_WDISP19
4155 && code != BFD_RELOC_SPARC_WDISP10
4156 && code != BFD_RELOC_SPARC_WPLT30
4157 && code != BFD_RELOC_SPARC_TLS_GD_CALL
4158 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
4159 reloc->addend = fixp->fx_addnumber;
4160 else if (symbol_section_p (fixp->fx_addsy))
4161 reloc->addend = (section->vma
4162 + fixp->fx_addnumber
4163 + md_pcrel_from (fixp));
4165 reloc->addend = fixp->fx_offset;
4168 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4169 on the same location. */
4170 if (code == BFD_RELOC_SPARC_OLO10)
4172 relocs[1] = reloc = XNEW (arelent);
4175 reloc->sym_ptr_ptr = XNEW (asymbol *);
4177 = symbol_get_bfdsym (section_symbol (absolute_section));
4178 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4179 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
4180 reloc->addend = fixp->tc_fix_data;
4186 /* We have no need to default values of symbols. */
4189 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
4194 /* Round up a section size to the appropriate boundary. */
4197 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
4200 /* This is not right for ELF; a.out wants it, and COFF will force
4201 the alignment anyways. */
4202 valueT align = ((valueT) 1
4203 << (valueT) bfd_get_section_alignment (stdoutput, segment));
4206 /* Turn alignment value into a mask. */
4208 newsize = (size + align) & ~align;
4215 /* Exactly what point is a PC-relative offset relative TO?
4216 On the sparc, they're relative to the address of the offset, plus
4217 its size. This gets us to the following instruction.
4218 (??? Is this right? FIXME-SOON) */
4220 md_pcrel_from (fixS *fixP)
4224 ret = fixP->fx_where + fixP->fx_frag->fr_address;
4225 if (! sparc_pic_code
4226 || fixP->fx_addsy == NULL
4227 || symbol_section_p (fixP->fx_addsy))
4228 ret += fixP->fx_size;
4232 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4243 for (shift = 0; (value & 1) == 0; value >>= 1)
4246 return (value == 1) ? shift : -1;
4249 /* Sort of like s_lcomm. */
4252 static int max_alignment = 15;
4256 s_reserve (int ignore ATTRIBUTE_UNUSED)
4266 c = get_symbol_name (&name);
4267 p = input_line_pointer;
4269 SKIP_WHITESPACE_AFTER_NAME ();
4271 if (*input_line_pointer != ',')
4273 as_bad (_("Expected comma after name"));
4274 ignore_rest_of_line ();
4278 ++input_line_pointer;
4280 if ((size = get_absolute_expression ()) < 0)
4282 as_bad (_("BSS length (%d.) <0! Ignored."), size);
4283 ignore_rest_of_line ();
4288 symbolP = symbol_find_or_make (name);
4291 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
4292 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
4294 as_bad (_("bad .reserve segment -- expected BSS segment"));
4298 if (input_line_pointer[2] == '.')
4299 input_line_pointer += 7;
4301 input_line_pointer += 6;
4304 if (*input_line_pointer == ',')
4306 ++input_line_pointer;
4309 if (*input_line_pointer == '\n')
4311 as_bad (_("missing alignment"));
4312 ignore_rest_of_line ();
4316 align = (int) get_absolute_expression ();
4319 if (align > max_alignment)
4321 align = max_alignment;
4322 as_warn (_("alignment too large; assuming %d"), align);
4328 as_bad (_("negative alignment"));
4329 ignore_rest_of_line ();
4335 temp = mylog2 (align);
4338 as_bad (_("alignment not a power of 2"));
4339 ignore_rest_of_line ();
4346 record_alignment (bss_section, align);
4351 if (!S_IS_DEFINED (symbolP)
4353 && S_GET_OTHER (symbolP) == 0
4354 && S_GET_DESC (symbolP) == 0
4361 segT current_seg = now_seg;
4362 subsegT current_subseg = now_subseg;
4364 /* Switch to bss. */
4365 subseg_set (bss_section, 1);
4369 frag_align (align, 0, 0);
4371 /* Detach from old frag. */
4372 if (S_GET_SEGMENT (symbolP) == bss_section)
4373 symbol_get_frag (symbolP)->fr_symbol = NULL;
4375 symbol_set_frag (symbolP, frag_now);
4376 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4377 (offsetT) size, (char *) 0);
4380 S_SET_SEGMENT (symbolP, bss_section);
4382 subseg_set (current_seg, current_subseg);
4385 S_SET_SIZE (symbolP, size);
4391 as_warn (_("Ignoring attempt to re-define symbol %s"),
4392 S_GET_NAME (symbolP));
4395 demand_empty_rest_of_line ();
4399 s_common (int ignore ATTRIBUTE_UNUSED)
4407 c = get_symbol_name (&name);
4408 /* Just after name is now '\0'. */
4409 p = input_line_pointer;
4411 SKIP_WHITESPACE_AFTER_NAME ();
4412 if (*input_line_pointer != ',')
4414 as_bad (_("Expected comma after symbol-name"));
4415 ignore_rest_of_line ();
4420 input_line_pointer++;
4422 if ((temp = get_absolute_expression ()) < 0)
4424 as_bad (_(".COMMon length (%lu) out of range ignored"),
4425 (unsigned long) temp);
4426 ignore_rest_of_line ();
4431 symbolP = symbol_find_or_make (name);
4433 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4435 as_bad (_("Ignoring attempt to re-define symbol"));
4436 ignore_rest_of_line ();
4439 if (S_GET_VALUE (symbolP) != 0)
4441 if (S_GET_VALUE (symbolP) != (valueT) size)
4443 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4444 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4450 S_SET_VALUE (symbolP, (valueT) size);
4451 S_SET_EXTERNAL (symbolP);
4454 know (symbol_get_frag (symbolP) == &zero_address_frag);
4455 if (*input_line_pointer != ',')
4457 as_bad (_("Expected comma after common length"));
4458 ignore_rest_of_line ();
4461 input_line_pointer++;
4463 if (*input_line_pointer != '"')
4465 temp = get_absolute_expression ();
4468 if (temp > max_alignment)
4470 temp = max_alignment;
4471 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4477 as_bad (_("negative alignment"));
4478 ignore_rest_of_line ();
4483 if (symbol_get_obj (symbolP)->local)
4490 old_subsec = now_subseg;
4495 align = mylog2 (temp);
4499 as_bad (_("alignment not a power of 2"));
4500 ignore_rest_of_line ();
4504 record_alignment (bss_section, align);
4505 subseg_set (bss_section, 0);
4507 frag_align (align, 0, 0);
4508 if (S_GET_SEGMENT (symbolP) == bss_section)
4509 symbol_get_frag (symbolP)->fr_symbol = 0;
4510 symbol_set_frag (symbolP, frag_now);
4511 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4512 (offsetT) size, (char *) 0);
4514 S_SET_SEGMENT (symbolP, bss_section);
4515 S_CLEAR_EXTERNAL (symbolP);
4516 S_SET_SIZE (symbolP, size);
4517 subseg_set (old_sec, old_subsec);
4520 #endif /* OBJ_ELF */
4523 S_SET_VALUE (symbolP, (valueT) size);
4525 S_SET_ALIGN (symbolP, temp);
4526 S_SET_SIZE (symbolP, size);
4528 S_SET_EXTERNAL (symbolP);
4529 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4534 input_line_pointer++;
4535 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4536 if (*input_line_pointer == '.')
4537 input_line_pointer++;
4538 /* @@ Some say data, some say bss. */
4539 if (strncmp (input_line_pointer, "bss\"", 4)
4540 && strncmp (input_line_pointer, "data\"", 5))
4542 while (*--input_line_pointer != '"')
4544 input_line_pointer--;
4545 goto bad_common_segment;
4547 while (*input_line_pointer++ != '"')
4549 goto allocate_common;
4552 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4554 demand_empty_rest_of_line ();
4559 p = input_line_pointer;
4560 while (*p && *p != '\n')
4564 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4566 input_line_pointer = p;
4567 ignore_rest_of_line ();
4572 /* Handle the .empty pseudo-op. This suppresses the warnings about
4573 invalid delay slot usage. */
4576 s_empty (int ignore ATTRIBUTE_UNUSED)
4578 /* The easy way to implement is to just forget about the last
4584 s_seg (int ignore ATTRIBUTE_UNUSED)
4587 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4589 input_line_pointer += 6;
4593 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4595 input_line_pointer += 6;
4599 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4601 input_line_pointer += 7;
4605 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4607 input_line_pointer += 5;
4608 /* We only support 2 segments -- text and data -- for now, so
4609 things in the "bss segment" will have to go into data for now.
4610 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4611 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4614 as_bad (_("Unknown segment type"));
4615 demand_empty_rest_of_line ();
4621 subseg_set (data_section, 1);
4622 demand_empty_rest_of_line ();
4626 s_proc (int ignore ATTRIBUTE_UNUSED)
4628 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4630 ++input_line_pointer;
4632 ++input_line_pointer;
4635 /* This static variable is set by s_uacons to tell sparc_cons_align
4636 that the expression does not need to be aligned. */
4638 static int sparc_no_align_cons = 0;
4640 /* This handles the unaligned space allocation pseudo-ops, such as
4641 .uaword. .uaword is just like .word, but the value does not need
4645 s_uacons (int bytes)
4647 /* Tell sparc_cons_align not to align this value. */
4648 sparc_no_align_cons = 1;
4650 sparc_no_align_cons = 0;
4653 /* This handles the native word allocation pseudo-op .nword.
4654 For sparc_arch_size 32 it is equivalent to .word, for
4655 sparc_arch_size 64 it is equivalent to .xword. */
4658 s_ncons (int bytes ATTRIBUTE_UNUSED)
4660 cons (sparc_arch_size == 32 ? 4 : 8);
4664 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4668 .register %g[2367],{#scratch|symbolname|#ignore}
4672 s_register (int ignore ATTRIBUTE_UNUSED)
4679 if (input_line_pointer[0] != '%'
4680 || input_line_pointer[1] != 'g'
4681 || ((input_line_pointer[2] & ~1) != '2'
4682 && (input_line_pointer[2] & ~1) != '6')
4683 || input_line_pointer[3] != ',')
4684 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4685 reg = input_line_pointer[2] - '0';
4686 input_line_pointer += 4;
4688 if (*input_line_pointer == '#')
4690 ++input_line_pointer;
4691 c = get_symbol_name (®name);
4692 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4693 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4694 if (regname[0] == 'i')
4697 regname = (char *) "";
4701 c = get_symbol_name (®name);
4704 if (sparc_arch_size == 64)
4708 if ((regname && globals[reg] != (symbolS *) 1
4709 && strcmp (S_GET_NAME (globals[reg]), regname))
4710 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4711 as_bad (_("redefinition of global register"));
4715 if (regname == NULL)
4716 globals[reg] = (symbolS *) 1;
4721 if (symbol_find (regname))
4722 as_bad (_("Register symbol %s already defined."),
4725 globals[reg] = symbol_make (regname);
4726 flags = symbol_get_bfdsym (globals[reg])->flags;
4728 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4729 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4730 flags |= BSF_GLOBAL;
4731 symbol_get_bfdsym (globals[reg])->flags = flags;
4732 S_SET_VALUE (globals[reg], (valueT) reg);
4733 S_SET_ALIGN (globals[reg], reg);
4734 S_SET_SIZE (globals[reg], 0);
4735 /* Although we actually want undefined_section here,
4736 we have to use absolute_section, because otherwise
4737 generic as code will make it a COM section.
4738 We fix this up in sparc_adjust_symtab. */
4739 S_SET_SEGMENT (globals[reg], absolute_section);
4740 S_SET_OTHER (globals[reg], 0);
4741 elf_symbol (symbol_get_bfdsym (globals[reg]))
4742 ->internal_elf_sym.st_info =
4743 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4744 elf_symbol (symbol_get_bfdsym (globals[reg]))
4745 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4750 (void) restore_line_pointer (c);
4752 demand_empty_rest_of_line ();
4755 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4756 symbols which need it. */
4759 sparc_adjust_symtab (void)
4763 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4765 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4766 ->internal_elf_sym.st_info) != STT_REGISTER)
4769 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4770 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4773 S_SET_SEGMENT (sym, undefined_section);
4778 /* If the --enforce-aligned-data option is used, we require .word,
4779 et. al., to be aligned correctly. We do it by setting up an
4780 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4781 no unexpected alignment was introduced.
4783 The SunOS and Solaris native assemblers enforce aligned data by
4784 default. We don't want to do that, because gcc can deliberately
4785 generate misaligned data if the packed attribute is used. Instead,
4786 we permit misaligned data by default, and permit the user to set an
4787 option to check for it. */
4790 sparc_cons_align (int nbytes)
4794 /* Only do this if we are enforcing aligned data. */
4795 if (! enforce_aligned_data)
4798 /* Don't align if this is an unaligned pseudo-op. */
4799 if (sparc_no_align_cons)
4802 nalign = mylog2 (nbytes);
4806 gas_assert (nalign > 0);
4808 if (now_seg == absolute_section)
4810 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4811 as_bad (_("misaligned data"));
4815 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4816 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4818 record_alignment (now_seg, nalign);
4821 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4824 sparc_handle_align (fragS *fragp)
4829 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4831 switch (fragp->fr_type)
4835 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4839 p = fragp->fr_literal + fragp->fr_fix;
4850 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4852 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4853 if (INSN_BIG_ENDIAN)
4854 number_to_chars_bigendian (p, wval, 4);
4856 number_to_chars_littleendian (p, wval, 4);
4862 if (INSN_BIG_ENDIAN)
4863 number_to_chars_bigendian (p, 0x01000000, 4);
4865 number_to_chars_littleendian (p, 0x01000000, 4);
4867 fragp->fr_fix += fix;
4877 /* Some special processing for a Sparc ELF file. */
4880 sparc_elf_final_processing (void)
4882 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4883 sort of BFD interface for this. */
4884 if (sparc_arch_size == 64)
4886 switch (sparc_memory_model)
4889 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4892 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4898 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4899 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4900 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4901 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4902 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4903 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4907 sparc_cons (expressionS *exp, int size)
4910 const char *sparc_cons_special_reloc = NULL;
4913 save = input_line_pointer;
4914 if (input_line_pointer[0] == '%'
4915 && input_line_pointer[1] == 'r'
4916 && input_line_pointer[2] == '_')
4918 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4920 input_line_pointer += 7;
4921 sparc_cons_special_reloc = "disp";
4923 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4925 if (size != 4 && size != 8)
4926 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4929 input_line_pointer += 6;
4930 sparc_cons_special_reloc = "plt";
4933 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4935 if (size != 4 && size != 8)
4936 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4939 input_line_pointer += 13;
4940 sparc_cons_special_reloc = "tls_dtpoff";
4943 if (sparc_cons_special_reloc)
4950 if (*input_line_pointer != '8')
4952 input_line_pointer--;
4955 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4959 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4963 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4973 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4974 sparc_cons_special_reloc, size * 8, size);
4978 input_line_pointer += 2;
4979 if (*input_line_pointer != '(')
4981 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4982 sparc_cons_special_reloc, size * 8);
4989 input_line_pointer = save;
4990 sparc_cons_special_reloc = NULL;
4995 char *end = ++input_line_pointer;
4998 while (! is_end_of_line[(c = *end)])
5012 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5013 sparc_cons_special_reloc, size * 8);
5019 if (input_line_pointer != end)
5021 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5022 sparc_cons_special_reloc, size * 8);
5026 input_line_pointer++;
5028 c = *input_line_pointer;
5029 if (! is_end_of_line[c] && c != ',')
5030 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
5031 sparc_cons_special_reloc, size * 8);
5037 if (sparc_cons_special_reloc == NULL)
5039 return sparc_cons_special_reloc;
5044 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5045 reloc for a cons. We could use the definition there, except that
5046 we want to handle little endian relocs specially. */
5049 cons_fix_new_sparc (fragS *frag,
5051 unsigned int nbytes,
5053 const char *sparc_cons_special_reloc)
5055 bfd_reloc_code_real_type r;
5057 r = (nbytes == 1 ? BFD_RELOC_8 :
5058 (nbytes == 2 ? BFD_RELOC_16 :
5059 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
5061 if (target_little_endian_data
5063 && now_seg->flags & SEC_ALLOC)
5064 r = BFD_RELOC_SPARC_REV32;
5067 /* The Solaris linker does not allow R_SPARC_UA64
5068 relocations for 32-bit executables. */
5069 if (!target_little_endian_data
5070 && sparc_arch_size != 64
5071 && r == BFD_RELOC_64)
5075 if (sparc_cons_special_reloc)
5077 if (*sparc_cons_special_reloc == 'd')
5080 case 1: r = BFD_RELOC_8_PCREL; break;
5081 case 2: r = BFD_RELOC_16_PCREL; break;
5082 case 4: r = BFD_RELOC_32_PCREL; break;
5083 case 8: r = BFD_RELOC_64_PCREL; break;
5086 else if (*sparc_cons_special_reloc == 'p')
5089 case 4: r = BFD_RELOC_SPARC_PLT32; break;
5090 case 8: r = BFD_RELOC_SPARC_PLT64; break;
5095 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
5096 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
5099 else if (sparc_no_align_cons
5100 || /* PR 20803 - relocs in the .eh_frame section
5101 need to support unaligned access. */
5102 strcmp (now_seg->name, ".eh_frame") == 0)
5106 case 2: r = BFD_RELOC_SPARC_UA16; break;
5107 case 4: r = BFD_RELOC_SPARC_UA32; break;
5109 /* The Solaris linker does not allow R_SPARC_UA64
5110 relocations for 32-bit executables. */
5111 case 8: r = sparc_arch_size == 64 ?
5112 BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break;
5114 case 8: r = BFD_RELOC_SPARC_UA64; break;
5120 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
5124 sparc_cfi_frame_initial_instructions (void)
5126 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
5130 sparc_regname_to_dw2regnum (char *regname)
5140 case 'g': i = 0; break;
5141 case 'o': i = 1; break;
5142 case 'l': i = 2; break;
5143 case 'i': i = 3; break;
5144 default: i = -1; break;
5148 if (regname[1] < '0' || regname[1] > '8' || regname[2])
5150 return i * 8 + regname[1] - '0';
5152 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
5154 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
5156 if (regname[0] == 'f' || regname[0] == 'r')
5158 unsigned int regnum;
5160 regnum = strtoul (regname + 1, &q, 10);
5161 if (q == NULL || *q)
5163 if (regnum >= ((regname[0] == 'f'
5164 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
5167 if (regname[0] == 'f')
5170 if (regnum >= 64 && (regnum & 1))
5179 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
5181 sparc_no_align_cons = 1;
5182 emit_expr_with_reloc (exp, nbytes, "disp");
5183 sparc_no_align_cons = 0;