1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode **);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static char *default_arch = DEFAULT_ARCH;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen;
84 static bfd_uint64_t hwcap_allowed;
86 static int architecture_requested;
87 static int warn_on_bump;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data;
106 extern int target_big_endian;
108 static int target_little_endian_data;
110 /* Symbols for global registers on v9. */
111 static symbolS *globals[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control *op_hash;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table[] =
143 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common, 0},
145 {"empty", s_empty, 0},
146 {"global", s_globl, 0},
148 {"nword", s_ncons, 0},
149 {"optim", s_ignore, 0},
151 {"reserve", s_reserve, 0},
153 {"skip", s_space, 0},
156 {"uahalf", s_uacons, 2},
157 {"uaword", s_uacons, 4},
158 {"uaxword", s_uacons, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons, 2},
162 {"4byte", s_uacons, 4},
163 {"8byte", s_uacons, 8},
164 {"register", s_register, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars[] = "#";
184 const char line_separator_chars[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode;
205 struct nlist *nlistp;
209 bfd_reloc_code_real_type reloc;
212 struct sparc_it the_insn, set_insn;
214 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
222 v8plusa, v9, v9a, v9b, v9_64};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch {
246 enum sparc_arch_types arch_type;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size;
250 /* Allowable arg to -A? */
254 } sparc_arch_table[] = {
255 { "v6", "v6", v6, 0, 1, 0, 0 },
256 { "v7", "v7", v7, 0, 1, 0, 0 },
257 { "v8", "v8", v8, 32, 1, HWS_V8, 0 },
258 { "v8a", "v8", v8, 32, 1, HWS_V8, 0 },
259 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
260 { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 },
261 { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 },
262 { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 },
263 { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 },
264 { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
265 { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
267 { "sparc4", "v9b", v9, 0, 1, HWS_VV, 0 },
268 { "sparc5", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
270 { "leon", "leon", leon, 32, 1, HWS_V8, 0 },
271 { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 },
272 { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 },
273 { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 },
275 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
276 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 },
277 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 },
278 { "v8plusc", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
279 { "v8plusd", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
280 { "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
281 { "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
282 { "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
284 { "v9", "v9", v9, 0, 1, HWS_V9, 0 },
285 { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 },
286 { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 },
287 { "v9c", "v9b", v9, 0, 1, HWS_VC, 0 },
288 { "v9d", "v9b", v9, 0, 1, HWS_VD, 0 },
289 { "v9e", "v9b", v9, 0, 1, HWS_VE, 0 },
290 { "v9v", "v9b", v9, 0, 1, HWS_VV, 0 },
291 { "v9m", "v9b", v9, 0, 1, HWS_VM, HWS2_VM },
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 },
296 { NULL, NULL, v8, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type;
302 static struct sparc_arch *
303 lookup_arch (char *name)
305 struct sparc_arch *sa;
307 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
308 if (strcmp (sa->name, name) == 0)
310 if (sa->name == NULL)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch *sa = lookup_arch (default_arch);
324 || sa->default_arch_size == 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
328 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size = sparc_arch_size = sa->default_arch_size;
332 default_arch_type = sa->arch_type;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian)
351 return "a.out-sunos-big";
352 else if (default_arch_type == sparc86x && target_little_endian_data)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts = "A:K:VQ:sq";
443 const char *md_shortopts = "A:k";
445 const char *md_shortopts = "A:";
448 struct option md_longopts[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument, NULL, OPTION_BUMP},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument, NULL, OPTION_SPARC},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument, NULL, OPTION_XARCH},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument, NULL, OPTION_32},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument, NULL, OPTION_64},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument, NULL, OPTION_TSO},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument, NULL, OPTION_PSO},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument, NULL, OPTION_RMO},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument, NULL, OPTION_RELAX},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
487 {NULL, no_argument, NULL, 0}
490 size_t md_longopts_size = sizeof (md_longopts);
493 md_parse_option (int c, char *arg)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p)
498 init_default_arch ();
504 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
509 if (!strncmp (arg, "v9", 2))
510 md_parse_option (OPTION_64, NULL);
513 if (!strncmp (arg, "v8", 2)
514 || !strncmp (arg, "v7", 2)
515 || !strncmp (arg, "v6", 2)
516 || !strcmp (arg, "sparclet")
517 || !strcmp (arg, "sparclite")
518 || !strcmp (arg, "sparc86x"))
519 md_parse_option (OPTION_32, NULL);
526 struct sparc_arch *sa;
527 enum sparc_opcode_arch_val opcode_arch;
529 sa = lookup_arch (arg);
531 || ! sa->user_option_p)
533 if (c == OPTION_XARCH)
534 as_bad (_("invalid architecture -xarch=%s"), arg);
536 as_bad (_("invalid architecture -A%s"), arg);
540 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
541 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch > max_architecture)
546 max_architecture = opcode_arch;
548 |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed;
549 architecture_requested = 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA:
558 enforce_aligned_data = 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN:
563 target_big_endian = 0;
564 if (default_arch_type != sparclet)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA:
568 target_little_endian_data = 1;
569 target_big_endian = 0;
570 if (default_arch_type != sparc86x
571 && default_arch_type != v9)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN:
575 target_big_endian = 1;
589 const char **list, **l;
591 sparc_arch_size = c == OPTION_32 ? 32 : 64;
592 list = bfd_target_list ();
593 for (l = list; *l != NULL; l++)
595 if (sparc_arch_size == 32)
597 if (CONST_STRNEQ (*l, "elf32-sparc"))
602 if (CONST_STRNEQ (*l, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size == 64
612 && max_architecture < SPARC_OPCODE_ARCH_V9)
613 max_architecture = SPARC_OPCODE_ARCH_V9;
618 sparc_memory_model = MM_TSO;
622 sparc_memory_model = MM_PSO;
626 sparc_memory_model = MM_RMO;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS:
654 no_undeclared_regs = 1;
657 case OPTION_UNDECLARED_REGS:
658 no_undeclared_regs = 0;
666 case OPTION_NO_RELAX:
678 md_show_usage (FILE *stream)
680 const struct sparc_arch *arch;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p)
686 init_default_arch ();
688 fprintf (stream, _("SPARC options:\n"));
690 for (arch = &sparc_arch_table[0]; arch->name; arch++)
692 if (!arch->user_option_p)
694 if (arch != &sparc_arch_table[0])
695 fprintf (stream, " | ");
696 if (column + strlen (arch->name) > 70)
699 fputc ('\n', stream);
701 column += 5 + 2 + strlen (arch->name);
702 fprintf (stream, "-A%s", arch->name);
704 for (arch = &sparc_arch_table[0]; arch->name; arch++)
706 if (!arch->user_option_p)
708 fprintf (stream, " | ");
709 if (column + strlen (arch->name) > 65)
712 fputc ('\n', stream);
714 column += 5 + 7 + strlen (arch->name);
715 fprintf (stream, "-xarch=%s", arch->name);
717 fprintf (stream, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream, _("\
726 -k generate PIC\n"));
729 fprintf (stream, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream, _("\
733 [default is %d]\n"), default_arch_size);
734 fprintf (stream, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream, _("\
739 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
740 fprintf (stream, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table[] =
809 {"", -1}, /* End marker. */
812 struct priv_reg_entry hpriv_reg_table[] =
819 {"hstick_offset", 28},
820 {"hstick_enable", 29},
822 {"", -1}, /* End marker. */
825 /* v9a specific asrs. This table is ordered by initial
826 letter, in reverse. */
828 struct priv_reg_entry v9a_asr_table[] =
831 {"sys_tick_cmpr", 25},
835 {"softint_clear", 21},
846 {"clear_softint", 21},
847 {"", -1}, /* End marker. */
851 cmp_reg_entry (const void *parg, const void *qarg)
853 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
854 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
856 return strcmp (q->name, p->name);
859 /* This function is called once, at assembler startup time. It should
860 set up all the tables, etc. that the MD part of the assembler will
866 register const char *retval = NULL;
868 register unsigned int i = 0;
870 /* We don't get a chance to initialize anything before md_parse_option
871 is called, and it may not be called, so handle default initialization
872 now if not already done. */
873 if (! default_init_p)
874 init_default_arch ();
876 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
877 op_hash = hash_new ();
879 while (i < (unsigned int) sparc_num_opcodes)
881 const char *name = sparc_opcodes[i].name;
882 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
885 as_bad (_("Internal error: can't hash `%s': %s\n"),
886 sparc_opcodes[i].name, retval);
891 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
893 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
894 sparc_opcodes[i].name, sparc_opcodes[i].args);
899 while (i < (unsigned int) sparc_num_opcodes
900 && !strcmp (sparc_opcodes[i].name, name));
903 for (i = 0; native_op_table[i].name; i++)
905 const struct sparc_opcode *insn;
906 char *name = ((sparc_arch_size == 32)
907 ? native_op_table[i].name32
908 : native_op_table[i].name64);
909 insn = (struct sparc_opcode *) hash_find (op_hash, name);
912 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
913 name, native_op_table[i].name);
918 retval = hash_insert (op_hash, native_op_table[i].name,
922 as_bad (_("Internal error: can't hash `%s': %s\n"),
923 sparc_opcodes[i].name, retval);
930 as_fatal (_("Broken assembler. No assembly attempted."));
932 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
933 sizeof (priv_reg_table[0]), cmp_reg_entry);
935 /* If -bump, record the architecture level at which we start issuing
936 warnings. The behaviour is different depending upon whether an
937 architecture was explicitly specified. If it wasn't, we issue warnings
938 for all upwards bumps. If it was, we don't start issuing warnings until
939 we need to bump beyond the requested architecture or when we bump between
940 conflicting architectures. */
943 && architecture_requested)
945 /* `max_architecture' records the requested architecture.
946 Issue warnings if we go above it. */
947 warn_after_architecture = max_architecture;
950 /* Find the highest architecture level that doesn't conflict with
951 the requested one. */
954 || !architecture_requested)
956 enum sparc_opcode_arch_val current_max_architecture
959 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
960 max_architecture > warn_after_architecture;
962 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
963 current_max_architecture))
968 /* Called after all assembly has been done. */
973 unsigned long mach = bfd_mach_sparc;
976 if (sparc_arch_size == 64)
977 switch (current_architecture)
979 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
980 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
981 default: mach = bfd_mach_sparc_v9; break;
984 switch (current_architecture)
986 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
987 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
988 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
989 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
990 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
991 be but for now it is (since that's the way it's always been
995 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
997 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
998 hwcaps = hwcap_seen & U0xffffffff;
999 hwcaps2 = hwcap_seen >> 32;
1002 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps);
1004 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2);
1008 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1011 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
1015 /* Sign-extend the value from the architecture word size, so that
1016 0xffffffff is always considered -1 on sparc32. */
1017 if (sparc_arch_size == 32)
1019 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
1020 val = ((val & U0xffffffff) ^ sign) - sign;
1029 /* Return non-zero if VAL is in the range 0 to MAX. */
1032 in_unsigned_range (bfd_vma val, bfd_vma max)
1039 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1040 (e.g. -15 to +31). */
1043 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
1049 if (val < ~(max >> 1))
1055 sparc_ffs (unsigned int mask)
1062 for (i = 0; (mask & 1) == 0; ++i)
1067 /* Implement big shift right. */
1069 BSR (bfd_vma val, int amount)
1071 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1072 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1073 return val >> amount;
1076 /* For communication between sparc_ip and get_expression. */
1077 static char *expr_end;
1079 /* Values for `special_case'.
1080 Instructions that require wierd handling because they're longer than
1082 #define SPECIAL_CASE_NONE 0
1083 #define SPECIAL_CASE_SET 1
1084 #define SPECIAL_CASE_SETSW 2
1085 #define SPECIAL_CASE_SETX 3
1086 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1087 #define SPECIAL_CASE_FDIV 4
1089 /* Bit masks of various insns. */
1090 #define NOP_INSN 0x01000000
1091 #define OR_INSN 0x80100000
1092 #define XOR_INSN 0x80180000
1093 #define FMOVS_INSN 0x81A00020
1094 #define SETHI_INSN 0x01000000
1095 #define SLLX_INSN 0x81281000
1096 #define SRA_INSN 0x81380000
1098 /* The last instruction to be assembled. */
1099 static const struct sparc_opcode *last_insn;
1100 /* The assembled opcode of `last_insn'. */
1101 static unsigned long last_opcode;
1103 /* Handle the set and setuw synthetic instructions. */
1106 synthetize_setuw (const struct sparc_opcode *insn)
1108 int need_hi22_p = 0;
1109 int rd = (the_insn.opcode & RD (~0)) >> 25;
1111 if (the_insn.exp.X_op == O_constant)
1113 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1115 if (sizeof (offsetT) > 4
1116 && (the_insn.exp.X_add_number < 0
1117 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1118 as_warn (_("set: number not in 0..4294967295 range"));
1122 if (sizeof (offsetT) > 4
1123 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1124 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1125 as_warn (_("set: number not in -2147483648..4294967295 range"));
1126 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1130 /* See if operand is absolute and small; skip sethi if so. */
1131 if (the_insn.exp.X_op != O_constant
1132 || the_insn.exp.X_add_number >= (1 << 12)
1133 || the_insn.exp.X_add_number < -(1 << 12))
1135 the_insn.opcode = (SETHI_INSN | RD (rd)
1136 | ((the_insn.exp.X_add_number >> 10)
1137 & (the_insn.exp.X_op == O_constant
1139 the_insn.reloc = (the_insn.exp.X_op != O_constant
1140 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1141 output_insn (insn, &the_insn);
1145 /* See if operand has no low-order bits; skip OR if so. */
1146 if (the_insn.exp.X_op != O_constant
1147 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1150 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1152 | (the_insn.exp.X_add_number
1153 & (the_insn.exp.X_op != O_constant
1154 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1155 the_insn.reloc = (the_insn.exp.X_op != O_constant
1156 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1157 output_insn (insn, &the_insn);
1161 /* Handle the setsw synthetic instruction. */
1164 synthetize_setsw (const struct sparc_opcode *insn)
1168 rd = (the_insn.opcode & RD (~0)) >> 25;
1170 if (the_insn.exp.X_op != O_constant)
1172 synthetize_setuw (insn);
1174 /* Need to sign extend it. */
1175 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1176 the_insn.reloc = BFD_RELOC_NONE;
1177 output_insn (insn, &the_insn);
1181 if (sizeof (offsetT) > 4
1182 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1183 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1184 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1186 low32 = the_insn.exp.X_add_number;
1190 synthetize_setuw (insn);
1196 the_insn.reloc = BFD_RELOC_NONE;
1197 /* See if operand is absolute and small; skip sethi if so. */
1198 if (low32 < -(1 << 12))
1200 the_insn.opcode = (SETHI_INSN | RD (rd)
1201 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1202 output_insn (insn, &the_insn);
1203 low32 = 0x1c00 | (low32 & 0x3ff);
1204 opc = RS1 (rd) | XOR_INSN;
1207 the_insn.opcode = (opc | RD (rd) | IMMED
1208 | (low32 & 0x1fff));
1209 output_insn (insn, &the_insn);
1212 /* Handle the setsw synthetic instruction. */
1215 synthetize_setx (const struct sparc_opcode *insn)
1217 int upper32, lower32;
1218 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1219 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1221 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1222 int need_xor10_p = 0;
1224 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1225 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1226 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1229 upper_dstreg = tmpreg;
1230 /* The tmp reg should not be the dst reg. */
1231 if (tmpreg == dstreg)
1232 as_warn (_("setx: temporary register same as destination register"));
1234 /* ??? Obviously there are other optimizations we can do
1235 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1236 doing some of these. Later. If you do change things, try to
1237 change all of this to be table driven as well. */
1238 /* What to output depends on the number if it's constant.
1239 Compute that first, then output what we've decided upon. */
1240 if (the_insn.exp.X_op != O_constant)
1242 if (sparc_arch_size == 32)
1244 /* When arch size is 32, we want setx to be equivalent
1245 to setuw for anything but constants. */
1246 the_insn.exp.X_add_number &= 0xffffffff;
1247 synthetize_setuw (insn);
1250 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1256 /* Reset X_add_number, we've extracted it as upper32/lower32.
1257 Otherwise fixup_segment will complain about not being able to
1258 write an 8 byte number in a 4 byte field. */
1259 the_insn.exp.X_add_number = 0;
1261 /* Only need hh22 if `or' insn can't handle constant. */
1262 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1265 /* Does bottom part (after sethi) have bits? */
1266 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1267 /* No hh22, but does upper32 still have bits we can't set
1269 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1272 /* If the lower half is all zero, we build the upper half directly
1273 into the dst reg. */
1275 /* Need lower half if number is zero or 0xffffffff00000000. */
1276 || (! need_hh22_p && ! need_hm10_p))
1278 /* No need for sethi if `or' insn can handle constant. */
1279 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1280 /* Note that we can't use a negative constant in the `or'
1281 insn unless the upper 32 bits are all ones. */
1282 || (lower32 < 0 && upper32 != -1)
1283 || (lower32 >= 0 && upper32 == -1))
1286 if (need_hi22_p && upper32 == -1)
1289 /* Does bottom part (after sethi) have bits? */
1290 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1292 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1293 /* Need `or' if we didn't set anything else. */
1294 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1298 /* Output directly to dst reg if lower 32 bits are all zero. */
1299 upper_dstreg = dstreg;
1302 if (!upper_dstreg && dstreg)
1303 as_warn (_("setx: illegal temporary register g0"));
1307 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1308 | ((upper32 >> 10) & 0x3fffff));
1309 the_insn.reloc = (the_insn.exp.X_op != O_constant
1310 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1311 output_insn (insn, &the_insn);
1316 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1317 | (((need_xor10_p ? ~lower32 : lower32)
1318 >> 10) & 0x3fffff));
1319 the_insn.reloc = (the_insn.exp.X_op != O_constant
1320 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1321 output_insn (insn, &the_insn);
1326 the_insn.opcode = (OR_INSN
1327 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1330 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1331 the_insn.reloc = (the_insn.exp.X_op != O_constant
1332 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1333 output_insn (insn, &the_insn);
1338 /* FIXME: One nice optimization to do here is to OR the low part
1339 with the highpart if hi22 isn't needed and the low part is
1341 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1344 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1345 the_insn.reloc = (the_insn.exp.X_op != O_constant
1346 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1347 output_insn (insn, &the_insn);
1350 /* If we needed to build the upper part, shift it into place. */
1351 if (need_hh22_p || need_hm10_p)
1353 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1355 the_insn.reloc = BFD_RELOC_NONE;
1356 output_insn (insn, &the_insn);
1359 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1362 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1363 | 0x1c00 | (lower32 & 0x3ff));
1364 the_insn.reloc = BFD_RELOC_NONE;
1365 output_insn (insn, &the_insn);
1368 /* If we needed to build both upper and lower parts, OR them together. */
1369 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1371 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1373 the_insn.reloc = BFD_RELOC_NONE;
1374 output_insn (insn, &the_insn);
1378 /* Main entry point to assemble one instruction. */
1381 md_assemble (char *str)
1383 const struct sparc_opcode *insn;
1387 special_case = sparc_ip (str, &insn);
1391 /* We warn about attempts to put a floating point branch in a delay slot,
1392 unless the delay slot has been annulled. */
1393 if (last_insn != NULL
1394 && (insn->flags & F_FBR) != 0
1395 && (last_insn->flags & F_DELAYED) != 0
1396 /* ??? This test isn't completely accurate. We assume anything with
1397 F_{UNBR,CONDBR,FBR} set is annullable. */
1398 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1399 || (last_opcode & ANNUL) == 0))
1400 as_warn (_("FP branch in delay slot"));
1402 /* SPARC before v9 requires a nop instruction between a floating
1403 point instruction and a floating point branch. We insert one
1404 automatically, with a warning. */
1405 if (max_architecture < SPARC_OPCODE_ARCH_V9
1406 && last_insn != NULL
1407 && (insn->flags & F_FBR) != 0
1408 && (last_insn->flags & F_FLOAT) != 0)
1410 struct sparc_it nop_insn;
1412 nop_insn.opcode = NOP_INSN;
1413 nop_insn.reloc = BFD_RELOC_NONE;
1414 output_insn (insn, &nop_insn);
1415 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1418 switch (special_case)
1420 case SPECIAL_CASE_NONE:
1422 output_insn (insn, &the_insn);
1425 case SPECIAL_CASE_SETSW:
1426 synthetize_setsw (insn);
1429 case SPECIAL_CASE_SET:
1430 synthetize_setuw (insn);
1433 case SPECIAL_CASE_SETX:
1434 synthetize_setx (insn);
1437 case SPECIAL_CASE_FDIV:
1439 int rd = (the_insn.opcode >> 25) & 0x1f;
1441 output_insn (insn, &the_insn);
1443 /* According to information leaked from Sun, the "fdiv" instructions
1444 on early SPARC machines would produce incorrect results sometimes.
1445 The workaround is to add an fmovs of the destination register to
1446 itself just after the instruction. This was true on machines
1447 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1448 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1449 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1450 output_insn (insn, &the_insn);
1455 as_fatal (_("failed special case insn sanity check"));
1460 get_hwcap_name (bfd_uint64_t mask)
1462 if (mask & HWCAP_MUL32)
1464 if (mask & HWCAP_DIV32)
1466 if (mask & HWCAP_FSMULD)
1468 if (mask & HWCAP_V8PLUS)
1470 if (mask & HWCAP_POPC)
1472 if (mask & HWCAP_VIS)
1474 if (mask & HWCAP_VIS2)
1476 if (mask & HWCAP_ASI_BLK_INIT)
1477 return "ASIBlkInit";
1478 if (mask & HWCAP_FMAF)
1480 if (mask & HWCAP_VIS3)
1482 if (mask & HWCAP_HPC)
1484 if (mask & HWCAP_RANDOM)
1486 if (mask & HWCAP_TRANS)
1488 if (mask & HWCAP_FJFMAU)
1490 if (mask & HWCAP_IMA)
1492 if (mask & HWCAP_ASI_CACHE_SPARING)
1494 if (mask & HWCAP_AES)
1496 if (mask & HWCAP_DES)
1498 if (mask & HWCAP_KASUMI)
1500 if (mask & HWCAP_CAMELLIA)
1502 if (mask & HWCAP_MD5)
1504 if (mask & HWCAP_SHA1)
1506 if (mask & HWCAP_SHA256)
1508 if (mask & HWCAP_SHA512)
1510 if (mask & HWCAP_MPMUL)
1512 if (mask & HWCAP_MONT)
1514 if (mask & HWCAP_PAUSE)
1516 if (mask & HWCAP_CBCOND)
1518 if (mask & HWCAP_CRC32C)
1522 if (mask & HWCAP2_FJATHPLUS)
1524 if (mask & HWCAP2_VIS3B)
1526 if (mask & HWCAP2_ADP)
1528 if (mask & HWCAP2_SPARC5)
1530 if (mask & HWCAP2_MWAIT)
1532 if (mask & HWCAP2_XMPMUL)
1534 if (mask & HWCAP2_XMONT)
1536 if (mask & HWCAP2_NSEC)
1542 /* Subroutine of md_assemble to do the actual parsing. */
1545 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1547 char *error_message = "";
1551 const struct sparc_opcode *insn;
1553 unsigned long opcode;
1554 unsigned int mask = 0;
1558 int special_case = SPECIAL_CASE_NONE;
1565 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1582 as_bad (_("Unknown opcode: `%s'"), str);
1584 return special_case;
1586 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1590 as_bad (_("Unknown opcode: `%s'"), str);
1591 return special_case;
1601 opcode = insn->match;
1602 memset (&the_insn, '\0', sizeof (the_insn));
1603 the_insn.reloc = BFD_RELOC_NONE;
1606 /* Build the opcode, checking as we go to make sure that the
1608 for (args = insn->args;; ++args)
1616 /* Parse a series of masks. */
1623 if (! parse_keyword_arg (sparc_encode_membar, &s,
1626 error_message = _(": invalid membar mask name");
1632 if (*s == '|' || *s == '+')
1640 if (! parse_const_expr_arg (&s, &kmask))
1642 error_message = _(": invalid membar mask expression");
1645 if (kmask < 0 || kmask > 127)
1647 error_message = _(": invalid membar mask number");
1652 opcode |= MEMBAR (kmask);
1660 if (! parse_const_expr_arg (&s, &smask))
1662 error_message = _(": invalid siam mode expression");
1665 if (smask < 0 || smask > 7)
1667 error_message = _(": invalid siam mode number");
1678 /* Parse a prefetch function. */
1681 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1683 error_message = _(": invalid prefetch function name");
1689 if (! parse_const_expr_arg (&s, &fcn))
1691 error_message = _(": invalid prefetch function expression");
1694 if (fcn < 0 || fcn > 31)
1696 error_message = _(": invalid prefetch function number");
1706 /* Parse a sparc64 privileged register. */
1709 struct priv_reg_entry *p = priv_reg_table;
1710 unsigned int len = 9999999; /* Init to make gcc happy. */
1713 while (p->name[0] > s[0])
1715 while (p->name[0] == s[0])
1717 len = strlen (p->name);
1718 if (strncmp (p->name, s, len) == 0)
1722 if (p->name[0] != s[0])
1724 error_message = _(": unrecognizable privileged register");
1728 opcode |= (p->regnum << 14);
1730 opcode |= (p->regnum << 25);
1736 error_message = _(": unrecognizable privileged register");
1742 /* Parse a sparc64 hyperprivileged register. */
1745 struct priv_reg_entry *p = hpriv_reg_table;
1746 unsigned int len = 9999999; /* Init to make gcc happy. */
1749 while (p->name[0] > s[0])
1751 while (p->name[0] == s[0])
1753 len = strlen (p->name);
1754 if (strncmp (p->name, s, len) == 0)
1758 if (p->name[0] != s[0])
1760 error_message = _(": unrecognizable hyperprivileged register");
1764 opcode |= (p->regnum << 14);
1766 opcode |= (p->regnum << 25);
1772 error_message = _(": unrecognizable hyperprivileged register");
1778 /* Parse a v9a/v9b ancillary state register. */
1781 struct priv_reg_entry *p = v9a_asr_table;
1782 unsigned int len = 9999999; /* Init to make gcc happy. */
1785 while (p->name[0] > s[0])
1787 while (p->name[0] == s[0])
1789 len = strlen (p->name);
1790 if (strncmp (p->name, s, len) == 0)
1794 if (p->name[0] != s[0])
1796 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1799 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1801 error_message = _(": rd on write only ancillary state register");
1805 && (insn->architecture
1806 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1808 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1809 error_message = _(": unrecognizable v9a ancillary state register");
1813 opcode |= (p->regnum << 14);
1815 opcode |= (p->regnum << 25);
1821 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1827 if (strncmp (s, "%asr", 4) == 0)
1835 while (ISDIGIT (*s))
1837 num = num * 10 + *s - '0';
1841 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1843 if (num < 16 || 31 < num)
1845 error_message = _(": asr number must be between 16 and 31");
1851 if (num < 0 || 31 < num)
1853 error_message = _(": asr number must be between 0 and 31");
1858 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1863 error_message = _(": expecting %asrN");
1870 the_insn.reloc = BFD_RELOC_SPARC_11;
1874 the_insn.reloc = BFD_RELOC_SPARC_10;
1880 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1885 if (s[0] == '0' && s[1] == 'x')
1888 while (ISXDIGIT (*s))
1891 num |= hex_value (*s);
1897 while (ISDIGIT (*s))
1899 num = num * 10 + *s - '0';
1903 if (num < 0 || num > 31)
1905 error_message = _(": crypto immediate must be between 0 and 31");
1909 opcode |= RS3 (num);
1914 error_message = _(": expecting crypto immediate");
1919 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1920 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1921 the_insn.reloc = BFD_RELOC_SPARC_5;
1923 the_insn.reloc = BFD_RELOC_SPARC13;
1924 /* These fields are unsigned, but for upward compatibility,
1925 allow negative values as well. */
1929 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1930 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1931 the_insn.reloc = BFD_RELOC_SPARC_6;
1933 the_insn.reloc = BFD_RELOC_SPARC13;
1934 /* These fields are unsigned, but for upward compatibility,
1935 allow negative values as well. */
1939 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1944 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1949 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1954 if (*s == 'p' && s[1] == 'n')
1962 if (*s == 'p' && s[1] == 't')
1974 if (strncmp (s, "%icc", 4) == 0)
1986 if (strncmp (s, "%xcc", 4) == 0)
1998 if (strncmp (s, "%fcc0", 5) == 0)
2010 if (strncmp (s, "%fcc1", 5) == 0)
2022 if (strncmp (s, "%fcc2", 5) == 0)
2034 if (strncmp (s, "%fcc3", 5) == 0)
2042 if (strncmp (s, "%pc", 3) == 0)
2050 if (strncmp (s, "%tick", 5) == 0)
2057 case '\0': /* End of args. */
2058 if (s[0] == ',' && s[1] == '%')
2060 static const struct ops
2062 /* The name as it appears in assembler. */
2064 /* strlen (name), precomputed for speed */
2066 /* The reloc this pseudo-op translates to. */
2068 /* 1 if tls call. */
2073 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2074 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2075 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2076 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2077 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2078 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2079 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2080 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2081 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2084 const struct ops *o;
2088 for (o = ops; o->name; o++)
2089 if (strncmp (s + 2, o->name, o->len) == 0)
2091 if (o->name == NULL)
2094 if (s[o->len + 2] != '(')
2096 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2097 return special_case;
2100 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2102 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2104 return special_case;
2108 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2109 || the_insn.exp.X_add_number != 0
2110 || the_insn.exp.X_add_symbol
2111 != symbol_find_or_make ("__tls_get_addr")))
2113 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2115 return special_case;
2118 the_insn.reloc = o->reloc;
2119 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2122 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2125 else if (*s1 == ')')
2134 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2135 return special_case;
2139 (void) get_expression (s);
2159 case '[': /* These must match exactly. */
2167 case '#': /* Must be at least one digit. */
2170 while (ISDIGIT (*s))
2178 case 'C': /* Coprocessor state register. */
2179 if (strncmp (s, "%csr", 4) == 0)
2186 case 'b': /* Next operand is a coprocessor register. */
2189 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2194 mask = 10 * (mask - '0') + (*s++ - '0');
2208 opcode |= mask << 14;
2216 opcode |= mask << 25;
2222 case 'r': /* next operand must be a register */
2232 case 'f': /* frame pointer */
2240 case 'g': /* global register */
2249 case 'i': /* in register */
2253 mask = c - '0' + 24;
2258 case 'l': /* local register */
2262 mask = (c - '0' + 16);
2267 case 'o': /* out register */
2271 mask = (c - '0' + 8);
2276 case 's': /* stack pointer */
2284 case 'r': /* any register */
2285 if (!ISDIGIT ((c = *s++)))
2302 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2318 if ((mask & ~1) == 2 && sparc_arch_size == 64
2319 && no_undeclared_regs && ! globals[mask])
2320 as_bad (_("detected global register use not covered by .register pseudo-op"));
2322 /* Got the register, now figure out where
2323 it goes in the opcode. */
2327 opcode |= mask << 14;
2335 opcode |= mask << 25;
2339 opcode |= (mask << 25) | (mask << 14);
2343 opcode |= (mask << 25) | (mask << 0);
2349 case 'e': /* next operand is a floating point register */
2368 && ((format = *s) == 'f')
2371 for (mask = 0; ISDIGIT (*s); ++s)
2373 mask = 10 * mask + (*s - '0');
2374 } /* read the number */
2383 } /* register must be even numbered */
2391 } /* register must be multiple of 4 */
2395 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2396 error_message = _(": There are only 64 f registers; [0-63]");
2398 error_message = _(": There are only 32 f registers; [0-31]");
2401 else if (mask >= 32)
2403 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2405 if (*args == 'e' || *args == 'f' || *args == 'g')
2408 = _(": There are only 32 single precision f registers; [0-31]");
2412 mask -= 31; /* wrap high bit */
2416 error_message = _(": There are only 32 f registers; [0-31]");
2424 } /* if not an 'f' register. */
2426 if (*args == '}' && mask != RS2 (opcode))
2429 = _(": Instruction requires frs2 and frsd must be the same register");
2438 opcode |= RS1 (mask);
2444 opcode |= RS2 (mask);
2449 opcode |= RS3 (mask);
2456 opcode |= RD (mask);
2465 if (strncmp (s, "%fsr", 4) == 0)
2473 if (strncmp (s, "%efsr", 5) == 0)
2480 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2481 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2484 case 'l': /* 22 bit PC relative immediate */
2485 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2489 case 'L': /* 30 bit immediate */
2490 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2495 case 'n': /* 22 bit immediate */
2496 the_insn.reloc = BFD_RELOC_SPARC22;
2499 case 'i': /* 13 bit immediate */
2500 the_insn.reloc = BFD_RELOC_SPARC13;
2510 char *op_arg = NULL;
2511 static expressionS op_exp;
2512 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2514 /* Check for %hi, etc. */
2517 static const struct ops {
2518 /* The name as it appears in assembler. */
2520 /* strlen (name), precomputed for speed */
2522 /* The reloc this pseudo-op translates to. */
2524 /* Non-zero if for v9 only. */
2526 /* Non-zero if can be used in pc-relative contexts. */
2527 int pcrel_p;/*FIXME:wip*/
2529 /* hix/lox must appear before hi/lo so %hix won't be
2530 mistaken for %hi. */
2531 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2532 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2533 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2534 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2535 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2536 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2537 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2538 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2539 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2540 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2541 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2542 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2543 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2544 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2545 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2546 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2547 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2548 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2549 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2550 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2551 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2553 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2555 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2556 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2557 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2558 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2559 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2561 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2563 { NULL, 0, 0, 0, 0 }
2565 const struct ops *o;
2567 for (o = ops; o->name; o++)
2568 if (strncmp (s + 1, o->name, o->len) == 0)
2570 if (o->name == NULL)
2573 if (s[o->len + 1] != '(')
2575 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2576 return special_case;
2580 the_insn.reloc = o->reloc;
2585 /* Note that if the get_expression() fails, we will still
2586 have created U entries in the symbol table for the
2587 'symbols' in the input string. Try not to create U
2588 symbols for registers, etc. */
2590 /* This stuff checks to see if the expression ends in
2591 +%reg. If it does, it removes the register from
2592 the expression, and re-sets 's' to point to the
2599 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2602 else if (*s1 == ')')
2611 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2612 return special_case;
2616 (void) get_expression (s);
2619 if (*s == ',' || *s == ']' || !*s)
2621 if (*s != '+' && *s != '-')
2623 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2624 return special_case;
2628 op_exp = the_insn.exp;
2629 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2632 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2635 if (s1 != s && ISDIGIT (s1[-1]))
2637 if (s1[-2] == '%' && s1[-3] == '+')
2639 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2641 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2648 if (op_arg && s1 == s + 1)
2649 the_insn.exp.X_op = O_absent;
2651 (void) get_expression (s);
2663 (void) get_expression (s);
2671 the_insn.exp2 = the_insn.exp;
2672 the_insn.exp = op_exp;
2673 if (the_insn.exp2.X_op == O_absent)
2674 the_insn.exp2.X_op = O_illegal;
2675 else if (the_insn.exp.X_op == O_absent)
2677 the_insn.exp = the_insn.exp2;
2678 the_insn.exp2.X_op = O_illegal;
2680 else if (the_insn.exp.X_op == O_constant)
2682 valueT val = the_insn.exp.X_add_number;
2683 switch (the_insn.reloc)
2688 case BFD_RELOC_SPARC_HH22:
2689 val = BSR (val, 32);
2692 case BFD_RELOC_SPARC_LM22:
2693 case BFD_RELOC_HI22:
2694 val = (val >> 10) & 0x3fffff;
2697 case BFD_RELOC_SPARC_HM10:
2698 val = BSR (val, 32);
2701 case BFD_RELOC_LO10:
2705 case BFD_RELOC_SPARC_H34:
2710 case BFD_RELOC_SPARC_H44:
2715 case BFD_RELOC_SPARC_M44:
2720 case BFD_RELOC_SPARC_L44:
2724 case BFD_RELOC_SPARC_HIX22:
2726 val = (val >> 10) & 0x3fffff;
2729 case BFD_RELOC_SPARC_LOX10:
2730 val = (val & 0x3ff) | 0x1c00;
2733 the_insn.exp = the_insn.exp2;
2734 the_insn.exp.X_add_number += val;
2735 the_insn.exp2.X_op = O_illegal;
2736 the_insn.reloc = old_reloc;
2738 else if (the_insn.exp2.X_op != O_constant)
2740 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2741 return special_case;
2745 if (old_reloc != BFD_RELOC_SPARC13
2746 || the_insn.reloc != BFD_RELOC_LO10
2747 || sparc_arch_size != 64
2750 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2751 return special_case;
2753 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2757 /* Check for constants that don't require emitting a reloc. */
2758 if (the_insn.exp.X_op == O_constant
2759 && the_insn.exp.X_add_symbol == 0
2760 && the_insn.exp.X_op_symbol == 0)
2762 /* For pc-relative call instructions, we reject
2763 constants to get better code. */
2765 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2766 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2768 error_message = _(": PC-relative operand can't be a constant");
2772 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2773 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2775 error_message = _(": TLS operand can't be a constant");
2779 /* Constants that won't fit are checked in md_apply_fix
2780 and bfd_install_relocation.
2781 ??? It would be preferable to install the constants
2782 into the insn here and save having to create a fixS
2783 for each one. There already exists code to handle
2784 all the various cases (e.g. in md_apply_fix and
2785 bfd_install_relocation) so duplicating all that code
2786 here isn't right. */
2788 /* This is a special case to handle cbcond instructions
2789 properly, which can need two relocations. The first
2790 one is for the 5-bit immediate field and the latter
2791 is going to be for the WDISP10 branch part. We
2792 handle the R_SPARC_5 immediate directly here so that
2793 we don't need to add support for multiple relocations
2794 in one instruction just yet. */
2795 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2797 valueT val = the_insn.exp.X_add_number;
2799 if (! in_bitfield_range (val, 0x1f))
2801 error_message = _(": Immediate value in cbcond is out of range.");
2804 opcode |= val & 0x1f;
2805 the_insn.reloc = BFD_RELOC_NONE;
2826 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2828 error_message = _(": invalid ASI name");
2834 if (! parse_const_expr_arg (&s, &asi))
2836 error_message = _(": invalid ASI expression");
2839 if (asi < 0 || asi > 255)
2841 error_message = _(": invalid ASI number");
2845 opcode |= ASI (asi);
2847 } /* Alternate space. */
2850 if (strncmp (s, "%psr", 4) == 0)
2857 case 'q': /* Floating point queue. */
2858 if (strncmp (s, "%fq", 3) == 0)
2865 case 'Q': /* Coprocessor queue. */
2866 if (strncmp (s, "%cq", 3) == 0)
2874 if (strcmp (str, "set") == 0
2875 || strcmp (str, "setuw") == 0)
2877 special_case = SPECIAL_CASE_SET;
2880 else if (strcmp (str, "setsw") == 0)
2882 special_case = SPECIAL_CASE_SETSW;
2885 else if (strcmp (str, "setx") == 0)
2887 special_case = SPECIAL_CASE_SETX;
2890 else if (strncmp (str, "fdiv", 4) == 0)
2892 special_case = SPECIAL_CASE_FDIV;
2898 if (strncmp (s, "%asi", 4) != 0)
2904 if (strncmp (s, "%fprs", 5) != 0)
2910 if (strncmp (s, "%mcdper",7) != 0)
2916 if (strncmp (s, "%ccr", 4) != 0)
2922 if (strncmp (s, "%tbr", 4) != 0)
2928 if (strncmp (s, "%wim", 4) != 0)
2935 char *push = input_line_pointer;
2938 input_line_pointer = s;
2940 if (e.X_op == O_constant)
2942 int n = e.X_add_number;
2943 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2944 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2946 opcode |= e.X_add_number << 5;
2949 as_bad (_("non-immediate OPF operand, ignored"));
2950 s = input_line_pointer;
2951 input_line_pointer = push;
2956 if (strncmp (s, "%y", 2) != 0)
2964 /* Parse a sparclet cpreg. */
2966 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2968 error_message = _(": invalid cpreg name");
2971 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2976 as_fatal (_("failed sanity check."));
2977 } /* switch on arg code. */
2979 /* Break out of for() loop. */
2981 } /* For each arg that we expect. */
2986 /* Args don't match. */
2987 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2988 && (insn->name == insn[1].name
2989 || !strcmp (insn->name, insn[1].name)))
2997 as_bad (_("Illegal operands%s"), error_message);
2998 return special_case;
3003 /* We have a match. Now see if the architecture is OK. */
3004 int needed_arch_mask = insn->architecture;
3006 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps;
3008 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3010 hwcap_seen |= hwcaps;
3015 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
3016 if (! needed_arch_mask)
3018 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
3021 if (needed_arch_mask
3022 & SPARC_OPCODE_SUPPORTED (current_architecture))
3025 /* Can we bump up the architecture? */
3026 else if (needed_arch_mask
3027 & SPARC_OPCODE_SUPPORTED (max_architecture))
3029 enum sparc_opcode_arch_val needed_architecture =
3030 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
3031 & needed_arch_mask);
3033 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
3035 && needed_architecture > warn_after_architecture)
3037 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3038 sparc_opcode_archs[current_architecture].name,
3039 sparc_opcode_archs[needed_architecture].name,
3041 warn_after_architecture = needed_architecture;
3043 current_architecture = needed_architecture;
3044 hwcap_allowed |= hwcaps;
3047 /* ??? This seems to be a bit fragile. What if the next entry in
3048 the opcode table is the one we want and it is supported?
3049 It is possible to arrange the table today so that this can't
3050 happen but what about tomorrow? */
3053 int arch, printed_one_p = 0;
3055 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
3057 /* Create a list of the architectures that support the insn. */
3058 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
3060 arch = sparc_ffs (needed_arch_mask);
3061 while ((1 << arch) <= needed_arch_mask)
3063 if ((1 << arch) & needed_arch_mask)
3067 strcpy (p, sparc_opcode_archs[arch].name);
3074 as_bad (_("Architecture mismatch on \"%s\"."), str);
3075 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3077 sparc_opcode_archs[max_architecture].name);
3078 return special_case;
3081 /* Make sure the hwcaps used by the instruction are
3082 currently enabled. */
3083 if (hwcaps & ~hwcap_allowed)
3085 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
3087 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3089 return special_case;
3091 } /* If no match. */
3094 } /* Forever looking for a match. */
3096 the_insn.opcode = opcode;
3097 return special_case;
3100 /* Parse an argument that can be expressed as a keyword.
3101 (eg: #StoreStore or %ccfr).
3102 The result is a boolean indicating success.
3103 If successful, INPUT_POINTER is updated. */
3106 parse_keyword_arg (int (*lookup_fn) (const char *),
3107 char **input_pointerP,
3113 p = *input_pointerP;
3114 for (q = p + (*p == '#' || *p == '%');
3115 ISALNUM (*q) || *q == '_';
3120 value = (*lookup_fn) (p);
3125 *input_pointerP = q;
3129 /* Parse an argument that is a constant expression.
3130 The result is a boolean indicating success. */
3133 parse_const_expr_arg (char **input_pointerP, int *valueP)
3135 char *save = input_line_pointer;
3138 input_line_pointer = *input_pointerP;
3139 /* The next expression may be something other than a constant
3140 (say if we're not processing the right variant of the insn).
3141 Don't call expression unless we're sure it will succeed as it will
3142 signal an error (which we want to defer until later). */
3143 /* FIXME: It might be better to define md_operand and have it recognize
3144 things like %asi, etc. but continuing that route through to the end
3145 is a lot of work. */
3146 if (*input_line_pointer == '%')
3148 input_line_pointer = save;
3152 *input_pointerP = input_line_pointer;
3153 input_line_pointer = save;
3154 if (exp.X_op != O_constant)
3156 *valueP = exp.X_add_number;
3160 /* Subroutine of sparc_ip to parse an expression. */
3163 get_expression (char *str)
3168 save_in = input_line_pointer;
3169 input_line_pointer = str;
3170 seg = expression (&the_insn.exp);
3171 if (seg != absolute_section
3172 && seg != text_section
3173 && seg != data_section
3174 && seg != bss_section
3175 && seg != undefined_section)
3177 the_insn.error = _("bad segment");
3178 expr_end = input_line_pointer;
3179 input_line_pointer = save_in;
3182 expr_end = input_line_pointer;
3183 input_line_pointer = save_in;
3187 /* Subroutine of md_assemble to output one insn. */
3190 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3192 char *toP = frag_more (4);
3194 /* Put out the opcode. */
3195 if (INSN_BIG_ENDIAN)
3196 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3198 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3200 /* Put out the symbol-dependent stuff. */
3201 if (theinsn->reloc != BFD_RELOC_NONE)
3203 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3204 (toP - frag_now->fr_literal), /* Where. */
3209 /* Turn off overflow checking in fixup_segment. We'll do our
3210 own overflow checking in md_apply_fix. This is necessary because
3211 the insn size is 4 and fixup_segment will signal an overflow for
3212 large 8 byte quantities. */
3213 fixP->fx_no_overflow = 1;
3214 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3215 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3219 last_opcode = theinsn->opcode;
3222 dwarf2_emit_insn (4);
3227 md_atof (int type, char *litP, int *sizeP)
3229 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3232 /* Write a value out to the object file, using the appropriate
3236 md_number_to_chars (char *buf, valueT val, int n)
3238 if (target_big_endian)
3239 number_to_chars_bigendian (buf, val, n);
3240 else if (target_little_endian_data
3241 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3242 /* Output debug words, which are not in allocated sections, as big
3244 number_to_chars_bigendian (buf, val, n);
3245 else if (target_little_endian_data || ! target_big_endian)
3246 number_to_chars_littleendian (buf, val, n);
3249 /* Apply a fixS to the frags, now that we know the value it ought to
3253 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3255 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3256 offsetT val = * (offsetT *) valP;
3259 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3261 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3264 /* SPARC ELF relocations don't use an addend in the data field. */
3265 if (fixP->fx_addsy != NULL)
3267 switch (fixP->fx_r_type)
3269 case BFD_RELOC_SPARC_TLS_GD_HI22:
3270 case BFD_RELOC_SPARC_TLS_GD_LO10:
3271 case BFD_RELOC_SPARC_TLS_GD_ADD:
3272 case BFD_RELOC_SPARC_TLS_GD_CALL:
3273 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3274 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3275 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3276 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3277 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3278 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3279 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3280 case BFD_RELOC_SPARC_TLS_IE_HI22:
3281 case BFD_RELOC_SPARC_TLS_IE_LO10:
3282 case BFD_RELOC_SPARC_TLS_IE_LD:
3283 case BFD_RELOC_SPARC_TLS_IE_LDX:
3284 case BFD_RELOC_SPARC_TLS_IE_ADD:
3285 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3286 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3287 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3288 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3289 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3290 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3291 case BFD_RELOC_SPARC_TLS_TPOFF32:
3292 case BFD_RELOC_SPARC_TLS_TPOFF64:
3293 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3303 /* This is a hack. There should be a better way to
3304 handle this. Probably in terms of howto fields, once
3305 we can look at these fixups in terms of howtos. */
3306 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3307 val += fixP->fx_where + fixP->fx_frag->fr_address;
3310 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3311 generate a reloc, then we just want to let the reloc addend set
3312 the value. We do not want to also stuff the addend into the
3313 object file. Including the addend in the object file works when
3314 doing a static link, because the linker will ignore the object
3315 file contents. However, the dynamic linker does not ignore the
3316 object file contents. */
3317 if (fixP->fx_addsy != NULL
3318 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3321 /* When generating PIC code, we do not want an addend for a reloc
3322 against a local symbol. We adjust fx_addnumber to cancel out the
3323 value already included in val, and to also cancel out the
3324 adjustment which bfd_install_relocation will create. */
3326 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3327 && fixP->fx_addsy != NULL
3328 && ! S_IS_COMMON (fixP->fx_addsy)
3329 && symbol_section_p (fixP->fx_addsy))
3330 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3332 /* When generating PIC code, we need to fiddle to get
3333 bfd_install_relocation to do the right thing for a PC relative
3334 reloc against a local symbol which we are going to keep. */
3336 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3337 && fixP->fx_addsy != NULL
3338 && (S_IS_EXTERNAL (fixP->fx_addsy)
3339 || S_IS_WEAK (fixP->fx_addsy))
3340 && S_IS_DEFINED (fixP->fx_addsy)
3341 && ! S_IS_COMMON (fixP->fx_addsy))
3344 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3348 /* If this is a data relocation, just output VAL. */
3350 if (fixP->fx_r_type == BFD_RELOC_8)
3352 md_number_to_chars (buf, val, 1);
3354 else if (fixP->fx_r_type == BFD_RELOC_16
3355 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3357 md_number_to_chars (buf, val, 2);
3359 else if (fixP->fx_r_type == BFD_RELOC_32
3360 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3361 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3363 md_number_to_chars (buf, val, 4);
3365 else if (fixP->fx_r_type == BFD_RELOC_64
3366 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3368 md_number_to_chars (buf, val, 8);
3370 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3371 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3378 /* It's a relocation against an instruction. */
3380 if (INSN_BIG_ENDIAN)
3381 insn = bfd_getb32 ((unsigned char *) buf);
3383 insn = bfd_getl32 ((unsigned char *) buf);
3385 switch (fixP->fx_r_type)
3387 case BFD_RELOC_32_PCREL_S2:
3389 /* FIXME: This increment-by-one deserves a comment of why it's
3391 if (! sparc_pic_code
3392 || fixP->fx_addsy == NULL
3393 || symbol_section_p (fixP->fx_addsy))
3396 insn |= val & 0x3fffffff;
3398 /* See if we have a delay slot. */
3399 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3403 #define XCC (2 << 20)
3404 #define COND(x) (((x)&0xf)<<25)
3405 #define CONDA COND(0x8)
3406 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3407 #define INSN_BA (F2(0,2) | CONDA)
3408 #define INSN_OR F3(2, 0x2, 0)
3409 #define INSN_NOP F2(0,4)
3413 /* If the instruction is a call with either:
3415 arithmetic instruction with rd == %o7
3416 where rs1 != %o7 and rs2 if it is register != %o7
3417 then we can optimize if the call destination is near
3418 by changing the call into a branch always. */
3419 if (INSN_BIG_ENDIAN)
3420 delay = bfd_getb32 ((unsigned char *) buf + 4);
3422 delay = bfd_getl32 ((unsigned char *) buf + 4);
3423 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3425 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3426 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3427 || ((delay & RD (~0)) != RD (O7))))
3429 if ((delay & RS1 (~0)) == RS1 (O7)
3430 || ((delay & F3I (~0)) == 0
3431 && (delay & RS2 (~0)) == RS2 (O7)))
3433 /* Ensure the branch will fit into simm22. */
3434 if ((val & 0x3fe00000)
3435 && (val & 0x3fe00000) != 0x3fe00000)
3437 /* Check if the arch is v9 and branch will fit
3439 if (((val & 0x3c0000) == 0
3440 || (val & 0x3c0000) == 0x3c0000)
3441 && (sparc_arch_size == 64
3442 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3444 insn = INSN_BPA | (val & 0x7ffff);
3447 insn = INSN_BA | (val & 0x3fffff);
3448 if (fixP->fx_where >= 4
3449 && ((delay & (0xffffffff ^ RS1 (~0)))
3450 == (INSN_OR | RD (O7) | RS2 (G0))))
3455 if (INSN_BIG_ENDIAN)
3456 setter = bfd_getb32 ((unsigned char *) buf - 4);
3458 setter = bfd_getl32 ((unsigned char *) buf - 4);
3459 if ((setter & (0xffffffff ^ RD (~0)))
3460 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3467 If call foo was replaced with ba, replace
3468 or %rN, %g0, %o7 with nop. */
3469 reg = (delay & RS1 (~0)) >> 14;
3470 if (reg != ((setter & RD (~0)) >> 25)
3471 || reg == G0 || reg == O7)
3474 if (INSN_BIG_ENDIAN)
3475 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3477 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3482 case BFD_RELOC_SPARC_11:
3483 if (! in_signed_range (val, 0x7ff))
3484 as_bad_where (fixP->fx_file, fixP->fx_line,
3485 _("relocation overflow"));
3486 insn |= val & 0x7ff;
3489 case BFD_RELOC_SPARC_10:
3490 if (! in_signed_range (val, 0x3ff))
3491 as_bad_where (fixP->fx_file, fixP->fx_line,
3492 _("relocation overflow"));
3493 insn |= val & 0x3ff;
3496 case BFD_RELOC_SPARC_7:
3497 if (! in_bitfield_range (val, 0x7f))
3498 as_bad_where (fixP->fx_file, fixP->fx_line,
3499 _("relocation overflow"));
3503 case BFD_RELOC_SPARC_6:
3504 if (! in_bitfield_range (val, 0x3f))
3505 as_bad_where (fixP->fx_file, fixP->fx_line,
3506 _("relocation overflow"));
3510 case BFD_RELOC_SPARC_5:
3511 if (! in_bitfield_range (val, 0x1f))
3512 as_bad_where (fixP->fx_file, fixP->fx_line,
3513 _("relocation overflow"));
3517 case BFD_RELOC_SPARC_WDISP10:
3520 || val <= -(offsetT) 0x808)
3521 as_bad_where (fixP->fx_file, fixP->fx_line,
3522 _("relocation overflow"));
3523 /* FIXME: The +1 deserves a comment. */
3524 val = (val >> 2) + 1;
3525 insn |= ((val & 0x300) << 11)
3526 | ((val & 0xff) << 5);
3529 case BFD_RELOC_SPARC_WDISP16:
3532 || val <= -(offsetT) 0x20008)
3533 as_bad_where (fixP->fx_file, fixP->fx_line,
3534 _("relocation overflow"));
3535 /* FIXME: The +1 deserves a comment. */
3536 val = (val >> 2) + 1;
3537 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3540 case BFD_RELOC_SPARC_WDISP19:
3543 || val <= -(offsetT) 0x100008)
3544 as_bad_where (fixP->fx_file, fixP->fx_line,
3545 _("relocation overflow"));
3546 /* FIXME: The +1 deserves a comment. */
3547 val = (val >> 2) + 1;
3548 insn |= val & 0x7ffff;
3551 case BFD_RELOC_SPARC_HH22:
3552 val = BSR (val, 32);
3555 case BFD_RELOC_SPARC_LM22:
3556 case BFD_RELOC_HI22:
3557 if (!fixP->fx_addsy)
3558 insn |= (val >> 10) & 0x3fffff;
3560 /* FIXME: Need comment explaining why we do this. */
3564 case BFD_RELOC_SPARC22:
3565 if (val & ~0x003fffff)
3566 as_bad_where (fixP->fx_file, fixP->fx_line,
3567 _("relocation overflow"));
3568 insn |= (val & 0x3fffff);
3571 case BFD_RELOC_SPARC_HM10:
3572 val = BSR (val, 32);
3575 case BFD_RELOC_LO10:
3576 if (!fixP->fx_addsy)
3577 insn |= val & 0x3ff;
3579 /* FIXME: Need comment explaining why we do this. */
3583 case BFD_RELOC_SPARC_OLO10:
3585 val += fixP->tc_fix_data;
3588 case BFD_RELOC_SPARC13:
3589 if (! in_signed_range (val, 0x1fff))
3590 as_bad_where (fixP->fx_file, fixP->fx_line,
3591 _("relocation overflow"));
3592 insn |= val & 0x1fff;
3595 case BFD_RELOC_SPARC_WDISP22:
3596 val = (val >> 2) + 1;
3598 case BFD_RELOC_SPARC_BASE22:
3599 insn |= val & 0x3fffff;
3602 case BFD_RELOC_SPARC_H34:
3603 if (!fixP->fx_addsy)
3607 insn |= tval & 0x3fffff;
3611 case BFD_RELOC_SPARC_H44:
3612 if (!fixP->fx_addsy)
3616 insn |= tval & 0x3fffff;
3620 case BFD_RELOC_SPARC_M44:
3621 if (!fixP->fx_addsy)
3622 insn |= (val >> 12) & 0x3ff;
3625 case BFD_RELOC_SPARC_L44:
3626 if (!fixP->fx_addsy)
3627 insn |= val & 0xfff;
3630 case BFD_RELOC_SPARC_HIX22:
3631 if (!fixP->fx_addsy)
3633 val ^= ~(offsetT) 0;
3634 insn |= (val >> 10) & 0x3fffff;
3638 case BFD_RELOC_SPARC_LOX10:
3639 if (!fixP->fx_addsy)
3640 insn |= 0x1c00 | (val & 0x3ff);
3643 case BFD_RELOC_NONE:
3645 as_bad_where (fixP->fx_file, fixP->fx_line,
3646 _("bad or unhandled relocation type: 0x%02x"),
3651 if (INSN_BIG_ENDIAN)
3652 bfd_putb32 (insn, (unsigned char *) buf);
3654 bfd_putl32 (insn, (unsigned char *) buf);
3657 /* Are we finished with this relocation now? */
3658 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3662 /* Translate internal representation of relocation info to BFD target
3666 tc_gen_reloc (asection *section, fixS *fixp)
3668 static arelent *relocs[3];
3670 bfd_reloc_code_real_type code;
3672 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3675 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3676 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3677 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3679 switch (fixp->fx_r_type)
3683 case BFD_RELOC_HI22:
3684 case BFD_RELOC_LO10:
3685 case BFD_RELOC_32_PCREL_S2:
3686 case BFD_RELOC_SPARC13:
3687 case BFD_RELOC_SPARC22:
3688 case BFD_RELOC_SPARC_PC22:
3689 case BFD_RELOC_SPARC_PC10:
3690 case BFD_RELOC_SPARC_BASE13:
3691 case BFD_RELOC_SPARC_WDISP10:
3692 case BFD_RELOC_SPARC_WDISP16:
3693 case BFD_RELOC_SPARC_WDISP19:
3694 case BFD_RELOC_SPARC_WDISP22:
3696 case BFD_RELOC_SPARC_5:
3697 case BFD_RELOC_SPARC_6:
3698 case BFD_RELOC_SPARC_7:
3699 case BFD_RELOC_SPARC_10:
3700 case BFD_RELOC_SPARC_11:
3701 case BFD_RELOC_SPARC_HH22:
3702 case BFD_RELOC_SPARC_HM10:
3703 case BFD_RELOC_SPARC_LM22:
3704 case BFD_RELOC_SPARC_PC_HH22:
3705 case BFD_RELOC_SPARC_PC_HM10:
3706 case BFD_RELOC_SPARC_PC_LM22:
3707 case BFD_RELOC_SPARC_H34:
3708 case BFD_RELOC_SPARC_H44:
3709 case BFD_RELOC_SPARC_M44:
3710 case BFD_RELOC_SPARC_L44:
3711 case BFD_RELOC_SPARC_HIX22:
3712 case BFD_RELOC_SPARC_LOX10:
3713 case BFD_RELOC_SPARC_REV32:
3714 case BFD_RELOC_SPARC_OLO10:
3715 case BFD_RELOC_SPARC_UA16:
3716 case BFD_RELOC_SPARC_UA32:
3717 case BFD_RELOC_SPARC_UA64:
3718 case BFD_RELOC_8_PCREL:
3719 case BFD_RELOC_16_PCREL:
3720 case BFD_RELOC_32_PCREL:
3721 case BFD_RELOC_64_PCREL:
3722 case BFD_RELOC_SPARC_PLT32:
3723 case BFD_RELOC_SPARC_PLT64:
3724 case BFD_RELOC_VTABLE_ENTRY:
3725 case BFD_RELOC_VTABLE_INHERIT:
3726 case BFD_RELOC_SPARC_TLS_GD_HI22:
3727 case BFD_RELOC_SPARC_TLS_GD_LO10:
3728 case BFD_RELOC_SPARC_TLS_GD_ADD:
3729 case BFD_RELOC_SPARC_TLS_GD_CALL:
3730 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3731 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3732 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3733 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3734 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3735 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3736 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3737 case BFD_RELOC_SPARC_TLS_IE_HI22:
3738 case BFD_RELOC_SPARC_TLS_IE_LO10:
3739 case BFD_RELOC_SPARC_TLS_IE_LD:
3740 case BFD_RELOC_SPARC_TLS_IE_LDX:
3741 case BFD_RELOC_SPARC_TLS_IE_ADD:
3742 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3743 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3744 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3745 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3746 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3747 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3748 case BFD_RELOC_SPARC_GOTDATA_OP:
3749 code = fixp->fx_r_type;
3756 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3757 /* If we are generating PIC code, we need to generate a different
3761 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3763 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3766 #define GOTT_BASE "__GOTT_BASE__"
3767 #define GOTT_INDEX "__GOTT_INDEX__"
3770 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3776 case BFD_RELOC_32_PCREL_S2:
3777 if (generic_force_reloc (fixp))
3778 code = BFD_RELOC_SPARC_WPLT30;
3780 case BFD_RELOC_HI22:
3781 code = BFD_RELOC_SPARC_GOT22;
3782 if (fixp->fx_addsy != NULL)
3784 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3785 code = BFD_RELOC_SPARC_PC22;
3787 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3788 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3789 code = BFD_RELOC_HI22; /* Unchanged. */
3793 case BFD_RELOC_LO10:
3794 code = BFD_RELOC_SPARC_GOT10;
3795 if (fixp->fx_addsy != NULL)
3797 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3798 code = BFD_RELOC_SPARC_PC10;
3800 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3801 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3802 code = BFD_RELOC_LO10; /* Unchanged. */
3806 case BFD_RELOC_SPARC13:
3807 code = BFD_RELOC_SPARC_GOT13;
3813 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3815 /* Nothing is aligned in DWARF debugging sections. */
3816 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3819 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3820 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3821 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3825 if (code == BFD_RELOC_SPARC_OLO10)
3826 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3828 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3829 if (reloc->howto == 0)
3831 as_bad_where (fixp->fx_file, fixp->fx_line,
3832 _("internal error: can't export reloc type %d (`%s')"),
3833 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3839 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3842 if (reloc->howto->pc_relative == 0
3843 || code == BFD_RELOC_SPARC_PC10
3844 || code == BFD_RELOC_SPARC_PC22)
3845 reloc->addend = fixp->fx_addnumber;
3846 else if (sparc_pic_code
3847 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3848 && fixp->fx_addsy != NULL
3849 && (S_IS_EXTERNAL (fixp->fx_addsy)
3850 || S_IS_WEAK (fixp->fx_addsy))
3851 && S_IS_DEFINED (fixp->fx_addsy)
3852 && ! S_IS_COMMON (fixp->fx_addsy))
3853 reloc->addend = fixp->fx_addnumber;
3855 reloc->addend = fixp->fx_offset - reloc->address;
3857 #else /* elf or coff */
3859 if (code != BFD_RELOC_32_PCREL_S2
3860 && code != BFD_RELOC_SPARC_WDISP22
3861 && code != BFD_RELOC_SPARC_WDISP16
3862 && code != BFD_RELOC_SPARC_WDISP19
3863 && code != BFD_RELOC_SPARC_WDISP10
3864 && code != BFD_RELOC_SPARC_WPLT30
3865 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3866 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3867 reloc->addend = fixp->fx_addnumber;
3868 else if (symbol_section_p (fixp->fx_addsy))
3869 reloc->addend = (section->vma
3870 + fixp->fx_addnumber
3871 + md_pcrel_from (fixp));
3873 reloc->addend = fixp->fx_offset;
3876 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3877 on the same location. */
3878 if (code == BFD_RELOC_SPARC_OLO10)
3880 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3883 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3885 = symbol_get_bfdsym (section_symbol (absolute_section));
3886 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3887 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3888 reloc->addend = fixp->tc_fix_data;
3894 /* We have no need to default values of symbols. */
3897 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3902 /* Round up a section size to the appropriate boundary. */
3905 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3908 /* This is not right for ELF; a.out wants it, and COFF will force
3909 the alignment anyways. */
3910 valueT align = ((valueT) 1
3911 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3914 /* Turn alignment value into a mask. */
3916 newsize = (size + align) & ~align;
3923 /* Exactly what point is a PC-relative offset relative TO?
3924 On the sparc, they're relative to the address of the offset, plus
3925 its size. This gets us to the following instruction.
3926 (??? Is this right? FIXME-SOON) */
3928 md_pcrel_from (fixS *fixP)
3932 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3933 if (! sparc_pic_code
3934 || fixP->fx_addsy == NULL
3935 || symbol_section_p (fixP->fx_addsy))
3936 ret += fixP->fx_size;
3940 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3951 for (shift = 0; (value & 1) == 0; value >>= 1)
3954 return (value == 1) ? shift : -1;
3957 /* Sort of like s_lcomm. */
3960 static int max_alignment = 15;
3964 s_reserve (int ignore ATTRIBUTE_UNUSED)
3974 name = input_line_pointer;
3975 c = get_symbol_end ();
3976 p = input_line_pointer;
3980 if (*input_line_pointer != ',')
3982 as_bad (_("Expected comma after name"));
3983 ignore_rest_of_line ();
3987 ++input_line_pointer;
3989 if ((size = get_absolute_expression ()) < 0)
3991 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3992 ignore_rest_of_line ();
3997 symbolP = symbol_find_or_make (name);
4000 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
4001 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
4003 as_bad (_("bad .reserve segment -- expected BSS segment"));
4007 if (input_line_pointer[2] == '.')
4008 input_line_pointer += 7;
4010 input_line_pointer += 6;
4013 if (*input_line_pointer == ',')
4015 ++input_line_pointer;
4018 if (*input_line_pointer == '\n')
4020 as_bad (_("missing alignment"));
4021 ignore_rest_of_line ();
4025 align = (int) get_absolute_expression ();
4028 if (align > max_alignment)
4030 align = max_alignment;
4031 as_warn (_("alignment too large; assuming %d"), align);
4037 as_bad (_("negative alignment"));
4038 ignore_rest_of_line ();
4044 temp = mylog2 (align);
4047 as_bad (_("alignment not a power of 2"));
4048 ignore_rest_of_line ();
4055 record_alignment (bss_section, align);
4060 if (!S_IS_DEFINED (symbolP)
4062 && S_GET_OTHER (symbolP) == 0
4063 && S_GET_DESC (symbolP) == 0
4070 segT current_seg = now_seg;
4071 subsegT current_subseg = now_subseg;
4073 /* Switch to bss. */
4074 subseg_set (bss_section, 1);
4078 frag_align (align, 0, 0);
4080 /* Detach from old frag. */
4081 if (S_GET_SEGMENT (symbolP) == bss_section)
4082 symbol_get_frag (symbolP)->fr_symbol = NULL;
4084 symbol_set_frag (symbolP, frag_now);
4085 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4086 (offsetT) size, (char *) 0);
4089 S_SET_SEGMENT (symbolP, bss_section);
4091 subseg_set (current_seg, current_subseg);
4094 S_SET_SIZE (symbolP, size);
4100 as_warn (_("Ignoring attempt to re-define symbol %s"),
4101 S_GET_NAME (symbolP));
4104 demand_empty_rest_of_line ();
4108 s_common (int ignore ATTRIBUTE_UNUSED)
4116 name = input_line_pointer;
4117 c = get_symbol_end ();
4118 /* Just after name is now '\0'. */
4119 p = input_line_pointer;
4122 if (*input_line_pointer != ',')
4124 as_bad (_("Expected comma after symbol-name"));
4125 ignore_rest_of_line ();
4130 input_line_pointer++;
4132 if ((temp = get_absolute_expression ()) < 0)
4134 as_bad (_(".COMMon length (%lu) out of range ignored"),
4135 (unsigned long) temp);
4136 ignore_rest_of_line ();
4141 symbolP = symbol_find_or_make (name);
4143 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4145 as_bad (_("Ignoring attempt to re-define symbol"));
4146 ignore_rest_of_line ();
4149 if (S_GET_VALUE (symbolP) != 0)
4151 if (S_GET_VALUE (symbolP) != (valueT) size)
4153 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4154 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4160 S_SET_VALUE (symbolP, (valueT) size);
4161 S_SET_EXTERNAL (symbolP);
4164 know (symbol_get_frag (symbolP) == &zero_address_frag);
4165 if (*input_line_pointer != ',')
4167 as_bad (_("Expected comma after common length"));
4168 ignore_rest_of_line ();
4171 input_line_pointer++;
4173 if (*input_line_pointer != '"')
4175 temp = get_absolute_expression ();
4178 if (temp > max_alignment)
4180 temp = max_alignment;
4181 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4187 as_bad (_("negative alignment"));
4188 ignore_rest_of_line ();
4193 if (symbol_get_obj (symbolP)->local)
4200 old_subsec = now_subseg;
4205 align = mylog2 (temp);
4209 as_bad (_("alignment not a power of 2"));
4210 ignore_rest_of_line ();
4214 record_alignment (bss_section, align);
4215 subseg_set (bss_section, 0);
4217 frag_align (align, 0, 0);
4218 if (S_GET_SEGMENT (symbolP) == bss_section)
4219 symbol_get_frag (symbolP)->fr_symbol = 0;
4220 symbol_set_frag (symbolP, frag_now);
4221 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4222 (offsetT) size, (char *) 0);
4224 S_SET_SEGMENT (symbolP, bss_section);
4225 S_CLEAR_EXTERNAL (symbolP);
4226 S_SET_SIZE (symbolP, size);
4227 subseg_set (old_sec, old_subsec);
4230 #endif /* OBJ_ELF */
4233 S_SET_VALUE (symbolP, (valueT) size);
4235 S_SET_ALIGN (symbolP, temp);
4236 S_SET_SIZE (symbolP, size);
4238 S_SET_EXTERNAL (symbolP);
4239 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4244 input_line_pointer++;
4245 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4246 if (*input_line_pointer == '.')
4247 input_line_pointer++;
4248 /* @@ Some say data, some say bss. */
4249 if (strncmp (input_line_pointer, "bss\"", 4)
4250 && strncmp (input_line_pointer, "data\"", 5))
4252 while (*--input_line_pointer != '"')
4254 input_line_pointer--;
4255 goto bad_common_segment;
4257 while (*input_line_pointer++ != '"')
4259 goto allocate_common;
4262 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4264 demand_empty_rest_of_line ();
4269 p = input_line_pointer;
4270 while (*p && *p != '\n')
4274 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4276 input_line_pointer = p;
4277 ignore_rest_of_line ();
4282 /* Handle the .empty pseudo-op. This suppresses the warnings about
4283 invalid delay slot usage. */
4286 s_empty (int ignore ATTRIBUTE_UNUSED)
4288 /* The easy way to implement is to just forget about the last
4294 s_seg (int ignore ATTRIBUTE_UNUSED)
4297 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4299 input_line_pointer += 6;
4303 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4305 input_line_pointer += 6;
4309 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4311 input_line_pointer += 7;
4315 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4317 input_line_pointer += 5;
4318 /* We only support 2 segments -- text and data -- for now, so
4319 things in the "bss segment" will have to go into data for now.
4320 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4321 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4324 as_bad (_("Unknown segment type"));
4325 demand_empty_rest_of_line ();
4331 subseg_set (data_section, 1);
4332 demand_empty_rest_of_line ();
4336 s_proc (int ignore ATTRIBUTE_UNUSED)
4338 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4340 ++input_line_pointer;
4342 ++input_line_pointer;
4345 /* This static variable is set by s_uacons to tell sparc_cons_align
4346 that the expression does not need to be aligned. */
4348 static int sparc_no_align_cons = 0;
4350 /* This handles the unaligned space allocation pseudo-ops, such as
4351 .uaword. .uaword is just like .word, but the value does not need
4355 s_uacons (int bytes)
4357 /* Tell sparc_cons_align not to align this value. */
4358 sparc_no_align_cons = 1;
4360 sparc_no_align_cons = 0;
4363 /* This handles the native word allocation pseudo-op .nword.
4364 For sparc_arch_size 32 it is equivalent to .word, for
4365 sparc_arch_size 64 it is equivalent to .xword. */
4368 s_ncons (int bytes ATTRIBUTE_UNUSED)
4370 cons (sparc_arch_size == 32 ? 4 : 8);
4374 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4378 .register %g[2367],{#scratch|symbolname|#ignore}
4382 s_register (int ignore ATTRIBUTE_UNUSED)
4387 const char *regname;
4389 if (input_line_pointer[0] != '%'
4390 || input_line_pointer[1] != 'g'
4391 || ((input_line_pointer[2] & ~1) != '2'
4392 && (input_line_pointer[2] & ~1) != '6')
4393 || input_line_pointer[3] != ',')
4394 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4395 reg = input_line_pointer[2] - '0';
4396 input_line_pointer += 4;
4398 if (*input_line_pointer == '#')
4400 ++input_line_pointer;
4401 regname = input_line_pointer;
4402 c = get_symbol_end ();
4403 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4404 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4405 if (regname[0] == 'i')
4412 regname = input_line_pointer;
4413 c = get_symbol_end ();
4415 if (sparc_arch_size == 64)
4419 if ((regname && globals[reg] != (symbolS *) 1
4420 && strcmp (S_GET_NAME (globals[reg]), regname))
4421 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4422 as_bad (_("redefinition of global register"));
4426 if (regname == NULL)
4427 globals[reg] = (symbolS *) 1;
4432 if (symbol_find (regname))
4433 as_bad (_("Register symbol %s already defined."),
4436 globals[reg] = symbol_make (regname);
4437 flags = symbol_get_bfdsym (globals[reg])->flags;
4439 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4440 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4441 flags |= BSF_GLOBAL;
4442 symbol_get_bfdsym (globals[reg])->flags = flags;
4443 S_SET_VALUE (globals[reg], (valueT) reg);
4444 S_SET_ALIGN (globals[reg], reg);
4445 S_SET_SIZE (globals[reg], 0);
4446 /* Although we actually want undefined_section here,
4447 we have to use absolute_section, because otherwise
4448 generic as code will make it a COM section.
4449 We fix this up in sparc_adjust_symtab. */
4450 S_SET_SEGMENT (globals[reg], absolute_section);
4451 S_SET_OTHER (globals[reg], 0);
4452 elf_symbol (symbol_get_bfdsym (globals[reg]))
4453 ->internal_elf_sym.st_info =
4454 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4455 elf_symbol (symbol_get_bfdsym (globals[reg]))
4456 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4461 *input_line_pointer = c;
4463 demand_empty_rest_of_line ();
4466 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4467 symbols which need it. */
4470 sparc_adjust_symtab (void)
4474 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4476 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4477 ->internal_elf_sym.st_info) != STT_REGISTER)
4480 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4481 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4484 S_SET_SEGMENT (sym, undefined_section);
4489 /* If the --enforce-aligned-data option is used, we require .word,
4490 et. al., to be aligned correctly. We do it by setting up an
4491 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4492 no unexpected alignment was introduced.
4494 The SunOS and Solaris native assemblers enforce aligned data by
4495 default. We don't want to do that, because gcc can deliberately
4496 generate misaligned data if the packed attribute is used. Instead,
4497 we permit misaligned data by default, and permit the user to set an
4498 option to check for it. */
4501 sparc_cons_align (int nbytes)
4505 /* Only do this if we are enforcing aligned data. */
4506 if (! enforce_aligned_data)
4509 /* Don't align if this is an unaligned pseudo-op. */
4510 if (sparc_no_align_cons)
4513 nalign = mylog2 (nbytes);
4517 gas_assert (nalign > 0);
4519 if (now_seg == absolute_section)
4521 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4522 as_bad (_("misaligned data"));
4526 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4527 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4529 record_alignment (now_seg, nalign);
4532 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4535 sparc_handle_align (fragS *fragp)
4540 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4542 switch (fragp->fr_type)
4546 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4550 p = fragp->fr_literal + fragp->fr_fix;
4561 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4563 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4564 if (INSN_BIG_ENDIAN)
4565 number_to_chars_bigendian (p, wval, 4);
4567 number_to_chars_littleendian (p, wval, 4);
4573 if (INSN_BIG_ENDIAN)
4574 number_to_chars_bigendian (p, 0x01000000, 4);
4576 number_to_chars_littleendian (p, 0x01000000, 4);
4578 fragp->fr_fix += fix;
4588 /* Some special processing for a Sparc ELF file. */
4591 sparc_elf_final_processing (void)
4593 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4594 sort of BFD interface for this. */
4595 if (sparc_arch_size == 64)
4597 switch (sparc_memory_model)
4600 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4603 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4609 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4610 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4611 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4612 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4613 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4614 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4618 sparc_cons (expressionS *exp, int size)
4621 const char *sparc_cons_special_reloc = NULL;
4624 save = input_line_pointer;
4625 if (input_line_pointer[0] == '%'
4626 && input_line_pointer[1] == 'r'
4627 && input_line_pointer[2] == '_')
4629 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4631 input_line_pointer += 7;
4632 sparc_cons_special_reloc = "disp";
4634 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4636 if (size != 4 && size != 8)
4637 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4640 input_line_pointer += 6;
4641 sparc_cons_special_reloc = "plt";
4644 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4646 if (size != 4 && size != 8)
4647 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4650 input_line_pointer += 13;
4651 sparc_cons_special_reloc = "tls_dtpoff";
4654 if (sparc_cons_special_reloc)
4661 if (*input_line_pointer != '8')
4663 input_line_pointer--;
4666 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4670 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4674 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4684 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4685 sparc_cons_special_reloc, size * 8, size);
4689 input_line_pointer += 2;
4690 if (*input_line_pointer != '(')
4692 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4693 sparc_cons_special_reloc, size * 8);
4700 input_line_pointer = save;
4701 sparc_cons_special_reloc = NULL;
4706 char *end = ++input_line_pointer;
4709 while (! is_end_of_line[(c = *end)])
4723 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4724 sparc_cons_special_reloc, size * 8);
4730 if (input_line_pointer != end)
4732 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4733 sparc_cons_special_reloc, size * 8);
4737 input_line_pointer++;
4739 c = *input_line_pointer;
4740 if (! is_end_of_line[c] && c != ',')
4741 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4742 sparc_cons_special_reloc, size * 8);
4748 if (sparc_cons_special_reloc == NULL)
4750 return sparc_cons_special_reloc;
4755 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4756 reloc for a cons. We could use the definition there, except that
4757 we want to handle little endian relocs specially. */
4760 cons_fix_new_sparc (fragS *frag,
4762 unsigned int nbytes,
4764 const char *sparc_cons_special_reloc)
4766 bfd_reloc_code_real_type r;
4768 r = (nbytes == 1 ? BFD_RELOC_8 :
4769 (nbytes == 2 ? BFD_RELOC_16 :
4770 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4772 if (target_little_endian_data
4774 && now_seg->flags & SEC_ALLOC)
4775 r = BFD_RELOC_SPARC_REV32;
4777 if (sparc_cons_special_reloc)
4779 if (*sparc_cons_special_reloc == 'd')
4782 case 1: r = BFD_RELOC_8_PCREL; break;
4783 case 2: r = BFD_RELOC_16_PCREL; break;
4784 case 4: r = BFD_RELOC_32_PCREL; break;
4785 case 8: r = BFD_RELOC_64_PCREL; break;
4788 else if (*sparc_cons_special_reloc == 'p')
4791 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4792 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4797 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4798 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4801 else if (sparc_no_align_cons)
4805 case 2: r = BFD_RELOC_SPARC_UA16; break;
4806 case 4: r = BFD_RELOC_SPARC_UA32; break;
4807 case 8: r = BFD_RELOC_SPARC_UA64; break;
4812 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4816 sparc_cfi_frame_initial_instructions (void)
4818 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4822 sparc_regname_to_dw2regnum (char *regname)
4830 p = strchr (q, regname[0]);
4833 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4835 return (p - q) * 8 + regname[1] - '0';
4837 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4839 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4841 if (regname[0] == 'f' || regname[0] == 'r')
4843 unsigned int regnum;
4845 regnum = strtoul (regname + 1, &q, 10);
4848 if (regnum >= ((regname[0] == 'f'
4849 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4852 if (regname[0] == 'f')
4855 if (regnum >= 64 && (regnum & 1))
4864 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4866 sparc_no_align_cons = 1;
4867 emit_expr_with_reloc (exp, nbytes, "disp");
4868 sparc_no_align_cons = 0;