1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode *insn_mo;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch[] = DEFAULT_ARCH;
64 static unsigned xlen = 0; /* width of an x-register */
65 static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
66 static bfd_boolean rve_abi = FALSE;
68 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
69 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
71 static unsigned elf_flags = 0;
73 /* This is the set of options which the .option pseudo-op may modify. */
75 struct riscv_set_options
77 int pic; /* Generate position-independent code. */
78 int rvc; /* Generate RVC code. */
79 int rve; /* Generate RVE code. */
80 int relax; /* Emit relocs the linker is allowed to relax. */
83 static struct riscv_set_options riscv_opts =
92 riscv_set_rvc (bfd_boolean rvc_value)
95 elf_flags |= EF_RISCV_RVC;
97 riscv_opts.rvc = rvc_value;
101 riscv_set_rve (bfd_boolean rve_value)
103 riscv_opts.rve = rve_value;
110 struct riscv_subset *next;
113 static struct riscv_subset *riscv_subsets;
116 riscv_subset_supports (const char *feature)
118 struct riscv_subset *s;
120 unsigned xlen_required = strtoul (feature, &p, 10);
122 if (xlen_required && xlen != xlen_required)
125 for (s = riscv_subsets; s != NULL; s = s->next)
126 if (strcasecmp (s->name, p) == 0)
133 riscv_clear_subsets (void)
135 while (riscv_subsets != NULL)
137 struct riscv_subset *next = riscv_subsets->next;
138 free ((void *) riscv_subsets->name);
139 free (riscv_subsets);
140 riscv_subsets = next;
145 riscv_add_subset (const char *subset)
147 struct riscv_subset *s = xmalloc (sizeof *s);
149 s->name = xstrdup (subset);
150 s->next = riscv_subsets;
154 /* Set which ISA and extensions are available. */
157 riscv_set_arch (const char *s)
159 const char *all_subsets = "imafdqc";
160 char *extension = NULL;
163 riscv_clear_subsets();
165 if (strncmp (p, "rv32", 4) == 0)
170 else if (strncmp (p, "rv64", 4) == 0)
176 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s);
185 riscv_add_subset ("e");
186 riscv_add_subset ("i");
189 as_fatal ("-march=%s: rv%de is not a valid base ISA", s, xlen);
195 for ( ; *all_subsets != 'q'; all_subsets++)
197 const char subset[] = {*all_subsets, '\0'};
198 riscv_add_subset (subset);
203 as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s);
210 char *subset = xstrdup (p);
213 while (*++q != '\0' && *q != '_')
218 as_fatal ("-march=%s: only one non-standard extension is supported"
219 " (found `%s' and `%s')", s, extension, subset);
221 riscv_add_subset (subset);
222 p += strlen (subset);
226 else if ((all_subsets = strchr (all_subsets, *p)) != NULL)
228 const char subset[] = {*p, 0};
229 riscv_add_subset (subset);
234 as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
237 if (riscv_subset_supports ("e") && riscv_subset_supports ("f"))
238 as_fatal ("-march=%s: rv32e does not support the `f' extension", s);
240 if (riscv_subset_supports ("d") && !riscv_subset_supports ("f"))
241 as_fatal ("-march=%s: `d' extension requires `f' extension", s);
243 if (riscv_subset_supports ("q") && !riscv_subset_supports ("d"))
244 as_fatal ("-march=%s: `q' extension requires `d' extension", s);
246 if (riscv_subset_supports ("q") && xlen < 64)
247 as_fatal ("-march=%s: rv32 does not support the `q' extension", s);
252 /* Handle of the OPCODE hash table. */
253 static struct hash_control *op_hash = NULL;
255 /* Handle of the type of .insn hash table. */
256 static struct hash_control *insn_type_hash = NULL;
258 /* This array holds the chars that always start a comment. If the
259 pre-processor is disabled, these aren't very useful */
260 const char comment_chars[] = "#";
262 /* This array holds the chars that only start a comment at the beginning of
263 a line. If the line seems to have the form '# 123 filename'
264 .line and .file directives will appear in the pre-processed output */
265 /* Note that input_file.c hand checks for '#' at the beginning of the
266 first line of the input file. This is because the compiler outputs
267 #NO_APP at the beginning of its output. */
268 /* Also note that C style comments are always supported. */
269 const char line_comment_chars[] = "#";
271 /* This array holds machine specific line separator characters. */
272 const char line_separator_chars[] = ";";
274 /* Chars that can be used to separate mant from exp in floating point nums */
275 const char EXP_CHARS[] = "eE";
277 /* Chars that mean this number is a floating point constant */
280 const char FLT_CHARS[] = "rRsSfFdDxXpP";
282 /* Macros for encoding relaxation state for RVC branches and far jumps. */
283 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
286 | ((uncond) ? 1 : 0) \
289 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
290 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
291 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
292 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
294 /* Is the given value a sign-extended 32-bit value? */
295 #define IS_SEXT_32BIT_NUM(x) \
296 (((x) &~ (offsetT) 0x7fffffff) == 0 \
297 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
299 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
300 #define IS_ZEXT_32BIT_NUM(x) \
301 (((x) &~ (offsetT) 0xffffffff) == 0 \
302 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
304 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
305 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
306 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
307 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
309 /* Determine if an instruction matches an opcode. */
310 #define OPCODE_MATCHES(OPCODE, OP) \
311 (((OPCODE) & MASK_##OP) == MATCH_##OP)
313 static char *expr_end;
315 /* The default target format to use. */
318 riscv_target_format (void)
320 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
323 /* Return the length of instruction INSN. */
325 static inline unsigned int
326 insn_length (const struct riscv_cl_insn *insn)
328 return riscv_insn_length (insn->insn_opcode);
331 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
334 create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
337 insn->insn_opcode = mo->match;
343 /* Install INSN at the location specified by its "frag" and "where" fields. */
346 install_insn (const struct riscv_cl_insn *insn)
348 char *f = insn->frag->fr_literal + insn->where;
349 md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
352 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
353 and install the opcode in the new location. */
356 move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
360 if (insn->fixp != NULL)
362 insn->fixp->fx_frag = frag;
363 insn->fixp->fx_where = where;
368 /* Add INSN to the end of the output. */
371 add_fixed_insn (struct riscv_cl_insn *insn)
373 char *f = frag_more (insn_length (insn));
374 move_insn (insn, frag_now, f - frag_now->fr_literal);
378 add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
379 relax_substateT subtype, symbolS *symbol, offsetT offset)
381 frag_grow (max_chars);
382 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
383 frag_var (rs_machine_dependent, max_chars, var,
384 subtype, symbol, offset, NULL);
387 /* Compute the length of a branch sequence, and adjust the stored length
388 accordingly. If FRAGP is NULL, the worst-case length is returned. */
391 relaxed_branch_length (fragS *fragp, asection *sec, int update)
393 int jump, rvc, length = 8;
398 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
399 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
400 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
402 /* Assume jumps are in range; the linker will catch any that aren't. */
403 length = jump ? 4 : 8;
405 if (fragp->fr_symbol != NULL
406 && S_IS_DEFINED (fragp->fr_symbol)
407 && !S_IS_WEAK (fragp->fr_symbol)
408 && sec == S_GET_SEGMENT (fragp->fr_symbol))
410 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
411 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
412 val -= fragp->fr_address + fragp->fr_fix;
414 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
416 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
418 else if (!jump && rvc)
423 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
428 /* Information about an opcode name, mnemonics and its value. */
435 /* List for all supported opcode name. */
436 static const struct opcode_name_t opcode_name_list[] =
481 /* Hash table for lookup opcode name. */
482 static struct hash_control *opcode_names_hash = NULL;
484 /* Initialization for hash table of opcode name. */
486 init_opcode_names_hash (void)
489 const struct opcode_name_t *opcode;
491 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
493 retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
496 as_fatal (_("internal error: can't hash `%s': %s"),
497 opcode->name, retval);
501 /* Find `s` is a valid opcode name or not,
502 return the opcode name info if found. */
503 static const struct opcode_name_t *
504 opcode_name_lookup (char **s)
508 struct opcode_name_t *o;
510 /* Find end of name. */
512 if (is_name_beginner (*e))
514 while (is_part_of_name (*e))
517 /* Terminate name. */
521 o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
523 /* Advance to next token if one was recognized. */
547 static struct hash_control *reg_names_hash = NULL;
549 #define ENCODE_REG_HASH(cls, n) \
550 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
551 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
552 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
555 hash_reg_name (enum reg_class class, const char *name, unsigned n)
557 void *hash = ENCODE_REG_HASH (class, n);
558 const char *retval = hash_insert (reg_names_hash, name, hash);
561 as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
565 hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
569 for (i = 0; i < n; i++)
570 hash_reg_name (class, names[i], i);
574 reg_lookup_internal (const char *s, enum reg_class class)
576 struct regname *r = (struct regname *) hash_find (reg_names_hash, s);
578 if (r == NULL || DECODE_REG_CLASS (r) != class)
581 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
584 return DECODE_REG_NUM (r);
588 reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
594 /* Find end of name. */
596 if (is_name_beginner (*e))
598 while (is_part_of_name (*e))
601 /* Terminate name. */
605 /* Look for the register. Advance to next token if one was recognized. */
606 if ((reg = reg_lookup_internal (*s, class)) >= 0)
616 arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
618 const char *p = strchr (*s, ',');
619 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
621 for (i = 0; i < size; i++)
622 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
632 /* For consistency checking, verify that all bits are specified either
633 by the match/mask part of the instruction definition, or by the
636 `length` could be 0, 4 or 8, 0 for auto detection. */
638 validate_riscv_insn (const struct riscv_opcode *opc, int length)
640 const char *p = opc->args;
642 insn_t used_bits = opc->mask;
644 insn_t required_bits;
647 insn_width = 8 * riscv_insn_length (opc->match);
649 insn_width = 8 * length;
651 required_bits = ~0ULL >> (64 - insn_width);
653 if ((used_bits & opc->match) != (opc->match & required_bits))
655 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
656 opc->name, opc->args);
660 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
667 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
668 case 'c': break; /* RS1, constrained to equal sp */
669 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
670 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
671 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
672 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
673 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
674 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
675 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
676 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
677 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
678 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
679 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
680 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
681 case 'w': break; /* RS1S, constrained to equal RD */
682 case 'x': break; /* RS2S, constrained to equal RD */
683 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
684 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
685 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
686 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
687 case 'U': break; /* RS1, constrained to equal RD */
688 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
689 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
690 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
691 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
692 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
693 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
694 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
695 case 'F': /* funct */
698 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
699 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
701 as_bad (_("internal: bad RISC-V opcode"
702 " (unknown operand type `CF%c'): %s %s"),
703 c, opc->name, opc->args);
708 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
709 c, opc->name, opc->args);
716 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
717 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
719 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
720 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
721 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
723 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
724 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
725 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
726 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
727 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
728 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
729 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
730 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
731 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
732 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
733 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
735 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
736 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
737 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
738 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
739 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
744 case 'F': /* funct */
747 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
748 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
749 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
751 as_bad (_("internal: bad RISC-V opcode"
752 " (unknown operand type `F%c'): %s %s"),
753 c, opc->name, opc->args);
757 case 'O': /* opcode */
760 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
761 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
763 as_bad (_("internal: bad RISC-V opcode"
764 " (unknown operand type `F%c'): %s %s"),
765 c, opc->name, opc->args);
770 as_bad (_("internal: bad RISC-V opcode "
771 "(unknown operand type `%c'): %s %s"),
772 c, opc->name, opc->args);
776 if (used_bits != required_bits)
778 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
779 ~(unsigned long)(used_bits & required_bits),
780 opc->name, opc->args);
786 struct percent_op_match
789 bfd_reloc_code_real_type reloc;
792 /* Common hash table initialization function for
793 instruction and .insn directive. */
794 static struct hash_control *
795 init_opcode_hash (const struct riscv_opcode *opcodes,
796 bfd_boolean insn_directive_p)
800 struct hash_control *hash = hash_new ();
801 while (opcodes[i].name)
803 const char *name = opcodes[i].name;
804 const char *hash_error =
805 hash_insert (hash, name, (void *) &opcodes[i]);
809 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
810 opcodes[i].name, hash_error);
811 /* Probably a memory allocation problem? Give up now. */
812 as_fatal (_("Broken assembler. No assembly attempted."));
817 if (opcodes[i].pinfo != INSN_MACRO)
819 if (insn_directive_p)
820 length = ((name[0] == 'c') ? 2 : 4);
822 length = 0; /* Let assembler determine the length. */
823 if (!validate_riscv_insn (&opcodes[i], length))
824 as_fatal (_("Broken assembler. No assembly attempted."));
827 gas_assert (!insn_directive_p);
830 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
836 /* This function is called once, at assembler startup time. It should set up
837 all the tables, etc. that the MD part of the assembler will need. */
842 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
844 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
845 as_warn (_("Could not set architecture and machine"));
847 op_hash = init_opcode_hash (riscv_opcodes, FALSE);
848 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
850 reg_names_hash = hash_new ();
851 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
852 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
853 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
854 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
856 opcode_names_hash = hash_new ();
857 init_opcode_names_hash ();
859 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
860 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
861 #include "opcode/riscv-opc.h"
864 /* Set the default alignment for the text section. */
865 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
869 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
876 case BFD_RELOC_RISCV_HI20:
877 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
879 case BFD_RELOC_RISCV_LO12_S:
880 return ENCODE_STYPE_IMM (value);
882 case BFD_RELOC_RISCV_LO12_I:
883 return ENCODE_ITYPE_IMM (value);
890 /* Output an instruction. IP is the instruction information.
891 ADDRESS_EXPR is an operand of the instruction to be used with
895 append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
896 bfd_reloc_code_real_type reloc_type)
898 dwarf2_emit_insn (0);
900 if (reloc_type != BFD_RELOC_UNUSED)
902 reloc_howto_type *howto;
904 gas_assert (address_expr);
905 if (reloc_type == BFD_RELOC_12_PCREL
906 || reloc_type == BFD_RELOC_RISCV_JMP)
908 int j = reloc_type == BFD_RELOC_RISCV_JMP;
909 int best_case = riscv_insn_length (ip->insn_opcode);
910 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
911 add_relaxed_insn (ip, worst_case, best_case,
912 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
913 address_expr->X_add_symbol,
914 address_expr->X_add_number);
919 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
921 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
923 ip->fixp = fix_new_exp (ip->frag, ip->where,
924 bfd_get_reloc_size (howto),
925 address_expr, FALSE, reloc_type);
927 ip->fixp->fx_tcbit = riscv_opts.relax;
934 /* We need to start a new frag after any instruction that can be
935 optimized away or compressed by the linker during relaxation, to prevent
936 the assembler from computing static offsets across such an instruction.
937 This is necessary to get correct EH info. */
938 if (reloc_type == BFD_RELOC_RISCV_CALL
939 || reloc_type == BFD_RELOC_RISCV_CALL_PLT
940 || reloc_type == BFD_RELOC_RISCV_HI20
941 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
942 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
943 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
945 frag_wane (frag_now);
950 /* Build an instruction created by a macro expansion. This is passed
951 a pointer to the count of instructions created so far, an
952 expression, the name of the instruction to build, an operand format
953 string, and corresponding arguments. */
956 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
958 const struct riscv_opcode *mo;
959 struct riscv_cl_insn insn;
960 bfd_reloc_code_real_type r;
963 va_start (args, fmt);
965 r = BFD_RELOC_UNUSED;
966 mo = (struct riscv_opcode *) hash_find (op_hash, name);
969 /* Find a non-RVC variant of the instruction. append_insn will compress
971 while (riscv_insn_length (mo->match) < 4)
973 gas_assert (strcmp (name, mo->name) == 0);
975 create_insn (&insn, mo);
981 INSERT_OPERAND (RD, insn, va_arg (args, int));
985 INSERT_OPERAND (RS1, insn, va_arg (args, int));
989 INSERT_OPERAND (RS2, insn, va_arg (args, int));
993 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
999 gas_assert (ep != NULL);
1000 r = va_arg (args, int);
1008 as_fatal (_("internal error: invalid macro"));
1013 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1015 append_insn (&insn, ep, r);
1018 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1021 normalize_constant_expr (expressionS *ex)
1025 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1026 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1027 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1031 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1032 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1035 check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1036 bfd_boolean maybe_csr)
1038 if (ex->X_op == O_big)
1039 as_bad (_("unsupported large constant"));
1040 else if (maybe_csr && ex->X_op == O_symbol)
1041 as_bad (_("unknown CSR `%s'"),
1042 S_GET_NAME (ex->X_add_symbol));
1043 else if (ex->X_op != O_constant)
1044 as_bad (_("Instruction %s requires absolute expression"),
1046 normalize_constant_expr (ex);
1050 make_internal_label (void)
1052 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
1053 (valueT) frag_now_fix (), frag_now);
1056 /* Load an entry from the GOT. */
1058 pcrel_access (int destreg, int tempreg, expressionS *ep,
1059 const char *lo_insn, const char *lo_pattern,
1060 bfd_reloc_code_real_type hi_reloc,
1061 bfd_reloc_code_real_type lo_reloc)
1064 ep2.X_op = O_symbol;
1065 ep2.X_add_symbol = make_internal_label ();
1066 ep2.X_add_number = 0;
1068 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1069 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1073 pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1074 bfd_reloc_code_real_type hi_reloc,
1075 bfd_reloc_code_real_type lo_reloc)
1077 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1081 pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1082 bfd_reloc_code_real_type hi_reloc,
1083 bfd_reloc_code_real_type lo_reloc)
1085 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1088 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1090 riscv_call (int destreg, int tempreg, expressionS *ep,
1091 bfd_reloc_code_real_type reloc)
1093 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1094 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1097 /* Load an integer constant into a register. */
1100 load_const (int reg, expressionS *ep)
1102 int shift = RISCV_IMM_BITS;
1103 expressionS upper = *ep, lower = *ep;
1104 lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
1105 upper.X_add_number -= lower.X_add_number;
1107 if (ep->X_op != O_constant)
1109 as_bad (_("unsupported large constant"));
1113 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
1115 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1116 while (((upper.X_add_number >> shift) & 1) == 0)
1119 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1120 load_const (reg, &upper);
1122 macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
1123 if (lower.X_add_number != 0)
1124 macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I);
1128 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1131 if (upper.X_add_number != 0)
1133 macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20);
1137 if (lower.X_add_number != 0 || hi_reg == 0)
1138 macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
1139 BFD_RELOC_RISCV_LO12_I);
1143 /* Expand RISC-V assembly macros into one or more instructions. */
1145 macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1146 bfd_reloc_code_real_type *imm_reloc)
1148 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1149 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1150 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1151 int mask = ip->insn_mo->mask;
1156 load_const (rd, imm_expr);
1161 /* Load the address of a symbol into a register. */
1162 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1163 as_bad (_("offset too large"));
1165 if (imm_expr->X_op == O_constant)
1166 load_const (rd, imm_expr);
1167 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
1168 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1169 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1170 else /* Local PIC symbol, or any non-PIC symbol */
1171 pcrel_load (rd, rd, imm_expr, "addi",
1172 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1176 pcrel_load (rd, rd, imm_expr, "addi",
1177 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1181 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1182 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1186 pcrel_load (rd, rd, imm_expr, "lb",
1187 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1191 pcrel_load (rd, rd, imm_expr, "lbu",
1192 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1196 pcrel_load (rd, rd, imm_expr, "lh",
1197 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1201 pcrel_load (rd, rd, imm_expr, "lhu",
1202 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1206 pcrel_load (rd, rd, imm_expr, "lw",
1207 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1211 pcrel_load (rd, rd, imm_expr, "lwu",
1212 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1216 pcrel_load (rd, rd, imm_expr, "ld",
1217 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1221 pcrel_load (rd, rs1, imm_expr, "flw",
1222 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1226 pcrel_load (rd, rs1, imm_expr, "fld",
1227 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1231 pcrel_store (rs2, rs1, imm_expr, "sb",
1232 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1236 pcrel_store (rs2, rs1, imm_expr, "sh",
1237 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1241 pcrel_store (rs2, rs1, imm_expr, "sw",
1242 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1246 pcrel_store (rs2, rs1, imm_expr, "sd",
1247 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1251 pcrel_store (rs2, rs1, imm_expr, "fsw",
1252 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1256 pcrel_store (rs2, rs1, imm_expr, "fsd",
1257 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1261 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1265 as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
1270 static const struct percent_op_match percent_op_utype[] =
1272 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1273 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
1274 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1275 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1276 {"%hi", BFD_RELOC_RISCV_HI20},
1280 static const struct percent_op_match percent_op_itype[] =
1282 {"%lo", BFD_RELOC_RISCV_LO12_I},
1283 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1284 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1288 static const struct percent_op_match percent_op_stype[] =
1290 {"%lo", BFD_RELOC_RISCV_LO12_S},
1291 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1292 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1296 static const struct percent_op_match percent_op_rtype[] =
1298 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1302 /* Return true if *STR points to a relocation operator. When returning true,
1303 move *STR over the operator and store its relocation code in *RELOC.
1304 Leave both *STR and *RELOC alone when returning false. */
1307 parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1308 const struct percent_op_match *percent_op)
1310 for ( ; percent_op->str; percent_op++)
1311 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1313 int len = strlen (percent_op->str);
1315 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1318 *str += strlen (percent_op->str);
1319 *reloc = percent_op->reloc;
1321 /* Check whether the output BFD supports this relocation.
1322 If not, issue an error and fall back on something safe. */
1323 if (*reloc != BFD_RELOC_UNUSED
1324 && !bfd_reloc_type_lookup (stdoutput, *reloc))
1326 as_bad ("relocation %s isn't supported by the current ABI",
1328 *reloc = BFD_RELOC_UNUSED;
1336 my_getExpression (expressionS *ep, char *str)
1340 save_in = input_line_pointer;
1341 input_line_pointer = str;
1343 expr_end = input_line_pointer;
1344 input_line_pointer = save_in;
1347 /* Parse string STR as a 16-bit relocatable operand. Store the
1348 expression in *EP and the relocation, if any, in RELOC.
1349 Return the number of relocation operators used (0 or 1).
1351 On exit, EXPR_END points to the first character after the expression. */
1354 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1355 char *str, const struct percent_op_match *percent_op)
1358 unsigned crux_depth, str_depth, regno;
1361 /* First, check for integer registers. */
1362 if (reg_lookup (&str, RCLASS_GPR, ®no))
1364 ep->X_op = O_register;
1365 ep->X_add_number = regno;
1369 /* Search for the start of the main expression.
1370 End the loop with CRUX pointing to the start
1371 of the main expression and with CRUX_DEPTH containing the number
1372 of open brackets at that point. */
1379 crux_depth = str_depth;
1381 /* Skip over whitespace and brackets, keeping count of the number
1383 while (*str == ' ' || *str == '\t' || *str == '(')
1389 && parse_relocation (&str, reloc, percent_op));
1391 my_getExpression (ep, crux);
1394 /* Match every open bracket. */
1395 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1400 as_bad ("unclosed '('");
1407 /* Parse opcode name, could be an mnemonics or number. */
1409 my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1410 char *str, const struct percent_op_match *percent_op)
1412 const struct opcode_name_t *o = opcode_name_lookup (&str);
1416 ep->X_op = O_constant;
1417 ep->X_add_number = o->val;
1421 return my_getSmallExpression (ep, reloc, str, percent_op);
1424 /* Detect and handle implicitly zero load-store offsets. For example,
1425 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1426 an implicit offset was detected. */
1429 riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
1431 /* Check whether there is only a single bracketed expression left.
1432 If so, it must be the base register and the constant must be zero. */
1433 if (*s == '(' && strchr (s + 1, '(') == 0)
1435 ep->X_op = O_constant;
1436 ep->X_add_number = 0;
1443 /* This routine assembles an instruction into its binary format. As a
1444 side effect, it sets the global variable imm_reloc to the type of
1445 relocation to do if one of the operands is an address expression. */
1448 riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
1449 bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash)
1454 struct riscv_opcode *insn;
1459 const struct percent_op_match *p;
1460 const char *error = "unrecognized opcode";
1462 /* Parse the name of the instruction. Terminate the string if whitespace
1463 is found so that hash_find only sees the name part of the string. */
1464 for (s = str; *s != '\0'; ++s)
1472 insn = (struct riscv_opcode *) hash_find (hash, str);
1475 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1477 if (!riscv_subset_supports (insn->subset))
1480 create_insn (ip, insn);
1483 imm_expr->X_op = O_absent;
1484 *imm_reloc = BFD_RELOC_UNUSED;
1485 p = percent_op_itype;
1487 for (args = insn->args;; ++args)
1489 s += strspn (s, " \t");
1492 case '\0': /* End of args. */
1493 if (insn->pinfo != INSN_MACRO)
1495 if (!insn->match_func (insn, ip->insn_opcode))
1498 /* For .insn, insn->match and insn->mask are 0. */
1499 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
1507 /* Successful assembly. */
1514 case 's': /* RS1 x8-x15 */
1515 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1516 || !(regno >= 8 && regno <= 15))
1518 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1520 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1521 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1522 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
1525 case 't': /* RS2 x8-x15 */
1526 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1527 || !(regno >= 8 && regno <= 15))
1529 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1531 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1532 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1533 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
1536 case 'U': /* RS1, constrained to equal RD. */
1537 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1538 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
1542 if (!reg_lookup (&s, RCLASS_GPR, ®no))
1544 INSERT_OPERAND (CRS2, *ip, regno);
1546 case 'c': /* RS1, constrained to equal sp. */
1547 if (!reg_lookup (&s, RCLASS_GPR, ®no)
1552 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1553 || imm_expr->X_op != O_constant
1554 || imm_expr->X_add_number <= 0
1555 || imm_expr->X_add_number >= 64)
1557 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1560 imm_expr->X_op = O_absent;
1563 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1564 || imm_expr->X_op != O_constant
1565 || !VALID_RVC_IMM (imm_expr->X_add_number)
1566 || imm_expr->X_add_number <= 0
1567 || imm_expr->X_add_number >= 32)
1569 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1572 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1573 || imm_expr->X_op != O_constant
1574 || !VALID_RVC_UIMM8 (imm_expr->X_add_number)
1575 || imm_expr->X_add_number < 0
1576 || imm_expr->X_add_number >= 256)
1578 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
1581 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1582 || imm_expr->X_op != O_constant
1583 || imm_expr->X_add_number == 0
1584 || !VALID_RVC_SIMM3 (imm_expr->X_add_number))
1586 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
1589 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1590 || imm_expr->X_op != O_constant
1591 || imm_expr->X_add_number == 0
1592 || !VALID_RVC_IMM (imm_expr->X_add_number))
1594 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1597 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1599 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1600 || imm_expr->X_op != O_constant
1601 || !VALID_RVC_LW_IMM (imm_expr->X_add_number))
1603 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
1606 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1608 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1609 || imm_expr->X_op != O_constant
1610 || !VALID_RVC_LD_IMM (imm_expr->X_add_number))
1612 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
1615 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1617 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1618 || imm_expr->X_op != O_constant
1619 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
1622 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
1625 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1627 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1628 || imm_expr->X_op != O_constant
1629 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
1632 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
1635 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1636 || imm_expr->X_op != O_constant
1637 /* C.addiw, c.li, and c.andi allow zero immediate.
1638 C.addi allows zero immediate as hint. Otherwise this
1640 || !VALID_RVC_IMM (imm_expr->X_add_number))
1642 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1645 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1646 || imm_expr->X_op != O_constant
1647 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
1648 || imm_expr->X_add_number == 0)
1651 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
1654 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1655 || imm_expr->X_op != O_constant
1656 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
1657 || imm_expr->X_add_number == 0)
1660 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
1663 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1665 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1666 || imm_expr->X_op != O_constant
1667 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
1670 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
1673 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1675 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1676 || imm_expr->X_op != O_constant
1677 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
1680 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
1683 p = percent_op_utype;
1684 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
1687 if (imm_expr->X_op != O_constant
1688 || imm_expr->X_add_number <= 0
1689 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
1690 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
1691 && (imm_expr->X_add_number <
1692 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
1694 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
1697 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1698 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
1699 || ((int32_t)imm_expr->X_add_number
1700 != imm_expr->X_add_number))
1702 imm_expr->X_add_number =
1703 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
1709 case 'S': /* Floating-point RS1 x8-x15. */
1710 if (!reg_lookup (&s, RCLASS_FPR, ®no)
1711 || !(regno >= 8 && regno <= 15))
1713 INSERT_OPERAND (CRS1S, *ip, regno % 8);
1715 case 'D': /* Floating-point RS2 x8-x15. */
1716 if (!reg_lookup (&s, RCLASS_FPR, ®no)
1717 || !(regno >= 8 && regno <= 15))
1719 INSERT_OPERAND (CRS2S, *ip, regno % 8);
1721 case 'T': /* Floating-point RS2. */
1722 if (!reg_lookup (&s, RCLASS_FPR, ®no))
1724 INSERT_OPERAND (CRS2, *ip, regno);
1730 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1731 || imm_expr->X_op != O_constant
1732 || imm_expr->X_add_number < 0
1733 || imm_expr->X_add_number >= 16)
1735 as_bad (_("bad value for funct4 field, "
1736 "value must be 0...15"));
1740 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
1741 imm_expr->X_op = O_absent;
1745 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
1746 || imm_expr->X_op != O_constant
1747 || imm_expr->X_add_number < 0
1748 || imm_expr->X_add_number >= 8)
1750 as_bad (_("bad value for funct3 field, "
1751 "value must be 0...7"));
1754 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
1755 imm_expr->X_op = O_absent;
1759 as_bad (_("bad compressed FUNCT field"
1760 " specifier 'CF%c'\n"),
1766 as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
1785 case '<': /* Shift amount, 0 - 31. */
1786 my_getExpression (imm_expr, s);
1787 check_absolute_expr (ip, imm_expr, FALSE);
1788 if ((unsigned long) imm_expr->X_add_number > 31)
1789 as_bad (_("Improper shift amount (%lu)"),
1790 (unsigned long) imm_expr->X_add_number);
1791 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
1792 imm_expr->X_op = O_absent;
1796 case '>': /* Shift amount, 0 - (XLEN-1). */
1797 my_getExpression (imm_expr, s);
1798 check_absolute_expr (ip, imm_expr, FALSE);
1799 if ((unsigned long) imm_expr->X_add_number >= xlen)
1800 as_bad (_("Improper shift amount (%lu)"),
1801 (unsigned long) imm_expr->X_add_number);
1802 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
1803 imm_expr->X_op = O_absent;
1807 case 'Z': /* CSRRxI immediate. */
1808 my_getExpression (imm_expr, s);
1809 check_absolute_expr (ip, imm_expr, FALSE);
1810 if ((unsigned long) imm_expr->X_add_number > 31)
1811 as_bad (_("Improper CSRxI immediate (%lu)"),
1812 (unsigned long) imm_expr->X_add_number);
1813 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
1814 imm_expr->X_op = O_absent;
1818 case 'E': /* Control register. */
1819 if (reg_lookup (&s, RCLASS_CSR, ®no))
1820 INSERT_OPERAND (CSR, *ip, regno);
1823 my_getExpression (imm_expr, s);
1824 check_absolute_expr (ip, imm_expr, TRUE);
1825 if ((unsigned long) imm_expr->X_add_number > 0xfff)
1826 as_bad (_("Improper CSR address (%lu)"),
1827 (unsigned long) imm_expr->X_add_number);
1828 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
1829 imm_expr->X_op = O_absent;
1834 case 'm': /* Rounding mode. */
1835 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no))
1837 INSERT_OPERAND (RM, *ip, regno);
1843 case 'Q': /* Fence predecessor/successor. */
1844 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
1848 INSERT_OPERAND (PRED, *ip, regno);
1850 INSERT_OPERAND (SUCC, *ip, regno);
1855 case 'd': /* Destination register. */
1856 case 's': /* Source register. */
1857 case 't': /* Target register. */
1858 case 'r': /* rs3. */
1859 if (reg_lookup (&s, RCLASS_GPR, ®no))
1865 /* Now that we have assembled one operand, we use the args
1866 string to figure out where it goes in the instruction. */
1870 INSERT_OPERAND (RS1, *ip, regno);
1873 INSERT_OPERAND (RD, *ip, regno);
1876 INSERT_OPERAND (RS2, *ip, regno);
1879 INSERT_OPERAND (RS3, *ip, regno);
1886 case 'D': /* Floating point rd. */
1887 case 'S': /* Floating point rs1. */
1888 case 'T': /* Floating point rs2. */
1889 case 'U': /* Floating point rs1 and rs2. */
1890 case 'R': /* Floating point rs3. */
1891 if (reg_lookup (&s, RCLASS_FPR, ®no))
1899 INSERT_OPERAND (RD, *ip, regno);
1902 INSERT_OPERAND (RS1, *ip, regno);
1905 INSERT_OPERAND (RS1, *ip, regno);
1908 INSERT_OPERAND (RS2, *ip, regno);
1911 INSERT_OPERAND (RS3, *ip, regno);
1920 my_getExpression (imm_expr, s);
1921 if (imm_expr->X_op != O_big
1922 && imm_expr->X_op != O_constant)
1924 normalize_constant_expr (imm_expr);
1929 my_getExpression (imm_expr, s);
1930 normalize_constant_expr (imm_expr);
1931 /* The 'A' format specifier must be a symbol. */
1932 if (imm_expr->X_op != O_symbol)
1934 *imm_reloc = BFD_RELOC_32;
1938 case 'j': /* Sign-extended immediate. */
1939 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
1940 p = percent_op_itype;
1942 case 'q': /* Store displacement. */
1943 p = percent_op_stype;
1944 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
1946 case 'o': /* Load displacement. */
1947 p = percent_op_itype;
1948 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
1950 case '0': /* AMO "displacement," which must be zero. */
1951 p = percent_op_rtype;
1952 *imm_reloc = BFD_RELOC_UNUSED;
1954 if (riscv_handle_implicit_zero_offset (imm_expr, s))
1957 /* If this value won't fit into a 16 bit offset, then go
1958 find a macro that will generate the 32 bit offset
1960 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
1962 normalize_constant_expr (imm_expr);
1963 if (imm_expr->X_op != O_constant
1964 || (*args == '0' && imm_expr->X_add_number != 0)
1965 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
1966 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
1973 case 'p': /* PC-relative offset. */
1975 *imm_reloc = BFD_RELOC_12_PCREL;
1976 my_getExpression (imm_expr, s);
1980 case 'u': /* Upper 20 bits. */
1981 p = percent_op_utype;
1982 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)
1983 && imm_expr->X_op == O_constant)
1985 if (imm_expr->X_add_number < 0
1986 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
1987 as_bad (_("lui expression not in range 0..1048575"));
1989 *imm_reloc = BFD_RELOC_RISCV_HI20;
1990 imm_expr->X_add_number <<= RISCV_IMM_BITS;
1995 case 'a': /* 20-bit PC-relative offset. */
1997 my_getExpression (imm_expr, s);
1999 *imm_reloc = BFD_RELOC_RISCV_JMP;
2003 my_getExpression (imm_expr, s);
2005 if (strcmp (s, "@plt") == 0)
2007 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2011 *imm_reloc = BFD_RELOC_RISCV_CALL;
2017 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2018 || imm_expr->X_op != O_constant
2019 || imm_expr->X_add_number < 0
2020 || imm_expr->X_add_number >= 128
2021 || (imm_expr->X_add_number & 0x3) != 3)
2023 as_bad (_("bad value for opcode field, "
2024 "value must be 0...127 and "
2025 "lower 2 bits must be 0x3"));
2029 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2030 imm_expr->X_op = O_absent;
2034 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2035 || imm_expr->X_op != O_constant
2036 || imm_expr->X_add_number < 0
2037 || imm_expr->X_add_number >= 3)
2039 as_bad (_("bad value for opcode field, "
2040 "value must be 0...2"));
2044 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2045 imm_expr->X_op = O_absent;
2049 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args);
2057 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2058 || imm_expr->X_op != O_constant
2059 || imm_expr->X_add_number < 0
2060 || imm_expr->X_add_number >= 128)
2062 as_bad (_("bad value for funct7 field, "
2063 "value must be 0...127"));
2067 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2068 imm_expr->X_op = O_absent;
2072 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2073 || imm_expr->X_op != O_constant
2074 || imm_expr->X_add_number < 0
2075 || imm_expr->X_add_number >= 8)
2077 as_bad (_("bad value for funct3 field, "
2078 "value must be 0...7"));
2082 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2083 imm_expr->X_op = O_absent;
2087 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2088 || imm_expr->X_op != O_constant
2089 || imm_expr->X_add_number < 0
2090 || imm_expr->X_add_number >= 4)
2092 as_bad (_("bad value for funct2 field, "
2093 "value must be 0...3"));
2097 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2098 imm_expr->X_op = O_absent;
2103 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args);
2108 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2109 || imm_expr->X_op != O_constant
2110 || imm_expr->X_add_number != 0)
2113 imm_expr->X_op = O_absent;
2117 as_fatal (_("internal error: bad argument type %c"), *args);
2122 error = _("illegal operands");
2126 /* Restore the character we might have clobbered above. */
2128 *(argsStart - 1) = save_c;
2134 md_assemble (char *str)
2136 struct riscv_cl_insn insn;
2137 expressionS imm_expr;
2138 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2140 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2144 as_bad ("%s `%s'", error, str);
2148 if (insn.insn_mo->pinfo == INSN_MACRO)
2149 macro (&insn, &imm_expr, &imm_reloc);
2151 append_insn (&insn, &imm_expr, imm_reloc);
2155 md_atof (int type, char *litP, int *sizeP)
2157 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2161 md_number_to_chars (char *buf, valueT val, int n)
2163 number_to_chars_littleendian (buf, val, n);
2166 const char *md_shortopts = "O::g::G:";
2170 OPTION_MARCH = OPTION_MD_BASE,
2179 struct option md_longopts[] =
2181 {"march", required_argument, NULL, OPTION_MARCH},
2182 {"fPIC", no_argument, NULL, OPTION_PIC},
2183 {"fpic", no_argument, NULL, OPTION_PIC},
2184 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2185 {"mabi", required_argument, NULL, OPTION_MABI},
2186 {"mrelax", no_argument, NULL, OPTION_RELAX},
2187 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2189 {NULL, no_argument, NULL, 0}
2191 size_t md_longopts_size = sizeof (md_longopts);
2194 FLOAT_ABI_DEFAULT = -1,
2200 static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
2203 riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
2205 abi_xlen = new_xlen;
2206 float_abi = new_float_abi;
2211 md_parse_option (int c, const char *arg)
2216 riscv_set_arch (arg);
2220 riscv_opts.pic = FALSE;
2224 riscv_opts.pic = TRUE;
2228 if (strcmp (arg, "ilp32") == 0)
2229 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
2230 else if (strcmp (arg, "ilp32e") == 0)
2231 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
2232 else if (strcmp (arg, "ilp32f") == 0)
2233 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
2234 else if (strcmp (arg, "ilp32d") == 0)
2235 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
2236 else if (strcmp (arg, "ilp32q") == 0)
2237 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
2238 else if (strcmp (arg, "lp64") == 0)
2239 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
2240 else if (strcmp (arg, "lp64f") == 0)
2241 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
2242 else if (strcmp (arg, "lp64d") == 0)
2243 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
2244 else if (strcmp (arg, "lp64q") == 0)
2245 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
2251 riscv_opts.relax = TRUE;
2254 case OPTION_NO_RELAX:
2255 riscv_opts.relax = FALSE;
2266 riscv_after_parse_args (void)
2270 if (strcmp (default_arch, "riscv32") == 0)
2272 else if (strcmp (default_arch, "riscv64") == 0)
2275 as_bad ("unknown default architecture `%s'", default_arch);
2278 if (riscv_subsets == NULL)
2279 riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
2281 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2282 riscv_set_rvc (FALSE);
2283 if (riscv_subset_supports ("c"))
2284 riscv_set_rvc (TRUE);
2286 riscv_add_subset ("c");
2288 /* Enable RVE if specified by the -march option. */
2289 riscv_set_rve (FALSE);
2290 if (riscv_subset_supports ("e"))
2291 riscv_set_rve (TRUE);
2293 /* Infer ABI from ISA if not specified on command line. */
2296 else if (abi_xlen > xlen)
2297 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
2298 else if (abi_xlen < xlen)
2299 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
2301 if (float_abi == FLOAT_ABI_DEFAULT)
2303 struct riscv_subset *subset;
2305 /* Assume soft-float unless D extension is present. */
2306 float_abi = FLOAT_ABI_SOFT;
2308 for (subset = riscv_subsets; subset != NULL; subset = subset->next)
2310 if (strcasecmp (subset->name, "D") == 0)
2311 float_abi = FLOAT_ABI_DOUBLE;
2312 if (strcasecmp (subset->name, "Q") == 0)
2313 float_abi = FLOAT_ABI_QUAD;
2318 elf_flags |= EF_RISCV_RVE;
2320 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2321 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
2325 md_pcrel_from (fixS *fixP)
2327 return fixP->fx_where + fixP->fx_frag->fr_address;
2330 /* Apply a fixup to the object file. */
2333 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2335 unsigned int subtype;
2336 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
2337 bfd_boolean relaxable = FALSE;
2341 /* Remember value for tc_gen_reloc. */
2342 fixP->fx_addnumber = *valP;
2344 switch (fixP->fx_r_type)
2346 case BFD_RELOC_RISCV_HI20:
2347 case BFD_RELOC_RISCV_LO12_I:
2348 case BFD_RELOC_RISCV_LO12_S:
2349 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2350 | bfd_getl32 (buf), buf);
2351 if (fixP->fx_addsy == NULL)
2352 fixP->fx_done = TRUE;
2356 case BFD_RELOC_RISCV_GOT_HI20:
2357 case BFD_RELOC_RISCV_ADD8:
2358 case BFD_RELOC_RISCV_ADD16:
2359 case BFD_RELOC_RISCV_ADD32:
2360 case BFD_RELOC_RISCV_ADD64:
2361 case BFD_RELOC_RISCV_SUB6:
2362 case BFD_RELOC_RISCV_SUB8:
2363 case BFD_RELOC_RISCV_SUB16:
2364 case BFD_RELOC_RISCV_SUB32:
2365 case BFD_RELOC_RISCV_SUB64:
2366 case BFD_RELOC_RISCV_RELAX:
2369 case BFD_RELOC_RISCV_TPREL_HI20:
2370 case BFD_RELOC_RISCV_TPREL_LO12_I:
2371 case BFD_RELOC_RISCV_TPREL_LO12_S:
2372 case BFD_RELOC_RISCV_TPREL_ADD:
2376 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2377 case BFD_RELOC_RISCV_TLS_GD_HI20:
2378 case BFD_RELOC_RISCV_TLS_DTPREL32:
2379 case BFD_RELOC_RISCV_TLS_DTPREL64:
2380 if (fixP->fx_addsy != NULL)
2381 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2383 as_bad_where (fixP->fx_file, fixP->fx_line,
2384 _("TLS relocation against a constant"));
2388 /* Use pc-relative relocation for FDE initial location.
2389 The symbol address in .eh_frame may be adjusted in
2390 _bfd_elf_discard_section_eh_frame, and the content of
2391 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2392 Therefore, we cannot insert a relocation whose addend symbol is
2393 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2394 if (fixP->fx_addsy && fixP->fx_subsy
2395 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
2396 && strcmp (sub_segment->name, ".eh_frame") == 0
2397 && S_GET_VALUE (fixP->fx_subsy)
2398 == fixP->fx_frag->fr_address + fixP->fx_where)
2400 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
2401 fixP->fx_subsy = NULL;
2408 case BFD_RELOC_RISCV_CFA:
2409 if (fixP->fx_addsy && fixP->fx_subsy)
2411 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2412 fixP->fx_next->fx_addsy = fixP->fx_subsy;
2413 fixP->fx_next->fx_subsy = NULL;
2414 fixP->fx_next->fx_offset = 0;
2415 fixP->fx_subsy = NULL;
2417 switch (fixP->fx_r_type)
2420 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
2421 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
2425 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
2426 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2430 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
2431 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2435 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
2436 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2439 case BFD_RELOC_RISCV_CFA:
2440 /* Load the byte to get the subtype. */
2441 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
2442 loc = fixP->fx_frag->fr_fix - (subtype & 7);
2445 case DW_CFA_advance_loc1:
2446 fixP->fx_where = loc + 1;
2447 fixP->fx_next->fx_where = loc + 1;
2448 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
2449 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
2452 case DW_CFA_advance_loc2:
2454 fixP->fx_next->fx_size = 2;
2455 fixP->fx_where = loc + 1;
2456 fixP->fx_next->fx_where = loc + 1;
2457 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
2458 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
2461 case DW_CFA_advance_loc4:
2463 fixP->fx_next->fx_size = 4;
2464 fixP->fx_where = loc;
2465 fixP->fx_next->fx_where = loc;
2466 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
2467 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
2471 if (subtype < 0x80 && (subtype & 0x40))
2473 /* DW_CFA_advance_loc */
2474 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
2475 fixP->fx_next->fx_frag = fixP->fx_frag;
2476 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
2477 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
2480 as_fatal (_("internal error: bad CFA value #%d"), subtype);
2486 /* This case is unreachable. */
2493 /* If we are deleting this reloc entry, we must fill in the
2494 value now. This can happen if we have a .word which is not
2495 resolved when it appears but is later defined. */
2496 if (fixP->fx_addsy == NULL)
2498 gas_assert (fixP->fx_size <= sizeof (valueT));
2499 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
2504 case BFD_RELOC_RISCV_JMP:
2507 /* Fill in a tentative value to improve objdump readability. */
2508 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2509 bfd_vma delta = target - md_pcrel_from (fixP);
2510 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
2514 case BFD_RELOC_12_PCREL:
2517 /* Fill in a tentative value to improve objdump readability. */
2518 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2519 bfd_vma delta = target - md_pcrel_from (fixP);
2520 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
2524 case BFD_RELOC_RISCV_RVC_BRANCH:
2527 /* Fill in a tentative value to improve objdump readability. */
2528 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2529 bfd_vma delta = target - md_pcrel_from (fixP);
2530 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
2534 case BFD_RELOC_RISCV_RVC_JUMP:
2537 /* Fill in a tentative value to improve objdump readability. */
2538 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
2539 bfd_vma delta = target - md_pcrel_from (fixP);
2540 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
2544 case BFD_RELOC_RISCV_CALL:
2545 case BFD_RELOC_RISCV_CALL_PLT:
2549 case BFD_RELOC_RISCV_PCREL_HI20:
2550 case BFD_RELOC_RISCV_PCREL_LO12_S:
2551 case BFD_RELOC_RISCV_PCREL_LO12_I:
2552 relaxable = riscv_opts.relax;
2555 case BFD_RELOC_RISCV_ALIGN:
2559 /* We ignore generic BFD relocations we don't know about. */
2560 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
2561 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
2564 if (fixP->fx_subsy != NULL)
2565 as_bad_where (fixP->fx_file, fixP->fx_line,
2566 _("unsupported symbol subtraction"));
2568 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2569 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
2571 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
2572 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
2573 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
2577 /* Because the value of .cfi_remember_state may changed after relaxation,
2578 we insert a fix to relocate it again in link-time. */
2581 riscv_pre_output_hook (void)
2583 const frchainS *frch;
2586 for (s = stdoutput->sections; s; s = s->next)
2587 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
2591 for (frag = frch->frch_root; frag; frag = frag->fr_next)
2593 if (frag->fr_type == rs_cfa)
2597 symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol;
2598 symbolS *op_symbol = frag->fr_symbol->sy_value.X_op_symbol;
2600 exp.X_op = O_subtract;
2601 exp.X_add_symbol = add_symbol;
2602 exp.X_add_number = 0;
2603 exp.X_op_symbol = op_symbol;
2605 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
2606 BFD_RELOC_RISCV_CFA);
2613 /* This structure is used to hold a stack of .option values. */
2615 struct riscv_option_stack
2617 struct riscv_option_stack *next;
2618 struct riscv_set_options options;
2621 static struct riscv_option_stack *riscv_opts_stack;
2623 /* Handle the .option pseudo-op. */
2626 s_riscv_option (int x ATTRIBUTE_UNUSED)
2628 char *name = input_line_pointer, ch;
2630 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2631 ++input_line_pointer;
2632 ch = *input_line_pointer;
2633 *input_line_pointer = '\0';
2635 if (strcmp (name, "rvc") == 0)
2636 riscv_set_rvc (TRUE);
2637 else if (strcmp (name, "norvc") == 0)
2638 riscv_set_rvc (FALSE);
2639 else if (strcmp (name, "pic") == 0)
2640 riscv_opts.pic = TRUE;
2641 else if (strcmp (name, "nopic") == 0)
2642 riscv_opts.pic = FALSE;
2643 else if (strcmp (name, "relax") == 0)
2644 riscv_opts.relax = TRUE;
2645 else if (strcmp (name, "norelax") == 0)
2646 riscv_opts.relax = FALSE;
2647 else if (strcmp (name, "push") == 0)
2649 struct riscv_option_stack *s;
2651 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
2652 s->next = riscv_opts_stack;
2653 s->options = riscv_opts;
2654 riscv_opts_stack = s;
2656 else if (strcmp (name, "pop") == 0)
2658 struct riscv_option_stack *s;
2660 s = riscv_opts_stack;
2662 as_bad (_(".option pop with no .option push"));
2665 riscv_opts = s->options;
2666 riscv_opts_stack = s->next;
2672 as_warn (_("Unrecognized .option directive: %s\n"), name);
2674 *input_line_pointer = ch;
2675 demand_empty_rest_of_line ();
2678 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2679 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2680 use in DWARF debug information. */
2683 s_dtprel (int bytes)
2690 if (ex.X_op != O_symbol)
2692 as_bad (_("Unsupported use of %s"), (bytes == 8
2695 ignore_rest_of_line ();
2698 p = frag_more (bytes);
2699 md_number_to_chars (p, 0, bytes);
2700 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
2702 ? BFD_RELOC_RISCV_TLS_DTPREL64
2703 : BFD_RELOC_RISCV_TLS_DTPREL32));
2705 demand_empty_rest_of_line ();
2708 /* Handle the .bss pseudo-op. */
2711 s_bss (int ignore ATTRIBUTE_UNUSED)
2713 subseg_set (bss_section, 0);
2714 demand_empty_rest_of_line ();
2718 riscv_make_nops (char *buf, bfd_vma bytes)
2722 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2723 means we are not within a valid instruction sequence. It is thus safe
2724 to use a zero byte, even though that is not a valid instruction. */
2728 /* Use at most one 2-byte NOP. */
2729 if ((bytes - i) % 4 == 2)
2731 md_number_to_chars (buf + i, RVC_NOP, 2);
2735 /* Fill the remainder with 4-byte NOPs. */
2736 for ( ; i < bytes; i += 4)
2737 md_number_to_chars (buf + i, RISCV_NOP, 4);
2740 /* Called from md_do_align. Used to create an alignment frag in a
2741 code section by emitting a worst-case NOP sequence that the linker
2742 will later relax to the correct number of NOPs. We can't compute
2743 the correct alignment now because of other linker relaxations. */
2746 riscv_frag_align_code (int n)
2748 bfd_vma bytes = (bfd_vma) 1 << n;
2749 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
2750 bfd_vma worst_case_bytes = bytes - insn_alignment;
2754 /* If we are moving to a smaller alignment than the instruction size, then no
2755 alignment is required. */
2756 if (bytes <= insn_alignment)
2759 nops = frag_more (worst_case_bytes);
2761 /* When not relaxing, riscv_handle_align handles code alignment. */
2762 if (!riscv_opts.relax)
2765 ex.X_op = O_constant;
2766 ex.X_add_number = worst_case_bytes;
2768 riscv_make_nops (nops, worst_case_bytes);
2770 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
2771 &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
2776 /* Implement HANDLE_ALIGN. */
2779 riscv_handle_align (fragS *fragP)
2781 switch (fragP->fr_type)
2784 /* When relaxing, riscv_frag_align_code handles code alignment. */
2785 if (!riscv_opts.relax)
2787 bfd_signed_vma count = fragP->fr_next->fr_address
2788 - fragP->fr_address - fragP->fr_fix;
2793 count &= MAX_MEM_FOR_RS_ALIGN_CODE;
2794 riscv_make_nops (fragP->fr_literal + fragP->fr_fix, count);
2795 fragP->fr_var = count;
2805 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
2807 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
2810 /* Translate internal representation of relocation info to BFD target
2814 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
2816 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
2818 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2819 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2820 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2821 reloc->addend = fixp->fx_addnumber;
2823 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2824 if (reloc->howto == NULL)
2826 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
2827 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
2829 /* We don't have R_RISCV_8/16, but for this special case,
2830 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2834 as_bad_where (fixp->fx_file, fixp->fx_line,
2835 _("cannot represent %s relocation in object file"),
2836 bfd_get_reloc_code_name (fixp->fx_r_type));
2844 riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
2846 if (RELAX_BRANCH_P (fragp->fr_subtype))
2848 offsetT old_var = fragp->fr_var;
2849 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
2850 return fragp->fr_var - old_var;
2856 /* Expand far branches to multi-instruction sequences. */
2859 md_convert_frag_branch (fragS *fragp)
2867 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
2869 exp.X_op = O_symbol;
2870 exp.X_add_symbol = fragp->fr_symbol;
2871 exp.X_add_number = fragp->fr_offset;
2873 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
2875 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
2877 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2881 /* Expand the RVC branch into a RISC-V one. */
2882 insn = bfd_getl16 (buf);
2883 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
2884 if ((insn & MASK_C_J) == MATCH_C_J)
2886 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
2887 insn = MATCH_JAL | (X_RA << OP_SH_RD);
2888 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
2889 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
2890 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
2891 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
2894 bfd_putl32 (insn, buf);
2898 /* Invert the branch condition. Branch over the jump. */
2899 insn = bfd_getl16 (buf);
2900 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
2901 insn |= ENCODE_RVC_B_IMM (6);
2902 bfd_putl16 (insn, buf);
2907 /* Just keep the RVC branch. */
2908 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2909 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
2910 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2911 2, &exp, FALSE, reloc);
2920 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
2923 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
2925 /* Invert the branch condition. Branch over the jump. */
2926 insn = bfd_getl32 (buf);
2927 insn ^= MATCH_BEQ ^ MATCH_BNE;
2928 insn |= ENCODE_SBTYPE_IMM (8);
2929 md_number_to_chars ((char *) buf, insn, 4);
2933 /* Jump to the target. */
2934 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2935 4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
2936 md_number_to_chars ((char *) buf, MATCH_JAL, 4);
2941 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
2942 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
2943 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
2944 4, &exp, FALSE, reloc);
2953 fixp->fx_file = fragp->fr_file;
2954 fixp->fx_line = fragp->fr_line;
2956 gas_assert (buf == (bfd_byte *)fragp->fr_literal
2957 + fragp->fr_fix + fragp->fr_var);
2959 fragp->fr_fix += fragp->fr_var;
2962 /* Relax a machine dependent frag. This returns the amount by which
2963 the current size of the frag should change. */
2966 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
2969 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
2970 md_convert_frag_branch (fragp);
2974 md_show_usage (FILE *stream)
2976 fprintf (stream, _("\
2978 -fpic generate position-independent code\n\
2979 -fno-pic don't generate position-independent code (default)\n\
2980 -march=ISA set the RISC-V architecture\n\
2981 -mabi=ABI set the RISC-V ABI\n\
2982 -mrelax enable relax (default)\n\
2983 -mno-relax disable relax\n\
2987 /* Standard calling conventions leave the CFA at SP on entry. */
2989 riscv_cfi_frame_initial_instructions (void)
2991 cfi_add_CFA_def_cfa_register (X_SP);
2995 tc_riscv_regname_to_dw2regnum (char *regname)
2999 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3002 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3005 as_bad (_("unknown register `%s'"), regname);
3010 riscv_elf_final_processing (void)
3012 elf_elfheader (stdoutput)->e_flags |= elf_flags;
3015 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3016 since these directives break relaxation when used with symbol deltas. */
3019 s_riscv_leb128 (int sign)
3022 char *save_in = input_line_pointer;
3025 if (exp.X_op != O_constant)
3026 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3027 demand_empty_rest_of_line ();
3029 input_line_pointer = save_in;
3030 return s_leb128 (sign);
3033 /* Parse the .insn directive. */
3036 s_riscv_insn (int x ATTRIBUTE_UNUSED)
3038 char *str = input_line_pointer;
3039 struct riscv_cl_insn insn;
3040 expressionS imm_expr;
3041 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3044 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3045 ++input_line_pointer;
3047 save_c = *input_line_pointer;
3048 *input_line_pointer = '\0';
3050 const char *error = riscv_ip (str, &insn, &imm_expr,
3051 &imm_reloc, insn_type_hash);
3055 as_bad ("%s `%s'", error, str);
3059 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3060 append_insn (&insn, &imm_expr, imm_reloc);
3063 *input_line_pointer = save_c;
3064 demand_empty_rest_of_line ();
3067 /* Pseudo-op table. */
3069 static const pseudo_typeS riscv_pseudo_table[] =
3071 /* RISC-V-specific pseudo-ops. */
3072 {"option", s_riscv_option, 0},
3076 {"dtprelword", s_dtprel, 4},
3077 {"dtpreldword", s_dtprel, 8},
3079 {"uleb128", s_riscv_leb128, 0},
3080 {"sleb128", s_riscv_leb128, 1},
3081 {"insn", s_riscv_insn, 0},
3087 riscv_pop_insert (void)
3089 extern void pop_insert (const pseudo_typeS *);
3091 pop_insert (riscv_pseudo_table);