1 /* tc-nds32.c -- Assemble for the nds32
2 Copyright (C) 2012-2014 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28 #include "opcodes/nds32-asm.h"
29 #include "elf/nds32.h"
30 #include "bfd/elf32-nds32.h"
34 #include "struc-symbol.h"
35 #include "opcode/nds32.h"
39 /* GAS definitions. */
41 /* Characters which start a comment. */
42 const char comment_chars[] = "!";
43 /* Characters which start a comment when they appear at the start of a line. */
44 const char line_comment_chars[] = "#!";
45 /* Characters which separate lines (null and newline are by default). */
46 const char line_separator_chars[] = ";";
47 /* Characters which may be used as the exponent character
48 in a floating point number. */
49 const char EXP_CHARS[] = "eE";
50 /* Characters which may be used to indicate a floating point constant. */
51 const char FLT_CHARS[] = "dDfF";
53 static int enable_16bit = 1;
54 /* Save for md_assemble to distinguish if this instruction is
55 expanded from the pseudo instruction. */
56 static bfd_boolean pseudo_opcode = FALSE;
57 static struct nds32_relocs_pattern *relocs_list = NULL;
58 /* Save instruction relation to inserting relaxation relocation. */
59 struct nds32_relocs_pattern
66 struct nds32_opcode *opcode;
68 struct nds32_relocs_pattern *next;
71 /* Suffix name and relocation. */
75 short unsigned int reloc;
78 static int vec_size = 0;
79 /* If the assembly code is generated by compiler, it is supposed to have
80 ".flag verbatim" at beginning of the content. We have
81 'nds32_flag' to parse it and set this field to be non-zero. */
82 static int verbatim = 0;
83 static struct hash_control *nds32_gprs_hash;
84 static struct hash_control *nds32_hint_hash;
85 #define TLS_REG "$r27"
86 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
88 /* Generate relocation for relax or not, and the default is true. */
89 static int enable_relax_relocs = 1;
90 /* The value will be used in RELAX_ENTRY. */
91 static int enable_relax_ex9 = 0;
92 /* The value will be used in RELAX_ENTRY. */
93 static int enable_relax_ifc = 0;
94 /* Save option -O for perfomance. */
95 static int optimize = 0;
96 /* Save option -Os for code size. */
97 static int optimize_for_space = 0;
98 /* Flag to save label exist. */
99 static int label_exist = 0;
100 /* Flag to save state in omit_fp region. */
101 static int in_omit_fp = 0;
102 extern struct nds32_keyword keyword_gpr[];
103 /* Tag there is relax relocation having to link. */
104 static bfd_boolean relaxing = FALSE;
106 static struct hash_control *nds32_relax_info_hash;
107 static relax_info_t relax_table[] =
111 BR_RANGE_S16M, /* br_range */
112 {{0, 0, 0, FALSE}}, /* cond_field */
115 INSN_JAL /* jal label */
116 }, /* BR_RANGE_S256 */
118 INSN_JAL /* jal label */
119 }, /* BR_RANGE_S16K */
121 INSN_JAL /* jal label */
122 }, /* BR_RANGE_S64K */
124 INSN_JAL /* jal label */
125 }, /* BR_RANGE_S16M */
127 INSN_SETHI_TA, /* sethi $ta, label */
128 INSN_ORI_TA, /* ori $ta, $ta, label */
130 }, /* BR_RANGE_U4G */
131 }, /* relax_code_seq */
133 {{0, 0, 0, FALSE}}, /* BR_RANGE_S256 */
134 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16K */
135 {{0, 0, 0, FALSE}}, /* BR_RANGE_S64K */
136 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16M */
137 {{0, 0, 0, FALSE}} /* BR_RANGE_U4G */
138 }, /* relax_code_condition */
139 {4, 4, 4, 4, 12}, /* relax_code_size */
140 {4, 4, 4, 4, 4}, /* relax_branch_isize */
143 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
145 }, /* BR_RANGE_S256 */
147 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
149 }, /* BR_RANGE_S16K */
151 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
153 }, /* BR_RANGE_S64K */
155 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
157 }, /* BR_RANGE_S16M */
159 {0, 4, 0, BFD_RELOC_NDS32_HI20},
160 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGCALL4},
161 {4, 4, NDS32_HINT | NDS32_FIX, BFD_RELOC_NDS32_LO12S0_ORI},
162 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
163 {8, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
164 {8, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
165 {8, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
171 "bltzal", /* opcode */
172 BR_RANGE_S64K, /* br_range */
174 {0, 20, 0x1F, FALSE},
179 INSN_BLTZAL /* bltzal $rt, label */
180 }, /* BR_RANGE_S256 */
182 INSN_BLTZAL /* bltzal $rt, label */
183 }, /* BR_RANGE_S16K */
185 INSN_BLTZAL /* bltzal $rt, label */
186 }, /* BR_RANGE_S64K */
188 INSN_BGEZ, /* bgez $rt, $1 */
189 INSN_JAL /* jal label */
190 }, /* BR_RANGE_S16M */
192 INSN_BGEZ, /* bgez $rt, $1 */
193 INSN_SETHI_TA, /* sethi $ta, label */
194 INSN_ORI_TA, /* ori $ta, $ta, label */
195 INSN_JRAL_TA /* jral $ta */
197 }, /* relax_code_seq */
200 {0, 20, 0x1F, FALSE},
202 }, /* BR_RANGE_S256 */
204 {0, 20, 0x1F, FALSE},
206 }, /* BR_RANGE_S16K */
208 {0, 20, 0x1F, FALSE},
210 }, /* BR_RANGE_S64K */
212 {0, 20, 0x1F, FALSE},
214 }, /* BR_RANGE_S16M */
216 {0, 20, 0x1F, FALSE},
219 }, /* relax_code_condition */
220 {4, 4, 4, 8, 16}, /* relax_code_size */
221 {4, 4, 4, 4, 4}, /* relax_branch_isize */
224 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
226 }, /* BR_RANGE_S256 */
228 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
230 }, /* BR_RANGE_S16K */
232 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
234 }, /* BR_RANGE_S64K */
236 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_17_PCREL},
237 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGCALL5},
238 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
240 }, /* BR_RANGE_S16M */
242 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_17_PCREL},
243 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGCALL6},
244 {4, 4, 0, BFD_RELOC_NDS32_HI20},
245 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
246 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
247 {8, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
248 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
249 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
250 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
256 "bgezal", /* opcode */
257 BR_RANGE_S64K, /* br_range */
259 {0, 20, 0x1F, FALSE},
264 INSN_BGEZAL /* bgezal $rt, label */
265 }, /* BR_RANGE_S256 */
267 INSN_BGEZAL /* bgezal $rt, label */
268 }, /* BR_RANGE_S16K */
270 INSN_BGEZAL /* bgezal $rt, label */
271 }, /* BR_RANGE_S64K */
273 INSN_BLTZ, /* bltz $rt, $1 */
274 INSN_JAL /* jal label */
275 }, /* BR_RANGE_S16M */
277 INSN_BLTZ, /* bltz $rt, $1 */
278 INSN_SETHI_TA, /* sethi $ta, label */
279 INSN_ORI_TA, /* ori $ta, $ta, label */
280 INSN_JRAL_TA /* jral $ta */
282 }, /* relax_code_seq */
285 {0, 20, 0x1F, FALSE},
287 }, /* BR_RANGE_S256 */
289 {0, 20, 0x1F, FALSE},
291 }, /* BR_RANGE_S16K */
293 {0, 20, 0x1F, FALSE},
295 }, /* BR_RANGE_S64K */
297 {0, 20, 0x1F, FALSE},
299 }, /* BR_RANGE_S16M */
301 {0, 20, 0x1F, FALSE},
304 }, /* relax_code_condition */
305 {4, 4, 4, 8, 16}, /* relax_code_size */
306 {4, 4, 4, 4, 4}, /* relax_branch_isize */
309 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
311 }, /* BR_RANGE_S256 */
313 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
315 }, /* BR_RANGE_S16K */
317 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
319 }, /* BR_RANGE_S64K */
321 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_17_PCREL},
322 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGCALL5},
323 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
325 }, /* BR_RANGE_S16M */
327 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_17_PCREL},
328 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGCALL6},
329 {4, 4, 0, BFD_RELOC_NDS32_HI20},
330 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
331 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
332 {8, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
333 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
334 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
335 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
342 BR_RANGE_S16M, /* br_range */
343 {{0, 0, 0, FALSE}}, /* cond_field */
346 (INSN_J8 << 16) /* j8 label */
347 }, /* BR_RANGE_S256 */
350 }, /* BR_RANGE_S16K */
353 }, /* BR_RANGE_S64K */
356 }, /* BR_RANGE_S16M */
358 INSN_SETHI_TA, /* sethi $ta, label */
359 INSN_ORI_TA, /* ori $ta, $ta, label */
360 INSN_JR_TA /* jr $ta */
361 }, /* BR_RANGE_U4G */
362 }, /* relax_code_seq */
364 {{0, 0, 0, FALSE}}, /* BR_RANGE_S256 */
365 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16K */
366 {{0, 0, 0, FALSE}}, /* BR_RANGE_S64K */
367 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16M */
368 {{0, 0, 0, FALSE}} /* BR_RANGE_U4G */
369 }, /* relax_code_condition */
370 {2, 4, 4, 4, 12}, /* relax_code_size */
371 {2, 4, 4, 4, 4}, /* relax_branch_isize */
374 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
376 }, /* BR_RANGE_S256 */
378 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
380 }, /* BR_RANGE_S16K */
382 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
384 }, /* BR_RANGE_S64K */
386 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
388 }, /* BR_RANGE_S16M */
390 {0, 4, 0, BFD_RELOC_NDS32_HI20},
391 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP4},
392 {4, 4, NDS32_HINT | NDS32_FIX, BFD_RELOC_NDS32_LO12S0_ORI},
393 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
394 {8, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
395 {8, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
396 {8, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
403 BR_RANGE_S256, /* br_range */
404 {{0, 0, 0, FALSE}}, /* cond_field */
407 (INSN_J8 << 16) /* j8 label */
408 }, /* BR_RANGE_S256 */
411 }, /* BR_RANGE_S16K */
414 }, /* BR_RANGE_S64K */
417 }, /* BR_RANGE_S16M */
419 INSN_SETHI_TA, /* sethi $ta, label */
420 INSN_ORI_TA, /* ori $ta, $ta, label */
421 INSN_JR_TA /* jr $ta */
422 }, /* BR_RANGE_U4G */
423 }, /* relax_code_seq */
425 {{0, 0, 0, FALSE}}, /* BR_RANGE_S256 */
426 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16K */
427 {{0, 0, 0, FALSE}}, /* BR_RANGE_S64K */
428 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16M */
429 {{0, 0, 0, FALSE}} /* BR_RANGE_U4G */
430 }, /* relax_code_condition */
431 {2, 4, 4, 4, 12}, /* relax_code_size */
432 {2, 4, 4, 4, 4}, /* relax_branch_isize */
435 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
437 }, /* BR_RANGE_S256 */
439 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
441 }, /* BR_RANGE_S16K */
443 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
445 }, /* BR_RANGE_S64K */
447 {0, 4, 0, BFD_RELOC_NDS32_25_PCREL},
449 }, /* BR_RANGE_S16M */
451 {0, 4, 0, BFD_RELOC_NDS32_HI20},
452 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP4},
453 {4, 4, NDS32_HINT | NDS32_FIX, BFD_RELOC_NDS32_LO12S0_ORI},
454 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
455 {8, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
456 {8, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
457 {8, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
464 BR_RANGE_S64K, /* br_range */
466 {0, 20, 0x1F, FALSE},
471 INSN_BEQZ /* beqz $rt, label */
472 }, /* BR_RANGE_S256 */
474 INSN_BEQZ /* beqz $rt, label */
475 }, /* BR_RANGE_S16K */
477 INSN_BEQZ /* beqz $rt, label */
478 }, /* BR_RANGE_S64K */
480 INSN_BNEZ, /* bnez $rt, $1 */
482 }, /* BR_RANGE_S16M */
484 INSN_BNEZ, /* bnez $rt, $1 */
485 INSN_SETHI_TA, /* sethi $ta, label */
486 INSN_ORI_TA, /* ori $ta, $ta, label */
487 INSN_JR_TA /* jr $ta */
489 }, /* relax_code_seq */
492 {0, 20, 0x1F, FALSE},
494 }, /* BR_RANGE_S256 */
496 {0, 20, 0x1F, FALSE},
498 }, /* BR_RANGE_S16K */
500 {0, 20, 0x1F, FALSE},
502 }, /* BR_RANGE_S64K */
504 {0, 20, 0x1F, FALSE},
506 }, /* BR_RANGE_S16M */
508 {0, 20, 0x1F, FALSE},
511 }, /* relax_code_condition */
512 {4, 4, 4, 8, 16}, /* relax_code_size */
513 {4, 4, 4, 4, 4}, /* relax_branch_isize */
516 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
517 {0, 4, NDS32_INSN16 , BFD_RELOC_NDS32_INSN16},
519 }, /* BR_RANGE_S256 */
521 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
523 }, /* BR_RANGE_S16K */
525 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
527 }, /* BR_RANGE_S64K */
529 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
530 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
531 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
532 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
533 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
535 }, /* BR_RANGE_S16M */
537 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
538 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
539 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
540 {4, 4, 0, BFD_RELOC_NDS32_HI20},
541 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
542 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
543 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
544 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
545 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
546 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
553 BR_RANGE_S64K, /* br_range */
555 {0, 20, 0x1F, FALSE},
560 INSN_BGEZ /* bgez $rt, label */
561 }, /* BR_RANGE_S256 */
563 INSN_BGEZ /* bgez $rt, label */
564 }, /* BR_RANGE_S16K */
566 INSN_BGEZ /* bgez $rt, label */
567 }, /* BR_RANGE_S64K */
569 INSN_BLTZ, /* bltz $rt, $1 */
571 }, /* BR_RANGE_S16M */
573 INSN_BLTZ, /* bltz $rt, $1 */
574 INSN_SETHI_TA, /* sethi $ta, label */
575 INSN_ORI_TA, /* ori $ta, $ta, label */
576 INSN_JR_TA /* jr $ta */
578 }, /* relax_code_seq */
581 {0, 20, 0x1F, FALSE},
583 }, /* BR_RANGE_S256 */
585 {0, 20, 0x1F, FALSE},
587 }, /* BR_RANGE_S16K */
589 {0, 20, 0x1F, FALSE},
591 }, /* BR_RANGE_S64K */
593 {0, 20, 0x1F, FALSE},
595 }, /* BR_RANGE_S16M */
597 {0, 20, 0x1F, FALSE},
600 }, /* relax_code_condition */
601 {4, 4, 4, 8, 16}, /* relax_code_size */
602 {4, 4, 4, 4, 4}, /* relax_branch_isize */
605 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
607 }, /* BR_RANGE_S256 */
609 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
611 }, /* BR_RANGE_S16K */
613 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
615 }, /* BR_RANGE_S64K */
617 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
618 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
619 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
621 }, /* BR_RANGE_S16M */
623 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
624 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
625 {4, 4, 0, BFD_RELOC_NDS32_HI20},
626 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
627 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
628 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
629 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
630 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
631 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
638 BR_RANGE_S64K, /* br_range */
640 {0, 20, 0x1F, FALSE},
645 INSN_BNEZ /* bnez $rt, label */
646 }, /* BR_RANGE_S256 */
648 INSN_BNEZ /* bnez $rt, label */
649 }, /* BR_RANGE_S16K */
651 INSN_BNEZ /* bnez $rt, label */
652 }, /* BR_RANGE_S64K */
654 INSN_BEQZ, /* beqz $rt, $1 */
656 }, /* BR_RANGE_S16M */
658 INSN_BEQZ, /* beqz $rt, $1 */
659 INSN_SETHI_TA, /* sethi $ta, label */
660 INSN_ORI_TA, /* ori $ta, $ta, label */
661 INSN_JR_TA /* jr $ta */
663 }, /* relax_code_seq */
666 {0, 20, 0x1F, FALSE},
668 }, /* BR_RANGE_S256 */
670 {0, 20, 0x1F, FALSE},
672 }, /* BR_RANGE_S16K */
674 {0, 20, 0x1F, FALSE},
676 }, /* BR_RANGE_S64K */
678 {0, 20, 0x1F, FALSE},
680 }, /* BR_RANGE_S16M */
682 {0, 20, 0x1F, FALSE},
685 }, /* relax_code_condition */
686 {4, 4, 4, 8, 16}, /* relax_code_size */
687 {4, 4, 4, 4, 4}, /* relax_branch_isize */
690 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
691 {0, 4, NDS32_INSN16 , BFD_RELOC_NDS32_INSN16},
693 }, /* BR_RANGE_S256 */
695 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
697 }, /* BR_RANGE_S16K */
699 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
701 }, /* BR_RANGE_S64K */
703 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
704 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
705 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
706 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
707 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
709 }, /* BR_RANGE_S16M */
711 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
712 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
713 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
714 {4, 4, 0, BFD_RELOC_NDS32_HI20},
715 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
716 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
717 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
718 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
719 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
720 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
727 BR_RANGE_S64K, /* br_range */
729 {0, 20, 0x1F, FALSE},
734 INSN_BGTZ /* bgtz $rt, label */
735 }, /* BR_RANGE_S256 */
737 INSN_BGTZ /* bgtz $rt, label */
738 }, /* BR_RANGE_S16K */
740 INSN_BGTZ /* bgtz $rt, label */
741 }, /* BR_RANGE_S64K */
743 INSN_BLEZ, /* blez $rt, $1 */
745 }, /* BR_RANGE_S16M */
747 INSN_BLEZ, /* blez $rt, $1 */
748 INSN_SETHI_TA, /* sethi $ta, label */
749 INSN_ORI_TA, /* ori $ta, $ta, label */
750 INSN_JR_TA /* jr $ta */
752 }, /* relax_code_seq */
755 {0, 20, 0x1F, FALSE},
757 }, /* BR_RANGE_S256 */
759 {0, 20, 0x1F, FALSE},
761 }, /* BR_RANGE_S16K */
763 {0, 20, 0x1F, FALSE},
765 }, /* BR_RANGE_S64K */
767 {0, 20, 0x1F, FALSE},
769 }, /* BR_RANGE_S16M */
771 {0, 20, 0x1F, FALSE},
774 }, /* relax_code_condition */
775 {4, 4, 4, 8, 16}, /* relax_code_size */
776 {4, 4, 4, 4, 4}, /* relax_branch_isize */
779 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
781 }, /* BR_RANGE_S256 */
783 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
785 }, /* BR_RANGE_S16K */
787 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
789 }, /* BR_RANGE_S64K */
791 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
792 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
793 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
795 }, /* BR_RANGE_S16M */
797 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
798 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
799 {4, 4, 0, BFD_RELOC_NDS32_HI20},
800 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
801 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
802 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
803 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
804 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
805 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
812 BR_RANGE_S64K, /* br_range */
814 {0, 20, 0x1F, FALSE},
819 INSN_BLEZ /* blez $rt, label */
820 }, /* BR_RANGE_S256 */
822 INSN_BLEZ /* blez $rt, label */
823 }, /* BR_RANGE_S16K */
825 INSN_BLEZ /* blez $rt, label */
826 }, /* BR_RANGE_S64K */
828 INSN_BGTZ, /* bgtz $rt, $1 */
830 }, /* BR_RANGE_S16M */
832 INSN_BGTZ, /* bgtz $rt, $1 */
833 INSN_SETHI_TA, /* sethi $ta, label */
834 INSN_ORI_TA, /* ori $ta, $ta, label */
835 INSN_JR_TA /* jr $ta */
837 }, /* relax_code_seq */
840 {0, 20, 0x1F, FALSE},
842 }, /* BR_RANGE_S256 */
844 {0, 20, 0x1F, FALSE},
846 }, /* BR_RANGE_S16K */
848 {0, 20, 0x1F, FALSE},
850 }, /* BR_RANGE_S64K */
852 {0, 20, 0x1F, FALSE},
854 }, /* BR_RANGE_S16M */
856 {0, 20, 0x1F, FALSE},
859 }, /* relax_code_condition */
860 {4, 4, 4, 8, 16}, /* relax_code_size */
861 {4, 4, 4, 4, 4}, /* relax_branch_isize */
864 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
866 }, /* BR_RANGE_S256 */
868 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
870 }, /* BR_RANGE_S16K */
872 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
874 }, /* BR_RANGE_S64K */
876 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
877 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
878 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
880 }, /* BR_RANGE_S16M */
882 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
883 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
884 {4, 4, 0, BFD_RELOC_NDS32_HI20},
885 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
886 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
887 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
888 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
889 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
890 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
897 BR_RANGE_S64K, /* br_range */
899 {0, 20, 0x1F, FALSE},
904 INSN_BLTZ /* bltz $rt, label */
905 }, /* BR_RANGE_S256 */
907 INSN_BLTZ /* bltz $rt, label */
908 }, /* BR_RANGE_S16K */
910 INSN_BLTZ /* bltz $rt, label */
911 }, /* BR_RANGE_S64K */
913 INSN_BGEZ, /* bgez $rt, $1 */
915 }, /* BR_RANGE_S16M */
917 INSN_BGEZ, /* bgez $rt, $1 */
918 INSN_SETHI_TA, /* sethi $ta, label */
919 INSN_ORI_TA, /* ori $ta, $ta, label */
920 INSN_JR_TA /* jr $ta */
922 }, /* relax_code_seq */
925 {0, 20, 0x1F, FALSE},
927 }, /* BR_RANGE_S256 */
929 {0, 20, 0x1F, FALSE},
931 }, /* BR_RANGE_S16K */
933 {0, 20, 0x1F, FALSE},
935 }, /* BR_RANGE_S64K */
937 {0, 20, 0x1F, FALSE},
939 }, /* BR_RANGE_S16M */
941 {0, 20, 0x1F, FALSE},
944 }, /* relax_code_condition */
945 {4, 4, 4, 8, 16}, /* relax_code_size */
946 {4, 4, 4, 4, 4}, /* relax_branch_isize */
949 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
951 }, /* BR_RANGE_S256 */
953 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
955 }, /* BR_RANGE_S16K */
957 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
959 }, /* BR_RANGE_S64K */
961 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
962 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
963 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
965 }, /* BR_RANGE_S16M */
967 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
968 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
969 {4, 4, 0, BFD_RELOC_NDS32_HI20},
970 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
971 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
972 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
973 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
974 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
975 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
982 BR_RANGE_S16K, /* br_range */
984 {0, 20, 0x1F, FALSE},
985 {0, 15, 0x1F, FALSE},
990 INSN_BEQ /* beq $rt, $ra, label */
991 }, /* BR_RANGE_S256 */
993 INSN_BEQ /* beq $rt, $ra, label */
994 }, /* BR_RANGE_S16K */
996 INSN_BNE, /* bne $rt, $ra, $1 */
998 }, /* BR_RANGE_S64K */
1000 INSN_BNE, /* bne $rt, $ra, $1 */
1001 INSN_J /* j label */
1002 }, /* BR_RANGE_S16M */
1004 INSN_BNE, /* bne $rt, $ra, $1 */
1005 INSN_SETHI_TA, /* sethi $ta, label */
1006 INSN_ORI_TA, /* ori $ta, $ta, label */
1007 INSN_JR_TA /* jr $ta */
1008 } /* BR_RANGE_U4G */
1009 }, /* relax_code_seq */
1012 {0, 20, 0x1F, FALSE},
1013 {0, 15, 0x1F, FALSE},
1015 }, /* BR_RANGE_S256 */
1017 {0, 20, 0x1F, FALSE},
1018 {0, 15, 0x1F, FALSE},
1020 }, /* BR_RANGE_S16K */
1022 {0, 20, 0x1F, FALSE},
1023 {0, 15, 0x1F, FALSE},
1025 }, /* BR_RANGE_S64K */
1027 {0, 20, 0x1F, FALSE},
1028 {0, 15, 0x1F, FALSE},
1030 }, /* BR_RANGE_S16M */
1032 {0, 20, 0x1F, FALSE},
1033 {0, 15, 0x1F, FALSE},
1035 } /* BR_RANGE_U4G */
1036 }, /* relax_code_condition */
1037 {4, 4, 8, 8, 16}, /* relax_code_size */
1038 {4, 4, 4, 4, 4}, /* relax_branch_isize */
1041 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1042 {0, 4, NDS32_INSN16, BFD_RELOC_NDS32_INSN16},
1044 }, /* BR_RANGE_S256 */
1046 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1048 }, /* BR_RANGE_S16K */
1050 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1051 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1052 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1053 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1054 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1056 }, /* BR_RANGE_S64K */
1058 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1059 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1060 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1061 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1062 {4, 4, NDS32_ABS, BFD_RELOC_NDS32_EMPTY},
1063 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1065 }, /* BR_RANGE_S16M */
1067 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1068 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1069 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1070 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1071 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1072 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1073 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1074 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1075 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1076 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1078 } /* BR_RANGE_U4G */
1083 BR_RANGE_S16K, /* br_range */
1085 {0, 20, 0x1F, FALSE},
1086 {0, 15, 0x1F, FALSE},
1091 INSN_BNE /* bne $rt, $ra, label */
1092 }, /* BR_RANGE_S256 */
1094 INSN_BNE /* bne $rt, $ra, label */
1095 }, /* BR_RANGE_S16K */
1097 INSN_BEQ, /* beq $rt, $ra, $1 */
1098 INSN_J /* j label */
1099 }, /* BR_RANGE_S64K */
1101 INSN_BEQ, /* beq $rt, $ra, $1 */
1102 INSN_J /* j label */
1103 }, /* BR_RANGE_S16M */
1105 INSN_BEQ, /* beq $rt, $ra, $1 */
1106 INSN_SETHI_TA, /* sethi $ta, label */
1107 INSN_ORI_TA, /* ori $ta, $ta, label */
1108 INSN_JR_TA /* jr $ta */
1109 } /* BR_RANGE_U4G */
1110 }, /* relax_code_seq */
1113 {0, 20, 0x1F, FALSE},
1114 {0, 15, 0x1F, FALSE},
1116 }, /* BR_RANGE_S256 */
1118 {0, 20, 0x1F, FALSE},
1119 {0, 15, 0x1F, FALSE},
1121 }, /* BR_RANGE_S16K */
1123 {0, 20, 0x1F, FALSE},
1124 {0, 15, 0x1F, FALSE},
1126 }, /* BR_RANGE_S64K */
1128 {0, 20, 0x1F, FALSE},
1129 {0, 15, 0x1F, FALSE},
1131 }, /* BR_RANGE_S16M */
1133 {0, 20, 0x1F, FALSE},
1134 {0, 15, 0x1F, FALSE},
1136 } /* BR_RANGE_U4G */
1137 }, /* relax_code_condition */
1138 {4, 4, 8, 8, 16}, /* relax_code_size */
1139 {4, 4, 4, 4, 4}, /* relax_branch_isize */
1142 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1143 {0, 4, NDS32_INSN16, BFD_RELOC_NDS32_INSN16},
1145 }, /* BR_RANGE_S256 */
1147 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1149 }, /* BR_RANGE_S16K */
1151 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1152 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1153 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1154 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1155 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1157 }, /* BR_RANGE_S64K */
1159 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1160 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1161 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1162 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1163 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1165 }, /* BR_RANGE_S16M */
1167 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1168 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1169 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1170 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1171 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1172 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1173 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1174 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1175 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1176 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1178 } /* BR_RANGE_U4G */
1182 "beqz38", /* opcode */
1183 BR_RANGE_S256, /* br_range */
1190 INSN_BEQZ38 << 16 /* beqz $rt, label */
1191 }, /* BR_RANGE_S256 */
1193 INSN_BEQZ /* beqz $rt, label */
1194 }, /* BR_RANGE_S16K */
1196 INSN_BEQZ /* beqz $rt, label */
1197 }, /* BR_RANGE_S64K */
1199 INSN_BNEZ, /* bnez $rt, $1 */
1200 INSN_J /* j label */
1201 }, /* BR_RANGE_S16M */
1203 INSN_BNEZ, /* bnez $rt, $1 */
1204 INSN_SETHI_TA, /* sethi $ta, label */
1205 INSN_ORI_TA, /* ori $ta, $ta, label */
1206 INSN_JR_TA /* jr $ta */
1207 } /* BR_RANGE_U4G */
1208 }, /* relax_code_seq */
1213 }, /* BR_RANGE_S256 */
1215 {0, 20, 0x1F, FALSE},
1217 }, /* BR_RANGE_S16K */
1219 {0, 20, 0x1F, FALSE},
1221 }, /* BR_RANGE_S64K */
1223 {0, 20, 0x1F, FALSE},
1225 }, /* BR_RANGE_S16M */
1227 {0, 20, 0x1F, FALSE},
1229 } /* BR_RANGE_U4G */
1230 }, /* relax_code_condition */
1231 {2, 4, 4, 8, 16}, /* relax_code_size */
1232 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1235 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1237 }, /* BR_RANGE_S256 */
1239 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1241 }, /* BR_RANGE_S16K */
1243 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1245 }, /* BR_RANGE_S64K */
1247 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1248 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1249 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1250 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1251 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1253 }, /* BR_RANGE_S16M */
1255 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1256 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1257 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1258 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1259 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1260 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1261 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1262 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1263 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1264 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1266 } /* BR_RANGE_U4G */
1270 "bnez38", /* opcode */
1271 BR_RANGE_S256, /* br_range */
1278 INSN_BNEZ38 << 16 /* bnez $rt, label */
1279 }, /* BR_RANGE_S256 */
1281 INSN_BNEZ /* bnez $rt, label */
1282 }, /* BR_RANGE_S16K */
1284 INSN_BNEZ /* bnez $rt, label */
1285 }, /* BR_RANGE_S64K */
1287 INSN_BEQZ, /* beqz $rt, $1 */
1288 INSN_J /* j label */
1289 }, /* BR_RANGE_S16M */
1291 INSN_BEQZ, /* beqz $rt, $1 */
1292 INSN_SETHI_TA, /* sethi $ta, label */
1293 INSN_ORI_TA, /* ori $ta, $ta, label */
1294 INSN_JR_TA /* jr $ta */
1295 } /* BR_RANGE_U4G */
1296 }, /* relax_code_seq */
1301 }, /* BR_RANGE_S256 */
1303 {0, 20, 0x1F, FALSE},
1305 }, /* BR_RANGE_S16K */
1307 {0, 20, 0x1F, FALSE},
1309 }, /* BR_RANGE_S64K */
1311 {0, 20, 0x1F, FALSE},
1313 }, /* BR_RANGE_S16M */
1315 {0, 20, 0x1F, FALSE},
1317 } /* BR_RANGE_U4G */
1318 }, /* relax_code_condition */
1319 {2, 4, 4, 8, 16}, /* relax_code_size */
1320 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1323 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1325 }, /* BR_RANGE_S256 */
1327 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1329 }, /* BR_RANGE_S16K */
1331 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1333 }, /* BR_RANGE_S64K */
1335 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1336 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1337 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1338 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1339 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1341 }, /* BR_RANGE_S16M */
1343 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1344 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1345 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1346 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1347 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1348 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1349 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1350 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1351 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1352 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1354 } /* BR_RANGE_U4G */
1358 "beqzs8", /* opcode */
1359 BR_RANGE_S256, /* br_range */
1360 {{0, 0, 0, FALSE}}, /* cond_field */
1363 INSN_BEQZS8 << 16 /* beqz $r15, label */
1364 }, /* BR_RANGE_S256 */
1366 INSN_BEQZ_TA /* bnez $rt, label */
1367 }, /* BR_RANGE_S16K */
1369 INSN_BEQZ_TA /* bnez $rt, label */
1370 }, /* BR_RANGE_S64K */
1372 INSN_BNEZ_TA, /* bnez $r15, $1 */
1373 INSN_J /* j label */
1374 }, /* BR_RANGE_S16M */
1376 INSN_BNEZ_TA, /* bnez $r15, $1 */
1377 INSN_SETHI_TA, /* sethi $ta, label */
1378 INSN_ORI_TA, /* ori $ta, $ta, label */
1379 INSN_JR_TA /* jr $ta */
1380 } /* BR_RANGE_U4G */
1381 }, /* relax_code_seq */
1383 {{0, 0, 0, FALSE}}, /* BR_RANGE_S256 */
1384 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16K */
1385 {{0, 0, 0, FALSE}}, /* BR_RANGE_S64K */
1386 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16M */
1387 {{0, 0, 0, FALSE}} /* BR_RANGE_U4G */
1388 }, /* relax_code_condition */
1389 {2, 4, 4, 8, 16}, /* relax_code_size */
1390 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1393 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1395 }, /* BR_RANGE_S256 */
1397 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1399 }, /* BR_RANGE_S16K */
1401 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1403 }, /* BR_RANGE_S64K */
1405 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1406 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1407 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1408 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1409 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1411 }, /* BR_RANGE_S16M */
1413 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1414 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1415 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1416 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1417 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1418 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1419 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1420 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1421 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1422 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1424 } /* BR_RANGE_U4G */
1428 "bnezs8", /* opcode */
1429 BR_RANGE_S256, /* br_range */
1430 {{0, 0, 0, FALSE}}, /* cond_field */
1433 INSN_BNEZS8 << 16 /* bnez $r15, label */
1434 }, /* BR_RANGE_S256 */
1436 INSN_BNEZ_TA /* bnez $r15, label */
1437 }, /* BR_RANGE_S16K */
1439 INSN_BNEZ_TA /* bnez $r15, label */
1440 }, /* BR_RANGE_S64K */
1442 INSN_BEQZ_TA, /* beqz $r15, $1 */
1443 INSN_J /* j label */
1444 }, /* BR_RANGE_S16M */
1446 INSN_BEQZ_TA, /* beqz $r15, $1 */
1447 INSN_SETHI_TA, /* sethi $ta, label */
1448 INSN_ORI_TA, /* ori $ta, $ta, label */
1449 INSN_JR_TA /* jr $ta */
1450 } /* BR_RANGE_U4G */
1451 }, /* relax_code_seq */
1453 {{0, 0, 0, FALSE}}, /* BR_RANGE_S256 */
1454 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16K */
1455 {{0, 0, 0, FALSE}}, /* BR_RANGE_S64K */
1456 {{0, 0, 0, FALSE}}, /* BR_RANGE_S16M */
1457 {{0, 0, 0, FALSE}} /* BR_RANGE_U4G */
1458 }, /* relax_code_condition */
1459 {2, 4, 4, 8, 16}, /* relax_code_size */
1460 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1463 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1465 }, /* BR_RANGE_S256 */
1467 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1469 }, /* BR_RANGE_S16K */
1471 {0, 4, 0, BFD_RELOC_NDS32_17_PCREL},
1473 }, /* BR_RANGE_S64K */
1475 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1476 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1477 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1478 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1479 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1481 }, /* BR_RANGE_S16M */
1483 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1484 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1485 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1486 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1487 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1488 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1489 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1490 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1491 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1492 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1494 } /* BR_RANGE_U4G */
1498 "bnes38", /* opcode */
1499 BR_RANGE_S256, /* br_range */
1506 INSN_BNES38 << 16 /* bne $rt, $R5, label */
1507 }, /* BR_RANGE_S256 */
1509 INSN_BNE_R5 /* bne $rt, $R5, label */
1510 }, /* BR_RANGE_S16K */
1512 INSN_BEQ_R5, /* beq $rt, $R5, $1 */
1513 INSN_J /* j label */
1514 }, /* BR_RANGE_S64K */
1516 INSN_BEQ_R5, /* beq $rt, $R5, $1 */
1517 INSN_J /* j label */
1518 }, /* BR_RANGE_S16M */
1520 INSN_BEQ_R5, /* beq $rt, $R5, $1 */
1521 INSN_SETHI_TA, /* sethi $ta, label */
1522 INSN_ORI_TA, /* ori $ta, $ta, label */
1523 INSN_JR_TA /* jr $ta */
1524 } /* BR_RANGE_U4G */
1525 }, /* relax_code_seq */
1530 }, /* BR_RANGE_S256 */
1532 {0, 20, 0x1F, FALSE},
1534 }, /* BR_RANGE_S16K */
1536 {0, 20, 0x1F, FALSE},
1538 }, /* BR_RANGE_S64K */
1540 {0, 20, 0x1F, FALSE},
1542 }, /* BR_RANGE_S16M */
1544 {0, 20, 0x1F, FALSE},
1546 } /* BR_RANGE_U4G */
1547 }, /* relax_code_condition */
1548 {2, 4, 8, 8, 16}, /* relax_code_size */
1549 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1552 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1554 }, /* BR_RANGE_S256 */
1556 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1558 }, /* BR_RANGE_S16K */
1560 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1561 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1562 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1563 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1564 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1566 }, /* BR_RANGE_S64K */
1568 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1569 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1570 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1571 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1572 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1574 }, /* BR_RANGE_S16M */
1576 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1577 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1578 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1579 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1580 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1581 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1582 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1583 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1584 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1585 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1587 } /* BR_RANGE_U4G */
1591 "beqs38", /* opcode */
1592 BR_RANGE_S256, /* br_range */
1599 INSN_BEQS38 << 16 /* beq $rt, $R5, label */
1600 }, /* BR_RANGE_S256 */
1602 INSN_BEQ_R5 /* beq $rt, $R5, label */
1603 }, /* BR_RANGE_S16K */
1605 INSN_BNE_R5, /* bne $rt, $R5, $1 */
1606 INSN_J /* j label */
1607 }, /* BR_RANGE_S64K */
1609 INSN_BNE_R5, /* bne $rt, $R5, $1 */
1610 INSN_J /* j label */
1611 }, /* BR_RANGE_S16M */
1613 INSN_BNE_R5, /* bne $rt, $R5, $1 */
1614 INSN_SETHI_TA, /* sethi $ta, label */
1615 INSN_ORI_TA, /* ori $ta, $ta, label */
1616 INSN_JR_TA /* jr $ta */
1617 } /* BR_RANGE_U4G */
1618 }, /* relax_code_seq */
1623 }, /* BR_RANGE_S256 */
1625 {0, 20, 0x1F, FALSE},
1627 }, /* BR_RANGE_S16K */
1629 {0, 20, 0x1F, FALSE},
1631 }, /* BR_RANGE_S64K */
1633 {0, 20, 0x1F, FALSE},
1635 }, /* BR_RANGE_S16M */
1637 {0, 20, 0x1F, FALSE},
1639 } /* BR_RANGE_U4G */
1640 }, /* relax_code_condition */
1641 {2, 4, 8, 8, 16}, /* relax_code_size */
1642 {2, 4, 4, 4, 4}, /* relax_branch_isize */
1645 {0, 2, 0, BFD_RELOC_NDS32_9_PCREL},
1647 }, /* BR_RANGE_S256 */
1649 {0, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1651 }, /* BR_RANGE_S16K */
1653 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1654 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1655 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1656 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1657 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1659 }, /* BR_RANGE_S64K */
1661 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1662 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1663 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP5},
1664 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1665 {4, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1667 }, /* BR_RANGE_S16M */
1669 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_15_PCREL},
1670 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1671 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP6},
1672 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1673 {4, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_PTR},
1674 {8, 4, NDS32_FIX | NDS32_HINT, BFD_RELOC_NDS32_LO12S0_ORI},
1675 {8, 4, NDS32_PTR |NDS32_HINT, BFD_RELOC_NDS32_PTR},
1676 {12, 4, NDS32_ABS | NDS32_HINT, BFD_RELOC_NDS32_PTR_RESOLVED},
1677 {12, 4, NDS32_SYM | NDS32_HINT, BFD_RELOC_NDS32_EMPTY},
1678 {12, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1680 } /* BR_RANGE_U4G */
1684 "beqc", /* opcode */
1685 BR_RANGE_S256, /* br_range */
1687 {0, 8, 0x7FF, TRUE},
1688 {0, 20, 0x1F, FALSE},
1693 INSN_BEQC /* beqc $rt, imm11s, label */
1694 }, /* BR_RANGE_S256 */
1696 INSN_MOVI_TA, /* movi $ta, imm11s */
1697 INSN_BEQ_TA /* beq $rt, $ta, label */
1698 }, /* BR_RANGE_S16K */
1700 INSN_BNEC, /* bnec $rt, imm11s, $1 */
1701 INSN_J /* j label */
1702 }, /* BR_RANGE_S64K */
1704 INSN_BNEC, /* bnec $rt, imm11s, $1 */
1705 INSN_J /* j label */
1706 }, /* BR_RANGE_S16M */
1708 INSN_BNEC, /* bnec $rt, imm11s, $1 */
1709 INSN_SETHI_TA, /* sethi $ta, label */
1710 INSN_ORI_TA, /* ori $ta, $ta, label */
1711 INSN_JR_TA /* jr $ta */
1712 } /* BR_RANGE_U4G */
1713 }, /* relax_code_seq */
1716 {0, 8, 0x7FF, TRUE},
1717 {0, 20, 0x1F, FALSE},
1719 }, /* BR_RANGE_S256 */
1721 {0, 0, 0xFFFFF, FALSE},
1722 {4, 20, 0x1F, FALSE},
1724 }, /* BR_RANGE_S16K */
1726 {0, 8, 0x7FF, FALSE},
1727 {0, 20, 0x1F, FALSE},
1729 }, /* BR_RANGE_S64K */
1731 {0, 8, 0x7FF, FALSE},
1732 {0, 20, 0x1F, FALSE},
1734 }, /* BR_RANGE_S16M */
1736 {0, 8, 0x7FF, FALSE},
1737 {0, 20, 0x1F, FALSE},
1739 } /* BR_RANGE_U4G */
1740 }, /* relax_code_condition */
1741 {4, 8, 8, 8, 16}, /* relax_code_size */
1742 {4, 4, 4, 4, 4}, /* relax_branch_isize */
1745 {0, 4, 0, BFD_RELOC_NDS32_WORD_9_PCREL},
1747 }, /* BR_RANGE_S256 */
1749 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1750 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP7},
1751 {4, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1753 }, /* BR_RANGE_S16K */
1755 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1756 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1758 }, /* BR_RANGE_S64K */
1760 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1761 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1763 }, /* BR_RANGE_S16M */
1765 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1766 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1767 {8, 4, 0, BFD_RELOC_NDS32_LO12S0_ORI},
1768 {12, 4, NDS32_INSN16, BFD_RELOC_NDS32_INSN16},
1770 } /* BR_RANGE_U4G */
1774 "bnec", /* opcode */
1775 BR_RANGE_S256, /* br_range */
1777 {0, 8, 0x7FF, TRUE},
1778 {0, 20, 0x1F, FALSE},
1783 INSN_BNEC /* bnec $rt, imm11s, label */
1784 }, /* BR_RANGE_S256 */
1786 INSN_MOVI_TA, /* movi $ta, imm11s */
1787 INSN_BNE_TA /* bne $rt, $ta, label */
1788 }, /* BR_RANGE_S16K */
1790 INSN_BEQC, /* beqc $rt, imm11s, $1 */
1791 INSN_J /* j label */
1792 }, /* BR_RANGE_S64K */
1794 INSN_BEQC, /* beqc $rt, imm11s, $1 */
1795 INSN_J /* j label */
1796 }, /* BR_RANGE_S16M */
1798 INSN_BEQC, /* beqc $rt, imm11s, $1 */
1799 INSN_SETHI_TA, /* sethi $ta, label */
1800 INSN_ORI_TA, /* ori $ta, $ta, label */
1801 INSN_JR_TA /* jr $ta */
1802 } /* BR_RANGE_U4G */
1803 }, /* relax_code_seq */
1806 {0, 8, 0x7FF, TRUE},
1807 {0, 20, 0x1F, FALSE},
1809 }, /* BR_RANGE_S256 */
1811 {0, 0, 0xFFFFF, FALSE},
1812 {4, 20, 0x1F, FALSE},
1814 }, /* BR_RANGE_S16K */
1816 {0, 8, 0x7FF, FALSE},
1817 {0, 20, 0x1F, FALSE},
1819 }, /* BR_RANGE_S64K */
1821 {0, 8, 0x7FF, FALSE},
1822 {0, 20, 0x1F, FALSE},
1824 }, /* BR_RANGE_S16M */
1826 {0, 8, 0x7FF, FALSE},
1827 {0, 20, 0x1F, FALSE},
1829 } /* BR_RANGE_U4G */
1830 }, /* relax_code_condition */
1831 {4, 8, 8, 8, 16}, /* relax_code_size */
1832 {4, 4, 4, 4, 4}, /* relax_branch_isize */
1835 {0, 4, 0, BFD_RELOC_NDS32_WORD_9_PCREL},
1837 }, /* BR_RANGE_S256 */
1839 {0, 4, NDS32_INSN16 | NDS32_HINT, BFD_RELOC_NDS32_INSN16},
1840 {0, 4, NDS32_PTR | NDS32_HINT, BFD_RELOC_NDS32_LONGJUMP7},
1841 {4, 4, 0, BFD_RELOC_NDS32_15_PCREL},
1843 }, /* BR_RANGE_S16K */
1845 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1846 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1848 }, /* BR_RANGE_S64K */
1850 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1851 {4, 4, 0, BFD_RELOC_NDS32_25_PCREL},
1853 }, /* BR_RANGE_S16M */
1855 {0, 4, NDS32_CREATE_LABEL, BFD_RELOC_NDS32_WORD_9_PCREL},
1856 {4, 4, 0, BFD_RELOC_NDS32_HI20},
1857 {8, 4, 0, BFD_RELOC_NDS32_LO12S0_ORI},
1858 {12, 4, NDS32_INSN16, BFD_RELOC_NDS32_INSN16},
1860 } /* BR_RANGE_U4G */
1866 {{0, 0, 0, FALSE}}, /* cond_field */
1867 {{0}}, /* relax_code_seq */
1868 {{{0, 0, 0, FALSE}}}, /* relax_code_condition */
1869 {0}, /* relax_code_size */
1870 {0}, /* relax_branch_isize */
1871 {{{0, 0, 0, 0}}}, /* relax_fixup */
1875 /* GAS definitions for command-line options. */
1878 OPTION_BIG = OPTION_MD_BASE,
1882 OPTION_RELAX_FP_AS_GP_OFF,
1883 OPTION_RELAX_B2BB_ON,
1884 OPTION_RELAX_ALL_OFF,
1886 OPTION_OPTIMIZE_SPACE
1889 const char *md_shortopts = "m:O:";
1890 struct option md_longopts[] =
1892 {"O1", no_argument, NULL, OPTION_OPTIMIZE},
1893 {"Os", no_argument, NULL, OPTION_OPTIMIZE_SPACE},
1894 {"big", no_argument, NULL, OPTION_BIG},
1895 {"little", no_argument, NULL, OPTION_LITTLE},
1896 {"EB", no_argument, NULL, OPTION_BIG},
1897 {"EL", no_argument, NULL, OPTION_LITTLE},
1898 {"meb", no_argument, NULL, OPTION_BIG},
1899 {"mel", no_argument, NULL, OPTION_LITTLE},
1900 {"mall-ext", no_argument, NULL, OPTION_TURBO},
1901 {"mext-all", no_argument, NULL, OPTION_TURBO},
1902 {"mpic", no_argument, NULL, OPTION_PIC},
1903 /* Relaxation related options. */
1904 {"mno-fp-as-gp-relax", no_argument, NULL, OPTION_RELAX_FP_AS_GP_OFF},
1905 {"mb2bb", no_argument, NULL, OPTION_RELAX_B2BB_ON},
1906 {"mno-all-relax", no_argument, NULL, OPTION_RELAX_ALL_OFF},
1907 {NULL, no_argument, NULL, 0}
1910 size_t md_longopts_size = sizeof (md_longopts);
1912 struct nds32_parse_option_table
1914 const char *name; /* Option string. */
1915 char *help; /* Help description. */
1916 int (*func) (char *arg); /* How to parse it. */
1920 /* The value `-1' represents this option has *NOT* been set. */
1921 #ifdef NDS32_DEFAULT_ARCH_NAME
1922 static char* nds32_arch_name = NDS32_DEFAULT_ARCH_NAME;
1924 static char* nds32_arch_name = "v3";
1926 static int nds32_baseline = -1;
1927 static int nds32_gpr16 = -1;
1928 static int nds32_fpu_sp_ext = -1;
1929 static int nds32_fpu_dp_ext = -1;
1930 static int nds32_freg = -1;
1931 static int nds32_abi = -1;
1933 /* Record ELF flags */
1934 static int nds32_elf_flags = 0;
1935 static int nds32_fpu_com = 0;
1937 static int nds32_parse_arch (char *str);
1938 static int nds32_parse_baseline (char *str);
1939 static int nds32_parse_freg (char *str);
1940 static int nds32_parse_abi (char *str);
1942 static struct nds32_parse_option_table parse_opts [] =
1944 {"arch=", N_("<arch name>\t Assemble for architecture <arch name>\n\
1945 <arch name> could be\n\
1946 v3, v3j, v3m, v3f, v3s, "\
1947 "v2, v2j, v2f, v2s"), nds32_parse_arch},
1948 {"baseline=", N_("<baseline>\t Assemble for baseline <baseline>\n\
1949 <baseline> could be v2, v3, v3m"),
1950 nds32_parse_baseline},
1951 {"fpu-freg=", N_("<freg>\t Specify a FPU configuration\n\
1953 0: 8 SP / 4 DP registers\n\
1954 1: 16 SP / 8 DP registers\n\
1955 2: 32 SP / 16 DP registers\n\
1956 3: 32 SP / 32 DP registers"), nds32_parse_freg},
1957 {"abi=", N_("<abi>\t Specify a abi version\n\
1958 <abi> could be v1, v2, v2fp, v2fpp"), nds32_parse_abi},
1962 static int nds32_mac = 1;
1963 static int nds32_div = 1;
1964 static int nds32_16bit_ext = 1;
1965 static int nds32_dx_regs = 1;
1966 static int nds32_perf_ext = 1;
1967 static int nds32_perf_ext2 = 1;
1968 static int nds32_string_ext = 1;
1969 static int nds32_audio_ext = 1;
1970 static int nds32_fpu_fma = 0;
1971 static int nds32_pic = 0;
1972 static int nds32_relax_fp_as_gp = 1;
1973 static int nds32_relax_b2bb = 0;
1974 static int nds32_relax_all = 1;
1975 struct nds32_set_option_table
1977 const char *name; /* Option string. */
1978 char *help; /* Help description. */
1979 int *var; /* Variable to be set. */
1980 int value; /* Value to set. */
1983 /* The option in this group has both Enable/Disable settings.
1984 Just list on here. */
1986 static struct nds32_set_option_table toggle_opts [] =
1988 {"mac", N_("Multiply instructions support"), &nds32_mac, 1},
1989 {"div", N_("Divide instructions support"), &nds32_div, 1},
1990 {"16bit-ext", N_("16-bit extension"), &nds32_16bit_ext, 1},
1991 {"dx-regs", N_("d0/d1 registers"), &nds32_dx_regs, 1},
1992 {"perf-ext", N_("Performance extension"), &nds32_perf_ext, 1},
1993 {"perf2-ext", N_("Performance extension 2"), &nds32_perf_ext2, 1},
1994 {"string-ext", N_("String extension"), &nds32_string_ext, 1},
1995 {"reduced-regs", N_("Reduced Register configuration (GPR16) option"), &nds32_gpr16, 1},
1996 {"audio-isa-ext", N_("AUDIO ISA extension"), &nds32_audio_ext, 1},
1997 {"fpu-sp-ext", N_("FPU SP extension"), &nds32_fpu_sp_ext, 1},
1998 {"fpu-dp-ext", N_("FPU DP extension"), &nds32_fpu_dp_ext, 1},
1999 {"fpu-fma", N_("FPU fused-multiply-add instructions"), &nds32_fpu_fma, 1},
2000 {NULL, NULL, NULL, 0}
2004 /* GAS declarations. */
2006 /* This is the callback for nds32-asm.c to parse operands. */
2008 nds32_asm_parse_operand (struct nds32_asm_desc *pdesc,
2009 struct nds32_asm_insn *pinsn,
2010 char **pstr, int64_t *value);
2013 struct nds32_asm_desc asm_desc;
2015 /* md_after_parse_args ()
2017 GAS will call md_after_parse_args whenever it is defined.
2018 This function checks any conflicting options specified. */
2021 nds32_after_parse_args (void)
2023 /* If -march option is not used in command-line, set the value of option
2024 variable according to NDS32_DEFAULT_ARCH_NAME. */
2025 nds32_parse_arch (nds32_arch_name);
2028 /* This function is called when printing usage message (--help). */
2031 md_show_usage (FILE *stream)
2033 struct nds32_parse_option_table *coarse_tune;
2034 struct nds32_set_option_table *fine_tune;
2036 fprintf (stream, _("\n NDS32-specific assembler options:\n"));
2037 fprintf (stream, _("\
2038 -O1, Optimize for performance\n\
2039 -Os Optimize for space\n"));
2040 fprintf (stream, _("\
2041 -EL, -mel or -little Produce little endian output\n\
2042 -EB, -meb or -big Produce big endian output\n\
2043 -mpic Generate PIC\n\
2044 -mno-fp-as-gp-relax Suppress fp-as-gp relaxation for this file\n\
2045 -mb2bb-relax Back-to-back branch optimization\n\
2046 -mno-all-relax Suppress all relaxation for this file\n"));
2048 for (coarse_tune = parse_opts; coarse_tune->name != NULL; coarse_tune++)
2050 if (coarse_tune->help != NULL)
2051 fprintf (stream, _(" -m%s%s\n"),
2052 coarse_tune->name, _(coarse_tune->help));
2055 for (fine_tune = toggle_opts; fine_tune->name != NULL; fine_tune++)
2057 if (fine_tune->help != NULL)
2058 fprintf (stream, _(" -m[no-]%-17sEnable/Disable %s\n"),
2059 fine_tune->name, _(fine_tune->help));
2062 fprintf (stream, _("\
2063 -mall-ext Turn on all extensions and instructions support\n"));
2067 nds32_frag_init (fragS *fragp)
2069 fragp->tc_frag_data.flag = 0;
2070 fragp->tc_frag_data.opcode = NULL;
2071 fragp->tc_frag_data.fixup = NULL;
2076 /* This function reads an expression from a C string and returns a pointer past
2077 the end of the expression. */
2080 parse_expression (char *str, expressionS *exp)
2085 tmp = input_line_pointer; /* Save line pointer. */
2086 input_line_pointer = str;
2088 s = input_line_pointer;
2089 input_line_pointer = tmp; /* Restore line pointer. */
2091 return s; /* Return pointer to where parsing stopped. */
2095 nds32_start_line_hook (void)
2103 typedef void (*nds32_pseudo_opcode_func) (int argc, char *argv[], int pv);
2104 struct nds32_pseudo_opcode
2108 nds32_pseudo_opcode_func proc;
2111 /* Some instructions are not pseudo opcode, but they might still be
2112 expanded or changed with other instruction combination for some
2113 conditions. We also apply this structure to assist such work.
2115 For example, if the distance of branch target '.L0' is larger than
2122 will be transformed into:
2128 However, sometimes we do not want assembler to do such changes
2129 because compiler knows how to generate corresponding instruction sequence.
2130 Use this field to indicate that this opcode is also a physical instruction.
2131 If the flag 'verbatim' is nozero and this opcode
2132 is a physical instruction, we should not expand it. */
2135 #define PV_DONT_CARE 0
2137 static struct hash_control *nds32_pseudo_opcode_hash = NULL;
2140 builtin_isreg (const char *s, const char *x ATTRIBUTE_UNUSED)
2146 builtin_regnum (const char *s, const char *x ATTRIBUTE_UNUSED)
2148 struct nds32_keyword *k;
2152 k = hash_find (nds32_gprs_hash, s);
2161 builtin_addend (const char *s, char *x ATTRIBUTE_UNUSED)
2163 const char *ptr = s;
2165 while (*ptr != '+' && *ptr != '-' && *ptr)
2171 return strtol (ptr, NULL, 0);
2175 md_assemblef (char *format, ...)
2177 /* FIXME: hope this is long enough. */
2182 va_start (ap, format);
2183 r = vsnprintf (line, sizeof (line), format, ap);
2186 gas_assert (r < sizeof (line));
2189 /* Some prototypes here, since some op may use another op. */
2190 static void do_pseudo_li_internal (char *rt, int imm32s);
2191 static void do_pseudo_move_reg_internal (char *dst, char *src);
2194 do_pseudo_b (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2196 char *arg_label = argv[0];
2199 if (nds32_pic && strstr (arg_label, "@PLT"))
2201 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2202 md_assemblef ("ori $ta,$ta,lo12(%s)", arg_label);
2203 md_assemble ("add $ta,$ta,$gp");
2204 md_assemble ("jr $ta");
2208 md_assemblef ("j %s", arg_label);
2214 do_pseudo_bal (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2216 char *arg_label = argv[0];
2218 /* bal|call label */
2220 && (strstr (arg_label, "@GOT") || strstr (arg_label, "@PLT")))
2222 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2223 md_assemblef ("ori $ta,$ta,lo12(%s)", arg_label);
2224 md_assemble ("add $ta,$ta,$gp");
2225 md_assemble ("jral $ta");
2229 md_assemblef ("jal %s", arg_label);
2235 do_pseudo_bge (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2237 /* rt5, ra5, label */
2238 md_assemblef ("slt $ta,%s,%s", argv[0], argv[1]);
2239 md_assemblef ("beqz $ta,%s", argv[2]);
2243 do_pseudo_bges (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2245 /* rt5, ra5, label */
2246 md_assemblef ("slts $ta,%s,%s", argv[0], argv[1]);
2247 md_assemblef ("beqz $ta,%s", argv[2]);
2251 do_pseudo_bgt (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2253 /* bgt rt5, ra5, label */
2254 md_assemblef ("slt $ta,%s,%s", argv[1], argv[0]);
2255 md_assemblef ("bnez $ta,%s", argv[2]);
2259 do_pseudo_bgts (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2261 /* bgt rt5, ra5, label */
2262 md_assemblef ("slts $ta,%s,%s", argv[1], argv[0]);
2263 md_assemblef ("bnez $ta,%s", argv[2]);
2267 do_pseudo_ble (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2269 /* bgt rt5, ra5, label */
2270 md_assemblef ("slt $ta,%s,%s", argv[1], argv[0]);
2271 md_assemblef ("beqz $ta,%s", argv[2]);
2275 do_pseudo_bles (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2277 /* bgt rt5, ra5, label */
2278 md_assemblef ("slts $ta,%s,%s", argv[1], argv[0]);
2279 md_assemblef ("beqz $ta,%s", argv[2]);
2283 do_pseudo_blt (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2285 /* rt5, ra5, label */
2286 md_assemblef ("slt $ta,%s,%s", argv[0], argv[1]);
2287 md_assemblef ("bnez $ta,%s", argv[2]);
2291 do_pseudo_blts (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2293 /* rt5, ra5, label */
2294 md_assemblef ("slts $ta,%s,%s", argv[0], argv[1]);
2295 md_assemblef ("bnez $ta,%s", argv[2]);
2299 do_pseudo_br (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2301 md_assemblef ("jr %s", argv[0]);
2305 do_pseudo_bral (int argc, char *argv[], int pv ATTRIBUTE_UNUSED)
2308 md_assemblef ("jral $lp,%s", argv[0]);
2310 md_assemblef ("jral %s,%s", argv[0], argv[1]);
2314 do_pseudo_la_internal (const char *arg_reg, const char *arg_label,
2319 if (!nds32_pic && !strstr(arg_label, "@"))
2321 md_assemblef ("sethi %s,hi20(%s)", arg_reg, arg_label);
2322 md_assemblef ("ori %s,%s,lo12(%s)", arg_reg, arg_reg, arg_label);
2324 else if (strstr (arg_label, "@TPOFF"))
2326 /* la $rt, sym@TPOFF */
2327 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2328 md_assemblef ("ori $ta,$ta,lo12(%s)", arg_label);
2329 md_assemblef ("add %s,$ta,%s", arg_reg, TLS_REG);
2331 else if (strstr(arg_label, "@GOTTPOFF"))
2333 /* la $rt, sym@GOTTPOFF*/
2334 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2335 md_assemblef ("lwi $ta,[$ta+lo12(%s)]", arg_label);
2336 md_assemblef ("add %s,$ta,%s", arg_reg, TLS_REG);
2338 else if (nds32_pic && ((strstr (arg_label, "@PLT")
2339 || strstr (arg_label, "@GOTOFF"))))
2341 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2342 md_assemblef ("ori $ta,$ta,lo12(%s)", arg_label);
2343 md_assemblef ("add %s,$ta,$gp", arg_reg);
2345 else if (nds32_pic && strstr (arg_label, "@GOT"))
2347 long addend = builtin_addend (arg_label, NULL);
2349 md_assemblef ("sethi $ta,hi20(%s)", arg_label);
2350 md_assemblef ("ori $ta,$ta,lo12(%s)", arg_label);
2351 md_assemblef ("lw %s,[$gp+$ta]", arg_reg);
2354 if (addend < 0x4000 && addend >= -0x4000)
2356 md_assemblef ("addi %s,%s,%d", arg_reg, arg_reg, addend);
2360 do_pseudo_li_internal ("$ta", addend);
2361 md_assemblef ("add %s,$ta,%s", arg_reg, arg_reg);
2366 as_bad (_("need PIC qualifier with symbol. '%s'"), line);
2371 do_pseudo_la (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2373 do_pseudo_la_internal (argv[0], argv[1], argv[argc]);
2377 do_pseudo_li_internal (char *rt, int imm32s)
2379 if (enable_16bit && imm32s <= 0xf && imm32s >= -0x10)
2380 md_assemblef ("movi55 %s,%d", rt, imm32s);
2381 else if (imm32s <= 0x7ffff && imm32s >= -0x80000)
2382 md_assemblef ("movi %s,%d", rt, imm32s);
2383 else if ((imm32s & 0xfff) == 0)
2384 md_assemblef ("sethi %s,hi20(%d)", rt, imm32s);
2387 md_assemblef ("sethi %s,hi20(%d)", rt, imm32s);
2388 md_assemblef ("ori %s,%s,lo12(%d)", rt, rt, imm32s);
2393 do_pseudo_li (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2395 /* Validate argv[1] for constant expression. */
2398 parse_expression (argv[1], &exp);
2399 if (exp.X_op != O_constant)
2401 as_bad (_("Operand is not a constant. `%s'"), argv[argc]);
2405 do_pseudo_li_internal (argv[0], exp.X_add_number);
2409 do_pseudo_ls_bhw (int argc ATTRIBUTE_UNUSED, char *argv[], int pv)
2413 const char *sign = "";
2415 /* Prepare arguments for various load/store. */
2416 sign = (pv & 0x10) ? "s" : "";
2417 ls = (pv & 0x80000000) ? 's' : 'l';
2420 case 0: size = 'b'; break;
2421 case 1: size = 'h'; break;
2422 case 2: size = 'w'; break;
2425 if (ls == 's' || size == 'w')
2428 if (builtin_isreg (argv[1], NULL))
2431 md_assemblef ("%c%ci %s,[%s]", ls, size, argv[0], argv[1]);
2433 else if (!nds32_pic)
2436 if (strstr (argv[1], "@TPOFF"))
2438 /* ls.w $rt, sym@TPOFF */
2439 md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
2440 md_assemblef ("ori $ta,$ta,lo12(%s)", argv[1]);
2441 md_assemblef ("%c%c%s %s,[$ta+%s]", ls, size, sign, argv[0], TLS_REG);
2443 else if (strstr (argv[1], "@GOTTPOFF"))
2445 /* ls.w $rt, sym@GOTTPOFF */
2446 md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
2447 md_assemblef ("lwi $ta,[$ta+lo12(%s)]", argv[1]);
2448 md_assemblef ("%c%c%s %s,[$ta+%s]", ls, size, sign, argv[0], TLS_REG);
2453 md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
2454 md_assemblef ("%c%c%si %s,[$ta+lo12(%s)]", ls, size, sign, argv[0], argv[1]);
2462 if (strstr (argv[1], "@GOTOFF"))
2465 md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
2466 md_assemblef ("ori $ta,$ta,lo12(%s)", argv[1]);
2467 md_assemblef ("%c%c%s %s,[$ta+$gp]", ls, size, sign, argv[0]);
2469 else if (strstr (argv[1], "@GOT"))
2471 long addend = builtin_addend (argv[1], NULL);
2473 md_assemblef ("sethi $ta,hi20(%s)", argv[1]);
2474 md_assemblef ("ori $ta,$ta,lo12(%s)", argv[1]);
2475 md_assemble ("lw $ta,[$gp+$ta]"); /* Load address word. */
2476 if (addend < 0x10000 && addend >= -0x10000)
2478 md_assemblef ("%c%c%si %s,[$ta+(%d)]", ls, size, sign, argv[0], addend);
2483 do_pseudo_li_internal (argv[0], addend);
2484 md_assemblef ("%c%c%s %s,[$ta+%s]", ls, size, sign, argv[0], argv[0]);
2489 as_bad (_("needs @GOT or @GOTOFF. %s"), argv[argc]);
2496 do_pseudo_ls_bhwp (int argc ATTRIBUTE_UNUSED, char *argv[], int pv)
2498 char *arg_rt = argv[0];
2499 char *arg_label = argv[1];
2500 char *arg_inc = argv[2];
2503 const char *sign = "";
2505 /* Prepare arguments for various load/store. */
2506 sign = (pv & 0x10) ? "s" : "";
2507 ls = (pv & 0x80000000) ? 's' : 'l';
2510 case 0: size = 'b'; break;
2511 case 1: size = 'h'; break;
2512 case 2: size = 'w'; break;
2515 if (ls == 's' || size == 'w')
2518 do_pseudo_la_internal ("$ta", arg_label, argv[argc]);
2519 md_assemblef ("%c%c%si.bi %s,[$ta],%s", ls, size, sign, arg_rt, arg_inc);
2523 do_pseudo_ls_bhwpc (int argc ATTRIBUTE_UNUSED, char *argv[], int pv)
2525 char *arg_rt = argv[0];
2526 char *arg_inc = argv[1];
2529 const char *sign = "";
2531 /* Prepare arguments for various load/store. */
2532 sign = (pv & 0x10) ? "s" : "";
2533 ls = (pv & 0x80000000) ? 's' : 'l';
2536 case 0: size = 'b'; break;
2537 case 1: size = 'h'; break;
2538 case 2: size = 'w'; break;
2541 if (ls == 's' || size == 'w')
2544 md_assemblef ("%c%c%si.bi %s,[$ta],%s", ls, size, sign, arg_rt, arg_inc);
2548 do_pseudo_ls_bhwi (int argc ATTRIBUTE_UNUSED, char *argv[], int pv)
2552 const char *sign = "";
2554 /* Prepare arguments for various load/store. */
2555 sign = (pv & 0x10) ? "s" : "";
2556 ls = (pv & 0x80000000) ? 's' : 'l';
2559 case 0: size = 'b'; break;
2560 case 1: size = 'h'; break;
2561 case 2: size = 'w'; break;
2564 if (ls == 's' || size == 'w')
2567 md_assemblef ("%c%c%si.bi %s,%s,%s",
2568 ls, size, sign, argv[0], argv[1], argv[2]);
2572 do_pseudo_move_reg_internal (char *dst, char *src)
2575 md_assemblef ("mov55 %s,%s", dst, src);
2577 md_assemblef ("ori %s,%s,0", dst, src);
2581 do_pseudo_move (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2585 parse_expression (argv[1], &exp);
2587 if (builtin_isreg (argv[1], NULL))
2588 do_pseudo_move_reg_internal (argv[0], argv[1]);
2589 else if (exp.X_op == O_constant)
2590 /* move $rt, imm -> li $rt, imm */
2591 do_pseudo_li_internal (argv[0], exp.X_add_number);
2593 /* l.w $rt, var -> l.w $rt, var */
2594 do_pseudo_ls_bhw (argc, argv, 2);
2598 do_pseudo_neg (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2600 /* Instead of "subri". */
2601 md_assemblef ("subri %s,%s,0", argv[0], argv[1]);
2605 do_pseudo_not (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2607 md_assemblef ("nor %s,%s,%s", argv[0], argv[1], argv[1]);
2611 do_pseudo_pushpopm (int argc, char *argv[], int pv ATTRIBUTE_UNUSED)
2613 /* posh/pop $ra, $rb */
2614 /* SMW.{b | a}{i | d}{m?} Rb, [Ra], Re, Enable4 */
2615 int rb, re, ra, en4;
2617 char *opc = "pushpopm";
2620 as_bad ("'pushm/popm $ra5, $rb5, $label' is deprecated. "
2621 "Only 'pushm/popm $ra5' is supported now. %s", argv[argc]);
2623 as_bad ("'pushm/popm $ra5, $rb5'. %s\n", argv[argc]);
2625 if (strstr (argv[argc], "pop") == argv[argc])
2627 else if (strstr (argv[argc], "push") == argv[argc])
2630 as_fatal ("nds32-as internal error. %s", argv[argc]);
2632 rb = builtin_regnum (argv[0], NULL);
2633 re = builtin_regnum (argv[1], NULL);
2637 as_warn ("$rb should not be smaller than $ra. %s", argv[argc]);
2638 /* Swap to right order. */
2644 /* Build enable4 mask. */
2646 if (re >= 28 || rb >= 28)
2648 for (i = (rb >= 28? rb: 28); i <= re; i++)
2649 en4 |= 1 << (3 - (i - 28));
2652 /* Adjust $re, $rb. */
2655 else if (nds32_gpr16 != 1 && re >= 28)
2658 /* Reduce register. */
2659 if (nds32_gpr16 && re > 10 && !(rb == 31 && re == 31))
2661 if (re >= 15 && strstr(opc, "smw") != NULL)
2662 md_assemblef ("%s $r15,[$sp],$r15,%d", opc, en4);
2664 md_assemblef ("%s $r%d,[$sp],$r10, 0x0", opc, rb);
2665 if (re >= 15 && strstr(opc, "lmw") != NULL)
2666 md_assemblef ("%s $r15,[$sp],$r15,%d", opc, en4);
2669 md_assemblef ("%s $r%d,[$sp],$r%d,%d", opc, rb, re, en4);
2673 do_pseudo_pushpop (int argc, char *argv[], int pv ATTRIBUTE_UNUSED)
2675 /* push/pop $ra5, $label=$sp */
2679 as_bad ("'push/pop $ra5, rb5' is deprecated. "
2680 "Only 'push/pop $ra5' is supported now. %s", argv[argc]);
2684 argvm[2] = argv[argc];
2685 do_pseudo_pushpopm (2, argvm, PV_DONT_CARE);
2689 do_pseudo_v3push (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2691 md_assemblef ("push25 %s,%s", argv[0], argv[1]);
2695 do_pseudo_v3pop (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2697 md_assemblef ("pop25 %s,%s", argv[0], argv[1]);
2700 /* pv == 0, parsing "push.s" pseudo instruction operands.
2701 pv != 0, parsing "pop.s" pseudo instruction operands. */
2704 do_pseudo_pushpop_stack (int argc, char *argv[], int pv)
2706 /* push.s Rb,Re,{$fp $gp $lp $sp} ==> smw.adm Rb,[$sp],Re,Eable4 */
2707 /* pop.s Rb,Re,{$fp $gp $lp $sp} ==> lmw.bim Rb,[$sp],Re,Eable4 */
2712 char *opc = (pv == 0) ? "smw.adm" : "lmw.bim";
2718 /* argc=1, operands pattern: { $fp $gp $lp $sp } */
2720 /* Set register number Rb = Re = $sp = $r31. */
2723 else if (argc == 2 || argc == 3)
2725 /* argc=2, operands pattern: Rb, Re */
2726 /* argc=3, operands pattern: Rb, Re, { $fp $gp $lp $sp } */
2728 /* Get register number in integer. */
2729 rb = builtin_regnum (argv[0], NULL);
2730 re = builtin_regnum (argv[1], NULL);
2732 /* Rb should be equal/less than Re. */
2734 as_bad ("The first operand (%s) should be equal to or smaller than "
2735 "second operand (%s).", argv[0], argv[1]);
2737 /* forbid using $fp|$gp|$lp|$sp in Rb or Re
2740 as_bad ("Cannot use $fp, $gp, $lp, or $sp at first operand !!");
2742 as_bad ("Cannot use $fp, $gp, $lp, or $sp at second operand !!");
2746 as_bad ("Invalid operands pattern !!");
2749 /* Build Enable4 mask. */
2750 /* Using last_arg_index for argc=1|2|3 is safe, because $fp, $gp, $lp,
2751 and $sp only appear in argc=1 or argc=3 if argc=2, en4 remains 0,
2752 which is also valid for code generation. */
2754 last_arg_index = argc - 1;
2755 if (strstr (argv[last_arg_index], "$fp"))
2757 if (strstr (argv[last_arg_index], "$gp"))
2759 if (strstr (argv[last_arg_index], "$lp"))
2761 if (strstr (argv[last_arg_index], "$sp"))
2764 md_assemblef ("%s $r%d,[$sp],$r%d,%d", opc, rb, re, en4);
2768 do_pseudo_push_bhwd (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2771 /* If users omit push location, use $sp as default value. */
2772 char location[8] = "$sp"; /* 8 is enough for register name. */
2776 case 0: size = 'b'; break;
2777 case 1: size = 'h'; break;
2778 case 2: size = 'w'; break;
2779 case 3: size = 'w'; break;
2784 strncpy (location, argv[1], 8);
2788 md_assemblef ("l.%c $ta,%s", size, argv[0]);
2789 md_assemblef ("smw.adm $ta,[%s],$ta", location);
2791 if ((pv & 0x3) == 0x3) /* double-word */
2793 md_assemblef ("l.w $ta,%s+4", argv[0]);
2794 md_assemblef ("smw.adm $ta,[%s],$ta", location);
2799 do_pseudo_pop_bhwd (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2802 /* If users omit pop location, use $sp as default value. */
2803 char location[8] = "$sp"; /* 8 is enough for register name. */
2807 case 0: size = 'b'; break;
2808 case 1: size = 'h'; break;
2809 case 2: size = 'w'; break;
2810 case 3: size = 'w'; break;
2815 strncpy (location, argv[2], 8);
2819 if ((pv & 0x3) == 0x3) /* double-word */
2821 md_assemblef ("lmw.bim %s,[%s],%s", argv[1], location, argv[1]);
2822 md_assemblef ("s.w %s,%s+4", argv[1], argv[0]);
2825 md_assemblef ("lmw.bim %s,[%s],%s", argv[1], location, argv[1]);
2826 md_assemblef ("s.%c %s,%s", size, argv[1], argv[0]);
2830 do_pseudo_pusha (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2832 /* If users omit push location, use $sp as default value. */
2833 char location[8] = "$sp"; /* 8 is enough for register name. */
2837 strncpy (location, argv[1], 8);
2841 md_assemblef ("la $ta,%s", argv[0]);
2842 md_assemblef ("smw.adm $ta,[%s],$ta", location);
2846 do_pseudo_pushi (int argc ATTRIBUTE_UNUSED, char *argv[], int pv ATTRIBUTE_UNUSED)
2848 /* If users omit push location, use $sp as default value. */
2849 char location[8] = "$sp"; /* 8 is enough for register name. */
2853 strncpy (location, argv[1], 8);
2857 md_assemblef ("li $ta,%s", argv[0]);
2858 md_assemblef ("smw.adm $ta,[%s],$ta", location);
2861 struct nds32_pseudo_opcode nds32_pseudo_opcode_table[] =
2863 {"b", 1, do_pseudo_b, 0, 0},
2864 {"bal", 1, do_pseudo_bal, 0, 0},
2866 {"bge", 3, do_pseudo_bge, 0, 0},
2867 {"bges", 3, do_pseudo_bges, 0, 0},
2869 {"bgt", 3, do_pseudo_bgt, 0, 0},
2870 {"bgts", 3, do_pseudo_bgts, 0, 0},
2872 {"ble", 3, do_pseudo_ble, 0, 0},
2873 {"bles", 3, do_pseudo_bles, 0, 0},
2875 {"blt", 3, do_pseudo_blt, 0, 0},
2876 {"blts", 3, do_pseudo_blts, 0, 0},
2878 {"br", 1, do_pseudo_br, 0, 0},
2879 {"bral", 1, do_pseudo_bral, 0, 0},
2881 {"call", 1, do_pseudo_bal, 0, 0},
2883 {"la", 2, do_pseudo_la, 0, 0},
2884 {"li", 2, do_pseudo_li, 0, 0},
2886 {"l.b", 2, do_pseudo_ls_bhw, 0, 0},
2887 {"l.h", 2, do_pseudo_ls_bhw, 1, 0},
2888 {"l.w", 2, do_pseudo_ls_bhw, 2, 0},
2889 {"l.bs", 2, do_pseudo_ls_bhw, 0 | 0x10, 0},
2890 {"l.hs", 2, do_pseudo_ls_bhw, 1 | 0x10, 0},
2891 {"s.b", 2, do_pseudo_ls_bhw, 0 | 0x80000000, 0},
2892 {"s.h", 2, do_pseudo_ls_bhw, 1 | 0x80000000, 0},
2893 {"s.w", 2, do_pseudo_ls_bhw, 2 | 0x80000000, 0},
2895 {"l.bp", 3, do_pseudo_ls_bhwp, 0, 0},
2896 {"l.bpc", 3, do_pseudo_ls_bhwpc, 0, 0},
2897 {"l.hp", 3, do_pseudo_ls_bhwp, 1, 0},
2898 {"l.hpc", 3, do_pseudo_ls_bhwpc, 1, 0},
2899 {"l.wp", 3, do_pseudo_ls_bhwp, 2, 0},
2900 {"l.wpc", 3, do_pseudo_ls_bhwpc, 2, 0},
2901 {"l.bsp", 3, do_pseudo_ls_bhwp, 0 | 0x10, 0},
2902 {"l.bspc", 3, do_pseudo_ls_bhwpc, 0 | 0x10, 0},
2903 {"l.hsp", 3, do_pseudo_ls_bhwp, 1 | 0x10, 0},
2904 {"l.hspc", 3, do_pseudo_ls_bhwpc, 1 | 0x10, 0},
2905 {"s.bp", 3, do_pseudo_ls_bhwp, 0 | 0x80000000, 0},
2906 {"s.bpc", 3, do_pseudo_ls_bhwpc, 0 | 0x80000000, 0},
2907 {"s.hp", 3, do_pseudo_ls_bhwp, 1 | 0x80000000, 0},
2908 {"s.hpc", 3, do_pseudo_ls_bhwpc, 1 | 0x80000000, 0},
2909 {"s.wp", 3, do_pseudo_ls_bhwp, 2 | 0x80000000, 0},
2910 {"s.wpc", 3, do_pseudo_ls_bhwpc, 2 | 0x80000000, 0},
2911 {"s.bsp", 3, do_pseudo_ls_bhwp, 0 | 0x80000000 | 0x10, 0},
2912 {"s.hsp", 3, do_pseudo_ls_bhwp, 1 | 0x80000000 | 0x10, 0},
2914 {"lbi.p", 3, do_pseudo_ls_bhwi, 0, 0},
2915 {"lhi.p", 3, do_pseudo_ls_bhwi, 1, 0},
2916 {"lwi.p", 3, do_pseudo_ls_bhwi, 2, 0},
2917 {"sbi.p", 3, do_pseudo_ls_bhwi, 0 | 0x80000000, 0},
2918 {"shi.p", 3, do_pseudo_ls_bhwi, 1 | 0x80000000, 0},
2919 {"swi.p", 3, do_pseudo_ls_bhwi, 2 | 0x80000000, 0},
2920 {"lbsi.p", 3, do_pseudo_ls_bhwi, 0 | 0x10, 0},
2921 {"lhsi.p", 3, do_pseudo_ls_bhwi, 1 | 0x10, 0},
2922 {"lwsi.p", 3, do_pseudo_ls_bhwi, 2 | 0x10, 0},
2924 {"move", 2, do_pseudo_move, 0, 0},
2925 {"neg", 2, do_pseudo_neg, 0, 0},
2926 {"not", 2, do_pseudo_not, 0, 0},
2928 {"pop", 2, do_pseudo_pushpop, 0, 0},
2929 {"push", 2, do_pseudo_pushpop, 0, 0},
2930 {"popm", 2, do_pseudo_pushpopm, 0, 0},
2931 {"pushm", 3, do_pseudo_pushpopm, 0, 0},
2933 {"v3push", 2, do_pseudo_v3push, 0, 0},
2934 {"v3pop", 2, do_pseudo_v3pop, 0, 0},
2936 /* Support pseudo instructions of pushing/poping registers into/from stack
2937 push.s Rb, Re, { $fp $gp $lp $sp } ==> smw.adm Rb,[$sp],Re,Enable4
2938 pop.s Rb, Re, { $fp $gp $lp $sp } ==> lmw.bim Rb,[$sp],Re,Enable4 */
2939 { "push.s", 3, do_pseudo_pushpop_stack, 0, 0 },
2940 { "pop.s", 3, do_pseudo_pushpop_stack, 1, 0 },
2941 { "push.b", 2, do_pseudo_push_bhwd, 0, 0 },
2942 { "push.h", 2, do_pseudo_push_bhwd, 1, 0 },
2943 { "push.w", 2, do_pseudo_push_bhwd, 2, 0 },
2944 { "push.d", 2, do_pseudo_push_bhwd, 3, 0 },
2945 { "pop.b", 3, do_pseudo_pop_bhwd, 0, 0 },
2946 { "pop.h", 3, do_pseudo_pop_bhwd, 1, 0 },
2947 { "pop.w", 3, do_pseudo_pop_bhwd, 2, 0 },
2948 { "pop.d", 3, do_pseudo_pop_bhwd, 3, 0 },
2949 { "pusha", 2, do_pseudo_pusha, 0, 0 },
2950 { "pushi", 2, do_pseudo_pushi, 0, 0 },
2952 {NULL, 0, NULL, 0, 0}
2956 nds32_init_nds32_pseudo_opcodes (void)
2958 struct nds32_pseudo_opcode *opcode = nds32_pseudo_opcode_table;
2960 nds32_pseudo_opcode_hash = hash_new ();
2961 for ( ; opcode->opcode; opcode++)
2965 op = hash_find (nds32_pseudo_opcode_hash, opcode->opcode);
2968 as_warn (_("Duplicated pseudo-opcode %s."), opcode->opcode);
2971 hash_insert (nds32_pseudo_opcode_hash, opcode->opcode, opcode);
2975 static struct nds32_pseudo_opcode *
2976 nds32_lookup_pseudo_opcode (char *str)
2979 /* Assume pseudo-opcode are less than 16-char in length. */
2982 for (i = 0; i < (int)ARRAY_SIZE (op); i++)
2984 if (ISSPACE (op[i] = str[i]))
2988 if (i >= (int)ARRAY_SIZE (op))
2993 return hash_find (nds32_pseudo_opcode_hash, op);
2997 nds32_pseudo_opcode_wrapper (char *line, struct nds32_pseudo_opcode *opcode)
3000 char *argv[8] = {NULL};
3002 char *str = xstrdup (line);
3004 /* Parse arguments for opcode. */
3005 s = str + strlen (opcode->opcode);
3010 /* Dummy comma to ease separate arguments as below. */
3016 if (argc >= opcode->argc
3017 || (argc >= (int)ARRAY_SIZE (argv) - 1))
3018 as_bad (_("Too many argument. `%s'"), line);
3025 } while (s[0] != '\0');
3027 /* Put the origin line for debugging. */
3029 opcode->proc (argc, argv, opcode->pseudo_val);
3033 /* This function will be invoked from function `nds32_after_parse_args'.
3034 Thus, if the value of option has been set, keep the value the way it is. */
3037 nds32_parse_arch (char *str)
3039 static const struct nds32_arch
3050 {"v3m", ISA_V3M, 1, 0, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_AABI},
3051 {"v3j", ISA_V3, 1, 0, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_AABI},
3052 {"v3s", ISA_V3, 0, 1, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_V2FP_PLUS},
3053 {"v3f", ISA_V3, 0, 1, 1, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_V2FP_PLUS},
3054 {"v3", ISA_V3, 0, 0, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_AABI},
3055 {"v2j", ISA_V2, 1, 0, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_AABI},
3056 {"v2s", ISA_V2, 0, 1, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_V2FP_PLUS},
3057 {"v2f", ISA_V2, 0, 1, 1, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_V2FP_PLUS},
3058 {"v2", ISA_V2, 0, 0, 0, E_NDS32_FPU_REG_32SP_16DP, E_NDS_ABI_AABI},
3062 for (i = 0; i < ARRAY_SIZE (archs); i++)
3064 if (strcmp (str, archs[i].name) != 0)
3067 /* The value `-1' represents this option has *NOT* been set. */
3068 nds32_baseline = (-1 != nds32_baseline) ? nds32_baseline : archs[i].baseline;
3069 nds32_gpr16 = (-1 != nds32_gpr16) ? nds32_gpr16 : archs[i].reduced_reg;
3070 nds32_fpu_sp_ext = (-1 != nds32_fpu_sp_ext) ? nds32_fpu_sp_ext : archs[i].fpu_sp_ext;
3071 nds32_fpu_dp_ext = (-1 != nds32_fpu_dp_ext) ? nds32_fpu_dp_ext : archs[i].fpu_dp_ext;
3072 nds32_freg = (-1 != nds32_freg) ? nds32_freg : archs[i].fpu_freg;
3073 nds32_abi = (-1 != nds32_abi) ? nds32_abi : archs[i].abi;
3078 /* Logic here rejects the input arch name. */
3079 as_bad (_("unknown arch name `%s'\n"), str);
3084 /* This function parses "baseline" specified. */
3087 nds32_parse_baseline (char *str)
3089 if (strcmp (str, "v3") == 0)
3090 nds32_baseline = ISA_V3;
3091 else if (strcmp (str, "v3m") == 0)
3092 nds32_baseline = ISA_V3M;
3093 else if (strcmp (str, "v2") == 0)
3094 nds32_baseline = ISA_V2;
3097 /* Logic here rejects the input baseline. */
3098 as_bad (_("unknown baseline `%s'\n"), str);
3105 /* This function parses "fpu-freg" specified. */
3108 nds32_parse_freg (char *str)
3110 if (strcmp (str, "2") == 0)
3111 nds32_freg = E_NDS32_FPU_REG_32SP_16DP;
3112 else if (strcmp (str, "3") == 0)
3113 nds32_freg = E_NDS32_FPU_REG_32SP_32DP;
3114 else if (strcmp (str, "1") == 0)
3115 nds32_freg = E_NDS32_FPU_REG_16SP_8DP;
3116 else if (strcmp (str, "0") == 0)
3117 nds32_freg = E_NDS32_FPU_REG_8SP_4DP;
3120 /* Logic here rejects the input FPU configuration. */
3121 as_bad (_("unknown FPU configuration `%s'\n"), str);
3128 /* This function parse "abi=" specified. */
3131 nds32_parse_abi (char *str)
3133 if (strcmp (str, "v2") == 0)
3134 nds32_abi = E_NDS_ABI_AABI;
3136 else if (strcmp (str, "v2fp") == 0)
3137 nds32_abi = E_NDS_ABI_V2FP;
3138 else if (strcmp (str, "v1") == 0)
3139 nds32_abi = E_NDS_ABI_V1;
3140 else if (strcmp (str,"v2fpp") == 0)
3141 nds32_abi = E_NDS_ABI_V2FP_PLUS;
3144 /* Logic here rejects the input abi version. */
3145 as_bad (_("unknown ABI version`%s'\n"), str);
3152 /* This function turn on all extensions and instructions support. */
3155 nds32_all_ext (void)
3160 nds32_16bit_ext = 1;
3162 nds32_perf_ext2 = 1;
3163 nds32_string_ext = 1;
3164 nds32_audio_ext = 1;
3166 nds32_fpu_sp_ext = 1;
3167 nds32_fpu_dp_ext = 1;
3172 /* GAS will call md_parse_option whenever getopt returns an unrecognized code,
3173 presumably indicating a special code value which appears in md_longopts.
3174 This function should return non-zero if it handled the option and zero
3175 otherwise. There is no need to print a message about an option not being
3176 recognized. This will be handled by the generic code. */
3179 nds32_parse_option (int c, char *arg)
3181 struct nds32_parse_option_table *coarse_tune;
3182 struct nds32_set_option_table *fine_tune;
3183 char *ptr_arg = NULL;
3187 case OPTION_OPTIMIZE:
3189 optimize_for_space = 0;
3191 case OPTION_OPTIMIZE_SPACE:
3193 optimize_for_space = 1;
3196 target_big_endian = 1;
3199 target_big_endian = 0;
3207 case OPTION_RELAX_FP_AS_GP_OFF:
3208 nds32_relax_fp_as_gp = 0;
3210 case OPTION_RELAX_B2BB_ON:
3211 nds32_relax_b2bb = 1;
3213 case OPTION_RELAX_ALL_OFF:
3214 nds32_relax_all = 0;
3217 /* Determination of which option table to search for to save time. */
3221 ptr_arg = strchr (arg, '=');
3225 /* Find the value after '='. */
3226 if (ptr_arg != NULL)
3228 for (coarse_tune = parse_opts; coarse_tune->name != NULL; coarse_tune++)
3230 if (strncmp (arg, coarse_tune->name, (ptr_arg - arg)) == 0)
3232 coarse_tune->func (ptr_arg);
3241 /* Filter out the Disable option first. */
3242 if (strncmp (arg, "no-", 3) == 0)
3248 for (fine_tune = toggle_opts; fine_tune->name != NULL; fine_tune++)
3250 if (strcmp (arg, fine_tune->name) == 0)
3252 if (fine_tune->var != NULL)
3253 *fine_tune->var = (disable) ? 0 : 1;
3258 /* Nothing match. */
3265 /* tc_check_label */
3268 nds32_check_label (symbolS *label ATTRIBUTE_UNUSED)
3270 /* The code used to create BB is move to frob_label.
3271 They should go there. */
3275 set_endian_little (int on)
3277 target_big_endian = !on;
3280 /* These functions toggles the generation of 16-bit. First encounter signals
3281 the beginning of not generating 16-bit instructions and next encounter
3282 signals the restoring back to default behavior. */
3285 trigger_16bit (int trigger)
3287 enable_16bit = trigger;
3290 static int backup_16bit_mode;
3292 restore_16bit (int no_use ATTRIBUTE_UNUSED)
3294 enable_16bit = backup_16bit_mode;
3298 off_16bit (int no_use ATTRIBUTE_UNUSED)
3300 backup_16bit_mode = enable_16bit;
3304 /* Built-in segments for small object. */
3305 typedef struct nds32_seg_entryT
3312 nds32_seg_entry nds32_seg_table[] =
3314 {NULL, ".sdata_f", SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA
3315 | SEC_HAS_CONTENTS | SEC_SMALL_DATA},
3316 {NULL, ".sdata_b", SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA
3317 | SEC_HAS_CONTENTS | SEC_SMALL_DATA},
3318 {NULL, ".sdata_h", SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA
3319 | SEC_HAS_CONTENTS | SEC_SMALL_DATA},
3320 {NULL, ".sdata_w", SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA
3321 | SEC_HAS_CONTENTS | SEC_SMALL_DATA},
3322 {NULL, ".sdata_d", SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA
3323 | SEC_HAS_CONTENTS | SEC_SMALL_DATA},
3324 {NULL, ".sbss_f", SEC_ALLOC | SEC_SMALL_DATA},
3325 {NULL, ".sbss_b", SEC_ALLOC | SEC_SMALL_DATA},
3326 {NULL, ".sbss_h", SEC_ALLOC | SEC_SMALL_DATA},
3327 {NULL, ".sbss_w", SEC_ALLOC | SEC_SMALL_DATA},
3328 {NULL, ".sbss_d", SEC_ALLOC | SEC_SMALL_DATA}
3331 /* Indexes to nds32_seg_table[]. */
3332 enum NDS32_SECTIONS_ENUM
3334 SDATA_F_SECTION = 0,
3335 SDATA_B_SECTION = 1,
3336 SDATA_H_SECTION = 2,
3337 SDATA_W_SECTION = 3,
3338 SDATA_D_SECTION = 4,
3346 /* The following code is borrowed from v850_seg. Revise this is needed. */
3349 do_nds32_seg (int i, subsegT sub)
3351 nds32_seg_entry *seg = nds32_seg_table + i;
3353 obj_elf_section_change_hook ();
3356 subseg_set (seg->s, sub);
3359 seg->s = subseg_new (seg->name, sub);
3360 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
3362 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
3363 if ((seg->flags & SEC_LOAD) == 0)
3364 seg_info (seg->s)->bss = 1;
3372 subsegT sub = get_absolute_expression ();
3374 do_nds32_seg (i, sub);
3375 demand_empty_rest_of_line ();
3378 /* Set if label adjustment is needed. I should not adjust .xbyte in dwarf. */
3379 static symbolS *nds32_last_label; /* Last label for aligment. */
3381 /* This code is referred from D30V for adjust label to be with pedning
3382 aligment. For example,
3386 Without this, the above label will not attatch to incoming data. */
3389 nds32_adjust_label (int n)
3391 /* FIXME: I think adjust lable and alignment is
3392 the programmer's obligation. Saddly, VLSI team doesn't
3393 properly use .align for their test cases.
3394 So I re-implement cons_align and auto adjust labels, again.
3396 I think d30v's implmentation is simple and good enough. */
3398 symbolS *label = nds32_last_label;
3399 nds32_last_label = NULL;
3401 /* SEC_ALLOC is used to eliminate .debug_ sections.
3402 SEC_CODE is used to include section for ILM. */
3403 if (((now_seg->flags & SEC_ALLOC) == 0 && (now_seg->flags & SEC_CODE) == 0)
3404 || strcmp (now_seg->name, ".eh_frame") == 0
3405 || strcmp (now_seg->name, ".gcc_except_table") == 0)
3408 /* Only frag by alignment when needed.
3409 Otherwise, it will fail to optimize labels on 4-byte boundary. (bug8454)
3410 See md_convert_frag () and RELAX_SET_RELAXABLE (frag) for details. */
3411 if (frag_now_fix () & ((1 << n) -1 ))
3413 if (subseg_text_p (now_seg))
3414 frag_align_code (n, 0);
3416 frag_align (n, 0, 0);
3418 /* Record the minimum alignment for this segment. */
3419 record_alignment (now_seg, n - OCTETS_PER_BYTE_POWER);
3425 int label_seen = FALSE;
3426 struct frag *old_frag;
3427 valueT old_value, new_value;
3429 gas_assert (S_GET_SEGMENT (label) == now_seg);
3431 old_frag = symbol_get_frag (label);
3432 old_value = S_GET_VALUE (label);
3433 new_value = (valueT) frag_now_fix ();
3435 /* Multiple labels may be on the same address. And the last symbol
3436 may not be a label at all, e.g., register name, external function names,
3437 so I have to track the last label in tc_frob_label instead of
3438 just using symbol_lastP. */
3439 for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
3441 if (symbol_get_frag (sym) == old_frag
3442 && S_GET_VALUE (sym) == old_value)
3446 symbol_set_frag (sym, frag_now);
3447 S_SET_VALUE (sym, new_value);
3449 else if (label_seen && symbol_get_frag (sym) != old_frag)
3456 nds32_cons_align (int size ATTRIBUTE_UNUSED)
3459 This is called before `md_flush_pending_output' is called by `cons'.
3461 There are two things should be done for auto-adjust-label.
3462 1. Align data/instructions and adjust label to be attached to them.
3463 2. Clear auto-adjust state, so incommng data/instructions will not
3471 in this case, '.word 0x2' will adjust the label, .L0, but '.word 0x3' should not.
3473 I think `md_flush_pending_output' is a good place to clear the auto-adjust state,
3474 but it is also called by `cons' before this function.
3475 To simplify the code, instead of overriding .zero, .fill, .space, etc,
3476 I think we should just adjust label in `nds32_aligned_X_cons' instead of here. */
3480 nds32_aligned_cons (int idx)
3482 nds32_adjust_label (idx);
3483 /* Call default handler. */
3485 if (now_seg->flags & SEC_CODE
3486 && now_seg->flags & SEC_ALLOC && now_seg->flags & SEC_RELOC)
3488 /* Use BFD_RELOC_NDS32_DATA to avoid EX9 optimization replacing data. */
3491 exp.X_add_number = 0;
3492 exp.X_op = O_constant;
3493 fix_new_exp (frag_now, frag_now_fix () - (1 << idx), 1 << idx,
3494 &exp, 0, BFD_RELOC_NDS32_DATA);
3498 /* `.double' directive. */
3501 nds32_aligned_float_cons (int type)
3509 nds32_adjust_label (2);
3515 nds32_adjust_label (4);
3518 as_bad ("Unrecognized float type, %c\n", (char)type);
3520 /* Call default handler. */
3525 nds32_enable_pic (int ignore ATTRIBUTE_UNUSED)
3527 /* Another way to do -mpic.
3528 This is for GCC internal use and should always be first line
3529 of code, otherwise, the effect is not determined. */
3534 nds32_set_abi (int ver)
3539 /* Relax directive to set relocation R_NDS32_RELAX_ENTRY value. */
3542 nds32_relax_relocs (int relax)
3547 char *subtype_relax[] =
3548 {"", "", "ex9", "ifc"};
3550 name = input_line_pointer;
3551 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
3552 input_line_pointer++;
3553 saved_char = *input_line_pointer;
3554 *input_line_pointer = 0;
3556 for (i = 0; i < (int) ARRAY_SIZE (subtype_relax); i++)
3558 if (strcmp (name, subtype_relax[i]) == 0)
3564 enable_relax_relocs = relax & enable_relax_relocs;
3565 enable_relax_ex9 = relax & enable_relax_ex9;
3566 enable_relax_ifc = relax & enable_relax_ifc;
3569 enable_relax_ex9 = relax;
3572 enable_relax_ifc = relax;
3580 *input_line_pointer = saved_char;
3581 ignore_rest_of_line ();
3584 /* Record which arguments register($r0 ~ $r5) is not used in callee.
3588 nds32_set_hint_func_args (int ignore ATTRIBUTE_UNUSED)
3590 ignore_rest_of_line ();
3593 /* Insert relocations to mark the begin and end of a fp-omitted function,
3594 for further relaxation use.
3598 nds32_omit_fp_begin (int mode)
3602 if (nds32_relax_fp_as_gp == 0)
3604 exp.X_op = O_symbol;
3605 exp.X_add_symbol = abs_section_sym;
3609 exp.X_add_number = R_NDS32_RELAX_REGION_OMIT_FP_FLAG;
3610 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3611 BFD_RELOC_NDS32_RELAX_REGION_BEGIN);
3616 exp.X_add_number = R_NDS32_RELAX_REGION_OMIT_FP_FLAG;
3617 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3618 BFD_RELOC_NDS32_RELAX_REGION_END);
3622 /* Insert relocations to mark the begin and end of ex9 region,
3623 for further relaxation use.
3627 nds32_no_ex9_begin (int mode)
3631 exp.X_op = O_symbol;
3632 exp.X_add_symbol = abs_section_sym;
3635 exp.X_add_number = R_NDS32_RELAX_REGION_NO_EX9_FLAG;
3636 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3637 BFD_RELOC_NDS32_RELAX_REGION_BEGIN);
3641 exp.X_add_number = R_NDS32_RELAX_REGION_NO_EX9_FLAG;
3642 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3643 BFD_RELOC_NDS32_RELAX_REGION_END);
3648 nds32_loop_begin (int mode)
3650 /* Insert loop region relocation here. */
3653 exp.X_op = O_symbol;
3654 exp.X_add_symbol = abs_section_sym;
3657 exp.X_add_number = R_NDS32_RELAX_REGION_INNERMOST_LOOP_FLAG;
3658 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3659 BFD_RELOC_NDS32_RELAX_REGION_BEGIN);
3663 exp.X_add_number = R_NDS32_RELAX_REGION_INNERMOST_LOOP_FLAG;
3664 fix_new_exp (frag_now, frag_now_fix (), 0, &exp, 0,
3665 BFD_RELOC_NDS32_RELAX_REGION_END);
3669 struct nds32_relocs_group
3671 struct nds32_relocs_pattern *pattern;
3672 struct nds32_relocs_group *next;
3675 static struct nds32_relocs_group *nds32_relax_hint_current = NULL;
3677 /* Insert a relax hint. */
3680 nds32_relax_hint (int mode ATTRIBUTE_UNUSED)
3684 struct nds32_relocs_pattern *relocs = NULL;
3685 struct nds32_relocs_group *group, *new;
3687 name = input_line_pointer;
3688 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
3689 input_line_pointer++;
3690 saved_char = *input_line_pointer;
3691 *input_line_pointer = 0;
3692 name = strdup (name);
3694 /* Find relax hint entry for next instruction, and all member will be
3695 initialized at that time. */
3696 relocs = hash_find (nds32_hint_hash, name);
3699 relocs = malloc (sizeof (struct nds32_relocs_pattern));
3700 hash_insert (nds32_hint_hash, name, relocs);
3704 while (relocs->next)
3705 relocs=relocs->next;
3706 relocs->next = malloc (sizeof (struct nds32_relocs_pattern));
3707 relocs = relocs->next;
3710 relocs->next = NULL;
3711 *input_line_pointer = saved_char;
3712 ignore_rest_of_line ();
3714 /* Get the final one of relax hint series. */
3716 /* It has to build this list because there are maybe more than one
3717 instructions relative to the same instruction. It to connect to
3718 next instruction after md_assemble. */
3719 new = malloc (sizeof (struct nds32_relocs_group));
3720 new->pattern = relocs;
3722 group = nds32_relax_hint_current;
3724 nds32_relax_hint_current = new;
3727 while (group->next != NULL)
3728 group = group->next;
3734 /* Decide the size of vector entries, only accepts 4 or 16 now. */
3737 nds32_vec_size (int ignore ATTRIBUTE_UNUSED)
3743 if (exp.X_op == O_constant)
3745 if (exp.X_add_number == 4 || exp.X_add_number == 16)
3748 vec_size = exp.X_add_number;
3749 else if (vec_size != exp.X_add_number)
3750 as_warn (_("Different arguments of .vec_size are found, "
3751 "previous %d, current %d"),
3752 (int) vec_size, (int) exp.X_add_number);
3755 as_warn (_("Argument of .vec_size is expected 4 or 16, actual: %d."),
3756 (int) exp.X_add_number);
3759 as_warn (_("Argument of .vec_size is not a constant."));
3762 /* The behavior of ".flag" directive varies depending on the target.
3763 In nds32 target, we use it to recognize whether this assembly content is
3764 generated by compiler. Other features can also be added in this function
3768 nds32_flag (int ignore ATTRIBUTE_UNUSED)
3773 char *possible_flags[] = { "verbatim" };
3775 /* Skip whitespaces. */
3776 name = input_line_pointer;
3777 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
3778 input_line_pointer++;
3779 saved_char = *input_line_pointer;
3780 *input_line_pointer = 0;
3782 for (i = 0; i < (int) ARRAY_SIZE (possible_flags); i++)
3784 if (strcmp (name, possible_flags[i]) == 0)
3789 /* flag: verbatim */
3795 /* Already found the flag, no need to continue next loop. */
3800 *input_line_pointer = saved_char;
3801 ignore_rest_of_line ();
3805 nds32_n12hc (int ignore ATTRIBUTE_UNUSED)
3807 /* N1213HC core is used. */
3811 /* The target specific pseudo-ops which we support. */
3812 const pseudo_typeS md_pseudo_table[] =
3814 /* Forced alignment if declared these ways. */
3815 {"ascii", stringer, 8 + 0},
3816 {"asciz", stringer, 8 + 1},
3817 {"double", nds32_aligned_float_cons, 'd'},
3818 {"dword", nds32_aligned_cons, 3},
3819 {"float", nds32_aligned_float_cons, 'f'},
3820 {"half", nds32_aligned_cons, 1},
3821 {"hword", nds32_aligned_cons, 1},
3822 {"int", nds32_aligned_cons, 2},
3823 {"long", nds32_aligned_cons, 2},
3824 {"octa", nds32_aligned_cons, 4},
3825 {"quad", nds32_aligned_cons, 3},
3826 {"qword", nds32_aligned_cons, 4},
3827 {"short", nds32_aligned_cons, 1},
3828 {"byte", nds32_aligned_cons, 0},
3829 {"single", nds32_aligned_float_cons, 'f'},
3830 {"string", stringer, 8 + 1},
3831 {"word", nds32_aligned_cons, 2},
3833 {"little", set_endian_little, 1},
3834 {"big", set_endian_little, 0},
3835 {"16bit_on", trigger_16bit, 1},
3836 {"16bit_off", trigger_16bit, 0},
3837 {"restore_16bit", restore_16bit, 0},
3838 {"off_16bit", off_16bit, 0},
3840 {"sdata_d", nds32_seg, SDATA_D_SECTION},
3841 {"sdata_w", nds32_seg, SDATA_W_SECTION},
3842 {"sdata_h", nds32_seg, SDATA_H_SECTION},
3843 {"sdata_b", nds32_seg, SDATA_B_SECTION},
3844 {"sdata_f", nds32_seg, SDATA_F_SECTION},
3846 {"sbss_d", nds32_seg, SBSS_D_SECTION},
3847 {"sbss_w", nds32_seg, SBSS_W_SECTION},
3848 {"sbss_h", nds32_seg, SBSS_H_SECTION},
3849 {"sbss_b", nds32_seg, SBSS_B_SECTION},
3850 {"sbss_f", nds32_seg, SBSS_F_SECTION},
3852 {"pic", nds32_enable_pic, 0},
3853 {"n12_hc", nds32_n12hc, 0},
3854 {"abi_1", nds32_set_abi, E_NDS_ABI_V1},
3855 {"abi_2", nds32_set_abi, E_NDS_ABI_AABI},
3857 {"abi_2fp", nds32_set_abi, E_NDS_ABI_V2FP},
3858 {"abi_2fp_plus", nds32_set_abi, E_NDS_ABI_V2FP_PLUS},
3859 {"relax", nds32_relax_relocs, 1},
3860 {"no_relax", nds32_relax_relocs, 0},
3861 {"hint_func_args", nds32_set_hint_func_args, 0}, /* Abandon?? */
3862 {"omit_fp_begin", nds32_omit_fp_begin, 1},
3863 {"omit_fp_end", nds32_omit_fp_begin, 0},
3864 {"no_ex9_begin", nds32_no_ex9_begin, 1},
3865 {"no_ex9_end", nds32_no_ex9_begin, 0},
3866 {"vec_size", nds32_vec_size, 0},
3867 {"flag", nds32_flag, 0},
3868 {"innermost_loop_begin", nds32_loop_begin, 1},
3869 {"innermost_loop_end", nds32_loop_begin, 0},
3870 {"relax_hint", nds32_relax_hint, 0},
3875 nds32_pre_do_align (int n, char *fill, int len, int max)
3877 /* Only make a frag if we HAVE to... */
3879 if (n != 0 && !need_pass_2)
3883 if (subseg_text_p (now_seg))
3886 frag_align_code (n, max);
3888 /* Tag this alignment when there is a lable before it. */
3891 fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
3896 frag_align (n, 0, max);
3899 frag_align (n, *fill, max);
3901 frag_align_pattern (n, fill, len, max);
3906 nds32_do_align (int n)
3908 /* Optimize for space and label exists. */
3911 /* FIXME:I think this will break debug info sections and except_table. */
3912 if (!enable_relax_relocs || !subseg_text_p (now_seg))
3915 /* Create and attach a BFD_RELOC_NDS32_LABEL fixup
3916 the size of instruction may not be correct because
3917 it could be relaxable. */
3918 exp.X_op = O_symbol;
3919 exp.X_add_symbol = section_symbol (now_seg);
3920 exp.X_add_number = n;
3921 fix_new_exp (frag_now,
3922 frag_now_fix (), 0, &exp, 0, BFD_RELOC_NDS32_LABEL);
3925 /* Supported Andes machines. */
3928 enum bfd_architecture bfd_mach;
3932 /* This is the callback for nds32-asm.c to parse operands. */
3935 nds32_asm_parse_operand (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
3936 struct nds32_asm_insn *pinsn,
3937 char **pstr, int64_t *value)
3940 expressionS *pexp = pinsn->info;
3942 hold = input_line_pointer;
3943 input_line_pointer = *pstr;
3945 *pstr = input_line_pointer;
3946 input_line_pointer = hold;
3952 return NASM_R_SYMBOL;
3954 *value = pexp->X_add_number;
3955 return NASM_R_CONST;
3960 return NASM_R_ILLEGAL;
3964 /* GAS will call this function at the start of the assembly, after the command
3965 line arguments have been parsed and all the machine independent
3966 initializations have been completed. */
3971 struct nds32_keyword *k;
3972 relax_info_t *relax_info;
3974 bfd_set_arch_mach (stdoutput, TARGET_ARCH, nds32_baseline);
3976 nds32_init_nds32_pseudo_opcodes ();
3977 asm_desc.parse_operand = nds32_asm_parse_operand;
3978 nds32_asm_init (&asm_desc, 0);
3980 /* Initial general pupose registers hash table. */
3981 nds32_gprs_hash = hash_new ();
3982 for (k = keyword_gpr; k->name; k++)
3983 hash_insert (nds32_gprs_hash, k->name, k);
3985 /* Initial branch hash table. */
3986 nds32_relax_info_hash = hash_new ();
3987 for (relax_info = relax_table; relax_info->opcode; relax_info++)
3988 hash_insert (nds32_relax_info_hash, relax_info->opcode, relax_info);
3990 /* Initial relax hint hash table. */
3991 nds32_hint_hash = hash_new ();
3992 enable_16bit = nds32_16bit_ext;
3995 /* HANDLE_ALIGN in write.c. */
3998 nds32_handle_align (fragS *fragp)
4000 static const unsigned char nop16[] = { 0x92, 0x00 };
4001 static const unsigned char nop32[] = { 0x40, 0x00, 0x00, 0x09 };
4005 if (fragp->fr_type != rs_align_code)
4008 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4009 p = fragp->fr_literal + fragp->fr_fix;
4020 exp_t.X_op = O_symbol;
4021 exp_t.X_add_symbol = abs_section_sym;
4022 exp_t.X_add_number = R_NDS32_INSN16_CONVERT_FLAG;
4023 fix_new_exp (fragp, fragp->fr_fix, 2, &exp_t, 0,
4024 BFD_RELOC_NDS32_INSN16);
4025 memcpy (p, nop16, 2);
4032 memcpy (p, nop32, 4);
4037 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4038 fragp->fr_fix += bytes;
4041 /* md_flush_pending_output */
4044 nds32_flush_pending_output (void)
4046 nds32_last_label = NULL;
4050 nds32_frob_label (symbolS *label)
4052 dwarf2_emit_label (label);
4055 /* TC_START_LABEL */
4058 nds32_start_label (int asmdone ATTRIBUTE_UNUSED, int secdone ATTRIBUTE_UNUSED)
4060 if (optimize && subseg_text_p (now_seg))
4068 nds32_target_format (void)
4071 if (target_big_endian)
4072 return "elf32-nds32be-linux";
4074 return "elf32-nds32le-linux";
4076 if (target_big_endian)
4077 return "elf32-nds32be";
4079 return "elf32-nds32le";
4083 static enum nds32_br_range
4084 get_range_type (const struct nds32_field *field)
4086 gas_assert (field != NULL);
4088 if (field->bitpos != 0)
4089 return BR_RANGE_U4G;
4091 if (field->bitsize == 24 && field->shift == 1)
4092 return BR_RANGE_S16M;
4093 else if (field->bitsize == 16 && field->shift == 1)
4094 return BR_RANGE_S64K;
4095 else if (field->bitsize == 14 && field->shift == 1)
4096 return BR_RANGE_S16K;
4097 else if (field->bitsize == 8 && field->shift == 1)
4098 return BR_RANGE_S256;
4100 return BR_RANGE_U4G;
4103 /* Save pseudo instruction relocation list. */
4105 static struct nds32_relocs_pattern*
4106 nds32_elf_save_pseudo_pattern (fixS* fixP, struct nds32_opcode *opcode,
4107 char *out, symbolS *sym,
4108 struct nds32_relocs_pattern *reloc_ptr,
4112 reloc_ptr = malloc (sizeof (struct nds32_relocs_pattern));
4113 reloc_ptr->seg = now_seg;
4114 reloc_ptr->sym = sym;
4115 reloc_ptr->frag = fragP;
4116 reloc_ptr->frchain = frchain_now;
4117 reloc_ptr->fixP = fixP;
4118 reloc_ptr->opcode = opcode;
4119 reloc_ptr->where = out;
4120 reloc_ptr->next = NULL;
4124 /* Check X_md to transform relocation. */
4127 nds32_elf_record_fixup_exp (fragS *fragP, char *str,
4128 const struct nds32_field *fld,
4129 expressionS *pexp, char* out,
4130 struct nds32_asm_insn *insn)
4136 /* Handle instruction relocation. */
4137 if (fld && fld->bitpos == 0 && (insn->attr & NASM_ATTR_HI20))
4139 /* Relocation for hi20 modifier. */
4142 case BFD_RELOC_NDS32_GOTOFF: /* @GOTOFF */
4143 reloc = BFD_RELOC_NDS32_GOTOFF_HI20;
4145 case BFD_RELOC_NDS32_GOT20: /* @GOT */
4146 reloc = BFD_RELOC_NDS32_GOT_HI20;
4148 case BFD_RELOC_NDS32_25_PLTREL: /* @PLT */
4150 as_bad (_("Invalid PIC expression."));
4152 reloc = BFD_RELOC_NDS32_PLT_GOTREL_HI20;
4154 case BFD_RELOC_NDS32_GOTPC20: /* _GLOBAL_OFFSET_TABLE_ */
4155 reloc = BFD_RELOC_NDS32_GOTPC_HI20;
4157 case BFD_RELOC_NDS32_TPOFF: /* @TPOFF */
4158 reloc = BFD_RELOC_NDS32_TLS_LE_HI20;
4160 case BFD_RELOC_NDS32_GOTTPOFF: /* @GOTTPOFF */
4161 reloc = BFD_RELOC_NDS32_TLS_IE_HI20;
4163 default: /* No suffix. */
4164 reloc = BFD_RELOC_NDS32_HI20;
4167 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4168 insn->info, 0 /* pcrel */, reloc);
4170 else if (fld && fld->bitpos == 0 && (insn->attr & NASM_ATTR_LO12))
4172 /* Relocation for lo12 modifier. */
4173 if (fld->bitsize == 15 && fld->shift == 0)
4178 case BFD_RELOC_NDS32_GOTOFF: /* @GOTOFF */
4179 reloc = BFD_RELOC_NDS32_GOTOFF_LO12;
4181 case BFD_RELOC_NDS32_GOT20: /* @GOT */
4182 reloc = BFD_RELOC_NDS32_GOT_LO12;
4184 case BFD_RELOC_NDS32_25_PLTREL: /* @PLT */
4186 as_bad (_("Invalid PIC expression."));
4188 reloc = BFD_RELOC_NDS32_PLT_GOTREL_LO12;
4190 case BFD_RELOC_NDS32_GOTPC20: /* _GLOBAL_OFFSET_TABLE_ */
4191 reloc = BFD_RELOC_NDS32_GOTPC_LO12;
4193 case BFD_RELOC_NDS32_TPOFF: /* @TPOFF */
4194 reloc = BFD_RELOC_NDS32_TLS_LE_LO12;
4196 default: /* No suffix. */
4197 reloc = BFD_RELOC_NDS32_LO12S0;
4201 else if (fld->bitsize == 15 && fld->shift == 1)
4202 reloc = BFD_RELOC_NDS32_LO12S1; /* [ls]hi */
4203 else if (fld->bitsize == 15 && fld->shift == 2)
4208 case BFD_RELOC_NDS32_GOTTPOFF: /* @GOTTPOFF */
4209 reloc = BFD_RELOC_NDS32_TLS_IE_LO12S2;
4211 default: /* No suffix. */
4212 reloc = BFD_RELOC_NDS32_LO12S2;
4216 else if (fld->bitsize == 15 && fld->shift == 3)
4217 reloc = BFD_RELOC_NDS32_LO12S3; /* [ls]di */
4218 else if (fld->bitsize == 12 && fld->shift == 2)
4219 reloc = R_NDS32_LO12S2_SP_RELA; /* f[ls][sd]i */
4221 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4222 insn->info, 0 /* pcrel */, reloc);
4224 else if (fld && fld->bitpos == 0 && insn->opcode->isize == 4
4225 && (insn->attr & NASM_ATTR_PCREL))
4227 /* Relocation for 32-bit branch instructions. */
4228 if (fld->bitsize == 24 && fld->shift == 1)
4229 reloc = BFD_RELOC_NDS32_25_PCREL;
4230 else if (fld->bitsize == 16 && fld->shift == 1)
4231 reloc = BFD_RELOC_NDS32_17_PCREL;
4232 else if (fld->bitsize == 14 && fld->shift == 1)
4233 reloc = BFD_RELOC_NDS32_15_PCREL;
4234 else if (fld->bitsize == 8 && fld->shift == 1)
4235 reloc = BFD_RELOC_NDS32_WORD_9_PCREL;
4239 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4240 insn->info, 1 /* pcrel */, reloc);
4242 else if (fld && fld->bitpos == 0 && insn->opcode->isize == 4
4243 && (insn->attr & NASM_ATTR_GPREL))
4245 /* Relocation for 32-bit gp-relative instructions. */
4246 if (fld->bitsize == 19 && fld->shift == 0)
4247 reloc = BFD_RELOC_NDS32_SDA19S0;
4248 else if (fld->bitsize == 18 && fld->shift == 1)
4249 reloc = BFD_RELOC_NDS32_SDA18S1;
4250 else if (fld->bitsize == 17 && fld->shift == 2)
4251 reloc = BFD_RELOC_NDS32_SDA17S2;
4255 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4256 insn->info, 0 /* pcrel */, reloc);
4257 /* Insert INSN16 for converting fp_as_gp. */
4258 exp.X_op = O_symbol;
4259 exp.X_add_symbol = abs_section_sym;
4260 exp.X_add_number = 0;
4261 if (in_omit_fp && reloc == BFD_RELOC_NDS32_SDA17S2)
4262 fix_new_exp (fragP, out - fragP->fr_literal,
4263 insn->opcode->isize, &exp, 0 /* pcrel */,
4264 BFD_RELOC_NDS32_INSN16);
4266 else if (fld && fld->bitpos == 0 && insn->opcode->isize == 2
4267 && (insn->attr & NASM_ATTR_PCREL))
4269 /* Relocation for 16-bit branch instructions. */
4270 if (fld->bitsize == 8 && fld->shift == 1)
4271 reloc = BFD_RELOC_NDS32_9_PCREL;
4275 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4276 insn->info, 1 /* pcrel */, reloc);
4278 else if (fld && fld->bitpos == 0 && (insn->attr & NASM_ATTR_IFC_EXT))
4280 /* Relocation for ifcall instruction. */
4281 if (insn->opcode->isize == 2 && fld->bitsize == 9 && fld->shift == 1)
4282 reloc = BFD_RELOC_NDS32_10IFCU_PCREL;
4283 else if (insn->opcode->isize == 4 && fld->bitsize == 16
4285 reloc = BFD_RELOC_NDS32_17IFC_PCREL;
4289 fixP = fix_new_exp (fragP, out - fragP->fr_literal, insn->opcode->isize,
4290 insn->info, 1 /* pcrel */, reloc);
4293 as_bad (_("Don't know how to handle this field. %s"), str);
4298 /* Build instruction pattern to relax. There are two type group pattern
4299 including pseudo instruction and relax hint. */
4302 nds32_elf_build_relax_relation (fixS *fixP, expressionS *pexp, char* out,
4303 struct nds32_opcode *opcode, fragS *fragP,
4304 const struct nds32_field *fld)
4306 struct nds32_relocs_pattern *reloc_ptr;
4307 struct nds32_relocs_group *group;
4308 symbolS *sym = NULL;
4310 /* The expression may be used uninitialized. */
4312 sym = pexp->X_add_symbol;
4316 /* Save instruction relation for pseudo instruction expanding pattern. */
4317 reloc_ptr = nds32_elf_save_pseudo_pattern (fixP, opcode, out, sym,
4320 relocs_list = reloc_ptr;
4323 struct nds32_relocs_pattern *temp = relocs_list;
4326 temp->next = reloc_ptr;
4329 else if (nds32_relax_hint_current)
4331 /* Save instruction relation by relax hint. */
4332 group = nds32_relax_hint_current;
4335 nds32_elf_save_pseudo_pattern (fixP, opcode, out, sym,
4336 group->pattern, fragP);
4337 group = group->next;
4338 free (nds32_relax_hint_current);
4339 nds32_relax_hint_current = group;
4343 /* Set relaxing false only for relax_hint trigger it. */
4348 #define N32_MEM_EXT(insn) ((N32_OP6_MEM << 25) | insn)
4350 /* Relax pattern for link time relaxation. */
4352 static struct nds32_relax_hint_table relax_ls_table[] =
4355 /* Set address: la -> sethi ori. */
4356 NDS32_RELAX_HINT_LA, /* main_type */
4357 8, /* relax_code_size */
4361 }, /* relax_code_seq */
4363 {0, 4, NDS32_HINT | NDS32_ADDEND, BFD_RELOC_NDS32_LOADSTORE},
4364 {4, 4, NDS32_HINT | NDS32_ABS, BFD_RELOC_NDS32_INSN16}
4368 /* Set address: l.w -> sethi ori. */
4369 NDS32_RELAX_HINT_LS, /* main_type */
4370 8, /* relax_code_size */
4374 }, /* relax_code_seq */
4376 {0, 4, NDS32_HINT | NDS32_ADDEND, BFD_RELOC_NDS32_LOADSTORE},
4377 {4, 4, NDS32_HINT | NDS32_ABS, BFD_RELOC_NDS32_INSN16}
4388 /* Since sethi loadstore relocation has to using next instruction to determine
4389 elimination itself or not, we have to return the next instruction range. */
4392 nds32_elf_sethi_range (struct nds32_relocs_pattern *pattern)
4397 switch (pattern->opcode->value)
4402 case N32_MEM_EXT (N32_MEM_LB):
4403 case N32_MEM_EXT (N32_MEM_LBS):
4404 case N32_MEM_EXT (N32_MEM_SB):
4405 range = NDS32_LOADSTORE_BYTE;
4410 case N32_MEM_EXT (N32_MEM_LH):
4411 case N32_MEM_EXT (N32_MEM_LHS):
4412 case N32_MEM_EXT (N32_MEM_SH):
4413 range = NDS32_LOADSTORE_HALF;
4417 case N32_MEM_EXT (N32_MEM_LW):
4418 case N32_MEM_EXT (N32_MEM_SW):
4419 range = NDS32_LOADSTORE_WORD;
4423 range = NDS32_LOADSTORE_FLOAT_S;
4427 range = NDS32_LOADSTORE_FLOAT_D;
4430 range = NDS32_LOADSTORE_IMM;
4433 range = NDS32_LOADSTORE_NONE;
4436 if (range != NDS32_LOADSTORE_NONE)
4438 pattern = pattern->next;
4443 /* The args means: instruction size, the 1st instruction is converted to 16 or
4444 not, optimize option, 16 bit instruction is enable. */
4445 #define SET_ADDEND(size, convertible, optimize, insn16_on) \
4446 (((size) & 0xff) | ((convertible) ? 1 << 31 : 0) \
4447 | ((optimize) ? 1<< 30 : 0) | (insn16_on ? 1 << 29 : 0))
4450 nds32_set_elf_flags_by_insn (struct nds32_asm_insn * insn)
4452 /* Set E_NDS32_HAS_EXT_INST. */
4453 if (insn->opcode->attr & NASM_ATTR_PERF_EXT)
4456 nds32_elf_flags |= E_NDS32_HAS_EXT_INST;
4458 as_bad (_("instruction %s requires enabling performance extension"),
4459 insn->opcode->opcode);
4461 else if (insn->opcode->attr & NASM_ATTR_PERF2_EXT)
4463 if (nds32_perf_ext2)
4464 nds32_elf_flags |= E_NDS32_HAS_EXT2_INST;
4466 as_bad (_("instruction %s requires enabling performance extension II"),
4467 insn->opcode->opcode);
4469 else if (insn->opcode->attr & NASM_ATTR_AUDIO_ISAEXT)
4471 if (nds32_audio_ext)
4472 nds32_elf_flags |= E_NDS32_HAS_AUDIO_INST;
4474 as_bad (_("instruction %s requires enabling AUDIO extension"),
4475 insn->opcode->opcode);
4477 else if (insn->opcode->attr & NASM_ATTR_STR_EXT)
4479 if (nds32_string_ext)
4480 nds32_elf_flags |= E_NDS32_HAS_STRING_INST;
4482 as_bad (_("instruction %s requires enabling STRING extension"),
4483 insn->opcode->opcode);
4485 else if ((insn->opcode->attr & NASM_ATTR_DIV)
4486 && (insn->opcode->attr & NASM_ATTR_DXREG))
4488 if (nds32_div && nds32_dx_regs)
4489 nds32_elf_flags |= E_NDS32_HAS_DIV_DX_INST;
4491 as_bad (_("instruction %s requires enabling DIV & DX_REGS extension"),
4492 insn->opcode->opcode);
4494 else if (insn->opcode->attr & NASM_ATTR_FPU)
4496 if (nds32_fpu_sp_ext || nds32_fpu_dp_ext)
4498 if (!(nds32_elf_flags & (E_NDS32_HAS_FPU_INST | E_NDS32_HAS_FPU_DP_INST)))
4502 as_bad (_("instruction %s requires enabling FPU extension"),
4503 insn->opcode->opcode);
4505 else if (insn->opcode->attr & NASM_ATTR_FPU_SP_EXT)
4507 if (nds32_fpu_sp_ext)
4508 nds32_elf_flags |= E_NDS32_HAS_FPU_INST;
4510 as_bad (_("instruction %s requires enabling FPU_SP extension"),
4511 insn->opcode->opcode);
4513 else if ((insn->opcode->attr & NASM_ATTR_FPU_SP_EXT)
4514 && (insn->opcode->attr & NASM_ATTR_MAC))
4516 if (nds32_fpu_sp_ext && nds32_mac)
4518 nds32_elf_flags |= E_NDS32_HAS_FPU_MAC_INST;
4519 nds32_elf_flags |= E_NDS32_HAS_FPU_INST;
4522 as_bad (_("instruction %s requires enabling FPU_MAC extension"),
4523 insn->opcode->opcode);
4525 else if (insn->opcode->attr & NASM_ATTR_FPU_DP_EXT)
4527 if (nds32_fpu_dp_ext)
4528 nds32_elf_flags |= E_NDS32_HAS_FPU_DP_INST;
4530 as_bad (_("instruction %s requires enabling FPU_DP extension"),
4531 insn->opcode->opcode);
4533 else if ((insn->opcode->attr & NASM_ATTR_FPU_DP_EXT)
4534 && (insn->opcode->attr & NASM_ATTR_MAC))
4536 if (nds32_fpu_dp_ext && nds32_mac)
4538 nds32_elf_flags |= E_NDS32_HAS_FPU_MAC_INST;
4539 nds32_elf_flags |= E_NDS32_HAS_FPU_DP_INST;
4542 as_bad (_("instruction %s requires enabling FPU_MAC extension"),
4543 insn->opcode->opcode);
4545 /* TODO: FPU_BOTH */
4546 else if ((insn->opcode->attr & NASM_ATTR_MAC)
4547 && (insn->opcode->attr & NASM_ATTR_DXREG))
4549 if (nds32_mac && nds32_dx_regs)
4550 nds32_elf_flags |= E_NDS32_HAS_MAC_DX_INST;
4552 as_bad (_("instruction %s requires enabling DX_REGS extension"),
4553 insn->opcode->opcode);
4555 /* TODO: for DX_REG set but not for MAC, DIV, AUDIO */
4556 else if (insn->opcode->attr & NASM_ATTR_IFC_EXT)
4558 nds32_elf_flags |= E_NDS32_HAS_IFC_INST;
4560 /* TODO: E_NDS32_HAS_SATURATION_INST */
4563 /* Flag for analysis relaxation type. */
4565 enum nds32_insn_type
4567 N32_RELAX_SETHI = 1,
4568 N32_RELAX_BR = (1 << 1),
4569 N32_RELAX_LSI = (1 << 2),
4570 N32_RELAX_JUMP = (1 << 3),
4571 N32_RELAX_CALL = (1 << 4),
4572 N32_RELAX_ORI = (1 << 5),
4573 N32_RELAX_MEM = (1 << 6),
4574 N32_RELAX_MOVI = (1 << 7),
4577 struct nds32_hint_map
4579 bfd_reloc_code_real_type hi_type;
4581 enum nds32_relax_hint_type hint_type;
4582 enum nds32_br_range range;
4583 enum nds32_insn_type insn_list;
4586 /* Table to match instructions with hint and relax pattern. */
4588 static struct nds32_hint_map hint_map [] =
4592 BFD_RELOC_NDS32_HI20,
4594 NDS32_RELAX_HINT_NONE,
4596 N32_RELAX_SETHI | N32_RELAX_ORI | N32_RELAX_CALL
4600 _dummy_first_bfd_reloc_code_real,
4602 NDS32_RELAX_HINT_NONE,
4604 N32_RELAX_BR | N32_RELAX_CALL
4608 BFD_RELOC_NDS32_HI20,
4610 NDS32_RELAX_HINT_NONE,
4612 N32_RELAX_BR | N32_RELAX_SETHI | N32_RELAX_ORI | N32_RELAX_CALL
4616 BFD_RELOC_NDS32_HI20,
4618 NDS32_RELAX_HINT_NONE,
4620 N32_RELAX_SETHI | N32_RELAX_ORI | N32_RELAX_JUMP
4624 /* There is two kinds of veriation of LONGJUMP5. One of them
4625 generate EMPTY relocation for converted INSN16 if needed.
4626 But we don't distinguish them here. */
4627 _dummy_first_bfd_reloc_code_real,
4629 NDS32_RELAX_HINT_NONE,
4631 N32_RELAX_BR | N32_RELAX_JUMP
4635 BFD_RELOC_NDS32_HI20,
4637 NDS32_RELAX_HINT_NONE,
4639 N32_RELAX_SETHI | N32_RELAX_ORI | N32_RELAX_BR | N32_RELAX_JUMP
4643 _dummy_first_bfd_reloc_code_real,
4645 NDS32_RELAX_HINT_NONE,
4647 N32_RELAX_MOVI | N32_RELAX_BR
4650 /* LOADSTORE ADDRESS. */
4651 BFD_RELOC_NDS32_HI20,
4653 NDS32_RELAX_HINT_LA,
4655 N32_RELAX_SETHI | N32_RELAX_ORI
4658 /* LOADSTORE ADDRESS. */
4659 BFD_RELOC_NDS32_HI20,
4661 NDS32_RELAX_HINT_LS,
4663 N32_RELAX_SETHI | N32_RELAX_LSI
4668 /* Find the relaxation pattern according to instructions. */
4671 nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
4672 struct nds32_relax_hint_table *hint_info)
4674 unsigned int opcode, seq_size;
4675 enum nds32_br_range range;
4676 struct nds32_relocs_pattern *pattern, *hi_pattern = NULL;
4678 relax_info_t *relax_info = NULL;
4679 nds32_relax_fixup_info_t *fixup_info, *hint_fixup;
4680 enum nds32_relax_hint_type hint_type = NDS32_RELAX_HINT_NONE;
4681 struct nds32_relax_hint_table *table_ptr;
4682 uint32_t *code_seq, *hint_code;
4683 enum nds32_insn_type relax_type = 0;
4684 struct nds32_hint_map *map_ptr = hint_map;
4686 char *check_insn[] =
4687 { "bnes38", "beqs38", "bnez38", "bnezs8", "beqz38", "beqzs8" };
4689 /* TODO: PLT GOT. */
4690 /* Traverse all pattern instruction and set flag. */
4691 pattern = relocs_pattern;
4694 if (pattern->opcode->isize == 4)
4696 /* 4 byte instruction. */
4697 opcode = N32_OP6 (pattern->opcode->value);
4701 hi_pattern = pattern;
4702 relax_type |= N32_RELAX_SETHI;
4705 relax_type |= N32_RELAX_MEM;
4708 relax_type |= N32_RELAX_ORI;
4713 relax_type |= N32_RELAX_BR;
4716 relax_type |= N32_RELAX_MOVI;
4728 relax_type |= N32_RELAX_LSI;
4731 if (__GF (pattern->opcode->value, 0, 1) == 1)
4732 relax_type |= N32_RELAX_CALL;
4734 relax_type |= N32_RELAX_JUMP;
4737 if (__GF (pattern->opcode->value, 24, 1) == 1)
4738 relax_type |= N32_RELAX_CALL;
4740 relax_type |= N32_RELAX_JUMP;
4743 as_warn (_("relax hint unrecognized instruction: line %d."),
4744 pattern->frag->fr_line);
4750 /* 2 byte instruction. Compare by opcode name because the opcode of
4751 2byte instruction is not regular. */
4752 for (i = 0; i < sizeof (check_insn) / sizeof (check_insn[0]); i++)
4754 if (strcmp (pattern->opcode->opcode, check_insn[i]) == 0)
4756 relax_type |= N32_RELAX_BR;
4760 if (strcmp (pattern->opcode->opcode, "movi55") == 0)
4761 relax_type |= N32_RELAX_MOVI;
4763 pattern = pattern->next;
4766 /* Analysis instruction flag to choose relaxation table. */
4767 while (map_ptr->insn_list != 0)
4769 if (map_ptr->insn_list == relax_type
4771 || (hi_pattern->fixP
4772 && hi_pattern->fixP->fx_r_type == map_ptr->hi_type)))
4775 hint_type = map_ptr->hint_type;
4776 range = map_ptr->range;
4782 if (map_ptr->insn_list == 0)
4784 as_warn (_("Can not find match relax hint. line : %d"),
4785 relocs_pattern->frag->fr_line);
4789 /* Get the match table. */
4792 /* Branch relax pattern. */
4793 relax_info = hash_find (nds32_relax_info_hash, opc);
4796 fixup_info = relax_info->relax_fixup[range];
4797 code_seq = relax_info->relax_code_seq[range];
4798 seq_size = relax_info->relax_code_size[range];
4802 /* Load-store relax pattern. */
4803 table_ptr = relax_ls_table;
4804 while (table_ptr->main_type != 0)
4806 if (table_ptr->main_type == hint_type)
4808 fixup_info = table_ptr->relax_fixup;
4809 code_seq = table_ptr->relax_code_seq;
4810 seq_size = table_ptr->relax_code_size;
4815 if (table_ptr->main_type == 0)
4821 hint_fixup = hint_info->relax_fixup;
4822 hint_code = hint_info->relax_code_seq;
4823 hint_info->relax_code_size = seq_size;
4825 while (fixup_info->size != 0)
4827 if (fixup_info->ramp & NDS32_HINT)
4829 memcpy (hint_fixup, fixup_info, sizeof (nds32_relax_fixup_info_t));
4834 /* Clear final relocation. */
4835 memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
4836 /* Copy code sequance. */
4837 memcpy (hint_code, code_seq, seq_size);
4841 /* Because there are a lot of variant of load-store, check
4842 all these type here. */
4844 #define CLEAN_REG(insn) ((insn) & 0xff0003ff)
4846 nds32_match_hint_insn (struct nds32_opcode *opcode, uint32_t seq)
4848 char *check_insn[] =
4849 { "bnes38", "beqs38", "bnez38", "bnezs8", "beqz38", "beqzs8" };
4850 uint32_t insn = opcode->value;
4853 insn = CLEAN_REG (opcode->value);
4860 /* In relocation_table, it regards instruction LBI as representation
4861 of all the NDS32_RELAX_HINT_LS pattern. */
4862 if (insn == OP6 (LBI) || insn == OP6 (SBI) || insn == OP6 (LBSI)
4863 || insn == OP6 (LHI) || insn == OP6 (SHI) || insn == OP6 (LHSI)
4864 || insn == OP6 (LWI) || insn == OP6 (SWI)
4865 || insn == OP6 (LWC) || insn == OP6 (SWC))
4869 /* This is for LONGCALL5 and LONGCALL6. */
4870 if (insn == OP6 (BR2))
4874 /* This is for LONGJUMP5 and LONGJUMP6. */
4875 if (opcode->isize == 4
4876 && (insn == OP6 (BR1) || insn == OP6 (BR2) || insn == OP6 (BR3)))
4878 else if (opcode->isize == 2)
4880 for (i = 0; i < sizeof (check_insn) / sizeof (check_insn[0]); i++)
4881 if (strcmp (opcode->opcode, check_insn[i]) == 0)
4886 /* This is for LONGJUMP7. */
4887 if (opcode->isize == 2 && strcmp (opcode->opcode, "movi55") == 0)
4894 /* Append relax relocation for link time relaxing. */
4897 nds32_elf_append_relax_relocs (const char *key ATTRIBUTE_UNUSED, void *value)
4899 struct nds32_relocs_pattern *relocs_pattern =
4900 (struct nds32_relocs_pattern *) value;
4901 struct nds32_relocs_pattern *pattern_temp, *pattern_now;
4902 symbolS *sym, *hi_sym = NULL;
4905 segT seg_bak = now_seg;
4906 frchainS *frchain_bak = frchain_now;
4907 struct nds32_relax_hint_table hint_info;
4908 nds32_relax_fixup_info_t *hint_fixup, *fixup_now;
4910 offsetT branch_offset;
4913 unsigned int ptr_offset, hint_count, relax_code_size, count = 0;
4914 uint32_t *code_seq, code_insn;
4917 if (!relocs_pattern)
4920 if (!nds32_find_reloc_table (relocs_pattern, &hint_info))
4923 /* Save symbol for some EMPTY relocation using. */
4924 pattern_now = relocs_pattern;
4927 if (pattern_now->opcode->value == OP6 (SETHI))
4929 hi_sym = pattern_now->sym;
4932 pattern_now = pattern_now->next;
4935 /* Inserting fix up must specify now_seg or frchain_now. */
4936 now_seg = relocs_pattern->seg;
4937 frchain_now = relocs_pattern->frchain;
4938 fragP = relocs_pattern->frag;
4939 branch_offset = fragP->fr_offset;
4941 hint_fixup = hint_info.relax_fixup;
4942 code_seq = hint_info.relax_code_seq;
4943 relax_code_size = hint_info.relax_code_size;
4944 pattern_now = relocs_pattern;
4946 /* Insert relaxation. */
4947 exp.X_op = O_symbol;
4951 /* Choose the match fixup by instruction. */
4952 code_insn = CLEAN_REG (*(code_seq + count));
4953 if (!nds32_match_hint_insn (pattern_now->opcode, code_insn))
4956 code_insn = CLEAN_REG (*(code_seq + count));
4958 while (!nds32_match_hint_insn (pattern_now->opcode, code_insn))
4961 if (count >= relax_code_size / 4)
4963 as_bad (_("Internal error: Relax hint error. %s: %x"),
4964 now_seg->name, pattern_now->opcode->value);
4967 code_insn = CLEAN_REG (*(code_seq + count));
4970 fragP = pattern_now->frag;
4971 sym = pattern_now->sym;
4972 branch_offset = fragP->fr_offset;
4974 where = pattern_now->where;
4975 /* Find the instruction map fix. */
4976 fixup_now = hint_fixup;
4977 while (fixup_now->offset != offset)
4980 if (fixup_now->size == 0)
4983 /* This element is without relaxation relocation. */
4984 if (fixup_now->size == 0)
4986 pattern_now = pattern_now->next;
4989 fixup_size = fixup_now->size;
4991 /* Insert all fixup. */
4992 while (fixup_size != 0 && fixup_now->offset == offset)
4994 /* Set the real instruction size in element. */
4995 fixup_size = pattern_now->opcode->isize;
4996 if (fixup_now->ramp & NDS32_FIX)
4998 /* Convert original relocation. */
4999 pattern_now->fixP->fx_r_type = fixup_now->r_type ;
5002 else if ((fixup_now->ramp & NDS32_PTR) != 0)
5004 /* This relocation has to point to another instruction. Make
5005 sure each resolved relocation has to be pointed. */
5006 pattern_temp = relocs_pattern;
5007 /* All instruction in relax_table should be 32-bit. */
5008 hint_count = hint_info.relax_code_size / 4;
5009 code_insn = CLEAN_REG (*(code_seq + hint_count - 1));
5010 while (pattern_temp)
5012 /* Point to every resolved relocation. */
5013 if (nds32_match_hint_insn (pattern_temp->opcode, code_insn))
5016 pattern_temp->where - pattern_temp->frag->fr_literal;
5017 exp.X_add_symbol = symbol_temp_new (now_seg, ptr_offset,
5018 pattern_temp->frag);
5019 exp.X_add_number = 0;
5021 fix_new_exp (fragP, where - fragP->fr_literal,
5022 fixup_size, &exp, 0, fixup_now->r_type);
5023 fixP->fx_addnumber = fixP->fx_offset;
5025 pattern_temp = pattern_temp->next;
5029 else if (fixup_now->ramp & NDS32_ADDEND)
5031 range = nds32_elf_sethi_range (relocs_pattern);
5032 if (range == NDS32_LOADSTORE_NONE)
5034 as_bad (_("Internal error: Range error. %s"), now_seg->name);
5037 exp.X_add_symbol = abs_section_sym;
5038 exp.X_add_number = SET_ADDEND (4, 0, optimize, enable_16bit);
5039 exp.X_add_number |= ((range & 0x3f) << 8);
5041 else if ((fixup_now->ramp & NDS32_ABS) != 0)
5043 /* This is a tag relocation. */
5044 exp.X_add_symbol = abs_section_sym;
5045 exp.X_add_number = 0;
5047 else if ((fixup_now->ramp & NDS32_INSN16) != 0)
5051 /* This is a tag relocation. */
5052 exp.X_add_symbol = abs_section_sym;
5053 exp.X_add_number = 0;
5055 else if ((fixup_now->ramp & NDS32_SYM) != 0)
5057 /* For EMPTY relocation save the true symbol. */
5058 exp.X_add_symbol = hi_sym;
5059 exp.X_add_number = branch_offset;
5063 exp.X_add_symbol = sym;
5064 exp.X_add_number = branch_offset;
5067 if (fixup_size != 0)
5069 fixP = fix_new_exp (fragP, where - fragP->fr_literal,
5070 fixup_size, &exp, 0, fixup_now->r_type);
5071 fixP->fx_addnumber = fixP->fx_offset;
5074 fixup_size = fixup_now->size;
5076 if (count < relax_code_size / 4)
5078 pattern_now = pattern_now->next;
5083 frchain_now = frchain_bak;
5086 /* Check instruction if it can be used for the baseline. */
5089 nds32_check_insn_available (struct nds32_asm_insn insn, char *str)
5091 int attr = insn.attr & ATTR_ALL;
5092 static int baseline_isa = 0;
5093 /* No isa setting or all isa can use. */
5094 if (attr == 0 || attr == ATTR_ALL)
5097 if (baseline_isa == 0)
5099 /* Map option baseline and instruction attribute. */
5100 switch (nds32_baseline)
5103 baseline_isa = ATTR (ISA_V2);
5106 baseline_isa = ATTR (ISA_V3);
5109 baseline_isa = ATTR (ISA_V3M);
5114 if ((baseline_isa & attr) == 0)
5116 as_bad (_("Not support instrcution %s in the baseline."), str);
5122 /* Stub of machine dependent. */
5125 md_assemble (char *str)
5127 struct nds32_asm_insn insn;
5129 struct nds32_pseudo_opcode *popcode;
5130 const struct nds32_field *fld = NULL;
5133 struct nds32_relocs_pattern *relocs_temp;
5136 int label = label_exist;
5138 popcode = nds32_lookup_pseudo_opcode (str);
5139 /* Note that we need to check 'verbatim' and
5140 'opcode->physical_op'. If the assembly content is generated by
5141 compiler and this opcode is a physical instruction, there is no
5142 need to perform pseudo instruction expansion/transformation. */
5143 if (popcode && !(verbatim && popcode->physical_op))
5145 pseudo_opcode = TRUE;
5146 nds32_pseudo_opcode_wrapper (str, popcode);
5147 pseudo_opcode = FALSE;
5148 nds32_elf_append_relax_relocs (NULL, relocs_list);
5150 /* Free pseudo list. */
5151 relocs_temp = relocs_list;
5154 relocs_list = relocs_list->next;
5156 relocs_temp = relocs_list;
5163 insn.info = (expressionS *) alloca (sizeof (expressionS));
5164 nds32_assemble (&asm_desc, &insn, str);
5166 switch (asm_desc.result)
5168 case NASM_ERR_UNKNOWN_OP:
5169 as_bad (_("Unrecognized opcode, %s."), str);
5171 case NASM_ERR_SYNTAX:
5172 as_bad (_("Incorrect syntax, %s."), str);
5174 case NASM_ERR_OPERAND:
5175 as_bad (_("Unrecognized operand, %s."), str);
5177 case NASM_ERR_OUT_OF_RANGE:
5178 as_bad (_("Operand out of range, %s."), str);
5180 case NASM_ERR_REG_REDUCED:
5181 as_bad (_("Prohibited register used for reduced-register, %s."), str);
5183 case NASM_ERR_JUNK_EOL:
5184 as_bad (_("Junk at end of line, %s."), str);
5188 gas_assert (insn.opcode);
5190 nds32_set_elf_flags_by_insn (&insn);
5192 gas_assert (insn.opcode->isize == 4 || insn.opcode->isize == 2);
5194 if (!nds32_check_insn_available (insn, str))
5197 /* Make sure the begining of text being 2-byte align. */
5198 nds32_adjust_label (1);
5200 /* Try to allocate the max size to guarantee relaxable same branch
5201 instructions in the same fragment. */
5202 frag_grow (NDS32_MAXCHAR);
5204 if (fld && (insn.attr & NASM_ATTR_BRANCH)
5205 && (pseudo_opcode || (insn.opcode->value != INSN_JAL
5206 && insn.opcode->value != INSN_J))
5207 && (!verbatim || pseudo_opcode))
5209 /* User assembly code branch relax for it. */
5210 /* If fld is not NULL, it is a symbol. */
5211 /* Branch msut relax to proper pattern in user assembly code exclude
5212 J and JAL. Keep these two in original type for users which wants
5213 to keep their size be fixed. In general, assembler does not convert
5214 instruction generated by compiler. But jump instruction may be
5215 truncated in text virtual model. For workaround, compiler generate
5216 pseudo jump to fix this issue currently. */
5218 /* Get branch range type. */
5219 dwarf2_emit_insn (0);
5220 enum nds32_br_range range_type;
5223 range_type = get_range_type (fld);
5225 out = frag_var (rs_machine_dependent, NDS32_MAXCHAR,
5226 0, /* VAR is un-used. */
5227 range_type, /* SUBTYPE is used as range type. */
5228 pexp->X_add_symbol, pexp->X_add_number, 0);
5230 fragP->fr_fix += insn.opcode->isize;
5231 fragP->tc_frag_data.opcode = insn.opcode;
5232 fragP->tc_frag_data.insn = insn.insn;
5233 if (insn.opcode->isize == 4)
5234 bfd_putb32 (insn.insn, out);
5235 else if (insn.opcode->isize == 2)
5236 bfd_putb16 (insn.insn, out);
5237 fragP->tc_frag_data.flag |= NDS32_FRAG_BRANCH;
5239 /* md_convert_frag will insert relocations. */
5241 else if (!fld && !relaxing && enable_16bit && (optimize || optimize_for_space)
5242 && ((!verbatim && insn.opcode->isize == 4
5243 && nds32_convert_32_to_16 (stdoutput, insn.insn, &insn_16, NULL))
5244 || (insn.opcode->isize == 2
5245 && nds32_convert_16_to_32 (stdoutput, insn.insn, NULL))))
5247 /* Record this one is relaxable. */
5248 dwarf2_emit_insn (0);
5249 out = frag_var (rs_machine_dependent,
5250 4, /* Max size is 32-bit instruction. */
5251 0, /* VAR is un-used. */
5253 fragP->tc_frag_data.flag |= NDS32_FRAG_RELAXABLE;
5254 fragP->tc_frag_data.opcode = insn.opcode;
5255 fragP->tc_frag_data.insn = insn.insn;
5258 /* In original, we don't relax the instrucion with label on it,
5259 but this may cause some redundant nop16. Therefore, tag this
5260 relaxable instruction and relax it carefully. */
5262 fragP->tc_frag_data.flag |= NDS32_FRAG_LABEL;
5264 if (insn.opcode->isize == 4)
5265 bfd_putb16 (insn_16, out);
5266 else if (insn.opcode->isize == 2)
5267 bfd_putb16 (insn.insn, out);
5270 else if ((verbatim || !relaxing) && optimize && label)
5272 /* This instruction is with label. */
5274 out = frag_var (rs_machine_dependent, insn.opcode->isize,
5275 0, 0, NULL, 0, NULL);
5276 /* If this insturction is branch target, it is not relaxable. */
5277 fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
5278 fragP->tc_frag_data.opcode = insn.opcode;
5279 fragP->tc_frag_data.insn = insn.insn;
5280 fragP->fr_fix += insn.opcode->isize;
5281 if (insn.opcode->isize == 4)
5283 exp.X_op = O_symbol;
5284 exp.X_add_symbol = abs_section_sym;
5285 exp.X_add_number = 0;
5286 fixP = fix_new_exp (fragP, 0, 0, &exp, 0, BFD_RELOC_NDS32_LABEL);
5290 out = frag_more (insn.opcode->isize);
5292 if (insn.opcode->isize == 4)
5293 bfd_putb32 (insn.insn, out);
5294 if (insn.opcode->isize == 2)
5295 bfd_putb16 (insn.insn, out);
5297 dwarf2_emit_insn (insn.opcode->isize);
5299 /* Compiler generating code and user assembly pseudo load-store, insert
5302 fixP = nds32_elf_record_fixup_exp (fragP, str, fld, pexp, out, &insn);
5303 /* Build relaxation pattern when relaxing is enable. */
5305 nds32_elf_build_relax_relation (fixP, pexp, out, insn.opcode, fragP, fld);
5308 /* md_macro_start */
5311 nds32_macro_start (void)
5318 nds32_macro_info (void *info ATTRIBUTE_UNUSED)
5325 nds32_macro_end (void)
5329 /* GAS will call this function with one argument, an expressionS pointer, for
5330 any expression that can not be recognized. When the function is called,
5331 input_line_pointer will point to the start of the expression. */
5334 md_operand (expressionS *expressionP)
5336 if (*input_line_pointer == '#')
5338 input_line_pointer++;
5339 expression (expressionP);
5343 /* GAS will call this function for each section at the end of the assembly, to
5344 permit the CPU back end to adjust the alignment of a section. The function
5345 must take two arguments, a segT for the section and a valueT for the size of
5346 the section, and return a valueT for the rounded size. */
5349 md_section_align (segT segment, valueT size)
5351 int align = bfd_get_section_alignment (stdoutput, segment);
5353 return ((size + (1 << align) - 1) & (-1 << align));
5356 /* GAS will call this function when a symbol table lookup fails, before it
5357 creates a new symbol. Typically this would be used to supply symbols whose
5358 name or value changes dynamically, possibly in a context sensitive way.
5359 Predefined symbols with fixed values, such as register names or condition
5360 codes, are typically entered directly into the symbol table when md_begin
5361 is called. One argument is passed, a char * for the symbol. */
5364 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5370 nds32_calc_branch_offset (segT segment, fragS *fragP,
5371 long stretch ATTRIBUTE_UNUSED,
5372 relax_info_t *relax_info,
5373 enum nds32_br_range branch_range_type)
5375 struct nds32_opcode *opcode = fragP->tc_frag_data.opcode;
5376 symbolS *branch_symbol = fragP->fr_symbol;
5377 offsetT branch_offset = fragP->fr_offset;
5378 offsetT branch_target_address;
5379 offsetT branch_insn_address;
5382 if ((S_GET_SEGMENT (branch_symbol) != segment)
5383 || S_IS_WEAK (branch_symbol))
5385 /* The symbol is not in the SEGMENT. It could be far far away. */
5386 offset = 0x80000000;
5390 /* Calculate symbol-to-instruction offset. */
5391 branch_target_address = S_GET_VALUE (branch_symbol) + branch_offset;
5392 /* If the destination symbol is beyond current frag address,
5393 STRETCH will take effect to symbol's position. */
5394 if (S_GET_VALUE (branch_symbol) > fragP->fr_address)
5395 branch_target_address += stretch;
5397 branch_insn_address = fragP->fr_address + fragP->fr_fix;
5398 branch_insn_address -= opcode->isize;
5400 /* Update BRANCH_INSN_ADDRESS to relaxed position. */
5401 branch_insn_address += (relax_info->relax_code_size[branch_range_type]
5402 - relax_info->relax_branch_isize[branch_range_type]);
5404 offset = branch_target_address - branch_insn_address;
5410 static enum nds32_br_range
5411 nds32_convert_to_range_type (long offset)
5413 enum nds32_br_range range_type;
5415 if (-(0x100) <= offset && offset < 0x100) /* 256 bytes */
5416 range_type = BR_RANGE_S256;
5417 else if (-(0x4000) <= offset && offset < 0x4000) /* 16K bytes */
5418 range_type = BR_RANGE_S16K;
5419 else if (-(0x10000) <= offset && offset < 0x10000) /* 64K bytes */
5420 range_type = BR_RANGE_S64K;
5421 else if (-(0x1000000) <= offset && offset < 0x1000000) /* 16M bytes */
5422 range_type = BR_RANGE_S16M;
5424 range_type = BR_RANGE_U4G;
5429 /* Set insntruction register mask. */
5432 nds32_elf_get_set_cond (relax_info_t *relax_info, int offset, uint32_t *insn,
5433 uint32_t ori_insn, int range)
5435 nds32_cond_field_t *cond_fields = relax_info->cond_field;
5436 nds32_cond_field_t *code_seq_cond = relax_info->relax_code_condition[range];
5440 /* The instruction has conditions. Collect condition values. */
5441 while (code_seq_cond[i].bitmask != 0)
5443 if (offset == code_seq_cond[i].offset)
5445 mask = (ori_insn >> cond_fields[i].bitpos) & cond_fields[i].bitmask;
5447 if (cond_fields[i].signed_extend)
5448 mask = (mask ^ ((cond_fields[i].bitmask + 1) >> 1)) -
5449 ((cond_fields[i].bitmask + 1) >> 1);
5450 *insn |= (mask & code_seq_cond[i].bitmask) << code_seq_cond[i].bitpos;
5458 nds32_relax_branch_instructions (segT segment, fragS *fragP,
5459 long stretch ATTRIBUTE_UNUSED,
5462 enum nds32_br_range branch_range_type;
5463 struct nds32_opcode *opcode = fragP->tc_frag_data.opcode;
5465 enum nds32_br_range real_range_type;
5467 relax_info_t *relax_info;
5474 int code_seq_offset;
5476 /* Replace with gas_assert (fragP->fr_symbol != NULL); */
5477 if (fragP->fr_symbol == NULL)
5480 /* If frag_var is not enough room, the previos frag is fr_full and with
5481 opcode. The new one is rs_dependent but without opcode. */
5485 relax_info = hash_find (nds32_relax_info_hash, opcode->opcode);
5487 if (relax_info == NULL)
5491 branch_range_type = relax_info->br_range;
5493 branch_range_type = fragP->fr_subtype;
5495 offset = nds32_calc_branch_offset (segment, fragP, stretch,
5496 relax_info, branch_range_type);
5498 real_range_type = nds32_convert_to_range_type (offset);
5500 /* If actual range is equal to instruction jump range, do nothing. */
5501 if (real_range_type == branch_range_type)
5504 /* Find out proper relaxation code sequence. */
5505 for (i = BR_RANGE_S256; i < BR_RANGE_NUM; i++)
5507 if (real_range_type <= (unsigned int) i)
5510 diff = relax_info->relax_code_size[i] - opcode->isize;
5512 diff = relax_info->relax_code_size[i]
5513 - relax_info->relax_code_size[branch_range_type];
5515 /* If the instruction could be converted to 16-bits,
5516 minus the difference. */
5517 code_seq_offset = 0;
5520 code_seq_size = relax_info->relax_code_size[i];
5521 code_seq = relax_info->relax_code_seq[i];
5522 while (code_seq_offset < code_seq_size)
5525 if (insn & 0x80000000) /* 16-bits instruction. */
5529 else /* 32-bits instruction. */
5533 while (relax_info->relax_fixup[i][k].size !=0
5534 && relax_info->relax_fixup[i][k].offset < code_seq_offset)
5538 code_seq_offset += insn_size;
5542 /* Update fr_subtype to new NDS32_BR_RANGE. */
5543 fragP->fr_subtype = i;
5548 return diff + adjust;
5551 /* Adjust relaxable frag till current frag. */
5554 nds32_adjust_relaxable_frag (fragS *startP, fragS *fragP)
5557 if (startP->tc_frag_data.flag & NDS32_FRAG_RELAXED)
5562 startP->tc_frag_data.flag ^= NDS32_FRAG_RELAXED;
5566 startP = startP->fr_next;
5569 startP->fr_address += adj;
5570 if (startP == fragP)
5578 nds32_get_align (addressT address, int align)
5580 addressT mask, new_address;
5582 mask = ~((~0) << align);
5583 new_address = (address + mask) & (~mask);
5584 return (new_address - address);
5587 /* Check the prev_frag is legal. */
5589 invalid_prev_frag (fragS * fragP, fragS **prev_frag)
5592 fragS *frag_start = *prev_frag;
5597 if (frag_start->last_fr_address >= fragP->last_fr_address)
5603 fragS *frag_t = *prev_frag;
5604 while (frag_t != fragP)
5606 if (frag_t->fr_type == rs_align
5607 || frag_t->fr_type == rs_align_code
5608 || frag_t->fr_type == rs_align_test)
5610 /* Relax instruction can not walk across lable. */
5611 if (frag_t->tc_frag_data.flag & NDS32_FRAG_LABEL)
5616 /* Relax previos relaxable to align rs_align frag. */
5617 address = frag_t->fr_address + frag_t->fr_fix;
5618 addressT offset = nds32_get_align (address, (int) frag_t->fr_offset);
5621 /* If there is label on the prev_frag, check if it is aligned. */
5622 if (!((*prev_frag)->tc_frag_data.flag & NDS32_FRAG_LABEL)
5623 || (((*prev_frag)->fr_address + (*prev_frag)->fr_fix - 2 )
5625 nds32_adjust_relaxable_frag (*prev_frag, frag_t);
5630 frag_t = frag_t->fr_next;
5637 nds32_relax_frag (segT segment, fragS *fragP, long stretch ATTRIBUTE_UNUSED)
5639 /* Currently, there are two kinds of relaxation in nds32 assembler.
5641 2. relax for 32-bits to 16-bits */
5643 static fragS *prev_frag = NULL;
5646 invalid_prev_frag (fragP, &prev_frag);
5648 if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
5649 adjust = nds32_relax_branch_instructions (segment, fragP, stretch, 0);
5650 if (fragP->tc_frag_data.flag & NDS32_FRAG_LABEL)
5652 if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE
5653 && (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED) == 0)
5654 /* Here is considered relaxed case originally. But it may cause
5655 unendless loop when relaxing. Once the instruction is relaxed,
5656 it can not be undo. */
5662 /* This function returns an initial guess of the length by which a fragment
5663 must grow to hold a branch to reach its destination. Also updates
5664 fr_type/fr_subtype as necessary.
5666 It is called just before doing relaxation. Any symbol that is now undefined
5667 will not become defined. The guess for fr_var is ACTUALLY the growth beyond
5668 fr_fix. Whatever we do to grow fr_fix or fr_var contributes to our returned
5669 value. Although it may not be explicit in the frag, pretend fr_var starts
5673 md_estimate_size_before_relax (fragS *fragP, segT segment)
5675 /* Currently, there are two kinds of relaxation in nds32 assembler.
5677 2. relax for 32-bits to 16-bits */
5679 /* Save previos relaxable frag. */
5680 static fragS *prev_frag = NULL;
5683 invalid_prev_frag (fragP, &prev_frag);
5685 if (fragP->tc_frag_data.flag & NDS32_FRAG_BRANCH)
5686 adjust = nds32_relax_branch_instructions (segment, fragP, 0, 1);
5687 if (fragP->tc_frag_data.flag & NDS32_FRAG_LABEL)
5689 if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED)
5691 else if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE)
5697 /* GAS will call this for each rs_machine_dependent fragment. The instruction
5698 is completed using the data from the relaxation pass. It may also create any
5699 necessary relocations.
5701 *FRAGP has been relaxed to its final size, and now needs to have the bytes
5702 inside it modified to conform to the new size. It is called after relaxation
5705 fragP->fr_type == rs_machine_dependent.
5706 fragP->fr_subtype is the subtype of what the address relaxed to. */
5709 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragP)
5711 /* Convert branch relaxation instructions. */
5712 symbolS *branch_symbol = fragP->fr_symbol;
5713 offsetT branch_offset = fragP->fr_offset;
5714 enum nds32_br_range branch_range_type = fragP->fr_subtype;
5715 struct nds32_opcode *opcode = fragP->tc_frag_data.opcode;
5716 uint32_t origin_insn = fragP->tc_frag_data.insn;
5718 relax_info_t *relax_info;
5721 int addend ATTRIBUTE_UNUSED;
5722 offsetT branch_target_address, branch_insn_address;
5727 int code_size, insn_size, offset, fixup_size;
5731 nds32_relax_fixup_info_t fixup_info[MAX_RELAX_FIX];
5732 /* Save the 1st instruction is converted to 16 bit or not. */
5733 unsigned int branch_size;
5735 /* Replace with gas_assert (branch_symbol != NULL); */
5736 if (branch_symbol == NULL && !(fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED))
5739 /* If frag_var is not enough room, the previos frag is fr_full and with
5740 opcode. The new one is rs_dependent but without opcode. */
5744 /* Relax the insntruction. */
5745 if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED)
5748 if (fragP->tc_frag_data.opcode->isize == 2)
5750 insn_16 = fragP->tc_frag_data.insn;
5751 nds32_convert_16_to_32 (stdoutput, insn_16, &insn);
5754 insn = fragP->tc_frag_data.insn;
5756 fr_where = fragP->fr_fix - 4;
5757 fr_buffer = fragP->fr_literal + fr_where;
5758 exp_t.X_op = O_symbol;
5759 exp_t.X_add_symbol = abs_section_sym;
5760 exp_t.X_add_number = 0;
5761 fix_new_exp (fragP, fr_where, 4, &exp_t, 0,
5762 BFD_RELOC_NDS32_INSN16);
5763 number_to_chars_bigendian (fr_buffer, insn, 4);
5767 /* Branch instruction adjust and append relocations. */
5768 relax_info = hash_find (nds32_relax_info_hash, opcode->opcode);
5770 if (relax_info == NULL)
5773 backup_endian = target_big_endian;
5774 target_big_endian = 1;
5776 fr_where = fragP->fr_fix - opcode->isize;
5777 fr_buffer = fragP->fr_literal + fr_where;
5779 if ((S_GET_SEGMENT (branch_symbol) != sec)
5780 || S_IS_WEAK (branch_symbol))
5782 if (fragP->fr_offset & 3)
5783 as_warn (_("Addend to unresolved symbol is not on word boundary."));
5788 /* Calculate symbol-to-instruction offset. */
5789 branch_target_address = S_GET_VALUE (branch_symbol) + branch_offset;
5790 branch_insn_address = fragP->fr_address + fr_where;
5791 addend = (branch_target_address - branch_insn_address) >> 1;
5794 code_size = relax_info->relax_code_size[branch_range_type];
5795 code_seq = relax_info->relax_code_seq[branch_range_type];
5797 memcpy (fixup_info, relax_info->relax_fixup[branch_range_type],
5798 sizeof (fixup_info));
5803 offset = 0; /* code_seq offset */
5804 buf_offset = 0; /* fr_buffer offset */
5805 while (offset < code_size)
5808 if (insn & 0x80000000) /* 16-bits instruction. */
5810 insn = (insn >> 16) & 0xFFFF;
5813 else /* 32-bits instruction. */
5818 nds32_elf_get_set_cond (relax_info, offset, &insn,
5819 origin_insn, branch_range_type);
5821 /* Try to convert to 16-bits instruction. Currently, only the first
5822 insntruction in pattern can be converted. EX: bnez sethi ori jr,
5823 only bnez can be converted to 16 bit and ori can't. */
5825 while (fixup_info[k].size != 0
5826 && relax_info->relax_fixup[branch_range_type][k].offset < offset)
5829 md_number_to_chars (fr_buffer + buf_offset, insn, insn_size);
5830 buf_offset += insn_size;
5832 offset += insn_size;
5837 exp.X_op = O_symbol;
5839 for (i = 0; fixup_info[i].size != 0; i++)
5841 fixup_size = fixup_info[i].size;
5843 if ((fixup_info[i].ramp & NDS32_CREATE_LABEL) != 0)
5845 /* This is a reverse branch. */
5846 exp.X_add_symbol = symbol_temp_new (sec, 0, fragP->fr_next);
5847 exp.X_add_number = 0;
5849 else if ((fixup_info[i].ramp & NDS32_PTR) != 0)
5851 /* This relocation has to point to another instruction. */
5852 branch_size = fr_where + code_size - 4;
5853 exp.X_add_symbol = symbol_temp_new (sec, branch_size, fragP);
5854 exp.X_add_number = 0;
5856 else if ((fixup_info[i].ramp & NDS32_ABS) != 0)
5858 /* This is a tag relocation. */
5859 exp.X_add_symbol = abs_section_sym;
5860 exp.X_add_number = 0;
5862 else if ((fixup_info[i].ramp & NDS32_INSN16) != 0)
5866 /* This is a tag relocation. */
5867 exp.X_add_symbol = abs_section_sym;
5868 exp.X_add_number = 0;
5872 exp.X_add_symbol = branch_symbol;
5873 exp.X_add_number = branch_offset;
5876 if (fixup_info[i].r_type != 0)
5878 fixP = fix_new_exp (fragP, fr_where + fixup_info[i].offset,
5879 fixup_size, &exp, 0, fixup_info[i].r_type);
5880 fixP->fx_addnumber = fixP->fx_offset;
5884 fragP->fr_fix = fr_where + buf_offset;
5886 target_big_endian = backup_endian;
5890 /* tc_frob_file_before_fix */
5893 nds32_frob_file_before_fix (void)
5898 nds32_relaxable_section (asection *sec)
5900 return ((sec->flags & SEC_DEBUGGING) == 0
5901 && strcmp (sec->name, ".eh_frame") != 0);
5904 /* TC_FORCE_RELOCATION */
5906 nds32_force_relocation (fixS * fix)
5908 switch (fix->fx_r_type)
5910 case BFD_RELOC_NDS32_INSN16:
5911 case BFD_RELOC_NDS32_LABEL:
5912 case BFD_RELOC_NDS32_LONGCALL1:
5913 case BFD_RELOC_NDS32_LONGCALL2:
5914 case BFD_RELOC_NDS32_LONGCALL3:
5915 case BFD_RELOC_NDS32_LONGJUMP1:
5916 case BFD_RELOC_NDS32_LONGJUMP2:
5917 case BFD_RELOC_NDS32_LONGJUMP3:
5918 case BFD_RELOC_NDS32_LOADSTORE:
5919 case BFD_RELOC_NDS32_9_FIXED:
5920 case BFD_RELOC_NDS32_15_FIXED:
5921 case BFD_RELOC_NDS32_17_FIXED:
5922 case BFD_RELOC_NDS32_25_FIXED:
5923 case BFD_RELOC_NDS32_9_PCREL:
5924 case BFD_RELOC_NDS32_15_PCREL:
5925 case BFD_RELOC_NDS32_17_PCREL:
5926 case BFD_RELOC_NDS32_WORD_9_PCREL:
5927 case BFD_RELOC_NDS32_10_UPCREL:
5928 case BFD_RELOC_NDS32_25_PCREL:
5929 case BFD_RELOC_NDS32_MINUEND:
5930 case BFD_RELOC_NDS32_SUBTRAHEND:
5936 case BFD_RELOC_NDS32_DIFF_ULEB128:
5937 /* Linker should handle difference between two symbol. */
5938 return fix->fx_subsy != NULL
5939 && nds32_relaxable_section (S_GET_SEGMENT (fix->fx_addsy));
5942 as_bad ("Double word for difference between two symbols "
5943 "is not supported across relaxation.");
5948 if (generic_force_reloc (fix))
5951 return fix->fx_pcrel;
5954 /* TC_VALIDATE_FIX_SUB */
5957 nds32_validate_fix_sub (fixS *fix, segT add_symbol_segment)
5959 segT sub_symbol_segment;
5961 /* This code is referred from Xtensa. Check their implementation for
5964 /* Make sure both symbols are in the same segment, and that segment is
5965 "normal" and relaxable. */
5966 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5967 return (sub_symbol_segment == add_symbol_segment
5968 && add_symbol_segment != undefined_section);
5972 md_number_to_chars (char *buf, valueT val, int n)
5974 if (target_big_endian)
5975 number_to_chars_bigendian (buf, val, n);
5977 number_to_chars_littleendian (buf, val, n);
5980 /* Equal to MAX_PRECISION in atof-ieee.c. */
5981 #define MAX_LITTLENUMS 6
5983 /* This function is called to convert an ASCII string into a floating point
5984 value in format used by the CPU. */
5987 md_atof (int type, char *litP, int *sizeP)
5991 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6010 return _("Bad call to md_atof()");
6013 t = atof_ieee (input_line_pointer, type, words);
6015 input_line_pointer = t;
6016 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6018 if (target_big_endian)
6020 for (i = 0; i < prec; i++)
6022 md_number_to_chars (litP, (valueT) words[i],
6023 sizeof (LITTLENUM_TYPE));
6024 litP += sizeof (LITTLENUM_TYPE);
6029 for (i = prec - 1; i >= 0; i--)
6031 md_number_to_chars (litP, (valueT) words[i],
6032 sizeof (LITTLENUM_TYPE));
6033 litP += sizeof (LITTLENUM_TYPE);
6040 /* md_elf_section_change_hook */
6043 nds32_elf_section_change_hook (void)
6050 nds32_cleanup (void)
6054 /* This function is used to scan leb128 subtraction expressions,
6055 and insert fixups for them.
6057 e.g., .leb128 .L1 - .L0
6059 These expressions are heavily used in debug information or
6060 exception tables. Because relaxation will change code size,
6061 we must resolve them in link time. */
6064 nds32_insert_leb128_fixes (bfd *abfd ATTRIBUTE_UNUSED,
6065 asection *sec, void *xxx ATTRIBUTE_UNUSED)
6067 segment_info_type *seginfo = seg_info (sec);
6070 subseg_set (sec, 0);
6072 for (fragP = seginfo->frchainP->frch_root;
6073 fragP; fragP = fragP->fr_next)
6077 /* Only unsigned leb128 can be handle. */
6078 if (fragP->fr_type != rs_leb128 || fragP->fr_subtype != 0
6079 || fragP->fr_symbol == NULL)
6082 exp = symbol_get_value_expression (fragP->fr_symbol);
6084 if (exp->X_op != O_subtract)
6087 fix_new_exp (fragP, fragP->fr_fix, 0,
6088 exp, 0, BFD_RELOC_NDS32_DIFF_ULEB128);
6093 nds32_insert_relax_entry (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
6094 void *xxx ATTRIBUTE_UNUSED)
6096 segment_info_type *seginfo;
6102 seginfo = seg_info (sec);
6103 if (!seginfo || !symbol_rootP || !subseg_text_p (sec) || sec->size == 0)
6105 /* If there is no relocation and relax is disabled, it is not necessary to
6106 insert R_NDS32_RELAX_ENTRY for linker do EX9 or IFC optimization. */
6107 for (fixp = seginfo->fix_root; fixp; fixp = fixp->fx_next)
6110 if (!fixp && !enable_relax_ex9 && !verbatim)
6113 subseg_change (sec, 0);
6115 /* Set RELAX_ENTRY flags for linker. */
6116 fragP = seginfo->frchainP->frch_root;
6117 exp.X_op = O_symbol;
6118 exp.X_add_symbol = section_symbol (sec);
6119 exp.X_add_number = 0;
6120 if (!enable_relax_relocs)
6121 exp.X_add_number |= R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG;
6124 /* These flags are only enabled when global relax is enabled.
6125 Maybe we can check DISABLE_RELAX_FLAG at linke-time,
6126 so we set them anyway. */
6127 if (enable_relax_ex9)
6128 exp.X_add_number |= R_NDS32_RELAX_ENTRY_EX9_FLAG;
6129 if (enable_relax_ifc)
6130 exp.X_add_number |= R_NDS32_RELAX_ENTRY_IFC_FLAG;
6132 exp.X_add_number |= R_NDS32_RELAX_ENTRY_VERBATIM_FLAG;
6135 exp.X_add_number |= R_NDS32_RELAX_ENTRY_OPTIMIZE_FLAG;
6136 if (optimize_for_space)
6137 exp.X_add_number |= R_NDS32_RELAX_ENTRY_OPTIMIZE_FOR_SPACE_FLAG;
6139 fixP = fix_new_exp (fragP, 0, 0, &exp, 0, BFD_RELOC_NDS32_RELAX_ENTRY);
6140 fixP->fx_no_overflow = 1;
6143 /* Analysis relax hint and insert suitable relocation pattern. */
6146 nds32_elf_analysis_relax_hint (void)
6148 hash_traverse (nds32_hint_hash, nds32_elf_append_relax_relocs);
6154 nds32_elf_analysis_relax_hint ();
6155 bfd_map_over_sections (stdoutput, nds32_insert_leb128_fixes, NULL);
6158 /* Implement md_allow_local_subtract. */
6161 nds32_allow_local_subtract (expressionS *expr_l ATTRIBUTE_UNUSED,
6162 expressionS *expr_r ATTRIBUTE_UNUSED,
6163 segT sec ATTRIBUTE_UNUSED)
6165 /* Don't allow any subtraction, because relax may change the code. */
6169 /* Sort relocation by address.
6171 We didn't use qsort () in stdlib, because quick-sort is not a stable
6172 sorting algorithm. Relocations at the same address (r_offset) must keep
6173 their relative order. For example, RELAX_ENTRY must be the very first
6176 Currently, this function implements insertion-sort. */
6179 compar_relent (const void *lhs, const void *rhs)
6181 const arelent **l = (const arelent **) lhs;
6182 const arelent **r = (const arelent **) rhs;
6184 if ((*l)->address > (*r)->address)
6186 else if ((*l)->address == (*r)->address)
6192 /* SET_SECTION_RELOCS ()
6194 Although this macro is originally used to set a relocation for each section,
6195 we use it to sort relocations in the same section by the address of the
6199 nds32_set_section_relocs (asection *sec, arelent ** relocs ATTRIBUTE_UNUSED,
6200 unsigned int n ATTRIBUTE_UNUSED)
6202 bfd *abfd ATTRIBUTE_UNUSED = sec->owner;
6203 if (bfd_get_section_flags (abfd, sec) & (flagword) SEC_RELOC)
6204 nds32_insertion_sort (sec->orelocation, sec->reloc_count,
6205 sizeof (arelent**), compar_relent);
6209 nds32_pcrel_from_section (fixS *fixP, segT sec ATTRIBUTE_UNUSED)
6211 if (fixP->fx_addsy == NULL || !S_IS_DEFINED (fixP->fx_addsy)
6212 || S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy))
6214 /* Let linker resolve undefined symbols. */
6218 return fixP->fx_frag->fr_address + fixP->fx_where;
6221 /* md_post_relax_hook ()
6222 Insert relax entry relocation into sections. */
6225 nds32_post_relax_hook (void)
6227 bfd_map_over_sections (stdoutput, nds32_insert_relax_entry, NULL);
6230 /* tc_fix_adjustable ()
6232 Return whether this symbol (fixup) can be replaced with
6236 nds32_fix_adjustable (fixS *fixP)
6238 switch (fixP->fx_r_type)
6240 case BFD_RELOC_NDS32_WORD_9_PCREL:
6241 case BFD_RELOC_NDS32_9_PCREL:
6242 case BFD_RELOC_NDS32_15_PCREL:
6243 case BFD_RELOC_NDS32_17_PCREL:
6244 case BFD_RELOC_NDS32_25_PCREL:
6245 case BFD_RELOC_NDS32_HI20:
6246 case BFD_RELOC_NDS32_LO12S0:
6250 case BFD_RELOC_NDS32_PTR:
6251 case BFD_RELOC_NDS32_LONGCALL4:
6252 case BFD_RELOC_NDS32_LONGCALL5:
6253 case BFD_RELOC_NDS32_LONGCALL6:
6254 case BFD_RELOC_NDS32_LONGJUMP4:
6255 case BFD_RELOC_NDS32_LONGJUMP5:
6256 case BFD_RELOC_NDS32_LONGJUMP6:
6257 case BFD_RELOC_NDS32_LONGJUMP7:
6264 /* elf_tc_final_processing */
6267 elf_nds32_final_processing (void)
6269 /* An FPU_COM instruction is found without previous non-FPU_COM
6272 && !(nds32_elf_flags & (E_NDS32_HAS_FPU_INST | E_NDS32_HAS_FPU_DP_INST)))
6274 /* Since only FPU_COM instructions are used and no other FPU instructions
6275 are used. The nds32_elf_flags will be decided by the enabled options
6276 by command line or default configuration. */
6277 if (nds32_fpu_dp_ext || nds32_fpu_sp_ext)
6279 nds32_elf_flags |= nds32_fpu_dp_ext ? E_NDS32_HAS_FPU_DP_INST : 0;
6280 nds32_elf_flags |= nds32_fpu_sp_ext ? E_NDS32_HAS_FPU_INST : 0;
6284 /* Should never here. */
6285 as_bad (_("Used FPU instructions requires enabling FPU extension"));
6289 if (nds32_elf_flags & (E_NDS32_HAS_FPU_INST | E_NDS32_HAS_FPU_DP_INST))
6291 /* Single/double FPU has been used, set FPU register config. */
6292 /* We did not check the actual number of register used. We may
6293 want to do it while assemble. */
6294 nds32_elf_flags &= ~E_NDS32_FPU_REG_CONF;
6295 nds32_elf_flags |= (nds32_freg << E_NDS32_FPU_REG_CONF_SHIFT);
6299 nds32_elf_flags |= E_NDS32_HAS_PIC;
6302 nds32_elf_flags |= E_NDS32_HAS_REDUCED_REGS;
6304 nds32_elf_flags |= (E_NDS32_ELF_VER_1_4 | nds32_abi);
6305 elf_elfheader (stdoutput)->e_flags |= nds32_elf_flags;
6308 /* Implement md_apply_fix. Apply the fix-up or tranform the fix-up for
6309 later relocation generation. */
6312 nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
6314 char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
6315 bfd_vma value = *valP;
6317 if (fixP->fx_r_type < BFD_RELOC_UNUSED
6318 && fixP->fx_r_type > BFD_RELOC_NONE
6319 && fixP->fx_r_type != BFD_RELOC_NDS32_DIFF_ULEB128)
6321 /* In our old nds32 binutils, it must convert relocations which is
6322 generated by CGEN. However, it does not have to consider this anymore.
6323 In current, it only deal with data relocations which enum
6324 is smaller than BFD_RELOC_NONE and BFD_RELOC_NDS32_DIFF_ULEB128.
6325 It is believed that we can construct a better mechanism to
6326 deal with the whole relocation issue in nds32 target
6327 without using CGEN. */
6328 fixP->fx_addnumber = value;
6329 fixP->tc_fix_data = NULL;
6331 /* Tranform specific relocations here for later relocation generation.
6332 Tag data here for ex9 relaxtion and tag tls data for linker. */
6333 switch (fixP->fx_r_type)
6335 case BFD_RELOC_NDS32_DATA:
6336 if (!enable_relax_ex9)
6339 case BFD_RELOC_NDS32_TPOFF:
6340 case BFD_RELOC_NDS32_TLS_LE_HI20:
6341 case BFD_RELOC_NDS32_TLS_LE_LO12:
6342 case BFD_RELOC_NDS32_TLS_LE_ADD:
6343 case BFD_RELOC_NDS32_TLS_LE_LS:
6344 case BFD_RELOC_NDS32_GOTTPOFF:
6345 case BFD_RELOC_NDS32_TLS_IE_HI20:
6346 case BFD_RELOC_NDS32_TLS_IE_LO12S2:
6347 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6355 if (fixP->fx_addsy == (symbolS *) NULL)
6358 if (fixP->fx_subsy != (symbolS *) NULL)
6360 /* HOW DIFF RELOCATION WORKS.
6362 First of all, this relocation is used to calculate the distance
6363 between two symbols in the SAME section. It is used for jump-
6364 table, debug information, exception table, et al. Therefore,
6365 it is a unsigned positive value. It is NOT used for general-
6368 Consider this example, the distance between .LEND and .LBEGIN
6369 is stored at the address of foo.
6371 ---- >8 ---- >8 ---- >8 ---- >8 ----
6374 .word .LBEGIN - .LEND
6384 ---- 8< ---- 8< ---- 8< ---- 8< ----
6386 We use a single relocation entry for this expression.
6387 * The initial distance value is stored direcly in that location
6388 specified by r_offset (i.e., foo in this example.)
6389 * The begin of the region, i.e., .LBEGIN, is specified by
6390 r_info/R_SYM and r_addend, e.g., .text + 0x32.
6391 * The end of region, i.e., .LEND, is represented by
6392 .LBEGIN + distance instead of .LEND, so we only need
6393 a single relocation entry instead of two.
6395 When an instruction is relaxed, we adjust the relocation entry
6396 depending on where the instruction locates. There are three
6397 cases, before, after and between the region.
6398 * between: Distance value is read from r_offset, adjusted and
6399 written back into r_offset.
6400 * before: Only r_addend is adjust.
6401 * after: We don't care about it.
6403 Hereby, there are some limitation.
6405 `(.LEND - 1) - .LBEGIN' and `(.LEND - .LBEGIN) - 1'
6406 are semantically different, and we cannot handle latter case
6409 The latter expression means subtracting 1 from the distance
6410 between .LEND and .LBEGIN. And the former expression means
6411 the distance between (.LEND - 1) and .LBEGIN.
6413 The nuance affects whether to adjust distance value when relax
6414 an instruction. In another words, whether the instruction
6415 locates in the region. Because we use a single relocation entry,
6416 there is no field left for .LEND and the subtrahend.
6418 Since GCC-4.5, GCC may produce debug information in such expression
6420 in order to describe register clobbering during an function-call.
6425 Check http://gcc.gnu.org/ml/gcc-patches/2009-06/msg01317.html
6428 value -= S_GET_VALUE (fixP->fx_subsy);
6430 fixP->fx_subsy = NULL;
6431 fixP->fx_offset -= value;
6433 switch (fixP->fx_r_type)
6436 fixP->fx_r_type = BFD_RELOC_NDS32_DIFF8;
6437 md_number_to_chars (where, value, 1);
6440 fixP->fx_r_type = BFD_RELOC_NDS32_DIFF16;
6441 md_number_to_chars (where, value, 2);
6444 fixP->fx_r_type = BFD_RELOC_NDS32_DIFF32;
6445 md_number_to_chars (where, value, 4);
6447 case BFD_RELOC_NDS32_DIFF_ULEB128:
6448 /* cvt_frag_to_fill () has called output_leb128 () for us. */
6451 as_bad_where (fixP->fx_file, fixP->fx_line,
6452 _("expression too complex"));
6456 else if (fixP->fx_done)
6458 /* We're finished with this fixup. Install it because
6459 bfd_install_relocation won't be called to do it. */
6460 switch (fixP->fx_r_type)
6463 md_number_to_chars (where, value, 1);
6466 md_number_to_chars (where, value, 2);
6469 md_number_to_chars (where, value, 4);
6472 md_number_to_chars (where, value, 8);
6474 as_bad_where (fixP->fx_file, fixP->fx_line,
6475 _("Internal error: Unknown fixup type %d (`%s')"),
6477 bfd_get_reloc_code_name (fixP->fx_r_type));
6483 /* Implement tc_gen_reloc. Generate ELF relocation for a fix-up. */
6486 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
6489 bfd_reloc_code_real_type code;
6491 reloc = (arelent *) xmalloc (sizeof (arelent));
6493 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6494 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
6495 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
6497 code = fixP->fx_r_type;
6499 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6500 if (reloc->howto == (reloc_howto_type *) NULL)
6502 as_bad_where (fixP->fx_file, fixP->fx_line,
6503 _("internal error: can't export reloc type %d (`%s')"),
6504 fixP->fx_r_type, bfd_get_reloc_code_name (code));
6508 /* Add relocation handling here. */
6510 switch (fixP->fx_r_type)
6513 /* In general, addend of a relocation is the offset to the
6514 associated symbol. */
6515 reloc->addend = fixP->fx_offset;
6518 case BFD_RELOC_NDS32_DATA:
6519 /* Prevent linker from optimizing data in text sections.
6520 For example, jump table. */
6521 reloc->addend = fixP->fx_size;
6528 struct suffix_name suffix_table[] =
6530 {"GOTOFF", BFD_RELOC_NDS32_GOTOFF, 1},
6531 {"GOT", BFD_RELOC_NDS32_GOT20, 1},
6532 {"TPOFF", BFD_RELOC_NDS32_TPOFF, 0},
6533 {"PLT", BFD_RELOC_NDS32_25_PLTREL, 1},
6534 {"GOTTPOFF", BFD_RELOC_NDS32_GOTTPOFF, 0}
6537 /* Implement md_parse_name. */
6540 nds32_parse_name (char const *name, expressionS *exprP,
6541 enum expr_mode mode ATTRIBUTE_UNUSED,
6542 char *nextcharP ATTRIBUTE_UNUSED)
6544 exprP->X_op_symbol = NULL;
6545 exprP->X_md = BFD_RELOC_UNUSED;
6547 exprP->X_add_symbol = symbol_find_or_make (name);
6548 exprP->X_op = O_symbol;
6549 exprP->X_add_number = 0;
6551 if (strcmp (name, GOT_NAME) == 0 && *nextcharP != '@')
6553 /* Set for _GOT_OFFSET_TABLE_. */
6554 exprP->X_md = BFD_RELOC_NDS32_GOTPC20;
6556 else if (*nextcharP == '@')
6560 for (i = 0; i < ARRAY_SIZE (suffix_table); i++)
6562 next = input_line_pointer + 1 + strlen(suffix_table[i].suffix);
6563 if (strncasecmp (input_line_pointer + 1, suffix_table[i].suffix,
6564 strlen (suffix_table[i].suffix)) == 0
6565 && !is_part_of_name (*next))
6567 if (!nds32_pic && suffix_table[i].pic)
6568 as_bad (_("need PIC qualifier with symbol."));
6569 exprP->X_md = suffix_table[i].reloc;
6570 *input_line_pointer = *nextcharP;
6571 input_line_pointer = next;
6572 *nextcharP = *input_line_pointer;
6573 *input_line_pointer = '\0';
6581 /* Implement tc_regname_to_dw2regnum. */
6584 tc_nds32_regname_to_dw2regnum (char *regname)
6586 struct nds32_keyword *sym = hash_find (nds32_gprs_hash, regname);
6595 tc_nds32_frame_initial_instructions (void)
6598 /* Default cfa is register-31/sp. */
6599 cfi_add_CFA_def_cfa (31, 0);
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