1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2017 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
26 #include "opcode/msp430.h"
27 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
29 #include "elf/msp430.h"
30 #include "libiberty.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax;
70 int msp430_enable_polys;
72 /* GCC uses the some condition codes which we'll
73 implement as new polymorph instructions.
75 COND EXPL SHORT JUMP LONG JUMP
76 ===============================================
77 eq == jeq jne +4; br lab
78 ne != jne jeq +4; br lab
80 ltn honours no-overflow flag
81 ltn < jn jn +2; jmp +4; br lab
83 lt < jl jge +4; br lab
84 ltu < jlo lhs +4; br lab
90 ge >= jge jl +4; br lab
91 geu >= jhs jlo +4; br lab
92 ===============================================
94 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
95 beq,bne,blt,bltn,bltu,bge,bgeu
96 'u' means unsigned compares
98 Also, we add 'jump' instruction:
99 jump UNCOND -> jmp br lab
101 They will have fmt == 4, and insn_opnumb == number of instruction. */
106 int index; /* Corresponding insn_opnumb. */
107 int sop; /* Opcode if jump length is short. */
108 long lpos; /* Label position. */
109 long lop0; /* Opcode 1 _word_ (16 bits). */
110 long lop1; /* Opcode second word. */
111 long lop2; /* Opcode third word. */
114 #define MSP430_RLC(n,i,sop,o1) \
115 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
117 static struct rcodes_s msp430_rcodes[] =
119 MSP430_RLC (beq, 0, 0x2400, 0x2000),
120 MSP430_RLC (bne, 1, 0x2000, 0x2400),
121 MSP430_RLC (blt, 2, 0x3800, 0x3400),
122 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
123 MSP430_RLC (bge, 4, 0x3400, 0x3800),
124 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
125 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
126 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
131 #define MSP430_RLC(n,i,sop,o1) \
132 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
134 static struct rcodes_s msp430x_rcodes[] =
136 MSP430_RLC (beq, 0, 0x2400, 0x2000),
137 MSP430_RLC (bne, 1, 0x2000, 0x2400),
138 MSP430_RLC (blt, 2, 0x3800, 0x3400),
139 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
140 MSP430_RLC (bge, 4, 0x3400, 0x3800),
141 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
142 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
143 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
148 /* More difficult than above and they have format 5.
151 =================================================================
152 gt > jeq +2; jge label jeq +6; jl +4; br label
153 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
154 leu <= jeq label; jlo label jeq +2; jhs +4; br label
155 le <= jeq label; jl label jeq +2; jge +4; br label
156 ================================================================= */
161 int index; /* Corresponding insn_opnumb. */
162 int tlab; /* Number of labels in short mode. */
163 int op0; /* Opcode for first word of short jump. */
164 int op1; /* Opcode for second word of short jump. */
165 int lop0; /* Opcodes for long jump mode. */
170 static struct hcodes_s msp430_hcodes[] =
172 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
173 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
174 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
175 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
179 static struct hcodes_s msp430x_hcodes[] =
181 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
182 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
183 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
184 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
188 const char comment_chars[] = ";";
189 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = "{";
191 const char EXP_CHARS[] = "eE";
192 const char FLT_CHARS[] = "dD";
194 /* Handle long expressions. */
195 extern LITTLENUM_TYPE generic_bignum[];
197 static struct hash_control *msp430_hash;
200 #define STATE_UNCOND_BRANCH 1 /* jump */
201 #define STATE_NOOV_BRANCH 3 /* bltn */
202 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
203 #define STATE_EMUL_BRANCH 4
212 #define STATE_BITS10 1 /* wild guess. short jump */
213 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
214 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
216 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
217 #define RELAX_STATE(s) ((s) & 3)
218 #define RELAX_LEN(s) ((s) >> 2)
219 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
221 relax_typeS md_relax_table[] =
229 /* Unconditional jump. */
231 {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
232 {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */
233 {1, 1, CUBL, 0}, /* state undef */
235 /* Simple branches. */
237 {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
238 {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */
241 /* blt no overflow branch. */
243 {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
244 {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */
247 /* Emulated branches. */
249 {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
250 {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */
255 #define MAX_OP_LEN 4096
264 static enum msp_isa selected_isa = MSP_ISA_430Xv2;
266 static inline bfd_boolean
267 target_is_430x (void)
269 return selected_isa >= MSP_ISA_430X;
272 static inline bfd_boolean
273 target_is_430xv2 (void)
275 return selected_isa == MSP_ISA_430Xv2;
278 /* Generate an absolute 16-bit relocation.
279 For the 430X we generate a relocation without linker range checking
280 if the value is being used in an extended (ie 20-bit) instruction,
281 otherwise if have a shifted expression we use a HI reloc.
282 For the 430 we generate a relocation without assembler range checking
283 if we are handling an immediate value or a byte-width instruction. */
285 #undef CHECK_RELOC_MSP430
286 #define CHECK_RELOC_MSP430(OP) \
290 : ((OP).vshift == 1) \
291 ? BFD_RELOC_MSP430_ABS_HI16 \
292 : BFD_RELOC_MSP430X_ABS16) \
293 : ((imm_op || byte_op) \
294 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
296 /* Generate a 16-bit pc-relative relocation.
297 For the 430X we generate a relocation without linker range checking.
298 For the 430 we generate a relocation without assembler range checking
299 if we are handling an immediate value or a byte-width instruction. */
300 #undef CHECK_RELOC_MSP430_PCREL
301 #define CHECK_RELOC_MSP430_PCREL \
303 ? BFD_RELOC_MSP430X_PCR16 \
304 : (imm_op || byte_op) \
305 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
307 /* Profiling capability:
308 It is a performance hit to use gcc's profiling approach for this tiny target.
309 Even more -- jtag hardware facility does not perform any profiling functions.
310 However we've got gdb's built-in simulator where we can do anything.
311 Therefore my suggestion is:
313 We define new section ".profiler" which holds all profiling information.
314 We define new pseudo operation .profiler which will instruct assembler to
315 add new profile entry to the object file. Profile should take place at the
320 .profiler flags,function_to_profile [, cycle_corrector, extra]
322 where 'flags' is a combination of the following chars:
325 i - function is in Init section
326 f - function is in Fini section
328 c - libC standard call
329 d - stack value Demand (saved at run-time in simulator)
330 I - Interrupt service routine
335 j - long Jump/ sjlj unwind
336 a - an Arbitrary code fragment
337 t - exTra parameter saved (constant value like frame size)
338 '""' optional: "sil" == sil
340 function_to_profile - function's address
341 cycle_corrector - a value which should be added to the cycle
342 counter, zero if omitted
343 extra - some extra parameter, zero if omitted.
346 ------------------------------
350 .LFrameOffset_fxx=0x08
351 .profiler "scdP", fxx ; function entry.
352 ; we also demand stack value to be displayed
357 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
358 ; (this is a prologue end)
359 ; note, that spare var filled with the frame size
362 .profiler cdE,fxx ; check stack
367 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
368 ret ; cause 'ret' insn takes 3 cycles
369 -------------------------------
371 This profiling approach does not produce any overhead and
373 So, even profiled code can be uploaded to the MCU. */
374 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
375 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
376 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
377 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
378 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
379 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
380 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
381 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
382 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
383 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
384 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
385 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
386 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
387 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
388 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
389 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
402 for (; x; x = x >> 1)
409 /* Parse ordinary expression. */
412 parse_exp (char * s, expressionS * op)
414 input_line_pointer = s;
416 if (op->X_op == O_absent)
417 as_bad (_("missing operand"));
418 /* Our caller is likely to check that the entire expression was parsed.
419 If we have found a hex constant with an 'h' suffix, ilp will be left
420 pointing at the 'h', so skip it here. */
421 if (input_line_pointer != NULL
422 && op->X_op == O_constant
423 && (*input_line_pointer == 'h' || *input_line_pointer == 'H'))
424 ++ input_line_pointer;
425 return input_line_pointer;
429 /* Delete spaces from s: X ( r 1 2) => X(r12). */
432 del_spaces (char * s)
440 while (ISSPACE (*m) && *m)
442 memmove (s, m, strlen (m) + 1);
450 skip_space (char * s)
457 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
460 extract_operand (char * from, char * to, int limit)
464 /* Drop leading whitespace. */
465 from = skip_space (from);
467 while (size < limit && *from)
469 *(to + size) = *from;
470 if (*from == ',' || *from == ';' || *from == '\n')
485 msp430_profiler (int dummy ATTRIBUTE_UNUSED)
502 s = input_line_pointer;
503 end = input_line_pointer;
505 while (*end && *end != '\n')
508 while (*s && *s != '\n')
519 as_bad (_(".profiler pseudo requires at least two operands."));
520 input_line_pointer = end;
524 input_line_pointer = extract_operand (input_line_pointer, flags, 32);
533 p_flags |= MSP430_PROFILER_FLAG_FRAGMENT;
536 p_flags |= MSP430_PROFILER_FLAG_JUMP;
539 p_flags |= MSP430_PROFILER_FLAG_PROLSTART;
542 p_flags |= MSP430_PROFILER_FLAG_PROLEND;
545 p_flags |= MSP430_PROFILER_FLAG_EPISTART;
548 p_flags |= MSP430_PROFILER_FLAG_EPIEND;
551 p_flags |= MSP430_PROFILER_FLAG_ENTRY;
554 p_flags |= MSP430_PROFILER_FLAG_EXIT;
557 p_flags |= MSP430_PROFILER_FLAG_INITSECT;
560 p_flags |= MSP430_PROFILER_FLAG_FINISECT;
563 p_flags |= MSP430_PROFILER_FLAG_LIBCALL;
566 p_flags |= MSP430_PROFILER_FLAG_STDCALL;
569 p_flags |= MSP430_PROFILER_FLAG_STACKDMD;
572 p_flags |= MSP430_PROFILER_FLAG_ISR;
575 p_flags |= MSP430_PROFILER_FLAG_EXTRA;
578 as_warn (_("unknown profiling flag - ignored."));
585 && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY
586 | MSP430_PROFILER_FLAG_EXIT))
587 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART
588 | MSP430_PROFILER_FLAG_PROLEND
589 | MSP430_PROFILER_FLAG_EPISTART
590 | MSP430_PROFILER_FLAG_EPIEND))
591 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT
592 | MSP430_PROFILER_FLAG_FINISECT))))
594 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
595 input_line_pointer = end;
599 /* Generate temp symbol which denotes current location. */
600 if (now_seg == absolute_section) /* Paranoia ? */
602 exp1.X_op = O_constant;
603 exp1.X_add_number = abs_section_offset;
604 as_warn (_("profiling in absolute section?"));
608 exp1.X_op = O_symbol;
609 exp1.X_add_symbol = symbol_temp_new_now ();
610 exp1.X_add_number = 0;
613 /* Generate a symbol which holds flags value. */
614 exp.X_op = O_constant;
615 exp.X_add_number = p_flags;
617 /* Save current section. */
621 /* Now go to .profiler section. */
622 obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0, 0);
625 emit_expr (& exp, 2);
627 /* Save label value. */
628 emit_expr (& exp1, 2);
632 /* Now get profiling info. */
633 halt = extract_operand (input_line_pointer, str, 1024);
634 /* Process like ".word xxx" directive. */
635 (void) parse_exp (str, & exp);
636 emit_expr (& exp, 2);
637 input_line_pointer = halt;
640 /* Fill the rest with zeros. */
641 exp.X_op = O_constant;
642 exp.X_add_number = 0;
644 emit_expr (& exp, 2);
646 /* Return to current section. */
647 subseg_set (seg, subseg);
651 extract_word (char * from, char * to, int limit)
656 /* Drop leading whitespace. */
657 from = skip_space (from);
660 /* Find the op code end. */
661 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
663 to[size++] = *op_end++;
664 if (size + 1 >= limit)
672 #define OPTION_MMCU 'm'
673 #define OPTION_RELAX 'Q'
674 #define OPTION_POLYMORPHS 'P'
675 #define OPTION_LARGE 'l'
676 static bfd_boolean large_model = FALSE;
677 #define OPTION_NO_INTR_NOPS 'N'
678 #define OPTION_INTR_NOPS 'n'
679 static bfd_boolean gen_interrupt_nops = FALSE;
680 #define OPTION_WARN_INTR_NOPS 'y'
681 #define OPTION_NO_WARN_INTR_NOPS 'Y'
682 static bfd_boolean warn_interrupt_nops = TRUE;
683 #define OPTION_MCPU 'c'
684 #define OPTION_MOVE_DATA 'd'
685 static bfd_boolean move_data = FALSE;
686 #define OPTION_DATA_REGION 'r'
687 static bfd_boolean upper_data_region_in_use = FALSE;
691 OPTION_SILICON_ERRATA = OPTION_MD_BASE,
692 OPTION_SILICON_ERRATA_WARN,
695 static unsigned int silicon_errata_fix = 0;
696 static unsigned int silicon_errata_warn = 0;
697 #define SILICON_ERRATA_CPU4 (1 << 0)
698 #define SILICON_ERRATA_CPU8 (1 << 1)
699 #define SILICON_ERRATA_CPU11 (1 << 2)
700 #define SILICON_ERRATA_CPU12 (1 << 3)
701 #define SILICON_ERRATA_CPU13 (1 << 4)
702 #define SILICON_ERRATA_CPU19 (1 << 5)
705 msp430_set_arch (int option)
707 char str[32]; /* 32 for good measure. */
709 input_line_pointer = extract_word (input_line_pointer, str, 32);
711 md_parse_option (option, str);
712 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
713 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
716 /* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
717 Keep these two structures in sync.
718 The data in this structure has been extracted from version 1.194 of the
719 devices.csv file released by TI in September 2016. */
721 struct msp430_mcu_data
724 unsigned int revision; /* 0=> MSP430, 1=>MSP430X, 2=> MSP430Xv2. */
725 unsigned int hwmpy; /* 0=>none, 1=>16-bit, 2=>16-bit w/sign extend, 4=>32-bit, 8=> 32-bit (5xx). */
729 { "cc430f5123",2,8 },
730 { "cc430f5125",2,8 },
731 { "cc430f5133",2,8 },
732 { "cc430f5135",2,8 },
733 { "cc430f5137",2,8 },
734 { "cc430f5143",2,8 },
735 { "cc430f5145",2,8 },
736 { "cc430f5147",2,8 },
737 { "cc430f6125",2,8 },
738 { "cc430f6126",2,8 },
739 { "cc430f6127",2,8 },
740 { "cc430f6135",2,8 },
741 { "cc430f6137",2,8 },
742 { "cc430f6143",2,8 },
743 { "cc430f6145",2,8 },
744 { "cc430f6147",2,8 },
745 { "msp430afe221",0,2 },
746 { "msp430afe222",0,2 },
747 { "msp430afe223",0,2 },
748 { "msp430afe231",0,2 },
749 { "msp430afe232",0,2 },
750 { "msp430afe233",0,2 },
751 { "msp430afe251",0,2 },
752 { "msp430afe252",0,2 },
753 { "msp430afe253",0,2 },
754 { "msp430bt5190",2,8 },
755 { "msp430c091",0,0 },
756 { "msp430c092",0,0 },
757 { "msp430c111",0,0 },
758 { "msp430c1111",0,0 },
759 { "msp430c112",0,0 },
760 { "msp430c1121",0,0 },
761 { "msp430c1331",0,0 },
762 { "msp430c1351",0,0 },
763 { "msp430c311s",0,0 },
764 { "msp430c312",0,0 },
765 { "msp430c313",0,0 },
766 { "msp430c314",0,0 },
767 { "msp430c315",0,0 },
768 { "msp430c323",0,0 },
769 { "msp430c325",0,0 },
770 { "msp430c336",0,1 },
771 { "msp430c337",0,1 },
772 { "msp430c412",0,0 },
773 { "msp430c413",0,0 },
774 { "msp430cg4616",1,1 },
775 { "msp430cg4617",1,1 },
776 { "msp430cg4618",1,1 },
777 { "msp430cg4619",1,1 },
778 { "msp430e112",0,0 },
779 { "msp430e313",0,0 },
780 { "msp430e315",0,0 },
781 { "msp430e325",0,0 },
782 { "msp430e337",0,1 },
783 { "msp430f110",0,0 },
784 { "msp430f1101",0,0 },
785 { "msp430f1101a",0,0 },
786 { "msp430f1111",0,0 },
787 { "msp430f1111a",0,0 },
788 { "msp430f112",0,0 },
789 { "msp430f1121",0,0 },
790 { "msp430f1121a",0,0 },
791 { "msp430f1122",0,0 },
792 { "msp430f1132",0,0 },
793 { "msp430f122",0,0 },
794 { "msp430f1222",0,0 },
795 { "msp430f123",0,0 },
796 { "msp430f1232",0,0 },
797 { "msp430f133",0,0 },
798 { "msp430f135",0,0 },
799 { "msp430f147",0,1 },
800 { "msp430f1471",0,1 },
801 { "msp430f148",0,1 },
802 { "msp430f1481",0,1 },
803 { "msp430f149",0,1 },
804 { "msp430f1491",0,1 },
805 { "msp430f155",0,0 },
806 { "msp430f156",0,0 },
807 { "msp430f157",0,0 },
808 { "msp430f1610",0,1 },
809 { "msp430f1611",0,1 },
810 { "msp430f1612",0,1 },
811 { "msp430f167",0,1 },
812 { "msp430f168",0,1 },
813 { "msp430f169",0,1 },
814 { "msp430f2001",0,0 },
815 { "msp430f2002",0,0 },
816 { "msp430f2003",0,0 },
817 { "msp430f2011",0,0 },
818 { "msp430f2012",0,0 },
819 { "msp430f2013",0,0 },
820 { "msp430f2101",0,0 },
821 { "msp430f2111",0,0 },
822 { "msp430f2112",0,0 },
823 { "msp430f2121",0,0 },
824 { "msp430f2122",0,0 },
825 { "msp430f2131",0,0 },
826 { "msp430f2132",0,0 },
827 { "msp430f2232",0,0 },
828 { "msp430f2234",0,0 },
829 { "msp430f2252",0,0 },
830 { "msp430f2254",0,0 },
831 { "msp430f2272",0,0 },
832 { "msp430f2274",0,0 },
833 { "msp430f233",0,2 },
834 { "msp430f2330",0,2 },
835 { "msp430f235",0,2 },
836 { "msp430f2350",0,2 },
837 { "msp430f2370",0,2 },
838 { "msp430f2410",0,2 },
839 { "msp430f2416",1,2 },
840 { "msp430f2417",1,2 },
841 { "msp430f2418",1,2 },
842 { "msp430f2419",1,2 },
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1326 { "rf430f5155",2,8 },
1327 { "rf430f5175",2,8 },
1328 { "rf430frl152h",0,0 },
1329 { "rf430frl152h_rom",0,0 },
1330 { "rf430frl153h",0,0 },
1331 { "rf430frl153h_rom",0,0 },
1332 { "rf430frl154h",0,0 },
1333 { "rf430frl154h_rom",0,0 }
1337 md_parse_option (int c, const char * arg)
1341 case OPTION_SILICON_ERRATA:
1342 case OPTION_SILICON_ERRATA_WARN:
1348 unsigned int length;
1349 unsigned int bitfield;
1352 { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4 },
1353 { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8 },
1354 { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11 },
1355 { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
1356 { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
1357 { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
1362 for (i = ARRAY_SIZE (erratas); i--;)
1363 if (strncasecmp (arg, erratas[i].name, erratas[i].length) == 0)
1365 if (c == OPTION_SILICON_ERRATA)
1366 silicon_errata_fix |= erratas[i].bitfield;
1368 silicon_errata_warn |= erratas[i].bitfield;
1369 arg += erratas[i].length;
1374 as_warn (_("Unrecognised CPU errata name starting here: %s"), arg);
1380 as_warn (_("Expecting comma after CPU errata name, not: %s"), arg);
1390 as_fatal (_("MCU option requires a name\n"));
1392 if (strcasecmp ("msp430", arg) == 0)
1393 selected_isa = MSP_ISA_430;
1394 else if (strcasecmp ("msp430xv2", arg) == 0)
1395 selected_isa = MSP_ISA_430Xv2;
1396 else if (strcasecmp ("msp430x", arg) == 0)
1397 selected_isa = MSP_ISA_430X;
1402 for (i = ARRAY_SIZE (msp430_mcu_data); i--;)
1403 if (strcasecmp (msp430_mcu_data[i].name, arg) == 0)
1405 switch (msp430_mcu_data[i].revision)
1407 case 0: selected_isa = MSP_ISA_430; break;
1408 case 1: selected_isa = MSP_ISA_430X; break;
1409 case 2: selected_isa = MSP_ISA_430Xv2; break;
1414 /* It is not an error if we do not match the MCU name. */
1418 if (strcmp (arg, "430") == 0
1419 || strcasecmp (arg, "msp430") == 0)
1420 selected_isa = MSP_ISA_430;
1421 else if (strcasecmp (arg, "430x") == 0
1422 || strcasecmp (arg, "msp430x") == 0)
1423 selected_isa = MSP_ISA_430X;
1424 else if (strcasecmp (arg, "430xv2") == 0
1425 || strcasecmp (arg, "msp430xv2") == 0)
1426 selected_isa = MSP_ISA_430Xv2;
1428 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg);
1432 msp430_enable_relax = 1;
1435 case OPTION_POLYMORPHS:
1436 msp430_enable_polys = 1;
1443 case OPTION_NO_INTR_NOPS:
1444 gen_interrupt_nops = FALSE;
1446 case OPTION_INTR_NOPS:
1447 gen_interrupt_nops = TRUE;
1450 case OPTION_WARN_INTR_NOPS:
1451 warn_interrupt_nops = TRUE;
1453 case OPTION_NO_WARN_INTR_NOPS:
1454 warn_interrupt_nops = FALSE;
1457 case OPTION_MOVE_DATA:
1461 case OPTION_DATA_REGION:
1462 if (strcmp (arg, "upper") == 0
1463 || strcmp (arg, "either") == 0)
1464 upper_data_region_in_use = TRUE;
1471 /* The intention here is to have the mere presence of these sections
1472 cause the object to have a reference to a well-known symbol. This
1473 reference pulls in the bits of the runtime (crt0) that initialize
1474 these sections. Thus, for example, the startup code to call
1475 memset() to initialize .bss will only be linked in when there is a
1476 non-empty .bss section. Otherwise, the call would exist but have a
1477 zero length parameter, which is a waste of memory and cycles.
1479 The code which initializes these sections should have a global
1480 label for these symbols, and should be marked with KEEP() in the
1484 msp430_make_init_symbols (const char * name)
1486 if (strncmp (name, ".bss", 4) == 0
1487 || strncmp (name, ".gnu.linkonce.b.", 16) == 0)
1488 (void) symbol_find_or_make ("__crt0_init_bss");
1490 if (strncmp (name, ".data", 5) == 0
1491 || strncmp (name, ".gnu.linkonce.d.", 16) == 0)
1492 (void) symbol_find_or_make ("__crt0_movedata");
1494 /* Note - data assigned to the .either.data section may end up being
1495 placed in the .upper.data section if the .lower.data section is
1496 full. Hence the need to define the crt0 symbol.
1497 The linker may create upper or either data sections, even when none exist
1498 at the moment, so use the value of the data-region flag to determine if
1499 the symbol is needed. */
1500 if (strncmp (name, ".either.data", 12) == 0
1501 || strncmp (name, ".upper.data", 11) == 0
1502 || upper_data_region_in_use)
1503 (void) symbol_find_or_make ("__crt0_move_highdata");
1505 /* See note about .either.data above. */
1506 if (strncmp (name, ".upper.bss", 10) == 0
1507 || strncmp (name, ".either.bss", 11) == 0
1508 || upper_data_region_in_use)
1509 (void) symbol_find_or_make ("__crt0_init_highbss");
1513 msp430_section (int arg)
1515 char * saved_ilp = input_line_pointer;
1516 const char * name = obj_elf_section_name ();
1518 msp430_make_init_symbols (name);
1520 input_line_pointer = saved_ilp;
1521 obj_elf_section (arg);
1525 msp430_frob_section (asection *sec)
1527 const char *name = sec->name;
1532 msp430_make_init_symbols (name);
1536 msp430_lcomm (int ignore ATTRIBUTE_UNUSED)
1538 symbolS *symbolP = s_comm_internal (0, s_lcomm_internal);
1541 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1542 (void) symbol_find_or_make ("__crt0_init_bss");
1546 msp430_comm (int needs_align)
1548 s_comm_internal (needs_align, elf_common_parse);
1549 (void) symbol_find_or_make ("__crt0_init_bss");
1553 msp430_refsym (int arg ATTRIBUTE_UNUSED)
1555 char sym_name[1024];
1556 input_line_pointer = extract_word (input_line_pointer, sym_name, 1024);
1558 (void) symbol_find_or_make (sym_name);
1561 const pseudo_typeS md_pseudo_table[] =
1563 {"arch", msp430_set_arch, OPTION_MMCU},
1564 {"cpu", msp430_set_arch, OPTION_MCPU},
1565 {"profiler", msp430_profiler, 0},
1566 {"section", msp430_section, 0},
1567 {"section.s", msp430_section, 0},
1568 {"sect", msp430_section, 0},
1569 {"sect.s", msp430_section, 0},
1570 {"pushsection", msp430_section, 1},
1571 {"refsym", msp430_refsym, 0},
1572 {"comm", msp430_comm, 0},
1573 {"lcomm", msp430_lcomm, 0},
1577 const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY";
1579 struct option md_longopts[] =
1581 {"msilicon-errata", required_argument, NULL, OPTION_SILICON_ERRATA},
1582 {"msilicon-errata-warn", required_argument, NULL, OPTION_SILICON_ERRATA_WARN},
1583 {"mmcu", required_argument, NULL, OPTION_MMCU},
1584 {"mcpu", required_argument, NULL, OPTION_MCPU},
1585 {"mP", no_argument, NULL, OPTION_POLYMORPHS},
1586 {"mQ", no_argument, NULL, OPTION_RELAX},
1587 {"ml", no_argument, NULL, OPTION_LARGE},
1588 {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS},
1589 {"mn", no_argument, NULL, OPTION_INTR_NOPS},
1590 {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS},
1591 {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS},
1592 {"md", no_argument, NULL, OPTION_MOVE_DATA},
1593 {"mdata-region", required_argument, NULL, OPTION_DATA_REGION},
1594 {NULL, no_argument, NULL, 0}
1597 size_t md_longopts_size = sizeof (md_longopts);
1600 md_show_usage (FILE * stream)
1603 _("MSP430 options:\n"
1604 " -mmcu=<msp430-name> - select microcontroller type\n"
1605 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
1607 _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
1608 " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
1609 " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
1611 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
1612 " -mP - enable polymorph instructions\n"));
1614 _(" -ml - enable large code model\n"));
1616 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
1618 _(" -mn - insert a NOP after changing interrupts\n"));
1620 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
1622 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
1624 _(" -md - Force copying of data from ROM to RAM at startup\n"));
1626 _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
1631 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
1637 extract_cmd (char * from, char * to, int limit)
1641 while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)
1643 *(to + size) = *from;
1654 md_atof (int type, char * litP, int * sizeP)
1656 return ieee_md_atof (type, litP, sizeP, FALSE);
1662 struct msp430_opcode_s * opcode;
1663 msp430_hash = hash_new ();
1665 for (opcode = msp430_opcodes; opcode->name; opcode++)
1666 hash_insert (msp430_hash, opcode->name, (char *) opcode);
1668 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
1669 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
1671 /* Set linkrelax here to avoid fixups in most sections. */
1675 /* Returns the register number equivalent to the string T.
1676 Returns -1 if there is no such register.
1677 Skips a leading 'r' or 'R' character if there is one.
1678 Handles the register aliases PC and SP. */
1681 check_reg (char * t)
1688 if (*t == 'r' || *t == 'R')
1691 if (strncasecmp (t, "pc", 2) == 0)
1694 if (strncasecmp (t, "sp", 2) == 0)
1697 if (strncasecmp (t, "sr", 2) == 0)
1705 if (val < 1 || val > 15)
1712 msp430_srcoperand (struct msp430_operand_s * op,
1715 bfd_boolean * imm_op,
1716 bfd_boolean allow_20bit_values,
1717 bfd_boolean constants_allowed)
1722 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1729 /* Check if there is:
1730 llo(x) - least significant 16 bits, x &= 0xffff
1731 lhi(x) - x = (x >> 16) & 0xffff,
1732 hlo(x) - x = (x >> 32) & 0xffff,
1733 hhi(x) - x = (x >> 48) & 0xffff
1734 The value _MUST_ be constant expression: #hlo(1231231231). */
1738 if (strncasecmp (h, "#llo(", 5) == 0)
1743 else if (strncasecmp (h, "#lhi(", 5) == 0)
1748 else if (strncasecmp (h, "#hlo(", 5) == 0)
1753 else if (strncasecmp (h, "#hhi(", 5) == 0)
1758 else if (strncasecmp (h, "#lo(", 4) == 0)
1763 else if (strncasecmp (h, "#hi(", 4) == 0)
1769 op->reg = 0; /* Reg PC. */
1771 op->ol = 1; /* Immediate will follow an instruction. */
1772 __tl = h + 1 + rval;
1774 op->vshift = vshift;
1776 end = parse_exp (__tl, &(op->exp));
1777 if (end != NULL && *end != 0 && *end != ')' )
1779 as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end, l);
1782 if (op->exp.X_op == O_constant)
1784 int x = op->exp.X_add_number;
1789 op->exp.X_add_number = x;
1791 else if (vshift == 1)
1793 x = (x >> 16) & 0xffff;
1794 op->exp.X_add_number = x;
1797 else if (vshift > 1)
1800 op->exp.X_add_number = -1;
1802 op->exp.X_add_number = 0; /* Nothing left. */
1803 x = op->exp.X_add_number;
1807 if (allow_20bit_values)
1809 if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < -524288)
1811 as_bad (_("value 0x%x out of extended range."), x);
1815 else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
1817 as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
1821 /* Now check constants. */
1822 /* Substitute register mode with a constant generator if applicable. */
1824 if (!allow_20bit_values)
1825 x = (short) x; /* Extend sign. */
1827 if (! constants_allowed)
1859 if (bin == 0x1200 && ! target_is_430x ())
1861 /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
1862 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
1863 as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
1864 /* No need to check silicon_errata_fixes - this fix is always implemented. */
1876 if (bin == 0x1200 && ! target_is_430x ())
1878 /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
1879 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
1880 as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
1891 else if (op->exp.X_op == O_symbol)
1894 as_bad (_("error: unsupported #foo() directive used on symbol"));
1897 else if (op->exp.X_op == O_big)
1903 op->exp.X_op = O_constant;
1904 op->exp.X_add_number = 0xffff & generic_bignum[vshift];
1905 x = op->exp.X_add_number;
1911 ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
1959 /* Redundant (yet) check. */
1960 else if (op->exp.X_op == O_register)
1962 (_("Registers cannot be used within immediate expression [%s]"), l);
1964 as_bad (_("unknown operand %s"), l);
1969 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1974 op->reg = 2; /* reg 2 in absolute addr mode. */
1975 op->am = 1; /* mode As == 01 bin. */
1976 op->ol = 1; /* Immediate value followed by instruction. */
1978 end = parse_exp (__tl, &(op->exp));
1979 if (end != NULL && *end != 0)
1981 as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end, l);
1986 if (op->exp.X_op == O_constant)
1988 int x = op->exp.X_add_number;
1990 if (allow_20bit_values)
1992 if (x > 0xfffff || x < -(0x7ffff))
1994 as_bad (_("value 0x%x out of extended range."), x);
1998 else if (x > 65535 || x < -32768)
2000 as_bad (_("value out of range: 0x%x"), x);
2004 else if (op->exp.X_op == O_symbol)
2008 /* Redundant (yet) check. */
2009 if (op->exp.X_op == O_register)
2011 (_("Registers cannot be used within absolute expression [%s]"), l);
2013 as_bad (_("unknown expression in operand %s"), l);
2019 /* Check if indirect register mode @Rn / postincrement @Rn+. */
2023 char *m = strchr (l, '+');
2027 as_bad (_("unknown addressing mode %s"), l);
2033 if ((op->reg = check_reg (t)) == -1)
2035 as_bad (_("Bad register name %s"), t);
2043 /* PC cannot be used in indirect addressing. */
2044 if (target_is_430xv2 () && op->reg == 0)
2046 as_bad (_("cannot use indirect addressing with the PC"));
2053 /* Check if register indexed X(Rn). */
2056 char *h = strrchr (l, '(');
2057 char *m = strrchr (l, ')');
2066 as_bad (_("')' required"));
2074 /* Extract a register. */
2075 if ((op->reg = check_reg (t + 1)) == -1)
2078 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
2085 as_bad (_("r2 should not be used in indexed addressing mode"));
2089 /* Extract constant. */
2094 end = parse_exp (__tl, &(op->exp));
2095 if (end != NULL && *end != 0)
2097 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2100 if (op->exp.X_op == O_constant)
2102 int x = op->exp.X_add_number;
2104 if (allow_20bit_values)
2106 if (x > 0xfffff || x < - (0x7ffff))
2108 as_bad (_("value 0x%x out of extended range."), x);
2112 else if (x > 65535 || x < -32768)
2114 as_bad (_("value out of range: 0x%x"), x);
2126 if (op->reg == 1 && (x & 1))
2128 if (silicon_errata_fix & SILICON_ERRATA_CPU8)
2129 as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
2130 else if (silicon_errata_warn & SILICON_ERRATA_CPU8)
2131 as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
2134 else if (op->exp.X_op == O_symbol)
2138 /* Redundant (yet) check. */
2139 if (op->exp.X_op == O_register)
2141 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
2143 as_bad (_("unknown expression in operand %s"), l);
2151 /* Possibly register mode 'mov r1,r2'. */
2152 if ((op->reg = check_reg (l)) != -1)
2160 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
2162 op->reg = 0; /* PC relative... be careful. */
2163 /* An expression starting with a minus sign is a constant, not an address. */
2164 op->am = (*l == '-' ? 3 : 1);
2168 end = parse_exp (__tl, &(op->exp));
2169 if (end != NULL && * end != 0)
2171 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2179 msp430_dstoperand (struct msp430_operand_s * op,
2182 bfd_boolean allow_20bit_values,
2183 bfd_boolean constants_allowed)
2186 int ret = msp430_srcoperand (op, l, bin, & dummy,
2195 char *__tl = (char *) "0";
2201 (void) parse_exp (__tl, &(op->exp));
2203 if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
2205 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
2215 ("this addressing mode is not applicable for destination operand"));
2221 /* Attempt to encode a MOVA instruction with the given operands.
2222 Returns the length of the encoded instruction if successful
2223 or 0 upon failure. If the encoding fails, an error message
2224 will be returned if a pointer is provided. */
2227 try_encode_mova (bfd_boolean imm_op,
2229 struct msp430_operand_s * op1,
2230 struct msp430_operand_s * op2,
2231 const char ** error_message_return)
2237 /* Only a restricted subset of the normal MSP430 addressing modes
2238 are supported here, so check for the ones that are allowed. */
2241 if (op1->mode == OP_EXP)
2243 if (op2->mode != OP_REG)
2245 if (error_message_return != NULL)
2246 * error_message_return = _("expected register as second argument of %s");
2252 /* MOVA #imm20, Rdst. */
2253 bin |= 0x80 | op2->reg;
2254 frag = frag_more (4);
2255 where = frag - frag_now->fr_literal;
2256 if (op1->exp.X_op == O_constant)
2258 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2259 bfd_putl16 ((bfd_vma) bin, frag);
2260 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2264 bfd_putl16 ((bfd_vma) bin, frag);
2265 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2266 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2267 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2272 else if (op1->am == 1)
2274 /* MOVA z16(Rsrc), Rdst. */
2275 bin |= 0x30 | (op1->reg << 8) | op2->reg;
2276 frag = frag_more (4);
2277 where = frag - frag_now->fr_literal;
2278 bfd_putl16 ((bfd_vma) bin, frag);
2279 if (op1->exp.X_op == O_constant)
2281 if (op1->exp.X_add_number > 0xffff
2282 || op1->exp.X_add_number < -(0x7fff))
2284 if (error_message_return != NULL)
2285 * error_message_return = _("index value too big for %s");
2288 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2292 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2293 fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
2295 BFD_RELOC_MSP430X_PCR16 :
2296 BFD_RELOC_MSP430X_ABS16);
2301 if (error_message_return != NULL)
2302 * error_message_return = _("unexpected addressing mode for %s");
2305 else if (op1->am == 0)
2307 /* MOVA Rsrc, ... */
2308 if (op2->mode == OP_REG)
2310 bin |= 0xc0 | (op1->reg << 8) | op2->reg;
2311 frag = frag_more (2);
2312 where = frag - frag_now->fr_literal;
2313 bfd_putl16 ((bfd_vma) bin, frag);
2316 else if (op2->am == 1)
2320 /* MOVA Rsrc, &abs20. */
2321 bin |= 0x60 | (op1->reg << 8);
2322 frag = frag_more (4);
2323 where = frag - frag_now->fr_literal;
2324 if (op2->exp.X_op == O_constant)
2326 bin |= (op2->exp.X_add_number >> 16) & 0xf;
2327 bfd_putl16 ((bfd_vma) bin, frag);
2328 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2332 bfd_putl16 ((bfd_vma) bin, frag);
2333 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2334 fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
2335 BFD_RELOC_MSP430X_ABS20_ADR_DST);
2340 /* MOVA Rsrc, z16(Rdst). */
2341 bin |= 0x70 | (op1->reg << 8) | op2->reg;
2342 frag = frag_more (4);
2343 where = frag - frag_now->fr_literal;
2344 bfd_putl16 ((bfd_vma) bin, frag);
2345 if (op2->exp.X_op == O_constant)
2347 if (op2->exp.X_add_number > 0xffff
2348 || op2->exp.X_add_number < -(0x7fff))
2350 if (error_message_return != NULL)
2351 * error_message_return = _("index value too big for %s");
2354 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2358 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2359 fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
2361 BFD_RELOC_MSP430X_PCR16 :
2362 BFD_RELOC_MSP430X_ABS16);
2367 if (error_message_return != NULL)
2368 * error_message_return = _("unexpected addressing mode for %s");
2373 /* imm_op == FALSE. */
2375 if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
2377 /* MOVA &abs20, Rdst. */
2378 if (op2->mode != OP_REG)
2380 if (error_message_return != NULL)
2381 * error_message_return = _("expected register as second argument of %s");
2385 if (op2->reg == 2 || op2->reg == 3)
2387 if (error_message_return != NULL)
2388 * error_message_return = _("constant generator destination register found in %s");
2392 bin |= 0x20 | op2->reg;
2393 frag = frag_more (4);
2394 where = frag - frag_now->fr_literal;
2395 if (op1->exp.X_op == O_constant)
2397 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2398 bfd_putl16 ((bfd_vma) bin, frag);
2399 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2403 bfd_putl16 ((bfd_vma) bin, frag);
2404 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2405 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2406 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2410 else if (op1->mode == OP_REG)
2414 /* MOVA @Rsrc+, Rdst. */
2415 if (op2->mode != OP_REG)
2417 if (error_message_return != NULL)
2418 * error_message_return = _("expected register as second argument of %s");
2422 if (op2->reg == 2 || op2->reg == 3)
2424 if (error_message_return != NULL)
2425 * error_message_return = _("constant generator destination register found in %s");
2429 if (op1->reg == 2 || op1->reg == 3)
2431 if (error_message_return != NULL)
2432 * error_message_return = _("constant generator source register found in %s");
2436 bin |= 0x10 | (op1->reg << 8) | op2->reg;
2437 frag = frag_more (2);
2438 where = frag - frag_now->fr_literal;
2439 bfd_putl16 ((bfd_vma) bin, frag);
2442 else if (op1->am == 2)
2444 /* MOVA @Rsrc,Rdst */
2445 if (op2->mode != OP_REG)
2447 if (error_message_return != NULL)
2448 * error_message_return = _("expected register as second argument of %s");
2452 if (op2->reg == 2 || op2->reg == 3)
2454 if (error_message_return != NULL)
2455 * error_message_return = _("constant generator destination register found in %s");
2459 if (op1->reg == 2 || op1->reg == 3)
2461 if (error_message_return != NULL)
2462 * error_message_return = _("constant generator source register found in %s");
2466 bin |= (op1->reg << 8) | op2->reg;
2467 frag = frag_more (2);
2468 where = frag - frag_now->fr_literal;
2469 bfd_putl16 ((bfd_vma) bin, frag);
2474 if (error_message_return != NULL)
2475 * error_message_return = _("unexpected addressing mode for %s");
2480 #define NOP_CHECK_INTERRUPT (1 << 0)
2481 #define NOP_CHECK_CPU12 (1 << 1)
2482 #define NOP_CHECK_CPU19 (1 << 2)
2484 static signed int check_for_nop = 0;
2486 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
2488 /* Parse instruction operands.
2489 Return binary opcode. */
2492 msp430_operands (struct msp430_opcode_s * opcode, char * line)
2494 int bin = opcode->bin_opcode; /* Opcode mask. */
2495 int insn_length = 0;
2496 char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
2500 struct msp430_operand_s op1, op2;
2502 static short ZEROS = 0;
2503 bfd_boolean byte_op, imm_op;
2506 int extended = 0x1800;
2507 bfd_boolean extended_op = FALSE;
2508 bfd_boolean addr_op;
2509 const char * error_message;
2510 static signed int repeat_count = 0;
2511 static bfd_boolean prev_insn_is_nop = FALSE;
2512 bfd_boolean fix_emitted;
2514 /* Opcode is the one from opcodes table
2515 line contains something like
2524 bfd_boolean check = FALSE;
2527 switch (TOLOWER (* line))
2530 /* Byte operation. */
2531 bin |= BYTE_OPERATION;
2537 /* "Address" ops work on 20-bit values. */
2539 bin |= BYTE_OPERATION;
2544 /* Word operation - this is the default. */
2552 as_warn (_("no size modifier after period, .w assumed"));
2556 as_bad (_("unrecognised instruction size modifier .%c"),
2568 if (*line && ! ISSPACE (*line))
2570 as_bad (_("junk found after instruction: %s.%s"),
2571 opcode->name, line);
2575 /* Catch the case where the programmer has used a ".a" size modifier on an
2576 instruction that does not support it. Look for an alternative extended
2577 instruction that has the same name without the period. Eg: "add.a"
2578 becomes "adda". Although this not an officially supported way of
2579 specifying instruction aliases other MSP430 assemblers allow it. So we
2580 support it for compatibility purposes. */
2581 if (addr_op && opcode->fmt >= 0)
2583 const char * old_name = opcode->name;
2586 sprintf (real_name, "%sa", old_name);
2587 opcode = hash_find (msp430_hash, real_name);
2590 as_bad (_("instruction %s.a does not exist"), old_name);
2593 #if 0 /* Enable for debugging. */
2594 as_warn ("treating %s.a as %s", old_name, real_name);
2597 bin = opcode->bin_opcode;
2600 if (opcode->fmt != -1
2601 && opcode->insn_opnumb
2602 && (!*line || *line == '\n'))
2604 as_bad (_("instruction %s requires %d operand(s)"),
2605 opcode->name, opcode->insn_opnumb);
2609 memset (l1, 0, sizeof (l1));
2610 memset (l2, 0, sizeof (l2));
2611 memset (&op1, 0, sizeof (op1));
2612 memset (&op2, 0, sizeof (op2));
2616 if ((fmt = opcode->fmt) < 0)
2618 if (! target_is_430x ())
2620 as_bad (_("instruction %s requires MSP430X mcu"),
2631 /* If requested set the extended instruction repeat count. */
2634 if (repeat_count > 0)
2635 extended |= (repeat_count - 1);
2637 extended |= (1 << 7) | (- repeat_count);
2640 as_bad (_("unable to repeat %s insn"), opcode->name);
2647 if (! is_opcode ("nop"))
2649 bfd_boolean doit = FALSE;
2653 switch (check_for_nop & - check_for_nop)
2655 case NOP_CHECK_INTERRUPT:
2656 if (warn_interrupt_nops)
2658 if (gen_interrupt_nops)
2659 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2661 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2664 if (gen_interrupt_nops)
2665 /* Emit a NOP between interrupt enable/disable.
2666 See 1.3.4.1 of the MSP430x5xx User Guide. */
2670 case NOP_CHECK_CPU12:
2671 if (silicon_errata_warn & SILICON_ERRATA_CPU12)
2672 as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
2674 if (silicon_errata_fix & SILICON_ERRATA_CPU12)
2678 case NOP_CHECK_CPU19:
2679 if (silicon_errata_warn & SILICON_ERRATA_CPU19)
2680 as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
2682 if (silicon_errata_fix & SILICON_ERRATA_CPU19)
2687 as_bad (_("internal error: unknown nop check state"));
2690 check_for_nop &= ~ (check_for_nop & - check_for_nop);
2692 while (check_for_nop);
2696 frag = frag_more (2);
2697 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2698 dwarf2_emit_insn (2);
2707 case 0: /* Emulated. */
2708 switch (opcode->insn_opnumb)
2711 if (is_opcode ("eint"))
2713 if (! prev_insn_is_nop)
2715 if (gen_interrupt_nops)
2717 frag = frag_more (2);
2718 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2719 dwarf2_emit_insn (2);
2721 if (warn_interrupt_nops)
2722 as_warn (_("inserting a NOP before EINT"));
2724 else if (warn_interrupt_nops)
2725 as_warn (_("a NOP might be needed before the EINT"));
2728 else if (is_opcode ("dint"))
2729 check_for_nop |= NOP_CHECK_INTERRUPT;
2731 /* Set/clear bits instructions. */
2735 extended |= BYTE_OPERATION;
2737 /* Emit the extension word. */
2739 frag = frag_more (2);
2740 bfd_putl16 (extended, frag);
2744 frag = frag_more (2);
2745 bfd_putl16 ((bfd_vma) bin, frag);
2746 dwarf2_emit_insn (insn_length);
2750 /* Something which works with destination operand. */
2751 line = extract_operand (line, l1, sizeof (l1));
2752 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
2756 bin |= (op1.reg | (op1.am << 7));
2758 /* If the PC is the destination... */
2759 if (op1.am == 0 && op1.reg == 0
2760 /* ... and the opcode alters the SR. */
2761 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
2762 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
2764 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
2765 as_bad (_("CPU11: PC is destination of SR altering instruction"));
2766 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
2767 as_warn (_("CPU11: PC is destination of SR altering instruction"));
2770 /* If the status register is the destination... */
2771 if (op1.am == 0 && op1.reg == 2
2772 /* ... and the opcode alters the SR. */
2773 && (is_opcode ("adc") || is_opcode ("dec") || is_opcode ("decd")
2774 || is_opcode ("inc") || is_opcode ("incd") || is_opcode ("inv")
2775 || is_opcode ("sbc") || is_opcode ("sxt")
2776 || is_opcode ("adcx") || is_opcode ("decx") || is_opcode ("decdx")
2777 || is_opcode ("incx") || is_opcode ("incdx") || is_opcode ("invx")
2778 || is_opcode ("sbcx")
2781 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
2782 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2783 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
2784 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2787 if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
2788 check_for_nop |= NOP_CHECK_INTERRUPT;
2790 /* Compute the entire instruction length, in bytes. */
2791 op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
2792 insn_length += op_length;
2793 frag = frag_more (op_length);
2794 where = frag - frag_now->fr_literal;
2799 extended |= BYTE_OPERATION;
2801 if (op1.ol != 0 && ((extended & 0xf) != 0))
2803 as_bad (_("repeat instruction used with non-register mode instruction"));
2807 if (op1.mode == OP_EXP)
2809 if (op1.exp.X_op == O_constant)
2810 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2812 else if (op1.reg || op1.am == 3) /* Not PC relative. */
2813 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2814 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2816 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2817 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2820 /* Emit the extension word. */
2821 bfd_putl16 (extended, frag);
2826 bfd_putl16 ((bfd_vma) bin, frag);
2830 if (op1.mode == OP_EXP)
2832 if (op1.exp.X_op == O_constant)
2834 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2838 bfd_putl16 ((bfd_vma) ZEROS, frag);
2843 fix_new_exp (frag_now, where, 2,
2844 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
2846 fix_new_exp (frag_now, where, 2,
2847 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2852 dwarf2_emit_insn (insn_length);
2856 /* Shift instruction. */
2857 line = extract_operand (line, l1, sizeof (l1));
2858 strncpy (l2, l1, sizeof (l2));
2859 l2[sizeof (l2) - 1] = '\0';
2860 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
2861 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
2864 break; /* An error occurred. All warnings were done before. */
2866 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2);
2867 frag = frag_more (insn_length);
2868 where = frag - frag_now->fr_literal;
2870 if (target_is_430xv2 ()
2871 && op1.mode == OP_REG
2873 && (is_opcode ("rlax")
2874 || is_opcode ("rlcx")
2875 || is_opcode ("rla")
2876 || is_opcode ("rlc")))
2878 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
2882 /* If the status register is the destination... */
2883 if (op1.am == 0 && op1.reg == 2
2884 /* ... and the opcode alters the SR. */
2885 && (is_opcode ("rla") || is_opcode ("rlc")
2886 || is_opcode ("rlax") || is_opcode ("rlcx")
2889 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
2890 as_bad (_("CPU13: SR is destination of SR altering instruction"));
2891 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
2892 as_warn (_("CPU13: SR is destination of SR altering instruction"));
2898 extended |= BYTE_OPERATION;
2900 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
2902 as_bad (_("repeat instruction used with non-register mode instruction"));
2906 if (op1.mode == OP_EXP)
2908 if (op1.exp.X_op == O_constant)
2909 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2911 else if (op1.reg || op1.am == 3) /* Not PC relative. */
2912 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2913 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2915 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2916 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2919 if (op2.mode == OP_EXP)
2921 if (op2.exp.X_op == O_constant)
2922 extended |= (op2.exp.X_add_number >> 16) & 0xf;
2924 else if (op1.mode == OP_EXP)
2925 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
2926 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2927 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
2929 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
2930 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
2931 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
2934 /* Emit the extension word. */
2935 bfd_putl16 (extended, frag);
2940 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
2941 bfd_putl16 ((bfd_vma) bin, frag);
2945 if (op1.mode == OP_EXP)
2947 if (op1.exp.X_op == O_constant)
2949 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2953 bfd_putl16 ((bfd_vma) ZEROS, frag);
2957 if (op1.reg || op1.am == 3) /* Not PC relative. */
2958 fix_new_exp (frag_now, where, 2,
2959 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
2961 fix_new_exp (frag_now, where, 2,
2962 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2969 if (op2.mode == OP_EXP)
2971 if (op2.exp.X_op == O_constant)
2973 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
2977 bfd_putl16 ((bfd_vma) ZEROS, frag);
2981 if (op2.reg) /* Not PC relative. */
2982 fix_new_exp (frag_now, where, 2,
2983 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
2985 fix_new_exp (frag_now, where, 2,
2986 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2991 dwarf2_emit_insn (insn_length);
2995 /* Branch instruction => mov dst, r0. */
2998 as_bad ("Internal error: state 0/3 not coded for extended instructions");
3002 line = extract_operand (line, l1, sizeof (l1));
3003 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
3009 bin |= ((op1.reg << 8) | (op1.am << 4));
3010 op_length = 2 + 2 * op1.ol;
3011 frag = frag_more (op_length);
3012 where = frag - frag_now->fr_literal;
3013 bfd_putl16 ((bfd_vma) bin, frag);
3015 if (op1.mode == OP_EXP)
3017 if (op1.exp.X_op == O_constant)
3019 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2);
3025 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3027 if (op1.reg || op1.am == 3)
3028 fix_new_exp (frag_now, where, 2,
3029 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3031 fix_new_exp (frag_now, where, 2,
3032 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3036 dwarf2_emit_insn (insn_length + op_length);
3040 /* CALLA instructions. */
3041 fix_emitted = FALSE;
3043 line = extract_operand (line, l1, sizeof (l1));
3046 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
3047 extended_op, FALSE);
3053 op_length = 2 + 2 * op1.ol;
3054 frag = frag_more (op_length);
3055 where = frag - frag_now->fr_literal;
3063 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3064 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3067 else if (op1.am == 1)
3073 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3074 BFD_RELOC_MSP430X_PCR20_CALL);
3078 bin |= 0x50 | op1.reg;
3080 else if (op1.am == 0)
3081 bin |= 0x40 | op1.reg;
3083 else if (op1.am == 1)
3087 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3088 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3091 else if (op1.am == 2)
3092 bin |= 0x60 | op1.reg;
3093 else if (op1.am == 3)
3094 bin |= 0x70 | op1.reg;
3096 bfd_putl16 ((bfd_vma) bin, frag);
3098 if (op1.mode == OP_EXP)
3102 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol);
3106 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3109 fix_new_exp (frag_now, where + 2, 2,
3110 &(op1.exp), FALSE, BFD_RELOC_16);
3113 dwarf2_emit_insn (insn_length + op_length);
3121 /* [POP|PUSH]M[.A] #N, Rd */
3122 line = extract_operand (line, l1, sizeof (l1));
3123 line = extract_operand (line, l2, sizeof (l2));
3127 as_bad (_("expected #n as first argument of %s"), opcode->name);
3130 end = parse_exp (l1 + 1, &(op1.exp));
3131 if (end != NULL && *end != 0)
3133 as_bad (_("extra characters '%s' at end of constant expression '%s'"), end, l1);
3136 if (op1.exp.X_op != O_constant)
3138 as_bad (_("expected constant expression as first argument of %s"),
3143 if ((reg = check_reg (l2)) == -1)
3145 as_bad (_("expected register as second argument of %s"),
3151 frag = frag_more (op_length);
3152 where = frag - frag_now->fr_literal;
3153 bin = opcode->bin_opcode;
3156 n = op1.exp.X_add_number;
3157 bin |= (n - 1) << 4;
3158 if (is_opcode ("pushm"))
3162 if (reg - n + 1 < 0)
3164 as_bad (_("Too many registers popped"));
3168 /* CPU21 errata: cannot use POPM to restore the SR register. */
3169 if (target_is_430xv2 ()
3170 && (reg - n + 1 < 3)
3172 && is_opcode ("popm"))
3174 as_bad (_("Cannot use POPM to restore the SR register"));
3178 bin |= (reg - n + 1);
3181 bfd_putl16 ((bfd_vma) bin, frag);
3182 dwarf2_emit_insn (op_length);
3191 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
3192 if (extended & 0xff)
3194 as_bad (_("repeat count cannot be used with %s"), opcode->name);
3198 line = extract_operand (line, l1, sizeof (l1));
3199 line = extract_operand (line, l2, sizeof (l2));
3203 as_bad (_("expected #n as first argument of %s"), opcode->name);
3206 end = parse_exp (l1 + 1, &(op1.exp));
3207 if (end != NULL && *end != 0)
3209 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3212 if (op1.exp.X_op != O_constant)
3214 as_bad (_("expected constant expression as first argument of %s"),
3218 n = op1.exp.X_add_number;
3221 as_bad (_("expected first argument of %s to be in the range 1-4"),
3226 if ((reg = check_reg (l2)) == -1)
3228 as_bad (_("expected register as second argument of %s"),
3233 if (target_is_430xv2 () && reg == 0)
3235 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
3240 frag = frag_more (op_length);
3241 where = frag - frag_now->fr_literal;
3243 bin = opcode->bin_opcode;
3246 bin |= (n - 1) << 10;
3249 bfd_putl16 ((bfd_vma) bin, frag);
3250 dwarf2_emit_insn (op_length);
3256 bfd_boolean need_reloc = FALSE;
3260 /* ADDA, CMPA and SUBA address instructions. */
3261 if (extended & 0xff)
3263 as_bad (_("repeat count cannot be used with %s"), opcode->name);
3267 line = extract_operand (line, l1, sizeof (l1));
3268 line = extract_operand (line, l2, sizeof (l2));
3270 bin = opcode->bin_opcode;
3274 end = parse_exp (l1 + 1, &(op1.exp));
3275 if (end != NULL && *end != 0)
3277 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3281 if (op1.exp.X_op == O_constant)
3283 n = op1.exp.X_add_number;
3284 if (n > 0xfffff || n < - (0x7ffff))
3286 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
3291 bin |= ((n >> 16) & 0xf) << 8;
3303 if ((n = check_reg (l1)) == -1)
3305 as_bad (_("expected register name or constant as first argument of %s"),
3310 bin |= (n << 8) | (1 << 6);
3314 if ((reg = check_reg (l2)) == -1)
3316 as_bad (_("expected register as second argument of %s"),
3321 frag = frag_more (op_length);
3322 where = frag - frag_now->fr_literal;
3325 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3326 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
3328 bfd_putl16 ((bfd_vma) bin, frag);
3330 bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2);
3331 dwarf2_emit_insn (op_length);
3335 case 9: /* MOVA, BRA, RETA. */
3337 bin = opcode->bin_opcode;
3339 if (is_opcode ("reta"))
3341 /* The RETA instruction does not take any arguments.
3342 The implicit first argument is @SP+.
3343 The implicit second argument is PC. */
3353 line = extract_operand (line, l1, sizeof (l1));
3354 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3355 &imm_op, extended_op, FALSE);
3357 if (is_opcode ("bra"))
3359 /* This is the BRA synthetic instruction.
3360 The second argument is always PC. */
3366 line = extract_operand (line, l2, sizeof (l2));
3367 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
3372 break; /* Error occurred. All warnings were done before. */
3375 /* Only a restricted subset of the normal MSP430 addressing modes
3376 are supported here, so check for the ones that are allowed. */
3377 if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2,
3378 & error_message)) == 0)
3380 as_bad (error_message, opcode->name);
3383 dwarf2_emit_insn (op_length);
3387 line = extract_operand (line, l1, sizeof l1);
3388 /* The RPT instruction only accepted immediates and registers. */
3391 end = parse_exp (l1 + 1, &(op1.exp));
3392 if (end != NULL && *end != 0)
3394 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3397 if (op1.exp.X_op != O_constant)
3399 as_bad (_("expected constant value as argument to RPT"));
3402 if (op1.exp.X_add_number < 1
3403 || op1.exp.X_add_number > (1 << 4))
3405 as_bad (_("expected constant in the range 2..16"));
3409 /* We silently accept and ignore a repeat count of 1. */
3410 if (op1.exp.X_add_number > 1)
3411 repeat_count = op1.exp.X_add_number;
3417 if ((reg = check_reg (l1)) != -1)
3420 as_warn (_("PC used as an argument to RPT"));
3422 repeat_count = - reg;
3426 as_bad (_("expected constant or register name as argument to RPT insn"));
3433 as_bad (_("Illegal emulated instruction"));
3438 case 1: /* Format 1, double operand. */
3439 line = extract_operand (line, l1, sizeof (l1));
3440 line = extract_operand (line, l2, sizeof (l2));
3441 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
3442 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
3445 break; /* Error occurred. All warnings were done before. */
3448 && is_opcode ("movx")
3450 && msp430_enable_relax)
3452 /* This is the MOVX.A instruction. See if we can convert
3453 it into the MOVA instruction instead. This saves 2 bytes. */
3454 if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2,
3457 dwarf2_emit_insn (op_length);
3462 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
3464 /* If the PC is the destination... */
3465 if (op2.am == 0 && op2.reg == 0
3466 /* ... and the opcode alters the SR. */
3467 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
3468 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
3470 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
3471 as_bad (_("CPU11: PC is destination of SR altering instruction"));
3472 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
3473 as_warn (_("CPU11: PC is destination of SR altering instruction"));
3476 /* If the status register is the destination... */
3477 if (op2.am == 0 && op2.reg == 2
3478 /* ... and the opcode alters the SR. */
3479 && (is_opcode ("add") || is_opcode ("addc") || is_opcode ("and")
3480 || is_opcode ("dadd") || is_opcode ("sub") || is_opcode ("subc")
3481 || is_opcode ("xor")
3482 || is_opcode ("addx") || is_opcode ("addcx") || is_opcode ("andx")
3483 || is_opcode ("daddx") || is_opcode ("subx") || is_opcode ("subcx")
3484 || is_opcode ("xorx")
3487 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
3488 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3489 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
3490 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3493 if ( (is_opcode ("bic") && bin == 0xc232)
3494 || (is_opcode ("bis") && bin == 0xd232)
3495 || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
3497 /* Avoid false checks when a constant value is being put into the SR. */
3498 if (op1.mode == OP_EXP
3499 && op1.exp.X_op == O_constant
3500 && (op1.exp.X_add_number & 0x8) != 0x8)
3503 check_for_nop |= NOP_CHECK_INTERRUPT;
3506 if (((is_opcode ("bis") && bin == 0xd032)
3507 || (is_opcode ("mov") && bin == 0x4032)
3508 || (is_opcode ("xor") && bin == 0xe032))
3509 && op1.mode == OP_EXP
3510 && op1.exp.X_op == O_constant
3511 && (op1.exp.X_add_number & 0x10) == 0x10)
3512 check_for_nop |= NOP_CHECK_CPU19;
3514 /* Compute the entire length of the instruction in bytes. */
3515 op_length = (extended_op ? 2 : 0) /* The extension word. */
3516 + 2 /* The opcode */
3517 + (2 * op1.ol) /* The first operand. */
3518 + (2 * op2.ol); /* The second operand. */
3520 insn_length += op_length;
3521 frag = frag_more (op_length);
3522 where = frag - frag_now->fr_literal;
3527 extended |= BYTE_OPERATION;
3529 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
3531 as_bad (_("repeat instruction used with non-register mode instruction"));
3535 /* If necessary, emit a reloc to update the extension word. */
3536 if (op1.mode == OP_EXP)
3538 if (op1.exp.X_op == O_constant)
3539 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3541 else if (op1.reg || op1.am == 3) /* Not PC relative. */
3542 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3543 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3545 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3546 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3549 if (op2.mode == OP_EXP)
3551 if (op2.exp.X_op == O_constant)
3552 extended |= (op2.exp.X_add_number >> 16) & 0xf;
3554 else if (op1.mode == OP_EXP)
3555 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
3556 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3557 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
3560 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
3561 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
3562 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
3565 /* Emit the extension word. */
3566 bfd_putl16 (extended, frag);
3571 bfd_putl16 ((bfd_vma) bin, frag);
3575 if (op1.mode == OP_EXP)
3577 if (op1.exp.X_op == O_constant)
3579 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3583 bfd_putl16 ((bfd_vma) ZEROS, frag);
3587 if (op1.reg || op1.am == 3) /* Not PC relative. */
3588 fix_new_exp (frag_now, where, 2,
3589 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3591 fix_new_exp (frag_now, where, 2,
3592 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3600 if (op2.mode == OP_EXP)
3602 if (op2.exp.X_op == O_constant)
3604 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
3608 bfd_putl16 ((bfd_vma) ZEROS, frag);
3612 if (op2.reg) /* Not PC relative. */
3613 fix_new_exp (frag_now, where, 2,
3614 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
3616 fix_new_exp (frag_now, where, 2,
3617 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3622 dwarf2_emit_insn (insn_length);
3624 /* If the PC is the destination... */
3625 if (op2.am == 0 && op2.reg == 0
3626 /* ... but the opcode does not alter the destination. */
3627 && (is_opcode ("cmp") || is_opcode ("bit") || is_opcode ("cmpx")))
3628 check_for_nop |= NOP_CHECK_CPU12;
3631 case 2: /* Single-operand mostly instr. */
3632 if (opcode->insn_opnumb == 0)
3634 /* reti instruction. */
3636 frag = frag_more (2);
3637 bfd_putl16 ((bfd_vma) bin, frag);
3638 dwarf2_emit_insn (insn_length);
3642 line = extract_operand (line, l1, sizeof (l1));
3643 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3644 &imm_op, extended_op, TRUE);
3646 break; /* Error in operand. */
3648 if (target_is_430xv2 ()
3649 && op1.mode == OP_REG
3651 && (is_opcode ("rrax")
3652 || is_opcode ("rrcx")
3653 || is_opcode ("rra")
3654 || is_opcode ("rrc")))
3656 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
3660 /* If the status register is the destination... */
3661 if (op1.am == 0 && op1.reg == 2
3662 /* ... and the opcode alters the SR. */
3663 && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
3665 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
3666 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3667 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
3668 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3671 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
3672 frag = frag_more (insn_length);
3673 where = frag - frag_now->fr_literal;
3677 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
3679 /* These two instructions use a special
3680 encoding of the A/L and B/W bits. */
3681 bin &= ~ BYTE_OPERATION;
3685 as_bad (_("%s instruction does not accept a .b suffix"),
3690 extended |= BYTE_OPERATION;
3693 extended |= BYTE_OPERATION;
3695 if (is_opcode ("rrux"))
3696 extended |= IGNORE_CARRY_BIT;
3698 if (op1.ol != 0 && ((extended & 0xf) != 0))
3700 as_bad (_("repeat instruction used with non-register mode instruction"));
3704 if (op1.mode == OP_EXP)
3706 if (op1.exp.X_op == O_constant)
3707 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3709 else if (op1.reg || op1.am == 3) /* Not PC relative. */
3710 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3711 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3713 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3714 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3717 /* Emit the extension word. */
3718 bfd_putl16 (extended, frag);
3723 bin |= op1.reg | (op1.am << 4);
3724 bfd_putl16 ((bfd_vma) bin, frag);
3728 if (op1.mode == OP_EXP)
3730 if (op1.exp.X_op == O_constant)
3732 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3736 bfd_putl16 ((bfd_vma) ZEROS, frag);
3740 if (op1.reg || op1.am == 3) /* Not PC relative. */
3741 fix_new_exp (frag_now, where, 2,
3742 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3744 fix_new_exp (frag_now, where, 2,
3745 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3750 dwarf2_emit_insn (insn_length);
3753 case 3: /* Conditional jumps instructions. */
3754 line = extract_operand (line, l1, sizeof (l1));
3755 /* l1 is a label. */
3764 end = parse_exp (m, &exp);
3765 if (end != NULL && *end != 0)
3767 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3771 /* In order to handle something like:
3775 jz 4 ; skip next 4 bytes
3778 nop ; will jump here if r5 positive or zero
3780 jCOND -n ;assumes jump n bytes backward:
3790 jCOND $n ; jump from PC in either direction. */
3792 if (exp.X_op == O_constant)
3794 int x = exp.X_add_number;
3798 as_warn (_("Even number required. Rounded to %d"), x + 1);
3802 if ((*l1 == '$' && x > 0) || x < 0)
3807 if (x > 512 || x < -511)
3809 as_bad (_("Wrong displacement %d"), x << 1);
3814 frag = frag_more (2); /* Instr size is 1 word. */
3817 bfd_putl16 ((bfd_vma) bin, frag);
3819 else if (exp.X_op == O_symbol && *l1 != '$')
3822 frag = frag_more (2); /* Instr size is 1 word. */
3823 where = frag - frag_now->fr_literal;
3824 fix_new_exp (frag_now, where, 2,
3825 &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
3827 bfd_putl16 ((bfd_vma) bin, frag);
3829 else if (*l1 == '$')
3831 as_bad (_("instruction requires label sans '$'"));
3835 ("instruction requires label or value in range -511:512"));
3836 dwarf2_emit_insn (insn_length);
3841 as_bad (_("instruction requires label"));
3846 case 4: /* Extended jumps. */
3847 if (!msp430_enable_polys)
3849 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3853 line = extract_operand (line, l1, sizeof (l1));
3859 /* Ignore absolute addressing. make it PC relative anyway. */
3860 if (*m == '#' || *m == '$')
3863 end = parse_exp (m, & exp);
3864 if (end != NULL && *end != 0)
3866 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3869 if (exp.X_op == O_symbol)
3871 /* Relaxation required. */
3872 struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];
3874 if (target_is_430x ())
3875 rc = msp430x_rcodes[opcode->insn_opnumb];
3877 /* The parameter to dwarf2_emit_insn is actually the offset to
3878 the start of the insn from the fix piece of instruction that
3879 was emitted. Since next fragments may have variable size we
3880 tie debug info to the beginning of the instruction. */
3882 frag = frag_more (8);
3883 dwarf2_emit_insn (0);
3884 bfd_putl16 ((bfd_vma) rc.sop, frag);
3885 frag = frag_variant (rs_machine_dependent, 8, 2,
3887 ENCODE_RELAX (rc.lpos, STATE_BITS10),
3889 0, /* Offset is zero if jump dist less than 1K. */
3895 as_bad (_("instruction requires label"));
3898 case 5: /* Emulated extended branches. */
3899 if (!msp430_enable_polys)
3901 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3904 line = extract_operand (line, l1, sizeof (l1));
3910 /* Ignore absolute addressing. make it PC relative anyway. */
3911 if (*m == '#' || *m == '$')
3914 end = parse_exp (m, & exp);
3915 if (end != NULL && *end != 0)
3917 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3920 if (exp.X_op == O_symbol)
3922 /* Relaxation required. */
3923 struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];
3925 if (target_is_430x ())
3926 hc = msp430x_hcodes[opcode->insn_opnumb];
3929 frag = frag_more (8);
3930 dwarf2_emit_insn (0);
3931 bfd_putl16 ((bfd_vma) hc.op0, frag);
3932 bfd_putl16 ((bfd_vma) hc.op1, frag+2);
3934 frag = frag_variant (rs_machine_dependent, 8, 2,
3935 ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */
3937 0, /* Offset is zero if jump dist less than 1K. */
3943 as_bad (_("instruction requires label"));
3947 as_bad (_("Illegal instruction or not implemented opcode."));
3950 if (is_opcode ("nop"))
3951 prev_insn_is_nop = TRUE;
3953 prev_insn_is_nop = FALSE;
3955 input_line_pointer = line;
3960 md_assemble (char * str)
3962 struct msp430_opcode_s * opcode;
3966 str = skip_space (str); /* Skip leading spaces. */
3967 str = extract_cmd (str, cmd, sizeof (cmd) - 1);
3971 char a = TOLOWER (cmd[i]);
3978 as_bad (_("can't find opcode"));
3982 opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);
3986 as_bad (_("unknown opcode `%s'"), cmd);
3991 char *__t = input_line_pointer;
3993 msp430_operands (opcode, str);
3994 input_line_pointer = __t;
3998 /* GAS will call this function for each section at the end of the assembly,
3999 to permit the CPU backend to adjust the alignment of a section. */
4002 md_section_align (asection * seg, valueT addr)
4004 int align = bfd_get_section_alignment (stdoutput, seg);
4006 return ((addr + (1 << align) - 1) & -(1 << align));
4009 /* If you define this macro, it should return the offset between the
4010 address of a PC relative fixup and the position from which the PC
4011 relative adjustment should be made. On many processors, the base
4012 of a PC relative instruction is the next instruction, so this
4013 macro would return the length of an instruction. */
4016 md_pcrel_from_section (fixS * fixp, segT sec)
4018 if (fixp->fx_addsy != (symbolS *) NULL
4019 && (!S_IS_DEFINED (fixp->fx_addsy)
4020 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
4023 return fixp->fx_frag->fr_address + fixp->fx_where;
4026 /* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
4027 Now it handles the situation when relocations
4028 have to be passed to linker. */
4030 msp430_force_relocation_local (fixS *fixp)
4032 if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL)
4036 if (msp430_enable_polys
4037 && !msp430_enable_relax)
4044 /* GAS will call this for each fixup. It should store the correct
4045 value in the object file. */
4047 md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
4049 unsigned char * where;
4053 if (fixp->fx_addsy == (symbolS *) NULL)
4058 else if (fixp->fx_pcrel)
4060 segT s = S_GET_SEGMENT (fixp->fx_addsy);
4062 if (fixp->fx_addsy && (s == seg || s == absolute_section))
4064 /* FIXME: We can appear here only in case if we perform a pc
4065 relative jump to the label which is i) global, ii) locally
4066 defined or this is a jump to an absolute symbol.
4067 If this is an absolute symbol -- everything is OK.
4068 If this is a global label, we've got a symbol value defined
4070 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
4071 from this section start
4072 2. *valuep will contain the real offset from jump insn to the
4074 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
4075 will be incorrect. Therefore remove s_get_value. */
4076 value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep;
4084 value = fixp->fx_offset;
4086 if (fixp->fx_subsy != (symbolS *) NULL)
4088 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4090 value -= S_GET_VALUE (fixp->fx_subsy);
4096 fixp->fx_no_overflow = 1;
4098 /* If polymorphs are enabled and relax disabled.
4099 do not kill any relocs and pass them to linker. */
4100 if (msp430_enable_polys
4101 && !msp430_enable_relax)
4104 || S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
4105 fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */
4112 /* Fetch the instruction, insert the fully resolved operand
4113 value, and stuff the instruction back again. */
4114 where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where;
4116 insn = bfd_getl16 (where);
4118 switch (fixp->fx_r_type)
4120 case BFD_RELOC_MSP430_10_PCREL:
4122 as_bad_where (fixp->fx_file, fixp->fx_line,
4123 _("odd address operand: %ld"), value);
4125 /* Jumps are in words. */
4127 --value; /* Correct PC. */
4129 if (value < -512 || value > 511)
4130 as_bad_where (fixp->fx_file, fixp->fx_line,
4131 _("operand out of range: %ld"), value);
4133 value &= 0x3ff; /* get rid of extended sign */
4134 bfd_putl16 ((bfd_vma) (value | insn), where);
4137 case BFD_RELOC_MSP430X_PCR16:
4138 case BFD_RELOC_MSP430_RL_PCREL:
4139 case BFD_RELOC_MSP430_16_PCREL:
4141 as_bad_where (fixp->fx_file, fixp->fx_line,
4142 _("odd address operand: %ld"), value);
4145 case BFD_RELOC_MSP430_16_PCREL_BYTE:
4146 /* Nothing to be corrected here. */
4147 if (value < -32768 || value > 65536)
4148 as_bad_where (fixp->fx_file, fixp->fx_line,
4149 _("operand out of range: %ld"), value);
4152 case BFD_RELOC_MSP430X_ABS16:
4153 case BFD_RELOC_MSP430_16:
4155 case BFD_RELOC_MSP430_16_BYTE:
4156 value &= 0xffff; /* Get rid of extended sign. */
4157 bfd_putl16 ((bfd_vma) value, where);
4160 case BFD_RELOC_MSP430_ABS_HI16:
4162 value &= 0xffff; /* Get rid of extended sign. */
4163 bfd_putl16 ((bfd_vma) value, where);
4167 bfd_putl16 ((bfd_vma) value, where);
4170 case BFD_RELOC_MSP430_ABS8:
4172 bfd_put_8 (NULL, (bfd_vma) value, where);
4175 case BFD_RELOC_MSP430X_ABS20_EXT_SRC:
4176 case BFD_RELOC_MSP430X_PCR20_EXT_SRC:
4177 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
4179 bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where);
4182 case BFD_RELOC_MSP430X_ABS20_ADR_SRC:
4183 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4185 bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where);
4188 case BFD_RELOC_MSP430X_ABS20_EXT_ODST:
4189 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4191 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4194 case BFD_RELOC_MSP430X_PCR20_CALL:
4195 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4197 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4200 case BFD_RELOC_MSP430X_ABS20_EXT_DST:
4201 case BFD_RELOC_MSP430X_PCR20_EXT_DST:
4202 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
4204 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4207 case BFD_RELOC_MSP430X_PCR20_EXT_ODST:
4208 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4210 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4213 case BFD_RELOC_MSP430X_ABS20_ADR_DST:
4214 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4216 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4220 as_fatal (_("line %d: unknown relocation type: 0x%x"),
4221 fixp->fx_line, fixp->fx_r_type);
4227 fixp->fx_addnumber = value;
4232 S_IS_GAS_LOCAL (symbolS * s)
4239 name = S_GET_NAME (s);
4240 len = strlen (name) - 1;
4242 return name[len] == 1 || name[len] == 2;
4245 /* GAS will call this to generate a reloc, passing the resulting reloc
4246 to `bfd_install_relocation'. This currently works poorly, as
4247 `bfd_install_relocation' often does the wrong thing, and instances of
4248 `tc_gen_reloc' have been written to work around the problems, which
4249 in turns makes it difficult to fix `bfd_install_relocation'. */
4251 /* If while processing a fixup, a reloc really needs to be created
4252 then it is done here. */
4255 tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
4257 static arelent * no_relocs = NULL;
4258 static arelent * relocs[MAX_RELOC_EXPANSION + 1];
4261 reloc = XNEW (arelent);
4262 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4263 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
4265 if (reloc->howto == (reloc_howto_type *) NULL)
4267 as_bad_where (fixp->fx_file, fixp->fx_line,
4268 _("reloc %d not supported by object file format"),
4269 (int) fixp->fx_r_type);
4278 && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4280 fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
4281 fixp->fx_subsy = NULL;
4284 if (fixp->fx_addsy && fixp->fx_subsy)
4286 asection *asec, *ssec;
4288 asec = S_GET_SEGMENT (fixp->fx_addsy);
4289 ssec = S_GET_SEGMENT (fixp->fx_subsy);
4291 /* If we have a difference between two different, non-absolute symbols
4292 we must generate two relocs (one for each symbol) and allow the
4293 linker to resolve them - relaxation may change the distances between
4294 symbols, even local symbols defined in the same section.
4296 Unfortunately we cannot do this with assembler generated local labels
4297 because there can be multiple incarnations of the same label, with
4298 exactly the same name, in any given section and the linker will have
4299 no way to identify the correct one. Instead we just have to hope
4300 that no relaxation will occur between the local label and the other
4301 symbol in the expression.
4303 Similarly we have to compute differences between symbols in the .eh_frame
4304 section as the linker is not smart enough to apply relocations there
4305 before attempting to process it. */
4306 if ((ssec != absolute_section || asec != absolute_section)
4307 && (fixp->fx_addsy != fixp->fx_subsy)
4308 && strcmp (ssec->name, ".eh_frame") != 0
4309 && ! S_IS_GAS_LOCAL (fixp->fx_addsy)
4310 && ! S_IS_GAS_LOCAL (fixp->fx_subsy))
4312 arelent * reloc2 = XNEW (arelent);
4317 reloc2->address = reloc->address;
4318 reloc2->howto = bfd_reloc_type_lookup (stdoutput,
4319 BFD_RELOC_MSP430_SYM_DIFF);
4320 reloc2->addend = - S_GET_VALUE (fixp->fx_subsy);
4322 if (ssec == absolute_section)
4323 reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4326 reloc2->sym_ptr_ptr = XNEW (asymbol *);
4327 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
4330 reloc->addend = fixp->fx_offset;
4331 if (asec == absolute_section)
4333 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
4334 reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4338 reloc->sym_ptr_ptr = XNEW (asymbol *);
4339 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4348 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4350 reloc->addend = (S_GET_VALUE (fixp->fx_addsy)
4351 - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset);
4353 switch (fixp->fx_r_type)
4356 md_number_to_chars (fixpos, reloc->addend, 1);
4360 md_number_to_chars (fixpos, reloc->addend, 2);
4364 md_number_to_chars (fixpos, reloc->addend, 3);
4368 md_number_to_chars (fixpos, reloc->addend, 4);
4373 = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
4384 if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16
4385 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
4387 bfd_vma amount = S_GET_VALUE (fixp->fx_addsy);
4388 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4390 md_number_to_chars (fixpos, amount, 2);
4395 reloc->sym_ptr_ptr = XNEW (asymbol *);
4396 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4397 reloc->addend = fixp->fx_offset;
4399 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4400 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4401 reloc->address = fixp->fx_offset;
4408 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
4409 asection * segment_type ATTRIBUTE_UNUSED)
4411 if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4413 /* This is a jump -> pcrel mode. Nothing to do much here.
4414 Return value == 2. */
4416 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10);
4418 else if (fragP->fr_symbol)
4420 /* It's got a segment, but it's not ours. Even if fr_symbol is in
4421 an absolute segment, we don't know a displacement until we link
4422 object files. So it will always be long. This also applies to
4423 labels in a subsegment of current. Liker may relax it to short
4424 jump later. Return value == 8. */
4426 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD);
4430 /* We know the abs value. may be it is a jump to fixed address.
4431 Impossible in our case, cause all constants already handled. */
4433 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF);
4436 return md_relax_table[fragP->fr_subtype].rlx_length;
4440 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
4441 asection * sec ATTRIBUTE_UNUSED,
4447 struct rcodes_s * cc = NULL;
4448 struct hcodes_s * hc = NULL;
4450 switch (fragP->fr_subtype)
4452 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10):
4453 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10):
4454 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10):
4455 /* We do not have to convert anything here.
4456 Just apply a fix. */
4457 rela = BFD_RELOC_MSP430_10_PCREL;
4460 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD):
4461 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF):
4462 /* Convert uncond branch jmp lab -> br lab. */
4463 if (target_is_430x ())
4464 cc = msp430x_rcodes + 7;
4466 cc = msp430_rcodes + 7;
4467 where = fragP->fr_literal + fragP->fr_fix;
4468 bfd_putl16 (cc->lop0, where);
4469 rela = BFD_RELOC_MSP430_RL_PCREL;
4473 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD):
4474 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF):
4476 /* Other simple branches. */
4477 int insn = bfd_getl16 (fragP->fr_opcode);
4480 /* Find actual instruction. */
4481 if (target_is_430x ())
4483 for (i = 0; i < 7 && !cc; i++)
4484 if (msp430x_rcodes[i].sop == insn)
4485 cc = msp430x_rcodes + i;
4489 for (i = 0; i < 7 && !cc; i++)
4490 if (msp430_rcodes[i].sop == insn)
4491 cc = & msp430_rcodes[i];
4494 if (!cc || !cc->name)
4495 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
4496 __FUNCTION__, (long) insn);
4497 where = fragP->fr_literal + fragP->fr_fix;
4498 bfd_putl16 (cc->lop0, where);
4499 bfd_putl16 (cc->lop1, where + 2);
4500 rela = BFD_RELOC_MSP430_RL_PCREL;
4505 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD):
4506 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF):
4507 if (target_is_430x ())
4508 cc = msp430x_rcodes + 6;
4510 cc = msp430_rcodes + 6;
4511 where = fragP->fr_literal + fragP->fr_fix;
4512 bfd_putl16 (cc->lop0, where);
4513 bfd_putl16 (cc->lop1, where + 2);
4514 bfd_putl16 (cc->lop2, where + 4);
4515 rela = BFD_RELOC_MSP430_RL_PCREL;
4519 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10):
4521 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4524 if (target_is_430x ())
4526 for (i = 0; i < 4 && !hc; i++)
4527 if (msp430x_hcodes[i].op1 == insn)
4528 hc = msp430x_hcodes + i;
4532 for (i = 0; i < 4 && !hc; i++)
4533 if (msp430_hcodes[i].op1 == insn)
4534 hc = &msp430_hcodes[i];
4536 if (!hc || !hc->name)
4537 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4538 __FUNCTION__, (long) insn);
4539 rela = BFD_RELOC_MSP430_10_PCREL;
4540 /* Apply a fix for a first label if necessary.
4541 another fix will be applied to the next word of insn anyway. */
4543 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4544 fragP->fr_offset, TRUE, rela);
4550 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD):
4551 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF):
4553 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4556 if (target_is_430x ())
4558 for (i = 0; i < 4 && !hc; i++)
4559 if (msp430x_hcodes[i].op1 == insn)
4560 hc = msp430x_hcodes + i;
4564 for (i = 0; i < 4 && !hc; i++)
4565 if (msp430_hcodes[i].op1 == insn)
4566 hc = & msp430_hcodes[i];
4568 if (!hc || !hc->name)
4569 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4570 __FUNCTION__, (long) insn);
4571 rela = BFD_RELOC_MSP430_RL_PCREL;
4572 where = fragP->fr_literal + fragP->fr_fix;
4573 bfd_putl16 (hc->lop0, where);
4574 bfd_putl16 (hc->lop1, where + 2);
4575 bfd_putl16 (hc->lop2, where + 4);
4581 as_fatal (_("internal inconsistency problem in %s: %lx"),
4582 __FUNCTION__, (long) fragP->fr_subtype);
4586 /* Now apply fix. */
4587 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4588 fragP->fr_offset, TRUE, rela);
4589 /* Just fixed 2 bytes. */
4593 /* Relax fragment. Mostly stolen from hc11 and mcore
4594 which arches I think I know. */
4597 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
4598 long stretch ATTRIBUTE_UNUSED)
4603 const relax_typeS *this_type;
4604 const relax_typeS *start_type;
4605 relax_substateT next_state;
4606 relax_substateT this_state;
4607 const relax_typeS *table = md_relax_table;
4609 /* Nothing to be done if the frag has already max size. */
4610 if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF
4611 || RELAX_STATE (fragP->fr_subtype) == STATE_WORD)
4614 if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10)
4616 symbolP = fragP->fr_symbol;
4617 if (symbol_resolved_p (symbolP))
4618 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
4620 /* We know the offset. calculate a distance. */
4621 aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix;
4624 if (!msp430_enable_relax)
4626 /* Relaxation is not enabled. So, make all jump as long ones
4627 by setting 'aim' to quite high value. */
4631 this_state = fragP->fr_subtype;
4632 start_type = this_type = table + this_state;
4636 /* Look backwards. */
4637 for (next_state = this_type->rlx_more; next_state;)
4638 if (aim >= this_type->rlx_backward || !this_type->rlx_backward)
4642 /* Grow to next state. */
4643 this_state = next_state;
4644 this_type = table + this_state;
4645 next_state = this_type->rlx_more;
4650 /* Look forwards. */
4651 for (next_state = this_type->rlx_more; next_state;)
4652 if (aim <= this_type->rlx_forward || !this_type->rlx_forward)
4656 /* Grow to next state. */
4657 this_state = next_state;
4658 this_type = table + this_state;
4659 next_state = this_type->rlx_more;
4663 growth = this_type->rlx_length - start_type->rlx_length;
4665 fragP->fr_subtype = this_state;
4669 /* Return FALSE if the fixup in fixp should be left alone and not
4670 adjusted. We return FALSE here so that linker relaxation will
4674 msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
4676 /* If the symbol is in a non-code section then it should be OK. */
4678 && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
4684 /* Set the contents of the .MSP430.attributes section. */
4687 msp430_md_end (void)
4690 as_warn ("assembly finished without a possibly needed NOP instruction");
4692 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
4693 target_is_430x () ? 2 : 1);
4695 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model,
4696 large_model ? 2 : 1);
4698 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model,
4699 large_model ? 2 : 1);
4702 /* Returns FALSE if there is a msp430 specific reason why the
4703 subtraction of two same-section symbols cannot be computed by
4707 msp430_allow_local_subtract (expressionS * left,
4708 expressionS * right,
4711 /* If the symbols are not in a code section then they are OK. */
4712 if ((section->flags & SEC_CODE) == 0)
4715 if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
4718 if (left->X_add_symbol == right->X_add_symbol)
4721 /* We have to assume that there may be instructions between the
4722 two symbols and that relaxation may increase the distance between