1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2013 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #define PUSH_1X_WORKAROUND
27 #include "opcode/msp430.h"
28 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "elf/msp430.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax;
70 int msp430_enable_polys;
72 /* Set linkrelax here to avoid fixups in most sections. */
75 /* GCC uses the some condition codes which we'll
76 implement as new polymorph instructions.
78 COND EXPL SHORT JUMP LONG JUMP
79 ===============================================
80 eq == jeq jne +4; br lab
81 ne != jne jeq +4; br lab
83 ltn honours no-overflow flag
84 ltn < jn jn +2; jmp +4; br lab
86 lt < jl jge +4; br lab
87 ltu < jlo lhs +4; br lab
93 ge >= jge jl +4; br lab
94 geu >= jhs jlo +4; br lab
95 ===============================================
97 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
98 beq,bne,blt,bltn,bltu,bge,bgeu
99 'u' means unsigned compares
101 Also, we add 'jump' instruction:
102 jump UNCOND -> jmp br lab
104 They will have fmt == 4, and insn_opnumb == number of instruction. */
109 int index; /* Corresponding insn_opnumb. */
110 int sop; /* Opcode if jump length is short. */
111 long lpos; /* Label position. */
112 long lop0; /* Opcode 1 _word_ (16 bits). */
113 long lop1; /* Opcode second word. */
114 long lop2; /* Opcode third word. */
117 #define MSP430_RLC(n,i,sop,o1) \
118 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
120 static struct rcodes_s msp430_rcodes[] =
122 MSP430_RLC (beq, 0, 0x2400, 0x2000),
123 MSP430_RLC (bne, 1, 0x2000, 0x2400),
124 MSP430_RLC (blt, 2, 0x3800, 0x3400),
125 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
126 MSP430_RLC (bge, 4, 0x3400, 0x3800),
127 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
128 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
129 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
134 #define MSP430_RLC(n,i,sop,o1) \
135 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
137 static struct rcodes_s msp430x_rcodes[] =
139 MSP430_RLC (beq, 0, 0x2400, 0x2000),
140 MSP430_RLC (bne, 1, 0x2000, 0x2400),
141 MSP430_RLC (blt, 2, 0x3800, 0x3400),
142 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
143 MSP430_RLC (bge, 4, 0x3400, 0x3800),
144 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
145 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
146 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
151 /* More difficult than above and they have format 5.
154 =================================================================
155 gt > jeq +2; jge label jeq +6; jl +4; br label
156 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
157 leu <= jeq label; jlo label jeq +2; jhs +4; br label
158 le <= jeq label; jl label jeq +2; jge +4; br label
159 ================================================================= */
164 int index; /* Corresponding insn_opnumb. */
165 int tlab; /* Number of labels in short mode. */
166 int op0; /* Opcode for first word of short jump. */
167 int op1; /* Opcode for second word of short jump. */
168 int lop0; /* Opcodes for long jump mode. */
173 static struct hcodes_s msp430_hcodes[] =
175 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
176 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
177 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
178 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
182 static struct hcodes_s msp430x_hcodes[] =
184 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
185 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
186 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
187 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
191 const char comment_chars[] = ";";
192 const char line_comment_chars[] = "#";
193 const char line_separator_chars[] = "{";
194 const char EXP_CHARS[] = "eE";
195 const char FLT_CHARS[] = "dD";
197 /* Handle long expressions. */
198 extern LITTLENUM_TYPE generic_bignum[];
200 static struct hash_control *msp430_hash;
203 #define STATE_UNCOND_BRANCH 1 /* jump */
204 #define STATE_NOOV_BRANCH 3 /* bltn */
205 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
206 #define STATE_EMUL_BRANCH 4
215 #define STATE_BITS10 1 /* wild guess. short jump */
216 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
217 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
219 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
220 #define RELAX_STATE(s) ((s) & 3)
221 #define RELAX_LEN(s) ((s) >> 2)
222 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
224 relax_typeS md_relax_table[] =
232 /* Unconditional jump. */
234 {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
235 {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */
236 {1, 1, CUBL, 0}, /* state undef */
238 /* Simple branches. */
240 {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
241 {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */
244 /* blt no overflow branch. */
246 {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
247 {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */
250 /* Emulated branches. */
252 {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
253 {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */
258 #define MAX_OP_LEN 256
267 #define MSP430_ISA_11 11
268 #define MSP430_ISA_110 110
269 #define MSP430_ISA_12 12
270 #define MSP430_ISA_13 13
271 #define MSP430_ISA_14 14
272 #define MSP430_ISA_15 15
273 #define MSP430_ISA_16 16
274 #define MSP430_ISA_20 20
275 #define MSP430_ISA_21 21
276 #define MSP430_ISA_22 22
277 #define MSP430_ISA_23 23
278 #define MSP430_ISA_24 24
279 #define MSP430_ISA_26 26
280 #define MSP430_ISA_31 31
281 #define MSP430_ISA_32 32
282 #define MSP430_ISA_33 33
283 #define MSP430_ISA_41 41
284 #define MSP430_ISA_42 42
285 #define MSP430_ISA_43 43
286 #define MSP430_ISA_44 44
287 #define MSP430X_ISA 45
288 #define MSP430_ISA_46 46
289 #define MSP430_ISA_47 47
290 #define MSP430_ISA_54 54
292 /* Generate a 16-bit relocation.
293 For the 430X we generate a relocation without linkwer range checking
294 if the value is being used in an extended (ie 20-bit) instruction.
295 For the 430 we generate a relocation without assembler range checking
296 if we are handling an immediate value or a byte-width instruction. */
297 #undef CHECK_RELOC_MSP430
298 #define CHECK_RELOC_MSP430 \
299 (msp430_mcu->isa == MSP430X_ISA \
300 ? (extended_op ? BFD_RELOC_16 : BFD_RELOC_MSP430X_ABS16) \
301 : ((imm_op || byte_op) \
302 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
304 /* Generate a 16-bit pc-relative relocation.
305 For the 430X we generate a relocation without linkwer range checking.
306 For the 430 we generate a relocation without assembler range checking
307 if we are handling an immediate value or a byte-width instruction. */
308 #undef CHECK_RELOC_MSP430_PCREL
309 #define CHECK_RELOC_MSP430_PCREL \
310 (msp430_mcu->isa == MSP430X_ISA \
311 ? BFD_RELOC_MSP430X_PCR16 \
312 : (imm_op || byte_op) \
313 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
315 static struct mcu_type_s mcu_types[] =
317 {"msp1", MSP430_ISA_11, bfd_mach_msp11},
318 {"msp2", MSP430_ISA_14, bfd_mach_msp14},
319 {"msp3", MSP430_ISA_20, bfd_mach_msp20},
320 {"msp4", MSP430_ISA_24, bfd_mach_msp24},
321 {"msp5", MSP430_ISA_31, bfd_mach_msp31},
322 {"msp6", MSP430_ISA_42, bfd_mach_msp42},
324 {"msp430x110", MSP430_ISA_11, bfd_mach_msp11},
325 {"msp430x112", MSP430_ISA_11, bfd_mach_msp11},
326 {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110},
327 {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110},
328 {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110},
329 {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110},
330 {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110},
332 {"msp430x122", MSP430_ISA_12, bfd_mach_msp12},
333 {"msp430x123", MSP430_ISA_12, bfd_mach_msp12},
334 {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12},
335 {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12},
337 {"msp430x133", MSP430_ISA_13, bfd_mach_msp13},
338 {"msp430x135", MSP430_ISA_13, bfd_mach_msp13},
339 {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13},
340 {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13},
341 {"msp430x147", MSP430_ISA_14, bfd_mach_msp14},
342 {"msp430x148", MSP430_ISA_14, bfd_mach_msp14},
343 {"msp430x149", MSP430_ISA_14, bfd_mach_msp14},
344 {"msp430x1471", MSP430_ISA_14, bfd_mach_msp14},
345 {"msp430x1481", MSP430_ISA_14, bfd_mach_msp14},
346 {"msp430x1491", MSP430_ISA_14, bfd_mach_msp14},
348 {"msp430x155", MSP430_ISA_15, bfd_mach_msp15},
349 {"msp430x156", MSP430_ISA_15, bfd_mach_msp15},
350 {"msp430x157", MSP430_ISA_15, bfd_mach_msp15},
351 {"msp430x167", MSP430_ISA_16, bfd_mach_msp16},
352 {"msp430x168", MSP430_ISA_16, bfd_mach_msp16},
353 {"msp430x169", MSP430_ISA_16, bfd_mach_msp16},
354 {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16},
355 {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16},
356 {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16},
358 {"msp430x2001", MSP430_ISA_20, bfd_mach_msp20},
359 {"msp430x2011", MSP430_ISA_20, bfd_mach_msp20},
360 {"msp430x2002", MSP430_ISA_20, bfd_mach_msp20},
361 {"msp430x2012", MSP430_ISA_20, bfd_mach_msp20},
362 {"msp430x2003", MSP430_ISA_20, bfd_mach_msp20},
363 {"msp430x2013", MSP430_ISA_20, bfd_mach_msp20 },
365 {"msp430x2101", MSP430_ISA_21, bfd_mach_msp21},
366 {"msp430x2111", MSP430_ISA_21, bfd_mach_msp21},
367 {"msp430x2112", MSP430_ISA_21, bfd_mach_msp21},
368 {"msp430x2121", MSP430_ISA_21, bfd_mach_msp21},
369 {"msp430x2131", MSP430_ISA_21, bfd_mach_msp21},
370 {"msp430x2132", MSP430_ISA_21, bfd_mach_msp21},
372 {"msp430x2232", MSP430_ISA_22, bfd_mach_msp22},
373 {"msp430x2234", MSP430_ISA_22, bfd_mach_msp22},
374 {"msp430x2252", MSP430_ISA_22, bfd_mach_msp22},
375 {"msp430x2254", MSP430_ISA_22, bfd_mach_msp22},
376 {"msp430x2272", MSP430_ISA_22, bfd_mach_msp22},
377 {"msp430x2274", MSP430_ISA_22, bfd_mach_msp22},
379 {"msp430x233", MSP430_ISA_23, bfd_mach_msp23},
380 {"msp430x235", MSP430_ISA_23, bfd_mach_msp23},
381 {"msp430x2330", MSP430_ISA_23, bfd_mach_msp23},
382 {"msp430x2350", MSP430_ISA_23, bfd_mach_msp23},
383 {"msp430x2370", MSP430_ISA_23, bfd_mach_msp23},
385 {"msp430x247", MSP430_ISA_24, bfd_mach_msp24},
386 {"msp430x2471", MSP430_ISA_24, bfd_mach_msp24},
387 {"msp430x248", MSP430_ISA_24, bfd_mach_msp24},
388 {"msp430x2481", MSP430_ISA_24, bfd_mach_msp24},
389 {"msp430x249", MSP430_ISA_24, bfd_mach_msp24},
390 {"msp430x2491", MSP430_ISA_24, bfd_mach_msp24},
391 {"msp430x2410", MSP430_ISA_24, bfd_mach_msp24},
392 {"msp430x2416", MSP430_ISA_24, bfd_mach_msp24},
393 {"msp430x2417", MSP430_ISA_24, bfd_mach_msp24},
394 {"msp430x2418", MSP430_ISA_24, bfd_mach_msp24},
395 {"msp430x2419", MSP430_ISA_24, bfd_mach_msp24},
397 {"msp430x2616", MSP430_ISA_26, bfd_mach_msp26},
398 {"msp430x2617", MSP430_ISA_26, bfd_mach_msp26},
399 {"msp430x2618", MSP430_ISA_26, bfd_mach_msp26},
400 {"msp430x2619", MSP430_ISA_26, bfd_mach_msp26},
402 {"msp430x311", MSP430_ISA_31, bfd_mach_msp31},
403 {"msp430x312", MSP430_ISA_31, bfd_mach_msp31},
404 {"msp430x313", MSP430_ISA_31, bfd_mach_msp31},
405 {"msp430x314", MSP430_ISA_31, bfd_mach_msp31},
406 {"msp430x315", MSP430_ISA_31, bfd_mach_msp31},
407 {"msp430x323", MSP430_ISA_32, bfd_mach_msp32},
408 {"msp430x325", MSP430_ISA_32, bfd_mach_msp32},
409 {"msp430x336", MSP430_ISA_33, bfd_mach_msp33},
410 {"msp430x337", MSP430_ISA_33, bfd_mach_msp33},
412 {"msp430x412", MSP430_ISA_41, bfd_mach_msp41},
413 {"msp430x413", MSP430_ISA_41, bfd_mach_msp41},
414 {"msp430x415", MSP430_ISA_41, bfd_mach_msp41},
415 {"msp430x417", MSP430_ISA_41, bfd_mach_msp41},
417 {"msp430x423", MSP430_ISA_42, bfd_mach_msp42},
418 {"msp430x425", MSP430_ISA_42, bfd_mach_msp42},
419 {"msp430x427", MSP430_ISA_42, bfd_mach_msp42},
420 {"msp430x4250", MSP430_ISA_42, bfd_mach_msp42},
421 {"msp430x4260", MSP430_ISA_42, bfd_mach_msp42},
422 {"msp430x4270", MSP430_ISA_42, bfd_mach_msp42},
423 {"msp430xG4250",MSP430_ISA_42, bfd_mach_msp42},
424 {"msp430xG4260",MSP430_ISA_42, bfd_mach_msp42},
425 {"msp430xG4270",MSP430_ISA_42, bfd_mach_msp42},
427 {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42},
428 {"msp430xE4232",MSP430_ISA_42, bfd_mach_msp42},
429 {"msp430xE4242",MSP430_ISA_42, bfd_mach_msp42},
430 {"msp430xE4252",MSP430_ISA_42, bfd_mach_msp42},
431 {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42},
432 {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42},
433 {"msp430xE4272",MSP430_ISA_42, bfd_mach_msp42},
435 {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42},
436 {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42},
437 {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42},
439 {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43},
440 {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43},
441 {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43},
443 {"msp430x435", MSP430_ISA_43, bfd_mach_msp43},
444 {"msp430x4351", MSP430_ISA_43, bfd_mach_msp43},
445 {"msp430x436", MSP430_ISA_43, bfd_mach_msp43},
446 {"msp430x4361", MSP430_ISA_43, bfd_mach_msp43},
447 {"msp430x437", MSP430_ISA_43, bfd_mach_msp43},
448 {"msp430x4371", MSP430_ISA_43, bfd_mach_msp43},
450 {"msp430x447", MSP430_ISA_44, bfd_mach_msp44},
451 {"msp430x448", MSP430_ISA_44, bfd_mach_msp44},
452 {"msp430x449", MSP430_ISA_44, bfd_mach_msp44},
454 {"msp430xG4616",MSP430_ISA_46, bfd_mach_msp46},
455 {"msp430xG4617",MSP430_ISA_46, bfd_mach_msp46},
456 {"msp430xG4618",MSP430_ISA_46, bfd_mach_msp46},
457 {"msp430xG4619",MSP430_ISA_46, bfd_mach_msp46},
459 {"msp430x4783", MSP430_ISA_47, bfd_mach_msp47},
460 {"msp430x4784", MSP430_ISA_47, bfd_mach_msp47},
461 {"msp430x4793", MSP430_ISA_47, bfd_mach_msp47},
462 {"msp430x4794", MSP430_ISA_47, bfd_mach_msp47},
463 {"msp430x47166",MSP430_ISA_47, bfd_mach_msp47},
464 {"msp430x47176",MSP430_ISA_47, bfd_mach_msp47},
465 {"msp430x47186",MSP430_ISA_47, bfd_mach_msp47},
466 {"msp430x47196",MSP430_ISA_47, bfd_mach_msp47},
467 {"msp430x47167",MSP430_ISA_47, bfd_mach_msp47},
468 {"msp430x47177",MSP430_ISA_47, bfd_mach_msp47},
469 {"msp430x47187",MSP430_ISA_47, bfd_mach_msp47},
470 {"msp430x47197",MSP430_ISA_47, bfd_mach_msp47},
472 {"msp430x5418", MSP430_ISA_54, bfd_mach_msp54},
473 {"msp430x5419", MSP430_ISA_54, bfd_mach_msp54},
474 {"msp430x5435", MSP430_ISA_54, bfd_mach_msp54},
475 {"msp430x5436", MSP430_ISA_54, bfd_mach_msp54},
476 {"msp430x5437", MSP430_ISA_54, bfd_mach_msp54},
477 {"msp430x5438", MSP430_ISA_54, bfd_mach_msp54},
479 {"msp430X", MSP430X_ISA, bfd_mach_msp430x},
485 static struct mcu_type_s default_mcu =
486 { "msp430x11", MSP430_ISA_11, bfd_mach_msp11 };
488 static struct mcu_type_s * msp430_mcu = & default_mcu;
490 /* Profiling capability:
491 It is a performance hit to use gcc's profiling approach for this tiny target.
492 Even more -- jtag hardware facility does not perform any profiling functions.
493 However we've got gdb's built-in simulator where we can do anything.
494 Therefore my suggestion is:
496 We define new section ".profiler" which holds all profiling information.
497 We define new pseudo operation .profiler which will instruct assembler to
498 add new profile entry to the object file. Profile should take place at the
503 .profiler flags,function_to_profile [, cycle_corrector, extra]
505 where 'flags' is a combination of the following chars:
508 i - function is in Init section
509 f - function is in Fini section
511 c - libC standard call
512 d - stack value Demand (saved at run-time in simulator)
513 I - Interrupt service routine
518 j - long Jump/ sjlj unwind
519 a - an Arbitrary code fragment
520 t - exTra parameter saved (constant value like frame size)
521 '""' optional: "sil" == sil
523 function_to_profile - function's address
524 cycle_corrector - a value which should be added to the cycle
525 counter, zero if omitted
526 extra - some extra parameter, zero if omitted.
529 ------------------------------
533 .LFrameOffset_fxx=0x08
534 .profiler "scdP", fxx ; function entry.
535 ; we also demand stack value to be displayed
540 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
541 ; (this is a prologue end)
542 ; note, that spare var filled with the frame size
545 .profiler cdE,fxx ; check stack
550 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
551 ret ; cause 'ret' insn takes 3 cycles
552 -------------------------------
554 This profiling approach does not produce any overhead and
556 So, even profiled code can be uploaded to the MCU. */
557 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
558 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
559 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
560 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
561 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
562 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
563 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
564 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
565 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
566 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
567 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
568 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
569 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
570 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
571 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
572 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
585 for (; x; x = x >> 1)
592 /* Parse ordinary expression. */
595 parse_exp (char * s, expressionS * op)
597 input_line_pointer = s;
599 if (op->X_op == O_absent)
600 as_bad (_("missing operand"));
601 return input_line_pointer;
605 /* Delete spaces from s: X ( r 1 2) => X(r12). */
608 del_spaces (char * s)
616 while (ISSPACE (*m) && *m)
618 memmove (s, m, strlen (m) + 1);
626 skip_space (char * s)
633 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
636 extract_operand (char * from, char * to, int limit)
640 /* Drop leading whitespace. */
641 from = skip_space (from);
643 while (size < limit && *from)
645 *(to + size) = *from;
646 if (*from == ',' || *from == ';' || *from == '\n')
661 msp430_profiler (int dummy ATTRIBUTE_UNUSED)
678 s = input_line_pointer;
679 end = input_line_pointer;
681 while (*end && *end != '\n')
684 while (*s && *s != '\n')
695 as_bad (_(".profiler pseudo requires at least two operands."));
696 input_line_pointer = end;
700 input_line_pointer = extract_operand (input_line_pointer, flags, 32);
709 p_flags |= MSP430_PROFILER_FLAG_FRAGMENT;
712 p_flags |= MSP430_PROFILER_FLAG_JUMP;
715 p_flags |= MSP430_PROFILER_FLAG_PROLSTART;
718 p_flags |= MSP430_PROFILER_FLAG_PROLEND;
721 p_flags |= MSP430_PROFILER_FLAG_EPISTART;
724 p_flags |= MSP430_PROFILER_FLAG_EPIEND;
727 p_flags |= MSP430_PROFILER_FLAG_ENTRY;
730 p_flags |= MSP430_PROFILER_FLAG_EXIT;
733 p_flags |= MSP430_PROFILER_FLAG_INITSECT;
736 p_flags |= MSP430_PROFILER_FLAG_FINISECT;
739 p_flags |= MSP430_PROFILER_FLAG_LIBCALL;
742 p_flags |= MSP430_PROFILER_FLAG_STDCALL;
745 p_flags |= MSP430_PROFILER_FLAG_STACKDMD;
748 p_flags |= MSP430_PROFILER_FLAG_ISR;
751 p_flags |= MSP430_PROFILER_FLAG_EXTRA;
754 as_warn (_("unknown profiling flag - ignored."));
761 && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY
762 | MSP430_PROFILER_FLAG_EXIT))
763 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART
764 | MSP430_PROFILER_FLAG_PROLEND
765 | MSP430_PROFILER_FLAG_EPISTART
766 | MSP430_PROFILER_FLAG_EPIEND))
767 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT
768 | MSP430_PROFILER_FLAG_FINISECT))))
770 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
771 input_line_pointer = end;
775 /* Generate temp symbol which denotes current location. */
776 if (now_seg == absolute_section) /* Paranoia ? */
778 exp1.X_op = O_constant;
779 exp1.X_add_number = abs_section_offset;
780 as_warn (_("profiling in absolute section?"));
784 exp1.X_op = O_symbol;
785 exp1.X_add_symbol = symbol_temp_new_now ();
786 exp1.X_add_number = 0;
789 /* Generate a symbol which holds flags value. */
790 exp.X_op = O_constant;
791 exp.X_add_number = p_flags;
793 /* Save current section. */
797 /* Now go to .profiler section. */
798 obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0);
801 emit_expr (& exp, 2);
803 /* Save label value. */
804 emit_expr (& exp1, 2);
808 /* Now get profiling info. */
809 halt = extract_operand (input_line_pointer, str, 1024);
810 /* Process like ".word xxx" directive. */
811 parse_exp (str, & exp);
812 emit_expr (& exp, 2);
813 input_line_pointer = halt;
816 /* Fill the rest with zeros. */
817 exp.X_op = O_constant;
818 exp.X_add_number = 0;
820 emit_expr (& exp, 2);
822 /* Return to current section. */
823 subseg_set (seg, subseg);
827 extract_word (char * from, char * to, int limit)
832 /* Drop leading whitespace. */
833 from = skip_space (from);
836 /* Find the op code end. */
837 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
839 to[size++] = *op_end++;
840 if (size + 1 >= limit)
848 #define OPTION_MMCU 'm'
849 #define OPTION_RELAX 'Q'
850 #define OPTION_POLYMORPHS 'P'
851 #define OPTION_LARGE 'l'
852 static bfd_boolean large_model = FALSE;
853 #define OPTION_NO_INTR_NOPS 'N'
854 static bfd_boolean gen_interrupt_nops = TRUE;
857 msp430_set_arch (int dummy ATTRIBUTE_UNUSED)
859 char *str = (char *) alloca (32); /* 32 for good measure. */
861 input_line_pointer = extract_word (input_line_pointer, str, 32);
863 md_parse_option (OPTION_MMCU, str);
864 bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);
868 show_mcu_list (FILE * stream)
872 fprintf (stream, _("Known MCU names:\n"));
874 for (i = 0; mcu_types[i].name; i++)
876 fprintf (stream, "%13.13s", mcu_types[i].name);
878 fprintf (stream, "\n");
881 fprintf (stream, "\n");
885 md_parse_option (int c, char * arg)
892 for (i = 0; mcu_types[i].name; ++i)
893 if (strcmp (mcu_types[i].name, arg) == 0)
896 if (!mcu_types[i].name)
898 show_mcu_list (stderr);
899 as_fatal (_("unknown MCU: %s\n"), arg);
902 if (msp430_mcu == &default_mcu || msp430_mcu->mach == mcu_types[i].mach)
903 msp430_mcu = &mcu_types[i];
904 else if (msp430_mcu->mach == bfd_mach_msp430x)
905 /* Allow switching to a lesser architecture. */
906 msp430_mcu = mcu_types + i;
908 as_fatal (_("redefinition of mcu type %s' to %s'"),
909 msp430_mcu->name, mcu_types[i].name);
913 msp430_enable_relax = 1;
916 case OPTION_POLYMORPHS:
917 msp430_enable_polys = 1;
924 case OPTION_NO_INTR_NOPS:
925 gen_interrupt_nops = FALSE;
933 const pseudo_typeS md_pseudo_table[] =
935 {"arch", msp430_set_arch, 0},
936 {"profiler", msp430_profiler, 0},
940 const char *md_shortopts = "m:";
942 struct option md_longopts[] =
944 {"mmcu", required_argument, NULL, OPTION_MMCU},
945 {"mP", no_argument, NULL, OPTION_POLYMORPHS},
946 {"mQ", no_argument, NULL, OPTION_RELAX},
947 {"ml", no_argument, NULL, OPTION_LARGE},
948 {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS},
949 {NULL, no_argument, NULL, 0}
952 size_t md_longopts_size = sizeof (md_longopts);
955 md_show_usage (FILE * stream)
958 _("MSP430 options:\n"
959 " -mmcu=<msp430-name> select microcontroller type\n"));
961 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
962 " -mP - enable polymorph instructions\n"));
964 _(" -ml - enable large code model\n"));
966 _(" -mN - disable generation of NOP after changing interrupts\n"));
968 show_mcu_list (stream);
972 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
978 extract_cmd (char * from, char * to, int limit)
982 while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)
984 *(to + size) = *from;
995 md_atof (int type, char * litP, int * sizeP)
997 return ieee_md_atof (type, litP, sizeP, FALSE);
1003 struct msp430_opcode_s * opcode;
1004 msp430_hash = hash_new ();
1006 for (opcode = msp430_opcodes; opcode->name; opcode++)
1007 hash_insert (msp430_hash, opcode->name, (char *) opcode);
1009 bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);
1012 /* Returns the register number equivalent to the string T.
1013 Returns -1 if there is no such register.
1014 Skips a leading 'r' or 'R' character if there is one.
1015 Handles the register aliases PC and SP. */
1018 check_reg (char * t)
1025 if (*t == 'r' || *t == 'R')
1028 if (strncasecmp (t, "pc", 2) == 0)
1031 if (strncasecmp (t, "sp", 2) == 0)
1034 if (strncasecmp (t, "sr", 2) == 0)
1042 if (val < 1 || val > 15)
1049 msp430_srcoperand (struct msp430_operand_s * op,
1053 bfd_boolean allow_20bit_values,
1054 bfd_boolean constants_allowed)
1058 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1065 /* Check if there is:
1066 llo(x) - least significant 16 bits, x &= 0xffff
1067 lhi(x) - x = (x >> 16) & 0xffff,
1068 hlo(x) - x = (x >> 32) & 0xffff,
1069 hhi(x) - x = (x >> 48) & 0xffff
1070 The value _MUST_ be constant expression: #hlo(1231231231). */
1074 if (strncasecmp (h, "#llo(", 5) == 0)
1079 else if (strncasecmp (h, "#lhi(", 5) == 0)
1084 else if (strncasecmp (h, "#hlo(", 5) == 0)
1089 else if (strncasecmp (h, "#hhi(", 5) == 0)
1094 else if (strncasecmp (h, "#lo(", 4) == 0)
1099 else if (strncasecmp (h, "#hi(", 4) == 0)
1105 op->reg = 0; /* Reg PC. */
1107 op->ol = 1; /* Immediate will follow an instruction. */
1108 __tl = h + 1 + rval;
1111 parse_exp (__tl, &(op->exp));
1112 if (op->exp.X_op == O_constant)
1114 int x = op->exp.X_add_number;
1119 op->exp.X_add_number = x;
1121 else if (vshift == 1)
1123 x = (x >> 16) & 0xffff;
1124 op->exp.X_add_number = x;
1126 else if (vshift > 1)
1129 op->exp.X_add_number = -1;
1131 op->exp.X_add_number = 0; /* Nothing left. */
1132 x = op->exp.X_add_number;
1135 if (allow_20bit_values)
1137 if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < - (0x7ffff))
1139 as_bad (_("value 0x%x out of extended range."), x);
1143 else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
1145 as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
1149 /* Now check constants. */
1150 /* Substitute register mode with a constant generator if applicable. */
1152 if (!allow_20bit_values)
1153 x = (short) x; /* Extend sign. */
1155 if (! constants_allowed)
1187 #ifdef PUSH_1X_WORKAROUND
1190 /* Remove warning as confusing.
1191 as_warn (_("Hardware push bug workaround")); */
1204 #ifdef PUSH_1X_WORKAROUND
1207 /* Remove warning as confusing.
1208 as_warn (_("Hardware push bug workaround")); */
1220 else if (op->exp.X_op == O_symbol)
1224 else if (op->exp.X_op == O_big)
1229 op->exp.X_op = O_constant;
1230 op->exp.X_add_number = 0xffff & generic_bignum[vshift];
1231 x = op->exp.X_add_number;
1236 ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
1284 /* Redundant (yet) check. */
1285 else if (op->exp.X_op == O_register)
1287 (_("Registers cannot be used within immediate expression [%s]"), l);
1289 as_bad (_("unknown operand %s"), l);
1294 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1299 op->reg = 2; /* reg 2 in absolute addr mode. */
1300 op->am = 1; /* mode As == 01 bin. */
1301 op->ol = 1; /* Immediate value followed by instruction. */
1303 parse_exp (__tl, &(op->exp));
1305 if (op->exp.X_op == O_constant)
1307 int x = op->exp.X_add_number;
1309 if (allow_20bit_values)
1311 if (x > 0xfffff || x < -(0x7ffff))
1313 as_bad (_("value 0x%x out of extended range."), x);
1317 else if (x > 65535 || x < -32768)
1319 as_bad (_("value out of range: 0x%x"), x);
1323 else if (op->exp.X_op == O_symbol)
1327 /* Redundant (yet) check. */
1328 if (op->exp.X_op == O_register)
1330 (_("Registers cannot be used within absolute expression [%s]"), l);
1332 as_bad (_("unknown expression in operand %s"), l);
1338 /* Check if indirect register mode @Rn / postincrement @Rn+. */
1342 char *m = strchr (l, '+');
1346 as_bad (_("unknown addressing mode %s"), l);
1352 if ((op->reg = check_reg (t)) == -1)
1354 as_bad (_("Bad register name %s"), t);
1365 /* Check if register indexed X(Rn). */
1368 char *h = strrchr (l, '(');
1369 char *m = strrchr (l, ')');
1378 as_bad (_("')' required"));
1386 /* Extract a register. */
1387 if ((op->reg = check_reg (t + 1)) == -1)
1390 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
1397 as_bad (_("r2 should not be used in indexed addressing mode"));
1401 /* Extract constant. */
1405 parse_exp (__tl, &(op->exp));
1406 if (op->exp.X_op == O_constant)
1408 int x = op->exp.X_add_number;
1410 if (allow_20bit_values)
1412 if (x > 0xfffff || x < - (0x7ffff))
1414 as_bad (_("value 0x%x out of extended range."), x);
1418 else if (x > 65535 || x < -32768)
1420 as_bad (_("value out of range: 0x%x"), x);
1432 else if (op->exp.X_op == O_symbol)
1436 /* Redundant (yet) check. */
1437 if (op->exp.X_op == O_register)
1439 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
1441 as_bad (_("unknown expression in operand %s"), l);
1449 /* Possibly register mode 'mov r1,r2'. */
1450 if ((op->reg = check_reg (l)) != -1)
1458 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
1462 op->reg = 0; /* PC relative... be careful. */
1463 /* An expression starting with a minus sign is a constant, not an address. */
1464 op->am = (*l == '-' ? 3 : 1);
1467 parse_exp (__tl, &(op->exp));
1473 as_bad (_("unknown addressing mode for operand %s"), l);
1479 msp430_dstoperand (struct msp430_operand_s * op,
1482 bfd_boolean allow_20bit_values,
1483 bfd_boolean constants_allowed)
1486 int ret = msp430_srcoperand (op, l, bin, & dummy,
1500 parse_exp (__tl, &(op->exp));
1502 if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
1504 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
1514 ("this addressing mode is not applicable for destination operand"));
1521 /* Attempt to encode a MOVA instruction with the given operands.
1522 Returns the length of the encoded instruction if successful
1523 or 0 upon failure. If the encoding fails, an error message
1524 will be returned if a pointer is provided. */
1527 try_encode_mova (bfd_boolean imm_op,
1529 struct msp430_operand_s * op1,
1530 struct msp430_operand_s * op2,
1531 const char ** error_message_return)
1537 /* Only a restricted subset of the normal MSP430 addressing modes
1538 are supported here, so check for the ones that are allowed. */
1541 if (op1->mode == OP_EXP)
1543 if (op2->mode != OP_REG)
1545 if (error_message_return != NULL)
1546 * error_message_return = _("expected register as second argument of %s");
1552 /* MOVA #imm20, Rdst. */
1553 bin |= 0x80 | op2->reg;
1554 frag = frag_more (4);
1555 where = frag - frag_now->fr_literal;
1556 if (op1->exp.X_op == O_constant)
1558 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
1559 bfd_putl16 ((bfd_vma) bin, frag);
1560 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
1564 bfd_putl16 ((bfd_vma) bin, frag);
1565 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
1566 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
1567 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
1572 else if (op1->am == 1)
1574 /* MOVA z16(Rsrc), Rdst. */
1575 bin |= 0x30 | (op1->reg << 8) | op2->reg;
1576 frag = frag_more (4);
1577 where = frag - frag_now->fr_literal;
1578 bfd_putl16 ((bfd_vma) bin, frag);
1579 if (op1->exp.X_op == O_constant)
1581 if (op1->exp.X_add_number > 0xffff
1582 || op1->exp.X_add_number < -(0x7fff))
1584 if (error_message_return != NULL)
1585 * error_message_return = _("index value too big for %s");
1588 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
1592 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
1593 fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
1595 BFD_RELOC_MSP430X_PCR16 :
1596 BFD_RELOC_MSP430X_ABS16);
1601 if (error_message_return != NULL)
1602 * error_message_return = _("unexpected addressing mode for %s");
1605 else if (op1->am == 0)
1607 /* MOVA Rsrc, ... */
1608 if (op2->mode == OP_REG)
1610 bin |= 0xc0 | (op1->reg << 8) | op2->reg;
1611 frag = frag_more (2);
1612 where = frag - frag_now->fr_literal;
1613 bfd_putl16 ((bfd_vma) bin, frag);
1616 else if (op2->am == 1)
1620 /* MOVA Rsrc, &abs20. */
1621 bin |= 0x60 | (op1->reg << 8);
1622 frag = frag_more (4);
1623 where = frag - frag_now->fr_literal;
1624 if (op2->exp.X_op == O_constant)
1626 bin |= (op2->exp.X_add_number >> 16) & 0xf;
1627 bfd_putl16 ((bfd_vma) bin, frag);
1628 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
1632 bfd_putl16 ((bfd_vma) bin, frag);
1633 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
1634 fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
1635 BFD_RELOC_MSP430X_ABS20_ADR_DST);
1640 /* MOVA Rsrc, z16(Rdst). */
1641 bin |= 0x70 | (op1->reg << 8) | op2->reg;
1642 frag = frag_more (4);
1643 where = frag - frag_now->fr_literal;
1644 bfd_putl16 ((bfd_vma) bin, frag);
1645 if (op2->exp.X_op == O_constant)
1647 if (op2->exp.X_add_number > 0xffff
1648 || op2->exp.X_add_number < -(0x7fff))
1650 if (error_message_return != NULL)
1651 * error_message_return = _("index value too big for %s");
1654 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
1658 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
1659 fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
1661 BFD_RELOC_MSP430X_PCR16 :
1662 BFD_RELOC_MSP430X_ABS16);
1667 if (error_message_return != NULL)
1668 * error_message_return = _("unexpected addressing mode for %s");
1673 /* imm_op == FALSE. */
1675 if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
1677 /* MOVA &abs20, Rdst. */
1678 if (op2->mode != OP_REG)
1680 if (error_message_return != NULL)
1681 * error_message_return = _("expected register as second argument of %s");
1685 if (op2->reg == 2 || op2->reg == 3)
1687 if (error_message_return != NULL)
1688 * error_message_return = _("constant generator destination register found in %s");
1692 bin |= 0x20 | op2->reg;
1693 frag = frag_more (4);
1694 where = frag - frag_now->fr_literal;
1695 if (op1->exp.X_op == O_constant)
1697 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
1698 bfd_putl16 ((bfd_vma) bin, frag);
1699 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
1703 bfd_putl16 ((bfd_vma) bin, frag);
1704 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
1705 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
1706 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
1710 else if (op1->mode == OP_REG)
1714 /* MOVA @Rsrc+, Rdst. */
1715 if (op2->mode != OP_REG)
1717 if (error_message_return != NULL)
1718 * error_message_return = _("expected register as second argument of %s");
1722 if (op2->reg == 2 || op2->reg == 3)
1724 if (error_message_return != NULL)
1725 * error_message_return = _("constant generator destination register found in %s");
1729 if (op1->reg == 2 || op1->reg == 3)
1731 if (error_message_return != NULL)
1732 * error_message_return = _("constant generator source register found in %s");
1736 bin |= 0x10 | (op1->reg << 8) | op2->reg;
1737 frag = frag_more (2);
1738 where = frag - frag_now->fr_literal;
1739 bfd_putl16 ((bfd_vma) bin, frag);
1742 else if (op1->am == 2)
1744 /* MOVA @Rsrc,Rdst */
1745 if (op2->mode != OP_REG)
1747 if (error_message_return != NULL)
1748 * error_message_return = _("expected register as second argument of %s");
1752 if (op2->reg == 2 || op2->reg == 3)
1754 if (error_message_return != NULL)
1755 * error_message_return = _("constant generator destination register found in %s");
1759 if (op1->reg == 2 || op1->reg == 3)
1761 if (error_message_return != NULL)
1762 * error_message_return = _("constant generator source register found in %s");
1766 bin |= (op1->reg << 8) | op2->reg;
1767 frag = frag_more (2);
1768 where = frag - frag_now->fr_literal;
1769 bfd_putl16 ((bfd_vma) bin, frag);
1774 if (error_message_return != NULL)
1775 * error_message_return = _("unexpected addressing mode for %s");
1780 /* Parse instruction operands.
1781 Return binary opcode. */
1784 msp430_operands (struct msp430_opcode_s * opcode, char * line)
1786 int bin = opcode->bin_opcode; /* Opcode mask. */
1787 int insn_length = 0;
1788 char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
1791 struct msp430_operand_s op1, op2;
1793 static short ZEROS = 0;
1794 int byte_op, imm_op;
1797 int extended = 0x1800;
1798 bfd_boolean extended_op = FALSE;
1799 bfd_boolean addr_op;
1800 const char * error_message;
1801 static signed int repeat_count = 0;
1802 bfd_boolean fix_emitted;
1804 /* Opcode is the one from opcodes table
1805 line contains something like
1810 /* Check if byte or word operation. */
1811 if (*line == '.' && TOLOWER (*(line + 1)) == 'b')
1813 bin |= BYTE_OPERATION;
1819 /* "Address" ops work on 20-bit values. */
1820 if (*line == '.' && TOLOWER (*(line + 1)) == 'a')
1823 bin |= BYTE_OPERATION;
1828 /* skip .[aAbwBW]. */
1829 while (! ISSPACE (*line) && *line)
1832 if (opcode->fmt != -1
1833 && opcode->insn_opnumb
1834 && (!*line || *line == '\n'))
1836 as_bad (_("instruction %s requires %d operand(s)"),
1837 opcode->name, opcode->insn_opnumb);
1841 memset (l1, 0, sizeof (l1));
1842 memset (l2, 0, sizeof (l2));
1843 memset (&op1, 0, sizeof (op1));
1844 memset (&op2, 0, sizeof (op2));
1848 if ((fmt = opcode->fmt) < 0)
1850 if (msp430_mcu->isa != MSP430X_ISA)
1852 as_bad (_("instruction %s requires MSP430X mcu"),
1863 /* If requested set the extended instruction repeat count. */
1866 if (repeat_count > 0)
1867 extended |= (repeat_count - 1);
1869 extended |= (1 << 7) | (- repeat_count);
1872 as_bad (_("unable to repeat %s insn"), opcode->name);
1879 case 0: /* Emulated. */
1880 switch (opcode->insn_opnumb)
1883 /* Set/clear bits instructions. */
1887 extended |= BYTE_OPERATION;
1889 /* Emit the extension word. */
1891 frag = frag_more (insn_length);
1892 bfd_putl16 (extended, frag);
1895 frag = frag_more (insn_length);
1896 bfd_putl16 ((bfd_vma) bin, frag);
1898 if (gen_interrupt_nops
1899 && msp430_mcu->isa == MSP430_ISA_54
1900 && (strcmp (opcode->name, "eint") == 0
1901 || strcmp (opcode->name, "dint") == 0))
1903 /* Emit a NOP following interrupt enable/disable.
1904 See 1.3.4.1 of the MSP430x5xx User Guide. */
1906 frag = frag_more (2);
1907 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
1910 dwarf2_emit_insn (insn_length);
1914 /* Something which works with destination operand. */
1915 line = extract_operand (line, l1, sizeof (l1));
1916 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
1920 /* Compute the entire instruction length, in bytes. */
1921 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
1922 frag = frag_more (insn_length);
1923 where = frag - frag_now->fr_literal;
1928 extended |= BYTE_OPERATION;
1930 if (op1.ol != 0 && ((extended & 0xf) != 0))
1932 as_bad (_("repeat instruction used with non-register mode instruction"));
1936 if (op1.mode == OP_EXP)
1938 if (op1.exp.X_op == O_constant)
1939 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
1941 else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
1942 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
1943 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
1945 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
1946 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
1949 /* Emit the extension word. */
1950 bfd_putl16 (extended, frag);
1955 bin |= (op1.reg | (op1.am << 7));
1956 bfd_putl16 ((bfd_vma) bin, frag);
1960 if (op1.mode == OP_EXP)
1962 if (op1.exp.X_op == O_constant)
1964 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
1968 bfd_putl16 ((bfd_vma) ZEROS, frag);
1973 fix_new_exp (frag_now, where, 2,
1974 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
1976 fix_new_exp (frag_now, where, 2,
1977 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
1982 if (gen_interrupt_nops
1983 && msp430_mcu->isa == MSP430_ISA_54
1984 && strcmp (opcode->name, "clr") == 0
1985 && bin == 0x4302 /* CLR R2*/)
1987 /* Emit a NOP following interrupt enable/disable.
1988 See 1.3.4.1 of the MSP430x5xx User Guide. */
1990 frag = frag_more (2);
1991 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
1994 dwarf2_emit_insn (insn_length);
1998 /* Shift instruction. */
1999 line = extract_operand (line, l1, sizeof (l1));
2000 strncpy (l2, l1, sizeof (l2));
2001 l2[sizeof (l2) - 1] = '\0';
2002 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
2003 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
2006 break; /* An error occurred. All warnings were done before. */
2008 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2);
2009 frag = frag_more (insn_length);
2010 where = frag - frag_now->fr_literal;
2015 extended |= BYTE_OPERATION;
2017 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
2019 as_bad (_("repeat instruction used with non-register mode instruction"));
2023 if (op1.mode == OP_EXP)
2025 if (op1.exp.X_op == O_constant)
2026 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2028 else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2029 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2030 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2032 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2033 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2036 if (op2.mode == OP_EXP)
2038 if (op2.exp.X_op == O_constant)
2039 extended |= (op2.exp.X_add_number >> 16) & 0xf;
2041 else if (op1.mode == OP_EXP)
2042 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
2043 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2044 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
2046 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
2047 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
2048 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
2051 /* Emit the extension word. */
2052 bfd_putl16 (extended, frag);
2057 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
2058 bfd_putl16 ((bfd_vma) bin, frag);
2062 if (op1.mode == OP_EXP)
2064 if (op1.exp.X_op == O_constant)
2066 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2070 bfd_putl16 ((bfd_vma) ZEROS, frag);
2074 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2075 fix_new_exp (frag_now, where, 2,
2076 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
2078 fix_new_exp (frag_now, where, 2,
2079 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2086 if (op2.mode == OP_EXP)
2088 if (op2.exp.X_op == O_constant)
2090 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
2094 bfd_putl16 ((bfd_vma) ZEROS, frag);
2098 if (op2.reg) /* Not PC relative. */
2099 fix_new_exp (frag_now, where, 2,
2100 &(op2.exp), FALSE, CHECK_RELOC_MSP430);
2102 fix_new_exp (frag_now, where, 2,
2103 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2108 dwarf2_emit_insn (insn_length);
2112 /* Branch instruction => mov dst, r0. */
2115 as_bad ("Internal error: state 0/3 not coded for extended instructions");
2119 line = extract_operand (line, l1, sizeof (l1));
2120 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
2126 bin |= ((op1.reg << 8) | (op1.am << 4));
2127 op_length = 2 + 2 * op1.ol;
2128 frag = frag_more (op_length);
2129 where = frag - frag_now->fr_literal;
2130 bfd_putl16 ((bfd_vma) bin, frag);
2132 if (op1.mode == OP_EXP)
2134 if (op1.exp.X_op == O_constant)
2136 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2);
2142 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2144 if (op1.reg || (op1.reg == 0 && op1.am == 3))
2145 fix_new_exp (frag_now, where, 2,
2146 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
2148 fix_new_exp (frag_now, where, 2,
2149 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2153 dwarf2_emit_insn (insn_length + op_length);
2157 /* CALLA instructions. */
2158 fix_emitted = FALSE;
2160 line = extract_operand (line, l1, sizeof (l1));
2163 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
2164 extended_op, FALSE);
2170 op_length = 2 + 2 * op1.ol;
2171 frag = frag_more (op_length);
2172 where = frag - frag_now->fr_literal;
2180 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
2181 BFD_RELOC_MSP430X_ABS20_ADR_DST);
2184 else if (op1.am == 1)
2190 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
2191 BFD_RELOC_MSP430X_PCR20_CALL);
2195 bin |= 0x50 | op1.reg;
2197 else if (op1.am == 0)
2198 bin |= 0x40 | op1.reg;
2200 else if (op1.am == 1)
2204 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
2205 BFD_RELOC_MSP430X_ABS20_ADR_DST);
2208 else if (op1.am == 2)
2209 bin |= 0x60 | op1.reg;
2210 else if (op1.am == 3)
2211 bin |= 0x70 | op1.reg;
2213 bfd_putl16 ((bfd_vma) bin, frag);
2215 if (op1.mode == OP_EXP)
2219 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol);
2223 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2226 fix_new_exp (frag_now, where + 2, 2,
2227 &(op1.exp), FALSE, BFD_RELOC_16);
2230 dwarf2_emit_insn (insn_length + op_length);
2238 /* [POP|PUSH]M[.A] #N, Rd */
2239 line = extract_operand (line, l1, sizeof (l1));
2240 line = extract_operand (line, l2, sizeof (l2));
2244 as_bad (_("expected #n as first argument of POPM"));
2247 parse_exp (l1 + 1, &(op1.exp));
2248 if (op1.exp.X_op != O_constant)
2250 as_bad (_("expected constant expression for first argument of %s"),
2255 if ((reg = check_reg (l2)) == -1)
2257 as_bad (_("expected register as second argument of %s"),
2263 frag = frag_more (op_length);
2264 where = frag - frag_now->fr_literal;
2265 bin = opcode->bin_opcode;
2268 n = op1.exp.X_add_number;
2269 bin |= (n - 1) << 4;
2270 if (strcmp (opcode->name, "pushm") == 0)
2274 if (reg - n + 1 < 0)
2276 as_bad (_("Too many registers popped"));
2279 bin |= (reg - n + 1);
2282 bfd_putl16 ((bfd_vma) bin, frag);
2283 dwarf2_emit_insn (op_length);
2292 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
2293 if (extended & 0xff)
2295 as_bad (_("repeat count cannot be used with %s"), opcode->name);
2299 line = extract_operand (line, l1, sizeof (l1));
2300 line = extract_operand (line, l2, sizeof (l2));
2304 as_bad (_("expected #n as first argument of %s"), opcode->name);
2307 parse_exp (l1 + 1, &(op1.exp));
2308 if (op1.exp.X_op != O_constant)
2310 as_bad (_("expected constant expression for first argument of %s"),
2314 n = op1.exp.X_add_number;
2317 as_bad (_("expected first argument of %s to be in the range 1-4"),
2322 if ((reg = check_reg (l2)) == -1)
2324 as_bad (_("expected register as second argument of %s"),
2330 frag = frag_more (op_length);
2331 where = frag - frag_now->fr_literal;
2333 bin = opcode->bin_opcode;
2336 bin |= (n - 1) << 10;
2339 bfd_putl16 ((bfd_vma) bin, frag);
2340 dwarf2_emit_insn (op_length);
2348 /* RRUX: Synthetic unsigned right shift of a register by one bit. */
2349 if (extended & 0xff)
2351 as_bad (_("repeat count cannot be used with %s"), opcode->name);
2355 line = extract_operand (line, l1, sizeof (l1));
2356 if ((reg = check_reg (l1)) == -1)
2358 as_bad (_("expected register as argument of %s"),
2365 /* Tricky - there is no single instruction that will do this.
2366 Encode as: RRA.B rN { BIC.B #0x80, rN */
2368 frag = frag_more (op_length);
2369 where = frag - frag_now->fr_literal;
2371 bfd_putl16 ((bfd_vma) bin, frag);
2372 dwarf2_emit_insn (2);
2374 bfd_putl16 ((bfd_vma) bin, frag + 2);
2376 bfd_putl16 ((bfd_vma) bin, frag + 4);
2377 dwarf2_emit_insn (4);
2381 /* Encode as RRUM[.A] rN. */
2382 bin = opcode->bin_opcode;
2387 frag = frag_more (op_length);
2388 where = frag - frag_now->fr_literal;
2389 bfd_putl16 ((bfd_vma) bin, frag);
2390 dwarf2_emit_insn (op_length);
2397 bfd_boolean need_reloc = FALSE;
2401 /* ADDA, CMPA and SUBA address instructions. */
2402 if (extended & 0xff)
2404 as_bad (_("repeat count cannot be used with %s"), opcode->name);
2408 line = extract_operand (line, l1, sizeof (l1));
2409 line = extract_operand (line, l2, sizeof (l2));
2411 bin = opcode->bin_opcode;
2415 parse_exp (l1 + 1, &(op1.exp));
2417 if (op1.exp.X_op == O_constant)
2419 n = op1.exp.X_add_number;
2420 if (n > 0xfffff || n < - (0x7ffff))
2422 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
2427 bin |= ((n >> 16) & 0xf) << 8;
2439 if ((n = check_reg (l1)) == -1)
2441 as_bad (_("expected register name or constant as first argument of %s"),
2446 bin |= (n << 8) | (1 << 6);
2450 if ((reg = check_reg (l2)) == -1)
2452 as_bad (_("expected register as second argument of %s"),
2457 frag = frag_more (op_length);
2458 where = frag - frag_now->fr_literal;
2461 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
2462 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2464 bfd_putl16 ((bfd_vma) bin, frag);
2466 bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2);
2467 dwarf2_emit_insn (op_length);
2471 case 9: /* MOVA, BRA, RETA. */
2473 bin = opcode->bin_opcode;
2475 if (strcmp (opcode->name, "reta") == 0)
2477 /* The RETA instruction does not take any arguments.
2478 The implicit first argument is @SP+.
2479 The implicit second argument is PC. */
2489 line = extract_operand (line, l1, sizeof (l1));
2490 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
2491 &imm_op, extended_op, FALSE);
2493 if (strcmp (opcode->name, "bra") == 0)
2495 /* This is the BRA synthetic instruction.
2496 The second argument is always PC. */
2502 line = extract_operand (line, l2, sizeof (l2));
2503 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
2508 break; /* Error occurred. All warnings were done before. */
2511 /* Only a restricted subset of the normal MSP430 addressing modes
2512 are supported here, so check for the ones that are allowed. */
2513 if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2,
2514 & error_message)) == 0)
2516 as_bad (error_message, opcode->name);
2519 dwarf2_emit_insn (op_length);
2523 line = extract_operand (line, l1, sizeof l1);
2524 /* The RPT instruction only accepted immediates and registers. */
2527 parse_exp (l1 + 1, &(op1.exp));
2528 if (op1.exp.X_op != O_constant)
2530 as_bad (_("expected constant value as argument to RPT"));
2533 if (op1.exp.X_add_number < 1
2534 || op1.exp.X_add_number > (1 << 4))
2536 as_bad (_("expected constant in the range 2..16"));
2540 /* We silently accept and ignore a repeat count of 1. */
2541 if (op1.exp.X_add_number > 1)
2542 repeat_count = op1.exp.X_add_number;
2548 if ((reg = check_reg (l1)) != -1)
2551 as_warn (_("PC used as an argument to RPT"));
2553 repeat_count = - reg;
2557 as_bad (_("expected constant or register name as argument to RPT insn"));
2564 as_bad (_("Illegal emulated instruction "));
2569 case 1: /* Format 1, double operand. */
2570 line = extract_operand (line, l1, sizeof (l1));
2571 line = extract_operand (line, l2, sizeof (l2));
2572 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
2573 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
2576 break; /* Error occurred. All warnings were done before. */
2579 && strcmp (opcode->name, "movx") == 0
2581 && msp430_enable_relax)
2583 /* This is the MOVX.A instruction. See if we can convert
2584 it into the MOVA instruction instead. This saves 2 bytes. */
2585 if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2,
2588 dwarf2_emit_insn (op_length);
2593 /* Compute the entire length of the instruction in bytes. */
2595 (extended_op ? 2 : 0) /* The extension word. */
2596 + 2 /* The opcode */
2597 + (2 * op1.ol) /* The first operand. */
2598 + (2 * op2.ol); /* The second operand. */
2600 frag = frag_more (insn_length);
2601 where = frag - frag_now->fr_literal;
2606 extended |= BYTE_OPERATION;
2608 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
2610 as_bad (_("repeat instruction used with non-register mode instruction"));
2614 /* If necessary, emit a reloc to update the extension word. */
2615 if (op1.mode == OP_EXP)
2617 if (op1.exp.X_op == O_constant)
2618 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2620 else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2621 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2622 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2624 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2625 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2628 if (op2.mode == OP_EXP)
2630 if (op2.exp.X_op == O_constant)
2631 extended |= (op2.exp.X_add_number >> 16) & 0xf;
2633 else if (op1.mode == OP_EXP)
2634 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
2635 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2636 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
2639 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
2640 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
2641 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
2644 /* Emit the extension word. */
2645 bfd_putl16 (extended, frag);
2650 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
2651 bfd_putl16 ((bfd_vma) bin, frag);
2655 if (op1.mode == OP_EXP)
2657 if (op1.exp.X_op == O_constant)
2659 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2663 bfd_putl16 ((bfd_vma) ZEROS, frag);
2667 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2668 fix_new_exp (frag_now, where, 2,
2669 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
2671 fix_new_exp (frag_now, where, 2,
2672 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2680 if (op2.mode == OP_EXP)
2682 if (op2.exp.X_op == O_constant)
2684 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
2688 bfd_putl16 ((bfd_vma) ZEROS, frag);
2692 if (op2.reg) /* Not PC relative. */
2693 fix_new_exp (frag_now, where, 2,
2694 &(op2.exp), FALSE, CHECK_RELOC_MSP430);
2696 fix_new_exp (frag_now, where, 2,
2697 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2702 if (gen_interrupt_nops
2703 && msp430_mcu->isa == MSP430_ISA_54
2704 && ( (strcmp (opcode->name, "bic") == 0 && bin == 0xc232)
2705 || (strcmp (opcode->name, "bis") == 0 && bin == 0xd232)
2706 || (strcmp (opcode->name, "mov") == 0 && op2.mode == OP_REG && op2.reg == 2)))
2708 /* Emit a NOP following interrupt enable/disable.
2709 See 1.3.4.1 of the MSP430x5xx User Guide. */
2711 frag = frag_more (2);
2712 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2715 dwarf2_emit_insn (insn_length);
2718 case 2: /* Single-operand mostly instr. */
2719 if (opcode->insn_opnumb == 0)
2721 /* reti instruction. */
2723 frag = frag_more (2);
2724 bfd_putl16 ((bfd_vma) bin, frag);
2725 dwarf2_emit_insn (insn_length);
2729 line = extract_operand (line, l1, sizeof (l1));
2730 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
2731 &imm_op, extended_op, TRUE);
2733 break; /* Error in operand. */
2735 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
2736 frag = frag_more (insn_length);
2737 where = frag - frag_now->fr_literal;
2741 if (strcmp (opcode->name, "swpbx") == 0
2742 || strcmp (opcode->name, "sxtx") == 0)
2744 /* These two instructions use a special
2745 encoding of the A/L and B/W bits. */
2746 bin &= ~ BYTE_OPERATION;
2750 as_bad (_("%s instruction does not accept a .b suffix"),
2755 extended |= BYTE_OPERATION;
2758 extended |= BYTE_OPERATION;
2760 if (op1.ol != 0 && ((extended & 0xf) != 0))
2762 as_bad (_("repeat instruction used with non-register mode instruction"));
2766 if (op1.mode == OP_EXP)
2768 if (op1.exp.X_op == O_constant)
2769 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
2771 else if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2772 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2773 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
2775 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
2776 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
2779 /* Emit the extension word. */
2780 bfd_putl16 (extended, frag);
2785 bin |= op1.reg | (op1.am << 4);
2786 bfd_putl16 ((bfd_vma) bin, frag);
2790 if (op1.mode == OP_EXP)
2792 if (op1.exp.X_op == O_constant)
2794 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
2798 bfd_putl16 ((bfd_vma) ZEROS, frag);
2802 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */
2803 fix_new_exp (frag_now, where, 2,
2804 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
2806 fix_new_exp (frag_now, where, 2,
2807 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
2812 dwarf2_emit_insn (insn_length);
2815 case 3: /* Conditional jumps instructions. */
2816 line = extract_operand (line, l1, sizeof (l1));
2817 /* l1 is a label. */
2826 parse_exp (m, &exp);
2828 /* In order to handle something like:
2832 jz 4 ; skip next 4 bytes
2835 nop ; will jump here if r5 positive or zero
2837 jCOND -n ;assumes jump n bytes backward:
2847 jCOND $n ; jump from PC in either direction. */
2849 if (exp.X_op == O_constant)
2851 int x = exp.X_add_number;
2855 as_warn (_("Even number required. Rounded to %d"), x + 1);
2859 if ((*l1 == '$' && x > 0) || x < 0)
2864 if (x > 512 || x < -511)
2866 as_bad (_("Wrong displacement %d"), x << 1);
2871 frag = frag_more (2); /* Instr size is 1 word. */
2874 bfd_putl16 ((bfd_vma) bin, frag);
2876 else if (exp.X_op == O_symbol && *l1 != '$')
2879 frag = frag_more (2); /* Instr size is 1 word. */
2880 where = frag - frag_now->fr_literal;
2881 fix_new_exp (frag_now, where, 2,
2882 &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
2884 bfd_putl16 ((bfd_vma) bin, frag);
2886 else if (*l1 == '$')
2888 as_bad (_("instruction requires label sans '$'"));
2892 ("instruction requires label or value in range -511:512"));
2893 dwarf2_emit_insn (insn_length);
2898 as_bad (_("instruction requires label"));
2903 case 4: /* Extended jumps. */
2904 if (!msp430_enable_polys)
2906 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
2910 line = extract_operand (line, l1, sizeof (l1));
2916 /* Ignore absolute addressing. make it PC relative anyway. */
2917 if (*m == '#' || *m == '$')
2920 parse_exp (m, & exp);
2921 if (exp.X_op == O_symbol)
2923 /* Relaxation required. */
2924 struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];
2926 if (msp430_mcu->isa == MSP430X_ISA)
2927 rc = msp430x_rcodes[opcode->insn_opnumb];
2929 /* The parameter to dwarf2_emit_insn is actually the offset to
2930 the start of the insn from the fix piece of instruction that
2931 was emitted. Since next fragments may have variable size we
2932 tie debug info to the beginning of the instruction. */
2934 frag = frag_more (8);
2935 dwarf2_emit_insn (0);
2936 bfd_putl16 ((bfd_vma) rc.sop, frag);
2937 frag = frag_variant (rs_machine_dependent, 8, 2,
2939 ENCODE_RELAX (rc.lpos, STATE_BITS10),
2941 0, /* Offset is zero if jump dist less than 1K. */
2947 as_bad (_("instruction requires label"));
2950 case 5: /* Emulated extended branches. */
2951 if (!msp430_enable_polys)
2953 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
2956 line = extract_operand (line, l1, sizeof (l1));
2962 /* Ignore absolute addressing. make it PC relative anyway. */
2963 if (*m == '#' || *m == '$')
2966 parse_exp (m, & exp);
2967 if (exp.X_op == O_symbol)
2969 /* Relaxation required. */
2970 struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];
2972 if (msp430_mcu->isa == MSP430X_ISA)
2973 hc = msp430x_hcodes[opcode->insn_opnumb];
2976 frag = frag_more (8);
2977 dwarf2_emit_insn (0);
2978 bfd_putl16 ((bfd_vma) hc.op0, frag);
2979 bfd_putl16 ((bfd_vma) hc.op1, frag+2);
2981 frag = frag_variant (rs_machine_dependent, 8, 2,
2982 ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */
2984 0, /* Offset is zero if jump dist less than 1K. */
2990 as_bad (_("instruction requires label"));
2994 as_bad (_("Illegal instruction or not implemented opcode."));
2997 input_line_pointer = line;
3002 md_assemble (char * str)
3004 struct msp430_opcode_s * opcode;
3008 str = skip_space (str); /* Skip leading spaces. */
3009 str = extract_cmd (str, cmd, sizeof (cmd));
3011 while (cmd[i] && i < sizeof (cmd))
3013 char a = TOLOWER (cmd[i]);
3020 as_bad (_("can't find opcode "));
3024 opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);
3028 as_bad (_("unknown opcode `%s'"), cmd);
3033 char *__t = input_line_pointer;
3035 msp430_operands (opcode, str);
3036 input_line_pointer = __t;
3040 /* GAS will call this function for each section at the end of the assembly,
3041 to permit the CPU backend to adjust the alignment of a section. */
3044 md_section_align (asection * seg, valueT addr)
3046 int align = bfd_get_section_alignment (stdoutput, seg);
3048 return ((addr + (1 << align) - 1) & (-1 << align));
3051 /* If you define this macro, it should return the offset between the
3052 address of a PC relative fixup and the position from which the PC
3053 relative adjustment should be made. On many processors, the base
3054 of a PC relative instruction is the next instruction, so this
3055 macro would return the length of an instruction. */
3058 md_pcrel_from_section (fixS * fixp, segT sec)
3060 if (fixp->fx_addsy != (symbolS *) NULL
3061 && (!S_IS_DEFINED (fixp->fx_addsy)
3062 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
3065 return fixp->fx_frag->fr_address + fixp->fx_where;
3068 /* Replaces standard TC_FORCE_RELOCATION_LOCAL.
3069 Now it handles the situation when relocations
3070 have to be passed to linker. */
3072 msp430_force_relocation_local (fixS *fixp)
3074 if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL)
3080 if (msp430_enable_polys
3081 && !msp430_enable_relax)
3084 return (!fixp->fx_pcrel
3085 || generic_force_reloc (fixp));
3089 /* GAS will call this for each fixup. It should store the correct
3090 value in the object file. */
3092 md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
3094 unsigned char * where;
3098 if (fixp->fx_addsy == (symbolS *) NULL)
3103 else if (fixp->fx_pcrel)
3105 segT s = S_GET_SEGMENT (fixp->fx_addsy);
3107 if (fixp->fx_addsy && (s == seg || s == absolute_section))
3109 /* FIXME: We can appear here only in case if we perform a pc
3110 relative jump to the label which is i) global, ii) locally
3111 defined or this is a jump to an absolute symbol.
3112 If this is an absolute symbol -- everything is OK.
3113 If this is a global label, we've got a symbol value defined
3115 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
3116 from this section start
3117 2. *valuep will contain the real offset from jump insn to the
3119 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
3120 will be incorrect. Therefore remove s_get_value. */
3121 value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep;
3129 value = fixp->fx_offset;
3131 if (fixp->fx_subsy != (symbolS *) NULL)
3133 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
3135 value -= S_GET_VALUE (fixp->fx_subsy);
3141 fixp->fx_no_overflow = 1;
3143 /* If polymorphs are enabled and relax disabled.
3144 do not kill any relocs and pass them to linker. */
3145 if (msp430_enable_polys
3146 && !msp430_enable_relax)
3148 if (!fixp->fx_addsy || (fixp->fx_addsy
3149 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section))
3150 fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */
3157 /* Fetch the instruction, insert the fully resolved operand
3158 value, and stuff the instruction back again. */
3159 where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where;
3161 insn = bfd_getl16 (where);
3163 switch (fixp->fx_r_type)
3165 case BFD_RELOC_MSP430_10_PCREL:
3167 as_bad_where (fixp->fx_file, fixp->fx_line,
3168 _("odd address operand: %ld"), value);
3170 /* Jumps are in words. */
3172 --value; /* Correct PC. */
3174 if (value < -512 || value > 511)
3175 as_bad_where (fixp->fx_file, fixp->fx_line,
3176 _("operand out of range: %ld"), value);
3178 value &= 0x3ff; /* get rid of extended sign */
3179 bfd_putl16 ((bfd_vma) (value | insn), where);
3182 case BFD_RELOC_MSP430X_PCR16:
3183 case BFD_RELOC_MSP430_RL_PCREL:
3184 case BFD_RELOC_MSP430_16_PCREL:
3186 as_bad_where (fixp->fx_file, fixp->fx_line,
3187 _("odd address operand: %ld"), value);
3190 case BFD_RELOC_MSP430_16_PCREL_BYTE:
3191 /* Nothing to be corrected here. */
3192 if (value < -32768 || value > 65536)
3193 as_bad_where (fixp->fx_file, fixp->fx_line,
3194 _("operand out of range: %ld"), value);
3197 case BFD_RELOC_MSP430X_ABS16:
3198 case BFD_RELOC_MSP430_16:
3200 case BFD_RELOC_MSP430_16_BYTE:
3201 value &= 0xffff; /* Get rid of extended sign. */
3202 bfd_putl16 ((bfd_vma) value, where);
3206 bfd_putl16 ((bfd_vma) value, where);
3209 case BFD_RELOC_MSP430_ABS8:
3211 bfd_put_8 (NULL, (bfd_vma) value, where);
3214 case BFD_RELOC_MSP430X_ABS20_EXT_SRC:
3215 case BFD_RELOC_MSP430X_PCR20_EXT_SRC:
3216 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
3218 bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where);
3221 case BFD_RELOC_MSP430X_ABS20_ADR_SRC:
3222 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
3224 bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where);
3227 case BFD_RELOC_MSP430X_ABS20_EXT_ODST:
3228 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
3230 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
3233 case BFD_RELOC_MSP430X_PCR20_CALL:
3234 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
3236 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
3239 case BFD_RELOC_MSP430X_ABS20_EXT_DST:
3240 case BFD_RELOC_MSP430X_PCR20_EXT_DST:
3241 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
3243 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
3246 case BFD_RELOC_MSP430X_PCR20_EXT_ODST:
3247 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
3249 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
3252 case BFD_RELOC_MSP430X_ABS20_ADR_DST:
3253 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
3255 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
3259 as_fatal (_("line %d: unknown relocation type: 0x%x"),
3260 fixp->fx_line, fixp->fx_r_type);
3266 fixp->fx_addnumber = value;
3271 S_IS_GAS_LOCAL (symbolS * s)
3278 name = S_GET_NAME (s);
3279 len = strlen (name) - 1;
3281 return name[len] == 1 || name[len] == 2;
3284 /* GAS will call this to generate a reloc, passing the resulting reloc
3285 to `bfd_install_relocation'. This currently works poorly, as
3286 `bfd_install_relocation' often does the wrong thing, and instances of
3287 `tc_gen_reloc' have been written to work around the problems, which
3288 in turns makes it difficult to fix `bfd_install_relocation'. */
3290 /* If while processing a fixup, a reloc really needs to be created
3291 then it is done here. */
3294 tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
3296 static arelent * no_relocs = NULL;
3297 static arelent * relocs[MAX_RELOC_EXPANSION + 1];
3300 reloc = xmalloc (sizeof (arelent));
3301 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3302 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3304 if (reloc->howto == (reloc_howto_type *) NULL)
3306 as_bad_where (fixp->fx_file, fixp->fx_line,
3307 _("reloc %d not supported by object file format"),
3308 (int) fixp->fx_r_type);
3317 && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
3319 fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
3320 fixp->fx_subsy = NULL;
3323 if (fixp->fx_addsy && fixp->fx_subsy)
3325 asection *asec, *ssec;
3327 asec = S_GET_SEGMENT (fixp->fx_addsy);
3328 ssec = S_GET_SEGMENT (fixp->fx_subsy);
3330 /* If we have a difference between two different, non-absolute symbols
3331 we must generate two relocs (one for each symbol) and allow the
3332 linker to resolve them - relaxation may change the distances between
3333 symbols, even local symbols defined in the same section.
3335 Unfortunately we cannot do this with assembler generated local labels
3336 because there can be multiple incarnations of the same label, with
3337 exactly the same name, in any given section and the linker will have
3338 no way to identify the correct one. Instead we just have to hope
3339 that no relaxtion will occur between the local label and the other
3340 symbol in the expression.
3342 Similarly we have to compute differences between symbols in the .eh_frame
3343 section as the linker is not smart enough to apply relocations there
3344 before attempting to process it. */
3345 if ((ssec != absolute_section || asec != absolute_section)
3346 && (fixp->fx_addsy != fixp->fx_subsy)
3347 && strcmp (ssec->name, ".eh_frame") != 0
3348 && ! S_IS_GAS_LOCAL (fixp->fx_addsy)
3349 && ! S_IS_GAS_LOCAL (fixp->fx_subsy))
3351 arelent * reloc2 = xmalloc (sizeof * reloc);
3356 reloc2->address = reloc->address;
3357 reloc2->howto = bfd_reloc_type_lookup (stdoutput,
3358 BFD_RELOC_MSP430_SYM_DIFF);
3359 reloc2->addend = - S_GET_VALUE (fixp->fx_subsy);
3361 if (ssec == absolute_section)
3362 reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
3365 reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3366 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
3369 reloc->addend = fixp->fx_offset;
3370 if (asec == absolute_section)
3372 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
3373 reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
3377 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3378 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3387 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
3389 reloc->addend = (S_GET_VALUE (fixp->fx_addsy)
3390 - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset);
3392 switch (fixp->fx_r_type)
3395 md_number_to_chars (fixpos, reloc->addend, 1);
3399 md_number_to_chars (fixpos, reloc->addend, 2);
3403 md_number_to_chars (fixpos, reloc->addend, 3);
3407 md_number_to_chars (fixpos, reloc->addend, 4);
3412 = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
3423 if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16
3424 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
3426 bfd_vma amount = S_GET_VALUE (fixp->fx_addsy);
3427 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
3429 md_number_to_chars (fixpos, amount, 2);
3434 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3435 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3436 reloc->addend = fixp->fx_offset;
3438 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3439 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3440 reloc->address = fixp->fx_offset;
3447 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
3448 asection * segment_type ATTRIBUTE_UNUSED)
3450 if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
3452 /* This is a jump -> pcrel mode. Nothing to do much here.
3453 Return value == 2. */
3455 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10);
3457 else if (fragP->fr_symbol)
3459 /* Its got a segment, but its not ours. Even if fr_symbol is in
3460 an absolute segment, we don't know a displacement until we link
3461 object files. So it will always be long. This also applies to
3462 labels in a subsegment of current. Liker may relax it to short
3463 jump later. Return value == 8. */
3465 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD);
3469 /* We know the abs value. may be it is a jump to fixed address.
3470 Impossible in our case, cause all constants already handled. */
3472 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF);
3475 return md_relax_table[fragP->fr_subtype].rlx_length;
3479 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
3480 asection * sec ATTRIBUTE_UNUSED,
3486 struct rcodes_s * cc = NULL;
3487 struct hcodes_s * hc = NULL;
3489 switch (fragP->fr_subtype)
3491 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10):
3492 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10):
3493 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10):
3494 /* We do not have to convert anything here.
3495 Just apply a fix. */
3496 rela = BFD_RELOC_MSP430_10_PCREL;
3499 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD):
3500 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF):
3501 /* Convert uncond branch jmp lab -> br lab. */
3502 cc = & msp430_rcodes[7];
3503 if (msp430_mcu->isa == MSP430X_ISA)
3504 cc = msp430x_rcodes + 7;
3505 where = fragP->fr_literal + fragP->fr_fix;
3506 bfd_putl16 (cc->lop0, where);
3507 rela = BFD_RELOC_MSP430_RL_PCREL;
3511 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD):
3512 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF):
3514 /* Other simple branches. */
3515 int insn = bfd_getl16 (fragP->fr_opcode);
3518 /* Find actual instruction. */
3519 if (msp430_mcu->isa == MSP430X_ISA)
3521 for (i = 0; i < 7 && !cc; i++)
3522 if (msp430x_rcodes[i].sop == insn)
3523 cc = msp430x_rcodes + i;
3527 for (i = 0; i < 7 && !cc; i++)
3528 if (msp430_rcodes[i].sop == insn)
3529 cc = & msp430_rcodes[i];
3532 if (!cc || !cc->name)
3533 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
3534 __FUNCTION__, (long) insn);
3535 where = fragP->fr_literal + fragP->fr_fix;
3536 bfd_putl16 (cc->lop0, where);
3537 bfd_putl16 (cc->lop1, where + 2);
3538 rela = BFD_RELOC_MSP430_RL_PCREL;
3543 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD):
3544 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF):
3545 cc = & msp430_rcodes[6];
3547 if (msp430_mcu->isa == MSP430X_ISA)
3548 cc = msp430x_rcodes + 6;
3550 where = fragP->fr_literal + fragP->fr_fix;
3551 bfd_putl16 (cc->lop0, where);
3552 bfd_putl16 (cc->lop1, where + 2);
3553 bfd_putl16 (cc->lop2, where + 4);
3554 rela = BFD_RELOC_MSP430_RL_PCREL;
3558 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10):
3560 int insn = bfd_getl16 (fragP->fr_opcode + 2);
3563 if (msp430_mcu->isa == MSP430X_ISA)
3565 for (i = 0; i < 4 && !hc; i++)
3566 if (msp430x_hcodes[i].op1 == insn)
3567 hc = msp430x_hcodes + i;
3571 for (i = 0; i < 4 && !hc; i++)
3572 if (msp430_hcodes[i].op1 == insn)
3573 hc = &msp430_hcodes[i];
3576 if (!hc || !hc->name)
3577 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3578 __FUNCTION__, (long) insn);
3579 rela = BFD_RELOC_MSP430_10_PCREL;
3580 /* Apply a fix for a first label if necessary.
3581 another fix will be applied to the next word of insn anyway. */
3583 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3584 fragP->fr_offset, TRUE, rela);
3590 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD):
3591 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF):
3593 int insn = bfd_getl16 (fragP->fr_opcode + 2);
3596 if (msp430_mcu->isa == MSP430X_ISA)
3598 for (i = 0; i < 4 && !hc; i++)
3599 if (msp430x_hcodes[i].op1 == insn)
3600 hc = msp430x_hcodes + i;
3604 for (i = 0; i < 4 && !hc; i++)
3605 if (msp430_hcodes[i].op1 == insn)
3606 hc = & msp430_hcodes[i];
3608 if (!hc || !hc->name)
3609 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3610 __FUNCTION__, (long) insn);
3611 rela = BFD_RELOC_MSP430_RL_PCREL;
3612 where = fragP->fr_literal + fragP->fr_fix;
3613 bfd_putl16 (hc->lop0, where);
3614 bfd_putl16 (hc->lop1, where + 2);
3615 bfd_putl16 (hc->lop2, where + 4);
3621 as_fatal (_("internal inconsistency problem in %s: %lx"),
3622 __FUNCTION__, (long) fragP->fr_subtype);
3626 /* Now apply fix. */
3627 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3628 fragP->fr_offset, TRUE, rela);
3629 /* Just fixed 2 bytes. */
3633 /* Relax fragment. Mostly stolen from hc11 and mcore
3634 which arches I think I know. */
3637 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
3638 long stretch ATTRIBUTE_UNUSED)
3643 const relax_typeS *this_type;
3644 const relax_typeS *start_type;
3645 relax_substateT next_state;
3646 relax_substateT this_state;
3647 const relax_typeS *table = md_relax_table;
3649 /* Nothing to be done if the frag has already max size. */
3650 if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF
3651 || RELAX_STATE (fragP->fr_subtype) == STATE_WORD)
3654 if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10)
3656 symbolP = fragP->fr_symbol;
3657 if (symbol_resolved_p (symbolP))
3658 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3660 /* We know the offset. calculate a distance. */
3661 aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix;
3664 if (!msp430_enable_relax)
3666 /* Relaxation is not enabled. So, make all jump as long ones
3667 by setting 'aim' to quite high value. */
3671 this_state = fragP->fr_subtype;
3672 start_type = this_type = table + this_state;
3676 /* Look backwards. */
3677 for (next_state = this_type->rlx_more; next_state;)
3678 if (aim >= this_type->rlx_backward || !this_type->rlx_backward)
3682 /* Grow to next state. */
3683 this_state = next_state;
3684 this_type = table + this_state;
3685 next_state = this_type->rlx_more;
3690 /* Look forwards. */
3691 for (next_state = this_type->rlx_more; next_state;)
3692 if (aim <= this_type->rlx_forward || !this_type->rlx_forward)
3696 /* Grow to next state. */
3697 this_state = next_state;
3698 this_type = table + this_state;
3699 next_state = this_type->rlx_more;
3703 growth = this_type->rlx_length - start_type->rlx_length;
3705 fragP->fr_subtype = this_state;
3709 /* Return FALSE if the fixup in fixp should be left alone and not
3710 adjusted. We return FALSE here so that linker relaxation will
3714 msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
3716 /* If the symbol is in a non-code section then it should be OK. */
3718 && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
3724 /* Set the contents of the .MSP430.attributes section. */
3727 msp430_md_end (void)
3729 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
3730 msp430_mcu->isa == MSP430X_ISA ? 2 : 1);
3732 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model,
3733 large_model ? 2 : 1);
3735 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model,
3736 large_model ? 2 : 1);
3739 /* Returns FALSE if there is a msp430 specific reason why the
3740 subtraction of two same-section symbols cannot be computed by
3744 msp430_allow_local_subtract (expressionS * left,
3745 expressionS * right,
3748 /* If the symbols are not in a code section then they are OK. */
3749 if ((section->flags & SEC_CODE) == 0)
3752 if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
3755 if (left->X_add_symbol == right->X_add_symbol)
3758 /* We have to assume that there may be instructions between the
3759 two symbols and that relaxation may increase the distance between