1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug = -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr = FALSE;
82 int mips_flag_pdr = TRUE;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode *insn_mo;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p : 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p : 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p : 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi = NO_ABI;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls = FALSE;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared = TRUE;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32 = -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32 = -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float = 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float = 0;
265 static struct mips_set_options mips_opts =
267 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
272 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask;
279 unsigned long mips_cprmask[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa = ISA_UNKNOWN;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch = CPU_UNKNOWN;
333 static const char *mips_arch_string;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune = CPU_UNKNOWN;
338 static const char *mips_tune_string;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode = 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got = 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap = 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value = 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen = 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS *, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control *op_hash = NULL;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control *mips16_op_hash = NULL;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error;
612 static int auto_align = 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset = -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset = -1;
624 static int mips_cpreturn_register = -1;
625 static int mips_gp_register = GP;
626 static int mips_gprel_offset = 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid = 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg = SP;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid = 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize = 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug = 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history[1 + MAX_NOPS];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn, mips16_nop_insn;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS *prev_nop_frag;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup *next;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup *mips_hi_fixup_list;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS *prev_reloc_op_frag;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map[] =
726 X, X, 2, 3, 4, 5, 6, 7,
727 X, X, X, X, X, X, X, X,
728 0, 1, X, X, X, X, X, X,
729 X, X, X, X, X, X, X, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class {
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130;
763 /* ...likewise -mfix-24k. */
764 static int mips_fix_24k;
766 /* We don't relax branches by default, since this causes us to expand
767 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
768 fail to compute the offset before expanding the macro to the most
769 efficient expansion. */
771 static int mips_relax_branch;
773 /* The expansion of many macros depends on the type of symbol that
774 they refer to. For example, when generating position-dependent code,
775 a macro that refers to a symbol may have two different expansions,
776 one which uses GP-relative addresses and one which uses absolute
777 addresses. When generating SVR4-style PIC, a macro may have
778 different expansions for local and global symbols.
780 We handle these situations by generating both sequences and putting
781 them in variant frags. In position-dependent code, the first sequence
782 will be the GP-relative one and the second sequence will be the
783 absolute one. In SVR4 PIC, the first sequence will be for global
784 symbols and the second will be for local symbols.
786 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
787 SECOND are the lengths of the two sequences in bytes. These fields
788 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
789 the subtype has the following flags:
792 Set if it has been decided that we should use the second
793 sequence instead of the first.
796 Set in the first variant frag if the macro's second implementation
797 is longer than its first. This refers to the macro as a whole,
798 not an individual relaxation.
801 Set in the first variant frag if the macro appeared in a .set nomacro
802 block and if one alternative requires a warning but the other does not.
805 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
808 The frag's "opcode" points to the first fixup for relaxable code.
810 Relaxable macros are generated using a sequence such as:
812 relax_start (SYMBOL);
813 ... generate first expansion ...
815 ... generate second expansion ...
818 The code and fixups for the unwanted alternative are discarded
819 by md_convert_frag. */
820 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
822 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
823 #define RELAX_SECOND(X) ((X) & 0xff)
824 #define RELAX_USE_SECOND 0x10000
825 #define RELAX_SECOND_LONGER 0x20000
826 #define RELAX_NOMACRO 0x40000
827 #define RELAX_DELAY_SLOT 0x80000
829 /* Branch without likely bit. If label is out of range, we turn:
831 beq reg1, reg2, label
841 with the following opcode replacements:
848 bltzal <-> bgezal (with jal label instead of j label)
850 Even though keeping the delay slot instruction in the delay slot of
851 the branch would be more efficient, it would be very tricky to do
852 correctly, because we'd have to introduce a variable frag *after*
853 the delay slot instruction, and expand that instead. Let's do it
854 the easy way for now, even if the branch-not-taken case now costs
855 one additional instruction. Out-of-range branches are not supposed
856 to be common, anyway.
858 Branch likely. If label is out of range, we turn:
860 beql reg1, reg2, label
861 delay slot (annulled if branch not taken)
870 delay slot (executed only if branch taken)
873 It would be possible to generate a shorter sequence by losing the
874 likely bit, generating something like:
879 delay slot (executed only if branch taken)
891 bltzall -> bgezal (with jal label instead of j label)
892 bgezall -> bltzal (ditto)
895 but it's not clear that it would actually improve performance. */
896 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
899 | ((toofar) ? 1 : 0) \
901 | ((likely) ? 4 : 0) \
902 | ((uncond) ? 8 : 0)))
903 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
904 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
905 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
906 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
907 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
909 /* For mips16 code, we use an entirely different form of relaxation.
910 mips16 supports two versions of most instructions which take
911 immediate values: a small one which takes some small value, and a
912 larger one which takes a 16 bit value. Since branches also follow
913 this pattern, relaxing these values is required.
915 We can assemble both mips16 and normal MIPS code in a single
916 object. Therefore, we need to support this type of relaxation at
917 the same time that we support the relaxation described above. We
918 use the high bit of the subtype field to distinguish these cases.
920 The information we store for this type of relaxation is the
921 argument code found in the opcode file for this relocation, whether
922 the user explicitly requested a small or extended form, and whether
923 the relocation is in a jump or jal delay slot. That tells us the
924 size of the value, and how it should be stored. We also store
925 whether the fragment is considered to be extended or not. We also
926 store whether this is known to be a branch to a different section,
927 whether we have tried to relax this frag yet, and whether we have
928 ever extended a PC relative fragment because of a shift count. */
929 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
932 | ((small) ? 0x100 : 0) \
933 | ((ext) ? 0x200 : 0) \
934 | ((dslot) ? 0x400 : 0) \
935 | ((jal_dslot) ? 0x800 : 0))
936 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
937 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
938 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
939 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
940 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
941 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
942 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
943 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
944 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
945 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
946 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
947 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
949 /* Is the given value a sign-extended 32-bit value? */
950 #define IS_SEXT_32BIT_NUM(x) \
951 (((x) &~ (offsetT) 0x7fffffff) == 0 \
952 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
954 /* Is the given value a sign-extended 16-bit value? */
955 #define IS_SEXT_16BIT_NUM(x) \
956 (((x) &~ (offsetT) 0x7fff) == 0 \
957 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
959 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
960 #define IS_ZEXT_32BIT_NUM(x) \
961 (((x) &~ (offsetT) 0xffffffff) == 0 \
962 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
964 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
965 VALUE << SHIFT. VALUE is evaluated exactly once. */
966 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
967 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
968 | (((VALUE) & (MASK)) << (SHIFT)))
970 /* Extract bits MASK << SHIFT from STRUCT and shift them right
972 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
973 (((STRUCT) >> (SHIFT)) & (MASK))
975 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
976 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
978 include/opcode/mips.h specifies operand fields using the macros
979 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
980 with "MIPS16OP" instead of "OP". */
981 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
982 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
983 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
984 INSERT_BITS ((INSN).insn_opcode, VALUE, \
985 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
987 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
988 #define EXTRACT_OPERAND(FIELD, INSN) \
989 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
990 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
991 EXTRACT_BITS ((INSN).insn_opcode, \
992 MIPS16OP_MASK_##FIELD, \
995 /* Global variables used when generating relaxable macros. See the
996 comment above RELAX_ENCODE for more details about how relaxation
999 /* 0 if we're not emitting a relaxable macro.
1000 1 if we're emitting the first of the two relaxation alternatives.
1001 2 if we're emitting the second alternative. */
1004 /* The first relaxable fixup in the current frag. (In other words,
1005 the first fixup that refers to relaxable code.) */
1008 /* sizes[0] says how many bytes of the first alternative are stored in
1009 the current frag. Likewise sizes[1] for the second alternative. */
1010 unsigned int sizes[2];
1012 /* The symbol on which the choice of sequence depends. */
1016 /* Global variables used to decide whether a macro needs a warning. */
1018 /* True if the macro is in a branch delay slot. */
1019 bfd_boolean delay_slot_p;
1021 /* For relaxable macros, sizes[0] is the length of the first alternative
1022 in bytes and sizes[1] is the length of the second alternative.
1023 For non-relaxable macros, both elements give the length of the
1025 unsigned int sizes[2];
1027 /* The first variant frag for this macro. */
1029 } mips_macro_warning;
1031 /* Prototypes for static functions. */
1033 #define internalError() \
1034 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1036 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1038 static void append_insn
1039 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
1040 static void mips_no_prev_insn (void);
1041 static void mips16_macro_build
1042 (expressionS *, const char *, const char *, va_list);
1043 static void load_register (int, expressionS *, int);
1044 static void macro_start (void);
1045 static void macro_end (void);
1046 static void macro (struct mips_cl_insn * ip);
1047 static void mips16_macro (struct mips_cl_insn * ip);
1048 #ifdef LOSING_COMPILER
1049 static void macro2 (struct mips_cl_insn * ip);
1051 static void mips_ip (char *str, struct mips_cl_insn * ip);
1052 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1053 static void mips16_immed
1054 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1055 unsigned long *, bfd_boolean *, unsigned short *);
1056 static size_t my_getSmallExpression
1057 (expressionS *, bfd_reloc_code_real_type *, char *);
1058 static void my_getExpression (expressionS *, char *);
1059 static void s_align (int);
1060 static void s_change_sec (int);
1061 static void s_change_section (int);
1062 static void s_cons (int);
1063 static void s_float_cons (int);
1064 static void s_mips_globl (int);
1065 static void s_option (int);
1066 static void s_mipsset (int);
1067 static void s_abicalls (int);
1068 static void s_cpload (int);
1069 static void s_cpsetup (int);
1070 static void s_cplocal (int);
1071 static void s_cprestore (int);
1072 static void s_cpreturn (int);
1073 static void s_dtprelword (int);
1074 static void s_dtpreldword (int);
1075 static void s_gpvalue (int);
1076 static void s_gpword (int);
1077 static void s_gpdword (int);
1078 static void s_cpadd (int);
1079 static void s_insn (int);
1080 static void md_obj_begin (void);
1081 static void md_obj_end (void);
1082 static void s_mips_ent (int);
1083 static void s_mips_end (int);
1084 static void s_mips_frame (int);
1085 static void s_mips_mask (int reg_type);
1086 static void s_mips_stab (int);
1087 static void s_mips_weakext (int);
1088 static void s_mips_file (int);
1089 static void s_mips_loc (int);
1090 static bfd_boolean pic_need_relax (symbolS *, asection *);
1091 static int relaxed_branch_length (fragS *, asection *, int);
1092 static int validate_mips_insn (const struct mips_opcode *);
1094 /* Table and functions used to map between CPU/ISA names, and
1095 ISA levels, and CPU numbers. */
1097 struct mips_cpu_info
1099 const char *name; /* CPU or ISA name. */
1100 int flags; /* ASEs available, or ISA flag. */
1101 int isa; /* ISA level. */
1102 int cpu; /* CPU number (default CPU if ISA). */
1105 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1106 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1107 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1108 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1109 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1110 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1111 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1113 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1114 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1115 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1119 The following pseudo-ops from the Kane and Heinrich MIPS book
1120 should be defined here, but are currently unsupported: .alias,
1121 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1123 The following pseudo-ops from the Kane and Heinrich MIPS book are
1124 specific to the type of debugging information being generated, and
1125 should be defined by the object format: .aent, .begin, .bend,
1126 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1129 The following pseudo-ops from the Kane and Heinrich MIPS book are
1130 not MIPS CPU specific, but are also not specific to the object file
1131 format. This file is probably the best place to define them, but
1132 they are not currently supported: .asm0, .endr, .lab, .struct. */
1134 static const pseudo_typeS mips_pseudo_table[] =
1136 /* MIPS specific pseudo-ops. */
1137 {"option", s_option, 0},
1138 {"set", s_mipsset, 0},
1139 {"rdata", s_change_sec, 'r'},
1140 {"sdata", s_change_sec, 's'},
1141 {"livereg", s_ignore, 0},
1142 {"abicalls", s_abicalls, 0},
1143 {"cpload", s_cpload, 0},
1144 {"cpsetup", s_cpsetup, 0},
1145 {"cplocal", s_cplocal, 0},
1146 {"cprestore", s_cprestore, 0},
1147 {"cpreturn", s_cpreturn, 0},
1148 {"dtprelword", s_dtprelword, 0},
1149 {"dtpreldword", s_dtpreldword, 0},
1150 {"gpvalue", s_gpvalue, 0},
1151 {"gpword", s_gpword, 0},
1152 {"gpdword", s_gpdword, 0},
1153 {"cpadd", s_cpadd, 0},
1154 {"insn", s_insn, 0},
1156 /* Relatively generic pseudo-ops that happen to be used on MIPS
1158 {"asciiz", stringer, 8 + 1},
1159 {"bss", s_change_sec, 'b'},
1161 {"half", s_cons, 1},
1162 {"dword", s_cons, 3},
1163 {"weakext", s_mips_weakext, 0},
1164 {"origin", s_org, 0},
1165 {"repeat", s_rept, 0},
1167 /* These pseudo-ops are defined in read.c, but must be overridden
1168 here for one reason or another. */
1169 {"align", s_align, 0},
1170 {"byte", s_cons, 0},
1171 {"data", s_change_sec, 'd'},
1172 {"double", s_float_cons, 'd'},
1173 {"float", s_float_cons, 'f'},
1174 {"globl", s_mips_globl, 0},
1175 {"global", s_mips_globl, 0},
1176 {"hword", s_cons, 1},
1178 {"long", s_cons, 2},
1179 {"octa", s_cons, 4},
1180 {"quad", s_cons, 3},
1181 {"section", s_change_section, 0},
1182 {"short", s_cons, 1},
1183 {"single", s_float_cons, 'f'},
1184 {"stabn", s_mips_stab, 'n'},
1185 {"text", s_change_sec, 't'},
1186 {"word", s_cons, 2},
1188 { "extern", ecoff_directive_extern, 0},
1193 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1195 /* These pseudo-ops should be defined by the object file format.
1196 However, a.out doesn't support them, so we have versions here. */
1197 {"aent", s_mips_ent, 1},
1198 {"bgnb", s_ignore, 0},
1199 {"end", s_mips_end, 0},
1200 {"endb", s_ignore, 0},
1201 {"ent", s_mips_ent, 0},
1202 {"file", s_mips_file, 0},
1203 {"fmask", s_mips_mask, 'F'},
1204 {"frame", s_mips_frame, 0},
1205 {"loc", s_mips_loc, 0},
1206 {"mask", s_mips_mask, 'R'},
1207 {"verstamp", s_ignore, 0},
1211 extern void pop_insert (const pseudo_typeS *);
1214 mips_pop_insert (void)
1216 pop_insert (mips_pseudo_table);
1217 if (! ECOFF_DEBUGGING)
1218 pop_insert (mips_nonecoff_pseudo_table);
1221 /* Symbols labelling the current insn. */
1223 struct insn_label_list
1225 struct insn_label_list *next;
1229 static struct insn_label_list *free_insn_labels;
1230 #define label_list tc_segment_info_data.labels
1232 static void mips_clear_insn_labels (void);
1235 mips_clear_insn_labels (void)
1237 register struct insn_label_list **pl;
1238 segment_info_type *si;
1242 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1245 si = seg_info (now_seg);
1246 *pl = si->label_list;
1247 si->label_list = NULL;
1252 static char *expr_end;
1254 /* Expressions which appear in instructions. These are set by
1257 static expressionS imm_expr;
1258 static expressionS imm2_expr;
1259 static expressionS offset_expr;
1261 /* Relocs associated with imm_expr and offset_expr. */
1263 static bfd_reloc_code_real_type imm_reloc[3]
1264 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1265 static bfd_reloc_code_real_type offset_reloc[3]
1266 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1268 /* These are set by mips16_ip if an explicit extension is used. */
1270 static bfd_boolean mips16_small, mips16_ext;
1273 /* The pdr segment for per procedure frame/regmask info. Not used for
1276 static segT pdr_seg;
1279 /* The default target format to use. */
1282 mips_target_format (void)
1284 switch (OUTPUT_FLAVOR)
1286 case bfd_target_ecoff_flavour:
1287 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1288 case bfd_target_coff_flavour:
1290 case bfd_target_elf_flavour:
1292 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1293 return (target_big_endian
1294 ? "elf32-bigmips-vxworks"
1295 : "elf32-littlemips-vxworks");
1298 /* This is traditional mips. */
1299 return (target_big_endian
1300 ? (HAVE_64BIT_OBJECTS
1301 ? "elf64-tradbigmips"
1303 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1304 : (HAVE_64BIT_OBJECTS
1305 ? "elf64-tradlittlemips"
1307 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1309 return (target_big_endian
1310 ? (HAVE_64BIT_OBJECTS
1313 ? "elf32-nbigmips" : "elf32-bigmips"))
1314 : (HAVE_64BIT_OBJECTS
1315 ? "elf64-littlemips"
1317 ? "elf32-nlittlemips" : "elf32-littlemips")));
1325 /* Return the length of instruction INSN. */
1327 static inline unsigned int
1328 insn_length (const struct mips_cl_insn *insn)
1330 if (!mips_opts.mips16)
1332 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1335 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1338 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1343 insn->use_extend = FALSE;
1345 insn->insn_opcode = mo->match;
1348 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1349 insn->fixp[i] = NULL;
1350 insn->fixed_p = (mips_opts.noreorder > 0);
1351 insn->noreorder_p = (mips_opts.noreorder > 0);
1352 insn->mips16_absolute_jump_p = 0;
1355 /* Record the current MIPS16 mode in now_seg. */
1358 mips_record_mips16_mode (void)
1360 segment_info_type *si;
1362 si = seg_info (now_seg);
1363 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1364 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1367 /* Install INSN at the location specified by its "frag" and "where" fields. */
1370 install_insn (const struct mips_cl_insn *insn)
1372 char *f = insn->frag->fr_literal + insn->where;
1373 if (!mips_opts.mips16)
1374 md_number_to_chars (f, insn->insn_opcode, 4);
1375 else if (insn->mips16_absolute_jump_p)
1377 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1378 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1382 if (insn->use_extend)
1384 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1387 md_number_to_chars (f, insn->insn_opcode, 2);
1389 mips_record_mips16_mode ();
1392 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1393 and install the opcode in the new location. */
1396 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1401 insn->where = where;
1402 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1403 if (insn->fixp[i] != NULL)
1405 insn->fixp[i]->fx_frag = frag;
1406 insn->fixp[i]->fx_where = where;
1408 install_insn (insn);
1411 /* Add INSN to the end of the output. */
1414 add_fixed_insn (struct mips_cl_insn *insn)
1416 char *f = frag_more (insn_length (insn));
1417 move_insn (insn, frag_now, f - frag_now->fr_literal);
1420 /* Start a variant frag and move INSN to the start of the variant part,
1421 marking it as fixed. The other arguments are as for frag_var. */
1424 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1425 relax_substateT subtype, symbolS *symbol, offsetT offset)
1427 frag_grow (max_chars);
1428 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1430 frag_var (rs_machine_dependent, max_chars, var,
1431 subtype, symbol, offset, NULL);
1434 /* Insert N copies of INSN into the history buffer, starting at
1435 position FIRST. Neither FIRST nor N need to be clipped. */
1438 insert_into_history (unsigned int first, unsigned int n,
1439 const struct mips_cl_insn *insn)
1441 if (mips_relax.sequence != 2)
1445 for (i = ARRAY_SIZE (history); i-- > first;)
1447 history[i] = history[i - n];
1453 /* Emit a nop instruction, recording it in the history buffer. */
1458 add_fixed_insn (NOP_INSN);
1459 insert_into_history (0, 1, NOP_INSN);
1462 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1463 the idea is to make it obvious at a glance that each errata is
1467 init_vr4120_conflicts (void)
1469 #define CONFLICT(FIRST, SECOND) \
1470 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1472 /* Errata 21 - [D]DIV[U] after [D]MACC */
1473 CONFLICT (MACC, DIV);
1474 CONFLICT (DMACC, DIV);
1476 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1477 CONFLICT (DMULT, DMULT);
1478 CONFLICT (DMULT, DMACC);
1479 CONFLICT (DMACC, DMULT);
1480 CONFLICT (DMACC, DMACC);
1482 /* Errata 24 - MT{LO,HI} after [D]MACC */
1483 CONFLICT (MACC, MTHILO);
1484 CONFLICT (DMACC, MTHILO);
1486 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1487 instruction is executed immediately after a MACC or DMACC
1488 instruction, the result of [either instruction] is incorrect." */
1489 CONFLICT (MACC, MULT);
1490 CONFLICT (MACC, DMULT);
1491 CONFLICT (DMACC, MULT);
1492 CONFLICT (DMACC, DMULT);
1494 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1495 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1496 DDIV or DDIVU instruction, the result of the MACC or
1497 DMACC instruction is incorrect.". */
1498 CONFLICT (DMULT, MACC);
1499 CONFLICT (DMULT, DMACC);
1500 CONFLICT (DIV, MACC);
1501 CONFLICT (DIV, DMACC);
1511 #define RTYPE_MASK 0x1ff00
1512 #define RTYPE_NUM 0x00100
1513 #define RTYPE_FPU 0x00200
1514 #define RTYPE_FCC 0x00400
1515 #define RTYPE_VEC 0x00800
1516 #define RTYPE_GP 0x01000
1517 #define RTYPE_CP0 0x02000
1518 #define RTYPE_PC 0x04000
1519 #define RTYPE_ACC 0x08000
1520 #define RTYPE_CCC 0x10000
1521 #define RNUM_MASK 0x000ff
1522 #define RWARN 0x80000
1524 #define GENERIC_REGISTER_NUMBERS \
1525 {"$0", RTYPE_NUM | 0}, \
1526 {"$1", RTYPE_NUM | 1}, \
1527 {"$2", RTYPE_NUM | 2}, \
1528 {"$3", RTYPE_NUM | 3}, \
1529 {"$4", RTYPE_NUM | 4}, \
1530 {"$5", RTYPE_NUM | 5}, \
1531 {"$6", RTYPE_NUM | 6}, \
1532 {"$7", RTYPE_NUM | 7}, \
1533 {"$8", RTYPE_NUM | 8}, \
1534 {"$9", RTYPE_NUM | 9}, \
1535 {"$10", RTYPE_NUM | 10}, \
1536 {"$11", RTYPE_NUM | 11}, \
1537 {"$12", RTYPE_NUM | 12}, \
1538 {"$13", RTYPE_NUM | 13}, \
1539 {"$14", RTYPE_NUM | 14}, \
1540 {"$15", RTYPE_NUM | 15}, \
1541 {"$16", RTYPE_NUM | 16}, \
1542 {"$17", RTYPE_NUM | 17}, \
1543 {"$18", RTYPE_NUM | 18}, \
1544 {"$19", RTYPE_NUM | 19}, \
1545 {"$20", RTYPE_NUM | 20}, \
1546 {"$21", RTYPE_NUM | 21}, \
1547 {"$22", RTYPE_NUM | 22}, \
1548 {"$23", RTYPE_NUM | 23}, \
1549 {"$24", RTYPE_NUM | 24}, \
1550 {"$25", RTYPE_NUM | 25}, \
1551 {"$26", RTYPE_NUM | 26}, \
1552 {"$27", RTYPE_NUM | 27}, \
1553 {"$28", RTYPE_NUM | 28}, \
1554 {"$29", RTYPE_NUM | 29}, \
1555 {"$30", RTYPE_NUM | 30}, \
1556 {"$31", RTYPE_NUM | 31}
1558 #define FPU_REGISTER_NAMES \
1559 {"$f0", RTYPE_FPU | 0}, \
1560 {"$f1", RTYPE_FPU | 1}, \
1561 {"$f2", RTYPE_FPU | 2}, \
1562 {"$f3", RTYPE_FPU | 3}, \
1563 {"$f4", RTYPE_FPU | 4}, \
1564 {"$f5", RTYPE_FPU | 5}, \
1565 {"$f6", RTYPE_FPU | 6}, \
1566 {"$f7", RTYPE_FPU | 7}, \
1567 {"$f8", RTYPE_FPU | 8}, \
1568 {"$f9", RTYPE_FPU | 9}, \
1569 {"$f10", RTYPE_FPU | 10}, \
1570 {"$f11", RTYPE_FPU | 11}, \
1571 {"$f12", RTYPE_FPU | 12}, \
1572 {"$f13", RTYPE_FPU | 13}, \
1573 {"$f14", RTYPE_FPU | 14}, \
1574 {"$f15", RTYPE_FPU | 15}, \
1575 {"$f16", RTYPE_FPU | 16}, \
1576 {"$f17", RTYPE_FPU | 17}, \
1577 {"$f18", RTYPE_FPU | 18}, \
1578 {"$f19", RTYPE_FPU | 19}, \
1579 {"$f20", RTYPE_FPU | 20}, \
1580 {"$f21", RTYPE_FPU | 21}, \
1581 {"$f22", RTYPE_FPU | 22}, \
1582 {"$f23", RTYPE_FPU | 23}, \
1583 {"$f24", RTYPE_FPU | 24}, \
1584 {"$f25", RTYPE_FPU | 25}, \
1585 {"$f26", RTYPE_FPU | 26}, \
1586 {"$f27", RTYPE_FPU | 27}, \
1587 {"$f28", RTYPE_FPU | 28}, \
1588 {"$f29", RTYPE_FPU | 29}, \
1589 {"$f30", RTYPE_FPU | 30}, \
1590 {"$f31", RTYPE_FPU | 31}
1592 #define FPU_CONDITION_CODE_NAMES \
1593 {"$fcc0", RTYPE_FCC | 0}, \
1594 {"$fcc1", RTYPE_FCC | 1}, \
1595 {"$fcc2", RTYPE_FCC | 2}, \
1596 {"$fcc3", RTYPE_FCC | 3}, \
1597 {"$fcc4", RTYPE_FCC | 4}, \
1598 {"$fcc5", RTYPE_FCC | 5}, \
1599 {"$fcc6", RTYPE_FCC | 6}, \
1600 {"$fcc7", RTYPE_FCC | 7}
1602 #define COPROC_CONDITION_CODE_NAMES \
1603 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1604 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1605 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1606 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1607 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1608 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1609 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1610 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1612 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1613 {"$a4", RTYPE_GP | 8}, \
1614 {"$a5", RTYPE_GP | 9}, \
1615 {"$a6", RTYPE_GP | 10}, \
1616 {"$a7", RTYPE_GP | 11}, \
1617 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1618 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1619 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1620 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1621 {"$t0", RTYPE_GP | 12}, \
1622 {"$t1", RTYPE_GP | 13}, \
1623 {"$t2", RTYPE_GP | 14}, \
1624 {"$t3", RTYPE_GP | 15}
1626 #define O32_SYMBOLIC_REGISTER_NAMES \
1627 {"$t0", RTYPE_GP | 8}, \
1628 {"$t1", RTYPE_GP | 9}, \
1629 {"$t2", RTYPE_GP | 10}, \
1630 {"$t3", RTYPE_GP | 11}, \
1631 {"$t4", RTYPE_GP | 12}, \
1632 {"$t5", RTYPE_GP | 13}, \
1633 {"$t6", RTYPE_GP | 14}, \
1634 {"$t7", RTYPE_GP | 15}, \
1635 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1636 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1637 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1638 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1640 /* Remaining symbolic register names */
1641 #define SYMBOLIC_REGISTER_NAMES \
1642 {"$zero", RTYPE_GP | 0}, \
1643 {"$at", RTYPE_GP | 1}, \
1644 {"$AT", RTYPE_GP | 1}, \
1645 {"$v0", RTYPE_GP | 2}, \
1646 {"$v1", RTYPE_GP | 3}, \
1647 {"$a0", RTYPE_GP | 4}, \
1648 {"$a1", RTYPE_GP | 5}, \
1649 {"$a2", RTYPE_GP | 6}, \
1650 {"$a3", RTYPE_GP | 7}, \
1651 {"$s0", RTYPE_GP | 16}, \
1652 {"$s1", RTYPE_GP | 17}, \
1653 {"$s2", RTYPE_GP | 18}, \
1654 {"$s3", RTYPE_GP | 19}, \
1655 {"$s4", RTYPE_GP | 20}, \
1656 {"$s5", RTYPE_GP | 21}, \
1657 {"$s6", RTYPE_GP | 22}, \
1658 {"$s7", RTYPE_GP | 23}, \
1659 {"$t8", RTYPE_GP | 24}, \
1660 {"$t9", RTYPE_GP | 25}, \
1661 {"$k0", RTYPE_GP | 26}, \
1662 {"$kt0", RTYPE_GP | 26}, \
1663 {"$k1", RTYPE_GP | 27}, \
1664 {"$kt1", RTYPE_GP | 27}, \
1665 {"$gp", RTYPE_GP | 28}, \
1666 {"$sp", RTYPE_GP | 29}, \
1667 {"$s8", RTYPE_GP | 30}, \
1668 {"$fp", RTYPE_GP | 30}, \
1669 {"$ra", RTYPE_GP | 31}
1671 #define MIPS16_SPECIAL_REGISTER_NAMES \
1672 {"$pc", RTYPE_PC | 0}
1674 #define MDMX_VECTOR_REGISTER_NAMES \
1675 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1676 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1677 {"$v2", RTYPE_VEC | 2}, \
1678 {"$v3", RTYPE_VEC | 3}, \
1679 {"$v4", RTYPE_VEC | 4}, \
1680 {"$v5", RTYPE_VEC | 5}, \
1681 {"$v6", RTYPE_VEC | 6}, \
1682 {"$v7", RTYPE_VEC | 7}, \
1683 {"$v8", RTYPE_VEC | 8}, \
1684 {"$v9", RTYPE_VEC | 9}, \
1685 {"$v10", RTYPE_VEC | 10}, \
1686 {"$v11", RTYPE_VEC | 11}, \
1687 {"$v12", RTYPE_VEC | 12}, \
1688 {"$v13", RTYPE_VEC | 13}, \
1689 {"$v14", RTYPE_VEC | 14}, \
1690 {"$v15", RTYPE_VEC | 15}, \
1691 {"$v16", RTYPE_VEC | 16}, \
1692 {"$v17", RTYPE_VEC | 17}, \
1693 {"$v18", RTYPE_VEC | 18}, \
1694 {"$v19", RTYPE_VEC | 19}, \
1695 {"$v20", RTYPE_VEC | 20}, \
1696 {"$v21", RTYPE_VEC | 21}, \
1697 {"$v22", RTYPE_VEC | 22}, \
1698 {"$v23", RTYPE_VEC | 23}, \
1699 {"$v24", RTYPE_VEC | 24}, \
1700 {"$v25", RTYPE_VEC | 25}, \
1701 {"$v26", RTYPE_VEC | 26}, \
1702 {"$v27", RTYPE_VEC | 27}, \
1703 {"$v28", RTYPE_VEC | 28}, \
1704 {"$v29", RTYPE_VEC | 29}, \
1705 {"$v30", RTYPE_VEC | 30}, \
1706 {"$v31", RTYPE_VEC | 31}
1708 #define MIPS_DSP_ACCUMULATOR_NAMES \
1709 {"$ac0", RTYPE_ACC | 0}, \
1710 {"$ac1", RTYPE_ACC | 1}, \
1711 {"$ac2", RTYPE_ACC | 2}, \
1712 {"$ac3", RTYPE_ACC | 3}
1714 static const struct regname reg_names[] = {
1715 GENERIC_REGISTER_NUMBERS,
1717 FPU_CONDITION_CODE_NAMES,
1718 COPROC_CONDITION_CODE_NAMES,
1720 /* The $txx registers depends on the abi,
1721 these will be added later into the symbol table from
1722 one of the tables below once mips_abi is set after
1723 parsing of arguments from the command line. */
1724 SYMBOLIC_REGISTER_NAMES,
1726 MIPS16_SPECIAL_REGISTER_NAMES,
1727 MDMX_VECTOR_REGISTER_NAMES,
1728 MIPS_DSP_ACCUMULATOR_NAMES,
1732 static const struct regname reg_names_o32[] = {
1733 O32_SYMBOLIC_REGISTER_NAMES,
1737 static const struct regname reg_names_n32n64[] = {
1738 N32N64_SYMBOLIC_REGISTER_NAMES,
1743 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1750 /* Find end of name. */
1752 if (is_name_beginner (*e))
1754 while (is_part_of_name (*e))
1757 /* Terminate name. */
1761 /* Look for a register symbol. */
1762 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1764 int r = S_GET_VALUE (symbolP);
1766 reg = r & RNUM_MASK;
1767 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1768 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1769 reg = (r & RNUM_MASK) - 2;
1771 /* Else see if this is a register defined in an itbl entry. */
1772 else if ((types & RTYPE_GP) && itbl_have_entries)
1779 if (itbl_get_reg_val (n, &r))
1780 reg = r & RNUM_MASK;
1783 /* Advance to next token if a register was recognised. */
1786 else if (types & RWARN)
1787 as_warn ("Unrecognized register name `%s'", *s);
1795 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1796 architecture. If EXPANSIONP is TRUE then this check is done while
1797 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1800 is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
1802 int isa = mips_opts.isa;
1805 if (mips_opts.ase_mdmx)
1807 if (mips_opts.ase_dsp)
1809 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1811 if (mips_opts.ase_dspr2)
1813 if (mips_opts.ase_mt)
1815 if (mips_opts.ase_mips3d)
1817 if (mips_opts.ase_smartmips)
1818 isa |= INSN_SMARTMIPS;
1820 /* For user code we don't check for mips_opts.mips16 since we want
1821 to allow jalx if -mips16 was specified on the command line. */
1822 if (expansionp ? mips_opts.mips16 : file_ase_mips16)
1825 /* Don't accept instructions based on the ISA if the CPU does not implement
1826 all the coprocessor insns. */
1827 if (NO_ISA_COP (mips_opts.arch)
1828 && COP_INSN (mo->pinfo))
1831 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1834 /* Check whether the instruction or macro requires single-precision or
1835 double-precision floating-point support. Note that this information is
1836 stored differently in the opcode table for insns and macros. */
1837 if (mo->pinfo == INSN_MACRO)
1839 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1840 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1844 fp_s = mo->pinfo & FP_S;
1845 fp_d = mo->pinfo & FP_D;
1848 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1851 if (fp_s && mips_opts.soft_float)
1857 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1858 selected ISA and architecture. */
1861 is_opcode_valid_16 (const struct mips_opcode *mo)
1863 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1866 /* This function is called once, at assembler startup time. It should set up
1867 all the tables, etc. that the MD part of the assembler will need. */
1872 const char *retval = NULL;
1876 if (mips_pic != NO_PIC)
1878 if (g_switch_seen && g_switch_value != 0)
1879 as_bad (_("-G may not be used in position-independent code"));
1883 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1884 as_warn (_("Could not set architecture and machine"));
1886 op_hash = hash_new ();
1888 for (i = 0; i < NUMOPCODES;)
1890 const char *name = mips_opcodes[i].name;
1892 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1895 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1896 mips_opcodes[i].name, retval);
1897 /* Probably a memory allocation problem? Give up now. */
1898 as_fatal (_("Broken assembler. No assembly attempted."));
1902 if (mips_opcodes[i].pinfo != INSN_MACRO)
1904 if (!validate_mips_insn (&mips_opcodes[i]))
1906 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1908 create_insn (&nop_insn, mips_opcodes + i);
1909 nop_insn.fixed_p = 1;
1914 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1917 mips16_op_hash = hash_new ();
1920 while (i < bfd_mips16_num_opcodes)
1922 const char *name = mips16_opcodes[i].name;
1924 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1926 as_fatal (_("internal: can't hash `%s': %s"),
1927 mips16_opcodes[i].name, retval);
1930 if (mips16_opcodes[i].pinfo != INSN_MACRO
1931 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1932 != mips16_opcodes[i].match))
1934 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1935 mips16_opcodes[i].name, mips16_opcodes[i].args);
1938 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1941 mips16_nop_insn.fixed_p = 1;
1945 while (i < bfd_mips16_num_opcodes
1946 && strcmp (mips16_opcodes[i].name, name) == 0);
1950 as_fatal (_("Broken assembler. No assembly attempted."));
1952 /* We add all the general register names to the symbol table. This
1953 helps us detect invalid uses of them. */
1954 for (i = 0; reg_names[i].name; i++)
1955 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1956 reg_names[i].num, /* & RNUM_MASK, */
1957 &zero_address_frag));
1959 for (i = 0; reg_names_n32n64[i].name; i++)
1960 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1961 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1962 &zero_address_frag));
1964 for (i = 0; reg_names_o32[i].name; i++)
1965 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1966 reg_names_o32[i].num, /* & RNUM_MASK, */
1967 &zero_address_frag));
1969 mips_no_prev_insn ();
1972 mips_cprmask[0] = 0;
1973 mips_cprmask[1] = 0;
1974 mips_cprmask[2] = 0;
1975 mips_cprmask[3] = 0;
1977 /* set the default alignment for the text section (2**2) */
1978 record_alignment (text_section, 2);
1980 bfd_set_gp_size (stdoutput, g_switch_value);
1985 /* On a native system other than VxWorks, sections must be aligned
1986 to 16 byte boundaries. When configured for an embedded ELF
1987 target, we don't bother. */
1988 if (strncmp (TARGET_OS, "elf", 3) != 0
1989 && strncmp (TARGET_OS, "vxworks", 7) != 0)
1991 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1992 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1993 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1996 /* Create a .reginfo section for register masks and a .mdebug
1997 section for debugging information. */
2005 subseg = now_subseg;
2007 /* The ABI says this section should be loaded so that the
2008 running program can access it. However, we don't load it
2009 if we are configured for an embedded target */
2010 flags = SEC_READONLY | SEC_DATA;
2011 if (strncmp (TARGET_OS, "elf", 3) != 0)
2012 flags |= SEC_ALLOC | SEC_LOAD;
2014 if (mips_abi != N64_ABI)
2016 sec = subseg_new (".reginfo", (subsegT) 0);
2018 bfd_set_section_flags (stdoutput, sec, flags);
2019 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2021 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2025 /* The 64-bit ABI uses a .MIPS.options section rather than
2026 .reginfo section. */
2027 sec = subseg_new (".MIPS.options", (subsegT) 0);
2028 bfd_set_section_flags (stdoutput, sec, flags);
2029 bfd_set_section_alignment (stdoutput, sec, 3);
2031 /* Set up the option header. */
2033 Elf_Internal_Options opthdr;
2036 opthdr.kind = ODK_REGINFO;
2037 opthdr.size = (sizeof (Elf_External_Options)
2038 + sizeof (Elf64_External_RegInfo));
2041 f = frag_more (sizeof (Elf_External_Options));
2042 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2043 (Elf_External_Options *) f);
2045 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2049 if (ECOFF_DEBUGGING)
2051 sec = subseg_new (".mdebug", (subsegT) 0);
2052 (void) bfd_set_section_flags (stdoutput, sec,
2053 SEC_HAS_CONTENTS | SEC_READONLY);
2054 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2056 else if (mips_flag_pdr)
2058 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2059 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2060 SEC_READONLY | SEC_RELOC
2062 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2065 subseg_set (seg, subseg);
2068 #endif /* OBJ_ELF */
2070 if (! ECOFF_DEBUGGING)
2073 if (mips_fix_vr4120)
2074 init_vr4120_conflicts ();
2080 if (! ECOFF_DEBUGGING)
2085 md_assemble (char *str)
2087 struct mips_cl_insn insn;
2088 bfd_reloc_code_real_type unused_reloc[3]
2089 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2091 imm_expr.X_op = O_absent;
2092 imm2_expr.X_op = O_absent;
2093 offset_expr.X_op = O_absent;
2094 imm_reloc[0] = BFD_RELOC_UNUSED;
2095 imm_reloc[1] = BFD_RELOC_UNUSED;
2096 imm_reloc[2] = BFD_RELOC_UNUSED;
2097 offset_reloc[0] = BFD_RELOC_UNUSED;
2098 offset_reloc[1] = BFD_RELOC_UNUSED;
2099 offset_reloc[2] = BFD_RELOC_UNUSED;
2101 if (mips_opts.mips16)
2102 mips16_ip (str, &insn);
2105 mips_ip (str, &insn);
2106 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2107 str, insn.insn_opcode));
2112 as_bad ("%s `%s'", insn_error, str);
2116 if (insn.insn_mo->pinfo == INSN_MACRO)
2119 if (mips_opts.mips16)
2120 mips16_macro (&insn);
2127 if (imm_expr.X_op != O_absent)
2128 append_insn (&insn, &imm_expr, imm_reloc);
2129 else if (offset_expr.X_op != O_absent)
2130 append_insn (&insn, &offset_expr, offset_reloc);
2132 append_insn (&insn, NULL, unused_reloc);
2136 /* Convenience functions for abstracting away the differences between
2137 MIPS16 and non-MIPS16 relocations. */
2139 static inline bfd_boolean
2140 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2144 case BFD_RELOC_MIPS16_JMP:
2145 case BFD_RELOC_MIPS16_GPREL:
2146 case BFD_RELOC_MIPS16_GOT16:
2147 case BFD_RELOC_MIPS16_CALL16:
2148 case BFD_RELOC_MIPS16_HI16_S:
2149 case BFD_RELOC_MIPS16_HI16:
2150 case BFD_RELOC_MIPS16_LO16:
2158 static inline bfd_boolean
2159 got16_reloc_p (bfd_reloc_code_real_type reloc)
2161 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2164 static inline bfd_boolean
2165 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2167 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2170 static inline bfd_boolean
2171 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2173 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2176 /* Return true if the given relocation might need a matching %lo().
2177 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2178 need a matching %lo() when applied to local symbols. */
2180 static inline bfd_boolean
2181 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2183 return (HAVE_IN_PLACE_ADDENDS
2184 && (hi16_reloc_p (reloc)
2185 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2186 all GOT16 relocations evaluate to "G". */
2187 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2190 /* Return the type of %lo() reloc needed by RELOC, given that
2191 reloc_needs_lo_p. */
2193 static inline bfd_reloc_code_real_type
2194 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2196 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2199 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2202 static inline bfd_boolean
2203 fixup_has_matching_lo_p (fixS *fixp)
2205 return (fixp->fx_next != NULL
2206 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2207 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2208 && fixp->fx_offset == fixp->fx_next->fx_offset);
2211 /* See whether instruction IP reads register REG. CLASS is the type
2215 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2216 enum mips_regclass class)
2218 if (class == MIPS16_REG)
2220 assert (mips_opts.mips16);
2221 reg = mips16_to_32_reg_map[reg];
2222 class = MIPS_GR_REG;
2225 /* Don't report on general register ZERO, since it never changes. */
2226 if (class == MIPS_GR_REG && reg == ZERO)
2229 if (class == MIPS_FP_REG)
2231 assert (! mips_opts.mips16);
2232 /* If we are called with either $f0 or $f1, we must check $f0.
2233 This is not optimal, because it will introduce an unnecessary
2234 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2235 need to distinguish reading both $f0 and $f1 or just one of
2236 them. Note that we don't have to check the other way,
2237 because there is no instruction that sets both $f0 and $f1
2238 and requires a delay. */
2239 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2240 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2241 == (reg &~ (unsigned) 1)))
2243 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2244 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2245 == (reg &~ (unsigned) 1)))
2248 else if (! mips_opts.mips16)
2250 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2251 && EXTRACT_OPERAND (RS, *ip) == reg)
2253 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2254 && EXTRACT_OPERAND (RT, *ip) == reg)
2259 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2260 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2262 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2263 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2265 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2266 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2269 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2271 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2273 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2275 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2276 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2283 /* This function returns true if modifying a register requires a
2287 reg_needs_delay (unsigned int reg)
2289 unsigned long prev_pinfo;
2291 prev_pinfo = history[0].insn_mo->pinfo;
2292 if (! mips_opts.noreorder
2293 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2294 && ! gpr_interlocks)
2295 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2296 && ! cop_interlocks)))
2298 /* A load from a coprocessor or from memory. All load delays
2299 delay the use of general register rt for one instruction. */
2300 /* Itbl support may require additional care here. */
2301 know (prev_pinfo & INSN_WRITE_GPR_T);
2302 if (reg == EXTRACT_OPERAND (RT, history[0]))
2309 /* Move all labels in insn_labels to the current insertion point. */
2312 mips_move_labels (void)
2314 segment_info_type *si = seg_info (now_seg);
2315 struct insn_label_list *l;
2318 for (l = si->label_list; l != NULL; l = l->next)
2320 assert (S_GET_SEGMENT (l->label) == now_seg);
2321 symbol_set_frag (l->label, frag_now);
2322 val = (valueT) frag_now_fix ();
2323 /* mips16 text labels are stored as odd. */
2324 if (mips_opts.mips16)
2326 S_SET_VALUE (l->label, val);
2331 s_is_linkonce (symbolS *sym, segT from_seg)
2333 bfd_boolean linkonce = FALSE;
2334 segT symseg = S_GET_SEGMENT (sym);
2336 if (symseg != from_seg && !S_IS_LOCAL (sym))
2338 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2341 /* The GNU toolchain uses an extension for ELF: a section
2342 beginning with the magic string .gnu.linkonce is a
2343 linkonce section. */
2344 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2345 sizeof ".gnu.linkonce" - 1) == 0)
2352 /* Mark instruction labels in mips16 mode. This permits the linker to
2353 handle them specially, such as generating jalx instructions when
2354 needed. We also make them odd for the duration of the assembly, in
2355 order to generate the right sort of code. We will make them even
2356 in the adjust_symtab routine, while leaving them marked. This is
2357 convenient for the debugger and the disassembler. The linker knows
2358 to make them odd again. */
2361 mips16_mark_labels (void)
2363 segment_info_type *si = seg_info (now_seg);
2364 struct insn_label_list *l;
2366 if (!mips_opts.mips16)
2369 for (l = si->label_list; l != NULL; l = l->next)
2371 symbolS *label = l->label;
2373 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2375 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2377 if ((S_GET_VALUE (label) & 1) == 0
2378 /* Don't adjust the address if the label is global or weak, or
2379 in a link-once section, since we'll be emitting symbol reloc
2380 references to it which will be patched up by the linker, and
2381 the final value of the symbol may or may not be MIPS16. */
2382 && ! S_IS_WEAK (label)
2383 && ! S_IS_EXTERNAL (label)
2384 && ! s_is_linkonce (label, now_seg))
2385 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2389 /* End the current frag. Make it a variant frag and record the
2393 relax_close_frag (void)
2395 mips_macro_warning.first_frag = frag_now;
2396 frag_var (rs_machine_dependent, 0, 0,
2397 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2398 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2400 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2401 mips_relax.first_fixup = 0;
2404 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2405 See the comment above RELAX_ENCODE for more details. */
2408 relax_start (symbolS *symbol)
2410 assert (mips_relax.sequence == 0);
2411 mips_relax.sequence = 1;
2412 mips_relax.symbol = symbol;
2415 /* Start generating the second version of a relaxable sequence.
2416 See the comment above RELAX_ENCODE for more details. */
2421 assert (mips_relax.sequence == 1);
2422 mips_relax.sequence = 2;
2425 /* End the current relaxable sequence. */
2430 assert (mips_relax.sequence == 2);
2431 relax_close_frag ();
2432 mips_relax.sequence = 0;
2435 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2436 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2437 by VR4120 errata. */
2440 classify_vr4120_insn (const char *name)
2442 if (strncmp (name, "macc", 4) == 0)
2443 return FIX_VR4120_MACC;
2444 if (strncmp (name, "dmacc", 5) == 0)
2445 return FIX_VR4120_DMACC;
2446 if (strncmp (name, "mult", 4) == 0)
2447 return FIX_VR4120_MULT;
2448 if (strncmp (name, "dmult", 5) == 0)
2449 return FIX_VR4120_DMULT;
2450 if (strstr (name, "div"))
2451 return FIX_VR4120_DIV;
2452 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2453 return FIX_VR4120_MTHILO;
2454 return NUM_FIX_VR4120_CLASSES;
2457 #define INSN_ERET 0x42000018
2458 #define INSN_DERET 0x4200001f
2460 /* Return the number of instructions that must separate INSN1 and INSN2,
2461 where INSN1 is the earlier instruction. Return the worst-case value
2462 for any INSN2 if INSN2 is null. */
2465 insns_between (const struct mips_cl_insn *insn1,
2466 const struct mips_cl_insn *insn2)
2468 unsigned long pinfo1, pinfo2;
2470 /* This function needs to know which pinfo flags are set for INSN2
2471 and which registers INSN2 uses. The former is stored in PINFO2 and
2472 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2473 will have every flag set and INSN2_USES_REG will always return true. */
2474 pinfo1 = insn1->insn_mo->pinfo;
2475 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2477 #define INSN2_USES_REG(REG, CLASS) \
2478 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2480 /* For most targets, write-after-read dependencies on the HI and LO
2481 registers must be separated by at least two instructions. */
2482 if (!hilo_interlocks)
2484 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2486 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2490 /* If we're working around r7000 errata, there must be two instructions
2491 between an mfhi or mflo and any instruction that uses the result. */
2492 if (mips_7000_hilo_fix
2493 && MF_HILO_INSN (pinfo1)
2494 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2497 /* If we're working around 24K errata, one instruction is required
2498 if an ERET or DERET is followed by a branch instruction. */
2501 if (insn1->insn_opcode == INSN_ERET
2502 || insn1->insn_opcode == INSN_DERET)
2505 || insn2->insn_opcode == INSN_ERET
2506 || insn2->insn_opcode == INSN_DERET
2507 || (insn2->insn_mo->pinfo
2508 & (INSN_UNCOND_BRANCH_DELAY
2509 | INSN_COND_BRANCH_DELAY
2510 | INSN_COND_BRANCH_LIKELY)) != 0)
2515 /* If working around VR4120 errata, check for combinations that need
2516 a single intervening instruction. */
2517 if (mips_fix_vr4120)
2519 unsigned int class1, class2;
2521 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2522 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2526 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2527 if (vr4120_conflicts[class1] & (1 << class2))
2532 if (!mips_opts.mips16)
2534 /* Check for GPR or coprocessor load delays. All such delays
2535 are on the RT register. */
2536 /* Itbl support may require additional care here. */
2537 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2538 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2540 know (pinfo1 & INSN_WRITE_GPR_T);
2541 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2545 /* Check for generic coprocessor hazards.
2547 This case is not handled very well. There is no special
2548 knowledge of CP0 handling, and the coprocessors other than
2549 the floating point unit are not distinguished at all. */
2550 /* Itbl support may require additional care here. FIXME!
2551 Need to modify this to include knowledge about
2552 user specified delays! */
2553 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2554 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2556 /* Handle cases where INSN1 writes to a known general coprocessor
2557 register. There must be a one instruction delay before INSN2
2558 if INSN2 reads that register, otherwise no delay is needed. */
2559 if (pinfo1 & INSN_WRITE_FPR_T)
2561 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2564 else if (pinfo1 & INSN_WRITE_FPR_S)
2566 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2571 /* Read-after-write dependencies on the control registers
2572 require a two-instruction gap. */
2573 if ((pinfo1 & INSN_WRITE_COND_CODE)
2574 && (pinfo2 & INSN_READ_COND_CODE))
2577 /* We don't know exactly what INSN1 does. If INSN2 is
2578 also a coprocessor instruction, assume there must be
2579 a one instruction gap. */
2580 if (pinfo2 & INSN_COP)
2585 /* Check for read-after-write dependencies on the coprocessor
2586 control registers in cases where INSN1 does not need a general
2587 coprocessor delay. This means that INSN1 is a floating point
2588 comparison instruction. */
2589 /* Itbl support may require additional care here. */
2590 else if (!cop_interlocks
2591 && (pinfo1 & INSN_WRITE_COND_CODE)
2592 && (pinfo2 & INSN_READ_COND_CODE))
2596 #undef INSN2_USES_REG
2601 /* Return the number of nops that would be needed to work around the
2602 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2603 the MAX_VR4130_NOPS instructions described by HISTORY. */
2606 nops_for_vr4130 (const struct mips_cl_insn *history,
2607 const struct mips_cl_insn *insn)
2611 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2612 are not affected by the errata. */
2614 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2615 || strcmp (insn->insn_mo->name, "mtlo") == 0
2616 || strcmp (insn->insn_mo->name, "mthi") == 0))
2619 /* Search for the first MFLO or MFHI. */
2620 for (i = 0; i < MAX_VR4130_NOPS; i++)
2621 if (MF_HILO_INSN (history[i].insn_mo->pinfo))
2623 /* Extract the destination register. */
2624 if (mips_opts.mips16)
2625 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2627 reg = EXTRACT_OPERAND (RD, history[i]);
2629 /* No nops are needed if INSN reads that register. */
2630 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2633 /* ...or if any of the intervening instructions do. */
2634 for (j = 0; j < i; j++)
2635 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2638 return MAX_VR4130_NOPS - i;
2643 /* Return the number of nops that would be needed if instruction INSN
2644 immediately followed the MAX_NOPS instructions given by HISTORY,
2645 where HISTORY[0] is the most recent instruction. If INSN is null,
2646 return the worse-case number of nops for any instruction. */
2649 nops_for_insn (const struct mips_cl_insn *history,
2650 const struct mips_cl_insn *insn)
2652 int i, nops, tmp_nops;
2655 for (i = 0; i < MAX_DELAY_NOPS; i++)
2657 tmp_nops = insns_between (history + i, insn) - i;
2658 if (tmp_nops > nops)
2662 if (mips_fix_vr4130)
2664 tmp_nops = nops_for_vr4130 (history, insn);
2665 if (tmp_nops > nops)
2672 /* The variable arguments provide NUM_INSNS extra instructions that
2673 might be added to HISTORY. Return the largest number of nops that
2674 would be needed after the extended sequence. */
2677 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2680 struct mips_cl_insn buffer[MAX_NOPS];
2681 struct mips_cl_insn *cursor;
2684 va_start (args, history);
2685 cursor = buffer + num_insns;
2686 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2687 while (cursor > buffer)
2688 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2690 nops = nops_for_insn (buffer, NULL);
2695 /* Like nops_for_insn, but if INSN is a branch, take into account the
2696 worst-case delay for the branch target. */
2699 nops_for_insn_or_target (const struct mips_cl_insn *history,
2700 const struct mips_cl_insn *insn)
2704 nops = nops_for_insn (history, insn);
2705 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2706 | INSN_COND_BRANCH_DELAY
2707 | INSN_COND_BRANCH_LIKELY))
2709 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2710 if (tmp_nops > nops)
2713 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2715 tmp_nops = nops_for_sequence (1, history, insn);
2716 if (tmp_nops > nops)
2722 /* Output an instruction. IP is the instruction information.
2723 ADDRESS_EXPR is an operand of the instruction to be used with
2727 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2728 bfd_reloc_code_real_type *reloc_type)
2730 unsigned long prev_pinfo, pinfo;
2731 relax_stateT prev_insn_frag_type = 0;
2732 bfd_boolean relaxed_branch = FALSE;
2733 segment_info_type *si = seg_info (now_seg);
2735 /* Mark instruction labels in mips16 mode. */
2736 mips16_mark_labels ();
2738 prev_pinfo = history[0].insn_mo->pinfo;
2739 pinfo = ip->insn_mo->pinfo;
2741 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2743 /* There are a lot of optimizations we could do that we don't.
2744 In particular, we do not, in general, reorder instructions.
2745 If you use gcc with optimization, it will reorder
2746 instructions and generally do much more optimization then we
2747 do here; repeating all that work in the assembler would only
2748 benefit hand written assembly code, and does not seem worth
2750 int nops = (mips_optimize == 0
2751 ? nops_for_insn (history, NULL)
2752 : nops_for_insn_or_target (history, ip));
2756 unsigned long old_frag_offset;
2759 old_frag = frag_now;
2760 old_frag_offset = frag_now_fix ();
2762 for (i = 0; i < nops; i++)
2767 listing_prev_line ();
2768 /* We may be at the start of a variant frag. In case we
2769 are, make sure there is enough space for the frag
2770 after the frags created by listing_prev_line. The
2771 argument to frag_grow here must be at least as large
2772 as the argument to all other calls to frag_grow in
2773 this file. We don't have to worry about being in the
2774 middle of a variant frag, because the variants insert
2775 all needed nop instructions themselves. */
2779 mips_move_labels ();
2781 #ifndef NO_ECOFF_DEBUGGING
2782 if (ECOFF_DEBUGGING)
2783 ecoff_fix_loc (old_frag, old_frag_offset);
2787 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2789 /* Work out how many nops in prev_nop_frag are needed by IP. */
2790 int nops = nops_for_insn_or_target (history, ip);
2791 assert (nops <= prev_nop_frag_holds);
2793 /* Enforce NOPS as a minimum. */
2794 if (nops > prev_nop_frag_required)
2795 prev_nop_frag_required = nops;
2797 if (prev_nop_frag_holds == prev_nop_frag_required)
2799 /* Settle for the current number of nops. Update the history
2800 accordingly (for the benefit of any future .set reorder code). */
2801 prev_nop_frag = NULL;
2802 insert_into_history (prev_nop_frag_since,
2803 prev_nop_frag_holds, NOP_INSN);
2807 /* Allow this instruction to replace one of the nops that was
2808 tentatively added to prev_nop_frag. */
2809 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2810 prev_nop_frag_holds--;
2811 prev_nop_frag_since++;
2816 /* The value passed to dwarf2_emit_insn is the distance between
2817 the beginning of the current instruction and the address that
2818 should be recorded in the debug tables. For MIPS16 debug info
2819 we want to use ISA-encoded addresses, so we pass -1 for an
2820 address higher by one than the current. */
2821 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2824 /* Record the frag type before frag_var. */
2825 if (history[0].frag)
2826 prev_insn_frag_type = history[0].frag->fr_type;
2829 && *reloc_type == BFD_RELOC_16_PCREL_S2
2830 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2831 || pinfo & INSN_COND_BRANCH_LIKELY)
2832 && mips_relax_branch
2833 /* Don't try branch relaxation within .set nomacro, or within
2834 .set noat if we use $at for PIC computations. If it turns
2835 out that the branch was out-of-range, we'll get an error. */
2836 && !mips_opts.warn_about_macros
2837 && (mips_opts.at || mips_pic == NO_PIC)
2838 && !mips_opts.mips16)
2840 relaxed_branch = TRUE;
2841 add_relaxed_insn (ip, (relaxed_branch_length
2843 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2844 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2847 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2848 pinfo & INSN_COND_BRANCH_LIKELY,
2849 pinfo & INSN_WRITE_GPR_31,
2851 address_expr->X_add_symbol,
2852 address_expr->X_add_number);
2853 *reloc_type = BFD_RELOC_UNUSED;
2855 else if (*reloc_type > BFD_RELOC_UNUSED)
2857 /* We need to set up a variant frag. */
2858 assert (mips_opts.mips16 && address_expr != NULL);
2859 add_relaxed_insn (ip, 4, 0,
2861 (*reloc_type - BFD_RELOC_UNUSED,
2862 mips16_small, mips16_ext,
2863 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2864 history[0].mips16_absolute_jump_p),
2865 make_expr_symbol (address_expr), 0);
2867 else if (mips_opts.mips16
2869 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2871 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2872 /* Make sure there is enough room to swap this instruction with
2873 a following jump instruction. */
2875 add_fixed_insn (ip);
2879 if (mips_opts.mips16
2880 && mips_opts.noreorder
2881 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2882 as_warn (_("extended instruction in delay slot"));
2884 if (mips_relax.sequence)
2886 /* If we've reached the end of this frag, turn it into a variant
2887 frag and record the information for the instructions we've
2889 if (frag_room () < 4)
2890 relax_close_frag ();
2891 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2894 if (mips_relax.sequence != 2)
2895 mips_macro_warning.sizes[0] += 4;
2896 if (mips_relax.sequence != 1)
2897 mips_macro_warning.sizes[1] += 4;
2899 if (mips_opts.mips16)
2902 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2904 add_fixed_insn (ip);
2907 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2909 if (address_expr->X_op == O_constant)
2913 switch (*reloc_type)
2916 ip->insn_opcode |= address_expr->X_add_number;
2919 case BFD_RELOC_MIPS_HIGHEST:
2920 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2921 ip->insn_opcode |= tmp & 0xffff;
2924 case BFD_RELOC_MIPS_HIGHER:
2925 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2926 ip->insn_opcode |= tmp & 0xffff;
2929 case BFD_RELOC_HI16_S:
2930 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2931 ip->insn_opcode |= tmp & 0xffff;
2934 case BFD_RELOC_HI16:
2935 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2938 case BFD_RELOC_UNUSED:
2939 case BFD_RELOC_LO16:
2940 case BFD_RELOC_MIPS_GOT_DISP:
2941 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2944 case BFD_RELOC_MIPS_JMP:
2945 if ((address_expr->X_add_number & 3) != 0)
2946 as_bad (_("jump to misaligned address (0x%lx)"),
2947 (unsigned long) address_expr->X_add_number);
2948 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2951 case BFD_RELOC_MIPS16_JMP:
2952 if ((address_expr->X_add_number & 3) != 0)
2953 as_bad (_("jump to misaligned address (0x%lx)"),
2954 (unsigned long) address_expr->X_add_number);
2956 (((address_expr->X_add_number & 0x7c0000) << 3)
2957 | ((address_expr->X_add_number & 0xf800000) >> 7)
2958 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2961 case BFD_RELOC_16_PCREL_S2:
2962 if ((address_expr->X_add_number & 3) != 0)
2963 as_bad (_("branch to misaligned address (0x%lx)"),
2964 (unsigned long) address_expr->X_add_number);
2965 if (mips_relax_branch)
2967 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
2968 as_bad (_("branch address range overflow (0x%lx)"),
2969 (unsigned long) address_expr->X_add_number);
2970 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
2977 else if (*reloc_type < BFD_RELOC_UNUSED)
2980 reloc_howto_type *howto;
2983 /* In a compound relocation, it is the final (outermost)
2984 operator that determines the relocated field. */
2985 for (i = 1; i < 3; i++)
2986 if (reloc_type[i] == BFD_RELOC_UNUSED)
2989 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2992 /* To reproduce this failure try assembling gas/testsuites/
2993 gas/mips/mips16-intermix.s with a mips-ecoff targeted
2995 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
2996 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
2999 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3000 bfd_get_reloc_size (howto),
3002 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3005 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3006 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3007 && ip->fixp[0]->fx_addsy)
3008 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3010 /* These relocations can have an addend that won't fit in
3011 4 octets for 64bit assembly. */
3013 && ! howto->partial_inplace
3014 && (reloc_type[0] == BFD_RELOC_16
3015 || reloc_type[0] == BFD_RELOC_32
3016 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3017 || reloc_type[0] == BFD_RELOC_GPREL16
3018 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3019 || reloc_type[0] == BFD_RELOC_GPREL32
3020 || reloc_type[0] == BFD_RELOC_64
3021 || reloc_type[0] == BFD_RELOC_CTOR
3022 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3023 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3024 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3025 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3026 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3027 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3028 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3029 || hi16_reloc_p (reloc_type[0])
3030 || lo16_reloc_p (reloc_type[0])))
3031 ip->fixp[0]->fx_no_overflow = 1;
3033 if (mips_relax.sequence)
3035 if (mips_relax.first_fixup == 0)
3036 mips_relax.first_fixup = ip->fixp[0];
3038 else if (reloc_needs_lo_p (*reloc_type))
3040 struct mips_hi_fixup *hi_fixup;
3042 /* Reuse the last entry if it already has a matching %lo. */
3043 hi_fixup = mips_hi_fixup_list;
3045 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3047 hi_fixup = ((struct mips_hi_fixup *)
3048 xmalloc (sizeof (struct mips_hi_fixup)));
3049 hi_fixup->next = mips_hi_fixup_list;
3050 mips_hi_fixup_list = hi_fixup;
3052 hi_fixup->fixp = ip->fixp[0];
3053 hi_fixup->seg = now_seg;
3056 /* Add fixups for the second and third relocations, if given.
3057 Note that the ABI allows the second relocation to be
3058 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3059 moment we only use RSS_UNDEF, but we could add support
3060 for the others if it ever becomes necessary. */
3061 for (i = 1; i < 3; i++)
3062 if (reloc_type[i] != BFD_RELOC_UNUSED)
3064 ip->fixp[i] = fix_new (ip->frag, ip->where,
3065 ip->fixp[0]->fx_size, NULL, 0,
3066 FALSE, reloc_type[i]);
3068 /* Use fx_tcbit to mark compound relocs. */
3069 ip->fixp[0]->fx_tcbit = 1;
3070 ip->fixp[i]->fx_tcbit = 1;
3076 /* Update the register mask information. */
3077 if (! mips_opts.mips16)
3079 if (pinfo & INSN_WRITE_GPR_D)
3080 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3081 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3082 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3083 if (pinfo & INSN_READ_GPR_S)
3084 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3085 if (pinfo & INSN_WRITE_GPR_31)
3086 mips_gprmask |= 1 << RA;
3087 if (pinfo & INSN_WRITE_FPR_D)
3088 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3089 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3090 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3091 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3092 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3093 if ((pinfo & INSN_READ_FPR_R) != 0)
3094 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3095 if (pinfo & INSN_COP)
3097 /* We don't keep enough information to sort these cases out.
3098 The itbl support does keep this information however, although
3099 we currently don't support itbl fprmats as part of the cop
3100 instruction. May want to add this support in the future. */
3102 /* Never set the bit for $0, which is always zero. */
3103 mips_gprmask &= ~1 << 0;
3107 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3108 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3109 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3110 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3111 if (pinfo & MIPS16_INSN_WRITE_Z)
3112 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3113 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3114 mips_gprmask |= 1 << TREG;
3115 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3116 mips_gprmask |= 1 << SP;
3117 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3118 mips_gprmask |= 1 << RA;
3119 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3120 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3121 if (pinfo & MIPS16_INSN_READ_Z)
3122 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3123 if (pinfo & MIPS16_INSN_READ_GPR_X)
3124 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3127 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3129 /* Filling the branch delay slot is more complex. We try to
3130 switch the branch with the previous instruction, which we can
3131 do if the previous instruction does not set up a condition
3132 that the branch tests and if the branch is not itself the
3133 target of any branch. */
3134 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3135 || (pinfo & INSN_COND_BRANCH_DELAY))
3137 if (mips_optimize < 2
3138 /* If we have seen .set volatile or .set nomove, don't
3140 || mips_opts.nomove != 0
3141 /* We can't swap if the previous instruction's position
3143 || history[0].fixed_p
3144 /* If the previous previous insn was in a .set
3145 noreorder, we can't swap. Actually, the MIPS
3146 assembler will swap in this situation. However, gcc
3147 configured -with-gnu-as will generate code like
3153 in which we can not swap the bne and INSN. If gcc is
3154 not configured -with-gnu-as, it does not output the
3156 || history[1].noreorder_p
3157 /* If the branch is itself the target of a branch, we
3158 can not swap. We cheat on this; all we check for is
3159 whether there is a label on this instruction. If
3160 there are any branches to anything other than a
3161 label, users must use .set noreorder. */
3162 || si->label_list != NULL
3163 /* If the previous instruction is in a variant frag
3164 other than this branch's one, we cannot do the swap.
3165 This does not apply to the mips16, which uses variant
3166 frags for different purposes. */
3167 || (! mips_opts.mips16
3168 && prev_insn_frag_type == rs_machine_dependent)
3169 /* Check for conflicts between the branch and the instructions
3170 before the candidate delay slot. */
3171 || nops_for_insn (history + 1, ip) > 0
3172 /* Check for conflicts between the swapped sequence and the
3173 target of the branch. */
3174 || nops_for_sequence (2, history + 1, ip, history) > 0
3175 /* We do not swap with a trap instruction, since it
3176 complicates trap handlers to have the trap
3177 instruction be in a delay slot. */
3178 || (prev_pinfo & INSN_TRAP)
3179 /* If the branch reads a register that the previous
3180 instruction sets, we can not swap. */
3181 || (! mips_opts.mips16
3182 && (prev_pinfo & INSN_WRITE_GPR_T)
3183 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3185 || (! mips_opts.mips16
3186 && (prev_pinfo & INSN_WRITE_GPR_D)
3187 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3189 || (mips_opts.mips16
3190 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3192 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3194 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3196 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3198 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3200 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3202 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3203 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3204 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3205 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3206 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3207 && insn_uses_reg (ip,
3208 MIPS16OP_EXTRACT_REG32R
3209 (history[0].insn_opcode),
3211 /* If the branch writes a register that the previous
3212 instruction sets, we can not swap (we know that
3213 branches write only to RD or to $31). */
3214 || (! mips_opts.mips16
3215 && (prev_pinfo & INSN_WRITE_GPR_T)
3216 && (((pinfo & INSN_WRITE_GPR_D)
3217 && (EXTRACT_OPERAND (RT, history[0])
3218 == EXTRACT_OPERAND (RD, *ip)))
3219 || ((pinfo & INSN_WRITE_GPR_31)
3220 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3221 || (! mips_opts.mips16
3222 && (prev_pinfo & INSN_WRITE_GPR_D)
3223 && (((pinfo & INSN_WRITE_GPR_D)
3224 && (EXTRACT_OPERAND (RD, history[0])
3225 == EXTRACT_OPERAND (RD, *ip)))
3226 || ((pinfo & INSN_WRITE_GPR_31)
3227 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3228 || (mips_opts.mips16
3229 && (pinfo & MIPS16_INSN_WRITE_31)
3230 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3231 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3232 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3234 /* If the branch writes a register that the previous
3235 instruction reads, we can not swap (we know that
3236 branches only write to RD or to $31). */
3237 || (! mips_opts.mips16
3238 && (pinfo & INSN_WRITE_GPR_D)
3239 && insn_uses_reg (&history[0],
3240 EXTRACT_OPERAND (RD, *ip),
3242 || (! mips_opts.mips16
3243 && (pinfo & INSN_WRITE_GPR_31)
3244 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3245 || (mips_opts.mips16
3246 && (pinfo & MIPS16_INSN_WRITE_31)
3247 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3248 /* If one instruction sets a condition code and the
3249 other one uses a condition code, we can not swap. */
3250 || ((pinfo & INSN_READ_COND_CODE)
3251 && (prev_pinfo & INSN_WRITE_COND_CODE))
3252 || ((pinfo & INSN_WRITE_COND_CODE)
3253 && (prev_pinfo & INSN_READ_COND_CODE))
3254 /* If the previous instruction uses the PC, we can not
3256 || (mips_opts.mips16
3257 && (prev_pinfo & MIPS16_INSN_READ_PC))
3258 /* If the previous instruction had a fixup in mips16
3259 mode, we can not swap. This normally means that the
3260 previous instruction was a 4 byte branch anyhow. */
3261 || (mips_opts.mips16 && history[0].fixp[0])
3262 /* If the previous instruction is a sync, sync.l, or
3263 sync.p, we can not swap. */
3264 || (prev_pinfo & INSN_SYNC)
3265 /* If the previous instruction is an ERET or
3266 DERET, avoid the swap. */
3267 || (history[0].insn_opcode == INSN_ERET)
3268 || (history[0].insn_opcode == INSN_DERET))
3270 if (mips_opts.mips16
3271 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3272 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3273 && ISA_SUPPORTS_MIPS16E)
3275 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3276 ip->insn_opcode |= 0x0080;
3278 insert_into_history (0, 1, ip);
3282 /* We could do even better for unconditional branches to
3283 portions of this object file; we could pick up the
3284 instruction at the destination, put it in the delay
3285 slot, and bump the destination address. */
3286 insert_into_history (0, 1, ip);
3290 if (mips_relax.sequence)
3291 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3295 /* It looks like we can actually do the swap. */
3296 struct mips_cl_insn delay = history[0];
3297 if (mips_opts.mips16)
3299 know (delay.frag == ip->frag);
3300 move_insn (ip, delay.frag, delay.where);
3301 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3303 else if (relaxed_branch)
3305 /* Add the delay slot instruction to the end of the
3306 current frag and shrink the fixed part of the
3307 original frag. If the branch occupies the tail of
3308 the latter, move it backwards to cover the gap. */
3309 delay.frag->fr_fix -= 4;
3310 if (delay.frag == ip->frag)
3311 move_insn (ip, ip->frag, ip->where - 4);
3312 add_fixed_insn (&delay);
3316 move_insn (&delay, ip->frag, ip->where);
3317 move_insn (ip, history[0].frag, history[0].where);
3321 insert_into_history (0, 1, &delay);
3324 /* If that was an unconditional branch, forget the previous
3325 insn information. */
3326 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3328 mips_no_prev_insn ();
3331 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3333 /* We don't yet optimize a branch likely. What we should do
3334 is look at the target, copy the instruction found there
3335 into the delay slot, and increment the branch to jump to
3336 the next instruction. */
3337 insert_into_history (0, 1, ip);
3341 insert_into_history (0, 1, ip);
3344 insert_into_history (0, 1, ip);
3346 /* We just output an insn, so the next one doesn't have a label. */
3347 mips_clear_insn_labels ();
3350 /* Forget that there was any previous instruction or label. */
3353 mips_no_prev_insn (void)
3355 prev_nop_frag = NULL;
3356 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3357 mips_clear_insn_labels ();
3360 /* This function must be called before we emit something other than
3361 instructions. It is like mips_no_prev_insn except that it inserts
3362 any NOPS that might be needed by previous instructions. */
3365 mips_emit_delays (void)
3367 if (! mips_opts.noreorder)
3369 int nops = nops_for_insn (history, NULL);
3373 add_fixed_insn (NOP_INSN);
3374 mips_move_labels ();
3377 mips_no_prev_insn ();
3380 /* Start a (possibly nested) noreorder block. */
3383 start_noreorder (void)
3385 if (mips_opts.noreorder == 0)
3390 /* None of the instructions before the .set noreorder can be moved. */
3391 for (i = 0; i < ARRAY_SIZE (history); i++)
3392 history[i].fixed_p = 1;
3394 /* Insert any nops that might be needed between the .set noreorder
3395 block and the previous instructions. We will later remove any
3396 nops that turn out not to be needed. */
3397 nops = nops_for_insn (history, NULL);
3400 if (mips_optimize != 0)
3402 /* Record the frag which holds the nop instructions, so
3403 that we can remove them if we don't need them. */
3404 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3405 prev_nop_frag = frag_now;
3406 prev_nop_frag_holds = nops;
3407 prev_nop_frag_required = 0;
3408 prev_nop_frag_since = 0;
3411 for (; nops > 0; --nops)
3412 add_fixed_insn (NOP_INSN);
3414 /* Move on to a new frag, so that it is safe to simply
3415 decrease the size of prev_nop_frag. */
3416 frag_wane (frag_now);
3418 mips_move_labels ();
3420 mips16_mark_labels ();
3421 mips_clear_insn_labels ();
3423 mips_opts.noreorder++;
3424 mips_any_noreorder = 1;
3427 /* End a nested noreorder block. */
3430 end_noreorder (void)
3433 mips_opts.noreorder--;
3434 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3436 /* Commit to inserting prev_nop_frag_required nops and go back to
3437 handling nop insertion the .set reorder way. */
3438 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3439 * (mips_opts.mips16 ? 2 : 4));
3440 insert_into_history (prev_nop_frag_since,
3441 prev_nop_frag_required, NOP_INSN);
3442 prev_nop_frag = NULL;
3446 /* Set up global variables for the start of a new macro. */
3451 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3452 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3453 && (history[0].insn_mo->pinfo
3454 & (INSN_UNCOND_BRANCH_DELAY
3455 | INSN_COND_BRANCH_DELAY
3456 | INSN_COND_BRANCH_LIKELY)) != 0);
3459 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3460 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3461 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3464 macro_warning (relax_substateT subtype)
3466 if (subtype & RELAX_DELAY_SLOT)
3467 return _("Macro instruction expanded into multiple instructions"
3468 " in a branch delay slot");
3469 else if (subtype & RELAX_NOMACRO)
3470 return _("Macro instruction expanded into multiple instructions");
3475 /* Finish up a macro. Emit warnings as appropriate. */
3480 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3482 relax_substateT subtype;
3484 /* Set up the relaxation warning flags. */
3486 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3487 subtype |= RELAX_SECOND_LONGER;
3488 if (mips_opts.warn_about_macros)
3489 subtype |= RELAX_NOMACRO;
3490 if (mips_macro_warning.delay_slot_p)
3491 subtype |= RELAX_DELAY_SLOT;
3493 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3495 /* Either the macro has a single implementation or both
3496 implementations are longer than 4 bytes. Emit the
3498 const char *msg = macro_warning (subtype);
3500 as_warn ("%s", msg);
3504 /* One implementation might need a warning but the other
3505 definitely doesn't. */
3506 mips_macro_warning.first_frag->fr_subtype |= subtype;
3511 /* Read a macro's relocation codes from *ARGS and store them in *R.
3512 The first argument in *ARGS will be either the code for a single
3513 relocation or -1 followed by the three codes that make up a
3514 composite relocation. */
3517 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3521 next = va_arg (*args, int);
3523 r[0] = (bfd_reloc_code_real_type) next;
3525 for (i = 0; i < 3; i++)
3526 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3529 /* Build an instruction created by a macro expansion. This is passed
3530 a pointer to the count of instructions created so far, an
3531 expression, the name of the instruction to build, an operand format
3532 string, and corresponding arguments. */
3535 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3537 const struct mips_opcode *mo;
3538 struct mips_cl_insn insn;
3539 bfd_reloc_code_real_type r[3];
3542 va_start (args, fmt);
3544 if (mips_opts.mips16)
3546 mips16_macro_build (ep, name, fmt, args);
3551 r[0] = BFD_RELOC_UNUSED;
3552 r[1] = BFD_RELOC_UNUSED;
3553 r[2] = BFD_RELOC_UNUSED;
3554 mo = (struct mips_opcode *) hash_find (op_hash, name);
3556 assert (strcmp (name, mo->name) == 0);
3560 /* Search until we get a match for NAME. It is assumed here that
3561 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3562 if (strcmp (fmt, mo->args) == 0
3563 && mo->pinfo != INSN_MACRO
3564 && is_opcode_valid (mo, TRUE))
3569 assert (strcmp (name, mo->name) == 0);
3572 create_insn (&insn, mo);
3590 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3595 /* Note that in the macro case, these arguments are already
3596 in MSB form. (When handling the instruction in the
3597 non-macro case, these arguments are sizes from which
3598 MSB values must be calculated.) */
3599 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3605 /* Note that in the macro case, these arguments are already
3606 in MSBD form. (When handling the instruction in the
3607 non-macro case, these arguments are sizes from which
3608 MSBD values must be calculated.) */
3609 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3613 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3622 INSERT_OPERAND (BP, insn, va_arg (args, int));
3628 INSERT_OPERAND (RT, insn, va_arg (args, int));
3632 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3637 INSERT_OPERAND (FT, insn, va_arg (args, int));
3643 INSERT_OPERAND (RD, insn, va_arg (args, int));
3648 int tmp = va_arg (args, int);
3650 INSERT_OPERAND (RT, insn, tmp);
3651 INSERT_OPERAND (RD, insn, tmp);
3657 INSERT_OPERAND (FS, insn, va_arg (args, int));
3664 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3668 INSERT_OPERAND (FD, insn, va_arg (args, int));
3672 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3676 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3680 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3687 INSERT_OPERAND (RS, insn, va_arg (args, int));
3693 macro_read_relocs (&args, r);
3694 assert (*r == BFD_RELOC_GPREL16
3695 || *r == BFD_RELOC_MIPS_LITERAL
3696 || *r == BFD_RELOC_MIPS_HIGHER
3697 || *r == BFD_RELOC_HI16_S
3698 || *r == BFD_RELOC_LO16
3699 || *r == BFD_RELOC_MIPS_GOT16
3700 || *r == BFD_RELOC_MIPS_CALL16
3701 || *r == BFD_RELOC_MIPS_GOT_DISP
3702 || *r == BFD_RELOC_MIPS_GOT_PAGE
3703 || *r == BFD_RELOC_MIPS_GOT_OFST
3704 || *r == BFD_RELOC_MIPS_GOT_LO16
3705 || *r == BFD_RELOC_MIPS_CALL_LO16);
3709 macro_read_relocs (&args, r);
3711 && (ep->X_op == O_constant
3712 || (ep->X_op == O_symbol
3713 && (*r == BFD_RELOC_MIPS_HIGHEST
3714 || *r == BFD_RELOC_HI16_S
3715 || *r == BFD_RELOC_HI16
3716 || *r == BFD_RELOC_GPREL16
3717 || *r == BFD_RELOC_MIPS_GOT_HI16
3718 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3722 assert (ep != NULL);
3725 * This allows macro() to pass an immediate expression for
3726 * creating short branches without creating a symbol.
3728 * We don't allow branch relaxation for these branches, as
3729 * they should only appear in ".set nomacro" anyway.
3731 if (ep->X_op == O_constant)
3733 if ((ep->X_add_number & 3) != 0)
3734 as_bad (_("branch to misaligned address (0x%lx)"),
3735 (unsigned long) ep->X_add_number);
3736 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3737 as_bad (_("branch address range overflow (0x%lx)"),
3738 (unsigned long) ep->X_add_number);
3739 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3743 *r = BFD_RELOC_16_PCREL_S2;
3747 assert (ep != NULL);
3748 *r = BFD_RELOC_MIPS_JMP;
3752 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3756 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3765 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3767 append_insn (&insn, ep, r);
3771 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3774 struct mips_opcode *mo;
3775 struct mips_cl_insn insn;
3776 bfd_reloc_code_real_type r[3]
3777 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3779 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3781 assert (strcmp (name, mo->name) == 0);
3783 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3787 assert (strcmp (name, mo->name) == 0);
3790 create_insn (&insn, mo);
3808 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3813 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3817 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3821 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3831 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3838 regno = va_arg (args, int);
3839 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3840 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3861 assert (ep != NULL);
3863 if (ep->X_op != O_constant)
3864 *r = (int) BFD_RELOC_UNUSED + c;
3867 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3868 FALSE, &insn.insn_opcode, &insn.use_extend,
3871 *r = BFD_RELOC_UNUSED;
3877 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3884 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3886 append_insn (&insn, ep, r);
3890 * Sign-extend 32-bit mode constants that have bit 31 set and all
3891 * higher bits unset.
3894 normalize_constant_expr (expressionS *ex)
3896 if (ex->X_op == O_constant
3897 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3898 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3903 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3904 * all higher bits unset.
3907 normalize_address_expr (expressionS *ex)
3909 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3910 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3911 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3912 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3917 * Generate a "jalr" instruction with a relocation hint to the called
3918 * function. This occurs in NewABI PIC code.
3921 macro_build_jalr (expressionS *ep)
3930 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3932 fix_new_exp (frag_now, f - frag_now->fr_literal,
3933 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3937 * Generate a "lui" instruction.
3940 macro_build_lui (expressionS *ep, int regnum)
3942 expressionS high_expr;
3943 const struct mips_opcode *mo;
3944 struct mips_cl_insn insn;
3945 bfd_reloc_code_real_type r[3]
3946 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3947 const char *name = "lui";
3948 const char *fmt = "t,u";
3950 assert (! mips_opts.mips16);
3954 if (high_expr.X_op == O_constant)
3956 /* We can compute the instruction now without a relocation entry. */
3957 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3959 *r = BFD_RELOC_UNUSED;
3963 assert (ep->X_op == O_symbol);
3964 /* _gp_disp is a special case, used from s_cpload.
3965 __gnu_local_gp is used if mips_no_shared. */
3966 assert (mips_pic == NO_PIC
3968 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
3969 || (! mips_in_shared
3970 && strcmp (S_GET_NAME (ep->X_add_symbol),
3971 "__gnu_local_gp") == 0));
3972 *r = BFD_RELOC_HI16_S;
3975 mo = hash_find (op_hash, name);
3976 assert (strcmp (name, mo->name) == 0);
3977 assert (strcmp (fmt, mo->args) == 0);
3978 create_insn (&insn, mo);
3980 insn.insn_opcode = insn.insn_mo->match;
3981 INSERT_OPERAND (RT, insn, regnum);
3982 if (*r == BFD_RELOC_UNUSED)
3984 insn.insn_opcode |= high_expr.X_add_number;
3985 append_insn (&insn, NULL, r);
3988 append_insn (&insn, &high_expr, r);
3991 /* Generate a sequence of instructions to do a load or store from a constant
3992 offset off of a base register (breg) into/from a target register (treg),
3993 using AT if necessary. */
3995 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3996 int treg, int breg, int dbl)
3998 assert (ep->X_op == O_constant);
4000 /* Sign-extending 32-bit constants makes their handling easier. */
4002 normalize_constant_expr (ep);
4004 /* Right now, this routine can only handle signed 32-bit constants. */
4005 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4006 as_warn (_("operand overflow"));
4008 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4010 /* Signed 16-bit offset will fit in the op. Easy! */
4011 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4015 /* 32-bit offset, need multiple instructions and AT, like:
4016 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4017 addu $tempreg,$tempreg,$breg
4018 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4019 to handle the complete offset. */
4020 macro_build_lui (ep, AT);
4021 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4022 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4025 as_bad (_("Macro used $at after \".set noat\""));
4030 * Generates code to set the $at register to true (one)
4031 * if reg is less than the immediate expression.
4034 set_at (int reg, int unsignedp)
4036 if (imm_expr.X_op == O_constant
4037 && imm_expr.X_add_number >= -0x8000
4038 && imm_expr.X_add_number < 0x8000)
4039 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4040 AT, reg, BFD_RELOC_LO16);
4043 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4044 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4048 /* Warn if an expression is not a constant. */
4051 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4053 if (ex->X_op == O_big)
4054 as_bad (_("unsupported large constant"));
4055 else if (ex->X_op != O_constant)
4056 as_bad (_("Instruction %s requires absolute expression"),
4059 if (HAVE_32BIT_GPRS)
4060 normalize_constant_expr (ex);
4063 /* Count the leading zeroes by performing a binary chop. This is a
4064 bulky bit of source, but performance is a LOT better for the
4065 majority of values than a simple loop to count the bits:
4066 for (lcnt = 0; (lcnt < 32); lcnt++)
4067 if ((v) & (1 << (31 - lcnt)))
4069 However it is not code size friendly, and the gain will drop a bit
4070 on certain cached systems.
4072 #define COUNT_TOP_ZEROES(v) \
4073 (((v) & ~0xffff) == 0 \
4074 ? ((v) & ~0xff) == 0 \
4075 ? ((v) & ~0xf) == 0 \
4076 ? ((v) & ~0x3) == 0 \
4077 ? ((v) & ~0x1) == 0 \
4082 : ((v) & ~0x7) == 0 \
4085 : ((v) & ~0x3f) == 0 \
4086 ? ((v) & ~0x1f) == 0 \
4089 : ((v) & ~0x7f) == 0 \
4092 : ((v) & ~0xfff) == 0 \
4093 ? ((v) & ~0x3ff) == 0 \
4094 ? ((v) & ~0x1ff) == 0 \
4097 : ((v) & ~0x7ff) == 0 \
4100 : ((v) & ~0x3fff) == 0 \
4101 ? ((v) & ~0x1fff) == 0 \
4104 : ((v) & ~0x7fff) == 0 \
4107 : ((v) & ~0xffffff) == 0 \
4108 ? ((v) & ~0xfffff) == 0 \
4109 ? ((v) & ~0x3ffff) == 0 \
4110 ? ((v) & ~0x1ffff) == 0 \
4113 : ((v) & ~0x7ffff) == 0 \
4116 : ((v) & ~0x3fffff) == 0 \
4117 ? ((v) & ~0x1fffff) == 0 \
4120 : ((v) & ~0x7fffff) == 0 \
4123 : ((v) & ~0xfffffff) == 0 \
4124 ? ((v) & ~0x3ffffff) == 0 \
4125 ? ((v) & ~0x1ffffff) == 0 \
4128 : ((v) & ~0x7ffffff) == 0 \
4131 : ((v) & ~0x3fffffff) == 0 \
4132 ? ((v) & ~0x1fffffff) == 0 \
4135 : ((v) & ~0x7fffffff) == 0 \
4140 * This routine generates the least number of instructions necessary to load
4141 * an absolute expression value into a register.
4144 load_register (int reg, expressionS *ep, int dbl)
4147 expressionS hi32, lo32;
4149 if (ep->X_op != O_big)
4151 assert (ep->X_op == O_constant);
4153 /* Sign-extending 32-bit constants makes their handling easier. */
4155 normalize_constant_expr (ep);
4157 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4159 /* We can handle 16 bit signed values with an addiu to
4160 $zero. No need to ever use daddiu here, since $zero and
4161 the result are always correct in 32 bit mode. */
4162 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4165 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4167 /* We can handle 16 bit unsigned values with an ori to
4169 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4172 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4174 /* 32 bit values require an lui. */
4175 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4176 if ((ep->X_add_number & 0xffff) != 0)
4177 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4182 /* The value is larger than 32 bits. */
4184 if (!dbl || HAVE_32BIT_GPRS)
4188 sprintf_vma (value, ep->X_add_number);
4189 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4190 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4194 if (ep->X_op != O_big)
4197 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4198 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4199 hi32.X_add_number &= 0xffffffff;
4201 lo32.X_add_number &= 0xffffffff;
4205 assert (ep->X_add_number > 2);
4206 if (ep->X_add_number == 3)
4207 generic_bignum[3] = 0;
4208 else if (ep->X_add_number > 4)
4209 as_bad (_("Number larger than 64 bits"));
4210 lo32.X_op = O_constant;
4211 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4212 hi32.X_op = O_constant;
4213 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4216 if (hi32.X_add_number == 0)
4221 unsigned long hi, lo;
4223 if (hi32.X_add_number == (offsetT) 0xffffffff)
4225 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4227 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4230 if (lo32.X_add_number & 0x80000000)
4232 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4233 if (lo32.X_add_number & 0xffff)
4234 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4239 /* Check for 16bit shifted constant. We know that hi32 is
4240 non-zero, so start the mask on the first bit of the hi32
4245 unsigned long himask, lomask;
4249 himask = 0xffff >> (32 - shift);
4250 lomask = (0xffff << shift) & 0xffffffff;
4254 himask = 0xffff << (shift - 32);
4257 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4258 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4262 tmp.X_op = O_constant;
4264 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4265 | (lo32.X_add_number >> shift));
4267 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4268 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4269 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4270 reg, reg, (shift >= 32) ? shift - 32 : shift);
4275 while (shift <= (64 - 16));
4277 /* Find the bit number of the lowest one bit, and store the
4278 shifted value in hi/lo. */
4279 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4280 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4284 while ((lo & 1) == 0)
4289 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4295 while ((hi & 1) == 0)
4304 /* Optimize if the shifted value is a (power of 2) - 1. */
4305 if ((hi == 0 && ((lo + 1) & lo) == 0)
4306 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4308 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4313 /* This instruction will set the register to be all
4315 tmp.X_op = O_constant;
4316 tmp.X_add_number = (offsetT) -1;
4317 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4321 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4322 reg, reg, (bit >= 32) ? bit - 32 : bit);
4324 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4325 reg, reg, (shift >= 32) ? shift - 32 : shift);
4330 /* Sign extend hi32 before calling load_register, because we can
4331 generally get better code when we load a sign extended value. */
4332 if ((hi32.X_add_number & 0x80000000) != 0)
4333 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4334 load_register (reg, &hi32, 0);
4337 if ((lo32.X_add_number & 0xffff0000) == 0)
4341 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4349 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4351 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4352 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4358 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4362 mid16.X_add_number >>= 16;
4363 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4364 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4367 if ((lo32.X_add_number & 0xffff) != 0)
4368 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4372 load_delay_nop (void)
4374 if (!gpr_interlocks)
4375 macro_build (NULL, "nop", "");
4378 /* Load an address into a register. */
4381 load_address (int reg, expressionS *ep, int *used_at)
4383 if (ep->X_op != O_constant
4384 && ep->X_op != O_symbol)
4386 as_bad (_("expression too complex"));
4387 ep->X_op = O_constant;
4390 if (ep->X_op == O_constant)
4392 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4396 if (mips_pic == NO_PIC)
4398 /* If this is a reference to a GP relative symbol, we want
4399 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4401 lui $reg,<sym> (BFD_RELOC_HI16_S)
4402 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4403 If we have an addend, we always use the latter form.
4405 With 64bit address space and a usable $at we want
4406 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4407 lui $at,<sym> (BFD_RELOC_HI16_S)
4408 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4409 daddiu $at,<sym> (BFD_RELOC_LO16)
4413 If $at is already in use, we use a path which is suboptimal
4414 on superscalar processors.
4415 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4416 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4418 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4420 daddiu $reg,<sym> (BFD_RELOC_LO16)
4422 For GP relative symbols in 64bit address space we can use
4423 the same sequence as in 32bit address space. */
4424 if (HAVE_64BIT_SYMBOLS)
4426 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4427 && !nopic_need_relax (ep->X_add_symbol, 1))
4429 relax_start (ep->X_add_symbol);
4430 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4431 mips_gp_register, BFD_RELOC_GPREL16);
4435 if (*used_at == 0 && mips_opts.at)
4437 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4438 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4439 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4440 BFD_RELOC_MIPS_HIGHER);
4441 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4442 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4443 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4448 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4449 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4450 BFD_RELOC_MIPS_HIGHER);
4451 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4452 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4453 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4454 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4457 if (mips_relax.sequence)
4462 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4463 && !nopic_need_relax (ep->X_add_symbol, 1))
4465 relax_start (ep->X_add_symbol);
4466 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4467 mips_gp_register, BFD_RELOC_GPREL16);
4470 macro_build_lui (ep, reg);
4471 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4472 reg, reg, BFD_RELOC_LO16);
4473 if (mips_relax.sequence)
4477 else if (!mips_big_got)
4481 /* If this is a reference to an external symbol, we want
4482 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4484 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4486 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4487 If there is a constant, it must be added in after.
4489 If we have NewABI, we want
4490 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4491 unless we're referencing a global symbol with a non-zero
4492 offset, in which case cst must be added separately. */
4495 if (ep->X_add_number)
4497 ex.X_add_number = ep->X_add_number;
4498 ep->X_add_number = 0;
4499 relax_start (ep->X_add_symbol);
4500 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4501 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4502 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4503 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4504 ex.X_op = O_constant;
4505 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4506 reg, reg, BFD_RELOC_LO16);
4507 ep->X_add_number = ex.X_add_number;
4510 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4511 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4512 if (mips_relax.sequence)
4517 ex.X_add_number = ep->X_add_number;
4518 ep->X_add_number = 0;
4519 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4520 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4522 relax_start (ep->X_add_symbol);
4524 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4528 if (ex.X_add_number != 0)
4530 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4531 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4532 ex.X_op = O_constant;
4533 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4534 reg, reg, BFD_RELOC_LO16);
4538 else if (mips_big_got)
4542 /* This is the large GOT case. If this is a reference to an
4543 external symbol, we want
4544 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4546 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4548 Otherwise, for a reference to a local symbol in old ABI, we want
4549 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4551 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4552 If there is a constant, it must be added in after.
4554 In the NewABI, for local symbols, with or without offsets, we want:
4555 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4556 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4560 ex.X_add_number = ep->X_add_number;
4561 ep->X_add_number = 0;
4562 relax_start (ep->X_add_symbol);
4563 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4565 reg, reg, mips_gp_register);
4566 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4567 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4568 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4569 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4570 else if (ex.X_add_number)
4572 ex.X_op = O_constant;
4573 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4577 ep->X_add_number = ex.X_add_number;
4579 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4580 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4581 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4582 BFD_RELOC_MIPS_GOT_OFST);
4587 ex.X_add_number = ep->X_add_number;
4588 ep->X_add_number = 0;
4589 relax_start (ep->X_add_symbol);
4590 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4591 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4592 reg, reg, mips_gp_register);
4593 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4594 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4596 if (reg_needs_delay (mips_gp_register))
4598 /* We need a nop before loading from $gp. This special
4599 check is required because the lui which starts the main
4600 instruction stream does not refer to $gp, and so will not
4601 insert the nop which may be required. */
4602 macro_build (NULL, "nop", "");
4604 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4605 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4607 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4611 if (ex.X_add_number != 0)
4613 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4614 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4615 ex.X_op = O_constant;
4616 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4624 if (!mips_opts.at && *used_at == 1)
4625 as_bad (_("Macro used $at after \".set noat\""));
4628 /* Move the contents of register SOURCE into register DEST. */
4631 move_register (int dest, int source)
4633 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4637 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4638 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4639 The two alternatives are:
4641 Global symbol Local sybmol
4642 ------------- ------------
4643 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4645 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4647 load_got_offset emits the first instruction and add_got_offset
4648 emits the second for a 16-bit offset or add_got_offset_hilo emits
4649 a sequence to add a 32-bit offset using a scratch register. */
4652 load_got_offset (int dest, expressionS *local)
4657 global.X_add_number = 0;
4659 relax_start (local->X_add_symbol);
4660 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4661 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4663 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4664 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4669 add_got_offset (int dest, expressionS *local)
4673 global.X_op = O_constant;
4674 global.X_op_symbol = NULL;
4675 global.X_add_symbol = NULL;
4676 global.X_add_number = local->X_add_number;
4678 relax_start (local->X_add_symbol);
4679 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4680 dest, dest, BFD_RELOC_LO16);
4682 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4687 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4690 int hold_mips_optimize;
4692 global.X_op = O_constant;
4693 global.X_op_symbol = NULL;
4694 global.X_add_symbol = NULL;
4695 global.X_add_number = local->X_add_number;
4697 relax_start (local->X_add_symbol);
4698 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4700 /* Set mips_optimize around the lui instruction to avoid
4701 inserting an unnecessary nop after the lw. */
4702 hold_mips_optimize = mips_optimize;
4704 macro_build_lui (&global, tmp);
4705 mips_optimize = hold_mips_optimize;
4706 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4709 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4714 * This routine implements the seemingly endless macro or synthesized
4715 * instructions and addressing modes in the mips assembly language. Many
4716 * of these macros are simple and are similar to each other. These could
4717 * probably be handled by some kind of table or grammar approach instead of
4718 * this verbose method. Others are not simple macros but are more like
4719 * optimizing code generation.
4720 * One interesting optimization is when several store macros appear
4721 * consecutively that would load AT with the upper half of the same address.
4722 * The ensuing load upper instructions are ommited. This implies some kind
4723 * of global optimization. We currently only optimize within a single macro.
4724 * For many of the load and store macros if the address is specified as a
4725 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4726 * first load register 'at' with zero and use it as the base register. The
4727 * mips assembler simply uses register $zero. Just one tiny optimization
4731 macro (struct mips_cl_insn *ip)
4733 unsigned int treg, sreg, dreg, breg;
4734 unsigned int tempreg;
4749 bfd_reloc_code_real_type r;
4750 int hold_mips_optimize;
4752 assert (! mips_opts.mips16);
4754 treg = (ip->insn_opcode >> 16) & 0x1f;
4755 dreg = (ip->insn_opcode >> 11) & 0x1f;
4756 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4757 mask = ip->insn_mo->mask;
4759 expr1.X_op = O_constant;
4760 expr1.X_op_symbol = NULL;
4761 expr1.X_add_symbol = NULL;
4762 expr1.X_add_number = 1;
4776 expr1.X_add_number = 8;
4777 macro_build (&expr1, "bgez", "s,p", sreg);
4779 macro_build (NULL, "nop", "", 0);
4781 move_register (dreg, sreg);
4782 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4805 if (imm_expr.X_op == O_constant
4806 && imm_expr.X_add_number >= -0x8000
4807 && imm_expr.X_add_number < 0x8000)
4809 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4813 load_register (AT, &imm_expr, dbl);
4814 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4833 if (imm_expr.X_op == O_constant
4834 && imm_expr.X_add_number >= 0
4835 && imm_expr.X_add_number < 0x10000)
4837 if (mask != M_NOR_I)
4838 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4841 macro_build (&imm_expr, "ori", "t,r,i",
4842 treg, sreg, BFD_RELOC_LO16);
4843 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4849 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4850 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4854 switch (imm_expr.X_add_number)
4857 macro_build (NULL, "nop", "");
4860 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4863 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4864 (int)imm_expr.X_add_number);
4883 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4885 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4889 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4890 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4898 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4903 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4907 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4908 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4914 /* check for > max integer */
4915 maxnum = 0x7fffffff;
4916 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4923 if (imm_expr.X_op == O_constant
4924 && imm_expr.X_add_number >= maxnum
4925 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4928 /* result is always false */
4930 macro_build (NULL, "nop", "", 0);
4932 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4935 if (imm_expr.X_op != O_constant)
4936 as_bad (_("Unsupported large constant"));
4937 ++imm_expr.X_add_number;
4941 if (mask == M_BGEL_I)
4943 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4945 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4948 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4950 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4953 maxnum = 0x7fffffff;
4954 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4961 maxnum = - maxnum - 1;
4962 if (imm_expr.X_op == O_constant
4963 && imm_expr.X_add_number <= maxnum
4964 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4967 /* result is always true */
4968 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4969 macro_build (&offset_expr, "b", "p");
4974 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4984 macro_build (&offset_expr, likely ? "beql" : "beq",
4989 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4990 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4998 && imm_expr.X_op == O_constant
4999 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5001 if (imm_expr.X_op != O_constant)
5002 as_bad (_("Unsupported large constant"));
5003 ++imm_expr.X_add_number;
5007 if (mask == M_BGEUL_I)
5009 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5011 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5013 macro_build (&offset_expr, likely ? "bnel" : "bne",
5019 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5027 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5032 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5036 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5037 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5045 macro_build (&offset_expr, likely ? "bnel" : "bne",
5052 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5053 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5061 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5066 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5070 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5071 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5077 maxnum = 0x7fffffff;
5078 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5085 if (imm_expr.X_op == O_constant
5086 && imm_expr.X_add_number >= maxnum
5087 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5089 if (imm_expr.X_op != O_constant)
5090 as_bad (_("Unsupported large constant"));
5091 ++imm_expr.X_add_number;
5095 if (mask == M_BLTL_I)
5097 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5099 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5102 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5104 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5109 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5117 macro_build (&offset_expr, likely ? "beql" : "beq",
5124 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5125 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5133 && imm_expr.X_op == O_constant
5134 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5136 if (imm_expr.X_op != O_constant)
5137 as_bad (_("Unsupported large constant"));
5138 ++imm_expr.X_add_number;
5142 if (mask == M_BLTUL_I)
5144 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5146 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5148 macro_build (&offset_expr, likely ? "beql" : "beq",
5154 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5162 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5167 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5171 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5172 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5182 macro_build (&offset_expr, likely ? "bnel" : "bne",
5187 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5188 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5196 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5198 as_bad (_("Unsupported large constant"));
5203 pos = (unsigned long) imm_expr.X_add_number;
5204 size = (unsigned long) imm2_expr.X_add_number;
5209 as_bad (_("Improper position (%lu)"), pos);
5212 if (size == 0 || size > 64
5213 || (pos + size - 1) > 63)
5215 as_bad (_("Improper extract size (%lu, position %lu)"),
5220 if (size <= 32 && pos < 32)
5225 else if (size <= 32)
5235 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5244 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5246 as_bad (_("Unsupported large constant"));
5251 pos = (unsigned long) imm_expr.X_add_number;
5252 size = (unsigned long) imm2_expr.X_add_number;
5257 as_bad (_("Improper position (%lu)"), pos);
5260 if (size == 0 || size > 64
5261 || (pos + size - 1) > 63)
5263 as_bad (_("Improper insert size (%lu, position %lu)"),
5268 if (pos < 32 && (pos + size - 1) < 32)
5283 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5284 (int) (pos + size - 1));
5300 as_warn (_("Divide by zero."));
5302 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5304 macro_build (NULL, "break", "c", 7);
5311 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5312 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5316 expr1.X_add_number = 8;
5317 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5318 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5319 macro_build (NULL, "break", "c", 7);
5321 expr1.X_add_number = -1;
5323 load_register (AT, &expr1, dbl);
5324 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5325 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5328 expr1.X_add_number = 1;
5329 load_register (AT, &expr1, dbl);
5330 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5334 expr1.X_add_number = 0x80000000;
5335 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5339 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5340 /* We want to close the noreorder block as soon as possible, so
5341 that later insns are available for delay slot filling. */
5346 expr1.X_add_number = 8;
5347 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5348 macro_build (NULL, "nop", "", 0);
5350 /* We want to close the noreorder block as soon as possible, so
5351 that later insns are available for delay slot filling. */
5354 macro_build (NULL, "break", "c", 6);
5356 macro_build (NULL, s, "d", dreg);
5395 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5397 as_warn (_("Divide by zero."));
5399 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5401 macro_build (NULL, "break", "c", 7);
5404 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5406 if (strcmp (s2, "mflo") == 0)
5407 move_register (dreg, sreg);
5409 move_register (dreg, 0);
5412 if (imm_expr.X_op == O_constant
5413 && imm_expr.X_add_number == -1
5414 && s[strlen (s) - 1] != 'u')
5416 if (strcmp (s2, "mflo") == 0)
5418 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5421 move_register (dreg, 0);
5426 load_register (AT, &imm_expr, dbl);
5427 macro_build (NULL, s, "z,s,t", sreg, AT);
5428 macro_build (NULL, s2, "d", dreg);
5450 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5451 macro_build (NULL, s, "z,s,t", sreg, treg);
5452 /* We want to close the noreorder block as soon as possible, so
5453 that later insns are available for delay slot filling. */
5458 expr1.X_add_number = 8;
5459 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5460 macro_build (NULL, s, "z,s,t", sreg, treg);
5462 /* We want to close the noreorder block as soon as possible, so
5463 that later insns are available for delay slot filling. */
5465 macro_build (NULL, "break", "c", 7);
5467 macro_build (NULL, s2, "d", dreg);
5479 /* Load the address of a symbol into a register. If breg is not
5480 zero, we then add a base register to it. */
5482 if (dbl && HAVE_32BIT_GPRS)
5483 as_warn (_("dla used to load 32-bit register"));
5485 if (! dbl && HAVE_64BIT_OBJECTS)
5486 as_warn (_("la used to load 64-bit address"));
5488 if (offset_expr.X_op == O_constant
5489 && offset_expr.X_add_number >= -0x8000
5490 && offset_expr.X_add_number < 0x8000)
5492 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5493 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5497 if (mips_opts.at && (treg == breg))
5507 if (offset_expr.X_op != O_symbol
5508 && offset_expr.X_op != O_constant)
5510 as_bad (_("expression too complex"));
5511 offset_expr.X_op = O_constant;
5514 if (offset_expr.X_op == O_constant)
5515 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5516 else if (mips_pic == NO_PIC)
5518 /* If this is a reference to a GP relative symbol, we want
5519 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5521 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5522 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5523 If we have a constant, we need two instructions anyhow,
5524 so we may as well always use the latter form.
5526 With 64bit address space and a usable $at we want
5527 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5528 lui $at,<sym> (BFD_RELOC_HI16_S)
5529 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5530 daddiu $at,<sym> (BFD_RELOC_LO16)
5532 daddu $tempreg,$tempreg,$at
5534 If $at is already in use, we use a path which is suboptimal
5535 on superscalar processors.
5536 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5537 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5539 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5541 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5543 For GP relative symbols in 64bit address space we can use
5544 the same sequence as in 32bit address space. */
5545 if (HAVE_64BIT_SYMBOLS)
5547 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5548 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5550 relax_start (offset_expr.X_add_symbol);
5551 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5552 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5556 if (used_at == 0 && mips_opts.at)
5558 macro_build (&offset_expr, "lui", "t,u",
5559 tempreg, BFD_RELOC_MIPS_HIGHEST);
5560 macro_build (&offset_expr, "lui", "t,u",
5561 AT, BFD_RELOC_HI16_S);
5562 macro_build (&offset_expr, "daddiu", "t,r,j",
5563 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5564 macro_build (&offset_expr, "daddiu", "t,r,j",
5565 AT, AT, BFD_RELOC_LO16);
5566 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5567 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5572 macro_build (&offset_expr, "lui", "t,u",
5573 tempreg, BFD_RELOC_MIPS_HIGHEST);
5574 macro_build (&offset_expr, "daddiu", "t,r,j",
5575 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5576 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5577 macro_build (&offset_expr, "daddiu", "t,r,j",
5578 tempreg, tempreg, BFD_RELOC_HI16_S);
5579 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5580 macro_build (&offset_expr, "daddiu", "t,r,j",
5581 tempreg, tempreg, BFD_RELOC_LO16);
5584 if (mips_relax.sequence)
5589 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5590 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5592 relax_start (offset_expr.X_add_symbol);
5593 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5594 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5597 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5598 as_bad (_("offset too large"));
5599 macro_build_lui (&offset_expr, tempreg);
5600 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5601 tempreg, tempreg, BFD_RELOC_LO16);
5602 if (mips_relax.sequence)
5606 else if (!mips_big_got && !HAVE_NEWABI)
5608 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5610 /* If this is a reference to an external symbol, and there
5611 is no constant, we want
5612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5613 or for lca or if tempreg is PIC_CALL_REG
5614 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5615 For a local symbol, we want
5616 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5618 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5620 If we have a small constant, and this is a reference to
5621 an external symbol, we want
5622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5624 addiu $tempreg,$tempreg,<constant>
5625 For a local symbol, we want the same instruction
5626 sequence, but we output a BFD_RELOC_LO16 reloc on the
5629 If we have a large constant, and this is a reference to
5630 an external symbol, we want
5631 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5632 lui $at,<hiconstant>
5633 addiu $at,$at,<loconstant>
5634 addu $tempreg,$tempreg,$at
5635 For a local symbol, we want the same instruction
5636 sequence, but we output a BFD_RELOC_LO16 reloc on the
5640 if (offset_expr.X_add_number == 0)
5642 if (mips_pic == SVR4_PIC
5644 && (call || tempreg == PIC_CALL_REG))
5645 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5647 relax_start (offset_expr.X_add_symbol);
5648 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5649 lw_reloc_type, mips_gp_register);
5652 /* We're going to put in an addu instruction using
5653 tempreg, so we may as well insert the nop right
5658 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5659 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5661 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5662 tempreg, tempreg, BFD_RELOC_LO16);
5664 /* FIXME: If breg == 0, and the next instruction uses
5665 $tempreg, then if this variant case is used an extra
5666 nop will be generated. */
5668 else if (offset_expr.X_add_number >= -0x8000
5669 && offset_expr.X_add_number < 0x8000)
5671 load_got_offset (tempreg, &offset_expr);
5673 add_got_offset (tempreg, &offset_expr);
5677 expr1.X_add_number = offset_expr.X_add_number;
5678 offset_expr.X_add_number =
5679 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5680 load_got_offset (tempreg, &offset_expr);
5681 offset_expr.X_add_number = expr1.X_add_number;
5682 /* If we are going to add in a base register, and the
5683 target register and the base register are the same,
5684 then we are using AT as a temporary register. Since
5685 we want to load the constant into AT, we add our
5686 current AT (from the global offset table) and the
5687 register into the register now, and pretend we were
5688 not using a base register. */
5692 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5697 add_got_offset_hilo (tempreg, &offset_expr, AT);
5701 else if (!mips_big_got && HAVE_NEWABI)
5703 int add_breg_early = 0;
5705 /* If this is a reference to an external, and there is no
5706 constant, or local symbol (*), with or without a
5708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5709 or for lca or if tempreg is PIC_CALL_REG
5710 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5712 If we have a small constant, and this is a reference to
5713 an external symbol, we want
5714 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5715 addiu $tempreg,$tempreg,<constant>
5717 If we have a large constant, and this is a reference to
5718 an external symbol, we want
5719 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5720 lui $at,<hiconstant>
5721 addiu $at,$at,<loconstant>
5722 addu $tempreg,$tempreg,$at
5724 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5725 local symbols, even though it introduces an additional
5728 if (offset_expr.X_add_number)
5730 expr1.X_add_number = offset_expr.X_add_number;
5731 offset_expr.X_add_number = 0;
5733 relax_start (offset_expr.X_add_symbol);
5734 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5735 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5737 if (expr1.X_add_number >= -0x8000
5738 && expr1.X_add_number < 0x8000)
5740 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5741 tempreg, tempreg, BFD_RELOC_LO16);
5743 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5747 /* If we are going to add in a base register, and the
5748 target register and the base register are the same,
5749 then we are using AT as a temporary register. Since
5750 we want to load the constant into AT, we add our
5751 current AT (from the global offset table) and the
5752 register into the register now, and pretend we were
5753 not using a base register. */
5758 assert (tempreg == AT);
5759 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5765 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5766 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5772 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5775 offset_expr.X_add_number = expr1.X_add_number;
5777 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5778 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5781 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5782 treg, tempreg, breg);
5788 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5790 relax_start (offset_expr.X_add_symbol);
5791 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5792 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5794 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5795 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5800 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5801 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5804 else if (mips_big_got && !HAVE_NEWABI)
5807 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5808 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5809 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5811 /* This is the large GOT case. If this is a reference to an
5812 external symbol, and there is no constant, we want
5813 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5814 addu $tempreg,$tempreg,$gp
5815 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5816 or for lca or if tempreg is PIC_CALL_REG
5817 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5818 addu $tempreg,$tempreg,$gp
5819 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5820 For a local symbol, we want
5821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5823 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5825 If we have a small constant, and this is a reference to
5826 an external symbol, we want
5827 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5828 addu $tempreg,$tempreg,$gp
5829 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5831 addiu $tempreg,$tempreg,<constant>
5832 For a local symbol, we want
5833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5835 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5837 If we have a large constant, and this is a reference to
5838 an external symbol, we want
5839 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5840 addu $tempreg,$tempreg,$gp
5841 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5842 lui $at,<hiconstant>
5843 addiu $at,$at,<loconstant>
5844 addu $tempreg,$tempreg,$at
5845 For a local symbol, we want
5846 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5847 lui $at,<hiconstant>
5848 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5849 addu $tempreg,$tempreg,$at
5852 expr1.X_add_number = offset_expr.X_add_number;
5853 offset_expr.X_add_number = 0;
5854 relax_start (offset_expr.X_add_symbol);
5855 gpdelay = reg_needs_delay (mips_gp_register);
5856 if (expr1.X_add_number == 0 && breg == 0
5857 && (call || tempreg == PIC_CALL_REG))
5859 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5860 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5862 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5863 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5864 tempreg, tempreg, mips_gp_register);
5865 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5866 tempreg, lw_reloc_type, tempreg);
5867 if (expr1.X_add_number == 0)
5871 /* We're going to put in an addu instruction using
5872 tempreg, so we may as well insert the nop right
5877 else if (expr1.X_add_number >= -0x8000
5878 && expr1.X_add_number < 0x8000)
5881 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5882 tempreg, tempreg, BFD_RELOC_LO16);
5888 /* If we are going to add in a base register, and the
5889 target register and the base register are the same,
5890 then we are using AT as a temporary register. Since
5891 we want to load the constant into AT, we add our
5892 current AT (from the global offset table) and the
5893 register into the register now, and pretend we were
5894 not using a base register. */
5899 assert (tempreg == AT);
5901 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5906 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5907 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5911 offset_expr.X_add_number =
5912 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5917 /* This is needed because this instruction uses $gp, but
5918 the first instruction on the main stream does not. */
5919 macro_build (NULL, "nop", "");
5922 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5923 local_reloc_type, mips_gp_register);
5924 if (expr1.X_add_number >= -0x8000
5925 && expr1.X_add_number < 0x8000)
5928 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5929 tempreg, tempreg, BFD_RELOC_LO16);
5930 /* FIXME: If add_number is 0, and there was no base
5931 register, the external symbol case ended with a load,
5932 so if the symbol turns out to not be external, and
5933 the next instruction uses tempreg, an unnecessary nop
5934 will be inserted. */
5940 /* We must add in the base register now, as in the
5941 external symbol case. */
5942 assert (tempreg == AT);
5944 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5947 /* We set breg to 0 because we have arranged to add
5948 it in in both cases. */
5952 macro_build_lui (&expr1, AT);
5953 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5954 AT, AT, BFD_RELOC_LO16);
5955 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5956 tempreg, tempreg, AT);
5961 else if (mips_big_got && HAVE_NEWABI)
5963 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5964 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5965 int add_breg_early = 0;
5967 /* This is the large GOT case. If this is a reference to an
5968 external symbol, and there is no constant, we want
5969 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5970 add $tempreg,$tempreg,$gp
5971 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5972 or for lca or if tempreg is PIC_CALL_REG
5973 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5974 add $tempreg,$tempreg,$gp
5975 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5977 If we have a small constant, and this is a reference to
5978 an external symbol, we want
5979 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5980 add $tempreg,$tempreg,$gp
5981 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5982 addi $tempreg,$tempreg,<constant>
5984 If we have a large constant, and this is a reference to
5985 an external symbol, we want
5986 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5987 addu $tempreg,$tempreg,$gp
5988 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5989 lui $at,<hiconstant>
5990 addi $at,$at,<loconstant>
5991 add $tempreg,$tempreg,$at
5993 If we have NewABI, and we know it's a local symbol, we want
5994 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5995 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5996 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5998 relax_start (offset_expr.X_add_symbol);
6000 expr1.X_add_number = offset_expr.X_add_number;
6001 offset_expr.X_add_number = 0;
6003 if (expr1.X_add_number == 0 && breg == 0
6004 && (call || tempreg == PIC_CALL_REG))
6006 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6007 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6009 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6011 tempreg, tempreg, mips_gp_register);
6012 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6013 tempreg, lw_reloc_type, tempreg);
6015 if (expr1.X_add_number == 0)
6017 else if (expr1.X_add_number >= -0x8000
6018 && expr1.X_add_number < 0x8000)
6020 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6021 tempreg, tempreg, BFD_RELOC_LO16);
6023 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6027 /* If we are going to add in a base register, and the
6028 target register and the base register are the same,
6029 then we are using AT as a temporary register. Since
6030 we want to load the constant into AT, we add our
6031 current AT (from the global offset table) and the
6032 register into the register now, and pretend we were
6033 not using a base register. */
6038 assert (tempreg == AT);
6039 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6045 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6046 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6051 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6054 offset_expr.X_add_number = expr1.X_add_number;
6055 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6056 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6057 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6058 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6062 treg, tempreg, breg);
6072 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6077 unsigned long temp = (treg << 16) | (0x01);
6078 macro_build (NULL, "c2", "C", temp);
6080 /* AT is not used, just return */
6085 unsigned long temp = (0x02);
6086 macro_build (NULL, "c2", "C", temp);
6088 /* AT is not used, just return */
6093 unsigned long temp = (treg << 16) | (0x02);
6094 macro_build (NULL, "c2", "C", temp);
6096 /* AT is not used, just return */
6100 macro_build (NULL, "c2", "C", 3);
6101 /* AT is not used, just return */
6106 unsigned long temp = (treg << 16) | 0x03;
6107 macro_build (NULL, "c2", "C", temp);
6109 /* AT is not used, just return */
6113 /* The j instruction may not be used in PIC code, since it
6114 requires an absolute address. We convert it to a b
6116 if (mips_pic == NO_PIC)
6117 macro_build (&offset_expr, "j", "a");
6119 macro_build (&offset_expr, "b", "p");
6122 /* The jal instructions must be handled as macros because when
6123 generating PIC code they expand to multi-instruction
6124 sequences. Normally they are simple instructions. */
6129 if (mips_pic == NO_PIC)
6130 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6133 if (sreg != PIC_CALL_REG)
6134 as_warn (_("MIPS PIC call to register other than $25"));
6136 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6137 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6139 if (mips_cprestore_offset < 0)
6140 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6143 if (! mips_frame_reg_valid)
6145 as_warn (_("No .frame pseudo-op used in PIC code"));
6146 /* Quiet this warning. */
6147 mips_frame_reg_valid = 1;
6149 if (! mips_cprestore_valid)
6151 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6152 /* Quiet this warning. */
6153 mips_cprestore_valid = 1;
6155 expr1.X_add_number = mips_cprestore_offset;
6156 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6159 HAVE_64BIT_ADDRESSES);
6167 if (mips_pic == NO_PIC)
6168 macro_build (&offset_expr, "jal", "a");
6169 else if (mips_pic == SVR4_PIC)
6171 /* If this is a reference to an external symbol, and we are
6172 using a small GOT, we want
6173 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6177 lw $gp,cprestore($sp)
6178 The cprestore value is set using the .cprestore
6179 pseudo-op. If we are using a big GOT, we want
6180 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6182 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6186 lw $gp,cprestore($sp)
6187 If the symbol is not external, we want
6188 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6190 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6193 lw $gp,cprestore($sp)
6195 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6196 sequences above, minus nops, unless the symbol is local,
6197 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6203 relax_start (offset_expr.X_add_symbol);
6204 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6205 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6208 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6209 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6215 relax_start (offset_expr.X_add_symbol);
6216 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6217 BFD_RELOC_MIPS_CALL_HI16);
6218 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6219 PIC_CALL_REG, mips_gp_register);
6220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6221 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6224 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6225 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6227 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6228 PIC_CALL_REG, PIC_CALL_REG,
6229 BFD_RELOC_MIPS_GOT_OFST);
6233 macro_build_jalr (&offset_expr);
6237 relax_start (offset_expr.X_add_symbol);
6240 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6241 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6250 gpdelay = reg_needs_delay (mips_gp_register);
6251 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6252 BFD_RELOC_MIPS_CALL_HI16);
6253 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6254 PIC_CALL_REG, mips_gp_register);
6255 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6256 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6261 macro_build (NULL, "nop", "");
6263 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6264 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6267 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6268 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6270 macro_build_jalr (&offset_expr);
6272 if (mips_cprestore_offset < 0)
6273 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6276 if (! mips_frame_reg_valid)
6278 as_warn (_("No .frame pseudo-op used in PIC code"));
6279 /* Quiet this warning. */
6280 mips_frame_reg_valid = 1;
6282 if (! mips_cprestore_valid)
6284 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6285 /* Quiet this warning. */
6286 mips_cprestore_valid = 1;
6288 if (mips_opts.noreorder)
6289 macro_build (NULL, "nop", "");
6290 expr1.X_add_number = mips_cprestore_offset;
6291 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6294 HAVE_64BIT_ADDRESSES);
6298 else if (mips_pic == VXWORKS_PIC)
6299 as_bad (_("Non-PIC jump used in PIC library"));
6322 /* Itbl support may require additional care here. */
6327 /* Itbl support may require additional care here. */
6332 /* Itbl support may require additional care here. */
6337 /* Itbl support may require additional care here. */
6350 /* Itbl support may require additional care here. */
6355 /* Itbl support may require additional care here. */
6360 /* Itbl support may require additional care here. */
6380 if (breg == treg || coproc || lr)
6401 /* Itbl support may require additional care here. */
6406 /* Itbl support may require additional care here. */
6411 /* Itbl support may require additional care here. */
6416 /* Itbl support may require additional care here. */
6437 /* Itbl support may require additional care here. */
6441 /* Itbl support may require additional care here. */
6446 /* Itbl support may require additional care here. */
6459 && NO_ISA_COP (mips_opts.arch)
6460 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6462 as_bad (_("opcode not supported on this processor: %s"),
6463 mips_cpu_info_from_arch (mips_opts.arch)->name);
6467 /* Itbl support may require additional care here. */
6468 if (mask == M_LWC1_AB
6469 || mask == M_SWC1_AB
6470 || mask == M_LDC1_AB
6471 || mask == M_SDC1_AB
6475 else if (mask == M_CACHE_AB)
6482 if (offset_expr.X_op != O_constant
6483 && offset_expr.X_op != O_symbol)
6485 as_bad (_("expression too complex"));
6486 offset_expr.X_op = O_constant;
6489 if (HAVE_32BIT_ADDRESSES
6490 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6494 sprintf_vma (value, offset_expr.X_add_number);
6495 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6498 /* A constant expression in PIC code can be handled just as it
6499 is in non PIC code. */
6500 if (offset_expr.X_op == O_constant)
6502 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6503 & ~(bfd_vma) 0xffff);
6504 normalize_address_expr (&expr1);
6505 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6507 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6508 tempreg, tempreg, breg);
6509 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6511 else if (mips_pic == NO_PIC)
6513 /* If this is a reference to a GP relative symbol, and there
6514 is no base register, we want
6515 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6516 Otherwise, if there is no base register, we want
6517 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6518 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6519 If we have a constant, we need two instructions anyhow,
6520 so we always use the latter form.
6522 If we have a base register, and this is a reference to a
6523 GP relative symbol, we want
6524 addu $tempreg,$breg,$gp
6525 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6527 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6528 addu $tempreg,$tempreg,$breg
6529 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6530 With a constant we always use the latter case.
6532 With 64bit address space and no base register and $at usable,
6534 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6535 lui $at,<sym> (BFD_RELOC_HI16_S)
6536 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6539 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6540 If we have a base register, we want
6541 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6542 lui $at,<sym> (BFD_RELOC_HI16_S)
6543 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6547 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6549 Without $at we can't generate the optimal path for superscalar
6550 processors here since this would require two temporary registers.
6551 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6552 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6554 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6556 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6557 If we have a base register, we want
6558 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6559 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6561 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6563 daddu $tempreg,$tempreg,$breg
6564 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6566 For GP relative symbols in 64bit address space we can use
6567 the same sequence as in 32bit address space. */
6568 if (HAVE_64BIT_SYMBOLS)
6570 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6571 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6573 relax_start (offset_expr.X_add_symbol);
6576 macro_build (&offset_expr, s, fmt, treg,
6577 BFD_RELOC_GPREL16, mips_gp_register);
6581 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6582 tempreg, breg, mips_gp_register);
6583 macro_build (&offset_expr, s, fmt, treg,
6584 BFD_RELOC_GPREL16, tempreg);
6589 if (used_at == 0 && mips_opts.at)
6591 macro_build (&offset_expr, "lui", "t,u", tempreg,
6592 BFD_RELOC_MIPS_HIGHEST);
6593 macro_build (&offset_expr, "lui", "t,u", AT,
6595 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6596 tempreg, BFD_RELOC_MIPS_HIGHER);
6598 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6599 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6600 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6601 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6607 macro_build (&offset_expr, "lui", "t,u", tempreg,
6608 BFD_RELOC_MIPS_HIGHEST);
6609 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6610 tempreg, BFD_RELOC_MIPS_HIGHER);
6611 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6612 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6613 tempreg, BFD_RELOC_HI16_S);
6614 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6616 macro_build (NULL, "daddu", "d,v,t",
6617 tempreg, tempreg, breg);
6618 macro_build (&offset_expr, s, fmt, treg,
6619 BFD_RELOC_LO16, tempreg);
6622 if (mips_relax.sequence)
6629 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6630 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6632 relax_start (offset_expr.X_add_symbol);
6633 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6637 macro_build_lui (&offset_expr, tempreg);
6638 macro_build (&offset_expr, s, fmt, treg,
6639 BFD_RELOC_LO16, tempreg);
6640 if (mips_relax.sequence)
6645 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6646 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6648 relax_start (offset_expr.X_add_symbol);
6649 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6650 tempreg, breg, mips_gp_register);
6651 macro_build (&offset_expr, s, fmt, treg,
6652 BFD_RELOC_GPREL16, tempreg);
6655 macro_build_lui (&offset_expr, tempreg);
6656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6657 tempreg, tempreg, breg);
6658 macro_build (&offset_expr, s, fmt, treg,
6659 BFD_RELOC_LO16, tempreg);
6660 if (mips_relax.sequence)
6664 else if (!mips_big_got)
6666 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6668 /* If this is a reference to an external symbol, we want
6669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6671 <op> $treg,0($tempreg)
6673 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6675 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6676 <op> $treg,0($tempreg)
6679 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6680 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6682 If there is a base register, we add it to $tempreg before
6683 the <op>. If there is a constant, we stick it in the
6684 <op> instruction. We don't handle constants larger than
6685 16 bits, because we have no way to load the upper 16 bits
6686 (actually, we could handle them for the subset of cases
6687 in which we are not using $at). */
6688 assert (offset_expr.X_op == O_symbol);
6691 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6692 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6694 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6695 tempreg, tempreg, breg);
6696 macro_build (&offset_expr, s, fmt, treg,
6697 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6700 expr1.X_add_number = offset_expr.X_add_number;
6701 offset_expr.X_add_number = 0;
6702 if (expr1.X_add_number < -0x8000
6703 || expr1.X_add_number >= 0x8000)
6704 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6705 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6706 lw_reloc_type, mips_gp_register);
6708 relax_start (offset_expr.X_add_symbol);
6710 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6711 tempreg, BFD_RELOC_LO16);
6714 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6715 tempreg, tempreg, breg);
6716 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6718 else if (mips_big_got && !HAVE_NEWABI)
6722 /* If this is a reference to an external symbol, we want
6723 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6724 addu $tempreg,$tempreg,$gp
6725 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6726 <op> $treg,0($tempreg)
6728 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6730 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6731 <op> $treg,0($tempreg)
6732 If there is a base register, we add it to $tempreg before
6733 the <op>. If there is a constant, we stick it in the
6734 <op> instruction. We don't handle constants larger than
6735 16 bits, because we have no way to load the upper 16 bits
6736 (actually, we could handle them for the subset of cases
6737 in which we are not using $at). */
6738 assert (offset_expr.X_op == O_symbol);
6739 expr1.X_add_number = offset_expr.X_add_number;
6740 offset_expr.X_add_number = 0;
6741 if (expr1.X_add_number < -0x8000
6742 || expr1.X_add_number >= 0x8000)
6743 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6744 gpdelay = reg_needs_delay (mips_gp_register);
6745 relax_start (offset_expr.X_add_symbol);
6746 macro_build (&offset_expr, "lui", "t,u", tempreg,
6747 BFD_RELOC_MIPS_GOT_HI16);
6748 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6750 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6751 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6754 macro_build (NULL, "nop", "");
6755 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6756 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6758 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6759 tempreg, BFD_RELOC_LO16);
6763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6764 tempreg, tempreg, breg);
6765 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6767 else if (mips_big_got && HAVE_NEWABI)
6769 /* If this is a reference to an external symbol, we want
6770 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6771 add $tempreg,$tempreg,$gp
6772 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6773 <op> $treg,<ofst>($tempreg)
6774 Otherwise, for local symbols, we want:
6775 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6776 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6777 assert (offset_expr.X_op == O_symbol);
6778 expr1.X_add_number = offset_expr.X_add_number;
6779 offset_expr.X_add_number = 0;
6780 if (expr1.X_add_number < -0x8000
6781 || expr1.X_add_number >= 0x8000)
6782 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6783 relax_start (offset_expr.X_add_symbol);
6784 macro_build (&offset_expr, "lui", "t,u", tempreg,
6785 BFD_RELOC_MIPS_GOT_HI16);
6786 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6788 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6789 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6791 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6792 tempreg, tempreg, breg);
6793 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6796 offset_expr.X_add_number = expr1.X_add_number;
6797 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6798 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6800 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6801 tempreg, tempreg, breg);
6802 macro_build (&offset_expr, s, fmt, treg,
6803 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6813 load_register (treg, &imm_expr, 0);
6817 load_register (treg, &imm_expr, 1);
6821 if (imm_expr.X_op == O_constant)
6824 load_register (AT, &imm_expr, 0);
6825 macro_build (NULL, "mtc1", "t,G", AT, treg);
6830 assert (offset_expr.X_op == O_symbol
6831 && strcmp (segment_name (S_GET_SEGMENT
6832 (offset_expr.X_add_symbol)),
6834 && offset_expr.X_add_number == 0);
6835 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6836 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6841 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6842 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6843 order 32 bits of the value and the low order 32 bits are either
6844 zero or in OFFSET_EXPR. */
6845 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6847 if (HAVE_64BIT_GPRS)
6848 load_register (treg, &imm_expr, 1);
6853 if (target_big_endian)
6865 load_register (hreg, &imm_expr, 0);
6868 if (offset_expr.X_op == O_absent)
6869 move_register (lreg, 0);
6872 assert (offset_expr.X_op == O_constant);
6873 load_register (lreg, &offset_expr, 0);
6880 /* We know that sym is in the .rdata section. First we get the
6881 upper 16 bits of the address. */
6882 if (mips_pic == NO_PIC)
6884 macro_build_lui (&offset_expr, AT);
6889 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6890 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6894 /* Now we load the register(s). */
6895 if (HAVE_64BIT_GPRS)
6898 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6903 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6906 /* FIXME: How in the world do we deal with the possible
6908 offset_expr.X_add_number += 4;
6909 macro_build (&offset_expr, "lw", "t,o(b)",
6910 treg + 1, BFD_RELOC_LO16, AT);
6916 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6917 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6918 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6919 the value and the low order 32 bits are either zero or in
6921 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6924 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6925 if (HAVE_64BIT_FPRS)
6927 assert (HAVE_64BIT_GPRS);
6928 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6932 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6933 if (offset_expr.X_op == O_absent)
6934 macro_build (NULL, "mtc1", "t,G", 0, treg);
6937 assert (offset_expr.X_op == O_constant);
6938 load_register (AT, &offset_expr, 0);
6939 macro_build (NULL, "mtc1", "t,G", AT, treg);
6945 assert (offset_expr.X_op == O_symbol
6946 && offset_expr.X_add_number == 0);
6947 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6948 if (strcmp (s, ".lit8") == 0)
6950 if (mips_opts.isa != ISA_MIPS1)
6952 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6953 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6956 breg = mips_gp_register;
6957 r = BFD_RELOC_MIPS_LITERAL;
6962 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6964 if (mips_pic != NO_PIC)
6965 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6966 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6969 /* FIXME: This won't work for a 64 bit address. */
6970 macro_build_lui (&offset_expr, AT);
6973 if (mips_opts.isa != ISA_MIPS1)
6975 macro_build (&offset_expr, "ldc1", "T,o(b)",
6976 treg, BFD_RELOC_LO16, AT);
6985 /* Even on a big endian machine $fn comes before $fn+1. We have
6986 to adjust when loading from memory. */
6989 assert (mips_opts.isa == ISA_MIPS1);
6990 macro_build (&offset_expr, "lwc1", "T,o(b)",
6991 target_big_endian ? treg + 1 : treg, r, breg);
6992 /* FIXME: A possible overflow which I don't know how to deal
6994 offset_expr.X_add_number += 4;
6995 macro_build (&offset_expr, "lwc1", "T,o(b)",
6996 target_big_endian ? treg : treg + 1, r, breg);
7001 * The MIPS assembler seems to check for X_add_number not
7002 * being double aligned and generating:
7005 * addiu at,at,%lo(foo+1)
7008 * But, the resulting address is the same after relocation so why
7009 * generate the extra instruction?
7011 /* Itbl support may require additional care here. */
7013 if (mips_opts.isa != ISA_MIPS1)
7024 if (mips_opts.isa != ISA_MIPS1)
7032 /* Itbl support may require additional care here. */
7037 if (HAVE_64BIT_GPRS)
7048 if (HAVE_64BIT_GPRS)
7058 if (offset_expr.X_op != O_symbol
7059 && offset_expr.X_op != O_constant)
7061 as_bad (_("expression too complex"));
7062 offset_expr.X_op = O_constant;
7065 if (HAVE_32BIT_ADDRESSES
7066 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7070 sprintf_vma (value, offset_expr.X_add_number);
7071 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7074 /* Even on a big endian machine $fn comes before $fn+1. We have
7075 to adjust when loading from memory. We set coproc if we must
7076 load $fn+1 first. */
7077 /* Itbl support may require additional care here. */
7078 if (! target_big_endian)
7081 if (mips_pic == NO_PIC
7082 || offset_expr.X_op == O_constant)
7084 /* If this is a reference to a GP relative symbol, we want
7085 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7086 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7087 If we have a base register, we use this
7089 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7090 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7091 If this is not a GP relative symbol, we want
7092 lui $at,<sym> (BFD_RELOC_HI16_S)
7093 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7094 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7095 If there is a base register, we add it to $at after the
7096 lui instruction. If there is a constant, we always use
7098 if (offset_expr.X_op == O_symbol
7099 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7100 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7102 relax_start (offset_expr.X_add_symbol);
7105 tempreg = mips_gp_register;
7109 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7110 AT, breg, mips_gp_register);
7115 /* Itbl support may require additional care here. */
7116 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7117 BFD_RELOC_GPREL16, tempreg);
7118 offset_expr.X_add_number += 4;
7120 /* Set mips_optimize to 2 to avoid inserting an
7122 hold_mips_optimize = mips_optimize;
7124 /* Itbl support may require additional care here. */
7125 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7126 BFD_RELOC_GPREL16, tempreg);
7127 mips_optimize = hold_mips_optimize;
7131 /* We just generated two relocs. When tc_gen_reloc
7132 handles this case, it will skip the first reloc and
7133 handle the second. The second reloc already has an
7134 extra addend of 4, which we added above. We must
7135 subtract it out, and then subtract another 4 to make
7136 the first reloc come out right. The second reloc
7137 will come out right because we are going to add 4 to
7138 offset_expr when we build its instruction below.
7140 If we have a symbol, then we don't want to include
7141 the offset, because it will wind up being included
7142 when we generate the reloc. */
7144 if (offset_expr.X_op == O_constant)
7145 offset_expr.X_add_number -= 8;
7148 offset_expr.X_add_number = -4;
7149 offset_expr.X_op = O_constant;
7153 macro_build_lui (&offset_expr, AT);
7155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7156 /* Itbl support may require additional care here. */
7157 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7158 BFD_RELOC_LO16, AT);
7159 /* FIXME: How do we handle overflow here? */
7160 offset_expr.X_add_number += 4;
7161 /* Itbl support may require additional care here. */
7162 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7163 BFD_RELOC_LO16, AT);
7164 if (mips_relax.sequence)
7167 else if (!mips_big_got)
7169 /* If this is a reference to an external symbol, we want
7170 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7175 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7177 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7178 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7179 If there is a base register we add it to $at before the
7180 lwc1 instructions. If there is a constant we include it
7181 in the lwc1 instructions. */
7183 expr1.X_add_number = offset_expr.X_add_number;
7184 if (expr1.X_add_number < -0x8000
7185 || expr1.X_add_number >= 0x8000 - 4)
7186 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7187 load_got_offset (AT, &offset_expr);
7190 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7192 /* Set mips_optimize to 2 to avoid inserting an undesired
7194 hold_mips_optimize = mips_optimize;
7197 /* Itbl support may require additional care here. */
7198 relax_start (offset_expr.X_add_symbol);
7199 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7200 BFD_RELOC_LO16, AT);
7201 expr1.X_add_number += 4;
7202 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7203 BFD_RELOC_LO16, AT);
7205 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7206 BFD_RELOC_LO16, AT);
7207 offset_expr.X_add_number += 4;
7208 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7209 BFD_RELOC_LO16, AT);
7212 mips_optimize = hold_mips_optimize;
7214 else if (mips_big_got)
7218 /* If this is a reference to an external symbol, we want
7219 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7221 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7226 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7228 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7229 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7230 If there is a base register we add it to $at before the
7231 lwc1 instructions. If there is a constant we include it
7232 in the lwc1 instructions. */
7234 expr1.X_add_number = offset_expr.X_add_number;
7235 offset_expr.X_add_number = 0;
7236 if (expr1.X_add_number < -0x8000
7237 || expr1.X_add_number >= 0x8000 - 4)
7238 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7239 gpdelay = reg_needs_delay (mips_gp_register);
7240 relax_start (offset_expr.X_add_symbol);
7241 macro_build (&offset_expr, "lui", "t,u",
7242 AT, BFD_RELOC_MIPS_GOT_HI16);
7243 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7244 AT, AT, mips_gp_register);
7245 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7246 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7249 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7250 /* Itbl support may require additional care here. */
7251 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7252 BFD_RELOC_LO16, AT);
7253 expr1.X_add_number += 4;
7255 /* Set mips_optimize to 2 to avoid inserting an undesired
7257 hold_mips_optimize = mips_optimize;
7259 /* Itbl support may require additional care here. */
7260 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7261 BFD_RELOC_LO16, AT);
7262 mips_optimize = hold_mips_optimize;
7263 expr1.X_add_number -= 4;
7266 offset_expr.X_add_number = expr1.X_add_number;
7268 macro_build (NULL, "nop", "");
7269 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7270 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7273 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7274 /* Itbl support may require additional care here. */
7275 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7276 BFD_RELOC_LO16, AT);
7277 offset_expr.X_add_number += 4;
7279 /* Set mips_optimize to 2 to avoid inserting an undesired
7281 hold_mips_optimize = mips_optimize;
7283 /* Itbl support may require additional care here. */
7284 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7285 BFD_RELOC_LO16, AT);
7286 mips_optimize = hold_mips_optimize;
7300 assert (HAVE_32BIT_ADDRESSES);
7301 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7302 offset_expr.X_add_number += 4;
7303 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7306 /* New code added to support COPZ instructions.
7307 This code builds table entries out of the macros in mip_opcodes.
7308 R4000 uses interlocks to handle coproc delays.
7309 Other chips (like the R3000) require nops to be inserted for delays.
7311 FIXME: Currently, we require that the user handle delays.
7312 In order to fill delay slots for non-interlocked chips,
7313 we must have a way to specify delays based on the coprocessor.
7314 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7315 What are the side-effects of the cop instruction?
7316 What cache support might we have and what are its effects?
7317 Both coprocessor & memory require delays. how long???
7318 What registers are read/set/modified?
7320 If an itbl is provided to interpret cop instructions,
7321 this knowledge can be encoded in the itbl spec. */
7335 if (NO_ISA_COP (mips_opts.arch)
7336 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7338 as_bad (_("opcode not supported on this processor: %s"),
7339 mips_cpu_info_from_arch (mips_opts.arch)->name);
7343 /* For now we just do C (same as Cz). The parameter will be
7344 stored in insn_opcode by mips_ip. */
7345 macro_build (NULL, s, "C", ip->insn_opcode);
7349 move_register (dreg, sreg);
7352 #ifdef LOSING_COMPILER
7354 /* Try and see if this is a new itbl instruction.
7355 This code builds table entries out of the macros in mip_opcodes.
7356 FIXME: For now we just assemble the expression and pass it's
7357 value along as a 32-bit immediate.
7358 We may want to have the assembler assemble this value,
7359 so that we gain the assembler's knowledge of delay slots,
7361 Would it be more efficient to use mask (id) here? */
7362 if (itbl_have_entries
7363 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7365 s = ip->insn_mo->name;
7367 coproc = ITBL_DECODE_PNUM (immed_expr);;
7368 macro_build (&immed_expr, s, "C");
7374 if (!mips_opts.at && used_at)
7375 as_bad (_("Macro used $at after \".set noat\""));
7379 macro2 (struct mips_cl_insn *ip)
7381 unsigned int treg, sreg, dreg, breg;
7382 unsigned int tempreg;
7396 bfd_reloc_code_real_type r;
7398 treg = (ip->insn_opcode >> 16) & 0x1f;
7399 dreg = (ip->insn_opcode >> 11) & 0x1f;
7400 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7401 mask = ip->insn_mo->mask;
7403 expr1.X_op = O_constant;
7404 expr1.X_op_symbol = NULL;
7405 expr1.X_add_symbol = NULL;
7406 expr1.X_add_number = 1;
7410 #endif /* LOSING_COMPILER */
7415 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7416 macro_build (NULL, "mflo", "d", dreg);
7422 /* The MIPS assembler some times generates shifts and adds. I'm
7423 not trying to be that fancy. GCC should do this for us
7426 load_register (AT, &imm_expr, dbl);
7427 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7428 macro_build (NULL, "mflo", "d", dreg);
7444 load_register (AT, &imm_expr, dbl);
7445 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7446 macro_build (NULL, "mflo", "d", dreg);
7447 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7448 macro_build (NULL, "mfhi", "d", AT);
7450 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7453 expr1.X_add_number = 8;
7454 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7455 macro_build (NULL, "nop", "", 0);
7456 macro_build (NULL, "break", "c", 6);
7459 macro_build (NULL, "mflo", "d", dreg);
7475 load_register (AT, &imm_expr, dbl);
7476 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7477 sreg, imm ? AT : treg);
7478 macro_build (NULL, "mfhi", "d", AT);
7479 macro_build (NULL, "mflo", "d", dreg);
7481 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7484 expr1.X_add_number = 8;
7485 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7486 macro_build (NULL, "nop", "", 0);
7487 macro_build (NULL, "break", "c", 6);
7493 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7504 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7505 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7509 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7510 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7511 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7512 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7516 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7527 macro_build (NULL, "negu", "d,w", tempreg, treg);
7528 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7532 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7533 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7534 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7535 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7543 if (imm_expr.X_op != O_constant)
7544 as_bad (_("Improper rotate count"));
7545 rot = imm_expr.X_add_number & 0x3f;
7546 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7548 rot = (64 - rot) & 0x3f;
7550 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7552 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7557 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7560 l = (rot < 0x20) ? "dsll" : "dsll32";
7561 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7564 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7565 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7566 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7574 if (imm_expr.X_op != O_constant)
7575 as_bad (_("Improper rotate count"));
7576 rot = imm_expr.X_add_number & 0x1f;
7577 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7579 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7584 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7588 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7589 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7590 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7595 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7597 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7601 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7602 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7603 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7604 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7608 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7610 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7614 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7615 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7616 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7617 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7625 if (imm_expr.X_op != O_constant)
7626 as_bad (_("Improper rotate count"));
7627 rot = imm_expr.X_add_number & 0x3f;
7628 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7631 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7633 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7638 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7641 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7642 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7645 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7646 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7647 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7655 if (imm_expr.X_op != O_constant)
7656 as_bad (_("Improper rotate count"));
7657 rot = imm_expr.X_add_number & 0x1f;
7658 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7660 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7665 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7669 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7670 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7671 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7676 assert (mips_opts.isa == ISA_MIPS1);
7677 /* Even on a big endian machine $fn comes before $fn+1. We have
7678 to adjust when storing to memory. */
7679 macro_build (&offset_expr, "swc1", "T,o(b)",
7680 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7681 offset_expr.X_add_number += 4;
7682 macro_build (&offset_expr, "swc1", "T,o(b)",
7683 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7688 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7690 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7693 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7694 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7699 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7701 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7706 as_warn (_("Instruction %s: result is always false"),
7708 move_register (dreg, 0);
7711 if (CPU_HAS_SEQ (mips_opts.arch)
7712 && -512 <= imm_expr.X_add_number
7713 && imm_expr.X_add_number < 512)
7715 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7716 (int) imm_expr.X_add_number);
7719 if (imm_expr.X_op == O_constant
7720 && imm_expr.X_add_number >= 0
7721 && imm_expr.X_add_number < 0x10000)
7723 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7725 else if (imm_expr.X_op == O_constant
7726 && imm_expr.X_add_number > -0x8000
7727 && imm_expr.X_add_number < 0)
7729 imm_expr.X_add_number = -imm_expr.X_add_number;
7730 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7731 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7733 else if (CPU_HAS_SEQ (mips_opts.arch))
7736 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7737 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7742 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7743 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7746 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7749 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7755 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7756 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7759 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7761 if (imm_expr.X_op == O_constant
7762 && imm_expr.X_add_number >= -0x8000
7763 && imm_expr.X_add_number < 0x8000)
7765 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7766 dreg, sreg, BFD_RELOC_LO16);
7770 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7771 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7775 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7778 case M_SGT: /* sreg > treg <==> treg < sreg */
7784 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7787 case M_SGT_I: /* sreg > I <==> I < sreg */
7794 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7795 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7798 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7804 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7805 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7808 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7815 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7816 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7817 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7821 if (imm_expr.X_op == O_constant
7822 && imm_expr.X_add_number >= -0x8000
7823 && imm_expr.X_add_number < 0x8000)
7825 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7829 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7830 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7834 if (imm_expr.X_op == O_constant
7835 && imm_expr.X_add_number >= -0x8000
7836 && imm_expr.X_add_number < 0x8000)
7838 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7843 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7844 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7849 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7851 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7854 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7855 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7860 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7862 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7867 as_warn (_("Instruction %s: result is always true"),
7869 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7870 dreg, 0, BFD_RELOC_LO16);
7873 if (CPU_HAS_SEQ (mips_opts.arch)
7874 && -512 <= imm_expr.X_add_number
7875 && imm_expr.X_add_number < 512)
7877 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7878 (int) imm_expr.X_add_number);
7881 if (imm_expr.X_op == O_constant
7882 && imm_expr.X_add_number >= 0
7883 && imm_expr.X_add_number < 0x10000)
7885 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7887 else if (imm_expr.X_op == O_constant
7888 && imm_expr.X_add_number > -0x8000
7889 && imm_expr.X_add_number < 0)
7891 imm_expr.X_add_number = -imm_expr.X_add_number;
7892 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7893 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7895 else if (CPU_HAS_SEQ (mips_opts.arch))
7898 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7899 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7904 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7905 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7908 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7914 if (imm_expr.X_op == O_constant
7915 && imm_expr.X_add_number > -0x8000
7916 && imm_expr.X_add_number <= 0x8000)
7918 imm_expr.X_add_number = -imm_expr.X_add_number;
7919 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7920 dreg, sreg, BFD_RELOC_LO16);
7924 load_register (AT, &imm_expr, dbl);
7925 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7931 if (imm_expr.X_op == O_constant
7932 && imm_expr.X_add_number > -0x8000
7933 && imm_expr.X_add_number <= 0x8000)
7935 imm_expr.X_add_number = -imm_expr.X_add_number;
7936 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7937 dreg, sreg, BFD_RELOC_LO16);
7941 load_register (AT, &imm_expr, dbl);
7942 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7964 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7965 macro_build (NULL, s, "s,t", sreg, AT);
7970 assert (mips_opts.isa == ISA_MIPS1);
7972 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7973 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7976 * Is the double cfc1 instruction a bug in the mips assembler;
7977 * or is there a reason for it?
7980 macro_build (NULL, "cfc1", "t,G", treg, RA);
7981 macro_build (NULL, "cfc1", "t,G", treg, RA);
7982 macro_build (NULL, "nop", "");
7983 expr1.X_add_number = 3;
7984 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7985 expr1.X_add_number = 2;
7986 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7987 macro_build (NULL, "ctc1", "t,G", AT, RA);
7988 macro_build (NULL, "nop", "");
7989 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7991 macro_build (NULL, "ctc1", "t,G", treg, RA);
7992 macro_build (NULL, "nop", "");
8003 if (offset_expr.X_add_number >= 0x7fff)
8004 as_bad (_("operand overflow"));
8005 if (! target_big_endian)
8006 ++offset_expr.X_add_number;
8007 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8008 if (! target_big_endian)
8009 --offset_expr.X_add_number;
8011 ++offset_expr.X_add_number;
8012 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8013 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8014 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8027 if (offset_expr.X_add_number >= 0x8000 - off)
8028 as_bad (_("operand overflow"));
8036 if (! target_big_endian)
8037 offset_expr.X_add_number += off;
8038 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8039 if (! target_big_endian)
8040 offset_expr.X_add_number -= off;
8042 offset_expr.X_add_number += off;
8043 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8045 /* If necessary, move the result in tempreg the final destination. */
8046 if (treg == tempreg)
8048 /* Protect second load's delay slot. */
8050 move_register (treg, tempreg);
8064 load_address (AT, &offset_expr, &used_at);
8066 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8067 if (! target_big_endian)
8068 expr1.X_add_number = off;
8070 expr1.X_add_number = 0;
8071 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8072 if (! target_big_endian)
8073 expr1.X_add_number = 0;
8075 expr1.X_add_number = off;
8076 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8082 load_address (AT, &offset_expr, &used_at);
8084 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8085 if (target_big_endian)
8086 expr1.X_add_number = 0;
8087 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8088 treg, BFD_RELOC_LO16, AT);
8089 if (target_big_endian)
8090 expr1.X_add_number = 1;
8092 expr1.X_add_number = 0;
8093 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8094 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8095 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8100 if (offset_expr.X_add_number >= 0x7fff)
8101 as_bad (_("operand overflow"));
8102 if (target_big_endian)
8103 ++offset_expr.X_add_number;
8104 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8105 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8106 if (target_big_endian)
8107 --offset_expr.X_add_number;
8109 ++offset_expr.X_add_number;
8110 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8123 if (offset_expr.X_add_number >= 0x8000 - off)
8124 as_bad (_("operand overflow"));
8125 if (! target_big_endian)
8126 offset_expr.X_add_number += off;
8127 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8128 if (! target_big_endian)
8129 offset_expr.X_add_number -= off;
8131 offset_expr.X_add_number += off;
8132 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8146 load_address (AT, &offset_expr, &used_at);
8148 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8149 if (! target_big_endian)
8150 expr1.X_add_number = off;
8152 expr1.X_add_number = 0;
8153 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8154 if (! target_big_endian)
8155 expr1.X_add_number = 0;
8157 expr1.X_add_number = off;
8158 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8163 load_address (AT, &offset_expr, &used_at);
8165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8166 if (! target_big_endian)
8167 expr1.X_add_number = 0;
8168 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8169 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8170 if (! target_big_endian)
8171 expr1.X_add_number = 1;
8173 expr1.X_add_number = 0;
8174 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8175 if (! target_big_endian)
8176 expr1.X_add_number = 0;
8178 expr1.X_add_number = 1;
8179 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8180 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8181 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8185 /* FIXME: Check if this is one of the itbl macros, since they
8186 are added dynamically. */
8187 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8190 if (!mips_opts.at && used_at)
8191 as_bad (_("Macro used $at after \".set noat\""));
8194 /* Implement macros in mips16 mode. */
8197 mips16_macro (struct mips_cl_insn *ip)
8200 int xreg, yreg, zreg, tmp;
8203 const char *s, *s2, *s3;
8205 mask = ip->insn_mo->mask;
8207 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8208 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8209 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8211 expr1.X_op = O_constant;
8212 expr1.X_op_symbol = NULL;
8213 expr1.X_add_symbol = NULL;
8214 expr1.X_add_number = 1;
8234 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8235 expr1.X_add_number = 2;
8236 macro_build (&expr1, "bnez", "x,p", yreg);
8237 macro_build (NULL, "break", "6", 7);
8239 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8240 since that causes an overflow. We should do that as well,
8241 but I don't see how to do the comparisons without a temporary
8244 macro_build (NULL, s, "x", zreg);
8264 macro_build (NULL, s, "0,x,y", xreg, yreg);
8265 expr1.X_add_number = 2;
8266 macro_build (&expr1, "bnez", "x,p", yreg);
8267 macro_build (NULL, "break", "6", 7);
8269 macro_build (NULL, s2, "x", zreg);
8275 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8276 macro_build (NULL, "mflo", "x", zreg);
8284 if (imm_expr.X_op != O_constant)
8285 as_bad (_("Unsupported large constant"));
8286 imm_expr.X_add_number = -imm_expr.X_add_number;
8287 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8291 if (imm_expr.X_op != O_constant)
8292 as_bad (_("Unsupported large constant"));
8293 imm_expr.X_add_number = -imm_expr.X_add_number;
8294 macro_build (&imm_expr, "addiu", "x,k", xreg);
8298 if (imm_expr.X_op != O_constant)
8299 as_bad (_("Unsupported large constant"));
8300 imm_expr.X_add_number = -imm_expr.X_add_number;
8301 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8323 goto do_reverse_branch;
8327 goto do_reverse_branch;
8339 goto do_reverse_branch;
8350 macro_build (NULL, s, "x,y", xreg, yreg);
8351 macro_build (&offset_expr, s2, "p");
8378 goto do_addone_branch_i;
8383 goto do_addone_branch_i;
8398 goto do_addone_branch_i;
8405 if (imm_expr.X_op != O_constant)
8406 as_bad (_("Unsupported large constant"));
8407 ++imm_expr.X_add_number;
8410 macro_build (&imm_expr, s, s3, xreg);
8411 macro_build (&offset_expr, s2, "p");
8415 expr1.X_add_number = 0;
8416 macro_build (&expr1, "slti", "x,8", yreg);
8418 move_register (xreg, yreg);
8419 expr1.X_add_number = 2;
8420 macro_build (&expr1, "bteqz", "p");
8421 macro_build (NULL, "neg", "x,w", xreg, xreg);
8425 /* For consistency checking, verify that all bits are specified either
8426 by the match/mask part of the instruction definition, or by the
8429 validate_mips_insn (const struct mips_opcode *opc)
8431 const char *p = opc->args;
8433 unsigned long used_bits = opc->mask;
8435 if ((used_bits & opc->match) != opc->match)
8437 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8438 opc->name, opc->args);
8441 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8451 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8452 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8453 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8454 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8455 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8456 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8457 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8458 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8459 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8460 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8461 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8462 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8463 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8465 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8466 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8467 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8468 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8469 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8470 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8471 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8472 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8473 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8474 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8477 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8478 c, opc->name, opc->args);
8482 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8483 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8485 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8486 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8487 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8488 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8490 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8491 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8493 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8494 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8496 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8497 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8498 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8499 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8500 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8501 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8502 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8503 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8504 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8505 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8506 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8507 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8508 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8509 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8510 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8511 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8512 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8514 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8515 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8516 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8517 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8519 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8520 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8521 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8522 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8523 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8524 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8525 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8526 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8527 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8530 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8531 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8532 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8533 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8534 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8537 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8538 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8539 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8540 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8541 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8542 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8543 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8544 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8545 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8546 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8547 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8548 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8549 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8550 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8551 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8552 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8553 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8554 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8556 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8557 c, opc->name, opc->args);
8561 if (used_bits != 0xffffffff)
8563 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8564 ~used_bits & 0xffffffff, opc->name, opc->args);
8570 /* UDI immediates. */
8578 static const struct mips_immed mips_immed[] = {
8579 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8580 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8581 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8582 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8586 /* Check whether an odd floating-point register is allowed. */
8588 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8590 const char *s = insn->name;
8592 if (insn->pinfo == INSN_MACRO)
8593 /* Let a macro pass, we'll catch it later when it is expanded. */
8596 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8598 /* Allow odd registers for single-precision ops. */
8599 switch (insn->pinfo & (FP_S | FP_D))
8603 return 1; /* both single precision - ok */
8605 return 0; /* both double precision - fail */
8610 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8611 s = strchr (insn->name, '.');
8613 s = s != NULL ? strchr (s + 1, '.') : NULL;
8614 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8617 /* Single-precision coprocessor loads and moves are OK too. */
8618 if ((insn->pinfo & FP_S)
8619 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8620 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8626 /* This routine assembles an instruction into its binary format. As a
8627 side effect, it sets one of the global variables imm_reloc or
8628 offset_reloc to the type of relocation to do if one of the operands
8629 is an address expression. */
8632 mips_ip (char *str, struct mips_cl_insn *ip)
8637 struct mips_opcode *insn;
8640 unsigned int lastregno = 0;
8641 unsigned int lastpos = 0;
8642 unsigned int limlo, limhi;
8645 offsetT min_range, max_range;
8651 /* If the instruction contains a '.', we first try to match an instruction
8652 including the '.'. Then we try again without the '.'. */
8654 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8657 /* If we stopped on whitespace, then replace the whitespace with null for
8658 the call to hash_find. Save the character we replaced just in case we
8659 have to re-parse the instruction. */
8666 insn = (struct mips_opcode *) hash_find (op_hash, str);
8668 /* If we didn't find the instruction in the opcode table, try again, but
8669 this time with just the instruction up to, but not including the
8673 /* Restore the character we overwrite above (if any). */
8677 /* Scan up to the first '.' or whitespace. */
8679 *s != '\0' && *s != '.' && !ISSPACE (*s);
8683 /* If we did not find a '.', then we can quit now. */
8686 insn_error = "unrecognized opcode";
8690 /* Lookup the instruction in the hash table. */
8692 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8694 insn_error = "unrecognized opcode";
8704 assert (strcmp (insn->name, str) == 0);
8706 ok = is_opcode_valid (insn, FALSE);
8709 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8710 && strcmp (insn->name, insn[1].name) == 0)
8719 static char buf[100];
8721 _("opcode not supported on this processor: %s (%s)"),
8722 mips_cpu_info_from_arch (mips_opts.arch)->name,
8723 mips_cpu_info_from_isa (mips_opts.isa)->name);
8732 create_insn (ip, insn);
8735 lastregno = 0xffffffff;
8736 for (args = insn->args;; ++args)
8740 s += strspn (s, " \t");
8744 case '\0': /* end of args */
8749 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8750 my_getExpression (&imm_expr, s);
8751 check_absolute_expr (ip, &imm_expr);
8752 if ((unsigned long) imm_expr.X_add_number != 1
8753 && (unsigned long) imm_expr.X_add_number != 3)
8755 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8756 (unsigned long) imm_expr.X_add_number);
8758 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8759 imm_expr.X_op = O_absent;
8763 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8764 my_getExpression (&imm_expr, s);
8765 check_absolute_expr (ip, &imm_expr);
8766 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8768 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8769 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8771 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8772 imm_expr.X_op = O_absent;
8776 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8777 my_getExpression (&imm_expr, s);
8778 check_absolute_expr (ip, &imm_expr);
8779 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8781 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8782 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8784 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8785 imm_expr.X_op = O_absent;
8789 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8790 my_getExpression (&imm_expr, s);
8791 check_absolute_expr (ip, &imm_expr);
8792 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8794 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8795 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8797 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8798 imm_expr.X_op = O_absent;
8802 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8803 my_getExpression (&imm_expr, s);
8804 check_absolute_expr (ip, &imm_expr);
8805 if (imm_expr.X_add_number & ~OP_MASK_RS)
8807 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8808 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8810 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8811 imm_expr.X_op = O_absent;
8815 case '7': /* four dsp accumulators in bits 11,12 */
8816 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8817 s[3] >= '0' && s[3] <= '3')
8821 INSERT_OPERAND (DSPACC, *ip, regno);
8825 as_bad (_("Invalid dsp acc register"));
8828 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8829 my_getExpression (&imm_expr, s);
8830 check_absolute_expr (ip, &imm_expr);
8831 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8833 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8835 (unsigned long) imm_expr.X_add_number);
8837 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8838 imm_expr.X_op = O_absent;
8842 case '9': /* four dsp accumulators in bits 21,22 */
8843 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8844 s[3] >= '0' && s[3] <= '3')
8848 INSERT_OPERAND (DSPACC_S, *ip, regno);
8852 as_bad (_("Invalid dsp acc register"));
8855 case '0': /* dsp 6-bit signed immediate in bit 20 */
8856 my_getExpression (&imm_expr, s);
8857 check_absolute_expr (ip, &imm_expr);
8858 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8859 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8860 if (imm_expr.X_add_number < min_range ||
8861 imm_expr.X_add_number > max_range)
8863 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8864 (long) min_range, (long) max_range,
8865 (long) imm_expr.X_add_number);
8867 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8868 imm_expr.X_op = O_absent;
8872 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8873 my_getExpression (&imm_expr, s);
8874 check_absolute_expr (ip, &imm_expr);
8875 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8877 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8879 (unsigned long) imm_expr.X_add_number);
8881 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8882 imm_expr.X_op = O_absent;
8886 case ':': /* dsp 7-bit signed immediate in bit 19 */
8887 my_getExpression (&imm_expr, s);
8888 check_absolute_expr (ip, &imm_expr);
8889 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8890 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8891 if (imm_expr.X_add_number < min_range ||
8892 imm_expr.X_add_number > max_range)
8894 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8895 (long) min_range, (long) max_range,
8896 (long) imm_expr.X_add_number);
8898 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8899 imm_expr.X_op = O_absent;
8903 case '@': /* dsp 10-bit signed immediate in bit 16 */
8904 my_getExpression (&imm_expr, s);
8905 check_absolute_expr (ip, &imm_expr);
8906 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8907 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8908 if (imm_expr.X_add_number < min_range ||
8909 imm_expr.X_add_number > max_range)
8911 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8912 (long) min_range, (long) max_range,
8913 (long) imm_expr.X_add_number);
8915 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8916 imm_expr.X_op = O_absent;
8920 case '!': /* MT usermode flag bit. */
8921 my_getExpression (&imm_expr, s);
8922 check_absolute_expr (ip, &imm_expr);
8923 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8924 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8925 (unsigned long) imm_expr.X_add_number);
8926 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8927 imm_expr.X_op = O_absent;
8931 case '$': /* MT load high flag bit. */
8932 my_getExpression (&imm_expr, s);
8933 check_absolute_expr (ip, &imm_expr);
8934 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8935 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8936 (unsigned long) imm_expr.X_add_number);
8937 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8938 imm_expr.X_op = O_absent;
8942 case '*': /* four dsp accumulators in bits 18,19 */
8943 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8944 s[3] >= '0' && s[3] <= '3')
8948 INSERT_OPERAND (MTACC_T, *ip, regno);
8952 as_bad (_("Invalid dsp/smartmips acc register"));
8955 case '&': /* four dsp accumulators in bits 13,14 */
8956 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8957 s[3] >= '0' && s[3] <= '3')
8961 INSERT_OPERAND (MTACC_D, *ip, regno);
8965 as_bad (_("Invalid dsp/smartmips acc register"));
8977 INSERT_OPERAND (RS, *ip, lastregno);
8981 INSERT_OPERAND (RT, *ip, lastregno);
8985 INSERT_OPERAND (FT, *ip, lastregno);
8989 INSERT_OPERAND (FS, *ip, lastregno);
8995 /* Handle optional base register.
8996 Either the base register is omitted or
8997 we must have a left paren. */
8998 /* This is dependent on the next operand specifier
8999 is a base register specification. */
9000 assert (args[1] == 'b' || args[1] == '5'
9001 || args[1] == '-' || args[1] == '4');
9005 case ')': /* these must match exactly */
9012 case '+': /* Opcode extension character. */
9015 case '1': /* UDI immediates. */
9020 const struct mips_immed *imm = mips_immed;
9022 while (imm->type && imm->type != *args)
9026 my_getExpression (&imm_expr, s);
9027 check_absolute_expr (ip, &imm_expr);
9028 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9030 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9031 imm->desc ? imm->desc : ip->insn_mo->name,
9032 (unsigned long) imm_expr.X_add_number,
9033 (unsigned long) imm_expr.X_add_number);
9034 imm_expr.X_add_number &= imm->mask;
9036 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9038 imm_expr.X_op = O_absent;
9043 case 'A': /* ins/ext position, becomes LSB. */
9052 my_getExpression (&imm_expr, s);
9053 check_absolute_expr (ip, &imm_expr);
9054 if ((unsigned long) imm_expr.X_add_number < limlo
9055 || (unsigned long) imm_expr.X_add_number > limhi)
9057 as_bad (_("Improper position (%lu)"),
9058 (unsigned long) imm_expr.X_add_number);
9059 imm_expr.X_add_number = limlo;
9061 lastpos = imm_expr.X_add_number;
9062 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9063 imm_expr.X_op = O_absent;
9067 case 'B': /* ins size, becomes MSB. */
9076 my_getExpression (&imm_expr, s);
9077 check_absolute_expr (ip, &imm_expr);
9078 /* Check for negative input so that small negative numbers
9079 will not succeed incorrectly. The checks against
9080 (pos+size) transitively check "size" itself,
9081 assuming that "pos" is reasonable. */
9082 if ((long) imm_expr.X_add_number < 0
9083 || ((unsigned long) imm_expr.X_add_number
9085 || ((unsigned long) imm_expr.X_add_number
9088 as_bad (_("Improper insert size (%lu, position %lu)"),
9089 (unsigned long) imm_expr.X_add_number,
9090 (unsigned long) lastpos);
9091 imm_expr.X_add_number = limlo - lastpos;
9093 INSERT_OPERAND (INSMSB, *ip,
9094 lastpos + imm_expr.X_add_number - 1);
9095 imm_expr.X_op = O_absent;
9099 case 'C': /* ext size, becomes MSBD. */
9112 my_getExpression (&imm_expr, s);
9113 check_absolute_expr (ip, &imm_expr);
9114 /* Check for negative input so that small negative numbers
9115 will not succeed incorrectly. The checks against
9116 (pos+size) transitively check "size" itself,
9117 assuming that "pos" is reasonable. */
9118 if ((long) imm_expr.X_add_number < 0
9119 || ((unsigned long) imm_expr.X_add_number
9121 || ((unsigned long) imm_expr.X_add_number
9124 as_bad (_("Improper extract size (%lu, position %lu)"),
9125 (unsigned long) imm_expr.X_add_number,
9126 (unsigned long) lastpos);
9127 imm_expr.X_add_number = limlo - lastpos;
9129 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9130 imm_expr.X_op = O_absent;
9135 /* +D is for disassembly only; never match. */
9139 /* "+I" is like "I", except that imm2_expr is used. */
9140 my_getExpression (&imm2_expr, s);
9141 if (imm2_expr.X_op != O_big
9142 && imm2_expr.X_op != O_constant)
9143 insn_error = _("absolute expression required");
9144 if (HAVE_32BIT_GPRS)
9145 normalize_constant_expr (&imm2_expr);
9149 case 'T': /* Coprocessor register. */
9150 /* +T is for disassembly only; never match. */
9153 case 't': /* Coprocessor register number. */
9154 if (s[0] == '$' && ISDIGIT (s[1]))
9164 while (ISDIGIT (*s));
9166 as_bad (_("Invalid register number (%d)"), regno);
9169 INSERT_OPERAND (RT, *ip, regno);
9174 as_bad (_("Invalid coprocessor 0 register number"));
9178 /* bbit[01] and bbit[01]32 bit index. Give error if index
9179 is not in the valid range. */
9180 my_getExpression (&imm_expr, s);
9181 check_absolute_expr (ip, &imm_expr);
9182 if ((unsigned) imm_expr.X_add_number > 31)
9184 as_bad (_("Improper bit index (%lu)"),
9185 (unsigned long) imm_expr.X_add_number);
9186 imm_expr.X_add_number = 0;
9188 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9189 imm_expr.X_op = O_absent;
9194 /* bbit[01] bit index when bbit is used but we generate
9195 bbit[01]32 because the index is over 32. Move to the
9196 next candidate if index is not in the valid range. */
9197 my_getExpression (&imm_expr, s);
9198 check_absolute_expr (ip, &imm_expr);
9199 if ((unsigned) imm_expr.X_add_number < 32
9200 || (unsigned) imm_expr.X_add_number > 63)
9202 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9203 imm_expr.X_op = O_absent;
9208 /* cins, cins32, exts and exts32 position field. Give error
9209 if it's not in the valid range. */
9210 my_getExpression (&imm_expr, s);
9211 check_absolute_expr (ip, &imm_expr);
9212 if ((unsigned) imm_expr.X_add_number > 31)
9214 as_bad (_("Improper position (%lu)"),
9215 (unsigned long) imm_expr.X_add_number);
9216 imm_expr.X_add_number = 0;
9218 /* Make the pos explicit to simplify +S. */
9219 lastpos = imm_expr.X_add_number + 32;
9220 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9221 imm_expr.X_op = O_absent;
9226 /* cins, cins32, exts and exts32 position field. Move to
9227 the next candidate if it's not in the valid range. */
9228 my_getExpression (&imm_expr, s);
9229 check_absolute_expr (ip, &imm_expr);
9230 if ((unsigned) imm_expr.X_add_number < 32
9231 || (unsigned) imm_expr.X_add_number > 63)
9233 lastpos = imm_expr.X_add_number;
9234 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9235 imm_expr.X_op = O_absent;
9240 /* cins and exts length-minus-one field. */
9241 my_getExpression (&imm_expr, s);
9242 check_absolute_expr (ip, &imm_expr);
9243 if ((unsigned long) imm_expr.X_add_number > 31)
9245 as_bad (_("Improper size (%lu)"),
9246 (unsigned long) imm_expr.X_add_number);
9247 imm_expr.X_add_number = 0;
9249 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9250 imm_expr.X_op = O_absent;
9255 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9256 length-minus-one field. */
9257 my_getExpression (&imm_expr, s);
9258 check_absolute_expr (ip, &imm_expr);
9259 if ((long) imm_expr.X_add_number < 0
9260 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9262 as_bad (_("Improper size (%lu)"),
9263 (unsigned long) imm_expr.X_add_number);
9264 imm_expr.X_add_number = 0;
9266 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9267 imm_expr.X_op = O_absent;
9272 /* seqi/snei immediate field. */
9273 my_getExpression (&imm_expr, s);
9274 check_absolute_expr (ip, &imm_expr);
9275 if ((long) imm_expr.X_add_number < -512
9276 || (long) imm_expr.X_add_number >= 512)
9278 as_bad (_("Improper immediate (%ld)"),
9279 (long) imm_expr.X_add_number);
9280 imm_expr.X_add_number = 0;
9282 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9283 imm_expr.X_op = O_absent;
9288 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9289 *args, insn->name, insn->args);
9290 /* Further processing is fruitless. */
9295 case '<': /* must be at least one digit */
9297 * According to the manual, if the shift amount is greater
9298 * than 31 or less than 0, then the shift amount should be
9299 * mod 32. In reality the mips assembler issues an error.
9300 * We issue a warning and mask out all but the low 5 bits.
9302 my_getExpression (&imm_expr, s);
9303 check_absolute_expr (ip, &imm_expr);
9304 if ((unsigned long) imm_expr.X_add_number > 31)
9305 as_warn (_("Improper shift amount (%lu)"),
9306 (unsigned long) imm_expr.X_add_number);
9307 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9308 imm_expr.X_op = O_absent;
9312 case '>': /* shift amount minus 32 */
9313 my_getExpression (&imm_expr, s);
9314 check_absolute_expr (ip, &imm_expr);
9315 if ((unsigned long) imm_expr.X_add_number < 32
9316 || (unsigned long) imm_expr.X_add_number > 63)
9318 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9319 imm_expr.X_op = O_absent;
9323 case 'k': /* cache code */
9324 case 'h': /* prefx code */
9325 case '1': /* sync type */
9326 my_getExpression (&imm_expr, s);
9327 check_absolute_expr (ip, &imm_expr);
9328 if ((unsigned long) imm_expr.X_add_number > 31)
9329 as_warn (_("Invalid value for `%s' (%lu)"),
9331 (unsigned long) imm_expr.X_add_number);
9333 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9334 else if (*args == 'h')
9335 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9337 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9338 imm_expr.X_op = O_absent;
9342 case 'c': /* break code */
9343 my_getExpression (&imm_expr, s);
9344 check_absolute_expr (ip, &imm_expr);
9345 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9346 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9348 (unsigned long) imm_expr.X_add_number);
9349 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9350 imm_expr.X_op = O_absent;
9354 case 'q': /* lower break code */
9355 my_getExpression (&imm_expr, s);
9356 check_absolute_expr (ip, &imm_expr);
9357 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9358 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9360 (unsigned long) imm_expr.X_add_number);
9361 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9362 imm_expr.X_op = O_absent;
9366 case 'B': /* 20-bit syscall/break code. */
9367 my_getExpression (&imm_expr, s);
9368 check_absolute_expr (ip, &imm_expr);
9369 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9370 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9372 (unsigned long) imm_expr.X_add_number);
9373 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9374 imm_expr.X_op = O_absent;
9378 case 'C': /* Coprocessor code */
9379 my_getExpression (&imm_expr, s);
9380 check_absolute_expr (ip, &imm_expr);
9381 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9383 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9384 (unsigned long) imm_expr.X_add_number);
9385 imm_expr.X_add_number &= OP_MASK_COPZ;
9387 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9388 imm_expr.X_op = O_absent;
9392 case 'J': /* 19-bit wait code. */
9393 my_getExpression (&imm_expr, s);
9394 check_absolute_expr (ip, &imm_expr);
9395 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9397 as_warn (_("Illegal 19-bit code (%lu)"),
9398 (unsigned long) imm_expr.X_add_number);
9399 imm_expr.X_add_number &= OP_MASK_CODE19;
9401 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9402 imm_expr.X_op = O_absent;
9406 case 'P': /* Performance register. */
9407 my_getExpression (&imm_expr, s);
9408 check_absolute_expr (ip, &imm_expr);
9409 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9410 as_warn (_("Invalid performance register (%lu)"),
9411 (unsigned long) imm_expr.X_add_number);
9412 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9413 imm_expr.X_op = O_absent;
9417 case 'G': /* Coprocessor destination register. */
9418 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9419 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9421 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9422 INSERT_OPERAND (RD, *ip, regno);
9431 case 'b': /* base register */
9432 case 'd': /* destination register */
9433 case 's': /* source register */
9434 case 't': /* target register */
9435 case 'r': /* both target and source */
9436 case 'v': /* both dest and source */
9437 case 'w': /* both dest and target */
9438 case 'E': /* coprocessor target register */
9439 case 'K': /* 'rdhwr' destination register */
9440 case 'x': /* ignore register name */
9441 case 'z': /* must be zero register */
9442 case 'U': /* destination register (clo/clz). */
9443 case 'g': /* coprocessor destination register */
9445 if (*args == 'E' || *args == 'K')
9446 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9449 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9450 if (regno == AT && mips_opts.at)
9452 if (mips_opts.at == ATREG)
9453 as_warn (_("used $at without \".set noat\""));
9455 as_warn (_("used $%u with \".set at=$%u\""),
9456 regno, mips_opts.at);
9466 if (c == 'r' || c == 'v' || c == 'w')
9473 /* 'z' only matches $0. */
9474 if (c == 'z' && regno != 0)
9477 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9479 if (regno == lastregno)
9481 insn_error = _("source and destination must be different");
9484 if (regno == 31 && lastregno == 0xffffffff)
9486 insn_error = _("a destination register must be supplied");
9490 /* Now that we have assembled one operand, we use the args string
9491 * to figure out where it goes in the instruction. */
9498 INSERT_OPERAND (RS, *ip, regno);
9504 INSERT_OPERAND (RD, *ip, regno);
9507 INSERT_OPERAND (RD, *ip, regno);
9508 INSERT_OPERAND (RT, *ip, regno);
9513 INSERT_OPERAND (RT, *ip, regno);
9516 /* This case exists because on the r3000 trunc
9517 expands into a macro which requires a gp
9518 register. On the r6000 or r4000 it is
9519 assembled into a single instruction which
9520 ignores the register. Thus the insn version
9521 is MIPS_ISA2 and uses 'x', and the macro
9522 version is MIPS_ISA1 and uses 't'. */
9525 /* This case is for the div instruction, which
9526 acts differently if the destination argument
9527 is $0. This only matches $0, and is checked
9528 outside the switch. */
9531 /* Itbl operand; not yet implemented. FIXME ?? */
9533 /* What about all other operands like 'i', which
9534 can be specified in the opcode table? */
9543 INSERT_OPERAND (RS, *ip, lastregno);
9546 INSERT_OPERAND (RT, *ip, lastregno);
9551 case 'O': /* MDMX alignment immediate constant. */
9552 my_getExpression (&imm_expr, s);
9553 check_absolute_expr (ip, &imm_expr);
9554 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9555 as_warn ("Improper align amount (%ld), using low bits",
9556 (long) imm_expr.X_add_number);
9557 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9558 imm_expr.X_op = O_absent;
9562 case 'Q': /* MDMX vector, element sel, or const. */
9565 /* MDMX Immediate. */
9566 my_getExpression (&imm_expr, s);
9567 check_absolute_expr (ip, &imm_expr);
9568 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9569 as_warn (_("Invalid MDMX Immediate (%ld)"),
9570 (long) imm_expr.X_add_number);
9571 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9572 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9573 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9575 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9576 imm_expr.X_op = O_absent;
9580 /* Not MDMX Immediate. Fall through. */
9581 case 'X': /* MDMX destination register. */
9582 case 'Y': /* MDMX source register. */
9583 case 'Z': /* MDMX target register. */
9585 case 'D': /* floating point destination register */
9586 case 'S': /* floating point source register */
9587 case 'T': /* floating point target register */
9588 case 'R': /* floating point source register */
9593 || (mips_opts.ase_mdmx
9594 && (ip->insn_mo->pinfo & FP_D)
9595 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9596 | INSN_COPROC_MEMORY_DELAY
9597 | INSN_LOAD_COPROC_DELAY
9598 | INSN_LOAD_MEMORY_DELAY
9599 | INSN_STORE_MEMORY))))
9602 if (reg_lookup (&s, rtype, ®no))
9604 if ((regno & 1) != 0
9606 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9607 as_warn (_("Float register should be even, was %d"),
9615 if (c == 'V' || c == 'W')
9626 INSERT_OPERAND (FD, *ip, regno);
9631 INSERT_OPERAND (FS, *ip, regno);
9634 /* This is like 'Z', but also needs to fix the MDMX
9635 vector/scalar select bits. Note that the
9636 scalar immediate case is handled above. */
9639 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9640 int max_el = (is_qh ? 3 : 7);
9642 my_getExpression(&imm_expr, s);
9643 check_absolute_expr (ip, &imm_expr);
9645 if (imm_expr.X_add_number > max_el)
9646 as_bad(_("Bad element selector %ld"),
9647 (long) imm_expr.X_add_number);
9648 imm_expr.X_add_number &= max_el;
9649 ip->insn_opcode |= (imm_expr.X_add_number
9652 imm_expr.X_op = O_absent;
9654 as_warn(_("Expecting ']' found '%s'"), s);
9660 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9661 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9664 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9671 INSERT_OPERAND (FT, *ip, regno);
9674 INSERT_OPERAND (FR, *ip, regno);
9684 INSERT_OPERAND (FS, *ip, lastregno);
9687 INSERT_OPERAND (FT, *ip, lastregno);
9693 my_getExpression (&imm_expr, s);
9694 if (imm_expr.X_op != O_big
9695 && imm_expr.X_op != O_constant)
9696 insn_error = _("absolute expression required");
9697 if (HAVE_32BIT_GPRS)
9698 normalize_constant_expr (&imm_expr);
9703 my_getExpression (&offset_expr, s);
9704 normalize_address_expr (&offset_expr);
9705 *imm_reloc = BFD_RELOC_32;
9718 unsigned char temp[8];
9720 unsigned int length;
9725 /* These only appear as the last operand in an
9726 instruction, and every instruction that accepts
9727 them in any variant accepts them in all variants.
9728 This means we don't have to worry about backing out
9729 any changes if the instruction does not match.
9731 The difference between them is the size of the
9732 floating point constant and where it goes. For 'F'
9733 and 'L' the constant is 64 bits; for 'f' and 'l' it
9734 is 32 bits. Where the constant is placed is based
9735 on how the MIPS assembler does things:
9738 f -- immediate value
9741 The .lit4 and .lit8 sections are only used if
9742 permitted by the -G argument.
9744 The code below needs to know whether the target register
9745 is 32 or 64 bits wide. It relies on the fact 'f' and
9746 'F' are used with GPR-based instructions and 'l' and
9747 'L' are used with FPR-based instructions. */
9749 f64 = *args == 'F' || *args == 'L';
9750 using_gprs = *args == 'F' || *args == 'f';
9752 save_in = input_line_pointer;
9753 input_line_pointer = s;
9754 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9756 s = input_line_pointer;
9757 input_line_pointer = save_in;
9758 if (err != NULL && *err != '\0')
9760 as_bad (_("Bad floating point constant: %s"), err);
9761 memset (temp, '\0', sizeof temp);
9762 length = f64 ? 8 : 4;
9765 assert (length == (unsigned) (f64 ? 8 : 4));
9769 && (g_switch_value < 4
9770 || (temp[0] == 0 && temp[1] == 0)
9771 || (temp[2] == 0 && temp[3] == 0))))
9773 imm_expr.X_op = O_constant;
9774 if (! target_big_endian)
9775 imm_expr.X_add_number = bfd_getl32 (temp);
9777 imm_expr.X_add_number = bfd_getb32 (temp);
9780 && ! mips_disable_float_construction
9781 /* Constants can only be constructed in GPRs and
9782 copied to FPRs if the GPRs are at least as wide
9783 as the FPRs. Force the constant into memory if
9784 we are using 64-bit FPRs but the GPRs are only
9787 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9788 && ((temp[0] == 0 && temp[1] == 0)
9789 || (temp[2] == 0 && temp[3] == 0))
9790 && ((temp[4] == 0 && temp[5] == 0)
9791 || (temp[6] == 0 && temp[7] == 0)))
9793 /* The value is simple enough to load with a couple of
9794 instructions. If using 32-bit registers, set
9795 imm_expr to the high order 32 bits and offset_expr to
9796 the low order 32 bits. Otherwise, set imm_expr to
9797 the entire 64 bit constant. */
9798 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9800 imm_expr.X_op = O_constant;
9801 offset_expr.X_op = O_constant;
9802 if (! target_big_endian)
9804 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9805 offset_expr.X_add_number = bfd_getl32 (temp);
9809 imm_expr.X_add_number = bfd_getb32 (temp);
9810 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9812 if (offset_expr.X_add_number == 0)
9813 offset_expr.X_op = O_absent;
9815 else if (sizeof (imm_expr.X_add_number) > 4)
9817 imm_expr.X_op = O_constant;
9818 if (! target_big_endian)
9819 imm_expr.X_add_number = bfd_getl64 (temp);
9821 imm_expr.X_add_number = bfd_getb64 (temp);
9825 imm_expr.X_op = O_big;
9826 imm_expr.X_add_number = 4;
9827 if (! target_big_endian)
9829 generic_bignum[0] = bfd_getl16 (temp);
9830 generic_bignum[1] = bfd_getl16 (temp + 2);
9831 generic_bignum[2] = bfd_getl16 (temp + 4);
9832 generic_bignum[3] = bfd_getl16 (temp + 6);
9836 generic_bignum[0] = bfd_getb16 (temp + 6);
9837 generic_bignum[1] = bfd_getb16 (temp + 4);
9838 generic_bignum[2] = bfd_getb16 (temp + 2);
9839 generic_bignum[3] = bfd_getb16 (temp);
9845 const char *newname;
9848 /* Switch to the right section. */
9850 subseg = now_subseg;
9853 default: /* unused default case avoids warnings. */
9855 newname = RDATA_SECTION_NAME;
9856 if (g_switch_value >= 8)
9860 newname = RDATA_SECTION_NAME;
9863 assert (g_switch_value >= 4);
9867 new_seg = subseg_new (newname, (subsegT) 0);
9869 bfd_set_section_flags (stdoutput, new_seg,
9874 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9875 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9876 record_alignment (new_seg, 4);
9878 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9880 as_bad (_("Can't use floating point insn in this section"));
9882 /* Set the argument to the current address in the
9884 offset_expr.X_op = O_symbol;
9885 offset_expr.X_add_symbol =
9886 symbol_new ("L0\001", now_seg,
9887 (valueT) frag_now_fix (), frag_now);
9888 offset_expr.X_add_number = 0;
9890 /* Put the floating point number into the section. */
9891 p = frag_more ((int) length);
9892 memcpy (p, temp, length);
9894 /* Switch back to the original section. */
9895 subseg_set (seg, subseg);
9900 case 'i': /* 16 bit unsigned immediate */
9901 case 'j': /* 16 bit signed immediate */
9902 *imm_reloc = BFD_RELOC_LO16;
9903 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9906 offsetT minval, maxval;
9908 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9909 && strcmp (insn->name, insn[1].name) == 0);
9911 /* If the expression was written as an unsigned number,
9912 only treat it as signed if there are no more
9916 && sizeof (imm_expr.X_add_number) <= 4
9917 && imm_expr.X_op == O_constant
9918 && imm_expr.X_add_number < 0
9919 && imm_expr.X_unsigned
9923 /* For compatibility with older assemblers, we accept
9924 0x8000-0xffff as signed 16-bit numbers when only
9925 signed numbers are allowed. */
9927 minval = 0, maxval = 0xffff;
9929 minval = -0x8000, maxval = 0x7fff;
9931 minval = -0x8000, maxval = 0xffff;
9933 if (imm_expr.X_op != O_constant
9934 || imm_expr.X_add_number < minval
9935 || imm_expr.X_add_number > maxval)
9939 if (imm_expr.X_op == O_constant
9940 || imm_expr.X_op == O_big)
9941 as_bad (_("expression out of range"));
9947 case 'o': /* 16 bit offset */
9948 /* Check whether there is only a single bracketed expression
9949 left. If so, it must be the base register and the
9950 constant must be zero. */
9951 if (*s == '(' && strchr (s + 1, '(') == 0)
9953 offset_expr.X_op = O_constant;
9954 offset_expr.X_add_number = 0;
9958 /* If this value won't fit into a 16 bit offset, then go
9959 find a macro that will generate the 32 bit offset
9961 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9962 && (offset_expr.X_op != O_constant
9963 || offset_expr.X_add_number >= 0x8000
9964 || offset_expr.X_add_number < -0x8000))
9970 case 'p': /* pc relative offset */
9971 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9972 my_getExpression (&offset_expr, s);
9976 case 'u': /* upper 16 bits */
9977 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9978 && imm_expr.X_op == O_constant
9979 && (imm_expr.X_add_number < 0
9980 || imm_expr.X_add_number >= 0x10000))
9981 as_bad (_("lui expression not in range 0..65535"));
9985 case 'a': /* 26 bit address */
9986 my_getExpression (&offset_expr, s);
9988 *offset_reloc = BFD_RELOC_MIPS_JMP;
9991 case 'N': /* 3 bit branch condition code */
9992 case 'M': /* 3 bit compare condition code */
9994 if (ip->insn_mo->pinfo & (FP_D| FP_S))
9996 if (!reg_lookup (&s, rtype, ®no))
9998 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9999 || strcmp(str + strlen(str) - 5, "any2f") == 0
10000 || strcmp(str + strlen(str) - 5, "any2t") == 0)
10001 && (regno & 1) != 0)
10002 as_warn(_("Condition code register should be even for %s, was %d"),
10004 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
10005 || strcmp(str + strlen(str) - 5, "any4t") == 0)
10006 && (regno & 3) != 0)
10007 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
10010 INSERT_OPERAND (BCC, *ip, regno);
10012 INSERT_OPERAND (CCC, *ip, regno);
10016 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10027 while (ISDIGIT (*s));
10030 c = 8; /* Invalid sel value. */
10033 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10034 ip->insn_opcode |= c;
10038 /* Must be at least one digit. */
10039 my_getExpression (&imm_expr, s);
10040 check_absolute_expr (ip, &imm_expr);
10042 if ((unsigned long) imm_expr.X_add_number
10043 > (unsigned long) OP_MASK_VECBYTE)
10045 as_bad (_("bad byte vector index (%ld)"),
10046 (long) imm_expr.X_add_number);
10047 imm_expr.X_add_number = 0;
10050 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10051 imm_expr.X_op = O_absent;
10056 my_getExpression (&imm_expr, s);
10057 check_absolute_expr (ip, &imm_expr);
10059 if ((unsigned long) imm_expr.X_add_number
10060 > (unsigned long) OP_MASK_VECALIGN)
10062 as_bad (_("bad byte vector index (%ld)"),
10063 (long) imm_expr.X_add_number);
10064 imm_expr.X_add_number = 0;
10067 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10068 imm_expr.X_op = O_absent;
10073 as_bad (_("bad char = '%c'\n"), *args);
10078 /* Args don't match. */
10079 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10080 !strcmp (insn->name, insn[1].name))
10084 insn_error = _("illegal operands");
10088 *(--argsStart) = save_c;
10089 insn_error = _("illegal operands");
10094 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10096 /* This routine assembles an instruction into its binary format when
10097 assembling for the mips16. As a side effect, it sets one of the
10098 global variables imm_reloc or offset_reloc to the type of
10099 relocation to do if one of the operands is an address expression.
10100 It also sets mips16_small and mips16_ext if the user explicitly
10101 requested a small or extended instruction. */
10104 mips16_ip (char *str, struct mips_cl_insn *ip)
10108 struct mips_opcode *insn;
10110 unsigned int regno;
10111 unsigned int lastregno = 0;
10117 mips16_small = FALSE;
10118 mips16_ext = FALSE;
10120 for (s = str; ISLOWER (*s); ++s)
10132 if (s[1] == 't' && s[2] == ' ')
10135 mips16_small = TRUE;
10139 else if (s[1] == 'e' && s[2] == ' ')
10146 /* Fall through. */
10148 insn_error = _("unknown opcode");
10152 if (mips_opts.noautoextend && ! mips16_ext)
10153 mips16_small = TRUE;
10155 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10157 insn_error = _("unrecognized opcode");
10166 assert (strcmp (insn->name, str) == 0);
10168 ok = is_opcode_valid_16 (insn);
10171 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10172 && strcmp (insn->name, insn[1].name) == 0)
10181 static char buf[100];
10183 _("opcode not supported on this processor: %s (%s)"),
10184 mips_cpu_info_from_arch (mips_opts.arch)->name,
10185 mips_cpu_info_from_isa (mips_opts.isa)->name);
10192 create_insn (ip, insn);
10193 imm_expr.X_op = O_absent;
10194 imm_reloc[0] = BFD_RELOC_UNUSED;
10195 imm_reloc[1] = BFD_RELOC_UNUSED;
10196 imm_reloc[2] = BFD_RELOC_UNUSED;
10197 imm2_expr.X_op = O_absent;
10198 offset_expr.X_op = O_absent;
10199 offset_reloc[0] = BFD_RELOC_UNUSED;
10200 offset_reloc[1] = BFD_RELOC_UNUSED;
10201 offset_reloc[2] = BFD_RELOC_UNUSED;
10202 for (args = insn->args; 1; ++args)
10209 /* In this switch statement we call break if we did not find
10210 a match, continue if we did find a match, or return if we
10219 /* Stuff the immediate value in now, if we can. */
10220 if (imm_expr.X_op == O_constant
10221 && *imm_reloc > BFD_RELOC_UNUSED
10222 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10223 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10224 && insn->pinfo != INSN_MACRO)
10228 switch (*offset_reloc)
10230 case BFD_RELOC_MIPS16_HI16_S:
10231 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10234 case BFD_RELOC_MIPS16_HI16:
10235 tmp = imm_expr.X_add_number >> 16;
10238 case BFD_RELOC_MIPS16_LO16:
10239 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10243 case BFD_RELOC_UNUSED:
10244 tmp = imm_expr.X_add_number;
10250 *offset_reloc = BFD_RELOC_UNUSED;
10252 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10253 tmp, TRUE, mips16_small,
10254 mips16_ext, &ip->insn_opcode,
10255 &ip->use_extend, &ip->extend);
10256 imm_expr.X_op = O_absent;
10257 *imm_reloc = BFD_RELOC_UNUSED;
10271 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10274 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10290 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10292 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10296 /* Fall through. */
10307 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10309 if (c == 'v' || c == 'w')
10312 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10314 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10325 if (c == 'v' || c == 'w')
10327 regno = mips16_to_32_reg_map[lastregno];
10341 regno = mips32_to_16_reg_map[regno];
10346 regno = ILLEGAL_REG;
10351 regno = ILLEGAL_REG;
10356 regno = ILLEGAL_REG;
10361 if (regno == AT && mips_opts.at)
10363 if (mips_opts.at == ATREG)
10364 as_warn (_("used $at without \".set noat\""));
10366 as_warn (_("used $%u with \".set at=$%u\""),
10367 regno, mips_opts.at);
10375 if (regno == ILLEGAL_REG)
10382 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10386 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10389 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10392 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10398 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10401 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10402 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10412 if (strncmp (s, "$pc", 3) == 0)
10429 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10432 if (imm_expr.X_op != O_constant)
10435 ip->use_extend = TRUE;
10440 /* We need to relax this instruction. */
10441 *offset_reloc = *imm_reloc;
10442 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10447 *imm_reloc = BFD_RELOC_UNUSED;
10448 /* Fall through. */
10455 my_getExpression (&imm_expr, s);
10456 if (imm_expr.X_op == O_register)
10458 /* What we thought was an expression turned out to
10461 if (s[0] == '(' && args[1] == '(')
10463 /* It looks like the expression was omitted
10464 before a register indirection, which means
10465 that the expression is implicitly zero. We
10466 still set up imm_expr, so that we handle
10467 explicit extensions correctly. */
10468 imm_expr.X_op = O_constant;
10469 imm_expr.X_add_number = 0;
10470 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10477 /* We need to relax this instruction. */
10478 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10487 /* We use offset_reloc rather than imm_reloc for the PC
10488 relative operands. This lets macros with both
10489 immediate and address operands work correctly. */
10490 my_getExpression (&offset_expr, s);
10492 if (offset_expr.X_op == O_register)
10495 /* We need to relax this instruction. */
10496 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10500 case '6': /* break code */
10501 my_getExpression (&imm_expr, s);
10502 check_absolute_expr (ip, &imm_expr);
10503 if ((unsigned long) imm_expr.X_add_number > 63)
10504 as_warn (_("Invalid value for `%s' (%lu)"),
10506 (unsigned long) imm_expr.X_add_number);
10507 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10508 imm_expr.X_op = O_absent;
10512 case 'a': /* 26 bit address */
10513 my_getExpression (&offset_expr, s);
10515 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10516 ip->insn_opcode <<= 16;
10519 case 'l': /* register list for entry macro */
10520 case 'L': /* register list for exit macro */
10530 unsigned int freg, reg1, reg2;
10532 while (*s == ' ' || *s == ',')
10534 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10536 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10540 as_bad (_("can't parse register list"));
10550 if (!reg_lookup (&s, freg ? RTYPE_FPU
10551 : (RTYPE_GP | RTYPE_NUM), ®2))
10553 as_bad (_("invalid register list"));
10557 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10559 mask &= ~ (7 << 3);
10562 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10564 mask &= ~ (7 << 3);
10567 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10568 mask |= (reg2 - 3) << 3;
10569 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10570 mask |= (reg2 - 15) << 1;
10571 else if (reg1 == RA && reg2 == RA)
10575 as_bad (_("invalid register list"));
10579 /* The mask is filled in in the opcode table for the
10580 benefit of the disassembler. We remove it before
10581 applying the actual mask. */
10582 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10583 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10587 case 'm': /* Register list for save insn. */
10588 case 'M': /* Register list for restore insn. */
10591 int framesz = 0, seen_framesz = 0;
10592 int args = 0, statics = 0, sregs = 0;
10596 unsigned int reg1, reg2;
10598 SKIP_SPACE_TABS (s);
10601 SKIP_SPACE_TABS (s);
10603 my_getExpression (&imm_expr, s);
10604 if (imm_expr.X_op == O_constant)
10606 /* Handle the frame size. */
10609 as_bad (_("more than one frame size in list"));
10613 framesz = imm_expr.X_add_number;
10614 imm_expr.X_op = O_absent;
10619 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10621 as_bad (_("can't parse register list"));
10633 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10636 as_bad (_("can't parse register list"));
10641 while (reg1 <= reg2)
10643 if (reg1 >= 4 && reg1 <= 7)
10647 args |= 1 << (reg1 - 4);
10649 /* statics $a0-$a3 */
10650 statics |= 1 << (reg1 - 4);
10652 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10655 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10657 else if (reg1 == 31)
10659 /* Add $ra to insn. */
10664 as_bad (_("unexpected register in list"));
10672 /* Encode args/statics combination. */
10673 if (args & statics)
10674 as_bad (_("arg/static registers overlap"));
10675 else if (args == 0xf)
10676 /* All $a0-$a3 are args. */
10677 opcode |= MIPS16_ALL_ARGS << 16;
10678 else if (statics == 0xf)
10679 /* All $a0-$a3 are statics. */
10680 opcode |= MIPS16_ALL_STATICS << 16;
10683 int narg = 0, nstat = 0;
10685 /* Count arg registers. */
10692 as_bad (_("invalid arg register list"));
10694 /* Count static registers. */
10695 while (statics & 0x8)
10697 statics = (statics << 1) & 0xf;
10701 as_bad (_("invalid static register list"));
10703 /* Encode args/statics. */
10704 opcode |= ((narg << 2) | nstat) << 16;
10707 /* Encode $s0/$s1. */
10708 if (sregs & (1 << 0)) /* $s0 */
10710 if (sregs & (1 << 1)) /* $s1 */
10716 /* Count regs $s2-$s8. */
10724 as_bad (_("invalid static register list"));
10725 /* Encode $s2-$s8. */
10726 opcode |= nsreg << 24;
10729 /* Encode frame size. */
10731 as_bad (_("missing frame size"));
10732 else if ((framesz & 7) != 0 || framesz < 0
10733 || framesz > 0xff * 8)
10734 as_bad (_("invalid frame size"));
10735 else if (framesz != 128 || (opcode >> 16) != 0)
10738 opcode |= (((framesz & 0xf0) << 16)
10739 | (framesz & 0x0f));
10742 /* Finally build the instruction. */
10743 if ((opcode >> 16) != 0 || framesz == 0)
10745 ip->use_extend = TRUE;
10746 ip->extend = opcode >> 16;
10748 ip->insn_opcode |= opcode & 0x7f;
10752 case 'e': /* extend code */
10753 my_getExpression (&imm_expr, s);
10754 check_absolute_expr (ip, &imm_expr);
10755 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10757 as_warn (_("Invalid value for `%s' (%lu)"),
10759 (unsigned long) imm_expr.X_add_number);
10760 imm_expr.X_add_number &= 0x7ff;
10762 ip->insn_opcode |= imm_expr.X_add_number;
10763 imm_expr.X_op = O_absent;
10773 /* Args don't match. */
10774 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10775 strcmp (insn->name, insn[1].name) == 0)
10782 insn_error = _("illegal operands");
10788 /* This structure holds information we know about a mips16 immediate
10791 struct mips16_immed_operand
10793 /* The type code used in the argument string in the opcode table. */
10795 /* The number of bits in the short form of the opcode. */
10797 /* The number of bits in the extended form of the opcode. */
10799 /* The amount by which the short form is shifted when it is used;
10800 for example, the sw instruction has a shift count of 2. */
10802 /* The amount by which the short form is shifted when it is stored
10803 into the instruction code. */
10805 /* Non-zero if the short form is unsigned. */
10807 /* Non-zero if the extended form is unsigned. */
10809 /* Non-zero if the value is PC relative. */
10813 /* The mips16 immediate operand types. */
10815 static const struct mips16_immed_operand mips16_immed_operands[] =
10817 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10818 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10819 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10820 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10821 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10822 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10823 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10824 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10825 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10826 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10827 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10828 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10829 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10830 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10831 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10832 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10833 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10834 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10835 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10836 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10837 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10840 #define MIPS16_NUM_IMMED \
10841 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10843 /* Handle a mips16 instruction with an immediate value. This or's the
10844 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10845 whether an extended value is needed; if one is needed, it sets
10846 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10847 If SMALL is true, an unextended opcode was explicitly requested.
10848 If EXT is true, an extended opcode was explicitly requested. If
10849 WARN is true, warn if EXT does not match reality. */
10852 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10853 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10854 unsigned long *insn, bfd_boolean *use_extend,
10855 unsigned short *extend)
10857 const struct mips16_immed_operand *op;
10858 int mintiny, maxtiny;
10859 bfd_boolean needext;
10861 op = mips16_immed_operands;
10862 while (op->type != type)
10865 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10870 if (type == '<' || type == '>' || type == '[' || type == ']')
10873 maxtiny = 1 << op->nbits;
10878 maxtiny = (1 << op->nbits) - 1;
10883 mintiny = - (1 << (op->nbits - 1));
10884 maxtiny = (1 << (op->nbits - 1)) - 1;
10887 /* Branch offsets have an implicit 0 in the lowest bit. */
10888 if (type == 'p' || type == 'q')
10891 if ((val & ((1 << op->shift) - 1)) != 0
10892 || val < (mintiny << op->shift)
10893 || val > (maxtiny << op->shift))
10898 if (warn && ext && ! needext)
10899 as_warn_where (file, line,
10900 _("extended operand requested but not required"));
10901 if (small && needext)
10902 as_bad_where (file, line, _("invalid unextended operand value"));
10904 if (small || (! ext && ! needext))
10908 *use_extend = FALSE;
10909 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10910 insnval <<= op->op_shift;
10915 long minext, maxext;
10921 maxext = (1 << op->extbits) - 1;
10925 minext = - (1 << (op->extbits - 1));
10926 maxext = (1 << (op->extbits - 1)) - 1;
10928 if (val < minext || val > maxext)
10929 as_bad_where (file, line,
10930 _("operand value out of range for instruction"));
10932 *use_extend = TRUE;
10933 if (op->extbits == 16)
10935 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
10938 else if (op->extbits == 15)
10940 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
10945 extval = ((val & 0x1f) << 6) | (val & 0x20);
10949 *extend = (unsigned short) extval;
10954 struct percent_op_match
10957 bfd_reloc_code_real_type reloc;
10960 static const struct percent_op_match mips_percent_op[] =
10962 {"%lo", BFD_RELOC_LO16},
10964 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10965 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10966 {"%call16", BFD_RELOC_MIPS_CALL16},
10967 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10968 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
10969 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
10970 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10971 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10972 {"%got", BFD_RELOC_MIPS_GOT16},
10973 {"%gp_rel", BFD_RELOC_GPREL16},
10974 {"%half", BFD_RELOC_16},
10975 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10976 {"%higher", BFD_RELOC_MIPS_HIGHER},
10977 {"%neg", BFD_RELOC_MIPS_SUB},
10978 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
10979 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
10980 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
10981 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
10982 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
10983 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
10984 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
10986 {"%hi", BFD_RELOC_HI16_S}
10989 static const struct percent_op_match mips16_percent_op[] =
10991 {"%lo", BFD_RELOC_MIPS16_LO16},
10992 {"%gprel", BFD_RELOC_MIPS16_GPREL},
10993 {"%got", BFD_RELOC_MIPS16_GOT16},
10994 {"%call16", BFD_RELOC_MIPS16_CALL16},
10995 {"%hi", BFD_RELOC_MIPS16_HI16_S}
10999 /* Return true if *STR points to a relocation operator. When returning true,
11000 move *STR over the operator and store its relocation code in *RELOC.
11001 Leave both *STR and *RELOC alone when returning false. */
11004 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11006 const struct percent_op_match *percent_op;
11009 if (mips_opts.mips16)
11011 percent_op = mips16_percent_op;
11012 limit = ARRAY_SIZE (mips16_percent_op);
11016 percent_op = mips_percent_op;
11017 limit = ARRAY_SIZE (mips_percent_op);
11020 for (i = 0; i < limit; i++)
11021 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11023 int len = strlen (percent_op[i].str);
11025 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11028 *str += strlen (percent_op[i].str);
11029 *reloc = percent_op[i].reloc;
11031 /* Check whether the output BFD supports this relocation.
11032 If not, issue an error and fall back on something safe. */
11033 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11035 as_bad ("relocation %s isn't supported by the current ABI",
11036 percent_op[i].str);
11037 *reloc = BFD_RELOC_UNUSED;
11045 /* Parse string STR as a 16-bit relocatable operand. Store the
11046 expression in *EP and the relocations in the array starting
11047 at RELOC. Return the number of relocation operators used.
11049 On exit, EXPR_END points to the first character after the expression. */
11052 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11055 bfd_reloc_code_real_type reversed_reloc[3];
11056 size_t reloc_index, i;
11057 int crux_depth, str_depth;
11060 /* Search for the start of the main expression, recoding relocations
11061 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11062 of the main expression and with CRUX_DEPTH containing the number
11063 of open brackets at that point. */
11070 crux_depth = str_depth;
11072 /* Skip over whitespace and brackets, keeping count of the number
11074 while (*str == ' ' || *str == '\t' || *str == '(')
11079 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11080 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11082 my_getExpression (ep, crux);
11085 /* Match every open bracket. */
11086 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11090 if (crux_depth > 0)
11091 as_bad ("unclosed '('");
11095 if (reloc_index != 0)
11097 prev_reloc_op_frag = frag_now;
11098 for (i = 0; i < reloc_index; i++)
11099 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11102 return reloc_index;
11106 my_getExpression (expressionS *ep, char *str)
11111 save_in = input_line_pointer;
11112 input_line_pointer = str;
11114 expr_end = input_line_pointer;
11115 input_line_pointer = save_in;
11117 /* If we are in mips16 mode, and this is an expression based on `.',
11118 then we bump the value of the symbol by 1 since that is how other
11119 text symbols are handled. We don't bother to handle complex
11120 expressions, just `.' plus or minus a constant. */
11121 if (mips_opts.mips16
11122 && ep->X_op == O_symbol
11123 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11124 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11125 && symbol_get_frag (ep->X_add_symbol) == frag_now
11126 && symbol_constant_p (ep->X_add_symbol)
11127 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11128 S_SET_VALUE (ep->X_add_symbol, val + 1);
11132 md_atof (int type, char *litP, int *sizeP)
11134 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11138 md_number_to_chars (char *buf, valueT val, int n)
11140 if (target_big_endian)
11141 number_to_chars_bigendian (buf, val, n);
11143 number_to_chars_littleendian (buf, val, n);
11147 static int support_64bit_objects(void)
11149 const char **list, **l;
11152 list = bfd_target_list ();
11153 for (l = list; *l != NULL; l++)
11155 /* This is traditional mips */
11156 if (strcmp (*l, "elf64-tradbigmips") == 0
11157 || strcmp (*l, "elf64-tradlittlemips") == 0)
11159 if (strcmp (*l, "elf64-bigmips") == 0
11160 || strcmp (*l, "elf64-littlemips") == 0)
11163 yes = (*l != NULL);
11167 #endif /* OBJ_ELF */
11169 const char *md_shortopts = "O::g::G:";
11173 OPTION_MARCH = OPTION_MD_BASE,
11195 OPTION_NO_SMARTMIPS,
11198 OPTION_COMPAT_ARCH_BASE,
11207 OPTION_M7000_HILO_FIX,
11208 OPTION_MNO_7000_HILO_FIX,
11212 OPTION_NO_FIX_VR4120,
11214 OPTION_NO_FIX_VR4130,
11221 OPTION_CONSTRUCT_FLOATS,
11222 OPTION_NO_CONSTRUCT_FLOATS,
11225 OPTION_RELAX_BRANCH,
11226 OPTION_NO_RELAX_BRANCH,
11233 OPTION_SINGLE_FLOAT,
11234 OPTION_DOUBLE_FLOAT,
11237 OPTION_CALL_SHARED,
11238 OPTION_CALL_NONPIC,
11248 OPTION_MVXWORKS_PIC,
11249 #endif /* OBJ_ELF */
11253 struct option md_longopts[] =
11255 /* Options which specify architecture. */
11256 {"march", required_argument, NULL, OPTION_MARCH},
11257 {"mtune", required_argument, NULL, OPTION_MTUNE},
11258 {"mips0", no_argument, NULL, OPTION_MIPS1},
11259 {"mips1", no_argument, NULL, OPTION_MIPS1},
11260 {"mips2", no_argument, NULL, OPTION_MIPS2},
11261 {"mips3", no_argument, NULL, OPTION_MIPS3},
11262 {"mips4", no_argument, NULL, OPTION_MIPS4},
11263 {"mips5", no_argument, NULL, OPTION_MIPS5},
11264 {"mips32", no_argument, NULL, OPTION_MIPS32},
11265 {"mips64", no_argument, NULL, OPTION_MIPS64},
11266 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11267 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11269 /* Options which specify Application Specific Extensions (ASEs). */
11270 {"mips16", no_argument, NULL, OPTION_MIPS16},
11271 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11272 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11273 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11274 {"mdmx", no_argument, NULL, OPTION_MDMX},
11275 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11276 {"mdsp", no_argument, NULL, OPTION_DSP},
11277 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11278 {"mmt", no_argument, NULL, OPTION_MT},
11279 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11280 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11281 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11282 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11283 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11285 /* Old-style architecture options. Don't add more of these. */
11286 {"m4650", no_argument, NULL, OPTION_M4650},
11287 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11288 {"m4010", no_argument, NULL, OPTION_M4010},
11289 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11290 {"m4100", no_argument, NULL, OPTION_M4100},
11291 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11292 {"m3900", no_argument, NULL, OPTION_M3900},
11293 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11295 /* Options which enable bug fixes. */
11296 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11297 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11298 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11299 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11300 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11301 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11302 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11303 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11304 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11306 /* Miscellaneous options. */
11307 {"trap", no_argument, NULL, OPTION_TRAP},
11308 {"no-break", no_argument, NULL, OPTION_TRAP},
11309 {"break", no_argument, NULL, OPTION_BREAK},
11310 {"no-trap", no_argument, NULL, OPTION_BREAK},
11311 {"EB", no_argument, NULL, OPTION_EB},
11312 {"EL", no_argument, NULL, OPTION_EL},
11313 {"mfp32", no_argument, NULL, OPTION_FP32},
11314 {"mgp32", no_argument, NULL, OPTION_GP32},
11315 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11316 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11317 {"mfp64", no_argument, NULL, OPTION_FP64},
11318 {"mgp64", no_argument, NULL, OPTION_GP64},
11319 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11320 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11321 {"mshared", no_argument, NULL, OPTION_MSHARED},
11322 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11323 {"msym32", no_argument, NULL, OPTION_MSYM32},
11324 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11325 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11326 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11327 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11328 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11330 /* Strictly speaking this next option is ELF specific,
11331 but we allow it for other ports as well in order to
11332 make testing easier. */
11333 {"32", no_argument, NULL, OPTION_32},
11335 /* ELF-specific options. */
11337 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11338 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11339 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11340 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11341 {"xgot", no_argument, NULL, OPTION_XGOT},
11342 {"mabi", required_argument, NULL, OPTION_MABI},
11343 {"n32", no_argument, NULL, OPTION_N32},
11344 {"64", no_argument, NULL, OPTION_64},
11345 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11346 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11347 {"mpdr", no_argument, NULL, OPTION_PDR},
11348 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11349 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11350 #endif /* OBJ_ELF */
11352 {NULL, no_argument, NULL, 0}
11354 size_t md_longopts_size = sizeof (md_longopts);
11356 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11357 NEW_VALUE. Warn if another value was already specified. Note:
11358 we have to defer parsing the -march and -mtune arguments in order
11359 to handle 'from-abi' correctly, since the ABI might be specified
11360 in a later argument. */
11363 mips_set_option_string (const char **string_ptr, const char *new_value)
11365 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11366 as_warn (_("A different %s was already specified, is now %s"),
11367 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11370 *string_ptr = new_value;
11374 md_parse_option (int c, char *arg)
11378 case OPTION_CONSTRUCT_FLOATS:
11379 mips_disable_float_construction = 0;
11382 case OPTION_NO_CONSTRUCT_FLOATS:
11383 mips_disable_float_construction = 1;
11395 target_big_endian = 1;
11399 target_big_endian = 0;
11405 else if (arg[0] == '0')
11407 else if (arg[0] == '1')
11417 mips_debug = atoi (arg);
11421 file_mips_isa = ISA_MIPS1;
11425 file_mips_isa = ISA_MIPS2;
11429 file_mips_isa = ISA_MIPS3;
11433 file_mips_isa = ISA_MIPS4;
11437 file_mips_isa = ISA_MIPS5;
11440 case OPTION_MIPS32:
11441 file_mips_isa = ISA_MIPS32;
11444 case OPTION_MIPS32R2:
11445 file_mips_isa = ISA_MIPS32R2;
11448 case OPTION_MIPS64R2:
11449 file_mips_isa = ISA_MIPS64R2;
11452 case OPTION_MIPS64:
11453 file_mips_isa = ISA_MIPS64;
11457 mips_set_option_string (&mips_tune_string, arg);
11461 mips_set_option_string (&mips_arch_string, arg);
11465 mips_set_option_string (&mips_arch_string, "4650");
11466 mips_set_option_string (&mips_tune_string, "4650");
11469 case OPTION_NO_M4650:
11473 mips_set_option_string (&mips_arch_string, "4010");
11474 mips_set_option_string (&mips_tune_string, "4010");
11477 case OPTION_NO_M4010:
11481 mips_set_option_string (&mips_arch_string, "4100");
11482 mips_set_option_string (&mips_tune_string, "4100");
11485 case OPTION_NO_M4100:
11489 mips_set_option_string (&mips_arch_string, "3900");
11490 mips_set_option_string (&mips_tune_string, "3900");
11493 case OPTION_NO_M3900:
11497 mips_opts.ase_mdmx = 1;
11500 case OPTION_NO_MDMX:
11501 mips_opts.ase_mdmx = 0;
11505 mips_opts.ase_dsp = 1;
11506 mips_opts.ase_dspr2 = 0;
11509 case OPTION_NO_DSP:
11510 mips_opts.ase_dsp = 0;
11511 mips_opts.ase_dspr2 = 0;
11515 mips_opts.ase_dspr2 = 1;
11516 mips_opts.ase_dsp = 1;
11519 case OPTION_NO_DSPR2:
11520 mips_opts.ase_dspr2 = 0;
11521 mips_opts.ase_dsp = 0;
11525 mips_opts.ase_mt = 1;
11529 mips_opts.ase_mt = 0;
11532 case OPTION_MIPS16:
11533 mips_opts.mips16 = 1;
11534 mips_no_prev_insn ();
11537 case OPTION_NO_MIPS16:
11538 mips_opts.mips16 = 0;
11539 mips_no_prev_insn ();
11542 case OPTION_MIPS3D:
11543 mips_opts.ase_mips3d = 1;
11546 case OPTION_NO_MIPS3D:
11547 mips_opts.ase_mips3d = 0;
11550 case OPTION_SMARTMIPS:
11551 mips_opts.ase_smartmips = 1;
11554 case OPTION_NO_SMARTMIPS:
11555 mips_opts.ase_smartmips = 0;
11558 case OPTION_FIX_24K:
11562 case OPTION_NO_FIX_24K:
11566 case OPTION_FIX_VR4120:
11567 mips_fix_vr4120 = 1;
11570 case OPTION_NO_FIX_VR4120:
11571 mips_fix_vr4120 = 0;
11574 case OPTION_FIX_VR4130:
11575 mips_fix_vr4130 = 1;
11578 case OPTION_NO_FIX_VR4130:
11579 mips_fix_vr4130 = 0;
11582 case OPTION_RELAX_BRANCH:
11583 mips_relax_branch = 1;
11586 case OPTION_NO_RELAX_BRANCH:
11587 mips_relax_branch = 0;
11590 case OPTION_MSHARED:
11591 mips_in_shared = TRUE;
11594 case OPTION_MNO_SHARED:
11595 mips_in_shared = FALSE;
11598 case OPTION_MSYM32:
11599 mips_opts.sym32 = TRUE;
11602 case OPTION_MNO_SYM32:
11603 mips_opts.sym32 = FALSE;
11607 /* When generating ELF code, we permit -KPIC and -call_shared to
11608 select SVR4_PIC, and -non_shared to select no PIC. This is
11609 intended to be compatible with Irix 5. */
11610 case OPTION_CALL_SHARED:
11613 as_bad (_("-call_shared is supported only for ELF format"));
11616 mips_pic = SVR4_PIC;
11617 mips_abicalls = TRUE;
11620 case OPTION_CALL_NONPIC:
11623 as_bad (_("-call_nonpic is supported only for ELF format"));
11627 mips_abicalls = TRUE;
11630 case OPTION_NON_SHARED:
11633 as_bad (_("-non_shared is supported only for ELF format"));
11637 mips_abicalls = FALSE;
11640 /* The -xgot option tells the assembler to use 32 bit offsets
11641 when accessing the got in SVR4_PIC mode. It is for Irix
11646 #endif /* OBJ_ELF */
11649 g_switch_value = atoi (arg);
11653 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11657 mips_abi = O32_ABI;
11658 /* We silently ignore -32 for non-ELF targets. This greatly
11659 simplifies the construction of the MIPS GAS test cases. */
11666 as_bad (_("-n32 is supported for ELF format only"));
11669 mips_abi = N32_ABI;
11675 as_bad (_("-64 is supported for ELF format only"));
11678 mips_abi = N64_ABI;
11679 if (!support_64bit_objects())
11680 as_fatal (_("No compiled in support for 64 bit object file format"));
11682 #endif /* OBJ_ELF */
11685 file_mips_gp32 = 1;
11689 file_mips_gp32 = 0;
11693 file_mips_fp32 = 1;
11697 file_mips_fp32 = 0;
11700 case OPTION_SINGLE_FLOAT:
11701 file_mips_single_float = 1;
11704 case OPTION_DOUBLE_FLOAT:
11705 file_mips_single_float = 0;
11708 case OPTION_SOFT_FLOAT:
11709 file_mips_soft_float = 1;
11712 case OPTION_HARD_FLOAT:
11713 file_mips_soft_float = 0;
11720 as_bad (_("-mabi is supported for ELF format only"));
11723 if (strcmp (arg, "32") == 0)
11724 mips_abi = O32_ABI;
11725 else if (strcmp (arg, "o64") == 0)
11726 mips_abi = O64_ABI;
11727 else if (strcmp (arg, "n32") == 0)
11728 mips_abi = N32_ABI;
11729 else if (strcmp (arg, "64") == 0)
11731 mips_abi = N64_ABI;
11732 if (! support_64bit_objects())
11733 as_fatal (_("No compiled in support for 64 bit object file "
11736 else if (strcmp (arg, "eabi") == 0)
11737 mips_abi = EABI_ABI;
11740 as_fatal (_("invalid abi -mabi=%s"), arg);
11744 #endif /* OBJ_ELF */
11746 case OPTION_M7000_HILO_FIX:
11747 mips_7000_hilo_fix = TRUE;
11750 case OPTION_MNO_7000_HILO_FIX:
11751 mips_7000_hilo_fix = FALSE;
11755 case OPTION_MDEBUG:
11756 mips_flag_mdebug = TRUE;
11759 case OPTION_NO_MDEBUG:
11760 mips_flag_mdebug = FALSE;
11764 mips_flag_pdr = TRUE;
11767 case OPTION_NO_PDR:
11768 mips_flag_pdr = FALSE;
11771 case OPTION_MVXWORKS_PIC:
11772 mips_pic = VXWORKS_PIC;
11774 #endif /* OBJ_ELF */
11783 /* Set up globals to generate code for the ISA or processor
11784 described by INFO. */
11787 mips_set_architecture (const struct mips_cpu_info *info)
11791 file_mips_arch = info->cpu;
11792 mips_opts.arch = info->cpu;
11793 mips_opts.isa = info->isa;
11798 /* Likewise for tuning. */
11801 mips_set_tune (const struct mips_cpu_info *info)
11804 mips_tune = info->cpu;
11809 mips_after_parse_args (void)
11811 const struct mips_cpu_info *arch_info = 0;
11812 const struct mips_cpu_info *tune_info = 0;
11814 /* GP relative stuff not working for PE */
11815 if (strncmp (TARGET_OS, "pe", 2) == 0)
11817 if (g_switch_seen && g_switch_value != 0)
11818 as_bad (_("-G not supported in this configuration."));
11819 g_switch_value = 0;
11822 if (mips_abi == NO_ABI)
11823 mips_abi = MIPS_DEFAULT_ABI;
11825 /* The following code determines the architecture and register size.
11826 Similar code was added to GCC 3.3 (see override_options() in
11827 config/mips/mips.c). The GAS and GCC code should be kept in sync
11828 as much as possible. */
11830 if (mips_arch_string != 0)
11831 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11833 if (file_mips_isa != ISA_UNKNOWN)
11835 /* Handle -mipsN. At this point, file_mips_isa contains the
11836 ISA level specified by -mipsN, while arch_info->isa contains
11837 the -march selection (if any). */
11838 if (arch_info != 0)
11840 /* -march takes precedence over -mipsN, since it is more descriptive.
11841 There's no harm in specifying both as long as the ISA levels
11843 if (file_mips_isa != arch_info->isa)
11844 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11845 mips_cpu_info_from_isa (file_mips_isa)->name,
11846 mips_cpu_info_from_isa (arch_info->isa)->name);
11849 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11852 if (arch_info == 0)
11853 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11855 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11856 as_bad ("-march=%s is not compatible with the selected ABI",
11859 mips_set_architecture (arch_info);
11861 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11862 if (mips_tune_string != 0)
11863 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11865 if (tune_info == 0)
11866 mips_set_tune (arch_info);
11868 mips_set_tune (tune_info);
11870 if (file_mips_gp32 >= 0)
11872 /* The user specified the size of the integer registers. Make sure
11873 it agrees with the ABI and ISA. */
11874 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11875 as_bad (_("-mgp64 used with a 32-bit processor"));
11876 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11877 as_bad (_("-mgp32 used with a 64-bit ABI"));
11878 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11879 as_bad (_("-mgp64 used with a 32-bit ABI"));
11883 /* Infer the integer register size from the ABI and processor.
11884 Restrict ourselves to 32-bit registers if that's all the
11885 processor has, or if the ABI cannot handle 64-bit registers. */
11886 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11887 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11890 switch (file_mips_fp32)
11894 /* No user specified float register size.
11895 ??? GAS treats single-float processors as though they had 64-bit
11896 float registers (although it complains when double-precision
11897 instructions are used). As things stand, saying they have 32-bit
11898 registers would lead to spurious "register must be even" messages.
11899 So here we assume float registers are never smaller than the
11901 if (file_mips_gp32 == 0)
11902 /* 64-bit integer registers implies 64-bit float registers. */
11903 file_mips_fp32 = 0;
11904 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11905 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11906 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11907 file_mips_fp32 = 0;
11909 /* 32-bit float registers. */
11910 file_mips_fp32 = 1;
11913 /* The user specified the size of the float registers. Check if it
11914 agrees with the ABI and ISA. */
11916 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11917 as_bad (_("-mfp64 used with a 32-bit fpu"));
11918 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11919 && !ISA_HAS_MXHC1 (mips_opts.isa))
11920 as_warn (_("-mfp64 used with a 32-bit ABI"));
11923 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11924 as_warn (_("-mfp32 used with a 64-bit ABI"));
11928 /* End of GCC-shared inference code. */
11930 /* This flag is set when we have a 64-bit capable CPU but use only
11931 32-bit wide registers. Note that EABI does not use it. */
11932 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11933 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11934 || mips_abi == O32_ABI))
11935 mips_32bitmode = 1;
11937 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11938 as_bad (_("trap exception not supported at ISA 1"));
11940 /* If the selected architecture includes support for ASEs, enable
11941 generation of code for them. */
11942 if (mips_opts.mips16 == -1)
11943 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11944 if (mips_opts.ase_mips3d == -1)
11945 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
11946 && file_mips_fp32 == 0) ? 1 : 0;
11947 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
11948 as_bad (_("-mfp32 used with -mips3d"));
11950 if (mips_opts.ase_mdmx == -1)
11951 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
11952 && file_mips_fp32 == 0) ? 1 : 0;
11953 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
11954 as_bad (_("-mfp32 used with -mdmx"));
11956 if (mips_opts.ase_smartmips == -1)
11957 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
11958 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
11959 as_warn ("%s ISA does not support SmartMIPS",
11960 mips_cpu_info_from_isa (mips_opts.isa)->name);
11962 if (mips_opts.ase_dsp == -1)
11963 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11964 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
11965 as_warn ("%s ISA does not support DSP ASE",
11966 mips_cpu_info_from_isa (mips_opts.isa)->name);
11968 if (mips_opts.ase_dspr2 == -1)
11970 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
11971 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11973 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
11974 as_warn ("%s ISA does not support DSP R2 ASE",
11975 mips_cpu_info_from_isa (mips_opts.isa)->name);
11977 if (mips_opts.ase_mt == -1)
11978 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
11979 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
11980 as_warn ("%s ISA does not support MT ASE",
11981 mips_cpu_info_from_isa (mips_opts.isa)->name);
11983 file_mips_isa = mips_opts.isa;
11984 file_ase_mips16 = mips_opts.mips16;
11985 file_ase_mips3d = mips_opts.ase_mips3d;
11986 file_ase_mdmx = mips_opts.ase_mdmx;
11987 file_ase_smartmips = mips_opts.ase_smartmips;
11988 file_ase_dsp = mips_opts.ase_dsp;
11989 file_ase_dspr2 = mips_opts.ase_dspr2;
11990 file_ase_mt = mips_opts.ase_mt;
11991 mips_opts.gp32 = file_mips_gp32;
11992 mips_opts.fp32 = file_mips_fp32;
11993 mips_opts.soft_float = file_mips_soft_float;
11994 mips_opts.single_float = file_mips_single_float;
11996 if (mips_flag_mdebug < 0)
11998 #ifdef OBJ_MAYBE_ECOFF
11999 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12000 mips_flag_mdebug = 1;
12002 #endif /* OBJ_MAYBE_ECOFF */
12003 mips_flag_mdebug = 0;
12008 mips_init_after_args (void)
12010 /* initialize opcodes */
12011 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12012 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12016 md_pcrel_from (fixS *fixP)
12018 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12019 switch (fixP->fx_r_type)
12021 case BFD_RELOC_16_PCREL_S2:
12022 case BFD_RELOC_MIPS_JMP:
12023 /* Return the address of the delay slot. */
12026 /* We have no relocation type for PC relative MIPS16 instructions. */
12027 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12028 as_bad_where (fixP->fx_file, fixP->fx_line,
12029 _("PC relative MIPS16 instruction references a different section"));
12034 /* This is called before the symbol table is processed. In order to
12035 work with gcc when using mips-tfile, we must keep all local labels.
12036 However, in other cases, we want to discard them. If we were
12037 called with -g, but we didn't see any debugging information, it may
12038 mean that gcc is smuggling debugging information through to
12039 mips-tfile, in which case we must generate all local labels. */
12042 mips_frob_file_before_adjust (void)
12044 #ifndef NO_ECOFF_DEBUGGING
12045 if (ECOFF_DEBUGGING
12047 && ! ecoff_debugging_seen)
12048 flag_keep_locals = 1;
12052 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12053 the corresponding LO16 reloc. This is called before md_apply_fix and
12054 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12055 relocation operators.
12057 For our purposes, a %lo() expression matches a %got() or %hi()
12060 (a) it refers to the same symbol; and
12061 (b) the offset applied in the %lo() expression is no lower than
12062 the offset applied in the %got() or %hi().
12064 (b) allows us to cope with code like:
12067 lh $4,%lo(foo+2)($4)
12069 ...which is legal on RELA targets, and has a well-defined behaviour
12070 if the user knows that adding 2 to "foo" will not induce a carry to
12073 When several %lo()s match a particular %got() or %hi(), we use the
12074 following rules to distinguish them:
12076 (1) %lo()s with smaller offsets are a better match than %lo()s with
12079 (2) %lo()s with no matching %got() or %hi() are better than those
12080 that already have a matching %got() or %hi().
12082 (3) later %lo()s are better than earlier %lo()s.
12084 These rules are applied in order.
12086 (1) means, among other things, that %lo()s with identical offsets are
12087 chosen if they exist.
12089 (2) means that we won't associate several high-part relocations with
12090 the same low-part relocation unless there's no alternative. Having
12091 several high parts for the same low part is a GNU extension; this rule
12092 allows careful users to avoid it.
12094 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12095 with the last high-part relocation being at the front of the list.
12096 It therefore makes sense to choose the last matching low-part
12097 relocation, all other things being equal. It's also easier
12098 to code that way. */
12101 mips_frob_file (void)
12103 struct mips_hi_fixup *l;
12104 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12106 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12108 segment_info_type *seginfo;
12109 bfd_boolean matched_lo_p;
12110 fixS **hi_pos, **lo_pos, **pos;
12112 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12114 /* If a GOT16 relocation turns out to be against a global symbol,
12115 there isn't supposed to be a matching LO. */
12116 if (got16_reloc_p (l->fixp->fx_r_type)
12117 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12120 /* Check quickly whether the next fixup happens to be a matching %lo. */
12121 if (fixup_has_matching_lo_p (l->fixp))
12124 seginfo = seg_info (l->seg);
12126 /* Set HI_POS to the position of this relocation in the chain.
12127 Set LO_POS to the position of the chosen low-part relocation.
12128 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12129 relocation that matches an immediately-preceding high-part
12133 matched_lo_p = FALSE;
12134 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12136 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12138 if (*pos == l->fixp)
12141 if ((*pos)->fx_r_type == looking_for_rtype
12142 && (*pos)->fx_addsy == l->fixp->fx_addsy
12143 && (*pos)->fx_offset >= l->fixp->fx_offset
12145 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12147 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12150 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12151 && fixup_has_matching_lo_p (*pos));
12154 /* If we found a match, remove the high-part relocation from its
12155 current position and insert it before the low-part relocation.
12156 Make the offsets match so that fixup_has_matching_lo_p()
12159 We don't warn about unmatched high-part relocations since some
12160 versions of gcc have been known to emit dead "lui ...%hi(...)"
12162 if (lo_pos != NULL)
12164 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12165 if (l->fixp->fx_next != *lo_pos)
12167 *hi_pos = l->fixp->fx_next;
12168 l->fixp->fx_next = *lo_pos;
12175 /* We may have combined relocations without symbols in the N32/N64 ABI.
12176 We have to prevent gas from dropping them. */
12179 mips_force_relocation (fixS *fixp)
12181 if (generic_force_reloc (fixp))
12185 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12186 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12187 || hi16_reloc_p (fixp->fx_r_type)
12188 || lo16_reloc_p (fixp->fx_r_type)))
12194 /* Apply a fixup to the object file. */
12197 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12201 reloc_howto_type *howto;
12203 /* We ignore generic BFD relocations we don't know about. */
12204 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12208 assert (fixP->fx_size == 4
12209 || fixP->fx_r_type == BFD_RELOC_16
12210 || fixP->fx_r_type == BFD_RELOC_64
12211 || fixP->fx_r_type == BFD_RELOC_CTOR
12212 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12213 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12214 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12215 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12217 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12219 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12221 /* Don't treat parts of a composite relocation as done. There are two
12224 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12225 should nevertheless be emitted if the first part is.
12227 (2) In normal usage, composite relocations are never assembly-time
12228 constants. The easiest way of dealing with the pathological
12229 exceptions is to generate a relocation against STN_UNDEF and
12230 leave everything up to the linker. */
12231 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12234 switch (fixP->fx_r_type)
12236 case BFD_RELOC_MIPS_TLS_GD:
12237 case BFD_RELOC_MIPS_TLS_LDM:
12238 case BFD_RELOC_MIPS_TLS_DTPREL32:
12239 case BFD_RELOC_MIPS_TLS_DTPREL64:
12240 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12241 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12242 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12243 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12244 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12245 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12248 case BFD_RELOC_MIPS_JMP:
12249 case BFD_RELOC_MIPS_SHIFT5:
12250 case BFD_RELOC_MIPS_SHIFT6:
12251 case BFD_RELOC_MIPS_GOT_DISP:
12252 case BFD_RELOC_MIPS_GOT_PAGE:
12253 case BFD_RELOC_MIPS_GOT_OFST:
12254 case BFD_RELOC_MIPS_SUB:
12255 case BFD_RELOC_MIPS_INSERT_A:
12256 case BFD_RELOC_MIPS_INSERT_B:
12257 case BFD_RELOC_MIPS_DELETE:
12258 case BFD_RELOC_MIPS_HIGHEST:
12259 case BFD_RELOC_MIPS_HIGHER:
12260 case BFD_RELOC_MIPS_SCN_DISP:
12261 case BFD_RELOC_MIPS_REL16:
12262 case BFD_RELOC_MIPS_RELGOT:
12263 case BFD_RELOC_MIPS_JALR:
12264 case BFD_RELOC_HI16:
12265 case BFD_RELOC_HI16_S:
12266 case BFD_RELOC_GPREL16:
12267 case BFD_RELOC_MIPS_LITERAL:
12268 case BFD_RELOC_MIPS_CALL16:
12269 case BFD_RELOC_MIPS_GOT16:
12270 case BFD_RELOC_GPREL32:
12271 case BFD_RELOC_MIPS_GOT_HI16:
12272 case BFD_RELOC_MIPS_GOT_LO16:
12273 case BFD_RELOC_MIPS_CALL_HI16:
12274 case BFD_RELOC_MIPS_CALL_LO16:
12275 case BFD_RELOC_MIPS16_GPREL:
12276 case BFD_RELOC_MIPS16_GOT16:
12277 case BFD_RELOC_MIPS16_CALL16:
12278 case BFD_RELOC_MIPS16_HI16:
12279 case BFD_RELOC_MIPS16_HI16_S:
12280 case BFD_RELOC_MIPS16_JMP:
12281 /* Nothing needed to do. The value comes from the reloc entry. */
12285 /* This is handled like BFD_RELOC_32, but we output a sign
12286 extended value if we are only 32 bits. */
12289 if (8 <= sizeof (valueT))
12290 md_number_to_chars ((char *) buf, *valP, 8);
12295 if ((*valP & 0x80000000) != 0)
12299 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12301 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12307 case BFD_RELOC_RVA:
12310 /* If we are deleting this reloc entry, we must fill in the
12311 value now. This can happen if we have a .word which is not
12312 resolved when it appears but is later defined. */
12314 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12317 case BFD_RELOC_LO16:
12318 case BFD_RELOC_MIPS16_LO16:
12319 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12320 may be safe to remove, but if so it's not obvious. */
12321 /* When handling an embedded PIC switch statement, we can wind
12322 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12325 if (*valP + 0x8000 > 0xffff)
12326 as_bad_where (fixP->fx_file, fixP->fx_line,
12327 _("relocation overflow"));
12328 if (target_big_endian)
12330 md_number_to_chars ((char *) buf, *valP, 2);
12334 case BFD_RELOC_16_PCREL_S2:
12335 if ((*valP & 0x3) != 0)
12336 as_bad_where (fixP->fx_file, fixP->fx_line,
12337 _("Branch to misaligned address (%lx)"), (long) *valP);
12339 /* We need to save the bits in the instruction since fixup_segment()
12340 might be deleting the relocation entry (i.e., a branch within
12341 the current segment). */
12342 if (! fixP->fx_done)
12345 /* Update old instruction data. */
12346 if (target_big_endian)
12347 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12349 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12351 if (*valP + 0x20000 <= 0x3ffff)
12353 insn |= (*valP >> 2) & 0xffff;
12354 md_number_to_chars ((char *) buf, insn, 4);
12356 else if (mips_pic == NO_PIC
12358 && fixP->fx_frag->fr_address >= text_section->vma
12359 && (fixP->fx_frag->fr_address
12360 < text_section->vma + bfd_get_section_size (text_section))
12361 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12362 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12363 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12365 /* The branch offset is too large. If this is an
12366 unconditional branch, and we are not generating PIC code,
12367 we can convert it to an absolute jump instruction. */
12368 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12369 insn = 0x0c000000; /* jal */
12371 insn = 0x08000000; /* j */
12372 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12374 fixP->fx_addsy = section_symbol (text_section);
12375 *valP += md_pcrel_from (fixP);
12376 md_number_to_chars ((char *) buf, insn, 4);
12380 /* If we got here, we have branch-relaxation disabled,
12381 and there's nothing we can do to fix this instruction
12382 without turning it into a longer sequence. */
12383 as_bad_where (fixP->fx_file, fixP->fx_line,
12384 _("Branch out of range"));
12388 case BFD_RELOC_VTABLE_INHERIT:
12391 && !S_IS_DEFINED (fixP->fx_addsy)
12392 && !S_IS_WEAK (fixP->fx_addsy))
12393 S_SET_WEAK (fixP->fx_addsy);
12396 case BFD_RELOC_VTABLE_ENTRY:
12404 /* Remember value for tc_gen_reloc. */
12405 fixP->fx_addnumber = *valP;
12415 name = input_line_pointer;
12416 c = get_symbol_end ();
12417 p = (symbolS *) symbol_find_or_make (name);
12418 *input_line_pointer = c;
12422 /* Align the current frag to a given power of two. If a particular
12423 fill byte should be used, FILL points to an integer that contains
12424 that byte, otherwise FILL is null.
12426 The MIPS assembler also automatically adjusts any preceding
12430 mips_align (int to, int *fill, symbolS *label)
12432 mips_emit_delays ();
12433 mips_record_mips16_mode ();
12434 if (fill == NULL && subseg_text_p (now_seg))
12435 frag_align_code (to, 0);
12437 frag_align (to, fill ? *fill : 0, 0);
12438 record_alignment (now_seg, to);
12441 assert (S_GET_SEGMENT (label) == now_seg);
12442 symbol_set_frag (label, frag_now);
12443 S_SET_VALUE (label, (valueT) frag_now_fix ());
12447 /* Align to a given power of two. .align 0 turns off the automatic
12448 alignment used by the data creating pseudo-ops. */
12451 s_align (int x ATTRIBUTE_UNUSED)
12453 int temp, fill_value, *fill_ptr;
12454 long max_alignment = 28;
12456 /* o Note that the assembler pulls down any immediately preceding label
12457 to the aligned address.
12458 o It's not documented but auto alignment is reinstated by
12459 a .align pseudo instruction.
12460 o Note also that after auto alignment is turned off the mips assembler
12461 issues an error on attempt to assemble an improperly aligned data item.
12464 temp = get_absolute_expression ();
12465 if (temp > max_alignment)
12466 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12469 as_warn (_("Alignment negative: 0 assumed."));
12472 if (*input_line_pointer == ',')
12474 ++input_line_pointer;
12475 fill_value = get_absolute_expression ();
12476 fill_ptr = &fill_value;
12482 segment_info_type *si = seg_info (now_seg);
12483 struct insn_label_list *l = si->label_list;
12484 /* Auto alignment should be switched on by next section change. */
12486 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12493 demand_empty_rest_of_line ();
12497 s_change_sec (int sec)
12502 /* The ELF backend needs to know that we are changing sections, so
12503 that .previous works correctly. We could do something like check
12504 for an obj_section_change_hook macro, but that might be confusing
12505 as it would not be appropriate to use it in the section changing
12506 functions in read.c, since obj-elf.c intercepts those. FIXME:
12507 This should be cleaner, somehow. */
12509 obj_elf_section_change_hook ();
12512 mips_emit_delays ();
12523 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12524 demand_empty_rest_of_line ();
12528 seg = subseg_new (RDATA_SECTION_NAME,
12529 (subsegT) get_absolute_expression ());
12532 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12533 | SEC_READONLY | SEC_RELOC
12535 if (strncmp (TARGET_OS, "elf", 3) != 0)
12536 record_alignment (seg, 4);
12538 demand_empty_rest_of_line ();
12542 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12545 bfd_set_section_flags (stdoutput, seg,
12546 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12547 if (strncmp (TARGET_OS, "elf", 3) != 0)
12548 record_alignment (seg, 4);
12550 demand_empty_rest_of_line ();
12558 s_change_section (int ignore ATTRIBUTE_UNUSED)
12561 char *section_name;
12566 int section_entry_size;
12567 int section_alignment;
12572 section_name = input_line_pointer;
12573 c = get_symbol_end ();
12575 next_c = *(input_line_pointer + 1);
12577 /* Do we have .section Name<,"flags">? */
12578 if (c != ',' || (c == ',' && next_c == '"'))
12580 /* just after name is now '\0'. */
12581 *input_line_pointer = c;
12582 input_line_pointer = section_name;
12583 obj_elf_section (ignore);
12586 input_line_pointer++;
12588 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12590 section_type = get_absolute_expression ();
12593 if (*input_line_pointer++ == ',')
12594 section_flag = get_absolute_expression ();
12597 if (*input_line_pointer++ == ',')
12598 section_entry_size = get_absolute_expression ();
12600 section_entry_size = 0;
12601 if (*input_line_pointer++ == ',')
12602 section_alignment = get_absolute_expression ();
12604 section_alignment = 0;
12606 section_name = xstrdup (section_name);
12608 /* When using the generic form of .section (as implemented by obj-elf.c),
12609 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12610 traditionally had to fall back on the more common @progbits instead.
12612 There's nothing really harmful in this, since bfd will correct
12613 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12614 means that, for backwards compatibility, the special_section entries
12615 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12617 Even so, we shouldn't force users of the MIPS .section syntax to
12618 incorrectly label the sections as SHT_PROGBITS. The best compromise
12619 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12620 generic type-checking code. */
12621 if (section_type == SHT_MIPS_DWARF)
12622 section_type = SHT_PROGBITS;
12624 obj_elf_change_section (section_name, section_type, section_flag,
12625 section_entry_size, 0, 0, 0);
12627 if (now_seg->name != section_name)
12628 free (section_name);
12629 #endif /* OBJ_ELF */
12633 mips_enable_auto_align (void)
12639 s_cons (int log_size)
12641 segment_info_type *si = seg_info (now_seg);
12642 struct insn_label_list *l = si->label_list;
12645 label = l != NULL ? l->label : NULL;
12646 mips_emit_delays ();
12647 if (log_size > 0 && auto_align)
12648 mips_align (log_size, 0, label);
12649 mips_clear_insn_labels ();
12650 cons (1 << log_size);
12654 s_float_cons (int type)
12656 segment_info_type *si = seg_info (now_seg);
12657 struct insn_label_list *l = si->label_list;
12660 label = l != NULL ? l->label : NULL;
12662 mips_emit_delays ();
12667 mips_align (3, 0, label);
12669 mips_align (2, 0, label);
12672 mips_clear_insn_labels ();
12677 /* Handle .globl. We need to override it because on Irix 5 you are
12680 where foo is an undefined symbol, to mean that foo should be
12681 considered to be the address of a function. */
12684 s_mips_globl (int x ATTRIBUTE_UNUSED)
12693 name = input_line_pointer;
12694 c = get_symbol_end ();
12695 symbolP = symbol_find_or_make (name);
12696 S_SET_EXTERNAL (symbolP);
12698 *input_line_pointer = c;
12699 SKIP_WHITESPACE ();
12701 /* On Irix 5, every global symbol that is not explicitly labelled as
12702 being a function is apparently labelled as being an object. */
12705 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12706 && (*input_line_pointer != ','))
12711 secname = input_line_pointer;
12712 c = get_symbol_end ();
12713 sec = bfd_get_section_by_name (stdoutput, secname);
12715 as_bad (_("%s: no such section"), secname);
12716 *input_line_pointer = c;
12718 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12719 flag = BSF_FUNCTION;
12722 symbol_get_bfdsym (symbolP)->flags |= flag;
12724 c = *input_line_pointer;
12727 input_line_pointer++;
12728 SKIP_WHITESPACE ();
12729 if (is_end_of_line[(unsigned char) *input_line_pointer])
12735 demand_empty_rest_of_line ();
12739 s_option (int x ATTRIBUTE_UNUSED)
12744 opt = input_line_pointer;
12745 c = get_symbol_end ();
12749 /* FIXME: What does this mean? */
12751 else if (strncmp (opt, "pic", 3) == 0)
12755 i = atoi (opt + 3);
12760 mips_pic = SVR4_PIC;
12761 mips_abicalls = TRUE;
12764 as_bad (_(".option pic%d not supported"), i);
12766 if (mips_pic == SVR4_PIC)
12768 if (g_switch_seen && g_switch_value != 0)
12769 as_warn (_("-G may not be used with SVR4 PIC code"));
12770 g_switch_value = 0;
12771 bfd_set_gp_size (stdoutput, 0);
12775 as_warn (_("Unrecognized option \"%s\""), opt);
12777 *input_line_pointer = c;
12778 demand_empty_rest_of_line ();
12781 /* This structure is used to hold a stack of .set values. */
12783 struct mips_option_stack
12785 struct mips_option_stack *next;
12786 struct mips_set_options options;
12789 static struct mips_option_stack *mips_opts_stack;
12791 /* Handle the .set pseudo-op. */
12794 s_mipsset (int x ATTRIBUTE_UNUSED)
12796 char *name = input_line_pointer, ch;
12798 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12799 ++input_line_pointer;
12800 ch = *input_line_pointer;
12801 *input_line_pointer = '\0';
12803 if (strcmp (name, "reorder") == 0)
12805 if (mips_opts.noreorder)
12808 else if (strcmp (name, "noreorder") == 0)
12810 if (!mips_opts.noreorder)
12811 start_noreorder ();
12813 else if (strncmp (name, "at=", 3) == 0)
12815 char *s = name + 3;
12817 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12818 as_bad (_("Unrecognized register name `%s'"), s);
12820 else if (strcmp (name, "at") == 0)
12822 mips_opts.at = ATREG;
12824 else if (strcmp (name, "noat") == 0)
12826 mips_opts.at = ZERO;
12828 else if (strcmp (name, "macro") == 0)
12830 mips_opts.warn_about_macros = 0;
12832 else if (strcmp (name, "nomacro") == 0)
12834 if (mips_opts.noreorder == 0)
12835 as_bad (_("`noreorder' must be set before `nomacro'"));
12836 mips_opts.warn_about_macros = 1;
12838 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12840 mips_opts.nomove = 0;
12842 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12844 mips_opts.nomove = 1;
12846 else if (strcmp (name, "bopt") == 0)
12848 mips_opts.nobopt = 0;
12850 else if (strcmp (name, "nobopt") == 0)
12852 mips_opts.nobopt = 1;
12854 else if (strcmp (name, "gp=default") == 0)
12855 mips_opts.gp32 = file_mips_gp32;
12856 else if (strcmp (name, "gp=32") == 0)
12857 mips_opts.gp32 = 1;
12858 else if (strcmp (name, "gp=64") == 0)
12860 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12861 as_warn ("%s isa does not support 64-bit registers",
12862 mips_cpu_info_from_isa (mips_opts.isa)->name);
12863 mips_opts.gp32 = 0;
12865 else if (strcmp (name, "fp=default") == 0)
12866 mips_opts.fp32 = file_mips_fp32;
12867 else if (strcmp (name, "fp=32") == 0)
12868 mips_opts.fp32 = 1;
12869 else if (strcmp (name, "fp=64") == 0)
12871 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12872 as_warn ("%s isa does not support 64-bit floating point registers",
12873 mips_cpu_info_from_isa (mips_opts.isa)->name);
12874 mips_opts.fp32 = 0;
12876 else if (strcmp (name, "softfloat") == 0)
12877 mips_opts.soft_float = 1;
12878 else if (strcmp (name, "hardfloat") == 0)
12879 mips_opts.soft_float = 0;
12880 else if (strcmp (name, "singlefloat") == 0)
12881 mips_opts.single_float = 1;
12882 else if (strcmp (name, "doublefloat") == 0)
12883 mips_opts.single_float = 0;
12884 else if (strcmp (name, "mips16") == 0
12885 || strcmp (name, "MIPS-16") == 0)
12886 mips_opts.mips16 = 1;
12887 else if (strcmp (name, "nomips16") == 0
12888 || strcmp (name, "noMIPS-16") == 0)
12889 mips_opts.mips16 = 0;
12890 else if (strcmp (name, "smartmips") == 0)
12892 if (!ISA_SUPPORTS_SMARTMIPS)
12893 as_warn ("%s ISA does not support SmartMIPS ASE",
12894 mips_cpu_info_from_isa (mips_opts.isa)->name);
12895 mips_opts.ase_smartmips = 1;
12897 else if (strcmp (name, "nosmartmips") == 0)
12898 mips_opts.ase_smartmips = 0;
12899 else if (strcmp (name, "mips3d") == 0)
12900 mips_opts.ase_mips3d = 1;
12901 else if (strcmp (name, "nomips3d") == 0)
12902 mips_opts.ase_mips3d = 0;
12903 else if (strcmp (name, "mdmx") == 0)
12904 mips_opts.ase_mdmx = 1;
12905 else if (strcmp (name, "nomdmx") == 0)
12906 mips_opts.ase_mdmx = 0;
12907 else if (strcmp (name, "dsp") == 0)
12909 if (!ISA_SUPPORTS_DSP_ASE)
12910 as_warn ("%s ISA does not support DSP ASE",
12911 mips_cpu_info_from_isa (mips_opts.isa)->name);
12912 mips_opts.ase_dsp = 1;
12913 mips_opts.ase_dspr2 = 0;
12915 else if (strcmp (name, "nodsp") == 0)
12917 mips_opts.ase_dsp = 0;
12918 mips_opts.ase_dspr2 = 0;
12920 else if (strcmp (name, "dspr2") == 0)
12922 if (!ISA_SUPPORTS_DSPR2_ASE)
12923 as_warn ("%s ISA does not support DSP R2 ASE",
12924 mips_cpu_info_from_isa (mips_opts.isa)->name);
12925 mips_opts.ase_dspr2 = 1;
12926 mips_opts.ase_dsp = 1;
12928 else if (strcmp (name, "nodspr2") == 0)
12930 mips_opts.ase_dspr2 = 0;
12931 mips_opts.ase_dsp = 0;
12933 else if (strcmp (name, "mt") == 0)
12935 if (!ISA_SUPPORTS_MT_ASE)
12936 as_warn ("%s ISA does not support MT ASE",
12937 mips_cpu_info_from_isa (mips_opts.isa)->name);
12938 mips_opts.ase_mt = 1;
12940 else if (strcmp (name, "nomt") == 0)
12941 mips_opts.ase_mt = 0;
12942 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12946 /* Permit the user to change the ISA and architecture on the fly.
12947 Needless to say, misuse can cause serious problems. */
12948 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
12951 mips_opts.isa = file_mips_isa;
12952 mips_opts.arch = file_mips_arch;
12954 else if (strncmp (name, "arch=", 5) == 0)
12956 const struct mips_cpu_info *p;
12958 p = mips_parse_cpu("internal use", name + 5);
12960 as_bad (_("unknown architecture %s"), name + 5);
12963 mips_opts.arch = p->cpu;
12964 mips_opts.isa = p->isa;
12967 else if (strncmp (name, "mips", 4) == 0)
12969 const struct mips_cpu_info *p;
12971 p = mips_parse_cpu("internal use", name);
12973 as_bad (_("unknown ISA level %s"), name + 4);
12976 mips_opts.arch = p->cpu;
12977 mips_opts.isa = p->isa;
12981 as_bad (_("unknown ISA or architecture %s"), name);
12983 switch (mips_opts.isa)
12991 mips_opts.gp32 = 1;
12992 mips_opts.fp32 = 1;
12999 mips_opts.gp32 = 0;
13000 mips_opts.fp32 = 0;
13003 as_bad (_("unknown ISA level %s"), name + 4);
13008 mips_opts.gp32 = file_mips_gp32;
13009 mips_opts.fp32 = file_mips_fp32;
13012 else if (strcmp (name, "autoextend") == 0)
13013 mips_opts.noautoextend = 0;
13014 else if (strcmp (name, "noautoextend") == 0)
13015 mips_opts.noautoextend = 1;
13016 else if (strcmp (name, "push") == 0)
13018 struct mips_option_stack *s;
13020 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13021 s->next = mips_opts_stack;
13022 s->options = mips_opts;
13023 mips_opts_stack = s;
13025 else if (strcmp (name, "pop") == 0)
13027 struct mips_option_stack *s;
13029 s = mips_opts_stack;
13031 as_bad (_(".set pop with no .set push"));
13034 /* If we're changing the reorder mode we need to handle
13035 delay slots correctly. */
13036 if (s->options.noreorder && ! mips_opts.noreorder)
13037 start_noreorder ();
13038 else if (! s->options.noreorder && mips_opts.noreorder)
13041 mips_opts = s->options;
13042 mips_opts_stack = s->next;
13046 else if (strcmp (name, "sym32") == 0)
13047 mips_opts.sym32 = TRUE;
13048 else if (strcmp (name, "nosym32") == 0)
13049 mips_opts.sym32 = FALSE;
13050 else if (strchr (name, ','))
13052 /* Generic ".set" directive; use the generic handler. */
13053 *input_line_pointer = ch;
13054 input_line_pointer = name;
13060 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13062 *input_line_pointer = ch;
13063 demand_empty_rest_of_line ();
13066 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13067 .option pic2. It means to generate SVR4 PIC calls. */
13070 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13072 mips_pic = SVR4_PIC;
13073 mips_abicalls = TRUE;
13075 if (g_switch_seen && g_switch_value != 0)
13076 as_warn (_("-G may not be used with SVR4 PIC code"));
13077 g_switch_value = 0;
13079 bfd_set_gp_size (stdoutput, 0);
13080 demand_empty_rest_of_line ();
13083 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13084 PIC code. It sets the $gp register for the function based on the
13085 function address, which is in the register named in the argument.
13086 This uses a relocation against _gp_disp, which is handled specially
13087 by the linker. The result is:
13088 lui $gp,%hi(_gp_disp)
13089 addiu $gp,$gp,%lo(_gp_disp)
13090 addu $gp,$gp,.cpload argument
13091 The .cpload argument is normally $25 == $t9.
13093 The -mno-shared option changes this to:
13094 lui $gp,%hi(__gnu_local_gp)
13095 addiu $gp,$gp,%lo(__gnu_local_gp)
13096 and the argument is ignored. This saves an instruction, but the
13097 resulting code is not position independent; it uses an absolute
13098 address for __gnu_local_gp. Thus code assembled with -mno-shared
13099 can go into an ordinary executable, but not into a shared library. */
13102 s_cpload (int ignore ATTRIBUTE_UNUSED)
13108 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13109 .cpload is ignored. */
13110 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13116 /* .cpload should be in a .set noreorder section. */
13117 if (mips_opts.noreorder == 0)
13118 as_warn (_(".cpload not in noreorder section"));
13120 reg = tc_get_register (0);
13122 /* If we need to produce a 64-bit address, we are better off using
13123 the default instruction sequence. */
13124 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13126 ex.X_op = O_symbol;
13127 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13129 ex.X_op_symbol = NULL;
13130 ex.X_add_number = 0;
13132 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13133 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13136 macro_build_lui (&ex, mips_gp_register);
13137 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13138 mips_gp_register, BFD_RELOC_LO16);
13140 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13141 mips_gp_register, reg);
13144 demand_empty_rest_of_line ();
13147 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13148 .cpsetup $reg1, offset|$reg2, label
13150 If offset is given, this results in:
13151 sd $gp, offset($sp)
13152 lui $gp, %hi(%neg(%gp_rel(label)))
13153 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13154 daddu $gp, $gp, $reg1
13156 If $reg2 is given, this results in:
13157 daddu $reg2, $gp, $0
13158 lui $gp, %hi(%neg(%gp_rel(label)))
13159 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13160 daddu $gp, $gp, $reg1
13161 $reg1 is normally $25 == $t9.
13163 The -mno-shared option replaces the last three instructions with
13165 addiu $gp,$gp,%lo(_gp) */
13168 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13170 expressionS ex_off;
13171 expressionS ex_sym;
13174 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13175 We also need NewABI support. */
13176 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13182 reg1 = tc_get_register (0);
13183 SKIP_WHITESPACE ();
13184 if (*input_line_pointer != ',')
13186 as_bad (_("missing argument separator ',' for .cpsetup"));
13190 ++input_line_pointer;
13191 SKIP_WHITESPACE ();
13192 if (*input_line_pointer == '$')
13194 mips_cpreturn_register = tc_get_register (0);
13195 mips_cpreturn_offset = -1;
13199 mips_cpreturn_offset = get_absolute_expression ();
13200 mips_cpreturn_register = -1;
13202 SKIP_WHITESPACE ();
13203 if (*input_line_pointer != ',')
13205 as_bad (_("missing argument separator ',' for .cpsetup"));
13209 ++input_line_pointer;
13210 SKIP_WHITESPACE ();
13211 expression (&ex_sym);
13214 if (mips_cpreturn_register == -1)
13216 ex_off.X_op = O_constant;
13217 ex_off.X_add_symbol = NULL;
13218 ex_off.X_op_symbol = NULL;
13219 ex_off.X_add_number = mips_cpreturn_offset;
13221 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13222 BFD_RELOC_LO16, SP);
13225 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13226 mips_gp_register, 0);
13228 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13230 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13231 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13234 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13235 mips_gp_register, -1, BFD_RELOC_GPREL16,
13236 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13238 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13239 mips_gp_register, reg1);
13245 ex.X_op = O_symbol;
13246 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13247 ex.X_op_symbol = NULL;
13248 ex.X_add_number = 0;
13250 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13251 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13253 macro_build_lui (&ex, mips_gp_register);
13254 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13255 mips_gp_register, BFD_RELOC_LO16);
13260 demand_empty_rest_of_line ();
13264 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13266 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13267 .cplocal is ignored. */
13268 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13274 mips_gp_register = tc_get_register (0);
13275 demand_empty_rest_of_line ();
13278 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13279 offset from $sp. The offset is remembered, and after making a PIC
13280 call $gp is restored from that location. */
13283 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13287 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13288 .cprestore is ignored. */
13289 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13295 mips_cprestore_offset = get_absolute_expression ();
13296 mips_cprestore_valid = 1;
13298 ex.X_op = O_constant;
13299 ex.X_add_symbol = NULL;
13300 ex.X_op_symbol = NULL;
13301 ex.X_add_number = mips_cprestore_offset;
13304 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13305 SP, HAVE_64BIT_ADDRESSES);
13308 demand_empty_rest_of_line ();
13311 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13312 was given in the preceding .cpsetup, it results in:
13313 ld $gp, offset($sp)
13315 If a register $reg2 was given there, it results in:
13316 daddu $gp, $reg2, $0 */
13319 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13323 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13324 We also need NewABI support. */
13325 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13332 if (mips_cpreturn_register == -1)
13334 ex.X_op = O_constant;
13335 ex.X_add_symbol = NULL;
13336 ex.X_op_symbol = NULL;
13337 ex.X_add_number = mips_cpreturn_offset;
13339 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13342 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13343 mips_cpreturn_register, 0);
13346 demand_empty_rest_of_line ();
13349 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13350 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13351 use in DWARF debug information. */
13354 s_dtprel_internal (size_t bytes)
13361 if (ex.X_op != O_symbol)
13363 as_bad (_("Unsupported use of %s"), (bytes == 8
13366 ignore_rest_of_line ();
13369 p = frag_more (bytes);
13370 md_number_to_chars (p, 0, bytes);
13371 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13373 ? BFD_RELOC_MIPS_TLS_DTPREL64
13374 : BFD_RELOC_MIPS_TLS_DTPREL32));
13376 demand_empty_rest_of_line ();
13379 /* Handle .dtprelword. */
13382 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13384 s_dtprel_internal (4);
13387 /* Handle .dtpreldword. */
13390 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13392 s_dtprel_internal (8);
13395 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13396 code. It sets the offset to use in gp_rel relocations. */
13399 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13401 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13402 We also need NewABI support. */
13403 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13409 mips_gprel_offset = get_absolute_expression ();
13411 demand_empty_rest_of_line ();
13414 /* Handle the .gpword pseudo-op. This is used when generating PIC
13415 code. It generates a 32 bit GP relative reloc. */
13418 s_gpword (int ignore ATTRIBUTE_UNUSED)
13420 segment_info_type *si;
13421 struct insn_label_list *l;
13426 /* When not generating PIC code, this is treated as .word. */
13427 if (mips_pic != SVR4_PIC)
13433 si = seg_info (now_seg);
13434 l = si->label_list;
13435 label = l != NULL ? l->label : NULL;
13436 mips_emit_delays ();
13438 mips_align (2, 0, label);
13439 mips_clear_insn_labels ();
13443 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13445 as_bad (_("Unsupported use of .gpword"));
13446 ignore_rest_of_line ();
13450 md_number_to_chars (p, 0, 4);
13451 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13452 BFD_RELOC_GPREL32);
13454 demand_empty_rest_of_line ();
13458 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13460 segment_info_type *si;
13461 struct insn_label_list *l;
13466 /* When not generating PIC code, this is treated as .dword. */
13467 if (mips_pic != SVR4_PIC)
13473 si = seg_info (now_seg);
13474 l = si->label_list;
13475 label = l != NULL ? l->label : NULL;
13476 mips_emit_delays ();
13478 mips_align (3, 0, label);
13479 mips_clear_insn_labels ();
13483 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13485 as_bad (_("Unsupported use of .gpdword"));
13486 ignore_rest_of_line ();
13490 md_number_to_chars (p, 0, 8);
13491 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13492 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13494 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13495 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13496 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13498 demand_empty_rest_of_line ();
13501 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13502 tables in SVR4 PIC code. */
13505 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13509 /* This is ignored when not generating SVR4 PIC code. */
13510 if (mips_pic != SVR4_PIC)
13516 /* Add $gp to the register named as an argument. */
13518 reg = tc_get_register (0);
13519 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13522 demand_empty_rest_of_line ();
13525 /* Handle the .insn pseudo-op. This marks instruction labels in
13526 mips16 mode. This permits the linker to handle them specially,
13527 such as generating jalx instructions when needed. We also make
13528 them odd for the duration of the assembly, in order to generate the
13529 right sort of code. We will make them even in the adjust_symtab
13530 routine, while leaving them marked. This is convenient for the
13531 debugger and the disassembler. The linker knows to make them odd
13535 s_insn (int ignore ATTRIBUTE_UNUSED)
13537 mips16_mark_labels ();
13539 demand_empty_rest_of_line ();
13542 /* Handle a .stabn directive. We need these in order to mark a label
13543 as being a mips16 text label correctly. Sometimes the compiler
13544 will emit a label, followed by a .stabn, and then switch sections.
13545 If the label and .stabn are in mips16 mode, then the label is
13546 really a mips16 text label. */
13549 s_mips_stab (int type)
13552 mips16_mark_labels ();
13557 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13560 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13567 name = input_line_pointer;
13568 c = get_symbol_end ();
13569 symbolP = symbol_find_or_make (name);
13570 S_SET_WEAK (symbolP);
13571 *input_line_pointer = c;
13573 SKIP_WHITESPACE ();
13575 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13577 if (S_IS_DEFINED (symbolP))
13579 as_bad ("ignoring attempt to redefine symbol %s",
13580 S_GET_NAME (symbolP));
13581 ignore_rest_of_line ();
13585 if (*input_line_pointer == ',')
13587 ++input_line_pointer;
13588 SKIP_WHITESPACE ();
13592 if (exp.X_op != O_symbol)
13594 as_bad ("bad .weakext directive");
13595 ignore_rest_of_line ();
13598 symbol_set_value_expression (symbolP, &exp);
13601 demand_empty_rest_of_line ();
13604 /* Parse a register string into a number. Called from the ECOFF code
13605 to parse .frame. The argument is non-zero if this is the frame
13606 register, so that we can record it in mips_frame_reg. */
13609 tc_get_register (int frame)
13613 SKIP_WHITESPACE ();
13614 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13618 mips_frame_reg = reg != 0 ? reg : SP;
13619 mips_frame_reg_valid = 1;
13620 mips_cprestore_valid = 0;
13626 md_section_align (asection *seg, valueT addr)
13628 int align = bfd_get_section_alignment (stdoutput, seg);
13632 /* We don't need to align ELF sections to the full alignment.
13633 However, Irix 5 may prefer that we align them at least to a 16
13634 byte boundary. We don't bother to align the sections if we
13635 are targeted for an embedded system. */
13636 if (strncmp (TARGET_OS, "elf", 3) == 0)
13642 return ((addr + (1 << align) - 1) & (-1 << align));
13645 /* Utility routine, called from above as well. If called while the
13646 input file is still being read, it's only an approximation. (For
13647 example, a symbol may later become defined which appeared to be
13648 undefined earlier.) */
13651 nopic_need_relax (symbolS *sym, int before_relaxing)
13656 if (g_switch_value > 0)
13658 const char *symname;
13661 /* Find out whether this symbol can be referenced off the $gp
13662 register. It can be if it is smaller than the -G size or if
13663 it is in the .sdata or .sbss section. Certain symbols can
13664 not be referenced off the $gp, although it appears as though
13666 symname = S_GET_NAME (sym);
13667 if (symname != (const char *) NULL
13668 && (strcmp (symname, "eprol") == 0
13669 || strcmp (symname, "etext") == 0
13670 || strcmp (symname, "_gp") == 0
13671 || strcmp (symname, "edata") == 0
13672 || strcmp (symname, "_fbss") == 0
13673 || strcmp (symname, "_fdata") == 0
13674 || strcmp (symname, "_ftext") == 0
13675 || strcmp (symname, "end") == 0
13676 || strcmp (symname, "_gp_disp") == 0))
13678 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13680 #ifndef NO_ECOFF_DEBUGGING
13681 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13682 && (symbol_get_obj (sym)->ecoff_extern_size
13683 <= g_switch_value))
13685 /* We must defer this decision until after the whole
13686 file has been read, since there might be a .extern
13687 after the first use of this symbol. */
13688 || (before_relaxing
13689 #ifndef NO_ECOFF_DEBUGGING
13690 && symbol_get_obj (sym)->ecoff_extern_size == 0
13692 && S_GET_VALUE (sym) == 0)
13693 || (S_GET_VALUE (sym) != 0
13694 && S_GET_VALUE (sym) <= g_switch_value)))
13698 const char *segname;
13700 segname = segment_name (S_GET_SEGMENT (sym));
13701 assert (strcmp (segname, ".lit8") != 0
13702 && strcmp (segname, ".lit4") != 0);
13703 change = (strcmp (segname, ".sdata") != 0
13704 && strcmp (segname, ".sbss") != 0
13705 && strncmp (segname, ".sdata.", 7) != 0
13706 && strncmp (segname, ".sbss.", 6) != 0
13707 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13708 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13713 /* We are not optimizing for the $gp register. */
13718 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13721 pic_need_relax (symbolS *sym, asection *segtype)
13725 /* Handle the case of a symbol equated to another symbol. */
13726 while (symbol_equated_reloc_p (sym))
13730 /* It's possible to get a loop here in a badly written program. */
13731 n = symbol_get_value_expression (sym)->X_add_symbol;
13737 if (symbol_section_p (sym))
13740 symsec = S_GET_SEGMENT (sym);
13742 /* This must duplicate the test in adjust_reloc_syms. */
13743 return (symsec != &bfd_und_section
13744 && symsec != &bfd_abs_section
13745 && !bfd_is_com_section (symsec)
13746 && !s_is_linkonce (sym, segtype)
13748 /* A global or weak symbol is treated as external. */
13749 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13755 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13756 extended opcode. SEC is the section the frag is in. */
13759 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13762 const struct mips16_immed_operand *op;
13764 int mintiny, maxtiny;
13768 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13770 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13773 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13774 op = mips16_immed_operands;
13775 while (op->type != type)
13778 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13783 if (type == '<' || type == '>' || type == '[' || type == ']')
13786 maxtiny = 1 << op->nbits;
13791 maxtiny = (1 << op->nbits) - 1;
13796 mintiny = - (1 << (op->nbits - 1));
13797 maxtiny = (1 << (op->nbits - 1)) - 1;
13800 sym_frag = symbol_get_frag (fragp->fr_symbol);
13801 val = S_GET_VALUE (fragp->fr_symbol);
13802 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13808 /* We won't have the section when we are called from
13809 mips_relax_frag. However, we will always have been called
13810 from md_estimate_size_before_relax first. If this is a
13811 branch to a different section, we mark it as such. If SEC is
13812 NULL, and the frag is not marked, then it must be a branch to
13813 the same section. */
13816 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13821 /* Must have been called from md_estimate_size_before_relax. */
13824 fragp->fr_subtype =
13825 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13827 /* FIXME: We should support this, and let the linker
13828 catch branches and loads that are out of range. */
13829 as_bad_where (fragp->fr_file, fragp->fr_line,
13830 _("unsupported PC relative reference to different section"));
13834 if (fragp != sym_frag && sym_frag->fr_address == 0)
13835 /* Assume non-extended on the first relaxation pass.
13836 The address we have calculated will be bogus if this is
13837 a forward branch to another frag, as the forward frag
13838 will have fr_address == 0. */
13842 /* In this case, we know for sure that the symbol fragment is in
13843 the same section. If the relax_marker of the symbol fragment
13844 differs from the relax_marker of this fragment, we have not
13845 yet adjusted the symbol fragment fr_address. We want to add
13846 in STRETCH in order to get a better estimate of the address.
13847 This particularly matters because of the shift bits. */
13849 && sym_frag->relax_marker != fragp->relax_marker)
13853 /* Adjust stretch for any alignment frag. Note that if have
13854 been expanding the earlier code, the symbol may be
13855 defined in what appears to be an earlier frag. FIXME:
13856 This doesn't handle the fr_subtype field, which specifies
13857 a maximum number of bytes to skip when doing an
13859 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13861 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13864 stretch = - ((- stretch)
13865 & ~ ((1 << (int) f->fr_offset) - 1));
13867 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13876 addr = fragp->fr_address + fragp->fr_fix;
13878 /* The base address rules are complicated. The base address of
13879 a branch is the following instruction. The base address of a
13880 PC relative load or add is the instruction itself, but if it
13881 is in a delay slot (in which case it can not be extended) use
13882 the address of the instruction whose delay slot it is in. */
13883 if (type == 'p' || type == 'q')
13887 /* If we are currently assuming that this frag should be
13888 extended, then, the current address is two bytes
13890 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13893 /* Ignore the low bit in the target, since it will be set
13894 for a text label. */
13895 if ((val & 1) != 0)
13898 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13900 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13903 val -= addr & ~ ((1 << op->shift) - 1);
13905 /* Branch offsets have an implicit 0 in the lowest bit. */
13906 if (type == 'p' || type == 'q')
13909 /* If any of the shifted bits are set, we must use an extended
13910 opcode. If the address depends on the size of this
13911 instruction, this can lead to a loop, so we arrange to always
13912 use an extended opcode. We only check this when we are in
13913 the main relaxation loop, when SEC is NULL. */
13914 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
13916 fragp->fr_subtype =
13917 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13921 /* If we are about to mark a frag as extended because the value
13922 is precisely maxtiny + 1, then there is a chance of an
13923 infinite loop as in the following code:
13928 In this case when the la is extended, foo is 0x3fc bytes
13929 away, so the la can be shrunk, but then foo is 0x400 away, so
13930 the la must be extended. To avoid this loop, we mark the
13931 frag as extended if it was small, and is about to become
13932 extended with a value of maxtiny + 1. */
13933 if (val == ((maxtiny + 1) << op->shift)
13934 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
13937 fragp->fr_subtype =
13938 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13942 else if (symsec != absolute_section && sec != NULL)
13943 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
13945 if ((val & ((1 << op->shift) - 1)) != 0
13946 || val < (mintiny << op->shift)
13947 || val > (maxtiny << op->shift))
13953 /* Compute the length of a branch sequence, and adjust the
13954 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13955 worst-case length is computed, with UPDATE being used to indicate
13956 whether an unconditional (-1), branch-likely (+1) or regular (0)
13957 branch is to be computed. */
13959 relaxed_branch_length (fragS *fragp, asection *sec, int update)
13961 bfd_boolean toofar;
13965 && S_IS_DEFINED (fragp->fr_symbol)
13966 && sec == S_GET_SEGMENT (fragp->fr_symbol))
13971 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
13973 addr = fragp->fr_address + fragp->fr_fix + 4;
13977 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
13980 /* If the symbol is not defined or it's in a different segment,
13981 assume the user knows what's going on and emit a short
13987 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13989 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
13990 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
13991 RELAX_BRANCH_LINK (fragp->fr_subtype),
13997 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14000 if (mips_pic != NO_PIC)
14002 /* Additional space for PIC loading of target address. */
14004 if (mips_opts.isa == ISA_MIPS1)
14005 /* Additional space for $at-stabilizing nop. */
14009 /* If branch is conditional. */
14010 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14017 /* Estimate the size of a frag before relaxing. Unless this is the
14018 mips16, we are not really relaxing here, and the final size is
14019 encoded in the subtype information. For the mips16, we have to
14020 decide whether we are using an extended opcode or not. */
14023 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14027 if (RELAX_BRANCH_P (fragp->fr_subtype))
14030 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14032 return fragp->fr_var;
14035 if (RELAX_MIPS16_P (fragp->fr_subtype))
14036 /* We don't want to modify the EXTENDED bit here; it might get us
14037 into infinite loops. We change it only in mips_relax_frag(). */
14038 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14040 if (mips_pic == NO_PIC)
14041 change = nopic_need_relax (fragp->fr_symbol, 0);
14042 else if (mips_pic == SVR4_PIC)
14043 change = pic_need_relax (fragp->fr_symbol, segtype);
14044 else if (mips_pic == VXWORKS_PIC)
14045 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14052 fragp->fr_subtype |= RELAX_USE_SECOND;
14053 return -RELAX_FIRST (fragp->fr_subtype);
14056 return -RELAX_SECOND (fragp->fr_subtype);
14059 /* This is called to see whether a reloc against a defined symbol
14060 should be converted into a reloc against a section. */
14063 mips_fix_adjustable (fixS *fixp)
14065 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14066 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14069 if (fixp->fx_addsy == NULL)
14072 /* If symbol SYM is in a mergeable section, relocations of the form
14073 SYM + 0 can usually be made section-relative. The mergeable data
14074 is then identified by the section offset rather than by the symbol.
14076 However, if we're generating REL LO16 relocations, the offset is split
14077 between the LO16 and parterning high part relocation. The linker will
14078 need to recalculate the complete offset in order to correctly identify
14081 The linker has traditionally not looked for the parterning high part
14082 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14083 placed anywhere. Rather than break backwards compatibility by changing
14084 this, it seems better not to force the issue, and instead keep the
14085 original symbol. This will work with either linker behavior. */
14086 if ((lo16_reloc_p (fixp->fx_r_type)
14087 || reloc_needs_lo_p (fixp->fx_r_type))
14088 && HAVE_IN_PLACE_ADDENDS
14089 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14093 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14094 to a floating-point stub. The same is true for non-R_MIPS16_26
14095 relocations against MIPS16 functions; in this case, the stub becomes
14096 the function's canonical address.
14098 Floating-point stubs are stored in unique .mips16.call.* or
14099 .mips16.fn.* sections. If a stub T for function F is in section S,
14100 the first relocation in section S must be against F; this is how the
14101 linker determines the target function. All relocations that might
14102 resolve to T must also be against F. We therefore have the following
14103 restrictions, which are given in an intentionally-redundant way:
14105 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14108 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14109 if that stub might be used.
14111 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14114 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14115 that stub might be used.
14117 There is a further restriction:
14119 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14120 on targets with in-place addends; the relocation field cannot
14121 encode the low bit.
14123 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14124 against a MIPS16 symbol.
14126 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14127 relocation against some symbol R, no relocation against R may be
14128 reduced. (Note that this deals with (2) as well as (1) because
14129 relocations against global symbols will never be reduced on ELF
14130 targets.) This approach is a little simpler than trying to detect
14131 stub sections, and gives the "all or nothing" per-symbol consistency
14132 that we have for MIPS16 symbols. */
14134 && fixp->fx_subsy == NULL
14135 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14136 || *symbol_get_tc (fixp->fx_addsy)))
14143 /* Translate internal representation of relocation info to BFD target
14147 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14149 static arelent *retval[4];
14151 bfd_reloc_code_real_type code;
14153 memset (retval, 0, sizeof(retval));
14154 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14155 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14156 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14157 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14159 if (fixp->fx_pcrel)
14161 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14163 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14164 Relocations want only the symbol offset. */
14165 reloc->addend = fixp->fx_addnumber + reloc->address;
14168 /* A gruesome hack which is a result of the gruesome gas
14169 reloc handling. What's worse, for COFF (as opposed to
14170 ECOFF), we might need yet another copy of reloc->address.
14171 See bfd_install_relocation. */
14172 reloc->addend += reloc->address;
14176 reloc->addend = fixp->fx_addnumber;
14178 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14179 entry to be used in the relocation's section offset. */
14180 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14182 reloc->address = reloc->addend;
14186 code = fixp->fx_r_type;
14188 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14189 if (reloc->howto == NULL)
14191 as_bad_where (fixp->fx_file, fixp->fx_line,
14192 _("Can not represent %s relocation in this object file format"),
14193 bfd_get_reloc_code_name (code));
14200 /* Relax a machine dependent frag. This returns the amount by which
14201 the current size of the frag should change. */
14204 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14206 if (RELAX_BRANCH_P (fragp->fr_subtype))
14208 offsetT old_var = fragp->fr_var;
14210 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14212 return fragp->fr_var - old_var;
14215 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14218 if (mips16_extended_frag (fragp, NULL, stretch))
14220 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14222 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14227 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14229 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14236 /* Convert a machine dependent frag. */
14239 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14241 if (RELAX_BRANCH_P (fragp->fr_subtype))
14244 unsigned long insn;
14248 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14250 if (target_big_endian)
14251 insn = bfd_getb32 (buf);
14253 insn = bfd_getl32 (buf);
14255 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14257 /* We generate a fixup instead of applying it right now
14258 because, if there are linker relaxations, we're going to
14259 need the relocations. */
14260 exp.X_op = O_symbol;
14261 exp.X_add_symbol = fragp->fr_symbol;
14262 exp.X_add_number = fragp->fr_offset;
14264 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14265 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14266 fixp->fx_file = fragp->fr_file;
14267 fixp->fx_line = fragp->fr_line;
14269 md_number_to_chars ((char *) buf, insn, 4);
14276 as_warn_where (fragp->fr_file, fragp->fr_line,
14277 _("relaxed out-of-range branch into a jump"));
14279 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14282 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14284 /* Reverse the branch. */
14285 switch ((insn >> 28) & 0xf)
14288 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14289 have the condition reversed by tweaking a single
14290 bit, and their opcodes all have 0x4???????. */
14291 assert ((insn & 0xf1000000) == 0x41000000);
14292 insn ^= 0x00010000;
14296 /* bltz 0x04000000 bgez 0x04010000
14297 bltzal 0x04100000 bgezal 0x04110000 */
14298 assert ((insn & 0xfc0e0000) == 0x04000000);
14299 insn ^= 0x00010000;
14303 /* beq 0x10000000 bne 0x14000000
14304 blez 0x18000000 bgtz 0x1c000000 */
14305 insn ^= 0x04000000;
14313 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14315 /* Clear the and-link bit. */
14316 assert ((insn & 0xfc1c0000) == 0x04100000);
14318 /* bltzal 0x04100000 bgezal 0x04110000
14319 bltzall 0x04120000 bgezall 0x04130000 */
14320 insn &= ~0x00100000;
14323 /* Branch over the branch (if the branch was likely) or the
14324 full jump (not likely case). Compute the offset from the
14325 current instruction to branch to. */
14326 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14330 /* How many bytes in instructions we've already emitted? */
14331 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14332 /* How many bytes in instructions from here to the end? */
14333 i = fragp->fr_var - i;
14335 /* Convert to instruction count. */
14337 /* Branch counts from the next instruction. */
14340 /* Branch over the jump. */
14341 md_number_to_chars ((char *) buf, insn, 4);
14345 md_number_to_chars ((char *) buf, 0, 4);
14348 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14350 /* beql $0, $0, 2f */
14352 /* Compute the PC offset from the current instruction to
14353 the end of the variable frag. */
14354 /* How many bytes in instructions we've already emitted? */
14355 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14356 /* How many bytes in instructions from here to the end? */
14357 i = fragp->fr_var - i;
14358 /* Convert to instruction count. */
14360 /* Don't decrement i, because we want to branch over the
14364 md_number_to_chars ((char *) buf, insn, 4);
14367 md_number_to_chars ((char *) buf, 0, 4);
14372 if (mips_pic == NO_PIC)
14375 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14376 ? 0x0c000000 : 0x08000000);
14377 exp.X_op = O_symbol;
14378 exp.X_add_symbol = fragp->fr_symbol;
14379 exp.X_add_number = fragp->fr_offset;
14381 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14382 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14383 fixp->fx_file = fragp->fr_file;
14384 fixp->fx_line = fragp->fr_line;
14386 md_number_to_chars ((char *) buf, insn, 4);
14391 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14392 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14393 exp.X_op = O_symbol;
14394 exp.X_add_symbol = fragp->fr_symbol;
14395 exp.X_add_number = fragp->fr_offset;
14397 if (fragp->fr_offset)
14399 exp.X_add_symbol = make_expr_symbol (&exp);
14400 exp.X_add_number = 0;
14403 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14404 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14405 fixp->fx_file = fragp->fr_file;
14406 fixp->fx_line = fragp->fr_line;
14408 md_number_to_chars ((char *) buf, insn, 4);
14411 if (mips_opts.isa == ISA_MIPS1)
14414 md_number_to_chars ((char *) buf, 0, 4);
14418 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14419 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14421 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14422 4, &exp, FALSE, BFD_RELOC_LO16);
14423 fixp->fx_file = fragp->fr_file;
14424 fixp->fx_line = fragp->fr_line;
14426 md_number_to_chars ((char *) buf, insn, 4);
14430 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14435 md_number_to_chars ((char *) buf, insn, 4);
14440 assert (buf == (bfd_byte *)fragp->fr_literal
14441 + fragp->fr_fix + fragp->fr_var);
14443 fragp->fr_fix += fragp->fr_var;
14448 if (RELAX_MIPS16_P (fragp->fr_subtype))
14451 const struct mips16_immed_operand *op;
14452 bfd_boolean small, ext;
14455 unsigned long insn;
14456 bfd_boolean use_extend;
14457 unsigned short extend;
14459 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14460 op = mips16_immed_operands;
14461 while (op->type != type)
14464 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14475 resolve_symbol_value (fragp->fr_symbol);
14476 val = S_GET_VALUE (fragp->fr_symbol);
14481 addr = fragp->fr_address + fragp->fr_fix;
14483 /* The rules for the base address of a PC relative reloc are
14484 complicated; see mips16_extended_frag. */
14485 if (type == 'p' || type == 'q')
14490 /* Ignore the low bit in the target, since it will be
14491 set for a text label. */
14492 if ((val & 1) != 0)
14495 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14497 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14500 addr &= ~ (addressT) ((1 << op->shift) - 1);
14503 /* Make sure the section winds up with the alignment we have
14506 record_alignment (asec, op->shift);
14510 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14511 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14512 as_warn_where (fragp->fr_file, fragp->fr_line,
14513 _("extended instruction in delay slot"));
14515 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14517 if (target_big_endian)
14518 insn = bfd_getb16 (buf);
14520 insn = bfd_getl16 (buf);
14522 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14523 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14524 small, ext, &insn, &use_extend, &extend);
14528 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14529 fragp->fr_fix += 2;
14533 md_number_to_chars ((char *) buf, insn, 2);
14534 fragp->fr_fix += 2;
14542 first = RELAX_FIRST (fragp->fr_subtype);
14543 second = RELAX_SECOND (fragp->fr_subtype);
14544 fixp = (fixS *) fragp->fr_opcode;
14546 /* Possibly emit a warning if we've chosen the longer option. */
14547 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14548 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14550 const char *msg = macro_warning (fragp->fr_subtype);
14552 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14555 /* Go through all the fixups for the first sequence. Disable them
14556 (by marking them as done) if we're going to use the second
14557 sequence instead. */
14559 && fixp->fx_frag == fragp
14560 && fixp->fx_where < fragp->fr_fix - second)
14562 if (fragp->fr_subtype & RELAX_USE_SECOND)
14564 fixp = fixp->fx_next;
14567 /* Go through the fixups for the second sequence. Disable them if
14568 we're going to use the first sequence, otherwise adjust their
14569 addresses to account for the relaxation. */
14570 while (fixp && fixp->fx_frag == fragp)
14572 if (fragp->fr_subtype & RELAX_USE_SECOND)
14573 fixp->fx_where -= first;
14576 fixp = fixp->fx_next;
14579 /* Now modify the frag contents. */
14580 if (fragp->fr_subtype & RELAX_USE_SECOND)
14584 start = fragp->fr_literal + fragp->fr_fix - first - second;
14585 memmove (start, start + first, second);
14586 fragp->fr_fix -= first;
14589 fragp->fr_fix -= second;
14595 /* This function is called after the relocs have been generated.
14596 We've been storing mips16 text labels as odd. Here we convert them
14597 back to even for the convenience of the debugger. */
14600 mips_frob_file_after_relocs (void)
14603 unsigned int count, i;
14608 syms = bfd_get_outsymbols (stdoutput);
14609 count = bfd_get_symcount (stdoutput);
14610 for (i = 0; i < count; i++, syms++)
14612 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14613 && ((*syms)->value & 1) != 0)
14615 (*syms)->value &= ~1;
14616 /* If the symbol has an odd size, it was probably computed
14617 incorrectly, so adjust that as well. */
14618 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14619 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14626 /* This function is called whenever a label is defined. It is used
14627 when handling branch delays; if a branch has a label, we assume we
14628 can not move it. */
14631 mips_define_label (symbolS *sym)
14633 segment_info_type *si = seg_info (now_seg);
14634 struct insn_label_list *l;
14636 if (free_insn_labels == NULL)
14637 l = (struct insn_label_list *) xmalloc (sizeof *l);
14640 l = free_insn_labels;
14641 free_insn_labels = l->next;
14645 l->next = si->label_list;
14646 si->label_list = l;
14649 dwarf2_emit_label (sym);
14653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14655 /* Some special processing for a MIPS ELF file. */
14658 mips_elf_final_processing (void)
14660 /* Write out the register information. */
14661 if (mips_abi != N64_ABI)
14665 s.ri_gprmask = mips_gprmask;
14666 s.ri_cprmask[0] = mips_cprmask[0];
14667 s.ri_cprmask[1] = mips_cprmask[1];
14668 s.ri_cprmask[2] = mips_cprmask[2];
14669 s.ri_cprmask[3] = mips_cprmask[3];
14670 /* The gp_value field is set by the MIPS ELF backend. */
14672 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14673 ((Elf32_External_RegInfo *)
14674 mips_regmask_frag));
14678 Elf64_Internal_RegInfo s;
14680 s.ri_gprmask = mips_gprmask;
14682 s.ri_cprmask[0] = mips_cprmask[0];
14683 s.ri_cprmask[1] = mips_cprmask[1];
14684 s.ri_cprmask[2] = mips_cprmask[2];
14685 s.ri_cprmask[3] = mips_cprmask[3];
14686 /* The gp_value field is set by the MIPS ELF backend. */
14688 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14689 ((Elf64_External_RegInfo *)
14690 mips_regmask_frag));
14693 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14694 sort of BFD interface for this. */
14695 if (mips_any_noreorder)
14696 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14697 if (mips_pic != NO_PIC)
14699 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14700 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14703 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14705 /* Set MIPS ELF flags for ASEs. */
14706 /* We may need to define a new flag for DSP ASE, and set this flag when
14707 file_ase_dsp is true. */
14708 /* Same for DSP R2. */
14709 /* We may need to define a new flag for MT ASE, and set this flag when
14710 file_ase_mt is true. */
14711 if (file_ase_mips16)
14712 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14713 #if 0 /* XXX FIXME */
14714 if (file_ase_mips3d)
14715 elf_elfheader (stdoutput)->e_flags |= ???;
14718 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14720 /* Set the MIPS ELF ABI flags. */
14721 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14722 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14723 else if (mips_abi == O64_ABI)
14724 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14725 else if (mips_abi == EABI_ABI)
14727 if (!file_mips_gp32)
14728 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14730 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14732 else if (mips_abi == N32_ABI)
14733 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14735 /* Nothing to do for N64_ABI. */
14737 if (mips_32bitmode)
14738 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14740 #if 0 /* XXX FIXME */
14741 /* 32 bit code with 64 bit FP registers. */
14742 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14743 elf_elfheader (stdoutput)->e_flags |= ???;
14747 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14749 typedef struct proc {
14751 symbolS *func_end_sym;
14752 unsigned long reg_mask;
14753 unsigned long reg_offset;
14754 unsigned long fpreg_mask;
14755 unsigned long fpreg_offset;
14756 unsigned long frame_offset;
14757 unsigned long frame_reg;
14758 unsigned long pc_reg;
14761 static procS cur_proc;
14762 static procS *cur_proc_ptr;
14763 static int numprocs;
14765 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14769 mips_nop_opcode (void)
14771 return seg_info (now_seg)->tc_segment_info_data.mips16;
14774 /* Fill in an rs_align_code fragment. This only needs to do something
14775 for MIPS16 code, where 0 is not a nop. */
14778 mips_handle_align (fragS *fragp)
14782 if (fragp->fr_type != rs_align_code)
14785 p = fragp->fr_literal + fragp->fr_fix;
14790 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14796 md_number_to_chars (p, mips16_nop_insn.insn_opcode, 2);
14802 md_obj_begin (void)
14809 /* Check for premature end, nesting errors, etc. */
14811 as_warn (_("missing .end at end of assembly"));
14820 if (*input_line_pointer == '-')
14822 ++input_line_pointer;
14825 if (!ISDIGIT (*input_line_pointer))
14826 as_bad (_("expected simple number"));
14827 if (input_line_pointer[0] == '0')
14829 if (input_line_pointer[1] == 'x')
14831 input_line_pointer += 2;
14832 while (ISXDIGIT (*input_line_pointer))
14835 val |= hex_value (*input_line_pointer++);
14837 return negative ? -val : val;
14841 ++input_line_pointer;
14842 while (ISDIGIT (*input_line_pointer))
14845 val |= *input_line_pointer++ - '0';
14847 return negative ? -val : val;
14850 if (!ISDIGIT (*input_line_pointer))
14852 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14853 *input_line_pointer, *input_line_pointer);
14854 as_warn (_("invalid number"));
14857 while (ISDIGIT (*input_line_pointer))
14860 val += *input_line_pointer++ - '0';
14862 return negative ? -val : val;
14865 /* The .file directive; just like the usual .file directive, but there
14866 is an initial number which is the ECOFF file index. In the non-ECOFF
14867 case .file implies DWARF-2. */
14870 s_mips_file (int x ATTRIBUTE_UNUSED)
14872 static int first_file_directive = 0;
14874 if (ECOFF_DEBUGGING)
14883 filename = dwarf2_directive_file (0);
14885 /* Versions of GCC up to 3.1 start files with a ".file"
14886 directive even for stabs output. Make sure that this
14887 ".file" is handled. Note that you need a version of GCC
14888 after 3.1 in order to support DWARF-2 on MIPS. */
14889 if (filename != NULL && ! first_file_directive)
14891 (void) new_logical_line (filename, -1);
14892 s_app_file_string (filename, 0);
14894 first_file_directive = 1;
14898 /* The .loc directive, implying DWARF-2. */
14901 s_mips_loc (int x ATTRIBUTE_UNUSED)
14903 if (!ECOFF_DEBUGGING)
14904 dwarf2_directive_loc (0);
14907 /* The .end directive. */
14910 s_mips_end (int x ATTRIBUTE_UNUSED)
14914 /* Following functions need their own .frame and .cprestore directives. */
14915 mips_frame_reg_valid = 0;
14916 mips_cprestore_valid = 0;
14918 if (!is_end_of_line[(unsigned char) *input_line_pointer])
14921 demand_empty_rest_of_line ();
14926 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
14927 as_warn (_(".end not in text section"));
14931 as_warn (_(".end directive without a preceding .ent directive."));
14932 demand_empty_rest_of_line ();
14938 assert (S_GET_NAME (p));
14939 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
14940 as_warn (_(".end symbol does not match .ent symbol."));
14942 if (debug_type == DEBUG_STABS)
14943 stabs_generate_asm_endfunc (S_GET_NAME (p),
14947 as_warn (_(".end directive missing or unknown symbol"));
14950 /* Create an expression to calculate the size of the function. */
14951 if (p && cur_proc_ptr)
14953 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
14954 expressionS *exp = xmalloc (sizeof (expressionS));
14957 exp->X_op = O_subtract;
14958 exp->X_add_symbol = symbol_temp_new_now ();
14959 exp->X_op_symbol = p;
14960 exp->X_add_number = 0;
14962 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14965 /* Generate a .pdr section. */
14966 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
14968 segT saved_seg = now_seg;
14969 subsegT saved_subseg = now_subseg;
14974 dot = frag_now_fix ();
14976 #ifdef md_flush_pending_output
14977 md_flush_pending_output ();
14981 subseg_set (pdr_seg, 0);
14983 /* Write the symbol. */
14984 exp.X_op = O_symbol;
14985 exp.X_add_symbol = p;
14986 exp.X_add_number = 0;
14987 emit_expr (&exp, 4);
14989 fragp = frag_more (7 * 4);
14991 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
14992 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
14993 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
14994 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
14995 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
14996 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
14997 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
14999 subseg_set (saved_seg, saved_subseg);
15001 #endif /* OBJ_ELF */
15003 cur_proc_ptr = NULL;
15006 /* The .aent and .ent directives. */
15009 s_mips_ent (int aent)
15013 symbolP = get_symbol ();
15014 if (*input_line_pointer == ',')
15015 ++input_line_pointer;
15016 SKIP_WHITESPACE ();
15017 if (ISDIGIT (*input_line_pointer)
15018 || *input_line_pointer == '-')
15021 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15022 as_warn (_(".ent or .aent not in text section."));
15024 if (!aent && cur_proc_ptr)
15025 as_warn (_("missing .end"));
15029 /* This function needs its own .frame and .cprestore directives. */
15030 mips_frame_reg_valid = 0;
15031 mips_cprestore_valid = 0;
15033 cur_proc_ptr = &cur_proc;
15034 memset (cur_proc_ptr, '\0', sizeof (procS));
15036 cur_proc_ptr->func_sym = symbolP;
15038 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15042 if (debug_type == DEBUG_STABS)
15043 stabs_generate_asm_func (S_GET_NAME (symbolP),
15044 S_GET_NAME (symbolP));
15047 demand_empty_rest_of_line ();
15050 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15051 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15052 s_mips_frame is used so that we can set the PDR information correctly.
15053 We can't use the ecoff routines because they make reference to the ecoff
15054 symbol table (in the mdebug section). */
15057 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15060 if (IS_ELF && !ECOFF_DEBUGGING)
15064 if (cur_proc_ptr == (procS *) NULL)
15066 as_warn (_(".frame outside of .ent"));
15067 demand_empty_rest_of_line ();
15071 cur_proc_ptr->frame_reg = tc_get_register (1);
15073 SKIP_WHITESPACE ();
15074 if (*input_line_pointer++ != ','
15075 || get_absolute_expression_and_terminator (&val) != ',')
15077 as_warn (_("Bad .frame directive"));
15078 --input_line_pointer;
15079 demand_empty_rest_of_line ();
15083 cur_proc_ptr->frame_offset = val;
15084 cur_proc_ptr->pc_reg = tc_get_register (0);
15086 demand_empty_rest_of_line ();
15089 #endif /* OBJ_ELF */
15093 /* The .fmask and .mask directives. If the mdebug section is present
15094 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15095 embedded targets, s_mips_mask is used so that we can set the PDR
15096 information correctly. We can't use the ecoff routines because they
15097 make reference to the ecoff symbol table (in the mdebug section). */
15100 s_mips_mask (int reg_type)
15103 if (IS_ELF && !ECOFF_DEBUGGING)
15107 if (cur_proc_ptr == (procS *) NULL)
15109 as_warn (_(".mask/.fmask outside of .ent"));
15110 demand_empty_rest_of_line ();
15114 if (get_absolute_expression_and_terminator (&mask) != ',')
15116 as_warn (_("Bad .mask/.fmask directive"));
15117 --input_line_pointer;
15118 demand_empty_rest_of_line ();
15122 off = get_absolute_expression ();
15124 if (reg_type == 'F')
15126 cur_proc_ptr->fpreg_mask = mask;
15127 cur_proc_ptr->fpreg_offset = off;
15131 cur_proc_ptr->reg_mask = mask;
15132 cur_proc_ptr->reg_offset = off;
15135 demand_empty_rest_of_line ();
15138 #endif /* OBJ_ELF */
15139 s_ignore (reg_type);
15142 /* A table describing all the processors gas knows about. Names are
15143 matched in the order listed.
15145 To ease comparison, please keep this table in the same order as
15146 gcc's mips_cpu_info_table[]. */
15147 static const struct mips_cpu_info mips_cpu_info_table[] =
15149 /* Entries for generic ISAs */
15150 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15151 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15152 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15153 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15154 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15155 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15156 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15157 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15158 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15161 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15162 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15163 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15166 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15169 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15170 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15171 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15172 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15173 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15174 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15175 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15176 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15177 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15178 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15179 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15180 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15181 /* ST Microelectronics Loongson 2E and 2F cores */
15182 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15183 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15186 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15187 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15188 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15189 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15190 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15191 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15192 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15193 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15194 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15195 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15196 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15197 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15198 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15199 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15200 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15203 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15204 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15205 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15206 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15208 /* MIPS 32 Release 2 */
15209 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15210 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15211 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15212 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15213 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15214 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15215 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15216 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15217 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15218 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15219 /* Deprecated forms of the above. */
15220 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15221 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15222 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15223 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15224 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15225 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15226 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15227 /* Deprecated forms of the above. */
15228 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15229 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15230 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15231 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15232 ISA_MIPS32R2, CPU_MIPS32R2 },
15233 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15234 ISA_MIPS32R2, CPU_MIPS32R2 },
15235 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15236 ISA_MIPS32R2, CPU_MIPS32R2 },
15237 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15238 ISA_MIPS32R2, CPU_MIPS32R2 },
15239 /* Deprecated forms of the above. */
15240 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15241 ISA_MIPS32R2, CPU_MIPS32R2 },
15242 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15243 ISA_MIPS32R2, CPU_MIPS32R2 },
15244 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15245 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15246 ISA_MIPS32R2, CPU_MIPS32R2 },
15247 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15248 ISA_MIPS32R2, CPU_MIPS32R2 },
15249 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15250 ISA_MIPS32R2, CPU_MIPS32R2 },
15251 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15252 ISA_MIPS32R2, CPU_MIPS32R2 },
15253 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15254 ISA_MIPS32R2, CPU_MIPS32R2 },
15255 /* Deprecated forms of the above. */
15256 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15257 ISA_MIPS32R2, CPU_MIPS32R2 },
15258 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15259 ISA_MIPS32R2, CPU_MIPS32R2 },
15262 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15263 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15264 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15265 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15267 /* Broadcom SB-1 CPU core */
15268 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15269 ISA_MIPS64, CPU_SB1 },
15270 /* Broadcom SB-1A CPU core */
15271 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15272 ISA_MIPS64, CPU_SB1 },
15274 /* MIPS 64 Release 2 */
15276 /* Cavium Networks Octeon CPU core */
15277 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15280 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15287 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15288 with a final "000" replaced by "k". Ignore case.
15290 Note: this function is shared between GCC and GAS. */
15293 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15295 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15296 given++, canonical++;
15298 return ((*given == 0 && *canonical == 0)
15299 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15303 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15304 CPU name. We've traditionally allowed a lot of variation here.
15306 Note: this function is shared between GCC and GAS. */
15309 mips_matching_cpu_name_p (const char *canonical, const char *given)
15311 /* First see if the name matches exactly, or with a final "000"
15312 turned into "k". */
15313 if (mips_strict_matching_cpu_name_p (canonical, given))
15316 /* If not, try comparing based on numerical designation alone.
15317 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15318 if (TOLOWER (*given) == 'r')
15320 if (!ISDIGIT (*given))
15323 /* Skip over some well-known prefixes in the canonical name,
15324 hoping to find a number there too. */
15325 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15327 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15329 else if (TOLOWER (canonical[0]) == 'r')
15332 return mips_strict_matching_cpu_name_p (canonical, given);
15336 /* Parse an option that takes the name of a processor as its argument.
15337 OPTION is the name of the option and CPU_STRING is the argument.
15338 Return the corresponding processor enumeration if the CPU_STRING is
15339 recognized, otherwise report an error and return null.
15341 A similar function exists in GCC. */
15343 static const struct mips_cpu_info *
15344 mips_parse_cpu (const char *option, const char *cpu_string)
15346 const struct mips_cpu_info *p;
15348 /* 'from-abi' selects the most compatible architecture for the given
15349 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15350 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15351 version. Look first at the -mgp options, if given, otherwise base
15352 the choice on MIPS_DEFAULT_64BIT.
15354 Treat NO_ABI like the EABIs. One reason to do this is that the
15355 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15356 architecture. This code picks MIPS I for 'mips' and MIPS III for
15357 'mips64', just as we did in the days before 'from-abi'. */
15358 if (strcasecmp (cpu_string, "from-abi") == 0)
15360 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15361 return mips_cpu_info_from_isa (ISA_MIPS1);
15363 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15364 return mips_cpu_info_from_isa (ISA_MIPS3);
15366 if (file_mips_gp32 >= 0)
15367 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15369 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15374 /* 'default' has traditionally been a no-op. Probably not very useful. */
15375 if (strcasecmp (cpu_string, "default") == 0)
15378 for (p = mips_cpu_info_table; p->name != 0; p++)
15379 if (mips_matching_cpu_name_p (p->name, cpu_string))
15382 as_bad ("Bad value (%s) for %s", cpu_string, option);
15386 /* Return the canonical processor information for ISA (a member of the
15387 ISA_MIPS* enumeration). */
15389 static const struct mips_cpu_info *
15390 mips_cpu_info_from_isa (int isa)
15394 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15395 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15396 && isa == mips_cpu_info_table[i].isa)
15397 return (&mips_cpu_info_table[i]);
15402 static const struct mips_cpu_info *
15403 mips_cpu_info_from_arch (int arch)
15407 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15408 if (arch == mips_cpu_info_table[i].cpu)
15409 return (&mips_cpu_info_table[i]);
15415 show (FILE *stream, const char *string, int *col_p, int *first_p)
15419 fprintf (stream, "%24s", "");
15424 fprintf (stream, ", ");
15428 if (*col_p + strlen (string) > 72)
15430 fprintf (stream, "\n%24s", "");
15434 fprintf (stream, "%s", string);
15435 *col_p += strlen (string);
15441 md_show_usage (FILE *stream)
15446 fprintf (stream, _("\
15448 -EB generate big endian output\n\
15449 -EL generate little endian output\n\
15450 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15451 -G NUM allow referencing objects up to NUM bytes\n\
15452 implicitly with the gp register [default 8]\n"));
15453 fprintf (stream, _("\
15454 -mips1 generate MIPS ISA I instructions\n\
15455 -mips2 generate MIPS ISA II instructions\n\
15456 -mips3 generate MIPS ISA III instructions\n\
15457 -mips4 generate MIPS ISA IV instructions\n\
15458 -mips5 generate MIPS ISA V instructions\n\
15459 -mips32 generate MIPS32 ISA instructions\n\
15460 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15461 -mips64 generate MIPS64 ISA instructions\n\
15462 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15463 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15467 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15468 show (stream, mips_cpu_info_table[i].name, &column, &first);
15469 show (stream, "from-abi", &column, &first);
15470 fputc ('\n', stream);
15472 fprintf (stream, _("\
15473 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15474 -no-mCPU don't generate code specific to CPU.\n\
15475 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15479 show (stream, "3900", &column, &first);
15480 show (stream, "4010", &column, &first);
15481 show (stream, "4100", &column, &first);
15482 show (stream, "4650", &column, &first);
15483 fputc ('\n', stream);
15485 fprintf (stream, _("\
15486 -mips16 generate mips16 instructions\n\
15487 -no-mips16 do not generate mips16 instructions\n"));
15488 fprintf (stream, _("\
15489 -msmartmips generate smartmips instructions\n\
15490 -mno-smartmips do not generate smartmips instructions\n"));
15491 fprintf (stream, _("\
15492 -mdsp generate DSP instructions\n\
15493 -mno-dsp do not generate DSP instructions\n"));
15494 fprintf (stream, _("\
15495 -mdspr2 generate DSP R2 instructions\n\
15496 -mno-dspr2 do not generate DSP R2 instructions\n"));
15497 fprintf (stream, _("\
15498 -mmt generate MT instructions\n\
15499 -mno-mt do not generate MT instructions\n"));
15500 fprintf (stream, _("\
15501 -mfix-vr4120 work around certain VR4120 errata\n\
15502 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15503 -mfix-24k insert a nop after ERET and DERET instructions\n\
15504 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15505 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15506 -msym32 assume all symbols have 32-bit values\n\
15507 -O0 remove unneeded NOPs, do not swap branches\n\
15508 -O remove unneeded NOPs and swap branches\n\
15509 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15510 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15511 fprintf (stream, _("\
15512 -mhard-float allow floating-point instructions\n\
15513 -msoft-float do not allow floating-point instructions\n\
15514 -msingle-float only allow 32-bit floating-point operations\n\
15515 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15516 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15519 fprintf (stream, _("\
15520 -KPIC, -call_shared generate SVR4 position independent code\n\
15521 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15522 -mvxworks-pic generate VxWorks position independent code\n\
15523 -non_shared do not generate code that can operate with DSOs\n\
15524 -xgot assume a 32 bit GOT\n\
15525 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15526 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15527 position dependent (non shared) code\n\
15528 -mabi=ABI create ABI conformant object file for:\n"));
15532 show (stream, "32", &column, &first);
15533 show (stream, "o64", &column, &first);
15534 show (stream, "n32", &column, &first);
15535 show (stream, "64", &column, &first);
15536 show (stream, "eabi", &column, &first);
15538 fputc ('\n', stream);
15540 fprintf (stream, _("\
15541 -32 create o32 ABI object file (default)\n\
15542 -n32 create n32 ABI object file\n\
15543 -64 create 64 ABI object file\n"));
15548 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15550 if (HAVE_64BIT_SYMBOLS)
15553 return dwarf2_format_64bit_irix;
15555 return dwarf2_format_64bit;
15559 return dwarf2_format_32bit;
15563 mips_dwarf2_addr_size (void)
15565 if (HAVE_64BIT_OBJECTS)
15571 /* Standard calling conventions leave the CFA at SP on entry. */
15573 mips_cfi_frame_initial_instructions (void)
15575 cfi_add_CFA_def_cfa_register (SP);
15579 tc_mips_regname_to_dw2regnum (char *regname)
15581 unsigned int regnum = -1;
15584 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))