1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi = NO_ABI;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls = FALSE;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared = TRUE;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32 = -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32 = -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float = 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float = 0;
266 static struct mips_set_options mips_opts =
268 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
273 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask;
280 unsigned long mips_cprmask[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa = ISA_UNKNOWN;
285 /* True if -mips16 was passed or implied by arguments passed on the
286 command line (e.g., by -march). */
287 static int file_ase_mips16;
289 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
290 || mips_opts.isa == ISA_MIPS32R2 \
291 || mips_opts.isa == ISA_MIPS64 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* True if we want to create R_MIPS_JALR for jalr $25. */
296 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
298 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
299 because there's no place for any addend, the only acceptable
300 expression is a bare symbol. */
301 #define MIPS_JALR_HINT_P(EXPR) \
302 (!HAVE_IN_PLACE_ADDENDS \
303 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
306 /* True if -mips3d was passed or implied by arguments passed on the
307 command line (e.g., by -march). */
308 static int file_ase_mips3d;
310 /* True if -mdmx was passed or implied by arguments passed on the
311 command line (e.g., by -march). */
312 static int file_ase_mdmx;
314 /* True if -msmartmips was passed or implied by arguments passed on the
315 command line (e.g., by -march). */
316 static int file_ase_smartmips;
318 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
319 || mips_opts.isa == ISA_MIPS32R2)
321 /* True if -mdsp was passed or implied by arguments passed on the
322 command line (e.g., by -march). */
323 static int file_ase_dsp;
325 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
326 || mips_opts.isa == ISA_MIPS64R2)
328 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
330 /* True if -mdspr2 was passed or implied by arguments passed on the
331 command line (e.g., by -march). */
332 static int file_ase_dspr2;
334 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
335 || mips_opts.isa == ISA_MIPS64R2)
337 /* True if -mmt was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mt;
341 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64R2)
344 /* The argument of the -march= flag. The architecture we are assembling. */
345 static int file_mips_arch = CPU_UNKNOWN;
346 static const char *mips_arch_string;
348 /* The argument of the -mtune= flag. The architecture for which we
350 static int mips_tune = CPU_UNKNOWN;
351 static const char *mips_tune_string;
353 /* True when generating 32-bit code for a 64-bit processor. */
354 static int mips_32bitmode = 0;
356 /* True if the given ABI requires 32-bit registers. */
357 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
359 /* Likewise 64-bit registers. */
360 #define ABI_NEEDS_64BIT_REGS(ABI) \
362 || (ABI) == N64_ABI \
365 /* Return true if ISA supports 64 bit wide gp registers. */
366 #define ISA_HAS_64BIT_REGS(ISA) \
367 ((ISA) == ISA_MIPS3 \
368 || (ISA) == ISA_MIPS4 \
369 || (ISA) == ISA_MIPS5 \
370 || (ISA) == ISA_MIPS64 \
371 || (ISA) == ISA_MIPS64R2)
373 /* Return true if ISA supports 64 bit wide float registers. */
374 #define ISA_HAS_64BIT_FPRS(ISA) \
375 ((ISA) == ISA_MIPS3 \
376 || (ISA) == ISA_MIPS4 \
377 || (ISA) == ISA_MIPS5 \
378 || (ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2)
382 /* Return true if ISA supports 64-bit right rotate (dror et al.)
384 #define ISA_HAS_DROR(ISA) \
385 ((ISA) == ISA_MIPS64R2)
387 /* Return true if ISA supports 32-bit right rotate (ror et al.)
389 #define ISA_HAS_ROR(ISA) \
390 ((ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS64R2 \
392 || mips_opts.ase_smartmips)
394 /* Return true if ISA supports single-precision floats in odd registers. */
395 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
396 ((ISA) == ISA_MIPS32 \
397 || (ISA) == ISA_MIPS32R2 \
398 || (ISA) == ISA_MIPS64 \
399 || (ISA) == ISA_MIPS64R2)
401 /* Return true if ISA supports move to/from high part of a 64-bit
402 floating-point register. */
403 #define ISA_HAS_MXHC1(ISA) \
404 ((ISA) == ISA_MIPS32R2 \
405 || (ISA) == ISA_MIPS64R2)
407 #define HAVE_32BIT_GPRS \
408 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
410 #define HAVE_32BIT_FPRS \
411 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
413 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
414 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
416 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
418 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
420 /* True if relocations are stored in-place. */
421 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
423 /* The ABI-derived address size. */
424 #define HAVE_64BIT_ADDRESSES \
425 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
426 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
428 /* The size of symbolic constants (i.e., expressions of the form
429 "SYMBOL" or "SYMBOL + OFFSET"). */
430 #define HAVE_32BIT_SYMBOLS \
431 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
432 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
434 /* Addresses are loaded in different ways, depending on the address size
435 in use. The n32 ABI Documentation also mandates the use of additions
436 with overflow checking, but existing implementations don't follow it. */
437 #define ADDRESS_ADD_INSN \
438 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
440 #define ADDRESS_ADDI_INSN \
441 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
443 #define ADDRESS_LOAD_INSN \
444 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
446 #define ADDRESS_STORE_INSN \
447 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
449 /* Return true if the given CPU supports the MIPS16 ASE. */
450 #define CPU_HAS_MIPS16(cpu) \
451 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
452 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
454 /* True if CPU has a dror instruction. */
455 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
457 /* True if CPU has a ror instruction. */
458 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
460 /* True if CPU has seq/sne and seqi/snei instructions. */
461 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
463 /* True if CPU does not implement the all the coprocessor insns. For these
464 CPUs only those COP insns are accepted that are explicitly marked to be
465 available on the CPU. ISA membership for COP insns is ignored. */
466 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
468 /* True if mflo and mfhi can be immediately followed by instructions
469 which write to the HI and LO registers.
471 According to MIPS specifications, MIPS ISAs I, II, and III need
472 (at least) two instructions between the reads of HI/LO and
473 instructions which write them, and later ISAs do not. Contradicting
474 the MIPS specifications, some MIPS IV processor user manuals (e.g.
475 the UM for the NEC Vr5000) document needing the instructions between
476 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
477 MIPS64 and later ISAs to have the interlocks, plus any specific
478 earlier-ISA CPUs for which CPU documentation declares that the
479 instructions are really interlocked. */
480 #define hilo_interlocks \
481 (mips_opts.isa == ISA_MIPS32 \
482 || mips_opts.isa == ISA_MIPS32R2 \
483 || mips_opts.isa == ISA_MIPS64 \
484 || mips_opts.isa == ISA_MIPS64R2 \
485 || mips_opts.arch == CPU_R4010 \
486 || mips_opts.arch == CPU_R10000 \
487 || mips_opts.arch == CPU_R12000 \
488 || mips_opts.arch == CPU_R14000 \
489 || mips_opts.arch == CPU_R16000 \
490 || mips_opts.arch == CPU_RM7000 \
491 || mips_opts.arch == CPU_VR5500 \
494 /* Whether the processor uses hardware interlocks to protect reads
495 from the GPRs after they are loaded from memory, and thus does not
496 require nops to be inserted. This applies to instructions marked
497 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
499 #define gpr_interlocks \
500 (mips_opts.isa != ISA_MIPS1 \
501 || mips_opts.arch == CPU_R3900)
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III. */
510 /* Itbl support may require additional care here. */
511 #define cop_interlocks \
512 ((mips_opts.isa != ISA_MIPS1 \
513 && mips_opts.isa != ISA_MIPS2 \
514 && mips_opts.isa != ISA_MIPS3) \
515 || mips_opts.arch == CPU_R4300 \
518 /* Whether the processor uses hardware interlocks to protect reads
519 from coprocessor registers after they are loaded from memory, and
520 thus does not require nops to be inserted. This applies to
521 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
522 requires at MIPS ISA level I. */
523 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Returns true for a (non floating-point) coprocessor instruction. Reading
530 or writing the condition code is only possible on the coprocessors and
531 these insns are not marked with INSN_COP. Thus for these insns use the
532 condition-code flags. */
533 #define COP_INSN(PINFO) \
534 (PINFO != INSN_MACRO \
535 && ((PINFO) & (FP_S | FP_D)) == 0 \
536 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
538 /* MIPS PIC level. */
540 enum mips_pic_level mips_pic;
542 /* 1 if we should generate 32 bit offsets from the $gp register in
543 SVR4_PIC mode. Currently has no meaning in other modes. */
544 static int mips_big_got = 0;
546 /* 1 if trap instructions should used for overflow rather than break
548 static int mips_trap = 0;
550 /* 1 if double width floating point constants should not be constructed
551 by assembling two single width halves into two single width floating
552 point registers which just happen to alias the double width destination
553 register. On some architectures this aliasing can be disabled by a bit
554 in the status register, and the setting of this bit cannot be determined
555 automatically at assemble time. */
556 static int mips_disable_float_construction;
558 /* Non-zero if any .set noreorder directives were used. */
560 static int mips_any_noreorder;
562 /* Non-zero if nops should be inserted when the register referenced in
563 an mfhi/mflo instruction is read in the next two instructions. */
564 static int mips_7000_hilo_fix;
566 /* The size of objects in the small data section. */
567 static unsigned int g_switch_value = 8;
568 /* Whether the -G option was used. */
569 static int g_switch_seen = 0;
574 /* If we can determine in advance that GP optimization won't be
575 possible, we can skip the relaxation stuff that tries to produce
576 GP-relative references. This makes delay slot optimization work
579 This function can only provide a guess, but it seems to work for
580 gcc output. It needs to guess right for gcc, otherwise gcc
581 will put what it thinks is a GP-relative instruction in a branch
584 I don't know if a fix is needed for the SVR4_PIC mode. I've only
585 fixed it for the non-PIC mode. KR 95/04/07 */
586 static int nopic_need_relax (symbolS *, int);
588 /* handle of the OPCODE hash table */
589 static struct hash_control *op_hash = NULL;
591 /* The opcode hash table we use for the mips16. */
592 static struct hash_control *mips16_op_hash = NULL;
594 /* This array holds the chars that always start a comment. If the
595 pre-processor is disabled, these aren't very useful */
596 const char comment_chars[] = "#";
598 /* This array holds the chars that only start a comment at the beginning of
599 a line. If the line seems to have the form '# 123 filename'
600 .line and .file directives will appear in the pre-processed output */
601 /* Note that input_file.c hand checks for '#' at the beginning of the
602 first line of the input file. This is because the compiler outputs
603 #NO_APP at the beginning of its output. */
604 /* Also note that C style comments are always supported. */
605 const char line_comment_chars[] = "#";
607 /* This array holds machine specific line separator characters. */
608 const char line_separator_chars[] = ";";
610 /* Chars that can be used to separate mant from exp in floating point nums */
611 const char EXP_CHARS[] = "eE";
613 /* Chars that mean this number is a floating point constant */
616 const char FLT_CHARS[] = "rRsSfFdDxXpP";
618 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
619 changed in read.c . Ideally it shouldn't have to know about it at all,
620 but nothing is ideal around here.
623 static char *insn_error;
625 static int auto_align = 1;
627 /* When outputting SVR4 PIC code, the assembler needs to know the
628 offset in the stack frame from which to restore the $gp register.
629 This is set by the .cprestore pseudo-op, and saved in this
631 static offsetT mips_cprestore_offset = -1;
633 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
634 more optimizations, it can use a register value instead of a memory-saved
635 offset and even an other register than $gp as global pointer. */
636 static offsetT mips_cpreturn_offset = -1;
637 static int mips_cpreturn_register = -1;
638 static int mips_gp_register = GP;
639 static int mips_gprel_offset = 0;
641 /* Whether mips_cprestore_offset has been set in the current function
642 (or whether it has already been warned about, if not). */
643 static int mips_cprestore_valid = 0;
645 /* This is the register which holds the stack frame, as set by the
646 .frame pseudo-op. This is needed to implement .cprestore. */
647 static int mips_frame_reg = SP;
649 /* Whether mips_frame_reg has been set in the current function
650 (or whether it has already been warned about, if not). */
651 static int mips_frame_reg_valid = 0;
653 /* To output NOP instructions correctly, we need to keep information
654 about the previous two instructions. */
656 /* Whether we are optimizing. The default value of 2 means to remove
657 unneeded NOPs and swap branch instructions when possible. A value
658 of 1 means to not swap branches. A value of 0 means to always
660 static int mips_optimize = 2;
662 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
663 equivalent to seeing no -g option at all. */
664 static int mips_debug = 0;
666 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
667 #define MAX_VR4130_NOPS 4
669 /* The maximum number of NOPs needed to fill delay slots. */
670 #define MAX_DELAY_NOPS 2
672 /* The maximum number of NOPs needed for any purpose. */
675 /* A list of previous instructions, with index 0 being the most recent.
676 We need to look back MAX_NOPS instructions when filling delay slots
677 or working around processor errata. We need to look back one
678 instruction further if we're thinking about using history[0] to
679 fill a branch delay slot. */
680 static struct mips_cl_insn history[1 + MAX_NOPS];
682 /* Nop instructions used by emit_nop. */
683 static struct mips_cl_insn nop_insn, mips16_nop_insn;
685 /* The appropriate nop for the current mode. */
686 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
688 /* If this is set, it points to a frag holding nop instructions which
689 were inserted before the start of a noreorder section. If those
690 nops turn out to be unnecessary, the size of the frag can be
692 static fragS *prev_nop_frag;
694 /* The number of nop instructions we created in prev_nop_frag. */
695 static int prev_nop_frag_holds;
697 /* The number of nop instructions that we know we need in
699 static int prev_nop_frag_required;
701 /* The number of instructions we've seen since prev_nop_frag. */
702 static int prev_nop_frag_since;
704 /* For ECOFF and ELF, relocations against symbols are done in two
705 parts, with a HI relocation and a LO relocation. Each relocation
706 has only 16 bits of space to store an addend. This means that in
707 order for the linker to handle carries correctly, it must be able
708 to locate both the HI and the LO relocation. This means that the
709 relocations must appear in order in the relocation table.
711 In order to implement this, we keep track of each unmatched HI
712 relocation. We then sort them so that they immediately precede the
713 corresponding LO relocation. */
718 struct mips_hi_fixup *next;
721 /* The section this fixup is in. */
725 /* The list of unmatched HI relocs. */
727 static struct mips_hi_fixup *mips_hi_fixup_list;
729 /* The frag containing the last explicit relocation operator.
730 Null if explicit relocations have not been used. */
732 static fragS *prev_reloc_op_frag;
734 /* Map normal MIPS register numbers to mips16 register numbers. */
736 #define X ILLEGAL_REG
737 static const int mips32_to_16_reg_map[] =
739 X, X, 2, 3, 4, 5, 6, 7,
740 X, X, X, X, X, X, X, X,
741 0, 1, X, X, X, X, X, X,
742 X, X, X, X, X, X, X, X
746 /* Map mips16 register numbers to normal MIPS register numbers. */
748 static const unsigned int mips16_to_32_reg_map[] =
750 16, 17, 2, 3, 4, 5, 6, 7
753 /* Classifies the kind of instructions we're interested in when
754 implementing -mfix-vr4120. */
755 enum fix_vr4120_class
763 NUM_FIX_VR4120_CLASSES
766 /* ...likewise -mfix-loongson2f-jump. */
767 static bfd_boolean mips_fix_loongson2f_jump;
769 /* ...likewise -mfix-loongson2f-nop. */
770 static bfd_boolean mips_fix_loongson2f_nop;
772 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
773 static bfd_boolean mips_fix_loongson2f;
775 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
776 there must be at least one other instruction between an instruction
777 of type X and an instruction of type Y. */
778 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
780 /* True if -mfix-vr4120 is in force. */
781 static int mips_fix_vr4120;
783 /* ...likewise -mfix-vr4130. */
784 static int mips_fix_vr4130;
786 /* ...likewise -mfix-24k. */
787 static int mips_fix_24k;
789 /* We don't relax branches by default, since this causes us to expand
790 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
791 fail to compute the offset before expanding the macro to the most
792 efficient expansion. */
794 static int mips_relax_branch;
796 /* The expansion of many macros depends on the type of symbol that
797 they refer to. For example, when generating position-dependent code,
798 a macro that refers to a symbol may have two different expansions,
799 one which uses GP-relative addresses and one which uses absolute
800 addresses. When generating SVR4-style PIC, a macro may have
801 different expansions for local and global symbols.
803 We handle these situations by generating both sequences and putting
804 them in variant frags. In position-dependent code, the first sequence
805 will be the GP-relative one and the second sequence will be the
806 absolute one. In SVR4 PIC, the first sequence will be for global
807 symbols and the second will be for local symbols.
809 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
810 SECOND are the lengths of the two sequences in bytes. These fields
811 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
812 the subtype has the following flags:
815 Set if it has been decided that we should use the second
816 sequence instead of the first.
819 Set in the first variant frag if the macro's second implementation
820 is longer than its first. This refers to the macro as a whole,
821 not an individual relaxation.
824 Set in the first variant frag if the macro appeared in a .set nomacro
825 block and if one alternative requires a warning but the other does not.
828 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
831 The frag's "opcode" points to the first fixup for relaxable code.
833 Relaxable macros are generated using a sequence such as:
835 relax_start (SYMBOL);
836 ... generate first expansion ...
838 ... generate second expansion ...
841 The code and fixups for the unwanted alternative are discarded
842 by md_convert_frag. */
843 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
845 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
846 #define RELAX_SECOND(X) ((X) & 0xff)
847 #define RELAX_USE_SECOND 0x10000
848 #define RELAX_SECOND_LONGER 0x20000
849 #define RELAX_NOMACRO 0x40000
850 #define RELAX_DELAY_SLOT 0x80000
852 /* Branch without likely bit. If label is out of range, we turn:
854 beq reg1, reg2, label
864 with the following opcode replacements:
871 bltzal <-> bgezal (with jal label instead of j label)
873 Even though keeping the delay slot instruction in the delay slot of
874 the branch would be more efficient, it would be very tricky to do
875 correctly, because we'd have to introduce a variable frag *after*
876 the delay slot instruction, and expand that instead. Let's do it
877 the easy way for now, even if the branch-not-taken case now costs
878 one additional instruction. Out-of-range branches are not supposed
879 to be common, anyway.
881 Branch likely. If label is out of range, we turn:
883 beql reg1, reg2, label
884 delay slot (annulled if branch not taken)
893 delay slot (executed only if branch taken)
896 It would be possible to generate a shorter sequence by losing the
897 likely bit, generating something like:
902 delay slot (executed only if branch taken)
914 bltzall -> bgezal (with jal label instead of j label)
915 bgezall -> bltzal (ditto)
918 but it's not clear that it would actually improve performance. */
919 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
922 | ((toofar) ? 1 : 0) \
924 | ((likely) ? 4 : 0) \
925 | ((uncond) ? 8 : 0)))
926 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
927 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
928 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
929 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
930 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
932 /* For mips16 code, we use an entirely different form of relaxation.
933 mips16 supports two versions of most instructions which take
934 immediate values: a small one which takes some small value, and a
935 larger one which takes a 16 bit value. Since branches also follow
936 this pattern, relaxing these values is required.
938 We can assemble both mips16 and normal MIPS code in a single
939 object. Therefore, we need to support this type of relaxation at
940 the same time that we support the relaxation described above. We
941 use the high bit of the subtype field to distinguish these cases.
943 The information we store for this type of relaxation is the
944 argument code found in the opcode file for this relocation, whether
945 the user explicitly requested a small or extended form, and whether
946 the relocation is in a jump or jal delay slot. That tells us the
947 size of the value, and how it should be stored. We also store
948 whether the fragment is considered to be extended or not. We also
949 store whether this is known to be a branch to a different section,
950 whether we have tried to relax this frag yet, and whether we have
951 ever extended a PC relative fragment because of a shift count. */
952 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
955 | ((small) ? 0x100 : 0) \
956 | ((ext) ? 0x200 : 0) \
957 | ((dslot) ? 0x400 : 0) \
958 | ((jal_dslot) ? 0x800 : 0))
959 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
960 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
961 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
962 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
963 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
964 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
965 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
966 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
967 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
968 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
969 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
970 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
972 /* Is the given value a sign-extended 32-bit value? */
973 #define IS_SEXT_32BIT_NUM(x) \
974 (((x) &~ (offsetT) 0x7fffffff) == 0 \
975 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
977 /* Is the given value a sign-extended 16-bit value? */
978 #define IS_SEXT_16BIT_NUM(x) \
979 (((x) &~ (offsetT) 0x7fff) == 0 \
980 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
982 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
983 #define IS_ZEXT_32BIT_NUM(x) \
984 (((x) &~ (offsetT) 0xffffffff) == 0 \
985 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
987 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
988 VALUE << SHIFT. VALUE is evaluated exactly once. */
989 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
990 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
991 | (((VALUE) & (MASK)) << (SHIFT)))
993 /* Extract bits MASK << SHIFT from STRUCT and shift them right
995 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
996 (((STRUCT) >> (SHIFT)) & (MASK))
998 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
999 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1001 include/opcode/mips.h specifies operand fields using the macros
1002 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1003 with "MIPS16OP" instead of "OP". */
1004 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1005 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1006 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1007 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1008 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1010 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1011 #define EXTRACT_OPERAND(FIELD, INSN) \
1012 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1014 EXTRACT_BITS ((INSN).insn_opcode, \
1015 MIPS16OP_MASK_##FIELD, \
1016 MIPS16OP_SH_##FIELD)
1018 /* Global variables used when generating relaxable macros. See the
1019 comment above RELAX_ENCODE for more details about how relaxation
1022 /* 0 if we're not emitting a relaxable macro.
1023 1 if we're emitting the first of the two relaxation alternatives.
1024 2 if we're emitting the second alternative. */
1027 /* The first relaxable fixup in the current frag. (In other words,
1028 the first fixup that refers to relaxable code.) */
1031 /* sizes[0] says how many bytes of the first alternative are stored in
1032 the current frag. Likewise sizes[1] for the second alternative. */
1033 unsigned int sizes[2];
1035 /* The symbol on which the choice of sequence depends. */
1039 /* Global variables used to decide whether a macro needs a warning. */
1041 /* True if the macro is in a branch delay slot. */
1042 bfd_boolean delay_slot_p;
1044 /* For relaxable macros, sizes[0] is the length of the first alternative
1045 in bytes and sizes[1] is the length of the second alternative.
1046 For non-relaxable macros, both elements give the length of the
1048 unsigned int sizes[2];
1050 /* The first variant frag for this macro. */
1052 } mips_macro_warning;
1054 /* Prototypes for static functions. */
1056 #define internalError() \
1057 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1059 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1061 static void append_insn
1062 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1063 static void mips_no_prev_insn (void);
1064 static void macro_build (expressionS *, const char *, const char *, ...);
1065 static void mips16_macro_build
1066 (expressionS *, const char *, const char *, va_list);
1067 static void load_register (int, expressionS *, int);
1068 static void macro_start (void);
1069 static void macro_end (void);
1070 static void macro (struct mips_cl_insn * ip);
1071 static void mips16_macro (struct mips_cl_insn * ip);
1072 #ifdef LOSING_COMPILER
1073 static void macro2 (struct mips_cl_insn * ip);
1075 static void mips_ip (char *str, struct mips_cl_insn * ip);
1076 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1077 static void mips16_immed
1078 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1079 unsigned long *, bfd_boolean *, unsigned short *);
1080 static size_t my_getSmallExpression
1081 (expressionS *, bfd_reloc_code_real_type *, char *);
1082 static void my_getExpression (expressionS *, char *);
1083 static void s_align (int);
1084 static void s_change_sec (int);
1085 static void s_change_section (int);
1086 static void s_cons (int);
1087 static void s_float_cons (int);
1088 static void s_mips_globl (int);
1089 static void s_option (int);
1090 static void s_mipsset (int);
1091 static void s_abicalls (int);
1092 static void s_cpload (int);
1093 static void s_cpsetup (int);
1094 static void s_cplocal (int);
1095 static void s_cprestore (int);
1096 static void s_cpreturn (int);
1097 static void s_dtprelword (int);
1098 static void s_dtpreldword (int);
1099 static void s_gpvalue (int);
1100 static void s_gpword (int);
1101 static void s_gpdword (int);
1102 static void s_cpadd (int);
1103 static void s_insn (int);
1104 static void md_obj_begin (void);
1105 static void md_obj_end (void);
1106 static void s_mips_ent (int);
1107 static void s_mips_end (int);
1108 static void s_mips_frame (int);
1109 static void s_mips_mask (int reg_type);
1110 static void s_mips_stab (int);
1111 static void s_mips_weakext (int);
1112 static void s_mips_file (int);
1113 static void s_mips_loc (int);
1114 static bfd_boolean pic_need_relax (symbolS *, asection *);
1115 static int relaxed_branch_length (fragS *, asection *, int);
1116 static int validate_mips_insn (const struct mips_opcode *);
1118 /* Table and functions used to map between CPU/ISA names, and
1119 ISA levels, and CPU numbers. */
1121 struct mips_cpu_info
1123 const char *name; /* CPU or ISA name. */
1124 int flags; /* ASEs available, or ISA flag. */
1125 int isa; /* ISA level. */
1126 int cpu; /* CPU number (default CPU if ISA). */
1129 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1130 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1131 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1132 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1133 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1134 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1135 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1137 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1138 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1139 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1143 The following pseudo-ops from the Kane and Heinrich MIPS book
1144 should be defined here, but are currently unsupported: .alias,
1145 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1147 The following pseudo-ops from the Kane and Heinrich MIPS book are
1148 specific to the type of debugging information being generated, and
1149 should be defined by the object format: .aent, .begin, .bend,
1150 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1153 The following pseudo-ops from the Kane and Heinrich MIPS book are
1154 not MIPS CPU specific, but are also not specific to the object file
1155 format. This file is probably the best place to define them, but
1156 they are not currently supported: .asm0, .endr, .lab, .struct. */
1158 static const pseudo_typeS mips_pseudo_table[] =
1160 /* MIPS specific pseudo-ops. */
1161 {"option", s_option, 0},
1162 {"set", s_mipsset, 0},
1163 {"rdata", s_change_sec, 'r'},
1164 {"sdata", s_change_sec, 's'},
1165 {"livereg", s_ignore, 0},
1166 {"abicalls", s_abicalls, 0},
1167 {"cpload", s_cpload, 0},
1168 {"cpsetup", s_cpsetup, 0},
1169 {"cplocal", s_cplocal, 0},
1170 {"cprestore", s_cprestore, 0},
1171 {"cpreturn", s_cpreturn, 0},
1172 {"dtprelword", s_dtprelword, 0},
1173 {"dtpreldword", s_dtpreldword, 0},
1174 {"gpvalue", s_gpvalue, 0},
1175 {"gpword", s_gpword, 0},
1176 {"gpdword", s_gpdword, 0},
1177 {"cpadd", s_cpadd, 0},
1178 {"insn", s_insn, 0},
1180 /* Relatively generic pseudo-ops that happen to be used on MIPS
1182 {"asciiz", stringer, 8 + 1},
1183 {"bss", s_change_sec, 'b'},
1185 {"half", s_cons, 1},
1186 {"dword", s_cons, 3},
1187 {"weakext", s_mips_weakext, 0},
1188 {"origin", s_org, 0},
1189 {"repeat", s_rept, 0},
1191 /* These pseudo-ops are defined in read.c, but must be overridden
1192 here for one reason or another. */
1193 {"align", s_align, 0},
1194 {"byte", s_cons, 0},
1195 {"data", s_change_sec, 'd'},
1196 {"double", s_float_cons, 'd'},
1197 {"float", s_float_cons, 'f'},
1198 {"globl", s_mips_globl, 0},
1199 {"global", s_mips_globl, 0},
1200 {"hword", s_cons, 1},
1202 {"long", s_cons, 2},
1203 {"octa", s_cons, 4},
1204 {"quad", s_cons, 3},
1205 {"section", s_change_section, 0},
1206 {"short", s_cons, 1},
1207 {"single", s_float_cons, 'f'},
1208 {"stabn", s_mips_stab, 'n'},
1209 {"text", s_change_sec, 't'},
1210 {"word", s_cons, 2},
1212 { "extern", ecoff_directive_extern, 0},
1217 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1219 /* These pseudo-ops should be defined by the object file format.
1220 However, a.out doesn't support them, so we have versions here. */
1221 {"aent", s_mips_ent, 1},
1222 {"bgnb", s_ignore, 0},
1223 {"end", s_mips_end, 0},
1224 {"endb", s_ignore, 0},
1225 {"ent", s_mips_ent, 0},
1226 {"file", s_mips_file, 0},
1227 {"fmask", s_mips_mask, 'F'},
1228 {"frame", s_mips_frame, 0},
1229 {"loc", s_mips_loc, 0},
1230 {"mask", s_mips_mask, 'R'},
1231 {"verstamp", s_ignore, 0},
1235 extern void pop_insert (const pseudo_typeS *);
1238 mips_pop_insert (void)
1240 pop_insert (mips_pseudo_table);
1241 if (! ECOFF_DEBUGGING)
1242 pop_insert (mips_nonecoff_pseudo_table);
1245 /* Symbols labelling the current insn. */
1247 struct insn_label_list
1249 struct insn_label_list *next;
1253 static struct insn_label_list *free_insn_labels;
1254 #define label_list tc_segment_info_data.labels
1256 static void mips_clear_insn_labels (void);
1259 mips_clear_insn_labels (void)
1261 register struct insn_label_list **pl;
1262 segment_info_type *si;
1266 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1269 si = seg_info (now_seg);
1270 *pl = si->label_list;
1271 si->label_list = NULL;
1276 static char *expr_end;
1278 /* Expressions which appear in instructions. These are set by
1281 static expressionS imm_expr;
1282 static expressionS imm2_expr;
1283 static expressionS offset_expr;
1285 /* Relocs associated with imm_expr and offset_expr. */
1287 static bfd_reloc_code_real_type imm_reloc[3]
1288 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1289 static bfd_reloc_code_real_type offset_reloc[3]
1290 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1292 /* These are set by mips16_ip if an explicit extension is used. */
1294 static bfd_boolean mips16_small, mips16_ext;
1297 /* The pdr segment for per procedure frame/regmask info. Not used for
1300 static segT pdr_seg;
1303 /* The default target format to use. */
1306 mips_target_format (void)
1308 switch (OUTPUT_FLAVOR)
1310 case bfd_target_ecoff_flavour:
1311 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1312 case bfd_target_coff_flavour:
1314 case bfd_target_elf_flavour:
1316 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1317 return (target_big_endian
1318 ? "elf32-bigmips-vxworks"
1319 : "elf32-littlemips-vxworks");
1322 /* This is traditional mips. */
1323 return (target_big_endian
1324 ? (HAVE_64BIT_OBJECTS
1325 ? "elf64-tradbigmips"
1327 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1328 : (HAVE_64BIT_OBJECTS
1329 ? "elf64-tradlittlemips"
1331 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1333 return (target_big_endian
1334 ? (HAVE_64BIT_OBJECTS
1337 ? "elf32-nbigmips" : "elf32-bigmips"))
1338 : (HAVE_64BIT_OBJECTS
1339 ? "elf64-littlemips"
1341 ? "elf32-nlittlemips" : "elf32-littlemips")));
1349 /* Return the length of instruction INSN. */
1351 static inline unsigned int
1352 insn_length (const struct mips_cl_insn *insn)
1354 if (!mips_opts.mips16)
1356 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1359 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1362 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1367 insn->use_extend = FALSE;
1369 insn->insn_opcode = mo->match;
1372 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1373 insn->fixp[i] = NULL;
1374 insn->fixed_p = (mips_opts.noreorder > 0);
1375 insn->noreorder_p = (mips_opts.noreorder > 0);
1376 insn->mips16_absolute_jump_p = 0;
1379 /* Record the current MIPS16 mode in now_seg. */
1382 mips_record_mips16_mode (void)
1384 segment_info_type *si;
1386 si = seg_info (now_seg);
1387 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1388 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1391 /* Install INSN at the location specified by its "frag" and "where" fields. */
1394 install_insn (const struct mips_cl_insn *insn)
1396 char *f = insn->frag->fr_literal + insn->where;
1397 if (!mips_opts.mips16)
1398 md_number_to_chars (f, insn->insn_opcode, 4);
1399 else if (insn->mips16_absolute_jump_p)
1401 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1402 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1406 if (insn->use_extend)
1408 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1411 md_number_to_chars (f, insn->insn_opcode, 2);
1413 mips_record_mips16_mode ();
1416 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1417 and install the opcode in the new location. */
1420 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1425 insn->where = where;
1426 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1427 if (insn->fixp[i] != NULL)
1429 insn->fixp[i]->fx_frag = frag;
1430 insn->fixp[i]->fx_where = where;
1432 install_insn (insn);
1435 /* Add INSN to the end of the output. */
1438 add_fixed_insn (struct mips_cl_insn *insn)
1440 char *f = frag_more (insn_length (insn));
1441 move_insn (insn, frag_now, f - frag_now->fr_literal);
1444 /* Start a variant frag and move INSN to the start of the variant part,
1445 marking it as fixed. The other arguments are as for frag_var. */
1448 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1449 relax_substateT subtype, symbolS *symbol, offsetT offset)
1451 frag_grow (max_chars);
1452 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1454 frag_var (rs_machine_dependent, max_chars, var,
1455 subtype, symbol, offset, NULL);
1458 /* Insert N copies of INSN into the history buffer, starting at
1459 position FIRST. Neither FIRST nor N need to be clipped. */
1462 insert_into_history (unsigned int first, unsigned int n,
1463 const struct mips_cl_insn *insn)
1465 if (mips_relax.sequence != 2)
1469 for (i = ARRAY_SIZE (history); i-- > first;)
1471 history[i] = history[i - n];
1477 /* Emit a nop instruction, recording it in the history buffer. */
1482 add_fixed_insn (NOP_INSN);
1483 insert_into_history (0, 1, NOP_INSN);
1486 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1487 the idea is to make it obvious at a glance that each errata is
1491 init_vr4120_conflicts (void)
1493 #define CONFLICT(FIRST, SECOND) \
1494 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1496 /* Errata 21 - [D]DIV[U] after [D]MACC */
1497 CONFLICT (MACC, DIV);
1498 CONFLICT (DMACC, DIV);
1500 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1501 CONFLICT (DMULT, DMULT);
1502 CONFLICT (DMULT, DMACC);
1503 CONFLICT (DMACC, DMULT);
1504 CONFLICT (DMACC, DMACC);
1506 /* Errata 24 - MT{LO,HI} after [D]MACC */
1507 CONFLICT (MACC, MTHILO);
1508 CONFLICT (DMACC, MTHILO);
1510 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1511 instruction is executed immediately after a MACC or DMACC
1512 instruction, the result of [either instruction] is incorrect." */
1513 CONFLICT (MACC, MULT);
1514 CONFLICT (MACC, DMULT);
1515 CONFLICT (DMACC, MULT);
1516 CONFLICT (DMACC, DMULT);
1518 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1519 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1520 DDIV or DDIVU instruction, the result of the MACC or
1521 DMACC instruction is incorrect.". */
1522 CONFLICT (DMULT, MACC);
1523 CONFLICT (DMULT, DMACC);
1524 CONFLICT (DIV, MACC);
1525 CONFLICT (DIV, DMACC);
1535 #define RTYPE_MASK 0x1ff00
1536 #define RTYPE_NUM 0x00100
1537 #define RTYPE_FPU 0x00200
1538 #define RTYPE_FCC 0x00400
1539 #define RTYPE_VEC 0x00800
1540 #define RTYPE_GP 0x01000
1541 #define RTYPE_CP0 0x02000
1542 #define RTYPE_PC 0x04000
1543 #define RTYPE_ACC 0x08000
1544 #define RTYPE_CCC 0x10000
1545 #define RNUM_MASK 0x000ff
1546 #define RWARN 0x80000
1548 #define GENERIC_REGISTER_NUMBERS \
1549 {"$0", RTYPE_NUM | 0}, \
1550 {"$1", RTYPE_NUM | 1}, \
1551 {"$2", RTYPE_NUM | 2}, \
1552 {"$3", RTYPE_NUM | 3}, \
1553 {"$4", RTYPE_NUM | 4}, \
1554 {"$5", RTYPE_NUM | 5}, \
1555 {"$6", RTYPE_NUM | 6}, \
1556 {"$7", RTYPE_NUM | 7}, \
1557 {"$8", RTYPE_NUM | 8}, \
1558 {"$9", RTYPE_NUM | 9}, \
1559 {"$10", RTYPE_NUM | 10}, \
1560 {"$11", RTYPE_NUM | 11}, \
1561 {"$12", RTYPE_NUM | 12}, \
1562 {"$13", RTYPE_NUM | 13}, \
1563 {"$14", RTYPE_NUM | 14}, \
1564 {"$15", RTYPE_NUM | 15}, \
1565 {"$16", RTYPE_NUM | 16}, \
1566 {"$17", RTYPE_NUM | 17}, \
1567 {"$18", RTYPE_NUM | 18}, \
1568 {"$19", RTYPE_NUM | 19}, \
1569 {"$20", RTYPE_NUM | 20}, \
1570 {"$21", RTYPE_NUM | 21}, \
1571 {"$22", RTYPE_NUM | 22}, \
1572 {"$23", RTYPE_NUM | 23}, \
1573 {"$24", RTYPE_NUM | 24}, \
1574 {"$25", RTYPE_NUM | 25}, \
1575 {"$26", RTYPE_NUM | 26}, \
1576 {"$27", RTYPE_NUM | 27}, \
1577 {"$28", RTYPE_NUM | 28}, \
1578 {"$29", RTYPE_NUM | 29}, \
1579 {"$30", RTYPE_NUM | 30}, \
1580 {"$31", RTYPE_NUM | 31}
1582 #define FPU_REGISTER_NAMES \
1583 {"$f0", RTYPE_FPU | 0}, \
1584 {"$f1", RTYPE_FPU | 1}, \
1585 {"$f2", RTYPE_FPU | 2}, \
1586 {"$f3", RTYPE_FPU | 3}, \
1587 {"$f4", RTYPE_FPU | 4}, \
1588 {"$f5", RTYPE_FPU | 5}, \
1589 {"$f6", RTYPE_FPU | 6}, \
1590 {"$f7", RTYPE_FPU | 7}, \
1591 {"$f8", RTYPE_FPU | 8}, \
1592 {"$f9", RTYPE_FPU | 9}, \
1593 {"$f10", RTYPE_FPU | 10}, \
1594 {"$f11", RTYPE_FPU | 11}, \
1595 {"$f12", RTYPE_FPU | 12}, \
1596 {"$f13", RTYPE_FPU | 13}, \
1597 {"$f14", RTYPE_FPU | 14}, \
1598 {"$f15", RTYPE_FPU | 15}, \
1599 {"$f16", RTYPE_FPU | 16}, \
1600 {"$f17", RTYPE_FPU | 17}, \
1601 {"$f18", RTYPE_FPU | 18}, \
1602 {"$f19", RTYPE_FPU | 19}, \
1603 {"$f20", RTYPE_FPU | 20}, \
1604 {"$f21", RTYPE_FPU | 21}, \
1605 {"$f22", RTYPE_FPU | 22}, \
1606 {"$f23", RTYPE_FPU | 23}, \
1607 {"$f24", RTYPE_FPU | 24}, \
1608 {"$f25", RTYPE_FPU | 25}, \
1609 {"$f26", RTYPE_FPU | 26}, \
1610 {"$f27", RTYPE_FPU | 27}, \
1611 {"$f28", RTYPE_FPU | 28}, \
1612 {"$f29", RTYPE_FPU | 29}, \
1613 {"$f30", RTYPE_FPU | 30}, \
1614 {"$f31", RTYPE_FPU | 31}
1616 #define FPU_CONDITION_CODE_NAMES \
1617 {"$fcc0", RTYPE_FCC | 0}, \
1618 {"$fcc1", RTYPE_FCC | 1}, \
1619 {"$fcc2", RTYPE_FCC | 2}, \
1620 {"$fcc3", RTYPE_FCC | 3}, \
1621 {"$fcc4", RTYPE_FCC | 4}, \
1622 {"$fcc5", RTYPE_FCC | 5}, \
1623 {"$fcc6", RTYPE_FCC | 6}, \
1624 {"$fcc7", RTYPE_FCC | 7}
1626 #define COPROC_CONDITION_CODE_NAMES \
1627 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1628 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1629 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1630 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1631 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1632 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1633 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1634 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1636 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1637 {"$a4", RTYPE_GP | 8}, \
1638 {"$a5", RTYPE_GP | 9}, \
1639 {"$a6", RTYPE_GP | 10}, \
1640 {"$a7", RTYPE_GP | 11}, \
1641 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1642 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1643 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1644 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1645 {"$t0", RTYPE_GP | 12}, \
1646 {"$t1", RTYPE_GP | 13}, \
1647 {"$t2", RTYPE_GP | 14}, \
1648 {"$t3", RTYPE_GP | 15}
1650 #define O32_SYMBOLIC_REGISTER_NAMES \
1651 {"$t0", RTYPE_GP | 8}, \
1652 {"$t1", RTYPE_GP | 9}, \
1653 {"$t2", RTYPE_GP | 10}, \
1654 {"$t3", RTYPE_GP | 11}, \
1655 {"$t4", RTYPE_GP | 12}, \
1656 {"$t5", RTYPE_GP | 13}, \
1657 {"$t6", RTYPE_GP | 14}, \
1658 {"$t7", RTYPE_GP | 15}, \
1659 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1660 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1661 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1662 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1664 /* Remaining symbolic register names */
1665 #define SYMBOLIC_REGISTER_NAMES \
1666 {"$zero", RTYPE_GP | 0}, \
1667 {"$at", RTYPE_GP | 1}, \
1668 {"$AT", RTYPE_GP | 1}, \
1669 {"$v0", RTYPE_GP | 2}, \
1670 {"$v1", RTYPE_GP | 3}, \
1671 {"$a0", RTYPE_GP | 4}, \
1672 {"$a1", RTYPE_GP | 5}, \
1673 {"$a2", RTYPE_GP | 6}, \
1674 {"$a3", RTYPE_GP | 7}, \
1675 {"$s0", RTYPE_GP | 16}, \
1676 {"$s1", RTYPE_GP | 17}, \
1677 {"$s2", RTYPE_GP | 18}, \
1678 {"$s3", RTYPE_GP | 19}, \
1679 {"$s4", RTYPE_GP | 20}, \
1680 {"$s5", RTYPE_GP | 21}, \
1681 {"$s6", RTYPE_GP | 22}, \
1682 {"$s7", RTYPE_GP | 23}, \
1683 {"$t8", RTYPE_GP | 24}, \
1684 {"$t9", RTYPE_GP | 25}, \
1685 {"$k0", RTYPE_GP | 26}, \
1686 {"$kt0", RTYPE_GP | 26}, \
1687 {"$k1", RTYPE_GP | 27}, \
1688 {"$kt1", RTYPE_GP | 27}, \
1689 {"$gp", RTYPE_GP | 28}, \
1690 {"$sp", RTYPE_GP | 29}, \
1691 {"$s8", RTYPE_GP | 30}, \
1692 {"$fp", RTYPE_GP | 30}, \
1693 {"$ra", RTYPE_GP | 31}
1695 #define MIPS16_SPECIAL_REGISTER_NAMES \
1696 {"$pc", RTYPE_PC | 0}
1698 #define MDMX_VECTOR_REGISTER_NAMES \
1699 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1700 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1701 {"$v2", RTYPE_VEC | 2}, \
1702 {"$v3", RTYPE_VEC | 3}, \
1703 {"$v4", RTYPE_VEC | 4}, \
1704 {"$v5", RTYPE_VEC | 5}, \
1705 {"$v6", RTYPE_VEC | 6}, \
1706 {"$v7", RTYPE_VEC | 7}, \
1707 {"$v8", RTYPE_VEC | 8}, \
1708 {"$v9", RTYPE_VEC | 9}, \
1709 {"$v10", RTYPE_VEC | 10}, \
1710 {"$v11", RTYPE_VEC | 11}, \
1711 {"$v12", RTYPE_VEC | 12}, \
1712 {"$v13", RTYPE_VEC | 13}, \
1713 {"$v14", RTYPE_VEC | 14}, \
1714 {"$v15", RTYPE_VEC | 15}, \
1715 {"$v16", RTYPE_VEC | 16}, \
1716 {"$v17", RTYPE_VEC | 17}, \
1717 {"$v18", RTYPE_VEC | 18}, \
1718 {"$v19", RTYPE_VEC | 19}, \
1719 {"$v20", RTYPE_VEC | 20}, \
1720 {"$v21", RTYPE_VEC | 21}, \
1721 {"$v22", RTYPE_VEC | 22}, \
1722 {"$v23", RTYPE_VEC | 23}, \
1723 {"$v24", RTYPE_VEC | 24}, \
1724 {"$v25", RTYPE_VEC | 25}, \
1725 {"$v26", RTYPE_VEC | 26}, \
1726 {"$v27", RTYPE_VEC | 27}, \
1727 {"$v28", RTYPE_VEC | 28}, \
1728 {"$v29", RTYPE_VEC | 29}, \
1729 {"$v30", RTYPE_VEC | 30}, \
1730 {"$v31", RTYPE_VEC | 31}
1732 #define MIPS_DSP_ACCUMULATOR_NAMES \
1733 {"$ac0", RTYPE_ACC | 0}, \
1734 {"$ac1", RTYPE_ACC | 1}, \
1735 {"$ac2", RTYPE_ACC | 2}, \
1736 {"$ac3", RTYPE_ACC | 3}
1738 static const struct regname reg_names[] = {
1739 GENERIC_REGISTER_NUMBERS,
1741 FPU_CONDITION_CODE_NAMES,
1742 COPROC_CONDITION_CODE_NAMES,
1744 /* The $txx registers depends on the abi,
1745 these will be added later into the symbol table from
1746 one of the tables below once mips_abi is set after
1747 parsing of arguments from the command line. */
1748 SYMBOLIC_REGISTER_NAMES,
1750 MIPS16_SPECIAL_REGISTER_NAMES,
1751 MDMX_VECTOR_REGISTER_NAMES,
1752 MIPS_DSP_ACCUMULATOR_NAMES,
1756 static const struct regname reg_names_o32[] = {
1757 O32_SYMBOLIC_REGISTER_NAMES,
1761 static const struct regname reg_names_n32n64[] = {
1762 N32N64_SYMBOLIC_REGISTER_NAMES,
1767 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1774 /* Find end of name. */
1776 if (is_name_beginner (*e))
1778 while (is_part_of_name (*e))
1781 /* Terminate name. */
1785 /* Look for a register symbol. */
1786 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1788 int r = S_GET_VALUE (symbolP);
1790 reg = r & RNUM_MASK;
1791 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1792 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1793 reg = (r & RNUM_MASK) - 2;
1795 /* Else see if this is a register defined in an itbl entry. */
1796 else if ((types & RTYPE_GP) && itbl_have_entries)
1803 if (itbl_get_reg_val (n, &r))
1804 reg = r & RNUM_MASK;
1807 /* Advance to next token if a register was recognised. */
1810 else if (types & RWARN)
1811 as_warn (_("Unrecognized register name `%s'"), *s);
1819 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1820 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1823 is_opcode_valid (const struct mips_opcode *mo)
1825 int isa = mips_opts.isa;
1828 if (mips_opts.ase_mdmx)
1830 if (mips_opts.ase_dsp)
1832 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1834 if (mips_opts.ase_dspr2)
1836 if (mips_opts.ase_mt)
1838 if (mips_opts.ase_mips3d)
1840 if (mips_opts.ase_smartmips)
1841 isa |= INSN_SMARTMIPS;
1843 /* Don't accept instructions based on the ISA if the CPU does not implement
1844 all the coprocessor insns. */
1845 if (NO_ISA_COP (mips_opts.arch)
1846 && COP_INSN (mo->pinfo))
1849 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1852 /* Check whether the instruction or macro requires single-precision or
1853 double-precision floating-point support. Note that this information is
1854 stored differently in the opcode table for insns and macros. */
1855 if (mo->pinfo == INSN_MACRO)
1857 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1858 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1862 fp_s = mo->pinfo & FP_S;
1863 fp_d = mo->pinfo & FP_D;
1866 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1869 if (fp_s && mips_opts.soft_float)
1875 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1876 selected ISA and architecture. */
1879 is_opcode_valid_16 (const struct mips_opcode *mo)
1881 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1884 /* This function is called once, at assembler startup time. It should set up
1885 all the tables, etc. that the MD part of the assembler will need. */
1890 const char *retval = NULL;
1894 if (mips_pic != NO_PIC)
1896 if (g_switch_seen && g_switch_value != 0)
1897 as_bad (_("-G may not be used in position-independent code"));
1901 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1902 as_warn (_("Could not set architecture and machine"));
1904 op_hash = hash_new ();
1906 for (i = 0; i < NUMOPCODES;)
1908 const char *name = mips_opcodes[i].name;
1910 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1913 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1914 mips_opcodes[i].name, retval);
1915 /* Probably a memory allocation problem? Give up now. */
1916 as_fatal (_("Broken assembler. No assembly attempted."));
1920 if (mips_opcodes[i].pinfo != INSN_MACRO)
1922 if (!validate_mips_insn (&mips_opcodes[i]))
1924 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1926 create_insn (&nop_insn, mips_opcodes + i);
1927 if (mips_fix_loongson2f_nop)
1928 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1929 nop_insn.fixed_p = 1;
1934 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1937 mips16_op_hash = hash_new ();
1940 while (i < bfd_mips16_num_opcodes)
1942 const char *name = mips16_opcodes[i].name;
1944 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1946 as_fatal (_("internal: can't hash `%s': %s"),
1947 mips16_opcodes[i].name, retval);
1950 if (mips16_opcodes[i].pinfo != INSN_MACRO
1951 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1952 != mips16_opcodes[i].match))
1954 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1955 mips16_opcodes[i].name, mips16_opcodes[i].args);
1958 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1960 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1961 mips16_nop_insn.fixed_p = 1;
1965 while (i < bfd_mips16_num_opcodes
1966 && strcmp (mips16_opcodes[i].name, name) == 0);
1970 as_fatal (_("Broken assembler. No assembly attempted."));
1972 /* We add all the general register names to the symbol table. This
1973 helps us detect invalid uses of them. */
1974 for (i = 0; reg_names[i].name; i++)
1975 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1976 reg_names[i].num, /* & RNUM_MASK, */
1977 &zero_address_frag));
1979 for (i = 0; reg_names_n32n64[i].name; i++)
1980 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1981 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1982 &zero_address_frag));
1984 for (i = 0; reg_names_o32[i].name; i++)
1985 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1986 reg_names_o32[i].num, /* & RNUM_MASK, */
1987 &zero_address_frag));
1989 mips_no_prev_insn ();
1992 mips_cprmask[0] = 0;
1993 mips_cprmask[1] = 0;
1994 mips_cprmask[2] = 0;
1995 mips_cprmask[3] = 0;
1997 /* set the default alignment for the text section (2**2) */
1998 record_alignment (text_section, 2);
2000 bfd_set_gp_size (stdoutput, g_switch_value);
2005 /* On a native system other than VxWorks, sections must be aligned
2006 to 16 byte boundaries. When configured for an embedded ELF
2007 target, we don't bother. */
2008 if (strncmp (TARGET_OS, "elf", 3) != 0
2009 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2011 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2012 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2013 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2016 /* Create a .reginfo section for register masks and a .mdebug
2017 section for debugging information. */
2025 subseg = now_subseg;
2027 /* The ABI says this section should be loaded so that the
2028 running program can access it. However, we don't load it
2029 if we are configured for an embedded target */
2030 flags = SEC_READONLY | SEC_DATA;
2031 if (strncmp (TARGET_OS, "elf", 3) != 0)
2032 flags |= SEC_ALLOC | SEC_LOAD;
2034 if (mips_abi != N64_ABI)
2036 sec = subseg_new (".reginfo", (subsegT) 0);
2038 bfd_set_section_flags (stdoutput, sec, flags);
2039 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2041 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2045 /* The 64-bit ABI uses a .MIPS.options section rather than
2046 .reginfo section. */
2047 sec = subseg_new (".MIPS.options", (subsegT) 0);
2048 bfd_set_section_flags (stdoutput, sec, flags);
2049 bfd_set_section_alignment (stdoutput, sec, 3);
2051 /* Set up the option header. */
2053 Elf_Internal_Options opthdr;
2056 opthdr.kind = ODK_REGINFO;
2057 opthdr.size = (sizeof (Elf_External_Options)
2058 + sizeof (Elf64_External_RegInfo));
2061 f = frag_more (sizeof (Elf_External_Options));
2062 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2063 (Elf_External_Options *) f);
2065 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2069 if (ECOFF_DEBUGGING)
2071 sec = subseg_new (".mdebug", (subsegT) 0);
2072 (void) bfd_set_section_flags (stdoutput, sec,
2073 SEC_HAS_CONTENTS | SEC_READONLY);
2074 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2076 else if (mips_flag_pdr)
2078 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2079 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2080 SEC_READONLY | SEC_RELOC
2082 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2085 subseg_set (seg, subseg);
2088 #endif /* OBJ_ELF */
2090 if (! ECOFF_DEBUGGING)
2093 if (mips_fix_vr4120)
2094 init_vr4120_conflicts ();
2100 if (! ECOFF_DEBUGGING)
2105 md_assemble (char *str)
2107 struct mips_cl_insn insn;
2108 bfd_reloc_code_real_type unused_reloc[3]
2109 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2111 imm_expr.X_op = O_absent;
2112 imm2_expr.X_op = O_absent;
2113 offset_expr.X_op = O_absent;
2114 imm_reloc[0] = BFD_RELOC_UNUSED;
2115 imm_reloc[1] = BFD_RELOC_UNUSED;
2116 imm_reloc[2] = BFD_RELOC_UNUSED;
2117 offset_reloc[0] = BFD_RELOC_UNUSED;
2118 offset_reloc[1] = BFD_RELOC_UNUSED;
2119 offset_reloc[2] = BFD_RELOC_UNUSED;
2121 if (mips_opts.mips16)
2122 mips16_ip (str, &insn);
2125 mips_ip (str, &insn);
2126 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2127 str, insn.insn_opcode));
2132 as_bad ("%s `%s'", insn_error, str);
2136 if (insn.insn_mo->pinfo == INSN_MACRO)
2139 if (mips_opts.mips16)
2140 mips16_macro (&insn);
2147 if (imm_expr.X_op != O_absent)
2148 append_insn (&insn, &imm_expr, imm_reloc);
2149 else if (offset_expr.X_op != O_absent)
2150 append_insn (&insn, &offset_expr, offset_reloc);
2152 append_insn (&insn, NULL, unused_reloc);
2156 /* Convenience functions for abstracting away the differences between
2157 MIPS16 and non-MIPS16 relocations. */
2159 static inline bfd_boolean
2160 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2164 case BFD_RELOC_MIPS16_JMP:
2165 case BFD_RELOC_MIPS16_GPREL:
2166 case BFD_RELOC_MIPS16_GOT16:
2167 case BFD_RELOC_MIPS16_CALL16:
2168 case BFD_RELOC_MIPS16_HI16_S:
2169 case BFD_RELOC_MIPS16_HI16:
2170 case BFD_RELOC_MIPS16_LO16:
2178 static inline bfd_boolean
2179 got16_reloc_p (bfd_reloc_code_real_type reloc)
2181 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2184 static inline bfd_boolean
2185 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2187 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2190 static inline bfd_boolean
2191 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2193 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2196 /* Return true if the given relocation might need a matching %lo().
2197 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2198 need a matching %lo() when applied to local symbols. */
2200 static inline bfd_boolean
2201 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2203 return (HAVE_IN_PLACE_ADDENDS
2204 && (hi16_reloc_p (reloc)
2205 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2206 all GOT16 relocations evaluate to "G". */
2207 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2210 /* Return the type of %lo() reloc needed by RELOC, given that
2211 reloc_needs_lo_p. */
2213 static inline bfd_reloc_code_real_type
2214 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2216 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2219 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2222 static inline bfd_boolean
2223 fixup_has_matching_lo_p (fixS *fixp)
2225 return (fixp->fx_next != NULL
2226 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2227 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2228 && fixp->fx_offset == fixp->fx_next->fx_offset);
2231 /* See whether instruction IP reads register REG. CLASS is the type
2235 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2236 enum mips_regclass regclass)
2238 if (regclass == MIPS16_REG)
2240 gas_assert (mips_opts.mips16);
2241 reg = mips16_to_32_reg_map[reg];
2242 regclass = MIPS_GR_REG;
2245 /* Don't report on general register ZERO, since it never changes. */
2246 if (regclass == MIPS_GR_REG && reg == ZERO)
2249 if (regclass == MIPS_FP_REG)
2251 gas_assert (! mips_opts.mips16);
2252 /* If we are called with either $f0 or $f1, we must check $f0.
2253 This is not optimal, because it will introduce an unnecessary
2254 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2255 need to distinguish reading both $f0 and $f1 or just one of
2256 them. Note that we don't have to check the other way,
2257 because there is no instruction that sets both $f0 and $f1
2258 and requires a delay. */
2259 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2260 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2261 == (reg &~ (unsigned) 1)))
2263 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2264 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2265 == (reg &~ (unsigned) 1)))
2268 else if (! mips_opts.mips16)
2270 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2271 && EXTRACT_OPERAND (RS, *ip) == reg)
2273 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2274 && EXTRACT_OPERAND (RT, *ip) == reg)
2279 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2280 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2282 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2283 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2285 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2286 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2289 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2291 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2293 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2295 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2296 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2303 /* This function returns true if modifying a register requires a
2307 reg_needs_delay (unsigned int reg)
2309 unsigned long prev_pinfo;
2311 prev_pinfo = history[0].insn_mo->pinfo;
2312 if (! mips_opts.noreorder
2313 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2314 && ! gpr_interlocks)
2315 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2316 && ! cop_interlocks)))
2318 /* A load from a coprocessor or from memory. All load delays
2319 delay the use of general register rt for one instruction. */
2320 /* Itbl support may require additional care here. */
2321 know (prev_pinfo & INSN_WRITE_GPR_T);
2322 if (reg == EXTRACT_OPERAND (RT, history[0]))
2329 /* Move all labels in insn_labels to the current insertion point. */
2332 mips_move_labels (void)
2334 segment_info_type *si = seg_info (now_seg);
2335 struct insn_label_list *l;
2338 for (l = si->label_list; l != NULL; l = l->next)
2340 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2341 symbol_set_frag (l->label, frag_now);
2342 val = (valueT) frag_now_fix ();
2343 /* mips16 text labels are stored as odd. */
2344 if (mips_opts.mips16)
2346 S_SET_VALUE (l->label, val);
2351 s_is_linkonce (symbolS *sym, segT from_seg)
2353 bfd_boolean linkonce = FALSE;
2354 segT symseg = S_GET_SEGMENT (sym);
2356 if (symseg != from_seg && !S_IS_LOCAL (sym))
2358 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2361 /* The GNU toolchain uses an extension for ELF: a section
2362 beginning with the magic string .gnu.linkonce is a
2363 linkonce section. */
2364 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2365 sizeof ".gnu.linkonce" - 1) == 0)
2372 /* Mark instruction labels in mips16 mode. This permits the linker to
2373 handle them specially, such as generating jalx instructions when
2374 needed. We also make them odd for the duration of the assembly, in
2375 order to generate the right sort of code. We will make them even
2376 in the adjust_symtab routine, while leaving them marked. This is
2377 convenient for the debugger and the disassembler. The linker knows
2378 to make them odd again. */
2381 mips16_mark_labels (void)
2383 segment_info_type *si = seg_info (now_seg);
2384 struct insn_label_list *l;
2386 if (!mips_opts.mips16)
2389 for (l = si->label_list; l != NULL; l = l->next)
2391 symbolS *label = l->label;
2393 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2395 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2397 if ((S_GET_VALUE (label) & 1) == 0
2398 /* Don't adjust the address if the label is global or weak, or
2399 in a link-once section, since we'll be emitting symbol reloc
2400 references to it which will be patched up by the linker, and
2401 the final value of the symbol may or may not be MIPS16. */
2402 && ! S_IS_WEAK (label)
2403 && ! S_IS_EXTERNAL (label)
2404 && ! s_is_linkonce (label, now_seg))
2405 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2409 /* End the current frag. Make it a variant frag and record the
2413 relax_close_frag (void)
2415 mips_macro_warning.first_frag = frag_now;
2416 frag_var (rs_machine_dependent, 0, 0,
2417 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2418 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2420 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2421 mips_relax.first_fixup = 0;
2424 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2425 See the comment above RELAX_ENCODE for more details. */
2428 relax_start (symbolS *symbol)
2430 gas_assert (mips_relax.sequence == 0);
2431 mips_relax.sequence = 1;
2432 mips_relax.symbol = symbol;
2435 /* Start generating the second version of a relaxable sequence.
2436 See the comment above RELAX_ENCODE for more details. */
2441 gas_assert (mips_relax.sequence == 1);
2442 mips_relax.sequence = 2;
2445 /* End the current relaxable sequence. */
2450 gas_assert (mips_relax.sequence == 2);
2451 relax_close_frag ();
2452 mips_relax.sequence = 0;
2455 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2456 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2457 by VR4120 errata. */
2460 classify_vr4120_insn (const char *name)
2462 if (strncmp (name, "macc", 4) == 0)
2463 return FIX_VR4120_MACC;
2464 if (strncmp (name, "dmacc", 5) == 0)
2465 return FIX_VR4120_DMACC;
2466 if (strncmp (name, "mult", 4) == 0)
2467 return FIX_VR4120_MULT;
2468 if (strncmp (name, "dmult", 5) == 0)
2469 return FIX_VR4120_DMULT;
2470 if (strstr (name, "div"))
2471 return FIX_VR4120_DIV;
2472 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2473 return FIX_VR4120_MTHILO;
2474 return NUM_FIX_VR4120_CLASSES;
2477 #define INSN_ERET 0x42000018
2478 #define INSN_DERET 0x4200001f
2480 /* Return the number of instructions that must separate INSN1 and INSN2,
2481 where INSN1 is the earlier instruction. Return the worst-case value
2482 for any INSN2 if INSN2 is null. */
2485 insns_between (const struct mips_cl_insn *insn1,
2486 const struct mips_cl_insn *insn2)
2488 unsigned long pinfo1, pinfo2;
2490 /* This function needs to know which pinfo flags are set for INSN2
2491 and which registers INSN2 uses. The former is stored in PINFO2 and
2492 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2493 will have every flag set and INSN2_USES_REG will always return true. */
2494 pinfo1 = insn1->insn_mo->pinfo;
2495 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2497 #define INSN2_USES_REG(REG, CLASS) \
2498 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2500 /* For most targets, write-after-read dependencies on the HI and LO
2501 registers must be separated by at least two instructions. */
2502 if (!hilo_interlocks)
2504 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2506 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2510 /* If we're working around r7000 errata, there must be two instructions
2511 between an mfhi or mflo and any instruction that uses the result. */
2512 if (mips_7000_hilo_fix
2513 && MF_HILO_INSN (pinfo1)
2514 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2517 /* If we're working around 24K errata, one instruction is required
2518 if an ERET or DERET is followed by a branch instruction. */
2521 if (insn1->insn_opcode == INSN_ERET
2522 || insn1->insn_opcode == INSN_DERET)
2525 || insn2->insn_opcode == INSN_ERET
2526 || insn2->insn_opcode == INSN_DERET
2527 || (insn2->insn_mo->pinfo
2528 & (INSN_UNCOND_BRANCH_DELAY
2529 | INSN_COND_BRANCH_DELAY
2530 | INSN_COND_BRANCH_LIKELY)) != 0)
2535 /* If working around VR4120 errata, check for combinations that need
2536 a single intervening instruction. */
2537 if (mips_fix_vr4120)
2539 unsigned int class1, class2;
2541 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2542 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2546 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2547 if (vr4120_conflicts[class1] & (1 << class2))
2552 if (!mips_opts.mips16)
2554 /* Check for GPR or coprocessor load delays. All such delays
2555 are on the RT register. */
2556 /* Itbl support may require additional care here. */
2557 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2558 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2560 know (pinfo1 & INSN_WRITE_GPR_T);
2561 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2565 /* Check for generic coprocessor hazards.
2567 This case is not handled very well. There is no special
2568 knowledge of CP0 handling, and the coprocessors other than
2569 the floating point unit are not distinguished at all. */
2570 /* Itbl support may require additional care here. FIXME!
2571 Need to modify this to include knowledge about
2572 user specified delays! */
2573 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2574 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2576 /* Handle cases where INSN1 writes to a known general coprocessor
2577 register. There must be a one instruction delay before INSN2
2578 if INSN2 reads that register, otherwise no delay is needed. */
2579 if (pinfo1 & INSN_WRITE_FPR_T)
2581 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2584 else if (pinfo1 & INSN_WRITE_FPR_S)
2586 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2591 /* Read-after-write dependencies on the control registers
2592 require a two-instruction gap. */
2593 if ((pinfo1 & INSN_WRITE_COND_CODE)
2594 && (pinfo2 & INSN_READ_COND_CODE))
2597 /* We don't know exactly what INSN1 does. If INSN2 is
2598 also a coprocessor instruction, assume there must be
2599 a one instruction gap. */
2600 if (pinfo2 & INSN_COP)
2605 /* Check for read-after-write dependencies on the coprocessor
2606 control registers in cases where INSN1 does not need a general
2607 coprocessor delay. This means that INSN1 is a floating point
2608 comparison instruction. */
2609 /* Itbl support may require additional care here. */
2610 else if (!cop_interlocks
2611 && (pinfo1 & INSN_WRITE_COND_CODE)
2612 && (pinfo2 & INSN_READ_COND_CODE))
2616 #undef INSN2_USES_REG
2621 /* Return the number of nops that would be needed to work around the
2622 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2623 the MAX_VR4130_NOPS instructions described by HIST. */
2626 nops_for_vr4130 (const struct mips_cl_insn *hist,
2627 const struct mips_cl_insn *insn)
2631 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2632 are not affected by the errata. */
2634 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2635 || strcmp (insn->insn_mo->name, "mtlo") == 0
2636 || strcmp (insn->insn_mo->name, "mthi") == 0))
2639 /* Search for the first MFLO or MFHI. */
2640 for (i = 0; i < MAX_VR4130_NOPS; i++)
2641 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2643 /* Extract the destination register. */
2644 if (mips_opts.mips16)
2645 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2647 reg = EXTRACT_OPERAND (RD, hist[i]);
2649 /* No nops are needed if INSN reads that register. */
2650 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2653 /* ...or if any of the intervening instructions do. */
2654 for (j = 0; j < i; j++)
2655 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2658 return MAX_VR4130_NOPS - i;
2663 /* Return the number of nops that would be needed if instruction INSN
2664 immediately followed the MAX_NOPS instructions given by HIST,
2665 where HIST[0] is the most recent instruction. If INSN is null,
2666 return the worse-case number of nops for any instruction. */
2669 nops_for_insn (const struct mips_cl_insn *hist,
2670 const struct mips_cl_insn *insn)
2672 int i, nops, tmp_nops;
2675 for (i = 0; i < MAX_DELAY_NOPS; i++)
2677 tmp_nops = insns_between (hist + i, insn) - i;
2678 if (tmp_nops > nops)
2682 if (mips_fix_vr4130)
2684 tmp_nops = nops_for_vr4130 (hist, insn);
2685 if (tmp_nops > nops)
2692 /* The variable arguments provide NUM_INSNS extra instructions that
2693 might be added to HIST. Return the largest number of nops that
2694 would be needed after the extended sequence. */
2697 nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...)
2700 struct mips_cl_insn buffer[MAX_NOPS];
2701 struct mips_cl_insn *cursor;
2704 va_start (args, hist);
2705 cursor = buffer + num_insns;
2706 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2707 while (cursor > buffer)
2708 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2710 nops = nops_for_insn (buffer, NULL);
2715 /* Like nops_for_insn, but if INSN is a branch, take into account the
2716 worst-case delay for the branch target. */
2719 nops_for_insn_or_target (const struct mips_cl_insn *hist,
2720 const struct mips_cl_insn *insn)
2724 nops = nops_for_insn (hist, insn);
2725 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2726 | INSN_COND_BRANCH_DELAY
2727 | INSN_COND_BRANCH_LIKELY))
2729 tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN);
2730 if (tmp_nops > nops)
2733 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2735 tmp_nops = nops_for_sequence (1, hist, insn);
2736 if (tmp_nops > nops)
2742 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2745 fix_loongson2f_nop (struct mips_cl_insn * ip)
2747 if (strcmp (ip->insn_mo->name, "nop") == 0)
2748 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2751 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2752 jr target pc &= 'hffff_ffff_cfff_ffff. */
2755 fix_loongson2f_jump (struct mips_cl_insn * ip)
2757 if (strcmp (ip->insn_mo->name, "j") == 0
2758 || strcmp (ip->insn_mo->name, "jr") == 0
2759 || strcmp (ip->insn_mo->name, "jalr") == 0)
2767 sreg = EXTRACT_OPERAND (RS, *ip);
2768 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
2771 ep.X_op = O_constant;
2772 ep.X_add_number = 0xcfff0000;
2773 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
2774 ep.X_add_number = 0xffff;
2775 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
2776 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
2781 fix_loongson2f (struct mips_cl_insn * ip)
2783 if (mips_fix_loongson2f_nop)
2784 fix_loongson2f_nop (ip);
2786 if (mips_fix_loongson2f_jump)
2787 fix_loongson2f_jump (ip);
2790 /* Output an instruction. IP is the instruction information.
2791 ADDRESS_EXPR is an operand of the instruction to be used with
2795 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2796 bfd_reloc_code_real_type *reloc_type)
2798 unsigned long prev_pinfo, pinfo;
2799 relax_stateT prev_insn_frag_type = 0;
2800 bfd_boolean relaxed_branch = FALSE;
2801 segment_info_type *si = seg_info (now_seg);
2803 if (mips_fix_loongson2f)
2804 fix_loongson2f (ip);
2806 /* Mark instruction labels in mips16 mode. */
2807 mips16_mark_labels ();
2809 prev_pinfo = history[0].insn_mo->pinfo;
2810 pinfo = ip->insn_mo->pinfo;
2812 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2814 /* There are a lot of optimizations we could do that we don't.
2815 In particular, we do not, in general, reorder instructions.
2816 If you use gcc with optimization, it will reorder
2817 instructions and generally do much more optimization then we
2818 do here; repeating all that work in the assembler would only
2819 benefit hand written assembly code, and does not seem worth
2821 int nops = (mips_optimize == 0
2822 ? nops_for_insn (history, NULL)
2823 : nops_for_insn_or_target (history, ip));
2827 unsigned long old_frag_offset;
2830 old_frag = frag_now;
2831 old_frag_offset = frag_now_fix ();
2833 for (i = 0; i < nops; i++)
2838 listing_prev_line ();
2839 /* We may be at the start of a variant frag. In case we
2840 are, make sure there is enough space for the frag
2841 after the frags created by listing_prev_line. The
2842 argument to frag_grow here must be at least as large
2843 as the argument to all other calls to frag_grow in
2844 this file. We don't have to worry about being in the
2845 middle of a variant frag, because the variants insert
2846 all needed nop instructions themselves. */
2850 mips_move_labels ();
2852 #ifndef NO_ECOFF_DEBUGGING
2853 if (ECOFF_DEBUGGING)
2854 ecoff_fix_loc (old_frag, old_frag_offset);
2858 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2860 /* Work out how many nops in prev_nop_frag are needed by IP. */
2861 int nops = nops_for_insn_or_target (history, ip);
2862 gas_assert (nops <= prev_nop_frag_holds);
2864 /* Enforce NOPS as a minimum. */
2865 if (nops > prev_nop_frag_required)
2866 prev_nop_frag_required = nops;
2868 if (prev_nop_frag_holds == prev_nop_frag_required)
2870 /* Settle for the current number of nops. Update the history
2871 accordingly (for the benefit of any future .set reorder code). */
2872 prev_nop_frag = NULL;
2873 insert_into_history (prev_nop_frag_since,
2874 prev_nop_frag_holds, NOP_INSN);
2878 /* Allow this instruction to replace one of the nops that was
2879 tentatively added to prev_nop_frag. */
2880 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2881 prev_nop_frag_holds--;
2882 prev_nop_frag_since++;
2887 /* The value passed to dwarf2_emit_insn is the distance between
2888 the beginning of the current instruction and the address that
2889 should be recorded in the debug tables. For MIPS16 debug info
2890 we want to use ISA-encoded addresses, so we pass -1 for an
2891 address higher by one than the current. */
2892 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2895 /* Record the frag type before frag_var. */
2896 if (history[0].frag)
2897 prev_insn_frag_type = history[0].frag->fr_type;
2900 && *reloc_type == BFD_RELOC_16_PCREL_S2
2901 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2902 || pinfo & INSN_COND_BRANCH_LIKELY)
2903 && mips_relax_branch
2904 /* Don't try branch relaxation within .set nomacro, or within
2905 .set noat if we use $at for PIC computations. If it turns
2906 out that the branch was out-of-range, we'll get an error. */
2907 && !mips_opts.warn_about_macros
2908 && (mips_opts.at || mips_pic == NO_PIC)
2909 && !mips_opts.mips16)
2911 relaxed_branch = TRUE;
2912 add_relaxed_insn (ip, (relaxed_branch_length
2914 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2915 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2918 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2919 pinfo & INSN_COND_BRANCH_LIKELY,
2920 pinfo & INSN_WRITE_GPR_31,
2922 address_expr->X_add_symbol,
2923 address_expr->X_add_number);
2924 *reloc_type = BFD_RELOC_UNUSED;
2926 else if (*reloc_type > BFD_RELOC_UNUSED)
2928 /* We need to set up a variant frag. */
2929 gas_assert (mips_opts.mips16 && address_expr != NULL);
2930 add_relaxed_insn (ip, 4, 0,
2932 (*reloc_type - BFD_RELOC_UNUSED,
2933 mips16_small, mips16_ext,
2934 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2935 history[0].mips16_absolute_jump_p),
2936 make_expr_symbol (address_expr), 0);
2938 else if (mips_opts.mips16
2940 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2942 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2943 /* Make sure there is enough room to swap this instruction with
2944 a following jump instruction. */
2946 add_fixed_insn (ip);
2950 if (mips_opts.mips16
2951 && mips_opts.noreorder
2952 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2953 as_warn (_("extended instruction in delay slot"));
2955 if (mips_relax.sequence)
2957 /* If we've reached the end of this frag, turn it into a variant
2958 frag and record the information for the instructions we've
2960 if (frag_room () < 4)
2961 relax_close_frag ();
2962 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2965 if (mips_relax.sequence != 2)
2966 mips_macro_warning.sizes[0] += 4;
2967 if (mips_relax.sequence != 1)
2968 mips_macro_warning.sizes[1] += 4;
2970 if (mips_opts.mips16)
2973 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2975 add_fixed_insn (ip);
2978 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2980 if (address_expr->X_op == O_constant)
2984 switch (*reloc_type)
2987 ip->insn_opcode |= address_expr->X_add_number;
2990 case BFD_RELOC_MIPS_HIGHEST:
2991 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2992 ip->insn_opcode |= tmp & 0xffff;
2995 case BFD_RELOC_MIPS_HIGHER:
2996 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2997 ip->insn_opcode |= tmp & 0xffff;
3000 case BFD_RELOC_HI16_S:
3001 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3002 ip->insn_opcode |= tmp & 0xffff;
3005 case BFD_RELOC_HI16:
3006 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3009 case BFD_RELOC_UNUSED:
3010 case BFD_RELOC_LO16:
3011 case BFD_RELOC_MIPS_GOT_DISP:
3012 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3015 case BFD_RELOC_MIPS_JMP:
3016 if ((address_expr->X_add_number & 3) != 0)
3017 as_bad (_("jump to misaligned address (0x%lx)"),
3018 (unsigned long) address_expr->X_add_number);
3019 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3022 case BFD_RELOC_MIPS16_JMP:
3023 if ((address_expr->X_add_number & 3) != 0)
3024 as_bad (_("jump to misaligned address (0x%lx)"),
3025 (unsigned long) address_expr->X_add_number);
3027 (((address_expr->X_add_number & 0x7c0000) << 3)
3028 | ((address_expr->X_add_number & 0xf800000) >> 7)
3029 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3032 case BFD_RELOC_16_PCREL_S2:
3033 if ((address_expr->X_add_number & 3) != 0)
3034 as_bad (_("branch to misaligned address (0x%lx)"),
3035 (unsigned long) address_expr->X_add_number);
3036 if (mips_relax_branch)
3038 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3039 as_bad (_("branch address range overflow (0x%lx)"),
3040 (unsigned long) address_expr->X_add_number);
3041 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3048 else if (*reloc_type < BFD_RELOC_UNUSED)
3051 reloc_howto_type *howto;
3054 /* In a compound relocation, it is the final (outermost)
3055 operator that determines the relocated field. */
3056 for (i = 1; i < 3; i++)
3057 if (reloc_type[i] == BFD_RELOC_UNUSED)
3060 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3063 /* To reproduce this failure try assembling gas/testsuites/
3064 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3066 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3067 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3070 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3071 bfd_get_reloc_size (howto),
3073 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3076 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3077 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3078 && ip->fixp[0]->fx_addsy)
3079 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3081 /* These relocations can have an addend that won't fit in
3082 4 octets for 64bit assembly. */
3084 && ! howto->partial_inplace
3085 && (reloc_type[0] == BFD_RELOC_16
3086 || reloc_type[0] == BFD_RELOC_32
3087 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3088 || reloc_type[0] == BFD_RELOC_GPREL16
3089 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3090 || reloc_type[0] == BFD_RELOC_GPREL32
3091 || reloc_type[0] == BFD_RELOC_64
3092 || reloc_type[0] == BFD_RELOC_CTOR
3093 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3094 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3095 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3096 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3097 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3098 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3099 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3100 || hi16_reloc_p (reloc_type[0])
3101 || lo16_reloc_p (reloc_type[0])))
3102 ip->fixp[0]->fx_no_overflow = 1;
3104 if (mips_relax.sequence)
3106 if (mips_relax.first_fixup == 0)
3107 mips_relax.first_fixup = ip->fixp[0];
3109 else if (reloc_needs_lo_p (*reloc_type))
3111 struct mips_hi_fixup *hi_fixup;
3113 /* Reuse the last entry if it already has a matching %lo. */
3114 hi_fixup = mips_hi_fixup_list;
3116 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3118 hi_fixup = ((struct mips_hi_fixup *)
3119 xmalloc (sizeof (struct mips_hi_fixup)));
3120 hi_fixup->next = mips_hi_fixup_list;
3121 mips_hi_fixup_list = hi_fixup;
3123 hi_fixup->fixp = ip->fixp[0];
3124 hi_fixup->seg = now_seg;
3127 /* Add fixups for the second and third relocations, if given.
3128 Note that the ABI allows the second relocation to be
3129 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3130 moment we only use RSS_UNDEF, but we could add support
3131 for the others if it ever becomes necessary. */
3132 for (i = 1; i < 3; i++)
3133 if (reloc_type[i] != BFD_RELOC_UNUSED)
3135 ip->fixp[i] = fix_new (ip->frag, ip->where,
3136 ip->fixp[0]->fx_size, NULL, 0,
3137 FALSE, reloc_type[i]);
3139 /* Use fx_tcbit to mark compound relocs. */
3140 ip->fixp[0]->fx_tcbit = 1;
3141 ip->fixp[i]->fx_tcbit = 1;
3147 /* Update the register mask information. */
3148 if (! mips_opts.mips16)
3150 if (pinfo & INSN_WRITE_GPR_D)
3151 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3152 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3153 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3154 if (pinfo & INSN_READ_GPR_S)
3155 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3156 if (pinfo & INSN_WRITE_GPR_31)
3157 mips_gprmask |= 1 << RA;
3158 if (pinfo & INSN_WRITE_FPR_D)
3159 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3160 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3161 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3162 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3163 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3164 if ((pinfo & INSN_READ_FPR_R) != 0)
3165 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3166 if (pinfo & INSN_COP)
3168 /* We don't keep enough information to sort these cases out.
3169 The itbl support does keep this information however, although
3170 we currently don't support itbl fprmats as part of the cop
3171 instruction. May want to add this support in the future. */
3173 /* Never set the bit for $0, which is always zero. */
3174 mips_gprmask &= ~1 << 0;
3178 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3179 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3180 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3181 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3182 if (pinfo & MIPS16_INSN_WRITE_Z)
3183 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3184 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3185 mips_gprmask |= 1 << TREG;
3186 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3187 mips_gprmask |= 1 << SP;
3188 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3189 mips_gprmask |= 1 << RA;
3190 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3191 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3192 if (pinfo & MIPS16_INSN_READ_Z)
3193 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3194 if (pinfo & MIPS16_INSN_READ_GPR_X)
3195 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3198 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3200 /* Filling the branch delay slot is more complex. We try to
3201 switch the branch with the previous instruction, which we can
3202 do if the previous instruction does not set up a condition
3203 that the branch tests and if the branch is not itself the
3204 target of any branch. */
3205 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3206 || (pinfo & INSN_COND_BRANCH_DELAY))
3208 if (mips_optimize < 2
3209 /* If we have seen .set volatile or .set nomove, don't
3211 || mips_opts.nomove != 0
3212 /* We can't swap if the previous instruction's position
3214 || history[0].fixed_p
3215 /* If the previous previous insn was in a .set
3216 noreorder, we can't swap. Actually, the MIPS
3217 assembler will swap in this situation. However, gcc
3218 configured -with-gnu-as will generate code like
3224 in which we can not swap the bne and INSN. If gcc is
3225 not configured -with-gnu-as, it does not output the
3227 || history[1].noreorder_p
3228 /* If the branch is itself the target of a branch, we
3229 can not swap. We cheat on this; all we check for is
3230 whether there is a label on this instruction. If
3231 there are any branches to anything other than a
3232 label, users must use .set noreorder. */
3233 || si->label_list != NULL
3234 /* If the previous instruction is in a variant frag
3235 other than this branch's one, we cannot do the swap.
3236 This does not apply to the mips16, which uses variant
3237 frags for different purposes. */
3238 || (! mips_opts.mips16
3239 && prev_insn_frag_type == rs_machine_dependent)
3240 /* Check for conflicts between the branch and the instructions
3241 before the candidate delay slot. */
3242 || nops_for_insn (history + 1, ip) > 0
3243 /* Check for conflicts between the swapped sequence and the
3244 target of the branch. */
3245 || nops_for_sequence (2, history + 1, ip, history) > 0
3246 /* We do not swap with a trap instruction, since it
3247 complicates trap handlers to have the trap
3248 instruction be in a delay slot. */
3249 || (prev_pinfo & INSN_TRAP)
3250 /* If the branch reads a register that the previous
3251 instruction sets, we can not swap. */
3252 || (! mips_opts.mips16
3253 && (prev_pinfo & INSN_WRITE_GPR_T)
3254 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3256 || (! mips_opts.mips16
3257 && (prev_pinfo & INSN_WRITE_GPR_D)
3258 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3260 || (mips_opts.mips16
3261 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3263 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3265 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3267 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3269 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3271 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3273 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3274 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3275 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3276 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3277 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3278 && insn_uses_reg (ip,
3279 MIPS16OP_EXTRACT_REG32R
3280 (history[0].insn_opcode),
3282 /* If the branch writes a register that the previous
3283 instruction sets, we can not swap (we know that
3284 branches write only to RD or to $31). */
3285 || (! mips_opts.mips16
3286 && (prev_pinfo & INSN_WRITE_GPR_T)
3287 && (((pinfo & INSN_WRITE_GPR_D)
3288 && (EXTRACT_OPERAND (RT, history[0])
3289 == EXTRACT_OPERAND (RD, *ip)))
3290 || ((pinfo & INSN_WRITE_GPR_31)
3291 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3292 || (! mips_opts.mips16
3293 && (prev_pinfo & INSN_WRITE_GPR_D)
3294 && (((pinfo & INSN_WRITE_GPR_D)
3295 && (EXTRACT_OPERAND (RD, history[0])
3296 == EXTRACT_OPERAND (RD, *ip)))
3297 || ((pinfo & INSN_WRITE_GPR_31)
3298 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3299 || (mips_opts.mips16
3300 && (pinfo & MIPS16_INSN_WRITE_31)
3301 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3302 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3303 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3305 /* If the branch writes a register that the previous
3306 instruction reads, we can not swap (we know that
3307 branches only write to RD or to $31). */
3308 || (! mips_opts.mips16
3309 && (pinfo & INSN_WRITE_GPR_D)
3310 && insn_uses_reg (&history[0],
3311 EXTRACT_OPERAND (RD, *ip),
3313 || (! mips_opts.mips16
3314 && (pinfo & INSN_WRITE_GPR_31)
3315 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3316 || (mips_opts.mips16
3317 && (pinfo & MIPS16_INSN_WRITE_31)
3318 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3319 /* If one instruction sets a condition code and the
3320 other one uses a condition code, we can not swap. */
3321 || ((pinfo & INSN_READ_COND_CODE)
3322 && (prev_pinfo & INSN_WRITE_COND_CODE))
3323 || ((pinfo & INSN_WRITE_COND_CODE)
3324 && (prev_pinfo & INSN_READ_COND_CODE))
3325 /* If the previous instruction uses the PC, we can not
3327 || (mips_opts.mips16
3328 && (prev_pinfo & MIPS16_INSN_READ_PC))
3329 /* If the previous instruction had a fixup in mips16
3330 mode, we can not swap. This normally means that the
3331 previous instruction was a 4 byte branch anyhow. */
3332 || (mips_opts.mips16 && history[0].fixp[0])
3333 /* If the previous instruction is a sync, sync.l, or
3334 sync.p, we can not swap. */
3335 || (prev_pinfo & INSN_SYNC)
3336 /* If the previous instruction is an ERET or
3337 DERET, avoid the swap. */
3338 || (history[0].insn_opcode == INSN_ERET)
3339 || (history[0].insn_opcode == INSN_DERET))
3341 if (mips_opts.mips16
3342 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3343 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3344 && ISA_SUPPORTS_MIPS16E)
3346 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3347 ip->insn_opcode |= 0x0080;
3349 insert_into_history (0, 1, ip);
3353 /* We could do even better for unconditional branches to
3354 portions of this object file; we could pick up the
3355 instruction at the destination, put it in the delay
3356 slot, and bump the destination address. */
3357 insert_into_history (0, 1, ip);
3361 if (mips_relax.sequence)
3362 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3366 /* It looks like we can actually do the swap. */
3367 struct mips_cl_insn delay = history[0];
3368 if (mips_opts.mips16)
3370 know (delay.frag == ip->frag);
3371 move_insn (ip, delay.frag, delay.where);
3372 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3374 else if (relaxed_branch)
3376 /* Add the delay slot instruction to the end of the
3377 current frag and shrink the fixed part of the
3378 original frag. If the branch occupies the tail of
3379 the latter, move it backwards to cover the gap. */
3380 delay.frag->fr_fix -= 4;
3381 if (delay.frag == ip->frag)
3382 move_insn (ip, ip->frag, ip->where - 4);
3383 add_fixed_insn (&delay);
3387 move_insn (&delay, ip->frag, ip->where);
3388 move_insn (ip, history[0].frag, history[0].where);
3392 insert_into_history (0, 1, &delay);
3395 /* If that was an unconditional branch, forget the previous
3396 insn information. */
3397 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3399 mips_no_prev_insn ();
3402 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3404 /* We don't yet optimize a branch likely. What we should do
3405 is look at the target, copy the instruction found there
3406 into the delay slot, and increment the branch to jump to
3407 the next instruction. */
3408 insert_into_history (0, 1, ip);
3412 insert_into_history (0, 1, ip);
3415 insert_into_history (0, 1, ip);
3417 /* We just output an insn, so the next one doesn't have a label. */
3418 mips_clear_insn_labels ();
3421 /* Forget that there was any previous instruction or label. */
3424 mips_no_prev_insn (void)
3426 prev_nop_frag = NULL;
3427 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3428 mips_clear_insn_labels ();
3431 /* This function must be called before we emit something other than
3432 instructions. It is like mips_no_prev_insn except that it inserts
3433 any NOPS that might be needed by previous instructions. */
3436 mips_emit_delays (void)
3438 if (! mips_opts.noreorder)
3440 int nops = nops_for_insn (history, NULL);
3444 add_fixed_insn (NOP_INSN);
3445 mips_move_labels ();
3448 mips_no_prev_insn ();
3451 /* Start a (possibly nested) noreorder block. */
3454 start_noreorder (void)
3456 if (mips_opts.noreorder == 0)
3461 /* None of the instructions before the .set noreorder can be moved. */
3462 for (i = 0; i < ARRAY_SIZE (history); i++)
3463 history[i].fixed_p = 1;
3465 /* Insert any nops that might be needed between the .set noreorder
3466 block and the previous instructions. We will later remove any
3467 nops that turn out not to be needed. */
3468 nops = nops_for_insn (history, NULL);
3471 if (mips_optimize != 0)
3473 /* Record the frag which holds the nop instructions, so
3474 that we can remove them if we don't need them. */
3475 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3476 prev_nop_frag = frag_now;
3477 prev_nop_frag_holds = nops;
3478 prev_nop_frag_required = 0;
3479 prev_nop_frag_since = 0;
3482 for (; nops > 0; --nops)
3483 add_fixed_insn (NOP_INSN);
3485 /* Move on to a new frag, so that it is safe to simply
3486 decrease the size of prev_nop_frag. */
3487 frag_wane (frag_now);
3489 mips_move_labels ();
3491 mips16_mark_labels ();
3492 mips_clear_insn_labels ();
3494 mips_opts.noreorder++;
3495 mips_any_noreorder = 1;
3498 /* End a nested noreorder block. */
3501 end_noreorder (void)
3504 mips_opts.noreorder--;
3505 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3507 /* Commit to inserting prev_nop_frag_required nops and go back to
3508 handling nop insertion the .set reorder way. */
3509 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3510 * (mips_opts.mips16 ? 2 : 4));
3511 insert_into_history (prev_nop_frag_since,
3512 prev_nop_frag_required, NOP_INSN);
3513 prev_nop_frag = NULL;
3517 /* Set up global variables for the start of a new macro. */
3522 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3523 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3524 && (history[0].insn_mo->pinfo
3525 & (INSN_UNCOND_BRANCH_DELAY
3526 | INSN_COND_BRANCH_DELAY
3527 | INSN_COND_BRANCH_LIKELY)) != 0);
3530 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3531 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3532 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3535 macro_warning (relax_substateT subtype)
3537 if (subtype & RELAX_DELAY_SLOT)
3538 return _("Macro instruction expanded into multiple instructions"
3539 " in a branch delay slot");
3540 else if (subtype & RELAX_NOMACRO)
3541 return _("Macro instruction expanded into multiple instructions");
3546 /* Finish up a macro. Emit warnings as appropriate. */
3551 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3553 relax_substateT subtype;
3555 /* Set up the relaxation warning flags. */
3557 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3558 subtype |= RELAX_SECOND_LONGER;
3559 if (mips_opts.warn_about_macros)
3560 subtype |= RELAX_NOMACRO;
3561 if (mips_macro_warning.delay_slot_p)
3562 subtype |= RELAX_DELAY_SLOT;
3564 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3566 /* Either the macro has a single implementation or both
3567 implementations are longer than 4 bytes. Emit the
3569 const char *msg = macro_warning (subtype);
3571 as_warn ("%s", msg);
3575 /* One implementation might need a warning but the other
3576 definitely doesn't. */
3577 mips_macro_warning.first_frag->fr_subtype |= subtype;
3582 /* Read a macro's relocation codes from *ARGS and store them in *R.
3583 The first argument in *ARGS will be either the code for a single
3584 relocation or -1 followed by the three codes that make up a
3585 composite relocation. */
3588 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3592 next = va_arg (*args, int);
3594 r[0] = (bfd_reloc_code_real_type) next;
3596 for (i = 0; i < 3; i++)
3597 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3600 /* Build an instruction created by a macro expansion. This is passed
3601 a pointer to the count of instructions created so far, an
3602 expression, the name of the instruction to build, an operand format
3603 string, and corresponding arguments. */
3606 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3608 const struct mips_opcode *mo;
3609 struct mips_cl_insn insn;
3610 bfd_reloc_code_real_type r[3];
3613 va_start (args, fmt);
3615 if (mips_opts.mips16)
3617 mips16_macro_build (ep, name, fmt, args);
3622 r[0] = BFD_RELOC_UNUSED;
3623 r[1] = BFD_RELOC_UNUSED;
3624 r[2] = BFD_RELOC_UNUSED;
3625 mo = (struct mips_opcode *) hash_find (op_hash, name);
3627 gas_assert (strcmp (name, mo->name) == 0);
3631 /* Search until we get a match for NAME. It is assumed here that
3632 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3633 if (strcmp (fmt, mo->args) == 0
3634 && mo->pinfo != INSN_MACRO
3635 && is_opcode_valid (mo))
3639 gas_assert (mo->name);
3640 gas_assert (strcmp (name, mo->name) == 0);
3643 create_insn (&insn, mo);
3661 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3666 /* Note that in the macro case, these arguments are already
3667 in MSB form. (When handling the instruction in the
3668 non-macro case, these arguments are sizes from which
3669 MSB values must be calculated.) */
3670 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3676 /* Note that in the macro case, these arguments are already
3677 in MSBD form. (When handling the instruction in the
3678 non-macro case, these arguments are sizes from which
3679 MSBD values must be calculated.) */
3680 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3684 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3693 INSERT_OPERAND (BP, insn, va_arg (args, int));
3699 INSERT_OPERAND (RT, insn, va_arg (args, int));
3703 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3708 INSERT_OPERAND (FT, insn, va_arg (args, int));
3714 INSERT_OPERAND (RD, insn, va_arg (args, int));
3719 int tmp = va_arg (args, int);
3721 INSERT_OPERAND (RT, insn, tmp);
3722 INSERT_OPERAND (RD, insn, tmp);
3728 INSERT_OPERAND (FS, insn, va_arg (args, int));
3735 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3739 INSERT_OPERAND (FD, insn, va_arg (args, int));
3743 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3747 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3751 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3758 INSERT_OPERAND (RS, insn, va_arg (args, int));
3764 macro_read_relocs (&args, r);
3765 gas_assert (*r == BFD_RELOC_GPREL16
3766 || *r == BFD_RELOC_MIPS_LITERAL
3767 || *r == BFD_RELOC_MIPS_HIGHER
3768 || *r == BFD_RELOC_HI16_S
3769 || *r == BFD_RELOC_LO16
3770 || *r == BFD_RELOC_MIPS_GOT16
3771 || *r == BFD_RELOC_MIPS_CALL16
3772 || *r == BFD_RELOC_MIPS_GOT_DISP
3773 || *r == BFD_RELOC_MIPS_GOT_PAGE
3774 || *r == BFD_RELOC_MIPS_GOT_OFST
3775 || *r == BFD_RELOC_MIPS_GOT_LO16
3776 || *r == BFD_RELOC_MIPS_CALL_LO16);
3780 macro_read_relocs (&args, r);
3781 gas_assert (ep != NULL
3782 && (ep->X_op == O_constant
3783 || (ep->X_op == O_symbol
3784 && (*r == BFD_RELOC_MIPS_HIGHEST
3785 || *r == BFD_RELOC_HI16_S
3786 || *r == BFD_RELOC_HI16
3787 || *r == BFD_RELOC_GPREL16
3788 || *r == BFD_RELOC_MIPS_GOT_HI16
3789 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3793 gas_assert (ep != NULL);
3796 * This allows macro() to pass an immediate expression for
3797 * creating short branches without creating a symbol.
3799 * We don't allow branch relaxation for these branches, as
3800 * they should only appear in ".set nomacro" anyway.
3802 if (ep->X_op == O_constant)
3804 if ((ep->X_add_number & 3) != 0)
3805 as_bad (_("branch to misaligned address (0x%lx)"),
3806 (unsigned long) ep->X_add_number);
3807 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3808 as_bad (_("branch address range overflow (0x%lx)"),
3809 (unsigned long) ep->X_add_number);
3810 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3814 *r = BFD_RELOC_16_PCREL_S2;
3818 gas_assert (ep != NULL);
3819 *r = BFD_RELOC_MIPS_JMP;
3823 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3827 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3836 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3838 append_insn (&insn, ep, r);
3842 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3845 struct mips_opcode *mo;
3846 struct mips_cl_insn insn;
3847 bfd_reloc_code_real_type r[3]
3848 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3850 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3852 gas_assert (strcmp (name, mo->name) == 0);
3854 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3857 gas_assert (mo->name);
3858 gas_assert (strcmp (name, mo->name) == 0);
3861 create_insn (&insn, mo);
3879 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3884 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3888 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3892 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3902 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3909 regno = va_arg (args, int);
3910 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3911 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3932 gas_assert (ep != NULL);
3934 if (ep->X_op != O_constant)
3935 *r = (int) BFD_RELOC_UNUSED + c;
3938 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3939 FALSE, &insn.insn_opcode, &insn.use_extend,
3942 *r = BFD_RELOC_UNUSED;
3948 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3955 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3957 append_insn (&insn, ep, r);
3961 * Sign-extend 32-bit mode constants that have bit 31 set and all
3962 * higher bits unset.
3965 normalize_constant_expr (expressionS *ex)
3967 if (ex->X_op == O_constant
3968 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3969 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3974 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3975 * all higher bits unset.
3978 normalize_address_expr (expressionS *ex)
3980 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3981 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3982 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3983 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3988 * Generate a "jalr" instruction with a relocation hint to the called
3989 * function. This occurs in NewABI PIC code.
3992 macro_build_jalr (expressionS *ep)
3996 if (MIPS_JALR_HINT_P (ep))
4001 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4002 if (MIPS_JALR_HINT_P (ep))
4003 fix_new_exp (frag_now, f - frag_now->fr_literal,
4004 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4008 * Generate a "lui" instruction.
4011 macro_build_lui (expressionS *ep, int regnum)
4013 expressionS high_expr;
4014 const struct mips_opcode *mo;
4015 struct mips_cl_insn insn;
4016 bfd_reloc_code_real_type r[3]
4017 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4018 const char *name = "lui";
4019 const char *fmt = "t,u";
4021 gas_assert (! mips_opts.mips16);
4025 if (high_expr.X_op == O_constant)
4027 /* We can compute the instruction now without a relocation entry. */
4028 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4030 *r = BFD_RELOC_UNUSED;
4034 gas_assert (ep->X_op == O_symbol);
4035 /* _gp_disp is a special case, used from s_cpload.
4036 __gnu_local_gp is used if mips_no_shared. */
4037 gas_assert (mips_pic == NO_PIC
4039 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4040 || (! mips_in_shared
4041 && strcmp (S_GET_NAME (ep->X_add_symbol),
4042 "__gnu_local_gp") == 0));
4043 *r = BFD_RELOC_HI16_S;
4046 mo = hash_find (op_hash, name);
4047 gas_assert (strcmp (name, mo->name) == 0);
4048 gas_assert (strcmp (fmt, mo->args) == 0);
4049 create_insn (&insn, mo);
4051 insn.insn_opcode = insn.insn_mo->match;
4052 INSERT_OPERAND (RT, insn, regnum);
4053 if (*r == BFD_RELOC_UNUSED)
4055 insn.insn_opcode |= high_expr.X_add_number;
4056 append_insn (&insn, NULL, r);
4059 append_insn (&insn, &high_expr, r);
4062 /* Generate a sequence of instructions to do a load or store from a constant
4063 offset off of a base register (breg) into/from a target register (treg),
4064 using AT if necessary. */
4066 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4067 int treg, int breg, int dbl)
4069 gas_assert (ep->X_op == O_constant);
4071 /* Sign-extending 32-bit constants makes their handling easier. */
4073 normalize_constant_expr (ep);
4075 /* Right now, this routine can only handle signed 32-bit constants. */
4076 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4077 as_warn (_("operand overflow"));
4079 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4081 /* Signed 16-bit offset will fit in the op. Easy! */
4082 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4086 /* 32-bit offset, need multiple instructions and AT, like:
4087 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4088 addu $tempreg,$tempreg,$breg
4089 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4090 to handle the complete offset. */
4091 macro_build_lui (ep, AT);
4092 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4093 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4096 as_bad (_("Macro used $at after \".set noat\""));
4101 * Generates code to set the $at register to true (one)
4102 * if reg is less than the immediate expression.
4105 set_at (int reg, int unsignedp)
4107 if (imm_expr.X_op == O_constant
4108 && imm_expr.X_add_number >= -0x8000
4109 && imm_expr.X_add_number < 0x8000)
4110 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4111 AT, reg, BFD_RELOC_LO16);
4114 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4115 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4119 /* Warn if an expression is not a constant. */
4122 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4124 if (ex->X_op == O_big)
4125 as_bad (_("unsupported large constant"));
4126 else if (ex->X_op != O_constant)
4127 as_bad (_("Instruction %s requires absolute expression"),
4130 if (HAVE_32BIT_GPRS)
4131 normalize_constant_expr (ex);
4134 /* Count the leading zeroes by performing a binary chop. This is a
4135 bulky bit of source, but performance is a LOT better for the
4136 majority of values than a simple loop to count the bits:
4137 for (lcnt = 0; (lcnt < 32); lcnt++)
4138 if ((v) & (1 << (31 - lcnt)))
4140 However it is not code size friendly, and the gain will drop a bit
4141 on certain cached systems.
4143 #define COUNT_TOP_ZEROES(v) \
4144 (((v) & ~0xffff) == 0 \
4145 ? ((v) & ~0xff) == 0 \
4146 ? ((v) & ~0xf) == 0 \
4147 ? ((v) & ~0x3) == 0 \
4148 ? ((v) & ~0x1) == 0 \
4153 : ((v) & ~0x7) == 0 \
4156 : ((v) & ~0x3f) == 0 \
4157 ? ((v) & ~0x1f) == 0 \
4160 : ((v) & ~0x7f) == 0 \
4163 : ((v) & ~0xfff) == 0 \
4164 ? ((v) & ~0x3ff) == 0 \
4165 ? ((v) & ~0x1ff) == 0 \
4168 : ((v) & ~0x7ff) == 0 \
4171 : ((v) & ~0x3fff) == 0 \
4172 ? ((v) & ~0x1fff) == 0 \
4175 : ((v) & ~0x7fff) == 0 \
4178 : ((v) & ~0xffffff) == 0 \
4179 ? ((v) & ~0xfffff) == 0 \
4180 ? ((v) & ~0x3ffff) == 0 \
4181 ? ((v) & ~0x1ffff) == 0 \
4184 : ((v) & ~0x7ffff) == 0 \
4187 : ((v) & ~0x3fffff) == 0 \
4188 ? ((v) & ~0x1fffff) == 0 \
4191 : ((v) & ~0x7fffff) == 0 \
4194 : ((v) & ~0xfffffff) == 0 \
4195 ? ((v) & ~0x3ffffff) == 0 \
4196 ? ((v) & ~0x1ffffff) == 0 \
4199 : ((v) & ~0x7ffffff) == 0 \
4202 : ((v) & ~0x3fffffff) == 0 \
4203 ? ((v) & ~0x1fffffff) == 0 \
4206 : ((v) & ~0x7fffffff) == 0 \
4211 * This routine generates the least number of instructions necessary to load
4212 * an absolute expression value into a register.
4215 load_register (int reg, expressionS *ep, int dbl)
4218 expressionS hi32, lo32;
4220 if (ep->X_op != O_big)
4222 gas_assert (ep->X_op == O_constant);
4224 /* Sign-extending 32-bit constants makes their handling easier. */
4226 normalize_constant_expr (ep);
4228 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4230 /* We can handle 16 bit signed values with an addiu to
4231 $zero. No need to ever use daddiu here, since $zero and
4232 the result are always correct in 32 bit mode. */
4233 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4236 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4238 /* We can handle 16 bit unsigned values with an ori to
4240 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4243 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4245 /* 32 bit values require an lui. */
4246 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4247 if ((ep->X_add_number & 0xffff) != 0)
4248 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4253 /* The value is larger than 32 bits. */
4255 if (!dbl || HAVE_32BIT_GPRS)
4259 sprintf_vma (value, ep->X_add_number);
4260 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4261 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4265 if (ep->X_op != O_big)
4268 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4269 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4270 hi32.X_add_number &= 0xffffffff;
4272 lo32.X_add_number &= 0xffffffff;
4276 gas_assert (ep->X_add_number > 2);
4277 if (ep->X_add_number == 3)
4278 generic_bignum[3] = 0;
4279 else if (ep->X_add_number > 4)
4280 as_bad (_("Number larger than 64 bits"));
4281 lo32.X_op = O_constant;
4282 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4283 hi32.X_op = O_constant;
4284 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4287 if (hi32.X_add_number == 0)
4292 unsigned long hi, lo;
4294 if (hi32.X_add_number == (offsetT) 0xffffffff)
4296 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4298 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4301 if (lo32.X_add_number & 0x80000000)
4303 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4304 if (lo32.X_add_number & 0xffff)
4305 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4310 /* Check for 16bit shifted constant. We know that hi32 is
4311 non-zero, so start the mask on the first bit of the hi32
4316 unsigned long himask, lomask;
4320 himask = 0xffff >> (32 - shift);
4321 lomask = (0xffff << shift) & 0xffffffff;
4325 himask = 0xffff << (shift - 32);
4328 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4329 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4333 tmp.X_op = O_constant;
4335 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4336 | (lo32.X_add_number >> shift));
4338 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4339 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4340 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4341 reg, reg, (shift >= 32) ? shift - 32 : shift);
4346 while (shift <= (64 - 16));
4348 /* Find the bit number of the lowest one bit, and store the
4349 shifted value in hi/lo. */
4350 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4351 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4355 while ((lo & 1) == 0)
4360 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4366 while ((hi & 1) == 0)
4375 /* Optimize if the shifted value is a (power of 2) - 1. */
4376 if ((hi == 0 && ((lo + 1) & lo) == 0)
4377 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4379 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4384 /* This instruction will set the register to be all
4386 tmp.X_op = O_constant;
4387 tmp.X_add_number = (offsetT) -1;
4388 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4392 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4393 reg, reg, (bit >= 32) ? bit - 32 : bit);
4395 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4396 reg, reg, (shift >= 32) ? shift - 32 : shift);
4401 /* Sign extend hi32 before calling load_register, because we can
4402 generally get better code when we load a sign extended value. */
4403 if ((hi32.X_add_number & 0x80000000) != 0)
4404 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4405 load_register (reg, &hi32, 0);
4408 if ((lo32.X_add_number & 0xffff0000) == 0)
4412 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4420 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4422 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4423 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4429 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4433 mid16.X_add_number >>= 16;
4434 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4435 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4438 if ((lo32.X_add_number & 0xffff) != 0)
4439 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4443 load_delay_nop (void)
4445 if (!gpr_interlocks)
4446 macro_build (NULL, "nop", "");
4449 /* Load an address into a register. */
4452 load_address (int reg, expressionS *ep, int *used_at)
4454 if (ep->X_op != O_constant
4455 && ep->X_op != O_symbol)
4457 as_bad (_("expression too complex"));
4458 ep->X_op = O_constant;
4461 if (ep->X_op == O_constant)
4463 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4467 if (mips_pic == NO_PIC)
4469 /* If this is a reference to a GP relative symbol, we want
4470 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4472 lui $reg,<sym> (BFD_RELOC_HI16_S)
4473 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4474 If we have an addend, we always use the latter form.
4476 With 64bit address space and a usable $at we want
4477 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4478 lui $at,<sym> (BFD_RELOC_HI16_S)
4479 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4480 daddiu $at,<sym> (BFD_RELOC_LO16)
4484 If $at is already in use, we use a path which is suboptimal
4485 on superscalar processors.
4486 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4487 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4489 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4491 daddiu $reg,<sym> (BFD_RELOC_LO16)
4493 For GP relative symbols in 64bit address space we can use
4494 the same sequence as in 32bit address space. */
4495 if (HAVE_64BIT_SYMBOLS)
4497 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4498 && !nopic_need_relax (ep->X_add_symbol, 1))
4500 relax_start (ep->X_add_symbol);
4501 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4502 mips_gp_register, BFD_RELOC_GPREL16);
4506 if (*used_at == 0 && mips_opts.at)
4508 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4509 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4510 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4511 BFD_RELOC_MIPS_HIGHER);
4512 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4513 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4514 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4519 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4520 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4521 BFD_RELOC_MIPS_HIGHER);
4522 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4523 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4524 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4525 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4528 if (mips_relax.sequence)
4533 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4534 && !nopic_need_relax (ep->X_add_symbol, 1))
4536 relax_start (ep->X_add_symbol);
4537 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4538 mips_gp_register, BFD_RELOC_GPREL16);
4541 macro_build_lui (ep, reg);
4542 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4543 reg, reg, BFD_RELOC_LO16);
4544 if (mips_relax.sequence)
4548 else if (!mips_big_got)
4552 /* If this is a reference to an external symbol, we want
4553 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4555 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4557 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4558 If there is a constant, it must be added in after.
4560 If we have NewABI, we want
4561 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4562 unless we're referencing a global symbol with a non-zero
4563 offset, in which case cst must be added separately. */
4566 if (ep->X_add_number)
4568 ex.X_add_number = ep->X_add_number;
4569 ep->X_add_number = 0;
4570 relax_start (ep->X_add_symbol);
4571 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4572 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4573 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4574 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4575 ex.X_op = O_constant;
4576 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4577 reg, reg, BFD_RELOC_LO16);
4578 ep->X_add_number = ex.X_add_number;
4581 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4582 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4583 if (mips_relax.sequence)
4588 ex.X_add_number = ep->X_add_number;
4589 ep->X_add_number = 0;
4590 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4591 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4593 relax_start (ep->X_add_symbol);
4595 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4599 if (ex.X_add_number != 0)
4601 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4602 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4603 ex.X_op = O_constant;
4604 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4605 reg, reg, BFD_RELOC_LO16);
4609 else if (mips_big_got)
4613 /* This is the large GOT case. If this is a reference to an
4614 external symbol, we want
4615 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4617 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4619 Otherwise, for a reference to a local symbol in old ABI, we want
4620 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4622 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4623 If there is a constant, it must be added in after.
4625 In the NewABI, for local symbols, with or without offsets, we want:
4626 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4627 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4631 ex.X_add_number = ep->X_add_number;
4632 ep->X_add_number = 0;
4633 relax_start (ep->X_add_symbol);
4634 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4635 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4636 reg, reg, mips_gp_register);
4637 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4638 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4639 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4640 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4641 else if (ex.X_add_number)
4643 ex.X_op = O_constant;
4644 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4648 ep->X_add_number = ex.X_add_number;
4650 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4651 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4652 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4653 BFD_RELOC_MIPS_GOT_OFST);
4658 ex.X_add_number = ep->X_add_number;
4659 ep->X_add_number = 0;
4660 relax_start (ep->X_add_symbol);
4661 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4662 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4663 reg, reg, mips_gp_register);
4664 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4665 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4667 if (reg_needs_delay (mips_gp_register))
4669 /* We need a nop before loading from $gp. This special
4670 check is required because the lui which starts the main
4671 instruction stream does not refer to $gp, and so will not
4672 insert the nop which may be required. */
4673 macro_build (NULL, "nop", "");
4675 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4676 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4678 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4682 if (ex.X_add_number != 0)
4684 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4685 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4686 ex.X_op = O_constant;
4687 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4695 if (!mips_opts.at && *used_at == 1)
4696 as_bad (_("Macro used $at after \".set noat\""));
4699 /* Move the contents of register SOURCE into register DEST. */
4702 move_register (int dest, int source)
4704 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4708 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4709 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4710 The two alternatives are:
4712 Global symbol Local sybmol
4713 ------------- ------------
4714 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4716 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4718 load_got_offset emits the first instruction and add_got_offset
4719 emits the second for a 16-bit offset or add_got_offset_hilo emits
4720 a sequence to add a 32-bit offset using a scratch register. */
4723 load_got_offset (int dest, expressionS *local)
4728 global.X_add_number = 0;
4730 relax_start (local->X_add_symbol);
4731 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4732 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4734 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4735 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4740 add_got_offset (int dest, expressionS *local)
4744 global.X_op = O_constant;
4745 global.X_op_symbol = NULL;
4746 global.X_add_symbol = NULL;
4747 global.X_add_number = local->X_add_number;
4749 relax_start (local->X_add_symbol);
4750 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4751 dest, dest, BFD_RELOC_LO16);
4753 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4758 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4761 int hold_mips_optimize;
4763 global.X_op = O_constant;
4764 global.X_op_symbol = NULL;
4765 global.X_add_symbol = NULL;
4766 global.X_add_number = local->X_add_number;
4768 relax_start (local->X_add_symbol);
4769 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4771 /* Set mips_optimize around the lui instruction to avoid
4772 inserting an unnecessary nop after the lw. */
4773 hold_mips_optimize = mips_optimize;
4775 macro_build_lui (&global, tmp);
4776 mips_optimize = hold_mips_optimize;
4777 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4780 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4785 * This routine implements the seemingly endless macro or synthesized
4786 * instructions and addressing modes in the mips assembly language. Many
4787 * of these macros are simple and are similar to each other. These could
4788 * probably be handled by some kind of table or grammar approach instead of
4789 * this verbose method. Others are not simple macros but are more like
4790 * optimizing code generation.
4791 * One interesting optimization is when several store macros appear
4792 * consecutively that would load AT with the upper half of the same address.
4793 * The ensuing load upper instructions are ommited. This implies some kind
4794 * of global optimization. We currently only optimize within a single macro.
4795 * For many of the load and store macros if the address is specified as a
4796 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4797 * first load register 'at' with zero and use it as the base register. The
4798 * mips assembler simply uses register $zero. Just one tiny optimization
4802 macro (struct mips_cl_insn *ip)
4804 unsigned int treg, sreg, dreg, breg;
4805 unsigned int tempreg;
4820 bfd_reloc_code_real_type r;
4821 int hold_mips_optimize;
4823 gas_assert (! mips_opts.mips16);
4825 treg = (ip->insn_opcode >> 16) & 0x1f;
4826 dreg = (ip->insn_opcode >> 11) & 0x1f;
4827 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4828 mask = ip->insn_mo->mask;
4830 expr1.X_op = O_constant;
4831 expr1.X_op_symbol = NULL;
4832 expr1.X_add_symbol = NULL;
4833 expr1.X_add_number = 1;
4847 expr1.X_add_number = 8;
4848 macro_build (&expr1, "bgez", "s,p", sreg);
4850 macro_build (NULL, "nop", "", 0);
4852 move_register (dreg, sreg);
4853 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4876 if (imm_expr.X_op == O_constant
4877 && imm_expr.X_add_number >= -0x8000
4878 && imm_expr.X_add_number < 0x8000)
4880 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4884 load_register (AT, &imm_expr, dbl);
4885 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4904 if (imm_expr.X_op == O_constant
4905 && imm_expr.X_add_number >= 0
4906 && imm_expr.X_add_number < 0x10000)
4908 if (mask != M_NOR_I)
4909 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4912 macro_build (&imm_expr, "ori", "t,r,i",
4913 treg, sreg, BFD_RELOC_LO16);
4914 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4920 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4921 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4925 switch (imm_expr.X_add_number)
4928 macro_build (NULL, "nop", "");
4931 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4934 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4935 (int)imm_expr.X_add_number);
4954 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4956 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4960 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4961 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4969 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4974 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4978 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4979 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4985 /* check for > max integer */
4986 maxnum = 0x7fffffff;
4987 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4994 if (imm_expr.X_op == O_constant
4995 && imm_expr.X_add_number >= maxnum
4996 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4999 /* result is always false */
5001 macro_build (NULL, "nop", "", 0);
5003 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
5006 if (imm_expr.X_op != O_constant)
5007 as_bad (_("Unsupported large constant"));
5008 ++imm_expr.X_add_number;
5012 if (mask == M_BGEL_I)
5014 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5016 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5019 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5021 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5024 maxnum = 0x7fffffff;
5025 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5032 maxnum = - maxnum - 1;
5033 if (imm_expr.X_op == O_constant
5034 && imm_expr.X_add_number <= maxnum
5035 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5038 /* result is always true */
5039 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5040 macro_build (&offset_expr, "b", "p");
5045 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5055 macro_build (&offset_expr, likely ? "beql" : "beq",
5060 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5061 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5069 && imm_expr.X_op == O_constant
5070 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5072 if (imm_expr.X_op != O_constant)
5073 as_bad (_("Unsupported large constant"));
5074 ++imm_expr.X_add_number;
5078 if (mask == M_BGEUL_I)
5080 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5082 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5084 macro_build (&offset_expr, likely ? "bnel" : "bne",
5090 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5098 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5103 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5107 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5108 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5116 macro_build (&offset_expr, likely ? "bnel" : "bne",
5123 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5124 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5132 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5137 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5141 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5142 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5148 maxnum = 0x7fffffff;
5149 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5156 if (imm_expr.X_op == O_constant
5157 && imm_expr.X_add_number >= maxnum
5158 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5160 if (imm_expr.X_op != O_constant)
5161 as_bad (_("Unsupported large constant"));
5162 ++imm_expr.X_add_number;
5166 if (mask == M_BLTL_I)
5168 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5170 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5173 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5175 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5180 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5188 macro_build (&offset_expr, likely ? "beql" : "beq",
5195 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5196 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
5204 && imm_expr.X_op == O_constant
5205 && imm_expr.X_add_number == (offsetT) 0xffffffff))
5207 if (imm_expr.X_op != O_constant)
5208 as_bad (_("Unsupported large constant"));
5209 ++imm_expr.X_add_number;
5213 if (mask == M_BLTUL_I)
5215 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5217 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5219 macro_build (&offset_expr, likely ? "beql" : "beq",
5225 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5233 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5238 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5242 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5243 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5253 macro_build (&offset_expr, likely ? "bnel" : "bne",
5258 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5259 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
5267 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5269 as_bad (_("Unsupported large constant"));
5274 pos = (unsigned long) imm_expr.X_add_number;
5275 size = (unsigned long) imm2_expr.X_add_number;
5280 as_bad (_("Improper position (%lu)"), pos);
5283 if (size == 0 || size > 64
5284 || (pos + size - 1) > 63)
5286 as_bad (_("Improper extract size (%lu, position %lu)"),
5291 if (size <= 32 && pos < 32)
5296 else if (size <= 32)
5306 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
5315 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5317 as_bad (_("Unsupported large constant"));
5322 pos = (unsigned long) imm_expr.X_add_number;
5323 size = (unsigned long) imm2_expr.X_add_number;
5328 as_bad (_("Improper position (%lu)"), pos);
5331 if (size == 0 || size > 64
5332 || (pos + size - 1) > 63)
5334 as_bad (_("Improper insert size (%lu, position %lu)"),
5339 if (pos < 32 && (pos + size - 1) < 32)
5354 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5355 (int) (pos + size - 1));
5371 as_warn (_("Divide by zero."));
5373 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5375 macro_build (NULL, "break", "c", 7);
5382 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5383 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5387 expr1.X_add_number = 8;
5388 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5389 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5390 macro_build (NULL, "break", "c", 7);
5392 expr1.X_add_number = -1;
5394 load_register (AT, &expr1, dbl);
5395 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5396 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5399 expr1.X_add_number = 1;
5400 load_register (AT, &expr1, dbl);
5401 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5405 expr1.X_add_number = 0x80000000;
5406 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5410 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5411 /* We want to close the noreorder block as soon as possible, so
5412 that later insns are available for delay slot filling. */
5417 expr1.X_add_number = 8;
5418 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5419 macro_build (NULL, "nop", "", 0);
5421 /* We want to close the noreorder block as soon as possible, so
5422 that later insns are available for delay slot filling. */
5425 macro_build (NULL, "break", "c", 6);
5427 macro_build (NULL, s, "d", dreg);
5466 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5468 as_warn (_("Divide by zero."));
5470 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
5472 macro_build (NULL, "break", "c", 7);
5475 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5477 if (strcmp (s2, "mflo") == 0)
5478 move_register (dreg, sreg);
5480 move_register (dreg, 0);
5483 if (imm_expr.X_op == O_constant
5484 && imm_expr.X_add_number == -1
5485 && s[strlen (s) - 1] != 'u')
5487 if (strcmp (s2, "mflo") == 0)
5489 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5492 move_register (dreg, 0);
5497 load_register (AT, &imm_expr, dbl);
5498 macro_build (NULL, s, "z,s,t", sreg, AT);
5499 macro_build (NULL, s2, "d", dreg);
5521 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
5522 macro_build (NULL, s, "z,s,t", sreg, treg);
5523 /* We want to close the noreorder block as soon as possible, so
5524 that later insns are available for delay slot filling. */
5529 expr1.X_add_number = 8;
5530 macro_build (&expr1, "bne", "s,t,p", treg, 0);
5531 macro_build (NULL, s, "z,s,t", sreg, treg);
5533 /* We want to close the noreorder block as soon as possible, so
5534 that later insns are available for delay slot filling. */
5536 macro_build (NULL, "break", "c", 7);
5538 macro_build (NULL, s2, "d", dreg);
5550 /* Load the address of a symbol into a register. If breg is not
5551 zero, we then add a base register to it. */
5553 if (dbl && HAVE_32BIT_GPRS)
5554 as_warn (_("dla used to load 32-bit register"));
5556 if (! dbl && HAVE_64BIT_OBJECTS)
5557 as_warn (_("la used to load 64-bit address"));
5559 if (offset_expr.X_op == O_constant
5560 && offset_expr.X_add_number >= -0x8000
5561 && offset_expr.X_add_number < 0x8000)
5563 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5564 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5568 if (mips_opts.at && (treg == breg))
5578 if (offset_expr.X_op != O_symbol
5579 && offset_expr.X_op != O_constant)
5581 as_bad (_("expression too complex"));
5582 offset_expr.X_op = O_constant;
5585 if (offset_expr.X_op == O_constant)
5586 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5587 else if (mips_pic == NO_PIC)
5589 /* If this is a reference to a GP relative symbol, we want
5590 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5592 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5593 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5594 If we have a constant, we need two instructions anyhow,
5595 so we may as well always use the latter form.
5597 With 64bit address space and a usable $at we want
5598 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5599 lui $at,<sym> (BFD_RELOC_HI16_S)
5600 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5601 daddiu $at,<sym> (BFD_RELOC_LO16)
5603 daddu $tempreg,$tempreg,$at
5605 If $at is already in use, we use a path which is suboptimal
5606 on superscalar processors.
5607 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5608 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5610 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5612 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5614 For GP relative symbols in 64bit address space we can use
5615 the same sequence as in 32bit address space. */
5616 if (HAVE_64BIT_SYMBOLS)
5618 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5619 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5621 relax_start (offset_expr.X_add_symbol);
5622 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5623 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5627 if (used_at == 0 && mips_opts.at)
5629 macro_build (&offset_expr, "lui", "t,u",
5630 tempreg, BFD_RELOC_MIPS_HIGHEST);
5631 macro_build (&offset_expr, "lui", "t,u",
5632 AT, BFD_RELOC_HI16_S);
5633 macro_build (&offset_expr, "daddiu", "t,r,j",
5634 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5635 macro_build (&offset_expr, "daddiu", "t,r,j",
5636 AT, AT, BFD_RELOC_LO16);
5637 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5638 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5643 macro_build (&offset_expr, "lui", "t,u",
5644 tempreg, BFD_RELOC_MIPS_HIGHEST);
5645 macro_build (&offset_expr, "daddiu", "t,r,j",
5646 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5647 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5648 macro_build (&offset_expr, "daddiu", "t,r,j",
5649 tempreg, tempreg, BFD_RELOC_HI16_S);
5650 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5651 macro_build (&offset_expr, "daddiu", "t,r,j",
5652 tempreg, tempreg, BFD_RELOC_LO16);
5655 if (mips_relax.sequence)
5660 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5661 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5663 relax_start (offset_expr.X_add_symbol);
5664 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5665 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5668 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5669 as_bad (_("offset too large"));
5670 macro_build_lui (&offset_expr, tempreg);
5671 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5672 tempreg, tempreg, BFD_RELOC_LO16);
5673 if (mips_relax.sequence)
5677 else if (!mips_big_got && !HAVE_NEWABI)
5679 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5681 /* If this is a reference to an external symbol, and there
5682 is no constant, we want
5683 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5684 or for lca or if tempreg is PIC_CALL_REG
5685 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5686 For a local symbol, we want
5687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5689 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5691 If we have a small constant, and this is a reference to
5692 an external symbol, we want
5693 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5695 addiu $tempreg,$tempreg,<constant>
5696 For a local symbol, we want the same instruction
5697 sequence, but we output a BFD_RELOC_LO16 reloc on the
5700 If we have a large constant, and this is a reference to
5701 an external symbol, we want
5702 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5703 lui $at,<hiconstant>
5704 addiu $at,$at,<loconstant>
5705 addu $tempreg,$tempreg,$at
5706 For a local symbol, we want the same instruction
5707 sequence, but we output a BFD_RELOC_LO16 reloc on the
5711 if (offset_expr.X_add_number == 0)
5713 if (mips_pic == SVR4_PIC
5715 && (call || tempreg == PIC_CALL_REG))
5716 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5718 relax_start (offset_expr.X_add_symbol);
5719 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5720 lw_reloc_type, mips_gp_register);
5723 /* We're going to put in an addu instruction using
5724 tempreg, so we may as well insert the nop right
5729 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5730 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5732 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5733 tempreg, tempreg, BFD_RELOC_LO16);
5735 /* FIXME: If breg == 0, and the next instruction uses
5736 $tempreg, then if this variant case is used an extra
5737 nop will be generated. */
5739 else if (offset_expr.X_add_number >= -0x8000
5740 && offset_expr.X_add_number < 0x8000)
5742 load_got_offset (tempreg, &offset_expr);
5744 add_got_offset (tempreg, &offset_expr);
5748 expr1.X_add_number = offset_expr.X_add_number;
5749 offset_expr.X_add_number =
5750 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5751 load_got_offset (tempreg, &offset_expr);
5752 offset_expr.X_add_number = expr1.X_add_number;
5753 /* If we are going to add in a base register, and the
5754 target register and the base register are the same,
5755 then we are using AT as a temporary register. Since
5756 we want to load the constant into AT, we add our
5757 current AT (from the global offset table) and the
5758 register into the register now, and pretend we were
5759 not using a base register. */
5763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5768 add_got_offset_hilo (tempreg, &offset_expr, AT);
5772 else if (!mips_big_got && HAVE_NEWABI)
5774 int add_breg_early = 0;
5776 /* If this is a reference to an external, and there is no
5777 constant, or local symbol (*), with or without a
5779 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5780 or for lca or if tempreg is PIC_CALL_REG
5781 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5783 If we have a small constant, and this is a reference to
5784 an external symbol, we want
5785 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5786 addiu $tempreg,$tempreg,<constant>
5788 If we have a large constant, and this is a reference to
5789 an external symbol, we want
5790 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5791 lui $at,<hiconstant>
5792 addiu $at,$at,<loconstant>
5793 addu $tempreg,$tempreg,$at
5795 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5796 local symbols, even though it introduces an additional
5799 if (offset_expr.X_add_number)
5801 expr1.X_add_number = offset_expr.X_add_number;
5802 offset_expr.X_add_number = 0;
5804 relax_start (offset_expr.X_add_symbol);
5805 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5806 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5808 if (expr1.X_add_number >= -0x8000
5809 && expr1.X_add_number < 0x8000)
5811 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5812 tempreg, tempreg, BFD_RELOC_LO16);
5814 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5816 /* If we are going to add in a base register, and the
5817 target register and the base register are the same,
5818 then we are using AT as a temporary register. Since
5819 we want to load the constant into AT, we add our
5820 current AT (from the global offset table) and the
5821 register into the register now, and pretend we were
5822 not using a base register. */
5827 gas_assert (tempreg == AT);
5828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5834 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5835 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5841 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5844 offset_expr.X_add_number = expr1.X_add_number;
5846 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5847 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5850 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5851 treg, tempreg, breg);
5857 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5859 relax_start (offset_expr.X_add_symbol);
5860 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5861 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5863 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5864 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5869 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5870 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5873 else if (mips_big_got && !HAVE_NEWABI)
5876 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5877 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5878 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5880 /* This is the large GOT case. If this is a reference to an
5881 external symbol, and there is no constant, we want
5882 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5883 addu $tempreg,$tempreg,$gp
5884 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5885 or for lca or if tempreg is PIC_CALL_REG
5886 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5887 addu $tempreg,$tempreg,$gp
5888 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5889 For a local symbol, we want
5890 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5892 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5894 If we have a small constant, and this is a reference to
5895 an external symbol, we want
5896 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5897 addu $tempreg,$tempreg,$gp
5898 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5900 addiu $tempreg,$tempreg,<constant>
5901 For a local symbol, we want
5902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5904 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5906 If we have a large constant, and this is a reference to
5907 an external symbol, we want
5908 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5909 addu $tempreg,$tempreg,$gp
5910 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5911 lui $at,<hiconstant>
5912 addiu $at,$at,<loconstant>
5913 addu $tempreg,$tempreg,$at
5914 For a local symbol, we want
5915 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5916 lui $at,<hiconstant>
5917 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5918 addu $tempreg,$tempreg,$at
5921 expr1.X_add_number = offset_expr.X_add_number;
5922 offset_expr.X_add_number = 0;
5923 relax_start (offset_expr.X_add_symbol);
5924 gpdelay = reg_needs_delay (mips_gp_register);
5925 if (expr1.X_add_number == 0 && breg == 0
5926 && (call || tempreg == PIC_CALL_REG))
5928 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5929 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5931 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5932 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5933 tempreg, tempreg, mips_gp_register);
5934 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5935 tempreg, lw_reloc_type, tempreg);
5936 if (expr1.X_add_number == 0)
5940 /* We're going to put in an addu instruction using
5941 tempreg, so we may as well insert the nop right
5946 else if (expr1.X_add_number >= -0x8000
5947 && expr1.X_add_number < 0x8000)
5950 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5951 tempreg, tempreg, BFD_RELOC_LO16);
5955 /* If we are going to add in a base register, and the
5956 target register and the base register are the same,
5957 then we are using AT as a temporary register. Since
5958 we want to load the constant into AT, we add our
5959 current AT (from the global offset table) and the
5960 register into the register now, and pretend we were
5961 not using a base register. */
5966 gas_assert (tempreg == AT);
5968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5973 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5978 offset_expr.X_add_number =
5979 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5984 /* This is needed because this instruction uses $gp, but
5985 the first instruction on the main stream does not. */
5986 macro_build (NULL, "nop", "");
5989 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5990 local_reloc_type, mips_gp_register);
5991 if (expr1.X_add_number >= -0x8000
5992 && expr1.X_add_number < 0x8000)
5995 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5996 tempreg, tempreg, BFD_RELOC_LO16);
5997 /* FIXME: If add_number is 0, and there was no base
5998 register, the external symbol case ended with a load,
5999 so if the symbol turns out to not be external, and
6000 the next instruction uses tempreg, an unnecessary nop
6001 will be inserted. */
6007 /* We must add in the base register now, as in the
6008 external symbol case. */
6009 gas_assert (tempreg == AT);
6011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6014 /* We set breg to 0 because we have arranged to add
6015 it in in both cases. */
6019 macro_build_lui (&expr1, AT);
6020 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6021 AT, AT, BFD_RELOC_LO16);
6022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6023 tempreg, tempreg, AT);
6028 else if (mips_big_got && HAVE_NEWABI)
6030 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6031 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6032 int add_breg_early = 0;
6034 /* This is the large GOT case. If this is a reference to an
6035 external symbol, and there is no constant, we want
6036 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6037 add $tempreg,$tempreg,$gp
6038 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6039 or for lca or if tempreg is PIC_CALL_REG
6040 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6041 add $tempreg,$tempreg,$gp
6042 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6044 If we have a small constant, and this is a reference to
6045 an external symbol, we want
6046 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6047 add $tempreg,$tempreg,$gp
6048 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6049 addi $tempreg,$tempreg,<constant>
6051 If we have a large constant, and this is a reference to
6052 an external symbol, we want
6053 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6054 addu $tempreg,$tempreg,$gp
6055 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6056 lui $at,<hiconstant>
6057 addi $at,$at,<loconstant>
6058 add $tempreg,$tempreg,$at
6060 If we have NewABI, and we know it's a local symbol, we want
6061 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6062 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6063 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6065 relax_start (offset_expr.X_add_symbol);
6067 expr1.X_add_number = offset_expr.X_add_number;
6068 offset_expr.X_add_number = 0;
6070 if (expr1.X_add_number == 0 && breg == 0
6071 && (call || tempreg == PIC_CALL_REG))
6073 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6074 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6076 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6077 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6078 tempreg, tempreg, mips_gp_register);
6079 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6080 tempreg, lw_reloc_type, tempreg);
6082 if (expr1.X_add_number == 0)
6084 else if (expr1.X_add_number >= -0x8000
6085 && expr1.X_add_number < 0x8000)
6087 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6088 tempreg, tempreg, BFD_RELOC_LO16);
6090 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6092 /* If we are going to add in a base register, and the
6093 target register and the base register are the same,
6094 then we are using AT as a temporary register. Since
6095 we want to load the constant into AT, we add our
6096 current AT (from the global offset table) and the
6097 register into the register now, and pretend we were
6098 not using a base register. */
6103 gas_assert (tempreg == AT);
6104 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6110 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6111 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6116 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6119 offset_expr.X_add_number = expr1.X_add_number;
6120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6121 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6122 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6123 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6127 treg, tempreg, breg);
6137 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6142 unsigned long temp = (treg << 16) | (0x01);
6143 macro_build (NULL, "c2", "C", temp);
6145 /* AT is not used, just return */
6150 unsigned long temp = (0x02);
6151 macro_build (NULL, "c2", "C", temp);
6153 /* AT is not used, just return */
6158 unsigned long temp = (treg << 16) | (0x02);
6159 macro_build (NULL, "c2", "C", temp);
6161 /* AT is not used, just return */
6165 macro_build (NULL, "c2", "C", 3);
6166 /* AT is not used, just return */
6171 unsigned long temp = (treg << 16) | 0x03;
6172 macro_build (NULL, "c2", "C", temp);
6174 /* AT is not used, just return */
6178 /* The j instruction may not be used in PIC code, since it
6179 requires an absolute address. We convert it to a b
6181 if (mips_pic == NO_PIC)
6182 macro_build (&offset_expr, "j", "a");
6184 macro_build (&offset_expr, "b", "p");
6187 /* The jal instructions must be handled as macros because when
6188 generating PIC code they expand to multi-instruction
6189 sequences. Normally they are simple instructions. */
6194 if (mips_pic == NO_PIC)
6195 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6198 if (sreg != PIC_CALL_REG)
6199 as_warn (_("MIPS PIC call to register other than $25"));
6201 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6202 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6204 if (mips_cprestore_offset < 0)
6205 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6208 if (! mips_frame_reg_valid)
6210 as_warn (_("No .frame pseudo-op used in PIC code"));
6211 /* Quiet this warning. */
6212 mips_frame_reg_valid = 1;
6214 if (! mips_cprestore_valid)
6216 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6217 /* Quiet this warning. */
6218 mips_cprestore_valid = 1;
6220 expr1.X_add_number = mips_cprestore_offset;
6221 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6224 HAVE_64BIT_ADDRESSES);
6232 if (mips_pic == NO_PIC)
6233 macro_build (&offset_expr, "jal", "a");
6234 else if (mips_pic == SVR4_PIC)
6236 /* If this is a reference to an external symbol, and we are
6237 using a small GOT, we want
6238 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6242 lw $gp,cprestore($sp)
6243 The cprestore value is set using the .cprestore
6244 pseudo-op. If we are using a big GOT, we want
6245 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6247 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6251 lw $gp,cprestore($sp)
6252 If the symbol is not external, we want
6253 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6255 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6258 lw $gp,cprestore($sp)
6260 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6261 sequences above, minus nops, unless the symbol is local,
6262 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6268 relax_start (offset_expr.X_add_symbol);
6269 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6270 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6273 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6274 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6280 relax_start (offset_expr.X_add_symbol);
6281 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6282 BFD_RELOC_MIPS_CALL_HI16);
6283 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6284 PIC_CALL_REG, mips_gp_register);
6285 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6286 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6289 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6290 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6292 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6293 PIC_CALL_REG, PIC_CALL_REG,
6294 BFD_RELOC_MIPS_GOT_OFST);
6298 macro_build_jalr (&offset_expr);
6302 relax_start (offset_expr.X_add_symbol);
6305 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6306 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6315 gpdelay = reg_needs_delay (mips_gp_register);
6316 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6317 BFD_RELOC_MIPS_CALL_HI16);
6318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6319 PIC_CALL_REG, mips_gp_register);
6320 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6321 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6326 macro_build (NULL, "nop", "");
6328 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6329 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6332 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6333 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6335 macro_build_jalr (&offset_expr);
6337 if (mips_cprestore_offset < 0)
6338 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6341 if (! mips_frame_reg_valid)
6343 as_warn (_("No .frame pseudo-op used in PIC code"));
6344 /* Quiet this warning. */
6345 mips_frame_reg_valid = 1;
6347 if (! mips_cprestore_valid)
6349 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6350 /* Quiet this warning. */
6351 mips_cprestore_valid = 1;
6353 if (mips_opts.noreorder)
6354 macro_build (NULL, "nop", "");
6355 expr1.X_add_number = mips_cprestore_offset;
6356 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6359 HAVE_64BIT_ADDRESSES);
6363 else if (mips_pic == VXWORKS_PIC)
6364 as_bad (_("Non-PIC jump used in PIC library"));
6387 /* Itbl support may require additional care here. */
6392 /* Itbl support may require additional care here. */
6397 /* Itbl support may require additional care here. */
6402 /* Itbl support may require additional care here. */
6415 /* Itbl support may require additional care here. */
6420 /* Itbl support may require additional care here. */
6425 /* Itbl support may require additional care here. */
6445 if (breg == treg || coproc || lr)
6466 /* Itbl support may require additional care here. */
6471 /* Itbl support may require additional care here. */
6476 /* Itbl support may require additional care here. */
6481 /* Itbl support may require additional care here. */
6502 /* Itbl support may require additional care here. */
6506 /* Itbl support may require additional care here. */
6511 /* Itbl support may require additional care here. */
6524 && NO_ISA_COP (mips_opts.arch)
6525 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6527 as_bad (_("opcode not supported on this processor: %s"),
6528 mips_cpu_info_from_arch (mips_opts.arch)->name);
6532 /* Itbl support may require additional care here. */
6533 if (mask == M_LWC1_AB
6534 || mask == M_SWC1_AB
6535 || mask == M_LDC1_AB
6536 || mask == M_SDC1_AB
6540 else if (mask == M_CACHE_AB)
6547 if (offset_expr.X_op != O_constant
6548 && offset_expr.X_op != O_symbol)
6550 as_bad (_("expression too complex"));
6551 offset_expr.X_op = O_constant;
6554 if (HAVE_32BIT_ADDRESSES
6555 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6559 sprintf_vma (value, offset_expr.X_add_number);
6560 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6563 /* A constant expression in PIC code can be handled just as it
6564 is in non PIC code. */
6565 if (offset_expr.X_op == O_constant)
6567 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
6568 & ~(bfd_vma) 0xffff);
6569 normalize_address_expr (&expr1);
6570 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6573 tempreg, tempreg, breg);
6574 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6576 else if (mips_pic == NO_PIC)
6578 /* If this is a reference to a GP relative symbol, and there
6579 is no base register, we want
6580 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6581 Otherwise, if there is no base register, we want
6582 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6583 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6584 If we have a constant, we need two instructions anyhow,
6585 so we always use the latter form.
6587 If we have a base register, and this is a reference to a
6588 GP relative symbol, we want
6589 addu $tempreg,$breg,$gp
6590 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6592 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6593 addu $tempreg,$tempreg,$breg
6594 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6595 With a constant we always use the latter case.
6597 With 64bit address space and no base register and $at usable,
6599 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6600 lui $at,<sym> (BFD_RELOC_HI16_S)
6601 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6604 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6605 If we have a base register, we want
6606 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6607 lui $at,<sym> (BFD_RELOC_HI16_S)
6608 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6612 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6614 Without $at we can't generate the optimal path for superscalar
6615 processors here since this would require two temporary registers.
6616 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6617 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6619 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6621 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6622 If we have a base register, we want
6623 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6624 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6626 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6628 daddu $tempreg,$tempreg,$breg
6629 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6631 For GP relative symbols in 64bit address space we can use
6632 the same sequence as in 32bit address space. */
6633 if (HAVE_64BIT_SYMBOLS)
6635 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6636 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6638 relax_start (offset_expr.X_add_symbol);
6641 macro_build (&offset_expr, s, fmt, treg,
6642 BFD_RELOC_GPREL16, mips_gp_register);
6646 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6647 tempreg, breg, mips_gp_register);
6648 macro_build (&offset_expr, s, fmt, treg,
6649 BFD_RELOC_GPREL16, tempreg);
6654 if (used_at == 0 && mips_opts.at)
6656 macro_build (&offset_expr, "lui", "t,u", tempreg,
6657 BFD_RELOC_MIPS_HIGHEST);
6658 macro_build (&offset_expr, "lui", "t,u", AT,
6660 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6661 tempreg, BFD_RELOC_MIPS_HIGHER);
6663 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6664 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6665 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6666 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6672 macro_build (&offset_expr, "lui", "t,u", tempreg,
6673 BFD_RELOC_MIPS_HIGHEST);
6674 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6675 tempreg, BFD_RELOC_MIPS_HIGHER);
6676 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6677 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6678 tempreg, BFD_RELOC_HI16_S);
6679 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6681 macro_build (NULL, "daddu", "d,v,t",
6682 tempreg, tempreg, breg);
6683 macro_build (&offset_expr, s, fmt, treg,
6684 BFD_RELOC_LO16, tempreg);
6687 if (mips_relax.sequence)
6694 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6695 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6697 relax_start (offset_expr.X_add_symbol);
6698 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6702 macro_build_lui (&offset_expr, tempreg);
6703 macro_build (&offset_expr, s, fmt, treg,
6704 BFD_RELOC_LO16, tempreg);
6705 if (mips_relax.sequence)
6710 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6711 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6713 relax_start (offset_expr.X_add_symbol);
6714 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6715 tempreg, breg, mips_gp_register);
6716 macro_build (&offset_expr, s, fmt, treg,
6717 BFD_RELOC_GPREL16, tempreg);
6720 macro_build_lui (&offset_expr, tempreg);
6721 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6722 tempreg, tempreg, breg);
6723 macro_build (&offset_expr, s, fmt, treg,
6724 BFD_RELOC_LO16, tempreg);
6725 if (mips_relax.sequence)
6729 else if (!mips_big_got)
6731 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6733 /* If this is a reference to an external symbol, we want
6734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6736 <op> $treg,0($tempreg)
6738 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6740 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6741 <op> $treg,0($tempreg)
6744 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6745 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6747 If there is a base register, we add it to $tempreg before
6748 the <op>. If there is a constant, we stick it in the
6749 <op> instruction. We don't handle constants larger than
6750 16 bits, because we have no way to load the upper 16 bits
6751 (actually, we could handle them for the subset of cases
6752 in which we are not using $at). */
6753 gas_assert (offset_expr.X_op == O_symbol);
6756 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6757 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6759 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6760 tempreg, tempreg, breg);
6761 macro_build (&offset_expr, s, fmt, treg,
6762 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6765 expr1.X_add_number = offset_expr.X_add_number;
6766 offset_expr.X_add_number = 0;
6767 if (expr1.X_add_number < -0x8000
6768 || expr1.X_add_number >= 0x8000)
6769 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6770 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6771 lw_reloc_type, mips_gp_register);
6773 relax_start (offset_expr.X_add_symbol);
6775 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6776 tempreg, BFD_RELOC_LO16);
6779 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6780 tempreg, tempreg, breg);
6781 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6783 else if (mips_big_got && !HAVE_NEWABI)
6787 /* If this is a reference to an external symbol, we want
6788 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6789 addu $tempreg,$tempreg,$gp
6790 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6791 <op> $treg,0($tempreg)
6793 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6795 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6796 <op> $treg,0($tempreg)
6797 If there is a base register, we add it to $tempreg before
6798 the <op>. If there is a constant, we stick it in the
6799 <op> instruction. We don't handle constants larger than
6800 16 bits, because we have no way to load the upper 16 bits
6801 (actually, we could handle them for the subset of cases
6802 in which we are not using $at). */
6803 gas_assert (offset_expr.X_op == O_symbol);
6804 expr1.X_add_number = offset_expr.X_add_number;
6805 offset_expr.X_add_number = 0;
6806 if (expr1.X_add_number < -0x8000
6807 || expr1.X_add_number >= 0x8000)
6808 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6809 gpdelay = reg_needs_delay (mips_gp_register);
6810 relax_start (offset_expr.X_add_symbol);
6811 macro_build (&offset_expr, "lui", "t,u", tempreg,
6812 BFD_RELOC_MIPS_GOT_HI16);
6813 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6815 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6816 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6819 macro_build (NULL, "nop", "");
6820 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6821 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6823 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6824 tempreg, BFD_RELOC_LO16);
6828 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6829 tempreg, tempreg, breg);
6830 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6832 else if (mips_big_got && HAVE_NEWABI)
6834 /* If this is a reference to an external symbol, we want
6835 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6836 add $tempreg,$tempreg,$gp
6837 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6838 <op> $treg,<ofst>($tempreg)
6839 Otherwise, for local symbols, we want:
6840 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6841 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6842 gas_assert (offset_expr.X_op == O_symbol);
6843 expr1.X_add_number = offset_expr.X_add_number;
6844 offset_expr.X_add_number = 0;
6845 if (expr1.X_add_number < -0x8000
6846 || expr1.X_add_number >= 0x8000)
6847 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6848 relax_start (offset_expr.X_add_symbol);
6849 macro_build (&offset_expr, "lui", "t,u", tempreg,
6850 BFD_RELOC_MIPS_GOT_HI16);
6851 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6853 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6854 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6856 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6857 tempreg, tempreg, breg);
6858 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6861 offset_expr.X_add_number = expr1.X_add_number;
6862 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6863 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6865 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6866 tempreg, tempreg, breg);
6867 macro_build (&offset_expr, s, fmt, treg,
6868 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6878 load_register (treg, &imm_expr, 0);
6882 load_register (treg, &imm_expr, 1);
6886 if (imm_expr.X_op == O_constant)
6889 load_register (AT, &imm_expr, 0);
6890 macro_build (NULL, "mtc1", "t,G", AT, treg);
6895 gas_assert (offset_expr.X_op == O_symbol
6896 && strcmp (segment_name (S_GET_SEGMENT
6897 (offset_expr.X_add_symbol)),
6899 && offset_expr.X_add_number == 0);
6900 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6901 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6906 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6907 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6908 order 32 bits of the value and the low order 32 bits are either
6909 zero or in OFFSET_EXPR. */
6910 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6912 if (HAVE_64BIT_GPRS)
6913 load_register (treg, &imm_expr, 1);
6918 if (target_big_endian)
6930 load_register (hreg, &imm_expr, 0);
6933 if (offset_expr.X_op == O_absent)
6934 move_register (lreg, 0);
6937 gas_assert (offset_expr.X_op == O_constant);
6938 load_register (lreg, &offset_expr, 0);
6945 /* We know that sym is in the .rdata section. First we get the
6946 upper 16 bits of the address. */
6947 if (mips_pic == NO_PIC)
6949 macro_build_lui (&offset_expr, AT);
6954 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6955 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6959 /* Now we load the register(s). */
6960 if (HAVE_64BIT_GPRS)
6963 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6968 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6971 /* FIXME: How in the world do we deal with the possible
6973 offset_expr.X_add_number += 4;
6974 macro_build (&offset_expr, "lw", "t,o(b)",
6975 treg + 1, BFD_RELOC_LO16, AT);
6981 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6982 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6983 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6984 the value and the low order 32 bits are either zero or in
6986 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6989 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6990 if (HAVE_64BIT_FPRS)
6992 gas_assert (HAVE_64BIT_GPRS);
6993 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6997 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6998 if (offset_expr.X_op == O_absent)
6999 macro_build (NULL, "mtc1", "t,G", 0, treg);
7002 gas_assert (offset_expr.X_op == O_constant);
7003 load_register (AT, &offset_expr, 0);
7004 macro_build (NULL, "mtc1", "t,G", AT, treg);
7010 gas_assert (offset_expr.X_op == O_symbol
7011 && offset_expr.X_add_number == 0);
7012 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7013 if (strcmp (s, ".lit8") == 0)
7015 if (mips_opts.isa != ISA_MIPS1)
7017 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7018 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7021 breg = mips_gp_register;
7022 r = BFD_RELOC_MIPS_LITERAL;
7027 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7029 if (mips_pic != NO_PIC)
7030 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7031 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7034 /* FIXME: This won't work for a 64 bit address. */
7035 macro_build_lui (&offset_expr, AT);
7038 if (mips_opts.isa != ISA_MIPS1)
7040 macro_build (&offset_expr, "ldc1", "T,o(b)",
7041 treg, BFD_RELOC_LO16, AT);
7050 /* Even on a big endian machine $fn comes before $fn+1. We have
7051 to adjust when loading from memory. */
7054 gas_assert (mips_opts.isa == ISA_MIPS1);
7055 macro_build (&offset_expr, "lwc1", "T,o(b)",
7056 target_big_endian ? treg + 1 : treg, r, breg);
7057 /* FIXME: A possible overflow which I don't know how to deal
7059 offset_expr.X_add_number += 4;
7060 macro_build (&offset_expr, "lwc1", "T,o(b)",
7061 target_big_endian ? treg : treg + 1, r, breg);
7066 * The MIPS assembler seems to check for X_add_number not
7067 * being double aligned and generating:
7070 * addiu at,at,%lo(foo+1)
7073 * But, the resulting address is the same after relocation so why
7074 * generate the extra instruction?
7076 /* Itbl support may require additional care here. */
7078 if (mips_opts.isa != ISA_MIPS1)
7089 if (mips_opts.isa != ISA_MIPS1)
7097 /* Itbl support may require additional care here. */
7102 if (HAVE_64BIT_GPRS)
7113 if (HAVE_64BIT_GPRS)
7123 if (offset_expr.X_op != O_symbol
7124 && offset_expr.X_op != O_constant)
7126 as_bad (_("expression too complex"));
7127 offset_expr.X_op = O_constant;
7130 if (HAVE_32BIT_ADDRESSES
7131 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7135 sprintf_vma (value, offset_expr.X_add_number);
7136 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7139 /* Even on a big endian machine $fn comes before $fn+1. We have
7140 to adjust when loading from memory. We set coproc if we must
7141 load $fn+1 first. */
7142 /* Itbl support may require additional care here. */
7143 if (! target_big_endian)
7146 if (mips_pic == NO_PIC
7147 || offset_expr.X_op == O_constant)
7149 /* If this is a reference to a GP relative symbol, we want
7150 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7151 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7152 If we have a base register, we use this
7154 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7155 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7156 If this is not a GP relative symbol, we want
7157 lui $at,<sym> (BFD_RELOC_HI16_S)
7158 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7159 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7160 If there is a base register, we add it to $at after the
7161 lui instruction. If there is a constant, we always use
7163 if (offset_expr.X_op == O_symbol
7164 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7165 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7167 relax_start (offset_expr.X_add_symbol);
7170 tempreg = mips_gp_register;
7174 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7175 AT, breg, mips_gp_register);
7180 /* Itbl support may require additional care here. */
7181 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7182 BFD_RELOC_GPREL16, tempreg);
7183 offset_expr.X_add_number += 4;
7185 /* Set mips_optimize to 2 to avoid inserting an
7187 hold_mips_optimize = mips_optimize;
7189 /* Itbl support may require additional care here. */
7190 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7191 BFD_RELOC_GPREL16, tempreg);
7192 mips_optimize = hold_mips_optimize;
7196 /* We just generated two relocs. When tc_gen_reloc
7197 handles this case, it will skip the first reloc and
7198 handle the second. The second reloc already has an
7199 extra addend of 4, which we added above. We must
7200 subtract it out, and then subtract another 4 to make
7201 the first reloc come out right. The second reloc
7202 will come out right because we are going to add 4 to
7203 offset_expr when we build its instruction below.
7205 If we have a symbol, then we don't want to include
7206 the offset, because it will wind up being included
7207 when we generate the reloc. */
7209 if (offset_expr.X_op == O_constant)
7210 offset_expr.X_add_number -= 8;
7213 offset_expr.X_add_number = -4;
7214 offset_expr.X_op = O_constant;
7218 macro_build_lui (&offset_expr, AT);
7220 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7221 /* Itbl support may require additional care here. */
7222 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7223 BFD_RELOC_LO16, AT);
7224 /* FIXME: How do we handle overflow here? */
7225 offset_expr.X_add_number += 4;
7226 /* Itbl support may require additional care here. */
7227 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7228 BFD_RELOC_LO16, AT);
7229 if (mips_relax.sequence)
7232 else if (!mips_big_got)
7234 /* If this is a reference to an external symbol, we want
7235 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7240 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7242 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7243 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7244 If there is a base register we add it to $at before the
7245 lwc1 instructions. If there is a constant we include it
7246 in the lwc1 instructions. */
7248 expr1.X_add_number = offset_expr.X_add_number;
7249 if (expr1.X_add_number < -0x8000
7250 || expr1.X_add_number >= 0x8000 - 4)
7251 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7252 load_got_offset (AT, &offset_expr);
7255 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7257 /* Set mips_optimize to 2 to avoid inserting an undesired
7259 hold_mips_optimize = mips_optimize;
7262 /* Itbl support may require additional care here. */
7263 relax_start (offset_expr.X_add_symbol);
7264 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7265 BFD_RELOC_LO16, AT);
7266 expr1.X_add_number += 4;
7267 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7268 BFD_RELOC_LO16, AT);
7270 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7271 BFD_RELOC_LO16, AT);
7272 offset_expr.X_add_number += 4;
7273 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7274 BFD_RELOC_LO16, AT);
7277 mips_optimize = hold_mips_optimize;
7279 else if (mips_big_got)
7283 /* If this is a reference to an external symbol, we want
7284 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7286 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7291 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7293 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7294 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7295 If there is a base register we add it to $at before the
7296 lwc1 instructions. If there is a constant we include it
7297 in the lwc1 instructions. */
7299 expr1.X_add_number = offset_expr.X_add_number;
7300 offset_expr.X_add_number = 0;
7301 if (expr1.X_add_number < -0x8000
7302 || expr1.X_add_number >= 0x8000 - 4)
7303 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7304 gpdelay = reg_needs_delay (mips_gp_register);
7305 relax_start (offset_expr.X_add_symbol);
7306 macro_build (&offset_expr, "lui", "t,u",
7307 AT, BFD_RELOC_MIPS_GOT_HI16);
7308 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7309 AT, AT, mips_gp_register);
7310 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7311 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7314 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7315 /* Itbl support may require additional care here. */
7316 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7317 BFD_RELOC_LO16, AT);
7318 expr1.X_add_number += 4;
7320 /* Set mips_optimize to 2 to avoid inserting an undesired
7322 hold_mips_optimize = mips_optimize;
7324 /* Itbl support may require additional care here. */
7325 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7326 BFD_RELOC_LO16, AT);
7327 mips_optimize = hold_mips_optimize;
7328 expr1.X_add_number -= 4;
7331 offset_expr.X_add_number = expr1.X_add_number;
7333 macro_build (NULL, "nop", "");
7334 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7335 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7338 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7339 /* Itbl support may require additional care here. */
7340 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7341 BFD_RELOC_LO16, AT);
7342 offset_expr.X_add_number += 4;
7344 /* Set mips_optimize to 2 to avoid inserting an undesired
7346 hold_mips_optimize = mips_optimize;
7348 /* Itbl support may require additional care here. */
7349 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7350 BFD_RELOC_LO16, AT);
7351 mips_optimize = hold_mips_optimize;
7365 gas_assert (HAVE_32BIT_ADDRESSES);
7366 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7367 offset_expr.X_add_number += 4;
7368 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
7371 /* New code added to support COPZ instructions.
7372 This code builds table entries out of the macros in mip_opcodes.
7373 R4000 uses interlocks to handle coproc delays.
7374 Other chips (like the R3000) require nops to be inserted for delays.
7376 FIXME: Currently, we require that the user handle delays.
7377 In order to fill delay slots for non-interlocked chips,
7378 we must have a way to specify delays based on the coprocessor.
7379 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7380 What are the side-effects of the cop instruction?
7381 What cache support might we have and what are its effects?
7382 Both coprocessor & memory require delays. how long???
7383 What registers are read/set/modified?
7385 If an itbl is provided to interpret cop instructions,
7386 this knowledge can be encoded in the itbl spec. */
7400 if (NO_ISA_COP (mips_opts.arch)
7401 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7403 as_bad (_("opcode not supported on this processor: %s"),
7404 mips_cpu_info_from_arch (mips_opts.arch)->name);
7408 /* For now we just do C (same as Cz). The parameter will be
7409 stored in insn_opcode by mips_ip. */
7410 macro_build (NULL, s, "C", ip->insn_opcode);
7414 move_register (dreg, sreg);
7417 #ifdef LOSING_COMPILER
7419 /* Try and see if this is a new itbl instruction.
7420 This code builds table entries out of the macros in mip_opcodes.
7421 FIXME: For now we just assemble the expression and pass it's
7422 value along as a 32-bit immediate.
7423 We may want to have the assembler assemble this value,
7424 so that we gain the assembler's knowledge of delay slots,
7426 Would it be more efficient to use mask (id) here? */
7427 if (itbl_have_entries
7428 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
7430 s = ip->insn_mo->name;
7432 coproc = ITBL_DECODE_PNUM (immed_expr);;
7433 macro_build (&immed_expr, s, "C");
7439 if (!mips_opts.at && used_at)
7440 as_bad (_("Macro used $at after \".set noat\""));
7444 macro2 (struct mips_cl_insn *ip)
7446 unsigned int treg, sreg, dreg, breg;
7447 unsigned int tempreg;
7461 bfd_reloc_code_real_type r;
7463 treg = (ip->insn_opcode >> 16) & 0x1f;
7464 dreg = (ip->insn_opcode >> 11) & 0x1f;
7465 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
7466 mask = ip->insn_mo->mask;
7468 expr1.X_op = O_constant;
7469 expr1.X_op_symbol = NULL;
7470 expr1.X_add_symbol = NULL;
7471 expr1.X_add_number = 1;
7475 #endif /* LOSING_COMPILER */
7480 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7481 macro_build (NULL, "mflo", "d", dreg);
7487 /* The MIPS assembler some times generates shifts and adds. I'm
7488 not trying to be that fancy. GCC should do this for us
7491 load_register (AT, &imm_expr, dbl);
7492 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7493 macro_build (NULL, "mflo", "d", dreg);
7509 load_register (AT, &imm_expr, dbl);
7510 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7511 macro_build (NULL, "mflo", "d", dreg);
7512 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7513 macro_build (NULL, "mfhi", "d", AT);
7515 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7518 expr1.X_add_number = 8;
7519 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7520 macro_build (NULL, "nop", "", 0);
7521 macro_build (NULL, "break", "c", 6);
7524 macro_build (NULL, "mflo", "d", dreg);
7540 load_register (AT, &imm_expr, dbl);
7541 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7542 sreg, imm ? AT : treg);
7543 macro_build (NULL, "mfhi", "d", AT);
7544 macro_build (NULL, "mflo", "d", dreg);
7546 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7549 expr1.X_add_number = 8;
7550 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7551 macro_build (NULL, "nop", "", 0);
7552 macro_build (NULL, "break", "c", 6);
7558 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7569 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7570 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7574 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7575 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7576 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7577 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7581 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7592 macro_build (NULL, "negu", "d,w", tempreg, treg);
7593 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7597 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7598 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7599 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7600 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7609 if (imm_expr.X_op != O_constant)
7610 as_bad (_("Improper rotate count"));
7611 rot = imm_expr.X_add_number & 0x3f;
7612 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7614 rot = (64 - rot) & 0x3f;
7616 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7618 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7623 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7626 l = (rot < 0x20) ? "dsll" : "dsll32";
7627 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7630 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7631 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7632 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7640 if (imm_expr.X_op != O_constant)
7641 as_bad (_("Improper rotate count"));
7642 rot = imm_expr.X_add_number & 0x1f;
7643 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7645 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7650 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7654 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7655 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7656 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7661 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7663 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7667 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7668 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7669 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7670 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7674 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7676 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7680 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7681 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7682 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7683 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7692 if (imm_expr.X_op != O_constant)
7693 as_bad (_("Improper rotate count"));
7694 rot = imm_expr.X_add_number & 0x3f;
7695 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7698 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7700 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7705 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7708 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7709 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7712 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7713 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7714 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7722 if (imm_expr.X_op != O_constant)
7723 as_bad (_("Improper rotate count"));
7724 rot = imm_expr.X_add_number & 0x1f;
7725 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7727 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7732 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7736 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7737 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7738 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7743 gas_assert (mips_opts.isa == ISA_MIPS1);
7744 /* Even on a big endian machine $fn comes before $fn+1. We have
7745 to adjust when storing to memory. */
7746 macro_build (&offset_expr, "swc1", "T,o(b)",
7747 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7748 offset_expr.X_add_number += 4;
7749 macro_build (&offset_expr, "swc1", "T,o(b)",
7750 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7755 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7757 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7760 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7761 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7766 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7768 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7773 as_warn (_("Instruction %s: result is always false"),
7775 move_register (dreg, 0);
7778 if (CPU_HAS_SEQ (mips_opts.arch)
7779 && -512 <= imm_expr.X_add_number
7780 && imm_expr.X_add_number < 512)
7782 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7783 (int) imm_expr.X_add_number);
7786 if (imm_expr.X_op == O_constant
7787 && imm_expr.X_add_number >= 0
7788 && imm_expr.X_add_number < 0x10000)
7790 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7792 else if (imm_expr.X_op == O_constant
7793 && imm_expr.X_add_number > -0x8000
7794 && imm_expr.X_add_number < 0)
7796 imm_expr.X_add_number = -imm_expr.X_add_number;
7797 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7798 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7800 else if (CPU_HAS_SEQ (mips_opts.arch))
7803 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7804 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7809 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7810 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7813 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7816 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7822 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7823 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7826 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7828 if (imm_expr.X_op == O_constant
7829 && imm_expr.X_add_number >= -0x8000
7830 && imm_expr.X_add_number < 0x8000)
7832 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7833 dreg, sreg, BFD_RELOC_LO16);
7837 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7838 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7842 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7845 case M_SGT: /* sreg > treg <==> treg < sreg */
7851 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7854 case M_SGT_I: /* sreg > I <==> I < sreg */
7861 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7862 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7865 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7871 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7872 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7875 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7882 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7883 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7884 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7888 if (imm_expr.X_op == O_constant
7889 && imm_expr.X_add_number >= -0x8000
7890 && imm_expr.X_add_number < 0x8000)
7892 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7896 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7897 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7901 if (imm_expr.X_op == O_constant
7902 && imm_expr.X_add_number >= -0x8000
7903 && imm_expr.X_add_number < 0x8000)
7905 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7910 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7911 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7916 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7918 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7921 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7922 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7927 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7929 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7934 as_warn (_("Instruction %s: result is always true"),
7936 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7937 dreg, 0, BFD_RELOC_LO16);
7940 if (CPU_HAS_SEQ (mips_opts.arch)
7941 && -512 <= imm_expr.X_add_number
7942 && imm_expr.X_add_number < 512)
7944 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
7945 (int) imm_expr.X_add_number);
7948 if (imm_expr.X_op == O_constant
7949 && imm_expr.X_add_number >= 0
7950 && imm_expr.X_add_number < 0x10000)
7952 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7954 else if (imm_expr.X_op == O_constant
7955 && imm_expr.X_add_number > -0x8000
7956 && imm_expr.X_add_number < 0)
7958 imm_expr.X_add_number = -imm_expr.X_add_number;
7959 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7960 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7962 else if (CPU_HAS_SEQ (mips_opts.arch))
7965 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7966 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
7971 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7972 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7975 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7981 if (imm_expr.X_op == O_constant
7982 && imm_expr.X_add_number > -0x8000
7983 && imm_expr.X_add_number <= 0x8000)
7985 imm_expr.X_add_number = -imm_expr.X_add_number;
7986 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7987 dreg, sreg, BFD_RELOC_LO16);
7991 load_register (AT, &imm_expr, dbl);
7992 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7998 if (imm_expr.X_op == O_constant
7999 && imm_expr.X_add_number > -0x8000
8000 && imm_expr.X_add_number <= 0x8000)
8002 imm_expr.X_add_number = -imm_expr.X_add_number;
8003 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8004 dreg, sreg, BFD_RELOC_LO16);
8008 load_register (AT, &imm_expr, dbl);
8009 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8031 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8032 macro_build (NULL, s, "s,t", sreg, AT);
8037 gas_assert (mips_opts.isa == ISA_MIPS1);
8039 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8040 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8043 * Is the double cfc1 instruction a bug in the mips assembler;
8044 * or is there a reason for it?
8047 macro_build (NULL, "cfc1", "t,G", treg, RA);
8048 macro_build (NULL, "cfc1", "t,G", treg, RA);
8049 macro_build (NULL, "nop", "");
8050 expr1.X_add_number = 3;
8051 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8052 expr1.X_add_number = 2;
8053 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8054 macro_build (NULL, "ctc1", "t,G", AT, RA);
8055 macro_build (NULL, "nop", "");
8056 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8058 macro_build (NULL, "ctc1", "t,G", treg, RA);
8059 macro_build (NULL, "nop", "");
8070 if (offset_expr.X_add_number >= 0x7fff)
8071 as_bad (_("operand overflow"));
8072 if (! target_big_endian)
8073 ++offset_expr.X_add_number;
8074 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8075 if (! target_big_endian)
8076 --offset_expr.X_add_number;
8078 ++offset_expr.X_add_number;
8079 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8080 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8081 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8094 if (offset_expr.X_add_number >= 0x8000 - off)
8095 as_bad (_("operand overflow"));
8103 if (! target_big_endian)
8104 offset_expr.X_add_number += off;
8105 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8106 if (! target_big_endian)
8107 offset_expr.X_add_number -= off;
8109 offset_expr.X_add_number += off;
8110 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8112 /* If necessary, move the result in tempreg the final destination. */
8113 if (treg == tempreg)
8115 /* Protect second load's delay slot. */
8117 move_register (treg, tempreg);
8131 load_address (AT, &offset_expr, &used_at);
8133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8134 if (! target_big_endian)
8135 expr1.X_add_number = off;
8137 expr1.X_add_number = 0;
8138 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8139 if (! target_big_endian)
8140 expr1.X_add_number = 0;
8142 expr1.X_add_number = off;
8143 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8149 load_address (AT, &offset_expr, &used_at);
8151 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8152 if (target_big_endian)
8153 expr1.X_add_number = 0;
8154 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8155 treg, BFD_RELOC_LO16, AT);
8156 if (target_big_endian)
8157 expr1.X_add_number = 1;
8159 expr1.X_add_number = 0;
8160 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8161 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8162 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8167 if (offset_expr.X_add_number >= 0x7fff)
8168 as_bad (_("operand overflow"));
8169 if (target_big_endian)
8170 ++offset_expr.X_add_number;
8171 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8172 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8173 if (target_big_endian)
8174 --offset_expr.X_add_number;
8176 ++offset_expr.X_add_number;
8177 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8190 if (offset_expr.X_add_number >= 0x8000 - off)
8191 as_bad (_("operand overflow"));
8192 if (! target_big_endian)
8193 offset_expr.X_add_number += off;
8194 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8195 if (! target_big_endian)
8196 offset_expr.X_add_number -= off;
8198 offset_expr.X_add_number += off;
8199 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8213 load_address (AT, &offset_expr, &used_at);
8215 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8216 if (! target_big_endian)
8217 expr1.X_add_number = off;
8219 expr1.X_add_number = 0;
8220 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8221 if (! target_big_endian)
8222 expr1.X_add_number = 0;
8224 expr1.X_add_number = off;
8225 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8230 load_address (AT, &offset_expr, &used_at);
8232 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8233 if (! target_big_endian)
8234 expr1.X_add_number = 0;
8235 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8236 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8237 if (! target_big_endian)
8238 expr1.X_add_number = 1;
8240 expr1.X_add_number = 0;
8241 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8242 if (! target_big_endian)
8243 expr1.X_add_number = 0;
8245 expr1.X_add_number = 1;
8246 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8247 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8248 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8252 /* FIXME: Check if this is one of the itbl macros, since they
8253 are added dynamically. */
8254 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8257 if (!mips_opts.at && used_at)
8258 as_bad (_("Macro used $at after \".set noat\""));
8261 /* Implement macros in mips16 mode. */
8264 mips16_macro (struct mips_cl_insn *ip)
8267 int xreg, yreg, zreg, tmp;
8270 const char *s, *s2, *s3;
8272 mask = ip->insn_mo->mask;
8274 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8275 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8276 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8278 expr1.X_op = O_constant;
8279 expr1.X_op_symbol = NULL;
8280 expr1.X_add_symbol = NULL;
8281 expr1.X_add_number = 1;
8301 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8302 expr1.X_add_number = 2;
8303 macro_build (&expr1, "bnez", "x,p", yreg);
8304 macro_build (NULL, "break", "6", 7);
8306 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8307 since that causes an overflow. We should do that as well,
8308 but I don't see how to do the comparisons without a temporary
8311 macro_build (NULL, s, "x", zreg);
8331 macro_build (NULL, s, "0,x,y", xreg, yreg);
8332 expr1.X_add_number = 2;
8333 macro_build (&expr1, "bnez", "x,p", yreg);
8334 macro_build (NULL, "break", "6", 7);
8336 macro_build (NULL, s2, "x", zreg);
8342 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8343 macro_build (NULL, "mflo", "x", zreg);
8351 if (imm_expr.X_op != O_constant)
8352 as_bad (_("Unsupported large constant"));
8353 imm_expr.X_add_number = -imm_expr.X_add_number;
8354 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8358 if (imm_expr.X_op != O_constant)
8359 as_bad (_("Unsupported large constant"));
8360 imm_expr.X_add_number = -imm_expr.X_add_number;
8361 macro_build (&imm_expr, "addiu", "x,k", xreg);
8365 if (imm_expr.X_op != O_constant)
8366 as_bad (_("Unsupported large constant"));
8367 imm_expr.X_add_number = -imm_expr.X_add_number;
8368 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8390 goto do_reverse_branch;
8394 goto do_reverse_branch;
8406 goto do_reverse_branch;
8417 macro_build (NULL, s, "x,y", xreg, yreg);
8418 macro_build (&offset_expr, s2, "p");
8445 goto do_addone_branch_i;
8450 goto do_addone_branch_i;
8465 goto do_addone_branch_i;
8472 if (imm_expr.X_op != O_constant)
8473 as_bad (_("Unsupported large constant"));
8474 ++imm_expr.X_add_number;
8477 macro_build (&imm_expr, s, s3, xreg);
8478 macro_build (&offset_expr, s2, "p");
8482 expr1.X_add_number = 0;
8483 macro_build (&expr1, "slti", "x,8", yreg);
8485 move_register (xreg, yreg);
8486 expr1.X_add_number = 2;
8487 macro_build (&expr1, "bteqz", "p");
8488 macro_build (NULL, "neg", "x,w", xreg, xreg);
8492 /* For consistency checking, verify that all bits are specified either
8493 by the match/mask part of the instruction definition, or by the
8496 validate_mips_insn (const struct mips_opcode *opc)
8498 const char *p = opc->args;
8500 unsigned long used_bits = opc->mask;
8502 if ((used_bits & opc->match) != opc->match)
8504 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8505 opc->name, opc->args);
8508 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8518 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8519 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8520 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8521 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8522 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8523 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8524 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8525 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8526 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8527 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8528 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8529 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8530 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8532 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8533 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8534 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8535 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8536 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8537 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8538 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8539 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8540 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8541 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8544 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8545 c, opc->name, opc->args);
8549 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8550 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8552 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8553 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8554 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8555 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8557 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8558 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8560 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8561 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8563 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8564 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8565 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8566 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8567 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8568 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8569 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8570 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8571 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8572 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8573 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8574 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8575 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8576 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8577 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8578 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8579 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8581 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8582 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8583 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8584 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8586 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8587 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8588 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8589 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8590 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8591 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8592 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8593 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8594 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8597 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8598 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8599 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8600 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8601 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8604 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8605 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8606 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8607 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8608 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8609 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8610 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8611 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8612 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8613 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8614 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8615 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8616 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8617 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8618 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8619 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8620 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8621 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8623 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8624 c, opc->name, opc->args);
8628 if (used_bits != 0xffffffff)
8630 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8631 ~used_bits & 0xffffffff, opc->name, opc->args);
8637 /* UDI immediates. */
8645 static const struct mips_immed mips_immed[] = {
8646 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8647 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8648 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8649 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8653 /* Check whether an odd floating-point register is allowed. */
8655 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8657 const char *s = insn->name;
8659 if (insn->pinfo == INSN_MACRO)
8660 /* Let a macro pass, we'll catch it later when it is expanded. */
8663 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8665 /* Allow odd registers for single-precision ops. */
8666 switch (insn->pinfo & (FP_S | FP_D))
8670 return 1; /* both single precision - ok */
8672 return 0; /* both double precision - fail */
8677 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8678 s = strchr (insn->name, '.');
8680 s = s != NULL ? strchr (s + 1, '.') : NULL;
8681 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8684 /* Single-precision coprocessor loads and moves are OK too. */
8685 if ((insn->pinfo & FP_S)
8686 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8687 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8693 /* This routine assembles an instruction into its binary format. As a
8694 side effect, it sets one of the global variables imm_reloc or
8695 offset_reloc to the type of relocation to do if one of the operands
8696 is an address expression. */
8699 mips_ip (char *str, struct mips_cl_insn *ip)
8704 struct mips_opcode *insn;
8707 unsigned int lastregno = 0;
8708 unsigned int lastpos = 0;
8709 unsigned int limlo, limhi;
8712 offsetT min_range, max_range;
8718 /* If the instruction contains a '.', we first try to match an instruction
8719 including the '.'. Then we try again without the '.'. */
8721 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8724 /* If we stopped on whitespace, then replace the whitespace with null for
8725 the call to hash_find. Save the character we replaced just in case we
8726 have to re-parse the instruction. */
8733 insn = (struct mips_opcode *) hash_find (op_hash, str);
8735 /* If we didn't find the instruction in the opcode table, try again, but
8736 this time with just the instruction up to, but not including the
8740 /* Restore the character we overwrite above (if any). */
8744 /* Scan up to the first '.' or whitespace. */
8746 *s != '\0' && *s != '.' && !ISSPACE (*s);
8750 /* If we did not find a '.', then we can quit now. */
8753 insn_error = _("unrecognized opcode");
8757 /* Lookup the instruction in the hash table. */
8759 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8761 insn_error = _("unrecognized opcode");
8771 gas_assert (strcmp (insn->name, str) == 0);
8773 ok = is_opcode_valid (insn);
8776 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8777 && strcmp (insn->name, insn[1].name) == 0)
8786 static char buf[100];
8788 _("opcode not supported on this processor: %s (%s)"),
8789 mips_cpu_info_from_arch (mips_opts.arch)->name,
8790 mips_cpu_info_from_isa (mips_opts.isa)->name);
8799 create_insn (ip, insn);
8802 lastregno = 0xffffffff;
8803 for (args = insn->args;; ++args)
8807 s += strspn (s, " \t");
8811 case '\0': /* end of args */
8816 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8817 my_getExpression (&imm_expr, s);
8818 check_absolute_expr (ip, &imm_expr);
8819 if ((unsigned long) imm_expr.X_add_number != 1
8820 && (unsigned long) imm_expr.X_add_number != 3)
8822 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8823 (unsigned long) imm_expr.X_add_number);
8825 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8826 imm_expr.X_op = O_absent;
8830 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8831 my_getExpression (&imm_expr, s);
8832 check_absolute_expr (ip, &imm_expr);
8833 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8835 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8836 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8838 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8839 imm_expr.X_op = O_absent;
8843 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8844 my_getExpression (&imm_expr, s);
8845 check_absolute_expr (ip, &imm_expr);
8846 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8848 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8849 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8851 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8852 imm_expr.X_op = O_absent;
8856 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8857 my_getExpression (&imm_expr, s);
8858 check_absolute_expr (ip, &imm_expr);
8859 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8861 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8862 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8864 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8865 imm_expr.X_op = O_absent;
8869 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8870 my_getExpression (&imm_expr, s);
8871 check_absolute_expr (ip, &imm_expr);
8872 if (imm_expr.X_add_number & ~OP_MASK_RS)
8874 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8875 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8877 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8878 imm_expr.X_op = O_absent;
8882 case '7': /* four dsp accumulators in bits 11,12 */
8883 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8884 s[3] >= '0' && s[3] <= '3')
8888 INSERT_OPERAND (DSPACC, *ip, regno);
8892 as_bad (_("Invalid dsp acc register"));
8895 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8896 my_getExpression (&imm_expr, s);
8897 check_absolute_expr (ip, &imm_expr);
8898 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8900 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8902 (unsigned long) imm_expr.X_add_number);
8904 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8905 imm_expr.X_op = O_absent;
8909 case '9': /* four dsp accumulators in bits 21,22 */
8910 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8911 s[3] >= '0' && s[3] <= '3')
8915 INSERT_OPERAND (DSPACC_S, *ip, regno);
8919 as_bad (_("Invalid dsp acc register"));
8922 case '0': /* dsp 6-bit signed immediate in bit 20 */
8923 my_getExpression (&imm_expr, s);
8924 check_absolute_expr (ip, &imm_expr);
8925 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8926 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8927 if (imm_expr.X_add_number < min_range ||
8928 imm_expr.X_add_number > max_range)
8930 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8931 (long) min_range, (long) max_range,
8932 (long) imm_expr.X_add_number);
8934 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8935 imm_expr.X_op = O_absent;
8939 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8940 my_getExpression (&imm_expr, s);
8941 check_absolute_expr (ip, &imm_expr);
8942 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8944 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8946 (unsigned long) imm_expr.X_add_number);
8948 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8949 imm_expr.X_op = O_absent;
8953 case ':': /* dsp 7-bit signed immediate in bit 19 */
8954 my_getExpression (&imm_expr, s);
8955 check_absolute_expr (ip, &imm_expr);
8956 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8957 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8958 if (imm_expr.X_add_number < min_range ||
8959 imm_expr.X_add_number > max_range)
8961 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8962 (long) min_range, (long) max_range,
8963 (long) imm_expr.X_add_number);
8965 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8966 imm_expr.X_op = O_absent;
8970 case '@': /* dsp 10-bit signed immediate in bit 16 */
8971 my_getExpression (&imm_expr, s);
8972 check_absolute_expr (ip, &imm_expr);
8973 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8974 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8975 if (imm_expr.X_add_number < min_range ||
8976 imm_expr.X_add_number > max_range)
8978 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8979 (long) min_range, (long) max_range,
8980 (long) imm_expr.X_add_number);
8982 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8983 imm_expr.X_op = O_absent;
8987 case '!': /* MT usermode flag bit. */
8988 my_getExpression (&imm_expr, s);
8989 check_absolute_expr (ip, &imm_expr);
8990 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8991 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8992 (unsigned long) imm_expr.X_add_number);
8993 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8994 imm_expr.X_op = O_absent;
8998 case '$': /* MT load high flag bit. */
8999 my_getExpression (&imm_expr, s);
9000 check_absolute_expr (ip, &imm_expr);
9001 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9002 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9003 (unsigned long) imm_expr.X_add_number);
9004 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9005 imm_expr.X_op = O_absent;
9009 case '*': /* four dsp accumulators in bits 18,19 */
9010 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9011 s[3] >= '0' && s[3] <= '3')
9015 INSERT_OPERAND (MTACC_T, *ip, regno);
9019 as_bad (_("Invalid dsp/smartmips acc register"));
9022 case '&': /* four dsp accumulators in bits 13,14 */
9023 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9024 s[3] >= '0' && s[3] <= '3')
9028 INSERT_OPERAND (MTACC_D, *ip, regno);
9032 as_bad (_("Invalid dsp/smartmips acc register"));
9044 INSERT_OPERAND (RS, *ip, lastregno);
9048 INSERT_OPERAND (RT, *ip, lastregno);
9052 INSERT_OPERAND (FT, *ip, lastregno);
9056 INSERT_OPERAND (FS, *ip, lastregno);
9062 /* Handle optional base register.
9063 Either the base register is omitted or
9064 we must have a left paren. */
9065 /* This is dependent on the next operand specifier
9066 is a base register specification. */
9067 gas_assert (args[1] == 'b' || args[1] == '5'
9068 || args[1] == '-' || args[1] == '4');
9072 case ')': /* these must match exactly */
9079 case '+': /* Opcode extension character. */
9082 case '1': /* UDI immediates. */
9087 const struct mips_immed *imm = mips_immed;
9089 while (imm->type && imm->type != *args)
9093 my_getExpression (&imm_expr, s);
9094 check_absolute_expr (ip, &imm_expr);
9095 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9097 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9098 imm->desc ? imm->desc : ip->insn_mo->name,
9099 (unsigned long) imm_expr.X_add_number,
9100 (unsigned long) imm_expr.X_add_number);
9101 imm_expr.X_add_number &= imm->mask;
9103 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9105 imm_expr.X_op = O_absent;
9110 case 'A': /* ins/ext position, becomes LSB. */
9119 my_getExpression (&imm_expr, s);
9120 check_absolute_expr (ip, &imm_expr);
9121 if ((unsigned long) imm_expr.X_add_number < limlo
9122 || (unsigned long) imm_expr.X_add_number > limhi)
9124 as_bad (_("Improper position (%lu)"),
9125 (unsigned long) imm_expr.X_add_number);
9126 imm_expr.X_add_number = limlo;
9128 lastpos = imm_expr.X_add_number;
9129 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9130 imm_expr.X_op = O_absent;
9134 case 'B': /* ins size, becomes MSB. */
9143 my_getExpression (&imm_expr, s);
9144 check_absolute_expr (ip, &imm_expr);
9145 /* Check for negative input so that small negative numbers
9146 will not succeed incorrectly. The checks against
9147 (pos+size) transitively check "size" itself,
9148 assuming that "pos" is reasonable. */
9149 if ((long) imm_expr.X_add_number < 0
9150 || ((unsigned long) imm_expr.X_add_number
9152 || ((unsigned long) imm_expr.X_add_number
9155 as_bad (_("Improper insert size (%lu, position %lu)"),
9156 (unsigned long) imm_expr.X_add_number,
9157 (unsigned long) lastpos);
9158 imm_expr.X_add_number = limlo - lastpos;
9160 INSERT_OPERAND (INSMSB, *ip,
9161 lastpos + imm_expr.X_add_number - 1);
9162 imm_expr.X_op = O_absent;
9166 case 'C': /* ext size, becomes MSBD. */
9179 my_getExpression (&imm_expr, s);
9180 check_absolute_expr (ip, &imm_expr);
9181 /* Check for negative input so that small negative numbers
9182 will not succeed incorrectly. The checks against
9183 (pos+size) transitively check "size" itself,
9184 assuming that "pos" is reasonable. */
9185 if ((long) imm_expr.X_add_number < 0
9186 || ((unsigned long) imm_expr.X_add_number
9188 || ((unsigned long) imm_expr.X_add_number
9191 as_bad (_("Improper extract size (%lu, position %lu)"),
9192 (unsigned long) imm_expr.X_add_number,
9193 (unsigned long) lastpos);
9194 imm_expr.X_add_number = limlo - lastpos;
9196 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9197 imm_expr.X_op = O_absent;
9202 /* +D is for disassembly only; never match. */
9206 /* "+I" is like "I", except that imm2_expr is used. */
9207 my_getExpression (&imm2_expr, s);
9208 if (imm2_expr.X_op != O_big
9209 && imm2_expr.X_op != O_constant)
9210 insn_error = _("absolute expression required");
9211 if (HAVE_32BIT_GPRS)
9212 normalize_constant_expr (&imm2_expr);
9216 case 'T': /* Coprocessor register. */
9217 /* +T is for disassembly only; never match. */
9220 case 't': /* Coprocessor register number. */
9221 if (s[0] == '$' && ISDIGIT (s[1]))
9231 while (ISDIGIT (*s));
9233 as_bad (_("Invalid register number (%d)"), regno);
9236 INSERT_OPERAND (RT, *ip, regno);
9241 as_bad (_("Invalid coprocessor 0 register number"));
9245 /* bbit[01] and bbit[01]32 bit index. Give error if index
9246 is not in the valid range. */
9247 my_getExpression (&imm_expr, s);
9248 check_absolute_expr (ip, &imm_expr);
9249 if ((unsigned) imm_expr.X_add_number > 31)
9251 as_bad (_("Improper bit index (%lu)"),
9252 (unsigned long) imm_expr.X_add_number);
9253 imm_expr.X_add_number = 0;
9255 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9256 imm_expr.X_op = O_absent;
9261 /* bbit[01] bit index when bbit is used but we generate
9262 bbit[01]32 because the index is over 32. Move to the
9263 next candidate if index is not in the valid range. */
9264 my_getExpression (&imm_expr, s);
9265 check_absolute_expr (ip, &imm_expr);
9266 if ((unsigned) imm_expr.X_add_number < 32
9267 || (unsigned) imm_expr.X_add_number > 63)
9269 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9270 imm_expr.X_op = O_absent;
9275 /* cins, cins32, exts and exts32 position field. Give error
9276 if it's not in the valid range. */
9277 my_getExpression (&imm_expr, s);
9278 check_absolute_expr (ip, &imm_expr);
9279 if ((unsigned) imm_expr.X_add_number > 31)
9281 as_bad (_("Improper position (%lu)"),
9282 (unsigned long) imm_expr.X_add_number);
9283 imm_expr.X_add_number = 0;
9285 /* Make the pos explicit to simplify +S. */
9286 lastpos = imm_expr.X_add_number + 32;
9287 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9288 imm_expr.X_op = O_absent;
9293 /* cins, cins32, exts and exts32 position field. Move to
9294 the next candidate if it's not in the valid range. */
9295 my_getExpression (&imm_expr, s);
9296 check_absolute_expr (ip, &imm_expr);
9297 if ((unsigned) imm_expr.X_add_number < 32
9298 || (unsigned) imm_expr.X_add_number > 63)
9300 lastpos = imm_expr.X_add_number;
9301 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9302 imm_expr.X_op = O_absent;
9307 /* cins and exts length-minus-one field. */
9308 my_getExpression (&imm_expr, s);
9309 check_absolute_expr (ip, &imm_expr);
9310 if ((unsigned long) imm_expr.X_add_number > 31)
9312 as_bad (_("Improper size (%lu)"),
9313 (unsigned long) imm_expr.X_add_number);
9314 imm_expr.X_add_number = 0;
9316 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9317 imm_expr.X_op = O_absent;
9322 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9323 length-minus-one field. */
9324 my_getExpression (&imm_expr, s);
9325 check_absolute_expr (ip, &imm_expr);
9326 if ((long) imm_expr.X_add_number < 0
9327 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9329 as_bad (_("Improper size (%lu)"),
9330 (unsigned long) imm_expr.X_add_number);
9331 imm_expr.X_add_number = 0;
9333 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9334 imm_expr.X_op = O_absent;
9339 /* seqi/snei immediate field. */
9340 my_getExpression (&imm_expr, s);
9341 check_absolute_expr (ip, &imm_expr);
9342 if ((long) imm_expr.X_add_number < -512
9343 || (long) imm_expr.X_add_number >= 512)
9345 as_bad (_("Improper immediate (%ld)"),
9346 (long) imm_expr.X_add_number);
9347 imm_expr.X_add_number = 0;
9349 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9350 imm_expr.X_op = O_absent;
9355 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9356 *args, insn->name, insn->args);
9357 /* Further processing is fruitless. */
9362 case '<': /* must be at least one digit */
9364 * According to the manual, if the shift amount is greater
9365 * than 31 or less than 0, then the shift amount should be
9366 * mod 32. In reality the mips assembler issues an error.
9367 * We issue a warning and mask out all but the low 5 bits.
9369 my_getExpression (&imm_expr, s);
9370 check_absolute_expr (ip, &imm_expr);
9371 if ((unsigned long) imm_expr.X_add_number > 31)
9372 as_warn (_("Improper shift amount (%lu)"),
9373 (unsigned long) imm_expr.X_add_number);
9374 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9375 imm_expr.X_op = O_absent;
9379 case '>': /* shift amount minus 32 */
9380 my_getExpression (&imm_expr, s);
9381 check_absolute_expr (ip, &imm_expr);
9382 if ((unsigned long) imm_expr.X_add_number < 32
9383 || (unsigned long) imm_expr.X_add_number > 63)
9385 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9386 imm_expr.X_op = O_absent;
9390 case 'k': /* cache code */
9391 case 'h': /* prefx code */
9392 case '1': /* sync type */
9393 my_getExpression (&imm_expr, s);
9394 check_absolute_expr (ip, &imm_expr);
9395 if ((unsigned long) imm_expr.X_add_number > 31)
9396 as_warn (_("Invalid value for `%s' (%lu)"),
9398 (unsigned long) imm_expr.X_add_number);
9400 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9401 else if (*args == 'h')
9402 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9404 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9405 imm_expr.X_op = O_absent;
9409 case 'c': /* break code */
9410 my_getExpression (&imm_expr, s);
9411 check_absolute_expr (ip, &imm_expr);
9412 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9413 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9415 (unsigned long) imm_expr.X_add_number);
9416 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9417 imm_expr.X_op = O_absent;
9421 case 'q': /* lower break code */
9422 my_getExpression (&imm_expr, s);
9423 check_absolute_expr (ip, &imm_expr);
9424 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9425 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9427 (unsigned long) imm_expr.X_add_number);
9428 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9429 imm_expr.X_op = O_absent;
9433 case 'B': /* 20-bit syscall/break code. */
9434 my_getExpression (&imm_expr, s);
9435 check_absolute_expr (ip, &imm_expr);
9436 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9437 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9439 (unsigned long) imm_expr.X_add_number);
9440 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9441 imm_expr.X_op = O_absent;
9445 case 'C': /* Coprocessor code */
9446 my_getExpression (&imm_expr, s);
9447 check_absolute_expr (ip, &imm_expr);
9448 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9450 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9451 (unsigned long) imm_expr.X_add_number);
9452 imm_expr.X_add_number &= OP_MASK_COPZ;
9454 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9455 imm_expr.X_op = O_absent;
9459 case 'J': /* 19-bit wait code. */
9460 my_getExpression (&imm_expr, s);
9461 check_absolute_expr (ip, &imm_expr);
9462 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9464 as_warn (_("Illegal 19-bit code (%lu)"),
9465 (unsigned long) imm_expr.X_add_number);
9466 imm_expr.X_add_number &= OP_MASK_CODE19;
9468 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9469 imm_expr.X_op = O_absent;
9473 case 'P': /* Performance register. */
9474 my_getExpression (&imm_expr, s);
9475 check_absolute_expr (ip, &imm_expr);
9476 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9477 as_warn (_("Invalid performance register (%lu)"),
9478 (unsigned long) imm_expr.X_add_number);
9479 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9480 imm_expr.X_op = O_absent;
9484 case 'G': /* Coprocessor destination register. */
9485 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9486 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9488 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9489 INSERT_OPERAND (RD, *ip, regno);
9498 case 'b': /* base register */
9499 case 'd': /* destination register */
9500 case 's': /* source register */
9501 case 't': /* target register */
9502 case 'r': /* both target and source */
9503 case 'v': /* both dest and source */
9504 case 'w': /* both dest and target */
9505 case 'E': /* coprocessor target register */
9506 case 'K': /* 'rdhwr' destination register */
9507 case 'x': /* ignore register name */
9508 case 'z': /* must be zero register */
9509 case 'U': /* destination register (clo/clz). */
9510 case 'g': /* coprocessor destination register */
9512 if (*args == 'E' || *args == 'K')
9513 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9516 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9517 if (regno == AT && mips_opts.at)
9519 if (mips_opts.at == ATREG)
9520 as_warn (_("used $at without \".set noat\""));
9522 as_warn (_("used $%u with \".set at=$%u\""),
9523 regno, mips_opts.at);
9533 if (c == 'r' || c == 'v' || c == 'w')
9540 /* 'z' only matches $0. */
9541 if (c == 'z' && regno != 0)
9544 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9546 if (regno == lastregno)
9548 insn_error = _("source and destination must be different");
9551 if (regno == 31 && lastregno == 0xffffffff)
9553 insn_error = _("a destination register must be supplied");
9557 /* Now that we have assembled one operand, we use the args string
9558 * to figure out where it goes in the instruction. */
9565 INSERT_OPERAND (RS, *ip, regno);
9571 INSERT_OPERAND (RD, *ip, regno);
9574 INSERT_OPERAND (RD, *ip, regno);
9575 INSERT_OPERAND (RT, *ip, regno);
9580 INSERT_OPERAND (RT, *ip, regno);
9583 /* This case exists because on the r3000 trunc
9584 expands into a macro which requires a gp
9585 register. On the r6000 or r4000 it is
9586 assembled into a single instruction which
9587 ignores the register. Thus the insn version
9588 is MIPS_ISA2 and uses 'x', and the macro
9589 version is MIPS_ISA1 and uses 't'. */
9592 /* This case is for the div instruction, which
9593 acts differently if the destination argument
9594 is $0. This only matches $0, and is checked
9595 outside the switch. */
9598 /* Itbl operand; not yet implemented. FIXME ?? */
9600 /* What about all other operands like 'i', which
9601 can be specified in the opcode table? */
9610 INSERT_OPERAND (RS, *ip, lastregno);
9613 INSERT_OPERAND (RT, *ip, lastregno);
9618 case 'O': /* MDMX alignment immediate constant. */
9619 my_getExpression (&imm_expr, s);
9620 check_absolute_expr (ip, &imm_expr);
9621 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9622 as_warn (_("Improper align amount (%ld), using low bits"),
9623 (long) imm_expr.X_add_number);
9624 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9625 imm_expr.X_op = O_absent;
9629 case 'Q': /* MDMX vector, element sel, or const. */
9632 /* MDMX Immediate. */
9633 my_getExpression (&imm_expr, s);
9634 check_absolute_expr (ip, &imm_expr);
9635 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9636 as_warn (_("Invalid MDMX Immediate (%ld)"),
9637 (long) imm_expr.X_add_number);
9638 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9639 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9640 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9642 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9643 imm_expr.X_op = O_absent;
9647 /* Not MDMX Immediate. Fall through. */
9648 case 'X': /* MDMX destination register. */
9649 case 'Y': /* MDMX source register. */
9650 case 'Z': /* MDMX target register. */
9652 case 'D': /* floating point destination register */
9653 case 'S': /* floating point source register */
9654 case 'T': /* floating point target register */
9655 case 'R': /* floating point source register */
9660 || (mips_opts.ase_mdmx
9661 && (ip->insn_mo->pinfo & FP_D)
9662 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9663 | INSN_COPROC_MEMORY_DELAY
9664 | INSN_LOAD_COPROC_DELAY
9665 | INSN_LOAD_MEMORY_DELAY
9666 | INSN_STORE_MEMORY))))
9669 if (reg_lookup (&s, rtype, ®no))
9671 if ((regno & 1) != 0
9673 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9674 as_warn (_("Float register should be even, was %d"),
9682 if (c == 'V' || c == 'W')
9693 INSERT_OPERAND (FD, *ip, regno);
9698 INSERT_OPERAND (FS, *ip, regno);
9701 /* This is like 'Z', but also needs to fix the MDMX
9702 vector/scalar select bits. Note that the
9703 scalar immediate case is handled above. */
9706 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9707 int max_el = (is_qh ? 3 : 7);
9709 my_getExpression(&imm_expr, s);
9710 check_absolute_expr (ip, &imm_expr);
9712 if (imm_expr.X_add_number > max_el)
9713 as_bad (_("Bad element selector %ld"),
9714 (long) imm_expr.X_add_number);
9715 imm_expr.X_add_number &= max_el;
9716 ip->insn_opcode |= (imm_expr.X_add_number
9719 imm_expr.X_op = O_absent;
9721 as_warn (_("Expecting ']' found '%s'"), s);
9727 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9728 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9731 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9738 INSERT_OPERAND (FT, *ip, regno);
9741 INSERT_OPERAND (FR, *ip, regno);
9751 INSERT_OPERAND (FS, *ip, lastregno);
9754 INSERT_OPERAND (FT, *ip, lastregno);
9760 my_getExpression (&imm_expr, s);
9761 if (imm_expr.X_op != O_big
9762 && imm_expr.X_op != O_constant)
9763 insn_error = _("absolute expression required");
9764 if (HAVE_32BIT_GPRS)
9765 normalize_constant_expr (&imm_expr);
9770 my_getExpression (&offset_expr, s);
9771 normalize_address_expr (&offset_expr);
9772 *imm_reloc = BFD_RELOC_32;
9785 unsigned char temp[8];
9787 unsigned int length;
9792 /* These only appear as the last operand in an
9793 instruction, and every instruction that accepts
9794 them in any variant accepts them in all variants.
9795 This means we don't have to worry about backing out
9796 any changes if the instruction does not match.
9798 The difference between them is the size of the
9799 floating point constant and where it goes. For 'F'
9800 and 'L' the constant is 64 bits; for 'f' and 'l' it
9801 is 32 bits. Where the constant is placed is based
9802 on how the MIPS assembler does things:
9805 f -- immediate value
9808 The .lit4 and .lit8 sections are only used if
9809 permitted by the -G argument.
9811 The code below needs to know whether the target register
9812 is 32 or 64 bits wide. It relies on the fact 'f' and
9813 'F' are used with GPR-based instructions and 'l' and
9814 'L' are used with FPR-based instructions. */
9816 f64 = *args == 'F' || *args == 'L';
9817 using_gprs = *args == 'F' || *args == 'f';
9819 save_in = input_line_pointer;
9820 input_line_pointer = s;
9821 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
9823 s = input_line_pointer;
9824 input_line_pointer = save_in;
9825 if (err != NULL && *err != '\0')
9827 as_bad (_("Bad floating point constant: %s"), err);
9828 memset (temp, '\0', sizeof temp);
9829 length = f64 ? 8 : 4;
9832 gas_assert (length == (unsigned) (f64 ? 8 : 4));
9836 && (g_switch_value < 4
9837 || (temp[0] == 0 && temp[1] == 0)
9838 || (temp[2] == 0 && temp[3] == 0))))
9840 imm_expr.X_op = O_constant;
9841 if (! target_big_endian)
9842 imm_expr.X_add_number = bfd_getl32 (temp);
9844 imm_expr.X_add_number = bfd_getb32 (temp);
9847 && ! mips_disable_float_construction
9848 /* Constants can only be constructed in GPRs and
9849 copied to FPRs if the GPRs are at least as wide
9850 as the FPRs. Force the constant into memory if
9851 we are using 64-bit FPRs but the GPRs are only
9854 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
9855 && ((temp[0] == 0 && temp[1] == 0)
9856 || (temp[2] == 0 && temp[3] == 0))
9857 && ((temp[4] == 0 && temp[5] == 0)
9858 || (temp[6] == 0 && temp[7] == 0)))
9860 /* The value is simple enough to load with a couple of
9861 instructions. If using 32-bit registers, set
9862 imm_expr to the high order 32 bits and offset_expr to
9863 the low order 32 bits. Otherwise, set imm_expr to
9864 the entire 64 bit constant. */
9865 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
9867 imm_expr.X_op = O_constant;
9868 offset_expr.X_op = O_constant;
9869 if (! target_big_endian)
9871 imm_expr.X_add_number = bfd_getl32 (temp + 4);
9872 offset_expr.X_add_number = bfd_getl32 (temp);
9876 imm_expr.X_add_number = bfd_getb32 (temp);
9877 offset_expr.X_add_number = bfd_getb32 (temp + 4);
9879 if (offset_expr.X_add_number == 0)
9880 offset_expr.X_op = O_absent;
9882 else if (sizeof (imm_expr.X_add_number) > 4)
9884 imm_expr.X_op = O_constant;
9885 if (! target_big_endian)
9886 imm_expr.X_add_number = bfd_getl64 (temp);
9888 imm_expr.X_add_number = bfd_getb64 (temp);
9892 imm_expr.X_op = O_big;
9893 imm_expr.X_add_number = 4;
9894 if (! target_big_endian)
9896 generic_bignum[0] = bfd_getl16 (temp);
9897 generic_bignum[1] = bfd_getl16 (temp + 2);
9898 generic_bignum[2] = bfd_getl16 (temp + 4);
9899 generic_bignum[3] = bfd_getl16 (temp + 6);
9903 generic_bignum[0] = bfd_getb16 (temp + 6);
9904 generic_bignum[1] = bfd_getb16 (temp + 4);
9905 generic_bignum[2] = bfd_getb16 (temp + 2);
9906 generic_bignum[3] = bfd_getb16 (temp);
9912 const char *newname;
9915 /* Switch to the right section. */
9917 subseg = now_subseg;
9920 default: /* unused default case avoids warnings. */
9922 newname = RDATA_SECTION_NAME;
9923 if (g_switch_value >= 8)
9927 newname = RDATA_SECTION_NAME;
9930 gas_assert (g_switch_value >= 4);
9934 new_seg = subseg_new (newname, (subsegT) 0);
9936 bfd_set_section_flags (stdoutput, new_seg,
9941 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9942 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
9943 record_alignment (new_seg, 4);
9945 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9947 as_bad (_("Can't use floating point insn in this section"));
9949 /* Set the argument to the current address in the
9951 offset_expr.X_op = O_symbol;
9952 offset_expr.X_add_symbol =
9953 symbol_new ("L0\001", now_seg,
9954 (valueT) frag_now_fix (), frag_now);
9955 offset_expr.X_add_number = 0;
9957 /* Put the floating point number into the section. */
9958 p = frag_more ((int) length);
9959 memcpy (p, temp, length);
9961 /* Switch back to the original section. */
9962 subseg_set (seg, subseg);
9967 case 'i': /* 16 bit unsigned immediate */
9968 case 'j': /* 16 bit signed immediate */
9969 *imm_reloc = BFD_RELOC_LO16;
9970 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9973 offsetT minval, maxval;
9975 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9976 && strcmp (insn->name, insn[1].name) == 0);
9978 /* If the expression was written as an unsigned number,
9979 only treat it as signed if there are no more
9983 && sizeof (imm_expr.X_add_number) <= 4
9984 && imm_expr.X_op == O_constant
9985 && imm_expr.X_add_number < 0
9986 && imm_expr.X_unsigned
9990 /* For compatibility with older assemblers, we accept
9991 0x8000-0xffff as signed 16-bit numbers when only
9992 signed numbers are allowed. */
9994 minval = 0, maxval = 0xffff;
9996 minval = -0x8000, maxval = 0x7fff;
9998 minval = -0x8000, maxval = 0xffff;
10000 if (imm_expr.X_op != O_constant
10001 || imm_expr.X_add_number < minval
10002 || imm_expr.X_add_number > maxval)
10006 if (imm_expr.X_op == O_constant
10007 || imm_expr.X_op == O_big)
10008 as_bad (_("expression out of range"));
10014 case 'o': /* 16 bit offset */
10015 /* Check whether there is only a single bracketed expression
10016 left. If so, it must be the base register and the
10017 constant must be zero. */
10018 if (*s == '(' && strchr (s + 1, '(') == 0)
10020 offset_expr.X_op = O_constant;
10021 offset_expr.X_add_number = 0;
10025 /* If this value won't fit into a 16 bit offset, then go
10026 find a macro that will generate the 32 bit offset
10028 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10029 && (offset_expr.X_op != O_constant
10030 || offset_expr.X_add_number >= 0x8000
10031 || offset_expr.X_add_number < -0x8000))
10037 case 'p': /* pc relative offset */
10038 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10039 my_getExpression (&offset_expr, s);
10043 case 'u': /* upper 16 bits */
10044 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10045 && imm_expr.X_op == O_constant
10046 && (imm_expr.X_add_number < 0
10047 || imm_expr.X_add_number >= 0x10000))
10048 as_bad (_("lui expression not in range 0..65535"));
10052 case 'a': /* 26 bit address */
10053 my_getExpression (&offset_expr, s);
10055 *offset_reloc = BFD_RELOC_MIPS_JMP;
10058 case 'N': /* 3 bit branch condition code */
10059 case 'M': /* 3 bit compare condition code */
10061 if (ip->insn_mo->pinfo & (FP_D| FP_S))
10062 rtype |= RTYPE_FCC;
10063 if (!reg_lookup (&s, rtype, ®no))
10065 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
10066 || strcmp(str + strlen(str) - 5, "any2f") == 0
10067 || strcmp(str + strlen(str) - 5, "any2t") == 0)
10068 && (regno & 1) != 0)
10069 as_warn (_("Condition code register should be even for %s, was %d"),
10071 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
10072 || strcmp(str + strlen(str) - 5, "any4t") == 0)
10073 && (regno & 3) != 0)
10074 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
10077 INSERT_OPERAND (BCC, *ip, regno);
10079 INSERT_OPERAND (CCC, *ip, regno);
10083 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10094 while (ISDIGIT (*s));
10097 c = 8; /* Invalid sel value. */
10100 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10101 ip->insn_opcode |= c;
10105 /* Must be at least one digit. */
10106 my_getExpression (&imm_expr, s);
10107 check_absolute_expr (ip, &imm_expr);
10109 if ((unsigned long) imm_expr.X_add_number
10110 > (unsigned long) OP_MASK_VECBYTE)
10112 as_bad (_("bad byte vector index (%ld)"),
10113 (long) imm_expr.X_add_number);
10114 imm_expr.X_add_number = 0;
10117 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10118 imm_expr.X_op = O_absent;
10123 my_getExpression (&imm_expr, s);
10124 check_absolute_expr (ip, &imm_expr);
10126 if ((unsigned long) imm_expr.X_add_number
10127 > (unsigned long) OP_MASK_VECALIGN)
10129 as_bad (_("bad byte vector index (%ld)"),
10130 (long) imm_expr.X_add_number);
10131 imm_expr.X_add_number = 0;
10134 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10135 imm_expr.X_op = O_absent;
10140 as_bad (_("bad char = '%c'\n"), *args);
10145 /* Args don't match. */
10146 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10147 !strcmp (insn->name, insn[1].name))
10151 insn_error = _("illegal operands");
10155 *(--argsStart) = save_c;
10156 insn_error = _("illegal operands");
10161 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10163 /* This routine assembles an instruction into its binary format when
10164 assembling for the mips16. As a side effect, it sets one of the
10165 global variables imm_reloc or offset_reloc to the type of
10166 relocation to do if one of the operands is an address expression.
10167 It also sets mips16_small and mips16_ext if the user explicitly
10168 requested a small or extended instruction. */
10171 mips16_ip (char *str, struct mips_cl_insn *ip)
10175 struct mips_opcode *insn;
10177 unsigned int regno;
10178 unsigned int lastregno = 0;
10184 mips16_small = FALSE;
10185 mips16_ext = FALSE;
10187 for (s = str; ISLOWER (*s); ++s)
10199 if (s[1] == 't' && s[2] == ' ')
10202 mips16_small = TRUE;
10206 else if (s[1] == 'e' && s[2] == ' ')
10213 /* Fall through. */
10215 insn_error = _("unknown opcode");
10219 if (mips_opts.noautoextend && ! mips16_ext)
10220 mips16_small = TRUE;
10222 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10224 insn_error = _("unrecognized opcode");
10233 gas_assert (strcmp (insn->name, str) == 0);
10235 ok = is_opcode_valid_16 (insn);
10238 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10239 && strcmp (insn->name, insn[1].name) == 0)
10248 static char buf[100];
10250 _("opcode not supported on this processor: %s (%s)"),
10251 mips_cpu_info_from_arch (mips_opts.arch)->name,
10252 mips_cpu_info_from_isa (mips_opts.isa)->name);
10259 create_insn (ip, insn);
10260 imm_expr.X_op = O_absent;
10261 imm_reloc[0] = BFD_RELOC_UNUSED;
10262 imm_reloc[1] = BFD_RELOC_UNUSED;
10263 imm_reloc[2] = BFD_RELOC_UNUSED;
10264 imm2_expr.X_op = O_absent;
10265 offset_expr.X_op = O_absent;
10266 offset_reloc[0] = BFD_RELOC_UNUSED;
10267 offset_reloc[1] = BFD_RELOC_UNUSED;
10268 offset_reloc[2] = BFD_RELOC_UNUSED;
10269 for (args = insn->args; 1; ++args)
10276 /* In this switch statement we call break if we did not find
10277 a match, continue if we did find a match, or return if we
10286 /* Stuff the immediate value in now, if we can. */
10287 if (imm_expr.X_op == O_constant
10288 && *imm_reloc > BFD_RELOC_UNUSED
10289 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10290 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10291 && insn->pinfo != INSN_MACRO)
10295 switch (*offset_reloc)
10297 case BFD_RELOC_MIPS16_HI16_S:
10298 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10301 case BFD_RELOC_MIPS16_HI16:
10302 tmp = imm_expr.X_add_number >> 16;
10305 case BFD_RELOC_MIPS16_LO16:
10306 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10310 case BFD_RELOC_UNUSED:
10311 tmp = imm_expr.X_add_number;
10317 *offset_reloc = BFD_RELOC_UNUSED;
10319 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10320 tmp, TRUE, mips16_small,
10321 mips16_ext, &ip->insn_opcode,
10322 &ip->use_extend, &ip->extend);
10323 imm_expr.X_op = O_absent;
10324 *imm_reloc = BFD_RELOC_UNUSED;
10338 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10341 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10357 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10359 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10363 /* Fall through. */
10374 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10376 if (c == 'v' || c == 'w')
10379 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10381 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10392 if (c == 'v' || c == 'w')
10394 regno = mips16_to_32_reg_map[lastregno];
10408 regno = mips32_to_16_reg_map[regno];
10413 regno = ILLEGAL_REG;
10418 regno = ILLEGAL_REG;
10423 regno = ILLEGAL_REG;
10428 if (regno == AT && mips_opts.at)
10430 if (mips_opts.at == ATREG)
10431 as_warn (_("used $at without \".set noat\""));
10433 as_warn (_("used $%u with \".set at=$%u\""),
10434 regno, mips_opts.at);
10442 if (regno == ILLEGAL_REG)
10449 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10453 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10456 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10459 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10465 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10468 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10469 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10479 if (strncmp (s, "$pc", 3) == 0)
10496 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10499 if (imm_expr.X_op != O_constant)
10502 ip->use_extend = TRUE;
10507 /* We need to relax this instruction. */
10508 *offset_reloc = *imm_reloc;
10509 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10514 *imm_reloc = BFD_RELOC_UNUSED;
10515 /* Fall through. */
10522 my_getExpression (&imm_expr, s);
10523 if (imm_expr.X_op == O_register)
10525 /* What we thought was an expression turned out to
10528 if (s[0] == '(' && args[1] == '(')
10530 /* It looks like the expression was omitted
10531 before a register indirection, which means
10532 that the expression is implicitly zero. We
10533 still set up imm_expr, so that we handle
10534 explicit extensions correctly. */
10535 imm_expr.X_op = O_constant;
10536 imm_expr.X_add_number = 0;
10537 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10544 /* We need to relax this instruction. */
10545 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10554 /* We use offset_reloc rather than imm_reloc for the PC
10555 relative operands. This lets macros with both
10556 immediate and address operands work correctly. */
10557 my_getExpression (&offset_expr, s);
10559 if (offset_expr.X_op == O_register)
10562 /* We need to relax this instruction. */
10563 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10567 case '6': /* break code */
10568 my_getExpression (&imm_expr, s);
10569 check_absolute_expr (ip, &imm_expr);
10570 if ((unsigned long) imm_expr.X_add_number > 63)
10571 as_warn (_("Invalid value for `%s' (%lu)"),
10573 (unsigned long) imm_expr.X_add_number);
10574 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10575 imm_expr.X_op = O_absent;
10579 case 'a': /* 26 bit address */
10580 my_getExpression (&offset_expr, s);
10582 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10583 ip->insn_opcode <<= 16;
10586 case 'l': /* register list for entry macro */
10587 case 'L': /* register list for exit macro */
10597 unsigned int freg, reg1, reg2;
10599 while (*s == ' ' || *s == ',')
10601 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10603 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10607 as_bad (_("can't parse register list"));
10617 if (!reg_lookup (&s, freg ? RTYPE_FPU
10618 : (RTYPE_GP | RTYPE_NUM), ®2))
10620 as_bad (_("invalid register list"));
10624 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10626 mask &= ~ (7 << 3);
10629 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10631 mask &= ~ (7 << 3);
10634 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10635 mask |= (reg2 - 3) << 3;
10636 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10637 mask |= (reg2 - 15) << 1;
10638 else if (reg1 == RA && reg2 == RA)
10642 as_bad (_("invalid register list"));
10646 /* The mask is filled in in the opcode table for the
10647 benefit of the disassembler. We remove it before
10648 applying the actual mask. */
10649 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10650 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10654 case 'm': /* Register list for save insn. */
10655 case 'M': /* Register list for restore insn. */
10658 int framesz = 0, seen_framesz = 0;
10659 int nargs = 0, statics = 0, sregs = 0;
10663 unsigned int reg1, reg2;
10665 SKIP_SPACE_TABS (s);
10668 SKIP_SPACE_TABS (s);
10670 my_getExpression (&imm_expr, s);
10671 if (imm_expr.X_op == O_constant)
10673 /* Handle the frame size. */
10676 as_bad (_("more than one frame size in list"));
10680 framesz = imm_expr.X_add_number;
10681 imm_expr.X_op = O_absent;
10686 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10688 as_bad (_("can't parse register list"));
10700 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10703 as_bad (_("can't parse register list"));
10708 while (reg1 <= reg2)
10710 if (reg1 >= 4 && reg1 <= 7)
10714 nargs |= 1 << (reg1 - 4);
10716 /* statics $a0-$a3 */
10717 statics |= 1 << (reg1 - 4);
10719 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10722 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10724 else if (reg1 == 31)
10726 /* Add $ra to insn. */
10731 as_bad (_("unexpected register in list"));
10739 /* Encode args/statics combination. */
10740 if (nargs & statics)
10741 as_bad (_("arg/static registers overlap"));
10742 else if (nargs == 0xf)
10743 /* All $a0-$a3 are args. */
10744 opcode |= MIPS16_ALL_ARGS << 16;
10745 else if (statics == 0xf)
10746 /* All $a0-$a3 are statics. */
10747 opcode |= MIPS16_ALL_STATICS << 16;
10750 int narg = 0, nstat = 0;
10752 /* Count arg registers. */
10753 while (nargs & 0x1)
10759 as_bad (_("invalid arg register list"));
10761 /* Count static registers. */
10762 while (statics & 0x8)
10764 statics = (statics << 1) & 0xf;
10768 as_bad (_("invalid static register list"));
10770 /* Encode args/statics. */
10771 opcode |= ((narg << 2) | nstat) << 16;
10774 /* Encode $s0/$s1. */
10775 if (sregs & (1 << 0)) /* $s0 */
10777 if (sregs & (1 << 1)) /* $s1 */
10783 /* Count regs $s2-$s8. */
10791 as_bad (_("invalid static register list"));
10792 /* Encode $s2-$s8. */
10793 opcode |= nsreg << 24;
10796 /* Encode frame size. */
10798 as_bad (_("missing frame size"));
10799 else if ((framesz & 7) != 0 || framesz < 0
10800 || framesz > 0xff * 8)
10801 as_bad (_("invalid frame size"));
10802 else if (framesz != 128 || (opcode >> 16) != 0)
10805 opcode |= (((framesz & 0xf0) << 16)
10806 | (framesz & 0x0f));
10809 /* Finally build the instruction. */
10810 if ((opcode >> 16) != 0 || framesz == 0)
10812 ip->use_extend = TRUE;
10813 ip->extend = opcode >> 16;
10815 ip->insn_opcode |= opcode & 0x7f;
10819 case 'e': /* extend code */
10820 my_getExpression (&imm_expr, s);
10821 check_absolute_expr (ip, &imm_expr);
10822 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10824 as_warn (_("Invalid value for `%s' (%lu)"),
10826 (unsigned long) imm_expr.X_add_number);
10827 imm_expr.X_add_number &= 0x7ff;
10829 ip->insn_opcode |= imm_expr.X_add_number;
10830 imm_expr.X_op = O_absent;
10840 /* Args don't match. */
10841 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
10842 strcmp (insn->name, insn[1].name) == 0)
10849 insn_error = _("illegal operands");
10855 /* This structure holds information we know about a mips16 immediate
10858 struct mips16_immed_operand
10860 /* The type code used in the argument string in the opcode table. */
10862 /* The number of bits in the short form of the opcode. */
10864 /* The number of bits in the extended form of the opcode. */
10866 /* The amount by which the short form is shifted when it is used;
10867 for example, the sw instruction has a shift count of 2. */
10869 /* The amount by which the short form is shifted when it is stored
10870 into the instruction code. */
10872 /* Non-zero if the short form is unsigned. */
10874 /* Non-zero if the extended form is unsigned. */
10876 /* Non-zero if the value is PC relative. */
10880 /* The mips16 immediate operand types. */
10882 static const struct mips16_immed_operand mips16_immed_operands[] =
10884 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10885 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10886 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
10887 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
10888 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
10889 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
10890 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
10891 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
10892 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
10893 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
10894 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
10895 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
10896 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
10897 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
10898 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
10899 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
10900 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10901 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
10902 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
10903 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
10904 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
10907 #define MIPS16_NUM_IMMED \
10908 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10910 /* Handle a mips16 instruction with an immediate value. This or's the
10911 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10912 whether an extended value is needed; if one is needed, it sets
10913 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10914 If SMALL is true, an unextended opcode was explicitly requested.
10915 If EXT is true, an extended opcode was explicitly requested. If
10916 WARN is true, warn if EXT does not match reality. */
10919 mips16_immed (char *file, unsigned int line, int type, offsetT val,
10920 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10921 unsigned long *insn, bfd_boolean *use_extend,
10922 unsigned short *extend)
10924 const struct mips16_immed_operand *op;
10925 int mintiny, maxtiny;
10926 bfd_boolean needext;
10928 op = mips16_immed_operands;
10929 while (op->type != type)
10932 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10937 if (type == '<' || type == '>' || type == '[' || type == ']')
10940 maxtiny = 1 << op->nbits;
10945 maxtiny = (1 << op->nbits) - 1;
10950 mintiny = - (1 << (op->nbits - 1));
10951 maxtiny = (1 << (op->nbits - 1)) - 1;
10954 /* Branch offsets have an implicit 0 in the lowest bit. */
10955 if (type == 'p' || type == 'q')
10958 if ((val & ((1 << op->shift) - 1)) != 0
10959 || val < (mintiny << op->shift)
10960 || val > (maxtiny << op->shift))
10965 if (warn && ext && ! needext)
10966 as_warn_where (file, line,
10967 _("extended operand requested but not required"));
10968 if (small && needext)
10969 as_bad_where (file, line, _("invalid unextended operand value"));
10971 if (small || (! ext && ! needext))
10975 *use_extend = FALSE;
10976 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
10977 insnval <<= op->op_shift;
10982 long minext, maxext;
10988 maxext = (1 << op->extbits) - 1;
10992 minext = - (1 << (op->extbits - 1));
10993 maxext = (1 << (op->extbits - 1)) - 1;
10995 if (val < minext || val > maxext)
10996 as_bad_where (file, line,
10997 _("operand value out of range for instruction"));
10999 *use_extend = TRUE;
11000 if (op->extbits == 16)
11002 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11005 else if (op->extbits == 15)
11007 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11012 extval = ((val & 0x1f) << 6) | (val & 0x20);
11016 *extend = (unsigned short) extval;
11021 struct percent_op_match
11024 bfd_reloc_code_real_type reloc;
11027 static const struct percent_op_match mips_percent_op[] =
11029 {"%lo", BFD_RELOC_LO16},
11031 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11032 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11033 {"%call16", BFD_RELOC_MIPS_CALL16},
11034 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11035 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11036 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11037 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11038 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11039 {"%got", BFD_RELOC_MIPS_GOT16},
11040 {"%gp_rel", BFD_RELOC_GPREL16},
11041 {"%half", BFD_RELOC_16},
11042 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11043 {"%higher", BFD_RELOC_MIPS_HIGHER},
11044 {"%neg", BFD_RELOC_MIPS_SUB},
11045 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11046 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11047 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11048 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11049 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11050 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11051 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11053 {"%hi", BFD_RELOC_HI16_S}
11056 static const struct percent_op_match mips16_percent_op[] =
11058 {"%lo", BFD_RELOC_MIPS16_LO16},
11059 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11060 {"%got", BFD_RELOC_MIPS16_GOT16},
11061 {"%call16", BFD_RELOC_MIPS16_CALL16},
11062 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11066 /* Return true if *STR points to a relocation operator. When returning true,
11067 move *STR over the operator and store its relocation code in *RELOC.
11068 Leave both *STR and *RELOC alone when returning false. */
11071 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11073 const struct percent_op_match *percent_op;
11076 if (mips_opts.mips16)
11078 percent_op = mips16_percent_op;
11079 limit = ARRAY_SIZE (mips16_percent_op);
11083 percent_op = mips_percent_op;
11084 limit = ARRAY_SIZE (mips_percent_op);
11087 for (i = 0; i < limit; i++)
11088 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11090 int len = strlen (percent_op[i].str);
11092 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11095 *str += strlen (percent_op[i].str);
11096 *reloc = percent_op[i].reloc;
11098 /* Check whether the output BFD supports this relocation.
11099 If not, issue an error and fall back on something safe. */
11100 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11102 as_bad (_("relocation %s isn't supported by the current ABI"),
11103 percent_op[i].str);
11104 *reloc = BFD_RELOC_UNUSED;
11112 /* Parse string STR as a 16-bit relocatable operand. Store the
11113 expression in *EP and the relocations in the array starting
11114 at RELOC. Return the number of relocation operators used.
11116 On exit, EXPR_END points to the first character after the expression. */
11119 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11122 bfd_reloc_code_real_type reversed_reloc[3];
11123 size_t reloc_index, i;
11124 int crux_depth, str_depth;
11127 /* Search for the start of the main expression, recoding relocations
11128 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11129 of the main expression and with CRUX_DEPTH containing the number
11130 of open brackets at that point. */
11137 crux_depth = str_depth;
11139 /* Skip over whitespace and brackets, keeping count of the number
11141 while (*str == ' ' || *str == '\t' || *str == '(')
11146 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11147 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11149 my_getExpression (ep, crux);
11152 /* Match every open bracket. */
11153 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11157 if (crux_depth > 0)
11158 as_bad (_("unclosed '('"));
11162 if (reloc_index != 0)
11164 prev_reloc_op_frag = frag_now;
11165 for (i = 0; i < reloc_index; i++)
11166 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11169 return reloc_index;
11173 my_getExpression (expressionS *ep, char *str)
11178 save_in = input_line_pointer;
11179 input_line_pointer = str;
11181 expr_end = input_line_pointer;
11182 input_line_pointer = save_in;
11184 /* If we are in mips16 mode, and this is an expression based on `.',
11185 then we bump the value of the symbol by 1 since that is how other
11186 text symbols are handled. We don't bother to handle complex
11187 expressions, just `.' plus or minus a constant. */
11188 if (mips_opts.mips16
11189 && ep->X_op == O_symbol
11190 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
11191 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
11192 && symbol_get_frag (ep->X_add_symbol) == frag_now
11193 && symbol_constant_p (ep->X_add_symbol)
11194 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
11195 S_SET_VALUE (ep->X_add_symbol, val + 1);
11199 md_atof (int type, char *litP, int *sizeP)
11201 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11205 md_number_to_chars (char *buf, valueT val, int n)
11207 if (target_big_endian)
11208 number_to_chars_bigendian (buf, val, n);
11210 number_to_chars_littleendian (buf, val, n);
11214 static int support_64bit_objects(void)
11216 const char **list, **l;
11219 list = bfd_target_list ();
11220 for (l = list; *l != NULL; l++)
11222 /* This is traditional mips */
11223 if (strcmp (*l, "elf64-tradbigmips") == 0
11224 || strcmp (*l, "elf64-tradlittlemips") == 0)
11226 if (strcmp (*l, "elf64-bigmips") == 0
11227 || strcmp (*l, "elf64-littlemips") == 0)
11230 yes = (*l != NULL);
11234 #endif /* OBJ_ELF */
11236 const char *md_shortopts = "O::g::G:";
11240 OPTION_MARCH = OPTION_MD_BASE,
11262 OPTION_NO_SMARTMIPS,
11265 OPTION_COMPAT_ARCH_BASE,
11274 OPTION_M7000_HILO_FIX,
11275 OPTION_MNO_7000_HILO_FIX,
11278 OPTION_FIX_LOONGSON2F_JUMP,
11279 OPTION_NO_FIX_LOONGSON2F_JUMP,
11280 OPTION_FIX_LOONGSON2F_NOP,
11281 OPTION_NO_FIX_LOONGSON2F_NOP,
11283 OPTION_NO_FIX_VR4120,
11285 OPTION_NO_FIX_VR4130,
11292 OPTION_CONSTRUCT_FLOATS,
11293 OPTION_NO_CONSTRUCT_FLOATS,
11296 OPTION_RELAX_BRANCH,
11297 OPTION_NO_RELAX_BRANCH,
11304 OPTION_SINGLE_FLOAT,
11305 OPTION_DOUBLE_FLOAT,
11308 OPTION_CALL_SHARED,
11309 OPTION_CALL_NONPIC,
11319 OPTION_MVXWORKS_PIC,
11320 #endif /* OBJ_ELF */
11324 struct option md_longopts[] =
11326 /* Options which specify architecture. */
11327 {"march", required_argument, NULL, OPTION_MARCH},
11328 {"mtune", required_argument, NULL, OPTION_MTUNE},
11329 {"mips0", no_argument, NULL, OPTION_MIPS1},
11330 {"mips1", no_argument, NULL, OPTION_MIPS1},
11331 {"mips2", no_argument, NULL, OPTION_MIPS2},
11332 {"mips3", no_argument, NULL, OPTION_MIPS3},
11333 {"mips4", no_argument, NULL, OPTION_MIPS4},
11334 {"mips5", no_argument, NULL, OPTION_MIPS5},
11335 {"mips32", no_argument, NULL, OPTION_MIPS32},
11336 {"mips64", no_argument, NULL, OPTION_MIPS64},
11337 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11338 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11340 /* Options which specify Application Specific Extensions (ASEs). */
11341 {"mips16", no_argument, NULL, OPTION_MIPS16},
11342 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11343 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11344 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11345 {"mdmx", no_argument, NULL, OPTION_MDMX},
11346 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11347 {"mdsp", no_argument, NULL, OPTION_DSP},
11348 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11349 {"mmt", no_argument, NULL, OPTION_MT},
11350 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11351 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11352 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11353 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11354 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11356 /* Old-style architecture options. Don't add more of these. */
11357 {"m4650", no_argument, NULL, OPTION_M4650},
11358 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11359 {"m4010", no_argument, NULL, OPTION_M4010},
11360 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11361 {"m4100", no_argument, NULL, OPTION_M4100},
11362 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11363 {"m3900", no_argument, NULL, OPTION_M3900},
11364 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11366 /* Options which enable bug fixes. */
11367 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11368 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11369 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11370 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11371 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11372 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11373 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11374 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11375 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11376 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11377 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11378 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11379 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11381 /* Miscellaneous options. */
11382 {"trap", no_argument, NULL, OPTION_TRAP},
11383 {"no-break", no_argument, NULL, OPTION_TRAP},
11384 {"break", no_argument, NULL, OPTION_BREAK},
11385 {"no-trap", no_argument, NULL, OPTION_BREAK},
11386 {"EB", no_argument, NULL, OPTION_EB},
11387 {"EL", no_argument, NULL, OPTION_EL},
11388 {"mfp32", no_argument, NULL, OPTION_FP32},
11389 {"mgp32", no_argument, NULL, OPTION_GP32},
11390 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11391 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11392 {"mfp64", no_argument, NULL, OPTION_FP64},
11393 {"mgp64", no_argument, NULL, OPTION_GP64},
11394 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11395 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11396 {"mshared", no_argument, NULL, OPTION_MSHARED},
11397 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11398 {"msym32", no_argument, NULL, OPTION_MSYM32},
11399 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11400 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11401 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11402 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11403 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11405 /* Strictly speaking this next option is ELF specific,
11406 but we allow it for other ports as well in order to
11407 make testing easier. */
11408 {"32", no_argument, NULL, OPTION_32},
11410 /* ELF-specific options. */
11412 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11413 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11414 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11415 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11416 {"xgot", no_argument, NULL, OPTION_XGOT},
11417 {"mabi", required_argument, NULL, OPTION_MABI},
11418 {"n32", no_argument, NULL, OPTION_N32},
11419 {"64", no_argument, NULL, OPTION_64},
11420 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11421 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11422 {"mpdr", no_argument, NULL, OPTION_PDR},
11423 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11424 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11425 #endif /* OBJ_ELF */
11427 {NULL, no_argument, NULL, 0}
11429 size_t md_longopts_size = sizeof (md_longopts);
11431 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11432 NEW_VALUE. Warn if another value was already specified. Note:
11433 we have to defer parsing the -march and -mtune arguments in order
11434 to handle 'from-abi' correctly, since the ABI might be specified
11435 in a later argument. */
11438 mips_set_option_string (const char **string_ptr, const char *new_value)
11440 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11441 as_warn (_("A different %s was already specified, is now %s"),
11442 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11445 *string_ptr = new_value;
11449 md_parse_option (int c, char *arg)
11453 case OPTION_CONSTRUCT_FLOATS:
11454 mips_disable_float_construction = 0;
11457 case OPTION_NO_CONSTRUCT_FLOATS:
11458 mips_disable_float_construction = 1;
11470 target_big_endian = 1;
11474 target_big_endian = 0;
11480 else if (arg[0] == '0')
11482 else if (arg[0] == '1')
11492 mips_debug = atoi (arg);
11496 file_mips_isa = ISA_MIPS1;
11500 file_mips_isa = ISA_MIPS2;
11504 file_mips_isa = ISA_MIPS3;
11508 file_mips_isa = ISA_MIPS4;
11512 file_mips_isa = ISA_MIPS5;
11515 case OPTION_MIPS32:
11516 file_mips_isa = ISA_MIPS32;
11519 case OPTION_MIPS32R2:
11520 file_mips_isa = ISA_MIPS32R2;
11523 case OPTION_MIPS64R2:
11524 file_mips_isa = ISA_MIPS64R2;
11527 case OPTION_MIPS64:
11528 file_mips_isa = ISA_MIPS64;
11532 mips_set_option_string (&mips_tune_string, arg);
11536 mips_set_option_string (&mips_arch_string, arg);
11540 mips_set_option_string (&mips_arch_string, "4650");
11541 mips_set_option_string (&mips_tune_string, "4650");
11544 case OPTION_NO_M4650:
11548 mips_set_option_string (&mips_arch_string, "4010");
11549 mips_set_option_string (&mips_tune_string, "4010");
11552 case OPTION_NO_M4010:
11556 mips_set_option_string (&mips_arch_string, "4100");
11557 mips_set_option_string (&mips_tune_string, "4100");
11560 case OPTION_NO_M4100:
11564 mips_set_option_string (&mips_arch_string, "3900");
11565 mips_set_option_string (&mips_tune_string, "3900");
11568 case OPTION_NO_M3900:
11572 mips_opts.ase_mdmx = 1;
11575 case OPTION_NO_MDMX:
11576 mips_opts.ase_mdmx = 0;
11580 mips_opts.ase_dsp = 1;
11581 mips_opts.ase_dspr2 = 0;
11584 case OPTION_NO_DSP:
11585 mips_opts.ase_dsp = 0;
11586 mips_opts.ase_dspr2 = 0;
11590 mips_opts.ase_dspr2 = 1;
11591 mips_opts.ase_dsp = 1;
11594 case OPTION_NO_DSPR2:
11595 mips_opts.ase_dspr2 = 0;
11596 mips_opts.ase_dsp = 0;
11600 mips_opts.ase_mt = 1;
11604 mips_opts.ase_mt = 0;
11607 case OPTION_MIPS16:
11608 mips_opts.mips16 = 1;
11609 mips_no_prev_insn ();
11612 case OPTION_NO_MIPS16:
11613 mips_opts.mips16 = 0;
11614 mips_no_prev_insn ();
11617 case OPTION_MIPS3D:
11618 mips_opts.ase_mips3d = 1;
11621 case OPTION_NO_MIPS3D:
11622 mips_opts.ase_mips3d = 0;
11625 case OPTION_SMARTMIPS:
11626 mips_opts.ase_smartmips = 1;
11629 case OPTION_NO_SMARTMIPS:
11630 mips_opts.ase_smartmips = 0;
11633 case OPTION_FIX_24K:
11637 case OPTION_NO_FIX_24K:
11641 case OPTION_FIX_LOONGSON2F_JUMP:
11642 mips_fix_loongson2f_jump = TRUE;
11645 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11646 mips_fix_loongson2f_jump = FALSE;
11649 case OPTION_FIX_LOONGSON2F_NOP:
11650 mips_fix_loongson2f_nop = TRUE;
11653 case OPTION_NO_FIX_LOONGSON2F_NOP:
11654 mips_fix_loongson2f_nop = FALSE;
11657 case OPTION_FIX_VR4120:
11658 mips_fix_vr4120 = 1;
11661 case OPTION_NO_FIX_VR4120:
11662 mips_fix_vr4120 = 0;
11665 case OPTION_FIX_VR4130:
11666 mips_fix_vr4130 = 1;
11669 case OPTION_NO_FIX_VR4130:
11670 mips_fix_vr4130 = 0;
11673 case OPTION_RELAX_BRANCH:
11674 mips_relax_branch = 1;
11677 case OPTION_NO_RELAX_BRANCH:
11678 mips_relax_branch = 0;
11681 case OPTION_MSHARED:
11682 mips_in_shared = TRUE;
11685 case OPTION_MNO_SHARED:
11686 mips_in_shared = FALSE;
11689 case OPTION_MSYM32:
11690 mips_opts.sym32 = TRUE;
11693 case OPTION_MNO_SYM32:
11694 mips_opts.sym32 = FALSE;
11698 /* When generating ELF code, we permit -KPIC and -call_shared to
11699 select SVR4_PIC, and -non_shared to select no PIC. This is
11700 intended to be compatible with Irix 5. */
11701 case OPTION_CALL_SHARED:
11704 as_bad (_("-call_shared is supported only for ELF format"));
11707 mips_pic = SVR4_PIC;
11708 mips_abicalls = TRUE;
11711 case OPTION_CALL_NONPIC:
11714 as_bad (_("-call_nonpic is supported only for ELF format"));
11718 mips_abicalls = TRUE;
11721 case OPTION_NON_SHARED:
11724 as_bad (_("-non_shared is supported only for ELF format"));
11728 mips_abicalls = FALSE;
11731 /* The -xgot option tells the assembler to use 32 bit offsets
11732 when accessing the got in SVR4_PIC mode. It is for Irix
11737 #endif /* OBJ_ELF */
11740 g_switch_value = atoi (arg);
11744 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11748 mips_abi = O32_ABI;
11749 /* We silently ignore -32 for non-ELF targets. This greatly
11750 simplifies the construction of the MIPS GAS test cases. */
11757 as_bad (_("-n32 is supported for ELF format only"));
11760 mips_abi = N32_ABI;
11766 as_bad (_("-64 is supported for ELF format only"));
11769 mips_abi = N64_ABI;
11770 if (!support_64bit_objects())
11771 as_fatal (_("No compiled in support for 64 bit object file format"));
11773 #endif /* OBJ_ELF */
11776 file_mips_gp32 = 1;
11780 file_mips_gp32 = 0;
11784 file_mips_fp32 = 1;
11788 file_mips_fp32 = 0;
11791 case OPTION_SINGLE_FLOAT:
11792 file_mips_single_float = 1;
11795 case OPTION_DOUBLE_FLOAT:
11796 file_mips_single_float = 0;
11799 case OPTION_SOFT_FLOAT:
11800 file_mips_soft_float = 1;
11803 case OPTION_HARD_FLOAT:
11804 file_mips_soft_float = 0;
11811 as_bad (_("-mabi is supported for ELF format only"));
11814 if (strcmp (arg, "32") == 0)
11815 mips_abi = O32_ABI;
11816 else if (strcmp (arg, "o64") == 0)
11817 mips_abi = O64_ABI;
11818 else if (strcmp (arg, "n32") == 0)
11819 mips_abi = N32_ABI;
11820 else if (strcmp (arg, "64") == 0)
11822 mips_abi = N64_ABI;
11823 if (! support_64bit_objects())
11824 as_fatal (_("No compiled in support for 64 bit object file "
11827 else if (strcmp (arg, "eabi") == 0)
11828 mips_abi = EABI_ABI;
11831 as_fatal (_("invalid abi -mabi=%s"), arg);
11835 #endif /* OBJ_ELF */
11837 case OPTION_M7000_HILO_FIX:
11838 mips_7000_hilo_fix = TRUE;
11841 case OPTION_MNO_7000_HILO_FIX:
11842 mips_7000_hilo_fix = FALSE;
11846 case OPTION_MDEBUG:
11847 mips_flag_mdebug = TRUE;
11850 case OPTION_NO_MDEBUG:
11851 mips_flag_mdebug = FALSE;
11855 mips_flag_pdr = TRUE;
11858 case OPTION_NO_PDR:
11859 mips_flag_pdr = FALSE;
11862 case OPTION_MVXWORKS_PIC:
11863 mips_pic = VXWORKS_PIC;
11865 #endif /* OBJ_ELF */
11871 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
11876 /* Set up globals to generate code for the ISA or processor
11877 described by INFO. */
11880 mips_set_architecture (const struct mips_cpu_info *info)
11884 file_mips_arch = info->cpu;
11885 mips_opts.arch = info->cpu;
11886 mips_opts.isa = info->isa;
11891 /* Likewise for tuning. */
11894 mips_set_tune (const struct mips_cpu_info *info)
11897 mips_tune = info->cpu;
11902 mips_after_parse_args (void)
11904 const struct mips_cpu_info *arch_info = 0;
11905 const struct mips_cpu_info *tune_info = 0;
11907 /* GP relative stuff not working for PE */
11908 if (strncmp (TARGET_OS, "pe", 2) == 0)
11910 if (g_switch_seen && g_switch_value != 0)
11911 as_bad (_("-G not supported in this configuration."));
11912 g_switch_value = 0;
11915 if (mips_abi == NO_ABI)
11916 mips_abi = MIPS_DEFAULT_ABI;
11918 /* The following code determines the architecture and register size.
11919 Similar code was added to GCC 3.3 (see override_options() in
11920 config/mips/mips.c). The GAS and GCC code should be kept in sync
11921 as much as possible. */
11923 if (mips_arch_string != 0)
11924 arch_info = mips_parse_cpu ("-march", mips_arch_string);
11926 if (file_mips_isa != ISA_UNKNOWN)
11928 /* Handle -mipsN. At this point, file_mips_isa contains the
11929 ISA level specified by -mipsN, while arch_info->isa contains
11930 the -march selection (if any). */
11931 if (arch_info != 0)
11933 /* -march takes precedence over -mipsN, since it is more descriptive.
11934 There's no harm in specifying both as long as the ISA levels
11936 if (file_mips_isa != arch_info->isa)
11937 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11938 mips_cpu_info_from_isa (file_mips_isa)->name,
11939 mips_cpu_info_from_isa (arch_info->isa)->name);
11942 arch_info = mips_cpu_info_from_isa (file_mips_isa);
11945 if (arch_info == 0)
11946 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
11948 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
11949 as_bad (_("-march=%s is not compatible with the selected ABI"),
11952 mips_set_architecture (arch_info);
11954 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11955 if (mips_tune_string != 0)
11956 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
11958 if (tune_info == 0)
11959 mips_set_tune (arch_info);
11961 mips_set_tune (tune_info);
11963 if (file_mips_gp32 >= 0)
11965 /* The user specified the size of the integer registers. Make sure
11966 it agrees with the ABI and ISA. */
11967 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
11968 as_bad (_("-mgp64 used with a 32-bit processor"));
11969 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
11970 as_bad (_("-mgp32 used with a 64-bit ABI"));
11971 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
11972 as_bad (_("-mgp64 used with a 32-bit ABI"));
11976 /* Infer the integer register size from the ABI and processor.
11977 Restrict ourselves to 32-bit registers if that's all the
11978 processor has, or if the ABI cannot handle 64-bit registers. */
11979 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11980 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11983 switch (file_mips_fp32)
11987 /* No user specified float register size.
11988 ??? GAS treats single-float processors as though they had 64-bit
11989 float registers (although it complains when double-precision
11990 instructions are used). As things stand, saying they have 32-bit
11991 registers would lead to spurious "register must be even" messages.
11992 So here we assume float registers are never smaller than the
11994 if (file_mips_gp32 == 0)
11995 /* 64-bit integer registers implies 64-bit float registers. */
11996 file_mips_fp32 = 0;
11997 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11998 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11999 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12000 file_mips_fp32 = 0;
12002 /* 32-bit float registers. */
12003 file_mips_fp32 = 1;
12006 /* The user specified the size of the float registers. Check if it
12007 agrees with the ABI and ISA. */
12009 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12010 as_bad (_("-mfp64 used with a 32-bit fpu"));
12011 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12012 && !ISA_HAS_MXHC1 (mips_opts.isa))
12013 as_warn (_("-mfp64 used with a 32-bit ABI"));
12016 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12017 as_warn (_("-mfp32 used with a 64-bit ABI"));
12021 /* End of GCC-shared inference code. */
12023 /* This flag is set when we have a 64-bit capable CPU but use only
12024 32-bit wide registers. Note that EABI does not use it. */
12025 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12026 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12027 || mips_abi == O32_ABI))
12028 mips_32bitmode = 1;
12030 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12031 as_bad (_("trap exception not supported at ISA 1"));
12033 /* If the selected architecture includes support for ASEs, enable
12034 generation of code for them. */
12035 if (mips_opts.mips16 == -1)
12036 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12037 if (mips_opts.ase_mips3d == -1)
12038 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12039 && file_mips_fp32 == 0) ? 1 : 0;
12040 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12041 as_bad (_("-mfp32 used with -mips3d"));
12043 if (mips_opts.ase_mdmx == -1)
12044 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12045 && file_mips_fp32 == 0) ? 1 : 0;
12046 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12047 as_bad (_("-mfp32 used with -mdmx"));
12049 if (mips_opts.ase_smartmips == -1)
12050 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12051 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12052 as_warn (_("%s ISA does not support SmartMIPS"),
12053 mips_cpu_info_from_isa (mips_opts.isa)->name);
12055 if (mips_opts.ase_dsp == -1)
12056 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12057 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12058 as_warn (_("%s ISA does not support DSP ASE"),
12059 mips_cpu_info_from_isa (mips_opts.isa)->name);
12061 if (mips_opts.ase_dspr2 == -1)
12063 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12064 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12066 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12067 as_warn (_("%s ISA does not support DSP R2 ASE"),
12068 mips_cpu_info_from_isa (mips_opts.isa)->name);
12070 if (mips_opts.ase_mt == -1)
12071 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12072 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12073 as_warn (_("%s ISA does not support MT ASE"),
12074 mips_cpu_info_from_isa (mips_opts.isa)->name);
12076 file_mips_isa = mips_opts.isa;
12077 file_ase_mips16 = mips_opts.mips16;
12078 file_ase_mips3d = mips_opts.ase_mips3d;
12079 file_ase_mdmx = mips_opts.ase_mdmx;
12080 file_ase_smartmips = mips_opts.ase_smartmips;
12081 file_ase_dsp = mips_opts.ase_dsp;
12082 file_ase_dspr2 = mips_opts.ase_dspr2;
12083 file_ase_mt = mips_opts.ase_mt;
12084 mips_opts.gp32 = file_mips_gp32;
12085 mips_opts.fp32 = file_mips_fp32;
12086 mips_opts.soft_float = file_mips_soft_float;
12087 mips_opts.single_float = file_mips_single_float;
12089 if (mips_flag_mdebug < 0)
12091 #ifdef OBJ_MAYBE_ECOFF
12092 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12093 mips_flag_mdebug = 1;
12095 #endif /* OBJ_MAYBE_ECOFF */
12096 mips_flag_mdebug = 0;
12101 mips_init_after_args (void)
12103 /* initialize opcodes */
12104 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12105 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12109 md_pcrel_from (fixS *fixP)
12111 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12112 switch (fixP->fx_r_type)
12114 case BFD_RELOC_16_PCREL_S2:
12115 case BFD_RELOC_MIPS_JMP:
12116 /* Return the address of the delay slot. */
12119 /* We have no relocation type for PC relative MIPS16 instructions. */
12120 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12121 as_bad_where (fixP->fx_file, fixP->fx_line,
12122 _("PC relative MIPS16 instruction references a different section"));
12127 /* This is called before the symbol table is processed. In order to
12128 work with gcc when using mips-tfile, we must keep all local labels.
12129 However, in other cases, we want to discard them. If we were
12130 called with -g, but we didn't see any debugging information, it may
12131 mean that gcc is smuggling debugging information through to
12132 mips-tfile, in which case we must generate all local labels. */
12135 mips_frob_file_before_adjust (void)
12137 #ifndef NO_ECOFF_DEBUGGING
12138 if (ECOFF_DEBUGGING
12140 && ! ecoff_debugging_seen)
12141 flag_keep_locals = 1;
12145 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12146 the corresponding LO16 reloc. This is called before md_apply_fix and
12147 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12148 relocation operators.
12150 For our purposes, a %lo() expression matches a %got() or %hi()
12153 (a) it refers to the same symbol; and
12154 (b) the offset applied in the %lo() expression is no lower than
12155 the offset applied in the %got() or %hi().
12157 (b) allows us to cope with code like:
12160 lh $4,%lo(foo+2)($4)
12162 ...which is legal on RELA targets, and has a well-defined behaviour
12163 if the user knows that adding 2 to "foo" will not induce a carry to
12166 When several %lo()s match a particular %got() or %hi(), we use the
12167 following rules to distinguish them:
12169 (1) %lo()s with smaller offsets are a better match than %lo()s with
12172 (2) %lo()s with no matching %got() or %hi() are better than those
12173 that already have a matching %got() or %hi().
12175 (3) later %lo()s are better than earlier %lo()s.
12177 These rules are applied in order.
12179 (1) means, among other things, that %lo()s with identical offsets are
12180 chosen if they exist.
12182 (2) means that we won't associate several high-part relocations with
12183 the same low-part relocation unless there's no alternative. Having
12184 several high parts for the same low part is a GNU extension; this rule
12185 allows careful users to avoid it.
12187 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12188 with the last high-part relocation being at the front of the list.
12189 It therefore makes sense to choose the last matching low-part
12190 relocation, all other things being equal. It's also easier
12191 to code that way. */
12194 mips_frob_file (void)
12196 struct mips_hi_fixup *l;
12197 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12199 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12201 segment_info_type *seginfo;
12202 bfd_boolean matched_lo_p;
12203 fixS **hi_pos, **lo_pos, **pos;
12205 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12207 /* If a GOT16 relocation turns out to be against a global symbol,
12208 there isn't supposed to be a matching LO. */
12209 if (got16_reloc_p (l->fixp->fx_r_type)
12210 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12213 /* Check quickly whether the next fixup happens to be a matching %lo. */
12214 if (fixup_has_matching_lo_p (l->fixp))
12217 seginfo = seg_info (l->seg);
12219 /* Set HI_POS to the position of this relocation in the chain.
12220 Set LO_POS to the position of the chosen low-part relocation.
12221 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12222 relocation that matches an immediately-preceding high-part
12226 matched_lo_p = FALSE;
12227 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12229 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12231 if (*pos == l->fixp)
12234 if ((*pos)->fx_r_type == looking_for_rtype
12235 && (*pos)->fx_addsy == l->fixp->fx_addsy
12236 && (*pos)->fx_offset >= l->fixp->fx_offset
12238 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12240 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12243 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12244 && fixup_has_matching_lo_p (*pos));
12247 /* If we found a match, remove the high-part relocation from its
12248 current position and insert it before the low-part relocation.
12249 Make the offsets match so that fixup_has_matching_lo_p()
12252 We don't warn about unmatched high-part relocations since some
12253 versions of gcc have been known to emit dead "lui ...%hi(...)"
12255 if (lo_pos != NULL)
12257 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12258 if (l->fixp->fx_next != *lo_pos)
12260 *hi_pos = l->fixp->fx_next;
12261 l->fixp->fx_next = *lo_pos;
12268 /* We may have combined relocations without symbols in the N32/N64 ABI.
12269 We have to prevent gas from dropping them. */
12272 mips_force_relocation (fixS *fixp)
12274 if (generic_force_reloc (fixp))
12278 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12279 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12280 || hi16_reloc_p (fixp->fx_r_type)
12281 || lo16_reloc_p (fixp->fx_r_type)))
12287 /* Apply a fixup to the object file. */
12290 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12294 reloc_howto_type *howto;
12296 /* We ignore generic BFD relocations we don't know about. */
12297 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12301 gas_assert (fixP->fx_size == 4
12302 || fixP->fx_r_type == BFD_RELOC_16
12303 || fixP->fx_r_type == BFD_RELOC_64
12304 || fixP->fx_r_type == BFD_RELOC_CTOR
12305 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12306 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12307 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12308 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12310 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12312 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12314 /* Don't treat parts of a composite relocation as done. There are two
12317 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12318 should nevertheless be emitted if the first part is.
12320 (2) In normal usage, composite relocations are never assembly-time
12321 constants. The easiest way of dealing with the pathological
12322 exceptions is to generate a relocation against STN_UNDEF and
12323 leave everything up to the linker. */
12324 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12327 switch (fixP->fx_r_type)
12329 case BFD_RELOC_MIPS_TLS_GD:
12330 case BFD_RELOC_MIPS_TLS_LDM:
12331 case BFD_RELOC_MIPS_TLS_DTPREL32:
12332 case BFD_RELOC_MIPS_TLS_DTPREL64:
12333 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12334 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12335 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12336 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12337 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12338 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12341 case BFD_RELOC_MIPS_JMP:
12342 case BFD_RELOC_MIPS_SHIFT5:
12343 case BFD_RELOC_MIPS_SHIFT6:
12344 case BFD_RELOC_MIPS_GOT_DISP:
12345 case BFD_RELOC_MIPS_GOT_PAGE:
12346 case BFD_RELOC_MIPS_GOT_OFST:
12347 case BFD_RELOC_MIPS_SUB:
12348 case BFD_RELOC_MIPS_INSERT_A:
12349 case BFD_RELOC_MIPS_INSERT_B:
12350 case BFD_RELOC_MIPS_DELETE:
12351 case BFD_RELOC_MIPS_HIGHEST:
12352 case BFD_RELOC_MIPS_HIGHER:
12353 case BFD_RELOC_MIPS_SCN_DISP:
12354 case BFD_RELOC_MIPS_REL16:
12355 case BFD_RELOC_MIPS_RELGOT:
12356 case BFD_RELOC_MIPS_JALR:
12357 case BFD_RELOC_HI16:
12358 case BFD_RELOC_HI16_S:
12359 case BFD_RELOC_GPREL16:
12360 case BFD_RELOC_MIPS_LITERAL:
12361 case BFD_RELOC_MIPS_CALL16:
12362 case BFD_RELOC_MIPS_GOT16:
12363 case BFD_RELOC_GPREL32:
12364 case BFD_RELOC_MIPS_GOT_HI16:
12365 case BFD_RELOC_MIPS_GOT_LO16:
12366 case BFD_RELOC_MIPS_CALL_HI16:
12367 case BFD_RELOC_MIPS_CALL_LO16:
12368 case BFD_RELOC_MIPS16_GPREL:
12369 case BFD_RELOC_MIPS16_GOT16:
12370 case BFD_RELOC_MIPS16_CALL16:
12371 case BFD_RELOC_MIPS16_HI16:
12372 case BFD_RELOC_MIPS16_HI16_S:
12373 case BFD_RELOC_MIPS16_JMP:
12374 /* Nothing needed to do. The value comes from the reloc entry. */
12378 /* This is handled like BFD_RELOC_32, but we output a sign
12379 extended value if we are only 32 bits. */
12382 if (8 <= sizeof (valueT))
12383 md_number_to_chars ((char *) buf, *valP, 8);
12388 if ((*valP & 0x80000000) != 0)
12392 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12394 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12400 case BFD_RELOC_RVA:
12403 /* If we are deleting this reloc entry, we must fill in the
12404 value now. This can happen if we have a .word which is not
12405 resolved when it appears but is later defined. */
12407 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12410 case BFD_RELOC_LO16:
12411 case BFD_RELOC_MIPS16_LO16:
12412 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12413 may be safe to remove, but if so it's not obvious. */
12414 /* When handling an embedded PIC switch statement, we can wind
12415 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12418 if (*valP + 0x8000 > 0xffff)
12419 as_bad_where (fixP->fx_file, fixP->fx_line,
12420 _("relocation overflow"));
12421 if (target_big_endian)
12423 md_number_to_chars ((char *) buf, *valP, 2);
12427 case BFD_RELOC_16_PCREL_S2:
12428 if ((*valP & 0x3) != 0)
12429 as_bad_where (fixP->fx_file, fixP->fx_line,
12430 _("Branch to misaligned address (%lx)"), (long) *valP);
12432 /* We need to save the bits in the instruction since fixup_segment()
12433 might be deleting the relocation entry (i.e., a branch within
12434 the current segment). */
12435 if (! fixP->fx_done)
12438 /* Update old instruction data. */
12439 if (target_big_endian)
12440 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12442 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12444 if (*valP + 0x20000 <= 0x3ffff)
12446 insn |= (*valP >> 2) & 0xffff;
12447 md_number_to_chars ((char *) buf, insn, 4);
12449 else if (mips_pic == NO_PIC
12451 && fixP->fx_frag->fr_address >= text_section->vma
12452 && (fixP->fx_frag->fr_address
12453 < text_section->vma + bfd_get_section_size (text_section))
12454 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12455 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12456 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12458 /* The branch offset is too large. If this is an
12459 unconditional branch, and we are not generating PIC code,
12460 we can convert it to an absolute jump instruction. */
12461 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12462 insn = 0x0c000000; /* jal */
12464 insn = 0x08000000; /* j */
12465 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12467 fixP->fx_addsy = section_symbol (text_section);
12468 *valP += md_pcrel_from (fixP);
12469 md_number_to_chars ((char *) buf, insn, 4);
12473 /* If we got here, we have branch-relaxation disabled,
12474 and there's nothing we can do to fix this instruction
12475 without turning it into a longer sequence. */
12476 as_bad_where (fixP->fx_file, fixP->fx_line,
12477 _("Branch out of range"));
12481 case BFD_RELOC_VTABLE_INHERIT:
12484 && !S_IS_DEFINED (fixP->fx_addsy)
12485 && !S_IS_WEAK (fixP->fx_addsy))
12486 S_SET_WEAK (fixP->fx_addsy);
12489 case BFD_RELOC_VTABLE_ENTRY:
12497 /* Remember value for tc_gen_reloc. */
12498 fixP->fx_addnumber = *valP;
12508 name = input_line_pointer;
12509 c = get_symbol_end ();
12510 p = (symbolS *) symbol_find_or_make (name);
12511 *input_line_pointer = c;
12515 /* Align the current frag to a given power of two. If a particular
12516 fill byte should be used, FILL points to an integer that contains
12517 that byte, otherwise FILL is null.
12519 The MIPS assembler also automatically adjusts any preceding
12523 mips_align (int to, int *fill, symbolS *label)
12525 mips_emit_delays ();
12526 mips_record_mips16_mode ();
12527 if (fill == NULL && subseg_text_p (now_seg))
12528 frag_align_code (to, 0);
12530 frag_align (to, fill ? *fill : 0, 0);
12531 record_alignment (now_seg, to);
12534 gas_assert (S_GET_SEGMENT (label) == now_seg);
12535 symbol_set_frag (label, frag_now);
12536 S_SET_VALUE (label, (valueT) frag_now_fix ());
12540 /* Align to a given power of two. .align 0 turns off the automatic
12541 alignment used by the data creating pseudo-ops. */
12544 s_align (int x ATTRIBUTE_UNUSED)
12546 int temp, fill_value, *fill_ptr;
12547 long max_alignment = 28;
12549 /* o Note that the assembler pulls down any immediately preceding label
12550 to the aligned address.
12551 o It's not documented but auto alignment is reinstated by
12552 a .align pseudo instruction.
12553 o Note also that after auto alignment is turned off the mips assembler
12554 issues an error on attempt to assemble an improperly aligned data item.
12557 temp = get_absolute_expression ();
12558 if (temp > max_alignment)
12559 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12562 as_warn (_("Alignment negative: 0 assumed."));
12565 if (*input_line_pointer == ',')
12567 ++input_line_pointer;
12568 fill_value = get_absolute_expression ();
12569 fill_ptr = &fill_value;
12575 segment_info_type *si = seg_info (now_seg);
12576 struct insn_label_list *l = si->label_list;
12577 /* Auto alignment should be switched on by next section change. */
12579 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12586 demand_empty_rest_of_line ();
12590 s_change_sec (int sec)
12595 /* The ELF backend needs to know that we are changing sections, so
12596 that .previous works correctly. We could do something like check
12597 for an obj_section_change_hook macro, but that might be confusing
12598 as it would not be appropriate to use it in the section changing
12599 functions in read.c, since obj-elf.c intercepts those. FIXME:
12600 This should be cleaner, somehow. */
12602 obj_elf_section_change_hook ();
12605 mips_emit_delays ();
12616 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12617 demand_empty_rest_of_line ();
12621 seg = subseg_new (RDATA_SECTION_NAME,
12622 (subsegT) get_absolute_expression ());
12625 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12626 | SEC_READONLY | SEC_RELOC
12628 if (strncmp (TARGET_OS, "elf", 3) != 0)
12629 record_alignment (seg, 4);
12631 demand_empty_rest_of_line ();
12635 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12638 bfd_set_section_flags (stdoutput, seg,
12639 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12640 if (strncmp (TARGET_OS, "elf", 3) != 0)
12641 record_alignment (seg, 4);
12643 demand_empty_rest_of_line ();
12651 s_change_section (int ignore ATTRIBUTE_UNUSED)
12654 char *section_name;
12659 int section_entry_size;
12660 int section_alignment;
12665 section_name = input_line_pointer;
12666 c = get_symbol_end ();
12668 next_c = *(input_line_pointer + 1);
12670 /* Do we have .section Name<,"flags">? */
12671 if (c != ',' || (c == ',' && next_c == '"'))
12673 /* just after name is now '\0'. */
12674 *input_line_pointer = c;
12675 input_line_pointer = section_name;
12676 obj_elf_section (ignore);
12679 input_line_pointer++;
12681 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12683 section_type = get_absolute_expression ();
12686 if (*input_line_pointer++ == ',')
12687 section_flag = get_absolute_expression ();
12690 if (*input_line_pointer++ == ',')
12691 section_entry_size = get_absolute_expression ();
12693 section_entry_size = 0;
12694 if (*input_line_pointer++ == ',')
12695 section_alignment = get_absolute_expression ();
12697 section_alignment = 0;
12699 section_name = xstrdup (section_name);
12701 /* When using the generic form of .section (as implemented by obj-elf.c),
12702 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12703 traditionally had to fall back on the more common @progbits instead.
12705 There's nothing really harmful in this, since bfd will correct
12706 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12707 means that, for backwards compatibility, the special_section entries
12708 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12710 Even so, we shouldn't force users of the MIPS .section syntax to
12711 incorrectly label the sections as SHT_PROGBITS. The best compromise
12712 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12713 generic type-checking code. */
12714 if (section_type == SHT_MIPS_DWARF)
12715 section_type = SHT_PROGBITS;
12717 obj_elf_change_section (section_name, section_type, section_flag,
12718 section_entry_size, 0, 0, 0);
12720 if (now_seg->name != section_name)
12721 free (section_name);
12722 #endif /* OBJ_ELF */
12726 mips_enable_auto_align (void)
12732 s_cons (int log_size)
12734 segment_info_type *si = seg_info (now_seg);
12735 struct insn_label_list *l = si->label_list;
12738 label = l != NULL ? l->label : NULL;
12739 mips_emit_delays ();
12740 if (log_size > 0 && auto_align)
12741 mips_align (log_size, 0, label);
12742 mips_clear_insn_labels ();
12743 cons (1 << log_size);
12747 s_float_cons (int type)
12749 segment_info_type *si = seg_info (now_seg);
12750 struct insn_label_list *l = si->label_list;
12753 label = l != NULL ? l->label : NULL;
12755 mips_emit_delays ();
12760 mips_align (3, 0, label);
12762 mips_align (2, 0, label);
12765 mips_clear_insn_labels ();
12770 /* Handle .globl. We need to override it because on Irix 5 you are
12773 where foo is an undefined symbol, to mean that foo should be
12774 considered to be the address of a function. */
12777 s_mips_globl (int x ATTRIBUTE_UNUSED)
12786 name = input_line_pointer;
12787 c = get_symbol_end ();
12788 symbolP = symbol_find_or_make (name);
12789 S_SET_EXTERNAL (symbolP);
12791 *input_line_pointer = c;
12792 SKIP_WHITESPACE ();
12794 /* On Irix 5, every global symbol that is not explicitly labelled as
12795 being a function is apparently labelled as being an object. */
12798 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12799 && (*input_line_pointer != ','))
12804 secname = input_line_pointer;
12805 c = get_symbol_end ();
12806 sec = bfd_get_section_by_name (stdoutput, secname);
12808 as_bad (_("%s: no such section"), secname);
12809 *input_line_pointer = c;
12811 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12812 flag = BSF_FUNCTION;
12815 symbol_get_bfdsym (symbolP)->flags |= flag;
12817 c = *input_line_pointer;
12820 input_line_pointer++;
12821 SKIP_WHITESPACE ();
12822 if (is_end_of_line[(unsigned char) *input_line_pointer])
12828 demand_empty_rest_of_line ();
12832 s_option (int x ATTRIBUTE_UNUSED)
12837 opt = input_line_pointer;
12838 c = get_symbol_end ();
12842 /* FIXME: What does this mean? */
12844 else if (strncmp (opt, "pic", 3) == 0)
12848 i = atoi (opt + 3);
12853 mips_pic = SVR4_PIC;
12854 mips_abicalls = TRUE;
12857 as_bad (_(".option pic%d not supported"), i);
12859 if (mips_pic == SVR4_PIC)
12861 if (g_switch_seen && g_switch_value != 0)
12862 as_warn (_("-G may not be used with SVR4 PIC code"));
12863 g_switch_value = 0;
12864 bfd_set_gp_size (stdoutput, 0);
12868 as_warn (_("Unrecognized option \"%s\""), opt);
12870 *input_line_pointer = c;
12871 demand_empty_rest_of_line ();
12874 /* This structure is used to hold a stack of .set values. */
12876 struct mips_option_stack
12878 struct mips_option_stack *next;
12879 struct mips_set_options options;
12882 static struct mips_option_stack *mips_opts_stack;
12884 /* Handle the .set pseudo-op. */
12887 s_mipsset (int x ATTRIBUTE_UNUSED)
12889 char *name = input_line_pointer, ch;
12891 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12892 ++input_line_pointer;
12893 ch = *input_line_pointer;
12894 *input_line_pointer = '\0';
12896 if (strcmp (name, "reorder") == 0)
12898 if (mips_opts.noreorder)
12901 else if (strcmp (name, "noreorder") == 0)
12903 if (!mips_opts.noreorder)
12904 start_noreorder ();
12906 else if (strncmp (name, "at=", 3) == 0)
12908 char *s = name + 3;
12910 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
12911 as_bad (_("Unrecognized register name `%s'"), s);
12913 else if (strcmp (name, "at") == 0)
12915 mips_opts.at = ATREG;
12917 else if (strcmp (name, "noat") == 0)
12919 mips_opts.at = ZERO;
12921 else if (strcmp (name, "macro") == 0)
12923 mips_opts.warn_about_macros = 0;
12925 else if (strcmp (name, "nomacro") == 0)
12927 if (mips_opts.noreorder == 0)
12928 as_bad (_("`noreorder' must be set before `nomacro'"));
12929 mips_opts.warn_about_macros = 1;
12931 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
12933 mips_opts.nomove = 0;
12935 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
12937 mips_opts.nomove = 1;
12939 else if (strcmp (name, "bopt") == 0)
12941 mips_opts.nobopt = 0;
12943 else if (strcmp (name, "nobopt") == 0)
12945 mips_opts.nobopt = 1;
12947 else if (strcmp (name, "gp=default") == 0)
12948 mips_opts.gp32 = file_mips_gp32;
12949 else if (strcmp (name, "gp=32") == 0)
12950 mips_opts.gp32 = 1;
12951 else if (strcmp (name, "gp=64") == 0)
12953 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12954 as_warn (_("%s isa does not support 64-bit registers"),
12955 mips_cpu_info_from_isa (mips_opts.isa)->name);
12956 mips_opts.gp32 = 0;
12958 else if (strcmp (name, "fp=default") == 0)
12959 mips_opts.fp32 = file_mips_fp32;
12960 else if (strcmp (name, "fp=32") == 0)
12961 mips_opts.fp32 = 1;
12962 else if (strcmp (name, "fp=64") == 0)
12964 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12965 as_warn (_("%s isa does not support 64-bit floating point registers"),
12966 mips_cpu_info_from_isa (mips_opts.isa)->name);
12967 mips_opts.fp32 = 0;
12969 else if (strcmp (name, "softfloat") == 0)
12970 mips_opts.soft_float = 1;
12971 else if (strcmp (name, "hardfloat") == 0)
12972 mips_opts.soft_float = 0;
12973 else if (strcmp (name, "singlefloat") == 0)
12974 mips_opts.single_float = 1;
12975 else if (strcmp (name, "doublefloat") == 0)
12976 mips_opts.single_float = 0;
12977 else if (strcmp (name, "mips16") == 0
12978 || strcmp (name, "MIPS-16") == 0)
12979 mips_opts.mips16 = 1;
12980 else if (strcmp (name, "nomips16") == 0
12981 || strcmp (name, "noMIPS-16") == 0)
12982 mips_opts.mips16 = 0;
12983 else if (strcmp (name, "smartmips") == 0)
12985 if (!ISA_SUPPORTS_SMARTMIPS)
12986 as_warn (_("%s ISA does not support SmartMIPS ASE"),
12987 mips_cpu_info_from_isa (mips_opts.isa)->name);
12988 mips_opts.ase_smartmips = 1;
12990 else if (strcmp (name, "nosmartmips") == 0)
12991 mips_opts.ase_smartmips = 0;
12992 else if (strcmp (name, "mips3d") == 0)
12993 mips_opts.ase_mips3d = 1;
12994 else if (strcmp (name, "nomips3d") == 0)
12995 mips_opts.ase_mips3d = 0;
12996 else if (strcmp (name, "mdmx") == 0)
12997 mips_opts.ase_mdmx = 1;
12998 else if (strcmp (name, "nomdmx") == 0)
12999 mips_opts.ase_mdmx = 0;
13000 else if (strcmp (name, "dsp") == 0)
13002 if (!ISA_SUPPORTS_DSP_ASE)
13003 as_warn (_("%s ISA does not support DSP ASE"),
13004 mips_cpu_info_from_isa (mips_opts.isa)->name);
13005 mips_opts.ase_dsp = 1;
13006 mips_opts.ase_dspr2 = 0;
13008 else if (strcmp (name, "nodsp") == 0)
13010 mips_opts.ase_dsp = 0;
13011 mips_opts.ase_dspr2 = 0;
13013 else if (strcmp (name, "dspr2") == 0)
13015 if (!ISA_SUPPORTS_DSPR2_ASE)
13016 as_warn (_("%s ISA does not support DSP R2 ASE"),
13017 mips_cpu_info_from_isa (mips_opts.isa)->name);
13018 mips_opts.ase_dspr2 = 1;
13019 mips_opts.ase_dsp = 1;
13021 else if (strcmp (name, "nodspr2") == 0)
13023 mips_opts.ase_dspr2 = 0;
13024 mips_opts.ase_dsp = 0;
13026 else if (strcmp (name, "mt") == 0)
13028 if (!ISA_SUPPORTS_MT_ASE)
13029 as_warn (_("%s ISA does not support MT ASE"),
13030 mips_cpu_info_from_isa (mips_opts.isa)->name);
13031 mips_opts.ase_mt = 1;
13033 else if (strcmp (name, "nomt") == 0)
13034 mips_opts.ase_mt = 0;
13035 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13039 /* Permit the user to change the ISA and architecture on the fly.
13040 Needless to say, misuse can cause serious problems. */
13041 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13044 mips_opts.isa = file_mips_isa;
13045 mips_opts.arch = file_mips_arch;
13047 else if (strncmp (name, "arch=", 5) == 0)
13049 const struct mips_cpu_info *p;
13051 p = mips_parse_cpu("internal use", name + 5);
13053 as_bad (_("unknown architecture %s"), name + 5);
13056 mips_opts.arch = p->cpu;
13057 mips_opts.isa = p->isa;
13060 else if (strncmp (name, "mips", 4) == 0)
13062 const struct mips_cpu_info *p;
13064 p = mips_parse_cpu("internal use", name);
13066 as_bad (_("unknown ISA level %s"), name + 4);
13069 mips_opts.arch = p->cpu;
13070 mips_opts.isa = p->isa;
13074 as_bad (_("unknown ISA or architecture %s"), name);
13076 switch (mips_opts.isa)
13084 mips_opts.gp32 = 1;
13085 mips_opts.fp32 = 1;
13092 mips_opts.gp32 = 0;
13093 mips_opts.fp32 = 0;
13096 as_bad (_("unknown ISA level %s"), name + 4);
13101 mips_opts.gp32 = file_mips_gp32;
13102 mips_opts.fp32 = file_mips_fp32;
13105 else if (strcmp (name, "autoextend") == 0)
13106 mips_opts.noautoextend = 0;
13107 else if (strcmp (name, "noautoextend") == 0)
13108 mips_opts.noautoextend = 1;
13109 else if (strcmp (name, "push") == 0)
13111 struct mips_option_stack *s;
13113 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13114 s->next = mips_opts_stack;
13115 s->options = mips_opts;
13116 mips_opts_stack = s;
13118 else if (strcmp (name, "pop") == 0)
13120 struct mips_option_stack *s;
13122 s = mips_opts_stack;
13124 as_bad (_(".set pop with no .set push"));
13127 /* If we're changing the reorder mode we need to handle
13128 delay slots correctly. */
13129 if (s->options.noreorder && ! mips_opts.noreorder)
13130 start_noreorder ();
13131 else if (! s->options.noreorder && mips_opts.noreorder)
13134 mips_opts = s->options;
13135 mips_opts_stack = s->next;
13139 else if (strcmp (name, "sym32") == 0)
13140 mips_opts.sym32 = TRUE;
13141 else if (strcmp (name, "nosym32") == 0)
13142 mips_opts.sym32 = FALSE;
13143 else if (strchr (name, ','))
13145 /* Generic ".set" directive; use the generic handler. */
13146 *input_line_pointer = ch;
13147 input_line_pointer = name;
13153 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13155 *input_line_pointer = ch;
13156 demand_empty_rest_of_line ();
13159 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13160 .option pic2. It means to generate SVR4 PIC calls. */
13163 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13165 mips_pic = SVR4_PIC;
13166 mips_abicalls = TRUE;
13168 if (g_switch_seen && g_switch_value != 0)
13169 as_warn (_("-G may not be used with SVR4 PIC code"));
13170 g_switch_value = 0;
13172 bfd_set_gp_size (stdoutput, 0);
13173 demand_empty_rest_of_line ();
13176 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13177 PIC code. It sets the $gp register for the function based on the
13178 function address, which is in the register named in the argument.
13179 This uses a relocation against _gp_disp, which is handled specially
13180 by the linker. The result is:
13181 lui $gp,%hi(_gp_disp)
13182 addiu $gp,$gp,%lo(_gp_disp)
13183 addu $gp,$gp,.cpload argument
13184 The .cpload argument is normally $25 == $t9.
13186 The -mno-shared option changes this to:
13187 lui $gp,%hi(__gnu_local_gp)
13188 addiu $gp,$gp,%lo(__gnu_local_gp)
13189 and the argument is ignored. This saves an instruction, but the
13190 resulting code is not position independent; it uses an absolute
13191 address for __gnu_local_gp. Thus code assembled with -mno-shared
13192 can go into an ordinary executable, but not into a shared library. */
13195 s_cpload (int ignore ATTRIBUTE_UNUSED)
13201 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13202 .cpload is ignored. */
13203 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13209 /* .cpload should be in a .set noreorder section. */
13210 if (mips_opts.noreorder == 0)
13211 as_warn (_(".cpload not in noreorder section"));
13213 reg = tc_get_register (0);
13215 /* If we need to produce a 64-bit address, we are better off using
13216 the default instruction sequence. */
13217 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13219 ex.X_op = O_symbol;
13220 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13222 ex.X_op_symbol = NULL;
13223 ex.X_add_number = 0;
13225 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13226 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13229 macro_build_lui (&ex, mips_gp_register);
13230 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13231 mips_gp_register, BFD_RELOC_LO16);
13233 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13234 mips_gp_register, reg);
13237 demand_empty_rest_of_line ();
13240 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13241 .cpsetup $reg1, offset|$reg2, label
13243 If offset is given, this results in:
13244 sd $gp, offset($sp)
13245 lui $gp, %hi(%neg(%gp_rel(label)))
13246 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13247 daddu $gp, $gp, $reg1
13249 If $reg2 is given, this results in:
13250 daddu $reg2, $gp, $0
13251 lui $gp, %hi(%neg(%gp_rel(label)))
13252 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13253 daddu $gp, $gp, $reg1
13254 $reg1 is normally $25 == $t9.
13256 The -mno-shared option replaces the last three instructions with
13258 addiu $gp,$gp,%lo(_gp) */
13261 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13263 expressionS ex_off;
13264 expressionS ex_sym;
13267 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13268 We also need NewABI support. */
13269 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13275 reg1 = tc_get_register (0);
13276 SKIP_WHITESPACE ();
13277 if (*input_line_pointer != ',')
13279 as_bad (_("missing argument separator ',' for .cpsetup"));
13283 ++input_line_pointer;
13284 SKIP_WHITESPACE ();
13285 if (*input_line_pointer == '$')
13287 mips_cpreturn_register = tc_get_register (0);
13288 mips_cpreturn_offset = -1;
13292 mips_cpreturn_offset = get_absolute_expression ();
13293 mips_cpreturn_register = -1;
13295 SKIP_WHITESPACE ();
13296 if (*input_line_pointer != ',')
13298 as_bad (_("missing argument separator ',' for .cpsetup"));
13302 ++input_line_pointer;
13303 SKIP_WHITESPACE ();
13304 expression (&ex_sym);
13307 if (mips_cpreturn_register == -1)
13309 ex_off.X_op = O_constant;
13310 ex_off.X_add_symbol = NULL;
13311 ex_off.X_op_symbol = NULL;
13312 ex_off.X_add_number = mips_cpreturn_offset;
13314 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13315 BFD_RELOC_LO16, SP);
13318 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13319 mips_gp_register, 0);
13321 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13323 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13324 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13327 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13328 mips_gp_register, -1, BFD_RELOC_GPREL16,
13329 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13331 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13332 mips_gp_register, reg1);
13338 ex.X_op = O_symbol;
13339 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13340 ex.X_op_symbol = NULL;
13341 ex.X_add_number = 0;
13343 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13344 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13346 macro_build_lui (&ex, mips_gp_register);
13347 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13348 mips_gp_register, BFD_RELOC_LO16);
13353 demand_empty_rest_of_line ();
13357 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13359 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13360 .cplocal is ignored. */
13361 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13367 mips_gp_register = tc_get_register (0);
13368 demand_empty_rest_of_line ();
13371 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13372 offset from $sp. The offset is remembered, and after making a PIC
13373 call $gp is restored from that location. */
13376 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13380 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13381 .cprestore is ignored. */
13382 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13388 mips_cprestore_offset = get_absolute_expression ();
13389 mips_cprestore_valid = 1;
13391 ex.X_op = O_constant;
13392 ex.X_add_symbol = NULL;
13393 ex.X_op_symbol = NULL;
13394 ex.X_add_number = mips_cprestore_offset;
13397 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13398 SP, HAVE_64BIT_ADDRESSES);
13401 demand_empty_rest_of_line ();
13404 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13405 was given in the preceding .cpsetup, it results in:
13406 ld $gp, offset($sp)
13408 If a register $reg2 was given there, it results in:
13409 daddu $gp, $reg2, $0 */
13412 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13416 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13417 We also need NewABI support. */
13418 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13425 if (mips_cpreturn_register == -1)
13427 ex.X_op = O_constant;
13428 ex.X_add_symbol = NULL;
13429 ex.X_op_symbol = NULL;
13430 ex.X_add_number = mips_cpreturn_offset;
13432 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13435 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13436 mips_cpreturn_register, 0);
13439 demand_empty_rest_of_line ();
13442 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13443 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13444 use in DWARF debug information. */
13447 s_dtprel_internal (size_t bytes)
13454 if (ex.X_op != O_symbol)
13456 as_bad (_("Unsupported use of %s"), (bytes == 8
13459 ignore_rest_of_line ();
13462 p = frag_more (bytes);
13463 md_number_to_chars (p, 0, bytes);
13464 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13466 ? BFD_RELOC_MIPS_TLS_DTPREL64
13467 : BFD_RELOC_MIPS_TLS_DTPREL32));
13469 demand_empty_rest_of_line ();
13472 /* Handle .dtprelword. */
13475 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13477 s_dtprel_internal (4);
13480 /* Handle .dtpreldword. */
13483 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13485 s_dtprel_internal (8);
13488 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13489 code. It sets the offset to use in gp_rel relocations. */
13492 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13494 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13495 We also need NewABI support. */
13496 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13502 mips_gprel_offset = get_absolute_expression ();
13504 demand_empty_rest_of_line ();
13507 /* Handle the .gpword pseudo-op. This is used when generating PIC
13508 code. It generates a 32 bit GP relative reloc. */
13511 s_gpword (int ignore ATTRIBUTE_UNUSED)
13513 segment_info_type *si;
13514 struct insn_label_list *l;
13519 /* When not generating PIC code, this is treated as .word. */
13520 if (mips_pic != SVR4_PIC)
13526 si = seg_info (now_seg);
13527 l = si->label_list;
13528 label = l != NULL ? l->label : NULL;
13529 mips_emit_delays ();
13531 mips_align (2, 0, label);
13532 mips_clear_insn_labels ();
13536 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13538 as_bad (_("Unsupported use of .gpword"));
13539 ignore_rest_of_line ();
13543 md_number_to_chars (p, 0, 4);
13544 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13545 BFD_RELOC_GPREL32);
13547 demand_empty_rest_of_line ();
13551 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13553 segment_info_type *si;
13554 struct insn_label_list *l;
13559 /* When not generating PIC code, this is treated as .dword. */
13560 if (mips_pic != SVR4_PIC)
13566 si = seg_info (now_seg);
13567 l = si->label_list;
13568 label = l != NULL ? l->label : NULL;
13569 mips_emit_delays ();
13571 mips_align (3, 0, label);
13572 mips_clear_insn_labels ();
13576 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13578 as_bad (_("Unsupported use of .gpdword"));
13579 ignore_rest_of_line ();
13583 md_number_to_chars (p, 0, 8);
13584 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13585 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13587 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13588 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13589 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13591 demand_empty_rest_of_line ();
13594 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13595 tables in SVR4 PIC code. */
13598 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13602 /* This is ignored when not generating SVR4 PIC code. */
13603 if (mips_pic != SVR4_PIC)
13609 /* Add $gp to the register named as an argument. */
13611 reg = tc_get_register (0);
13612 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13615 demand_empty_rest_of_line ();
13618 /* Handle the .insn pseudo-op. This marks instruction labels in
13619 mips16 mode. This permits the linker to handle them specially,
13620 such as generating jalx instructions when needed. We also make
13621 them odd for the duration of the assembly, in order to generate the
13622 right sort of code. We will make them even in the adjust_symtab
13623 routine, while leaving them marked. This is convenient for the
13624 debugger and the disassembler. The linker knows to make them odd
13628 s_insn (int ignore ATTRIBUTE_UNUSED)
13630 mips16_mark_labels ();
13632 demand_empty_rest_of_line ();
13635 /* Handle a .stabn directive. We need these in order to mark a label
13636 as being a mips16 text label correctly. Sometimes the compiler
13637 will emit a label, followed by a .stabn, and then switch sections.
13638 If the label and .stabn are in mips16 mode, then the label is
13639 really a mips16 text label. */
13642 s_mips_stab (int type)
13645 mips16_mark_labels ();
13650 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13653 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13660 name = input_line_pointer;
13661 c = get_symbol_end ();
13662 symbolP = symbol_find_or_make (name);
13663 S_SET_WEAK (symbolP);
13664 *input_line_pointer = c;
13666 SKIP_WHITESPACE ();
13668 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13670 if (S_IS_DEFINED (symbolP))
13672 as_bad (_("ignoring attempt to redefine symbol %s"),
13673 S_GET_NAME (symbolP));
13674 ignore_rest_of_line ();
13678 if (*input_line_pointer == ',')
13680 ++input_line_pointer;
13681 SKIP_WHITESPACE ();
13685 if (exp.X_op != O_symbol)
13687 as_bad (_("bad .weakext directive"));
13688 ignore_rest_of_line ();
13691 symbol_set_value_expression (symbolP, &exp);
13694 demand_empty_rest_of_line ();
13697 /* Parse a register string into a number. Called from the ECOFF code
13698 to parse .frame. The argument is non-zero if this is the frame
13699 register, so that we can record it in mips_frame_reg. */
13702 tc_get_register (int frame)
13706 SKIP_WHITESPACE ();
13707 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13711 mips_frame_reg = reg != 0 ? reg : SP;
13712 mips_frame_reg_valid = 1;
13713 mips_cprestore_valid = 0;
13719 md_section_align (asection *seg, valueT addr)
13721 int align = bfd_get_section_alignment (stdoutput, seg);
13725 /* We don't need to align ELF sections to the full alignment.
13726 However, Irix 5 may prefer that we align them at least to a 16
13727 byte boundary. We don't bother to align the sections if we
13728 are targeted for an embedded system. */
13729 if (strncmp (TARGET_OS, "elf", 3) == 0)
13735 return ((addr + (1 << align) - 1) & (-1 << align));
13738 /* Utility routine, called from above as well. If called while the
13739 input file is still being read, it's only an approximation. (For
13740 example, a symbol may later become defined which appeared to be
13741 undefined earlier.) */
13744 nopic_need_relax (symbolS *sym, int before_relaxing)
13749 if (g_switch_value > 0)
13751 const char *symname;
13754 /* Find out whether this symbol can be referenced off the $gp
13755 register. It can be if it is smaller than the -G size or if
13756 it is in the .sdata or .sbss section. Certain symbols can
13757 not be referenced off the $gp, although it appears as though
13759 symname = S_GET_NAME (sym);
13760 if (symname != (const char *) NULL
13761 && (strcmp (symname, "eprol") == 0
13762 || strcmp (symname, "etext") == 0
13763 || strcmp (symname, "_gp") == 0
13764 || strcmp (symname, "edata") == 0
13765 || strcmp (symname, "_fbss") == 0
13766 || strcmp (symname, "_fdata") == 0
13767 || strcmp (symname, "_ftext") == 0
13768 || strcmp (symname, "end") == 0
13769 || strcmp (symname, "_gp_disp") == 0))
13771 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
13773 #ifndef NO_ECOFF_DEBUGGING
13774 || (symbol_get_obj (sym)->ecoff_extern_size != 0
13775 && (symbol_get_obj (sym)->ecoff_extern_size
13776 <= g_switch_value))
13778 /* We must defer this decision until after the whole
13779 file has been read, since there might be a .extern
13780 after the first use of this symbol. */
13781 || (before_relaxing
13782 #ifndef NO_ECOFF_DEBUGGING
13783 && symbol_get_obj (sym)->ecoff_extern_size == 0
13785 && S_GET_VALUE (sym) == 0)
13786 || (S_GET_VALUE (sym) != 0
13787 && S_GET_VALUE (sym) <= g_switch_value)))
13791 const char *segname;
13793 segname = segment_name (S_GET_SEGMENT (sym));
13794 gas_assert (strcmp (segname, ".lit8") != 0
13795 && strcmp (segname, ".lit4") != 0);
13796 change = (strcmp (segname, ".sdata") != 0
13797 && strcmp (segname, ".sbss") != 0
13798 && strncmp (segname, ".sdata.", 7) != 0
13799 && strncmp (segname, ".sbss.", 6) != 0
13800 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13801 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13806 /* We are not optimizing for the $gp register. */
13811 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13814 pic_need_relax (symbolS *sym, asection *segtype)
13818 /* Handle the case of a symbol equated to another symbol. */
13819 while (symbol_equated_reloc_p (sym))
13823 /* It's possible to get a loop here in a badly written program. */
13824 n = symbol_get_value_expression (sym)->X_add_symbol;
13830 if (symbol_section_p (sym))
13833 symsec = S_GET_SEGMENT (sym);
13835 /* This must duplicate the test in adjust_reloc_syms. */
13836 return (symsec != &bfd_und_section
13837 && symsec != &bfd_abs_section
13838 && !bfd_is_com_section (symsec)
13839 && !s_is_linkonce (sym, segtype)
13841 /* A global or weak symbol is treated as external. */
13842 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13848 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13849 extended opcode. SEC is the section the frag is in. */
13852 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13855 const struct mips16_immed_operand *op;
13857 int mintiny, maxtiny;
13861 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13863 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
13866 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13867 op = mips16_immed_operands;
13868 while (op->type != type)
13871 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13876 if (type == '<' || type == '>' || type == '[' || type == ']')
13879 maxtiny = 1 << op->nbits;
13884 maxtiny = (1 << op->nbits) - 1;
13889 mintiny = - (1 << (op->nbits - 1));
13890 maxtiny = (1 << (op->nbits - 1)) - 1;
13893 sym_frag = symbol_get_frag (fragp->fr_symbol);
13894 val = S_GET_VALUE (fragp->fr_symbol);
13895 symsec = S_GET_SEGMENT (fragp->fr_symbol);
13901 /* We won't have the section when we are called from
13902 mips_relax_frag. However, we will always have been called
13903 from md_estimate_size_before_relax first. If this is a
13904 branch to a different section, we mark it as such. If SEC is
13905 NULL, and the frag is not marked, then it must be a branch to
13906 the same section. */
13909 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
13914 /* Must have been called from md_estimate_size_before_relax. */
13917 fragp->fr_subtype =
13918 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
13920 /* FIXME: We should support this, and let the linker
13921 catch branches and loads that are out of range. */
13922 as_bad_where (fragp->fr_file, fragp->fr_line,
13923 _("unsupported PC relative reference to different section"));
13927 if (fragp != sym_frag && sym_frag->fr_address == 0)
13928 /* Assume non-extended on the first relaxation pass.
13929 The address we have calculated will be bogus if this is
13930 a forward branch to another frag, as the forward frag
13931 will have fr_address == 0. */
13935 /* In this case, we know for sure that the symbol fragment is in
13936 the same section. If the relax_marker of the symbol fragment
13937 differs from the relax_marker of this fragment, we have not
13938 yet adjusted the symbol fragment fr_address. We want to add
13939 in STRETCH in order to get a better estimate of the address.
13940 This particularly matters because of the shift bits. */
13942 && sym_frag->relax_marker != fragp->relax_marker)
13946 /* Adjust stretch for any alignment frag. Note that if have
13947 been expanding the earlier code, the symbol may be
13948 defined in what appears to be an earlier frag. FIXME:
13949 This doesn't handle the fr_subtype field, which specifies
13950 a maximum number of bytes to skip when doing an
13952 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
13954 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
13957 stretch = - ((- stretch)
13958 & ~ ((1 << (int) f->fr_offset) - 1));
13960 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
13969 addr = fragp->fr_address + fragp->fr_fix;
13971 /* The base address rules are complicated. The base address of
13972 a branch is the following instruction. The base address of a
13973 PC relative load or add is the instruction itself, but if it
13974 is in a delay slot (in which case it can not be extended) use
13975 the address of the instruction whose delay slot it is in. */
13976 if (type == 'p' || type == 'q')
13980 /* If we are currently assuming that this frag should be
13981 extended, then, the current address is two bytes
13983 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13986 /* Ignore the low bit in the target, since it will be set
13987 for a text label. */
13988 if ((val & 1) != 0)
13991 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13993 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13996 val -= addr & ~ ((1 << op->shift) - 1);
13998 /* Branch offsets have an implicit 0 in the lowest bit. */
13999 if (type == 'p' || type == 'q')
14002 /* If any of the shifted bits are set, we must use an extended
14003 opcode. If the address depends on the size of this
14004 instruction, this can lead to a loop, so we arrange to always
14005 use an extended opcode. We only check this when we are in
14006 the main relaxation loop, when SEC is NULL. */
14007 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14009 fragp->fr_subtype =
14010 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14014 /* If we are about to mark a frag as extended because the value
14015 is precisely maxtiny + 1, then there is a chance of an
14016 infinite loop as in the following code:
14021 In this case when the la is extended, foo is 0x3fc bytes
14022 away, so the la can be shrunk, but then foo is 0x400 away, so
14023 the la must be extended. To avoid this loop, we mark the
14024 frag as extended if it was small, and is about to become
14025 extended with a value of maxtiny + 1. */
14026 if (val == ((maxtiny + 1) << op->shift)
14027 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14030 fragp->fr_subtype =
14031 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14035 else if (symsec != absolute_section && sec != NULL)
14036 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14038 if ((val & ((1 << op->shift) - 1)) != 0
14039 || val < (mintiny << op->shift)
14040 || val > (maxtiny << op->shift))
14046 /* Compute the length of a branch sequence, and adjust the
14047 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14048 worst-case length is computed, with UPDATE being used to indicate
14049 whether an unconditional (-1), branch-likely (+1) or regular (0)
14050 branch is to be computed. */
14052 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14054 bfd_boolean toofar;
14058 && S_IS_DEFINED (fragp->fr_symbol)
14059 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14064 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14066 addr = fragp->fr_address + fragp->fr_fix + 4;
14070 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14073 /* If the symbol is not defined or it's in a different segment,
14074 assume the user knows what's going on and emit a short
14080 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14082 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14083 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14084 RELAX_BRANCH_LINK (fragp->fr_subtype),
14090 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14093 if (mips_pic != NO_PIC)
14095 /* Additional space for PIC loading of target address. */
14097 if (mips_opts.isa == ISA_MIPS1)
14098 /* Additional space for $at-stabilizing nop. */
14102 /* If branch is conditional. */
14103 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14110 /* Estimate the size of a frag before relaxing. Unless this is the
14111 mips16, we are not really relaxing here, and the final size is
14112 encoded in the subtype information. For the mips16, we have to
14113 decide whether we are using an extended opcode or not. */
14116 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14120 if (RELAX_BRANCH_P (fragp->fr_subtype))
14123 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14125 return fragp->fr_var;
14128 if (RELAX_MIPS16_P (fragp->fr_subtype))
14129 /* We don't want to modify the EXTENDED bit here; it might get us
14130 into infinite loops. We change it only in mips_relax_frag(). */
14131 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14133 if (mips_pic == NO_PIC)
14134 change = nopic_need_relax (fragp->fr_symbol, 0);
14135 else if (mips_pic == SVR4_PIC)
14136 change = pic_need_relax (fragp->fr_symbol, segtype);
14137 else if (mips_pic == VXWORKS_PIC)
14138 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14145 fragp->fr_subtype |= RELAX_USE_SECOND;
14146 return -RELAX_FIRST (fragp->fr_subtype);
14149 return -RELAX_SECOND (fragp->fr_subtype);
14152 /* This is called to see whether a reloc against a defined symbol
14153 should be converted into a reloc against a section. */
14156 mips_fix_adjustable (fixS *fixp)
14158 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14159 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14162 if (fixp->fx_addsy == NULL)
14165 /* If symbol SYM is in a mergeable section, relocations of the form
14166 SYM + 0 can usually be made section-relative. The mergeable data
14167 is then identified by the section offset rather than by the symbol.
14169 However, if we're generating REL LO16 relocations, the offset is split
14170 between the LO16 and parterning high part relocation. The linker will
14171 need to recalculate the complete offset in order to correctly identify
14174 The linker has traditionally not looked for the parterning high part
14175 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14176 placed anywhere. Rather than break backwards compatibility by changing
14177 this, it seems better not to force the issue, and instead keep the
14178 original symbol. This will work with either linker behavior. */
14179 if ((lo16_reloc_p (fixp->fx_r_type)
14180 || reloc_needs_lo_p (fixp->fx_r_type))
14181 && HAVE_IN_PLACE_ADDENDS
14182 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14185 /* There is no place to store an in-place offset for JALR relocations. */
14186 if (fixp->fx_r_type == BFD_RELOC_MIPS_JALR && HAVE_IN_PLACE_ADDENDS)
14190 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14191 to a floating-point stub. The same is true for non-R_MIPS16_26
14192 relocations against MIPS16 functions; in this case, the stub becomes
14193 the function's canonical address.
14195 Floating-point stubs are stored in unique .mips16.call.* or
14196 .mips16.fn.* sections. If a stub T for function F is in section S,
14197 the first relocation in section S must be against F; this is how the
14198 linker determines the target function. All relocations that might
14199 resolve to T must also be against F. We therefore have the following
14200 restrictions, which are given in an intentionally-redundant way:
14202 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14205 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14206 if that stub might be used.
14208 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14211 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14212 that stub might be used.
14214 There is a further restriction:
14216 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14217 on targets with in-place addends; the relocation field cannot
14218 encode the low bit.
14220 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14221 against a MIPS16 symbol.
14223 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14224 relocation against some symbol R, no relocation against R may be
14225 reduced. (Note that this deals with (2) as well as (1) because
14226 relocations against global symbols will never be reduced on ELF
14227 targets.) This approach is a little simpler than trying to detect
14228 stub sections, and gives the "all or nothing" per-symbol consistency
14229 that we have for MIPS16 symbols. */
14231 && fixp->fx_subsy == NULL
14232 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14233 || *symbol_get_tc (fixp->fx_addsy)))
14240 /* Translate internal representation of relocation info to BFD target
14244 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14246 static arelent *retval[4];
14248 bfd_reloc_code_real_type code;
14250 memset (retval, 0, sizeof(retval));
14251 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14252 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14253 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14254 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14256 if (fixp->fx_pcrel)
14258 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14260 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14261 Relocations want only the symbol offset. */
14262 reloc->addend = fixp->fx_addnumber + reloc->address;
14265 /* A gruesome hack which is a result of the gruesome gas
14266 reloc handling. What's worse, for COFF (as opposed to
14267 ECOFF), we might need yet another copy of reloc->address.
14268 See bfd_install_relocation. */
14269 reloc->addend += reloc->address;
14273 reloc->addend = fixp->fx_addnumber;
14275 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14276 entry to be used in the relocation's section offset. */
14277 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14279 reloc->address = reloc->addend;
14283 code = fixp->fx_r_type;
14285 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14286 if (reloc->howto == NULL)
14288 as_bad_where (fixp->fx_file, fixp->fx_line,
14289 _("Can not represent %s relocation in this object file format"),
14290 bfd_get_reloc_code_name (code));
14297 /* Relax a machine dependent frag. This returns the amount by which
14298 the current size of the frag should change. */
14301 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14303 if (RELAX_BRANCH_P (fragp->fr_subtype))
14305 offsetT old_var = fragp->fr_var;
14307 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14309 return fragp->fr_var - old_var;
14312 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14315 if (mips16_extended_frag (fragp, NULL, stretch))
14317 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14319 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14324 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14326 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14333 /* Convert a machine dependent frag. */
14336 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14338 if (RELAX_BRANCH_P (fragp->fr_subtype))
14341 unsigned long insn;
14345 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14347 if (target_big_endian)
14348 insn = bfd_getb32 (buf);
14350 insn = bfd_getl32 (buf);
14352 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14354 /* We generate a fixup instead of applying it right now
14355 because, if there are linker relaxations, we're going to
14356 need the relocations. */
14357 exp.X_op = O_symbol;
14358 exp.X_add_symbol = fragp->fr_symbol;
14359 exp.X_add_number = fragp->fr_offset;
14361 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14362 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14363 fixp->fx_file = fragp->fr_file;
14364 fixp->fx_line = fragp->fr_line;
14366 md_number_to_chars ((char *) buf, insn, 4);
14373 as_warn_where (fragp->fr_file, fragp->fr_line,
14374 _("relaxed out-of-range branch into a jump"));
14376 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14379 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14381 /* Reverse the branch. */
14382 switch ((insn >> 28) & 0xf)
14385 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14386 have the condition reversed by tweaking a single
14387 bit, and their opcodes all have 0x4???????. */
14388 gas_assert ((insn & 0xf1000000) == 0x41000000);
14389 insn ^= 0x00010000;
14393 /* bltz 0x04000000 bgez 0x04010000
14394 bltzal 0x04100000 bgezal 0x04110000 */
14395 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14396 insn ^= 0x00010000;
14400 /* beq 0x10000000 bne 0x14000000
14401 blez 0x18000000 bgtz 0x1c000000 */
14402 insn ^= 0x04000000;
14410 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14412 /* Clear the and-link bit. */
14413 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14415 /* bltzal 0x04100000 bgezal 0x04110000
14416 bltzall 0x04120000 bgezall 0x04130000 */
14417 insn &= ~0x00100000;
14420 /* Branch over the branch (if the branch was likely) or the
14421 full jump (not likely case). Compute the offset from the
14422 current instruction to branch to. */
14423 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14427 /* How many bytes in instructions we've already emitted? */
14428 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14429 /* How many bytes in instructions from here to the end? */
14430 i = fragp->fr_var - i;
14432 /* Convert to instruction count. */
14434 /* Branch counts from the next instruction. */
14437 /* Branch over the jump. */
14438 md_number_to_chars ((char *) buf, insn, 4);
14442 md_number_to_chars ((char *) buf, 0, 4);
14445 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14447 /* beql $0, $0, 2f */
14449 /* Compute the PC offset from the current instruction to
14450 the end of the variable frag. */
14451 /* How many bytes in instructions we've already emitted? */
14452 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14453 /* How many bytes in instructions from here to the end? */
14454 i = fragp->fr_var - i;
14455 /* Convert to instruction count. */
14457 /* Don't decrement i, because we want to branch over the
14461 md_number_to_chars ((char *) buf, insn, 4);
14464 md_number_to_chars ((char *) buf, 0, 4);
14469 if (mips_pic == NO_PIC)
14472 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14473 ? 0x0c000000 : 0x08000000);
14474 exp.X_op = O_symbol;
14475 exp.X_add_symbol = fragp->fr_symbol;
14476 exp.X_add_number = fragp->fr_offset;
14478 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14479 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14480 fixp->fx_file = fragp->fr_file;
14481 fixp->fx_line = fragp->fr_line;
14483 md_number_to_chars ((char *) buf, insn, 4);
14488 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14489 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
14490 exp.X_op = O_symbol;
14491 exp.X_add_symbol = fragp->fr_symbol;
14492 exp.X_add_number = fragp->fr_offset;
14494 if (fragp->fr_offset)
14496 exp.X_add_symbol = make_expr_symbol (&exp);
14497 exp.X_add_number = 0;
14500 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14501 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14502 fixp->fx_file = fragp->fr_file;
14503 fixp->fx_line = fragp->fr_line;
14505 md_number_to_chars ((char *) buf, insn, 4);
14508 if (mips_opts.isa == ISA_MIPS1)
14511 md_number_to_chars ((char *) buf, 0, 4);
14515 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14516 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14518 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14519 4, &exp, FALSE, BFD_RELOC_LO16);
14520 fixp->fx_file = fragp->fr_file;
14521 fixp->fx_line = fragp->fr_line;
14523 md_number_to_chars ((char *) buf, insn, 4);
14527 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14532 md_number_to_chars ((char *) buf, insn, 4);
14537 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14538 + fragp->fr_fix + fragp->fr_var);
14540 fragp->fr_fix += fragp->fr_var;
14545 if (RELAX_MIPS16_P (fragp->fr_subtype))
14548 const struct mips16_immed_operand *op;
14549 bfd_boolean small, ext;
14552 unsigned long insn;
14553 bfd_boolean use_extend;
14554 unsigned short extend;
14556 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14557 op = mips16_immed_operands;
14558 while (op->type != type)
14561 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14572 resolve_symbol_value (fragp->fr_symbol);
14573 val = S_GET_VALUE (fragp->fr_symbol);
14578 addr = fragp->fr_address + fragp->fr_fix;
14580 /* The rules for the base address of a PC relative reloc are
14581 complicated; see mips16_extended_frag. */
14582 if (type == 'p' || type == 'q')
14587 /* Ignore the low bit in the target, since it will be
14588 set for a text label. */
14589 if ((val & 1) != 0)
14592 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14594 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14597 addr &= ~ (addressT) ((1 << op->shift) - 1);
14600 /* Make sure the section winds up with the alignment we have
14603 record_alignment (asec, op->shift);
14607 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14608 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14609 as_warn_where (fragp->fr_file, fragp->fr_line,
14610 _("extended instruction in delay slot"));
14612 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14614 if (target_big_endian)
14615 insn = bfd_getb16 (buf);
14617 insn = bfd_getl16 (buf);
14619 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14620 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14621 small, ext, &insn, &use_extend, &extend);
14625 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14626 fragp->fr_fix += 2;
14630 md_number_to_chars ((char *) buf, insn, 2);
14631 fragp->fr_fix += 2;
14639 first = RELAX_FIRST (fragp->fr_subtype);
14640 second = RELAX_SECOND (fragp->fr_subtype);
14641 fixp = (fixS *) fragp->fr_opcode;
14643 /* Possibly emit a warning if we've chosen the longer option. */
14644 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14645 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14647 const char *msg = macro_warning (fragp->fr_subtype);
14649 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14652 /* Go through all the fixups for the first sequence. Disable them
14653 (by marking them as done) if we're going to use the second
14654 sequence instead. */
14656 && fixp->fx_frag == fragp
14657 && fixp->fx_where < fragp->fr_fix - second)
14659 if (fragp->fr_subtype & RELAX_USE_SECOND)
14661 fixp = fixp->fx_next;
14664 /* Go through the fixups for the second sequence. Disable them if
14665 we're going to use the first sequence, otherwise adjust their
14666 addresses to account for the relaxation. */
14667 while (fixp && fixp->fx_frag == fragp)
14669 if (fragp->fr_subtype & RELAX_USE_SECOND)
14670 fixp->fx_where -= first;
14673 fixp = fixp->fx_next;
14676 /* Now modify the frag contents. */
14677 if (fragp->fr_subtype & RELAX_USE_SECOND)
14681 start = fragp->fr_literal + fragp->fr_fix - first - second;
14682 memmove (start, start + first, second);
14683 fragp->fr_fix -= first;
14686 fragp->fr_fix -= second;
14692 /* This function is called after the relocs have been generated.
14693 We've been storing mips16 text labels as odd. Here we convert them
14694 back to even for the convenience of the debugger. */
14697 mips_frob_file_after_relocs (void)
14700 unsigned int count, i;
14705 syms = bfd_get_outsymbols (stdoutput);
14706 count = bfd_get_symcount (stdoutput);
14707 for (i = 0; i < count; i++, syms++)
14709 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
14710 && ((*syms)->value & 1) != 0)
14712 (*syms)->value &= ~1;
14713 /* If the symbol has an odd size, it was probably computed
14714 incorrectly, so adjust that as well. */
14715 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
14716 ++elf_symbol (*syms)->internal_elf_sym.st_size;
14723 /* This function is called whenever a label is defined. It is used
14724 when handling branch delays; if a branch has a label, we assume we
14725 can not move it. */
14728 mips_define_label (symbolS *sym)
14730 segment_info_type *si = seg_info (now_seg);
14731 struct insn_label_list *l;
14733 if (free_insn_labels == NULL)
14734 l = (struct insn_label_list *) xmalloc (sizeof *l);
14737 l = free_insn_labels;
14738 free_insn_labels = l->next;
14742 l->next = si->label_list;
14743 si->label_list = l;
14746 dwarf2_emit_label (sym);
14750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14752 /* Some special processing for a MIPS ELF file. */
14755 mips_elf_final_processing (void)
14757 /* Write out the register information. */
14758 if (mips_abi != N64_ABI)
14762 s.ri_gprmask = mips_gprmask;
14763 s.ri_cprmask[0] = mips_cprmask[0];
14764 s.ri_cprmask[1] = mips_cprmask[1];
14765 s.ri_cprmask[2] = mips_cprmask[2];
14766 s.ri_cprmask[3] = mips_cprmask[3];
14767 /* The gp_value field is set by the MIPS ELF backend. */
14769 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
14770 ((Elf32_External_RegInfo *)
14771 mips_regmask_frag));
14775 Elf64_Internal_RegInfo s;
14777 s.ri_gprmask = mips_gprmask;
14779 s.ri_cprmask[0] = mips_cprmask[0];
14780 s.ri_cprmask[1] = mips_cprmask[1];
14781 s.ri_cprmask[2] = mips_cprmask[2];
14782 s.ri_cprmask[3] = mips_cprmask[3];
14783 /* The gp_value field is set by the MIPS ELF backend. */
14785 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
14786 ((Elf64_External_RegInfo *)
14787 mips_regmask_frag));
14790 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14791 sort of BFD interface for this. */
14792 if (mips_any_noreorder)
14793 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
14794 if (mips_pic != NO_PIC)
14796 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14797 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14800 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14802 /* Set MIPS ELF flags for ASEs. */
14803 /* We may need to define a new flag for DSP ASE, and set this flag when
14804 file_ase_dsp is true. */
14805 /* Same for DSP R2. */
14806 /* We may need to define a new flag for MT ASE, and set this flag when
14807 file_ase_mt is true. */
14808 if (file_ase_mips16)
14809 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14810 #if 0 /* XXX FIXME */
14811 if (file_ase_mips3d)
14812 elf_elfheader (stdoutput)->e_flags |= ???;
14815 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
14817 /* Set the MIPS ELF ABI flags. */
14818 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
14819 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
14820 else if (mips_abi == O64_ABI)
14821 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
14822 else if (mips_abi == EABI_ABI)
14824 if (!file_mips_gp32)
14825 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
14827 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
14829 else if (mips_abi == N32_ABI)
14830 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14832 /* Nothing to do for N64_ABI. */
14834 if (mips_32bitmode)
14835 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14837 #if 0 /* XXX FIXME */
14838 /* 32 bit code with 64 bit FP registers. */
14839 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14840 elf_elfheader (stdoutput)->e_flags |= ???;
14844 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14846 typedef struct proc {
14848 symbolS *func_end_sym;
14849 unsigned long reg_mask;
14850 unsigned long reg_offset;
14851 unsigned long fpreg_mask;
14852 unsigned long fpreg_offset;
14853 unsigned long frame_offset;
14854 unsigned long frame_reg;
14855 unsigned long pc_reg;
14858 static procS cur_proc;
14859 static procS *cur_proc_ptr;
14860 static int numprocs;
14862 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14866 mips_nop_opcode (void)
14868 return seg_info (now_seg)->tc_segment_info_data.mips16;
14871 /* Fill in an rs_align_code fragment. This only needs to do something
14872 for MIPS16 code, where 0 is not a nop. */
14875 mips_handle_align (fragS *fragp)
14878 int bytes, size, excess;
14881 if (fragp->fr_type != rs_align_code)
14884 p = fragp->fr_literal + fragp->fr_fix;
14887 opcode = mips16_nop_insn.insn_opcode;
14892 opcode = nop_insn.insn_opcode;
14896 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
14897 excess = bytes % size;
14900 /* If we're not inserting a whole number of instructions,
14901 pad the end of the fixed part of the frag with zeros. */
14902 memset (p, 0, excess);
14904 fragp->fr_fix += excess;
14907 md_number_to_chars (p, opcode, size);
14908 fragp->fr_var = size;
14912 md_obj_begin (void)
14919 /* Check for premature end, nesting errors, etc. */
14921 as_warn (_("missing .end at end of assembly"));
14930 if (*input_line_pointer == '-')
14932 ++input_line_pointer;
14935 if (!ISDIGIT (*input_line_pointer))
14936 as_bad (_("expected simple number"));
14937 if (input_line_pointer[0] == '0')
14939 if (input_line_pointer[1] == 'x')
14941 input_line_pointer += 2;
14942 while (ISXDIGIT (*input_line_pointer))
14945 val |= hex_value (*input_line_pointer++);
14947 return negative ? -val : val;
14951 ++input_line_pointer;
14952 while (ISDIGIT (*input_line_pointer))
14955 val |= *input_line_pointer++ - '0';
14957 return negative ? -val : val;
14960 if (!ISDIGIT (*input_line_pointer))
14962 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14963 *input_line_pointer, *input_line_pointer);
14964 as_warn (_("invalid number"));
14967 while (ISDIGIT (*input_line_pointer))
14970 val += *input_line_pointer++ - '0';
14972 return negative ? -val : val;
14975 /* The .file directive; just like the usual .file directive, but there
14976 is an initial number which is the ECOFF file index. In the non-ECOFF
14977 case .file implies DWARF-2. */
14980 s_mips_file (int x ATTRIBUTE_UNUSED)
14982 static int first_file_directive = 0;
14984 if (ECOFF_DEBUGGING)
14993 filename = dwarf2_directive_file (0);
14995 /* Versions of GCC up to 3.1 start files with a ".file"
14996 directive even for stabs output. Make sure that this
14997 ".file" is handled. Note that you need a version of GCC
14998 after 3.1 in order to support DWARF-2 on MIPS. */
14999 if (filename != NULL && ! first_file_directive)
15001 (void) new_logical_line (filename, -1);
15002 s_app_file_string (filename, 0);
15004 first_file_directive = 1;
15008 /* The .loc directive, implying DWARF-2. */
15011 s_mips_loc (int x ATTRIBUTE_UNUSED)
15013 if (!ECOFF_DEBUGGING)
15014 dwarf2_directive_loc (0);
15017 /* The .end directive. */
15020 s_mips_end (int x ATTRIBUTE_UNUSED)
15024 /* Following functions need their own .frame and .cprestore directives. */
15025 mips_frame_reg_valid = 0;
15026 mips_cprestore_valid = 0;
15028 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15031 demand_empty_rest_of_line ();
15036 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15037 as_warn (_(".end not in text section"));
15041 as_warn (_(".end directive without a preceding .ent directive."));
15042 demand_empty_rest_of_line ();
15048 gas_assert (S_GET_NAME (p));
15049 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15050 as_warn (_(".end symbol does not match .ent symbol."));
15052 if (debug_type == DEBUG_STABS)
15053 stabs_generate_asm_endfunc (S_GET_NAME (p),
15057 as_warn (_(".end directive missing or unknown symbol"));
15060 /* Create an expression to calculate the size of the function. */
15061 if (p && cur_proc_ptr)
15063 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15064 expressionS *exp = xmalloc (sizeof (expressionS));
15067 exp->X_op = O_subtract;
15068 exp->X_add_symbol = symbol_temp_new_now ();
15069 exp->X_op_symbol = p;
15070 exp->X_add_number = 0;
15072 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15075 /* Generate a .pdr section. */
15076 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15078 segT saved_seg = now_seg;
15079 subsegT saved_subseg = now_subseg;
15084 dot = frag_now_fix ();
15086 #ifdef md_flush_pending_output
15087 md_flush_pending_output ();
15090 gas_assert (pdr_seg);
15091 subseg_set (pdr_seg, 0);
15093 /* Write the symbol. */
15094 exp.X_op = O_symbol;
15095 exp.X_add_symbol = p;
15096 exp.X_add_number = 0;
15097 emit_expr (&exp, 4);
15099 fragp = frag_more (7 * 4);
15101 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15102 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15103 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15104 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15105 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15106 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15107 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15109 subseg_set (saved_seg, saved_subseg);
15111 #endif /* OBJ_ELF */
15113 cur_proc_ptr = NULL;
15116 /* The .aent and .ent directives. */
15119 s_mips_ent (int aent)
15123 symbolP = get_symbol ();
15124 if (*input_line_pointer == ',')
15125 ++input_line_pointer;
15126 SKIP_WHITESPACE ();
15127 if (ISDIGIT (*input_line_pointer)
15128 || *input_line_pointer == '-')
15131 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15132 as_warn (_(".ent or .aent not in text section."));
15134 if (!aent && cur_proc_ptr)
15135 as_warn (_("missing .end"));
15139 /* This function needs its own .frame and .cprestore directives. */
15140 mips_frame_reg_valid = 0;
15141 mips_cprestore_valid = 0;
15143 cur_proc_ptr = &cur_proc;
15144 memset (cur_proc_ptr, '\0', sizeof (procS));
15146 cur_proc_ptr->func_sym = symbolP;
15150 if (debug_type == DEBUG_STABS)
15151 stabs_generate_asm_func (S_GET_NAME (symbolP),
15152 S_GET_NAME (symbolP));
15155 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15157 demand_empty_rest_of_line ();
15160 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15161 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15162 s_mips_frame is used so that we can set the PDR information correctly.
15163 We can't use the ecoff routines because they make reference to the ecoff
15164 symbol table (in the mdebug section). */
15167 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15170 if (IS_ELF && !ECOFF_DEBUGGING)
15174 if (cur_proc_ptr == (procS *) NULL)
15176 as_warn (_(".frame outside of .ent"));
15177 demand_empty_rest_of_line ();
15181 cur_proc_ptr->frame_reg = tc_get_register (1);
15183 SKIP_WHITESPACE ();
15184 if (*input_line_pointer++ != ','
15185 || get_absolute_expression_and_terminator (&val) != ',')
15187 as_warn (_("Bad .frame directive"));
15188 --input_line_pointer;
15189 demand_empty_rest_of_line ();
15193 cur_proc_ptr->frame_offset = val;
15194 cur_proc_ptr->pc_reg = tc_get_register (0);
15196 demand_empty_rest_of_line ();
15199 #endif /* OBJ_ELF */
15203 /* The .fmask and .mask directives. If the mdebug section is present
15204 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15205 embedded targets, s_mips_mask is used so that we can set the PDR
15206 information correctly. We can't use the ecoff routines because they
15207 make reference to the ecoff symbol table (in the mdebug section). */
15210 s_mips_mask (int reg_type)
15213 if (IS_ELF && !ECOFF_DEBUGGING)
15217 if (cur_proc_ptr == (procS *) NULL)
15219 as_warn (_(".mask/.fmask outside of .ent"));
15220 demand_empty_rest_of_line ();
15224 if (get_absolute_expression_and_terminator (&mask) != ',')
15226 as_warn (_("Bad .mask/.fmask directive"));
15227 --input_line_pointer;
15228 demand_empty_rest_of_line ();
15232 off = get_absolute_expression ();
15234 if (reg_type == 'F')
15236 cur_proc_ptr->fpreg_mask = mask;
15237 cur_proc_ptr->fpreg_offset = off;
15241 cur_proc_ptr->reg_mask = mask;
15242 cur_proc_ptr->reg_offset = off;
15245 demand_empty_rest_of_line ();
15248 #endif /* OBJ_ELF */
15249 s_ignore (reg_type);
15252 /* A table describing all the processors gas knows about. Names are
15253 matched in the order listed.
15255 To ease comparison, please keep this table in the same order as
15256 gcc's mips_cpu_info_table[]. */
15257 static const struct mips_cpu_info mips_cpu_info_table[] =
15259 /* Entries for generic ISAs */
15260 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15261 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15262 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15263 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15264 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15265 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15266 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15267 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15268 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15271 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15272 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15273 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15276 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15279 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15280 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15281 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15282 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15283 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15284 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15285 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15286 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15287 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15288 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15289 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15290 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15291 /* ST Microelectronics Loongson 2E and 2F cores */
15292 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15293 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15296 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15297 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15298 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15299 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15300 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15301 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15302 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15303 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15304 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15305 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15306 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15307 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15308 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15309 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15310 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15313 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15314 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15315 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15316 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15318 /* MIPS 32 Release 2 */
15319 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15320 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15321 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15322 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15323 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15324 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15325 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15326 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15327 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15328 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15329 /* Deprecated forms of the above. */
15330 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15331 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15332 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15333 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15334 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15335 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15336 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15337 /* Deprecated forms of the above. */
15338 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15339 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15340 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15341 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15342 ISA_MIPS32R2, CPU_MIPS32R2 },
15343 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15344 ISA_MIPS32R2, CPU_MIPS32R2 },
15345 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15346 ISA_MIPS32R2, CPU_MIPS32R2 },
15347 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15348 ISA_MIPS32R2, CPU_MIPS32R2 },
15349 /* Deprecated forms of the above. */
15350 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15351 ISA_MIPS32R2, CPU_MIPS32R2 },
15352 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15353 ISA_MIPS32R2, CPU_MIPS32R2 },
15354 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15355 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15356 ISA_MIPS32R2, CPU_MIPS32R2 },
15357 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15358 ISA_MIPS32R2, CPU_MIPS32R2 },
15359 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15360 ISA_MIPS32R2, CPU_MIPS32R2 },
15361 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15362 ISA_MIPS32R2, CPU_MIPS32R2 },
15363 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15364 ISA_MIPS32R2, CPU_MIPS32R2 },
15365 /* Deprecated forms of the above. */
15366 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15367 ISA_MIPS32R2, CPU_MIPS32R2 },
15368 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15369 ISA_MIPS32R2, CPU_MIPS32R2 },
15370 /* 1004K cores are multiprocessor versions of the 34K. */
15371 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15372 ISA_MIPS32R2, CPU_MIPS32R2 },
15373 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15374 ISA_MIPS32R2, CPU_MIPS32R2 },
15375 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15376 ISA_MIPS32R2, CPU_MIPS32R2 },
15377 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15378 ISA_MIPS32R2, CPU_MIPS32R2 },
15381 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15382 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15383 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15384 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15386 /* Broadcom SB-1 CPU core */
15387 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15388 ISA_MIPS64, CPU_SB1 },
15389 /* Broadcom SB-1A CPU core */
15390 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15391 ISA_MIPS64, CPU_SB1 },
15393 /* MIPS 64 Release 2 */
15395 /* Cavium Networks Octeon CPU core */
15396 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15399 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15406 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15407 with a final "000" replaced by "k". Ignore case.
15409 Note: this function is shared between GCC and GAS. */
15412 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15414 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15415 given++, canonical++;
15417 return ((*given == 0 && *canonical == 0)
15418 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15422 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15423 CPU name. We've traditionally allowed a lot of variation here.
15425 Note: this function is shared between GCC and GAS. */
15428 mips_matching_cpu_name_p (const char *canonical, const char *given)
15430 /* First see if the name matches exactly, or with a final "000"
15431 turned into "k". */
15432 if (mips_strict_matching_cpu_name_p (canonical, given))
15435 /* If not, try comparing based on numerical designation alone.
15436 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15437 if (TOLOWER (*given) == 'r')
15439 if (!ISDIGIT (*given))
15442 /* Skip over some well-known prefixes in the canonical name,
15443 hoping to find a number there too. */
15444 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15446 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15448 else if (TOLOWER (canonical[0]) == 'r')
15451 return mips_strict_matching_cpu_name_p (canonical, given);
15455 /* Parse an option that takes the name of a processor as its argument.
15456 OPTION is the name of the option and CPU_STRING is the argument.
15457 Return the corresponding processor enumeration if the CPU_STRING is
15458 recognized, otherwise report an error and return null.
15460 A similar function exists in GCC. */
15462 static const struct mips_cpu_info *
15463 mips_parse_cpu (const char *option, const char *cpu_string)
15465 const struct mips_cpu_info *p;
15467 /* 'from-abi' selects the most compatible architecture for the given
15468 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15469 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15470 version. Look first at the -mgp options, if given, otherwise base
15471 the choice on MIPS_DEFAULT_64BIT.
15473 Treat NO_ABI like the EABIs. One reason to do this is that the
15474 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15475 architecture. This code picks MIPS I for 'mips' and MIPS III for
15476 'mips64', just as we did in the days before 'from-abi'. */
15477 if (strcasecmp (cpu_string, "from-abi") == 0)
15479 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15480 return mips_cpu_info_from_isa (ISA_MIPS1);
15482 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15483 return mips_cpu_info_from_isa (ISA_MIPS3);
15485 if (file_mips_gp32 >= 0)
15486 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15488 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15493 /* 'default' has traditionally been a no-op. Probably not very useful. */
15494 if (strcasecmp (cpu_string, "default") == 0)
15497 for (p = mips_cpu_info_table; p->name != 0; p++)
15498 if (mips_matching_cpu_name_p (p->name, cpu_string))
15501 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15505 /* Return the canonical processor information for ISA (a member of the
15506 ISA_MIPS* enumeration). */
15508 static const struct mips_cpu_info *
15509 mips_cpu_info_from_isa (int isa)
15513 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15514 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15515 && isa == mips_cpu_info_table[i].isa)
15516 return (&mips_cpu_info_table[i]);
15521 static const struct mips_cpu_info *
15522 mips_cpu_info_from_arch (int arch)
15526 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15527 if (arch == mips_cpu_info_table[i].cpu)
15528 return (&mips_cpu_info_table[i]);
15534 show (FILE *stream, const char *string, int *col_p, int *first_p)
15538 fprintf (stream, "%24s", "");
15543 fprintf (stream, ", ");
15547 if (*col_p + strlen (string) > 72)
15549 fprintf (stream, "\n%24s", "");
15553 fprintf (stream, "%s", string);
15554 *col_p += strlen (string);
15560 md_show_usage (FILE *stream)
15565 fprintf (stream, _("\
15567 -EB generate big endian output\n\
15568 -EL generate little endian output\n\
15569 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15570 -G NUM allow referencing objects up to NUM bytes\n\
15571 implicitly with the gp register [default 8]\n"));
15572 fprintf (stream, _("\
15573 -mips1 generate MIPS ISA I instructions\n\
15574 -mips2 generate MIPS ISA II instructions\n\
15575 -mips3 generate MIPS ISA III instructions\n\
15576 -mips4 generate MIPS ISA IV instructions\n\
15577 -mips5 generate MIPS ISA V instructions\n\
15578 -mips32 generate MIPS32 ISA instructions\n\
15579 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15580 -mips64 generate MIPS64 ISA instructions\n\
15581 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15582 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15586 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15587 show (stream, mips_cpu_info_table[i].name, &column, &first);
15588 show (stream, "from-abi", &column, &first);
15589 fputc ('\n', stream);
15591 fprintf (stream, _("\
15592 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15593 -no-mCPU don't generate code specific to CPU.\n\
15594 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15598 show (stream, "3900", &column, &first);
15599 show (stream, "4010", &column, &first);
15600 show (stream, "4100", &column, &first);
15601 show (stream, "4650", &column, &first);
15602 fputc ('\n', stream);
15604 fprintf (stream, _("\
15605 -mips16 generate mips16 instructions\n\
15606 -no-mips16 do not generate mips16 instructions\n"));
15607 fprintf (stream, _("\
15608 -msmartmips generate smartmips instructions\n\
15609 -mno-smartmips do not generate smartmips instructions\n"));
15610 fprintf (stream, _("\
15611 -mdsp generate DSP instructions\n\
15612 -mno-dsp do not generate DSP instructions\n"));
15613 fprintf (stream, _("\
15614 -mdspr2 generate DSP R2 instructions\n\
15615 -mno-dspr2 do not generate DSP R2 instructions\n"));
15616 fprintf (stream, _("\
15617 -mmt generate MT instructions\n\
15618 -mno-mt do not generate MT instructions\n"));
15619 fprintf (stream, _("\
15620 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15621 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15622 -mfix-vr4120 work around certain VR4120 errata\n\
15623 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15624 -mfix-24k insert a nop after ERET and DERET instructions\n\
15625 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15626 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15627 -msym32 assume all symbols have 32-bit values\n\
15628 -O0 remove unneeded NOPs, do not swap branches\n\
15629 -O remove unneeded NOPs and swap branches\n\
15630 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15631 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15632 fprintf (stream, _("\
15633 -mhard-float allow floating-point instructions\n\
15634 -msoft-float do not allow floating-point instructions\n\
15635 -msingle-float only allow 32-bit floating-point operations\n\
15636 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15637 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15640 fprintf (stream, _("\
15641 -KPIC, -call_shared generate SVR4 position independent code\n\
15642 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15643 -mvxworks-pic generate VxWorks position independent code\n\
15644 -non_shared do not generate code that can operate with DSOs\n\
15645 -xgot assume a 32 bit GOT\n\
15646 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15647 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15648 position dependent (non shared) code\n\
15649 -mabi=ABI create ABI conformant object file for:\n"));
15653 show (stream, "32", &column, &first);
15654 show (stream, "o64", &column, &first);
15655 show (stream, "n32", &column, &first);
15656 show (stream, "64", &column, &first);
15657 show (stream, "eabi", &column, &first);
15659 fputc ('\n', stream);
15661 fprintf (stream, _("\
15662 -32 create o32 ABI object file (default)\n\
15663 -n32 create n32 ABI object file\n\
15664 -64 create 64 ABI object file\n"));
15669 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15671 if (HAVE_64BIT_SYMBOLS)
15674 return dwarf2_format_64bit_irix;
15676 return dwarf2_format_64bit;
15680 return dwarf2_format_32bit;
15684 mips_dwarf2_addr_size (void)
15686 if (HAVE_64BIT_OBJECTS)
15692 /* Standard calling conventions leave the CFA at SP on entry. */
15694 mips_cfi_frame_initial_instructions (void)
15696 cfi_add_CFA_def_cfa_register (SP);
15700 tc_mips_regname_to_dw2regnum (char *regname)
15702 unsigned int regnum = -1;
15705 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))