1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode *insn_mo;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p : 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p : 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p : 1;
160 /* True if this instruction is complete. */
161 unsigned int complete_p : 1;
164 /* The ABI to use. */
175 /* MIPS ABI we are using for this output file. */
176 static enum mips_abi_level mips_abi = NO_ABI;
178 /* Whether or not we have code that can call pic code. */
179 int mips_abicalls = FALSE;
181 /* Whether or not we have code which can be put into a shared
183 static bfd_boolean mips_in_shared = TRUE;
185 /* This is the set of options which may be modified by the .set
186 pseudo-op. We use a struct so that .set push and .set pop are more
189 struct mips_set_options
191 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
192 if it has not been initialized. Changed by `.set mipsN', and the
193 -mipsN command line option, and the default CPU. */
195 /* Enabled Application Specific Extensions (ASEs). These are set to -1
196 if they have not been initialized. Changed by `.set <asename>', by
197 command line options, and based on the default architecture. */
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Non-zero if we should not reorder instructions. Changed by `.set
210 reorder' and `.set noreorder'. */
212 /* Non-zero if we should not permit the register designated "assembler
213 temporary" to be used in instructions. The value is the register
214 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
215 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
217 /* Non-zero if we should warn when a macro instruction expands into
218 more than one machine instruction. Changed by `.set nomacro' and
220 int warn_about_macros;
221 /* Non-zero if we should not move instructions. Changed by `.set
222 move', `.set volatile', `.set nomove', and `.set novolatile'. */
224 /* Non-zero if we should not optimize branches by moving the target
225 of the branch into the delay slot. Actually, we don't perform
226 this optimization anyhow. Changed by `.set bopt' and `.set
229 /* Non-zero if we should not autoextend mips16 instructions.
230 Changed by `.set autoextend' and `.set noautoextend'. */
232 /* Restrict general purpose registers and floating point registers
233 to 32 bit. This is initially determined when -mgp32 or -mfp32
234 is passed but can changed if the assembler code uses .set mipsN. */
237 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
238 command line option, and the default CPU. */
240 /* True if ".set sym32" is in effect. */
242 /* True if floating-point operations are not allowed. Changed by .set
243 softfloat or .set hardfloat, by command line options -msoft-float or
244 -mhard-float. The default is false. */
245 bfd_boolean soft_float;
247 /* True if only single-precision floating-point operations are allowed.
248 Changed by .set singlefloat or .set doublefloat, command-line options
249 -msingle-float or -mdouble-float. The default is false. */
250 bfd_boolean single_float;
253 /* This is the struct we use to hold the current set of options. Note
254 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
255 -1 to indicate that they have not been initialized. */
257 /* True if -mgp32 was passed. */
258 static int file_mips_gp32 = -1;
260 /* True if -mfp32 was passed. */
261 static int file_mips_fp32 = -1;
263 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
264 static int file_mips_soft_float = 0;
266 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
267 static int file_mips_single_float = 0;
269 static struct mips_set_options mips_opts =
271 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
272 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
273 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
274 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
275 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
276 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
279 /* These variables are filled in with the masks of registers used.
280 The object format code reads them and puts them in the appropriate
282 unsigned long mips_gprmask;
283 unsigned long mips_cprmask[4];
285 /* MIPS ISA we are using for this output file. */
286 static int file_mips_isa = ISA_UNKNOWN;
288 /* True if any MIPS16 code was produced. */
289 static int file_ase_mips16;
291 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
292 || mips_opts.isa == ISA_MIPS32R2 \
293 || mips_opts.isa == ISA_MIPS64 \
294 || mips_opts.isa == ISA_MIPS64R2)
296 /* True if we want to create R_MIPS_JALR for jalr $25. */
298 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
300 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
301 because there's no place for any addend, the only acceptable
302 expression is a bare symbol. */
303 #define MIPS_JALR_HINT_P(EXPR) \
304 (!HAVE_IN_PLACE_ADDENDS \
305 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
308 /* True if -mips3d was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_mips3d;
312 /* True if -mdmx was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314 static int file_ase_mdmx;
316 /* True if -msmartmips was passed or implied by arguments passed on the
317 command line (e.g., by -march). */
318 static int file_ase_smartmips;
320 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
321 || mips_opts.isa == ISA_MIPS32R2)
323 /* True if -mdsp was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_dsp;
327 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS64R2)
330 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
332 /* True if -mdspr2 was passed or implied by arguments passed on the
333 command line (e.g., by -march). */
334 static int file_ase_dspr2;
336 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
337 || mips_opts.isa == ISA_MIPS64R2)
339 /* True if -mmt was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mt;
343 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
344 || mips_opts.isa == ISA_MIPS64R2)
346 /* The argument of the -march= flag. The architecture we are assembling. */
347 static int file_mips_arch = CPU_UNKNOWN;
348 static const char *mips_arch_string;
350 /* The argument of the -mtune= flag. The architecture for which we
352 static int mips_tune = CPU_UNKNOWN;
353 static const char *mips_tune_string;
355 /* True when generating 32-bit code for a 64-bit processor. */
356 static int mips_32bitmode = 0;
358 /* True if the given ABI requires 32-bit registers. */
359 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
361 /* Likewise 64-bit registers. */
362 #define ABI_NEEDS_64BIT_REGS(ABI) \
364 || (ABI) == N64_ABI \
367 /* Return true if ISA supports 64 bit wide gp registers. */
368 #define ISA_HAS_64BIT_REGS(ISA) \
369 ((ISA) == ISA_MIPS3 \
370 || (ISA) == ISA_MIPS4 \
371 || (ISA) == ISA_MIPS5 \
372 || (ISA) == ISA_MIPS64 \
373 || (ISA) == ISA_MIPS64R2)
375 /* Return true if ISA supports 64 bit wide float registers. */
376 #define ISA_HAS_64BIT_FPRS(ISA) \
377 ((ISA) == ISA_MIPS3 \
378 || (ISA) == ISA_MIPS4 \
379 || (ISA) == ISA_MIPS5 \
380 || (ISA) == ISA_MIPS32R2 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2)
384 /* Return true if ISA supports 64-bit right rotate (dror et al.)
386 #define ISA_HAS_DROR(ISA) \
387 ((ISA) == ISA_MIPS64R2)
389 /* Return true if ISA supports 32-bit right rotate (ror et al.)
391 #define ISA_HAS_ROR(ISA) \
392 ((ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS64R2 \
394 || mips_opts.ase_smartmips)
396 /* Return true if ISA supports single-precision floats in odd registers. */
397 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
398 ((ISA) == ISA_MIPS32 \
399 || (ISA) == ISA_MIPS32R2 \
400 || (ISA) == ISA_MIPS64 \
401 || (ISA) == ISA_MIPS64R2)
403 /* Return true if ISA supports move to/from high part of a 64-bit
404 floating-point register. */
405 #define ISA_HAS_MXHC1(ISA) \
406 ((ISA) == ISA_MIPS32R2 \
407 || (ISA) == ISA_MIPS64R2)
409 #define HAVE_32BIT_GPRS \
410 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
412 #define HAVE_32BIT_FPRS \
413 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
415 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
416 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
418 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
420 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
422 /* True if relocations are stored in-place. */
423 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
425 /* The ABI-derived address size. */
426 #define HAVE_64BIT_ADDRESSES \
427 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
428 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
430 /* The size of symbolic constants (i.e., expressions of the form
431 "SYMBOL" or "SYMBOL + OFFSET"). */
432 #define HAVE_32BIT_SYMBOLS \
433 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
434 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
436 /* Addresses are loaded in different ways, depending on the address size
437 in use. The n32 ABI Documentation also mandates the use of additions
438 with overflow checking, but existing implementations don't follow it. */
439 #define ADDRESS_ADD_INSN \
440 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
442 #define ADDRESS_ADDI_INSN \
443 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
445 #define ADDRESS_LOAD_INSN \
446 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
448 #define ADDRESS_STORE_INSN \
449 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
451 /* Return true if the given CPU supports the MIPS16 ASE. */
452 #define CPU_HAS_MIPS16(cpu) \
453 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
454 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
456 /* True if CPU has a dror instruction. */
457 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
459 /* True if CPU has a ror instruction. */
460 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
462 /* True if CPU has seq/sne and seqi/snei instructions. */
463 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
465 /* True if CPU does not implement the all the coprocessor insns. For these
466 CPUs only those COP insns are accepted that are explicitly marked to be
467 available on the CPU. ISA membership for COP insns is ignored. */
468 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
470 /* True if mflo and mfhi can be immediately followed by instructions
471 which write to the HI and LO registers.
473 According to MIPS specifications, MIPS ISAs I, II, and III need
474 (at least) two instructions between the reads of HI/LO and
475 instructions which write them, and later ISAs do not. Contradicting
476 the MIPS specifications, some MIPS IV processor user manuals (e.g.
477 the UM for the NEC Vr5000) document needing the instructions between
478 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
479 MIPS64 and later ISAs to have the interlocks, plus any specific
480 earlier-ISA CPUs for which CPU documentation declares that the
481 instructions are really interlocked. */
482 #define hilo_interlocks \
483 (mips_opts.isa == ISA_MIPS32 \
484 || mips_opts.isa == ISA_MIPS32R2 \
485 || mips_opts.isa == ISA_MIPS64 \
486 || mips_opts.isa == ISA_MIPS64R2 \
487 || mips_opts.arch == CPU_R4010 \
488 || mips_opts.arch == CPU_R10000 \
489 || mips_opts.arch == CPU_R12000 \
490 || mips_opts.arch == CPU_R14000 \
491 || mips_opts.arch == CPU_R16000 \
492 || mips_opts.arch == CPU_RM7000 \
493 || mips_opts.arch == CPU_VR5500 \
496 /* Whether the processor uses hardware interlocks to protect reads
497 from the GPRs after they are loaded from memory, and thus does not
498 require nops to be inserted. This applies to instructions marked
499 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
501 #define gpr_interlocks \
502 (mips_opts.isa != ISA_MIPS1 \
503 || mips_opts.arch == CPU_R3900)
505 /* Whether the processor uses hardware interlocks to avoid delays
506 required by coprocessor instructions, and thus does not require
507 nops to be inserted. This applies to instructions marked
508 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
509 between instructions marked INSN_WRITE_COND_CODE and ones marked
510 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
511 levels I, II, and III. */
512 /* Itbl support may require additional care here. */
513 #define cop_interlocks \
514 ((mips_opts.isa != ISA_MIPS1 \
515 && mips_opts.isa != ISA_MIPS2 \
516 && mips_opts.isa != ISA_MIPS3) \
517 || mips_opts.arch == CPU_R4300 \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I. */
525 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
527 /* Is this a mfhi or mflo instruction? */
528 #define MF_HILO_INSN(PINFO) \
529 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
531 /* Returns true for a (non floating-point) coprocessor instruction. Reading
532 or writing the condition code is only possible on the coprocessors and
533 these insns are not marked with INSN_COP. Thus for these insns use the
534 condition-code flags. */
535 #define COP_INSN(PINFO) \
536 (PINFO != INSN_MACRO \
537 && ((PINFO) & (FP_S | FP_D)) == 0 \
538 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
540 /* MIPS PIC level. */
542 enum mips_pic_level mips_pic;
544 /* 1 if we should generate 32 bit offsets from the $gp register in
545 SVR4_PIC mode. Currently has no meaning in other modes. */
546 static int mips_big_got = 0;
548 /* 1 if trap instructions should used for overflow rather than break
550 static int mips_trap = 0;
552 /* 1 if double width floating point constants should not be constructed
553 by assembling two single width halves into two single width floating
554 point registers which just happen to alias the double width destination
555 register. On some architectures this aliasing can be disabled by a bit
556 in the status register, and the setting of this bit cannot be determined
557 automatically at assemble time. */
558 static int mips_disable_float_construction;
560 /* Non-zero if any .set noreorder directives were used. */
562 static int mips_any_noreorder;
564 /* Non-zero if nops should be inserted when the register referenced in
565 an mfhi/mflo instruction is read in the next two instructions. */
566 static int mips_7000_hilo_fix;
568 /* The size of objects in the small data section. */
569 static unsigned int g_switch_value = 8;
570 /* Whether the -G option was used. */
571 static int g_switch_seen = 0;
576 /* If we can determine in advance that GP optimization won't be
577 possible, we can skip the relaxation stuff that tries to produce
578 GP-relative references. This makes delay slot optimization work
581 This function can only provide a guess, but it seems to work for
582 gcc output. It needs to guess right for gcc, otherwise gcc
583 will put what it thinks is a GP-relative instruction in a branch
586 I don't know if a fix is needed for the SVR4_PIC mode. I've only
587 fixed it for the non-PIC mode. KR 95/04/07 */
588 static int nopic_need_relax (symbolS *, int);
590 /* handle of the OPCODE hash table */
591 static struct hash_control *op_hash = NULL;
593 /* The opcode hash table we use for the mips16. */
594 static struct hash_control *mips16_op_hash = NULL;
596 /* This array holds the chars that always start a comment. If the
597 pre-processor is disabled, these aren't very useful */
598 const char comment_chars[] = "#";
600 /* This array holds the chars that only start a comment at the beginning of
601 a line. If the line seems to have the form '# 123 filename'
602 .line and .file directives will appear in the pre-processed output */
603 /* Note that input_file.c hand checks for '#' at the beginning of the
604 first line of the input file. This is because the compiler outputs
605 #NO_APP at the beginning of its output. */
606 /* Also note that C style comments are always supported. */
607 const char line_comment_chars[] = "#";
609 /* This array holds machine specific line separator characters. */
610 const char line_separator_chars[] = ";";
612 /* Chars that can be used to separate mant from exp in floating point nums */
613 const char EXP_CHARS[] = "eE";
615 /* Chars that mean this number is a floating point constant */
618 const char FLT_CHARS[] = "rRsSfFdDxXpP";
620 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
621 changed in read.c . Ideally it shouldn't have to know about it at all,
622 but nothing is ideal around here.
625 static char *insn_error;
627 static int auto_align = 1;
629 /* When outputting SVR4 PIC code, the assembler needs to know the
630 offset in the stack frame from which to restore the $gp register.
631 This is set by the .cprestore pseudo-op, and saved in this
633 static offsetT mips_cprestore_offset = -1;
635 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
636 more optimizations, it can use a register value instead of a memory-saved
637 offset and even an other register than $gp as global pointer. */
638 static offsetT mips_cpreturn_offset = -1;
639 static int mips_cpreturn_register = -1;
640 static int mips_gp_register = GP;
641 static int mips_gprel_offset = 0;
643 /* Whether mips_cprestore_offset has been set in the current function
644 (or whether it has already been warned about, if not). */
645 static int mips_cprestore_valid = 0;
647 /* This is the register which holds the stack frame, as set by the
648 .frame pseudo-op. This is needed to implement .cprestore. */
649 static int mips_frame_reg = SP;
651 /* Whether mips_frame_reg has been set in the current function
652 (or whether it has already been warned about, if not). */
653 static int mips_frame_reg_valid = 0;
655 /* To output NOP instructions correctly, we need to keep information
656 about the previous two instructions. */
658 /* Whether we are optimizing. The default value of 2 means to remove
659 unneeded NOPs and swap branch instructions when possible. A value
660 of 1 means to not swap branches. A value of 0 means to always
662 static int mips_optimize = 2;
664 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
665 equivalent to seeing no -g option at all. */
666 static int mips_debug = 0;
668 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
669 #define MAX_VR4130_NOPS 4
671 /* The maximum number of NOPs needed to fill delay slots. */
672 #define MAX_DELAY_NOPS 2
674 /* The maximum number of NOPs needed for any purpose. */
677 /* A list of previous instructions, with index 0 being the most recent.
678 We need to look back MAX_NOPS instructions when filling delay slots
679 or working around processor errata. We need to look back one
680 instruction further if we're thinking about using history[0] to
681 fill a branch delay slot. */
682 static struct mips_cl_insn history[1 + MAX_NOPS];
684 /* Nop instructions used by emit_nop. */
685 static struct mips_cl_insn nop_insn, mips16_nop_insn;
687 /* The appropriate nop for the current mode. */
688 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
690 /* If this is set, it points to a frag holding nop instructions which
691 were inserted before the start of a noreorder section. If those
692 nops turn out to be unnecessary, the size of the frag can be
694 static fragS *prev_nop_frag;
696 /* The number of nop instructions we created in prev_nop_frag. */
697 static int prev_nop_frag_holds;
699 /* The number of nop instructions that we know we need in
701 static int prev_nop_frag_required;
703 /* The number of instructions we've seen since prev_nop_frag. */
704 static int prev_nop_frag_since;
706 /* For ECOFF and ELF, relocations against symbols are done in two
707 parts, with a HI relocation and a LO relocation. Each relocation
708 has only 16 bits of space to store an addend. This means that in
709 order for the linker to handle carries correctly, it must be able
710 to locate both the HI and the LO relocation. This means that the
711 relocations must appear in order in the relocation table.
713 In order to implement this, we keep track of each unmatched HI
714 relocation. We then sort them so that they immediately precede the
715 corresponding LO relocation. */
720 struct mips_hi_fixup *next;
723 /* The section this fixup is in. */
727 /* The list of unmatched HI relocs. */
729 static struct mips_hi_fixup *mips_hi_fixup_list;
731 /* The frag containing the last explicit relocation operator.
732 Null if explicit relocations have not been used. */
734 static fragS *prev_reloc_op_frag;
736 /* Map normal MIPS register numbers to mips16 register numbers. */
738 #define X ILLEGAL_REG
739 static const int mips32_to_16_reg_map[] =
741 X, X, 2, 3, 4, 5, 6, 7,
742 X, X, X, X, X, X, X, X,
743 0, 1, X, X, X, X, X, X,
744 X, X, X, X, X, X, X, X
748 /* Map mips16 register numbers to normal MIPS register numbers. */
750 static const unsigned int mips16_to_32_reg_map[] =
752 16, 17, 2, 3, 4, 5, 6, 7
755 /* Classifies the kind of instructions we're interested in when
756 implementing -mfix-vr4120. */
757 enum fix_vr4120_class
765 NUM_FIX_VR4120_CLASSES
768 /* ...likewise -mfix-loongson2f-jump. */
769 static bfd_boolean mips_fix_loongson2f_jump;
771 /* ...likewise -mfix-loongson2f-nop. */
772 static bfd_boolean mips_fix_loongson2f_nop;
774 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
775 static bfd_boolean mips_fix_loongson2f;
777 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
778 there must be at least one other instruction between an instruction
779 of type X and an instruction of type Y. */
780 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
782 /* True if -mfix-vr4120 is in force. */
783 static int mips_fix_vr4120;
785 /* ...likewise -mfix-vr4130. */
786 static int mips_fix_vr4130;
788 /* ...likewise -mfix-24k. */
789 static int mips_fix_24k;
791 /* ...likewise -mfix-cn63xxp1 */
792 static bfd_boolean mips_fix_cn63xxp1;
794 /* We don't relax branches by default, since this causes us to expand
795 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
796 fail to compute the offset before expanding the macro to the most
797 efficient expansion. */
799 static int mips_relax_branch;
801 /* The expansion of many macros depends on the type of symbol that
802 they refer to. For example, when generating position-dependent code,
803 a macro that refers to a symbol may have two different expansions,
804 one which uses GP-relative addresses and one which uses absolute
805 addresses. When generating SVR4-style PIC, a macro may have
806 different expansions for local and global symbols.
808 We handle these situations by generating both sequences and putting
809 them in variant frags. In position-dependent code, the first sequence
810 will be the GP-relative one and the second sequence will be the
811 absolute one. In SVR4 PIC, the first sequence will be for global
812 symbols and the second will be for local symbols.
814 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
815 SECOND are the lengths of the two sequences in bytes. These fields
816 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
817 the subtype has the following flags:
820 Set if it has been decided that we should use the second
821 sequence instead of the first.
824 Set in the first variant frag if the macro's second implementation
825 is longer than its first. This refers to the macro as a whole,
826 not an individual relaxation.
829 Set in the first variant frag if the macro appeared in a .set nomacro
830 block and if one alternative requires a warning but the other does not.
833 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
836 The frag's "opcode" points to the first fixup for relaxable code.
838 Relaxable macros are generated using a sequence such as:
840 relax_start (SYMBOL);
841 ... generate first expansion ...
843 ... generate second expansion ...
846 The code and fixups for the unwanted alternative are discarded
847 by md_convert_frag. */
848 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
850 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
851 #define RELAX_SECOND(X) ((X) & 0xff)
852 #define RELAX_USE_SECOND 0x10000
853 #define RELAX_SECOND_LONGER 0x20000
854 #define RELAX_NOMACRO 0x40000
855 #define RELAX_DELAY_SLOT 0x80000
857 /* Branch without likely bit. If label is out of range, we turn:
859 beq reg1, reg2, label
869 with the following opcode replacements:
876 bltzal <-> bgezal (with jal label instead of j label)
878 Even though keeping the delay slot instruction in the delay slot of
879 the branch would be more efficient, it would be very tricky to do
880 correctly, because we'd have to introduce a variable frag *after*
881 the delay slot instruction, and expand that instead. Let's do it
882 the easy way for now, even if the branch-not-taken case now costs
883 one additional instruction. Out-of-range branches are not supposed
884 to be common, anyway.
886 Branch likely. If label is out of range, we turn:
888 beql reg1, reg2, label
889 delay slot (annulled if branch not taken)
898 delay slot (executed only if branch taken)
901 It would be possible to generate a shorter sequence by losing the
902 likely bit, generating something like:
907 delay slot (executed only if branch taken)
919 bltzall -> bgezal (with jal label instead of j label)
920 bgezall -> bltzal (ditto)
923 but it's not clear that it would actually improve performance. */
924 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
928 | ((toofar) ? 0x20 : 0) \
929 | ((link) ? 0x40 : 0) \
930 | ((likely) ? 0x80 : 0) \
931 | ((uncond) ? 0x100 : 0)))
932 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
933 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
934 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
935 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
936 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
937 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
939 /* For mips16 code, we use an entirely different form of relaxation.
940 mips16 supports two versions of most instructions which take
941 immediate values: a small one which takes some small value, and a
942 larger one which takes a 16 bit value. Since branches also follow
943 this pattern, relaxing these values is required.
945 We can assemble both mips16 and normal MIPS code in a single
946 object. Therefore, we need to support this type of relaxation at
947 the same time that we support the relaxation described above. We
948 use the high bit of the subtype field to distinguish these cases.
950 The information we store for this type of relaxation is the
951 argument code found in the opcode file for this relocation, whether
952 the user explicitly requested a small or extended form, and whether
953 the relocation is in a jump or jal delay slot. That tells us the
954 size of the value, and how it should be stored. We also store
955 whether the fragment is considered to be extended or not. We also
956 store whether this is known to be a branch to a different section,
957 whether we have tried to relax this frag yet, and whether we have
958 ever extended a PC relative fragment because of a shift count. */
959 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
962 | ((small) ? 0x100 : 0) \
963 | ((ext) ? 0x200 : 0) \
964 | ((dslot) ? 0x400 : 0) \
965 | ((jal_dslot) ? 0x800 : 0))
966 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
967 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
968 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
969 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
970 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
971 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
972 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
973 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
974 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
975 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
976 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
977 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
979 /* Is the given value a sign-extended 32-bit value? */
980 #define IS_SEXT_32BIT_NUM(x) \
981 (((x) &~ (offsetT) 0x7fffffff) == 0 \
982 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
984 /* Is the given value a sign-extended 16-bit value? */
985 #define IS_SEXT_16BIT_NUM(x) \
986 (((x) &~ (offsetT) 0x7fff) == 0 \
987 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
989 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
990 #define IS_ZEXT_32BIT_NUM(x) \
991 (((x) &~ (offsetT) 0xffffffff) == 0 \
992 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
994 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
995 VALUE << SHIFT. VALUE is evaluated exactly once. */
996 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
997 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
998 | (((VALUE) & (MASK)) << (SHIFT)))
1000 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1002 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1003 (((STRUCT) >> (SHIFT)) & (MASK))
1005 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1006 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1008 include/opcode/mips.h specifies operand fields using the macros
1009 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1010 with "MIPS16OP" instead of "OP". */
1011 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1012 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1013 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1014 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1015 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1017 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1018 #define EXTRACT_OPERAND(FIELD, INSN) \
1019 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1020 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1021 EXTRACT_BITS ((INSN).insn_opcode, \
1022 MIPS16OP_MASK_##FIELD, \
1023 MIPS16OP_SH_##FIELD)
1025 /* Global variables used when generating relaxable macros. See the
1026 comment above RELAX_ENCODE for more details about how relaxation
1029 /* 0 if we're not emitting a relaxable macro.
1030 1 if we're emitting the first of the two relaxation alternatives.
1031 2 if we're emitting the second alternative. */
1034 /* The first relaxable fixup in the current frag. (In other words,
1035 the first fixup that refers to relaxable code.) */
1038 /* sizes[0] says how many bytes of the first alternative are stored in
1039 the current frag. Likewise sizes[1] for the second alternative. */
1040 unsigned int sizes[2];
1042 /* The symbol on which the choice of sequence depends. */
1046 /* Global variables used to decide whether a macro needs a warning. */
1048 /* True if the macro is in a branch delay slot. */
1049 bfd_boolean delay_slot_p;
1051 /* For relaxable macros, sizes[0] is the length of the first alternative
1052 in bytes and sizes[1] is the length of the second alternative.
1053 For non-relaxable macros, both elements give the length of the
1055 unsigned int sizes[2];
1057 /* The first variant frag for this macro. */
1059 } mips_macro_warning;
1061 /* Prototypes for static functions. */
1063 #define internalError() \
1064 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1066 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1068 static void append_insn
1069 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1070 static void mips_no_prev_insn (void);
1071 static void macro_build (expressionS *, const char *, const char *, ...);
1072 static void mips16_macro_build
1073 (expressionS *, const char *, const char *, va_list *);
1074 static void load_register (int, expressionS *, int);
1075 static void macro_start (void);
1076 static void macro_end (void);
1077 static void macro (struct mips_cl_insn * ip);
1078 static void mips16_macro (struct mips_cl_insn * ip);
1079 static void mips_ip (char *str, struct mips_cl_insn * ip);
1080 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1081 static void mips16_immed
1082 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1083 unsigned long *, bfd_boolean *, unsigned short *);
1084 static size_t my_getSmallExpression
1085 (expressionS *, bfd_reloc_code_real_type *, char *);
1086 static void my_getExpression (expressionS *, char *);
1087 static void s_align (int);
1088 static void s_change_sec (int);
1089 static void s_change_section (int);
1090 static void s_cons (int);
1091 static void s_float_cons (int);
1092 static void s_mips_globl (int);
1093 static void s_option (int);
1094 static void s_mipsset (int);
1095 static void s_abicalls (int);
1096 static void s_cpload (int);
1097 static void s_cpsetup (int);
1098 static void s_cplocal (int);
1099 static void s_cprestore (int);
1100 static void s_cpreturn (int);
1101 static void s_dtprelword (int);
1102 static void s_dtpreldword (int);
1103 static void s_gpvalue (int);
1104 static void s_gpword (int);
1105 static void s_gpdword (int);
1106 static void s_cpadd (int);
1107 static void s_insn (int);
1108 static void md_obj_begin (void);
1109 static void md_obj_end (void);
1110 static void s_mips_ent (int);
1111 static void s_mips_end (int);
1112 static void s_mips_frame (int);
1113 static void s_mips_mask (int reg_type);
1114 static void s_mips_stab (int);
1115 static void s_mips_weakext (int);
1116 static void s_mips_file (int);
1117 static void s_mips_loc (int);
1118 static bfd_boolean pic_need_relax (symbolS *, asection *);
1119 static int relaxed_branch_length (fragS *, asection *, int);
1120 static int validate_mips_insn (const struct mips_opcode *);
1122 /* Table and functions used to map between CPU/ISA names, and
1123 ISA levels, and CPU numbers. */
1125 struct mips_cpu_info
1127 const char *name; /* CPU or ISA name. */
1128 int flags; /* ASEs available, or ISA flag. */
1129 int isa; /* ISA level. */
1130 int cpu; /* CPU number (default CPU if ISA). */
1133 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1134 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1135 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1136 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1137 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1138 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1139 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1141 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1142 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1143 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1147 The following pseudo-ops from the Kane and Heinrich MIPS book
1148 should be defined here, but are currently unsupported: .alias,
1149 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1151 The following pseudo-ops from the Kane and Heinrich MIPS book are
1152 specific to the type of debugging information being generated, and
1153 should be defined by the object format: .aent, .begin, .bend,
1154 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1157 The following pseudo-ops from the Kane and Heinrich MIPS book are
1158 not MIPS CPU specific, but are also not specific to the object file
1159 format. This file is probably the best place to define them, but
1160 they are not currently supported: .asm0, .endr, .lab, .struct. */
1162 static const pseudo_typeS mips_pseudo_table[] =
1164 /* MIPS specific pseudo-ops. */
1165 {"option", s_option, 0},
1166 {"set", s_mipsset, 0},
1167 {"rdata", s_change_sec, 'r'},
1168 {"sdata", s_change_sec, 's'},
1169 {"livereg", s_ignore, 0},
1170 {"abicalls", s_abicalls, 0},
1171 {"cpload", s_cpload, 0},
1172 {"cpsetup", s_cpsetup, 0},
1173 {"cplocal", s_cplocal, 0},
1174 {"cprestore", s_cprestore, 0},
1175 {"cpreturn", s_cpreturn, 0},
1176 {"dtprelword", s_dtprelword, 0},
1177 {"dtpreldword", s_dtpreldword, 0},
1178 {"gpvalue", s_gpvalue, 0},
1179 {"gpword", s_gpword, 0},
1180 {"gpdword", s_gpdword, 0},
1181 {"cpadd", s_cpadd, 0},
1182 {"insn", s_insn, 0},
1184 /* Relatively generic pseudo-ops that happen to be used on MIPS
1186 {"asciiz", stringer, 8 + 1},
1187 {"bss", s_change_sec, 'b'},
1189 {"half", s_cons, 1},
1190 {"dword", s_cons, 3},
1191 {"weakext", s_mips_weakext, 0},
1192 {"origin", s_org, 0},
1193 {"repeat", s_rept, 0},
1195 /* For MIPS this is non-standard, but we define it for consistency. */
1196 {"sbss", s_change_sec, 'B'},
1198 /* These pseudo-ops are defined in read.c, but must be overridden
1199 here for one reason or another. */
1200 {"align", s_align, 0},
1201 {"byte", s_cons, 0},
1202 {"data", s_change_sec, 'd'},
1203 {"double", s_float_cons, 'd'},
1204 {"float", s_float_cons, 'f'},
1205 {"globl", s_mips_globl, 0},
1206 {"global", s_mips_globl, 0},
1207 {"hword", s_cons, 1},
1209 {"long", s_cons, 2},
1210 {"octa", s_cons, 4},
1211 {"quad", s_cons, 3},
1212 {"section", s_change_section, 0},
1213 {"short", s_cons, 1},
1214 {"single", s_float_cons, 'f'},
1215 {"stabn", s_mips_stab, 'n'},
1216 {"text", s_change_sec, 't'},
1217 {"word", s_cons, 2},
1219 { "extern", ecoff_directive_extern, 0},
1224 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1226 /* These pseudo-ops should be defined by the object file format.
1227 However, a.out doesn't support them, so we have versions here. */
1228 {"aent", s_mips_ent, 1},
1229 {"bgnb", s_ignore, 0},
1230 {"end", s_mips_end, 0},
1231 {"endb", s_ignore, 0},
1232 {"ent", s_mips_ent, 0},
1233 {"file", s_mips_file, 0},
1234 {"fmask", s_mips_mask, 'F'},
1235 {"frame", s_mips_frame, 0},
1236 {"loc", s_mips_loc, 0},
1237 {"mask", s_mips_mask, 'R'},
1238 {"verstamp", s_ignore, 0},
1242 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1243 purpose of the `.dc.a' internal pseudo-op. */
1246 mips_address_bytes (void)
1248 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1251 extern void pop_insert (const pseudo_typeS *);
1254 mips_pop_insert (void)
1256 pop_insert (mips_pseudo_table);
1257 if (! ECOFF_DEBUGGING)
1258 pop_insert (mips_nonecoff_pseudo_table);
1261 /* Symbols labelling the current insn. */
1263 struct insn_label_list
1265 struct insn_label_list *next;
1269 static struct insn_label_list *free_insn_labels;
1270 #define label_list tc_segment_info_data.labels
1272 static void mips_clear_insn_labels (void);
1275 mips_clear_insn_labels (void)
1277 register struct insn_label_list **pl;
1278 segment_info_type *si;
1282 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1285 si = seg_info (now_seg);
1286 *pl = si->label_list;
1287 si->label_list = NULL;
1292 static char *expr_end;
1294 /* Expressions which appear in instructions. These are set by
1297 static expressionS imm_expr;
1298 static expressionS imm2_expr;
1299 static expressionS offset_expr;
1301 /* Relocs associated with imm_expr and offset_expr. */
1303 static bfd_reloc_code_real_type imm_reloc[3]
1304 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1305 static bfd_reloc_code_real_type offset_reloc[3]
1306 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1308 /* These are set by mips16_ip if an explicit extension is used. */
1310 static bfd_boolean mips16_small, mips16_ext;
1313 /* The pdr segment for per procedure frame/regmask info. Not used for
1316 static segT pdr_seg;
1319 /* The default target format to use. */
1321 #if defined (TE_FreeBSD)
1322 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1323 #elif defined (TE_TMIPS)
1324 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1326 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1330 mips_target_format (void)
1332 switch (OUTPUT_FLAVOR)
1334 case bfd_target_ecoff_flavour:
1335 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1336 case bfd_target_coff_flavour:
1338 case bfd_target_elf_flavour:
1340 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1341 return (target_big_endian
1342 ? "elf32-bigmips-vxworks"
1343 : "elf32-littlemips-vxworks");
1345 return (target_big_endian
1346 ? (HAVE_64BIT_OBJECTS
1347 ? ELF_TARGET ("elf64-", "big")
1349 ? ELF_TARGET ("elf32-n", "big")
1350 : ELF_TARGET ("elf32-", "big")))
1351 : (HAVE_64BIT_OBJECTS
1352 ? ELF_TARGET ("elf64-", "little")
1354 ? ELF_TARGET ("elf32-n", "little")
1355 : ELF_TARGET ("elf32-", "little"))));
1362 /* Return the length of instruction INSN. */
1364 static inline unsigned int
1365 insn_length (const struct mips_cl_insn *insn)
1367 if (!mips_opts.mips16)
1369 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1372 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1375 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1380 insn->use_extend = FALSE;
1382 insn->insn_opcode = mo->match;
1385 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1386 insn->fixp[i] = NULL;
1387 insn->fixed_p = (mips_opts.noreorder > 0);
1388 insn->noreorder_p = (mips_opts.noreorder > 0);
1389 insn->mips16_absolute_jump_p = 0;
1390 insn->complete_p = 0;
1393 /* Record the current MIPS16 mode in now_seg. */
1396 mips_record_mips16_mode (void)
1398 segment_info_type *si;
1400 si = seg_info (now_seg);
1401 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1402 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1405 /* Install INSN at the location specified by its "frag" and "where" fields. */
1408 install_insn (const struct mips_cl_insn *insn)
1410 char *f = insn->frag->fr_literal + insn->where;
1411 if (!mips_opts.mips16)
1412 md_number_to_chars (f, insn->insn_opcode, 4);
1413 else if (insn->mips16_absolute_jump_p)
1415 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1416 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1420 if (insn->use_extend)
1422 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1425 md_number_to_chars (f, insn->insn_opcode, 2);
1427 mips_record_mips16_mode ();
1430 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1431 and install the opcode in the new location. */
1434 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1439 insn->where = where;
1440 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1441 if (insn->fixp[i] != NULL)
1443 insn->fixp[i]->fx_frag = frag;
1444 insn->fixp[i]->fx_where = where;
1446 install_insn (insn);
1449 /* Add INSN to the end of the output. */
1452 add_fixed_insn (struct mips_cl_insn *insn)
1454 char *f = frag_more (insn_length (insn));
1455 move_insn (insn, frag_now, f - frag_now->fr_literal);
1458 /* Start a variant frag and move INSN to the start of the variant part,
1459 marking it as fixed. The other arguments are as for frag_var. */
1462 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1463 relax_substateT subtype, symbolS *symbol, offsetT offset)
1465 frag_grow (max_chars);
1466 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1468 frag_var (rs_machine_dependent, max_chars, var,
1469 subtype, symbol, offset, NULL);
1472 /* Insert N copies of INSN into the history buffer, starting at
1473 position FIRST. Neither FIRST nor N need to be clipped. */
1476 insert_into_history (unsigned int first, unsigned int n,
1477 const struct mips_cl_insn *insn)
1479 if (mips_relax.sequence != 2)
1483 for (i = ARRAY_SIZE (history); i-- > first;)
1485 history[i] = history[i - n];
1491 /* Emit a nop instruction, recording it in the history buffer. */
1496 add_fixed_insn (NOP_INSN);
1497 insert_into_history (0, 1, NOP_INSN);
1500 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1501 the idea is to make it obvious at a glance that each errata is
1505 init_vr4120_conflicts (void)
1507 #define CONFLICT(FIRST, SECOND) \
1508 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1510 /* Errata 21 - [D]DIV[U] after [D]MACC */
1511 CONFLICT (MACC, DIV);
1512 CONFLICT (DMACC, DIV);
1514 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1515 CONFLICT (DMULT, DMULT);
1516 CONFLICT (DMULT, DMACC);
1517 CONFLICT (DMACC, DMULT);
1518 CONFLICT (DMACC, DMACC);
1520 /* Errata 24 - MT{LO,HI} after [D]MACC */
1521 CONFLICT (MACC, MTHILO);
1522 CONFLICT (DMACC, MTHILO);
1524 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1525 instruction is executed immediately after a MACC or DMACC
1526 instruction, the result of [either instruction] is incorrect." */
1527 CONFLICT (MACC, MULT);
1528 CONFLICT (MACC, DMULT);
1529 CONFLICT (DMACC, MULT);
1530 CONFLICT (DMACC, DMULT);
1532 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1533 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1534 DDIV or DDIVU instruction, the result of the MACC or
1535 DMACC instruction is incorrect.". */
1536 CONFLICT (DMULT, MACC);
1537 CONFLICT (DMULT, DMACC);
1538 CONFLICT (DIV, MACC);
1539 CONFLICT (DIV, DMACC);
1549 #define RTYPE_MASK 0x1ff00
1550 #define RTYPE_NUM 0x00100
1551 #define RTYPE_FPU 0x00200
1552 #define RTYPE_FCC 0x00400
1553 #define RTYPE_VEC 0x00800
1554 #define RTYPE_GP 0x01000
1555 #define RTYPE_CP0 0x02000
1556 #define RTYPE_PC 0x04000
1557 #define RTYPE_ACC 0x08000
1558 #define RTYPE_CCC 0x10000
1559 #define RNUM_MASK 0x000ff
1560 #define RWARN 0x80000
1562 #define GENERIC_REGISTER_NUMBERS \
1563 {"$0", RTYPE_NUM | 0}, \
1564 {"$1", RTYPE_NUM | 1}, \
1565 {"$2", RTYPE_NUM | 2}, \
1566 {"$3", RTYPE_NUM | 3}, \
1567 {"$4", RTYPE_NUM | 4}, \
1568 {"$5", RTYPE_NUM | 5}, \
1569 {"$6", RTYPE_NUM | 6}, \
1570 {"$7", RTYPE_NUM | 7}, \
1571 {"$8", RTYPE_NUM | 8}, \
1572 {"$9", RTYPE_NUM | 9}, \
1573 {"$10", RTYPE_NUM | 10}, \
1574 {"$11", RTYPE_NUM | 11}, \
1575 {"$12", RTYPE_NUM | 12}, \
1576 {"$13", RTYPE_NUM | 13}, \
1577 {"$14", RTYPE_NUM | 14}, \
1578 {"$15", RTYPE_NUM | 15}, \
1579 {"$16", RTYPE_NUM | 16}, \
1580 {"$17", RTYPE_NUM | 17}, \
1581 {"$18", RTYPE_NUM | 18}, \
1582 {"$19", RTYPE_NUM | 19}, \
1583 {"$20", RTYPE_NUM | 20}, \
1584 {"$21", RTYPE_NUM | 21}, \
1585 {"$22", RTYPE_NUM | 22}, \
1586 {"$23", RTYPE_NUM | 23}, \
1587 {"$24", RTYPE_NUM | 24}, \
1588 {"$25", RTYPE_NUM | 25}, \
1589 {"$26", RTYPE_NUM | 26}, \
1590 {"$27", RTYPE_NUM | 27}, \
1591 {"$28", RTYPE_NUM | 28}, \
1592 {"$29", RTYPE_NUM | 29}, \
1593 {"$30", RTYPE_NUM | 30}, \
1594 {"$31", RTYPE_NUM | 31}
1596 #define FPU_REGISTER_NAMES \
1597 {"$f0", RTYPE_FPU | 0}, \
1598 {"$f1", RTYPE_FPU | 1}, \
1599 {"$f2", RTYPE_FPU | 2}, \
1600 {"$f3", RTYPE_FPU | 3}, \
1601 {"$f4", RTYPE_FPU | 4}, \
1602 {"$f5", RTYPE_FPU | 5}, \
1603 {"$f6", RTYPE_FPU | 6}, \
1604 {"$f7", RTYPE_FPU | 7}, \
1605 {"$f8", RTYPE_FPU | 8}, \
1606 {"$f9", RTYPE_FPU | 9}, \
1607 {"$f10", RTYPE_FPU | 10}, \
1608 {"$f11", RTYPE_FPU | 11}, \
1609 {"$f12", RTYPE_FPU | 12}, \
1610 {"$f13", RTYPE_FPU | 13}, \
1611 {"$f14", RTYPE_FPU | 14}, \
1612 {"$f15", RTYPE_FPU | 15}, \
1613 {"$f16", RTYPE_FPU | 16}, \
1614 {"$f17", RTYPE_FPU | 17}, \
1615 {"$f18", RTYPE_FPU | 18}, \
1616 {"$f19", RTYPE_FPU | 19}, \
1617 {"$f20", RTYPE_FPU | 20}, \
1618 {"$f21", RTYPE_FPU | 21}, \
1619 {"$f22", RTYPE_FPU | 22}, \
1620 {"$f23", RTYPE_FPU | 23}, \
1621 {"$f24", RTYPE_FPU | 24}, \
1622 {"$f25", RTYPE_FPU | 25}, \
1623 {"$f26", RTYPE_FPU | 26}, \
1624 {"$f27", RTYPE_FPU | 27}, \
1625 {"$f28", RTYPE_FPU | 28}, \
1626 {"$f29", RTYPE_FPU | 29}, \
1627 {"$f30", RTYPE_FPU | 30}, \
1628 {"$f31", RTYPE_FPU | 31}
1630 #define FPU_CONDITION_CODE_NAMES \
1631 {"$fcc0", RTYPE_FCC | 0}, \
1632 {"$fcc1", RTYPE_FCC | 1}, \
1633 {"$fcc2", RTYPE_FCC | 2}, \
1634 {"$fcc3", RTYPE_FCC | 3}, \
1635 {"$fcc4", RTYPE_FCC | 4}, \
1636 {"$fcc5", RTYPE_FCC | 5}, \
1637 {"$fcc6", RTYPE_FCC | 6}, \
1638 {"$fcc7", RTYPE_FCC | 7}
1640 #define COPROC_CONDITION_CODE_NAMES \
1641 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1642 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1643 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1644 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1645 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1646 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1647 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1648 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1650 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1651 {"$a4", RTYPE_GP | 8}, \
1652 {"$a5", RTYPE_GP | 9}, \
1653 {"$a6", RTYPE_GP | 10}, \
1654 {"$a7", RTYPE_GP | 11}, \
1655 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1656 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1657 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1658 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1659 {"$t0", RTYPE_GP | 12}, \
1660 {"$t1", RTYPE_GP | 13}, \
1661 {"$t2", RTYPE_GP | 14}, \
1662 {"$t3", RTYPE_GP | 15}
1664 #define O32_SYMBOLIC_REGISTER_NAMES \
1665 {"$t0", RTYPE_GP | 8}, \
1666 {"$t1", RTYPE_GP | 9}, \
1667 {"$t2", RTYPE_GP | 10}, \
1668 {"$t3", RTYPE_GP | 11}, \
1669 {"$t4", RTYPE_GP | 12}, \
1670 {"$t5", RTYPE_GP | 13}, \
1671 {"$t6", RTYPE_GP | 14}, \
1672 {"$t7", RTYPE_GP | 15}, \
1673 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1674 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1675 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1676 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1678 /* Remaining symbolic register names */
1679 #define SYMBOLIC_REGISTER_NAMES \
1680 {"$zero", RTYPE_GP | 0}, \
1681 {"$at", RTYPE_GP | 1}, \
1682 {"$AT", RTYPE_GP | 1}, \
1683 {"$v0", RTYPE_GP | 2}, \
1684 {"$v1", RTYPE_GP | 3}, \
1685 {"$a0", RTYPE_GP | 4}, \
1686 {"$a1", RTYPE_GP | 5}, \
1687 {"$a2", RTYPE_GP | 6}, \
1688 {"$a3", RTYPE_GP | 7}, \
1689 {"$s0", RTYPE_GP | 16}, \
1690 {"$s1", RTYPE_GP | 17}, \
1691 {"$s2", RTYPE_GP | 18}, \
1692 {"$s3", RTYPE_GP | 19}, \
1693 {"$s4", RTYPE_GP | 20}, \
1694 {"$s5", RTYPE_GP | 21}, \
1695 {"$s6", RTYPE_GP | 22}, \
1696 {"$s7", RTYPE_GP | 23}, \
1697 {"$t8", RTYPE_GP | 24}, \
1698 {"$t9", RTYPE_GP | 25}, \
1699 {"$k0", RTYPE_GP | 26}, \
1700 {"$kt0", RTYPE_GP | 26}, \
1701 {"$k1", RTYPE_GP | 27}, \
1702 {"$kt1", RTYPE_GP | 27}, \
1703 {"$gp", RTYPE_GP | 28}, \
1704 {"$sp", RTYPE_GP | 29}, \
1705 {"$s8", RTYPE_GP | 30}, \
1706 {"$fp", RTYPE_GP | 30}, \
1707 {"$ra", RTYPE_GP | 31}
1709 #define MIPS16_SPECIAL_REGISTER_NAMES \
1710 {"$pc", RTYPE_PC | 0}
1712 #define MDMX_VECTOR_REGISTER_NAMES \
1713 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1714 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1715 {"$v2", RTYPE_VEC | 2}, \
1716 {"$v3", RTYPE_VEC | 3}, \
1717 {"$v4", RTYPE_VEC | 4}, \
1718 {"$v5", RTYPE_VEC | 5}, \
1719 {"$v6", RTYPE_VEC | 6}, \
1720 {"$v7", RTYPE_VEC | 7}, \
1721 {"$v8", RTYPE_VEC | 8}, \
1722 {"$v9", RTYPE_VEC | 9}, \
1723 {"$v10", RTYPE_VEC | 10}, \
1724 {"$v11", RTYPE_VEC | 11}, \
1725 {"$v12", RTYPE_VEC | 12}, \
1726 {"$v13", RTYPE_VEC | 13}, \
1727 {"$v14", RTYPE_VEC | 14}, \
1728 {"$v15", RTYPE_VEC | 15}, \
1729 {"$v16", RTYPE_VEC | 16}, \
1730 {"$v17", RTYPE_VEC | 17}, \
1731 {"$v18", RTYPE_VEC | 18}, \
1732 {"$v19", RTYPE_VEC | 19}, \
1733 {"$v20", RTYPE_VEC | 20}, \
1734 {"$v21", RTYPE_VEC | 21}, \
1735 {"$v22", RTYPE_VEC | 22}, \
1736 {"$v23", RTYPE_VEC | 23}, \
1737 {"$v24", RTYPE_VEC | 24}, \
1738 {"$v25", RTYPE_VEC | 25}, \
1739 {"$v26", RTYPE_VEC | 26}, \
1740 {"$v27", RTYPE_VEC | 27}, \
1741 {"$v28", RTYPE_VEC | 28}, \
1742 {"$v29", RTYPE_VEC | 29}, \
1743 {"$v30", RTYPE_VEC | 30}, \
1744 {"$v31", RTYPE_VEC | 31}
1746 #define MIPS_DSP_ACCUMULATOR_NAMES \
1747 {"$ac0", RTYPE_ACC | 0}, \
1748 {"$ac1", RTYPE_ACC | 1}, \
1749 {"$ac2", RTYPE_ACC | 2}, \
1750 {"$ac3", RTYPE_ACC | 3}
1752 static const struct regname reg_names[] = {
1753 GENERIC_REGISTER_NUMBERS,
1755 FPU_CONDITION_CODE_NAMES,
1756 COPROC_CONDITION_CODE_NAMES,
1758 /* The $txx registers depends on the abi,
1759 these will be added later into the symbol table from
1760 one of the tables below once mips_abi is set after
1761 parsing of arguments from the command line. */
1762 SYMBOLIC_REGISTER_NAMES,
1764 MIPS16_SPECIAL_REGISTER_NAMES,
1765 MDMX_VECTOR_REGISTER_NAMES,
1766 MIPS_DSP_ACCUMULATOR_NAMES,
1770 static const struct regname reg_names_o32[] = {
1771 O32_SYMBOLIC_REGISTER_NAMES,
1775 static const struct regname reg_names_n32n64[] = {
1776 N32N64_SYMBOLIC_REGISTER_NAMES,
1781 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1788 /* Find end of name. */
1790 if (is_name_beginner (*e))
1792 while (is_part_of_name (*e))
1795 /* Terminate name. */
1799 /* Look for a register symbol. */
1800 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1802 int r = S_GET_VALUE (symbolP);
1804 reg = r & RNUM_MASK;
1805 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1806 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1807 reg = (r & RNUM_MASK) - 2;
1809 /* Else see if this is a register defined in an itbl entry. */
1810 else if ((types & RTYPE_GP) && itbl_have_entries)
1817 if (itbl_get_reg_val (n, &r))
1818 reg = r & RNUM_MASK;
1821 /* Advance to next token if a register was recognised. */
1824 else if (types & RWARN)
1825 as_warn (_("Unrecognized register name `%s'"), *s);
1833 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1834 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1837 is_opcode_valid (const struct mips_opcode *mo)
1839 int isa = mips_opts.isa;
1842 if (mips_opts.ase_mdmx)
1844 if (mips_opts.ase_dsp)
1846 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1848 if (mips_opts.ase_dspr2)
1850 if (mips_opts.ase_mt)
1852 if (mips_opts.ase_mips3d)
1854 if (mips_opts.ase_smartmips)
1855 isa |= INSN_SMARTMIPS;
1857 /* Don't accept instructions based on the ISA if the CPU does not implement
1858 all the coprocessor insns. */
1859 if (NO_ISA_COP (mips_opts.arch)
1860 && COP_INSN (mo->pinfo))
1863 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1866 /* Check whether the instruction or macro requires single-precision or
1867 double-precision floating-point support. Note that this information is
1868 stored differently in the opcode table for insns and macros. */
1869 if (mo->pinfo == INSN_MACRO)
1871 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1872 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1876 fp_s = mo->pinfo & FP_S;
1877 fp_d = mo->pinfo & FP_D;
1880 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1883 if (fp_s && mips_opts.soft_float)
1889 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1890 selected ISA and architecture. */
1893 is_opcode_valid_16 (const struct mips_opcode *mo)
1895 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1898 /* This function is called once, at assembler startup time. It should set up
1899 all the tables, etc. that the MD part of the assembler will need. */
1904 const char *retval = NULL;
1908 if (mips_pic != NO_PIC)
1910 if (g_switch_seen && g_switch_value != 0)
1911 as_bad (_("-G may not be used in position-independent code"));
1915 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1916 as_warn (_("Could not set architecture and machine"));
1918 op_hash = hash_new ();
1920 for (i = 0; i < NUMOPCODES;)
1922 const char *name = mips_opcodes[i].name;
1924 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1927 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1928 mips_opcodes[i].name, retval);
1929 /* Probably a memory allocation problem? Give up now. */
1930 as_fatal (_("Broken assembler. No assembly attempted."));
1934 if (mips_opcodes[i].pinfo != INSN_MACRO)
1936 if (!validate_mips_insn (&mips_opcodes[i]))
1938 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1940 create_insn (&nop_insn, mips_opcodes + i);
1941 if (mips_fix_loongson2f_nop)
1942 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1943 nop_insn.fixed_p = 1;
1948 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1951 mips16_op_hash = hash_new ();
1954 while (i < bfd_mips16_num_opcodes)
1956 const char *name = mips16_opcodes[i].name;
1958 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1960 as_fatal (_("internal: can't hash `%s': %s"),
1961 mips16_opcodes[i].name, retval);
1964 if (mips16_opcodes[i].pinfo != INSN_MACRO
1965 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1966 != mips16_opcodes[i].match))
1968 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1969 mips16_opcodes[i].name, mips16_opcodes[i].args);
1972 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1974 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1975 mips16_nop_insn.fixed_p = 1;
1979 while (i < bfd_mips16_num_opcodes
1980 && strcmp (mips16_opcodes[i].name, name) == 0);
1984 as_fatal (_("Broken assembler. No assembly attempted."));
1986 /* We add all the general register names to the symbol table. This
1987 helps us detect invalid uses of them. */
1988 for (i = 0; reg_names[i].name; i++)
1989 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1990 reg_names[i].num, /* & RNUM_MASK, */
1991 &zero_address_frag));
1993 for (i = 0; reg_names_n32n64[i].name; i++)
1994 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1995 reg_names_n32n64[i].num, /* & RNUM_MASK, */
1996 &zero_address_frag));
1998 for (i = 0; reg_names_o32[i].name; i++)
1999 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2000 reg_names_o32[i].num, /* & RNUM_MASK, */
2001 &zero_address_frag));
2003 mips_no_prev_insn ();
2006 mips_cprmask[0] = 0;
2007 mips_cprmask[1] = 0;
2008 mips_cprmask[2] = 0;
2009 mips_cprmask[3] = 0;
2011 /* set the default alignment for the text section (2**2) */
2012 record_alignment (text_section, 2);
2014 bfd_set_gp_size (stdoutput, g_switch_value);
2019 /* On a native system other than VxWorks, sections must be aligned
2020 to 16 byte boundaries. When configured for an embedded ELF
2021 target, we don't bother. */
2022 if (strncmp (TARGET_OS, "elf", 3) != 0
2023 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2025 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2026 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2027 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2030 /* Create a .reginfo section for register masks and a .mdebug
2031 section for debugging information. */
2039 subseg = now_subseg;
2041 /* The ABI says this section should be loaded so that the
2042 running program can access it. However, we don't load it
2043 if we are configured for an embedded target */
2044 flags = SEC_READONLY | SEC_DATA;
2045 if (strncmp (TARGET_OS, "elf", 3) != 0)
2046 flags |= SEC_ALLOC | SEC_LOAD;
2048 if (mips_abi != N64_ABI)
2050 sec = subseg_new (".reginfo", (subsegT) 0);
2052 bfd_set_section_flags (stdoutput, sec, flags);
2053 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2055 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2059 /* The 64-bit ABI uses a .MIPS.options section rather than
2060 .reginfo section. */
2061 sec = subseg_new (".MIPS.options", (subsegT) 0);
2062 bfd_set_section_flags (stdoutput, sec, flags);
2063 bfd_set_section_alignment (stdoutput, sec, 3);
2065 /* Set up the option header. */
2067 Elf_Internal_Options opthdr;
2070 opthdr.kind = ODK_REGINFO;
2071 opthdr.size = (sizeof (Elf_External_Options)
2072 + sizeof (Elf64_External_RegInfo));
2075 f = frag_more (sizeof (Elf_External_Options));
2076 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2077 (Elf_External_Options *) f);
2079 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2083 if (ECOFF_DEBUGGING)
2085 sec = subseg_new (".mdebug", (subsegT) 0);
2086 (void) bfd_set_section_flags (stdoutput, sec,
2087 SEC_HAS_CONTENTS | SEC_READONLY);
2088 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2090 else if (mips_flag_pdr)
2092 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2093 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2094 SEC_READONLY | SEC_RELOC
2096 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2099 subseg_set (seg, subseg);
2102 #endif /* OBJ_ELF */
2104 if (! ECOFF_DEBUGGING)
2107 if (mips_fix_vr4120)
2108 init_vr4120_conflicts ();
2114 if (! ECOFF_DEBUGGING)
2119 md_assemble (char *str)
2121 struct mips_cl_insn insn;
2122 bfd_reloc_code_real_type unused_reloc[3]
2123 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2125 imm_expr.X_op = O_absent;
2126 imm2_expr.X_op = O_absent;
2127 offset_expr.X_op = O_absent;
2128 imm_reloc[0] = BFD_RELOC_UNUSED;
2129 imm_reloc[1] = BFD_RELOC_UNUSED;
2130 imm_reloc[2] = BFD_RELOC_UNUSED;
2131 offset_reloc[0] = BFD_RELOC_UNUSED;
2132 offset_reloc[1] = BFD_RELOC_UNUSED;
2133 offset_reloc[2] = BFD_RELOC_UNUSED;
2135 if (mips_opts.mips16)
2136 mips16_ip (str, &insn);
2139 mips_ip (str, &insn);
2140 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2141 str, insn.insn_opcode));
2146 as_bad ("%s `%s'", insn_error, str);
2150 if (insn.insn_mo->pinfo == INSN_MACRO)
2153 if (mips_opts.mips16)
2154 mips16_macro (&insn);
2161 if (imm_expr.X_op != O_absent)
2162 append_insn (&insn, &imm_expr, imm_reloc);
2163 else if (offset_expr.X_op != O_absent)
2164 append_insn (&insn, &offset_expr, offset_reloc);
2166 append_insn (&insn, NULL, unused_reloc);
2170 /* Convenience functions for abstracting away the differences between
2171 MIPS16 and non-MIPS16 relocations. */
2173 static inline bfd_boolean
2174 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2178 case BFD_RELOC_MIPS16_JMP:
2179 case BFD_RELOC_MIPS16_GPREL:
2180 case BFD_RELOC_MIPS16_GOT16:
2181 case BFD_RELOC_MIPS16_CALL16:
2182 case BFD_RELOC_MIPS16_HI16_S:
2183 case BFD_RELOC_MIPS16_HI16:
2184 case BFD_RELOC_MIPS16_LO16:
2192 static inline bfd_boolean
2193 got16_reloc_p (bfd_reloc_code_real_type reloc)
2195 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2198 static inline bfd_boolean
2199 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2201 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2204 static inline bfd_boolean
2205 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2207 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2210 /* Return true if the given relocation might need a matching %lo().
2211 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2212 need a matching %lo() when applied to local symbols. */
2214 static inline bfd_boolean
2215 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2217 return (HAVE_IN_PLACE_ADDENDS
2218 && (hi16_reloc_p (reloc)
2219 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2220 all GOT16 relocations evaluate to "G". */
2221 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2224 /* Return the type of %lo() reloc needed by RELOC, given that
2225 reloc_needs_lo_p. */
2227 static inline bfd_reloc_code_real_type
2228 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2230 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2233 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2236 static inline bfd_boolean
2237 fixup_has_matching_lo_p (fixS *fixp)
2239 return (fixp->fx_next != NULL
2240 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2241 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2242 && fixp->fx_offset == fixp->fx_next->fx_offset);
2245 /* See whether instruction IP reads register REG. CLASS is the type
2249 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
2250 enum mips_regclass regclass)
2252 if (regclass == MIPS16_REG)
2254 gas_assert (mips_opts.mips16);
2255 reg = mips16_to_32_reg_map[reg];
2256 regclass = MIPS_GR_REG;
2259 /* Don't report on general register ZERO, since it never changes. */
2260 if (regclass == MIPS_GR_REG && reg == ZERO)
2263 if (regclass == MIPS_FP_REG)
2265 gas_assert (! mips_opts.mips16);
2266 /* If we are called with either $f0 or $f1, we must check $f0.
2267 This is not optimal, because it will introduce an unnecessary
2268 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2269 need to distinguish reading both $f0 and $f1 or just one of
2270 them. Note that we don't have to check the other way,
2271 because there is no instruction that sets both $f0 and $f1
2272 and requires a delay. */
2273 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
2274 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
2275 == (reg &~ (unsigned) 1)))
2277 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
2278 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
2279 == (reg &~ (unsigned) 1)))
2281 if ((ip->insn_mo->pinfo2 & INSN2_READ_FPR_Z)
2282 && ((EXTRACT_OPERAND (FZ, *ip) & ~(unsigned) 1)
2283 == (reg &~ (unsigned) 1)))
2286 else if (! mips_opts.mips16)
2288 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
2289 && EXTRACT_OPERAND (RS, *ip) == reg)
2291 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
2292 && EXTRACT_OPERAND (RT, *ip) == reg)
2294 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_D)
2295 && EXTRACT_OPERAND (RD, *ip) == reg)
2297 if ((ip->insn_mo->pinfo2 & INSN2_READ_GPR_Z)
2298 && EXTRACT_OPERAND (RZ, *ip) == reg)
2303 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
2304 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
2306 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
2307 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
2309 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
2310 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
2313 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
2315 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
2317 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
2319 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
2320 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
2327 /* This function returns true if modifying a register requires a
2331 reg_needs_delay (unsigned int reg)
2333 unsigned long prev_pinfo;
2335 prev_pinfo = history[0].insn_mo->pinfo;
2336 if (! mips_opts.noreorder
2337 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2338 && ! gpr_interlocks)
2339 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2340 && ! cop_interlocks)))
2342 /* A load from a coprocessor or from memory. All load delays
2343 delay the use of general register rt for one instruction. */
2344 /* Itbl support may require additional care here. */
2345 know (prev_pinfo & INSN_WRITE_GPR_T);
2346 if (reg == EXTRACT_OPERAND (RT, history[0]))
2353 /* Move all labels in insn_labels to the current insertion point. */
2356 mips_move_labels (void)
2358 segment_info_type *si = seg_info (now_seg);
2359 struct insn_label_list *l;
2362 for (l = si->label_list; l != NULL; l = l->next)
2364 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2365 symbol_set_frag (l->label, frag_now);
2366 val = (valueT) frag_now_fix ();
2367 /* mips16 text labels are stored as odd. */
2368 if (mips_opts.mips16)
2370 S_SET_VALUE (l->label, val);
2375 s_is_linkonce (symbolS *sym, segT from_seg)
2377 bfd_boolean linkonce = FALSE;
2378 segT symseg = S_GET_SEGMENT (sym);
2380 if (symseg != from_seg && !S_IS_LOCAL (sym))
2382 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2385 /* The GNU toolchain uses an extension for ELF: a section
2386 beginning with the magic string .gnu.linkonce is a
2387 linkonce section. */
2388 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2389 sizeof ".gnu.linkonce" - 1) == 0)
2396 /* Mark instruction labels in mips16 mode. This permits the linker to
2397 handle them specially, such as generating jalx instructions when
2398 needed. We also make them odd for the duration of the assembly, in
2399 order to generate the right sort of code. We will make them even
2400 in the adjust_symtab routine, while leaving them marked. This is
2401 convenient for the debugger and the disassembler. The linker knows
2402 to make them odd again. */
2405 mips16_mark_labels (void)
2407 segment_info_type *si = seg_info (now_seg);
2408 struct insn_label_list *l;
2410 if (!mips_opts.mips16)
2413 for (l = si->label_list; l != NULL; l = l->next)
2415 symbolS *label = l->label;
2417 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2419 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2421 if ((S_GET_VALUE (label) & 1) == 0
2422 /* Don't adjust the address if the label is global or weak, or
2423 in a link-once section, since we'll be emitting symbol reloc
2424 references to it which will be patched up by the linker, and
2425 the final value of the symbol may or may not be MIPS16. */
2426 && ! S_IS_WEAK (label)
2427 && ! S_IS_EXTERNAL (label)
2428 && ! s_is_linkonce (label, now_seg))
2429 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2433 /* End the current frag. Make it a variant frag and record the
2437 relax_close_frag (void)
2439 mips_macro_warning.first_frag = frag_now;
2440 frag_var (rs_machine_dependent, 0, 0,
2441 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2442 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2444 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2445 mips_relax.first_fixup = 0;
2448 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2449 See the comment above RELAX_ENCODE for more details. */
2452 relax_start (symbolS *symbol)
2454 gas_assert (mips_relax.sequence == 0);
2455 mips_relax.sequence = 1;
2456 mips_relax.symbol = symbol;
2459 /* Start generating the second version of a relaxable sequence.
2460 See the comment above RELAX_ENCODE for more details. */
2465 gas_assert (mips_relax.sequence == 1);
2466 mips_relax.sequence = 2;
2469 /* End the current relaxable sequence. */
2474 gas_assert (mips_relax.sequence == 2);
2475 relax_close_frag ();
2476 mips_relax.sequence = 0;
2479 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2480 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2481 by VR4120 errata. */
2484 classify_vr4120_insn (const char *name)
2486 if (strncmp (name, "macc", 4) == 0)
2487 return FIX_VR4120_MACC;
2488 if (strncmp (name, "dmacc", 5) == 0)
2489 return FIX_VR4120_DMACC;
2490 if (strncmp (name, "mult", 4) == 0)
2491 return FIX_VR4120_MULT;
2492 if (strncmp (name, "dmult", 5) == 0)
2493 return FIX_VR4120_DMULT;
2494 if (strstr (name, "div"))
2495 return FIX_VR4120_DIV;
2496 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2497 return FIX_VR4120_MTHILO;
2498 return NUM_FIX_VR4120_CLASSES;
2501 #define INSN_ERET 0x42000018
2502 #define INSN_DERET 0x4200001f
2504 /* Return the number of instructions that must separate INSN1 and INSN2,
2505 where INSN1 is the earlier instruction. Return the worst-case value
2506 for any INSN2 if INSN2 is null. */
2509 insns_between (const struct mips_cl_insn *insn1,
2510 const struct mips_cl_insn *insn2)
2512 unsigned long pinfo1, pinfo2;
2514 /* This function needs to know which pinfo flags are set for INSN2
2515 and which registers INSN2 uses. The former is stored in PINFO2 and
2516 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2517 will have every flag set and INSN2_USES_REG will always return true. */
2518 pinfo1 = insn1->insn_mo->pinfo;
2519 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2521 #define INSN2_USES_REG(REG, CLASS) \
2522 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2524 /* For most targets, write-after-read dependencies on the HI and LO
2525 registers must be separated by at least two instructions. */
2526 if (!hilo_interlocks)
2528 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2530 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2534 /* If we're working around r7000 errata, there must be two instructions
2535 between an mfhi or mflo and any instruction that uses the result. */
2536 if (mips_7000_hilo_fix
2537 && MF_HILO_INSN (pinfo1)
2538 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
2541 /* If we're working around 24K errata, one instruction is required
2542 if an ERET or DERET is followed by a branch instruction. */
2545 if (insn1->insn_opcode == INSN_ERET
2546 || insn1->insn_opcode == INSN_DERET)
2549 || insn2->insn_opcode == INSN_ERET
2550 || insn2->insn_opcode == INSN_DERET
2551 || (insn2->insn_mo->pinfo
2552 & (INSN_UNCOND_BRANCH_DELAY
2553 | INSN_COND_BRANCH_DELAY
2554 | INSN_COND_BRANCH_LIKELY)) != 0)
2559 /* If working around VR4120 errata, check for combinations that need
2560 a single intervening instruction. */
2561 if (mips_fix_vr4120)
2563 unsigned int class1, class2;
2565 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2566 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2570 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2571 if (vr4120_conflicts[class1] & (1 << class2))
2576 if (!mips_opts.mips16)
2578 /* Check for GPR or coprocessor load delays. All such delays
2579 are on the RT register. */
2580 /* Itbl support may require additional care here. */
2581 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2582 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2584 know (pinfo1 & INSN_WRITE_GPR_T);
2585 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2589 /* Check for generic coprocessor hazards.
2591 This case is not handled very well. There is no special
2592 knowledge of CP0 handling, and the coprocessors other than
2593 the floating point unit are not distinguished at all. */
2594 /* Itbl support may require additional care here. FIXME!
2595 Need to modify this to include knowledge about
2596 user specified delays! */
2597 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2598 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2600 /* Handle cases where INSN1 writes to a known general coprocessor
2601 register. There must be a one instruction delay before INSN2
2602 if INSN2 reads that register, otherwise no delay is needed. */
2603 if (pinfo1 & INSN_WRITE_FPR_T)
2605 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2608 else if (pinfo1 & INSN_WRITE_FPR_S)
2610 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2615 /* Read-after-write dependencies on the control registers
2616 require a two-instruction gap. */
2617 if ((pinfo1 & INSN_WRITE_COND_CODE)
2618 && (pinfo2 & INSN_READ_COND_CODE))
2621 /* We don't know exactly what INSN1 does. If INSN2 is
2622 also a coprocessor instruction, assume there must be
2623 a one instruction gap. */
2624 if (pinfo2 & INSN_COP)
2629 /* Check for read-after-write dependencies on the coprocessor
2630 control registers in cases where INSN1 does not need a general
2631 coprocessor delay. This means that INSN1 is a floating point
2632 comparison instruction. */
2633 /* Itbl support may require additional care here. */
2634 else if (!cop_interlocks
2635 && (pinfo1 & INSN_WRITE_COND_CODE)
2636 && (pinfo2 & INSN_READ_COND_CODE))
2640 #undef INSN2_USES_REG
2645 /* Return the number of nops that would be needed to work around the
2646 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2647 the MAX_VR4130_NOPS instructions described by HIST. */
2650 nops_for_vr4130 (const struct mips_cl_insn *hist,
2651 const struct mips_cl_insn *insn)
2655 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2656 are not affected by the errata. */
2658 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2659 || strcmp (insn->insn_mo->name, "mtlo") == 0
2660 || strcmp (insn->insn_mo->name, "mthi") == 0))
2663 /* Search for the first MFLO or MFHI. */
2664 for (i = 0; i < MAX_VR4130_NOPS; i++)
2665 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2667 /* Extract the destination register. */
2668 if (mips_opts.mips16)
2669 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, hist[i])];
2671 reg = EXTRACT_OPERAND (RD, hist[i]);
2673 /* No nops are needed if INSN reads that register. */
2674 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2677 /* ...or if any of the intervening instructions do. */
2678 for (j = 0; j < i; j++)
2679 if (insn_uses_reg (&hist[j], reg, MIPS_GR_REG))
2682 return MAX_VR4130_NOPS - i;
2687 #define BASE_REG_EQ(INSN1, INSN2) \
2688 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2689 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2691 /* Return the minimum alignment for this store instruction. */
2694 fix_24k_align_to (const struct mips_opcode *mo)
2696 if (strcmp (mo->name, "sh") == 0)
2699 if (strcmp (mo->name, "swc1") == 0
2700 || strcmp (mo->name, "swc2") == 0
2701 || strcmp (mo->name, "sw") == 0
2702 || strcmp (mo->name, "sc") == 0
2703 || strcmp (mo->name, "s.s") == 0)
2706 if (strcmp (mo->name, "sdc1") == 0
2707 || strcmp (mo->name, "sdc2") == 0
2708 || strcmp (mo->name, "s.d") == 0)
2715 struct fix_24k_store_info
2717 /* Immediate offset, if any, for this store instruction. */
2719 /* Alignment required by this store instruction. */
2721 /* True for register offsets. */
2722 int register_offset;
2725 /* Comparison function used by qsort. */
2728 fix_24k_sort (const void *a, const void *b)
2730 const struct fix_24k_store_info *pos1 = a;
2731 const struct fix_24k_store_info *pos2 = b;
2733 return (pos1->off - pos2->off);
2736 /* INSN is a store instruction. Try to record the store information
2737 in STINFO. Return false if the information isn't known. */
2740 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2741 const struct mips_cl_insn *insn)
2743 /* The instruction must have a known offset. */
2744 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2747 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2748 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2752 /* 24K Errata: Lost Data on Stores During Refill.
2754 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2755 for the data cache refills and store data. The following describes
2756 the scenario where the store data could be lost.
2758 * A data cache miss, due to either a load or a store, causing fill
2759 data to be supplied by the memory subsystem
2760 * The first three doublewords of fill data are returned and written
2762 * A sequence of four stores occurs in consecutive cycles around the
2763 final doubleword of the fill:
2767 * Zero, One or more instructions
2770 The four stores A-D must be to different doublewords of the line that
2771 is being filled. The fourth instruction in the sequence above permits
2772 the fill of the final doubleword to be transferred from the FSB into
2773 the cache. In the sequence above, the stores may be either integer
2774 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2775 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2776 different doublewords on the line. If the floating point unit is
2777 running in 1:2 mode, it is not possible to create the sequence above
2778 using only floating point store instructions.
2780 In this case, the cache line being filled is incorrectly marked
2781 invalid, thereby losing the data from any store to the line that
2782 occurs between the original miss and the completion of the five
2783 cycle sequence shown above.
2785 The workarounds are:
2787 * Run the data cache in write-through mode.
2788 * Insert a non-store instruction between
2789 Store A and Store B or Store B and Store C. */
2792 nops_for_24k (const struct mips_cl_insn *hist,
2793 const struct mips_cl_insn *insn)
2795 struct fix_24k_store_info pos[3];
2796 int align, i, base_offset;
2798 /* If INSN is definitely not a store, there's nothing to worry about. */
2799 if (insn && (insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2802 /* Likewise, the previous instruction wasn't a store. */
2803 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2806 /* If we don't know what came before, assume the worst. */
2807 if (hist[1].frag == NULL)
2810 /* If the instruction was not a store, there's nothing to worry about. */
2811 if ((hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2814 /* If we don't know the relationship between the store addresses,
2815 assume the worst. */
2817 || !BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2818 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2821 if (!fix_24k_record_store_info (&pos[0], insn)
2822 || !fix_24k_record_store_info (&pos[1], &hist[0])
2823 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2826 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2828 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2829 X bytes and such that the base register + X is known to be aligned
2832 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2836 align = pos[0].align_to;
2837 base_offset = pos[0].off;
2838 for (i = 1; i < 3; i++)
2839 if (align < pos[i].align_to)
2841 align = pos[i].align_to;
2842 base_offset = pos[i].off;
2844 for (i = 0; i < 3; i++)
2845 pos[i].off -= base_offset;
2848 pos[0].off &= ~align + 1;
2849 pos[1].off &= ~align + 1;
2850 pos[2].off &= ~align + 1;
2852 /* If any two stores write to the same chunk, they also write to the
2853 same doubleword. The offsets are still sorted at this point. */
2854 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2857 /* A range of at least 9 bytes is needed for the stores to be in
2858 non-overlapping doublewords. */
2859 if (pos[2].off - pos[0].off <= 8)
2862 if (pos[2].off - pos[1].off >= 24
2863 || pos[1].off - pos[0].off >= 24
2864 || pos[2].off - pos[0].off >= 32)
2870 /* Return the number of nops that would be needed if instruction INSN
2871 immediately followed the MAX_NOPS instructions given by HIST,
2872 where HIST[0] is the most recent instruction. If INSN is null,
2873 return the worse-case number of nops for any instruction. */
2876 nops_for_insn (const struct mips_cl_insn *hist,
2877 const struct mips_cl_insn *insn)
2879 int i, nops, tmp_nops;
2882 for (i = 0; i < MAX_DELAY_NOPS; i++)
2884 tmp_nops = insns_between (hist + i, insn) - i;
2885 if (tmp_nops > nops)
2889 if (mips_fix_vr4130)
2891 tmp_nops = nops_for_vr4130 (hist, insn);
2892 if (tmp_nops > nops)
2898 tmp_nops = nops_for_24k (hist, insn);
2899 if (tmp_nops > nops)
2906 /* The variable arguments provide NUM_INSNS extra instructions that
2907 might be added to HIST. Return the largest number of nops that
2908 would be needed after the extended sequence. */
2911 nops_for_sequence (int num_insns, const struct mips_cl_insn *hist, ...)
2914 struct mips_cl_insn buffer[MAX_NOPS];
2915 struct mips_cl_insn *cursor;
2918 va_start (args, hist);
2919 cursor = buffer + num_insns;
2920 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
2921 while (cursor > buffer)
2922 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2924 nops = nops_for_insn (buffer, NULL);
2929 /* Like nops_for_insn, but if INSN is a branch, take into account the
2930 worst-case delay for the branch target. */
2933 nops_for_insn_or_target (const struct mips_cl_insn *hist,
2934 const struct mips_cl_insn *insn)
2938 nops = nops_for_insn (hist, insn);
2939 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2940 | INSN_COND_BRANCH_DELAY
2941 | INSN_COND_BRANCH_LIKELY))
2943 tmp_nops = nops_for_sequence (2, hist, insn, NOP_INSN);
2944 if (tmp_nops > nops)
2947 else if (mips_opts.mips16
2948 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2949 | MIPS16_INSN_COND_BRANCH)))
2951 tmp_nops = nops_for_sequence (1, hist, insn);
2952 if (tmp_nops > nops)
2958 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2961 fix_loongson2f_nop (struct mips_cl_insn * ip)
2963 if (strcmp (ip->insn_mo->name, "nop") == 0)
2964 ip->insn_opcode = LOONGSON2F_NOP_INSN;
2967 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2968 jr target pc &= 'hffff_ffff_cfff_ffff. */
2971 fix_loongson2f_jump (struct mips_cl_insn * ip)
2973 if (strcmp (ip->insn_mo->name, "j") == 0
2974 || strcmp (ip->insn_mo->name, "jr") == 0
2975 || strcmp (ip->insn_mo->name, "jalr") == 0)
2983 sreg = EXTRACT_OPERAND (RS, *ip);
2984 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
2987 ep.X_op = O_constant;
2988 ep.X_add_number = 0xcfff0000;
2989 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
2990 ep.X_add_number = 0xffff;
2991 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
2992 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
2997 fix_loongson2f (struct mips_cl_insn * ip)
2999 if (mips_fix_loongson2f_nop)
3000 fix_loongson2f_nop (ip);
3002 if (mips_fix_loongson2f_jump)
3003 fix_loongson2f_jump (ip);
3006 /* Output an instruction. IP is the instruction information.
3007 ADDRESS_EXPR is an operand of the instruction to be used with
3011 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3012 bfd_reloc_code_real_type *reloc_type)
3014 unsigned long prev_pinfo, pinfo;
3015 unsigned long prev_pinfo2, pinfo2;
3016 relax_stateT prev_insn_frag_type = 0;
3017 bfd_boolean relaxed_branch = FALSE;
3018 segment_info_type *si = seg_info (now_seg);
3020 if (mips_fix_loongson2f)
3021 fix_loongson2f (ip);
3023 /* Mark instruction labels in mips16 mode. */
3024 mips16_mark_labels ();
3026 file_ase_mips16 |= mips_opts.mips16;
3028 prev_pinfo = history[0].insn_mo->pinfo;
3029 prev_pinfo2 = history[0].insn_mo->pinfo2;
3030 pinfo = ip->insn_mo->pinfo;
3031 pinfo2 = ip->insn_mo->pinfo2;
3033 if (address_expr == NULL)
3035 else if (*reloc_type <= BFD_RELOC_UNUSED
3036 && address_expr->X_op == O_constant)
3041 switch (*reloc_type)
3044 ip->insn_opcode |= address_expr->X_add_number;
3047 case BFD_RELOC_MIPS_HIGHEST:
3048 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3049 ip->insn_opcode |= tmp & 0xffff;
3052 case BFD_RELOC_MIPS_HIGHER:
3053 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3054 ip->insn_opcode |= tmp & 0xffff;
3057 case BFD_RELOC_HI16_S:
3058 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3059 ip->insn_opcode |= tmp & 0xffff;
3062 case BFD_RELOC_HI16:
3063 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3066 case BFD_RELOC_UNUSED:
3067 case BFD_RELOC_LO16:
3068 case BFD_RELOC_MIPS_GOT_DISP:
3069 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3072 case BFD_RELOC_MIPS_JMP:
3073 if ((address_expr->X_add_number & 3) != 0)
3074 as_bad (_("jump to misaligned address (0x%lx)"),
3075 (unsigned long) address_expr->X_add_number);
3076 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3080 case BFD_RELOC_MIPS16_JMP:
3081 if ((address_expr->X_add_number & 3) != 0)
3082 as_bad (_("jump to misaligned address (0x%lx)"),
3083 (unsigned long) address_expr->X_add_number);
3085 (((address_expr->X_add_number & 0x7c0000) << 3)
3086 | ((address_expr->X_add_number & 0xf800000) >> 7)
3087 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3091 case BFD_RELOC_16_PCREL_S2:
3092 if ((address_expr->X_add_number & 3) != 0)
3093 as_bad (_("branch to misaligned address (0x%lx)"),
3094 (unsigned long) address_expr->X_add_number);
3095 if (mips_relax_branch)
3097 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3098 as_bad (_("branch address range overflow (0x%lx)"),
3099 (unsigned long) address_expr->X_add_number);
3100 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3109 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3111 /* There are a lot of optimizations we could do that we don't.
3112 In particular, we do not, in general, reorder instructions.
3113 If you use gcc with optimization, it will reorder
3114 instructions and generally do much more optimization then we
3115 do here; repeating all that work in the assembler would only
3116 benefit hand written assembly code, and does not seem worth
3118 int nops = (mips_optimize == 0
3119 ? nops_for_insn (history, NULL)
3120 : nops_for_insn_or_target (history, ip));
3124 unsigned long old_frag_offset;
3127 old_frag = frag_now;
3128 old_frag_offset = frag_now_fix ();
3130 for (i = 0; i < nops; i++)
3135 listing_prev_line ();
3136 /* We may be at the start of a variant frag. In case we
3137 are, make sure there is enough space for the frag
3138 after the frags created by listing_prev_line. The
3139 argument to frag_grow here must be at least as large
3140 as the argument to all other calls to frag_grow in
3141 this file. We don't have to worry about being in the
3142 middle of a variant frag, because the variants insert
3143 all needed nop instructions themselves. */
3147 mips_move_labels ();
3149 #ifndef NO_ECOFF_DEBUGGING
3150 if (ECOFF_DEBUGGING)
3151 ecoff_fix_loc (old_frag, old_frag_offset);
3155 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3157 struct mips_cl_insn stubbed_history[ARRAY_SIZE (history)];
3160 /* Work out how many nops in prev_nop_frag are needed by IP.
3161 Base this on a history in which all insns since prev_nop_frag
3162 are stubbed out with nops. */
3163 for (i = 0; i < (int) ARRAY_SIZE (history); i++)
3164 if (i < prev_nop_frag_since)
3165 stubbed_history[i] = *NOP_INSN;
3167 stubbed_history[i] = history[i];
3168 nops = nops_for_insn_or_target (stubbed_history, ip);
3169 gas_assert (nops <= prev_nop_frag_holds);
3171 /* Enforce NOPS as a minimum. */
3172 if (nops > prev_nop_frag_required)
3173 prev_nop_frag_required = nops;
3175 if (prev_nop_frag_holds == prev_nop_frag_required)
3177 /* Settle for the current number of nops. Update the history
3178 accordingly (for the benefit of any future .set reorder code). */
3179 prev_nop_frag = NULL;
3180 insert_into_history (prev_nop_frag_since,
3181 prev_nop_frag_holds, NOP_INSN);
3185 /* Allow this instruction to replace one of the nops that was
3186 tentatively added to prev_nop_frag. */
3187 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3188 prev_nop_frag_holds--;
3189 prev_nop_frag_since++;
3194 /* The value passed to dwarf2_emit_insn is the distance between
3195 the beginning of the current instruction and the address that
3196 should be recorded in the debug tables. For MIPS16 debug info
3197 we want to use ISA-encoded addresses, so we pass -1 for an
3198 address higher by one than the current. */
3199 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
3202 /* Record the frag type before frag_var. */
3203 if (history[0].frag)
3204 prev_insn_frag_type = history[0].frag->fr_type;
3207 && *reloc_type == BFD_RELOC_16_PCREL_S2
3208 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3209 || pinfo & INSN_COND_BRANCH_LIKELY)
3210 && mips_relax_branch
3211 /* Don't try branch relaxation within .set nomacro, or within
3212 .set noat if we use $at for PIC computations. If it turns
3213 out that the branch was out-of-range, we'll get an error. */
3214 && !mips_opts.warn_about_macros
3215 && (mips_opts.at || mips_pic == NO_PIC)
3216 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3217 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3218 && !mips_opts.mips16)
3220 relaxed_branch = TRUE;
3221 add_relaxed_insn (ip, (relaxed_branch_length
3223 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3224 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3228 pinfo & INSN_UNCOND_BRANCH_DELAY,
3229 pinfo & INSN_COND_BRANCH_LIKELY,
3230 pinfo & INSN_WRITE_GPR_31,
3232 address_expr->X_add_symbol,
3233 address_expr->X_add_number);
3234 *reloc_type = BFD_RELOC_UNUSED;
3236 else if (*reloc_type > BFD_RELOC_UNUSED)
3238 /* We need to set up a variant frag. */
3239 gas_assert (mips_opts.mips16 && address_expr != NULL);
3240 add_relaxed_insn (ip, 4, 0,
3242 (*reloc_type - BFD_RELOC_UNUSED,
3243 mips16_small, mips16_ext,
3244 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3245 history[0].mips16_absolute_jump_p),
3246 make_expr_symbol (address_expr), 0);
3248 else if (mips_opts.mips16
3250 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3252 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3253 /* Make sure there is enough room to swap this instruction with
3254 a following jump instruction. */
3256 add_fixed_insn (ip);
3260 if (mips_opts.mips16
3261 && mips_opts.noreorder
3262 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3263 as_warn (_("extended instruction in delay slot"));
3265 if (mips_relax.sequence)
3267 /* If we've reached the end of this frag, turn it into a variant
3268 frag and record the information for the instructions we've
3270 if (frag_room () < 4)
3271 relax_close_frag ();
3272 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3275 if (mips_relax.sequence != 2)
3276 mips_macro_warning.sizes[0] += 4;
3277 if (mips_relax.sequence != 1)
3278 mips_macro_warning.sizes[1] += 4;
3280 if (mips_opts.mips16)
3283 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3285 add_fixed_insn (ip);
3288 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
3291 && *reloc_type < BFD_RELOC_UNUSED)
3294 reloc_howto_type *howto;
3297 /* In a compound relocation, it is the final (outermost)
3298 operator that determines the relocated field. */
3299 for (i = 1; i < 3; i++)
3300 if (reloc_type[i] == BFD_RELOC_UNUSED)
3303 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3306 /* To reproduce this failure try assembling gas/testsuites/
3307 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3309 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3310 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3313 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3314 bfd_get_reloc_size (howto),
3316 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3319 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3320 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3321 && ip->fixp[0]->fx_addsy)
3322 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3324 /* These relocations can have an addend that won't fit in
3325 4 octets for 64bit assembly. */
3327 && ! howto->partial_inplace
3328 && (reloc_type[0] == BFD_RELOC_16
3329 || reloc_type[0] == BFD_RELOC_32
3330 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3331 || reloc_type[0] == BFD_RELOC_GPREL16
3332 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3333 || reloc_type[0] == BFD_RELOC_GPREL32
3334 || reloc_type[0] == BFD_RELOC_64
3335 || reloc_type[0] == BFD_RELOC_CTOR
3336 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3337 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3338 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3339 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3340 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3341 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3342 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3343 || hi16_reloc_p (reloc_type[0])
3344 || lo16_reloc_p (reloc_type[0])))
3345 ip->fixp[0]->fx_no_overflow = 1;
3347 if (mips_relax.sequence)
3349 if (mips_relax.first_fixup == 0)
3350 mips_relax.first_fixup = ip->fixp[0];
3352 else if (reloc_needs_lo_p (*reloc_type))
3354 struct mips_hi_fixup *hi_fixup;
3356 /* Reuse the last entry if it already has a matching %lo. */
3357 hi_fixup = mips_hi_fixup_list;
3359 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3361 hi_fixup = ((struct mips_hi_fixup *)
3362 xmalloc (sizeof (struct mips_hi_fixup)));
3363 hi_fixup->next = mips_hi_fixup_list;
3364 mips_hi_fixup_list = hi_fixup;
3366 hi_fixup->fixp = ip->fixp[0];
3367 hi_fixup->seg = now_seg;
3370 /* Add fixups for the second and third relocations, if given.
3371 Note that the ABI allows the second relocation to be
3372 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3373 moment we only use RSS_UNDEF, but we could add support
3374 for the others if it ever becomes necessary. */
3375 for (i = 1; i < 3; i++)
3376 if (reloc_type[i] != BFD_RELOC_UNUSED)
3378 ip->fixp[i] = fix_new (ip->frag, ip->where,
3379 ip->fixp[0]->fx_size, NULL, 0,
3380 FALSE, reloc_type[i]);
3382 /* Use fx_tcbit to mark compound relocs. */
3383 ip->fixp[0]->fx_tcbit = 1;
3384 ip->fixp[i]->fx_tcbit = 1;
3390 /* Update the register mask information. */
3391 if (! mips_opts.mips16)
3393 if ((pinfo & INSN_WRITE_GPR_D) || (pinfo2 & INSN2_READ_GPR_D))
3394 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
3395 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
3396 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
3397 if (pinfo & INSN_READ_GPR_S)
3398 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
3399 if (pinfo & INSN_WRITE_GPR_31)
3400 mips_gprmask |= 1 << RA;
3401 if (pinfo2 & (INSN2_WRITE_GPR_Z | INSN2_READ_GPR_Z))
3402 mips_gprmask |= 1 << EXTRACT_OPERAND (RZ, *ip);
3403 if (pinfo & INSN_WRITE_FPR_D)
3404 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
3405 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
3406 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
3407 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
3408 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
3409 if ((pinfo & INSN_READ_FPR_R) != 0)
3410 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
3411 if (pinfo2 & (INSN2_WRITE_FPR_Z | INSN2_READ_FPR_Z))
3412 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FZ, *ip);
3413 if (pinfo & INSN_COP)
3415 /* We don't keep enough information to sort these cases out.
3416 The itbl support does keep this information however, although
3417 we currently don't support itbl fprmats as part of the cop
3418 instruction. May want to add this support in the future. */
3420 /* Never set the bit for $0, which is always zero. */
3421 mips_gprmask &= ~1 << 0;
3425 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
3426 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
3427 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
3428 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
3429 if (pinfo & MIPS16_INSN_WRITE_Z)
3430 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
3431 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
3432 mips_gprmask |= 1 << TREG;
3433 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
3434 mips_gprmask |= 1 << SP;
3435 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
3436 mips_gprmask |= 1 << RA;
3437 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3438 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3439 if (pinfo & MIPS16_INSN_READ_Z)
3440 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
3441 if (pinfo & MIPS16_INSN_READ_GPR_X)
3442 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3445 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3447 /* Filling the branch delay slot is more complex. We try to
3448 switch the branch with the previous instruction, which we can
3449 do if the previous instruction does not set up a condition
3450 that the branch tests and if the branch is not itself the
3451 target of any branch. */
3452 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3453 || (pinfo & INSN_COND_BRANCH_DELAY))
3455 if (mips_optimize < 2
3456 /* If we have seen .set volatile or .set nomove, don't
3458 || mips_opts.nomove != 0
3459 /* We can't swap if the previous instruction's position
3461 || history[0].fixed_p
3462 /* If the previous previous insn was in a .set
3463 noreorder, we can't swap. Actually, the MIPS
3464 assembler will swap in this situation. However, gcc
3465 configured -with-gnu-as will generate code like
3471 in which we can not swap the bne and INSN. If gcc is
3472 not configured -with-gnu-as, it does not output the
3474 || history[1].noreorder_p
3475 /* If the branch is itself the target of a branch, we
3476 can not swap. We cheat on this; all we check for is
3477 whether there is a label on this instruction. If
3478 there are any branches to anything other than a
3479 label, users must use .set noreorder. */
3480 || si->label_list != NULL
3481 /* If the previous instruction is in a variant frag
3482 other than this branch's one, we cannot do the swap.
3483 This does not apply to the mips16, which uses variant
3484 frags for different purposes. */
3485 || (! mips_opts.mips16
3486 && prev_insn_frag_type == rs_machine_dependent)
3487 /* Check for conflicts between the branch and the instructions
3488 before the candidate delay slot. */
3489 || nops_for_insn (history + 1, ip) > 0
3490 /* Check for conflicts between the swapped sequence and the
3491 target of the branch. */
3492 || nops_for_sequence (2, history + 1, ip, history) > 0
3493 /* We do not swap with a trap instruction, since it
3494 complicates trap handlers to have the trap
3495 instruction be in a delay slot. */
3496 || (prev_pinfo & INSN_TRAP)
3497 /* If the branch reads a register that the previous
3498 instruction sets, we can not swap. */
3499 || (! mips_opts.mips16
3500 && (prev_pinfo & INSN_WRITE_GPR_T)
3501 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
3503 || (! mips_opts.mips16
3504 && (prev_pinfo & INSN_WRITE_GPR_D)
3505 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
3507 || (! mips_opts.mips16
3508 && (prev_pinfo2 & INSN2_WRITE_GPR_Z)
3509 && insn_uses_reg (ip, EXTRACT_OPERAND (RZ, history[0]),
3511 || (mips_opts.mips16
3512 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
3514 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
3516 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
3518 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
3520 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
3522 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
3524 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
3525 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
3526 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
3527 && insn_uses_reg (ip, RA, MIPS_GR_REG))
3528 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3529 && insn_uses_reg (ip,
3530 MIPS16OP_EXTRACT_REG32R
3531 (history[0].insn_opcode),
3533 /* If the branch writes a register that the previous
3534 instruction sets, we can not swap (we know that
3535 branches write only to RD or to $31). */
3536 || (! mips_opts.mips16
3537 && (prev_pinfo & INSN_WRITE_GPR_T)
3538 && (((pinfo & INSN_WRITE_GPR_D)
3539 && (EXTRACT_OPERAND (RT, history[0])
3540 == EXTRACT_OPERAND (RD, *ip)))
3541 || ((pinfo & INSN_WRITE_GPR_31)
3542 && EXTRACT_OPERAND (RT, history[0]) == RA)))
3543 || (! mips_opts.mips16
3544 && (prev_pinfo & INSN_WRITE_GPR_D)
3545 && (((pinfo & INSN_WRITE_GPR_D)
3546 && (EXTRACT_OPERAND (RD, history[0])
3547 == EXTRACT_OPERAND (RD, *ip)))
3548 || ((pinfo & INSN_WRITE_GPR_31)
3549 && EXTRACT_OPERAND (RD, history[0]) == RA)))
3550 || (mips_opts.mips16
3551 && (pinfo & MIPS16_INSN_WRITE_31)
3552 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
3553 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
3554 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
3556 /* If the branch writes a register that the previous
3557 instruction reads, we can not swap (we know that
3558 branches only write to RD or to $31). */
3559 || (! mips_opts.mips16
3560 && (pinfo & INSN_WRITE_GPR_D)
3561 && insn_uses_reg (&history[0],
3562 EXTRACT_OPERAND (RD, *ip),
3564 || (! mips_opts.mips16
3565 && (pinfo & INSN_WRITE_GPR_31)
3566 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3567 || (mips_opts.mips16
3568 && (pinfo & MIPS16_INSN_WRITE_31)
3569 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
3570 /* If one instruction sets a condition code and the
3571 other one uses a condition code, we can not swap. */
3572 || ((pinfo & INSN_READ_COND_CODE)
3573 && (prev_pinfo & INSN_WRITE_COND_CODE))
3574 || ((pinfo & INSN_WRITE_COND_CODE)
3575 && (prev_pinfo & INSN_READ_COND_CODE))
3576 /* If the previous instruction uses the PC, we can not
3578 || (mips_opts.mips16
3579 && (prev_pinfo & MIPS16_INSN_READ_PC))
3580 /* If the previous instruction had a fixup in mips16
3581 mode, we can not swap. This normally means that the
3582 previous instruction was a 4 byte branch anyhow. */
3583 || (mips_opts.mips16 && history[0].fixp[0])
3584 /* If the previous instruction is a sync, sync.l, or
3585 sync.p, we can not swap. */
3586 || (prev_pinfo & INSN_SYNC)
3587 /* If the previous instruction is an ERET or
3588 DERET, avoid the swap. */
3589 || (history[0].insn_opcode == INSN_ERET)
3590 || (history[0].insn_opcode == INSN_DERET))
3592 if (mips_opts.mips16
3593 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3594 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
3595 && ISA_SUPPORTS_MIPS16E)
3597 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3598 ip->insn_opcode |= 0x0080;
3600 insert_into_history (0, 1, ip);
3604 /* We could do even better for unconditional branches to
3605 portions of this object file; we could pick up the
3606 instruction at the destination, put it in the delay
3607 slot, and bump the destination address. */
3608 insert_into_history (0, 1, ip);
3612 if (mips_relax.sequence)
3613 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3617 /* It looks like we can actually do the swap. */
3618 struct mips_cl_insn delay = history[0];
3619 if (mips_opts.mips16)
3621 know (delay.frag == ip->frag);
3622 move_insn (ip, delay.frag, delay.where);
3623 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3625 else if (relaxed_branch)
3627 /* Add the delay slot instruction to the end of the
3628 current frag and shrink the fixed part of the
3629 original frag. If the branch occupies the tail of
3630 the latter, move it backwards to cover the gap. */
3631 delay.frag->fr_fix -= 4;
3632 if (delay.frag == ip->frag)
3633 move_insn (ip, ip->frag, ip->where - 4);
3634 add_fixed_insn (&delay);
3638 move_insn (&delay, ip->frag, ip->where);
3639 move_insn (ip, history[0].frag, history[0].where);
3643 insert_into_history (0, 1, &delay);
3646 /* If that was an unconditional branch, forget the previous
3647 insn information. */
3648 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
3650 mips_no_prev_insn ();
3653 else if (pinfo & INSN_COND_BRANCH_LIKELY)
3655 /* We don't yet optimize a branch likely. What we should do
3656 is look at the target, copy the instruction found there
3657 into the delay slot, and increment the branch to jump to
3658 the next instruction. */
3659 insert_into_history (0, 1, ip);
3663 insert_into_history (0, 1, ip);
3666 insert_into_history (0, 1, ip);
3668 /* We just output an insn, so the next one doesn't have a label. */
3669 mips_clear_insn_labels ();
3672 /* Forget that there was any previous instruction or label. */
3675 mips_no_prev_insn (void)
3677 prev_nop_frag = NULL;
3678 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3679 mips_clear_insn_labels ();
3682 /* This function must be called before we emit something other than
3683 instructions. It is like mips_no_prev_insn except that it inserts
3684 any NOPS that might be needed by previous instructions. */
3687 mips_emit_delays (void)
3689 if (! mips_opts.noreorder)
3691 int nops = nops_for_insn (history, NULL);
3695 add_fixed_insn (NOP_INSN);
3696 mips_move_labels ();
3699 mips_no_prev_insn ();
3702 /* Start a (possibly nested) noreorder block. */
3705 start_noreorder (void)
3707 if (mips_opts.noreorder == 0)
3712 /* None of the instructions before the .set noreorder can be moved. */
3713 for (i = 0; i < ARRAY_SIZE (history); i++)
3714 history[i].fixed_p = 1;
3716 /* Insert any nops that might be needed between the .set noreorder
3717 block and the previous instructions. We will later remove any
3718 nops that turn out not to be needed. */
3719 nops = nops_for_insn (history, NULL);
3722 if (mips_optimize != 0)
3724 /* Record the frag which holds the nop instructions, so
3725 that we can remove them if we don't need them. */
3726 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3727 prev_nop_frag = frag_now;
3728 prev_nop_frag_holds = nops;
3729 prev_nop_frag_required = 0;
3730 prev_nop_frag_since = 0;
3733 for (; nops > 0; --nops)
3734 add_fixed_insn (NOP_INSN);
3736 /* Move on to a new frag, so that it is safe to simply
3737 decrease the size of prev_nop_frag. */
3738 frag_wane (frag_now);
3740 mips_move_labels ();
3742 mips16_mark_labels ();
3743 mips_clear_insn_labels ();
3745 mips_opts.noreorder++;
3746 mips_any_noreorder = 1;
3749 /* End a nested noreorder block. */
3752 end_noreorder (void)
3755 mips_opts.noreorder--;
3756 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3758 /* Commit to inserting prev_nop_frag_required nops and go back to
3759 handling nop insertion the .set reorder way. */
3760 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3761 * (mips_opts.mips16 ? 2 : 4));
3762 insert_into_history (prev_nop_frag_since,
3763 prev_nop_frag_required, NOP_INSN);
3764 prev_nop_frag = NULL;
3768 /* Set up global variables for the start of a new macro. */
3773 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3774 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3775 && (history[0].insn_mo->pinfo
3776 & (INSN_UNCOND_BRANCH_DELAY
3777 | INSN_COND_BRANCH_DELAY
3778 | INSN_COND_BRANCH_LIKELY)) != 0);
3781 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3782 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3783 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3786 macro_warning (relax_substateT subtype)
3788 if (subtype & RELAX_DELAY_SLOT)
3789 return _("Macro instruction expanded into multiple instructions"
3790 " in a branch delay slot");
3791 else if (subtype & RELAX_NOMACRO)
3792 return _("Macro instruction expanded into multiple instructions");
3797 /* Finish up a macro. Emit warnings as appropriate. */
3802 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3804 relax_substateT subtype;
3806 /* Set up the relaxation warning flags. */
3808 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3809 subtype |= RELAX_SECOND_LONGER;
3810 if (mips_opts.warn_about_macros)
3811 subtype |= RELAX_NOMACRO;
3812 if (mips_macro_warning.delay_slot_p)
3813 subtype |= RELAX_DELAY_SLOT;
3815 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3817 /* Either the macro has a single implementation or both
3818 implementations are longer than 4 bytes. Emit the
3820 const char *msg = macro_warning (subtype);
3822 as_warn ("%s", msg);
3826 /* One implementation might need a warning but the other
3827 definitely doesn't. */
3828 mips_macro_warning.first_frag->fr_subtype |= subtype;
3833 /* Read a macro's relocation codes from *ARGS and store them in *R.
3834 The first argument in *ARGS will be either the code for a single
3835 relocation or -1 followed by the three codes that make up a
3836 composite relocation. */
3839 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3843 next = va_arg (*args, int);
3845 r[0] = (bfd_reloc_code_real_type) next;
3847 for (i = 0; i < 3; i++)
3848 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3851 /* Build an instruction created by a macro expansion. This is passed
3852 a pointer to the count of instructions created so far, an
3853 expression, the name of the instruction to build, an operand format
3854 string, and corresponding arguments. */
3857 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3859 const struct mips_opcode *mo;
3860 struct mips_cl_insn insn;
3861 bfd_reloc_code_real_type r[3];
3864 va_start (args, fmt);
3866 if (mips_opts.mips16)
3868 mips16_macro_build (ep, name, fmt, &args);
3873 r[0] = BFD_RELOC_UNUSED;
3874 r[1] = BFD_RELOC_UNUSED;
3875 r[2] = BFD_RELOC_UNUSED;
3876 mo = (struct mips_opcode *) hash_find (op_hash, name);
3878 gas_assert (strcmp (name, mo->name) == 0);
3882 /* Search until we get a match for NAME. It is assumed here that
3883 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3884 if (strcmp (fmt, mo->args) == 0
3885 && mo->pinfo != INSN_MACRO
3886 && is_opcode_valid (mo))
3890 gas_assert (mo->name);
3891 gas_assert (strcmp (name, mo->name) == 0);
3894 create_insn (&insn, mo);
3912 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3917 /* Note that in the macro case, these arguments are already
3918 in MSB form. (When handling the instruction in the
3919 non-macro case, these arguments are sizes from which
3920 MSB values must be calculated.) */
3921 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3927 /* Note that in the macro case, these arguments are already
3928 in MSBD form. (When handling the instruction in the
3929 non-macro case, these arguments are sizes from which
3930 MSBD values must be calculated.) */
3931 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3935 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3944 INSERT_OPERAND (BP, insn, va_arg (args, int));
3950 INSERT_OPERAND (RT, insn, va_arg (args, int));
3954 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3959 INSERT_OPERAND (FT, insn, va_arg (args, int));
3965 INSERT_OPERAND (RD, insn, va_arg (args, int));
3970 int tmp = va_arg (args, int);
3972 INSERT_OPERAND (RT, insn, tmp);
3973 INSERT_OPERAND (RD, insn, tmp);
3979 INSERT_OPERAND (FS, insn, va_arg (args, int));
3986 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3990 INSERT_OPERAND (FD, insn, va_arg (args, int));
3994 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3998 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4002 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4009 INSERT_OPERAND (RS, insn, va_arg (args, int));
4014 macro_read_relocs (&args, r);
4015 gas_assert (*r == BFD_RELOC_GPREL16
4016 || *r == BFD_RELOC_MIPS_HIGHER
4017 || *r == BFD_RELOC_HI16_S
4018 || *r == BFD_RELOC_LO16
4019 || *r == BFD_RELOC_MIPS_GOT_OFST);
4023 macro_read_relocs (&args, r);
4027 macro_read_relocs (&args, r);
4028 gas_assert (ep != NULL
4029 && (ep->X_op == O_constant
4030 || (ep->X_op == O_symbol
4031 && (*r == BFD_RELOC_MIPS_HIGHEST
4032 || *r == BFD_RELOC_HI16_S
4033 || *r == BFD_RELOC_HI16
4034 || *r == BFD_RELOC_GPREL16
4035 || *r == BFD_RELOC_MIPS_GOT_HI16
4036 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4040 gas_assert (ep != NULL);
4043 * This allows macro() to pass an immediate expression for
4044 * creating short branches without creating a symbol.
4046 * We don't allow branch relaxation for these branches, as
4047 * they should only appear in ".set nomacro" anyway.
4049 if (ep->X_op == O_constant)
4051 if ((ep->X_add_number & 3) != 0)
4052 as_bad (_("branch to misaligned address (0x%lx)"),
4053 (unsigned long) ep->X_add_number);
4054 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4055 as_bad (_("branch address range overflow (0x%lx)"),
4056 (unsigned long) ep->X_add_number);
4057 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4061 *r = BFD_RELOC_16_PCREL_S2;
4065 gas_assert (ep != NULL);
4066 *r = BFD_RELOC_MIPS_JMP;
4070 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4074 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4083 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4085 append_insn (&insn, ep, r);
4089 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4092 struct mips_opcode *mo;
4093 struct mips_cl_insn insn;
4094 bfd_reloc_code_real_type r[3]
4095 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4097 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4099 gas_assert (strcmp (name, mo->name) == 0);
4101 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4104 gas_assert (mo->name);
4105 gas_assert (strcmp (name, mo->name) == 0);
4108 create_insn (&insn, mo);
4126 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4131 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4135 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4139 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4149 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4156 regno = va_arg (*args, int);
4157 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4158 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4179 gas_assert (ep != NULL);
4181 if (ep->X_op != O_constant)
4182 *r = (int) BFD_RELOC_UNUSED + c;
4185 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4186 FALSE, &insn.insn_opcode, &insn.use_extend,
4189 *r = BFD_RELOC_UNUSED;
4195 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4202 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4204 append_insn (&insn, ep, r);
4208 * Sign-extend 32-bit mode constants that have bit 31 set and all
4209 * higher bits unset.
4212 normalize_constant_expr (expressionS *ex)
4214 if (ex->X_op == O_constant
4215 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4216 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4221 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4222 * all higher bits unset.
4225 normalize_address_expr (expressionS *ex)
4227 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4228 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4229 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4230 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4235 * Generate a "jalr" instruction with a relocation hint to the called
4236 * function. This occurs in NewABI PIC code.
4239 macro_build_jalr (expressionS *ep)
4243 if (MIPS_JALR_HINT_P (ep))
4248 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4249 if (MIPS_JALR_HINT_P (ep))
4250 fix_new_exp (frag_now, f - frag_now->fr_literal,
4251 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4255 * Generate a "lui" instruction.
4258 macro_build_lui (expressionS *ep, int regnum)
4260 expressionS high_expr;
4261 const struct mips_opcode *mo;
4262 struct mips_cl_insn insn;
4263 bfd_reloc_code_real_type r[3]
4264 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4265 const char *name = "lui";
4266 const char *fmt = "t,u";
4268 gas_assert (! mips_opts.mips16);
4272 if (high_expr.X_op == O_constant)
4274 /* We can compute the instruction now without a relocation entry. */
4275 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4277 *r = BFD_RELOC_UNUSED;
4281 gas_assert (ep->X_op == O_symbol);
4282 /* _gp_disp is a special case, used from s_cpload.
4283 __gnu_local_gp is used if mips_no_shared. */
4284 gas_assert (mips_pic == NO_PIC
4286 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4287 || (! mips_in_shared
4288 && strcmp (S_GET_NAME (ep->X_add_symbol),
4289 "__gnu_local_gp") == 0));
4290 *r = BFD_RELOC_HI16_S;
4293 mo = hash_find (op_hash, name);
4294 gas_assert (strcmp (name, mo->name) == 0);
4295 gas_assert (strcmp (fmt, mo->args) == 0);
4296 create_insn (&insn, mo);
4298 insn.insn_opcode = insn.insn_mo->match;
4299 INSERT_OPERAND (RT, insn, regnum);
4300 if (*r == BFD_RELOC_UNUSED)
4302 insn.insn_opcode |= high_expr.X_add_number;
4303 append_insn (&insn, NULL, r);
4306 append_insn (&insn, &high_expr, r);
4309 /* Generate a sequence of instructions to do a load or store from a constant
4310 offset off of a base register (breg) into/from a target register (treg),
4311 using AT if necessary. */
4313 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4314 int treg, int breg, int dbl)
4316 gas_assert (ep->X_op == O_constant);
4318 /* Sign-extending 32-bit constants makes their handling easier. */
4320 normalize_constant_expr (ep);
4322 /* Right now, this routine can only handle signed 32-bit constants. */
4323 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4324 as_warn (_("operand overflow"));
4326 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4328 /* Signed 16-bit offset will fit in the op. Easy! */
4329 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4333 /* 32-bit offset, need multiple instructions and AT, like:
4334 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4335 addu $tempreg,$tempreg,$breg
4336 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4337 to handle the complete offset. */
4338 macro_build_lui (ep, AT);
4339 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4340 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4343 as_bad (_("Macro used $at after \".set noat\""));
4348 * Generates code to set the $at register to true (one)
4349 * if reg is less than the immediate expression.
4352 set_at (int reg, int unsignedp)
4354 if (imm_expr.X_op == O_constant
4355 && imm_expr.X_add_number >= -0x8000
4356 && imm_expr.X_add_number < 0x8000)
4357 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4358 AT, reg, BFD_RELOC_LO16);
4361 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4362 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4366 /* Warn if an expression is not a constant. */
4369 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4371 if (ex->X_op == O_big)
4372 as_bad (_("unsupported large constant"));
4373 else if (ex->X_op != O_constant)
4374 as_bad (_("Instruction %s requires absolute expression"),
4377 if (HAVE_32BIT_GPRS)
4378 normalize_constant_expr (ex);
4381 /* Count the leading zeroes by performing a binary chop. This is a
4382 bulky bit of source, but performance is a LOT better for the
4383 majority of values than a simple loop to count the bits:
4384 for (lcnt = 0; (lcnt < 32); lcnt++)
4385 if ((v) & (1 << (31 - lcnt)))
4387 However it is not code size friendly, and the gain will drop a bit
4388 on certain cached systems.
4390 #define COUNT_TOP_ZEROES(v) \
4391 (((v) & ~0xffff) == 0 \
4392 ? ((v) & ~0xff) == 0 \
4393 ? ((v) & ~0xf) == 0 \
4394 ? ((v) & ~0x3) == 0 \
4395 ? ((v) & ~0x1) == 0 \
4400 : ((v) & ~0x7) == 0 \
4403 : ((v) & ~0x3f) == 0 \
4404 ? ((v) & ~0x1f) == 0 \
4407 : ((v) & ~0x7f) == 0 \
4410 : ((v) & ~0xfff) == 0 \
4411 ? ((v) & ~0x3ff) == 0 \
4412 ? ((v) & ~0x1ff) == 0 \
4415 : ((v) & ~0x7ff) == 0 \
4418 : ((v) & ~0x3fff) == 0 \
4419 ? ((v) & ~0x1fff) == 0 \
4422 : ((v) & ~0x7fff) == 0 \
4425 : ((v) & ~0xffffff) == 0 \
4426 ? ((v) & ~0xfffff) == 0 \
4427 ? ((v) & ~0x3ffff) == 0 \
4428 ? ((v) & ~0x1ffff) == 0 \
4431 : ((v) & ~0x7ffff) == 0 \
4434 : ((v) & ~0x3fffff) == 0 \
4435 ? ((v) & ~0x1fffff) == 0 \
4438 : ((v) & ~0x7fffff) == 0 \
4441 : ((v) & ~0xfffffff) == 0 \
4442 ? ((v) & ~0x3ffffff) == 0 \
4443 ? ((v) & ~0x1ffffff) == 0 \
4446 : ((v) & ~0x7ffffff) == 0 \
4449 : ((v) & ~0x3fffffff) == 0 \
4450 ? ((v) & ~0x1fffffff) == 0 \
4453 : ((v) & ~0x7fffffff) == 0 \
4458 * This routine generates the least number of instructions necessary to load
4459 * an absolute expression value into a register.
4462 load_register (int reg, expressionS *ep, int dbl)
4465 expressionS hi32, lo32;
4467 if (ep->X_op != O_big)
4469 gas_assert (ep->X_op == O_constant);
4471 /* Sign-extending 32-bit constants makes their handling easier. */
4473 normalize_constant_expr (ep);
4475 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4477 /* We can handle 16 bit signed values with an addiu to
4478 $zero. No need to ever use daddiu here, since $zero and
4479 the result are always correct in 32 bit mode. */
4480 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4483 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4485 /* We can handle 16 bit unsigned values with an ori to
4487 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4490 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4492 /* 32 bit values require an lui. */
4493 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4494 if ((ep->X_add_number & 0xffff) != 0)
4495 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4500 /* The value is larger than 32 bits. */
4502 if (!dbl || HAVE_32BIT_GPRS)
4506 sprintf_vma (value, ep->X_add_number);
4507 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4508 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4512 if (ep->X_op != O_big)
4515 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4516 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4517 hi32.X_add_number &= 0xffffffff;
4519 lo32.X_add_number &= 0xffffffff;
4523 gas_assert (ep->X_add_number > 2);
4524 if (ep->X_add_number == 3)
4525 generic_bignum[3] = 0;
4526 else if (ep->X_add_number > 4)
4527 as_bad (_("Number larger than 64 bits"));
4528 lo32.X_op = O_constant;
4529 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4530 hi32.X_op = O_constant;
4531 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4534 if (hi32.X_add_number == 0)
4539 unsigned long hi, lo;
4541 if (hi32.X_add_number == (offsetT) 0xffffffff)
4543 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4545 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4548 if (lo32.X_add_number & 0x80000000)
4550 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4551 if (lo32.X_add_number & 0xffff)
4552 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4557 /* Check for 16bit shifted constant. We know that hi32 is
4558 non-zero, so start the mask on the first bit of the hi32
4563 unsigned long himask, lomask;
4567 himask = 0xffff >> (32 - shift);
4568 lomask = (0xffff << shift) & 0xffffffff;
4572 himask = 0xffff << (shift - 32);
4575 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4576 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4580 tmp.X_op = O_constant;
4582 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4583 | (lo32.X_add_number >> shift));
4585 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4586 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4587 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4588 reg, reg, (shift >= 32) ? shift - 32 : shift);
4593 while (shift <= (64 - 16));
4595 /* Find the bit number of the lowest one bit, and store the
4596 shifted value in hi/lo. */
4597 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4598 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4602 while ((lo & 1) == 0)
4607 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4613 while ((hi & 1) == 0)
4622 /* Optimize if the shifted value is a (power of 2) - 1. */
4623 if ((hi == 0 && ((lo + 1) & lo) == 0)
4624 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4626 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4631 /* This instruction will set the register to be all
4633 tmp.X_op = O_constant;
4634 tmp.X_add_number = (offsetT) -1;
4635 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4639 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4640 reg, reg, (bit >= 32) ? bit - 32 : bit);
4642 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4643 reg, reg, (shift >= 32) ? shift - 32 : shift);
4648 /* Sign extend hi32 before calling load_register, because we can
4649 generally get better code when we load a sign extended value. */
4650 if ((hi32.X_add_number & 0x80000000) != 0)
4651 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4652 load_register (reg, &hi32, 0);
4655 if ((lo32.X_add_number & 0xffff0000) == 0)
4659 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4667 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4669 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4670 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4676 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4680 mid16.X_add_number >>= 16;
4681 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4682 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4685 if ((lo32.X_add_number & 0xffff) != 0)
4686 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4690 load_delay_nop (void)
4692 if (!gpr_interlocks)
4693 macro_build (NULL, "nop", "");
4696 /* Load an address into a register. */
4699 load_address (int reg, expressionS *ep, int *used_at)
4701 if (ep->X_op != O_constant
4702 && ep->X_op != O_symbol)
4704 as_bad (_("expression too complex"));
4705 ep->X_op = O_constant;
4708 if (ep->X_op == O_constant)
4710 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4714 if (mips_pic == NO_PIC)
4716 /* If this is a reference to a GP relative symbol, we want
4717 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4719 lui $reg,<sym> (BFD_RELOC_HI16_S)
4720 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4721 If we have an addend, we always use the latter form.
4723 With 64bit address space and a usable $at we want
4724 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4725 lui $at,<sym> (BFD_RELOC_HI16_S)
4726 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4727 daddiu $at,<sym> (BFD_RELOC_LO16)
4731 If $at is already in use, we use a path which is suboptimal
4732 on superscalar processors.
4733 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4734 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4736 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4738 daddiu $reg,<sym> (BFD_RELOC_LO16)
4740 For GP relative symbols in 64bit address space we can use
4741 the same sequence as in 32bit address space. */
4742 if (HAVE_64BIT_SYMBOLS)
4744 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4745 && !nopic_need_relax (ep->X_add_symbol, 1))
4747 relax_start (ep->X_add_symbol);
4748 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4749 mips_gp_register, BFD_RELOC_GPREL16);
4753 if (*used_at == 0 && mips_opts.at)
4755 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4756 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4757 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4758 BFD_RELOC_MIPS_HIGHER);
4759 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4760 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4761 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4766 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4767 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4768 BFD_RELOC_MIPS_HIGHER);
4769 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4770 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4771 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4772 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4775 if (mips_relax.sequence)
4780 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4781 && !nopic_need_relax (ep->X_add_symbol, 1))
4783 relax_start (ep->X_add_symbol);
4784 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4785 mips_gp_register, BFD_RELOC_GPREL16);
4788 macro_build_lui (ep, reg);
4789 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4790 reg, reg, BFD_RELOC_LO16);
4791 if (mips_relax.sequence)
4795 else if (!mips_big_got)
4799 /* If this is a reference to an external symbol, we want
4800 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4802 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4804 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4805 If there is a constant, it must be added in after.
4807 If we have NewABI, we want
4808 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4809 unless we're referencing a global symbol with a non-zero
4810 offset, in which case cst must be added separately. */
4813 if (ep->X_add_number)
4815 ex.X_add_number = ep->X_add_number;
4816 ep->X_add_number = 0;
4817 relax_start (ep->X_add_symbol);
4818 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4819 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4820 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4821 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4822 ex.X_op = O_constant;
4823 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4824 reg, reg, BFD_RELOC_LO16);
4825 ep->X_add_number = ex.X_add_number;
4828 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4829 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4830 if (mips_relax.sequence)
4835 ex.X_add_number = ep->X_add_number;
4836 ep->X_add_number = 0;
4837 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4838 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4840 relax_start (ep->X_add_symbol);
4842 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4846 if (ex.X_add_number != 0)
4848 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4849 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4850 ex.X_op = O_constant;
4851 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4852 reg, reg, BFD_RELOC_LO16);
4856 else if (mips_big_got)
4860 /* This is the large GOT case. If this is a reference to an
4861 external symbol, we want
4862 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4864 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4866 Otherwise, for a reference to a local symbol in old ABI, we want
4867 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4869 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4870 If there is a constant, it must be added in after.
4872 In the NewABI, for local symbols, with or without offsets, we want:
4873 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4874 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4878 ex.X_add_number = ep->X_add_number;
4879 ep->X_add_number = 0;
4880 relax_start (ep->X_add_symbol);
4881 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4882 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4883 reg, reg, mips_gp_register);
4884 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4885 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4886 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4888 else if (ex.X_add_number)
4890 ex.X_op = O_constant;
4891 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4895 ep->X_add_number = ex.X_add_number;
4897 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4898 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4899 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4900 BFD_RELOC_MIPS_GOT_OFST);
4905 ex.X_add_number = ep->X_add_number;
4906 ep->X_add_number = 0;
4907 relax_start (ep->X_add_symbol);
4908 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4909 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4910 reg, reg, mips_gp_register);
4911 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4912 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4914 if (reg_needs_delay (mips_gp_register))
4916 /* We need a nop before loading from $gp. This special
4917 check is required because the lui which starts the main
4918 instruction stream does not refer to $gp, and so will not
4919 insert the nop which may be required. */
4920 macro_build (NULL, "nop", "");
4922 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4923 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4925 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4929 if (ex.X_add_number != 0)
4931 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4932 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4933 ex.X_op = O_constant;
4934 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4942 if (!mips_opts.at && *used_at == 1)
4943 as_bad (_("Macro used $at after \".set noat\""));
4946 /* Move the contents of register SOURCE into register DEST. */
4949 move_register (int dest, int source)
4951 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4955 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4956 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4957 The two alternatives are:
4959 Global symbol Local sybmol
4960 ------------- ------------
4961 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4963 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4965 load_got_offset emits the first instruction and add_got_offset
4966 emits the second for a 16-bit offset or add_got_offset_hilo emits
4967 a sequence to add a 32-bit offset using a scratch register. */
4970 load_got_offset (int dest, expressionS *local)
4975 global.X_add_number = 0;
4977 relax_start (local->X_add_symbol);
4978 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4979 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4981 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4982 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4987 add_got_offset (int dest, expressionS *local)
4991 global.X_op = O_constant;
4992 global.X_op_symbol = NULL;
4993 global.X_add_symbol = NULL;
4994 global.X_add_number = local->X_add_number;
4996 relax_start (local->X_add_symbol);
4997 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4998 dest, dest, BFD_RELOC_LO16);
5000 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5005 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5008 int hold_mips_optimize;
5010 global.X_op = O_constant;
5011 global.X_op_symbol = NULL;
5012 global.X_add_symbol = NULL;
5013 global.X_add_number = local->X_add_number;
5015 relax_start (local->X_add_symbol);
5016 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5018 /* Set mips_optimize around the lui instruction to avoid
5019 inserting an unnecessary nop after the lw. */
5020 hold_mips_optimize = mips_optimize;
5022 macro_build_lui (&global, tmp);
5023 mips_optimize = hold_mips_optimize;
5024 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5027 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5032 * This routine implements the seemingly endless macro or synthesized
5033 * instructions and addressing modes in the mips assembly language. Many
5034 * of these macros are simple and are similar to each other. These could
5035 * probably be handled by some kind of table or grammar approach instead of
5036 * this verbose method. Others are not simple macros but are more like
5037 * optimizing code generation.
5038 * One interesting optimization is when several store macros appear
5039 * consecutively that would load AT with the upper half of the same address.
5040 * The ensuing load upper instructions are ommited. This implies some kind
5041 * of global optimization. We currently only optimize within a single macro.
5042 * For many of the load and store macros if the address is specified as a
5043 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5044 * first load register 'at' with zero and use it as the base register. The
5045 * mips assembler simply uses register $zero. Just one tiny optimization
5049 macro (struct mips_cl_insn *ip)
5051 unsigned int treg, sreg, dreg, breg;
5052 unsigned int tempreg;
5067 bfd_reloc_code_real_type r;
5068 int hold_mips_optimize;
5070 gas_assert (! mips_opts.mips16);
5072 treg = EXTRACT_OPERAND (RT, *ip);
5073 dreg = EXTRACT_OPERAND (RD, *ip);
5074 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5075 mask = ip->insn_mo->mask;
5077 expr1.X_op = O_constant;
5078 expr1.X_op_symbol = NULL;
5079 expr1.X_add_symbol = NULL;
5080 expr1.X_add_number = 1;
5094 expr1.X_add_number = 8;
5095 macro_build (&expr1, "bgez", "s,p", sreg);
5097 macro_build (NULL, "nop", "");
5099 move_register (dreg, sreg);
5100 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5123 if (imm_expr.X_op == O_constant
5124 && imm_expr.X_add_number >= -0x8000
5125 && imm_expr.X_add_number < 0x8000)
5127 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5131 load_register (AT, &imm_expr, dbl);
5132 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5151 if (imm_expr.X_op == O_constant
5152 && imm_expr.X_add_number >= 0
5153 && imm_expr.X_add_number < 0x10000)
5155 if (mask != M_NOR_I)
5156 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5159 macro_build (&imm_expr, "ori", "t,r,i",
5160 treg, sreg, BFD_RELOC_LO16);
5161 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5167 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5168 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5172 switch (imm_expr.X_add_number)
5175 macro_build (NULL, "nop", "");
5178 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5181 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5182 (int) imm_expr.X_add_number);
5201 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5203 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5207 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5208 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5216 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5221 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5225 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5226 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5232 /* Check for > max integer. */
5233 maxnum = 0x7fffffff;
5234 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5241 if (imm_expr.X_op == O_constant
5242 && imm_expr.X_add_number >= maxnum
5243 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5246 /* Result is always false. */
5248 macro_build (NULL, "nop", "");
5250 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5253 if (imm_expr.X_op != O_constant)
5254 as_bad (_("Unsupported large constant"));
5255 ++imm_expr.X_add_number;
5259 if (mask == M_BGEL_I)
5261 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5263 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5266 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5268 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5271 maxnum = 0x7fffffff;
5272 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5279 maxnum = - maxnum - 1;
5280 if (imm_expr.X_op == O_constant
5281 && imm_expr.X_add_number <= maxnum
5282 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5285 /* result is always true */
5286 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5287 macro_build (&offset_expr, "b", "p");
5292 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5302 macro_build (&offset_expr, likely ? "beql" : "beq",
5303 "s,t,p", ZERO, treg);
5307 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5308 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5316 && imm_expr.X_op == O_constant
5317 && imm_expr.X_add_number == -1))
5319 if (imm_expr.X_op != O_constant)
5320 as_bad (_("Unsupported large constant"));
5321 ++imm_expr.X_add_number;
5325 if (mask == M_BGEUL_I)
5327 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5329 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5331 macro_build (&offset_expr, likely ? "bnel" : "bne",
5332 "s,t,p", sreg, ZERO);
5337 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5345 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5350 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5354 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5355 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5363 macro_build (&offset_expr, likely ? "bnel" : "bne",
5364 "s,t,p", sreg, ZERO);
5370 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5371 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5379 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5384 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5388 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5389 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5395 maxnum = 0x7fffffff;
5396 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5403 if (imm_expr.X_op == O_constant
5404 && imm_expr.X_add_number >= maxnum
5405 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5407 if (imm_expr.X_op != O_constant)
5408 as_bad (_("Unsupported large constant"));
5409 ++imm_expr.X_add_number;
5413 if (mask == M_BLTL_I)
5415 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5417 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5420 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5422 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5427 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5435 macro_build (&offset_expr, likely ? "beql" : "beq",
5436 "s,t,p", sreg, ZERO);
5442 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5443 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5451 && imm_expr.X_op == O_constant
5452 && imm_expr.X_add_number == -1))
5454 if (imm_expr.X_op != O_constant)
5455 as_bad (_("Unsupported large constant"));
5456 ++imm_expr.X_add_number;
5460 if (mask == M_BLTUL_I)
5462 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5464 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5466 macro_build (&offset_expr, likely ? "beql" : "beq",
5467 "s,t,p", sreg, ZERO);
5472 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5480 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5485 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5489 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5490 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5500 macro_build (&offset_expr, likely ? "bnel" : "bne",
5501 "s,t,p", ZERO, treg);
5505 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5506 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5511 /* Use unsigned arithmetic. */
5515 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5517 as_bad (_("Unsupported large constant"));
5522 pos = imm_expr.X_add_number;
5523 size = imm2_expr.X_add_number;
5528 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5531 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5533 as_bad (_("Improper extract size (%lu, position %lu)"),
5534 (unsigned long) size, (unsigned long) pos);
5538 if (size <= 32 && pos < 32)
5543 else if (size <= 32)
5553 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5560 /* Use unsigned arithmetic. */
5564 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5566 as_bad (_("Unsupported large constant"));
5571 pos = imm_expr.X_add_number;
5572 size = imm2_expr.X_add_number;
5577 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5580 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5582 as_bad (_("Improper insert size (%lu, position %lu)"),
5583 (unsigned long) size, (unsigned long) pos);
5587 if (pos < 32 && (pos + size - 1) < 32)
5602 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5603 (int) (pos + size - 1));
5619 as_warn (_("Divide by zero."));
5621 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5623 macro_build (NULL, "break", "c", 7);
5630 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5631 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5635 expr1.X_add_number = 8;
5636 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5637 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5638 macro_build (NULL, "break", "c", 7);
5640 expr1.X_add_number = -1;
5642 load_register (AT, &expr1, dbl);
5643 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5644 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5647 expr1.X_add_number = 1;
5648 load_register (AT, &expr1, dbl);
5649 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5653 expr1.X_add_number = 0x80000000;
5654 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5658 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5659 /* We want to close the noreorder block as soon as possible, so
5660 that later insns are available for delay slot filling. */
5665 expr1.X_add_number = 8;
5666 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5667 macro_build (NULL, "nop", "");
5669 /* We want to close the noreorder block as soon as possible, so
5670 that later insns are available for delay slot filling. */
5673 macro_build (NULL, "break", "c", 6);
5675 macro_build (NULL, s, "d", dreg);
5714 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5716 as_warn (_("Divide by zero."));
5718 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5720 macro_build (NULL, "break", "c", 7);
5723 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5725 if (strcmp (s2, "mflo") == 0)
5726 move_register (dreg, sreg);
5728 move_register (dreg, ZERO);
5731 if (imm_expr.X_op == O_constant
5732 && imm_expr.X_add_number == -1
5733 && s[strlen (s) - 1] != 'u')
5735 if (strcmp (s2, "mflo") == 0)
5737 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5740 move_register (dreg, ZERO);
5745 load_register (AT, &imm_expr, dbl);
5746 macro_build (NULL, s, "z,s,t", sreg, AT);
5747 macro_build (NULL, s2, "d", dreg);
5769 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5770 macro_build (NULL, s, "z,s,t", sreg, treg);
5771 /* We want to close the noreorder block as soon as possible, so
5772 that later insns are available for delay slot filling. */
5777 expr1.X_add_number = 8;
5778 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5779 macro_build (NULL, s, "z,s,t", sreg, treg);
5781 /* We want to close the noreorder block as soon as possible, so
5782 that later insns are available for delay slot filling. */
5784 macro_build (NULL, "break", "c", 7);
5786 macro_build (NULL, s2, "d", dreg);
5798 /* Load the address of a symbol into a register. If breg is not
5799 zero, we then add a base register to it. */
5801 if (dbl && HAVE_32BIT_GPRS)
5802 as_warn (_("dla used to load 32-bit register"));
5804 if (!dbl && HAVE_64BIT_OBJECTS)
5805 as_warn (_("la used to load 64-bit address"));
5807 if (offset_expr.X_op == O_constant
5808 && offset_expr.X_add_number >= -0x8000
5809 && offset_expr.X_add_number < 0x8000)
5811 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5812 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5816 if (mips_opts.at && (treg == breg))
5826 if (offset_expr.X_op != O_symbol
5827 && offset_expr.X_op != O_constant)
5829 as_bad (_("Expression too complex"));
5830 offset_expr.X_op = O_constant;
5833 if (offset_expr.X_op == O_constant)
5834 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5835 else if (mips_pic == NO_PIC)
5837 /* If this is a reference to a GP relative symbol, we want
5838 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5840 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5841 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5842 If we have a constant, we need two instructions anyhow,
5843 so we may as well always use the latter form.
5845 With 64bit address space and a usable $at we want
5846 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5847 lui $at,<sym> (BFD_RELOC_HI16_S)
5848 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5849 daddiu $at,<sym> (BFD_RELOC_LO16)
5851 daddu $tempreg,$tempreg,$at
5853 If $at is already in use, we use a path which is suboptimal
5854 on superscalar processors.
5855 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5856 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5858 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5860 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5862 For GP relative symbols in 64bit address space we can use
5863 the same sequence as in 32bit address space. */
5864 if (HAVE_64BIT_SYMBOLS)
5866 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5867 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5869 relax_start (offset_expr.X_add_symbol);
5870 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5871 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5875 if (used_at == 0 && mips_opts.at)
5877 macro_build (&offset_expr, "lui", "t,u",
5878 tempreg, BFD_RELOC_MIPS_HIGHEST);
5879 macro_build (&offset_expr, "lui", "t,u",
5880 AT, BFD_RELOC_HI16_S);
5881 macro_build (&offset_expr, "daddiu", "t,r,j",
5882 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5883 macro_build (&offset_expr, "daddiu", "t,r,j",
5884 AT, AT, BFD_RELOC_LO16);
5885 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5886 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5891 macro_build (&offset_expr, "lui", "t,u",
5892 tempreg, BFD_RELOC_MIPS_HIGHEST);
5893 macro_build (&offset_expr, "daddiu", "t,r,j",
5894 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5895 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5896 macro_build (&offset_expr, "daddiu", "t,r,j",
5897 tempreg, tempreg, BFD_RELOC_HI16_S);
5898 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5899 macro_build (&offset_expr, "daddiu", "t,r,j",
5900 tempreg, tempreg, BFD_RELOC_LO16);
5903 if (mips_relax.sequence)
5908 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5909 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5911 relax_start (offset_expr.X_add_symbol);
5912 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5913 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5916 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5917 as_bad (_("Offset too large"));
5918 macro_build_lui (&offset_expr, tempreg);
5919 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5920 tempreg, tempreg, BFD_RELOC_LO16);
5921 if (mips_relax.sequence)
5925 else if (!mips_big_got && !HAVE_NEWABI)
5927 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5929 /* If this is a reference to an external symbol, and there
5930 is no constant, we want
5931 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5932 or for lca or if tempreg is PIC_CALL_REG
5933 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5934 For a local symbol, we want
5935 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5937 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5939 If we have a small constant, and this is a reference to
5940 an external symbol, we want
5941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5943 addiu $tempreg,$tempreg,<constant>
5944 For a local symbol, we want the same instruction
5945 sequence, but we output a BFD_RELOC_LO16 reloc on the
5948 If we have a large constant, and this is a reference to
5949 an external symbol, we want
5950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5951 lui $at,<hiconstant>
5952 addiu $at,$at,<loconstant>
5953 addu $tempreg,$tempreg,$at
5954 For a local symbol, we want the same instruction
5955 sequence, but we output a BFD_RELOC_LO16 reloc on the
5959 if (offset_expr.X_add_number == 0)
5961 if (mips_pic == SVR4_PIC
5963 && (call || tempreg == PIC_CALL_REG))
5964 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5966 relax_start (offset_expr.X_add_symbol);
5967 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5968 lw_reloc_type, mips_gp_register);
5971 /* We're going to put in an addu instruction using
5972 tempreg, so we may as well insert the nop right
5977 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5978 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5980 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5981 tempreg, tempreg, BFD_RELOC_LO16);
5983 /* FIXME: If breg == 0, and the next instruction uses
5984 $tempreg, then if this variant case is used an extra
5985 nop will be generated. */
5987 else if (offset_expr.X_add_number >= -0x8000
5988 && offset_expr.X_add_number < 0x8000)
5990 load_got_offset (tempreg, &offset_expr);
5992 add_got_offset (tempreg, &offset_expr);
5996 expr1.X_add_number = offset_expr.X_add_number;
5997 offset_expr.X_add_number =
5998 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5999 load_got_offset (tempreg, &offset_expr);
6000 offset_expr.X_add_number = expr1.X_add_number;
6001 /* If we are going to add in a base register, and the
6002 target register and the base register are the same,
6003 then we are using AT as a temporary register. Since
6004 we want to load the constant into AT, we add our
6005 current AT (from the global offset table) and the
6006 register into the register now, and pretend we were
6007 not using a base register. */
6011 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6016 add_got_offset_hilo (tempreg, &offset_expr, AT);
6020 else if (!mips_big_got && HAVE_NEWABI)
6022 int add_breg_early = 0;
6024 /* If this is a reference to an external, and there is no
6025 constant, or local symbol (*), with or without a
6027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6028 or for lca or if tempreg is PIC_CALL_REG
6029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6031 If we have a small constant, and this is a reference to
6032 an external symbol, we want
6033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6034 addiu $tempreg,$tempreg,<constant>
6036 If we have a large constant, and this is a reference to
6037 an external symbol, we want
6038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6039 lui $at,<hiconstant>
6040 addiu $at,$at,<loconstant>
6041 addu $tempreg,$tempreg,$at
6043 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6044 local symbols, even though it introduces an additional
6047 if (offset_expr.X_add_number)
6049 expr1.X_add_number = offset_expr.X_add_number;
6050 offset_expr.X_add_number = 0;
6052 relax_start (offset_expr.X_add_symbol);
6053 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6054 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6056 if (expr1.X_add_number >= -0x8000
6057 && expr1.X_add_number < 0x8000)
6059 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6060 tempreg, tempreg, BFD_RELOC_LO16);
6062 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6064 /* If we are going to add in a base register, and the
6065 target register and the base register are the same,
6066 then we are using AT as a temporary register. Since
6067 we want to load the constant into AT, we add our
6068 current AT (from the global offset table) and the
6069 register into the register now, and pretend we were
6070 not using a base register. */
6075 gas_assert (tempreg == AT);
6076 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6082 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6089 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6092 offset_expr.X_add_number = expr1.X_add_number;
6094 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6095 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6098 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6099 treg, tempreg, breg);
6105 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6107 relax_start (offset_expr.X_add_symbol);
6108 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6109 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6111 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6112 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6118 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6121 else if (mips_big_got && !HAVE_NEWABI)
6124 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6125 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6126 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6128 /* This is the large GOT case. If this is a reference to an
6129 external symbol, and there is no constant, we want
6130 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6131 addu $tempreg,$tempreg,$gp
6132 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6133 or for lca or if tempreg is PIC_CALL_REG
6134 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6135 addu $tempreg,$tempreg,$gp
6136 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6137 For a local symbol, we want
6138 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6140 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6142 If we have a small constant, and this is a reference to
6143 an external symbol, we want
6144 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6145 addu $tempreg,$tempreg,$gp
6146 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6148 addiu $tempreg,$tempreg,<constant>
6149 For a local symbol, we want
6150 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6152 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6154 If we have a large constant, and this is a reference to
6155 an external symbol, we want
6156 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6157 addu $tempreg,$tempreg,$gp
6158 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6159 lui $at,<hiconstant>
6160 addiu $at,$at,<loconstant>
6161 addu $tempreg,$tempreg,$at
6162 For a local symbol, we want
6163 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6164 lui $at,<hiconstant>
6165 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6166 addu $tempreg,$tempreg,$at
6169 expr1.X_add_number = offset_expr.X_add_number;
6170 offset_expr.X_add_number = 0;
6171 relax_start (offset_expr.X_add_symbol);
6172 gpdelay = reg_needs_delay (mips_gp_register);
6173 if (expr1.X_add_number == 0 && breg == 0
6174 && (call || tempreg == PIC_CALL_REG))
6176 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6177 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6179 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6180 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6181 tempreg, tempreg, mips_gp_register);
6182 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6183 tempreg, lw_reloc_type, tempreg);
6184 if (expr1.X_add_number == 0)
6188 /* We're going to put in an addu instruction using
6189 tempreg, so we may as well insert the nop right
6194 else if (expr1.X_add_number >= -0x8000
6195 && expr1.X_add_number < 0x8000)
6198 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6199 tempreg, tempreg, BFD_RELOC_LO16);
6203 /* If we are going to add in a base register, and the
6204 target register and the base register are the same,
6205 then we are using AT as a temporary register. Since
6206 we want to load the constant into AT, we add our
6207 current AT (from the global offset table) and the
6208 register into the register now, and pretend we were
6209 not using a base register. */
6214 gas_assert (tempreg == AT);
6216 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6221 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6222 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6226 offset_expr.X_add_number =
6227 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6232 /* This is needed because this instruction uses $gp, but
6233 the first instruction on the main stream does not. */
6234 macro_build (NULL, "nop", "");
6237 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6238 local_reloc_type, mips_gp_register);
6239 if (expr1.X_add_number >= -0x8000
6240 && expr1.X_add_number < 0x8000)
6243 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6244 tempreg, tempreg, BFD_RELOC_LO16);
6245 /* FIXME: If add_number is 0, and there was no base
6246 register, the external symbol case ended with a load,
6247 so if the symbol turns out to not be external, and
6248 the next instruction uses tempreg, an unnecessary nop
6249 will be inserted. */
6255 /* We must add in the base register now, as in the
6256 external symbol case. */
6257 gas_assert (tempreg == AT);
6259 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6262 /* We set breg to 0 because we have arranged to add
6263 it in in both cases. */
6267 macro_build_lui (&expr1, AT);
6268 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6269 AT, AT, BFD_RELOC_LO16);
6270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6271 tempreg, tempreg, AT);
6276 else if (mips_big_got && HAVE_NEWABI)
6278 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6279 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6280 int add_breg_early = 0;
6282 /* This is the large GOT case. If this is a reference to an
6283 external symbol, and there is no constant, we want
6284 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6285 add $tempreg,$tempreg,$gp
6286 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6287 or for lca or if tempreg is PIC_CALL_REG
6288 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6289 add $tempreg,$tempreg,$gp
6290 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6292 If we have a small constant, and this is a reference to
6293 an external symbol, we want
6294 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6295 add $tempreg,$tempreg,$gp
6296 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6297 addi $tempreg,$tempreg,<constant>
6299 If we have a large constant, and this is a reference to
6300 an external symbol, we want
6301 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6302 addu $tempreg,$tempreg,$gp
6303 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6304 lui $at,<hiconstant>
6305 addi $at,$at,<loconstant>
6306 add $tempreg,$tempreg,$at
6308 If we have NewABI, and we know it's a local symbol, we want
6309 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6310 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6311 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6313 relax_start (offset_expr.X_add_symbol);
6315 expr1.X_add_number = offset_expr.X_add_number;
6316 offset_expr.X_add_number = 0;
6318 if (expr1.X_add_number == 0 && breg == 0
6319 && (call || tempreg == PIC_CALL_REG))
6321 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6322 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6324 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6325 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6326 tempreg, tempreg, mips_gp_register);
6327 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6328 tempreg, lw_reloc_type, tempreg);
6330 if (expr1.X_add_number == 0)
6332 else if (expr1.X_add_number >= -0x8000
6333 && expr1.X_add_number < 0x8000)
6335 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6336 tempreg, tempreg, BFD_RELOC_LO16);
6338 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6340 /* If we are going to add in a base register, and the
6341 target register and the base register are the same,
6342 then we are using AT as a temporary register. Since
6343 we want to load the constant into AT, we add our
6344 current AT (from the global offset table) and the
6345 register into the register now, and pretend we were
6346 not using a base register. */
6351 gas_assert (tempreg == AT);
6352 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6358 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6359 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6364 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6367 offset_expr.X_add_number = expr1.X_add_number;
6368 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6369 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6370 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6371 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6374 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6375 treg, tempreg, breg);
6385 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6390 unsigned long temp = (treg << 16) | (0x01);
6391 macro_build (NULL, "c2", "C", temp);
6397 unsigned long temp = (0x02);
6398 macro_build (NULL, "c2", "C", temp);
6404 unsigned long temp = (treg << 16) | (0x02);
6405 macro_build (NULL, "c2", "C", temp);
6410 macro_build (NULL, "c2", "C", 3);
6415 unsigned long temp = (treg << 16) | 0x03;
6416 macro_build (NULL, "c2", "C", temp);
6421 /* The j instruction may not be used in PIC code, since it
6422 requires an absolute address. We convert it to a b
6424 if (mips_pic == NO_PIC)
6425 macro_build (&offset_expr, "j", "a");
6427 macro_build (&offset_expr, "b", "p");
6430 /* The jal instructions must be handled as macros because when
6431 generating PIC code they expand to multi-instruction
6432 sequences. Normally they are simple instructions. */
6437 if (mips_pic == NO_PIC)
6438 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6441 if (sreg != PIC_CALL_REG)
6442 as_warn (_("MIPS PIC call to register other than $25"));
6444 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6445 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6447 if (mips_cprestore_offset < 0)
6448 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6451 if (!mips_frame_reg_valid)
6453 as_warn (_("No .frame pseudo-op used in PIC code"));
6454 /* Quiet this warning. */
6455 mips_frame_reg_valid = 1;
6457 if (!mips_cprestore_valid)
6459 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6460 /* Quiet this warning. */
6461 mips_cprestore_valid = 1;
6463 if (mips_opts.noreorder)
6464 macro_build (NULL, "nop", "");
6465 expr1.X_add_number = mips_cprestore_offset;
6466 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6469 HAVE_64BIT_ADDRESSES);
6477 if (mips_pic == NO_PIC)
6478 macro_build (&offset_expr, "jal", "a");
6479 else if (mips_pic == SVR4_PIC)
6481 /* If this is a reference to an external symbol, and we are
6482 using a small GOT, we want
6483 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6487 lw $gp,cprestore($sp)
6488 The cprestore value is set using the .cprestore
6489 pseudo-op. If we are using a big GOT, we want
6490 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6492 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6496 lw $gp,cprestore($sp)
6497 If the symbol is not external, we want
6498 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6500 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6503 lw $gp,cprestore($sp)
6505 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6506 sequences above, minus nops, unless the symbol is local,
6507 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6513 relax_start (offset_expr.X_add_symbol);
6514 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6515 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6518 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6519 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6525 relax_start (offset_expr.X_add_symbol);
6526 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6527 BFD_RELOC_MIPS_CALL_HI16);
6528 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6529 PIC_CALL_REG, mips_gp_register);
6530 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6531 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6534 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6535 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6537 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6538 PIC_CALL_REG, PIC_CALL_REG,
6539 BFD_RELOC_MIPS_GOT_OFST);
6543 macro_build_jalr (&offset_expr);
6547 relax_start (offset_expr.X_add_symbol);
6550 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6551 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6560 gpdelay = reg_needs_delay (mips_gp_register);
6561 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6562 BFD_RELOC_MIPS_CALL_HI16);
6563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6564 PIC_CALL_REG, mips_gp_register);
6565 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6566 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6571 macro_build (NULL, "nop", "");
6573 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6574 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6577 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6578 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6580 macro_build_jalr (&offset_expr);
6582 if (mips_cprestore_offset < 0)
6583 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6586 if (!mips_frame_reg_valid)
6588 as_warn (_("No .frame pseudo-op used in PIC code"));
6589 /* Quiet this warning. */
6590 mips_frame_reg_valid = 1;
6592 if (!mips_cprestore_valid)
6594 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6595 /* Quiet this warning. */
6596 mips_cprestore_valid = 1;
6598 if (mips_opts.noreorder)
6599 macro_build (NULL, "nop", "");
6600 expr1.X_add_number = mips_cprestore_offset;
6601 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6604 HAVE_64BIT_ADDRESSES);
6608 else if (mips_pic == VXWORKS_PIC)
6609 as_bad (_("Non-PIC jump used in PIC library"));
6632 /* Itbl support may require additional care here. */
6637 /* Itbl support may require additional care here. */
6642 /* Itbl support may require additional care here. */
6647 /* Itbl support may require additional care here. */
6660 /* Itbl support may require additional care here. */
6665 /* Itbl support may require additional care here. */
6670 /* Itbl support may require additional care here. */
6690 if (breg == treg || coproc || lr)
6711 /* Itbl support may require additional care here. */
6716 /* Itbl support may require additional care here. */
6721 /* Itbl support may require additional care here. */
6726 /* Itbl support may require additional care here. */
6750 /* Itbl support may require additional care here. */
6754 /* Itbl support may require additional care here. */
6759 /* Itbl support may require additional care here. */
6772 && NO_ISA_COP (mips_opts.arch)
6773 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6775 as_bad (_("Opcode not supported on this processor: %s"),
6776 mips_cpu_info_from_arch (mips_opts.arch)->name);
6780 /* Itbl support may require additional care here. */
6781 if (mask == M_LWC1_AB
6782 || mask == M_SWC1_AB
6783 || mask == M_LDC1_AB
6784 || mask == M_SDC1_AB
6788 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6795 if (offset_expr.X_op != O_constant
6796 && offset_expr.X_op != O_symbol)
6798 as_bad (_("Expression too complex"));
6799 offset_expr.X_op = O_constant;
6802 if (HAVE_32BIT_ADDRESSES
6803 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6807 sprintf_vma (value, offset_expr.X_add_number);
6808 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6811 /* A constant expression in PIC code can be handled just as it
6812 is in non PIC code. */
6813 if (offset_expr.X_op == O_constant)
6815 expr1.X_add_number = offset_expr.X_add_number;
6816 normalize_address_expr (&expr1);
6817 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6819 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6820 & ~(bfd_vma) 0xffff);
6821 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6823 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6824 tempreg, tempreg, breg);
6827 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6829 else if (mips_pic == NO_PIC)
6831 /* If this is a reference to a GP relative symbol, and there
6832 is no base register, we want
6833 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6834 Otherwise, if there is no base register, we want
6835 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6836 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6837 If we have a constant, we need two instructions anyhow,
6838 so we always use the latter form.
6840 If we have a base register, and this is a reference to a
6841 GP relative symbol, we want
6842 addu $tempreg,$breg,$gp
6843 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6845 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6846 addu $tempreg,$tempreg,$breg
6847 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6848 With a constant we always use the latter case.
6850 With 64bit address space and no base register and $at usable,
6852 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6853 lui $at,<sym> (BFD_RELOC_HI16_S)
6854 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6857 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6858 If we have a base register, we want
6859 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6860 lui $at,<sym> (BFD_RELOC_HI16_S)
6861 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6865 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6867 Without $at we can't generate the optimal path for superscalar
6868 processors here since this would require two temporary registers.
6869 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6870 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6872 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6874 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6875 If we have a base register, we want
6876 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6877 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6879 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6881 daddu $tempreg,$tempreg,$breg
6882 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6884 For GP relative symbols in 64bit address space we can use
6885 the same sequence as in 32bit address space. */
6886 if (HAVE_64BIT_SYMBOLS)
6888 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6889 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6891 relax_start (offset_expr.X_add_symbol);
6894 macro_build (&offset_expr, s, fmt, treg,
6895 BFD_RELOC_GPREL16, mips_gp_register);
6899 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6900 tempreg, breg, mips_gp_register);
6901 macro_build (&offset_expr, s, fmt, treg,
6902 BFD_RELOC_GPREL16, tempreg);
6907 if (used_at == 0 && mips_opts.at)
6909 macro_build (&offset_expr, "lui", "t,u", tempreg,
6910 BFD_RELOC_MIPS_HIGHEST);
6911 macro_build (&offset_expr, "lui", "t,u", AT,
6913 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6914 tempreg, BFD_RELOC_MIPS_HIGHER);
6916 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6917 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6918 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6919 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6925 macro_build (&offset_expr, "lui", "t,u", tempreg,
6926 BFD_RELOC_MIPS_HIGHEST);
6927 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6928 tempreg, BFD_RELOC_MIPS_HIGHER);
6929 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6930 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6931 tempreg, BFD_RELOC_HI16_S);
6932 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6934 macro_build (NULL, "daddu", "d,v,t",
6935 tempreg, tempreg, breg);
6936 macro_build (&offset_expr, s, fmt, treg,
6937 BFD_RELOC_LO16, tempreg);
6940 if (mips_relax.sequence)
6947 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6948 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6950 relax_start (offset_expr.X_add_symbol);
6951 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6955 macro_build_lui (&offset_expr, tempreg);
6956 macro_build (&offset_expr, s, fmt, treg,
6957 BFD_RELOC_LO16, tempreg);
6958 if (mips_relax.sequence)
6963 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6964 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6966 relax_start (offset_expr.X_add_symbol);
6967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6968 tempreg, breg, mips_gp_register);
6969 macro_build (&offset_expr, s, fmt, treg,
6970 BFD_RELOC_GPREL16, tempreg);
6973 macro_build_lui (&offset_expr, tempreg);
6974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6975 tempreg, tempreg, breg);
6976 macro_build (&offset_expr, s, fmt, treg,
6977 BFD_RELOC_LO16, tempreg);
6978 if (mips_relax.sequence)
6982 else if (!mips_big_got)
6984 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6986 /* If this is a reference to an external symbol, we want
6987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6989 <op> $treg,0($tempreg)
6991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6993 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6994 <op> $treg,0($tempreg)
6997 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6998 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7000 If there is a base register, we add it to $tempreg before
7001 the <op>. If there is a constant, we stick it in the
7002 <op> instruction. We don't handle constants larger than
7003 16 bits, because we have no way to load the upper 16 bits
7004 (actually, we could handle them for the subset of cases
7005 in which we are not using $at). */
7006 gas_assert (offset_expr.X_op == O_symbol);
7009 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7010 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7012 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7013 tempreg, tempreg, breg);
7014 macro_build (&offset_expr, s, fmt, treg,
7015 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7018 expr1.X_add_number = offset_expr.X_add_number;
7019 offset_expr.X_add_number = 0;
7020 if (expr1.X_add_number < -0x8000
7021 || expr1.X_add_number >= 0x8000)
7022 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7023 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7024 lw_reloc_type, mips_gp_register);
7026 relax_start (offset_expr.X_add_symbol);
7028 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7029 tempreg, BFD_RELOC_LO16);
7032 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7033 tempreg, tempreg, breg);
7034 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7036 else if (mips_big_got && !HAVE_NEWABI)
7040 /* If this is a reference to an external symbol, we want
7041 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7042 addu $tempreg,$tempreg,$gp
7043 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7044 <op> $treg,0($tempreg)
7046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7048 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7049 <op> $treg,0($tempreg)
7050 If there is a base register, we add it to $tempreg before
7051 the <op>. If there is a constant, we stick it in the
7052 <op> instruction. We don't handle constants larger than
7053 16 bits, because we have no way to load the upper 16 bits
7054 (actually, we could handle them for the subset of cases
7055 in which we are not using $at). */
7056 gas_assert (offset_expr.X_op == O_symbol);
7057 expr1.X_add_number = offset_expr.X_add_number;
7058 offset_expr.X_add_number = 0;
7059 if (expr1.X_add_number < -0x8000
7060 || expr1.X_add_number >= 0x8000)
7061 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7062 gpdelay = reg_needs_delay (mips_gp_register);
7063 relax_start (offset_expr.X_add_symbol);
7064 macro_build (&offset_expr, "lui", "t,u", tempreg,
7065 BFD_RELOC_MIPS_GOT_HI16);
7066 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7068 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7069 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7072 macro_build (NULL, "nop", "");
7073 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7074 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7076 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7077 tempreg, BFD_RELOC_LO16);
7081 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7082 tempreg, tempreg, breg);
7083 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7085 else if (mips_big_got && HAVE_NEWABI)
7087 /* If this is a reference to an external symbol, we want
7088 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7089 add $tempreg,$tempreg,$gp
7090 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7091 <op> $treg,<ofst>($tempreg)
7092 Otherwise, for local symbols, we want:
7093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7094 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7095 gas_assert (offset_expr.X_op == O_symbol);
7096 expr1.X_add_number = offset_expr.X_add_number;
7097 offset_expr.X_add_number = 0;
7098 if (expr1.X_add_number < -0x8000
7099 || expr1.X_add_number >= 0x8000)
7100 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7101 relax_start (offset_expr.X_add_symbol);
7102 macro_build (&offset_expr, "lui", "t,u", tempreg,
7103 BFD_RELOC_MIPS_GOT_HI16);
7104 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7106 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7107 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7109 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7110 tempreg, tempreg, breg);
7111 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7114 offset_expr.X_add_number = expr1.X_add_number;
7115 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7116 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7119 tempreg, tempreg, breg);
7120 macro_build (&offset_expr, s, fmt, treg,
7121 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7131 load_register (treg, &imm_expr, 0);
7135 load_register (treg, &imm_expr, 1);
7139 if (imm_expr.X_op == O_constant)
7142 load_register (AT, &imm_expr, 0);
7143 macro_build (NULL, "mtc1", "t,G", AT, treg);
7148 gas_assert (offset_expr.X_op == O_symbol
7149 && strcmp (segment_name (S_GET_SEGMENT
7150 (offset_expr.X_add_symbol)),
7152 && offset_expr.X_add_number == 0);
7153 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7154 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7159 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7160 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7161 order 32 bits of the value and the low order 32 bits are either
7162 zero or in OFFSET_EXPR. */
7163 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7165 if (HAVE_64BIT_GPRS)
7166 load_register (treg, &imm_expr, 1);
7171 if (target_big_endian)
7183 load_register (hreg, &imm_expr, 0);
7186 if (offset_expr.X_op == O_absent)
7187 move_register (lreg, 0);
7190 gas_assert (offset_expr.X_op == O_constant);
7191 load_register (lreg, &offset_expr, 0);
7198 /* We know that sym is in the .rdata section. First we get the
7199 upper 16 bits of the address. */
7200 if (mips_pic == NO_PIC)
7202 macro_build_lui (&offset_expr, AT);
7207 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7208 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7212 /* Now we load the register(s). */
7213 if (HAVE_64BIT_GPRS)
7216 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7221 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7224 /* FIXME: How in the world do we deal with the possible
7226 offset_expr.X_add_number += 4;
7227 macro_build (&offset_expr, "lw", "t,o(b)",
7228 treg + 1, BFD_RELOC_LO16, AT);
7234 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7235 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7236 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7237 the value and the low order 32 bits are either zero or in
7239 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7242 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7243 if (HAVE_64BIT_FPRS)
7245 gas_assert (HAVE_64BIT_GPRS);
7246 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7250 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7251 if (offset_expr.X_op == O_absent)
7252 macro_build (NULL, "mtc1", "t,G", 0, treg);
7255 gas_assert (offset_expr.X_op == O_constant);
7256 load_register (AT, &offset_expr, 0);
7257 macro_build (NULL, "mtc1", "t,G", AT, treg);
7263 gas_assert (offset_expr.X_op == O_symbol
7264 && offset_expr.X_add_number == 0);
7265 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7266 if (strcmp (s, ".lit8") == 0)
7268 if (mips_opts.isa != ISA_MIPS1)
7270 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7271 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7274 breg = mips_gp_register;
7275 r = BFD_RELOC_MIPS_LITERAL;
7280 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7282 if (mips_pic != NO_PIC)
7283 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7284 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7287 /* FIXME: This won't work for a 64 bit address. */
7288 macro_build_lui (&offset_expr, AT);
7291 if (mips_opts.isa != ISA_MIPS1)
7293 macro_build (&offset_expr, "ldc1", "T,o(b)",
7294 treg, BFD_RELOC_LO16, AT);
7303 /* Even on a big endian machine $fn comes before $fn+1. We have
7304 to adjust when loading from memory. */
7307 gas_assert (mips_opts.isa == ISA_MIPS1);
7308 macro_build (&offset_expr, "lwc1", "T,o(b)",
7309 target_big_endian ? treg + 1 : treg, r, breg);
7310 /* FIXME: A possible overflow which I don't know how to deal
7312 offset_expr.X_add_number += 4;
7313 macro_build (&offset_expr, "lwc1", "T,o(b)",
7314 target_big_endian ? treg : treg + 1, r, breg);
7318 gas_assert (mips_opts.isa == ISA_MIPS1);
7319 /* Even on a big endian machine $fn comes before $fn+1. We have
7320 to adjust when storing to memory. */
7321 macro_build (&offset_expr, "swc1", "T,o(b)",
7322 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7323 offset_expr.X_add_number += 4;
7324 macro_build (&offset_expr, "swc1", "T,o(b)",
7325 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7330 * The MIPS assembler seems to check for X_add_number not
7331 * being double aligned and generating:
7334 * addiu at,at,%lo(foo+1)
7337 * But, the resulting address is the same after relocation so why
7338 * generate the extra instruction?
7340 /* Itbl support may require additional care here. */
7342 if (mips_opts.isa != ISA_MIPS1)
7353 if (mips_opts.isa != ISA_MIPS1)
7361 /* Itbl support may require additional care here. */
7366 if (HAVE_64BIT_GPRS)
7377 if (HAVE_64BIT_GPRS)
7387 if (offset_expr.X_op != O_symbol
7388 && offset_expr.X_op != O_constant)
7390 as_bad (_("Expression too complex"));
7391 offset_expr.X_op = O_constant;
7394 if (HAVE_32BIT_ADDRESSES
7395 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7399 sprintf_vma (value, offset_expr.X_add_number);
7400 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7403 /* Even on a big endian machine $fn comes before $fn+1. We have
7404 to adjust when loading from memory. We set coproc if we must
7405 load $fn+1 first. */
7406 /* Itbl support may require additional care here. */
7407 if (!target_big_endian)
7410 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7412 /* If this is a reference to a GP relative symbol, we want
7413 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7414 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7415 If we have a base register, we use this
7417 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7418 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7419 If this is not a GP relative symbol, we want
7420 lui $at,<sym> (BFD_RELOC_HI16_S)
7421 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7422 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7423 If there is a base register, we add it to $at after the
7424 lui instruction. If there is a constant, we always use
7426 if (offset_expr.X_op == O_symbol
7427 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7428 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7430 relax_start (offset_expr.X_add_symbol);
7433 tempreg = mips_gp_register;
7437 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7438 AT, breg, mips_gp_register);
7443 /* Itbl support may require additional care here. */
7444 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7445 BFD_RELOC_GPREL16, tempreg);
7446 offset_expr.X_add_number += 4;
7448 /* Set mips_optimize to 2 to avoid inserting an
7450 hold_mips_optimize = mips_optimize;
7452 /* Itbl support may require additional care here. */
7453 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7454 BFD_RELOC_GPREL16, tempreg);
7455 mips_optimize = hold_mips_optimize;
7459 offset_expr.X_add_number -= 4;
7462 macro_build_lui (&offset_expr, AT);
7464 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7465 /* Itbl support may require additional care here. */
7466 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7467 BFD_RELOC_LO16, AT);
7468 /* FIXME: How do we handle overflow here? */
7469 offset_expr.X_add_number += 4;
7470 /* Itbl support may require additional care here. */
7471 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7472 BFD_RELOC_LO16, AT);
7473 if (mips_relax.sequence)
7476 else if (!mips_big_got)
7478 /* If this is a reference to an external symbol, we want
7479 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7484 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7486 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7487 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7488 If there is a base register we add it to $at before the
7489 lwc1 instructions. If there is a constant we include it
7490 in the lwc1 instructions. */
7492 expr1.X_add_number = offset_expr.X_add_number;
7493 if (expr1.X_add_number < -0x8000
7494 || expr1.X_add_number >= 0x8000 - 4)
7495 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7496 load_got_offset (AT, &offset_expr);
7499 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7501 /* Set mips_optimize to 2 to avoid inserting an undesired
7503 hold_mips_optimize = mips_optimize;
7506 /* Itbl support may require additional care here. */
7507 relax_start (offset_expr.X_add_symbol);
7508 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7509 BFD_RELOC_LO16, AT);
7510 expr1.X_add_number += 4;
7511 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7512 BFD_RELOC_LO16, AT);
7514 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7515 BFD_RELOC_LO16, AT);
7516 offset_expr.X_add_number += 4;
7517 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7518 BFD_RELOC_LO16, AT);
7521 mips_optimize = hold_mips_optimize;
7523 else if (mips_big_got)
7527 /* If this is a reference to an external symbol, we want
7528 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7530 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7535 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7537 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7538 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7539 If there is a base register we add it to $at before the
7540 lwc1 instructions. If there is a constant we include it
7541 in the lwc1 instructions. */
7543 expr1.X_add_number = offset_expr.X_add_number;
7544 offset_expr.X_add_number = 0;
7545 if (expr1.X_add_number < -0x8000
7546 || expr1.X_add_number >= 0x8000 - 4)
7547 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7548 gpdelay = reg_needs_delay (mips_gp_register);
7549 relax_start (offset_expr.X_add_symbol);
7550 macro_build (&offset_expr, "lui", "t,u",
7551 AT, BFD_RELOC_MIPS_GOT_HI16);
7552 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7553 AT, AT, mips_gp_register);
7554 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7555 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7558 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7559 /* Itbl support may require additional care here. */
7560 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7561 BFD_RELOC_LO16, AT);
7562 expr1.X_add_number += 4;
7564 /* Set mips_optimize to 2 to avoid inserting an undesired
7566 hold_mips_optimize = mips_optimize;
7568 /* Itbl support may require additional care here. */
7569 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7570 BFD_RELOC_LO16, AT);
7571 mips_optimize = hold_mips_optimize;
7572 expr1.X_add_number -= 4;
7575 offset_expr.X_add_number = expr1.X_add_number;
7577 macro_build (NULL, "nop", "");
7578 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7579 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7582 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7583 /* Itbl support may require additional care here. */
7584 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7585 BFD_RELOC_LO16, AT);
7586 offset_expr.X_add_number += 4;
7588 /* Set mips_optimize to 2 to avoid inserting an undesired
7590 hold_mips_optimize = mips_optimize;
7592 /* Itbl support may require additional care here. */
7593 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7594 BFD_RELOC_LO16, AT);
7595 mips_optimize = hold_mips_optimize;
7604 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7607 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7609 macro_build (&offset_expr, s, "t,o(b)", treg,
7610 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7612 if (!HAVE_64BIT_GPRS)
7614 offset_expr.X_add_number += 4;
7615 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7616 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7621 /* New code added to support COPZ instructions.
7622 This code builds table entries out of the macros in mip_opcodes.
7623 R4000 uses interlocks to handle coproc delays.
7624 Other chips (like the R3000) require nops to be inserted for delays.
7626 FIXME: Currently, we require that the user handle delays.
7627 In order to fill delay slots for non-interlocked chips,
7628 we must have a way to specify delays based on the coprocessor.
7629 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7630 What are the side-effects of the cop instruction?
7631 What cache support might we have and what are its effects?
7632 Both coprocessor & memory require delays. how long???
7633 What registers are read/set/modified?
7635 If an itbl is provided to interpret cop instructions,
7636 this knowledge can be encoded in the itbl spec. */
7650 if (NO_ISA_COP (mips_opts.arch)
7651 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7653 as_bad (_("opcode not supported on this processor: %s"),
7654 mips_cpu_info_from_arch (mips_opts.arch)->name);
7658 /* For now we just do C (same as Cz). The parameter will be
7659 stored in insn_opcode by mips_ip. */
7660 macro_build (NULL, s, "C", ip->insn_opcode);
7664 move_register (dreg, sreg);
7670 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7671 macro_build (NULL, "mflo", "d", dreg);
7677 /* The MIPS assembler some times generates shifts and adds. I'm
7678 not trying to be that fancy. GCC should do this for us
7681 load_register (AT, &imm_expr, dbl);
7682 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7683 macro_build (NULL, "mflo", "d", dreg);
7699 load_register (AT, &imm_expr, dbl);
7700 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7701 macro_build (NULL, "mflo", "d", dreg);
7702 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7703 macro_build (NULL, "mfhi", "d", AT);
7705 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7708 expr1.X_add_number = 8;
7709 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7710 macro_build (NULL, "nop", "");
7711 macro_build (NULL, "break", "c", 6);
7714 macro_build (NULL, "mflo", "d", dreg);
7730 load_register (AT, &imm_expr, dbl);
7731 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7732 sreg, imm ? AT : treg);
7733 macro_build (NULL, "mfhi", "d", AT);
7734 macro_build (NULL, "mflo", "d", dreg);
7736 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7739 expr1.X_add_number = 8;
7740 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7741 macro_build (NULL, "nop", "");
7742 macro_build (NULL, "break", "c", 6);
7748 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7759 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7760 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7764 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7765 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7766 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7767 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7771 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7782 macro_build (NULL, "negu", "d,w", tempreg, treg);
7783 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7787 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7788 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7789 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7790 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7799 if (imm_expr.X_op != O_constant)
7800 as_bad (_("Improper rotate count"));
7801 rot = imm_expr.X_add_number & 0x3f;
7802 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7804 rot = (64 - rot) & 0x3f;
7806 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7808 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7813 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7816 l = (rot < 0x20) ? "dsll" : "dsll32";
7817 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7820 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7821 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7822 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7830 if (imm_expr.X_op != O_constant)
7831 as_bad (_("Improper rotate count"));
7832 rot = imm_expr.X_add_number & 0x1f;
7833 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7835 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7840 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7844 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7845 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7846 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7851 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7853 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7857 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7858 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7859 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7860 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7864 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7866 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7870 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7871 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7872 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7873 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7882 if (imm_expr.X_op != O_constant)
7883 as_bad (_("Improper rotate count"));
7884 rot = imm_expr.X_add_number & 0x3f;
7885 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7888 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7890 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7895 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7898 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7899 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7902 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7903 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7904 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7912 if (imm_expr.X_op != O_constant)
7913 as_bad (_("Improper rotate count"));
7914 rot = imm_expr.X_add_number & 0x1f;
7915 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7917 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7922 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7926 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7927 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7928 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7934 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7936 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7939 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7940 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7945 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7947 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7952 as_warn (_("Instruction %s: result is always false"),
7954 move_register (dreg, 0);
7957 if (CPU_HAS_SEQ (mips_opts.arch)
7958 && -512 <= imm_expr.X_add_number
7959 && imm_expr.X_add_number < 512)
7961 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
7962 (int) imm_expr.X_add_number);
7965 if (imm_expr.X_op == O_constant
7966 && imm_expr.X_add_number >= 0
7967 && imm_expr.X_add_number < 0x10000)
7969 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7971 else if (imm_expr.X_op == O_constant
7972 && imm_expr.X_add_number > -0x8000
7973 && imm_expr.X_add_number < 0)
7975 imm_expr.X_add_number = -imm_expr.X_add_number;
7976 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7977 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7979 else if (CPU_HAS_SEQ (mips_opts.arch))
7982 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7983 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
7988 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7989 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7992 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7995 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8001 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8002 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8005 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8007 if (imm_expr.X_op == O_constant
8008 && imm_expr.X_add_number >= -0x8000
8009 && imm_expr.X_add_number < 0x8000)
8011 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8012 dreg, sreg, BFD_RELOC_LO16);
8016 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8017 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8021 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8024 case M_SGT: /* sreg > treg <==> treg < sreg */
8030 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8033 case M_SGT_I: /* sreg > I <==> I < sreg */
8040 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8041 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8044 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8050 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8051 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8054 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8061 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8062 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8063 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8067 if (imm_expr.X_op == O_constant
8068 && imm_expr.X_add_number >= -0x8000
8069 && imm_expr.X_add_number < 0x8000)
8071 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8075 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8076 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8080 if (imm_expr.X_op == O_constant
8081 && imm_expr.X_add_number >= -0x8000
8082 && imm_expr.X_add_number < 0x8000)
8084 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8089 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8090 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8095 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8097 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8100 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8101 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8106 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8108 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8113 as_warn (_("Instruction %s: result is always true"),
8115 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8116 dreg, 0, BFD_RELOC_LO16);
8119 if (CPU_HAS_SEQ (mips_opts.arch)
8120 && -512 <= imm_expr.X_add_number
8121 && imm_expr.X_add_number < 512)
8123 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8124 (int) imm_expr.X_add_number);
8127 if (imm_expr.X_op == O_constant
8128 && imm_expr.X_add_number >= 0
8129 && imm_expr.X_add_number < 0x10000)
8131 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8133 else if (imm_expr.X_op == O_constant
8134 && imm_expr.X_add_number > -0x8000
8135 && imm_expr.X_add_number < 0)
8137 imm_expr.X_add_number = -imm_expr.X_add_number;
8138 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8139 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8141 else if (CPU_HAS_SEQ (mips_opts.arch))
8144 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8145 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8150 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8151 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8154 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8160 if (imm_expr.X_op == O_constant
8161 && imm_expr.X_add_number > -0x8000
8162 && imm_expr.X_add_number <= 0x8000)
8164 imm_expr.X_add_number = -imm_expr.X_add_number;
8165 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8166 dreg, sreg, BFD_RELOC_LO16);
8170 load_register (AT, &imm_expr, dbl);
8171 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8177 if (imm_expr.X_op == O_constant
8178 && imm_expr.X_add_number > -0x8000
8179 && imm_expr.X_add_number <= 0x8000)
8181 imm_expr.X_add_number = -imm_expr.X_add_number;
8182 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8183 dreg, sreg, BFD_RELOC_LO16);
8187 load_register (AT, &imm_expr, dbl);
8188 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8210 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8211 macro_build (NULL, s, "s,t", sreg, AT);
8216 gas_assert (mips_opts.isa == ISA_MIPS1);
8218 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8219 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8222 * Is the double cfc1 instruction a bug in the mips assembler;
8223 * or is there a reason for it?
8226 macro_build (NULL, "cfc1", "t,G", treg, RA);
8227 macro_build (NULL, "cfc1", "t,G", treg, RA);
8228 macro_build (NULL, "nop", "");
8229 expr1.X_add_number = 3;
8230 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8231 expr1.X_add_number = 2;
8232 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8233 macro_build (NULL, "ctc1", "t,G", AT, RA);
8234 macro_build (NULL, "nop", "");
8235 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8237 macro_build (NULL, "ctc1", "t,G", treg, RA);
8238 macro_build (NULL, "nop", "");
8249 if (offset_expr.X_add_number >= 0x7fff)
8250 as_bad (_("Operand overflow"));
8251 if (!target_big_endian)
8252 ++offset_expr.X_add_number;
8253 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8254 if (!target_big_endian)
8255 --offset_expr.X_add_number;
8257 ++offset_expr.X_add_number;
8258 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8259 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8260 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8273 if (offset_expr.X_add_number >= 0x8000 - off)
8274 as_bad (_("Operand overflow"));
8282 if (!target_big_endian)
8283 offset_expr.X_add_number += off;
8284 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8285 if (!target_big_endian)
8286 offset_expr.X_add_number -= off;
8288 offset_expr.X_add_number += off;
8289 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8291 /* If necessary, move the result in tempreg to the final destination. */
8292 if (treg == tempreg)
8294 /* Protect second load's delay slot. */
8296 move_register (treg, tempreg);
8310 load_address (AT, &offset_expr, &used_at);
8312 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8313 if (!target_big_endian)
8314 expr1.X_add_number = off;
8316 expr1.X_add_number = 0;
8317 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8318 if (!target_big_endian)
8319 expr1.X_add_number = 0;
8321 expr1.X_add_number = off;
8322 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8328 load_address (AT, &offset_expr, &used_at);
8330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8331 if (target_big_endian)
8332 expr1.X_add_number = 0;
8333 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8334 treg, BFD_RELOC_LO16, AT);
8335 if (target_big_endian)
8336 expr1.X_add_number = 1;
8338 expr1.X_add_number = 0;
8339 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8340 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8341 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8346 if (offset_expr.X_add_number >= 0x7fff)
8347 as_bad (_("Operand overflow"));
8348 if (target_big_endian)
8349 ++offset_expr.X_add_number;
8350 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8351 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8352 if (target_big_endian)
8353 --offset_expr.X_add_number;
8355 ++offset_expr.X_add_number;
8356 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8369 if (offset_expr.X_add_number >= 0x8000 - off)
8370 as_bad (_("Operand overflow"));
8371 if (!target_big_endian)
8372 offset_expr.X_add_number += off;
8373 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8374 if (!target_big_endian)
8375 offset_expr.X_add_number -= off;
8377 offset_expr.X_add_number += off;
8378 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8392 load_address (AT, &offset_expr, &used_at);
8394 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8395 if (!target_big_endian)
8396 expr1.X_add_number = off;
8398 expr1.X_add_number = 0;
8399 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8400 if (!target_big_endian)
8401 expr1.X_add_number = 0;
8403 expr1.X_add_number = off;
8404 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8409 load_address (AT, &offset_expr, &used_at);
8411 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8412 if (!target_big_endian)
8413 expr1.X_add_number = 0;
8414 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8415 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8416 if (!target_big_endian)
8417 expr1.X_add_number = 1;
8419 expr1.X_add_number = 0;
8420 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8421 if (!target_big_endian)
8422 expr1.X_add_number = 0;
8424 expr1.X_add_number = 1;
8425 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8426 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8427 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8431 /* FIXME: Check if this is one of the itbl macros, since they
8432 are added dynamically. */
8433 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8436 if (!mips_opts.at && used_at)
8437 as_bad (_("Macro used $at after \".set noat\""));
8440 /* Implement macros in mips16 mode. */
8443 mips16_macro (struct mips_cl_insn *ip)
8446 int xreg, yreg, zreg, tmp;
8449 const char *s, *s2, *s3;
8451 mask = ip->insn_mo->mask;
8453 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8454 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8455 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8457 expr1.X_op = O_constant;
8458 expr1.X_op_symbol = NULL;
8459 expr1.X_add_symbol = NULL;
8460 expr1.X_add_number = 1;
8480 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8481 expr1.X_add_number = 2;
8482 macro_build (&expr1, "bnez", "x,p", yreg);
8483 macro_build (NULL, "break", "6", 7);
8485 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8486 since that causes an overflow. We should do that as well,
8487 but I don't see how to do the comparisons without a temporary
8490 macro_build (NULL, s, "x", zreg);
8510 macro_build (NULL, s, "0,x,y", xreg, yreg);
8511 expr1.X_add_number = 2;
8512 macro_build (&expr1, "bnez", "x,p", yreg);
8513 macro_build (NULL, "break", "6", 7);
8515 macro_build (NULL, s2, "x", zreg);
8521 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8522 macro_build (NULL, "mflo", "x", zreg);
8530 if (imm_expr.X_op != O_constant)
8531 as_bad (_("Unsupported large constant"));
8532 imm_expr.X_add_number = -imm_expr.X_add_number;
8533 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8537 if (imm_expr.X_op != O_constant)
8538 as_bad (_("Unsupported large constant"));
8539 imm_expr.X_add_number = -imm_expr.X_add_number;
8540 macro_build (&imm_expr, "addiu", "x,k", xreg);
8544 if (imm_expr.X_op != O_constant)
8545 as_bad (_("Unsupported large constant"));
8546 imm_expr.X_add_number = -imm_expr.X_add_number;
8547 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8569 goto do_reverse_branch;
8573 goto do_reverse_branch;
8585 goto do_reverse_branch;
8596 macro_build (NULL, s, "x,y", xreg, yreg);
8597 macro_build (&offset_expr, s2, "p");
8624 goto do_addone_branch_i;
8629 goto do_addone_branch_i;
8644 goto do_addone_branch_i;
8651 if (imm_expr.X_op != O_constant)
8652 as_bad (_("Unsupported large constant"));
8653 ++imm_expr.X_add_number;
8656 macro_build (&imm_expr, s, s3, xreg);
8657 macro_build (&offset_expr, s2, "p");
8661 expr1.X_add_number = 0;
8662 macro_build (&expr1, "slti", "x,8", yreg);
8664 move_register (xreg, yreg);
8665 expr1.X_add_number = 2;
8666 macro_build (&expr1, "bteqz", "p");
8667 macro_build (NULL, "neg", "x,w", xreg, xreg);
8671 /* For consistency checking, verify that all bits are specified either
8672 by the match/mask part of the instruction definition, or by the
8675 validate_mips_insn (const struct mips_opcode *opc)
8677 const char *p = opc->args;
8679 unsigned long used_bits = opc->mask;
8681 if ((used_bits & opc->match) != opc->match)
8683 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8684 opc->name, opc->args);
8687 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8697 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8698 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8699 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8700 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8701 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8702 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8703 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8704 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8705 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8706 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8707 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8708 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8709 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8711 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8712 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8713 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8714 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8715 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8716 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8717 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8718 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8719 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8720 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8721 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8722 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8723 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8724 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8725 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8728 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8729 c, opc->name, opc->args);
8733 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8734 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8736 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8737 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8738 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8739 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8741 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8742 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8744 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8745 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8747 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8748 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8749 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8750 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8751 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8752 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8753 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8754 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8755 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8756 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8757 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8758 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8759 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8760 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8761 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8762 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8763 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8765 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8766 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8767 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8768 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8770 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8771 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8772 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8773 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8774 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8775 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8776 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8777 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8778 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8781 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8782 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8783 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8784 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8785 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8788 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8789 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8790 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8791 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8792 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8793 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8794 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8795 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8796 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8797 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8798 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8799 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8800 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8801 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8802 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8803 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8804 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8805 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8807 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8808 c, opc->name, opc->args);
8812 if (used_bits != 0xffffffff)
8814 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8815 ~used_bits & 0xffffffff, opc->name, opc->args);
8821 /* UDI immediates. */
8829 static const struct mips_immed mips_immed[] = {
8830 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8831 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8832 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8833 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8837 /* Check whether an odd floating-point register is allowed. */
8839 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8841 const char *s = insn->name;
8843 if (insn->pinfo == INSN_MACRO)
8844 /* Let a macro pass, we'll catch it later when it is expanded. */
8847 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8849 /* Allow odd registers for single-precision ops. */
8850 switch (insn->pinfo & (FP_S | FP_D))
8854 return 1; /* both single precision - ok */
8856 return 0; /* both double precision - fail */
8861 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8862 s = strchr (insn->name, '.');
8864 s = s != NULL ? strchr (s + 1, '.') : NULL;
8865 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8868 /* Single-precision coprocessor loads and moves are OK too. */
8869 if ((insn->pinfo & FP_S)
8870 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8871 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8877 /* This routine assembles an instruction into its binary format. As a
8878 side effect, it sets one of the global variables imm_reloc or
8879 offset_reloc to the type of relocation to do if one of the operands
8880 is an address expression. */
8883 mips_ip (char *str, struct mips_cl_insn *ip)
8888 struct mips_opcode *insn;
8891 unsigned int lastregno;
8892 unsigned int lastpos = 0;
8893 unsigned int limlo, limhi;
8896 offsetT min_range, max_range;
8902 /* If the instruction contains a '.', we first try to match an instruction
8903 including the '.'. Then we try again without the '.'. */
8905 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8908 /* If we stopped on whitespace, then replace the whitespace with null for
8909 the call to hash_find. Save the character we replaced just in case we
8910 have to re-parse the instruction. */
8917 insn = (struct mips_opcode *) hash_find (op_hash, str);
8919 /* If we didn't find the instruction in the opcode table, try again, but
8920 this time with just the instruction up to, but not including the
8924 /* Restore the character we overwrite above (if any). */
8928 /* Scan up to the first '.' or whitespace. */
8930 *s != '\0' && *s != '.' && !ISSPACE (*s);
8934 /* If we did not find a '.', then we can quit now. */
8937 insn_error = _("Unrecognized opcode");
8941 /* Lookup the instruction in the hash table. */
8943 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8945 insn_error = _("Unrecognized opcode");
8955 gas_assert (strcmp (insn->name, str) == 0);
8957 ok = is_opcode_valid (insn);
8960 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8961 && strcmp (insn->name, insn[1].name) == 0)
8970 static char buf[100];
8972 _("opcode not supported on this processor: %s (%s)"),
8973 mips_cpu_info_from_arch (mips_opts.arch)->name,
8974 mips_cpu_info_from_isa (mips_opts.isa)->name);
8983 create_insn (ip, insn);
8986 lastregno = 0xffffffff;
8987 for (args = insn->args;; ++args)
8991 s += strspn (s, " \t");
8995 case '\0': /* end of args */
9000 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9001 my_getExpression (&imm_expr, s);
9002 check_absolute_expr (ip, &imm_expr);
9003 if ((unsigned long) imm_expr.X_add_number != 1
9004 && (unsigned long) imm_expr.X_add_number != 3)
9006 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9007 (unsigned long) imm_expr.X_add_number);
9009 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9010 imm_expr.X_op = O_absent;
9014 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9015 my_getExpression (&imm_expr, s);
9016 check_absolute_expr (ip, &imm_expr);
9017 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9019 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9020 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9022 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9023 imm_expr.X_op = O_absent;
9027 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9028 my_getExpression (&imm_expr, s);
9029 check_absolute_expr (ip, &imm_expr);
9030 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9032 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9033 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9035 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9036 imm_expr.X_op = O_absent;
9040 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9041 my_getExpression (&imm_expr, s);
9042 check_absolute_expr (ip, &imm_expr);
9043 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9045 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9046 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9048 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9049 imm_expr.X_op = O_absent;
9053 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9054 my_getExpression (&imm_expr, s);
9055 check_absolute_expr (ip, &imm_expr);
9056 if (imm_expr.X_add_number & ~OP_MASK_RS)
9058 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9059 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9061 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9062 imm_expr.X_op = O_absent;
9066 case '7': /* Four DSP accumulators in bits 11,12. */
9067 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9068 s[3] >= '0' && s[3] <= '3')
9072 INSERT_OPERAND (DSPACC, *ip, regno);
9076 as_bad (_("Invalid dsp acc register"));
9079 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9080 my_getExpression (&imm_expr, s);
9081 check_absolute_expr (ip, &imm_expr);
9082 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9084 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9086 (unsigned long) imm_expr.X_add_number);
9088 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9089 imm_expr.X_op = O_absent;
9093 case '9': /* Four DSP accumulators in bits 21,22. */
9094 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9095 s[3] >= '0' && s[3] <= '3')
9099 INSERT_OPERAND (DSPACC_S, *ip, regno);
9103 as_bad (_("Invalid dsp acc register"));
9106 case '0': /* DSP 6-bit signed immediate in bit 20. */
9107 my_getExpression (&imm_expr, s);
9108 check_absolute_expr (ip, &imm_expr);
9109 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9110 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9111 if (imm_expr.X_add_number < min_range ||
9112 imm_expr.X_add_number > max_range)
9114 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9115 (long) min_range, (long) max_range,
9116 (long) imm_expr.X_add_number);
9118 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9119 imm_expr.X_op = O_absent;
9123 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9124 my_getExpression (&imm_expr, s);
9125 check_absolute_expr (ip, &imm_expr);
9126 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9128 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9130 (unsigned long) imm_expr.X_add_number);
9132 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9133 imm_expr.X_op = O_absent;
9137 case ':': /* DSP 7-bit signed immediate in bit 19. */
9138 my_getExpression (&imm_expr, s);
9139 check_absolute_expr (ip, &imm_expr);
9140 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9141 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9142 if (imm_expr.X_add_number < min_range ||
9143 imm_expr.X_add_number > max_range)
9145 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9146 (long) min_range, (long) max_range,
9147 (long) imm_expr.X_add_number);
9149 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9150 imm_expr.X_op = O_absent;
9154 case '@': /* DSP 10-bit signed immediate in bit 16. */
9155 my_getExpression (&imm_expr, s);
9156 check_absolute_expr (ip, &imm_expr);
9157 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9158 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9159 if (imm_expr.X_add_number < min_range ||
9160 imm_expr.X_add_number > max_range)
9162 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9163 (long) min_range, (long) max_range,
9164 (long) imm_expr.X_add_number);
9166 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9167 imm_expr.X_op = O_absent;
9171 case '!': /* MT usermode flag bit. */
9172 my_getExpression (&imm_expr, s);
9173 check_absolute_expr (ip, &imm_expr);
9174 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9175 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9176 (unsigned long) imm_expr.X_add_number);
9177 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9178 imm_expr.X_op = O_absent;
9182 case '$': /* MT load high flag bit. */
9183 my_getExpression (&imm_expr, s);
9184 check_absolute_expr (ip, &imm_expr);
9185 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9186 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9187 (unsigned long) imm_expr.X_add_number);
9188 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9189 imm_expr.X_op = O_absent;
9193 case '*': /* Four DSP accumulators in bits 18,19. */
9194 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9195 s[3] >= '0' && s[3] <= '3')
9199 INSERT_OPERAND (MTACC_T, *ip, regno);
9203 as_bad (_("Invalid dsp/smartmips acc register"));
9206 case '&': /* Four DSP accumulators in bits 13,14. */
9207 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9208 s[3] >= '0' && s[3] <= '3')
9212 INSERT_OPERAND (MTACC_D, *ip, regno);
9216 as_bad (_("Invalid dsp/smartmips acc register"));
9228 INSERT_OPERAND (RS, *ip, lastregno);
9232 INSERT_OPERAND (RT, *ip, lastregno);
9236 INSERT_OPERAND (FT, *ip, lastregno);
9240 INSERT_OPERAND (FS, *ip, lastregno);
9246 /* Handle optional base register.
9247 Either the base register is omitted or
9248 we must have a left paren. */
9249 /* This is dependent on the next operand specifier
9250 is a base register specification. */
9251 gas_assert (args[1] == 'b');
9255 case ')': /* These must match exactly. */
9262 case '+': /* Opcode extension character. */
9265 case '1': /* UDI immediates. */
9270 const struct mips_immed *imm = mips_immed;
9272 while (imm->type && imm->type != *args)
9276 my_getExpression (&imm_expr, s);
9277 check_absolute_expr (ip, &imm_expr);
9278 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9280 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9281 imm->desc ? imm->desc : ip->insn_mo->name,
9282 (unsigned long) imm_expr.X_add_number,
9283 (unsigned long) imm_expr.X_add_number);
9284 imm_expr.X_add_number &= imm->mask;
9286 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9288 imm_expr.X_op = O_absent;
9293 case 'A': /* ins/ext position, becomes LSB. */
9302 my_getExpression (&imm_expr, s);
9303 check_absolute_expr (ip, &imm_expr);
9304 if ((unsigned long) imm_expr.X_add_number < limlo
9305 || (unsigned long) imm_expr.X_add_number > limhi)
9307 as_bad (_("Improper position (%lu)"),
9308 (unsigned long) imm_expr.X_add_number);
9309 imm_expr.X_add_number = limlo;
9311 lastpos = imm_expr.X_add_number;
9312 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9313 imm_expr.X_op = O_absent;
9317 case 'B': /* ins size, becomes MSB. */
9326 my_getExpression (&imm_expr, s);
9327 check_absolute_expr (ip, &imm_expr);
9328 /* Check for negative input so that small negative numbers
9329 will not succeed incorrectly. The checks against
9330 (pos+size) transitively check "size" itself,
9331 assuming that "pos" is reasonable. */
9332 if ((long) imm_expr.X_add_number < 0
9333 || ((unsigned long) imm_expr.X_add_number
9335 || ((unsigned long) imm_expr.X_add_number
9338 as_bad (_("Improper insert size (%lu, position %lu)"),
9339 (unsigned long) imm_expr.X_add_number,
9340 (unsigned long) lastpos);
9341 imm_expr.X_add_number = limlo - lastpos;
9343 INSERT_OPERAND (INSMSB, *ip,
9344 lastpos + imm_expr.X_add_number - 1);
9345 imm_expr.X_op = O_absent;
9349 case 'C': /* ext size, becomes MSBD. */
9362 my_getExpression (&imm_expr, s);
9363 check_absolute_expr (ip, &imm_expr);
9364 /* Check for negative input so that small negative numbers
9365 will not succeed incorrectly. The checks against
9366 (pos+size) transitively check "size" itself,
9367 assuming that "pos" is reasonable. */
9368 if ((long) imm_expr.X_add_number < 0
9369 || ((unsigned long) imm_expr.X_add_number
9371 || ((unsigned long) imm_expr.X_add_number
9374 as_bad (_("Improper extract size (%lu, position %lu)"),
9375 (unsigned long) imm_expr.X_add_number,
9376 (unsigned long) lastpos);
9377 imm_expr.X_add_number = limlo - lastpos;
9379 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9380 imm_expr.X_op = O_absent;
9385 /* +D is for disassembly only; never match. */
9389 /* "+I" is like "I", except that imm2_expr is used. */
9390 my_getExpression (&imm2_expr, s);
9391 if (imm2_expr.X_op != O_big
9392 && imm2_expr.X_op != O_constant)
9393 insn_error = _("absolute expression required");
9394 if (HAVE_32BIT_GPRS)
9395 normalize_constant_expr (&imm2_expr);
9399 case 'T': /* Coprocessor register. */
9400 /* +T is for disassembly only; never match. */
9403 case 't': /* Coprocessor register number. */
9404 if (s[0] == '$' && ISDIGIT (s[1]))
9414 while (ISDIGIT (*s));
9416 as_bad (_("Invalid register number (%d)"), regno);
9419 INSERT_OPERAND (RT, *ip, regno);
9424 as_bad (_("Invalid coprocessor 0 register number"));
9428 /* bbit[01] and bbit[01]32 bit index. Give error if index
9429 is not in the valid range. */
9430 my_getExpression (&imm_expr, s);
9431 check_absolute_expr (ip, &imm_expr);
9432 if ((unsigned) imm_expr.X_add_number > 31)
9434 as_bad (_("Improper bit index (%lu)"),
9435 (unsigned long) imm_expr.X_add_number);
9436 imm_expr.X_add_number = 0;
9438 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9439 imm_expr.X_op = O_absent;
9444 /* bbit[01] bit index when bbit is used but we generate
9445 bbit[01]32 because the index is over 32. Move to the
9446 next candidate if index is not in the valid range. */
9447 my_getExpression (&imm_expr, s);
9448 check_absolute_expr (ip, &imm_expr);
9449 if ((unsigned) imm_expr.X_add_number < 32
9450 || (unsigned) imm_expr.X_add_number > 63)
9452 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9453 imm_expr.X_op = O_absent;
9458 /* cins, cins32, exts and exts32 position field. Give error
9459 if it's not in the valid range. */
9460 my_getExpression (&imm_expr, s);
9461 check_absolute_expr (ip, &imm_expr);
9462 if ((unsigned) imm_expr.X_add_number > 31)
9464 as_bad (_("Improper position (%lu)"),
9465 (unsigned long) imm_expr.X_add_number);
9466 imm_expr.X_add_number = 0;
9468 /* Make the pos explicit to simplify +S. */
9469 lastpos = imm_expr.X_add_number + 32;
9470 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9471 imm_expr.X_op = O_absent;
9476 /* cins, cins32, exts and exts32 position field. Move to
9477 the next candidate if it's not in the valid range. */
9478 my_getExpression (&imm_expr, s);
9479 check_absolute_expr (ip, &imm_expr);
9480 if ((unsigned) imm_expr.X_add_number < 32
9481 || (unsigned) imm_expr.X_add_number > 63)
9483 lastpos = imm_expr.X_add_number;
9484 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9485 imm_expr.X_op = O_absent;
9490 /* cins and exts length-minus-one field. */
9491 my_getExpression (&imm_expr, s);
9492 check_absolute_expr (ip, &imm_expr);
9493 if ((unsigned long) imm_expr.X_add_number > 31)
9495 as_bad (_("Improper size (%lu)"),
9496 (unsigned long) imm_expr.X_add_number);
9497 imm_expr.X_add_number = 0;
9499 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9500 imm_expr.X_op = O_absent;
9505 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9506 length-minus-one field. */
9507 my_getExpression (&imm_expr, s);
9508 check_absolute_expr (ip, &imm_expr);
9509 if ((long) imm_expr.X_add_number < 0
9510 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9512 as_bad (_("Improper size (%lu)"),
9513 (unsigned long) imm_expr.X_add_number);
9514 imm_expr.X_add_number = 0;
9516 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9517 imm_expr.X_op = O_absent;
9522 /* seqi/snei immediate field. */
9523 my_getExpression (&imm_expr, s);
9524 check_absolute_expr (ip, &imm_expr);
9525 if ((long) imm_expr.X_add_number < -512
9526 || (long) imm_expr.X_add_number >= 512)
9528 as_bad (_("Improper immediate (%ld)"),
9529 (long) imm_expr.X_add_number);
9530 imm_expr.X_add_number = 0;
9532 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9533 imm_expr.X_op = O_absent;
9537 case 'a': /* 8-bit signed offset in bit 6 */
9538 my_getExpression (&imm_expr, s);
9539 check_absolute_expr (ip, &imm_expr);
9540 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9541 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9542 if (imm_expr.X_add_number < min_range
9543 || imm_expr.X_add_number > max_range)
9545 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9546 (long) min_range, (long) max_range,
9547 (long) imm_expr.X_add_number);
9549 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9550 imm_expr.X_op = O_absent;
9554 case 'b': /* 8-bit signed offset in bit 3 */
9555 my_getExpression (&imm_expr, s);
9556 check_absolute_expr (ip, &imm_expr);
9557 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9558 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9559 if (imm_expr.X_add_number < min_range
9560 || imm_expr.X_add_number > max_range)
9562 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9563 (long) min_range, (long) max_range,
9564 (long) imm_expr.X_add_number);
9566 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9567 imm_expr.X_op = O_absent;
9571 case 'c': /* 9-bit signed offset in bit 6 */
9572 my_getExpression (&imm_expr, s);
9573 check_absolute_expr (ip, &imm_expr);
9574 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9575 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9576 /* We check the offset range before adjusted. */
9579 if (imm_expr.X_add_number < min_range
9580 || imm_expr.X_add_number > max_range)
9582 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9583 (long) min_range, (long) max_range,
9584 (long) imm_expr.X_add_number);
9586 if (imm_expr.X_add_number & 0xf)
9588 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9589 (long) imm_expr.X_add_number);
9591 /* Right shift 4 bits to adjust the offset operand. */
9592 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9593 imm_expr.X_op = O_absent;
9598 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9600 if (regno == AT && mips_opts.at)
9602 if (mips_opts.at == ATREG)
9603 as_warn (_("used $at without \".set noat\""));
9605 as_warn (_("used $%u with \".set at=$%u\""),
9606 regno, mips_opts.at);
9608 INSERT_OPERAND (RZ, *ip, regno);
9612 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9614 INSERT_OPERAND (FZ, *ip, regno);
9618 as_bad (_("Internal error: bad mips opcode "
9619 "(unknown extension operand type `+%c'): %s %s"),
9620 *args, insn->name, insn->args);
9621 /* Further processing is fruitless. */
9626 case '<': /* must be at least one digit */
9628 * According to the manual, if the shift amount is greater
9629 * than 31 or less than 0, then the shift amount should be
9630 * mod 32. In reality the mips assembler issues an error.
9631 * We issue a warning and mask out all but the low 5 bits.
9633 my_getExpression (&imm_expr, s);
9634 check_absolute_expr (ip, &imm_expr);
9635 if ((unsigned long) imm_expr.X_add_number > 31)
9636 as_warn (_("Improper shift amount (%lu)"),
9637 (unsigned long) imm_expr.X_add_number);
9638 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9639 imm_expr.X_op = O_absent;
9643 case '>': /* shift amount minus 32 */
9644 my_getExpression (&imm_expr, s);
9645 check_absolute_expr (ip, &imm_expr);
9646 if ((unsigned long) imm_expr.X_add_number < 32
9647 || (unsigned long) imm_expr.X_add_number > 63)
9649 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9650 imm_expr.X_op = O_absent;
9654 case 'k': /* CACHE code. */
9655 case 'h': /* PREFX code. */
9656 case '1': /* SYNC type. */
9657 my_getExpression (&imm_expr, s);
9658 check_absolute_expr (ip, &imm_expr);
9659 if ((unsigned long) imm_expr.X_add_number > 31)
9660 as_warn (_("Invalid value for `%s' (%lu)"),
9662 (unsigned long) imm_expr.X_add_number);
9665 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9666 switch (imm_expr.X_add_number)
9675 case 31: /* These are ok. */
9678 default: /* The rest must be changed to 28. */
9679 imm_expr.X_add_number = 28;
9682 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9684 else if (*args == 'h')
9685 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9687 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9688 imm_expr.X_op = O_absent;
9692 case 'c': /* BREAK code. */
9693 my_getExpression (&imm_expr, s);
9694 check_absolute_expr (ip, &imm_expr);
9695 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9696 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9698 (unsigned long) imm_expr.X_add_number);
9699 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9700 imm_expr.X_op = O_absent;
9704 case 'q': /* Lower BREAK code. */
9705 my_getExpression (&imm_expr, s);
9706 check_absolute_expr (ip, &imm_expr);
9707 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9708 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9710 (unsigned long) imm_expr.X_add_number);
9711 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9712 imm_expr.X_op = O_absent;
9716 case 'B': /* 20-bit SYSCALL/BREAK code. */
9717 my_getExpression (&imm_expr, s);
9718 check_absolute_expr (ip, &imm_expr);
9719 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9720 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9722 (unsigned long) imm_expr.X_add_number);
9723 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9724 imm_expr.X_op = O_absent;
9728 case 'C': /* Coprocessor code. */
9729 my_getExpression (&imm_expr, s);
9730 check_absolute_expr (ip, &imm_expr);
9731 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9733 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9734 (unsigned long) imm_expr.X_add_number);
9735 imm_expr.X_add_number &= OP_MASK_COPZ;
9737 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9738 imm_expr.X_op = O_absent;
9742 case 'J': /* 19-bit WAIT code. */
9743 my_getExpression (&imm_expr, s);
9744 check_absolute_expr (ip, &imm_expr);
9745 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9747 as_warn (_("Illegal 19-bit code (%lu)"),
9748 (unsigned long) imm_expr.X_add_number);
9749 imm_expr.X_add_number &= OP_MASK_CODE19;
9751 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9752 imm_expr.X_op = O_absent;
9756 case 'P': /* Performance register. */
9757 my_getExpression (&imm_expr, s);
9758 check_absolute_expr (ip, &imm_expr);
9759 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9760 as_warn (_("Invalid performance register (%lu)"),
9761 (unsigned long) imm_expr.X_add_number);
9762 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9763 imm_expr.X_op = O_absent;
9767 case 'G': /* Coprocessor destination register. */
9768 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9769 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9771 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9772 INSERT_OPERAND (RD, *ip, regno);
9781 case 'b': /* Base register. */
9782 case 'd': /* Destination register. */
9783 case 's': /* Source register. */
9784 case 't': /* Target register. */
9785 case 'r': /* Both target and source. */
9786 case 'v': /* Both dest and source. */
9787 case 'w': /* Both dest and target. */
9788 case 'E': /* Coprocessor target register. */
9789 case 'K': /* RDHWR destination register. */
9790 case 'x': /* Ignore register name. */
9791 case 'z': /* Must be zero register. */
9792 case 'U': /* Destination register (CLO/CLZ). */
9793 case 'g': /* Coprocessor destination register. */
9795 if (*args == 'E' || *args == 'K')
9796 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9799 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9800 if (regno == AT && mips_opts.at)
9802 if (mips_opts.at == ATREG)
9803 as_warn (_("Used $at without \".set noat\""));
9805 as_warn (_("Used $%u with \".set at=$%u\""),
9806 regno, mips_opts.at);
9816 if (c == 'r' || c == 'v' || c == 'w')
9823 /* 'z' only matches $0. */
9824 if (c == 'z' && regno != 0)
9827 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9829 if (regno == lastregno)
9832 = _("Source and destination must be different");
9835 if (regno == 31 && lastregno == 0xffffffff)
9838 = _("A destination register must be supplied");
9842 /* Now that we have assembled one operand, we use the args
9843 string to figure out where it goes in the instruction. */
9850 INSERT_OPERAND (RS, *ip, regno);
9855 INSERT_OPERAND (RD, *ip, regno);
9858 INSERT_OPERAND (RD, *ip, regno);
9859 INSERT_OPERAND (RT, *ip, regno);
9864 INSERT_OPERAND (RT, *ip, regno);
9867 /* This case exists because on the r3000 trunc
9868 expands into a macro which requires a gp
9869 register. On the r6000 or r4000 it is
9870 assembled into a single instruction which
9871 ignores the register. Thus the insn version
9872 is MIPS_ISA2 and uses 'x', and the macro
9873 version is MIPS_ISA1 and uses 't'. */
9876 /* This case is for the div instruction, which
9877 acts differently if the destination argument
9878 is $0. This only matches $0, and is checked
9879 outside the switch. */
9889 INSERT_OPERAND (RS, *ip, lastregno);
9892 INSERT_OPERAND (RT, *ip, lastregno);
9897 case 'O': /* MDMX alignment immediate constant. */
9898 my_getExpression (&imm_expr, s);
9899 check_absolute_expr (ip, &imm_expr);
9900 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9901 as_warn (_("Improper align amount (%ld), using low bits"),
9902 (long) imm_expr.X_add_number);
9903 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9904 imm_expr.X_op = O_absent;
9908 case 'Q': /* MDMX vector, element sel, or const. */
9911 /* MDMX Immediate. */
9912 my_getExpression (&imm_expr, s);
9913 check_absolute_expr (ip, &imm_expr);
9914 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9915 as_warn (_("Invalid MDMX Immediate (%ld)"),
9916 (long) imm_expr.X_add_number);
9917 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9918 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9919 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9921 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9922 imm_expr.X_op = O_absent;
9926 /* Not MDMX Immediate. Fall through. */
9927 case 'X': /* MDMX destination register. */
9928 case 'Y': /* MDMX source register. */
9929 case 'Z': /* MDMX target register. */
9931 case 'D': /* Floating point destination register. */
9932 case 'S': /* Floating point source register. */
9933 case 'T': /* Floating point target register. */
9934 case 'R': /* Floating point source register. */
9939 || (mips_opts.ase_mdmx
9940 && (ip->insn_mo->pinfo & FP_D)
9941 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9942 | INSN_COPROC_MEMORY_DELAY
9943 | INSN_LOAD_COPROC_DELAY
9944 | INSN_LOAD_MEMORY_DELAY
9945 | INSN_STORE_MEMORY))))
9948 if (reg_lookup (&s, rtype, ®no))
9950 if ((regno & 1) != 0
9952 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
9953 as_warn (_("Float register should be even, was %d"),
9961 if (c == 'V' || c == 'W')
9972 INSERT_OPERAND (FD, *ip, regno);
9977 INSERT_OPERAND (FS, *ip, regno);
9980 /* This is like 'Z', but also needs to fix the MDMX
9981 vector/scalar select bits. Note that the
9982 scalar immediate case is handled above. */
9985 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
9986 int max_el = (is_qh ? 3 : 7);
9988 my_getExpression(&imm_expr, s);
9989 check_absolute_expr (ip, &imm_expr);
9991 if (imm_expr.X_add_number > max_el)
9992 as_bad (_("Bad element selector %ld"),
9993 (long) imm_expr.X_add_number);
9994 imm_expr.X_add_number &= max_el;
9995 ip->insn_opcode |= (imm_expr.X_add_number
9998 imm_expr.X_op = O_absent;
10000 as_warn (_("Expecting ']' found '%s'"), s);
10006 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10007 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10010 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10013 /* Fall through. */
10017 INSERT_OPERAND (FT, *ip, regno);
10020 INSERT_OPERAND (FR, *ip, regno);
10030 INSERT_OPERAND (FS, *ip, lastregno);
10033 INSERT_OPERAND (FT, *ip, lastregno);
10039 my_getExpression (&imm_expr, s);
10040 if (imm_expr.X_op != O_big
10041 && imm_expr.X_op != O_constant)
10042 insn_error = _("absolute expression required");
10043 if (HAVE_32BIT_GPRS)
10044 normalize_constant_expr (&imm_expr);
10049 my_getExpression (&offset_expr, s);
10050 normalize_address_expr (&offset_expr);
10051 *imm_reloc = BFD_RELOC_32;
10064 unsigned char temp[8];
10066 unsigned int length;
10071 /* These only appear as the last operand in an
10072 instruction, and every instruction that accepts
10073 them in any variant accepts them in all variants.
10074 This means we don't have to worry about backing out
10075 any changes if the instruction does not match.
10077 The difference between them is the size of the
10078 floating point constant and where it goes. For 'F'
10079 and 'L' the constant is 64 bits; for 'f' and 'l' it
10080 is 32 bits. Where the constant is placed is based
10081 on how the MIPS assembler does things:
10084 f -- immediate value
10087 The .lit4 and .lit8 sections are only used if
10088 permitted by the -G argument.
10090 The code below needs to know whether the target register
10091 is 32 or 64 bits wide. It relies on the fact 'f' and
10092 'F' are used with GPR-based instructions and 'l' and
10093 'L' are used with FPR-based instructions. */
10095 f64 = *args == 'F' || *args == 'L';
10096 using_gprs = *args == 'F' || *args == 'f';
10098 save_in = input_line_pointer;
10099 input_line_pointer = s;
10100 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10102 s = input_line_pointer;
10103 input_line_pointer = save_in;
10104 if (err != NULL && *err != '\0')
10106 as_bad (_("Bad floating point constant: %s"), err);
10107 memset (temp, '\0', sizeof temp);
10108 length = f64 ? 8 : 4;
10111 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10115 && (g_switch_value < 4
10116 || (temp[0] == 0 && temp[1] == 0)
10117 || (temp[2] == 0 && temp[3] == 0))))
10119 imm_expr.X_op = O_constant;
10120 if (!target_big_endian)
10121 imm_expr.X_add_number = bfd_getl32 (temp);
10123 imm_expr.X_add_number = bfd_getb32 (temp);
10125 else if (length > 4
10126 && !mips_disable_float_construction
10127 /* Constants can only be constructed in GPRs and
10128 copied to FPRs if the GPRs are at least as wide
10129 as the FPRs. Force the constant into memory if
10130 we are using 64-bit FPRs but the GPRs are only
10133 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10134 && ((temp[0] == 0 && temp[1] == 0)
10135 || (temp[2] == 0 && temp[3] == 0))
10136 && ((temp[4] == 0 && temp[5] == 0)
10137 || (temp[6] == 0 && temp[7] == 0)))
10139 /* The value is simple enough to load with a couple of
10140 instructions. If using 32-bit registers, set
10141 imm_expr to the high order 32 bits and offset_expr to
10142 the low order 32 bits. Otherwise, set imm_expr to
10143 the entire 64 bit constant. */
10144 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10146 imm_expr.X_op = O_constant;
10147 offset_expr.X_op = O_constant;
10148 if (!target_big_endian)
10150 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10151 offset_expr.X_add_number = bfd_getl32 (temp);
10155 imm_expr.X_add_number = bfd_getb32 (temp);
10156 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10158 if (offset_expr.X_add_number == 0)
10159 offset_expr.X_op = O_absent;
10161 else if (sizeof (imm_expr.X_add_number) > 4)
10163 imm_expr.X_op = O_constant;
10164 if (!target_big_endian)
10165 imm_expr.X_add_number = bfd_getl64 (temp);
10167 imm_expr.X_add_number = bfd_getb64 (temp);
10171 imm_expr.X_op = O_big;
10172 imm_expr.X_add_number = 4;
10173 if (!target_big_endian)
10175 generic_bignum[0] = bfd_getl16 (temp);
10176 generic_bignum[1] = bfd_getl16 (temp + 2);
10177 generic_bignum[2] = bfd_getl16 (temp + 4);
10178 generic_bignum[3] = bfd_getl16 (temp + 6);
10182 generic_bignum[0] = bfd_getb16 (temp + 6);
10183 generic_bignum[1] = bfd_getb16 (temp + 4);
10184 generic_bignum[2] = bfd_getb16 (temp + 2);
10185 generic_bignum[3] = bfd_getb16 (temp);
10191 const char *newname;
10194 /* Switch to the right section. */
10196 subseg = now_subseg;
10199 default: /* unused default case avoids warnings. */
10201 newname = RDATA_SECTION_NAME;
10202 if (g_switch_value >= 8)
10206 newname = RDATA_SECTION_NAME;
10209 gas_assert (g_switch_value >= 4);
10213 new_seg = subseg_new (newname, (subsegT) 0);
10215 bfd_set_section_flags (stdoutput, new_seg,
10220 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10221 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10222 record_alignment (new_seg, 4);
10224 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10225 if (seg == now_seg)
10226 as_bad (_("Can't use floating point insn in this section"));
10228 /* Set the argument to the current address in the
10230 offset_expr.X_op = O_symbol;
10231 offset_expr.X_add_symbol = symbol_temp_new_now ();
10232 offset_expr.X_add_number = 0;
10234 /* Put the floating point number into the section. */
10235 p = frag_more ((int) length);
10236 memcpy (p, temp, length);
10238 /* Switch back to the original section. */
10239 subseg_set (seg, subseg);
10244 case 'i': /* 16-bit unsigned immediate. */
10245 case 'j': /* 16-bit signed immediate. */
10246 *imm_reloc = BFD_RELOC_LO16;
10247 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10250 offsetT minval, maxval;
10252 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10253 && strcmp (insn->name, insn[1].name) == 0);
10255 /* If the expression was written as an unsigned number,
10256 only treat it as signed if there are no more
10260 && sizeof (imm_expr.X_add_number) <= 4
10261 && imm_expr.X_op == O_constant
10262 && imm_expr.X_add_number < 0
10263 && imm_expr.X_unsigned
10264 && HAVE_64BIT_GPRS)
10267 /* For compatibility with older assemblers, we accept
10268 0x8000-0xffff as signed 16-bit numbers when only
10269 signed numbers are allowed. */
10271 minval = 0, maxval = 0xffff;
10273 minval = -0x8000, maxval = 0x7fff;
10275 minval = -0x8000, maxval = 0xffff;
10277 if (imm_expr.X_op != O_constant
10278 || imm_expr.X_add_number < minval
10279 || imm_expr.X_add_number > maxval)
10283 if (imm_expr.X_op == O_constant
10284 || imm_expr.X_op == O_big)
10285 as_bad (_("Expression out of range"));
10291 case 'o': /* 16-bit offset. */
10292 offset_reloc[0] = BFD_RELOC_LO16;
10293 offset_reloc[1] = BFD_RELOC_UNUSED;
10294 offset_reloc[2] = BFD_RELOC_UNUSED;
10296 /* Check whether there is only a single bracketed expression
10297 left. If so, it must be the base register and the
10298 constant must be zero. */
10299 if (*s == '(' && strchr (s + 1, '(') == 0)
10301 offset_expr.X_op = O_constant;
10302 offset_expr.X_add_number = 0;
10306 /* If this value won't fit into a 16 bit offset, then go
10307 find a macro that will generate the 32 bit offset
10309 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10310 && (offset_expr.X_op != O_constant
10311 || offset_expr.X_add_number >= 0x8000
10312 || offset_expr.X_add_number < -0x8000))
10318 case 'p': /* PC-relative offset. */
10319 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10320 my_getExpression (&offset_expr, s);
10324 case 'u': /* Upper 16 bits. */
10325 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10326 && imm_expr.X_op == O_constant
10327 && (imm_expr.X_add_number < 0
10328 || imm_expr.X_add_number >= 0x10000))
10329 as_bad (_("lui expression (%lu) not in range 0..65535"),
10330 (unsigned long) imm_expr.X_add_number);
10334 case 'a': /* 26-bit address. */
10335 my_getExpression (&offset_expr, s);
10337 *offset_reloc = BFD_RELOC_MIPS_JMP;
10340 case 'N': /* 3-bit branch condition code. */
10341 case 'M': /* 3-bit compare condition code. */
10343 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10344 rtype |= RTYPE_FCC;
10345 if (!reg_lookup (&s, rtype, ®no))
10347 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10348 || strcmp (str + strlen (str) - 5, "any2f") == 0
10349 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10350 && (regno & 1) != 0)
10351 as_warn (_("Condition code register should be even for %s, "
10354 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10355 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10356 && (regno & 3) != 0)
10357 as_warn (_("Condition code register should be 0 or 4 for %s, "
10361 INSERT_OPERAND (BCC, *ip, regno);
10363 INSERT_OPERAND (CCC, *ip, regno);
10367 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10378 while (ISDIGIT (*s));
10381 c = 8; /* Invalid sel value. */
10384 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10385 ip->insn_opcode |= c;
10389 /* Must be at least one digit. */
10390 my_getExpression (&imm_expr, s);
10391 check_absolute_expr (ip, &imm_expr);
10393 if ((unsigned long) imm_expr.X_add_number
10394 > (unsigned long) OP_MASK_VECBYTE)
10396 as_bad (_("bad byte vector index (%ld)"),
10397 (long) imm_expr.X_add_number);
10398 imm_expr.X_add_number = 0;
10401 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10402 imm_expr.X_op = O_absent;
10407 my_getExpression (&imm_expr, s);
10408 check_absolute_expr (ip, &imm_expr);
10410 if ((unsigned long) imm_expr.X_add_number
10411 > (unsigned long) OP_MASK_VECALIGN)
10413 as_bad (_("bad byte vector index (%ld)"),
10414 (long) imm_expr.X_add_number);
10415 imm_expr.X_add_number = 0;
10418 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10419 imm_expr.X_op = O_absent;
10424 as_bad (_("Bad char = '%c'\n"), *args);
10429 /* Args don't match. */
10430 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10431 !strcmp (insn->name, insn[1].name))
10435 insn_error = _("Illegal operands");
10439 *(--argsStart) = save_c;
10440 insn_error = _("Illegal operands");
10445 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10447 /* This routine assembles an instruction into its binary format when
10448 assembling for the mips16. As a side effect, it sets one of the
10449 global variables imm_reloc or offset_reloc to the type of
10450 relocation to do if one of the operands is an address expression.
10451 It also sets mips16_small and mips16_ext if the user explicitly
10452 requested a small or extended instruction. */
10455 mips16_ip (char *str, struct mips_cl_insn *ip)
10459 struct mips_opcode *insn;
10461 unsigned int regno;
10462 unsigned int lastregno = 0;
10468 mips16_small = FALSE;
10469 mips16_ext = FALSE;
10471 for (s = str; ISLOWER (*s); ++s)
10483 if (s[1] == 't' && s[2] == ' ')
10486 mips16_small = TRUE;
10490 else if (s[1] == 'e' && s[2] == ' ')
10497 /* Fall through. */
10499 insn_error = _("unknown opcode");
10503 if (mips_opts.noautoextend && ! mips16_ext)
10504 mips16_small = TRUE;
10506 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10508 insn_error = _("unrecognized opcode");
10517 gas_assert (strcmp (insn->name, str) == 0);
10519 ok = is_opcode_valid_16 (insn);
10522 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10523 && strcmp (insn->name, insn[1].name) == 0)
10532 static char buf[100];
10534 _("opcode not supported on this processor: %s (%s)"),
10535 mips_cpu_info_from_arch (mips_opts.arch)->name,
10536 mips_cpu_info_from_isa (mips_opts.isa)->name);
10543 create_insn (ip, insn);
10544 imm_expr.X_op = O_absent;
10545 imm_reloc[0] = BFD_RELOC_UNUSED;
10546 imm_reloc[1] = BFD_RELOC_UNUSED;
10547 imm_reloc[2] = BFD_RELOC_UNUSED;
10548 imm2_expr.X_op = O_absent;
10549 offset_expr.X_op = O_absent;
10550 offset_reloc[0] = BFD_RELOC_UNUSED;
10551 offset_reloc[1] = BFD_RELOC_UNUSED;
10552 offset_reloc[2] = BFD_RELOC_UNUSED;
10553 for (args = insn->args; 1; ++args)
10560 /* In this switch statement we call break if we did not find
10561 a match, continue if we did find a match, or return if we
10570 /* Stuff the immediate value in now, if we can. */
10571 if (imm_expr.X_op == O_constant
10572 && *imm_reloc > BFD_RELOC_UNUSED
10573 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10574 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10575 && insn->pinfo != INSN_MACRO)
10579 switch (*offset_reloc)
10581 case BFD_RELOC_MIPS16_HI16_S:
10582 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10585 case BFD_RELOC_MIPS16_HI16:
10586 tmp = imm_expr.X_add_number >> 16;
10589 case BFD_RELOC_MIPS16_LO16:
10590 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10594 case BFD_RELOC_UNUSED:
10595 tmp = imm_expr.X_add_number;
10601 *offset_reloc = BFD_RELOC_UNUSED;
10603 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10604 tmp, TRUE, mips16_small,
10605 mips16_ext, &ip->insn_opcode,
10606 &ip->use_extend, &ip->extend);
10607 imm_expr.X_op = O_absent;
10608 *imm_reloc = BFD_RELOC_UNUSED;
10622 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10625 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10641 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10643 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10647 /* Fall through. */
10658 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10660 if (c == 'v' || c == 'w')
10663 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10665 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10676 if (c == 'v' || c == 'w')
10678 regno = mips16_to_32_reg_map[lastregno];
10692 regno = mips32_to_16_reg_map[regno];
10697 regno = ILLEGAL_REG;
10702 regno = ILLEGAL_REG;
10707 regno = ILLEGAL_REG;
10712 if (regno == AT && mips_opts.at)
10714 if (mips_opts.at == ATREG)
10715 as_warn (_("used $at without \".set noat\""));
10717 as_warn (_("used $%u with \".set at=$%u\""),
10718 regno, mips_opts.at);
10726 if (regno == ILLEGAL_REG)
10733 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10737 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10740 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10743 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10749 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10752 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10753 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10763 if (strncmp (s, "$pc", 3) == 0)
10780 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10783 if (imm_expr.X_op != O_constant)
10786 ip->use_extend = TRUE;
10791 /* We need to relax this instruction. */
10792 *offset_reloc = *imm_reloc;
10793 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10798 *imm_reloc = BFD_RELOC_UNUSED;
10799 /* Fall through. */
10806 my_getExpression (&imm_expr, s);
10807 if (imm_expr.X_op == O_register)
10809 /* What we thought was an expression turned out to
10812 if (s[0] == '(' && args[1] == '(')
10814 /* It looks like the expression was omitted
10815 before a register indirection, which means
10816 that the expression is implicitly zero. We
10817 still set up imm_expr, so that we handle
10818 explicit extensions correctly. */
10819 imm_expr.X_op = O_constant;
10820 imm_expr.X_add_number = 0;
10821 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10828 /* We need to relax this instruction. */
10829 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10838 /* We use offset_reloc rather than imm_reloc for the PC
10839 relative operands. This lets macros with both
10840 immediate and address operands work correctly. */
10841 my_getExpression (&offset_expr, s);
10843 if (offset_expr.X_op == O_register)
10846 /* We need to relax this instruction. */
10847 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10851 case '6': /* break code */
10852 my_getExpression (&imm_expr, s);
10853 check_absolute_expr (ip, &imm_expr);
10854 if ((unsigned long) imm_expr.X_add_number > 63)
10855 as_warn (_("Invalid value for `%s' (%lu)"),
10857 (unsigned long) imm_expr.X_add_number);
10858 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10859 imm_expr.X_op = O_absent;
10863 case 'a': /* 26 bit address */
10864 my_getExpression (&offset_expr, s);
10866 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10867 ip->insn_opcode <<= 16;
10870 case 'l': /* register list for entry macro */
10871 case 'L': /* register list for exit macro */
10881 unsigned int freg, reg1, reg2;
10883 while (*s == ' ' || *s == ',')
10885 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10887 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10891 as_bad (_("can't parse register list"));
10901 if (!reg_lookup (&s, freg ? RTYPE_FPU
10902 : (RTYPE_GP | RTYPE_NUM), ®2))
10904 as_bad (_("invalid register list"));
10908 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10910 mask &= ~ (7 << 3);
10913 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10915 mask &= ~ (7 << 3);
10918 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10919 mask |= (reg2 - 3) << 3;
10920 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10921 mask |= (reg2 - 15) << 1;
10922 else if (reg1 == RA && reg2 == RA)
10926 as_bad (_("invalid register list"));
10930 /* The mask is filled in in the opcode table for the
10931 benefit of the disassembler. We remove it before
10932 applying the actual mask. */
10933 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10934 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10938 case 'm': /* Register list for save insn. */
10939 case 'M': /* Register list for restore insn. */
10942 int framesz = 0, seen_framesz = 0;
10943 int nargs = 0, statics = 0, sregs = 0;
10947 unsigned int reg1, reg2;
10949 SKIP_SPACE_TABS (s);
10952 SKIP_SPACE_TABS (s);
10954 my_getExpression (&imm_expr, s);
10955 if (imm_expr.X_op == O_constant)
10957 /* Handle the frame size. */
10960 as_bad (_("more than one frame size in list"));
10964 framesz = imm_expr.X_add_number;
10965 imm_expr.X_op = O_absent;
10970 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10972 as_bad (_("can't parse register list"));
10984 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
10987 as_bad (_("can't parse register list"));
10992 while (reg1 <= reg2)
10994 if (reg1 >= 4 && reg1 <= 7)
10998 nargs |= 1 << (reg1 - 4);
11000 /* statics $a0-$a3 */
11001 statics |= 1 << (reg1 - 4);
11003 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11006 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11008 else if (reg1 == 31)
11010 /* Add $ra to insn. */
11015 as_bad (_("unexpected register in list"));
11023 /* Encode args/statics combination. */
11024 if (nargs & statics)
11025 as_bad (_("arg/static registers overlap"));
11026 else if (nargs == 0xf)
11027 /* All $a0-$a3 are args. */
11028 opcode |= MIPS16_ALL_ARGS << 16;
11029 else if (statics == 0xf)
11030 /* All $a0-$a3 are statics. */
11031 opcode |= MIPS16_ALL_STATICS << 16;
11034 int narg = 0, nstat = 0;
11036 /* Count arg registers. */
11037 while (nargs & 0x1)
11043 as_bad (_("invalid arg register list"));
11045 /* Count static registers. */
11046 while (statics & 0x8)
11048 statics = (statics << 1) & 0xf;
11052 as_bad (_("invalid static register list"));
11054 /* Encode args/statics. */
11055 opcode |= ((narg << 2) | nstat) << 16;
11058 /* Encode $s0/$s1. */
11059 if (sregs & (1 << 0)) /* $s0 */
11061 if (sregs & (1 << 1)) /* $s1 */
11067 /* Count regs $s2-$s8. */
11075 as_bad (_("invalid static register list"));
11076 /* Encode $s2-$s8. */
11077 opcode |= nsreg << 24;
11080 /* Encode frame size. */
11082 as_bad (_("missing frame size"));
11083 else if ((framesz & 7) != 0 || framesz < 0
11084 || framesz > 0xff * 8)
11085 as_bad (_("invalid frame size"));
11086 else if (framesz != 128 || (opcode >> 16) != 0)
11089 opcode |= (((framesz & 0xf0) << 16)
11090 | (framesz & 0x0f));
11093 /* Finally build the instruction. */
11094 if ((opcode >> 16) != 0 || framesz == 0)
11096 ip->use_extend = TRUE;
11097 ip->extend = opcode >> 16;
11099 ip->insn_opcode |= opcode & 0x7f;
11103 case 'e': /* extend code */
11104 my_getExpression (&imm_expr, s);
11105 check_absolute_expr (ip, &imm_expr);
11106 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11108 as_warn (_("Invalid value for `%s' (%lu)"),
11110 (unsigned long) imm_expr.X_add_number);
11111 imm_expr.X_add_number &= 0x7ff;
11113 ip->insn_opcode |= imm_expr.X_add_number;
11114 imm_expr.X_op = O_absent;
11124 /* Args don't match. */
11125 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11126 strcmp (insn->name, insn[1].name) == 0)
11133 insn_error = _("illegal operands");
11139 /* This structure holds information we know about a mips16 immediate
11142 struct mips16_immed_operand
11144 /* The type code used in the argument string in the opcode table. */
11146 /* The number of bits in the short form of the opcode. */
11148 /* The number of bits in the extended form of the opcode. */
11150 /* The amount by which the short form is shifted when it is used;
11151 for example, the sw instruction has a shift count of 2. */
11153 /* The amount by which the short form is shifted when it is stored
11154 into the instruction code. */
11156 /* Non-zero if the short form is unsigned. */
11158 /* Non-zero if the extended form is unsigned. */
11160 /* Non-zero if the value is PC relative. */
11164 /* The mips16 immediate operand types. */
11166 static const struct mips16_immed_operand mips16_immed_operands[] =
11168 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11169 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11170 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11171 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11172 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11173 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11174 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11175 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11176 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11177 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11178 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11179 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11180 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11181 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11182 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11183 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11184 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11185 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11186 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11187 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11188 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11191 #define MIPS16_NUM_IMMED \
11192 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11194 /* Handle a mips16 instruction with an immediate value. This or's the
11195 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11196 whether an extended value is needed; if one is needed, it sets
11197 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11198 If SMALL is true, an unextended opcode was explicitly requested.
11199 If EXT is true, an extended opcode was explicitly requested. If
11200 WARN is true, warn if EXT does not match reality. */
11203 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11204 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11205 unsigned long *insn, bfd_boolean *use_extend,
11206 unsigned short *extend)
11208 const struct mips16_immed_operand *op;
11209 int mintiny, maxtiny;
11210 bfd_boolean needext;
11212 op = mips16_immed_operands;
11213 while (op->type != type)
11216 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11221 if (type == '<' || type == '>' || type == '[' || type == ']')
11224 maxtiny = 1 << op->nbits;
11229 maxtiny = (1 << op->nbits) - 1;
11234 mintiny = - (1 << (op->nbits - 1));
11235 maxtiny = (1 << (op->nbits - 1)) - 1;
11238 /* Branch offsets have an implicit 0 in the lowest bit. */
11239 if (type == 'p' || type == 'q')
11242 if ((val & ((1 << op->shift) - 1)) != 0
11243 || val < (mintiny << op->shift)
11244 || val > (maxtiny << op->shift))
11249 if (warn && ext && ! needext)
11250 as_warn_where (file, line,
11251 _("extended operand requested but not required"));
11252 if (small && needext)
11253 as_bad_where (file, line, _("invalid unextended operand value"));
11255 if (small || (! ext && ! needext))
11259 *use_extend = FALSE;
11260 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11261 insnval <<= op->op_shift;
11266 long minext, maxext;
11272 maxext = (1 << op->extbits) - 1;
11276 minext = - (1 << (op->extbits - 1));
11277 maxext = (1 << (op->extbits - 1)) - 1;
11279 if (val < minext || val > maxext)
11280 as_bad_where (file, line,
11281 _("operand value out of range for instruction"));
11283 *use_extend = TRUE;
11284 if (op->extbits == 16)
11286 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11289 else if (op->extbits == 15)
11291 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11296 extval = ((val & 0x1f) << 6) | (val & 0x20);
11300 *extend = (unsigned short) extval;
11305 struct percent_op_match
11308 bfd_reloc_code_real_type reloc;
11311 static const struct percent_op_match mips_percent_op[] =
11313 {"%lo", BFD_RELOC_LO16},
11315 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11316 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11317 {"%call16", BFD_RELOC_MIPS_CALL16},
11318 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11319 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11320 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11321 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11322 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11323 {"%got", BFD_RELOC_MIPS_GOT16},
11324 {"%gp_rel", BFD_RELOC_GPREL16},
11325 {"%half", BFD_RELOC_16},
11326 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11327 {"%higher", BFD_RELOC_MIPS_HIGHER},
11328 {"%neg", BFD_RELOC_MIPS_SUB},
11329 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11330 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11331 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11332 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11333 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11334 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11335 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11337 {"%hi", BFD_RELOC_HI16_S}
11340 static const struct percent_op_match mips16_percent_op[] =
11342 {"%lo", BFD_RELOC_MIPS16_LO16},
11343 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11344 {"%got", BFD_RELOC_MIPS16_GOT16},
11345 {"%call16", BFD_RELOC_MIPS16_CALL16},
11346 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11350 /* Return true if *STR points to a relocation operator. When returning true,
11351 move *STR over the operator and store its relocation code in *RELOC.
11352 Leave both *STR and *RELOC alone when returning false. */
11355 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11357 const struct percent_op_match *percent_op;
11360 if (mips_opts.mips16)
11362 percent_op = mips16_percent_op;
11363 limit = ARRAY_SIZE (mips16_percent_op);
11367 percent_op = mips_percent_op;
11368 limit = ARRAY_SIZE (mips_percent_op);
11371 for (i = 0; i < limit; i++)
11372 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11374 int len = strlen (percent_op[i].str);
11376 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11379 *str += strlen (percent_op[i].str);
11380 *reloc = percent_op[i].reloc;
11382 /* Check whether the output BFD supports this relocation.
11383 If not, issue an error and fall back on something safe. */
11384 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11386 as_bad (_("relocation %s isn't supported by the current ABI"),
11387 percent_op[i].str);
11388 *reloc = BFD_RELOC_UNUSED;
11396 /* Parse string STR as a 16-bit relocatable operand. Store the
11397 expression in *EP and the relocations in the array starting
11398 at RELOC. Return the number of relocation operators used.
11400 On exit, EXPR_END points to the first character after the expression. */
11403 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11406 bfd_reloc_code_real_type reversed_reloc[3];
11407 size_t reloc_index, i;
11408 int crux_depth, str_depth;
11411 /* Search for the start of the main expression, recoding relocations
11412 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11413 of the main expression and with CRUX_DEPTH containing the number
11414 of open brackets at that point. */
11421 crux_depth = str_depth;
11423 /* Skip over whitespace and brackets, keeping count of the number
11425 while (*str == ' ' || *str == '\t' || *str == '(')
11430 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11431 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11433 my_getExpression (ep, crux);
11436 /* Match every open bracket. */
11437 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11441 if (crux_depth > 0)
11442 as_bad (_("unclosed '('"));
11446 if (reloc_index != 0)
11448 prev_reloc_op_frag = frag_now;
11449 for (i = 0; i < reloc_index; i++)
11450 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11453 return reloc_index;
11457 my_getExpression (expressionS *ep, char *str)
11461 save_in = input_line_pointer;
11462 input_line_pointer = str;
11464 expr_end = input_line_pointer;
11465 input_line_pointer = save_in;
11469 md_atof (int type, char *litP, int *sizeP)
11471 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11475 md_number_to_chars (char *buf, valueT val, int n)
11477 if (target_big_endian)
11478 number_to_chars_bigendian (buf, val, n);
11480 number_to_chars_littleendian (buf, val, n);
11484 static int support_64bit_objects(void)
11486 const char **list, **l;
11489 list = bfd_target_list ();
11490 for (l = list; *l != NULL; l++)
11491 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11492 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11494 yes = (*l != NULL);
11498 #endif /* OBJ_ELF */
11500 const char *md_shortopts = "O::g::G:";
11504 OPTION_MARCH = OPTION_MD_BASE,
11526 OPTION_NO_SMARTMIPS,
11529 OPTION_COMPAT_ARCH_BASE,
11538 OPTION_M7000_HILO_FIX,
11539 OPTION_MNO_7000_HILO_FIX,
11542 OPTION_FIX_LOONGSON2F_JUMP,
11543 OPTION_NO_FIX_LOONGSON2F_JUMP,
11544 OPTION_FIX_LOONGSON2F_NOP,
11545 OPTION_NO_FIX_LOONGSON2F_NOP,
11547 OPTION_NO_FIX_VR4120,
11549 OPTION_NO_FIX_VR4130,
11550 OPTION_FIX_CN63XXP1,
11551 OPTION_NO_FIX_CN63XXP1,
11558 OPTION_CONSTRUCT_FLOATS,
11559 OPTION_NO_CONSTRUCT_FLOATS,
11562 OPTION_RELAX_BRANCH,
11563 OPTION_NO_RELAX_BRANCH,
11570 OPTION_SINGLE_FLOAT,
11571 OPTION_DOUBLE_FLOAT,
11574 OPTION_CALL_SHARED,
11575 OPTION_CALL_NONPIC,
11585 OPTION_MVXWORKS_PIC,
11586 #endif /* OBJ_ELF */
11590 struct option md_longopts[] =
11592 /* Options which specify architecture. */
11593 {"march", required_argument, NULL, OPTION_MARCH},
11594 {"mtune", required_argument, NULL, OPTION_MTUNE},
11595 {"mips0", no_argument, NULL, OPTION_MIPS1},
11596 {"mips1", no_argument, NULL, OPTION_MIPS1},
11597 {"mips2", no_argument, NULL, OPTION_MIPS2},
11598 {"mips3", no_argument, NULL, OPTION_MIPS3},
11599 {"mips4", no_argument, NULL, OPTION_MIPS4},
11600 {"mips5", no_argument, NULL, OPTION_MIPS5},
11601 {"mips32", no_argument, NULL, OPTION_MIPS32},
11602 {"mips64", no_argument, NULL, OPTION_MIPS64},
11603 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11604 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11606 /* Options which specify Application Specific Extensions (ASEs). */
11607 {"mips16", no_argument, NULL, OPTION_MIPS16},
11608 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11609 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11610 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11611 {"mdmx", no_argument, NULL, OPTION_MDMX},
11612 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11613 {"mdsp", no_argument, NULL, OPTION_DSP},
11614 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11615 {"mmt", no_argument, NULL, OPTION_MT},
11616 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11617 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11618 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11619 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11620 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11622 /* Old-style architecture options. Don't add more of these. */
11623 {"m4650", no_argument, NULL, OPTION_M4650},
11624 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11625 {"m4010", no_argument, NULL, OPTION_M4010},
11626 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11627 {"m4100", no_argument, NULL, OPTION_M4100},
11628 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11629 {"m3900", no_argument, NULL, OPTION_M3900},
11630 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11632 /* Options which enable bug fixes. */
11633 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11634 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11635 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11636 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11637 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11638 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11639 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11640 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11641 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11642 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11643 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11644 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11645 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11646 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11647 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11649 /* Miscellaneous options. */
11650 {"trap", no_argument, NULL, OPTION_TRAP},
11651 {"no-break", no_argument, NULL, OPTION_TRAP},
11652 {"break", no_argument, NULL, OPTION_BREAK},
11653 {"no-trap", no_argument, NULL, OPTION_BREAK},
11654 {"EB", no_argument, NULL, OPTION_EB},
11655 {"EL", no_argument, NULL, OPTION_EL},
11656 {"mfp32", no_argument, NULL, OPTION_FP32},
11657 {"mgp32", no_argument, NULL, OPTION_GP32},
11658 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11659 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11660 {"mfp64", no_argument, NULL, OPTION_FP64},
11661 {"mgp64", no_argument, NULL, OPTION_GP64},
11662 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11663 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11664 {"mshared", no_argument, NULL, OPTION_MSHARED},
11665 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11666 {"msym32", no_argument, NULL, OPTION_MSYM32},
11667 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11668 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11669 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11670 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11671 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11673 /* Strictly speaking this next option is ELF specific,
11674 but we allow it for other ports as well in order to
11675 make testing easier. */
11676 {"32", no_argument, NULL, OPTION_32},
11678 /* ELF-specific options. */
11680 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11681 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11682 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11683 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11684 {"xgot", no_argument, NULL, OPTION_XGOT},
11685 {"mabi", required_argument, NULL, OPTION_MABI},
11686 {"n32", no_argument, NULL, OPTION_N32},
11687 {"64", no_argument, NULL, OPTION_64},
11688 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11689 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11690 {"mpdr", no_argument, NULL, OPTION_PDR},
11691 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11692 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11693 #endif /* OBJ_ELF */
11695 {NULL, no_argument, NULL, 0}
11697 size_t md_longopts_size = sizeof (md_longopts);
11699 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11700 NEW_VALUE. Warn if another value was already specified. Note:
11701 we have to defer parsing the -march and -mtune arguments in order
11702 to handle 'from-abi' correctly, since the ABI might be specified
11703 in a later argument. */
11706 mips_set_option_string (const char **string_ptr, const char *new_value)
11708 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11709 as_warn (_("A different %s was already specified, is now %s"),
11710 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11713 *string_ptr = new_value;
11717 md_parse_option (int c, char *arg)
11721 case OPTION_CONSTRUCT_FLOATS:
11722 mips_disable_float_construction = 0;
11725 case OPTION_NO_CONSTRUCT_FLOATS:
11726 mips_disable_float_construction = 1;
11738 target_big_endian = 1;
11742 target_big_endian = 0;
11748 else if (arg[0] == '0')
11750 else if (arg[0] == '1')
11760 mips_debug = atoi (arg);
11764 file_mips_isa = ISA_MIPS1;
11768 file_mips_isa = ISA_MIPS2;
11772 file_mips_isa = ISA_MIPS3;
11776 file_mips_isa = ISA_MIPS4;
11780 file_mips_isa = ISA_MIPS5;
11783 case OPTION_MIPS32:
11784 file_mips_isa = ISA_MIPS32;
11787 case OPTION_MIPS32R2:
11788 file_mips_isa = ISA_MIPS32R2;
11791 case OPTION_MIPS64R2:
11792 file_mips_isa = ISA_MIPS64R2;
11795 case OPTION_MIPS64:
11796 file_mips_isa = ISA_MIPS64;
11800 mips_set_option_string (&mips_tune_string, arg);
11804 mips_set_option_string (&mips_arch_string, arg);
11808 mips_set_option_string (&mips_arch_string, "4650");
11809 mips_set_option_string (&mips_tune_string, "4650");
11812 case OPTION_NO_M4650:
11816 mips_set_option_string (&mips_arch_string, "4010");
11817 mips_set_option_string (&mips_tune_string, "4010");
11820 case OPTION_NO_M4010:
11824 mips_set_option_string (&mips_arch_string, "4100");
11825 mips_set_option_string (&mips_tune_string, "4100");
11828 case OPTION_NO_M4100:
11832 mips_set_option_string (&mips_arch_string, "3900");
11833 mips_set_option_string (&mips_tune_string, "3900");
11836 case OPTION_NO_M3900:
11840 mips_opts.ase_mdmx = 1;
11843 case OPTION_NO_MDMX:
11844 mips_opts.ase_mdmx = 0;
11848 mips_opts.ase_dsp = 1;
11849 mips_opts.ase_dspr2 = 0;
11852 case OPTION_NO_DSP:
11853 mips_opts.ase_dsp = 0;
11854 mips_opts.ase_dspr2 = 0;
11858 mips_opts.ase_dspr2 = 1;
11859 mips_opts.ase_dsp = 1;
11862 case OPTION_NO_DSPR2:
11863 mips_opts.ase_dspr2 = 0;
11864 mips_opts.ase_dsp = 0;
11868 mips_opts.ase_mt = 1;
11872 mips_opts.ase_mt = 0;
11875 case OPTION_MIPS16:
11876 mips_opts.mips16 = 1;
11877 mips_no_prev_insn ();
11880 case OPTION_NO_MIPS16:
11881 mips_opts.mips16 = 0;
11882 mips_no_prev_insn ();
11885 case OPTION_MIPS3D:
11886 mips_opts.ase_mips3d = 1;
11889 case OPTION_NO_MIPS3D:
11890 mips_opts.ase_mips3d = 0;
11893 case OPTION_SMARTMIPS:
11894 mips_opts.ase_smartmips = 1;
11897 case OPTION_NO_SMARTMIPS:
11898 mips_opts.ase_smartmips = 0;
11901 case OPTION_FIX_24K:
11905 case OPTION_NO_FIX_24K:
11909 case OPTION_FIX_LOONGSON2F_JUMP:
11910 mips_fix_loongson2f_jump = TRUE;
11913 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11914 mips_fix_loongson2f_jump = FALSE;
11917 case OPTION_FIX_LOONGSON2F_NOP:
11918 mips_fix_loongson2f_nop = TRUE;
11921 case OPTION_NO_FIX_LOONGSON2F_NOP:
11922 mips_fix_loongson2f_nop = FALSE;
11925 case OPTION_FIX_VR4120:
11926 mips_fix_vr4120 = 1;
11929 case OPTION_NO_FIX_VR4120:
11930 mips_fix_vr4120 = 0;
11933 case OPTION_FIX_VR4130:
11934 mips_fix_vr4130 = 1;
11937 case OPTION_NO_FIX_VR4130:
11938 mips_fix_vr4130 = 0;
11941 case OPTION_FIX_CN63XXP1:
11942 mips_fix_cn63xxp1 = TRUE;
11945 case OPTION_NO_FIX_CN63XXP1:
11946 mips_fix_cn63xxp1 = FALSE;
11949 case OPTION_RELAX_BRANCH:
11950 mips_relax_branch = 1;
11953 case OPTION_NO_RELAX_BRANCH:
11954 mips_relax_branch = 0;
11957 case OPTION_MSHARED:
11958 mips_in_shared = TRUE;
11961 case OPTION_MNO_SHARED:
11962 mips_in_shared = FALSE;
11965 case OPTION_MSYM32:
11966 mips_opts.sym32 = TRUE;
11969 case OPTION_MNO_SYM32:
11970 mips_opts.sym32 = FALSE;
11974 /* When generating ELF code, we permit -KPIC and -call_shared to
11975 select SVR4_PIC, and -non_shared to select no PIC. This is
11976 intended to be compatible with Irix 5. */
11977 case OPTION_CALL_SHARED:
11980 as_bad (_("-call_shared is supported only for ELF format"));
11983 mips_pic = SVR4_PIC;
11984 mips_abicalls = TRUE;
11987 case OPTION_CALL_NONPIC:
11990 as_bad (_("-call_nonpic is supported only for ELF format"));
11994 mips_abicalls = TRUE;
11997 case OPTION_NON_SHARED:
12000 as_bad (_("-non_shared is supported only for ELF format"));
12004 mips_abicalls = FALSE;
12007 /* The -xgot option tells the assembler to use 32 bit offsets
12008 when accessing the got in SVR4_PIC mode. It is for Irix
12013 #endif /* OBJ_ELF */
12016 g_switch_value = atoi (arg);
12020 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12024 mips_abi = O32_ABI;
12025 /* We silently ignore -32 for non-ELF targets. This greatly
12026 simplifies the construction of the MIPS GAS test cases. */
12033 as_bad (_("-n32 is supported for ELF format only"));
12036 mips_abi = N32_ABI;
12042 as_bad (_("-64 is supported for ELF format only"));
12045 mips_abi = N64_ABI;
12046 if (!support_64bit_objects())
12047 as_fatal (_("No compiled in support for 64 bit object file format"));
12049 #endif /* OBJ_ELF */
12052 file_mips_gp32 = 1;
12056 file_mips_gp32 = 0;
12060 file_mips_fp32 = 1;
12064 file_mips_fp32 = 0;
12067 case OPTION_SINGLE_FLOAT:
12068 file_mips_single_float = 1;
12071 case OPTION_DOUBLE_FLOAT:
12072 file_mips_single_float = 0;
12075 case OPTION_SOFT_FLOAT:
12076 file_mips_soft_float = 1;
12079 case OPTION_HARD_FLOAT:
12080 file_mips_soft_float = 0;
12087 as_bad (_("-mabi is supported for ELF format only"));
12090 if (strcmp (arg, "32") == 0)
12091 mips_abi = O32_ABI;
12092 else if (strcmp (arg, "o64") == 0)
12093 mips_abi = O64_ABI;
12094 else if (strcmp (arg, "n32") == 0)
12095 mips_abi = N32_ABI;
12096 else if (strcmp (arg, "64") == 0)
12098 mips_abi = N64_ABI;
12099 if (! support_64bit_objects())
12100 as_fatal (_("No compiled in support for 64 bit object file "
12103 else if (strcmp (arg, "eabi") == 0)
12104 mips_abi = EABI_ABI;
12107 as_fatal (_("invalid abi -mabi=%s"), arg);
12111 #endif /* OBJ_ELF */
12113 case OPTION_M7000_HILO_FIX:
12114 mips_7000_hilo_fix = TRUE;
12117 case OPTION_MNO_7000_HILO_FIX:
12118 mips_7000_hilo_fix = FALSE;
12122 case OPTION_MDEBUG:
12123 mips_flag_mdebug = TRUE;
12126 case OPTION_NO_MDEBUG:
12127 mips_flag_mdebug = FALSE;
12131 mips_flag_pdr = TRUE;
12134 case OPTION_NO_PDR:
12135 mips_flag_pdr = FALSE;
12138 case OPTION_MVXWORKS_PIC:
12139 mips_pic = VXWORKS_PIC;
12141 #endif /* OBJ_ELF */
12147 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12152 /* Set up globals to generate code for the ISA or processor
12153 described by INFO. */
12156 mips_set_architecture (const struct mips_cpu_info *info)
12160 file_mips_arch = info->cpu;
12161 mips_opts.arch = info->cpu;
12162 mips_opts.isa = info->isa;
12167 /* Likewise for tuning. */
12170 mips_set_tune (const struct mips_cpu_info *info)
12173 mips_tune = info->cpu;
12178 mips_after_parse_args (void)
12180 const struct mips_cpu_info *arch_info = 0;
12181 const struct mips_cpu_info *tune_info = 0;
12183 /* GP relative stuff not working for PE */
12184 if (strncmp (TARGET_OS, "pe", 2) == 0)
12186 if (g_switch_seen && g_switch_value != 0)
12187 as_bad (_("-G not supported in this configuration."));
12188 g_switch_value = 0;
12191 if (mips_abi == NO_ABI)
12192 mips_abi = MIPS_DEFAULT_ABI;
12194 /* The following code determines the architecture and register size.
12195 Similar code was added to GCC 3.3 (see override_options() in
12196 config/mips/mips.c). The GAS and GCC code should be kept in sync
12197 as much as possible. */
12199 if (mips_arch_string != 0)
12200 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12202 if (file_mips_isa != ISA_UNKNOWN)
12204 /* Handle -mipsN. At this point, file_mips_isa contains the
12205 ISA level specified by -mipsN, while arch_info->isa contains
12206 the -march selection (if any). */
12207 if (arch_info != 0)
12209 /* -march takes precedence over -mipsN, since it is more descriptive.
12210 There's no harm in specifying both as long as the ISA levels
12212 if (file_mips_isa != arch_info->isa)
12213 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12214 mips_cpu_info_from_isa (file_mips_isa)->name,
12215 mips_cpu_info_from_isa (arch_info->isa)->name);
12218 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12221 if (arch_info == 0)
12222 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12224 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12225 as_bad (_("-march=%s is not compatible with the selected ABI"),
12228 mips_set_architecture (arch_info);
12230 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12231 if (mips_tune_string != 0)
12232 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12234 if (tune_info == 0)
12235 mips_set_tune (arch_info);
12237 mips_set_tune (tune_info);
12239 if (file_mips_gp32 >= 0)
12241 /* The user specified the size of the integer registers. Make sure
12242 it agrees with the ABI and ISA. */
12243 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12244 as_bad (_("-mgp64 used with a 32-bit processor"));
12245 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12246 as_bad (_("-mgp32 used with a 64-bit ABI"));
12247 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12248 as_bad (_("-mgp64 used with a 32-bit ABI"));
12252 /* Infer the integer register size from the ABI and processor.
12253 Restrict ourselves to 32-bit registers if that's all the
12254 processor has, or if the ABI cannot handle 64-bit registers. */
12255 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12256 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12259 switch (file_mips_fp32)
12263 /* No user specified float register size.
12264 ??? GAS treats single-float processors as though they had 64-bit
12265 float registers (although it complains when double-precision
12266 instructions are used). As things stand, saying they have 32-bit
12267 registers would lead to spurious "register must be even" messages.
12268 So here we assume float registers are never smaller than the
12270 if (file_mips_gp32 == 0)
12271 /* 64-bit integer registers implies 64-bit float registers. */
12272 file_mips_fp32 = 0;
12273 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12274 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12275 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12276 file_mips_fp32 = 0;
12278 /* 32-bit float registers. */
12279 file_mips_fp32 = 1;
12282 /* The user specified the size of the float registers. Check if it
12283 agrees with the ABI and ISA. */
12285 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12286 as_bad (_("-mfp64 used with a 32-bit fpu"));
12287 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12288 && !ISA_HAS_MXHC1 (mips_opts.isa))
12289 as_warn (_("-mfp64 used with a 32-bit ABI"));
12292 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12293 as_warn (_("-mfp32 used with a 64-bit ABI"));
12297 /* End of GCC-shared inference code. */
12299 /* This flag is set when we have a 64-bit capable CPU but use only
12300 32-bit wide registers. Note that EABI does not use it. */
12301 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12302 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12303 || mips_abi == O32_ABI))
12304 mips_32bitmode = 1;
12306 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12307 as_bad (_("trap exception not supported at ISA 1"));
12309 /* If the selected architecture includes support for ASEs, enable
12310 generation of code for them. */
12311 if (mips_opts.mips16 == -1)
12312 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12313 if (mips_opts.ase_mips3d == -1)
12314 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12315 && file_mips_fp32 == 0) ? 1 : 0;
12316 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12317 as_bad (_("-mfp32 used with -mips3d"));
12319 if (mips_opts.ase_mdmx == -1)
12320 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12321 && file_mips_fp32 == 0) ? 1 : 0;
12322 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12323 as_bad (_("-mfp32 used with -mdmx"));
12325 if (mips_opts.ase_smartmips == -1)
12326 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12327 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12328 as_warn (_("%s ISA does not support SmartMIPS"),
12329 mips_cpu_info_from_isa (mips_opts.isa)->name);
12331 if (mips_opts.ase_dsp == -1)
12332 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12333 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12334 as_warn (_("%s ISA does not support DSP ASE"),
12335 mips_cpu_info_from_isa (mips_opts.isa)->name);
12337 if (mips_opts.ase_dspr2 == -1)
12339 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12340 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12342 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12343 as_warn (_("%s ISA does not support DSP R2 ASE"),
12344 mips_cpu_info_from_isa (mips_opts.isa)->name);
12346 if (mips_opts.ase_mt == -1)
12347 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12348 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12349 as_warn (_("%s ISA does not support MT ASE"),
12350 mips_cpu_info_from_isa (mips_opts.isa)->name);
12352 file_mips_isa = mips_opts.isa;
12353 file_ase_mips3d = mips_opts.ase_mips3d;
12354 file_ase_mdmx = mips_opts.ase_mdmx;
12355 file_ase_smartmips = mips_opts.ase_smartmips;
12356 file_ase_dsp = mips_opts.ase_dsp;
12357 file_ase_dspr2 = mips_opts.ase_dspr2;
12358 file_ase_mt = mips_opts.ase_mt;
12359 mips_opts.gp32 = file_mips_gp32;
12360 mips_opts.fp32 = file_mips_fp32;
12361 mips_opts.soft_float = file_mips_soft_float;
12362 mips_opts.single_float = file_mips_single_float;
12364 if (mips_flag_mdebug < 0)
12366 #ifdef OBJ_MAYBE_ECOFF
12367 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12368 mips_flag_mdebug = 1;
12370 #endif /* OBJ_MAYBE_ECOFF */
12371 mips_flag_mdebug = 0;
12376 mips_init_after_args (void)
12378 /* initialize opcodes */
12379 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12380 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12384 md_pcrel_from (fixS *fixP)
12386 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12387 switch (fixP->fx_r_type)
12389 case BFD_RELOC_16_PCREL_S2:
12390 case BFD_RELOC_MIPS_JMP:
12391 /* Return the address of the delay slot. */
12394 /* We have no relocation type for PC relative MIPS16 instructions. */
12395 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12396 as_bad_where (fixP->fx_file, fixP->fx_line,
12397 _("PC relative MIPS16 instruction references a different section"));
12402 /* This is called before the symbol table is processed. In order to
12403 work with gcc when using mips-tfile, we must keep all local labels.
12404 However, in other cases, we want to discard them. If we were
12405 called with -g, but we didn't see any debugging information, it may
12406 mean that gcc is smuggling debugging information through to
12407 mips-tfile, in which case we must generate all local labels. */
12410 mips_frob_file_before_adjust (void)
12412 #ifndef NO_ECOFF_DEBUGGING
12413 if (ECOFF_DEBUGGING
12415 && ! ecoff_debugging_seen)
12416 flag_keep_locals = 1;
12420 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12421 the corresponding LO16 reloc. This is called before md_apply_fix and
12422 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12423 relocation operators.
12425 For our purposes, a %lo() expression matches a %got() or %hi()
12428 (a) it refers to the same symbol; and
12429 (b) the offset applied in the %lo() expression is no lower than
12430 the offset applied in the %got() or %hi().
12432 (b) allows us to cope with code like:
12435 lh $4,%lo(foo+2)($4)
12437 ...which is legal on RELA targets, and has a well-defined behaviour
12438 if the user knows that adding 2 to "foo" will not induce a carry to
12441 When several %lo()s match a particular %got() or %hi(), we use the
12442 following rules to distinguish them:
12444 (1) %lo()s with smaller offsets are a better match than %lo()s with
12447 (2) %lo()s with no matching %got() or %hi() are better than those
12448 that already have a matching %got() or %hi().
12450 (3) later %lo()s are better than earlier %lo()s.
12452 These rules are applied in order.
12454 (1) means, among other things, that %lo()s with identical offsets are
12455 chosen if they exist.
12457 (2) means that we won't associate several high-part relocations with
12458 the same low-part relocation unless there's no alternative. Having
12459 several high parts for the same low part is a GNU extension; this rule
12460 allows careful users to avoid it.
12462 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12463 with the last high-part relocation being at the front of the list.
12464 It therefore makes sense to choose the last matching low-part
12465 relocation, all other things being equal. It's also easier
12466 to code that way. */
12469 mips_frob_file (void)
12471 struct mips_hi_fixup *l;
12472 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12474 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12476 segment_info_type *seginfo;
12477 bfd_boolean matched_lo_p;
12478 fixS **hi_pos, **lo_pos, **pos;
12480 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12482 /* If a GOT16 relocation turns out to be against a global symbol,
12483 there isn't supposed to be a matching LO. */
12484 if (got16_reloc_p (l->fixp->fx_r_type)
12485 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12488 /* Check quickly whether the next fixup happens to be a matching %lo. */
12489 if (fixup_has_matching_lo_p (l->fixp))
12492 seginfo = seg_info (l->seg);
12494 /* Set HI_POS to the position of this relocation in the chain.
12495 Set LO_POS to the position of the chosen low-part relocation.
12496 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12497 relocation that matches an immediately-preceding high-part
12501 matched_lo_p = FALSE;
12502 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12504 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12506 if (*pos == l->fixp)
12509 if ((*pos)->fx_r_type == looking_for_rtype
12510 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12511 && (*pos)->fx_offset >= l->fixp->fx_offset
12513 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12515 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12518 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12519 && fixup_has_matching_lo_p (*pos));
12522 /* If we found a match, remove the high-part relocation from its
12523 current position and insert it before the low-part relocation.
12524 Make the offsets match so that fixup_has_matching_lo_p()
12527 We don't warn about unmatched high-part relocations since some
12528 versions of gcc have been known to emit dead "lui ...%hi(...)"
12530 if (lo_pos != NULL)
12532 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12533 if (l->fixp->fx_next != *lo_pos)
12535 *hi_pos = l->fixp->fx_next;
12536 l->fixp->fx_next = *lo_pos;
12543 /* We may have combined relocations without symbols in the N32/N64 ABI.
12544 We have to prevent gas from dropping them. */
12547 mips_force_relocation (fixS *fixp)
12549 if (generic_force_reloc (fixp))
12553 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12554 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12555 || hi16_reloc_p (fixp->fx_r_type)
12556 || lo16_reloc_p (fixp->fx_r_type)))
12562 /* Apply a fixup to the object file. */
12565 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12569 reloc_howto_type *howto;
12571 /* We ignore generic BFD relocations we don't know about. */
12572 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12576 gas_assert (fixP->fx_size == 4
12577 || fixP->fx_r_type == BFD_RELOC_16
12578 || fixP->fx_r_type == BFD_RELOC_64
12579 || fixP->fx_r_type == BFD_RELOC_CTOR
12580 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12581 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12582 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12583 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12585 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12587 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12589 /* Don't treat parts of a composite relocation as done. There are two
12592 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12593 should nevertheless be emitted if the first part is.
12595 (2) In normal usage, composite relocations are never assembly-time
12596 constants. The easiest way of dealing with the pathological
12597 exceptions is to generate a relocation against STN_UNDEF and
12598 leave everything up to the linker. */
12599 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12602 switch (fixP->fx_r_type)
12604 case BFD_RELOC_MIPS_TLS_GD:
12605 case BFD_RELOC_MIPS_TLS_LDM:
12606 case BFD_RELOC_MIPS_TLS_DTPREL32:
12607 case BFD_RELOC_MIPS_TLS_DTPREL64:
12608 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12609 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12610 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12611 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12612 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12613 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12616 case BFD_RELOC_MIPS_JMP:
12617 case BFD_RELOC_MIPS_SHIFT5:
12618 case BFD_RELOC_MIPS_SHIFT6:
12619 case BFD_RELOC_MIPS_GOT_DISP:
12620 case BFD_RELOC_MIPS_GOT_PAGE:
12621 case BFD_RELOC_MIPS_GOT_OFST:
12622 case BFD_RELOC_MIPS_SUB:
12623 case BFD_RELOC_MIPS_INSERT_A:
12624 case BFD_RELOC_MIPS_INSERT_B:
12625 case BFD_RELOC_MIPS_DELETE:
12626 case BFD_RELOC_MIPS_HIGHEST:
12627 case BFD_RELOC_MIPS_HIGHER:
12628 case BFD_RELOC_MIPS_SCN_DISP:
12629 case BFD_RELOC_MIPS_REL16:
12630 case BFD_RELOC_MIPS_RELGOT:
12631 case BFD_RELOC_MIPS_JALR:
12632 case BFD_RELOC_HI16:
12633 case BFD_RELOC_HI16_S:
12634 case BFD_RELOC_GPREL16:
12635 case BFD_RELOC_MIPS_LITERAL:
12636 case BFD_RELOC_MIPS_CALL16:
12637 case BFD_RELOC_MIPS_GOT16:
12638 case BFD_RELOC_GPREL32:
12639 case BFD_RELOC_MIPS_GOT_HI16:
12640 case BFD_RELOC_MIPS_GOT_LO16:
12641 case BFD_RELOC_MIPS_CALL_HI16:
12642 case BFD_RELOC_MIPS_CALL_LO16:
12643 case BFD_RELOC_MIPS16_GPREL:
12644 case BFD_RELOC_MIPS16_GOT16:
12645 case BFD_RELOC_MIPS16_CALL16:
12646 case BFD_RELOC_MIPS16_HI16:
12647 case BFD_RELOC_MIPS16_HI16_S:
12648 case BFD_RELOC_MIPS16_JMP:
12649 /* Nothing needed to do. The value comes from the reloc entry. */
12653 /* This is handled like BFD_RELOC_32, but we output a sign
12654 extended value if we are only 32 bits. */
12657 if (8 <= sizeof (valueT))
12658 md_number_to_chars ((char *) buf, *valP, 8);
12663 if ((*valP & 0x80000000) != 0)
12667 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12669 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12675 case BFD_RELOC_RVA:
12678 /* If we are deleting this reloc entry, we must fill in the
12679 value now. This can happen if we have a .word which is not
12680 resolved when it appears but is later defined. */
12682 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12685 case BFD_RELOC_LO16:
12686 case BFD_RELOC_MIPS16_LO16:
12687 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12688 may be safe to remove, but if so it's not obvious. */
12689 /* When handling an embedded PIC switch statement, we can wind
12690 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12693 if (*valP + 0x8000 > 0xffff)
12694 as_bad_where (fixP->fx_file, fixP->fx_line,
12695 _("relocation overflow"));
12696 if (target_big_endian)
12698 md_number_to_chars ((char *) buf, *valP, 2);
12702 case BFD_RELOC_16_PCREL_S2:
12703 if ((*valP & 0x3) != 0)
12704 as_bad_where (fixP->fx_file, fixP->fx_line,
12705 _("Branch to misaligned address (%lx)"), (long) *valP);
12707 /* We need to save the bits in the instruction since fixup_segment()
12708 might be deleting the relocation entry (i.e., a branch within
12709 the current segment). */
12710 if (! fixP->fx_done)
12713 /* Update old instruction data. */
12714 if (target_big_endian)
12715 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12717 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12719 if (*valP + 0x20000 <= 0x3ffff)
12721 insn |= (*valP >> 2) & 0xffff;
12722 md_number_to_chars ((char *) buf, insn, 4);
12724 else if (mips_pic == NO_PIC
12726 && fixP->fx_frag->fr_address >= text_section->vma
12727 && (fixP->fx_frag->fr_address
12728 < text_section->vma + bfd_get_section_size (text_section))
12729 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12730 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12731 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12733 /* The branch offset is too large. If this is an
12734 unconditional branch, and we are not generating PIC code,
12735 we can convert it to an absolute jump instruction. */
12736 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12737 insn = 0x0c000000; /* jal */
12739 insn = 0x08000000; /* j */
12740 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12742 fixP->fx_addsy = section_symbol (text_section);
12743 *valP += md_pcrel_from (fixP);
12744 md_number_to_chars ((char *) buf, insn, 4);
12748 /* If we got here, we have branch-relaxation disabled,
12749 and there's nothing we can do to fix this instruction
12750 without turning it into a longer sequence. */
12751 as_bad_where (fixP->fx_file, fixP->fx_line,
12752 _("Branch out of range"));
12756 case BFD_RELOC_VTABLE_INHERIT:
12759 && !S_IS_DEFINED (fixP->fx_addsy)
12760 && !S_IS_WEAK (fixP->fx_addsy))
12761 S_SET_WEAK (fixP->fx_addsy);
12764 case BFD_RELOC_VTABLE_ENTRY:
12772 /* Remember value for tc_gen_reloc. */
12773 fixP->fx_addnumber = *valP;
12783 name = input_line_pointer;
12784 c = get_symbol_end ();
12785 p = (symbolS *) symbol_find_or_make (name);
12786 *input_line_pointer = c;
12790 /* Align the current frag to a given power of two. If a particular
12791 fill byte should be used, FILL points to an integer that contains
12792 that byte, otherwise FILL is null.
12794 The MIPS assembler also automatically adjusts any preceding
12798 mips_align (int to, int *fill, symbolS *label)
12800 mips_emit_delays ();
12801 mips_record_mips16_mode ();
12802 if (fill == NULL && subseg_text_p (now_seg))
12803 frag_align_code (to, 0);
12805 frag_align (to, fill ? *fill : 0, 0);
12806 record_alignment (now_seg, to);
12809 gas_assert (S_GET_SEGMENT (label) == now_seg);
12810 symbol_set_frag (label, frag_now);
12811 S_SET_VALUE (label, (valueT) frag_now_fix ());
12815 /* Align to a given power of two. .align 0 turns off the automatic
12816 alignment used by the data creating pseudo-ops. */
12819 s_align (int x ATTRIBUTE_UNUSED)
12821 int temp, fill_value, *fill_ptr;
12822 long max_alignment = 28;
12824 /* o Note that the assembler pulls down any immediately preceding label
12825 to the aligned address.
12826 o It's not documented but auto alignment is reinstated by
12827 a .align pseudo instruction.
12828 o Note also that after auto alignment is turned off the mips assembler
12829 issues an error on attempt to assemble an improperly aligned data item.
12832 temp = get_absolute_expression ();
12833 if (temp > max_alignment)
12834 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12837 as_warn (_("Alignment negative: 0 assumed."));
12840 if (*input_line_pointer == ',')
12842 ++input_line_pointer;
12843 fill_value = get_absolute_expression ();
12844 fill_ptr = &fill_value;
12850 segment_info_type *si = seg_info (now_seg);
12851 struct insn_label_list *l = si->label_list;
12852 /* Auto alignment should be switched on by next section change. */
12854 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12861 demand_empty_rest_of_line ();
12865 s_change_sec (int sec)
12870 /* The ELF backend needs to know that we are changing sections, so
12871 that .previous works correctly. We could do something like check
12872 for an obj_section_change_hook macro, but that might be confusing
12873 as it would not be appropriate to use it in the section changing
12874 functions in read.c, since obj-elf.c intercepts those. FIXME:
12875 This should be cleaner, somehow. */
12877 obj_elf_section_change_hook ();
12880 mips_emit_delays ();
12891 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12892 demand_empty_rest_of_line ();
12896 seg = subseg_new (RDATA_SECTION_NAME,
12897 (subsegT) get_absolute_expression ());
12900 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12901 | SEC_READONLY | SEC_RELOC
12903 if (strncmp (TARGET_OS, "elf", 3) != 0)
12904 record_alignment (seg, 4);
12906 demand_empty_rest_of_line ();
12910 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12913 bfd_set_section_flags (stdoutput, seg,
12914 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12915 if (strncmp (TARGET_OS, "elf", 3) != 0)
12916 record_alignment (seg, 4);
12918 demand_empty_rest_of_line ();
12922 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12925 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12926 if (strncmp (TARGET_OS, "elf", 3) != 0)
12927 record_alignment (seg, 4);
12929 demand_empty_rest_of_line ();
12937 s_change_section (int ignore ATTRIBUTE_UNUSED)
12940 char *section_name;
12945 int section_entry_size;
12946 int section_alignment;
12951 section_name = input_line_pointer;
12952 c = get_symbol_end ();
12954 next_c = *(input_line_pointer + 1);
12956 /* Do we have .section Name<,"flags">? */
12957 if (c != ',' || (c == ',' && next_c == '"'))
12959 /* just after name is now '\0'. */
12960 *input_line_pointer = c;
12961 input_line_pointer = section_name;
12962 obj_elf_section (ignore);
12965 input_line_pointer++;
12967 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12969 section_type = get_absolute_expression ();
12972 if (*input_line_pointer++ == ',')
12973 section_flag = get_absolute_expression ();
12976 if (*input_line_pointer++ == ',')
12977 section_entry_size = get_absolute_expression ();
12979 section_entry_size = 0;
12980 if (*input_line_pointer++ == ',')
12981 section_alignment = get_absolute_expression ();
12983 section_alignment = 0;
12984 /* FIXME: really ignore? */
12985 (void) section_alignment;
12987 section_name = xstrdup (section_name);
12989 /* When using the generic form of .section (as implemented by obj-elf.c),
12990 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12991 traditionally had to fall back on the more common @progbits instead.
12993 There's nothing really harmful in this, since bfd will correct
12994 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12995 means that, for backwards compatibility, the special_section entries
12996 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12998 Even so, we shouldn't force users of the MIPS .section syntax to
12999 incorrectly label the sections as SHT_PROGBITS. The best compromise
13000 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13001 generic type-checking code. */
13002 if (section_type == SHT_MIPS_DWARF)
13003 section_type = SHT_PROGBITS;
13005 obj_elf_change_section (section_name, section_type, section_flag,
13006 section_entry_size, 0, 0, 0);
13008 if (now_seg->name != section_name)
13009 free (section_name);
13010 #endif /* OBJ_ELF */
13014 mips_enable_auto_align (void)
13020 s_cons (int log_size)
13022 segment_info_type *si = seg_info (now_seg);
13023 struct insn_label_list *l = si->label_list;
13026 label = l != NULL ? l->label : NULL;
13027 mips_emit_delays ();
13028 if (log_size > 0 && auto_align)
13029 mips_align (log_size, 0, label);
13030 cons (1 << log_size);
13031 mips_clear_insn_labels ();
13035 s_float_cons (int type)
13037 segment_info_type *si = seg_info (now_seg);
13038 struct insn_label_list *l = si->label_list;
13041 label = l != NULL ? l->label : NULL;
13043 mips_emit_delays ();
13048 mips_align (3, 0, label);
13050 mips_align (2, 0, label);
13054 mips_clear_insn_labels ();
13057 /* Handle .globl. We need to override it because on Irix 5 you are
13060 where foo is an undefined symbol, to mean that foo should be
13061 considered to be the address of a function. */
13064 s_mips_globl (int x ATTRIBUTE_UNUSED)
13073 name = input_line_pointer;
13074 c = get_symbol_end ();
13075 symbolP = symbol_find_or_make (name);
13076 S_SET_EXTERNAL (symbolP);
13078 *input_line_pointer = c;
13079 SKIP_WHITESPACE ();
13081 /* On Irix 5, every global symbol that is not explicitly labelled as
13082 being a function is apparently labelled as being an object. */
13085 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13086 && (*input_line_pointer != ','))
13091 secname = input_line_pointer;
13092 c = get_symbol_end ();
13093 sec = bfd_get_section_by_name (stdoutput, secname);
13095 as_bad (_("%s: no such section"), secname);
13096 *input_line_pointer = c;
13098 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13099 flag = BSF_FUNCTION;
13102 symbol_get_bfdsym (symbolP)->flags |= flag;
13104 c = *input_line_pointer;
13107 input_line_pointer++;
13108 SKIP_WHITESPACE ();
13109 if (is_end_of_line[(unsigned char) *input_line_pointer])
13115 demand_empty_rest_of_line ();
13119 s_option (int x ATTRIBUTE_UNUSED)
13124 opt = input_line_pointer;
13125 c = get_symbol_end ();
13129 /* FIXME: What does this mean? */
13131 else if (strncmp (opt, "pic", 3) == 0)
13135 i = atoi (opt + 3);
13140 mips_pic = SVR4_PIC;
13141 mips_abicalls = TRUE;
13144 as_bad (_(".option pic%d not supported"), i);
13146 if (mips_pic == SVR4_PIC)
13148 if (g_switch_seen && g_switch_value != 0)
13149 as_warn (_("-G may not be used with SVR4 PIC code"));
13150 g_switch_value = 0;
13151 bfd_set_gp_size (stdoutput, 0);
13155 as_warn (_("Unrecognized option \"%s\""), opt);
13157 *input_line_pointer = c;
13158 demand_empty_rest_of_line ();
13161 /* This structure is used to hold a stack of .set values. */
13163 struct mips_option_stack
13165 struct mips_option_stack *next;
13166 struct mips_set_options options;
13169 static struct mips_option_stack *mips_opts_stack;
13171 /* Handle the .set pseudo-op. */
13174 s_mipsset (int x ATTRIBUTE_UNUSED)
13176 char *name = input_line_pointer, ch;
13178 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13179 ++input_line_pointer;
13180 ch = *input_line_pointer;
13181 *input_line_pointer = '\0';
13183 if (strcmp (name, "reorder") == 0)
13185 if (mips_opts.noreorder)
13188 else if (strcmp (name, "noreorder") == 0)
13190 if (!mips_opts.noreorder)
13191 start_noreorder ();
13193 else if (strncmp (name, "at=", 3) == 0)
13195 char *s = name + 3;
13197 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13198 as_bad (_("Unrecognized register name `%s'"), s);
13200 else if (strcmp (name, "at") == 0)
13202 mips_opts.at = ATREG;
13204 else if (strcmp (name, "noat") == 0)
13206 mips_opts.at = ZERO;
13208 else if (strcmp (name, "macro") == 0)
13210 mips_opts.warn_about_macros = 0;
13212 else if (strcmp (name, "nomacro") == 0)
13214 if (mips_opts.noreorder == 0)
13215 as_bad (_("`noreorder' must be set before `nomacro'"));
13216 mips_opts.warn_about_macros = 1;
13218 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13220 mips_opts.nomove = 0;
13222 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13224 mips_opts.nomove = 1;
13226 else if (strcmp (name, "bopt") == 0)
13228 mips_opts.nobopt = 0;
13230 else if (strcmp (name, "nobopt") == 0)
13232 mips_opts.nobopt = 1;
13234 else if (strcmp (name, "gp=default") == 0)
13235 mips_opts.gp32 = file_mips_gp32;
13236 else if (strcmp (name, "gp=32") == 0)
13237 mips_opts.gp32 = 1;
13238 else if (strcmp (name, "gp=64") == 0)
13240 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13241 as_warn (_("%s isa does not support 64-bit registers"),
13242 mips_cpu_info_from_isa (mips_opts.isa)->name);
13243 mips_opts.gp32 = 0;
13245 else if (strcmp (name, "fp=default") == 0)
13246 mips_opts.fp32 = file_mips_fp32;
13247 else if (strcmp (name, "fp=32") == 0)
13248 mips_opts.fp32 = 1;
13249 else if (strcmp (name, "fp=64") == 0)
13251 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13252 as_warn (_("%s isa does not support 64-bit floating point registers"),
13253 mips_cpu_info_from_isa (mips_opts.isa)->name);
13254 mips_opts.fp32 = 0;
13256 else if (strcmp (name, "softfloat") == 0)
13257 mips_opts.soft_float = 1;
13258 else if (strcmp (name, "hardfloat") == 0)
13259 mips_opts.soft_float = 0;
13260 else if (strcmp (name, "singlefloat") == 0)
13261 mips_opts.single_float = 1;
13262 else if (strcmp (name, "doublefloat") == 0)
13263 mips_opts.single_float = 0;
13264 else if (strcmp (name, "mips16") == 0
13265 || strcmp (name, "MIPS-16") == 0)
13266 mips_opts.mips16 = 1;
13267 else if (strcmp (name, "nomips16") == 0
13268 || strcmp (name, "noMIPS-16") == 0)
13269 mips_opts.mips16 = 0;
13270 else if (strcmp (name, "smartmips") == 0)
13272 if (!ISA_SUPPORTS_SMARTMIPS)
13273 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13274 mips_cpu_info_from_isa (mips_opts.isa)->name);
13275 mips_opts.ase_smartmips = 1;
13277 else if (strcmp (name, "nosmartmips") == 0)
13278 mips_opts.ase_smartmips = 0;
13279 else if (strcmp (name, "mips3d") == 0)
13280 mips_opts.ase_mips3d = 1;
13281 else if (strcmp (name, "nomips3d") == 0)
13282 mips_opts.ase_mips3d = 0;
13283 else if (strcmp (name, "mdmx") == 0)
13284 mips_opts.ase_mdmx = 1;
13285 else if (strcmp (name, "nomdmx") == 0)
13286 mips_opts.ase_mdmx = 0;
13287 else if (strcmp (name, "dsp") == 0)
13289 if (!ISA_SUPPORTS_DSP_ASE)
13290 as_warn (_("%s ISA does not support DSP ASE"),
13291 mips_cpu_info_from_isa (mips_opts.isa)->name);
13292 mips_opts.ase_dsp = 1;
13293 mips_opts.ase_dspr2 = 0;
13295 else if (strcmp (name, "nodsp") == 0)
13297 mips_opts.ase_dsp = 0;
13298 mips_opts.ase_dspr2 = 0;
13300 else if (strcmp (name, "dspr2") == 0)
13302 if (!ISA_SUPPORTS_DSPR2_ASE)
13303 as_warn (_("%s ISA does not support DSP R2 ASE"),
13304 mips_cpu_info_from_isa (mips_opts.isa)->name);
13305 mips_opts.ase_dspr2 = 1;
13306 mips_opts.ase_dsp = 1;
13308 else if (strcmp (name, "nodspr2") == 0)
13310 mips_opts.ase_dspr2 = 0;
13311 mips_opts.ase_dsp = 0;
13313 else if (strcmp (name, "mt") == 0)
13315 if (!ISA_SUPPORTS_MT_ASE)
13316 as_warn (_("%s ISA does not support MT ASE"),
13317 mips_cpu_info_from_isa (mips_opts.isa)->name);
13318 mips_opts.ase_mt = 1;
13320 else if (strcmp (name, "nomt") == 0)
13321 mips_opts.ase_mt = 0;
13322 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13326 /* Permit the user to change the ISA and architecture on the fly.
13327 Needless to say, misuse can cause serious problems. */
13328 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13331 mips_opts.isa = file_mips_isa;
13332 mips_opts.arch = file_mips_arch;
13334 else if (strncmp (name, "arch=", 5) == 0)
13336 const struct mips_cpu_info *p;
13338 p = mips_parse_cpu("internal use", name + 5);
13340 as_bad (_("unknown architecture %s"), name + 5);
13343 mips_opts.arch = p->cpu;
13344 mips_opts.isa = p->isa;
13347 else if (strncmp (name, "mips", 4) == 0)
13349 const struct mips_cpu_info *p;
13351 p = mips_parse_cpu("internal use", name);
13353 as_bad (_("unknown ISA level %s"), name + 4);
13356 mips_opts.arch = p->cpu;
13357 mips_opts.isa = p->isa;
13361 as_bad (_("unknown ISA or architecture %s"), name);
13363 switch (mips_opts.isa)
13371 mips_opts.gp32 = 1;
13372 mips_opts.fp32 = 1;
13379 mips_opts.gp32 = 0;
13380 mips_opts.fp32 = 0;
13383 as_bad (_("unknown ISA level %s"), name + 4);
13388 mips_opts.gp32 = file_mips_gp32;
13389 mips_opts.fp32 = file_mips_fp32;
13392 else if (strcmp (name, "autoextend") == 0)
13393 mips_opts.noautoextend = 0;
13394 else if (strcmp (name, "noautoextend") == 0)
13395 mips_opts.noautoextend = 1;
13396 else if (strcmp (name, "push") == 0)
13398 struct mips_option_stack *s;
13400 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13401 s->next = mips_opts_stack;
13402 s->options = mips_opts;
13403 mips_opts_stack = s;
13405 else if (strcmp (name, "pop") == 0)
13407 struct mips_option_stack *s;
13409 s = mips_opts_stack;
13411 as_bad (_(".set pop with no .set push"));
13414 /* If we're changing the reorder mode we need to handle
13415 delay slots correctly. */
13416 if (s->options.noreorder && ! mips_opts.noreorder)
13417 start_noreorder ();
13418 else if (! s->options.noreorder && mips_opts.noreorder)
13421 mips_opts = s->options;
13422 mips_opts_stack = s->next;
13426 else if (strcmp (name, "sym32") == 0)
13427 mips_opts.sym32 = TRUE;
13428 else if (strcmp (name, "nosym32") == 0)
13429 mips_opts.sym32 = FALSE;
13430 else if (strchr (name, ','))
13432 /* Generic ".set" directive; use the generic handler. */
13433 *input_line_pointer = ch;
13434 input_line_pointer = name;
13440 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13442 *input_line_pointer = ch;
13443 demand_empty_rest_of_line ();
13446 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13447 .option pic2. It means to generate SVR4 PIC calls. */
13450 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13452 mips_pic = SVR4_PIC;
13453 mips_abicalls = TRUE;
13455 if (g_switch_seen && g_switch_value != 0)
13456 as_warn (_("-G may not be used with SVR4 PIC code"));
13457 g_switch_value = 0;
13459 bfd_set_gp_size (stdoutput, 0);
13460 demand_empty_rest_of_line ();
13463 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13464 PIC code. It sets the $gp register for the function based on the
13465 function address, which is in the register named in the argument.
13466 This uses a relocation against _gp_disp, which is handled specially
13467 by the linker. The result is:
13468 lui $gp,%hi(_gp_disp)
13469 addiu $gp,$gp,%lo(_gp_disp)
13470 addu $gp,$gp,.cpload argument
13471 The .cpload argument is normally $25 == $t9.
13473 The -mno-shared option changes this to:
13474 lui $gp,%hi(__gnu_local_gp)
13475 addiu $gp,$gp,%lo(__gnu_local_gp)
13476 and the argument is ignored. This saves an instruction, but the
13477 resulting code is not position independent; it uses an absolute
13478 address for __gnu_local_gp. Thus code assembled with -mno-shared
13479 can go into an ordinary executable, but not into a shared library. */
13482 s_cpload (int ignore ATTRIBUTE_UNUSED)
13488 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13489 .cpload is ignored. */
13490 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13496 /* .cpload should be in a .set noreorder section. */
13497 if (mips_opts.noreorder == 0)
13498 as_warn (_(".cpload not in noreorder section"));
13500 reg = tc_get_register (0);
13502 /* If we need to produce a 64-bit address, we are better off using
13503 the default instruction sequence. */
13504 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13506 ex.X_op = O_symbol;
13507 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13509 ex.X_op_symbol = NULL;
13510 ex.X_add_number = 0;
13512 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13513 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13516 macro_build_lui (&ex, mips_gp_register);
13517 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13518 mips_gp_register, BFD_RELOC_LO16);
13520 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13521 mips_gp_register, reg);
13524 demand_empty_rest_of_line ();
13527 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13528 .cpsetup $reg1, offset|$reg2, label
13530 If offset is given, this results in:
13531 sd $gp, offset($sp)
13532 lui $gp, %hi(%neg(%gp_rel(label)))
13533 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13534 daddu $gp, $gp, $reg1
13536 If $reg2 is given, this results in:
13537 daddu $reg2, $gp, $0
13538 lui $gp, %hi(%neg(%gp_rel(label)))
13539 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13540 daddu $gp, $gp, $reg1
13541 $reg1 is normally $25 == $t9.
13543 The -mno-shared option replaces the last three instructions with
13545 addiu $gp,$gp,%lo(_gp) */
13548 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13550 expressionS ex_off;
13551 expressionS ex_sym;
13554 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13555 We also need NewABI support. */
13556 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13562 reg1 = tc_get_register (0);
13563 SKIP_WHITESPACE ();
13564 if (*input_line_pointer != ',')
13566 as_bad (_("missing argument separator ',' for .cpsetup"));
13570 ++input_line_pointer;
13571 SKIP_WHITESPACE ();
13572 if (*input_line_pointer == '$')
13574 mips_cpreturn_register = tc_get_register (0);
13575 mips_cpreturn_offset = -1;
13579 mips_cpreturn_offset = get_absolute_expression ();
13580 mips_cpreturn_register = -1;
13582 SKIP_WHITESPACE ();
13583 if (*input_line_pointer != ',')
13585 as_bad (_("missing argument separator ',' for .cpsetup"));
13589 ++input_line_pointer;
13590 SKIP_WHITESPACE ();
13591 expression (&ex_sym);
13594 if (mips_cpreturn_register == -1)
13596 ex_off.X_op = O_constant;
13597 ex_off.X_add_symbol = NULL;
13598 ex_off.X_op_symbol = NULL;
13599 ex_off.X_add_number = mips_cpreturn_offset;
13601 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13602 BFD_RELOC_LO16, SP);
13605 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13606 mips_gp_register, 0);
13608 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13610 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13611 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13614 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13615 mips_gp_register, -1, BFD_RELOC_GPREL16,
13616 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13618 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13619 mips_gp_register, reg1);
13625 ex.X_op = O_symbol;
13626 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13627 ex.X_op_symbol = NULL;
13628 ex.X_add_number = 0;
13630 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13631 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13633 macro_build_lui (&ex, mips_gp_register);
13634 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13635 mips_gp_register, BFD_RELOC_LO16);
13640 demand_empty_rest_of_line ();
13644 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13646 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13647 .cplocal is ignored. */
13648 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13654 mips_gp_register = tc_get_register (0);
13655 demand_empty_rest_of_line ();
13658 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13659 offset from $sp. The offset is remembered, and after making a PIC
13660 call $gp is restored from that location. */
13663 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13667 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13668 .cprestore is ignored. */
13669 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13675 mips_cprestore_offset = get_absolute_expression ();
13676 mips_cprestore_valid = 1;
13678 ex.X_op = O_constant;
13679 ex.X_add_symbol = NULL;
13680 ex.X_op_symbol = NULL;
13681 ex.X_add_number = mips_cprestore_offset;
13684 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13685 SP, HAVE_64BIT_ADDRESSES);
13688 demand_empty_rest_of_line ();
13691 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13692 was given in the preceding .cpsetup, it results in:
13693 ld $gp, offset($sp)
13695 If a register $reg2 was given there, it results in:
13696 daddu $gp, $reg2, $0 */
13699 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13703 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13704 We also need NewABI support. */
13705 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13712 if (mips_cpreturn_register == -1)
13714 ex.X_op = O_constant;
13715 ex.X_add_symbol = NULL;
13716 ex.X_op_symbol = NULL;
13717 ex.X_add_number = mips_cpreturn_offset;
13719 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13722 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13723 mips_cpreturn_register, 0);
13726 demand_empty_rest_of_line ();
13729 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13730 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13731 use in DWARF debug information. */
13734 s_dtprel_internal (size_t bytes)
13741 if (ex.X_op != O_symbol)
13743 as_bad (_("Unsupported use of %s"), (bytes == 8
13746 ignore_rest_of_line ();
13749 p = frag_more (bytes);
13750 md_number_to_chars (p, 0, bytes);
13751 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13753 ? BFD_RELOC_MIPS_TLS_DTPREL64
13754 : BFD_RELOC_MIPS_TLS_DTPREL32));
13756 demand_empty_rest_of_line ();
13759 /* Handle .dtprelword. */
13762 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13764 s_dtprel_internal (4);
13767 /* Handle .dtpreldword. */
13770 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13772 s_dtprel_internal (8);
13775 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13776 code. It sets the offset to use in gp_rel relocations. */
13779 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13781 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13782 We also need NewABI support. */
13783 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13789 mips_gprel_offset = get_absolute_expression ();
13791 demand_empty_rest_of_line ();
13794 /* Handle the .gpword pseudo-op. This is used when generating PIC
13795 code. It generates a 32 bit GP relative reloc. */
13798 s_gpword (int ignore ATTRIBUTE_UNUSED)
13800 segment_info_type *si;
13801 struct insn_label_list *l;
13806 /* When not generating PIC code, this is treated as .word. */
13807 if (mips_pic != SVR4_PIC)
13813 si = seg_info (now_seg);
13814 l = si->label_list;
13815 label = l != NULL ? l->label : NULL;
13816 mips_emit_delays ();
13818 mips_align (2, 0, label);
13821 mips_clear_insn_labels ();
13823 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13825 as_bad (_("Unsupported use of .gpword"));
13826 ignore_rest_of_line ();
13830 md_number_to_chars (p, 0, 4);
13831 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13832 BFD_RELOC_GPREL32);
13834 demand_empty_rest_of_line ();
13838 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13840 segment_info_type *si;
13841 struct insn_label_list *l;
13846 /* When not generating PIC code, this is treated as .dword. */
13847 if (mips_pic != SVR4_PIC)
13853 si = seg_info (now_seg);
13854 l = si->label_list;
13855 label = l != NULL ? l->label : NULL;
13856 mips_emit_delays ();
13858 mips_align (3, 0, label);
13861 mips_clear_insn_labels ();
13863 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13865 as_bad (_("Unsupported use of .gpdword"));
13866 ignore_rest_of_line ();
13870 md_number_to_chars (p, 0, 8);
13871 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13872 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13874 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13875 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13876 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13878 demand_empty_rest_of_line ();
13881 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13882 tables in SVR4 PIC code. */
13885 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13889 /* This is ignored when not generating SVR4 PIC code. */
13890 if (mips_pic != SVR4_PIC)
13896 /* Add $gp to the register named as an argument. */
13898 reg = tc_get_register (0);
13899 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13902 demand_empty_rest_of_line ();
13905 /* Handle the .insn pseudo-op. This marks instruction labels in
13906 mips16 mode. This permits the linker to handle them specially,
13907 such as generating jalx instructions when needed. We also make
13908 them odd for the duration of the assembly, in order to generate the
13909 right sort of code. We will make them even in the adjust_symtab
13910 routine, while leaving them marked. This is convenient for the
13911 debugger and the disassembler. The linker knows to make them odd
13915 s_insn (int ignore ATTRIBUTE_UNUSED)
13917 mips16_mark_labels ();
13919 demand_empty_rest_of_line ();
13922 /* Handle a .stabn directive. We need these in order to mark a label
13923 as being a mips16 text label correctly. Sometimes the compiler
13924 will emit a label, followed by a .stabn, and then switch sections.
13925 If the label and .stabn are in mips16 mode, then the label is
13926 really a mips16 text label. */
13929 s_mips_stab (int type)
13932 mips16_mark_labels ();
13937 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13940 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13947 name = input_line_pointer;
13948 c = get_symbol_end ();
13949 symbolP = symbol_find_or_make (name);
13950 S_SET_WEAK (symbolP);
13951 *input_line_pointer = c;
13953 SKIP_WHITESPACE ();
13955 if (! is_end_of_line[(unsigned char) *input_line_pointer])
13957 if (S_IS_DEFINED (symbolP))
13959 as_bad (_("ignoring attempt to redefine symbol %s"),
13960 S_GET_NAME (symbolP));
13961 ignore_rest_of_line ();
13965 if (*input_line_pointer == ',')
13967 ++input_line_pointer;
13968 SKIP_WHITESPACE ();
13972 if (exp.X_op != O_symbol)
13974 as_bad (_("bad .weakext directive"));
13975 ignore_rest_of_line ();
13978 symbol_set_value_expression (symbolP, &exp);
13981 demand_empty_rest_of_line ();
13984 /* Parse a register string into a number. Called from the ECOFF code
13985 to parse .frame. The argument is non-zero if this is the frame
13986 register, so that we can record it in mips_frame_reg. */
13989 tc_get_register (int frame)
13993 SKIP_WHITESPACE ();
13994 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
13998 mips_frame_reg = reg != 0 ? reg : SP;
13999 mips_frame_reg_valid = 1;
14000 mips_cprestore_valid = 0;
14006 md_section_align (asection *seg, valueT addr)
14008 int align = bfd_get_section_alignment (stdoutput, seg);
14012 /* We don't need to align ELF sections to the full alignment.
14013 However, Irix 5 may prefer that we align them at least to a 16
14014 byte boundary. We don't bother to align the sections if we
14015 are targeted for an embedded system. */
14016 if (strncmp (TARGET_OS, "elf", 3) == 0)
14022 return ((addr + (1 << align) - 1) & (-1 << align));
14025 /* Utility routine, called from above as well. If called while the
14026 input file is still being read, it's only an approximation. (For
14027 example, a symbol may later become defined which appeared to be
14028 undefined earlier.) */
14031 nopic_need_relax (symbolS *sym, int before_relaxing)
14036 if (g_switch_value > 0)
14038 const char *symname;
14041 /* Find out whether this symbol can be referenced off the $gp
14042 register. It can be if it is smaller than the -G size or if
14043 it is in the .sdata or .sbss section. Certain symbols can
14044 not be referenced off the $gp, although it appears as though
14046 symname = S_GET_NAME (sym);
14047 if (symname != (const char *) NULL
14048 && (strcmp (symname, "eprol") == 0
14049 || strcmp (symname, "etext") == 0
14050 || strcmp (symname, "_gp") == 0
14051 || strcmp (symname, "edata") == 0
14052 || strcmp (symname, "_fbss") == 0
14053 || strcmp (symname, "_fdata") == 0
14054 || strcmp (symname, "_ftext") == 0
14055 || strcmp (symname, "end") == 0
14056 || strcmp (symname, "_gp_disp") == 0))
14058 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14060 #ifndef NO_ECOFF_DEBUGGING
14061 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14062 && (symbol_get_obj (sym)->ecoff_extern_size
14063 <= g_switch_value))
14065 /* We must defer this decision until after the whole
14066 file has been read, since there might be a .extern
14067 after the first use of this symbol. */
14068 || (before_relaxing
14069 #ifndef NO_ECOFF_DEBUGGING
14070 && symbol_get_obj (sym)->ecoff_extern_size == 0
14072 && S_GET_VALUE (sym) == 0)
14073 || (S_GET_VALUE (sym) != 0
14074 && S_GET_VALUE (sym) <= g_switch_value)))
14078 const char *segname;
14080 segname = segment_name (S_GET_SEGMENT (sym));
14081 gas_assert (strcmp (segname, ".lit8") != 0
14082 && strcmp (segname, ".lit4") != 0);
14083 change = (strcmp (segname, ".sdata") != 0
14084 && strcmp (segname, ".sbss") != 0
14085 && strncmp (segname, ".sdata.", 7) != 0
14086 && strncmp (segname, ".sbss.", 6) != 0
14087 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14088 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14093 /* We are not optimizing for the $gp register. */
14098 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14101 pic_need_relax (symbolS *sym, asection *segtype)
14105 /* Handle the case of a symbol equated to another symbol. */
14106 while (symbol_equated_reloc_p (sym))
14110 /* It's possible to get a loop here in a badly written program. */
14111 n = symbol_get_value_expression (sym)->X_add_symbol;
14117 if (symbol_section_p (sym))
14120 symsec = S_GET_SEGMENT (sym);
14122 /* This must duplicate the test in adjust_reloc_syms. */
14123 return (symsec != &bfd_und_section
14124 && symsec != &bfd_abs_section
14125 && !bfd_is_com_section (symsec)
14126 && !s_is_linkonce (sym, segtype)
14128 /* A global or weak symbol is treated as external. */
14129 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14135 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14136 extended opcode. SEC is the section the frag is in. */
14139 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14142 const struct mips16_immed_operand *op;
14144 int mintiny, maxtiny;
14148 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14150 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14153 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14154 op = mips16_immed_operands;
14155 while (op->type != type)
14158 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14163 if (type == '<' || type == '>' || type == '[' || type == ']')
14166 maxtiny = 1 << op->nbits;
14171 maxtiny = (1 << op->nbits) - 1;
14176 mintiny = - (1 << (op->nbits - 1));
14177 maxtiny = (1 << (op->nbits - 1)) - 1;
14180 sym_frag = symbol_get_frag (fragp->fr_symbol);
14181 val = S_GET_VALUE (fragp->fr_symbol);
14182 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14188 /* We won't have the section when we are called from
14189 mips_relax_frag. However, we will always have been called
14190 from md_estimate_size_before_relax first. If this is a
14191 branch to a different section, we mark it as such. If SEC is
14192 NULL, and the frag is not marked, then it must be a branch to
14193 the same section. */
14196 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14201 /* Must have been called from md_estimate_size_before_relax. */
14204 fragp->fr_subtype =
14205 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14207 /* FIXME: We should support this, and let the linker
14208 catch branches and loads that are out of range. */
14209 as_bad_where (fragp->fr_file, fragp->fr_line,
14210 _("unsupported PC relative reference to different section"));
14214 if (fragp != sym_frag && sym_frag->fr_address == 0)
14215 /* Assume non-extended on the first relaxation pass.
14216 The address we have calculated will be bogus if this is
14217 a forward branch to another frag, as the forward frag
14218 will have fr_address == 0. */
14222 /* In this case, we know for sure that the symbol fragment is in
14223 the same section. If the relax_marker of the symbol fragment
14224 differs from the relax_marker of this fragment, we have not
14225 yet adjusted the symbol fragment fr_address. We want to add
14226 in STRETCH in order to get a better estimate of the address.
14227 This particularly matters because of the shift bits. */
14229 && sym_frag->relax_marker != fragp->relax_marker)
14233 /* Adjust stretch for any alignment frag. Note that if have
14234 been expanding the earlier code, the symbol may be
14235 defined in what appears to be an earlier frag. FIXME:
14236 This doesn't handle the fr_subtype field, which specifies
14237 a maximum number of bytes to skip when doing an
14239 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14241 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14244 stretch = - ((- stretch)
14245 & ~ ((1 << (int) f->fr_offset) - 1));
14247 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14256 addr = fragp->fr_address + fragp->fr_fix;
14258 /* The base address rules are complicated. The base address of
14259 a branch is the following instruction. The base address of a
14260 PC relative load or add is the instruction itself, but if it
14261 is in a delay slot (in which case it can not be extended) use
14262 the address of the instruction whose delay slot it is in. */
14263 if (type == 'p' || type == 'q')
14267 /* If we are currently assuming that this frag should be
14268 extended, then, the current address is two bytes
14270 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14273 /* Ignore the low bit in the target, since it will be set
14274 for a text label. */
14275 if ((val & 1) != 0)
14278 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14280 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14283 val -= addr & ~ ((1 << op->shift) - 1);
14285 /* Branch offsets have an implicit 0 in the lowest bit. */
14286 if (type == 'p' || type == 'q')
14289 /* If any of the shifted bits are set, we must use an extended
14290 opcode. If the address depends on the size of this
14291 instruction, this can lead to a loop, so we arrange to always
14292 use an extended opcode. We only check this when we are in
14293 the main relaxation loop, when SEC is NULL. */
14294 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14296 fragp->fr_subtype =
14297 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14301 /* If we are about to mark a frag as extended because the value
14302 is precisely maxtiny + 1, then there is a chance of an
14303 infinite loop as in the following code:
14308 In this case when the la is extended, foo is 0x3fc bytes
14309 away, so the la can be shrunk, but then foo is 0x400 away, so
14310 the la must be extended. To avoid this loop, we mark the
14311 frag as extended if it was small, and is about to become
14312 extended with a value of maxtiny + 1. */
14313 if (val == ((maxtiny + 1) << op->shift)
14314 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14317 fragp->fr_subtype =
14318 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14322 else if (symsec != absolute_section && sec != NULL)
14323 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14325 if ((val & ((1 << op->shift) - 1)) != 0
14326 || val < (mintiny << op->shift)
14327 || val > (maxtiny << op->shift))
14333 /* Compute the length of a branch sequence, and adjust the
14334 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14335 worst-case length is computed, with UPDATE being used to indicate
14336 whether an unconditional (-1), branch-likely (+1) or regular (0)
14337 branch is to be computed. */
14339 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14341 bfd_boolean toofar;
14345 && S_IS_DEFINED (fragp->fr_symbol)
14346 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14351 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14353 addr = fragp->fr_address + fragp->fr_fix + 4;
14357 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14360 /* If the symbol is not defined or it's in a different segment,
14361 assume the user knows what's going on and emit a short
14367 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14369 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14370 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14371 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14372 RELAX_BRANCH_LINK (fragp->fr_subtype),
14378 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14381 if (mips_pic != NO_PIC)
14383 /* Additional space for PIC loading of target address. */
14385 if (mips_opts.isa == ISA_MIPS1)
14386 /* Additional space for $at-stabilizing nop. */
14390 /* If branch is conditional. */
14391 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14398 /* Estimate the size of a frag before relaxing. Unless this is the
14399 mips16, we are not really relaxing here, and the final size is
14400 encoded in the subtype information. For the mips16, we have to
14401 decide whether we are using an extended opcode or not. */
14404 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14408 if (RELAX_BRANCH_P (fragp->fr_subtype))
14411 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14413 return fragp->fr_var;
14416 if (RELAX_MIPS16_P (fragp->fr_subtype))
14417 /* We don't want to modify the EXTENDED bit here; it might get us
14418 into infinite loops. We change it only in mips_relax_frag(). */
14419 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14421 if (mips_pic == NO_PIC)
14422 change = nopic_need_relax (fragp->fr_symbol, 0);
14423 else if (mips_pic == SVR4_PIC)
14424 change = pic_need_relax (fragp->fr_symbol, segtype);
14425 else if (mips_pic == VXWORKS_PIC)
14426 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14433 fragp->fr_subtype |= RELAX_USE_SECOND;
14434 return -RELAX_FIRST (fragp->fr_subtype);
14437 return -RELAX_SECOND (fragp->fr_subtype);
14440 /* This is called to see whether a reloc against a defined symbol
14441 should be converted into a reloc against a section. */
14444 mips_fix_adjustable (fixS *fixp)
14446 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14447 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14450 if (fixp->fx_addsy == NULL)
14453 /* If symbol SYM is in a mergeable section, relocations of the form
14454 SYM + 0 can usually be made section-relative. The mergeable data
14455 is then identified by the section offset rather than by the symbol.
14457 However, if we're generating REL LO16 relocations, the offset is split
14458 between the LO16 and parterning high part relocation. The linker will
14459 need to recalculate the complete offset in order to correctly identify
14462 The linker has traditionally not looked for the parterning high part
14463 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14464 placed anywhere. Rather than break backwards compatibility by changing
14465 this, it seems better not to force the issue, and instead keep the
14466 original symbol. This will work with either linker behavior. */
14467 if ((lo16_reloc_p (fixp->fx_r_type)
14468 || reloc_needs_lo_p (fixp->fx_r_type))
14469 && HAVE_IN_PLACE_ADDENDS
14470 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14473 /* There is no place to store an in-place offset for JALR relocations.
14474 Likewise an in-range offset of PC-relative relocations may overflow
14475 the in-place relocatable field if recalculated against the start
14476 address of the symbol's containing section. */
14477 if (HAVE_IN_PLACE_ADDENDS
14478 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14482 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14483 to a floating-point stub. The same is true for non-R_MIPS16_26
14484 relocations against MIPS16 functions; in this case, the stub becomes
14485 the function's canonical address.
14487 Floating-point stubs are stored in unique .mips16.call.* or
14488 .mips16.fn.* sections. If a stub T for function F is in section S,
14489 the first relocation in section S must be against F; this is how the
14490 linker determines the target function. All relocations that might
14491 resolve to T must also be against F. We therefore have the following
14492 restrictions, which are given in an intentionally-redundant way:
14494 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14497 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14498 if that stub might be used.
14500 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14503 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14504 that stub might be used.
14506 There is a further restriction:
14508 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14509 on targets with in-place addends; the relocation field cannot
14510 encode the low bit.
14512 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14513 against a MIPS16 symbol.
14515 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14516 relocation against some symbol R, no relocation against R may be
14517 reduced. (Note that this deals with (2) as well as (1) because
14518 relocations against global symbols will never be reduced on ELF
14519 targets.) This approach is a little simpler than trying to detect
14520 stub sections, and gives the "all or nothing" per-symbol consistency
14521 that we have for MIPS16 symbols. */
14523 && fixp->fx_subsy == NULL
14524 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14525 || *symbol_get_tc (fixp->fx_addsy)))
14532 /* Translate internal representation of relocation info to BFD target
14536 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14538 static arelent *retval[4];
14540 bfd_reloc_code_real_type code;
14542 memset (retval, 0, sizeof(retval));
14543 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14544 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14545 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14546 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14548 if (fixp->fx_pcrel)
14550 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14552 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14553 Relocations want only the symbol offset. */
14554 reloc->addend = fixp->fx_addnumber + reloc->address;
14557 /* A gruesome hack which is a result of the gruesome gas
14558 reloc handling. What's worse, for COFF (as opposed to
14559 ECOFF), we might need yet another copy of reloc->address.
14560 See bfd_install_relocation. */
14561 reloc->addend += reloc->address;
14565 reloc->addend = fixp->fx_addnumber;
14567 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14568 entry to be used in the relocation's section offset. */
14569 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14571 reloc->address = reloc->addend;
14575 code = fixp->fx_r_type;
14577 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14578 if (reloc->howto == NULL)
14580 as_bad_where (fixp->fx_file, fixp->fx_line,
14581 _("Can not represent %s relocation in this object file format"),
14582 bfd_get_reloc_code_name (code));
14589 /* Relax a machine dependent frag. This returns the amount by which
14590 the current size of the frag should change. */
14593 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14595 if (RELAX_BRANCH_P (fragp->fr_subtype))
14597 offsetT old_var = fragp->fr_var;
14599 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14601 return fragp->fr_var - old_var;
14604 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14607 if (mips16_extended_frag (fragp, NULL, stretch))
14609 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14611 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14616 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14618 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14625 /* Convert a machine dependent frag. */
14628 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14630 if (RELAX_BRANCH_P (fragp->fr_subtype))
14633 unsigned long insn;
14637 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14639 if (target_big_endian)
14640 insn = bfd_getb32 (buf);
14642 insn = bfd_getl32 (buf);
14644 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14646 /* We generate a fixup instead of applying it right now
14647 because, if there are linker relaxations, we're going to
14648 need the relocations. */
14649 exp.X_op = O_symbol;
14650 exp.X_add_symbol = fragp->fr_symbol;
14651 exp.X_add_number = fragp->fr_offset;
14653 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14654 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14655 fixp->fx_file = fragp->fr_file;
14656 fixp->fx_line = fragp->fr_line;
14658 md_number_to_chars ((char *) buf, insn, 4);
14665 as_warn_where (fragp->fr_file, fragp->fr_line,
14666 _("Relaxed out-of-range branch into a jump"));
14668 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14671 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14673 /* Reverse the branch. */
14674 switch ((insn >> 28) & 0xf)
14677 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14678 have the condition reversed by tweaking a single
14679 bit, and their opcodes all have 0x4???????. */
14680 gas_assert ((insn & 0xf1000000) == 0x41000000);
14681 insn ^= 0x00010000;
14685 /* bltz 0x04000000 bgez 0x04010000
14686 bltzal 0x04100000 bgezal 0x04110000 */
14687 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14688 insn ^= 0x00010000;
14692 /* beq 0x10000000 bne 0x14000000
14693 blez 0x18000000 bgtz 0x1c000000 */
14694 insn ^= 0x04000000;
14702 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14704 /* Clear the and-link bit. */
14705 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14707 /* bltzal 0x04100000 bgezal 0x04110000
14708 bltzall 0x04120000 bgezall 0x04130000 */
14709 insn &= ~0x00100000;
14712 /* Branch over the branch (if the branch was likely) or the
14713 full jump (not likely case). Compute the offset from the
14714 current instruction to branch to. */
14715 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14719 /* How many bytes in instructions we've already emitted? */
14720 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14721 /* How many bytes in instructions from here to the end? */
14722 i = fragp->fr_var - i;
14724 /* Convert to instruction count. */
14726 /* Branch counts from the next instruction. */
14729 /* Branch over the jump. */
14730 md_number_to_chars ((char *) buf, insn, 4);
14734 md_number_to_chars ((char *) buf, 0, 4);
14737 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14739 /* beql $0, $0, 2f */
14741 /* Compute the PC offset from the current instruction to
14742 the end of the variable frag. */
14743 /* How many bytes in instructions we've already emitted? */
14744 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14745 /* How many bytes in instructions from here to the end? */
14746 i = fragp->fr_var - i;
14747 /* Convert to instruction count. */
14749 /* Don't decrement i, because we want to branch over the
14753 md_number_to_chars ((char *) buf, insn, 4);
14756 md_number_to_chars ((char *) buf, 0, 4);
14761 if (mips_pic == NO_PIC)
14764 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14765 ? 0x0c000000 : 0x08000000);
14766 exp.X_op = O_symbol;
14767 exp.X_add_symbol = fragp->fr_symbol;
14768 exp.X_add_number = fragp->fr_offset;
14770 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14771 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14772 fixp->fx_file = fragp->fr_file;
14773 fixp->fx_line = fragp->fr_line;
14775 md_number_to_chars ((char *) buf, insn, 4);
14780 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14782 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14783 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14784 insn |= at << OP_SH_RT;
14785 exp.X_op = O_symbol;
14786 exp.X_add_symbol = fragp->fr_symbol;
14787 exp.X_add_number = fragp->fr_offset;
14789 if (fragp->fr_offset)
14791 exp.X_add_symbol = make_expr_symbol (&exp);
14792 exp.X_add_number = 0;
14795 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14796 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14797 fixp->fx_file = fragp->fr_file;
14798 fixp->fx_line = fragp->fr_line;
14800 md_number_to_chars ((char *) buf, insn, 4);
14803 if (mips_opts.isa == ISA_MIPS1)
14806 md_number_to_chars ((char *) buf, 0, 4);
14810 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14811 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14812 insn |= at << OP_SH_RS | at << OP_SH_RT;
14814 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14815 4, &exp, FALSE, BFD_RELOC_LO16);
14816 fixp->fx_file = fragp->fr_file;
14817 fixp->fx_line = fragp->fr_line;
14819 md_number_to_chars ((char *) buf, insn, 4);
14823 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14827 insn |= at << OP_SH_RS;
14829 md_number_to_chars ((char *) buf, insn, 4);
14834 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14835 + fragp->fr_fix + fragp->fr_var);
14837 fragp->fr_fix += fragp->fr_var;
14842 if (RELAX_MIPS16_P (fragp->fr_subtype))
14845 const struct mips16_immed_operand *op;
14846 bfd_boolean small, ext;
14849 unsigned long insn;
14850 bfd_boolean use_extend;
14851 unsigned short extend;
14853 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14854 op = mips16_immed_operands;
14855 while (op->type != type)
14858 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14869 val = resolve_symbol_value (fragp->fr_symbol);
14874 addr = fragp->fr_address + fragp->fr_fix;
14876 /* The rules for the base address of a PC relative reloc are
14877 complicated; see mips16_extended_frag. */
14878 if (type == 'p' || type == 'q')
14883 /* Ignore the low bit in the target, since it will be
14884 set for a text label. */
14885 if ((val & 1) != 0)
14888 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14890 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14893 addr &= ~ (addressT) ((1 << op->shift) - 1);
14896 /* Make sure the section winds up with the alignment we have
14899 record_alignment (asec, op->shift);
14903 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14904 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14905 as_warn_where (fragp->fr_file, fragp->fr_line,
14906 _("extended instruction in delay slot"));
14908 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14910 if (target_big_endian)
14911 insn = bfd_getb16 (buf);
14913 insn = bfd_getl16 (buf);
14915 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14916 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14917 small, ext, &insn, &use_extend, &extend);
14921 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14922 fragp->fr_fix += 2;
14926 md_number_to_chars ((char *) buf, insn, 2);
14927 fragp->fr_fix += 2;
14935 first = RELAX_FIRST (fragp->fr_subtype);
14936 second = RELAX_SECOND (fragp->fr_subtype);
14937 fixp = (fixS *) fragp->fr_opcode;
14939 /* Possibly emit a warning if we've chosen the longer option. */
14940 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14941 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14943 const char *msg = macro_warning (fragp->fr_subtype);
14945 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14948 /* Go through all the fixups for the first sequence. Disable them
14949 (by marking them as done) if we're going to use the second
14950 sequence instead. */
14952 && fixp->fx_frag == fragp
14953 && fixp->fx_where < fragp->fr_fix - second)
14955 if (fragp->fr_subtype & RELAX_USE_SECOND)
14957 fixp = fixp->fx_next;
14960 /* Go through the fixups for the second sequence. Disable them if
14961 we're going to use the first sequence, otherwise adjust their
14962 addresses to account for the relaxation. */
14963 while (fixp && fixp->fx_frag == fragp)
14965 if (fragp->fr_subtype & RELAX_USE_SECOND)
14966 fixp->fx_where -= first;
14969 fixp = fixp->fx_next;
14972 /* Now modify the frag contents. */
14973 if (fragp->fr_subtype & RELAX_USE_SECOND)
14977 start = fragp->fr_literal + fragp->fr_fix - first - second;
14978 memmove (start, start + first, second);
14979 fragp->fr_fix -= first;
14982 fragp->fr_fix -= second;
14988 /* This function is called after the relocs have been generated.
14989 We've been storing mips16 text labels as odd. Here we convert them
14990 back to even for the convenience of the debugger. */
14993 mips_frob_file_after_relocs (void)
14996 unsigned int count, i;
15001 syms = bfd_get_outsymbols (stdoutput);
15002 count = bfd_get_symcount (stdoutput);
15003 for (i = 0; i < count; i++, syms++)
15005 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15006 && ((*syms)->value & 1) != 0)
15008 (*syms)->value &= ~1;
15009 /* If the symbol has an odd size, it was probably computed
15010 incorrectly, so adjust that as well. */
15011 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15012 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15019 /* This function is called whenever a label is defined, including fake
15020 labels instantiated off the dot special symbol. It is used when
15021 handling branch delays; if a branch has a label, we assume we cannot
15022 move it. This also bumps the value of the symbol by 1 in compressed
15026 mips_record_label (symbolS *sym)
15028 segment_info_type *si = seg_info (now_seg);
15029 struct insn_label_list *l;
15031 if (free_insn_labels == NULL)
15032 l = (struct insn_label_list *) xmalloc (sizeof *l);
15035 l = free_insn_labels;
15036 free_insn_labels = l->next;
15040 l->next = si->label_list;
15041 si->label_list = l;
15044 /* This function is called as tc_frob_label() whenever a label is defined
15045 and adds a DWARF-2 record we only want for true labels. */
15048 mips_define_label (symbolS *sym)
15050 mips_record_label (sym);
15052 dwarf2_emit_label (sym);
15056 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15058 /* Some special processing for a MIPS ELF file. */
15061 mips_elf_final_processing (void)
15063 /* Write out the register information. */
15064 if (mips_abi != N64_ABI)
15068 s.ri_gprmask = mips_gprmask;
15069 s.ri_cprmask[0] = mips_cprmask[0];
15070 s.ri_cprmask[1] = mips_cprmask[1];
15071 s.ri_cprmask[2] = mips_cprmask[2];
15072 s.ri_cprmask[3] = mips_cprmask[3];
15073 /* The gp_value field is set by the MIPS ELF backend. */
15075 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15076 ((Elf32_External_RegInfo *)
15077 mips_regmask_frag));
15081 Elf64_Internal_RegInfo s;
15083 s.ri_gprmask = mips_gprmask;
15085 s.ri_cprmask[0] = mips_cprmask[0];
15086 s.ri_cprmask[1] = mips_cprmask[1];
15087 s.ri_cprmask[2] = mips_cprmask[2];
15088 s.ri_cprmask[3] = mips_cprmask[3];
15089 /* The gp_value field is set by the MIPS ELF backend. */
15091 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15092 ((Elf64_External_RegInfo *)
15093 mips_regmask_frag));
15096 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15097 sort of BFD interface for this. */
15098 if (mips_any_noreorder)
15099 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15100 if (mips_pic != NO_PIC)
15102 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15103 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15106 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15108 /* Set MIPS ELF flags for ASEs. */
15109 /* We may need to define a new flag for DSP ASE, and set this flag when
15110 file_ase_dsp is true. */
15111 /* Same for DSP R2. */
15112 /* We may need to define a new flag for MT ASE, and set this flag when
15113 file_ase_mt is true. */
15114 if (file_ase_mips16)
15115 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15116 #if 0 /* XXX FIXME */
15117 if (file_ase_mips3d)
15118 elf_elfheader (stdoutput)->e_flags |= ???;
15121 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15123 /* Set the MIPS ELF ABI flags. */
15124 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15125 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15126 else if (mips_abi == O64_ABI)
15127 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15128 else if (mips_abi == EABI_ABI)
15130 if (!file_mips_gp32)
15131 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15133 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15135 else if (mips_abi == N32_ABI)
15136 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15138 /* Nothing to do for N64_ABI. */
15140 if (mips_32bitmode)
15141 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15143 #if 0 /* XXX FIXME */
15144 /* 32 bit code with 64 bit FP registers. */
15145 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15146 elf_elfheader (stdoutput)->e_flags |= ???;
15150 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15152 typedef struct proc {
15154 symbolS *func_end_sym;
15155 unsigned long reg_mask;
15156 unsigned long reg_offset;
15157 unsigned long fpreg_mask;
15158 unsigned long fpreg_offset;
15159 unsigned long frame_offset;
15160 unsigned long frame_reg;
15161 unsigned long pc_reg;
15164 static procS cur_proc;
15165 static procS *cur_proc_ptr;
15166 static int numprocs;
15168 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15172 mips_nop_opcode (void)
15174 return seg_info (now_seg)->tc_segment_info_data.mips16;
15177 /* Fill in an rs_align_code fragment. This only needs to do something
15178 for MIPS16 code, where 0 is not a nop. */
15181 mips_handle_align (fragS *fragp)
15184 int bytes, size, excess;
15187 if (fragp->fr_type != rs_align_code)
15190 p = fragp->fr_literal + fragp->fr_fix;
15193 opcode = mips16_nop_insn.insn_opcode;
15198 opcode = nop_insn.insn_opcode;
15202 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15203 excess = bytes % size;
15206 /* If we're not inserting a whole number of instructions,
15207 pad the end of the fixed part of the frag with zeros. */
15208 memset (p, 0, excess);
15210 fragp->fr_fix += excess;
15213 md_number_to_chars (p, opcode, size);
15214 fragp->fr_var = size;
15218 md_obj_begin (void)
15225 /* Check for premature end, nesting errors, etc. */
15227 as_warn (_("missing .end at end of assembly"));
15236 if (*input_line_pointer == '-')
15238 ++input_line_pointer;
15241 if (!ISDIGIT (*input_line_pointer))
15242 as_bad (_("expected simple number"));
15243 if (input_line_pointer[0] == '0')
15245 if (input_line_pointer[1] == 'x')
15247 input_line_pointer += 2;
15248 while (ISXDIGIT (*input_line_pointer))
15251 val |= hex_value (*input_line_pointer++);
15253 return negative ? -val : val;
15257 ++input_line_pointer;
15258 while (ISDIGIT (*input_line_pointer))
15261 val |= *input_line_pointer++ - '0';
15263 return negative ? -val : val;
15266 if (!ISDIGIT (*input_line_pointer))
15268 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15269 *input_line_pointer, *input_line_pointer);
15270 as_warn (_("invalid number"));
15273 while (ISDIGIT (*input_line_pointer))
15276 val += *input_line_pointer++ - '0';
15278 return negative ? -val : val;
15281 /* The .file directive; just like the usual .file directive, but there
15282 is an initial number which is the ECOFF file index. In the non-ECOFF
15283 case .file implies DWARF-2. */
15286 s_mips_file (int x ATTRIBUTE_UNUSED)
15288 static int first_file_directive = 0;
15290 if (ECOFF_DEBUGGING)
15299 filename = dwarf2_directive_file (0);
15301 /* Versions of GCC up to 3.1 start files with a ".file"
15302 directive even for stabs output. Make sure that this
15303 ".file" is handled. Note that you need a version of GCC
15304 after 3.1 in order to support DWARF-2 on MIPS. */
15305 if (filename != NULL && ! first_file_directive)
15307 (void) new_logical_line (filename, -1);
15308 s_app_file_string (filename, 0);
15310 first_file_directive = 1;
15314 /* The .loc directive, implying DWARF-2. */
15317 s_mips_loc (int x ATTRIBUTE_UNUSED)
15319 if (!ECOFF_DEBUGGING)
15320 dwarf2_directive_loc (0);
15323 /* The .end directive. */
15326 s_mips_end (int x ATTRIBUTE_UNUSED)
15330 /* Following functions need their own .frame and .cprestore directives. */
15331 mips_frame_reg_valid = 0;
15332 mips_cprestore_valid = 0;
15334 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15337 demand_empty_rest_of_line ();
15342 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15343 as_warn (_(".end not in text section"));
15347 as_warn (_(".end directive without a preceding .ent directive."));
15348 demand_empty_rest_of_line ();
15354 gas_assert (S_GET_NAME (p));
15355 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15356 as_warn (_(".end symbol does not match .ent symbol."));
15358 if (debug_type == DEBUG_STABS)
15359 stabs_generate_asm_endfunc (S_GET_NAME (p),
15363 as_warn (_(".end directive missing or unknown symbol"));
15366 /* Create an expression to calculate the size of the function. */
15367 if (p && cur_proc_ptr)
15369 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15370 expressionS *exp = xmalloc (sizeof (expressionS));
15373 exp->X_op = O_subtract;
15374 exp->X_add_symbol = symbol_temp_new_now ();
15375 exp->X_op_symbol = p;
15376 exp->X_add_number = 0;
15378 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15381 /* Generate a .pdr section. */
15382 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15384 segT saved_seg = now_seg;
15385 subsegT saved_subseg = now_subseg;
15389 #ifdef md_flush_pending_output
15390 md_flush_pending_output ();
15393 gas_assert (pdr_seg);
15394 subseg_set (pdr_seg, 0);
15396 /* Write the symbol. */
15397 exp.X_op = O_symbol;
15398 exp.X_add_symbol = p;
15399 exp.X_add_number = 0;
15400 emit_expr (&exp, 4);
15402 fragp = frag_more (7 * 4);
15404 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15405 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15406 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15407 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15408 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15409 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15410 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15412 subseg_set (saved_seg, saved_subseg);
15414 #endif /* OBJ_ELF */
15416 cur_proc_ptr = NULL;
15419 /* The .aent and .ent directives. */
15422 s_mips_ent (int aent)
15426 symbolP = get_symbol ();
15427 if (*input_line_pointer == ',')
15428 ++input_line_pointer;
15429 SKIP_WHITESPACE ();
15430 if (ISDIGIT (*input_line_pointer)
15431 || *input_line_pointer == '-')
15434 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15435 as_warn (_(".ent or .aent not in text section."));
15437 if (!aent && cur_proc_ptr)
15438 as_warn (_("missing .end"));
15442 /* This function needs its own .frame and .cprestore directives. */
15443 mips_frame_reg_valid = 0;
15444 mips_cprestore_valid = 0;
15446 cur_proc_ptr = &cur_proc;
15447 memset (cur_proc_ptr, '\0', sizeof (procS));
15449 cur_proc_ptr->func_sym = symbolP;
15453 if (debug_type == DEBUG_STABS)
15454 stabs_generate_asm_func (S_GET_NAME (symbolP),
15455 S_GET_NAME (symbolP));
15458 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15460 demand_empty_rest_of_line ();
15463 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15464 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15465 s_mips_frame is used so that we can set the PDR information correctly.
15466 We can't use the ecoff routines because they make reference to the ecoff
15467 symbol table (in the mdebug section). */
15470 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15473 if (IS_ELF && !ECOFF_DEBUGGING)
15477 if (cur_proc_ptr == (procS *) NULL)
15479 as_warn (_(".frame outside of .ent"));
15480 demand_empty_rest_of_line ();
15484 cur_proc_ptr->frame_reg = tc_get_register (1);
15486 SKIP_WHITESPACE ();
15487 if (*input_line_pointer++ != ','
15488 || get_absolute_expression_and_terminator (&val) != ',')
15490 as_warn (_("Bad .frame directive"));
15491 --input_line_pointer;
15492 demand_empty_rest_of_line ();
15496 cur_proc_ptr->frame_offset = val;
15497 cur_proc_ptr->pc_reg = tc_get_register (0);
15499 demand_empty_rest_of_line ();
15502 #endif /* OBJ_ELF */
15506 /* The .fmask and .mask directives. If the mdebug section is present
15507 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15508 embedded targets, s_mips_mask is used so that we can set the PDR
15509 information correctly. We can't use the ecoff routines because they
15510 make reference to the ecoff symbol table (in the mdebug section). */
15513 s_mips_mask (int reg_type)
15516 if (IS_ELF && !ECOFF_DEBUGGING)
15520 if (cur_proc_ptr == (procS *) NULL)
15522 as_warn (_(".mask/.fmask outside of .ent"));
15523 demand_empty_rest_of_line ();
15527 if (get_absolute_expression_and_terminator (&mask) != ',')
15529 as_warn (_("Bad .mask/.fmask directive"));
15530 --input_line_pointer;
15531 demand_empty_rest_of_line ();
15535 off = get_absolute_expression ();
15537 if (reg_type == 'F')
15539 cur_proc_ptr->fpreg_mask = mask;
15540 cur_proc_ptr->fpreg_offset = off;
15544 cur_proc_ptr->reg_mask = mask;
15545 cur_proc_ptr->reg_offset = off;
15548 demand_empty_rest_of_line ();
15551 #endif /* OBJ_ELF */
15552 s_ignore (reg_type);
15555 /* A table describing all the processors gas knows about. Names are
15556 matched in the order listed.
15558 To ease comparison, please keep this table in the same order as
15559 gcc's mips_cpu_info_table[]. */
15560 static const struct mips_cpu_info mips_cpu_info_table[] =
15562 /* Entries for generic ISAs */
15563 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15564 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15565 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15566 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15567 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15568 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15569 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15570 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15571 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15574 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15575 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15576 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15579 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15582 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15583 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15584 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15585 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15586 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15587 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15588 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15589 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15590 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15591 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15592 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15593 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15594 /* ST Microelectronics Loongson 2E and 2F cores */
15595 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15596 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15599 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15600 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15601 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15602 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15603 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15604 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15605 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15606 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15607 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15608 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15609 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15610 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15611 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15612 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15613 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15616 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15617 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15618 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15619 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15621 /* MIPS 32 Release 2 */
15622 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15623 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15624 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15625 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15626 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15627 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15628 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15629 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15630 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15631 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15632 /* Deprecated forms of the above. */
15633 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15634 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15635 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15636 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15637 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15638 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15639 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15640 /* Deprecated forms of the above. */
15641 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15642 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15643 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15644 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15645 ISA_MIPS32R2, CPU_MIPS32R2 },
15646 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15647 ISA_MIPS32R2, CPU_MIPS32R2 },
15648 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15649 ISA_MIPS32R2, CPU_MIPS32R2 },
15650 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15651 ISA_MIPS32R2, CPU_MIPS32R2 },
15652 /* Deprecated forms of the above. */
15653 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15654 ISA_MIPS32R2, CPU_MIPS32R2 },
15655 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15656 ISA_MIPS32R2, CPU_MIPS32R2 },
15657 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15658 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15659 ISA_MIPS32R2, CPU_MIPS32R2 },
15660 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15661 ISA_MIPS32R2, CPU_MIPS32R2 },
15662 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15663 ISA_MIPS32R2, CPU_MIPS32R2 },
15664 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15665 ISA_MIPS32R2, CPU_MIPS32R2 },
15666 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15667 ISA_MIPS32R2, CPU_MIPS32R2 },
15668 /* Deprecated forms of the above. */
15669 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15670 ISA_MIPS32R2, CPU_MIPS32R2 },
15671 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15672 ISA_MIPS32R2, CPU_MIPS32R2 },
15673 /* 1004K cores are multiprocessor versions of the 34K. */
15674 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15675 ISA_MIPS32R2, CPU_MIPS32R2 },
15676 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15677 ISA_MIPS32R2, CPU_MIPS32R2 },
15678 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15679 ISA_MIPS32R2, CPU_MIPS32R2 },
15680 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15681 ISA_MIPS32R2, CPU_MIPS32R2 },
15684 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15685 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15686 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15687 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15689 /* Broadcom SB-1 CPU core */
15690 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15691 ISA_MIPS64, CPU_SB1 },
15692 /* Broadcom SB-1A CPU core */
15693 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15694 ISA_MIPS64, CPU_SB1 },
15696 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15698 /* MIPS 64 Release 2 */
15700 /* Cavium Networks Octeon CPU core */
15701 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15704 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15711 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15712 with a final "000" replaced by "k". Ignore case.
15714 Note: this function is shared between GCC and GAS. */
15717 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15719 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15720 given++, canonical++;
15722 return ((*given == 0 && *canonical == 0)
15723 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15727 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15728 CPU name. We've traditionally allowed a lot of variation here.
15730 Note: this function is shared between GCC and GAS. */
15733 mips_matching_cpu_name_p (const char *canonical, const char *given)
15735 /* First see if the name matches exactly, or with a final "000"
15736 turned into "k". */
15737 if (mips_strict_matching_cpu_name_p (canonical, given))
15740 /* If not, try comparing based on numerical designation alone.
15741 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15742 if (TOLOWER (*given) == 'r')
15744 if (!ISDIGIT (*given))
15747 /* Skip over some well-known prefixes in the canonical name,
15748 hoping to find a number there too. */
15749 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15751 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15753 else if (TOLOWER (canonical[0]) == 'r')
15756 return mips_strict_matching_cpu_name_p (canonical, given);
15760 /* Parse an option that takes the name of a processor as its argument.
15761 OPTION is the name of the option and CPU_STRING is the argument.
15762 Return the corresponding processor enumeration if the CPU_STRING is
15763 recognized, otherwise report an error and return null.
15765 A similar function exists in GCC. */
15767 static const struct mips_cpu_info *
15768 mips_parse_cpu (const char *option, const char *cpu_string)
15770 const struct mips_cpu_info *p;
15772 /* 'from-abi' selects the most compatible architecture for the given
15773 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15774 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15775 version. Look first at the -mgp options, if given, otherwise base
15776 the choice on MIPS_DEFAULT_64BIT.
15778 Treat NO_ABI like the EABIs. One reason to do this is that the
15779 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15780 architecture. This code picks MIPS I for 'mips' and MIPS III for
15781 'mips64', just as we did in the days before 'from-abi'. */
15782 if (strcasecmp (cpu_string, "from-abi") == 0)
15784 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15785 return mips_cpu_info_from_isa (ISA_MIPS1);
15787 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15788 return mips_cpu_info_from_isa (ISA_MIPS3);
15790 if (file_mips_gp32 >= 0)
15791 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15793 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15798 /* 'default' has traditionally been a no-op. Probably not very useful. */
15799 if (strcasecmp (cpu_string, "default") == 0)
15802 for (p = mips_cpu_info_table; p->name != 0; p++)
15803 if (mips_matching_cpu_name_p (p->name, cpu_string))
15806 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15810 /* Return the canonical processor information for ISA (a member of the
15811 ISA_MIPS* enumeration). */
15813 static const struct mips_cpu_info *
15814 mips_cpu_info_from_isa (int isa)
15818 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15819 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15820 && isa == mips_cpu_info_table[i].isa)
15821 return (&mips_cpu_info_table[i]);
15826 static const struct mips_cpu_info *
15827 mips_cpu_info_from_arch (int arch)
15831 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15832 if (arch == mips_cpu_info_table[i].cpu)
15833 return (&mips_cpu_info_table[i]);
15839 show (FILE *stream, const char *string, int *col_p, int *first_p)
15843 fprintf (stream, "%24s", "");
15848 fprintf (stream, ", ");
15852 if (*col_p + strlen (string) > 72)
15854 fprintf (stream, "\n%24s", "");
15858 fprintf (stream, "%s", string);
15859 *col_p += strlen (string);
15865 md_show_usage (FILE *stream)
15870 fprintf (stream, _("\
15872 -EB generate big endian output\n\
15873 -EL generate little endian output\n\
15874 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15875 -G NUM allow referencing objects up to NUM bytes\n\
15876 implicitly with the gp register [default 8]\n"));
15877 fprintf (stream, _("\
15878 -mips1 generate MIPS ISA I instructions\n\
15879 -mips2 generate MIPS ISA II instructions\n\
15880 -mips3 generate MIPS ISA III instructions\n\
15881 -mips4 generate MIPS ISA IV instructions\n\
15882 -mips5 generate MIPS ISA V instructions\n\
15883 -mips32 generate MIPS32 ISA instructions\n\
15884 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15885 -mips64 generate MIPS64 ISA instructions\n\
15886 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15887 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15891 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15892 show (stream, mips_cpu_info_table[i].name, &column, &first);
15893 show (stream, "from-abi", &column, &first);
15894 fputc ('\n', stream);
15896 fprintf (stream, _("\
15897 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15898 -no-mCPU don't generate code specific to CPU.\n\
15899 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15903 show (stream, "3900", &column, &first);
15904 show (stream, "4010", &column, &first);
15905 show (stream, "4100", &column, &first);
15906 show (stream, "4650", &column, &first);
15907 fputc ('\n', stream);
15909 fprintf (stream, _("\
15910 -mips16 generate mips16 instructions\n\
15911 -no-mips16 do not generate mips16 instructions\n"));
15912 fprintf (stream, _("\
15913 -msmartmips generate smartmips instructions\n\
15914 -mno-smartmips do not generate smartmips instructions\n"));
15915 fprintf (stream, _("\
15916 -mdsp generate DSP instructions\n\
15917 -mno-dsp do not generate DSP instructions\n"));
15918 fprintf (stream, _("\
15919 -mdspr2 generate DSP R2 instructions\n\
15920 -mno-dspr2 do not generate DSP R2 instructions\n"));
15921 fprintf (stream, _("\
15922 -mmt generate MT instructions\n\
15923 -mno-mt do not generate MT instructions\n"));
15924 fprintf (stream, _("\
15925 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15926 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15927 -mfix-vr4120 work around certain VR4120 errata\n\
15928 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15929 -mfix-24k insert a nop after ERET and DERET instructions\n\
15930 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15931 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15932 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15933 -msym32 assume all symbols have 32-bit values\n\
15934 -O0 remove unneeded NOPs, do not swap branches\n\
15935 -O remove unneeded NOPs and swap branches\n\
15936 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15937 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15938 fprintf (stream, _("\
15939 -mhard-float allow floating-point instructions\n\
15940 -msoft-float do not allow floating-point instructions\n\
15941 -msingle-float only allow 32-bit floating-point operations\n\
15942 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15943 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15946 fprintf (stream, _("\
15947 -KPIC, -call_shared generate SVR4 position independent code\n\
15948 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15949 -mvxworks-pic generate VxWorks position independent code\n\
15950 -non_shared do not generate code that can operate with DSOs\n\
15951 -xgot assume a 32 bit GOT\n\
15952 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15953 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15954 position dependent (non shared) code\n\
15955 -mabi=ABI create ABI conformant object file for:\n"));
15959 show (stream, "32", &column, &first);
15960 show (stream, "o64", &column, &first);
15961 show (stream, "n32", &column, &first);
15962 show (stream, "64", &column, &first);
15963 show (stream, "eabi", &column, &first);
15965 fputc ('\n', stream);
15967 fprintf (stream, _("\
15968 -32 create o32 ABI object file (default)\n\
15969 -n32 create n32 ABI object file\n\
15970 -64 create 64 ABI object file\n"));
15976 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
15978 if (HAVE_64BIT_SYMBOLS)
15979 return dwarf2_format_64bit_irix;
15981 return dwarf2_format_32bit;
15986 mips_dwarf2_addr_size (void)
15988 if (HAVE_64BIT_OBJECTS)
15994 /* Standard calling conventions leave the CFA at SP on entry. */
15996 mips_cfi_frame_initial_instructions (void)
15998 cfi_add_CFA_def_cfa_register (SP);
16002 tc_mips_regname_to_dw2regnum (char *regname)
16004 unsigned int regnum = -1;
16007 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))