1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
40 #include "dwarf2dbg.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
80 int mips_flag_mdebug = -1;
84 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
85 static char *mips_regmask_frag;
91 #define PIC_CALL_REG 25
99 #define ILLEGAL_REG (32)
101 /* Allow override of standard little-endian ECOFF format. */
103 #ifndef ECOFF_LITTLE_FORMAT
104 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* The ABI to use. */
131 /* MIPS ABI we are using for this output file. */
132 static enum mips_abi_level mips_abi = NO_ABI;
134 /* This is the set of options which may be modified by the .set
135 pseudo-op. We use a struct so that .set push and .set pop are more
138 struct mips_set_options
140 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
141 if it has not been initialized. Changed by `.set mipsN', and the
142 -mipsN command line option, and the default CPU. */
144 /* Enabled Application Specific Extensions (ASEs). These are set to -1
145 if they have not been initialized. Changed by `.set <asename>', by
146 command line options, and based on the default architecture. */
149 /* Whether we are assembling for the mips16 processor. 0 if we are
150 not, 1 if we are, and -1 if the value has not been initialized.
151 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
152 -nomips16 command line options, and the default CPU. */
154 /* Non-zero if we should not reorder instructions. Changed by `.set
155 reorder' and `.set noreorder'. */
157 /* Non-zero if we should not permit the $at ($1) register to be used
158 in instructions. Changed by `.set at' and `.set noat'. */
160 /* Non-zero if we should warn when a macro instruction expands into
161 more than one machine instruction. Changed by `.set nomacro' and
163 int warn_about_macros;
164 /* Non-zero if we should not move instructions. Changed by `.set
165 move', `.set volatile', `.set nomove', and `.set novolatile'. */
167 /* Non-zero if we should not optimize branches by moving the target
168 of the branch into the delay slot. Actually, we don't perform
169 this optimization anyhow. Changed by `.set bopt' and `.set
172 /* Non-zero if we should not autoextend mips16 instructions.
173 Changed by `.set autoextend' and `.set noautoextend'. */
175 /* Restrict general purpose registers and floating point registers
176 to 32 bit. This is initially determined when -mgp32 or -mfp32
177 is passed but can changed if the assembler code uses .set mipsN. */
182 /* True if -mgp32 was passed. */
183 static int file_mips_gp32 = -1;
185 /* True if -mfp32 was passed. */
186 static int file_mips_fp32 = -1;
188 /* This is the struct we use to hold the current set of options. Note
189 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
190 -1 to indicate that they have not been initialized. */
192 static struct mips_set_options mips_opts =
194 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask;
201 unsigned long mips_cprmask[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa = ISA_UNKNOWN;
206 /* True if -mips16 was passed or implied by arguments passed on the
207 command line (e.g., by -march). */
208 static int file_ase_mips16;
210 /* True if -mips3d was passed or implied by arguments passed on the
211 command line (e.g., by -march). */
212 static int file_ase_mips3d;
214 /* True if -mdmx was passed or implied by arguments passed on the
215 command line (e.g., by -march). */
216 static int file_ase_mdmx;
218 /* The argument of the -march= flag. The architecture we are assembling. */
219 static int mips_arch = CPU_UNKNOWN;
220 static const char *mips_arch_string;
221 static const struct mips_cpu_info *mips_arch_info;
223 /* The argument of the -mtune= flag. The architecture for which we
225 static int mips_tune = CPU_UNKNOWN;
226 static const char *mips_tune_string;
227 static const struct mips_cpu_info *mips_tune_info;
229 /* True when generating 32-bit code for a 64-bit processor. */
230 static int mips_32bitmode = 0;
232 /* Some ISA's have delay slots for instructions which read or write
233 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
234 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
235 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
236 delay slot in this ISA. The uses of this macro assume that any
237 ISA that has delay slots for one of these, has them for all. They
238 also assume that ISAs which don't have delays for these insns, don't
239 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
240 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
242 || (ISA) == ISA_MIPS2 \
243 || (ISA) == ISA_MIPS3 \
246 /* True if the given ABI requires 32-bit registers. */
247 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
249 /* Likewise 64-bit registers. */
250 #define ABI_NEEDS_64BIT_REGS(ABI) \
252 || (ABI) == N64_ABI \
255 /* Return true if ISA supports 64 bit gp register instructions. */
256 #define ISA_HAS_64BIT_REGS(ISA) ( \
258 || (ISA) == ISA_MIPS4 \
259 || (ISA) == ISA_MIPS5 \
260 || (ISA) == ISA_MIPS64 \
263 #define HAVE_32BIT_GPRS \
264 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
266 #define HAVE_32BIT_FPRS \
267 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
274 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
276 /* We can only have 64bit addresses if the object file format
278 #define HAVE_32BIT_ADDRESSES \
280 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
281 || ! HAVE_64BIT_OBJECTS) \
282 && mips_pic != EMBEDDED_PIC))
284 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
286 /* Return true if the given CPU supports the MIPS16 ASE. */
287 #define CPU_HAS_MIPS16(cpu) \
288 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0)
290 /* Return true if the given CPU supports the MIPS3D ASE. */
291 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
294 /* Return true if the given CPU supports the MDMX ASE. */
295 #define CPU_HAS_MDMX(cpu) (false \
298 /* Whether the processor uses hardware interlocks to protect
299 reads from the HI and LO registers, and thus does not
300 require nops to be inserted. */
302 #define hilo_interlocks (mips_arch == CPU_R4010 \
303 || mips_arch == CPU_SB1 \
306 /* Whether the processor uses hardware interlocks to protect reads
307 from the GPRs, and thus does not require nops to be inserted. */
308 #define gpr_interlocks \
309 (mips_opts.isa != ISA_MIPS1 \
310 || mips_arch == CPU_R3900)
312 /* As with other "interlocks" this is used by hardware that has FP
313 (co-processor) interlocks. */
314 /* Itbl support may require additional care here. */
315 #define cop_interlocks (mips_arch == CPU_R4300 \
316 || mips_arch == CPU_SB1 \
319 /* Is this a mfhi or mflo instruction? */
320 #define MF_HILO_INSN(PINFO) \
321 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
323 /* MIPS PIC level. */
325 enum mips_pic_level mips_pic;
327 /* Warn about all NOPS that the assembler generates. */
328 static int warn_nops = 0;
330 /* 1 if we should generate 32 bit offsets from the $gp register in
331 SVR4_PIC mode. Currently has no meaning in other modes. */
332 static int mips_big_got = 0;
334 /* 1 if trap instructions should used for overflow rather than break
336 static int mips_trap = 0;
338 /* 1 if double width floating point constants should not be constructed
339 by assembling two single width halves into two single width floating
340 point registers which just happen to alias the double width destination
341 register. On some architectures this aliasing can be disabled by a bit
342 in the status register, and the setting of this bit cannot be determined
343 automatically at assemble time. */
344 static int mips_disable_float_construction;
346 /* Non-zero if any .set noreorder directives were used. */
348 static int mips_any_noreorder;
350 /* Non-zero if nops should be inserted when the register referenced in
351 an mfhi/mflo instruction is read in the next two instructions. */
352 static int mips_7000_hilo_fix;
354 /* The size of the small data section. */
355 static unsigned int g_switch_value = 8;
356 /* Whether the -G option was used. */
357 static int g_switch_seen = 0;
362 /* If we can determine in advance that GP optimization won't be
363 possible, we can skip the relaxation stuff that tries to produce
364 GP-relative references. This makes delay slot optimization work
367 This function can only provide a guess, but it seems to work for
368 gcc output. It needs to guess right for gcc, otherwise gcc
369 will put what it thinks is a GP-relative instruction in a branch
372 I don't know if a fix is needed for the SVR4_PIC mode. I've only
373 fixed it for the non-PIC mode. KR 95/04/07 */
374 static int nopic_need_relax PARAMS ((symbolS *, int));
376 /* handle of the OPCODE hash table */
377 static struct hash_control *op_hash = NULL;
379 /* The opcode hash table we use for the mips16. */
380 static struct hash_control *mips16_op_hash = NULL;
382 /* This array holds the chars that always start a comment. If the
383 pre-processor is disabled, these aren't very useful */
384 const char comment_chars[] = "#";
386 /* This array holds the chars that only start a comment at the beginning of
387 a line. If the line seems to have the form '# 123 filename'
388 .line and .file directives will appear in the pre-processed output */
389 /* Note that input_file.c hand checks for '#' at the beginning of the
390 first line of the input file. This is because the compiler outputs
391 #NO_APP at the beginning of its output. */
392 /* Also note that C style comments are always supported. */
393 const char line_comment_chars[] = "#";
395 /* This array holds machine specific line separator characters. */
396 const char line_separator_chars[] = ";";
398 /* Chars that can be used to separate mant from exp in floating point nums */
399 const char EXP_CHARS[] = "eE";
401 /* Chars that mean this number is a floating point constant */
404 const char FLT_CHARS[] = "rRsSfFdDxXpP";
406 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
407 changed in read.c . Ideally it shouldn't have to know about it at all,
408 but nothing is ideal around here.
411 static char *insn_error;
413 static int auto_align = 1;
415 /* When outputting SVR4 PIC code, the assembler needs to know the
416 offset in the stack frame from which to restore the $gp register.
417 This is set by the .cprestore pseudo-op, and saved in this
419 static offsetT mips_cprestore_offset = -1;
421 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
422 more optimizations, it can use a register value instead of a memory-saved
423 offset and even an other register than $gp as global pointer. */
424 static offsetT mips_cpreturn_offset = -1;
425 static int mips_cpreturn_register = -1;
426 static int mips_gp_register = GP;
427 static int mips_gprel_offset = 0;
429 /* Whether mips_cprestore_offset has been set in the current function
430 (or whether it has already been warned about, if not). */
431 static int mips_cprestore_valid = 0;
433 /* This is the register which holds the stack frame, as set by the
434 .frame pseudo-op. This is needed to implement .cprestore. */
435 static int mips_frame_reg = SP;
437 /* Whether mips_frame_reg has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_frame_reg_valid = 0;
441 /* To output NOP instructions correctly, we need to keep information
442 about the previous two instructions. */
444 /* Whether we are optimizing. The default value of 2 means to remove
445 unneeded NOPs and swap branch instructions when possible. A value
446 of 1 means to not swap branches. A value of 0 means to always
448 static int mips_optimize = 2;
450 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
451 equivalent to seeing no -g option at all. */
452 static int mips_debug = 0;
454 /* The previous instruction. */
455 static struct mips_cl_insn prev_insn;
457 /* The instruction before prev_insn. */
458 static struct mips_cl_insn prev_prev_insn;
460 /* If we don't want information for prev_insn or prev_prev_insn, we
461 point the insn_mo field at this dummy integer. */
462 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
464 /* Non-zero if prev_insn is valid. */
465 static int prev_insn_valid;
467 /* The frag for the previous instruction. */
468 static struct frag *prev_insn_frag;
470 /* The offset into prev_insn_frag for the previous instruction. */
471 static long prev_insn_where;
473 /* The reloc type for the previous instruction, if any. */
474 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
476 /* The reloc for the previous instruction, if any. */
477 static fixS *prev_insn_fixp[3];
479 /* Non-zero if the previous instruction was in a delay slot. */
480 static int prev_insn_is_delay_slot;
482 /* Non-zero if the previous instruction was in a .set noreorder. */
483 static int prev_insn_unreordered;
485 /* Non-zero if the previous instruction uses an extend opcode (if
487 static int prev_insn_extended;
489 /* Non-zero if the previous previous instruction was in a .set
491 static int prev_prev_insn_unreordered;
493 /* If this is set, it points to a frag holding nop instructions which
494 were inserted before the start of a noreorder section. If those
495 nops turn out to be unnecessary, the size of the frag can be
497 static fragS *prev_nop_frag;
499 /* The number of nop instructions we created in prev_nop_frag. */
500 static int prev_nop_frag_holds;
502 /* The number of nop instructions that we know we need in
504 static int prev_nop_frag_required;
506 /* The number of instructions we've seen since prev_nop_frag. */
507 static int prev_nop_frag_since;
509 /* For ECOFF and ELF, relocations against symbols are done in two
510 parts, with a HI relocation and a LO relocation. Each relocation
511 has only 16 bits of space to store an addend. This means that in
512 order for the linker to handle carries correctly, it must be able
513 to locate both the HI and the LO relocation. This means that the
514 relocations must appear in order in the relocation table.
516 In order to implement this, we keep track of each unmatched HI
517 relocation. We then sort them so that they immediately precede the
518 corresponding LO relocation. */
523 struct mips_hi_fixup *next;
526 /* The section this fixup is in. */
530 /* The list of unmatched HI relocs. */
532 static struct mips_hi_fixup *mips_hi_fixup_list;
534 /* Map normal MIPS register numbers to mips16 register numbers. */
536 #define X ILLEGAL_REG
537 static const int mips32_to_16_reg_map[] =
539 X, X, 2, 3, 4, 5, 6, 7,
540 X, X, X, X, X, X, X, X,
541 0, 1, X, X, X, X, X, X,
542 X, X, X, X, X, X, X, X
546 /* Map mips16 register numbers to normal MIPS register numbers. */
548 static const unsigned int mips16_to_32_reg_map[] =
550 16, 17, 2, 3, 4, 5, 6, 7
553 /* Since the MIPS does not have multiple forms of PC relative
554 instructions, we do not have to do relaxing as is done on other
555 platforms. However, we do have to handle GP relative addressing
556 correctly, which turns out to be a similar problem.
558 Every macro that refers to a symbol can occur in (at least) two
559 forms, one with GP relative addressing and one without. For
560 example, loading a global variable into a register generally uses
561 a macro instruction like this:
563 If i can be addressed off the GP register (this is true if it is in
564 the .sbss or .sdata section, or if it is known to be smaller than
565 the -G argument) this will generate the following instruction:
567 This instruction will use a GPREL reloc. If i can not be addressed
568 off the GP register, the following instruction sequence will be used:
571 In this case the first instruction will have a HI16 reloc, and the
572 second reloc will have a LO16 reloc. Both relocs will be against
575 The issue here is that we may not know whether i is GP addressable
576 until after we see the instruction that uses it. Therefore, we
577 want to be able to choose the final instruction sequence only at
578 the end of the assembly. This is similar to the way other
579 platforms choose the size of a PC relative instruction only at the
582 When generating position independent code we do not use GP
583 addressing in quite the same way, but the issue still arises as
584 external symbols and local symbols must be handled differently.
586 We handle these issues by actually generating both possible
587 instruction sequences. The longer one is put in a frag_var with
588 type rs_machine_dependent. We encode what to do with the frag in
589 the subtype field. We encode (1) the number of existing bytes to
590 replace, (2) the number of new bytes to use, (3) the offset from
591 the start of the existing bytes to the first reloc we must generate
592 (that is, the offset is applied from the start of the existing
593 bytes after they are replaced by the new bytes, if any), (4) the
594 offset from the start of the existing bytes to the second reloc,
595 (5) whether a third reloc is needed (the third reloc is always four
596 bytes after the second reloc), and (6) whether to warn if this
597 variant is used (this is sometimes needed if .set nomacro or .set
598 noat is in effect). All these numbers are reasonably small.
600 Generating two instruction sequences must be handled carefully to
601 ensure that delay slots are handled correctly. Fortunately, there
602 are a limited number of cases. When the second instruction
603 sequence is generated, append_insn is directed to maintain the
604 existing delay slot information, so it continues to apply to any
605 code after the second instruction sequence. This means that the
606 second instruction sequence must not impose any requirements not
607 required by the first instruction sequence.
609 These variant frags are then handled in functions called by the
610 machine independent code. md_estimate_size_before_relax returns
611 the final size of the frag. md_convert_frag sets up the final form
612 of the frag. tc_gen_reloc adjust the first reloc and adds a second
614 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
618 | (((reloc1) + 64) << 9) \
619 | (((reloc2) + 64) << 2) \
620 | ((reloc3) ? (1 << 1) : 0) \
622 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
623 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
624 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
625 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
626 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
627 #define RELAX_WARN(i) ((i) & 1)
629 /* For mips16 code, we use an entirely different form of relaxation.
630 mips16 supports two versions of most instructions which take
631 immediate values: a small one which takes some small value, and a
632 larger one which takes a 16 bit value. Since branches also follow
633 this pattern, relaxing these values is required.
635 We can assemble both mips16 and normal MIPS code in a single
636 object. Therefore, we need to support this type of relaxation at
637 the same time that we support the relaxation described above. We
638 use the high bit of the subtype field to distinguish these cases.
640 The information we store for this type of relaxation is the
641 argument code found in the opcode file for this relocation, whether
642 the user explicitly requested a small or extended form, and whether
643 the relocation is in a jump or jal delay slot. That tells us the
644 size of the value, and how it should be stored. We also store
645 whether the fragment is considered to be extended or not. We also
646 store whether this is known to be a branch to a different section,
647 whether we have tried to relax this frag yet, and whether we have
648 ever extended a PC relative fragment because of a shift count. */
649 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
652 | ((small) ? 0x100 : 0) \
653 | ((ext) ? 0x200 : 0) \
654 | ((dslot) ? 0x400 : 0) \
655 | ((jal_dslot) ? 0x800 : 0))
656 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
657 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
658 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
659 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
660 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
661 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
662 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
663 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
664 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
665 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
666 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
667 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
669 /* Is the given value a sign-extended 32-bit value? */
670 #define IS_SEXT_32BIT_NUM(x) \
671 (((x) &~ (offsetT) 0x7fffffff) == 0 \
672 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
674 /* Is the given value a sign-extended 16-bit value? */
675 #define IS_SEXT_16BIT_NUM(x) \
676 (((x) &~ (offsetT) 0x7fff) == 0 \
677 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
680 /* Prototypes for static functions. */
683 #define internalError() \
684 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
686 #define internalError() as_fatal (_("MIPS internal Error"));
689 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
691 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
692 unsigned int reg, enum mips_regclass class));
693 static int reg_needs_delay PARAMS ((unsigned int));
694 static void mips16_mark_labels PARAMS ((void));
695 static void append_insn PARAMS ((char *place,
696 struct mips_cl_insn * ip,
698 bfd_reloc_code_real_type *r,
700 static void mips_no_prev_insn PARAMS ((int));
701 static void mips_emit_delays PARAMS ((boolean));
703 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
704 const char *name, const char *fmt,
707 static void macro_build ();
709 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
710 const char *, const char *,
712 static void macro_build_jalr PARAMS ((int, expressionS *));
713 static void macro_build_lui PARAMS ((char *place, int *counter,
714 expressionS * ep, int regnum));
715 static void macro_build_ldst_constoffset PARAMS ((char *place, int *counter,
716 expressionS * ep, const char *op,
717 int valreg, int breg));
718 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
719 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
721 static void load_register PARAMS ((int *, int, expressionS *, int));
722 static void load_address PARAMS ((int *, int, expressionS *, int *));
723 static void move_register PARAMS ((int *, int, int));
724 static void macro PARAMS ((struct mips_cl_insn * ip));
725 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
726 #ifdef LOSING_COMPILER
727 static void macro2 PARAMS ((struct mips_cl_insn * ip));
729 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
730 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
731 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
732 boolean, boolean, unsigned long *,
733 boolean *, unsigned short *));
734 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
735 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
736 static int my_getSmallExpression PARAMS ((expressionS *, char *));
737 static void my_getExpression PARAMS ((expressionS *, char *));
739 static int support_64bit_objects PARAMS((void));
741 static void mips_set_option_string PARAMS ((const char **, const char *));
742 static symbolS *get_symbol PARAMS ((void));
743 static void mips_align PARAMS ((int to, int fill, symbolS *label));
744 static void s_align PARAMS ((int));
745 static void s_change_sec PARAMS ((int));
746 static void s_change_section PARAMS ((int));
747 static void s_cons PARAMS ((int));
748 static void s_float_cons PARAMS ((int));
749 static void s_mips_globl PARAMS ((int));
750 static void s_option PARAMS ((int));
751 static void s_mipsset PARAMS ((int));
752 static void s_abicalls PARAMS ((int));
753 static void s_cpload PARAMS ((int));
754 static void s_cpsetup PARAMS ((int));
755 static void s_cplocal PARAMS ((int));
756 static void s_cprestore PARAMS ((int));
757 static void s_cpreturn PARAMS ((int));
758 static void s_gpvalue PARAMS ((int));
759 static void s_gpword PARAMS ((int));
760 static void s_cpadd PARAMS ((int));
761 static void s_insn PARAMS ((int));
762 static void md_obj_begin PARAMS ((void));
763 static void md_obj_end PARAMS ((void));
764 static long get_number PARAMS ((void));
765 static void s_mips_ent PARAMS ((int));
766 static void s_mips_end PARAMS ((int));
767 static void s_mips_frame PARAMS ((int));
768 static void s_mips_mask PARAMS ((int));
769 static void s_mips_stab PARAMS ((int));
770 static void s_mips_weakext PARAMS ((int));
771 static void s_mips_file PARAMS ((int));
772 static void s_mips_loc PARAMS ((int));
773 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
774 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
775 static void show PARAMS ((FILE *, const char *, int *, int *));
777 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
780 /* Return values of my_getSmallExpression(). */
787 /* Direct relocation creation by %percent_op(). */
806 /* Table and functions used to map between CPU/ISA names, and
807 ISA levels, and CPU numbers. */
811 const char *name; /* CPU or ISA name. */
812 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
813 int isa; /* ISA level. */
814 int cpu; /* CPU number (default CPU if ISA). */
817 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
818 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
819 static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *,
821 static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *));
822 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
824 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
828 The following pseudo-ops from the Kane and Heinrich MIPS book
829 should be defined here, but are currently unsupported: .alias,
830 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
832 The following pseudo-ops from the Kane and Heinrich MIPS book are
833 specific to the type of debugging information being generated, and
834 should be defined by the object format: .aent, .begin, .bend,
835 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
838 The following pseudo-ops from the Kane and Heinrich MIPS book are
839 not MIPS CPU specific, but are also not specific to the object file
840 format. This file is probably the best place to define them, but
841 they are not currently supported: .asm0, .endr, .lab, .repeat,
844 static const pseudo_typeS mips_pseudo_table[] =
846 /* MIPS specific pseudo-ops. */
847 {"option", s_option, 0},
848 {"set", s_mipsset, 0},
849 {"rdata", s_change_sec, 'r'},
850 {"sdata", s_change_sec, 's'},
851 {"livereg", s_ignore, 0},
852 {"abicalls", s_abicalls, 0},
853 {"cpload", s_cpload, 0},
854 {"cpsetup", s_cpsetup, 0},
855 {"cplocal", s_cplocal, 0},
856 {"cprestore", s_cprestore, 0},
857 {"cpreturn", s_cpreturn, 0},
858 {"gpvalue", s_gpvalue, 0},
859 {"gpword", s_gpword, 0},
860 {"cpadd", s_cpadd, 0},
863 /* Relatively generic pseudo-ops that happen to be used on MIPS
865 {"asciiz", stringer, 1},
866 {"bss", s_change_sec, 'b'},
869 {"dword", s_cons, 3},
870 {"weakext", s_mips_weakext, 0},
872 /* These pseudo-ops are defined in read.c, but must be overridden
873 here for one reason or another. */
874 {"align", s_align, 0},
876 {"data", s_change_sec, 'd'},
877 {"double", s_float_cons, 'd'},
878 {"float", s_float_cons, 'f'},
879 {"globl", s_mips_globl, 0},
880 {"global", s_mips_globl, 0},
881 {"hword", s_cons, 1},
886 {"section", s_change_section, 0},
887 {"short", s_cons, 1},
888 {"single", s_float_cons, 'f'},
889 {"stabn", s_mips_stab, 'n'},
890 {"text", s_change_sec, 't'},
893 { "extern", ecoff_directive_extern, 0},
898 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
900 /* These pseudo-ops should be defined by the object file format.
901 However, a.out doesn't support them, so we have versions here. */
902 {"aent", s_mips_ent, 1},
903 {"bgnb", s_ignore, 0},
904 {"end", s_mips_end, 0},
905 {"endb", s_ignore, 0},
906 {"ent", s_mips_ent, 0},
907 {"file", s_mips_file, 0},
908 {"fmask", s_mips_mask, 'F'},
909 {"frame", s_mips_frame, 0},
910 {"loc", s_mips_loc, 0},
911 {"mask", s_mips_mask, 'R'},
912 {"verstamp", s_ignore, 0},
916 extern void pop_insert PARAMS ((const pseudo_typeS *));
921 pop_insert (mips_pseudo_table);
922 if (! ECOFF_DEBUGGING)
923 pop_insert (mips_nonecoff_pseudo_table);
926 /* Symbols labelling the current insn. */
928 struct insn_label_list
930 struct insn_label_list *next;
934 static struct insn_label_list *insn_labels;
935 static struct insn_label_list *free_insn_labels;
937 static void mips_clear_insn_labels PARAMS ((void));
940 mips_clear_insn_labels ()
942 register struct insn_label_list **pl;
944 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
950 static char *expr_end;
952 /* Expressions which appear in instructions. These are set by
955 static expressionS imm_expr;
956 static expressionS offset_expr;
958 /* Relocs associated with imm_expr and offset_expr. */
960 static bfd_reloc_code_real_type imm_reloc[3]
961 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
962 static bfd_reloc_code_real_type offset_reloc[3]
963 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
965 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
967 static boolean imm_unmatched_hi;
969 /* These are set by mips16_ip if an explicit extension is used. */
971 static boolean mips16_small, mips16_ext;
974 /* The pdr segment for per procedure frame/regmask info. Not used for
980 /* The default target format to use. */
983 mips_target_format ()
985 switch (OUTPUT_FLAVOR)
987 case bfd_target_aout_flavour:
988 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
989 case bfd_target_ecoff_flavour:
990 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
991 case bfd_target_coff_flavour:
993 case bfd_target_elf_flavour:
995 /* This is traditional mips. */
996 return (target_big_endian
997 ? (HAVE_64BIT_OBJECTS
998 ? "elf64-tradbigmips"
1000 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1001 : (HAVE_64BIT_OBJECTS
1002 ? "elf64-tradlittlemips"
1004 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1006 return (target_big_endian
1007 ? (HAVE_64BIT_OBJECTS
1010 ? "elf32-nbigmips" : "elf32-bigmips"))
1011 : (HAVE_64BIT_OBJECTS
1012 ? "elf64-littlemips"
1014 ? "elf32-nlittlemips" : "elf32-littlemips")));
1022 /* This function is called once, at assembler startup time. It should
1023 set up all the tables, etc. that the MD part of the assembler will need. */
1028 register const char *retval = NULL;
1032 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1033 as_warn (_("Could not set architecture and machine"));
1035 op_hash = hash_new ();
1037 for (i = 0; i < NUMOPCODES;)
1039 const char *name = mips_opcodes[i].name;
1041 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1044 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1045 mips_opcodes[i].name, retval);
1046 /* Probably a memory allocation problem? Give up now. */
1047 as_fatal (_("Broken assembler. No assembly attempted."));
1051 if (mips_opcodes[i].pinfo != INSN_MACRO)
1053 if (!validate_mips_insn (&mips_opcodes[i]))
1058 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1061 mips16_op_hash = hash_new ();
1064 while (i < bfd_mips16_num_opcodes)
1066 const char *name = mips16_opcodes[i].name;
1068 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1070 as_fatal (_("internal: can't hash `%s': %s"),
1071 mips16_opcodes[i].name, retval);
1074 if (mips16_opcodes[i].pinfo != INSN_MACRO
1075 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1076 != mips16_opcodes[i].match))
1078 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1079 mips16_opcodes[i].name, mips16_opcodes[i].args);
1084 while (i < bfd_mips16_num_opcodes
1085 && strcmp (mips16_opcodes[i].name, name) == 0);
1089 as_fatal (_("Broken assembler. No assembly attempted."));
1091 /* We add all the general register names to the symbol table. This
1092 helps us detect invalid uses of them. */
1093 for (i = 0; i < 32; i++)
1097 sprintf (buf, "$%d", i);
1098 symbol_table_insert (symbol_new (buf, reg_section, i,
1099 &zero_address_frag));
1101 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1102 &zero_address_frag));
1103 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1104 &zero_address_frag));
1105 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1106 &zero_address_frag));
1107 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1108 &zero_address_frag));
1109 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1110 &zero_address_frag));
1111 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1112 &zero_address_frag));
1113 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1114 &zero_address_frag));
1115 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1116 &zero_address_frag));
1117 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1118 &zero_address_frag));
1120 mips_no_prev_insn (false);
1123 mips_cprmask[0] = 0;
1124 mips_cprmask[1] = 0;
1125 mips_cprmask[2] = 0;
1126 mips_cprmask[3] = 0;
1128 /* set the default alignment for the text section (2**2) */
1129 record_alignment (text_section, 2);
1131 if (USE_GLOBAL_POINTER_OPT)
1132 bfd_set_gp_size (stdoutput, g_switch_value);
1134 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1136 /* On a native system, sections must be aligned to 16 byte
1137 boundaries. When configured for an embedded ELF target, we
1139 if (strcmp (TARGET_OS, "elf") != 0)
1141 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1142 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1143 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1146 /* Create a .reginfo section for register masks and a .mdebug
1147 section for debugging information. */
1155 subseg = now_subseg;
1157 /* The ABI says this section should be loaded so that the
1158 running program can access it. However, we don't load it
1159 if we are configured for an embedded target */
1160 flags = SEC_READONLY | SEC_DATA;
1161 if (strcmp (TARGET_OS, "elf") != 0)
1162 flags |= SEC_ALLOC | SEC_LOAD;
1164 if (mips_abi != N64_ABI)
1166 sec = subseg_new (".reginfo", (subsegT) 0);
1168 bfd_set_section_flags (stdoutput, sec, flags);
1169 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1172 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1177 /* The 64-bit ABI uses a .MIPS.options section rather than
1178 .reginfo section. */
1179 sec = subseg_new (".MIPS.options", (subsegT) 0);
1180 bfd_set_section_flags (stdoutput, sec, flags);
1181 bfd_set_section_alignment (stdoutput, sec, 3);
1184 /* Set up the option header. */
1186 Elf_Internal_Options opthdr;
1189 opthdr.kind = ODK_REGINFO;
1190 opthdr.size = (sizeof (Elf_External_Options)
1191 + sizeof (Elf64_External_RegInfo));
1194 f = frag_more (sizeof (Elf_External_Options));
1195 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1196 (Elf_External_Options *) f);
1198 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1203 if (ECOFF_DEBUGGING)
1205 sec = subseg_new (".mdebug", (subsegT) 0);
1206 (void) bfd_set_section_flags (stdoutput, sec,
1207 SEC_HAS_CONTENTS | SEC_READONLY);
1208 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1211 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1213 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1214 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1215 SEC_READONLY | SEC_RELOC
1217 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1221 subseg_set (seg, subseg);
1225 if (! ECOFF_DEBUGGING)
1232 if (! ECOFF_DEBUGGING)
1240 struct mips_cl_insn insn;
1241 bfd_reloc_code_real_type unused_reloc[3]
1242 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1244 imm_expr.X_op = O_absent;
1245 imm_unmatched_hi = false;
1246 offset_expr.X_op = O_absent;
1247 imm_reloc[0] = BFD_RELOC_UNUSED;
1248 imm_reloc[1] = BFD_RELOC_UNUSED;
1249 imm_reloc[2] = BFD_RELOC_UNUSED;
1250 offset_reloc[0] = BFD_RELOC_UNUSED;
1251 offset_reloc[1] = BFD_RELOC_UNUSED;
1252 offset_reloc[2] = BFD_RELOC_UNUSED;
1254 if (mips_opts.mips16)
1255 mips16_ip (str, &insn);
1258 mips_ip (str, &insn);
1259 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1260 str, insn.insn_opcode));
1265 as_bad ("%s `%s'", insn_error, str);
1269 if (insn.insn_mo->pinfo == INSN_MACRO)
1271 if (mips_opts.mips16)
1272 mips16_macro (&insn);
1278 if (imm_expr.X_op != O_absent)
1279 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1280 else if (offset_expr.X_op != O_absent)
1281 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1283 append_insn (NULL, &insn, NULL, unused_reloc, false);
1287 /* See whether instruction IP reads register REG. CLASS is the type
1291 insn_uses_reg (ip, reg, class)
1292 struct mips_cl_insn *ip;
1294 enum mips_regclass class;
1296 if (class == MIPS16_REG)
1298 assert (mips_opts.mips16);
1299 reg = mips16_to_32_reg_map[reg];
1300 class = MIPS_GR_REG;
1303 /* Don't report on general register ZERO, since it never changes. */
1304 if (class == MIPS_GR_REG && reg == ZERO)
1307 if (class == MIPS_FP_REG)
1309 assert (! mips_opts.mips16);
1310 /* If we are called with either $f0 or $f1, we must check $f0.
1311 This is not optimal, because it will introduce an unnecessary
1312 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1313 need to distinguish reading both $f0 and $f1 or just one of
1314 them. Note that we don't have to check the other way,
1315 because there is no instruction that sets both $f0 and $f1
1316 and requires a delay. */
1317 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1318 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1319 == (reg &~ (unsigned) 1)))
1321 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1322 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1323 == (reg &~ (unsigned) 1)))
1326 else if (! mips_opts.mips16)
1328 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1329 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1331 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1332 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1337 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1338 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1339 & MIPS16OP_MASK_RX)]
1342 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1343 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1344 & MIPS16OP_MASK_RY)]
1347 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1348 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1349 & MIPS16OP_MASK_MOVE32Z)]
1352 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1354 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1356 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1358 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1359 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1360 & MIPS16OP_MASK_REGR32) == reg)
1367 /* This function returns true if modifying a register requires a
1371 reg_needs_delay (reg)
1374 unsigned long prev_pinfo;
1376 prev_pinfo = prev_insn.insn_mo->pinfo;
1377 if (! mips_opts.noreorder
1378 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1379 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1380 || (! gpr_interlocks
1381 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1383 /* A load from a coprocessor or from memory. All load
1384 delays delay the use of general register rt for one
1385 instruction on the r3000. The r6000 and r4000 use
1387 /* Itbl support may require additional care here. */
1388 know (prev_pinfo & INSN_WRITE_GPR_T);
1389 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1396 /* Mark instruction labels in mips16 mode. This permits the linker to
1397 handle them specially, such as generating jalx instructions when
1398 needed. We also make them odd for the duration of the assembly, in
1399 order to generate the right sort of code. We will make them even
1400 in the adjust_symtab routine, while leaving them marked. This is
1401 convenient for the debugger and the disassembler. The linker knows
1402 to make them odd again. */
1405 mips16_mark_labels ()
1407 if (mips_opts.mips16)
1409 struct insn_label_list *l;
1412 for (l = insn_labels; l != NULL; l = l->next)
1415 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1416 S_SET_OTHER (l->label, STO_MIPS16);
1418 val = S_GET_VALUE (l->label);
1420 S_SET_VALUE (l->label, val + 1);
1425 /* Output an instruction. PLACE is where to put the instruction; if
1426 it is NULL, this uses frag_more to get room. IP is the instruction
1427 information. ADDRESS_EXPR is an operand of the instruction to be
1428 used with RELOC_TYPE. */
1431 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1433 struct mips_cl_insn *ip;
1434 expressionS *address_expr;
1435 bfd_reloc_code_real_type *reloc_type;
1436 boolean unmatched_hi;
1438 register unsigned long prev_pinfo, pinfo;
1443 /* Mark instruction labels in mips16 mode. */
1444 mips16_mark_labels ();
1446 prev_pinfo = prev_insn.insn_mo->pinfo;
1447 pinfo = ip->insn_mo->pinfo;
1449 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1453 /* If the previous insn required any delay slots, see if we need
1454 to insert a NOP or two. There are eight kinds of possible
1455 hazards, of which an instruction can have at most one type.
1456 (1) a load from memory delay
1457 (2) a load from a coprocessor delay
1458 (3) an unconditional branch delay
1459 (4) a conditional branch delay
1460 (5) a move to coprocessor register delay
1461 (6) a load coprocessor register from memory delay
1462 (7) a coprocessor condition code delay
1463 (8) a HI/LO special register delay
1465 There are a lot of optimizations we could do that we don't.
1466 In particular, we do not, in general, reorder instructions.
1467 If you use gcc with optimization, it will reorder
1468 instructions and generally do much more optimization then we
1469 do here; repeating all that work in the assembler would only
1470 benefit hand written assembly code, and does not seem worth
1473 /* This is how a NOP is emitted. */
1474 #define emit_nop() \
1476 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1477 : md_number_to_chars (frag_more (4), 0, 4))
1479 /* The previous insn might require a delay slot, depending upon
1480 the contents of the current insn. */
1481 if (! mips_opts.mips16
1482 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1483 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1484 && ! cop_interlocks)
1485 || (! gpr_interlocks
1486 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1488 /* A load from a coprocessor or from memory. All load
1489 delays delay the use of general register rt for one
1490 instruction on the r3000. The r6000 and r4000 use
1492 /* Itbl support may require additional care here. */
1493 know (prev_pinfo & INSN_WRITE_GPR_T);
1494 if (mips_optimize == 0
1495 || insn_uses_reg (ip,
1496 ((prev_insn.insn_opcode >> OP_SH_RT)
1501 else if (! mips_opts.mips16
1502 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1503 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1504 && ! cop_interlocks)
1505 || (mips_opts.isa == ISA_MIPS1
1506 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1508 /* A generic coprocessor delay. The previous instruction
1509 modified a coprocessor general or control register. If
1510 it modified a control register, we need to avoid any
1511 coprocessor instruction (this is probably not always
1512 required, but it sometimes is). If it modified a general
1513 register, we avoid using that register.
1515 On the r6000 and r4000 loading a coprocessor register
1516 from memory is interlocked, and does not require a delay.
1518 This case is not handled very well. There is no special
1519 knowledge of CP0 handling, and the coprocessors other
1520 than the floating point unit are not distinguished at
1522 /* Itbl support may require additional care here. FIXME!
1523 Need to modify this to include knowledge about
1524 user specified delays! */
1525 if (prev_pinfo & INSN_WRITE_FPR_T)
1527 if (mips_optimize == 0
1528 || insn_uses_reg (ip,
1529 ((prev_insn.insn_opcode >> OP_SH_FT)
1534 else if (prev_pinfo & INSN_WRITE_FPR_S)
1536 if (mips_optimize == 0
1537 || insn_uses_reg (ip,
1538 ((prev_insn.insn_opcode >> OP_SH_FS)
1545 /* We don't know exactly what the previous instruction
1546 does. If the current instruction uses a coprocessor
1547 register, we must insert a NOP. If previous
1548 instruction may set the condition codes, and the
1549 current instruction uses them, we must insert two
1551 /* Itbl support may require additional care here. */
1552 if (mips_optimize == 0
1553 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1554 && (pinfo & INSN_READ_COND_CODE)))
1556 else if (pinfo & INSN_COP)
1560 else if (! mips_opts.mips16
1561 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1562 && (prev_pinfo & INSN_WRITE_COND_CODE)
1563 && ! cop_interlocks)
1565 /* The previous instruction sets the coprocessor condition
1566 codes, but does not require a general coprocessor delay
1567 (this means it is a floating point comparison
1568 instruction). If this instruction uses the condition
1569 codes, we need to insert a single NOP. */
1570 /* Itbl support may require additional care here. */
1571 if (mips_optimize == 0
1572 || (pinfo & INSN_READ_COND_CODE))
1576 /* If we're fixing up mfhi/mflo for the r7000 and the
1577 previous insn was an mfhi/mflo and the current insn
1578 reads the register that the mfhi/mflo wrote to, then
1581 else if (mips_7000_hilo_fix
1582 && MF_HILO_INSN (prev_pinfo)
1583 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1590 /* If we're fixing up mfhi/mflo for the r7000 and the
1591 2nd previous insn was an mfhi/mflo and the current insn
1592 reads the register that the mfhi/mflo wrote to, then
1595 else if (mips_7000_hilo_fix
1596 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1597 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1605 else if (prev_pinfo & INSN_READ_LO)
1607 /* The previous instruction reads the LO register; if the
1608 current instruction writes to the LO register, we must
1609 insert two NOPS. Some newer processors have interlocks.
1610 Also the tx39's multiply instructions can be exectuted
1611 immediatly after a read from HI/LO (without the delay),
1612 though the tx39's divide insns still do require the
1614 if (! (hilo_interlocks
1615 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1616 && (mips_optimize == 0
1617 || (pinfo & INSN_WRITE_LO)))
1619 /* Most mips16 branch insns don't have a delay slot.
1620 If a read from LO is immediately followed by a branch
1621 to a write to LO we have a read followed by a write
1622 less than 2 insns away. We assume the target of
1623 a branch might be a write to LO, and insert a nop
1624 between a read and an immediately following branch. */
1625 else if (mips_opts.mips16
1626 && (mips_optimize == 0
1627 || (pinfo & MIPS16_INSN_BRANCH)))
1630 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1632 /* The previous instruction reads the HI register; if the
1633 current instruction writes to the HI register, we must
1634 insert a NOP. Some newer processors have interlocks.
1635 Also the note tx39's multiply above. */
1636 if (! (hilo_interlocks
1637 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1638 && (mips_optimize == 0
1639 || (pinfo & INSN_WRITE_HI)))
1641 /* Most mips16 branch insns don't have a delay slot.
1642 If a read from HI is immediately followed by a branch
1643 to a write to HI we have a read followed by a write
1644 less than 2 insns away. We assume the target of
1645 a branch might be a write to HI, and insert a nop
1646 between a read and an immediately following branch. */
1647 else if (mips_opts.mips16
1648 && (mips_optimize == 0
1649 || (pinfo & MIPS16_INSN_BRANCH)))
1653 /* If the previous instruction was in a noreorder section, then
1654 we don't want to insert the nop after all. */
1655 /* Itbl support may require additional care here. */
1656 if (prev_insn_unreordered)
1659 /* There are two cases which require two intervening
1660 instructions: 1) setting the condition codes using a move to
1661 coprocessor instruction which requires a general coprocessor
1662 delay and then reading the condition codes 2) reading the HI
1663 or LO register and then writing to it (except on processors
1664 which have interlocks). If we are not already emitting a NOP
1665 instruction, we must check for these cases compared to the
1666 instruction previous to the previous instruction. */
1667 if ((! mips_opts.mips16
1668 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1669 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1670 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1671 && (pinfo & INSN_READ_COND_CODE)
1672 && ! cop_interlocks)
1673 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1674 && (pinfo & INSN_WRITE_LO)
1675 && ! (hilo_interlocks
1676 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1677 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1678 && (pinfo & INSN_WRITE_HI)
1679 && ! (hilo_interlocks
1680 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1685 if (prev_prev_insn_unreordered)
1688 if (prev_prev_nop && nops == 0)
1691 /* If we are being given a nop instruction, don't bother with
1692 one of the nops we would otherwise output. This will only
1693 happen when a nop instruction is used with mips_optimize set
1696 && ! mips_opts.noreorder
1697 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1700 /* Now emit the right number of NOP instructions. */
1701 if (nops > 0 && ! mips_opts.noreorder)
1704 unsigned long old_frag_offset;
1706 struct insn_label_list *l;
1708 old_frag = frag_now;
1709 old_frag_offset = frag_now_fix ();
1711 for (i = 0; i < nops; i++)
1716 listing_prev_line ();
1717 /* We may be at the start of a variant frag. In case we
1718 are, make sure there is enough space for the frag
1719 after the frags created by listing_prev_line. The
1720 argument to frag_grow here must be at least as large
1721 as the argument to all other calls to frag_grow in
1722 this file. We don't have to worry about being in the
1723 middle of a variant frag, because the variants insert
1724 all needed nop instructions themselves. */
1728 for (l = insn_labels; l != NULL; l = l->next)
1732 assert (S_GET_SEGMENT (l->label) == now_seg);
1733 symbol_set_frag (l->label, frag_now);
1734 val = (valueT) frag_now_fix ();
1735 /* mips16 text labels are stored as odd. */
1736 if (mips_opts.mips16)
1738 S_SET_VALUE (l->label, val);
1741 #ifndef NO_ECOFF_DEBUGGING
1742 if (ECOFF_DEBUGGING)
1743 ecoff_fix_loc (old_frag, old_frag_offset);
1746 else if (prev_nop_frag != NULL)
1748 /* We have a frag holding nops we may be able to remove. If
1749 we don't need any nops, we can decrease the size of
1750 prev_nop_frag by the size of one instruction. If we do
1751 need some nops, we count them in prev_nops_required. */
1752 if (prev_nop_frag_since == 0)
1756 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1757 --prev_nop_frag_holds;
1760 prev_nop_frag_required += nops;
1764 if (prev_prev_nop == 0)
1766 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1767 --prev_nop_frag_holds;
1770 ++prev_nop_frag_required;
1773 if (prev_nop_frag_holds <= prev_nop_frag_required)
1774 prev_nop_frag = NULL;
1776 ++prev_nop_frag_since;
1778 /* Sanity check: by the time we reach the second instruction
1779 after prev_nop_frag, we should have used up all the nops
1780 one way or another. */
1781 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1785 if (*reloc_type > BFD_RELOC_UNUSED)
1787 /* We need to set up a variant frag. */
1788 assert (mips_opts.mips16 && address_expr != NULL);
1789 f = frag_var (rs_machine_dependent, 4, 0,
1790 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1791 mips16_small, mips16_ext,
1793 & INSN_UNCOND_BRANCH_DELAY),
1794 (*prev_insn_reloc_type
1795 == BFD_RELOC_MIPS16_JMP)),
1796 make_expr_symbol (address_expr), 0, NULL);
1798 else if (place != NULL)
1800 else if (mips_opts.mips16
1802 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1804 /* Make sure there is enough room to swap this instruction with
1805 a following jump instruction. */
1811 if (mips_opts.mips16
1812 && mips_opts.noreorder
1813 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1814 as_warn (_("extended instruction in delay slot"));
1819 fixp[0] = fixp[1] = fixp[2] = NULL;
1820 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1822 if (address_expr->X_op == O_constant)
1826 switch (*reloc_type)
1829 ip->insn_opcode |= address_expr->X_add_number;
1832 case BFD_RELOC_MIPS_HIGHEST:
1833 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1835 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1838 case BFD_RELOC_MIPS_HIGHER:
1839 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1840 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1843 case BFD_RELOC_HI16_S:
1844 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1848 case BFD_RELOC_HI16:
1849 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1852 case BFD_RELOC_LO16:
1853 case BFD_RELOC_MIPS_GOT_DISP:
1854 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1857 case BFD_RELOC_MIPS_JMP:
1858 if ((address_expr->X_add_number & 3) != 0)
1859 as_bad (_("jump to misaligned address (0x%lx)"),
1860 (unsigned long) address_expr->X_add_number);
1861 if (address_expr->X_add_number & ~0xfffffff)
1862 as_bad (_("jump address range overflow (0x%lx)"),
1863 (unsigned long) address_expr->X_add_number);
1864 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1867 case BFD_RELOC_MIPS16_JMP:
1868 if ((address_expr->X_add_number & 3) != 0)
1869 as_bad (_("jump to misaligned address (0x%lx)"),
1870 (unsigned long) address_expr->X_add_number);
1871 if (address_expr->X_add_number & ~0xfffffff)
1872 as_bad (_("jump address range overflow (0x%lx)"),
1873 (unsigned long) address_expr->X_add_number);
1875 (((address_expr->X_add_number & 0x7c0000) << 3)
1876 | ((address_expr->X_add_number & 0xf800000) >> 7)
1877 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1880 case BFD_RELOC_16_PCREL:
1881 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1884 case BFD_RELOC_16_PCREL_S2:
1894 /* Don't generate a reloc if we are writing into a variant frag. */
1897 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1899 (*reloc_type == BFD_RELOC_16_PCREL
1900 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1903 /* These relocations can have an addend that won't fit in
1904 4 octets for 64bit assembly. */
1905 if (HAVE_64BIT_GPRS &&
1906 (*reloc_type == BFD_RELOC_16
1907 || *reloc_type == BFD_RELOC_32
1908 || *reloc_type == BFD_RELOC_MIPS_JMP
1909 || *reloc_type == BFD_RELOC_HI16_S
1910 || *reloc_type == BFD_RELOC_LO16
1911 || *reloc_type == BFD_RELOC_GPREL16
1912 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1913 || *reloc_type == BFD_RELOC_GPREL32
1914 || *reloc_type == BFD_RELOC_64
1915 || *reloc_type == BFD_RELOC_CTOR
1916 || *reloc_type == BFD_RELOC_MIPS_SUB
1917 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1918 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1919 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1920 || *reloc_type == BFD_RELOC_MIPS_REL16
1921 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1922 fixp[0]->fx_no_overflow = 1;
1926 struct mips_hi_fixup *hi_fixup;
1928 assert (*reloc_type == BFD_RELOC_HI16_S);
1929 hi_fixup = ((struct mips_hi_fixup *)
1930 xmalloc (sizeof (struct mips_hi_fixup)));
1931 hi_fixup->fixp = fixp[0];
1932 hi_fixup->seg = now_seg;
1933 hi_fixup->next = mips_hi_fixup_list;
1934 mips_hi_fixup_list = hi_fixup;
1937 if (reloc_type[1] != BFD_RELOC_UNUSED)
1939 /* FIXME: This symbol can be one of
1940 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1941 address_expr->X_op = O_absent;
1942 address_expr->X_add_symbol = 0;
1943 address_expr->X_add_number = 0;
1945 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1946 4, address_expr, false,
1949 /* These relocations can have an addend that won't fit in
1950 4 octets for 64bit assembly. */
1951 if (HAVE_64BIT_GPRS &&
1952 (*reloc_type == BFD_RELOC_16
1953 || *reloc_type == BFD_RELOC_32
1954 || *reloc_type == BFD_RELOC_MIPS_JMP
1955 || *reloc_type == BFD_RELOC_HI16_S
1956 || *reloc_type == BFD_RELOC_LO16
1957 || *reloc_type == BFD_RELOC_GPREL16
1958 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1959 || *reloc_type == BFD_RELOC_GPREL32
1960 || *reloc_type == BFD_RELOC_64
1961 || *reloc_type == BFD_RELOC_CTOR
1962 || *reloc_type == BFD_RELOC_MIPS_SUB
1963 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1964 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1965 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1966 || *reloc_type == BFD_RELOC_MIPS_REL16
1967 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1968 fixp[1]->fx_no_overflow = 1;
1970 if (reloc_type[2] != BFD_RELOC_UNUSED)
1972 address_expr->X_op = O_absent;
1973 address_expr->X_add_symbol = 0;
1974 address_expr->X_add_number = 0;
1976 fixp[2] = fix_new_exp (frag_now,
1977 f - frag_now->fr_literal, 4,
1978 address_expr, false,
1981 /* These relocations can have an addend that won't fit in
1982 4 octets for 64bit assembly. */
1983 if (HAVE_64BIT_GPRS &&
1984 (*reloc_type == BFD_RELOC_16
1985 || *reloc_type == BFD_RELOC_32
1986 || *reloc_type == BFD_RELOC_MIPS_JMP
1987 || *reloc_type == BFD_RELOC_HI16_S
1988 || *reloc_type == BFD_RELOC_LO16
1989 || *reloc_type == BFD_RELOC_GPREL16
1990 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1991 || *reloc_type == BFD_RELOC_GPREL32
1992 || *reloc_type == BFD_RELOC_64
1993 || *reloc_type == BFD_RELOC_CTOR
1994 || *reloc_type == BFD_RELOC_MIPS_SUB
1995 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1996 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1997 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1998 || *reloc_type == BFD_RELOC_MIPS_REL16
1999 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2000 fixp[2]->fx_no_overflow = 1;
2007 if (! mips_opts.mips16)
2009 md_number_to_chars (f, ip->insn_opcode, 4);
2011 dwarf2_emit_insn (4);
2014 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2016 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2017 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2019 dwarf2_emit_insn (4);
2026 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2029 md_number_to_chars (f, ip->insn_opcode, 2);
2031 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2035 /* Update the register mask information. */
2036 if (! mips_opts.mips16)
2038 if (pinfo & INSN_WRITE_GPR_D)
2039 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2040 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2041 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2042 if (pinfo & INSN_READ_GPR_S)
2043 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2044 if (pinfo & INSN_WRITE_GPR_31)
2045 mips_gprmask |= 1 << RA;
2046 if (pinfo & INSN_WRITE_FPR_D)
2047 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2048 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2049 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2050 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2051 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2052 if ((pinfo & INSN_READ_FPR_R) != 0)
2053 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2054 if (pinfo & INSN_COP)
2056 /* We don't keep enough information to sort these cases out.
2057 The itbl support does keep this information however, although
2058 we currently don't support itbl fprmats as part of the cop
2059 instruction. May want to add this support in the future. */
2061 /* Never set the bit for $0, which is always zero. */
2062 mips_gprmask &= ~1 << 0;
2066 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2067 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2068 & MIPS16OP_MASK_RX);
2069 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2070 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2071 & MIPS16OP_MASK_RY);
2072 if (pinfo & MIPS16_INSN_WRITE_Z)
2073 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2074 & MIPS16OP_MASK_RZ);
2075 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2076 mips_gprmask |= 1 << TREG;
2077 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2078 mips_gprmask |= 1 << SP;
2079 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2080 mips_gprmask |= 1 << RA;
2081 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2082 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2083 if (pinfo & MIPS16_INSN_READ_Z)
2084 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2085 & MIPS16OP_MASK_MOVE32Z);
2086 if (pinfo & MIPS16_INSN_READ_GPR_X)
2087 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2088 & MIPS16OP_MASK_REGR32);
2091 if (place == NULL && ! mips_opts.noreorder)
2093 /* Filling the branch delay slot is more complex. We try to
2094 switch the branch with the previous instruction, which we can
2095 do if the previous instruction does not set up a condition
2096 that the branch tests and if the branch is not itself the
2097 target of any branch. */
2098 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2099 || (pinfo & INSN_COND_BRANCH_DELAY))
2101 if (mips_optimize < 2
2102 /* If we have seen .set volatile or .set nomove, don't
2104 || mips_opts.nomove != 0
2105 /* If we had to emit any NOP instructions, then we
2106 already know we can not swap. */
2108 /* If we don't even know the previous insn, we can not
2110 || ! prev_insn_valid
2111 /* If the previous insn is already in a branch delay
2112 slot, then we can not swap. */
2113 || prev_insn_is_delay_slot
2114 /* If the previous previous insn was in a .set
2115 noreorder, we can't swap. Actually, the MIPS
2116 assembler will swap in this situation. However, gcc
2117 configured -with-gnu-as will generate code like
2123 in which we can not swap the bne and INSN. If gcc is
2124 not configured -with-gnu-as, it does not output the
2125 .set pseudo-ops. We don't have to check
2126 prev_insn_unreordered, because prev_insn_valid will
2127 be 0 in that case. We don't want to use
2128 prev_prev_insn_valid, because we do want to be able
2129 to swap at the start of a function. */
2130 || prev_prev_insn_unreordered
2131 /* If the branch is itself the target of a branch, we
2132 can not swap. We cheat on this; all we check for is
2133 whether there is a label on this instruction. If
2134 there are any branches to anything other than a
2135 label, users must use .set noreorder. */
2136 || insn_labels != NULL
2137 /* If the previous instruction is in a variant frag, we
2138 can not do the swap. This does not apply to the
2139 mips16, which uses variant frags for different
2141 || (! mips_opts.mips16
2142 && prev_insn_frag->fr_type == rs_machine_dependent)
2143 /* If the branch reads the condition codes, we don't
2144 even try to swap, because in the sequence
2149 we can not swap, and I don't feel like handling that
2151 || (! mips_opts.mips16
2152 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2153 && (pinfo & INSN_READ_COND_CODE))
2154 /* We can not swap with an instruction that requires a
2155 delay slot, becase the target of the branch might
2156 interfere with that instruction. */
2157 || (! mips_opts.mips16
2158 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2160 /* Itbl support may require additional care here. */
2161 & (INSN_LOAD_COPROC_DELAY
2162 | INSN_COPROC_MOVE_DELAY
2163 | INSN_WRITE_COND_CODE)))
2164 || (! (hilo_interlocks
2165 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2169 || (! mips_opts.mips16
2171 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2172 || (! mips_opts.mips16
2173 && mips_opts.isa == ISA_MIPS1
2174 /* Itbl support may require additional care here. */
2175 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2176 /* We can not swap with a branch instruction. */
2178 & (INSN_UNCOND_BRANCH_DELAY
2179 | INSN_COND_BRANCH_DELAY
2180 | INSN_COND_BRANCH_LIKELY))
2181 /* We do not swap with a trap instruction, since it
2182 complicates trap handlers to have the trap
2183 instruction be in a delay slot. */
2184 || (prev_pinfo & INSN_TRAP)
2185 /* If the branch reads a register that the previous
2186 instruction sets, we can not swap. */
2187 || (! mips_opts.mips16
2188 && (prev_pinfo & INSN_WRITE_GPR_T)
2189 && insn_uses_reg (ip,
2190 ((prev_insn.insn_opcode >> OP_SH_RT)
2193 || (! mips_opts.mips16
2194 && (prev_pinfo & INSN_WRITE_GPR_D)
2195 && insn_uses_reg (ip,
2196 ((prev_insn.insn_opcode >> OP_SH_RD)
2199 || (mips_opts.mips16
2200 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2201 && insn_uses_reg (ip,
2202 ((prev_insn.insn_opcode
2204 & MIPS16OP_MASK_RX),
2206 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2207 && insn_uses_reg (ip,
2208 ((prev_insn.insn_opcode
2210 & MIPS16OP_MASK_RY),
2212 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2213 && insn_uses_reg (ip,
2214 ((prev_insn.insn_opcode
2216 & MIPS16OP_MASK_RZ),
2218 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2219 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2220 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2221 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2222 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2223 && insn_uses_reg (ip,
2224 MIPS16OP_EXTRACT_REG32R (prev_insn.
2227 /* If the branch writes a register that the previous
2228 instruction sets, we can not swap (we know that
2229 branches write only to RD or to $31). */
2230 || (! mips_opts.mips16
2231 && (prev_pinfo & INSN_WRITE_GPR_T)
2232 && (((pinfo & INSN_WRITE_GPR_D)
2233 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2234 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2235 || ((pinfo & INSN_WRITE_GPR_31)
2236 && (((prev_insn.insn_opcode >> OP_SH_RT)
2239 || (! mips_opts.mips16
2240 && (prev_pinfo & INSN_WRITE_GPR_D)
2241 && (((pinfo & INSN_WRITE_GPR_D)
2242 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2243 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2244 || ((pinfo & INSN_WRITE_GPR_31)
2245 && (((prev_insn.insn_opcode >> OP_SH_RD)
2248 || (mips_opts.mips16
2249 && (pinfo & MIPS16_INSN_WRITE_31)
2250 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2251 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2252 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2254 /* If the branch writes a register that the previous
2255 instruction reads, we can not swap (we know that
2256 branches only write to RD or to $31). */
2257 || (! mips_opts.mips16
2258 && (pinfo & INSN_WRITE_GPR_D)
2259 && insn_uses_reg (&prev_insn,
2260 ((ip->insn_opcode >> OP_SH_RD)
2263 || (! mips_opts.mips16
2264 && (pinfo & INSN_WRITE_GPR_31)
2265 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2266 || (mips_opts.mips16
2267 && (pinfo & MIPS16_INSN_WRITE_31)
2268 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2269 /* If we are generating embedded PIC code, the branch
2270 might be expanded into a sequence which uses $at, so
2271 we can't swap with an instruction which reads it. */
2272 || (mips_pic == EMBEDDED_PIC
2273 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2274 /* If the previous previous instruction has a load
2275 delay, and sets a register that the branch reads, we
2277 || (! mips_opts.mips16
2278 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2279 /* Itbl support may require additional care here. */
2280 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2281 || (! gpr_interlocks
2282 && (prev_prev_insn.insn_mo->pinfo
2283 & INSN_LOAD_MEMORY_DELAY)))
2284 && insn_uses_reg (ip,
2285 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2288 /* If one instruction sets a condition code and the
2289 other one uses a condition code, we can not swap. */
2290 || ((pinfo & INSN_READ_COND_CODE)
2291 && (prev_pinfo & INSN_WRITE_COND_CODE))
2292 || ((pinfo & INSN_WRITE_COND_CODE)
2293 && (prev_pinfo & INSN_READ_COND_CODE))
2294 /* If the previous instruction uses the PC, we can not
2296 || (mips_opts.mips16
2297 && (prev_pinfo & MIPS16_INSN_READ_PC))
2298 /* If the previous instruction was extended, we can not
2300 || (mips_opts.mips16 && prev_insn_extended)
2301 /* If the previous instruction had a fixup in mips16
2302 mode, we can not swap. This normally means that the
2303 previous instruction was a 4 byte branch anyhow. */
2304 || (mips_opts.mips16 && prev_insn_fixp[0])
2305 /* If the previous instruction is a sync, sync.l, or
2306 sync.p, we can not swap. */
2307 || (prev_pinfo & INSN_SYNC))
2309 /* We could do even better for unconditional branches to
2310 portions of this object file; we could pick up the
2311 instruction at the destination, put it in the delay
2312 slot, and bump the destination address. */
2314 /* Update the previous insn information. */
2315 prev_prev_insn = *ip;
2316 prev_insn.insn_mo = &dummy_opcode;
2320 /* It looks like we can actually do the swap. */
2321 if (! mips_opts.mips16)
2326 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2327 memcpy (temp, prev_f, 4);
2328 memcpy (prev_f, f, 4);
2329 memcpy (f, temp, 4);
2330 if (prev_insn_fixp[0])
2332 prev_insn_fixp[0]->fx_frag = frag_now;
2333 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2335 if (prev_insn_fixp[1])
2337 prev_insn_fixp[1]->fx_frag = frag_now;
2338 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2340 if (prev_insn_fixp[2])
2342 prev_insn_fixp[2]->fx_frag = frag_now;
2343 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2347 fixp[0]->fx_frag = prev_insn_frag;
2348 fixp[0]->fx_where = prev_insn_where;
2352 fixp[1]->fx_frag = prev_insn_frag;
2353 fixp[1]->fx_where = prev_insn_where;
2357 fixp[2]->fx_frag = prev_insn_frag;
2358 fixp[2]->fx_where = prev_insn_where;
2366 assert (prev_insn_fixp[0] == NULL);
2367 assert (prev_insn_fixp[1] == NULL);
2368 assert (prev_insn_fixp[2] == NULL);
2369 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2370 memcpy (temp, prev_f, 2);
2371 memcpy (prev_f, f, 2);
2372 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2374 assert (*reloc_type == BFD_RELOC_UNUSED);
2375 memcpy (f, temp, 2);
2379 memcpy (f, f + 2, 2);
2380 memcpy (f + 2, temp, 2);
2384 fixp[0]->fx_frag = prev_insn_frag;
2385 fixp[0]->fx_where = prev_insn_where;
2389 fixp[1]->fx_frag = prev_insn_frag;
2390 fixp[1]->fx_where = prev_insn_where;
2394 fixp[2]->fx_frag = prev_insn_frag;
2395 fixp[2]->fx_where = prev_insn_where;
2399 /* Update the previous insn information; leave prev_insn
2401 prev_prev_insn = *ip;
2403 prev_insn_is_delay_slot = 1;
2405 /* If that was an unconditional branch, forget the previous
2406 insn information. */
2407 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2409 prev_prev_insn.insn_mo = &dummy_opcode;
2410 prev_insn.insn_mo = &dummy_opcode;
2413 prev_insn_fixp[0] = NULL;
2414 prev_insn_fixp[1] = NULL;
2415 prev_insn_fixp[2] = NULL;
2416 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2417 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2418 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2419 prev_insn_extended = 0;
2421 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2423 /* We don't yet optimize a branch likely. What we should do
2424 is look at the target, copy the instruction found there
2425 into the delay slot, and increment the branch to jump to
2426 the next instruction. */
2428 /* Update the previous insn information. */
2429 prev_prev_insn = *ip;
2430 prev_insn.insn_mo = &dummy_opcode;
2431 prev_insn_fixp[0] = NULL;
2432 prev_insn_fixp[1] = NULL;
2433 prev_insn_fixp[2] = NULL;
2434 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2435 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2436 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2437 prev_insn_extended = 0;
2441 /* Update the previous insn information. */
2443 prev_prev_insn.insn_mo = &dummy_opcode;
2445 prev_prev_insn = prev_insn;
2448 /* Any time we see a branch, we always fill the delay slot
2449 immediately; since this insn is not a branch, we know it
2450 is not in a delay slot. */
2451 prev_insn_is_delay_slot = 0;
2453 prev_insn_fixp[0] = fixp[0];
2454 prev_insn_fixp[1] = fixp[1];
2455 prev_insn_fixp[2] = fixp[2];
2456 prev_insn_reloc_type[0] = reloc_type[0];
2457 prev_insn_reloc_type[1] = reloc_type[1];
2458 prev_insn_reloc_type[2] = reloc_type[2];
2459 if (mips_opts.mips16)
2460 prev_insn_extended = (ip->use_extend
2461 || *reloc_type > BFD_RELOC_UNUSED);
2464 prev_prev_insn_unreordered = prev_insn_unreordered;
2465 prev_insn_unreordered = 0;
2466 prev_insn_frag = frag_now;
2467 prev_insn_where = f - frag_now->fr_literal;
2468 prev_insn_valid = 1;
2470 else if (place == NULL)
2472 /* We need to record a bit of information even when we are not
2473 reordering, in order to determine the base address for mips16
2474 PC relative relocs. */
2475 prev_prev_insn = prev_insn;
2477 prev_insn_reloc_type[0] = reloc_type[0];
2478 prev_insn_reloc_type[1] = reloc_type[1];
2479 prev_insn_reloc_type[2] = reloc_type[2];
2480 prev_prev_insn_unreordered = prev_insn_unreordered;
2481 prev_insn_unreordered = 1;
2484 /* We just output an insn, so the next one doesn't have a label. */
2485 mips_clear_insn_labels ();
2487 /* We must ensure that a fixup associated with an unmatched %hi
2488 reloc does not become a variant frag. Otherwise, the
2489 rearrangement of %hi relocs in frob_file may confuse
2493 frag_wane (frag_now);
2498 /* This function forgets that there was any previous instruction or
2499 label. If PRESERVE is non-zero, it remembers enough information to
2500 know whether nops are needed before a noreorder section. */
2503 mips_no_prev_insn (preserve)
2508 prev_insn.insn_mo = &dummy_opcode;
2509 prev_prev_insn.insn_mo = &dummy_opcode;
2510 prev_nop_frag = NULL;
2511 prev_nop_frag_holds = 0;
2512 prev_nop_frag_required = 0;
2513 prev_nop_frag_since = 0;
2515 prev_insn_valid = 0;
2516 prev_insn_is_delay_slot = 0;
2517 prev_insn_unreordered = 0;
2518 prev_insn_extended = 0;
2519 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2520 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2521 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2522 prev_prev_insn_unreordered = 0;
2523 mips_clear_insn_labels ();
2526 /* This function must be called whenever we turn on noreorder or emit
2527 something other than instructions. It inserts any NOPS which might
2528 be needed by the previous instruction, and clears the information
2529 kept for the previous instructions. The INSNS parameter is true if
2530 instructions are to follow. */
2533 mips_emit_delays (insns)
2536 if (! mips_opts.noreorder)
2541 if ((! mips_opts.mips16
2542 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2543 && (! cop_interlocks
2544 && (prev_insn.insn_mo->pinfo
2545 & (INSN_LOAD_COPROC_DELAY
2546 | INSN_COPROC_MOVE_DELAY
2547 | INSN_WRITE_COND_CODE))))
2548 || (! hilo_interlocks
2549 && (prev_insn.insn_mo->pinfo
2552 || (! mips_opts.mips16
2554 && (prev_insn.insn_mo->pinfo
2555 & INSN_LOAD_MEMORY_DELAY))
2556 || (! mips_opts.mips16
2557 && mips_opts.isa == ISA_MIPS1
2558 && (prev_insn.insn_mo->pinfo
2559 & INSN_COPROC_MEMORY_DELAY)))
2561 /* Itbl support may require additional care here. */
2563 if ((! mips_opts.mips16
2564 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2565 && (! cop_interlocks
2566 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2567 || (! hilo_interlocks
2568 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2569 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2572 if (prev_insn_unreordered)
2575 else if ((! mips_opts.mips16
2576 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2577 && (! cop_interlocks
2578 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2579 || (! hilo_interlocks
2580 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2581 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2583 /* Itbl support may require additional care here. */
2584 if (! prev_prev_insn_unreordered)
2590 struct insn_label_list *l;
2594 /* Record the frag which holds the nop instructions, so
2595 that we can remove them if we don't need them. */
2596 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2597 prev_nop_frag = frag_now;
2598 prev_nop_frag_holds = nops;
2599 prev_nop_frag_required = 0;
2600 prev_nop_frag_since = 0;
2603 for (; nops > 0; --nops)
2608 /* Move on to a new frag, so that it is safe to simply
2609 decrease the size of prev_nop_frag. */
2610 frag_wane (frag_now);
2614 for (l = insn_labels; l != NULL; l = l->next)
2618 assert (S_GET_SEGMENT (l->label) == now_seg);
2619 symbol_set_frag (l->label, frag_now);
2620 val = (valueT) frag_now_fix ();
2621 /* mips16 text labels are stored as odd. */
2622 if (mips_opts.mips16)
2624 S_SET_VALUE (l->label, val);
2629 /* Mark instruction labels in mips16 mode. */
2631 mips16_mark_labels ();
2633 mips_no_prev_insn (insns);
2636 /* Build an instruction created by a macro expansion. This is passed
2637 a pointer to the count of instructions created so far, an
2638 expression, the name of the instruction to build, an operand format
2639 string, and corresponding arguments. */
2643 macro_build (char *place,
2651 macro_build (place, counter, ep, name, fmt, va_alist)
2660 struct mips_cl_insn insn;
2661 bfd_reloc_code_real_type r[3];
2665 va_start (args, fmt);
2671 * If the macro is about to expand into a second instruction,
2672 * print a warning if needed. We need to pass ip as a parameter
2673 * to generate a better warning message here...
2675 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2676 as_warn (_("Macro instruction expanded into multiple instructions"));
2679 * If the macro is about to expand into a second instruction,
2680 * and it is in a delay slot, print a warning.
2684 && mips_opts.noreorder
2685 && (prev_prev_insn.insn_mo->pinfo
2686 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2687 | INSN_COND_BRANCH_LIKELY)) != 0)
2688 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2691 ++*counter; /* bump instruction counter */
2693 if (mips_opts.mips16)
2695 mips16_macro_build (place, counter, ep, name, fmt, args);
2700 r[0] = BFD_RELOC_UNUSED;
2701 r[1] = BFD_RELOC_UNUSED;
2702 r[2] = BFD_RELOC_UNUSED;
2703 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2704 assert (insn.insn_mo);
2705 assert (strcmp (name, insn.insn_mo->name) == 0);
2707 /* Search until we get a match for NAME. */
2710 /* It is assumed here that macros will never generate
2711 MDMX or MIPS-3D instructions. */
2712 if (strcmp (fmt, insn.insn_mo->args) == 0
2713 && insn.insn_mo->pinfo != INSN_MACRO
2714 && OPCODE_IS_MEMBER (insn.insn_mo,
2716 | (mips_opts.mips16 ? INSN_MIPS16 : 0)),
2718 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2722 assert (insn.insn_mo->name);
2723 assert (strcmp (name, insn.insn_mo->name) == 0);
2726 insn.insn_opcode = insn.insn_mo->match;
2742 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2746 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2751 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2756 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2761 int tmp = va_arg (args, int);
2763 insn.insn_opcode |= tmp << OP_SH_RT;
2764 insn.insn_opcode |= tmp << OP_SH_RD;
2770 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2777 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2781 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2785 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2789 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2793 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2800 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2806 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2807 assert (*r == BFD_RELOC_GPREL16
2808 || *r == BFD_RELOC_MIPS_LITERAL
2809 || *r == BFD_RELOC_MIPS_HIGHER
2810 || *r == BFD_RELOC_HI16_S
2811 || *r == BFD_RELOC_LO16
2812 || *r == BFD_RELOC_MIPS_GOT16
2813 || *r == BFD_RELOC_MIPS_CALL16
2814 || *r == BFD_RELOC_MIPS_GOT_DISP
2815 || *r == BFD_RELOC_MIPS_GOT_PAGE
2816 || *r == BFD_RELOC_MIPS_GOT_OFST
2817 || *r == BFD_RELOC_MIPS_GOT_LO16
2818 || *r == BFD_RELOC_MIPS_CALL_LO16
2819 || (ep->X_op == O_subtract
2820 && *r == BFD_RELOC_PCREL_LO16));
2824 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2826 && (ep->X_op == O_constant
2827 || (ep->X_op == O_symbol
2828 && (*r == BFD_RELOC_MIPS_HIGHEST
2829 || *r == BFD_RELOC_HI16_S
2830 || *r == BFD_RELOC_HI16
2831 || *r == BFD_RELOC_GPREL16
2832 || *r == BFD_RELOC_MIPS_GOT_HI16
2833 || *r == BFD_RELOC_MIPS_CALL_HI16))
2834 || (ep->X_op == O_subtract
2835 && *r == BFD_RELOC_PCREL_HI16_S)));
2839 assert (ep != NULL);
2841 * This allows macro() to pass an immediate expression for
2842 * creating short branches without creating a symbol.
2843 * Note that the expression still might come from the assembly
2844 * input, in which case the value is not checked for range nor
2845 * is a relocation entry generated (yuck).
2847 if (ep->X_op == O_constant)
2849 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2853 if (mips_pic == EMBEDDED_PIC)
2854 *r = BFD_RELOC_16_PCREL_S2;
2856 *r = BFD_RELOC_16_PCREL;
2860 assert (ep != NULL);
2861 *r = BFD_RELOC_MIPS_JMP;
2865 insn.insn_opcode |= va_arg (args, unsigned long);
2874 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2876 append_insn (place, &insn, ep, r, false);
2880 mips16_macro_build (place, counter, ep, name, fmt, args)
2882 int *counter ATTRIBUTE_UNUSED;
2888 struct mips_cl_insn insn;
2889 bfd_reloc_code_real_type r[3]
2890 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2892 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2893 assert (insn.insn_mo);
2894 assert (strcmp (name, insn.insn_mo->name) == 0);
2896 while (strcmp (fmt, insn.insn_mo->args) != 0
2897 || insn.insn_mo->pinfo == INSN_MACRO)
2900 assert (insn.insn_mo->name);
2901 assert (strcmp (name, insn.insn_mo->name) == 0);
2904 insn.insn_opcode = insn.insn_mo->match;
2905 insn.use_extend = false;
2924 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2929 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2933 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2937 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2947 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2954 regno = va_arg (args, int);
2955 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2956 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2977 assert (ep != NULL);
2979 if (ep->X_op != O_constant)
2980 *r = (int) BFD_RELOC_UNUSED + c;
2983 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2984 false, &insn.insn_opcode, &insn.use_extend,
2987 *r = BFD_RELOC_UNUSED;
2993 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3000 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3002 append_insn (place, &insn, ep, r, false);
3006 * Generate a "jalr" instruction with a relocation hint to the called
3007 * function. This occurs in NewABI PIC code.
3010 macro_build_jalr (icnt, ep)
3021 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3024 fix_new_exp (frag_now, f - frag_now->fr_literal,
3025 0, ep, false, BFD_RELOC_MIPS_JALR);
3029 * Generate a "lui" instruction.
3032 macro_build_lui (place, counter, ep, regnum)
3038 expressionS high_expr;
3039 struct mips_cl_insn insn;
3040 bfd_reloc_code_real_type r[3]
3041 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3042 const char *name = "lui";
3043 const char *fmt = "t,u";
3045 assert (! mips_opts.mips16);
3051 high_expr.X_op = O_constant;
3052 high_expr.X_add_number = ep->X_add_number;
3055 if (high_expr.X_op == O_constant)
3057 /* we can compute the instruction now without a relocation entry */
3058 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3060 *r = BFD_RELOC_UNUSED;
3062 else if (! HAVE_NEWABI)
3064 assert (ep->X_op == O_symbol);
3065 /* _gp_disp is a special case, used from s_cpload. */
3066 assert (mips_pic == NO_PIC
3067 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3068 *r = BFD_RELOC_HI16_S;
3072 * If the macro is about to expand into a second instruction,
3073 * print a warning if needed. We need to pass ip as a parameter
3074 * to generate a better warning message here...
3076 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3077 as_warn (_("Macro instruction expanded into multiple instructions"));
3080 ++*counter; /* bump instruction counter */
3082 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3083 assert (insn.insn_mo);
3084 assert (strcmp (name, insn.insn_mo->name) == 0);
3085 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3087 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3088 if (*r == BFD_RELOC_UNUSED)
3090 insn.insn_opcode |= high_expr.X_add_number;
3091 append_insn (place, &insn, NULL, r, false);
3094 append_insn (place, &insn, &high_expr, r, false);
3097 /* Generate a sequence of instructions to do a load or store from a constant
3098 offset off of a base register (breg) into/from a target register (treg),
3099 using AT if necessary. */
3101 macro_build_ldst_constoffset (place, counter, ep, op, treg, breg)
3108 assert (ep->X_op == O_constant);
3110 /* Right now, this routine can only handle signed 32-bit contants. */
3111 if (! IS_SEXT_32BIT_NUM(ep->X_add_number))
3112 as_warn (_("operand overflow"));
3114 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3116 /* Signed 16-bit offset will fit in the op. Easy! */
3117 macro_build (place, counter, ep, op, "t,o(b)", treg,
3118 (int) BFD_RELOC_LO16, breg);
3122 /* 32-bit offset, need multiple instructions and AT, like:
3123 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3124 addu $tempreg,$tempreg,$breg
3125 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3126 to handle the complete offset. */
3127 macro_build_lui (place, counter, ep, AT);
3130 macro_build (place, counter, (expressionS *) NULL,
3131 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
3132 "d,v,t", AT, AT, breg);
3135 macro_build (place, counter, ep, op, "t,o(b)", treg,
3136 (int) BFD_RELOC_LO16, AT);
3139 as_warn (_("Macro used $at after \".set noat\""));
3144 * Generates code to set the $at register to true (one)
3145 * if reg is less than the immediate expression.
3148 set_at (counter, reg, unsignedp)
3153 if (imm_expr.X_op == O_constant
3154 && imm_expr.X_add_number >= -0x8000
3155 && imm_expr.X_add_number < 0x8000)
3156 macro_build ((char *) NULL, counter, &imm_expr,
3157 unsignedp ? "sltiu" : "slti",
3158 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3161 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3162 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3163 unsignedp ? "sltu" : "slt",
3164 "d,v,t", AT, reg, AT);
3168 /* Warn if an expression is not a constant. */
3171 check_absolute_expr (ip, ex)
3172 struct mips_cl_insn *ip;
3175 if (ex->X_op == O_big)
3176 as_bad (_("unsupported large constant"));
3177 else if (ex->X_op != O_constant)
3178 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3181 /* Count the leading zeroes by performing a binary chop. This is a
3182 bulky bit of source, but performance is a LOT better for the
3183 majority of values than a simple loop to count the bits:
3184 for (lcnt = 0; (lcnt < 32); lcnt++)
3185 if ((v) & (1 << (31 - lcnt)))
3187 However it is not code size friendly, and the gain will drop a bit
3188 on certain cached systems.
3190 #define COUNT_TOP_ZEROES(v) \
3191 (((v) & ~0xffff) == 0 \
3192 ? ((v) & ~0xff) == 0 \
3193 ? ((v) & ~0xf) == 0 \
3194 ? ((v) & ~0x3) == 0 \
3195 ? ((v) & ~0x1) == 0 \
3200 : ((v) & ~0x7) == 0 \
3203 : ((v) & ~0x3f) == 0 \
3204 ? ((v) & ~0x1f) == 0 \
3207 : ((v) & ~0x7f) == 0 \
3210 : ((v) & ~0xfff) == 0 \
3211 ? ((v) & ~0x3ff) == 0 \
3212 ? ((v) & ~0x1ff) == 0 \
3215 : ((v) & ~0x7ff) == 0 \
3218 : ((v) & ~0x3fff) == 0 \
3219 ? ((v) & ~0x1fff) == 0 \
3222 : ((v) & ~0x7fff) == 0 \
3225 : ((v) & ~0xffffff) == 0 \
3226 ? ((v) & ~0xfffff) == 0 \
3227 ? ((v) & ~0x3ffff) == 0 \
3228 ? ((v) & ~0x1ffff) == 0 \
3231 : ((v) & ~0x7ffff) == 0 \
3234 : ((v) & ~0x3fffff) == 0 \
3235 ? ((v) & ~0x1fffff) == 0 \
3238 : ((v) & ~0x7fffff) == 0 \
3241 : ((v) & ~0xfffffff) == 0 \
3242 ? ((v) & ~0x3ffffff) == 0 \
3243 ? ((v) & ~0x1ffffff) == 0 \
3246 : ((v) & ~0x7ffffff) == 0 \
3249 : ((v) & ~0x3fffffff) == 0 \
3250 ? ((v) & ~0x1fffffff) == 0 \
3253 : ((v) & ~0x7fffffff) == 0 \
3258 * This routine generates the least number of instructions neccessary to load
3259 * an absolute expression value into a register.
3262 load_register (counter, reg, ep, dbl)
3269 expressionS hi32, lo32;
3271 if (ep->X_op != O_big)
3273 assert (ep->X_op == O_constant);
3274 if (ep->X_add_number < 0x8000
3275 && (ep->X_add_number >= 0
3276 || (ep->X_add_number >= -0x8000
3279 || sizeof (ep->X_add_number) > 4))))
3281 /* We can handle 16 bit signed values with an addiu to
3282 $zero. No need to ever use daddiu here, since $zero and
3283 the result are always correct in 32 bit mode. */
3284 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3285 (int) BFD_RELOC_LO16);
3288 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3290 /* We can handle 16 bit unsigned values with an ori to
3292 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3293 (int) BFD_RELOC_LO16);
3296 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3299 || sizeof (ep->X_add_number) > 4
3300 || (ep->X_add_number & 0x80000000) == 0))
3301 || ((HAVE_32BIT_GPRS || ! dbl)
3302 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3305 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3306 == ~ (offsetT) 0xffffffff)))
3308 /* 32 bit values require an lui. */
3309 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3310 (int) BFD_RELOC_HI16);
3311 if ((ep->X_add_number & 0xffff) != 0)
3312 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3313 (int) BFD_RELOC_LO16);
3318 /* The value is larger than 32 bits. */
3320 if (HAVE_32BIT_GPRS)
3322 as_bad (_("Number (0x%lx) larger than 32 bits"),
3323 (unsigned long) ep->X_add_number);
3324 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3325 (int) BFD_RELOC_LO16);
3329 if (ep->X_op != O_big)
3332 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3333 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3334 hi32.X_add_number &= 0xffffffff;
3336 lo32.X_add_number &= 0xffffffff;
3340 assert (ep->X_add_number > 2);
3341 if (ep->X_add_number == 3)
3342 generic_bignum[3] = 0;
3343 else if (ep->X_add_number > 4)
3344 as_bad (_("Number larger than 64 bits"));
3345 lo32.X_op = O_constant;
3346 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3347 hi32.X_op = O_constant;
3348 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3351 if (hi32.X_add_number == 0)
3356 unsigned long hi, lo;
3358 if (hi32.X_add_number == (offsetT) 0xffffffff)
3360 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3362 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3363 reg, 0, (int) BFD_RELOC_LO16);
3366 if (lo32.X_add_number & 0x80000000)
3368 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3369 (int) BFD_RELOC_HI16);
3370 if (lo32.X_add_number & 0xffff)
3371 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3372 reg, reg, (int) BFD_RELOC_LO16);
3377 /* Check for 16bit shifted constant. We know that hi32 is
3378 non-zero, so start the mask on the first bit of the hi32
3383 unsigned long himask, lomask;
3387 himask = 0xffff >> (32 - shift);
3388 lomask = (0xffff << shift) & 0xffffffff;
3392 himask = 0xffff << (shift - 32);
3395 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3396 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3400 tmp.X_op = O_constant;
3402 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3403 | (lo32.X_add_number >> shift));
3405 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3406 macro_build ((char *) NULL, counter, &tmp,
3407 "ori", "t,r,i", reg, 0,
3408 (int) BFD_RELOC_LO16);
3409 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3410 (shift >= 32) ? "dsll32" : "dsll",
3412 (shift >= 32) ? shift - 32 : shift);
3417 while (shift <= (64 - 16));
3419 /* Find the bit number of the lowest one bit, and store the
3420 shifted value in hi/lo. */
3421 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3422 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3426 while ((lo & 1) == 0)
3431 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3437 while ((hi & 1) == 0)
3446 /* Optimize if the shifted value is a (power of 2) - 1. */
3447 if ((hi == 0 && ((lo + 1) & lo) == 0)
3448 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3450 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3455 /* This instruction will set the register to be all
3457 tmp.X_op = O_constant;
3458 tmp.X_add_number = (offsetT) -1;
3459 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3460 reg, 0, (int) BFD_RELOC_LO16);
3464 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3465 (bit >= 32) ? "dsll32" : "dsll",
3467 (bit >= 32) ? bit - 32 : bit);
3469 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3470 (shift >= 32) ? "dsrl32" : "dsrl",
3472 (shift >= 32) ? shift - 32 : shift);
3477 /* Sign extend hi32 before calling load_register, because we can
3478 generally get better code when we load a sign extended value. */
3479 if ((hi32.X_add_number & 0x80000000) != 0)
3480 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3481 load_register (counter, reg, &hi32, 0);
3484 if ((lo32.X_add_number & 0xffff0000) == 0)
3488 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3489 "dsll32", "d,w,<", reg, freg, 0);
3497 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3499 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3500 (int) BFD_RELOC_HI16);
3501 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3502 "dsrl32", "d,w,<", reg, reg, 0);
3508 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3509 "d,w,<", reg, freg, 16);
3513 mid16.X_add_number >>= 16;
3514 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3515 freg, (int) BFD_RELOC_LO16);
3516 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3517 "d,w,<", reg, reg, 16);
3520 if ((lo32.X_add_number & 0xffff) != 0)
3521 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3522 (int) BFD_RELOC_LO16);
3525 /* Load an address into a register. */
3528 load_address (counter, reg, ep, used_at)
3536 if (ep->X_op != O_constant
3537 && ep->X_op != O_symbol)
3539 as_bad (_("expression too complex"));
3540 ep->X_op = O_constant;
3543 if (ep->X_op == O_constant)
3545 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3549 if (mips_pic == NO_PIC)
3551 /* If this is a reference to a GP relative symbol, we want
3552 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3554 lui $reg,<sym> (BFD_RELOC_HI16_S)
3555 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3556 If we have an addend, we always use the latter form.
3558 With 64bit address space and a usable $at we want
3559 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3560 lui $at,<sym> (BFD_RELOC_HI16_S)
3561 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3562 daddiu $at,<sym> (BFD_RELOC_LO16)
3566 If $at is already in use, we use an path which is suboptimal
3567 on superscalar processors.
3568 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3569 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3571 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3573 daddiu $reg,<sym> (BFD_RELOC_LO16)
3575 if (HAVE_64BIT_ADDRESSES)
3577 /* We don't do GP optimization for now because RELAX_ENCODE can't
3578 hold the data for such large chunks. */
3580 if (*used_at == 0 && ! mips_opts.noat)
3582 macro_build (p, counter, ep, "lui", "t,u",
3583 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3584 macro_build (p, counter, ep, "lui", "t,u",
3585 AT, (int) BFD_RELOC_HI16_S);
3586 macro_build (p, counter, ep, "daddiu", "t,r,j",
3587 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3588 macro_build (p, counter, ep, "daddiu", "t,r,j",
3589 AT, AT, (int) BFD_RELOC_LO16);
3590 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3591 "d,w,<", reg, reg, 0);
3592 macro_build (p, counter, (expressionS *) NULL, "daddu",
3593 "d,v,t", reg, reg, AT);
3598 macro_build (p, counter, ep, "lui", "t,u",
3599 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3600 macro_build (p, counter, ep, "daddiu", "t,r,j",
3601 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3602 macro_build (p, counter, (expressionS *) NULL, "dsll",
3603 "d,w,<", reg, reg, 16);
3604 macro_build (p, counter, ep, "daddiu", "t,r,j",
3605 reg, reg, (int) BFD_RELOC_HI16_S);
3606 macro_build (p, counter, (expressionS *) NULL, "dsll",
3607 "d,w,<", reg, reg, 16);
3608 macro_build (p, counter, ep, "daddiu", "t,r,j",
3609 reg, reg, (int) BFD_RELOC_LO16);
3614 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3615 && ! nopic_need_relax (ep->X_add_symbol, 1))
3618 macro_build ((char *) NULL, counter, ep,
3619 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3620 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3621 p = frag_var (rs_machine_dependent, 8, 0,
3622 RELAX_ENCODE (4, 8, 0, 4, 0,
3623 mips_opts.warn_about_macros),
3624 ep->X_add_symbol, 0, NULL);
3626 macro_build_lui (p, counter, ep, reg);
3629 macro_build (p, counter, ep,
3630 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3631 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3634 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3638 /* If this is a reference to an external symbol, we want
3639 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3641 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3643 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3644 If we have NewABI, we want
3645 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3646 If there is a constant, it must be added in after. */
3647 ex.X_add_number = ep->X_add_number;
3648 ep->X_add_number = 0;
3652 macro_build ((char *) NULL, counter, ep,
3653 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3654 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3658 macro_build ((char *) NULL, counter, ep,
3659 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3660 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3661 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3662 p = frag_var (rs_machine_dependent, 4, 0,
3663 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3664 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3665 macro_build (p, counter, ep,
3666 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3667 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3670 if (ex.X_add_number != 0)
3672 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3673 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3674 ex.X_op = O_constant;
3675 macro_build ((char *) NULL, counter, &ex,
3676 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3677 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3680 else if (mips_pic == SVR4_PIC)
3685 /* This is the large GOT case. If this is a reference to an
3686 external symbol, we want
3687 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3689 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3690 Otherwise, for a reference to a local symbol, we want
3691 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3693 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3694 If we have NewABI, we want
3695 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3696 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3697 If there is a constant, it must be added in after. */
3698 ex.X_add_number = ep->X_add_number;
3699 ep->X_add_number = 0;
3702 macro_build ((char *) NULL, counter, ep,
3703 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3704 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3705 macro_build (p, counter, ep,
3706 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3707 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3711 if (reg_needs_delay (mips_gp_register))
3716 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3717 (int) BFD_RELOC_MIPS_GOT_HI16);
3718 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3719 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3720 reg, mips_gp_register);
3721 macro_build ((char *) NULL, counter, ep,
3722 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3723 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3724 p = frag_var (rs_machine_dependent, 12 + off, 0,
3725 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3726 mips_opts.warn_about_macros),
3727 ep->X_add_symbol, 0, NULL);
3730 /* We need a nop before loading from $gp. This special
3731 check is required because the lui which starts the main
3732 instruction stream does not refer to $gp, and so will not
3733 insert the nop which may be required. */
3734 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3737 macro_build (p, counter, ep,
3738 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3739 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3741 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3743 macro_build (p, counter, ep,
3744 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3745 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3748 if (ex.X_add_number != 0)
3750 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3751 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3752 ex.X_op = O_constant;
3753 macro_build ((char *) NULL, counter, &ex,
3754 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3755 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3758 else if (mips_pic == EMBEDDED_PIC)
3761 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3763 macro_build ((char *) NULL, counter, ep,
3764 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3765 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3771 /* Move the contents of register SOURCE into register DEST. */
3774 move_register (counter, dest, source)
3779 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3780 HAVE_32BIT_GPRS ? "addu" : "daddu",
3781 "d,v,t", dest, source, 0);
3786 * This routine implements the seemingly endless macro or synthesized
3787 * instructions and addressing modes in the mips assembly language. Many
3788 * of these macros are simple and are similar to each other. These could
3789 * probably be handled by some kind of table or grammer aproach instead of
3790 * this verbose method. Others are not simple macros but are more like
3791 * optimizing code generation.
3792 * One interesting optimization is when several store macros appear
3793 * consecutivly that would load AT with the upper half of the same address.
3794 * The ensuing load upper instructions are ommited. This implies some kind
3795 * of global optimization. We currently only optimize within a single macro.
3796 * For many of the load and store macros if the address is specified as a
3797 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3798 * first load register 'at' with zero and use it as the base register. The
3799 * mips assembler simply uses register $zero. Just one tiny optimization
3804 struct mips_cl_insn *ip;
3806 register int treg, sreg, dreg, breg;
3822 bfd_reloc_code_real_type r;
3823 int hold_mips_optimize;
3825 assert (! mips_opts.mips16);
3827 treg = (ip->insn_opcode >> 16) & 0x1f;
3828 dreg = (ip->insn_opcode >> 11) & 0x1f;
3829 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3830 mask = ip->insn_mo->mask;
3832 expr1.X_op = O_constant;
3833 expr1.X_op_symbol = NULL;
3834 expr1.X_add_symbol = NULL;
3835 expr1.X_add_number = 1;
3847 mips_emit_delays (true);
3848 ++mips_opts.noreorder;
3849 mips_any_noreorder = 1;
3851 expr1.X_add_number = 8;
3852 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3854 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3857 move_register (&icnt, dreg, sreg);
3858 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3859 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3861 --mips_opts.noreorder;
3882 if (imm_expr.X_op == O_constant
3883 && imm_expr.X_add_number >= -0x8000
3884 && imm_expr.X_add_number < 0x8000)
3886 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3887 (int) BFD_RELOC_LO16);
3890 load_register (&icnt, AT, &imm_expr, dbl);
3891 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3911 if (imm_expr.X_op == O_constant
3912 && imm_expr.X_add_number >= 0
3913 && imm_expr.X_add_number < 0x10000)
3915 if (mask != M_NOR_I)
3916 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3917 sreg, (int) BFD_RELOC_LO16);
3920 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3921 treg, sreg, (int) BFD_RELOC_LO16);
3922 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3923 "d,v,t", treg, treg, 0);
3928 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3929 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3947 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3949 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3953 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3954 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3962 macro_build ((char *) NULL, &icnt, &offset_expr,
3963 likely ? "bgezl" : "bgez", "s,p", sreg);
3968 macro_build ((char *) NULL, &icnt, &offset_expr,
3969 likely ? "blezl" : "blez", "s,p", treg);
3972 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3974 macro_build ((char *) NULL, &icnt, &offset_expr,
3975 likely ? "beql" : "beq", "s,t,p", AT, 0);
3981 /* check for > max integer */
3982 maxnum = 0x7fffffff;
3983 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3990 if (imm_expr.X_op == O_constant
3991 && imm_expr.X_add_number >= maxnum
3992 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3995 /* result is always false */
3999 as_warn (_("Branch %s is always false (nop)"),
4001 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
4007 as_warn (_("Branch likely %s is always false"),
4009 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
4014 if (imm_expr.X_op != O_constant)
4015 as_bad (_("Unsupported large constant"));
4016 ++imm_expr.X_add_number;
4020 if (mask == M_BGEL_I)
4022 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4024 macro_build ((char *) NULL, &icnt, &offset_expr,
4025 likely ? "bgezl" : "bgez", "s,p", sreg);
4028 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4030 macro_build ((char *) NULL, &icnt, &offset_expr,
4031 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4034 maxnum = 0x7fffffff;
4035 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4042 maxnum = - maxnum - 1;
4043 if (imm_expr.X_op == O_constant
4044 && imm_expr.X_add_number <= maxnum
4045 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4048 /* result is always true */
4049 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4050 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4053 set_at (&icnt, sreg, 0);
4054 macro_build ((char *) NULL, &icnt, &offset_expr,
4055 likely ? "beql" : "beq", "s,t,p", AT, 0);
4065 macro_build ((char *) NULL, &icnt, &offset_expr,
4066 likely ? "beql" : "beq", "s,t,p", 0, treg);
4069 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4070 "d,v,t", AT, sreg, treg);
4071 macro_build ((char *) NULL, &icnt, &offset_expr,
4072 likely ? "beql" : "beq", "s,t,p", AT, 0);
4080 && imm_expr.X_op == O_constant
4081 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4083 if (imm_expr.X_op != O_constant)
4084 as_bad (_("Unsupported large constant"));
4085 ++imm_expr.X_add_number;
4089 if (mask == M_BGEUL_I)
4091 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4093 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4095 macro_build ((char *) NULL, &icnt, &offset_expr,
4096 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4099 set_at (&icnt, sreg, 1);
4100 macro_build ((char *) NULL, &icnt, &offset_expr,
4101 likely ? "beql" : "beq", "s,t,p", AT, 0);
4109 macro_build ((char *) NULL, &icnt, &offset_expr,
4110 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4115 macro_build ((char *) NULL, &icnt, &offset_expr,
4116 likely ? "bltzl" : "bltz", "s,p", treg);
4119 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4121 macro_build ((char *) NULL, &icnt, &offset_expr,
4122 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4130 macro_build ((char *) NULL, &icnt, &offset_expr,
4131 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4136 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4137 "d,v,t", AT, treg, sreg);
4138 macro_build ((char *) NULL, &icnt, &offset_expr,
4139 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4147 macro_build ((char *) NULL, &icnt, &offset_expr,
4148 likely ? "blezl" : "blez", "s,p", sreg);
4153 macro_build ((char *) NULL, &icnt, &offset_expr,
4154 likely ? "bgezl" : "bgez", "s,p", treg);
4157 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4159 macro_build ((char *) NULL, &icnt, &offset_expr,
4160 likely ? "beql" : "beq", "s,t,p", AT, 0);
4166 maxnum = 0x7fffffff;
4167 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4174 if (imm_expr.X_op == O_constant
4175 && imm_expr.X_add_number >= maxnum
4176 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4178 if (imm_expr.X_op != O_constant)
4179 as_bad (_("Unsupported large constant"));
4180 ++imm_expr.X_add_number;
4184 if (mask == M_BLTL_I)
4186 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4188 macro_build ((char *) NULL, &icnt, &offset_expr,
4189 likely ? "bltzl" : "bltz", "s,p", sreg);
4192 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4194 macro_build ((char *) NULL, &icnt, &offset_expr,
4195 likely ? "blezl" : "blez", "s,p", sreg);
4198 set_at (&icnt, sreg, 0);
4199 macro_build ((char *) NULL, &icnt, &offset_expr,
4200 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4208 macro_build ((char *) NULL, &icnt, &offset_expr,
4209 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4214 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4215 "d,v,t", AT, treg, sreg);
4216 macro_build ((char *) NULL, &icnt, &offset_expr,
4217 likely ? "beql" : "beq", "s,t,p", AT, 0);
4225 && imm_expr.X_op == O_constant
4226 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4228 if (imm_expr.X_op != O_constant)
4229 as_bad (_("Unsupported large constant"));
4230 ++imm_expr.X_add_number;
4234 if (mask == M_BLTUL_I)
4236 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4238 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4240 macro_build ((char *) NULL, &icnt, &offset_expr,
4241 likely ? "beql" : "beq",
4245 set_at (&icnt, sreg, 1);
4246 macro_build ((char *) NULL, &icnt, &offset_expr,
4247 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4255 macro_build ((char *) NULL, &icnt, &offset_expr,
4256 likely ? "bltzl" : "bltz", "s,p", sreg);
4261 macro_build ((char *) NULL, &icnt, &offset_expr,
4262 likely ? "bgtzl" : "bgtz", "s,p", treg);
4265 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4267 macro_build ((char *) NULL, &icnt, &offset_expr,
4268 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4278 macro_build ((char *) NULL, &icnt, &offset_expr,
4279 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4282 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4285 macro_build ((char *) NULL, &icnt, &offset_expr,
4286 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4301 as_warn (_("Divide by zero."));
4303 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4306 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4311 mips_emit_delays (true);
4312 ++mips_opts.noreorder;
4313 mips_any_noreorder = 1;
4316 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4317 "s,t,q", treg, 0, 7);
4318 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4319 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4323 expr1.X_add_number = 8;
4324 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4325 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4326 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4327 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4330 expr1.X_add_number = -1;
4331 macro_build ((char *) NULL, &icnt, &expr1,
4332 dbl ? "daddiu" : "addiu",
4333 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4334 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4335 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4338 expr1.X_add_number = 1;
4339 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4340 (int) BFD_RELOC_LO16);
4341 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4342 "d,w,<", AT, AT, 31);
4346 expr1.X_add_number = 0x80000000;
4347 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4348 (int) BFD_RELOC_HI16);
4352 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4353 "s,t,q", sreg, AT, 6);
4354 /* We want to close the noreorder block as soon as possible, so
4355 that later insns are available for delay slot filling. */
4356 --mips_opts.noreorder;
4360 expr1.X_add_number = 8;
4361 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4362 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4365 /* We want to close the noreorder block as soon as possible, so
4366 that later insns are available for delay slot filling. */
4367 --mips_opts.noreorder;
4369 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4372 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4411 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4413 as_warn (_("Divide by zero."));
4415 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4418 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4422 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4424 if (strcmp (s2, "mflo") == 0)
4425 move_register (&icnt, dreg, sreg);
4427 move_register (&icnt, dreg, 0);
4430 if (imm_expr.X_op == O_constant
4431 && imm_expr.X_add_number == -1
4432 && s[strlen (s) - 1] != 'u')
4434 if (strcmp (s2, "mflo") == 0)
4436 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4437 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4440 move_register (&icnt, dreg, 0);
4444 load_register (&icnt, AT, &imm_expr, dbl);
4445 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4447 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4466 mips_emit_delays (true);
4467 ++mips_opts.noreorder;
4468 mips_any_noreorder = 1;
4471 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4472 "s,t,q", treg, 0, 7);
4473 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4475 /* We want to close the noreorder block as soon as possible, so
4476 that later insns are available for delay slot filling. */
4477 --mips_opts.noreorder;
4481 expr1.X_add_number = 8;
4482 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4483 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4486 /* We want to close the noreorder block as soon as possible, so
4487 that later insns are available for delay slot filling. */
4488 --mips_opts.noreorder;
4489 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4492 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4498 /* Load the address of a symbol into a register. If breg is not
4499 zero, we then add a base register to it. */
4501 if (dbl && HAVE_32BIT_GPRS)
4502 as_warn (_("dla used to load 32-bit register"));
4504 if (! dbl && HAVE_64BIT_OBJECTS)
4505 as_warn (_("la used to load 64-bit address"));
4507 if (offset_expr.X_op == O_constant
4508 && offset_expr.X_add_number >= -0x8000
4509 && offset_expr.X_add_number < 0x8000)
4511 macro_build ((char *) NULL, &icnt, &offset_expr,
4512 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4513 "t,r,j", treg, sreg, (int) BFD_RELOC_LO16);
4528 /* When generating embedded PIC code, we permit expressions of
4531 la $treg,foo-bar($breg)
4532 where bar is an address in the current section. These are used
4533 when getting the addresses of functions. We don't permit
4534 X_add_number to be non-zero, because if the symbol is
4535 external the relaxing code needs to know that any addend is
4536 purely the offset to X_op_symbol. */
4537 if (mips_pic == EMBEDDED_PIC
4538 && offset_expr.X_op == O_subtract
4539 && (symbol_constant_p (offset_expr.X_op_symbol)
4540 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4541 : (symbol_equated_p (offset_expr.X_op_symbol)
4543 (symbol_get_value_expression (offset_expr.X_op_symbol)
4546 && (offset_expr.X_add_number == 0
4547 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4553 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4554 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4558 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4559 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4560 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4561 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4562 "d,v,t", tempreg, tempreg, breg);
4564 macro_build ((char *) NULL, &icnt, &offset_expr,
4565 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4566 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4572 if (offset_expr.X_op != O_symbol
4573 && offset_expr.X_op != O_constant)
4575 as_bad (_("expression too complex"));
4576 offset_expr.X_op = O_constant;
4579 if (offset_expr.X_op == O_constant)
4580 load_register (&icnt, tempreg, &offset_expr,
4581 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4582 ? (dbl || HAVE_64BIT_ADDRESSES)
4583 : HAVE_64BIT_ADDRESSES));
4584 else if (mips_pic == NO_PIC)
4586 /* If this is a reference to a GP relative symbol, we want
4587 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4589 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4590 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4591 If we have a constant, we need two instructions anyhow,
4592 so we may as well always use the latter form.
4594 With 64bit address space and a usable $at we want
4595 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4596 lui $at,<sym> (BFD_RELOC_HI16_S)
4597 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4598 daddiu $at,<sym> (BFD_RELOC_LO16)
4600 daddu $tempreg,$tempreg,$at
4602 If $at is already in use, we use an path which is suboptimal
4603 on superscalar processors.
4604 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4605 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4607 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4609 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4612 if (HAVE_64BIT_ADDRESSES)
4614 /* We don't do GP optimization for now because RELAX_ENCODE can't
4615 hold the data for such large chunks. */
4617 if (used_at == 0 && ! mips_opts.noat)
4619 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4620 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4621 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4622 AT, (int) BFD_RELOC_HI16_S);
4623 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4624 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4625 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4626 AT, AT, (int) BFD_RELOC_LO16);
4627 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4628 "d,w,<", tempreg, tempreg, 0);
4629 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
4630 "d,v,t", tempreg, tempreg, AT);
4635 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4636 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4637 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4638 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4639 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4640 tempreg, tempreg, 16);
4641 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4642 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4643 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4644 tempreg, tempreg, 16);
4645 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4646 tempreg, tempreg, (int) BFD_RELOC_LO16);
4651 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4652 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4655 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4656 "t,r,j", tempreg, mips_gp_register,
4657 (int) BFD_RELOC_GPREL16);
4658 p = frag_var (rs_machine_dependent, 8, 0,
4659 RELAX_ENCODE (4, 8, 0, 4, 0,
4660 mips_opts.warn_about_macros),
4661 offset_expr.X_add_symbol, 0, NULL);
4663 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4666 macro_build (p, &icnt, &offset_expr, "addiu",
4667 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4670 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4672 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4674 /* If this is a reference to an external symbol, and there
4675 is no constant, we want
4676 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4677 or if tempreg is PIC_CALL_REG
4678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4679 For a local symbol, we want
4680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4682 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4684 If we have a small constant, and this is a reference to
4685 an external symbol, we want
4686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4688 addiu $tempreg,$tempreg,<constant>
4689 For a local symbol, we want the same instruction
4690 sequence, but we output a BFD_RELOC_LO16 reloc on the
4693 If we have a large constant, and this is a reference to
4694 an external symbol, we want
4695 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4696 lui $at,<hiconstant>
4697 addiu $at,$at,<loconstant>
4698 addu $tempreg,$tempreg,$at
4699 For a local symbol, we want the same instruction
4700 sequence, but we output a BFD_RELOC_LO16 reloc on the
4703 For NewABI, we want for local or external data addresses
4704 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4705 For a local function symbol, we want
4706 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4708 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4711 expr1.X_add_number = offset_expr.X_add_number;
4712 offset_expr.X_add_number = 0;
4714 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4715 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4716 else if (HAVE_NEWABI)
4717 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4718 macro_build ((char *) NULL, &icnt, &offset_expr,
4719 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4720 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4721 if (expr1.X_add_number == 0)
4730 /* We're going to put in an addu instruction using
4731 tempreg, so we may as well insert the nop right
4733 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4737 p = frag_var (rs_machine_dependent, 8 - off, 0,
4738 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4740 ? mips_opts.warn_about_macros
4742 offset_expr.X_add_symbol, 0, NULL);
4745 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4748 macro_build (p, &icnt, &expr1,
4749 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4750 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4751 /* FIXME: If breg == 0, and the next instruction uses
4752 $tempreg, then if this variant case is used an extra
4753 nop will be generated. */
4755 else if (expr1.X_add_number >= -0x8000
4756 && expr1.X_add_number < 0x8000)
4758 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4760 macro_build ((char *) NULL, &icnt, &expr1,
4761 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4762 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4763 frag_var (rs_machine_dependent, 0, 0,
4764 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4765 offset_expr.X_add_symbol, 0, NULL);
4771 /* If we are going to add in a base register, and the
4772 target register and the base register are the same,
4773 then we are using AT as a temporary register. Since
4774 we want to load the constant into AT, we add our
4775 current AT (from the global offset table) and the
4776 register into the register now, and pretend we were
4777 not using a base register. */
4782 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4784 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4785 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4786 "d,v,t", treg, AT, breg);
4792 /* Set mips_optimize around the lui instruction to avoid
4793 inserting an unnecessary nop after the lw. */
4794 hold_mips_optimize = mips_optimize;
4796 macro_build_lui (NULL, &icnt, &expr1, AT);
4797 mips_optimize = hold_mips_optimize;
4799 macro_build ((char *) NULL, &icnt, &expr1,
4800 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4801 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4802 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4803 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4804 "d,v,t", tempreg, tempreg, AT);
4805 frag_var (rs_machine_dependent, 0, 0,
4806 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4807 offset_expr.X_add_symbol, 0, NULL);
4811 else if (mips_pic == SVR4_PIC)
4815 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4816 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4817 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4819 /* This is the large GOT case. If this is a reference to an
4820 external symbol, and there is no constant, we want
4821 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4822 addu $tempreg,$tempreg,$gp
4823 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4824 or if tempreg is PIC_CALL_REG
4825 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4826 addu $tempreg,$tempreg,$gp
4827 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4828 For a local symbol, we want
4829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4831 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4833 If we have a small constant, and this is a reference to
4834 an external symbol, we want
4835 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4836 addu $tempreg,$tempreg,$gp
4837 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4839 addiu $tempreg,$tempreg,<constant>
4840 For a local symbol, we want
4841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4843 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4845 If we have a large constant, and this is a reference to
4846 an external symbol, we want
4847 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4848 addu $tempreg,$tempreg,$gp
4849 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4850 lui $at,<hiconstant>
4851 addiu $at,$at,<loconstant>
4852 addu $tempreg,$tempreg,$at
4853 For a local symbol, we want
4854 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4855 lui $at,<hiconstant>
4856 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4857 addu $tempreg,$tempreg,$at
4859 For NewABI, we want for local data addresses
4860 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4863 expr1.X_add_number = offset_expr.X_add_number;
4864 offset_expr.X_add_number = 0;
4866 if (reg_needs_delay (mips_gp_register))
4870 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4872 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4873 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4875 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4876 tempreg, lui_reloc_type);
4877 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4878 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4879 "d,v,t", tempreg, tempreg, mips_gp_register);
4880 macro_build ((char *) NULL, &icnt, &offset_expr,
4881 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4882 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4883 if (expr1.X_add_number == 0)
4891 /* We're going to put in an addu instruction using
4892 tempreg, so we may as well insert the nop right
4894 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4899 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4900 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4903 ? mips_opts.warn_about_macros
4905 offset_expr.X_add_symbol, 0, NULL);
4907 else if (expr1.X_add_number >= -0x8000
4908 && expr1.X_add_number < 0x8000)
4910 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4912 macro_build ((char *) NULL, &icnt, &expr1,
4913 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4914 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4916 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4917 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4919 ? mips_opts.warn_about_macros
4921 offset_expr.X_add_symbol, 0, NULL);
4927 /* If we are going to add in a base register, and the
4928 target register and the base register are the same,
4929 then we are using AT as a temporary register. Since
4930 we want to load the constant into AT, we add our
4931 current AT (from the global offset table) and the
4932 register into the register now, and pretend we were
4933 not using a base register. */
4941 assert (tempreg == AT);
4942 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4944 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4945 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4946 "d,v,t", treg, AT, breg);
4951 /* Set mips_optimize around the lui instruction to avoid
4952 inserting an unnecessary nop after the lw. */
4953 hold_mips_optimize = mips_optimize;
4955 macro_build_lui (NULL, &icnt, &expr1, AT);
4956 mips_optimize = hold_mips_optimize;
4958 macro_build ((char *) NULL, &icnt, &expr1,
4959 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4960 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4961 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4962 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4963 "d,v,t", dreg, dreg, AT);
4965 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4966 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4969 ? mips_opts.warn_about_macros
4971 offset_expr.X_add_symbol, 0, NULL);
4978 /* This is needed because this instruction uses $gp, but
4979 the first instruction on the main stream does not. */
4980 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4985 local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
4986 macro_build (p, &icnt, &offset_expr,
4987 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4992 if (expr1.X_add_number == 0 && HAVE_NEWABI)
4994 /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */
4997 if (expr1.X_add_number >= -0x8000
4998 && expr1.X_add_number < 0x8000)
5000 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5002 macro_build (p, &icnt, &expr1,
5003 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5004 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5005 /* FIXME: If add_number is 0, and there was no base
5006 register, the external symbol case ended with a load,
5007 so if the symbol turns out to not be external, and
5008 the next instruction uses tempreg, an unnecessary nop
5009 will be inserted. */
5015 /* We must add in the base register now, as in the
5016 external symbol case. */
5017 assert (tempreg == AT);
5018 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5020 macro_build (p, &icnt, (expressionS *) NULL,
5021 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5022 "d,v,t", treg, AT, breg);
5025 /* We set breg to 0 because we have arranged to add
5026 it in in both cases. */
5030 macro_build_lui (p, &icnt, &expr1, AT);
5032 macro_build (p, &icnt, &expr1,
5033 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5034 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
5036 macro_build (p, &icnt, (expressionS *) NULL,
5037 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5038 "d,v,t", tempreg, tempreg, AT);
5042 else if (mips_pic == EMBEDDED_PIC)
5045 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5047 macro_build ((char *) NULL, &icnt, &offset_expr,
5048 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
5049 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
5058 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5059 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5061 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
5063 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
5064 "d,v,t", treg, tempreg, breg);
5073 /* The j instruction may not be used in PIC code, since it
5074 requires an absolute address. We convert it to a b
5076 if (mips_pic == NO_PIC)
5077 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5079 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5082 /* The jal instructions must be handled as macros because when
5083 generating PIC code they expand to multi-instruction
5084 sequences. Normally they are simple instructions. */
5089 if (mips_pic == NO_PIC
5090 || mips_pic == EMBEDDED_PIC)
5091 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5093 else if (mips_pic == SVR4_PIC)
5095 if (sreg != PIC_CALL_REG)
5096 as_warn (_("MIPS PIC call to register other than $25"));
5098 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5102 if (mips_cprestore_offset < 0)
5103 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5106 if (! mips_frame_reg_valid)
5108 as_warn (_("No .frame pseudo-op used in PIC code"));
5109 /* Quiet this warning. */
5110 mips_frame_reg_valid = 1;
5112 if (! mips_cprestore_valid)
5114 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5115 /* Quiet this warning. */
5116 mips_cprestore_valid = 1;
5118 expr1.X_add_number = mips_cprestore_offset;
5119 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5120 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5121 mips_gp_register, mips_frame_reg);
5131 if (mips_pic == NO_PIC)
5132 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5133 else if (mips_pic == SVR4_PIC)
5137 /* If this is a reference to an external symbol, and we are
5138 using a small GOT, we want
5139 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5143 lw $gp,cprestore($sp)
5144 The cprestore value is set using the .cprestore
5145 pseudo-op. If we are using a big GOT, we want
5146 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5148 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5152 lw $gp,cprestore($sp)
5153 If the symbol is not external, we want
5154 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5156 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5159 lw $gp,cprestore($sp)
5161 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5162 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5166 macro_build ((char *) NULL, &icnt, &offset_expr,
5167 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5168 "t,o(b)", PIC_CALL_REG,
5169 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5170 macro_build_jalr (icnt, &offset_expr);
5177 macro_build ((char *) NULL, &icnt, &offset_expr,
5178 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5179 "t,o(b)", PIC_CALL_REG,
5180 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5181 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5183 p = frag_var (rs_machine_dependent, 4, 0,
5184 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5185 offset_expr.X_add_symbol, 0, NULL);
5191 if (reg_needs_delay (mips_gp_register))
5195 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5196 "t,u", PIC_CALL_REG,
5197 (int) BFD_RELOC_MIPS_CALL_HI16);
5198 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5199 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5200 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5202 macro_build ((char *) NULL, &icnt, &offset_expr,
5203 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5204 "t,o(b)", PIC_CALL_REG,
5205 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5206 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5208 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5209 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5211 offset_expr.X_add_symbol, 0, NULL);
5214 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5217 macro_build (p, &icnt, &offset_expr,
5218 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5219 "t,o(b)", PIC_CALL_REG,
5220 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5222 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5225 macro_build (p, &icnt, &offset_expr,
5226 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5227 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5228 (int) BFD_RELOC_LO16);
5229 macro_build_jalr (icnt, &offset_expr);
5231 if (mips_cprestore_offset < 0)
5232 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5235 if (! mips_frame_reg_valid)
5237 as_warn (_("No .frame pseudo-op used in PIC code"));
5238 /* Quiet this warning. */
5239 mips_frame_reg_valid = 1;
5241 if (! mips_cprestore_valid)
5243 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5244 /* Quiet this warning. */
5245 mips_cprestore_valid = 1;
5247 if (mips_opts.noreorder)
5248 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5250 expr1.X_add_number = mips_cprestore_offset;
5251 macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1,
5252 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5253 mips_gp_register, mips_frame_reg);
5257 else if (mips_pic == EMBEDDED_PIC)
5259 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5260 /* The linker may expand the call to a longer sequence which
5261 uses $at, so we must break rather than return. */
5286 /* Itbl support may require additional care here. */
5291 /* Itbl support may require additional care here. */
5296 /* Itbl support may require additional care here. */
5301 /* Itbl support may require additional care here. */
5313 if (mips_arch == CPU_R4650)
5315 as_bad (_("opcode not supported on this processor"));
5319 /* Itbl support may require additional care here. */
5324 /* Itbl support may require additional care here. */
5329 /* Itbl support may require additional care here. */
5349 if (breg == treg || coproc || lr)
5371 /* Itbl support may require additional care here. */
5376 /* Itbl support may require additional care here. */
5381 /* Itbl support may require additional care here. */
5386 /* Itbl support may require additional care here. */
5402 if (mips_arch == CPU_R4650)
5404 as_bad (_("opcode not supported on this processor"));
5409 /* Itbl support may require additional care here. */
5413 /* Itbl support may require additional care here. */
5418 /* Itbl support may require additional care here. */
5430 /* Itbl support may require additional care here. */
5431 if (mask == M_LWC1_AB
5432 || mask == M_SWC1_AB
5433 || mask == M_LDC1_AB
5434 || mask == M_SDC1_AB
5443 /* For embedded PIC, we allow loads where the offset is calculated
5444 by subtracting a symbol in the current segment from an unknown
5445 symbol, relative to a base register, e.g.:
5446 <op> $treg, <sym>-<localsym>($breg)
5447 This is used by the compiler for switch statements. */
5448 if (mips_pic == EMBEDDED_PIC
5449 && offset_expr.X_op == O_subtract
5450 && (symbol_constant_p (offset_expr.X_op_symbol)
5451 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5452 : (symbol_equated_p (offset_expr.X_op_symbol)
5454 (symbol_get_value_expression (offset_expr.X_op_symbol)
5458 && (offset_expr.X_add_number == 0
5459 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5461 /* For this case, we output the instructions:
5462 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5463 addiu $tempreg,$tempreg,$breg
5464 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5465 If the relocation would fit entirely in 16 bits, it would be
5467 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5468 instead, but that seems quite difficult. */
5469 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5470 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5471 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5472 ((bfd_arch_bits_per_address (stdoutput) == 32
5473 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5474 ? "addu" : "daddu"),
5475 "d,v,t", tempreg, tempreg, breg);
5476 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5477 (int) BFD_RELOC_PCREL_LO16, tempreg);
5483 if (offset_expr.X_op != O_constant
5484 && offset_expr.X_op != O_symbol)
5486 as_bad (_("expression too complex"));
5487 offset_expr.X_op = O_constant;
5490 /* A constant expression in PIC code can be handled just as it
5491 is in non PIC code. */
5492 if (mips_pic == NO_PIC
5493 || offset_expr.X_op == O_constant)
5497 /* If this is a reference to a GP relative symbol, and there
5498 is no base register, we want
5499 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5500 Otherwise, if there is no base register, we want
5501 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5502 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5503 If we have a constant, we need two instructions anyhow,
5504 so we always use the latter form.
5506 If we have a base register, and this is a reference to a
5507 GP relative symbol, we want
5508 addu $tempreg,$breg,$gp
5509 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5511 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5512 addu $tempreg,$tempreg,$breg
5513 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5514 With a constant we always use the latter case.
5516 With 64bit address space and no base register and $at usable,
5518 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5519 lui $at,<sym> (BFD_RELOC_HI16_S)
5520 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5523 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5524 If we have a base register, we want
5525 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5526 lui $at,<sym> (BFD_RELOC_HI16_S)
5527 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5531 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5533 Without $at we can't generate the optimal path for superscalar
5534 processors here since this would require two temporary registers.
5535 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5536 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5538 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5540 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5541 If we have a base register, we want
5542 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5543 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5545 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5547 daddu $tempreg,$tempreg,$breg
5548 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5550 If we have 64-bit addresses, as an optimization, for
5551 addresses which are 32-bit constants (e.g. kseg0/kseg1
5552 addresses) we fall back to the 32-bit address generation
5553 mechanism since it is more efficient. Note that due to
5554 the signed offset used by memory operations, the 32-bit
5555 range is shifted down by 32768 here. This code should
5556 probably attempt to generate 64-bit constants more
5557 efficiently in general.
5559 if (HAVE_64BIT_ADDRESSES
5560 && !(offset_expr.X_op == O_constant
5561 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5565 /* We don't do GP optimization for now because RELAX_ENCODE can't
5566 hold the data for such large chunks. */
5568 if (used_at == 0 && ! mips_opts.noat)
5570 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5571 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5572 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5573 AT, (int) BFD_RELOC_HI16_S);
5574 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5575 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5577 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5578 "d,v,t", AT, AT, breg);
5579 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5580 "d,w,<", tempreg, tempreg, 0);
5581 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5582 "d,v,t", tempreg, tempreg, AT);
5583 macro_build (p, &icnt, &offset_expr, s,
5584 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5589 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5590 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5591 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5592 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5593 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5594 "d,w,<", tempreg, tempreg, 16);
5595 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5596 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5597 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5598 "d,w,<", tempreg, tempreg, 16);
5600 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5601 "d,v,t", tempreg, tempreg, breg);
5602 macro_build (p, &icnt, &offset_expr, s,
5603 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5611 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5612 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5617 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5618 treg, (int) BFD_RELOC_GPREL16,
5620 p = frag_var (rs_machine_dependent, 8, 0,
5621 RELAX_ENCODE (4, 8, 0, 4, 0,
5622 (mips_opts.warn_about_macros
5624 && mips_opts.noat))),
5625 offset_expr.X_add_symbol, 0, NULL);
5628 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5631 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5632 (int) BFD_RELOC_LO16, tempreg);
5636 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5637 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5642 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5643 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5644 "d,v,t", tempreg, breg, mips_gp_register);
5645 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5646 treg, (int) BFD_RELOC_GPREL16, tempreg);
5647 p = frag_var (rs_machine_dependent, 12, 0,
5648 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5649 offset_expr.X_add_symbol, 0, NULL);
5651 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5654 macro_build (p, &icnt, (expressionS *) NULL,
5655 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5656 "d,v,t", tempreg, tempreg, breg);
5659 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5660 (int) BFD_RELOC_LO16, tempreg);
5663 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5666 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5668 /* If this is a reference to an external symbol, we want
5669 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5671 <op> $treg,0($tempreg)
5673 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5675 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5676 <op> $treg,0($tempreg)
5677 If we have NewABI, we want
5678 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5679 If there is a base register, we add it to $tempreg before
5680 the <op>. If there is a constant, we stick it in the
5681 <op> instruction. We don't handle constants larger than
5682 16 bits, because we have no way to load the upper 16 bits
5683 (actually, we could handle them for the subset of cases
5684 in which we are not using $at). */
5685 assert (offset_expr.X_op == O_symbol);
5686 expr1.X_add_number = offset_expr.X_add_number;
5687 offset_expr.X_add_number = 0;
5689 lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP;
5690 if (expr1.X_add_number < -0x8000
5691 || expr1.X_add_number >= 0x8000)
5692 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5694 macro_build ((char *) NULL, &icnt, &offset_expr,
5695 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5696 (int) lw_reloc_type, mips_gp_register);
5697 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5698 p = frag_var (rs_machine_dependent, 4, 0,
5699 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5700 offset_expr.X_add_symbol, 0, NULL);
5701 macro_build (p, &icnt, &offset_expr,
5702 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5703 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5706 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5707 "d,v,t", tempreg, tempreg, breg);
5708 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5709 (int) BFD_RELOC_LO16, tempreg);
5711 else if (mips_pic == SVR4_PIC)
5716 /* If this is a reference to an external symbol, we want
5717 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5718 addu $tempreg,$tempreg,$gp
5719 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5720 <op> $treg,0($tempreg)
5722 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5724 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5725 <op> $treg,0($tempreg)
5726 If there is a base register, we add it to $tempreg before
5727 the <op>. If there is a constant, we stick it in the
5728 <op> instruction. We don't handle constants larger than
5729 16 bits, because we have no way to load the upper 16 bits
5730 (actually, we could handle them for the subset of cases
5731 in which we are not using $at).
5734 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5735 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5736 <op> $treg,0($tempreg)
5738 assert (offset_expr.X_op == O_symbol);
5739 expr1.X_add_number = offset_expr.X_add_number;
5740 offset_expr.X_add_number = 0;
5741 if (expr1.X_add_number < -0x8000
5742 || expr1.X_add_number >= 0x8000)
5743 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5746 macro_build ((char *) NULL, &icnt, &offset_expr,
5747 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5748 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5750 macro_build ((char *) NULL, &icnt, &offset_expr,
5751 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5752 "t,r,j", tempreg, tempreg,
5753 BFD_RELOC_MIPS_GOT_OFST);
5755 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5756 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5757 "d,v,t", tempreg, tempreg, breg);
5758 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5759 (int) BFD_RELOC_LO16, tempreg);
5766 if (reg_needs_delay (mips_gp_register))
5771 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5772 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5773 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5774 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5775 "d,v,t", tempreg, tempreg, mips_gp_register);
5776 macro_build ((char *) NULL, &icnt, &offset_expr,
5777 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5778 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5780 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5781 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5782 offset_expr.X_add_symbol, 0, NULL);
5785 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5788 macro_build (p, &icnt, &offset_expr,
5789 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5790 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5793 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5795 macro_build (p, &icnt, &offset_expr,
5796 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5797 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5799 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5800 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5801 "d,v,t", tempreg, tempreg, breg);
5802 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5803 (int) BFD_RELOC_LO16, tempreg);
5805 else if (mips_pic == EMBEDDED_PIC)
5807 /* If there is no base register, we want
5808 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5809 If there is a base register, we want
5810 addu $tempreg,$breg,$gp
5811 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5813 assert (offset_expr.X_op == O_symbol);
5816 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5817 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5822 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5823 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5824 "d,v,t", tempreg, breg, mips_gp_register);
5825 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5826 treg, (int) BFD_RELOC_GPREL16, tempreg);
5839 load_register (&icnt, treg, &imm_expr, 0);
5843 load_register (&icnt, treg, &imm_expr, 1);
5847 if (imm_expr.X_op == O_constant)
5849 load_register (&icnt, AT, &imm_expr, 0);
5850 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5851 "mtc1", "t,G", AT, treg);
5856 assert (offset_expr.X_op == O_symbol
5857 && strcmp (segment_name (S_GET_SEGMENT
5858 (offset_expr.X_add_symbol)),
5860 && offset_expr.X_add_number == 0);
5861 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5862 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5867 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5868 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5869 order 32 bits of the value and the low order 32 bits are either
5870 zero or in OFFSET_EXPR. */
5871 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5873 if (HAVE_64BIT_GPRS)
5874 load_register (&icnt, treg, &imm_expr, 1);
5879 if (target_big_endian)
5891 load_register (&icnt, hreg, &imm_expr, 0);
5894 if (offset_expr.X_op == O_absent)
5895 move_register (&icnt, lreg, 0);
5898 assert (offset_expr.X_op == O_constant);
5899 load_register (&icnt, lreg, &offset_expr, 0);
5906 /* We know that sym is in the .rdata section. First we get the
5907 upper 16 bits of the address. */
5908 if (mips_pic == NO_PIC)
5910 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5912 else if (mips_pic == SVR4_PIC)
5914 macro_build ((char *) NULL, &icnt, &offset_expr,
5915 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5916 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5919 else if (mips_pic == EMBEDDED_PIC)
5921 /* For embedded PIC we pick up the entire address off $gp in
5922 a single instruction. */
5923 macro_build ((char *) NULL, &icnt, &offset_expr,
5924 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5925 mips_gp_register, (int) BFD_RELOC_GPREL16);
5926 offset_expr.X_op = O_constant;
5927 offset_expr.X_add_number = 0;
5932 /* Now we load the register(s). */
5933 if (HAVE_64BIT_GPRS)
5934 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5935 treg, (int) BFD_RELOC_LO16, AT);
5938 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5939 treg, (int) BFD_RELOC_LO16, AT);
5942 /* FIXME: How in the world do we deal with the possible
5944 offset_expr.X_add_number += 4;
5945 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5946 treg + 1, (int) BFD_RELOC_LO16, AT);
5950 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5951 does not become a variant frag. */
5952 frag_wane (frag_now);
5958 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5959 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5960 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5961 the value and the low order 32 bits are either zero or in
5963 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5965 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5966 if (HAVE_64BIT_FPRS)
5968 assert (HAVE_64BIT_GPRS);
5969 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5970 "dmtc1", "t,S", AT, treg);
5974 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5975 "mtc1", "t,G", AT, treg + 1);
5976 if (offset_expr.X_op == O_absent)
5977 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5978 "mtc1", "t,G", 0, treg);
5981 assert (offset_expr.X_op == O_constant);
5982 load_register (&icnt, AT, &offset_expr, 0);
5983 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5984 "mtc1", "t,G", AT, treg);
5990 assert (offset_expr.X_op == O_symbol
5991 && offset_expr.X_add_number == 0);
5992 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5993 if (strcmp (s, ".lit8") == 0)
5995 if (mips_opts.isa != ISA_MIPS1)
5997 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5998 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
6002 breg = mips_gp_register;
6003 r = BFD_RELOC_MIPS_LITERAL;
6008 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6009 if (mips_pic == SVR4_PIC)
6010 macro_build ((char *) NULL, &icnt, &offset_expr,
6011 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6012 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6016 /* FIXME: This won't work for a 64 bit address. */
6017 macro_build_lui (NULL, &icnt, &offset_expr, AT);
6020 if (mips_opts.isa != ISA_MIPS1)
6022 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
6023 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
6025 /* To avoid confusion in tc_gen_reloc, we must ensure
6026 that this does not become a variant frag. */
6027 frag_wane (frag_now);
6038 if (mips_arch == CPU_R4650)
6040 as_bad (_("opcode not supported on this processor"));
6043 /* Even on a big endian machine $fn comes before $fn+1. We have
6044 to adjust when loading from memory. */
6047 assert (mips_opts.isa == ISA_MIPS1);
6048 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6049 target_big_endian ? treg + 1 : treg,
6051 /* FIXME: A possible overflow which I don't know how to deal
6053 offset_expr.X_add_number += 4;
6054 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
6055 target_big_endian ? treg : treg + 1,
6058 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6059 does not become a variant frag. */
6060 frag_wane (frag_now);
6069 * The MIPS assembler seems to check for X_add_number not
6070 * being double aligned and generating:
6073 * addiu at,at,%lo(foo+1)
6076 * But, the resulting address is the same after relocation so why
6077 * generate the extra instruction?
6079 if (mips_arch == CPU_R4650)
6081 as_bad (_("opcode not supported on this processor"));
6084 /* Itbl support may require additional care here. */
6086 if (mips_opts.isa != ISA_MIPS1)
6097 if (mips_arch == CPU_R4650)
6099 as_bad (_("opcode not supported on this processor"));
6103 if (mips_opts.isa != ISA_MIPS1)
6111 /* Itbl support may require additional care here. */
6116 if (HAVE_64BIT_GPRS)
6127 if (HAVE_64BIT_GPRS)
6137 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6138 loads for the case of doing a pair of loads to simulate an 'ld'.
6139 This is not currently done by the compiler, and assembly coders
6140 writing embedded-pic code can cope. */
6142 if (offset_expr.X_op != O_symbol
6143 && offset_expr.X_op != O_constant)
6145 as_bad (_("expression too complex"));
6146 offset_expr.X_op = O_constant;
6149 /* Even on a big endian machine $fn comes before $fn+1. We have
6150 to adjust when loading from memory. We set coproc if we must
6151 load $fn+1 first. */
6152 /* Itbl support may require additional care here. */
6153 if (! target_big_endian)
6156 if (mips_pic == NO_PIC
6157 || offset_expr.X_op == O_constant)
6161 /* If this is a reference to a GP relative symbol, we want
6162 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6163 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6164 If we have a base register, we use this
6166 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6167 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6168 If this is not a GP relative symbol, we want
6169 lui $at,<sym> (BFD_RELOC_HI16_S)
6170 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6171 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6172 If there is a base register, we add it to $at after the
6173 lui instruction. If there is a constant, we always use
6175 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6176 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6188 tempreg = mips_gp_register;
6195 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6196 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6197 "d,v,t", AT, breg, mips_gp_register);
6203 /* Itbl support may require additional care here. */
6204 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6205 coproc ? treg + 1 : treg,
6206 (int) BFD_RELOC_GPREL16, tempreg);
6207 offset_expr.X_add_number += 4;
6209 /* Set mips_optimize to 2 to avoid inserting an
6211 hold_mips_optimize = mips_optimize;
6213 /* Itbl support may require additional care here. */
6214 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6215 coproc ? treg : treg + 1,
6216 (int) BFD_RELOC_GPREL16, tempreg);
6217 mips_optimize = hold_mips_optimize;
6219 p = frag_var (rs_machine_dependent, 12 + off, 0,
6220 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6221 used_at && mips_opts.noat),
6222 offset_expr.X_add_symbol, 0, NULL);
6224 /* We just generated two relocs. When tc_gen_reloc
6225 handles this case, it will skip the first reloc and
6226 handle the second. The second reloc already has an
6227 extra addend of 4, which we added above. We must
6228 subtract it out, and then subtract another 4 to make
6229 the first reloc come out right. The second reloc
6230 will come out right because we are going to add 4 to
6231 offset_expr when we build its instruction below.
6233 If we have a symbol, then we don't want to include
6234 the offset, because it will wind up being included
6235 when we generate the reloc. */
6237 if (offset_expr.X_op == O_constant)
6238 offset_expr.X_add_number -= 8;
6241 offset_expr.X_add_number = -4;
6242 offset_expr.X_op = O_constant;
6245 macro_build_lui (p, &icnt, &offset_expr, AT);
6250 macro_build (p, &icnt, (expressionS *) NULL,
6251 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6252 "d,v,t", AT, breg, AT);
6256 /* Itbl support may require additional care here. */
6257 macro_build (p, &icnt, &offset_expr, s, fmt,
6258 coproc ? treg + 1 : treg,
6259 (int) BFD_RELOC_LO16, AT);
6262 /* FIXME: How do we handle overflow here? */
6263 offset_expr.X_add_number += 4;
6264 /* Itbl support may require additional care here. */
6265 macro_build (p, &icnt, &offset_expr, s, fmt,
6266 coproc ? treg : treg + 1,
6267 (int) BFD_RELOC_LO16, AT);
6269 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6273 /* If this is a reference to an external symbol, we want
6274 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6279 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6281 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6282 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6283 If there is a base register we add it to $at before the
6284 lwc1 instructions. If there is a constant we include it
6285 in the lwc1 instructions. */
6287 expr1.X_add_number = offset_expr.X_add_number;
6288 offset_expr.X_add_number = 0;
6289 if (expr1.X_add_number < -0x8000
6290 || expr1.X_add_number >= 0x8000 - 4)
6291 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6296 frag_grow (24 + off);
6297 macro_build ((char *) NULL, &icnt, &offset_expr,
6298 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6299 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6300 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6302 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6303 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6304 "d,v,t", AT, breg, AT);
6305 /* Itbl support may require additional care here. */
6306 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6307 coproc ? treg + 1 : treg,
6308 (int) BFD_RELOC_LO16, AT);
6309 expr1.X_add_number += 4;
6311 /* Set mips_optimize to 2 to avoid inserting an undesired
6313 hold_mips_optimize = mips_optimize;
6315 /* Itbl support may require additional care here. */
6316 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6317 coproc ? treg : treg + 1,
6318 (int) BFD_RELOC_LO16, AT);
6319 mips_optimize = hold_mips_optimize;
6321 (void) frag_var (rs_machine_dependent, 0, 0,
6322 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6323 offset_expr.X_add_symbol, 0, NULL);
6325 else if (mips_pic == SVR4_PIC)
6330 /* If this is a reference to an external symbol, we want
6331 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6333 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6338 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6340 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6341 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6342 If there is a base register we add it to $at before the
6343 lwc1 instructions. If there is a constant we include it
6344 in the lwc1 instructions. */
6346 expr1.X_add_number = offset_expr.X_add_number;
6347 offset_expr.X_add_number = 0;
6348 if (expr1.X_add_number < -0x8000
6349 || expr1.X_add_number >= 0x8000 - 4)
6350 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6351 if (reg_needs_delay (mips_gp_register))
6360 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6361 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6362 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6363 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6364 "d,v,t", AT, AT, mips_gp_register);
6365 macro_build ((char *) NULL, &icnt, &offset_expr,
6366 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6367 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6370 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6371 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6372 "d,v,t", AT, breg, AT);
6373 /* Itbl support may require additional care here. */
6374 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6375 coproc ? treg + 1 : treg,
6376 (int) BFD_RELOC_LO16, AT);
6377 expr1.X_add_number += 4;
6379 /* Set mips_optimize to 2 to avoid inserting an undesired
6381 hold_mips_optimize = mips_optimize;
6383 /* Itbl support may require additional care here. */
6384 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6385 coproc ? treg : treg + 1,
6386 (int) BFD_RELOC_LO16, AT);
6387 mips_optimize = hold_mips_optimize;
6388 expr1.X_add_number -= 4;
6390 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6391 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6392 8 + gpdel + off, 1, 0),
6393 offset_expr.X_add_symbol, 0, NULL);
6396 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6399 macro_build (p, &icnt, &offset_expr,
6400 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6401 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6404 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6408 macro_build (p, &icnt, (expressionS *) NULL,
6409 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6410 "d,v,t", AT, breg, AT);
6413 /* Itbl support may require additional care here. */
6414 macro_build (p, &icnt, &expr1, s, fmt,
6415 coproc ? treg + 1 : treg,
6416 (int) BFD_RELOC_LO16, AT);
6418 expr1.X_add_number += 4;
6420 /* Set mips_optimize to 2 to avoid inserting an undesired
6422 hold_mips_optimize = mips_optimize;
6424 /* Itbl support may require additional care here. */
6425 macro_build (p, &icnt, &expr1, s, fmt,
6426 coproc ? treg : treg + 1,
6427 (int) BFD_RELOC_LO16, AT);
6428 mips_optimize = hold_mips_optimize;
6430 else if (mips_pic == EMBEDDED_PIC)
6432 /* If there is no base register, we use
6433 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6434 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6435 If we have a base register, we use
6437 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6438 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6442 tempreg = mips_gp_register;
6447 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6448 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6449 "d,v,t", AT, breg, mips_gp_register);
6454 /* Itbl support may require additional care here. */
6455 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6456 coproc ? treg + 1 : treg,
6457 (int) BFD_RELOC_GPREL16, tempreg);
6458 offset_expr.X_add_number += 4;
6459 /* Itbl support may require additional care here. */
6460 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6461 coproc ? treg : treg + 1,
6462 (int) BFD_RELOC_GPREL16, tempreg);
6478 assert (HAVE_32BIT_ADDRESSES);
6479 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6480 (int) BFD_RELOC_LO16, breg);
6481 offset_expr.X_add_number += 4;
6482 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6483 (int) BFD_RELOC_LO16, breg);
6486 /* New code added to support COPZ instructions.
6487 This code builds table entries out of the macros in mip_opcodes.
6488 R4000 uses interlocks to handle coproc delays.
6489 Other chips (like the R3000) require nops to be inserted for delays.
6491 FIXME: Currently, we require that the user handle delays.
6492 In order to fill delay slots for non-interlocked chips,
6493 we must have a way to specify delays based on the coprocessor.
6494 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6495 What are the side-effects of the cop instruction?
6496 What cache support might we have and what are its effects?
6497 Both coprocessor & memory require delays. how long???
6498 What registers are read/set/modified?
6500 If an itbl is provided to interpret cop instructions,
6501 this knowledge can be encoded in the itbl spec. */
6515 /* For now we just do C (same as Cz). The parameter will be
6516 stored in insn_opcode by mips_ip. */
6517 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6522 move_register (&icnt, dreg, sreg);
6525 #ifdef LOSING_COMPILER
6527 /* Try and see if this is a new itbl instruction.
6528 This code builds table entries out of the macros in mip_opcodes.
6529 FIXME: For now we just assemble the expression and pass it's
6530 value along as a 32-bit immediate.
6531 We may want to have the assembler assemble this value,
6532 so that we gain the assembler's knowledge of delay slots,
6534 Would it be more efficient to use mask (id) here? */
6535 if (itbl_have_entries
6536 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6538 s = ip->insn_mo->name;
6540 coproc = ITBL_DECODE_PNUM (immed_expr);;
6541 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6548 as_warn (_("Macro used $at after \".set noat\""));
6553 struct mips_cl_insn *ip;
6555 register int treg, sreg, dreg, breg;
6571 bfd_reloc_code_real_type r;
6574 treg = (ip->insn_opcode >> 16) & 0x1f;
6575 dreg = (ip->insn_opcode >> 11) & 0x1f;
6576 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6577 mask = ip->insn_mo->mask;
6579 expr1.X_op = O_constant;
6580 expr1.X_op_symbol = NULL;
6581 expr1.X_add_symbol = NULL;
6582 expr1.X_add_number = 1;
6586 #endif /* LOSING_COMPILER */
6591 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6592 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6593 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6600 /* The MIPS assembler some times generates shifts and adds. I'm
6601 not trying to be that fancy. GCC should do this for us
6603 load_register (&icnt, AT, &imm_expr, dbl);
6604 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6605 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6606 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6620 mips_emit_delays (true);
6621 ++mips_opts.noreorder;
6622 mips_any_noreorder = 1;
6624 load_register (&icnt, AT, &imm_expr, dbl);
6625 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6626 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6627 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6629 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6630 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6631 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6634 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6635 "s,t,q", dreg, AT, 6);
6638 expr1.X_add_number = 8;
6639 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6646 --mips_opts.noreorder;
6647 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6660 mips_emit_delays (true);
6661 ++mips_opts.noreorder;
6662 mips_any_noreorder = 1;
6664 load_register (&icnt, AT, &imm_expr, dbl);
6665 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6666 dbl ? "dmultu" : "multu",
6667 "s,t", sreg, imm ? AT : treg);
6668 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6670 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6673 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne",
6677 expr1.X_add_number = 8;
6678 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6679 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6681 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6684 --mips_opts.noreorder;
6688 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6689 "d,v,t", AT, 0, treg);
6690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6691 "d,t,s", AT, sreg, AT);
6692 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6693 "d,t,s", dreg, sreg, treg);
6694 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6695 "d,v,t", dreg, dreg, AT);
6699 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6700 "d,v,t", AT, 0, treg);
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6702 "d,t,s", AT, sreg, AT);
6703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6704 "d,t,s", dreg, sreg, treg);
6705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6706 "d,v,t", dreg, dreg, AT);
6713 if (imm_expr.X_op != O_constant)
6714 as_bad (_("rotate count too large"));
6715 rot = imm_expr.X_add_number & 0x3f;
6717 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6718 "d,w,<", dreg, sreg, 0);
6723 l = (rot < 0x20) ? "dsll" : "dsll32";
6724 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6726 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6727 "d,w,<", AT, sreg, rot);
6728 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6729 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6730 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6731 "d,v,t", dreg, dreg, AT);
6740 if (imm_expr.X_op != O_constant)
6741 as_bad (_("rotate count too large"));
6742 rot = imm_expr.X_add_number & 0x1f;
6744 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6745 "d,w,<", dreg, sreg, 0);
6748 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6749 "d,w,<", AT, sreg, rot);
6750 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6751 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6752 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6753 "d,v,t", dreg, dreg, AT);
6759 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6760 "d,v,t", AT, 0, treg);
6761 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6762 "d,t,s", AT, sreg, AT);
6763 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6764 "d,t,s", dreg, sreg, treg);
6765 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6766 "d,v,t", dreg, dreg, AT);
6770 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6771 "d,v,t", AT, 0, treg);
6772 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6773 "d,t,s", AT, sreg, AT);
6774 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6775 "d,t,s", dreg, sreg, treg);
6776 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6777 "d,v,t", dreg, dreg, AT);
6784 if (imm_expr.X_op != O_constant)
6785 as_bad (_("rotate count too large"));
6786 rot = imm_expr.X_add_number & 0x3f;
6788 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
6789 "d,w,<", dreg, sreg, 0);
6794 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6795 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6797 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6798 "d,w,<", AT, sreg, rot);
6799 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6800 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6801 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6802 "d,v,t", dreg, dreg, AT);
6811 if (imm_expr.X_op != O_constant)
6812 as_bad (_("rotate count too large"));
6813 rot = imm_expr.X_add_number & 0x1f;
6815 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6816 "d,w,<", dreg, sreg, 0);
6819 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6820 "d,w,<", AT, sreg, rot);
6821 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6822 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6823 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6824 "d,v,t", dreg, dreg, AT);
6830 if (mips_arch == CPU_R4650)
6832 as_bad (_("opcode not supported on this processor"));
6835 assert (mips_opts.isa == ISA_MIPS1);
6836 /* Even on a big endian machine $fn comes before $fn+1. We have
6837 to adjust when storing to memory. */
6838 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6839 target_big_endian ? treg + 1 : treg,
6840 (int) BFD_RELOC_LO16, breg);
6841 offset_expr.X_add_number += 4;
6842 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6843 target_big_endian ? treg : treg + 1,
6844 (int) BFD_RELOC_LO16, breg);
6849 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6850 treg, (int) BFD_RELOC_LO16);
6852 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6853 sreg, (int) BFD_RELOC_LO16);
6856 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6857 "d,v,t", dreg, sreg, treg);
6858 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6859 dreg, (int) BFD_RELOC_LO16);
6864 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6866 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6867 sreg, (int) BFD_RELOC_LO16);
6872 as_warn (_("Instruction %s: result is always false"),
6874 move_register (&icnt, dreg, 0);
6877 if (imm_expr.X_op == O_constant
6878 && imm_expr.X_add_number >= 0
6879 && imm_expr.X_add_number < 0x10000)
6881 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6882 sreg, (int) BFD_RELOC_LO16);
6885 else if (imm_expr.X_op == O_constant
6886 && imm_expr.X_add_number > -0x8000
6887 && imm_expr.X_add_number < 0)
6889 imm_expr.X_add_number = -imm_expr.X_add_number;
6890 macro_build ((char *) NULL, &icnt, &imm_expr,
6891 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6892 "t,r,j", dreg, sreg,
6893 (int) BFD_RELOC_LO16);
6898 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6899 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6900 "d,v,t", dreg, sreg, AT);
6903 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6904 (int) BFD_RELOC_LO16);
6909 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6915 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6917 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6918 (int) BFD_RELOC_LO16);
6921 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6923 if (imm_expr.X_op == O_constant
6924 && imm_expr.X_add_number >= -0x8000
6925 && imm_expr.X_add_number < 0x8000)
6927 macro_build ((char *) NULL, &icnt, &imm_expr,
6928 mask == M_SGE_I ? "slti" : "sltiu",
6929 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6934 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6935 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6936 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6940 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6941 (int) BFD_RELOC_LO16);
6946 case M_SGT: /* sreg > treg <==> treg < sreg */
6952 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6956 case M_SGT_I: /* sreg > I <==> I < sreg */
6962 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6963 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6967 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6973 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6975 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6976 (int) BFD_RELOC_LO16);
6979 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6985 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6986 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6988 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6989 (int) BFD_RELOC_LO16);
6993 if (imm_expr.X_op == O_constant
6994 && imm_expr.X_add_number >= -0x8000
6995 && imm_expr.X_add_number < 0x8000)
6997 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6998 dreg, sreg, (int) BFD_RELOC_LO16);
7001 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7002 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
7007 if (imm_expr.X_op == O_constant
7008 && imm_expr.X_add_number >= -0x8000
7009 && imm_expr.X_add_number < 0x8000)
7011 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
7012 dreg, sreg, (int) BFD_RELOC_LO16);
7015 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7016 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7017 "d,v,t", dreg, sreg, AT);
7022 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7023 "d,v,t", dreg, 0, treg);
7025 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7026 "d,v,t", dreg, 0, sreg);
7029 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7030 "d,v,t", dreg, sreg, treg);
7031 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7032 "d,v,t", dreg, 0, dreg);
7037 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7039 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7040 "d,v,t", dreg, 0, sreg);
7045 as_warn (_("Instruction %s: result is always true"),
7047 macro_build ((char *) NULL, &icnt, &expr1,
7048 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7049 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
7052 if (imm_expr.X_op == O_constant
7053 && imm_expr.X_add_number >= 0
7054 && imm_expr.X_add_number < 0x10000)
7056 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
7057 dreg, sreg, (int) BFD_RELOC_LO16);
7060 else if (imm_expr.X_op == O_constant
7061 && imm_expr.X_add_number > -0x8000
7062 && imm_expr.X_add_number < 0)
7064 imm_expr.X_add_number = -imm_expr.X_add_number;
7065 macro_build ((char *) NULL, &icnt, &imm_expr,
7066 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7067 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7072 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7073 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
7074 "d,v,t", dreg, sreg, AT);
7077 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
7078 "d,v,t", dreg, 0, dreg);
7086 if (imm_expr.X_op == O_constant
7087 && imm_expr.X_add_number > -0x8000
7088 && imm_expr.X_add_number <= 0x8000)
7090 imm_expr.X_add_number = -imm_expr.X_add_number;
7091 macro_build ((char *) NULL, &icnt, &imm_expr,
7092 dbl ? "daddi" : "addi",
7093 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7096 load_register (&icnt, AT, &imm_expr, dbl);
7097 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7098 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7104 if (imm_expr.X_op == O_constant
7105 && imm_expr.X_add_number > -0x8000
7106 && imm_expr.X_add_number <= 0x8000)
7108 imm_expr.X_add_number = -imm_expr.X_add_number;
7109 macro_build ((char *) NULL, &icnt, &imm_expr,
7110 dbl ? "daddiu" : "addiu",
7111 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7114 load_register (&icnt, AT, &imm_expr, dbl);
7115 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7116 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7137 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7138 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7144 assert (mips_opts.isa == ISA_MIPS1);
7145 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7146 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7149 * Is the double cfc1 instruction a bug in the mips assembler;
7150 * or is there a reason for it?
7152 mips_emit_delays (true);
7153 ++mips_opts.noreorder;
7154 mips_any_noreorder = 1;
7155 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7157 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7159 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7160 expr1.X_add_number = 3;
7161 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7162 (int) BFD_RELOC_LO16);
7163 expr1.X_add_number = 2;
7164 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7165 (int) BFD_RELOC_LO16);
7166 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7168 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7169 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7170 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7171 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7173 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7174 --mips_opts.noreorder;
7183 if (offset_expr.X_add_number >= 0x7fff)
7184 as_bad (_("operand overflow"));
7185 /* avoid load delay */
7186 if (! target_big_endian)
7187 ++offset_expr.X_add_number;
7188 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7189 (int) BFD_RELOC_LO16, breg);
7190 if (! target_big_endian)
7191 --offset_expr.X_add_number;
7193 ++offset_expr.X_add_number;
7194 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7195 (int) BFD_RELOC_LO16, breg);
7196 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7198 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7212 if (offset_expr.X_add_number >= 0x8000 - off)
7213 as_bad (_("operand overflow"));
7214 if (! target_big_endian)
7215 offset_expr.X_add_number += off;
7216 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7217 (int) BFD_RELOC_LO16, breg);
7218 if (! target_big_endian)
7219 offset_expr.X_add_number -= off;
7221 offset_expr.X_add_number += off;
7222 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7223 (int) BFD_RELOC_LO16, breg);
7237 load_address (&icnt, AT, &offset_expr, &used_at);
7239 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7240 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7241 "d,v,t", AT, AT, breg);
7242 if (! target_big_endian)
7243 expr1.X_add_number = off;
7245 expr1.X_add_number = 0;
7246 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7247 (int) BFD_RELOC_LO16, AT);
7248 if (! target_big_endian)
7249 expr1.X_add_number = 0;
7251 expr1.X_add_number = off;
7252 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7253 (int) BFD_RELOC_LO16, AT);
7259 load_address (&icnt, AT, &offset_expr, &used_at);
7261 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7262 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7263 "d,v,t", AT, AT, breg);
7264 if (target_big_endian)
7265 expr1.X_add_number = 0;
7266 macro_build ((char *) NULL, &icnt, &expr1,
7267 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7268 (int) BFD_RELOC_LO16, AT);
7269 if (target_big_endian)
7270 expr1.X_add_number = 1;
7272 expr1.X_add_number = 0;
7273 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7274 (int) BFD_RELOC_LO16, AT);
7275 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7277 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7282 if (offset_expr.X_add_number >= 0x7fff)
7283 as_bad (_("operand overflow"));
7284 if (target_big_endian)
7285 ++offset_expr.X_add_number;
7286 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7287 (int) BFD_RELOC_LO16, breg);
7288 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7290 if (target_big_endian)
7291 --offset_expr.X_add_number;
7293 ++offset_expr.X_add_number;
7294 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7295 (int) BFD_RELOC_LO16, breg);
7308 if (offset_expr.X_add_number >= 0x8000 - off)
7309 as_bad (_("operand overflow"));
7310 if (! target_big_endian)
7311 offset_expr.X_add_number += off;
7312 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7313 (int) BFD_RELOC_LO16, breg);
7314 if (! target_big_endian)
7315 offset_expr.X_add_number -= off;
7317 offset_expr.X_add_number += off;
7318 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7319 (int) BFD_RELOC_LO16, breg);
7333 load_address (&icnt, AT, &offset_expr, &used_at);
7335 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7336 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7337 "d,v,t", AT, AT, breg);
7338 if (! target_big_endian)
7339 expr1.X_add_number = off;
7341 expr1.X_add_number = 0;
7342 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7343 (int) BFD_RELOC_LO16, AT);
7344 if (! target_big_endian)
7345 expr1.X_add_number = 0;
7347 expr1.X_add_number = off;
7348 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7349 (int) BFD_RELOC_LO16, AT);
7354 load_address (&icnt, AT, &offset_expr, &used_at);
7356 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7357 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7358 "d,v,t", AT, AT, breg);
7359 if (! target_big_endian)
7360 expr1.X_add_number = 0;
7361 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7362 (int) BFD_RELOC_LO16, AT);
7363 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7365 if (! target_big_endian)
7366 expr1.X_add_number = 1;
7368 expr1.X_add_number = 0;
7369 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7370 (int) BFD_RELOC_LO16, AT);
7371 if (! target_big_endian)
7372 expr1.X_add_number = 0;
7374 expr1.X_add_number = 1;
7375 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7376 (int) BFD_RELOC_LO16, AT);
7377 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7379 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7384 /* FIXME: Check if this is one of the itbl macros, since they
7385 are added dynamically. */
7386 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7390 as_warn (_("Macro used $at after \".set noat\""));
7393 /* Implement macros in mips16 mode. */
7397 struct mips_cl_insn *ip;
7400 int xreg, yreg, zreg, tmp;
7404 const char *s, *s2, *s3;
7406 mask = ip->insn_mo->mask;
7408 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7409 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7410 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7414 expr1.X_op = O_constant;
7415 expr1.X_op_symbol = NULL;
7416 expr1.X_add_symbol = NULL;
7417 expr1.X_add_number = 1;
7436 mips_emit_delays (true);
7437 ++mips_opts.noreorder;
7438 mips_any_noreorder = 1;
7439 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7440 dbl ? "ddiv" : "div",
7441 "0,x,y", xreg, yreg);
7442 expr1.X_add_number = 2;
7443 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7444 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7447 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7448 since that causes an overflow. We should do that as well,
7449 but I don't see how to do the comparisons without a temporary
7451 --mips_opts.noreorder;
7452 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7471 mips_emit_delays (true);
7472 ++mips_opts.noreorder;
7473 mips_any_noreorder = 1;
7474 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7476 expr1.X_add_number = 2;
7477 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7478 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7480 --mips_opts.noreorder;
7481 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7487 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7488 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7489 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7498 if (imm_expr.X_op != O_constant)
7499 as_bad (_("Unsupported large constant"));
7500 imm_expr.X_add_number = -imm_expr.X_add_number;
7501 macro_build ((char *) NULL, &icnt, &imm_expr,
7502 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7506 if (imm_expr.X_op != O_constant)
7507 as_bad (_("Unsupported large constant"));
7508 imm_expr.X_add_number = -imm_expr.X_add_number;
7509 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7514 if (imm_expr.X_op != O_constant)
7515 as_bad (_("Unsupported large constant"));
7516 imm_expr.X_add_number = -imm_expr.X_add_number;
7517 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7540 goto do_reverse_branch;
7544 goto do_reverse_branch;
7556 goto do_reverse_branch;
7567 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7569 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7596 goto do_addone_branch_i;
7601 goto do_addone_branch_i;
7616 goto do_addone_branch_i;
7623 if (imm_expr.X_op != O_constant)
7624 as_bad (_("Unsupported large constant"));
7625 ++imm_expr.X_add_number;
7628 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7629 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7633 expr1.X_add_number = 0;
7634 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7636 move_register (&icnt, xreg, yreg);
7637 expr1.X_add_number = 2;
7638 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7640 "neg", "x,w", xreg, xreg);
7644 /* For consistency checking, verify that all bits are specified either
7645 by the match/mask part of the instruction definition, or by the
7648 validate_mips_insn (opc)
7649 const struct mips_opcode *opc;
7651 const char *p = opc->args;
7653 unsigned long used_bits = opc->mask;
7655 if ((used_bits & opc->match) != opc->match)
7657 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7658 opc->name, opc->args);
7661 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7668 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7669 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7671 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7672 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7673 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7674 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7676 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7677 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7679 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7681 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7682 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7683 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7684 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7685 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7686 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7687 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7688 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7689 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7690 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7691 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7692 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7693 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7694 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7695 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7696 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7697 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7699 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7700 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7701 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7702 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7704 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7705 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7706 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7707 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7708 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7709 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7710 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7711 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7712 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7715 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7716 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7717 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7719 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7720 c, opc->name, opc->args);
7724 if (used_bits != 0xffffffff)
7726 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7727 ~used_bits & 0xffffffff, opc->name, opc->args);
7733 /* This routine assembles an instruction into its binary format. As a
7734 side effect, it sets one of the global variables imm_reloc or
7735 offset_reloc to the type of relocation to do if one of the operands
7736 is an address expression. */
7741 struct mips_cl_insn *ip;
7746 struct mips_opcode *insn;
7749 unsigned int lastregno = 0;
7755 /* If the instruction contains a '.', we first try to match an instruction
7756 including the '.'. Then we try again without the '.'. */
7758 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7761 /* If we stopped on whitespace, then replace the whitespace with null for
7762 the call to hash_find. Save the character we replaced just in case we
7763 have to re-parse the instruction. */
7770 insn = (struct mips_opcode *) hash_find (op_hash, str);
7772 /* If we didn't find the instruction in the opcode table, try again, but
7773 this time with just the instruction up to, but not including the
7777 /* Restore the character we overwrite above (if any). */
7781 /* Scan up to the first '.' or whitespace. */
7783 *s != '\0' && *s != '.' && !ISSPACE (*s);
7787 /* If we did not find a '.', then we can quit now. */
7790 insn_error = "unrecognized opcode";
7794 /* Lookup the instruction in the hash table. */
7796 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7798 insn_error = "unrecognized opcode";
7808 assert (strcmp (insn->name, str) == 0);
7810 if (OPCODE_IS_MEMBER (insn,
7812 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
7813 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7814 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7820 if (insn->pinfo != INSN_MACRO)
7822 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7828 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7829 && strcmp (insn->name, insn[1].name) == 0)
7838 static char buf[100];
7839 if (mips_arch_info->is_isa)
7841 _("opcode not supported at this ISA level (%s)"),
7842 mips_cpu_info_from_isa (mips_opts.isa)->name);
7845 _("opcode not supported on this processor: %s (%s)"),
7846 mips_arch_info->name,
7847 mips_cpu_info_from_isa (mips_opts.isa)->name);
7857 ip->insn_opcode = insn->match;
7859 for (args = insn->args;; ++args)
7863 s += strspn (s, " \t");
7867 case '\0': /* end of args */
7880 ip->insn_opcode |= lastregno << OP_SH_RS;
7884 ip->insn_opcode |= lastregno << OP_SH_RT;
7888 ip->insn_opcode |= lastregno << OP_SH_FT;
7892 ip->insn_opcode |= lastregno << OP_SH_FS;
7898 /* Handle optional base register.
7899 Either the base register is omitted or
7900 we must have a left paren. */
7901 /* This is dependent on the next operand specifier
7902 is a base register specification. */
7903 assert (args[1] == 'b' || args[1] == '5'
7904 || args[1] == '-' || args[1] == '4');
7908 case ')': /* these must match exactly */
7913 case '<': /* must be at least one digit */
7915 * According to the manual, if the shift amount is greater
7916 * than 31 or less than 0, then the shift amount should be
7917 * mod 32. In reality the mips assembler issues an error.
7918 * We issue a warning and mask out all but the low 5 bits.
7920 my_getExpression (&imm_expr, s);
7921 check_absolute_expr (ip, &imm_expr);
7922 if ((unsigned long) imm_expr.X_add_number > 31)
7924 as_warn (_("Improper shift amount (%lu)"),
7925 (unsigned long) imm_expr.X_add_number);
7926 imm_expr.X_add_number &= OP_MASK_SHAMT;
7928 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7929 imm_expr.X_op = O_absent;
7933 case '>': /* shift amount minus 32 */
7934 my_getExpression (&imm_expr, s);
7935 check_absolute_expr (ip, &imm_expr);
7936 if ((unsigned long) imm_expr.X_add_number < 32
7937 || (unsigned long) imm_expr.X_add_number > 63)
7939 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7940 imm_expr.X_op = O_absent;
7944 case 'k': /* cache code */
7945 case 'h': /* prefx code */
7946 my_getExpression (&imm_expr, s);
7947 check_absolute_expr (ip, &imm_expr);
7948 if ((unsigned long) imm_expr.X_add_number > 31)
7950 as_warn (_("Invalid value for `%s' (%lu)"),
7952 (unsigned long) imm_expr.X_add_number);
7953 imm_expr.X_add_number &= 0x1f;
7956 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7958 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7959 imm_expr.X_op = O_absent;
7963 case 'c': /* break code */
7964 my_getExpression (&imm_expr, s);
7965 check_absolute_expr (ip, &imm_expr);
7966 if ((unsigned long) imm_expr.X_add_number > 1023)
7968 as_warn (_("Illegal break code (%lu)"),
7969 (unsigned long) imm_expr.X_add_number);
7970 imm_expr.X_add_number &= OP_MASK_CODE;
7972 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7973 imm_expr.X_op = O_absent;
7977 case 'q': /* lower break code */
7978 my_getExpression (&imm_expr, s);
7979 check_absolute_expr (ip, &imm_expr);
7980 if ((unsigned long) imm_expr.X_add_number > 1023)
7982 as_warn (_("Illegal lower break code (%lu)"),
7983 (unsigned long) imm_expr.X_add_number);
7984 imm_expr.X_add_number &= OP_MASK_CODE2;
7986 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7987 imm_expr.X_op = O_absent;
7991 case 'B': /* 20-bit syscall/break code. */
7992 my_getExpression (&imm_expr, s);
7993 check_absolute_expr (ip, &imm_expr);
7994 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7995 as_warn (_("Illegal 20-bit code (%lu)"),
7996 (unsigned long) imm_expr.X_add_number);
7997 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7998 imm_expr.X_op = O_absent;
8002 case 'C': /* Coprocessor code */
8003 my_getExpression (&imm_expr, s);
8004 check_absolute_expr (ip, &imm_expr);
8005 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8007 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8008 (unsigned long) imm_expr.X_add_number);
8009 imm_expr.X_add_number &= ((1 << 25) - 1);
8011 ip->insn_opcode |= imm_expr.X_add_number;
8012 imm_expr.X_op = O_absent;
8016 case 'J': /* 19-bit wait code. */
8017 my_getExpression (&imm_expr, s);
8018 check_absolute_expr (ip, &imm_expr);
8019 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8020 as_warn (_("Illegal 19-bit code (%lu)"),
8021 (unsigned long) imm_expr.X_add_number);
8022 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8023 imm_expr.X_op = O_absent;
8027 case 'P': /* Performance register */
8028 my_getExpression (&imm_expr, s);
8029 check_absolute_expr (ip, &imm_expr);
8030 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8032 as_warn (_("Invalid performance register (%lu)"),
8033 (unsigned long) imm_expr.X_add_number);
8034 imm_expr.X_add_number &= OP_MASK_PERFREG;
8036 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8037 imm_expr.X_op = O_absent;
8041 case 'b': /* base register */
8042 case 'd': /* destination register */
8043 case 's': /* source register */
8044 case 't': /* target register */
8045 case 'r': /* both target and source */
8046 case 'v': /* both dest and source */
8047 case 'w': /* both dest and target */
8048 case 'E': /* coprocessor target register */
8049 case 'G': /* coprocessor destination register */
8050 case 'x': /* ignore register name */
8051 case 'z': /* must be zero register */
8052 case 'U': /* destination register (clo/clz). */
8067 while (ISDIGIT (*s));
8069 as_bad (_("Invalid register number (%d)"), regno);
8071 else if (*args == 'E' || *args == 'G')
8075 if (s[1] == 'r' && s[2] == 'a')
8080 else if (s[1] == 'f' && s[2] == 'p')
8085 else if (s[1] == 's' && s[2] == 'p')
8090 else if (s[1] == 'g' && s[2] == 'p')
8095 else if (s[1] == 'a' && s[2] == 't')
8100 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8105 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8110 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8115 else if (itbl_have_entries)
8120 p = s + 1; /* advance past '$' */
8121 n = itbl_get_field (&p); /* n is name */
8123 /* See if this is a register defined in an
8125 if (itbl_get_reg_val (n, &r))
8127 /* Get_field advances to the start of
8128 the next field, so we need to back
8129 rack to the end of the last field. */
8133 s = strchr (s, '\0');
8146 as_warn (_("Used $at without \".set noat\""));
8152 if (c == 'r' || c == 'v' || c == 'w')
8159 /* 'z' only matches $0. */
8160 if (c == 'z' && regno != 0)
8163 /* Now that we have assembled one operand, we use the args string
8164 * to figure out where it goes in the instruction. */
8171 ip->insn_opcode |= regno << OP_SH_RS;
8175 ip->insn_opcode |= regno << OP_SH_RD;
8178 ip->insn_opcode |= regno << OP_SH_RD;
8179 ip->insn_opcode |= regno << OP_SH_RT;
8184 ip->insn_opcode |= regno << OP_SH_RT;
8187 /* This case exists because on the r3000 trunc
8188 expands into a macro which requires a gp
8189 register. On the r6000 or r4000 it is
8190 assembled into a single instruction which
8191 ignores the register. Thus the insn version
8192 is MIPS_ISA2 and uses 'x', and the macro
8193 version is MIPS_ISA1 and uses 't'. */
8196 /* This case is for the div instruction, which
8197 acts differently if the destination argument
8198 is $0. This only matches $0, and is checked
8199 outside the switch. */
8202 /* Itbl operand; not yet implemented. FIXME ?? */
8204 /* What about all other operands like 'i', which
8205 can be specified in the opcode table? */
8215 ip->insn_opcode |= lastregno << OP_SH_RS;
8218 ip->insn_opcode |= lastregno << OP_SH_RT;
8223 case 'O': /* MDMX alignment immediate constant. */
8224 my_getExpression (&imm_expr, s);
8225 check_absolute_expr (ip, &imm_expr);
8226 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8228 as_warn ("Improper align amount (%ld), using low bits",
8229 (long) imm_expr.X_add_number);
8230 imm_expr.X_add_number &= OP_MASK_ALN;
8232 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8233 imm_expr.X_op = O_absent;
8237 case 'Q': /* MDMX vector, element sel, or const. */
8240 /* MDMX Immediate. */
8241 my_getExpression (&imm_expr, s);
8242 check_absolute_expr (ip, &imm_expr);
8243 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8245 as_warn (_("Invalid MDMX Immediate (%ld)"),
8246 (long) imm_expr.X_add_number);
8247 imm_expr.X_add_number &= OP_MASK_FT;
8249 imm_expr.X_add_number &= OP_MASK_FT;
8250 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8251 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8253 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8254 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8255 imm_expr.X_op = O_absent;
8259 /* Not MDMX Immediate. Fall through. */
8260 case 'X': /* MDMX destination register. */
8261 case 'Y': /* MDMX source register. */
8262 case 'Z': /* MDMX target register. */
8264 case 'D': /* floating point destination register */
8265 case 'S': /* floating point source register */
8266 case 'T': /* floating point target register */
8267 case 'R': /* floating point source register */
8271 /* Accept $fN for FP and MDMX register numbers, and in
8272 addition accept $vN for MDMX register numbers. */
8273 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8274 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8285 while (ISDIGIT (*s));
8288 as_bad (_("Invalid float register number (%d)"), regno);
8290 if ((regno & 1) != 0
8292 && ! (strcmp (str, "mtc1") == 0
8293 || strcmp (str, "mfc1") == 0
8294 || strcmp (str, "lwc1") == 0
8295 || strcmp (str, "swc1") == 0
8296 || strcmp (str, "l.s") == 0
8297 || strcmp (str, "s.s") == 0))
8298 as_warn (_("Float register should be even, was %d"),
8306 if (c == 'V' || c == 'W')
8317 ip->insn_opcode |= regno << OP_SH_FD;
8322 ip->insn_opcode |= regno << OP_SH_FS;
8325 /* This is like 'Z', but also needs to fix the MDMX
8326 vector/scalar select bits. Note that the
8327 scalar immediate case is handled above. */
8330 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8331 int max_el = (is_qh ? 3 : 7);
8333 my_getExpression(&imm_expr, s);
8334 check_absolute_expr (ip, &imm_expr);
8336 if (imm_expr.X_add_number > max_el)
8337 as_bad(_("Bad element selector %ld"),
8338 (long) imm_expr.X_add_number);
8339 imm_expr.X_add_number &= max_el;
8340 ip->insn_opcode |= (imm_expr.X_add_number
8344 as_warn(_("Expecting ']' found '%s'"), s);
8350 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8351 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8354 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8361 ip->insn_opcode |= regno << OP_SH_FT;
8364 ip->insn_opcode |= regno << OP_SH_FR;
8374 ip->insn_opcode |= lastregno << OP_SH_FS;
8377 ip->insn_opcode |= lastregno << OP_SH_FT;
8383 my_getExpression (&imm_expr, s);
8384 if (imm_expr.X_op != O_big
8385 && imm_expr.X_op != O_constant)
8386 insn_error = _("absolute expression required");
8391 my_getExpression (&offset_expr, s);
8392 *imm_reloc = BFD_RELOC_32;
8405 unsigned char temp[8];
8407 unsigned int length;
8412 /* These only appear as the last operand in an
8413 instruction, and every instruction that accepts
8414 them in any variant accepts them in all variants.
8415 This means we don't have to worry about backing out
8416 any changes if the instruction does not match.
8418 The difference between them is the size of the
8419 floating point constant and where it goes. For 'F'
8420 and 'L' the constant is 64 bits; for 'f' and 'l' it
8421 is 32 bits. Where the constant is placed is based
8422 on how the MIPS assembler does things:
8425 f -- immediate value
8428 The .lit4 and .lit8 sections are only used if
8429 permitted by the -G argument.
8431 When generating embedded PIC code, we use the
8432 .lit8 section but not the .lit4 section (we can do
8433 .lit4 inline easily; we need to put .lit8
8434 somewhere in the data segment, and using .lit8
8435 permits the linker to eventually combine identical
8438 The code below needs to know whether the target register
8439 is 32 or 64 bits wide. It relies on the fact 'f' and
8440 'F' are used with GPR-based instructions and 'l' and
8441 'L' are used with FPR-based instructions. */
8443 f64 = *args == 'F' || *args == 'L';
8444 using_gprs = *args == 'F' || *args == 'f';
8446 save_in = input_line_pointer;
8447 input_line_pointer = s;
8448 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8450 s = input_line_pointer;
8451 input_line_pointer = save_in;
8452 if (err != NULL && *err != '\0')
8454 as_bad (_("Bad floating point constant: %s"), err);
8455 memset (temp, '\0', sizeof temp);
8456 length = f64 ? 8 : 4;
8459 assert (length == (unsigned) (f64 ? 8 : 4));
8463 && (! USE_GLOBAL_POINTER_OPT
8464 || mips_pic == EMBEDDED_PIC
8465 || g_switch_value < 4
8466 || (temp[0] == 0 && temp[1] == 0)
8467 || (temp[2] == 0 && temp[3] == 0))))
8469 imm_expr.X_op = O_constant;
8470 if (! target_big_endian)
8471 imm_expr.X_add_number = bfd_getl32 (temp);
8473 imm_expr.X_add_number = bfd_getb32 (temp);
8476 && ! mips_disable_float_construction
8477 /* Constants can only be constructed in GPRs and
8478 copied to FPRs if the GPRs are at least as wide
8479 as the FPRs. Force the constant into memory if
8480 we are using 64-bit FPRs but the GPRs are only
8483 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8484 && ((temp[0] == 0 && temp[1] == 0)
8485 || (temp[2] == 0 && temp[3] == 0))
8486 && ((temp[4] == 0 && temp[5] == 0)
8487 || (temp[6] == 0 && temp[7] == 0)))
8489 /* The value is simple enough to load with a couple of
8490 instructions. If using 32-bit registers, set
8491 imm_expr to the high order 32 bits and offset_expr to
8492 the low order 32 bits. Otherwise, set imm_expr to
8493 the entire 64 bit constant. */
8494 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8496 imm_expr.X_op = O_constant;
8497 offset_expr.X_op = O_constant;
8498 if (! target_big_endian)
8500 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8501 offset_expr.X_add_number = bfd_getl32 (temp);
8505 imm_expr.X_add_number = bfd_getb32 (temp);
8506 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8508 if (offset_expr.X_add_number == 0)
8509 offset_expr.X_op = O_absent;
8511 else if (sizeof (imm_expr.X_add_number) > 4)
8513 imm_expr.X_op = O_constant;
8514 if (! target_big_endian)
8515 imm_expr.X_add_number = bfd_getl64 (temp);
8517 imm_expr.X_add_number = bfd_getb64 (temp);
8521 imm_expr.X_op = O_big;
8522 imm_expr.X_add_number = 4;
8523 if (! target_big_endian)
8525 generic_bignum[0] = bfd_getl16 (temp);
8526 generic_bignum[1] = bfd_getl16 (temp + 2);
8527 generic_bignum[2] = bfd_getl16 (temp + 4);
8528 generic_bignum[3] = bfd_getl16 (temp + 6);
8532 generic_bignum[0] = bfd_getb16 (temp + 6);
8533 generic_bignum[1] = bfd_getb16 (temp + 4);
8534 generic_bignum[2] = bfd_getb16 (temp + 2);
8535 generic_bignum[3] = bfd_getb16 (temp);
8541 const char *newname;
8544 /* Switch to the right section. */
8546 subseg = now_subseg;
8549 default: /* unused default case avoids warnings. */
8551 newname = RDATA_SECTION_NAME;
8552 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8553 || mips_pic == EMBEDDED_PIC)
8557 if (mips_pic == EMBEDDED_PIC)
8560 newname = RDATA_SECTION_NAME;
8563 assert (!USE_GLOBAL_POINTER_OPT
8564 || g_switch_value >= 4);
8568 new_seg = subseg_new (newname, (subsegT) 0);
8569 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8570 bfd_set_section_flags (stdoutput, new_seg,
8575 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8576 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8577 && strcmp (TARGET_OS, "elf") != 0)
8578 record_alignment (new_seg, 4);
8580 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8582 as_bad (_("Can't use floating point insn in this section"));
8584 /* Set the argument to the current address in the
8586 offset_expr.X_op = O_symbol;
8587 offset_expr.X_add_symbol =
8588 symbol_new ("L0\001", now_seg,
8589 (valueT) frag_now_fix (), frag_now);
8590 offset_expr.X_add_number = 0;
8592 /* Put the floating point number into the section. */
8593 p = frag_more ((int) length);
8594 memcpy (p, temp, length);
8596 /* Switch back to the original section. */
8597 subseg_set (seg, subseg);
8602 case 'i': /* 16 bit unsigned immediate */
8603 case 'j': /* 16 bit signed immediate */
8604 *imm_reloc = BFD_RELOC_LO16;
8605 c = my_getSmallExpression (&imm_expr, s);
8612 *imm_reloc = BFD_RELOC_HI16_S;
8613 imm_unmatched_hi = true;
8616 else if (c == S_EX_HIGHEST)
8617 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8618 else if (c == S_EX_HIGHER)
8619 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8620 else if (c == S_EX_GP_REL)
8622 /* This occurs in NewABI only. */
8623 c = my_getSmallExpression (&imm_expr, s);
8625 as_bad (_("bad composition of relocations"));
8628 c = my_getSmallExpression (&imm_expr, s);
8630 as_bad (_("bad composition of relocations"));
8633 imm_reloc[0] = BFD_RELOC_GPREL16;
8634 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8635 imm_reloc[2] = BFD_RELOC_LO16;
8641 *imm_reloc = BFD_RELOC_HI16;
8643 else if (imm_expr.X_op == O_constant)
8644 imm_expr.X_add_number &= 0xffff;
8648 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8649 || ((imm_expr.X_add_number < 0
8650 || imm_expr.X_add_number >= 0x10000)
8651 && imm_expr.X_op == O_constant))
8653 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8654 !strcmp (insn->name, insn[1].name))
8656 if (imm_expr.X_op == O_constant
8657 || imm_expr.X_op == O_big)
8658 as_bad (_("16 bit expression not in range 0..65535"));
8666 /* The upper bound should be 0x8000, but
8667 unfortunately the MIPS assembler accepts numbers
8668 from 0x8000 to 0xffff and sign extends them, and
8669 we want to be compatible. We only permit this
8670 extended range for an instruction which does not
8671 provide any further alternates, since those
8672 alternates may handle other cases. People should
8673 use the numbers they mean, rather than relying on
8674 a mysterious sign extension. */
8675 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8676 strcmp (insn->name, insn[1].name) == 0);
8681 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8682 || ((imm_expr.X_add_number < -0x8000
8683 || imm_expr.X_add_number >= max)
8684 && imm_expr.X_op == O_constant)
8686 && imm_expr.X_add_number < 0
8688 && imm_expr.X_unsigned
8689 && sizeof (imm_expr.X_add_number) <= 4))
8693 if (imm_expr.X_op == O_constant
8694 || imm_expr.X_op == O_big)
8695 as_bad (_("16 bit expression not in range -32768..32767"));
8701 case 'o': /* 16 bit offset */
8702 c = my_getSmallExpression (&offset_expr, s);
8704 /* If this value won't fit into a 16 bit offset, then go
8705 find a macro that will generate the 32 bit offset
8708 && (offset_expr.X_op != O_constant
8709 || offset_expr.X_add_number >= 0x8000
8710 || offset_expr.X_add_number < -0x8000))
8715 if (offset_expr.X_op != O_constant)
8717 offset_expr.X_add_number =
8718 (offset_expr.X_add_number >> 16) & 0xffff;
8720 *offset_reloc = BFD_RELOC_LO16;
8724 case 'p': /* pc relative offset */
8725 if (mips_pic == EMBEDDED_PIC)
8726 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8728 *offset_reloc = BFD_RELOC_16_PCREL;
8729 my_getExpression (&offset_expr, s);
8733 case 'u': /* upper 16 bits */
8734 c = my_getSmallExpression (&imm_expr, s);
8735 *imm_reloc = BFD_RELOC_LO16;
8742 *imm_reloc = BFD_RELOC_HI16_S;
8743 imm_unmatched_hi = true;
8746 else if (c == S_EX_HIGHEST)
8747 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8748 else if (c == S_EX_GP_REL)
8750 /* This occurs in NewABI only. */
8751 c = my_getSmallExpression (&imm_expr, s);
8753 as_bad (_("bad composition of relocations"));
8756 c = my_getSmallExpression (&imm_expr, s);
8758 as_bad (_("bad composition of relocations"));
8761 imm_reloc[0] = BFD_RELOC_GPREL16;
8762 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8763 imm_reloc[2] = BFD_RELOC_HI16_S;
8769 *imm_reloc = BFD_RELOC_HI16;
8771 else if (imm_expr.X_op == O_constant)
8772 imm_expr.X_add_number &= 0xffff;
8774 else if (imm_expr.X_op == O_constant
8775 && (imm_expr.X_add_number < 0
8776 || imm_expr.X_add_number >= 0x10000))
8777 as_bad (_("lui expression not in range 0..65535"));
8781 case 'a': /* 26 bit address */
8782 my_getExpression (&offset_expr, s);
8784 *offset_reloc = BFD_RELOC_MIPS_JMP;
8787 case 'N': /* 3 bit branch condition code */
8788 case 'M': /* 3 bit compare condition code */
8789 if (strncmp (s, "$fcc", 4) != 0)
8799 while (ISDIGIT (*s));
8801 as_bad (_("invalid condition code register $fcc%d"), regno);
8803 ip->insn_opcode |= regno << OP_SH_BCC;
8805 ip->insn_opcode |= regno << OP_SH_CCC;
8809 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8820 while (ISDIGIT (*s));
8823 c = 8; /* Invalid sel value. */
8826 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8827 ip->insn_opcode |= c;
8831 as_bad (_("bad char = '%c'\n"), *args);
8836 /* Args don't match. */
8837 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8838 !strcmp (insn->name, insn[1].name))
8842 insn_error = _("illegal operands");
8847 insn_error = _("illegal operands");
8852 /* This routine assembles an instruction into its binary format when
8853 assembling for the mips16. As a side effect, it sets one of the
8854 global variables imm_reloc or offset_reloc to the type of
8855 relocation to do if one of the operands is an address expression.
8856 It also sets mips16_small and mips16_ext if the user explicitly
8857 requested a small or extended instruction. */
8862 struct mips_cl_insn *ip;
8866 struct mips_opcode *insn;
8869 unsigned int lastregno = 0;
8874 mips16_small = false;
8877 for (s = str; ISLOWER (*s); ++s)
8889 if (s[1] == 't' && s[2] == ' ')
8892 mips16_small = true;
8896 else if (s[1] == 'e' && s[2] == ' ')
8905 insn_error = _("unknown opcode");
8909 if (mips_opts.noautoextend && ! mips16_ext)
8910 mips16_small = true;
8912 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8914 insn_error = _("unrecognized opcode");
8921 assert (strcmp (insn->name, str) == 0);
8924 ip->insn_opcode = insn->match;
8925 ip->use_extend = false;
8926 imm_expr.X_op = O_absent;
8927 imm_reloc[0] = BFD_RELOC_UNUSED;
8928 imm_reloc[1] = BFD_RELOC_UNUSED;
8929 imm_reloc[2] = BFD_RELOC_UNUSED;
8930 offset_expr.X_op = O_absent;
8931 offset_reloc[0] = BFD_RELOC_UNUSED;
8932 offset_reloc[1] = BFD_RELOC_UNUSED;
8933 offset_reloc[2] = BFD_RELOC_UNUSED;
8934 for (args = insn->args; 1; ++args)
8941 /* In this switch statement we call break if we did not find
8942 a match, continue if we did find a match, or return if we
8951 /* Stuff the immediate value in now, if we can. */
8952 if (imm_expr.X_op == O_constant
8953 && *imm_reloc > BFD_RELOC_UNUSED
8954 && insn->pinfo != INSN_MACRO)
8956 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8957 imm_expr.X_add_number, true, mips16_small,
8958 mips16_ext, &ip->insn_opcode,
8959 &ip->use_extend, &ip->extend);
8960 imm_expr.X_op = O_absent;
8961 *imm_reloc = BFD_RELOC_UNUSED;
8975 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8978 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8994 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8996 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9023 while (ISDIGIT (*s));
9026 as_bad (_("invalid register number (%d)"), regno);
9032 if (s[1] == 'r' && s[2] == 'a')
9037 else if (s[1] == 'f' && s[2] == 'p')
9042 else if (s[1] == 's' && s[2] == 'p')
9047 else if (s[1] == 'g' && s[2] == 'p')
9052 else if (s[1] == 'a' && s[2] == 't')
9057 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9062 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9067 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9080 if (c == 'v' || c == 'w')
9082 regno = mips16_to_32_reg_map[lastregno];
9096 regno = mips32_to_16_reg_map[regno];
9101 regno = ILLEGAL_REG;
9106 regno = ILLEGAL_REG;
9111 regno = ILLEGAL_REG;
9116 if (regno == AT && ! mips_opts.noat)
9117 as_warn (_("used $at without \".set noat\""));
9124 if (regno == ILLEGAL_REG)
9131 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9135 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9138 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9141 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9147 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9150 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9151 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9161 if (strncmp (s, "$pc", 3) == 0)
9185 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9187 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9188 and generate the appropriate reloc. If the text
9189 inside %gprel is not a symbol name with an
9190 optional offset, then we generate a normal reloc
9191 and will probably fail later. */
9192 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9193 if (imm_expr.X_op == O_symbol)
9196 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9198 ip->use_extend = true;
9205 /* Just pick up a normal expression. */
9206 my_getExpression (&imm_expr, s);
9209 if (imm_expr.X_op == O_register)
9211 /* What we thought was an expression turned out to
9214 if (s[0] == '(' && args[1] == '(')
9216 /* It looks like the expression was omitted
9217 before a register indirection, which means
9218 that the expression is implicitly zero. We
9219 still set up imm_expr, so that we handle
9220 explicit extensions correctly. */
9221 imm_expr.X_op = O_constant;
9222 imm_expr.X_add_number = 0;
9223 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9230 /* We need to relax this instruction. */
9231 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9240 /* We use offset_reloc rather than imm_reloc for the PC
9241 relative operands. This lets macros with both
9242 immediate and address operands work correctly. */
9243 my_getExpression (&offset_expr, s);
9245 if (offset_expr.X_op == O_register)
9248 /* We need to relax this instruction. */
9249 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9253 case '6': /* break code */
9254 my_getExpression (&imm_expr, s);
9255 check_absolute_expr (ip, &imm_expr);
9256 if ((unsigned long) imm_expr.X_add_number > 63)
9258 as_warn (_("Invalid value for `%s' (%lu)"),
9260 (unsigned long) imm_expr.X_add_number);
9261 imm_expr.X_add_number &= 0x3f;
9263 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9264 imm_expr.X_op = O_absent;
9268 case 'a': /* 26 bit address */
9269 my_getExpression (&offset_expr, s);
9271 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9272 ip->insn_opcode <<= 16;
9275 case 'l': /* register list for entry macro */
9276 case 'L': /* register list for exit macro */
9286 int freg, reg1, reg2;
9288 while (*s == ' ' || *s == ',')
9292 as_bad (_("can't parse register list"));
9304 while (ISDIGIT (*s))
9326 as_bad (_("invalid register list"));
9331 while (ISDIGIT (*s))
9338 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9343 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9348 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9349 mask |= (reg2 - 3) << 3;
9350 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9351 mask |= (reg2 - 15) << 1;
9352 else if (reg1 == RA && reg2 == RA)
9356 as_bad (_("invalid register list"));
9360 /* The mask is filled in in the opcode table for the
9361 benefit of the disassembler. We remove it before
9362 applying the actual mask. */
9363 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9364 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9368 case 'e': /* extend code */
9369 my_getExpression (&imm_expr, s);
9370 check_absolute_expr (ip, &imm_expr);
9371 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9373 as_warn (_("Invalid value for `%s' (%lu)"),
9375 (unsigned long) imm_expr.X_add_number);
9376 imm_expr.X_add_number &= 0x7ff;
9378 ip->insn_opcode |= imm_expr.X_add_number;
9379 imm_expr.X_op = O_absent;
9389 /* Args don't match. */
9390 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9391 strcmp (insn->name, insn[1].name) == 0)
9398 insn_error = _("illegal operands");
9404 /* This structure holds information we know about a mips16 immediate
9407 struct mips16_immed_operand
9409 /* The type code used in the argument string in the opcode table. */
9411 /* The number of bits in the short form of the opcode. */
9413 /* The number of bits in the extended form of the opcode. */
9415 /* The amount by which the short form is shifted when it is used;
9416 for example, the sw instruction has a shift count of 2. */
9418 /* The amount by which the short form is shifted when it is stored
9419 into the instruction code. */
9421 /* Non-zero if the short form is unsigned. */
9423 /* Non-zero if the extended form is unsigned. */
9425 /* Non-zero if the value is PC relative. */
9429 /* The mips16 immediate operand types. */
9431 static const struct mips16_immed_operand mips16_immed_operands[] =
9433 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9434 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9435 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9436 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9437 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9438 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9439 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9440 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9441 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9442 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9443 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9444 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9445 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9446 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9447 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9448 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9449 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9450 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9451 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9452 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9453 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9456 #define MIPS16_NUM_IMMED \
9457 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9459 /* Handle a mips16 instruction with an immediate value. This or's the
9460 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9461 whether an extended value is needed; if one is needed, it sets
9462 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9463 If SMALL is true, an unextended opcode was explicitly requested.
9464 If EXT is true, an extended opcode was explicitly requested. If
9465 WARN is true, warn if EXT does not match reality. */
9468 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9477 unsigned long *insn;
9478 boolean *use_extend;
9479 unsigned short *extend;
9481 register const struct mips16_immed_operand *op;
9482 int mintiny, maxtiny;
9485 op = mips16_immed_operands;
9486 while (op->type != type)
9489 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9494 if (type == '<' || type == '>' || type == '[' || type == ']')
9497 maxtiny = 1 << op->nbits;
9502 maxtiny = (1 << op->nbits) - 1;
9507 mintiny = - (1 << (op->nbits - 1));
9508 maxtiny = (1 << (op->nbits - 1)) - 1;
9511 /* Branch offsets have an implicit 0 in the lowest bit. */
9512 if (type == 'p' || type == 'q')
9515 if ((val & ((1 << op->shift) - 1)) != 0
9516 || val < (mintiny << op->shift)
9517 || val > (maxtiny << op->shift))
9522 if (warn && ext && ! needext)
9523 as_warn_where (file, line,
9524 _("extended operand requested but not required"));
9525 if (small && needext)
9526 as_bad_where (file, line, _("invalid unextended operand value"));
9528 if (small || (! ext && ! needext))
9532 *use_extend = false;
9533 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9534 insnval <<= op->op_shift;
9539 long minext, maxext;
9545 maxext = (1 << op->extbits) - 1;
9549 minext = - (1 << (op->extbits - 1));
9550 maxext = (1 << (op->extbits - 1)) - 1;
9552 if (val < minext || val > maxext)
9553 as_bad_where (file, line,
9554 _("operand value out of range for instruction"));
9557 if (op->extbits == 16)
9559 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9562 else if (op->extbits == 15)
9564 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9569 extval = ((val & 0x1f) << 6) | (val & 0x20);
9573 *extend = (unsigned short) extval;
9578 static struct percent_op_match
9581 const enum small_ex_type type;
9586 {"%call_hi", S_EX_CALL_HI},
9587 {"%call_lo", S_EX_CALL_LO},
9588 {"%call16", S_EX_CALL16},
9589 {"%got_disp", S_EX_GOT_DISP},
9590 {"%got_page", S_EX_GOT_PAGE},
9591 {"%got_ofst", S_EX_GOT_OFST},
9592 {"%got_hi", S_EX_GOT_HI},
9593 {"%got_lo", S_EX_GOT_LO},
9595 {"%gp_rel", S_EX_GP_REL},
9596 {"%half", S_EX_HALF},
9597 {"%highest", S_EX_HIGHEST},
9598 {"%higher", S_EX_HIGHER},
9604 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9605 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9606 can be nested, this is handled by blanking the innermost, parsing the
9607 rest by subsequent calls. */
9610 my_getSmallParser (str, len, nestlevel)
9616 *str += strspn (*str, " \t");
9617 /* Check for expression in parentheses. */
9620 char *b = *str + 1 + strspn (*str + 1, " \t");
9623 /* Check for base register. */
9627 && (e = b + strcspn (b, ") \t"))
9628 && e - b > 1 && e - b < 4)
9631 && ((b[1] == 'f' && b[2] == 'p')
9632 || (b[1] == 's' && b[2] == 'p')
9633 || (b[1] == 'g' && b[2] == 'p')
9634 || (b[1] == 'a' && b[2] == 't')
9636 && ISDIGIT (b[2]))))
9637 || (ISDIGIT (b[1])))
9639 *len = strcspn (*str, ")") + 1;
9640 return S_EX_REGISTER;
9644 /* Check for percent_op (in parentheses). */
9645 else if (b[0] == '%')
9648 return my_getPercentOp (str, len, nestlevel);
9651 /* Some other expression in the parentheses, which can contain
9652 parentheses itself. Attempt to find the matching one. */
9658 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9667 /* Check for percent_op (outside of parentheses). */
9668 else if (*str[0] == '%')
9669 return my_getPercentOp (str, len, nestlevel);
9671 /* Any other expression. */
9676 my_getPercentOp (str, len, nestlevel)
9681 char *tmp = *str + 1;
9684 while (ISALPHA (*tmp) || *tmp == '_')
9686 *tmp = TOLOWER (*tmp);
9689 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9691 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9695 int type = percent_op[i].type;
9697 /* Only %hi and %lo are allowed for OldABI. */
9698 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9701 *len = strlen (percent_op[i].str);
9710 my_getSmallExpression (ep, str)
9714 static char *oldstr = NULL;
9720 /* Don't update oldstr if the last call had nested percent_op's. We need
9721 it to parse the outer ones later. */
9728 c = my_getSmallParser (&str, &len, &nestlevel);
9729 if (c != S_EX_NONE && c != S_EX_REGISTER)
9732 while (c != S_EX_NONE && c != S_EX_REGISTER);
9736 /* A percent_op was encountered. Don't try to get an expression if
9737 it is already blanked out. */
9738 if (*(str + strspn (str + 1, " )")) != ')')
9742 /* Let my_getExpression() stop at the closing parenthesis. */
9743 save = *(str + len);
9744 *(str + len) = '\0';
9745 my_getExpression (ep, str);
9746 *(str + len) = save;
9750 /* Blank out including the % sign and the proper matching
9753 char *s = strrchr (oldstr, '%');
9756 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9760 else if (*end == ')')
9764 memset (s, ' ', end - s);
9768 expr_end = str + len;
9772 else if (c == S_EX_NONE)
9774 my_getExpression (ep, str);
9776 else if (c == S_EX_REGISTER)
9778 ep->X_op = O_constant;
9780 ep->X_add_symbol = NULL;
9781 ep->X_op_symbol = NULL;
9782 ep->X_add_number = 0;
9786 as_fatal (_("internal error"));
9790 /* All percent_op's have been handled. */
9797 my_getExpression (ep, str)
9804 save_in = input_line_pointer;
9805 input_line_pointer = str;
9807 expr_end = input_line_pointer;
9808 input_line_pointer = save_in;
9810 /* If we are in mips16 mode, and this is an expression based on `.',
9811 then we bump the value of the symbol by 1 since that is how other
9812 text symbols are handled. We don't bother to handle complex
9813 expressions, just `.' plus or minus a constant. */
9814 if (mips_opts.mips16
9815 && ep->X_op == O_symbol
9816 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9817 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9818 && symbol_get_frag (ep->X_add_symbol) == frag_now
9819 && symbol_constant_p (ep->X_add_symbol)
9820 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9821 S_SET_VALUE (ep->X_add_symbol, val + 1);
9824 /* Turn a string in input_line_pointer into a floating point constant
9825 of type TYPE, and store the appropriate bytes in *LITP. The number
9826 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9827 returned, or NULL on OK. */
9830 md_atof (type, litP, sizeP)
9836 LITTLENUM_TYPE words[4];
9852 return _("bad call to md_atof");
9855 t = atof_ieee (input_line_pointer, type, words);
9857 input_line_pointer = t;
9861 if (! target_big_endian)
9863 for (i = prec - 1; i >= 0; i--)
9865 md_number_to_chars (litP, (valueT) words[i], 2);
9871 for (i = 0; i < prec; i++)
9873 md_number_to_chars (litP, (valueT) words[i], 2);
9882 md_number_to_chars (buf, val, n)
9887 if (target_big_endian)
9888 number_to_chars_bigendian (buf, val, n);
9890 number_to_chars_littleendian (buf, val, n);
9894 static int support_64bit_objects(void)
9896 const char **list, **l;
9898 list = bfd_target_list ();
9899 for (l = list; *l != NULL; l++)
9901 /* This is traditional mips */
9902 if (strcmp (*l, "elf64-tradbigmips") == 0
9903 || strcmp (*l, "elf64-tradlittlemips") == 0)
9905 if (strcmp (*l, "elf64-bigmips") == 0
9906 || strcmp (*l, "elf64-littlemips") == 0)
9910 return (*l != NULL);
9912 #endif /* OBJ_ELF */
9914 const char *md_shortopts = "nO::g::G:";
9916 struct option md_longopts[] =
9918 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9919 {"mips0", no_argument, NULL, OPTION_MIPS1},
9920 {"mips1", no_argument, NULL, OPTION_MIPS1},
9921 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9922 {"mips2", no_argument, NULL, OPTION_MIPS2},
9923 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9924 {"mips3", no_argument, NULL, OPTION_MIPS3},
9925 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9926 {"mips4", no_argument, NULL, OPTION_MIPS4},
9927 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9928 {"mips5", no_argument, NULL, OPTION_MIPS5},
9929 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9930 {"mips32", no_argument, NULL, OPTION_MIPS32},
9931 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9932 {"mips64", no_argument, NULL, OPTION_MIPS64},
9933 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9934 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9935 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9936 {"trap", no_argument, NULL, OPTION_TRAP},
9937 {"no-break", no_argument, NULL, OPTION_TRAP},
9938 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9939 {"break", no_argument, NULL, OPTION_BREAK},
9940 {"no-trap", no_argument, NULL, OPTION_BREAK},
9941 #define OPTION_EB (OPTION_MD_BASE + 11)
9942 {"EB", no_argument, NULL, OPTION_EB},
9943 #define OPTION_EL (OPTION_MD_BASE + 12)
9944 {"EL", no_argument, NULL, OPTION_EL},
9945 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9946 {"mips16", no_argument, NULL, OPTION_MIPS16},
9947 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9948 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9949 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9950 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9951 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9952 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9953 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9954 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9955 {"mfp32", no_argument, NULL, OPTION_FP32},
9956 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9957 {"mgp32", no_argument, NULL, OPTION_GP32},
9958 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9959 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9960 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9961 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9962 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9963 {"march", required_argument, NULL, OPTION_MARCH},
9964 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9965 {"mtune", required_argument, NULL, OPTION_MTUNE},
9966 #define OPTION_FP64 (OPTION_MD_BASE + 23)
9967 {"mfp64", no_argument, NULL, OPTION_FP64},
9968 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9969 {"m4650", no_argument, NULL, OPTION_M4650},
9970 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9971 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9972 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9973 {"m4010", no_argument, NULL, OPTION_M4010},
9974 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9975 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9976 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9977 {"m4100", no_argument, NULL, OPTION_M4100},
9978 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9979 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9980 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9981 {"m3900", no_argument, NULL, OPTION_M3900},
9982 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9983 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9984 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9985 {"mgp64", no_argument, NULL, OPTION_GP64},
9986 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9987 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9988 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9989 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9990 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9991 {"mdmx", no_argument, NULL, OPTION_MDMX},
9992 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9993 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9995 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9996 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9997 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9998 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9999 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10000 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10001 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10002 {"xgot", no_argument, NULL, OPTION_XGOT},
10003 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10004 {"mabi", required_argument, NULL, OPTION_MABI},
10005 #define OPTION_32 (OPTION_ELF_BASE + 4)
10006 {"32", no_argument, NULL, OPTION_32},
10007 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10008 {"n32", no_argument, NULL, OPTION_N32},
10009 #define OPTION_64 (OPTION_ELF_BASE + 6)
10010 {"64", no_argument, NULL, OPTION_64},
10011 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10012 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10013 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10014 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10015 #endif /* OBJ_ELF */
10016 {NULL, no_argument, NULL, 0}
10018 size_t md_longopts_size = sizeof (md_longopts);
10020 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10021 NEW_VALUE. Warn if another value was already specified. Note:
10022 we have to defer parsing the -march and -mtune arguments in order
10023 to handle 'from-abi' correctly, since the ABI might be specified
10024 in a later argument. */
10027 mips_set_option_string (string_ptr, new_value)
10028 const char **string_ptr, *new_value;
10030 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10031 as_warn (_("A different %s was already specified, is now %s"),
10032 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10035 *string_ptr = new_value;
10039 md_parse_option (c, arg)
10045 case OPTION_CONSTRUCT_FLOATS:
10046 mips_disable_float_construction = 0;
10049 case OPTION_NO_CONSTRUCT_FLOATS:
10050 mips_disable_float_construction = 1;
10062 target_big_endian = 1;
10066 target_big_endian = 0;
10074 if (arg && arg[1] == '0')
10084 mips_debug = atoi (arg);
10085 /* When the MIPS assembler sees -g or -g2, it does not do
10086 optimizations which limit full symbolic debugging. We take
10087 that to be equivalent to -O0. */
10088 if (mips_debug == 2)
10093 file_mips_isa = ISA_MIPS1;
10097 file_mips_isa = ISA_MIPS2;
10101 file_mips_isa = ISA_MIPS3;
10105 file_mips_isa = ISA_MIPS4;
10109 file_mips_isa = ISA_MIPS5;
10112 case OPTION_MIPS32:
10113 file_mips_isa = ISA_MIPS32;
10116 case OPTION_MIPS64:
10117 file_mips_isa = ISA_MIPS64;
10121 mips_set_option_string (&mips_tune_string, arg);
10125 mips_set_option_string (&mips_arch_string, arg);
10129 mips_set_option_string (&mips_arch_string, "4650");
10130 mips_set_option_string (&mips_tune_string, "4650");
10133 case OPTION_NO_M4650:
10137 mips_set_option_string (&mips_arch_string, "4010");
10138 mips_set_option_string (&mips_tune_string, "4010");
10141 case OPTION_NO_M4010:
10145 mips_set_option_string (&mips_arch_string, "4100");
10146 mips_set_option_string (&mips_tune_string, "4100");
10149 case OPTION_NO_M4100:
10153 mips_set_option_string (&mips_arch_string, "3900");
10154 mips_set_option_string (&mips_tune_string, "3900");
10157 case OPTION_NO_M3900:
10161 mips_opts.ase_mdmx = 1;
10164 case OPTION_NO_MDMX:
10165 mips_opts.ase_mdmx = 0;
10168 case OPTION_MIPS16:
10169 mips_opts.mips16 = 1;
10170 mips_no_prev_insn (false);
10173 case OPTION_NO_MIPS16:
10174 mips_opts.mips16 = 0;
10175 mips_no_prev_insn (false);
10178 case OPTION_MIPS3D:
10179 mips_opts.ase_mips3d = 1;
10182 case OPTION_NO_MIPS3D:
10183 mips_opts.ase_mips3d = 0;
10186 case OPTION_MEMBEDDED_PIC:
10187 mips_pic = EMBEDDED_PIC;
10188 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10190 as_bad (_("-G may not be used with embedded PIC code"));
10193 g_switch_value = 0x7fffffff;
10197 /* When generating ELF code, we permit -KPIC and -call_shared to
10198 select SVR4_PIC, and -non_shared to select no PIC. This is
10199 intended to be compatible with Irix 5. */
10200 case OPTION_CALL_SHARED:
10201 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10203 as_bad (_("-call_shared is supported only for ELF format"));
10206 mips_pic = SVR4_PIC;
10207 if (g_switch_seen && g_switch_value != 0)
10209 as_bad (_("-G may not be used with SVR4 PIC code"));
10212 g_switch_value = 0;
10215 case OPTION_NON_SHARED:
10216 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10218 as_bad (_("-non_shared is supported only for ELF format"));
10224 /* The -xgot option tells the assembler to use 32 offsets when
10225 accessing the got in SVR4_PIC mode. It is for Irix
10230 #endif /* OBJ_ELF */
10233 if (! USE_GLOBAL_POINTER_OPT)
10235 as_bad (_("-G is not supported for this configuration"));
10238 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10240 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10244 g_switch_value = atoi (arg);
10249 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10252 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10254 as_bad (_("-32 is supported for ELF format only"));
10257 mips_abi = O32_ABI;
10261 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10263 as_bad (_("-n32 is supported for ELF format only"));
10266 mips_abi = N32_ABI;
10270 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10272 as_bad (_("-64 is supported for ELF format only"));
10275 mips_abi = N64_ABI;
10276 if (! support_64bit_objects())
10277 as_fatal (_("No compiled in support for 64 bit object file format"));
10279 #endif /* OBJ_ELF */
10282 file_mips_gp32 = 1;
10286 file_mips_gp32 = 0;
10290 file_mips_fp32 = 1;
10294 file_mips_fp32 = 0;
10299 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10301 as_bad (_("-mabi is supported for ELF format only"));
10304 if (strcmp (arg, "32") == 0)
10305 mips_abi = O32_ABI;
10306 else if (strcmp (arg, "o64") == 0)
10307 mips_abi = O64_ABI;
10308 else if (strcmp (arg, "n32") == 0)
10309 mips_abi = N32_ABI;
10310 else if (strcmp (arg, "64") == 0)
10312 mips_abi = N64_ABI;
10313 if (! support_64bit_objects())
10314 as_fatal (_("No compiled in support for 64 bit object file "
10317 else if (strcmp (arg, "eabi") == 0)
10318 mips_abi = EABI_ABI;
10321 as_fatal (_("invalid abi -mabi=%s"), arg);
10325 #endif /* OBJ_ELF */
10327 case OPTION_M7000_HILO_FIX:
10328 mips_7000_hilo_fix = true;
10331 case OPTION_MNO_7000_HILO_FIX:
10332 mips_7000_hilo_fix = false;
10336 case OPTION_MDEBUG:
10337 mips_flag_mdebug = true;
10340 case OPTION_NO_MDEBUG:
10341 mips_flag_mdebug = false;
10343 #endif /* OBJ_ELF */
10352 /* Set up globals to generate code for the ISA or processor
10353 described by INFO. */
10356 mips_set_architecture (info)
10357 const struct mips_cpu_info *info;
10361 mips_arch_info = info;
10362 mips_arch = info->cpu;
10363 mips_opts.isa = info->isa;
10368 /* Likewise for tuning. */
10371 mips_set_tune (info)
10372 const struct mips_cpu_info *info;
10376 mips_tune_info = info;
10377 mips_tune = info->cpu;
10383 mips_after_parse_args ()
10385 /* GP relative stuff not working for PE */
10386 if (strncmp (TARGET_OS, "pe", 2) == 0
10387 && g_switch_value != 0)
10390 as_bad (_("-G not supported in this configuration."));
10391 g_switch_value = 0;
10394 /* The following code determines the architecture and register size.
10395 Similar code was added to GCC 3.3 (see override_options() in
10396 config/mips/mips.c). The GAS and GCC code should be kept in sync
10397 as much as possible. */
10399 if (mips_arch_string != 0)
10400 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
10402 if (mips_tune_string != 0)
10403 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
10405 if (file_mips_isa != ISA_UNKNOWN)
10407 /* Handle -mipsN. At this point, file_mips_isa contains the
10408 ISA level specified by -mipsN, while mips_opts.isa contains
10409 the -march selection (if any). */
10410 if (mips_arch_info != 0)
10412 /* -march takes precedence over -mipsN, since it is more descriptive.
10413 There's no harm in specifying both as long as the ISA levels
10415 if (file_mips_isa != mips_opts.isa)
10416 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10417 mips_cpu_info_from_isa (file_mips_isa)->name,
10418 mips_cpu_info_from_isa (mips_opts.isa)->name);
10421 mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa));
10424 if (mips_arch_info == 0)
10425 mips_set_architecture (mips_parse_cpu ("default CPU",
10426 MIPS_CPU_STRING_DEFAULT));
10428 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10429 as_bad ("-march=%s is not compatible with the selected ABI",
10430 mips_arch_info->name);
10432 /* Optimize for mips_arch, unless -mtune selects a different processor. */
10433 if (mips_tune_info == 0)
10434 mips_set_tune (mips_arch_info);
10436 if (file_mips_gp32 >= 0)
10438 /* The user specified the size of the integer registers. Make sure
10439 it agrees with the ABI and ISA. */
10440 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10441 as_bad (_("-mgp64 used with a 32-bit processor"));
10442 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10443 as_bad (_("-mgp32 used with a 64-bit ABI"));
10444 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10445 as_bad (_("-mgp64 used with a 32-bit ABI"));
10449 /* Infer the integer register size from the ABI and processor.
10450 Restrict ourselves to 32-bit registers if that's all the
10451 processor has, or if the ABI cannot handle 64-bit registers. */
10452 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10453 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10456 /* ??? GAS treats single-float processors as though they had 64-bit
10457 float registers (although it complains when double-precision
10458 instructions are used). As things stand, saying they have 32-bit
10459 registers would lead to spurious "register must be even" messages.
10460 So here we assume float registers are always the same size as
10461 integer ones, unless the user says otherwise. */
10462 if (file_mips_fp32 < 0)
10463 file_mips_fp32 = file_mips_gp32;
10465 /* End of GCC-shared inference code. */
10467 /* ??? When do we want this flag to be set? Who uses it? */
10468 if (file_mips_gp32 == 1
10469 && mips_abi == NO_ABI
10470 && ISA_HAS_64BIT_REGS (mips_opts.isa))
10471 mips_32bitmode = 1;
10473 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10474 as_bad (_("trap exception not supported at ISA 1"));
10476 /* If the selected architecture includes support for ASEs, enable
10477 generation of code for them. */
10478 if (mips_opts.mips16 == -1)
10479 mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0;
10480 if (mips_opts.ase_mips3d == -1)
10481 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0;
10482 if (mips_opts.ase_mdmx == -1)
10483 mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0;
10485 file_mips_isa = mips_opts.isa;
10486 file_ase_mips16 = mips_opts.mips16;
10487 file_ase_mips3d = mips_opts.ase_mips3d;
10488 file_ase_mdmx = mips_opts.ase_mdmx;
10489 mips_opts.gp32 = file_mips_gp32;
10490 mips_opts.fp32 = file_mips_fp32;
10492 if (mips_flag_mdebug < 0)
10494 #ifdef OBJ_MAYBE_ECOFF
10495 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10496 mips_flag_mdebug = 1;
10498 #endif /* OBJ_MAYBE_ECOFF */
10499 mips_flag_mdebug = 0;
10504 mips_init_after_args ()
10506 /* initialize opcodes */
10507 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10508 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10512 md_pcrel_from (fixP)
10515 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10516 && fixP->fx_addsy != (symbolS *) NULL
10517 && ! S_IS_DEFINED (fixP->fx_addsy))
10519 /* This makes a branch to an undefined symbol be a branch to the
10520 current location. */
10521 if (mips_pic == EMBEDDED_PIC)
10527 /* Return the address of the delay slot. */
10528 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10531 /* This is called before the symbol table is processed. In order to
10532 work with gcc when using mips-tfile, we must keep all local labels.
10533 However, in other cases, we want to discard them. If we were
10534 called with -g, but we didn't see any debugging information, it may
10535 mean that gcc is smuggling debugging information through to
10536 mips-tfile, in which case we must generate all local labels. */
10539 mips_frob_file_before_adjust ()
10541 #ifndef NO_ECOFF_DEBUGGING
10542 if (ECOFF_DEBUGGING
10544 && ! ecoff_debugging_seen)
10545 flag_keep_locals = 1;
10549 /* Sort any unmatched HI16_S relocs so that they immediately precede
10550 the corresponding LO reloc. This is called before md_apply_fix3 and
10551 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10552 explicit use of the %hi modifier. */
10557 struct mips_hi_fixup *l;
10559 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10561 segment_info_type *seginfo;
10564 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10566 /* Check quickly whether the next fixup happens to be a matching
10568 if (l->fixp->fx_next != NULL
10569 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10570 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10571 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10574 /* Look through the fixups for this segment for a matching %lo.
10575 When we find one, move the %hi just in front of it. We do
10576 this in two passes. In the first pass, we try to find a
10577 unique %lo. In the second pass, we permit multiple %hi
10578 relocs for a single %lo (this is a GNU extension). */
10579 seginfo = seg_info (l->seg);
10580 for (pass = 0; pass < 2; pass++)
10585 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10587 /* Check whether this is a %lo fixup which matches l->fixp. */
10588 if (f->fx_r_type == BFD_RELOC_LO16
10589 && f->fx_addsy == l->fixp->fx_addsy
10590 && f->fx_offset == l->fixp->fx_offset
10593 || prev->fx_r_type != BFD_RELOC_HI16_S
10594 || prev->fx_addsy != f->fx_addsy
10595 || prev->fx_offset != f->fx_offset))
10599 /* Move l->fixp before f. */
10600 for (pf = &seginfo->fix_root;
10602 pf = &(*pf)->fx_next)
10603 assert (*pf != NULL);
10605 *pf = l->fixp->fx_next;
10607 l->fixp->fx_next = f;
10609 seginfo->fix_root = l->fixp;
10611 prev->fx_next = l->fixp;
10622 #if 0 /* GCC code motion plus incomplete dead code elimination
10623 can leave a %hi without a %lo. */
10625 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10626 _("Unmatched %%hi reloc"));
10632 /* When generating embedded PIC code we need to use a special
10633 relocation to represent the difference of two symbols in the .text
10634 section (switch tables use a difference of this sort). See
10635 include/coff/mips.h for details. This macro checks whether this
10636 fixup requires the special reloc. */
10637 #define SWITCH_TABLE(fixp) \
10638 ((fixp)->fx_r_type == BFD_RELOC_32 \
10639 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10640 && (fixp)->fx_addsy != NULL \
10641 && (fixp)->fx_subsy != NULL \
10642 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10643 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10645 /* When generating embedded PIC code we must keep all PC relative
10646 relocations, in case the linker has to relax a call. We also need
10647 to keep relocations for switch table entries.
10649 We may have combined relocations without symbols in the N32/N64 ABI.
10650 We have to prevent gas from dropping them. */
10653 mips_force_relocation (fixp)
10656 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10657 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10658 || S_FORCE_RELOC (fixp->fx_addsy))
10662 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10663 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10664 || fixp->fx_r_type == BFD_RELOC_HI16_S
10665 || fixp->fx_r_type == BFD_RELOC_LO16))
10668 return (mips_pic == EMBEDDED_PIC
10670 || SWITCH_TABLE (fixp)
10671 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10672 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10677 mips_need_elf_addend_fixup (fixP)
10680 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10682 if (mips_pic == EMBEDDED_PIC
10683 && S_IS_WEAK (fixP->fx_addsy))
10685 if (mips_pic != EMBEDDED_PIC
10686 && (S_IS_WEAK (fixP->fx_addsy)
10687 || S_IS_EXTERNAL (fixP->fx_addsy))
10688 && !S_IS_COMMON (fixP->fx_addsy))
10690 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10691 && (((bfd_get_section_flags (stdoutput,
10692 S_GET_SEGMENT (fixP->fx_addsy))
10693 & SEC_LINK_ONCE) != 0)
10694 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10696 sizeof (".gnu.linkonce") - 1)))
10702 /* Apply a fixup to the object file. */
10705 md_apply_fix3 (fixP, valP, seg)
10708 segT seg ATTRIBUTE_UNUSED;
10713 static int previous_fx_r_type = 0;
10715 /* FIXME: Maybe just return for all reloc types not listed below?
10716 Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */
10717 if (fixP->fx_r_type == BFD_RELOC_8)
10720 assert (fixP->fx_size == 4
10721 || fixP->fx_r_type == BFD_RELOC_16
10722 || fixP->fx_r_type == BFD_RELOC_32
10723 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10724 || fixP->fx_r_type == BFD_RELOC_HI16_S
10725 || fixP->fx_r_type == BFD_RELOC_LO16
10726 || fixP->fx_r_type == BFD_RELOC_GPREL16
10727 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10728 || fixP->fx_r_type == BFD_RELOC_GPREL32
10729 || fixP->fx_r_type == BFD_RELOC_64
10730 || fixP->fx_r_type == BFD_RELOC_CTOR
10731 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10732 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10733 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10734 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10735 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10736 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10737 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10738 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10739 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10743 /* If we aren't adjusting this fixup to be against the section
10744 symbol, we need to adjust the value. */
10746 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10748 if (mips_need_elf_addend_fixup (fixP))
10750 reloc_howto_type *howto;
10751 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10755 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
10756 if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel)
10758 /* In this case, the bfd_install_relocation routine will
10759 incorrectly add the symbol value back in. We just want
10760 the addend to appear in the object file. */
10763 /* Make sure the addend is still non-zero. If it became zero
10764 after the last operation, set it to a spurious value and
10765 subtract the same value from the object file's contents. */
10770 /* The in-place addends for LO16 relocations are signed;
10771 leave the matching HI16 in-place addends as zero. */
10772 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10774 bfd_vma contents, mask, field;
10776 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10779 target_big_endian);
10781 /* MASK has bits set where the relocation should go.
10782 FIELD is -value, shifted into the appropriate place
10783 for this relocation. */
10784 mask = 1 << (howto->bitsize - 1);
10785 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10786 field = (-value >> howto->rightshift) << howto->bitpos;
10788 bfd_put_bits ((field & mask) | (contents & ~mask),
10789 fixP->fx_frag->fr_literal + fixP->fx_where,
10791 target_big_endian);
10797 /* This code was generated using trial and error and so is
10798 fragile and not trustworthy. If you change it, you should
10799 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10800 they still pass. */
10801 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10803 value += fixP->fx_frag->fr_address + fixP->fx_where;
10805 /* BFD's REL handling, for MIPS, is _very_ weird.
10806 This gives the right results, but it can't possibly
10807 be the way things are supposed to work. */
10808 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10809 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10810 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10811 value += fixP->fx_frag->fr_address + fixP->fx_where;
10816 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10818 /* We are not done if this is a composite relocation to set up gp. */
10819 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
10820 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10821 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
10822 && (fixP->fx_r_type == BFD_RELOC_HI16_S
10823 || fixP->fx_r_type == BFD_RELOC_LO16))))
10825 previous_fx_r_type = fixP->fx_r_type;
10827 switch (fixP->fx_r_type)
10829 case BFD_RELOC_MIPS_JMP:
10830 case BFD_RELOC_MIPS_SHIFT5:
10831 case BFD_RELOC_MIPS_SHIFT6:
10832 case BFD_RELOC_MIPS_GOT_DISP:
10833 case BFD_RELOC_MIPS_GOT_PAGE:
10834 case BFD_RELOC_MIPS_GOT_OFST:
10835 case BFD_RELOC_MIPS_SUB:
10836 case BFD_RELOC_MIPS_INSERT_A:
10837 case BFD_RELOC_MIPS_INSERT_B:
10838 case BFD_RELOC_MIPS_DELETE:
10839 case BFD_RELOC_MIPS_HIGHEST:
10840 case BFD_RELOC_MIPS_HIGHER:
10841 case BFD_RELOC_MIPS_SCN_DISP:
10842 case BFD_RELOC_MIPS_REL16:
10843 case BFD_RELOC_MIPS_RELGOT:
10844 case BFD_RELOC_MIPS_JALR:
10845 case BFD_RELOC_HI16:
10846 case BFD_RELOC_HI16_S:
10847 case BFD_RELOC_GPREL16:
10848 case BFD_RELOC_MIPS_LITERAL:
10849 case BFD_RELOC_MIPS_CALL16:
10850 case BFD_RELOC_MIPS_GOT16:
10851 case BFD_RELOC_GPREL32:
10852 case BFD_RELOC_MIPS_GOT_HI16:
10853 case BFD_RELOC_MIPS_GOT_LO16:
10854 case BFD_RELOC_MIPS_CALL_HI16:
10855 case BFD_RELOC_MIPS_CALL_LO16:
10856 case BFD_RELOC_MIPS16_GPREL:
10857 if (fixP->fx_pcrel)
10858 as_bad_where (fixP->fx_file, fixP->fx_line,
10859 _("Invalid PC relative reloc"));
10860 /* Nothing needed to do. The value comes from the reloc entry */
10863 case BFD_RELOC_MIPS16_JMP:
10864 /* We currently always generate a reloc against a symbol, which
10865 means that we don't want an addend even if the symbol is
10867 fixP->fx_addnumber = 0;
10870 case BFD_RELOC_PCREL_HI16_S:
10871 /* The addend for this is tricky if it is internal, so we just
10872 do everything here rather than in bfd_install_relocation. */
10873 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10878 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10880 /* For an external symbol adjust by the address to make it
10881 pcrel_offset. We use the address of the RELLO reloc
10882 which follows this one. */
10883 value += (fixP->fx_next->fx_frag->fr_address
10884 + fixP->fx_next->fx_where);
10886 value = ((value + 0x8000) >> 16) & 0xffff;
10887 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10888 if (target_big_endian)
10890 md_number_to_chars ((char *) buf, value, 2);
10893 case BFD_RELOC_PCREL_LO16:
10894 /* The addend for this is tricky if it is internal, so we just
10895 do everything here rather than in bfd_install_relocation. */
10896 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
10901 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
10902 value += fixP->fx_frag->fr_address + fixP->fx_where;
10903 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10904 if (target_big_endian)
10906 md_number_to_chars ((char *) buf, value, 2);
10910 /* This is handled like BFD_RELOC_32, but we output a sign
10911 extended value if we are only 32 bits. */
10913 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10915 if (8 <= sizeof (valueT))
10916 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10923 w1 = w2 = fixP->fx_where;
10924 if (target_big_endian)
10928 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
10929 if ((value & 0x80000000) != 0)
10933 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
10938 case BFD_RELOC_RVA:
10940 /* If we are deleting this reloc entry, we must fill in the
10941 value now. This can happen if we have a .word which is not
10942 resolved when it appears but is later defined. We also need
10943 to fill in the value if this is an embedded PIC switch table
10946 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
10947 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10952 /* If we are deleting this reloc entry, we must fill in the
10954 assert (fixP->fx_size == 2);
10956 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
10960 case BFD_RELOC_LO16:
10961 /* When handling an embedded PIC switch statement, we can wind
10962 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10965 if (value + 0x8000 > 0xffff)
10966 as_bad_where (fixP->fx_file, fixP->fx_line,
10967 _("relocation overflow"));
10968 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
10969 if (target_big_endian)
10971 md_number_to_chars ((char *) buf, value, 2);
10975 case BFD_RELOC_16_PCREL_S2:
10976 if ((value & 0x3) != 0)
10977 as_bad_where (fixP->fx_file, fixP->fx_line,
10978 _("Branch to odd address (%lx)"), (long) value);
10980 /* Fall through. */
10982 case BFD_RELOC_16_PCREL:
10984 * We need to save the bits in the instruction since fixup_segment()
10985 * might be deleting the relocation entry (i.e., a branch within
10986 * the current segment).
10988 if (!fixP->fx_done && value != 0)
10990 /* If 'value' is zero, the remaining reloc code won't actually
10991 do the store, so it must be done here. This is probably
10992 a bug somewhere. */
10994 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
10995 || fixP->fx_addsy == NULL /* ??? */
10996 || ! S_IS_DEFINED (fixP->fx_addsy)))
10997 value -= fixP->fx_frag->fr_address + fixP->fx_where;
10999 value = (offsetT) value >> 2;
11001 /* update old instruction data */
11002 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11003 if (target_big_endian)
11004 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11006 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11008 if (value + 0x8000 <= 0xffff)
11009 insn |= value & 0xffff;
11012 /* The branch offset is too large. If this is an
11013 unconditional branch, and we are not generating PIC code,
11014 we can convert it to an absolute jump instruction. */
11015 if (mips_pic == NO_PIC
11017 && fixP->fx_frag->fr_address >= text_section->vma
11018 && (fixP->fx_frag->fr_address
11019 < text_section->vma + text_section->_raw_size)
11020 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11021 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11022 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11024 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11025 insn = 0x0c000000; /* jal */
11027 insn = 0x08000000; /* j */
11028 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11030 fixP->fx_addsy = section_symbol (text_section);
11031 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11035 /* FIXME. It would be possible in principle to handle
11036 conditional branches which overflow. They could be
11037 transformed into a branch around a jump. This would
11038 require setting up variant frags for each different
11039 branch type. The native MIPS assembler attempts to
11040 handle these cases, but it appears to do it
11042 as_bad_where (fixP->fx_file, fixP->fx_line,
11043 _("Branch out of range"));
11047 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11050 case BFD_RELOC_VTABLE_INHERIT:
11053 && !S_IS_DEFINED (fixP->fx_addsy)
11054 && !S_IS_WEAK (fixP->fx_addsy))
11055 S_SET_WEAK (fixP->fx_addsy);
11058 case BFD_RELOC_VTABLE_ENTRY:
11072 const struct mips_opcode *p;
11073 int treg, sreg, dreg, shamt;
11078 for (i = 0; i < NUMOPCODES; ++i)
11080 p = &mips_opcodes[i];
11081 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11083 printf ("%08lx %s\t", oc, p->name);
11084 treg = (oc >> 16) & 0x1f;
11085 sreg = (oc >> 21) & 0x1f;
11086 dreg = (oc >> 11) & 0x1f;
11087 shamt = (oc >> 6) & 0x1f;
11089 for (args = p->args;; ++args)
11100 printf ("%c", *args);
11104 assert (treg == sreg);
11105 printf ("$%d,$%d", treg, sreg);
11110 printf ("$%d", dreg);
11115 printf ("$%d", treg);
11119 printf ("0x%x", treg);
11124 printf ("$%d", sreg);
11128 printf ("0x%08lx", oc & 0x1ffffff);
11135 printf ("%d", imm);
11140 printf ("$%d", shamt);
11151 printf (_("%08lx UNDEFINED\n"), oc);
11162 name = input_line_pointer;
11163 c = get_symbol_end ();
11164 p = (symbolS *) symbol_find_or_make (name);
11165 *input_line_pointer = c;
11169 /* Align the current frag to a given power of two. The MIPS assembler
11170 also automatically adjusts any preceding label. */
11173 mips_align (to, fill, label)
11178 mips_emit_delays (false);
11179 frag_align (to, fill, 0);
11180 record_alignment (now_seg, to);
11183 assert (S_GET_SEGMENT (label) == now_seg);
11184 symbol_set_frag (label, frag_now);
11185 S_SET_VALUE (label, (valueT) frag_now_fix ());
11189 /* Align to a given power of two. .align 0 turns off the automatic
11190 alignment used by the data creating pseudo-ops. */
11194 int x ATTRIBUTE_UNUSED;
11197 register long temp_fill;
11198 long max_alignment = 15;
11202 o Note that the assembler pulls down any immediately preceeding label
11203 to the aligned address.
11204 o It's not documented but auto alignment is reinstated by
11205 a .align pseudo instruction.
11206 o Note also that after auto alignment is turned off the mips assembler
11207 issues an error on attempt to assemble an improperly aligned data item.
11212 temp = get_absolute_expression ();
11213 if (temp > max_alignment)
11214 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11217 as_warn (_("Alignment negative: 0 assumed."));
11220 if (*input_line_pointer == ',')
11222 ++input_line_pointer;
11223 temp_fill = get_absolute_expression ();
11230 mips_align (temp, (int) temp_fill,
11231 insn_labels != NULL ? insn_labels->label : NULL);
11238 demand_empty_rest_of_line ();
11242 mips_flush_pending_output ()
11244 mips_emit_delays (false);
11245 mips_clear_insn_labels ();
11254 /* When generating embedded PIC code, we only use the .text, .lit8,
11255 .sdata and .sbss sections. We change the .data and .rdata
11256 pseudo-ops to use .sdata. */
11257 if (mips_pic == EMBEDDED_PIC
11258 && (sec == 'd' || sec == 'r'))
11262 /* The ELF backend needs to know that we are changing sections, so
11263 that .previous works correctly. We could do something like check
11264 for an obj_section_change_hook macro, but that might be confusing
11265 as it would not be appropriate to use it in the section changing
11266 functions in read.c, since obj-elf.c intercepts those. FIXME:
11267 This should be cleaner, somehow. */
11268 obj_elf_section_change_hook ();
11271 mips_emit_delays (false);
11281 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11282 demand_empty_rest_of_line ();
11286 if (USE_GLOBAL_POINTER_OPT)
11288 seg = subseg_new (RDATA_SECTION_NAME,
11289 (subsegT) get_absolute_expression ());
11290 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11292 bfd_set_section_flags (stdoutput, seg,
11298 if (strcmp (TARGET_OS, "elf") != 0)
11299 record_alignment (seg, 4);
11301 demand_empty_rest_of_line ();
11305 as_bad (_("No read only data section in this object file format"));
11306 demand_empty_rest_of_line ();
11312 if (USE_GLOBAL_POINTER_OPT)
11314 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11315 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11317 bfd_set_section_flags (stdoutput, seg,
11318 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11320 if (strcmp (TARGET_OS, "elf") != 0)
11321 record_alignment (seg, 4);
11323 demand_empty_rest_of_line ();
11328 as_bad (_("Global pointers not supported; recompile -G 0"));
11329 demand_empty_rest_of_line ();
11338 s_change_section (ignore)
11339 int ignore ATTRIBUTE_UNUSED;
11342 char *section_name;
11347 int section_entry_size;
11348 int section_alignment;
11350 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11353 section_name = input_line_pointer;
11354 c = get_symbol_end ();
11355 next_c = *(input_line_pointer + 1);
11357 /* Do we have .section Name<,"flags">? */
11358 if (c != ',' || (c == ',' && next_c == '"'))
11360 /* just after name is now '\0'. */
11361 *input_line_pointer = c;
11362 input_line_pointer = section_name;
11363 obj_elf_section (ignore);
11366 input_line_pointer++;
11368 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11370 section_type = get_absolute_expression ();
11373 if (*input_line_pointer++ == ',')
11374 section_flag = get_absolute_expression ();
11377 if (*input_line_pointer++ == ',')
11378 section_entry_size = get_absolute_expression ();
11380 section_entry_size = 0;
11381 if (*input_line_pointer++ == ',')
11382 section_alignment = get_absolute_expression ();
11384 section_alignment = 0;
11386 obj_elf_change_section (section_name, section_type, section_flag,
11387 section_entry_size, 0, 0, 0);
11388 #endif /* OBJ_ELF */
11392 mips_enable_auto_align ()
11403 label = insn_labels != NULL ? insn_labels->label : NULL;
11404 mips_emit_delays (false);
11405 if (log_size > 0 && auto_align)
11406 mips_align (log_size, 0, label);
11407 mips_clear_insn_labels ();
11408 cons (1 << log_size);
11412 s_float_cons (type)
11417 label = insn_labels != NULL ? insn_labels->label : NULL;
11419 mips_emit_delays (false);
11424 mips_align (3, 0, label);
11426 mips_align (2, 0, label);
11429 mips_clear_insn_labels ();
11434 /* Handle .globl. We need to override it because on Irix 5 you are
11437 where foo is an undefined symbol, to mean that foo should be
11438 considered to be the address of a function. */
11442 int x ATTRIBUTE_UNUSED;
11449 name = input_line_pointer;
11450 c = get_symbol_end ();
11451 symbolP = symbol_find_or_make (name);
11452 *input_line_pointer = c;
11453 SKIP_WHITESPACE ();
11455 /* On Irix 5, every global symbol that is not explicitly labelled as
11456 being a function is apparently labelled as being an object. */
11459 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11464 secname = input_line_pointer;
11465 c = get_symbol_end ();
11466 sec = bfd_get_section_by_name (stdoutput, secname);
11468 as_bad (_("%s: no such section"), secname);
11469 *input_line_pointer = c;
11471 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11472 flag = BSF_FUNCTION;
11475 symbol_get_bfdsym (symbolP)->flags |= flag;
11477 S_SET_EXTERNAL (symbolP);
11478 demand_empty_rest_of_line ();
11483 int x ATTRIBUTE_UNUSED;
11488 opt = input_line_pointer;
11489 c = get_symbol_end ();
11493 /* FIXME: What does this mean? */
11495 else if (strncmp (opt, "pic", 3) == 0)
11499 i = atoi (opt + 3);
11503 mips_pic = SVR4_PIC;
11505 as_bad (_(".option pic%d not supported"), i);
11507 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11509 if (g_switch_seen && g_switch_value != 0)
11510 as_warn (_("-G may not be used with SVR4 PIC code"));
11511 g_switch_value = 0;
11512 bfd_set_gp_size (stdoutput, 0);
11516 as_warn (_("Unrecognized option \"%s\""), opt);
11518 *input_line_pointer = c;
11519 demand_empty_rest_of_line ();
11522 /* This structure is used to hold a stack of .set values. */
11524 struct mips_option_stack
11526 struct mips_option_stack *next;
11527 struct mips_set_options options;
11530 static struct mips_option_stack *mips_opts_stack;
11532 /* Handle the .set pseudo-op. */
11536 int x ATTRIBUTE_UNUSED;
11538 char *name = input_line_pointer, ch;
11540 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11541 ++input_line_pointer;
11542 ch = *input_line_pointer;
11543 *input_line_pointer = '\0';
11545 if (strcmp (name, "reorder") == 0)
11547 if (mips_opts.noreorder && prev_nop_frag != NULL)
11549 /* If we still have pending nops, we can discard them. The
11550 usual nop handling will insert any that are still
11552 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11553 * (mips_opts.mips16 ? 2 : 4));
11554 prev_nop_frag = NULL;
11556 mips_opts.noreorder = 0;
11558 else if (strcmp (name, "noreorder") == 0)
11560 mips_emit_delays (true);
11561 mips_opts.noreorder = 1;
11562 mips_any_noreorder = 1;
11564 else if (strcmp (name, "at") == 0)
11566 mips_opts.noat = 0;
11568 else if (strcmp (name, "noat") == 0)
11570 mips_opts.noat = 1;
11572 else if (strcmp (name, "macro") == 0)
11574 mips_opts.warn_about_macros = 0;
11576 else if (strcmp (name, "nomacro") == 0)
11578 if (mips_opts.noreorder == 0)
11579 as_bad (_("`noreorder' must be set before `nomacro'"));
11580 mips_opts.warn_about_macros = 1;
11582 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11584 mips_opts.nomove = 0;
11586 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11588 mips_opts.nomove = 1;
11590 else if (strcmp (name, "bopt") == 0)
11592 mips_opts.nobopt = 0;
11594 else if (strcmp (name, "nobopt") == 0)
11596 mips_opts.nobopt = 1;
11598 else if (strcmp (name, "mips16") == 0
11599 || strcmp (name, "MIPS-16") == 0)
11600 mips_opts.mips16 = 1;
11601 else if (strcmp (name, "nomips16") == 0
11602 || strcmp (name, "noMIPS-16") == 0)
11603 mips_opts.mips16 = 0;
11604 else if (strcmp (name, "mips3d") == 0)
11605 mips_opts.ase_mips3d = 1;
11606 else if (strcmp (name, "nomips3d") == 0)
11607 mips_opts.ase_mips3d = 0;
11608 else if (strcmp (name, "mdmx") == 0)
11609 mips_opts.ase_mdmx = 1;
11610 else if (strcmp (name, "nomdmx") == 0)
11611 mips_opts.ase_mdmx = 0;
11612 else if (strncmp (name, "mips", 4) == 0)
11616 /* Permit the user to change the ISA on the fly. Needless to
11617 say, misuse can cause serious problems. */
11618 isa = atoi (name + 4);
11622 mips_opts.gp32 = file_mips_gp32;
11623 mips_opts.fp32 = file_mips_fp32;
11628 mips_opts.gp32 = 1;
11629 mips_opts.fp32 = 1;
11635 mips_opts.gp32 = 0;
11636 mips_opts.fp32 = 0;
11639 as_bad (_("unknown ISA level %s"), name + 4);
11645 case 0: mips_opts.isa = file_mips_isa; break;
11646 case 1: mips_opts.isa = ISA_MIPS1; break;
11647 case 2: mips_opts.isa = ISA_MIPS2; break;
11648 case 3: mips_opts.isa = ISA_MIPS3; break;
11649 case 4: mips_opts.isa = ISA_MIPS4; break;
11650 case 5: mips_opts.isa = ISA_MIPS5; break;
11651 case 32: mips_opts.isa = ISA_MIPS32; break;
11652 case 64: mips_opts.isa = ISA_MIPS64; break;
11653 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11656 else if (strcmp (name, "autoextend") == 0)
11657 mips_opts.noautoextend = 0;
11658 else if (strcmp (name, "noautoextend") == 0)
11659 mips_opts.noautoextend = 1;
11660 else if (strcmp (name, "push") == 0)
11662 struct mips_option_stack *s;
11664 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11665 s->next = mips_opts_stack;
11666 s->options = mips_opts;
11667 mips_opts_stack = s;
11669 else if (strcmp (name, "pop") == 0)
11671 struct mips_option_stack *s;
11673 s = mips_opts_stack;
11675 as_bad (_(".set pop with no .set push"));
11678 /* If we're changing the reorder mode we need to handle
11679 delay slots correctly. */
11680 if (s->options.noreorder && ! mips_opts.noreorder)
11681 mips_emit_delays (true);
11682 else if (! s->options.noreorder && mips_opts.noreorder)
11684 if (prev_nop_frag != NULL)
11686 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11687 * (mips_opts.mips16 ? 2 : 4));
11688 prev_nop_frag = NULL;
11692 mips_opts = s->options;
11693 mips_opts_stack = s->next;
11699 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11701 *input_line_pointer = ch;
11702 demand_empty_rest_of_line ();
11705 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11706 .option pic2. It means to generate SVR4 PIC calls. */
11709 s_abicalls (ignore)
11710 int ignore ATTRIBUTE_UNUSED;
11712 mips_pic = SVR4_PIC;
11713 if (USE_GLOBAL_POINTER_OPT)
11715 if (g_switch_seen && g_switch_value != 0)
11716 as_warn (_("-G may not be used with SVR4 PIC code"));
11717 g_switch_value = 0;
11719 bfd_set_gp_size (stdoutput, 0);
11720 demand_empty_rest_of_line ();
11723 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11724 PIC code. It sets the $gp register for the function based on the
11725 function address, which is in the register named in the argument.
11726 This uses a relocation against _gp_disp, which is handled specially
11727 by the linker. The result is:
11728 lui $gp,%hi(_gp_disp)
11729 addiu $gp,$gp,%lo(_gp_disp)
11730 addu $gp,$gp,.cpload argument
11731 The .cpload argument is normally $25 == $t9. */
11735 int ignore ATTRIBUTE_UNUSED;
11740 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11741 .cpload is ignored. */
11742 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11748 /* .cpload should be in a .set noreorder section. */
11749 if (mips_opts.noreorder == 0)
11750 as_warn (_(".cpload not in noreorder section"));
11752 ex.X_op = O_symbol;
11753 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11754 ex.X_op_symbol = NULL;
11755 ex.X_add_number = 0;
11757 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11758 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11760 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11761 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11762 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11764 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11765 mips_gp_register, mips_gp_register, tc_get_register (0));
11767 demand_empty_rest_of_line ();
11770 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11771 .cpsetup $reg1, offset|$reg2, label
11773 If offset is given, this results in:
11774 sd $gp, offset($sp)
11775 lui $gp, %hi(%neg(%gp_rel(label)))
11776 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11777 daddu $gp, $gp, $reg1
11779 If $reg2 is given, this results in:
11780 daddu $reg2, $gp, $0
11781 lui $gp, %hi(%neg(%gp_rel(label)))
11782 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11783 daddu $gp, $gp, $reg1
11784 $reg1 is normally $25 == $t9. */
11787 int ignore ATTRIBUTE_UNUSED;
11789 expressionS ex_off;
11790 expressionS ex_sym;
11795 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11796 We also need NewABI support. */
11797 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11803 reg1 = tc_get_register (0);
11804 SKIP_WHITESPACE ();
11805 if (*input_line_pointer != ',')
11807 as_bad (_("missing argument separator ',' for .cpsetup"));
11811 ++input_line_pointer;
11812 SKIP_WHITESPACE ();
11813 if (*input_line_pointer == '$')
11815 mips_cpreturn_register = tc_get_register (0);
11816 mips_cpreturn_offset = -1;
11820 mips_cpreturn_offset = get_absolute_expression ();
11821 mips_cpreturn_register = -1;
11823 SKIP_WHITESPACE ();
11824 if (*input_line_pointer != ',')
11826 as_bad (_("missing argument separator ',' for .cpsetup"));
11830 ++input_line_pointer;
11831 SKIP_WHITESPACE ();
11832 expression (&ex_sym);
11834 if (mips_cpreturn_register == -1)
11836 ex_off.X_op = O_constant;
11837 ex_off.X_add_symbol = NULL;
11838 ex_off.X_op_symbol = NULL;
11839 ex_off.X_add_number = mips_cpreturn_offset;
11841 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11842 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11845 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11846 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11848 /* Ensure there's room for the next two instructions, so that `f'
11849 doesn't end up with an address in the wrong frag. */
11852 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11853 (int) BFD_RELOC_GPREL16);
11854 fix_new (frag_now, f - frag_now->fr_literal,
11855 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11856 fix_new (frag_now, f - frag_now->fr_literal,
11857 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11860 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11861 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11862 fix_new (frag_now, f - frag_now->fr_literal,
11863 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11864 fix_new (frag_now, f - frag_now->fr_literal,
11865 0, NULL, 0, 0, BFD_RELOC_LO16);
11867 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11868 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11869 mips_gp_register, mips_gp_register, reg1);
11871 demand_empty_rest_of_line ();
11876 int ignore ATTRIBUTE_UNUSED;
11878 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11879 .cplocal is ignored. */
11880 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11886 mips_gp_register = tc_get_register (0);
11887 demand_empty_rest_of_line ();
11890 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11891 offset from $sp. The offset is remembered, and after making a PIC
11892 call $gp is restored from that location. */
11895 s_cprestore (ignore)
11896 int ignore ATTRIBUTE_UNUSED;
11901 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11902 .cprestore is ignored. */
11903 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11909 mips_cprestore_offset = get_absolute_expression ();
11910 mips_cprestore_valid = 1;
11912 ex.X_op = O_constant;
11913 ex.X_add_symbol = NULL;
11914 ex.X_op_symbol = NULL;
11915 ex.X_add_number = mips_cprestore_offset;
11917 macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex,
11918 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11919 mips_gp_register, SP);
11921 demand_empty_rest_of_line ();
11924 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11925 was given in the preceeding .gpsetup, it results in:
11926 ld $gp, offset($sp)
11928 If a register $reg2 was given there, it results in:
11929 daddiu $gp, $gp, $reg2
11932 s_cpreturn (ignore)
11933 int ignore ATTRIBUTE_UNUSED;
11938 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11939 We also need NewABI support. */
11940 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11946 if (mips_cpreturn_register == -1)
11948 ex.X_op = O_constant;
11949 ex.X_add_symbol = NULL;
11950 ex.X_op_symbol = NULL;
11951 ex.X_add_number = mips_cpreturn_offset;
11953 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
11954 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11957 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11958 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
11960 demand_empty_rest_of_line ();
11963 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11964 code. It sets the offset to use in gp_rel relocations. */
11968 int ignore ATTRIBUTE_UNUSED;
11970 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11971 We also need NewABI support. */
11972 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11978 mips_gprel_offset = get_absolute_expression ();
11980 demand_empty_rest_of_line ();
11983 /* Handle the .gpword pseudo-op. This is used when generating PIC
11984 code. It generates a 32 bit GP relative reloc. */
11988 int ignore ATTRIBUTE_UNUSED;
11994 /* When not generating PIC code, this is treated as .word. */
11995 if (mips_pic != SVR4_PIC)
12001 label = insn_labels != NULL ? insn_labels->label : NULL;
12002 mips_emit_delays (true);
12004 mips_align (2, 0, label);
12005 mips_clear_insn_labels ();
12009 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12011 as_bad (_("Unsupported use of .gpword"));
12012 ignore_rest_of_line ();
12016 md_number_to_chars (p, (valueT) 0, 4);
12017 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12018 BFD_RELOC_GPREL32);
12020 demand_empty_rest_of_line ();
12023 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12024 tables in SVR4 PIC code. */
12028 int ignore ATTRIBUTE_UNUSED;
12033 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12035 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12041 /* Add $gp to the register named as an argument. */
12042 reg = tc_get_register (0);
12043 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12044 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12045 "d,v,t", reg, reg, mips_gp_register);
12047 demand_empty_rest_of_line ();
12050 /* Handle the .insn pseudo-op. This marks instruction labels in
12051 mips16 mode. This permits the linker to handle them specially,
12052 such as generating jalx instructions when needed. We also make
12053 them odd for the duration of the assembly, in order to generate the
12054 right sort of code. We will make them even in the adjust_symtab
12055 routine, while leaving them marked. This is convenient for the
12056 debugger and the disassembler. The linker knows to make them odd
12061 int ignore ATTRIBUTE_UNUSED;
12063 mips16_mark_labels ();
12065 demand_empty_rest_of_line ();
12068 /* Handle a .stabn directive. We need these in order to mark a label
12069 as being a mips16 text label correctly. Sometimes the compiler
12070 will emit a label, followed by a .stabn, and then switch sections.
12071 If the label and .stabn are in mips16 mode, then the label is
12072 really a mips16 text label. */
12079 mips16_mark_labels ();
12084 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12088 s_mips_weakext (ignore)
12089 int ignore ATTRIBUTE_UNUSED;
12096 name = input_line_pointer;
12097 c = get_symbol_end ();
12098 symbolP = symbol_find_or_make (name);
12099 S_SET_WEAK (symbolP);
12100 *input_line_pointer = c;
12102 SKIP_WHITESPACE ();
12104 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12106 if (S_IS_DEFINED (symbolP))
12108 as_bad ("ignoring attempt to redefine symbol %s",
12109 S_GET_NAME (symbolP));
12110 ignore_rest_of_line ();
12114 if (*input_line_pointer == ',')
12116 ++input_line_pointer;
12117 SKIP_WHITESPACE ();
12121 if (exp.X_op != O_symbol)
12123 as_bad ("bad .weakext directive");
12124 ignore_rest_of_line ();
12127 symbol_set_value_expression (symbolP, &exp);
12130 demand_empty_rest_of_line ();
12133 /* Parse a register string into a number. Called from the ECOFF code
12134 to parse .frame. The argument is non-zero if this is the frame
12135 register, so that we can record it in mips_frame_reg. */
12138 tc_get_register (frame)
12143 SKIP_WHITESPACE ();
12144 if (*input_line_pointer++ != '$')
12146 as_warn (_("expected `$'"));
12149 else if (ISDIGIT (*input_line_pointer))
12151 reg = get_absolute_expression ();
12152 if (reg < 0 || reg >= 32)
12154 as_warn (_("Bad register number"));
12160 if (strncmp (input_line_pointer, "ra", 2) == 0)
12163 input_line_pointer += 2;
12165 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12168 input_line_pointer += 2;
12170 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12173 input_line_pointer += 2;
12175 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12178 input_line_pointer += 2;
12180 else if (strncmp (input_line_pointer, "at", 2) == 0)
12183 input_line_pointer += 2;
12185 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12188 input_line_pointer += 3;
12190 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12193 input_line_pointer += 3;
12195 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12198 input_line_pointer += 4;
12202 as_warn (_("Unrecognized register name"));
12204 while (ISALNUM(*input_line_pointer))
12205 input_line_pointer++;
12210 mips_frame_reg = reg != 0 ? reg : SP;
12211 mips_frame_reg_valid = 1;
12212 mips_cprestore_valid = 0;
12218 md_section_align (seg, addr)
12222 int align = bfd_get_section_alignment (stdoutput, seg);
12225 /* We don't need to align ELF sections to the full alignment.
12226 However, Irix 5 may prefer that we align them at least to a 16
12227 byte boundary. We don't bother to align the sections if we are
12228 targeted for an embedded system. */
12229 if (strcmp (TARGET_OS, "elf") == 0)
12235 return ((addr + (1 << align) - 1) & (-1 << align));
12238 /* Utility routine, called from above as well. If called while the
12239 input file is still being read, it's only an approximation. (For
12240 example, a symbol may later become defined which appeared to be
12241 undefined earlier.) */
12244 nopic_need_relax (sym, before_relaxing)
12246 int before_relaxing;
12251 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12253 const char *symname;
12256 /* Find out whether this symbol can be referenced off the $gp
12257 register. It can be if it is smaller than the -G size or if
12258 it is in the .sdata or .sbss section. Certain symbols can
12259 not be referenced off the $gp, although it appears as though
12261 symname = S_GET_NAME (sym);
12262 if (symname != (const char *) NULL
12263 && (strcmp (symname, "eprol") == 0
12264 || strcmp (symname, "etext") == 0
12265 || strcmp (symname, "_gp") == 0
12266 || strcmp (symname, "edata") == 0
12267 || strcmp (symname, "_fbss") == 0
12268 || strcmp (symname, "_fdata") == 0
12269 || strcmp (symname, "_ftext") == 0
12270 || strcmp (symname, "end") == 0
12271 || strcmp (symname, "_gp_disp") == 0))
12273 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12275 #ifndef NO_ECOFF_DEBUGGING
12276 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12277 && (symbol_get_obj (sym)->ecoff_extern_size
12278 <= g_switch_value))
12280 /* We must defer this decision until after the whole
12281 file has been read, since there might be a .extern
12282 after the first use of this symbol. */
12283 || (before_relaxing
12284 #ifndef NO_ECOFF_DEBUGGING
12285 && symbol_get_obj (sym)->ecoff_extern_size == 0
12287 && S_GET_VALUE (sym) == 0)
12288 || (S_GET_VALUE (sym) != 0
12289 && S_GET_VALUE (sym) <= g_switch_value)))
12293 const char *segname;
12295 segname = segment_name (S_GET_SEGMENT (sym));
12296 assert (strcmp (segname, ".lit8") != 0
12297 && strcmp (segname, ".lit4") != 0);
12298 change = (strcmp (segname, ".sdata") != 0
12299 && strcmp (segname, ".sbss") != 0
12300 && strncmp (segname, ".sdata.", 7) != 0
12301 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12306 /* We are not optimizing for the $gp register. */
12310 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12311 extended opcode. SEC is the section the frag is in. */
12314 mips16_extended_frag (fragp, sec, stretch)
12320 register const struct mips16_immed_operand *op;
12322 int mintiny, maxtiny;
12326 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12328 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12331 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12332 op = mips16_immed_operands;
12333 while (op->type != type)
12336 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12341 if (type == '<' || type == '>' || type == '[' || type == ']')
12344 maxtiny = 1 << op->nbits;
12349 maxtiny = (1 << op->nbits) - 1;
12354 mintiny = - (1 << (op->nbits - 1));
12355 maxtiny = (1 << (op->nbits - 1)) - 1;
12358 sym_frag = symbol_get_frag (fragp->fr_symbol);
12359 val = S_GET_VALUE (fragp->fr_symbol);
12360 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12366 /* We won't have the section when we are called from
12367 mips_relax_frag. However, we will always have been called
12368 from md_estimate_size_before_relax first. If this is a
12369 branch to a different section, we mark it as such. If SEC is
12370 NULL, and the frag is not marked, then it must be a branch to
12371 the same section. */
12374 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12379 /* Must have been called from md_estimate_size_before_relax. */
12382 fragp->fr_subtype =
12383 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12385 /* FIXME: We should support this, and let the linker
12386 catch branches and loads that are out of range. */
12387 as_bad_where (fragp->fr_file, fragp->fr_line,
12388 _("unsupported PC relative reference to different section"));
12392 if (fragp != sym_frag && sym_frag->fr_address == 0)
12393 /* Assume non-extended on the first relaxation pass.
12394 The address we have calculated will be bogus if this is
12395 a forward branch to another frag, as the forward frag
12396 will have fr_address == 0. */
12400 /* In this case, we know for sure that the symbol fragment is in
12401 the same section. If the relax_marker of the symbol fragment
12402 differs from the relax_marker of this fragment, we have not
12403 yet adjusted the symbol fragment fr_address. We want to add
12404 in STRETCH in order to get a better estimate of the address.
12405 This particularly matters because of the shift bits. */
12407 && sym_frag->relax_marker != fragp->relax_marker)
12411 /* Adjust stretch for any alignment frag. Note that if have
12412 been expanding the earlier code, the symbol may be
12413 defined in what appears to be an earlier frag. FIXME:
12414 This doesn't handle the fr_subtype field, which specifies
12415 a maximum number of bytes to skip when doing an
12417 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12419 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12422 stretch = - ((- stretch)
12423 & ~ ((1 << (int) f->fr_offset) - 1));
12425 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12434 addr = fragp->fr_address + fragp->fr_fix;
12436 /* The base address rules are complicated. The base address of
12437 a branch is the following instruction. The base address of a
12438 PC relative load or add is the instruction itself, but if it
12439 is in a delay slot (in which case it can not be extended) use
12440 the address of the instruction whose delay slot it is in. */
12441 if (type == 'p' || type == 'q')
12445 /* If we are currently assuming that this frag should be
12446 extended, then, the current address is two bytes
12448 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12451 /* Ignore the low bit in the target, since it will be set
12452 for a text label. */
12453 if ((val & 1) != 0)
12456 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12458 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12461 val -= addr & ~ ((1 << op->shift) - 1);
12463 /* Branch offsets have an implicit 0 in the lowest bit. */
12464 if (type == 'p' || type == 'q')
12467 /* If any of the shifted bits are set, we must use an extended
12468 opcode. If the address depends on the size of this
12469 instruction, this can lead to a loop, so we arrange to always
12470 use an extended opcode. We only check this when we are in
12471 the main relaxation loop, when SEC is NULL. */
12472 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12474 fragp->fr_subtype =
12475 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12479 /* If we are about to mark a frag as extended because the value
12480 is precisely maxtiny + 1, then there is a chance of an
12481 infinite loop as in the following code:
12486 In this case when the la is extended, foo is 0x3fc bytes
12487 away, so the la can be shrunk, but then foo is 0x400 away, so
12488 the la must be extended. To avoid this loop, we mark the
12489 frag as extended if it was small, and is about to become
12490 extended with a value of maxtiny + 1. */
12491 if (val == ((maxtiny + 1) << op->shift)
12492 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12495 fragp->fr_subtype =
12496 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12500 else if (symsec != absolute_section && sec != NULL)
12501 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12503 if ((val & ((1 << op->shift) - 1)) != 0
12504 || val < (mintiny << op->shift)
12505 || val > (maxtiny << op->shift))
12511 /* Estimate the size of a frag before relaxing. Unless this is the
12512 mips16, we are not really relaxing here, and the final size is
12513 encoded in the subtype information. For the mips16, we have to
12514 decide whether we are using an extended opcode or not. */
12517 md_estimate_size_before_relax (fragp, segtype)
12522 boolean linkonce = false;
12524 if (RELAX_MIPS16_P (fragp->fr_subtype))
12525 /* We don't want to modify the EXTENDED bit here; it might get us
12526 into infinite loops. We change it only in mips_relax_frag(). */
12527 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12529 if (mips_pic == NO_PIC)
12531 change = nopic_need_relax (fragp->fr_symbol, 0);
12533 else if (mips_pic == SVR4_PIC)
12538 sym = fragp->fr_symbol;
12540 /* Handle the case of a symbol equated to another symbol. */
12541 while (symbol_equated_reloc_p (sym))
12545 /* It's possible to get a loop here in a badly written
12547 n = symbol_get_value_expression (sym)->X_add_symbol;
12553 symsec = S_GET_SEGMENT (sym);
12555 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12556 if (symsec != segtype && ! S_IS_LOCAL (sym))
12558 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12562 /* The GNU toolchain uses an extension for ELF: a section
12563 beginning with the magic string .gnu.linkonce is a linkonce
12565 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12566 sizeof ".gnu.linkonce" - 1) == 0)
12570 /* This must duplicate the test in adjust_reloc_syms. */
12571 change = (symsec != &bfd_und_section
12572 && symsec != &bfd_abs_section
12573 && ! bfd_is_com_section (symsec)
12576 /* A global or weak symbol is treated as external. */
12577 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12578 || (! S_IS_WEAK (sym)
12579 && (! S_IS_EXTERNAL (sym)
12580 || mips_pic == EMBEDDED_PIC)))
12589 /* Record the offset to the first reloc in the fr_opcode field.
12590 This lets md_convert_frag and tc_gen_reloc know that the code
12591 must be expanded. */
12592 fragp->fr_opcode = (fragp->fr_literal
12594 - RELAX_OLD (fragp->fr_subtype)
12595 + RELAX_RELOC1 (fragp->fr_subtype));
12596 /* FIXME: This really needs as_warn_where. */
12597 if (RELAX_WARN (fragp->fr_subtype))
12598 as_warn (_("AT used after \".set noat\" or macro used after "
12599 "\".set nomacro\""));
12601 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12607 /* This is called to see whether a reloc against a defined symbol
12608 should be converted into a reloc against a section. Don't adjust
12609 MIPS16 jump relocations, so we don't have to worry about the format
12610 of the offset in the .o file. Don't adjust relocations against
12611 mips16 symbols, so that the linker can find them if it needs to set
12615 mips_fix_adjustable (fixp)
12618 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12621 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12622 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12625 if (fixp->fx_addsy == NULL)
12629 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12630 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12631 && fixp->fx_subsy == NULL)
12638 /* Translate internal representation of relocation info to BFD target
12642 tc_gen_reloc (section, fixp)
12643 asection *section ATTRIBUTE_UNUSED;
12646 static arelent *retval[4];
12648 bfd_reloc_code_real_type code;
12650 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12653 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12654 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12655 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12657 if (mips_pic == EMBEDDED_PIC
12658 && SWITCH_TABLE (fixp))
12660 /* For a switch table entry we use a special reloc. The addend
12661 is actually the difference between the reloc address and the
12663 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12664 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12665 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12666 fixp->fx_r_type = BFD_RELOC_GPREL32;
12668 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12670 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12671 reloc->addend = fixp->fx_addnumber;
12674 /* We use a special addend for an internal RELLO reloc. */
12675 if (symbol_section_p (fixp->fx_addsy))
12676 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12678 reloc->addend = fixp->fx_addnumber + reloc->address;
12681 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12683 assert (fixp->fx_next != NULL
12684 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12686 /* The reloc is relative to the RELLO; adjust the addend
12688 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12689 reloc->addend = fixp->fx_next->fx_addnumber;
12692 /* We use a special addend for an internal RELHI reloc. */
12693 if (symbol_section_p (fixp->fx_addsy))
12694 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12695 + fixp->fx_next->fx_where
12696 - S_GET_VALUE (fixp->fx_subsy));
12698 reloc->addend = (fixp->fx_addnumber
12699 + fixp->fx_next->fx_frag->fr_address
12700 + fixp->fx_next->fx_where);
12703 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12704 reloc->addend = fixp->fx_addnumber;
12707 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12708 /* A gruesome hack which is a result of the gruesome gas reloc
12710 reloc->addend = reloc->address;
12712 reloc->addend = -reloc->address;
12715 /* If this is a variant frag, we may need to adjust the existing
12716 reloc and generate a new one. */
12717 if (fixp->fx_frag->fr_opcode != NULL
12718 && ((fixp->fx_r_type == BFD_RELOC_GPREL16
12720 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12721 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12722 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12723 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12724 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12725 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12730 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12732 /* If this is not the last reloc in this frag, then we have two
12733 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12734 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12735 the second one handle all of them. */
12736 if (fixp->fx_next != NULL
12737 && fixp->fx_frag == fixp->fx_next->fx_frag)
12739 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12740 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12741 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12742 && (fixp->fx_next->fx_r_type
12743 == BFD_RELOC_MIPS_GOT_LO16))
12744 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12745 && (fixp->fx_next->fx_r_type
12746 == BFD_RELOC_MIPS_CALL_LO16)));
12751 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12752 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12753 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12755 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12756 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12757 reloc2->address = (reloc->address
12758 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12759 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12760 reloc2->addend = fixp->fx_addnumber;
12761 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12762 assert (reloc2->howto != NULL);
12764 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12768 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12771 reloc3->address += 4;
12774 if (mips_pic == NO_PIC)
12776 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12777 fixp->fx_r_type = BFD_RELOC_HI16_S;
12779 else if (mips_pic == SVR4_PIC)
12781 switch (fixp->fx_r_type)
12785 case BFD_RELOC_MIPS_GOT16:
12787 case BFD_RELOC_MIPS_GOT_LO16:
12788 case BFD_RELOC_MIPS_CALL_LO16:
12789 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12791 case BFD_RELOC_MIPS_CALL16:
12794 /* BFD_RELOC_MIPS_GOT16;*/
12795 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE;
12796 reloc2->howto = bfd_reloc_type_lookup
12797 (stdoutput, BFD_RELOC_MIPS_GOT_OFST);
12800 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12807 /* newabi uses R_MIPS_GOT_DISP for local symbols */
12808 if (HAVE_NEWABI && BFD_RELOC_MIPS_GOT_LO16)
12810 fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP;
12815 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12816 entry to be used in the relocation's section offset. */
12817 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12819 reloc->address = reloc->addend;
12823 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12824 fixup_segment converted a non-PC relative reloc into a PC
12825 relative reloc. In such a case, we need to convert the reloc
12827 code = fixp->fx_r_type;
12828 if (fixp->fx_pcrel)
12833 code = BFD_RELOC_8_PCREL;
12836 code = BFD_RELOC_16_PCREL;
12839 code = BFD_RELOC_32_PCREL;
12842 code = BFD_RELOC_64_PCREL;
12844 case BFD_RELOC_8_PCREL:
12845 case BFD_RELOC_16_PCREL:
12846 case BFD_RELOC_32_PCREL:
12847 case BFD_RELOC_64_PCREL:
12848 case BFD_RELOC_16_PCREL_S2:
12849 case BFD_RELOC_PCREL_HI16_S:
12850 case BFD_RELOC_PCREL_LO16:
12853 as_bad_where (fixp->fx_file, fixp->fx_line,
12854 _("Cannot make %s relocation PC relative"),
12855 bfd_get_reloc_code_name (code));
12860 /* md_apply_fix3 has a double-subtraction hack to get
12861 bfd_install_relocation to behave nicely. GPREL relocations are
12862 handled correctly without this hack, so undo it here. We can't
12863 stop md_apply_fix3 from subtracting twice in the first place since
12864 the fake addend is required for variant frags above. */
12865 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12866 && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL)
12867 && reloc->addend != 0
12868 && mips_need_elf_addend_fixup (fixp))
12869 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12872 /* To support a PC relative reloc when generating embedded PIC code
12873 for ECOFF, we use a Cygnus extension. We check for that here to
12874 make sure that we don't let such a reloc escape normally. */
12875 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12876 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12877 && code == BFD_RELOC_16_PCREL_S2
12878 && mips_pic != EMBEDDED_PIC)
12879 reloc->howto = NULL;
12881 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12883 if (reloc->howto == NULL)
12885 as_bad_where (fixp->fx_file, fixp->fx_line,
12886 _("Can not represent %s relocation in this object file format"),
12887 bfd_get_reloc_code_name (code));
12894 /* Relax a machine dependent frag. This returns the amount by which
12895 the current size of the frag should change. */
12898 mips_relax_frag (fragp, stretch)
12902 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12905 if (mips16_extended_frag (fragp, NULL, stretch))
12907 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12909 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12914 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12916 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12923 /* Convert a machine dependent frag. */
12926 md_convert_frag (abfd, asec, fragp)
12927 bfd *abfd ATTRIBUTE_UNUSED;
12934 if (RELAX_MIPS16_P (fragp->fr_subtype))
12937 register const struct mips16_immed_operand *op;
12938 boolean small, ext;
12941 unsigned long insn;
12942 boolean use_extend;
12943 unsigned short extend;
12945 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12946 op = mips16_immed_operands;
12947 while (op->type != type)
12950 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12961 resolve_symbol_value (fragp->fr_symbol);
12962 val = S_GET_VALUE (fragp->fr_symbol);
12967 addr = fragp->fr_address + fragp->fr_fix;
12969 /* The rules for the base address of a PC relative reloc are
12970 complicated; see mips16_extended_frag. */
12971 if (type == 'p' || type == 'q')
12976 /* Ignore the low bit in the target, since it will be
12977 set for a text label. */
12978 if ((val & 1) != 0)
12981 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12983 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12986 addr &= ~ (addressT) ((1 << op->shift) - 1);
12989 /* Make sure the section winds up with the alignment we have
12992 record_alignment (asec, op->shift);
12996 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
12997 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
12998 as_warn_where (fragp->fr_file, fragp->fr_line,
12999 _("extended instruction in delay slot"));
13001 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13003 if (target_big_endian)
13004 insn = bfd_getb16 (buf);
13006 insn = bfd_getl16 (buf);
13008 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13009 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13010 small, ext, &insn, &use_extend, &extend);
13014 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13015 fragp->fr_fix += 2;
13019 md_number_to_chars ((char *) buf, insn, 2);
13020 fragp->fr_fix += 2;
13025 if (fragp->fr_opcode == NULL)
13028 old = RELAX_OLD (fragp->fr_subtype);
13029 new = RELAX_NEW (fragp->fr_subtype);
13030 fixptr = fragp->fr_literal + fragp->fr_fix;
13033 memcpy (fixptr - old, fixptr, new);
13035 fragp->fr_fix += new - old;
13041 /* This function is called after the relocs have been generated.
13042 We've been storing mips16 text labels as odd. Here we convert them
13043 back to even for the convenience of the debugger. */
13046 mips_frob_file_after_relocs ()
13049 unsigned int count, i;
13051 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13054 syms = bfd_get_outsymbols (stdoutput);
13055 count = bfd_get_symcount (stdoutput);
13056 for (i = 0; i < count; i++, syms++)
13058 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13059 && ((*syms)->value & 1) != 0)
13061 (*syms)->value &= ~1;
13062 /* If the symbol has an odd size, it was probably computed
13063 incorrectly, so adjust that as well. */
13064 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13065 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13072 /* This function is called whenever a label is defined. It is used
13073 when handling branch delays; if a branch has a label, we assume we
13074 can not move it. */
13077 mips_define_label (sym)
13080 struct insn_label_list *l;
13082 if (free_insn_labels == NULL)
13083 l = (struct insn_label_list *) xmalloc (sizeof *l);
13086 l = free_insn_labels;
13087 free_insn_labels = l->next;
13091 l->next = insn_labels;
13095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13097 /* Some special processing for a MIPS ELF file. */
13100 mips_elf_final_processing ()
13102 /* Write out the register information. */
13103 if (mips_abi != N64_ABI)
13107 s.ri_gprmask = mips_gprmask;
13108 s.ri_cprmask[0] = mips_cprmask[0];
13109 s.ri_cprmask[1] = mips_cprmask[1];
13110 s.ri_cprmask[2] = mips_cprmask[2];
13111 s.ri_cprmask[3] = mips_cprmask[3];
13112 /* The gp_value field is set by the MIPS ELF backend. */
13114 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13115 ((Elf32_External_RegInfo *)
13116 mips_regmask_frag));
13120 Elf64_Internal_RegInfo s;
13122 s.ri_gprmask = mips_gprmask;
13124 s.ri_cprmask[0] = mips_cprmask[0];
13125 s.ri_cprmask[1] = mips_cprmask[1];
13126 s.ri_cprmask[2] = mips_cprmask[2];
13127 s.ri_cprmask[3] = mips_cprmask[3];
13128 /* The gp_value field is set by the MIPS ELF backend. */
13130 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13131 ((Elf64_External_RegInfo *)
13132 mips_regmask_frag));
13135 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13136 sort of BFD interface for this. */
13137 if (mips_any_noreorder)
13138 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13139 if (mips_pic != NO_PIC)
13140 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13142 /* Set MIPS ELF flags for ASEs. */
13143 if (file_ase_mips16)
13144 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13145 #if 0 /* XXX FIXME */
13146 if (file_ase_mips3d)
13147 elf_elfheader (stdoutput)->e_flags |= ???;
13150 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13152 /* Set the MIPS ELF ABI flags. */
13153 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13154 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13155 else if (mips_abi == O64_ABI)
13156 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13157 else if (mips_abi == EABI_ABI)
13159 if (!file_mips_gp32)
13160 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13162 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13164 else if (mips_abi == N32_ABI)
13165 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13167 /* Nothing to do for N64_ABI. */
13169 if (mips_32bitmode)
13170 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13173 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13175 typedef struct proc {
13177 unsigned long reg_mask;
13178 unsigned long reg_offset;
13179 unsigned long fpreg_mask;
13180 unsigned long fpreg_offset;
13181 unsigned long frame_offset;
13182 unsigned long frame_reg;
13183 unsigned long pc_reg;
13186 static procS cur_proc;
13187 static procS *cur_proc_ptr;
13188 static int numprocs;
13190 /* Fill in an rs_align_code fragment. */
13193 mips_handle_align (fragp)
13196 if (fragp->fr_type != rs_align_code)
13199 if (mips_opts.mips16)
13201 static const unsigned char be_nop[] = { 0x65, 0x00 };
13202 static const unsigned char le_nop[] = { 0x00, 0x65 };
13207 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13208 p = fragp->fr_literal + fragp->fr_fix;
13216 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13220 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13231 /* check for premature end, nesting errors, etc */
13233 as_warn (_("missing .end at end of assembly"));
13242 if (*input_line_pointer == '-')
13244 ++input_line_pointer;
13247 if (!ISDIGIT (*input_line_pointer))
13248 as_bad (_("expected simple number"));
13249 if (input_line_pointer[0] == '0')
13251 if (input_line_pointer[1] == 'x')
13253 input_line_pointer += 2;
13254 while (ISXDIGIT (*input_line_pointer))
13257 val |= hex_value (*input_line_pointer++);
13259 return negative ? -val : val;
13263 ++input_line_pointer;
13264 while (ISDIGIT (*input_line_pointer))
13267 val |= *input_line_pointer++ - '0';
13269 return negative ? -val : val;
13272 if (!ISDIGIT (*input_line_pointer))
13274 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13275 *input_line_pointer, *input_line_pointer);
13276 as_warn (_("invalid number"));
13279 while (ISDIGIT (*input_line_pointer))
13282 val += *input_line_pointer++ - '0';
13284 return negative ? -val : val;
13287 /* The .file directive; just like the usual .file directive, but there
13288 is an initial number which is the ECOFF file index. In the non-ECOFF
13289 case .file implies DWARF-2. */
13293 int x ATTRIBUTE_UNUSED;
13295 static int first_file_directive = 0;
13297 if (ECOFF_DEBUGGING)
13306 filename = dwarf2_directive_file (0);
13308 /* Versions of GCC up to 3.1 start files with a ".file"
13309 directive even for stabs output. Make sure that this
13310 ".file" is handled. Note that you need a version of GCC
13311 after 3.1 in order to support DWARF-2 on MIPS. */
13312 if (filename != NULL && ! first_file_directive)
13314 (void) new_logical_line (filename, -1);
13315 s_app_file_string (filename);
13317 first_file_directive = 1;
13321 /* The .loc directive, implying DWARF-2. */
13325 int x ATTRIBUTE_UNUSED;
13327 if (!ECOFF_DEBUGGING)
13328 dwarf2_directive_loc (0);
13331 /* The .end directive. */
13335 int x ATTRIBUTE_UNUSED;
13340 /* Following functions need their own .frame and .cprestore directives. */
13341 mips_frame_reg_valid = 0;
13342 mips_cprestore_valid = 0;
13344 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13347 demand_empty_rest_of_line ();
13352 #ifdef BFD_ASSEMBLER
13353 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13358 if (now_seg != data_section && now_seg != bss_section)
13365 as_warn (_(".end not in text section"));
13369 as_warn (_(".end directive without a preceding .ent directive."));
13370 demand_empty_rest_of_line ();
13376 assert (S_GET_NAME (p));
13377 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13378 as_warn (_(".end symbol does not match .ent symbol."));
13380 if (debug_type == DEBUG_STABS)
13381 stabs_generate_asm_endfunc (S_GET_NAME (p),
13385 as_warn (_(".end directive missing or unknown symbol"));
13388 /* Generate a .pdr section. */
13389 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13391 segT saved_seg = now_seg;
13392 subsegT saved_subseg = now_subseg;
13397 dot = frag_now_fix ();
13399 #ifdef md_flush_pending_output
13400 md_flush_pending_output ();
13404 subseg_set (pdr_seg, 0);
13406 /* Write the symbol. */
13407 exp.X_op = O_symbol;
13408 exp.X_add_symbol = p;
13409 exp.X_add_number = 0;
13410 emit_expr (&exp, 4);
13412 fragp = frag_more (7 * 4);
13414 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13415 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13416 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13417 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13418 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13419 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13420 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13422 subseg_set (saved_seg, saved_subseg);
13424 #endif /* OBJ_ELF */
13426 cur_proc_ptr = NULL;
13429 /* The .aent and .ent directives. */
13438 symbolP = get_symbol ();
13439 if (*input_line_pointer == ',')
13440 ++input_line_pointer;
13441 SKIP_WHITESPACE ();
13442 if (ISDIGIT (*input_line_pointer)
13443 || *input_line_pointer == '-')
13446 #ifdef BFD_ASSEMBLER
13447 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13452 if (now_seg != data_section && now_seg != bss_section)
13459 as_warn (_(".ent or .aent not in text section."));
13461 if (!aent && cur_proc_ptr)
13462 as_warn (_("missing .end"));
13466 /* This function needs its own .frame and .cprestore directives. */
13467 mips_frame_reg_valid = 0;
13468 mips_cprestore_valid = 0;
13470 cur_proc_ptr = &cur_proc;
13471 memset (cur_proc_ptr, '\0', sizeof (procS));
13473 cur_proc_ptr->isym = symbolP;
13475 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13479 if (debug_type == DEBUG_STABS)
13480 stabs_generate_asm_func (S_GET_NAME (symbolP),
13481 S_GET_NAME (symbolP));
13484 demand_empty_rest_of_line ();
13487 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13488 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13489 s_mips_frame is used so that we can set the PDR information correctly.
13490 We can't use the ecoff routines because they make reference to the ecoff
13491 symbol table (in the mdebug section). */
13494 s_mips_frame (ignore)
13495 int ignore ATTRIBUTE_UNUSED;
13498 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13502 if (cur_proc_ptr == (procS *) NULL)
13504 as_warn (_(".frame outside of .ent"));
13505 demand_empty_rest_of_line ();
13509 cur_proc_ptr->frame_reg = tc_get_register (1);
13511 SKIP_WHITESPACE ();
13512 if (*input_line_pointer++ != ','
13513 || get_absolute_expression_and_terminator (&val) != ',')
13515 as_warn (_("Bad .frame directive"));
13516 --input_line_pointer;
13517 demand_empty_rest_of_line ();
13521 cur_proc_ptr->frame_offset = val;
13522 cur_proc_ptr->pc_reg = tc_get_register (0);
13524 demand_empty_rest_of_line ();
13527 #endif /* OBJ_ELF */
13531 /* The .fmask and .mask directives. If the mdebug section is present
13532 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13533 embedded targets, s_mips_mask is used so that we can set the PDR
13534 information correctly. We can't use the ecoff routines because they
13535 make reference to the ecoff symbol table (in the mdebug section). */
13538 s_mips_mask (reg_type)
13542 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
13546 if (cur_proc_ptr == (procS *) NULL)
13548 as_warn (_(".mask/.fmask outside of .ent"));
13549 demand_empty_rest_of_line ();
13553 if (get_absolute_expression_and_terminator (&mask) != ',')
13555 as_warn (_("Bad .mask/.fmask directive"));
13556 --input_line_pointer;
13557 demand_empty_rest_of_line ();
13561 off = get_absolute_expression ();
13563 if (reg_type == 'F')
13565 cur_proc_ptr->fpreg_mask = mask;
13566 cur_proc_ptr->fpreg_offset = off;
13570 cur_proc_ptr->reg_mask = mask;
13571 cur_proc_ptr->reg_offset = off;
13574 demand_empty_rest_of_line ();
13577 #endif /* OBJ_ELF */
13578 s_ignore (reg_type);
13581 /* The .loc directive. */
13592 assert (now_seg == text_section);
13594 lineno = get_number ();
13595 addroff = frag_now_fix ();
13597 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13598 S_SET_TYPE (symbolP, N_SLINE);
13599 S_SET_OTHER (symbolP, 0);
13600 S_SET_DESC (symbolP, lineno);
13601 symbolP->sy_segment = now_seg;
13605 /* A table describing all the processors gas knows about. Names are
13606 matched in the order listed.
13608 To ease comparison, please keep this table in the same order as
13609 gcc's mips_cpu_info_table[]. */
13610 static const struct mips_cpu_info mips_cpu_info_table[] =
13612 /* Entries for generic ISAs */
13613 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
13614 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
13615 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
13616 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
13617 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
13618 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
13619 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
13622 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
13623 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
13624 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
13627 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
13630 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
13631 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
13632 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
13633 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
13634 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
13635 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
13636 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
13637 { "orion", 0, ISA_MIPS3, CPU_R4600 },
13638 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
13641 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
13642 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
13643 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
13644 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
13645 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
13646 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
13647 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
13648 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
13649 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
13650 { "r7000", 0, ISA_MIPS4, CPU_R5000 },
13653 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13654 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
13655 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
13658 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
13659 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
13661 /* Broadcom SB-1 CPU core */
13662 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
13669 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13670 with a final "000" replaced by "k". Ignore case.
13672 Note: this function is shared between GCC and GAS. */
13675 mips_strict_matching_cpu_name_p (canonical, given)
13676 const char *canonical, *given;
13678 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
13679 given++, canonical++;
13681 return ((*given == 0 && *canonical == 0)
13682 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
13686 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13687 CPU name. We've traditionally allowed a lot of variation here.
13689 Note: this function is shared between GCC and GAS. */
13692 mips_matching_cpu_name_p (canonical, given)
13693 const char *canonical, *given;
13695 /* First see if the name matches exactly, or with a final "000"
13696 turned into "k". */
13697 if (mips_strict_matching_cpu_name_p (canonical, given))
13700 /* If not, try comparing based on numerical designation alone.
13701 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13702 if (TOLOWER (*given) == 'r')
13704 if (!ISDIGIT (*given))
13707 /* Skip over some well-known prefixes in the canonical name,
13708 hoping to find a number there too. */
13709 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
13711 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
13713 else if (TOLOWER (canonical[0]) == 'r')
13716 return mips_strict_matching_cpu_name_p (canonical, given);
13720 /* Parse an option that takes the name of a processor as its argument.
13721 OPTION is the name of the option and CPU_STRING is the argument.
13722 Return the corresponding processor enumeration if the CPU_STRING is
13723 recognized, otherwise report an error and return null.
13725 A similar function exists in GCC. */
13727 static const struct mips_cpu_info *
13728 mips_parse_cpu (option, cpu_string)
13729 const char *option, *cpu_string;
13731 const struct mips_cpu_info *p;
13733 /* 'from-abi' selects the most compatible architecture for the given
13734 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13735 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13736 version. Look first at the -mgp options, if given, otherwise base
13737 the choice on MIPS_DEFAULT_64BIT.
13739 Treat NO_ABI like the EABIs. One reason to do this is that the
13740 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13741 architecture. This code picks MIPS I for 'mips' and MIPS III for
13742 'mips64', just as we did in the days before 'from-abi'. */
13743 if (strcasecmp (cpu_string, "from-abi") == 0)
13745 if (ABI_NEEDS_32BIT_REGS (mips_abi))
13746 return mips_cpu_info_from_isa (ISA_MIPS1);
13748 if (ABI_NEEDS_64BIT_REGS (mips_abi))
13749 return mips_cpu_info_from_isa (ISA_MIPS3);
13751 if (file_mips_gp32 >= 0)
13752 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
13754 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13759 /* 'default' has traditionally been a no-op. Probably not very useful. */
13760 if (strcasecmp (cpu_string, "default") == 0)
13763 for (p = mips_cpu_info_table; p->name != 0; p++)
13764 if (mips_matching_cpu_name_p (p->name, cpu_string))
13767 as_bad ("Bad value (%s) for %s", cpu_string, option);
13771 /* Return the canonical processor information for ISA (a member of the
13772 ISA_MIPS* enumeration). */
13774 static const struct mips_cpu_info *
13775 mips_cpu_info_from_isa (isa)
13780 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13781 if (mips_cpu_info_table[i].is_isa
13782 && isa == mips_cpu_info_table[i].isa)
13783 return (&mips_cpu_info_table[i]);
13789 show (stream, string, col_p, first_p)
13791 const char *string;
13797 fprintf (stream, "%24s", "");
13802 fprintf (stream, ", ");
13806 if (*col_p + strlen (string) > 72)
13808 fprintf (stream, "\n%24s", "");
13812 fprintf (stream, "%s", string);
13813 *col_p += strlen (string);
13819 md_show_usage (stream)
13825 fprintf (stream, _("\
13827 -membedded-pic generate embedded position independent code\n\
13828 -EB generate big endian output\n\
13829 -EL generate little endian output\n\
13830 -g, -g2 do not remove unneeded NOPs or swap branches\n\
13831 -G NUM allow referencing objects up to NUM bytes\n\
13832 implicitly with the gp register [default 8]\n"));
13833 fprintf (stream, _("\
13834 -mips1 generate MIPS ISA I instructions\n\
13835 -mips2 generate MIPS ISA II instructions\n\
13836 -mips3 generate MIPS ISA III instructions\n\
13837 -mips4 generate MIPS ISA IV instructions\n\
13838 -mips5 generate MIPS ISA V instructions\n\
13839 -mips32 generate MIPS32 ISA instructions\n\
13840 -mips64 generate MIPS64 ISA instructions\n\
13841 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
13845 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13846 show (stream, mips_cpu_info_table[i].name, &column, &first);
13847 show (stream, "from-abi", &column, &first);
13848 fputc ('\n', stream);
13850 fprintf (stream, _("\
13851 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
13852 -no-mCPU don't generate code specific to CPU.\n\
13853 For -mCPU and -no-mCPU, CPU must be one of:\n"));
13857 show (stream, "3900", &column, &first);
13858 show (stream, "4010", &column, &first);
13859 show (stream, "4100", &column, &first);
13860 show (stream, "4650", &column, &first);
13861 fputc ('\n', stream);
13863 fprintf (stream, _("\
13864 -mips16 generate mips16 instructions\n\
13865 -no-mips16 do not generate mips16 instructions\n"));
13866 fprintf (stream, _("\
13867 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
13868 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
13869 -O0 remove unneeded NOPs, do not swap branches\n\
13870 -O remove unneeded NOPs and swap branches\n\
13871 -n warn about NOPs generated from macros\n\
13872 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
13873 --trap, --no-break trap exception on div by 0 and mult overflow\n\
13874 --break, --no-trap break exception on div by 0 and mult overflow\n"));
13876 fprintf (stream, _("\
13877 -KPIC, -call_shared generate SVR4 position independent code\n\
13878 -non_shared do not generate position independent code\n\
13879 -xgot assume a 32 bit GOT\n\
13880 -mabi=ABI create ABI conformant object file for:\n"));
13884 show (stream, "32", &column, &first);
13885 show (stream, "o64", &column, &first);
13886 show (stream, "n32", &column, &first);
13887 show (stream, "64", &column, &first);
13888 show (stream, "eabi", &column, &first);
13890 fputc ('\n', stream);
13892 fprintf (stream, _("\
13893 -32 create o32 ABI object file (default)\n\
13894 -n32 create n32 ABI object file\n\
13895 -64 create 64 ABI object file\n"));