1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32 = -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32 = -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float = 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float = 0;
275 static struct mips_set_options mips_opts =
277 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
278 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
279 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
280 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
281 /* soft_float */ FALSE, /* single_float */ FALSE
284 /* The set of ASEs that were selected on the command line, either
285 explicitly via ASE options or implicitly through things like -march. */
286 static unsigned int file_ase;
288 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
289 static unsigned int file_ase_explicit;
291 /* These variables are filled in with the masks of registers used.
292 The object format code reads them and puts them in the appropriate
294 unsigned long mips_gprmask;
295 unsigned long mips_cprmask[4];
297 /* MIPS ISA we are using for this output file. */
298 static int file_mips_isa = ISA_UNKNOWN;
300 /* True if any MIPS16 code was produced. */
301 static int file_ase_mips16;
303 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
304 || mips_opts.isa == ISA_MIPS32R2 \
305 || mips_opts.isa == ISA_MIPS64 \
306 || mips_opts.isa == ISA_MIPS64R2)
308 /* True if any microMIPS code was produced. */
309 static int file_ase_micromips;
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* The argument of the -march= flag. The architecture we are assembling. */
324 static int file_mips_arch = CPU_UNKNOWN;
325 static const char *mips_arch_string;
327 /* The argument of the -mtune= flag. The architecture for which we
329 static int mips_tune = CPU_UNKNOWN;
330 static const char *mips_tune_string;
332 /* True when generating 32-bit code for a 64-bit processor. */
333 static int mips_32bitmode = 0;
335 /* True if the given ABI requires 32-bit registers. */
336 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
338 /* Likewise 64-bit registers. */
339 #define ABI_NEEDS_64BIT_REGS(ABI) \
341 || (ABI) == N64_ABI \
344 /* Return true if ISA supports 64 bit wide gp registers. */
345 #define ISA_HAS_64BIT_REGS(ISA) \
346 ((ISA) == ISA_MIPS3 \
347 || (ISA) == ISA_MIPS4 \
348 || (ISA) == ISA_MIPS5 \
349 || (ISA) == ISA_MIPS64 \
350 || (ISA) == ISA_MIPS64R2)
352 /* Return true if ISA supports 64 bit wide float registers. */
353 #define ISA_HAS_64BIT_FPRS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS32R2 \
358 || (ISA) == ISA_MIPS64 \
359 || (ISA) == ISA_MIPS64R2)
361 /* Return true if ISA supports 64-bit right rotate (dror et al.)
363 #define ISA_HAS_DROR(ISA) \
364 ((ISA) == ISA_MIPS64R2 \
365 || (mips_opts.micromips \
366 && ISA_HAS_64BIT_REGS (ISA)) \
369 /* Return true if ISA supports 32-bit right rotate (ror et al.)
371 #define ISA_HAS_ROR(ISA) \
372 ((ISA) == ISA_MIPS32R2 \
373 || (ISA) == ISA_MIPS64R2 \
374 || (mips_opts.ase & ASE_SMARTMIPS) \
375 || mips_opts.micromips \
378 /* Return true if ISA supports single-precision floats in odd registers. */
379 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
380 ((ISA) == ISA_MIPS32 \
381 || (ISA) == ISA_MIPS32R2 \
382 || (ISA) == ISA_MIPS64 \
383 || (ISA) == ISA_MIPS64R2)
385 /* Return true if ISA supports move to/from high part of a 64-bit
386 floating-point register. */
387 #define ISA_HAS_MXHC1(ISA) \
388 ((ISA) == ISA_MIPS32R2 \
389 || (ISA) == ISA_MIPS64R2)
391 #define HAVE_32BIT_GPRS \
392 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
394 #define HAVE_32BIT_FPRS \
395 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
397 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
398 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
400 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
402 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
404 /* True if relocations are stored in-place. */
405 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
407 /* The ABI-derived address size. */
408 #define HAVE_64BIT_ADDRESSES \
409 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
410 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
412 /* The size of symbolic constants (i.e., expressions of the form
413 "SYMBOL" or "SYMBOL + OFFSET"). */
414 #define HAVE_32BIT_SYMBOLS \
415 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
416 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
418 /* Addresses are loaded in different ways, depending on the address size
419 in use. The n32 ABI Documentation also mandates the use of additions
420 with overflow checking, but existing implementations don't follow it. */
421 #define ADDRESS_ADD_INSN \
422 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
424 #define ADDRESS_ADDI_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
427 #define ADDRESS_LOAD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
430 #define ADDRESS_STORE_INSN \
431 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
433 /* Return true if the given CPU supports the MIPS16 ASE. */
434 #define CPU_HAS_MIPS16(cpu) \
435 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
436 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
438 /* Return true if the given CPU supports the microMIPS ASE. */
439 #define CPU_HAS_MICROMIPS(cpu) 0
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU is in the Octeon family */
448 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
450 /* True if CPU has seq/sne and seqi/snei instructions. */
451 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
453 /* True, if CPU has support for ldc1 and sdc1. */
454 #define CPU_HAS_LDC1_SDC1(CPU) \
455 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
457 /* True if mflo and mfhi can be immediately followed by instructions
458 which write to the HI and LO registers.
460 According to MIPS specifications, MIPS ISAs I, II, and III need
461 (at least) two instructions between the reads of HI/LO and
462 instructions which write them, and later ISAs do not. Contradicting
463 the MIPS specifications, some MIPS IV processor user manuals (e.g.
464 the UM for the NEC Vr5000) document needing the instructions between
465 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
466 MIPS64 and later ISAs to have the interlocks, plus any specific
467 earlier-ISA CPUs for which CPU documentation declares that the
468 instructions are really interlocked. */
469 #define hilo_interlocks \
470 (mips_opts.isa == ISA_MIPS32 \
471 || mips_opts.isa == ISA_MIPS32R2 \
472 || mips_opts.isa == ISA_MIPS64 \
473 || mips_opts.isa == ISA_MIPS64R2 \
474 || mips_opts.arch == CPU_R4010 \
475 || mips_opts.arch == CPU_R5900 \
476 || mips_opts.arch == CPU_R10000 \
477 || mips_opts.arch == CPU_R12000 \
478 || mips_opts.arch == CPU_R14000 \
479 || mips_opts.arch == CPU_R16000 \
480 || mips_opts.arch == CPU_RM7000 \
481 || mips_opts.arch == CPU_VR5500 \
482 || mips_opts.micromips \
485 /* Whether the processor uses hardware interlocks to protect reads
486 from the GPRs after they are loaded from memory, and thus does not
487 require nops to be inserted. This applies to instructions marked
488 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
489 level I and microMIPS mode instructions are always interlocked. */
490 #define gpr_interlocks \
491 (mips_opts.isa != ISA_MIPS1 \
492 || mips_opts.arch == CPU_R3900 \
493 || mips_opts.arch == CPU_R5900 \
494 || mips_opts.micromips \
497 /* Whether the processor uses hardware interlocks to avoid delays
498 required by coprocessor instructions, and thus does not require
499 nops to be inserted. This applies to instructions marked
500 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
501 between instructions marked INSN_WRITE_COND_CODE and ones marked
502 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
503 levels I, II, and III and microMIPS mode instructions are always
505 /* Itbl support may require additional care here. */
506 #define cop_interlocks \
507 ((mips_opts.isa != ISA_MIPS1 \
508 && mips_opts.isa != ISA_MIPS2 \
509 && mips_opts.isa != ISA_MIPS3) \
510 || mips_opts.arch == CPU_R4300 \
511 || mips_opts.micromips \
514 /* Whether the processor uses hardware interlocks to protect reads
515 from coprocessor registers after they are loaded from memory, and
516 thus does not require nops to be inserted. This applies to
517 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
518 requires at MIPS ISA level I and microMIPS mode instructions are
519 always interlocked. */
520 #define cop_mem_interlocks \
521 (mips_opts.isa != ISA_MIPS1 \
522 || mips_opts.micromips \
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
530 has been selected. This implies, in particular, that addresses of text
531 labels have their LSB set. */
532 #define HAVE_CODE_COMPRESSION \
533 ((mips_opts.mips16 | mips_opts.micromips) != 0)
535 /* The minimum and maximum signed values that can be stored in a GPR. */
536 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
537 #define GPR_SMIN (-GPR_SMAX - 1)
539 /* MIPS PIC level. */
541 enum mips_pic_level mips_pic;
543 /* 1 if we should generate 32 bit offsets from the $gp register in
544 SVR4_PIC mode. Currently has no meaning in other modes. */
545 static int mips_big_got = 0;
547 /* 1 if trap instructions should used for overflow rather than break
549 static int mips_trap = 0;
551 /* 1 if double width floating point constants should not be constructed
552 by assembling two single width halves into two single width floating
553 point registers which just happen to alias the double width destination
554 register. On some architectures this aliasing can be disabled by a bit
555 in the status register, and the setting of this bit cannot be determined
556 automatically at assemble time. */
557 static int mips_disable_float_construction;
559 /* Non-zero if any .set noreorder directives were used. */
561 static int mips_any_noreorder;
563 /* Non-zero if nops should be inserted when the register referenced in
564 an mfhi/mflo instruction is read in the next two instructions. */
565 static int mips_7000_hilo_fix;
567 /* The size of objects in the small data section. */
568 static unsigned int g_switch_value = 8;
569 /* Whether the -G option was used. */
570 static int g_switch_seen = 0;
575 /* If we can determine in advance that GP optimization won't be
576 possible, we can skip the relaxation stuff that tries to produce
577 GP-relative references. This makes delay slot optimization work
580 This function can only provide a guess, but it seems to work for
581 gcc output. It needs to guess right for gcc, otherwise gcc
582 will put what it thinks is a GP-relative instruction in a branch
585 I don't know if a fix is needed for the SVR4_PIC mode. I've only
586 fixed it for the non-PIC mode. KR 95/04/07 */
587 static int nopic_need_relax (symbolS *, int);
589 /* handle of the OPCODE hash table */
590 static struct hash_control *op_hash = NULL;
592 /* The opcode hash table we use for the mips16. */
593 static struct hash_control *mips16_op_hash = NULL;
595 /* The opcode hash table we use for the microMIPS ASE. */
596 static struct hash_control *micromips_op_hash = NULL;
598 /* This array holds the chars that always start a comment. If the
599 pre-processor is disabled, these aren't very useful */
600 const char comment_chars[] = "#";
602 /* This array holds the chars that only start a comment at the beginning of
603 a line. If the line seems to have the form '# 123 filename'
604 .line and .file directives will appear in the pre-processed output */
605 /* Note that input_file.c hand checks for '#' at the beginning of the
606 first line of the input file. This is because the compiler outputs
607 #NO_APP at the beginning of its output. */
608 /* Also note that C style comments are always supported. */
609 const char line_comment_chars[] = "#";
611 /* This array holds machine specific line separator characters. */
612 const char line_separator_chars[] = ";";
614 /* Chars that can be used to separate mant from exp in floating point nums */
615 const char EXP_CHARS[] = "eE";
617 /* Chars that mean this number is a floating point constant */
620 const char FLT_CHARS[] = "rRsSfFdDxXpP";
622 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
623 changed in read.c . Ideally it shouldn't have to know about it at all,
624 but nothing is ideal around here.
627 static char *insn_error;
629 static int auto_align = 1;
631 /* When outputting SVR4 PIC code, the assembler needs to know the
632 offset in the stack frame from which to restore the $gp register.
633 This is set by the .cprestore pseudo-op, and saved in this
635 static offsetT mips_cprestore_offset = -1;
637 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
638 more optimizations, it can use a register value instead of a memory-saved
639 offset and even an other register than $gp as global pointer. */
640 static offsetT mips_cpreturn_offset = -1;
641 static int mips_cpreturn_register = -1;
642 static int mips_gp_register = GP;
643 static int mips_gprel_offset = 0;
645 /* Whether mips_cprestore_offset has been set in the current function
646 (or whether it has already been warned about, if not). */
647 static int mips_cprestore_valid = 0;
649 /* This is the register which holds the stack frame, as set by the
650 .frame pseudo-op. This is needed to implement .cprestore. */
651 static int mips_frame_reg = SP;
653 /* Whether mips_frame_reg has been set in the current function
654 (or whether it has already been warned about, if not). */
655 static int mips_frame_reg_valid = 0;
657 /* To output NOP instructions correctly, we need to keep information
658 about the previous two instructions. */
660 /* Whether we are optimizing. The default value of 2 means to remove
661 unneeded NOPs and swap branch instructions when possible. A value
662 of 1 means to not swap branches. A value of 0 means to always
664 static int mips_optimize = 2;
666 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
667 equivalent to seeing no -g option at all. */
668 static int mips_debug = 0;
670 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
671 #define MAX_VR4130_NOPS 4
673 /* The maximum number of NOPs needed to fill delay slots. */
674 #define MAX_DELAY_NOPS 2
676 /* The maximum number of NOPs needed for any purpose. */
679 /* A list of previous instructions, with index 0 being the most recent.
680 We need to look back MAX_NOPS instructions when filling delay slots
681 or working around processor errata. We need to look back one
682 instruction further if we're thinking about using history[0] to
683 fill a branch delay slot. */
684 static struct mips_cl_insn history[1 + MAX_NOPS];
686 /* Nop instructions used by emit_nop. */
687 static struct mips_cl_insn nop_insn;
688 static struct mips_cl_insn mips16_nop_insn;
689 static struct mips_cl_insn micromips_nop16_insn;
690 static struct mips_cl_insn micromips_nop32_insn;
692 /* The appropriate nop for the current mode. */
693 #define NOP_INSN (mips_opts.mips16 \
695 : (mips_opts.micromips \
696 ? (mips_opts.insn32 \
697 ? µmips_nop32_insn \
698 : µmips_nop16_insn) \
701 /* The size of NOP_INSN in bytes. */
702 #define NOP_INSN_SIZE ((mips_opts.mips16 \
703 || (mips_opts.micromips && !mips_opts.insn32)) \
706 /* If this is set, it points to a frag holding nop instructions which
707 were inserted before the start of a noreorder section. If those
708 nops turn out to be unnecessary, the size of the frag can be
710 static fragS *prev_nop_frag;
712 /* The number of nop instructions we created in prev_nop_frag. */
713 static int prev_nop_frag_holds;
715 /* The number of nop instructions that we know we need in
717 static int prev_nop_frag_required;
719 /* The number of instructions we've seen since prev_nop_frag. */
720 static int prev_nop_frag_since;
722 /* Relocations against symbols are sometimes done in two parts, with a HI
723 relocation and a LO relocation. Each relocation has only 16 bits of
724 space to store an addend. This means that in order for the linker to
725 handle carries correctly, it must be able to locate both the HI and
726 the LO relocation. This means that the relocations must appear in
727 order in the relocation table.
729 In order to implement this, we keep track of each unmatched HI
730 relocation. We then sort them so that they immediately precede the
731 corresponding LO relocation. */
736 struct mips_hi_fixup *next;
739 /* The section this fixup is in. */
743 /* The list of unmatched HI relocs. */
745 static struct mips_hi_fixup *mips_hi_fixup_list;
747 /* The frag containing the last explicit relocation operator.
748 Null if explicit relocations have not been used. */
750 static fragS *prev_reloc_op_frag;
752 /* Map normal MIPS register numbers to mips16 register numbers. */
754 #define X ILLEGAL_REG
755 static const int mips32_to_16_reg_map[] =
757 X, X, 2, 3, 4, 5, 6, 7,
758 X, X, X, X, X, X, X, X,
759 0, 1, X, X, X, X, X, X,
760 X, X, X, X, X, X, X, X
764 /* Map mips16 register numbers to normal MIPS register numbers. */
766 static const unsigned int mips16_to_32_reg_map[] =
768 16, 17, 2, 3, 4, 5, 6, 7
771 /* Map normal MIPS register numbers to microMIPS register numbers. */
773 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
774 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
775 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
776 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
781 #define X ILLEGAL_REG
782 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
783 static const int mips32_to_micromips_reg_m_map[] =
785 0, X, 2, 3, X, X, X, X,
786 X, X, X, X, X, X, X, X,
787 4, 1, 5, 6, 7, X, X, X,
788 X, X, X, X, X, X, X, X
791 /* reg type q: 0, 2-7. 17. */
792 static const int mips32_to_micromips_reg_q_map[] =
794 0, X, 2, 3, 4, 5, 6, 7,
795 X, X, X, X, X, X, X, X,
796 X, 1, X, X, X, X, X, X,
797 X, X, X, X, X, X, X, X
800 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
803 /* Map microMIPS register numbers to normal MIPS register numbers. */
805 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
806 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
807 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
808 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
812 /* The microMIPS registers with type h. */
813 static const unsigned int micromips_to_32_reg_h_map1[] =
815 5, 5, 6, 4, 4, 4, 4, 4
817 static const unsigned int micromips_to_32_reg_h_map2[] =
819 6, 7, 7, 21, 22, 5, 6, 7
822 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* The microMIPS registers with type q. */
833 static const unsigned int micromips_to_32_reg_q_map[] =
835 0, 17, 2, 3, 4, 5, 6, 7
838 /* microMIPS imm type B. */
839 static const int micromips_imm_b_map[] =
841 1, 4, 8, 12, 16, 20, 24, -1
844 /* microMIPS imm type C. */
845 static const int micromips_imm_c_map[] =
847 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
850 /* Classifies the kind of instructions we're interested in when
851 implementing -mfix-vr4120. */
852 enum fix_vr4120_class
860 NUM_FIX_VR4120_CLASSES
863 /* ...likewise -mfix-loongson2f-jump. */
864 static bfd_boolean mips_fix_loongson2f_jump;
866 /* ...likewise -mfix-loongson2f-nop. */
867 static bfd_boolean mips_fix_loongson2f_nop;
869 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
870 static bfd_boolean mips_fix_loongson2f;
872 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
873 there must be at least one other instruction between an instruction
874 of type X and an instruction of type Y. */
875 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
877 /* True if -mfix-vr4120 is in force. */
878 static int mips_fix_vr4120;
880 /* ...likewise -mfix-vr4130. */
881 static int mips_fix_vr4130;
883 /* ...likewise -mfix-24k. */
884 static int mips_fix_24k;
886 /* ...likewise -mfix-cn63xxp1 */
887 static bfd_boolean mips_fix_cn63xxp1;
889 /* We don't relax branches by default, since this causes us to expand
890 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
891 fail to compute the offset before expanding the macro to the most
892 efficient expansion. */
894 static int mips_relax_branch;
896 /* The expansion of many macros depends on the type of symbol that
897 they refer to. For example, when generating position-dependent code,
898 a macro that refers to a symbol may have two different expansions,
899 one which uses GP-relative addresses and one which uses absolute
900 addresses. When generating SVR4-style PIC, a macro may have
901 different expansions for local and global symbols.
903 We handle these situations by generating both sequences and putting
904 them in variant frags. In position-dependent code, the first sequence
905 will be the GP-relative one and the second sequence will be the
906 absolute one. In SVR4 PIC, the first sequence will be for global
907 symbols and the second will be for local symbols.
909 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
910 SECOND are the lengths of the two sequences in bytes. These fields
911 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
912 the subtype has the following flags:
915 Set if it has been decided that we should use the second
916 sequence instead of the first.
919 Set in the first variant frag if the macro's second implementation
920 is longer than its first. This refers to the macro as a whole,
921 not an individual relaxation.
924 Set in the first variant frag if the macro appeared in a .set nomacro
925 block and if one alternative requires a warning but the other does not.
928 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
931 RELAX_DELAY_SLOT_16BIT
932 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
935 RELAX_DELAY_SLOT_SIZE_FIRST
936 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
937 the macro is of the wrong size for the branch delay slot.
939 RELAX_DELAY_SLOT_SIZE_SECOND
940 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
941 the macro is of the wrong size for the branch delay slot.
943 The frag's "opcode" points to the first fixup for relaxable code.
945 Relaxable macros are generated using a sequence such as:
947 relax_start (SYMBOL);
948 ... generate first expansion ...
950 ... generate second expansion ...
953 The code and fixups for the unwanted alternative are discarded
954 by md_convert_frag. */
955 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
957 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
958 #define RELAX_SECOND(X) ((X) & 0xff)
959 #define RELAX_USE_SECOND 0x10000
960 #define RELAX_SECOND_LONGER 0x20000
961 #define RELAX_NOMACRO 0x40000
962 #define RELAX_DELAY_SLOT 0x80000
963 #define RELAX_DELAY_SLOT_16BIT 0x100000
964 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
965 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
967 /* Branch without likely bit. If label is out of range, we turn:
969 beq reg1, reg2, label
979 with the following opcode replacements:
986 bltzal <-> bgezal (with jal label instead of j label)
988 Even though keeping the delay slot instruction in the delay slot of
989 the branch would be more efficient, it would be very tricky to do
990 correctly, because we'd have to introduce a variable frag *after*
991 the delay slot instruction, and expand that instead. Let's do it
992 the easy way for now, even if the branch-not-taken case now costs
993 one additional instruction. Out-of-range branches are not supposed
994 to be common, anyway.
996 Branch likely. If label is out of range, we turn:
998 beql reg1, reg2, label
999 delay slot (annulled if branch not taken)
1008 delay slot (executed only if branch taken)
1011 It would be possible to generate a shorter sequence by losing the
1012 likely bit, generating something like:
1017 delay slot (executed only if branch taken)
1029 bltzall -> bgezal (with jal label instead of j label)
1030 bgezall -> bltzal (ditto)
1033 but it's not clear that it would actually improve performance. */
1034 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1035 ((relax_substateT) \
1038 | ((toofar) ? 0x20 : 0) \
1039 | ((link) ? 0x40 : 0) \
1040 | ((likely) ? 0x80 : 0) \
1041 | ((uncond) ? 0x100 : 0)))
1042 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1043 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1044 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1045 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1046 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1047 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1049 /* For mips16 code, we use an entirely different form of relaxation.
1050 mips16 supports two versions of most instructions which take
1051 immediate values: a small one which takes some small value, and a
1052 larger one which takes a 16 bit value. Since branches also follow
1053 this pattern, relaxing these values is required.
1055 We can assemble both mips16 and normal MIPS code in a single
1056 object. Therefore, we need to support this type of relaxation at
1057 the same time that we support the relaxation described above. We
1058 use the high bit of the subtype field to distinguish these cases.
1060 The information we store for this type of relaxation is the
1061 argument code found in the opcode file for this relocation, whether
1062 the user explicitly requested a small or extended form, and whether
1063 the relocation is in a jump or jal delay slot. That tells us the
1064 size of the value, and how it should be stored. We also store
1065 whether the fragment is considered to be extended or not. We also
1066 store whether this is known to be a branch to a different section,
1067 whether we have tried to relax this frag yet, and whether we have
1068 ever extended a PC relative fragment because of a shift count. */
1069 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1072 | ((small) ? 0x100 : 0) \
1073 | ((ext) ? 0x200 : 0) \
1074 | ((dslot) ? 0x400 : 0) \
1075 | ((jal_dslot) ? 0x800 : 0))
1076 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1077 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1078 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1079 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1080 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1081 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1082 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1083 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1084 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1085 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1086 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1087 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1089 /* For microMIPS code, we use relaxation similar to one we use for
1090 MIPS16 code. Some instructions that take immediate values support
1091 two encodings: a small one which takes some small value, and a
1092 larger one which takes a 16 bit value. As some branches also follow
1093 this pattern, relaxing these values is required.
1095 We can assemble both microMIPS and normal MIPS code in a single
1096 object. Therefore, we need to support this type of relaxation at
1097 the same time that we support the relaxation described above. We
1098 use one of the high bits of the subtype field to distinguish these
1101 The information we store for this type of relaxation is the argument
1102 code found in the opcode file for this relocation, the register
1103 selected as the assembler temporary, whether the branch is
1104 unconditional, whether it is compact, whether it stores the link
1105 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1106 branches to a sequence of instructions is enabled, and whether the
1107 displacement of a branch is too large to fit as an immediate argument
1108 of a 16-bit and a 32-bit branch, respectively. */
1109 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1110 relax32, toofar16, toofar32) \
1113 | (((at) & 0x1f) << 8) \
1114 | ((uncond) ? 0x2000 : 0) \
1115 | ((compact) ? 0x4000 : 0) \
1116 | ((link) ? 0x8000 : 0) \
1117 | ((relax32) ? 0x10000 : 0) \
1118 | ((toofar16) ? 0x20000 : 0) \
1119 | ((toofar32) ? 0x40000 : 0))
1120 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1121 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1123 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1124 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1125 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1126 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1128 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1129 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1130 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1131 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1135 /* Sign-extend 16-bit value X. */
1136 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1138 /* Is the given value a sign-extended 32-bit value? */
1139 #define IS_SEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1141 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1143 /* Is the given value a sign-extended 16-bit value? */
1144 #define IS_SEXT_16BIT_NUM(x) \
1145 (((x) &~ (offsetT) 0x7fff) == 0 \
1146 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1148 /* Is the given value a sign-extended 12-bit value? */
1149 #define IS_SEXT_12BIT_NUM(x) \
1150 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1152 /* Is the given value a sign-extended 9-bit value? */
1153 #define IS_SEXT_9BIT_NUM(x) \
1154 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1156 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1157 #define IS_ZEXT_32BIT_NUM(x) \
1158 (((x) &~ (offsetT) 0xffffffff) == 0 \
1159 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1161 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1162 VALUE << SHIFT. VALUE is evaluated exactly once. */
1163 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1164 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1165 | (((VALUE) & (MASK)) << (SHIFT)))
1167 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1169 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1170 (((STRUCT) >> (SHIFT)) & (MASK))
1172 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1173 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1175 include/opcode/mips.h specifies operand fields using the macros
1176 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1177 with "MIPS16OP" instead of "OP". */
1178 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1181 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1182 OP_MASK_##FIELD, OP_SH_##FIELD); \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1187 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1188 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1189 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1191 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1192 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1194 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1195 : EXTRACT_BITS ((INSN).insn_opcode, \
1196 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1197 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1198 EXTRACT_BITS ((INSN).insn_opcode, \
1199 MIPS16OP_MASK_##FIELD, \
1200 MIPS16OP_SH_##FIELD)
1202 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1203 #define MIPS16_EXTEND (0xf000U << 16)
1205 /* Whether or not we are emitting a branch-likely macro. */
1206 static bfd_boolean emit_branch_likely_macro = FALSE;
1208 /* Global variables used when generating relaxable macros. See the
1209 comment above RELAX_ENCODE for more details about how relaxation
1212 /* 0 if we're not emitting a relaxable macro.
1213 1 if we're emitting the first of the two relaxation alternatives.
1214 2 if we're emitting the second alternative. */
1217 /* The first relaxable fixup in the current frag. (In other words,
1218 the first fixup that refers to relaxable code.) */
1221 /* sizes[0] says how many bytes of the first alternative are stored in
1222 the current frag. Likewise sizes[1] for the second alternative. */
1223 unsigned int sizes[2];
1225 /* The symbol on which the choice of sequence depends. */
1229 /* Global variables used to decide whether a macro needs a warning. */
1231 /* True if the macro is in a branch delay slot. */
1232 bfd_boolean delay_slot_p;
1234 /* Set to the length in bytes required if the macro is in a delay slot
1235 that requires a specific length of instruction, otherwise zero. */
1236 unsigned int delay_slot_length;
1238 /* For relaxable macros, sizes[0] is the length of the first alternative
1239 in bytes and sizes[1] is the length of the second alternative.
1240 For non-relaxable macros, both elements give the length of the
1242 unsigned int sizes[2];
1244 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1245 instruction of the first alternative in bytes and first_insn_sizes[1]
1246 is the length of the first instruction of the second alternative.
1247 For non-relaxable macros, both elements give the length of the first
1248 instruction in bytes.
1250 Set to zero if we haven't yet seen the first instruction. */
1251 unsigned int first_insn_sizes[2];
1253 /* For relaxable macros, insns[0] is the number of instructions for the
1254 first alternative and insns[1] is the number of instructions for the
1257 For non-relaxable macros, both elements give the number of
1258 instructions for the macro. */
1259 unsigned int insns[2];
1261 /* The first variant frag for this macro. */
1263 } mips_macro_warning;
1265 /* Prototypes for static functions. */
1267 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1269 static void append_insn
1270 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1271 bfd_boolean expansionp);
1272 static void mips_no_prev_insn (void);
1273 static void macro_build (expressionS *, const char *, const char *, ...);
1274 static void mips16_macro_build
1275 (expressionS *, const char *, const char *, va_list *);
1276 static void load_register (int, expressionS *, int);
1277 static void macro_start (void);
1278 static void macro_end (void);
1279 static void macro (struct mips_cl_insn *ip, char *str);
1280 static void mips16_macro (struct mips_cl_insn * ip);
1281 static void mips_ip (char *str, struct mips_cl_insn * ip);
1282 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1283 static void mips16_immed
1284 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1285 unsigned int, unsigned long *);
1286 static size_t my_getSmallExpression
1287 (expressionS *, bfd_reloc_code_real_type *, char *);
1288 static void my_getExpression (expressionS *, char *);
1289 static void s_align (int);
1290 static void s_change_sec (int);
1291 static void s_change_section (int);
1292 static void s_cons (int);
1293 static void s_float_cons (int);
1294 static void s_mips_globl (int);
1295 static void s_option (int);
1296 static void s_mipsset (int);
1297 static void s_abicalls (int);
1298 static void s_cpload (int);
1299 static void s_cpsetup (int);
1300 static void s_cplocal (int);
1301 static void s_cprestore (int);
1302 static void s_cpreturn (int);
1303 static void s_dtprelword (int);
1304 static void s_dtpreldword (int);
1305 static void s_tprelword (int);
1306 static void s_tpreldword (int);
1307 static void s_gpvalue (int);
1308 static void s_gpword (int);
1309 static void s_gpdword (int);
1310 static void s_ehword (int);
1311 static void s_cpadd (int);
1312 static void s_insn (int);
1313 static void md_obj_begin (void);
1314 static void md_obj_end (void);
1315 static void s_mips_ent (int);
1316 static void s_mips_end (int);
1317 static void s_mips_frame (int);
1318 static void s_mips_mask (int reg_type);
1319 static void s_mips_stab (int);
1320 static void s_mips_weakext (int);
1321 static void s_mips_file (int);
1322 static void s_mips_loc (int);
1323 static bfd_boolean pic_need_relax (symbolS *, asection *);
1324 static int relaxed_branch_length (fragS *, asection *, int);
1325 static int validate_mips_insn (const struct mips_opcode *);
1326 static int validate_micromips_insn (const struct mips_opcode *);
1327 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1328 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1330 /* Table and functions used to map between CPU/ISA names, and
1331 ISA levels, and CPU numbers. */
1333 struct mips_cpu_info
1335 const char *name; /* CPU or ISA name. */
1336 int flags; /* MIPS_CPU_* flags. */
1337 int ase; /* Set of ASEs implemented by the CPU. */
1338 int isa; /* ISA level. */
1339 int cpu; /* CPU number (default CPU if ISA). */
1342 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1344 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1345 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1346 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1348 /* Command-line options. */
1349 const char *md_shortopts = "O::g::G:";
1353 OPTION_MARCH = OPTION_MD_BASE,
1377 OPTION_NO_SMARTMIPS,
1383 OPTION_NO_MICROMIPS,
1386 OPTION_COMPAT_ARCH_BASE,
1395 OPTION_M7000_HILO_FIX,
1396 OPTION_MNO_7000_HILO_FIX,
1399 OPTION_FIX_LOONGSON2F_JUMP,
1400 OPTION_NO_FIX_LOONGSON2F_JUMP,
1401 OPTION_FIX_LOONGSON2F_NOP,
1402 OPTION_NO_FIX_LOONGSON2F_NOP,
1404 OPTION_NO_FIX_VR4120,
1406 OPTION_NO_FIX_VR4130,
1407 OPTION_FIX_CN63XXP1,
1408 OPTION_NO_FIX_CN63XXP1,
1415 OPTION_CONSTRUCT_FLOATS,
1416 OPTION_NO_CONSTRUCT_FLOATS,
1419 OPTION_RELAX_BRANCH,
1420 OPTION_NO_RELAX_BRANCH,
1429 OPTION_SINGLE_FLOAT,
1430 OPTION_DOUBLE_FLOAT,
1443 OPTION_MVXWORKS_PIC,
1447 struct option md_longopts[] =
1449 /* Options which specify architecture. */
1450 {"march", required_argument, NULL, OPTION_MARCH},
1451 {"mtune", required_argument, NULL, OPTION_MTUNE},
1452 {"mips0", no_argument, NULL, OPTION_MIPS1},
1453 {"mips1", no_argument, NULL, OPTION_MIPS1},
1454 {"mips2", no_argument, NULL, OPTION_MIPS2},
1455 {"mips3", no_argument, NULL, OPTION_MIPS3},
1456 {"mips4", no_argument, NULL, OPTION_MIPS4},
1457 {"mips5", no_argument, NULL, OPTION_MIPS5},
1458 {"mips32", no_argument, NULL, OPTION_MIPS32},
1459 {"mips64", no_argument, NULL, OPTION_MIPS64},
1460 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1461 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1463 /* Options which specify Application Specific Extensions (ASEs). */
1464 {"mips16", no_argument, NULL, OPTION_MIPS16},
1465 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1466 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1467 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1468 {"mdmx", no_argument, NULL, OPTION_MDMX},
1469 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1470 {"mdsp", no_argument, NULL, OPTION_DSP},
1471 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1472 {"mmt", no_argument, NULL, OPTION_MT},
1473 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1474 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1475 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1476 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1477 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1478 {"meva", no_argument, NULL, OPTION_EVA},
1479 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1480 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1481 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1482 {"mmcu", no_argument, NULL, OPTION_MCU},
1483 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1484 {"mvirt", no_argument, NULL, OPTION_VIRT},
1485 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1487 /* Old-style architecture options. Don't add more of these. */
1488 {"m4650", no_argument, NULL, OPTION_M4650},
1489 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1490 {"m4010", no_argument, NULL, OPTION_M4010},
1491 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1492 {"m4100", no_argument, NULL, OPTION_M4100},
1493 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1494 {"m3900", no_argument, NULL, OPTION_M3900},
1495 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1497 /* Options which enable bug fixes. */
1498 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1499 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1500 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1501 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1502 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1503 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1504 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1505 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1506 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1507 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1508 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1509 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1510 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1511 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1512 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1514 /* Miscellaneous options. */
1515 {"trap", no_argument, NULL, OPTION_TRAP},
1516 {"no-break", no_argument, NULL, OPTION_TRAP},
1517 {"break", no_argument, NULL, OPTION_BREAK},
1518 {"no-trap", no_argument, NULL, OPTION_BREAK},
1519 {"EB", no_argument, NULL, OPTION_EB},
1520 {"EL", no_argument, NULL, OPTION_EL},
1521 {"mfp32", no_argument, NULL, OPTION_FP32},
1522 {"mgp32", no_argument, NULL, OPTION_GP32},
1523 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1524 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1525 {"mfp64", no_argument, NULL, OPTION_FP64},
1526 {"mgp64", no_argument, NULL, OPTION_GP64},
1527 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1528 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1529 {"minsn32", no_argument, NULL, OPTION_INSN32},
1530 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1531 {"mshared", no_argument, NULL, OPTION_MSHARED},
1532 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1533 {"msym32", no_argument, NULL, OPTION_MSYM32},
1534 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1535 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1536 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1537 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1538 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1540 /* Strictly speaking this next option is ELF specific,
1541 but we allow it for other ports as well in order to
1542 make testing easier. */
1543 {"32", no_argument, NULL, OPTION_32},
1545 /* ELF-specific options. */
1546 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1547 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1548 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1549 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1550 {"xgot", no_argument, NULL, OPTION_XGOT},
1551 {"mabi", required_argument, NULL, OPTION_MABI},
1552 {"n32", no_argument, NULL, OPTION_N32},
1553 {"64", no_argument, NULL, OPTION_64},
1554 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1555 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1556 {"mpdr", no_argument, NULL, OPTION_PDR},
1557 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1558 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1560 {NULL, no_argument, NULL, 0}
1562 size_t md_longopts_size = sizeof (md_longopts);
1564 /* Information about either an Application Specific Extension or an
1565 optional architecture feature that, for simplicity, we treat in the
1566 same way as an ASE. */
1569 /* The name of the ASE, used in both the command-line and .set options. */
1572 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1573 and 64-bit architectures, the flags here refer to the subset that
1574 is available on both. */
1577 /* The ASE_* flag used for instructions that are available on 64-bit
1578 architectures but that are not included in FLAGS. */
1579 unsigned int flags64;
1581 /* The command-line options that turn the ASE on and off. */
1585 /* The minimum required architecture revisions for MIPS32, MIPS64,
1586 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1589 int micromips32_rev;
1590 int micromips64_rev;
1593 /* A table of all supported ASEs. */
1594 static const struct mips_ase mips_ases[] = {
1595 { "dsp", ASE_DSP, ASE_DSP64,
1596 OPTION_DSP, OPTION_NO_DSP,
1599 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1600 OPTION_DSPR2, OPTION_NO_DSPR2,
1603 { "eva", ASE_EVA, 0,
1604 OPTION_EVA, OPTION_NO_EVA,
1607 { "mcu", ASE_MCU, 0,
1608 OPTION_MCU, OPTION_NO_MCU,
1611 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1612 { "mdmx", ASE_MDMX, 0,
1613 OPTION_MDMX, OPTION_NO_MDMX,
1616 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1617 { "mips3d", ASE_MIPS3D, 0,
1618 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1622 OPTION_MT, OPTION_NO_MT,
1625 { "smartmips", ASE_SMARTMIPS, 0,
1626 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1629 { "virt", ASE_VIRT, ASE_VIRT64,
1630 OPTION_VIRT, OPTION_NO_VIRT,
1634 /* The set of ASEs that require -mfp64. */
1635 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1637 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1638 static const unsigned int mips_ase_groups[] = {
1644 The following pseudo-ops from the Kane and Heinrich MIPS book
1645 should be defined here, but are currently unsupported: .alias,
1646 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1648 The following pseudo-ops from the Kane and Heinrich MIPS book are
1649 specific to the type of debugging information being generated, and
1650 should be defined by the object format: .aent, .begin, .bend,
1651 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 not MIPS CPU specific, but are also not specific to the object file
1656 format. This file is probably the best place to define them, but
1657 they are not currently supported: .asm0, .endr, .lab, .struct. */
1659 static const pseudo_typeS mips_pseudo_table[] =
1661 /* MIPS specific pseudo-ops. */
1662 {"option", s_option, 0},
1663 {"set", s_mipsset, 0},
1664 {"rdata", s_change_sec, 'r'},
1665 {"sdata", s_change_sec, 's'},
1666 {"livereg", s_ignore, 0},
1667 {"abicalls", s_abicalls, 0},
1668 {"cpload", s_cpload, 0},
1669 {"cpsetup", s_cpsetup, 0},
1670 {"cplocal", s_cplocal, 0},
1671 {"cprestore", s_cprestore, 0},
1672 {"cpreturn", s_cpreturn, 0},
1673 {"dtprelword", s_dtprelword, 0},
1674 {"dtpreldword", s_dtpreldword, 0},
1675 {"tprelword", s_tprelword, 0},
1676 {"tpreldword", s_tpreldword, 0},
1677 {"gpvalue", s_gpvalue, 0},
1678 {"gpword", s_gpword, 0},
1679 {"gpdword", s_gpdword, 0},
1680 {"ehword", s_ehword, 0},
1681 {"cpadd", s_cpadd, 0},
1682 {"insn", s_insn, 0},
1684 /* Relatively generic pseudo-ops that happen to be used on MIPS
1686 {"asciiz", stringer, 8 + 1},
1687 {"bss", s_change_sec, 'b'},
1689 {"half", s_cons, 1},
1690 {"dword", s_cons, 3},
1691 {"weakext", s_mips_weakext, 0},
1692 {"origin", s_org, 0},
1693 {"repeat", s_rept, 0},
1695 /* For MIPS this is non-standard, but we define it for consistency. */
1696 {"sbss", s_change_sec, 'B'},
1698 /* These pseudo-ops are defined in read.c, but must be overridden
1699 here for one reason or another. */
1700 {"align", s_align, 0},
1701 {"byte", s_cons, 0},
1702 {"data", s_change_sec, 'd'},
1703 {"double", s_float_cons, 'd'},
1704 {"float", s_float_cons, 'f'},
1705 {"globl", s_mips_globl, 0},
1706 {"global", s_mips_globl, 0},
1707 {"hword", s_cons, 1},
1709 {"long", s_cons, 2},
1710 {"octa", s_cons, 4},
1711 {"quad", s_cons, 3},
1712 {"section", s_change_section, 0},
1713 {"short", s_cons, 1},
1714 {"single", s_float_cons, 'f'},
1715 {"stabd", s_mips_stab, 'd'},
1716 {"stabn", s_mips_stab, 'n'},
1717 {"stabs", s_mips_stab, 's'},
1718 {"text", s_change_sec, 't'},
1719 {"word", s_cons, 2},
1721 { "extern", ecoff_directive_extern, 0},
1726 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1728 /* These pseudo-ops should be defined by the object file format.
1729 However, a.out doesn't support them, so we have versions here. */
1730 {"aent", s_mips_ent, 1},
1731 {"bgnb", s_ignore, 0},
1732 {"end", s_mips_end, 0},
1733 {"endb", s_ignore, 0},
1734 {"ent", s_mips_ent, 0},
1735 {"file", s_mips_file, 0},
1736 {"fmask", s_mips_mask, 'F'},
1737 {"frame", s_mips_frame, 0},
1738 {"loc", s_mips_loc, 0},
1739 {"mask", s_mips_mask, 'R'},
1740 {"verstamp", s_ignore, 0},
1744 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1745 purpose of the `.dc.a' internal pseudo-op. */
1748 mips_address_bytes (void)
1750 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1753 extern void pop_insert (const pseudo_typeS *);
1756 mips_pop_insert (void)
1758 pop_insert (mips_pseudo_table);
1759 if (! ECOFF_DEBUGGING)
1760 pop_insert (mips_nonecoff_pseudo_table);
1763 /* Symbols labelling the current insn. */
1765 struct insn_label_list
1767 struct insn_label_list *next;
1771 static struct insn_label_list *free_insn_labels;
1772 #define label_list tc_segment_info_data.labels
1774 static void mips_clear_insn_labels (void);
1775 static void mips_mark_labels (void);
1776 static void mips_compressed_mark_labels (void);
1779 mips_clear_insn_labels (void)
1781 register struct insn_label_list **pl;
1782 segment_info_type *si;
1786 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1789 si = seg_info (now_seg);
1790 *pl = si->label_list;
1791 si->label_list = NULL;
1795 /* Mark instruction labels in MIPS16/microMIPS mode. */
1798 mips_mark_labels (void)
1800 if (HAVE_CODE_COMPRESSION)
1801 mips_compressed_mark_labels ();
1804 static char *expr_end;
1806 /* Expressions which appear in instructions. These are set by
1809 static expressionS imm_expr;
1810 static expressionS imm2_expr;
1811 static expressionS offset_expr;
1813 /* Relocs associated with imm_expr and offset_expr. */
1815 static bfd_reloc_code_real_type imm_reloc[3]
1816 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1817 static bfd_reloc_code_real_type offset_reloc[3]
1818 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1820 /* This is set to the resulting size of the instruction to be produced
1821 by mips16_ip if an explicit extension is used or by mips_ip if an
1822 explicit size is supplied. */
1824 static unsigned int forced_insn_length;
1826 /* True if we are assembling an instruction. All dot symbols defined during
1827 this time should be treated as code labels. */
1829 static bfd_boolean mips_assembling_insn;
1831 /* The pdr segment for per procedure frame/regmask info. Not used for
1834 static segT pdr_seg;
1836 /* The default target format to use. */
1838 #if defined (TE_FreeBSD)
1839 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1840 #elif defined (TE_TMIPS)
1841 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1843 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1847 mips_target_format (void)
1849 switch (OUTPUT_FLAVOR)
1851 case bfd_target_elf_flavour:
1853 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1854 return (target_big_endian
1855 ? "elf32-bigmips-vxworks"
1856 : "elf32-littlemips-vxworks");
1858 return (target_big_endian
1859 ? (HAVE_64BIT_OBJECTS
1860 ? ELF_TARGET ("elf64-", "big")
1862 ? ELF_TARGET ("elf32-n", "big")
1863 : ELF_TARGET ("elf32-", "big")))
1864 : (HAVE_64BIT_OBJECTS
1865 ? ELF_TARGET ("elf64-", "little")
1867 ? ELF_TARGET ("elf32-n", "little")
1868 : ELF_TARGET ("elf32-", "little"))));
1875 /* Return the ISA revision that is currently in use, or 0 if we are
1876 generating code for MIPS V or below. */
1881 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1884 /* microMIPS implies revision 2 or above. */
1885 if (mips_opts.micromips)
1888 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1894 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1897 mips_ase_mask (unsigned int flags)
1901 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1902 if (flags & mips_ase_groups[i])
1903 flags |= mips_ase_groups[i];
1907 /* Check whether the current ISA supports ASE. Issue a warning if
1911 mips_check_isa_supports_ase (const struct mips_ase *ase)
1915 static unsigned int warned_isa;
1916 static unsigned int warned_fp32;
1918 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1919 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1921 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1922 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1923 && (warned_isa & ase->flags) != ase->flags)
1925 warned_isa |= ase->flags;
1926 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1927 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1929 as_warn (_("The %d-bit %s architecture does not support the"
1930 " `%s' extension"), size, base, ase->name);
1932 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1933 ase->name, base, size, min_rev);
1935 if ((ase->flags & FP64_ASES)
1937 && (warned_fp32 & ase->flags) != ase->flags)
1939 warned_fp32 |= ase->flags;
1940 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1944 /* Check all enabled ASEs to see whether they are supported by the
1945 chosen architecture. */
1948 mips_check_isa_supports_ases (void)
1950 unsigned int i, mask;
1952 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1954 mask = mips_ase_mask (mips_ases[i].flags);
1955 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1956 mips_check_isa_supports_ase (&mips_ases[i]);
1960 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1961 that were affected. */
1964 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1968 mask = mips_ase_mask (ase->flags);
1969 mips_opts.ase &= ~mask;
1971 mips_opts.ase |= ase->flags;
1975 /* Return the ASE called NAME, or null if none. */
1977 static const struct mips_ase *
1978 mips_lookup_ase (const char *name)
1982 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1983 if (strcmp (name, mips_ases[i].name) == 0)
1984 return &mips_ases[i];
1988 /* Return the length of a microMIPS instruction in bytes. If bits of
1989 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1990 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1991 major opcode) will require further modifications to the opcode
1994 static inline unsigned int
1995 micromips_insn_length (const struct mips_opcode *mo)
1997 return (mo->mask >> 16) == 0 ? 2 : 4;
2000 /* Return the length of MIPS16 instruction OPCODE. */
2002 static inline unsigned int
2003 mips16_opcode_length (unsigned long opcode)
2005 return (opcode >> 16) == 0 ? 2 : 4;
2008 /* Return the length of instruction INSN. */
2010 static inline unsigned int
2011 insn_length (const struct mips_cl_insn *insn)
2013 if (mips_opts.micromips)
2014 return micromips_insn_length (insn->insn_mo);
2015 else if (mips_opts.mips16)
2016 return mips16_opcode_length (insn->insn_opcode);
2021 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2024 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2029 insn->insn_opcode = mo->match;
2032 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2033 insn->fixp[i] = NULL;
2034 insn->fixed_p = (mips_opts.noreorder > 0);
2035 insn->noreorder_p = (mips_opts.noreorder > 0);
2036 insn->mips16_absolute_jump_p = 0;
2037 insn->complete_p = 0;
2038 insn->cleared_p = 0;
2041 /* Record the current MIPS16/microMIPS mode in now_seg. */
2044 mips_record_compressed_mode (void)
2046 segment_info_type *si;
2048 si = seg_info (now_seg);
2049 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2050 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2051 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2052 si->tc_segment_info_data.micromips = mips_opts.micromips;
2055 /* Read a standard MIPS instruction from BUF. */
2057 static unsigned long
2058 read_insn (char *buf)
2060 if (target_big_endian)
2061 return bfd_getb32 ((bfd_byte *) buf);
2063 return bfd_getl32 ((bfd_byte *) buf);
2066 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2070 write_insn (char *buf, unsigned int insn)
2072 md_number_to_chars (buf, insn, 4);
2076 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2077 has length LENGTH. */
2079 static unsigned long
2080 read_compressed_insn (char *buf, unsigned int length)
2086 for (i = 0; i < length; i += 2)
2089 if (target_big_endian)
2090 insn |= bfd_getb16 ((char *) buf);
2092 insn |= bfd_getl16 ((char *) buf);
2098 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2099 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2102 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2106 for (i = 0; i < length; i += 2)
2107 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2108 return buf + length;
2111 /* Install INSN at the location specified by its "frag" and "where" fields. */
2114 install_insn (const struct mips_cl_insn *insn)
2116 char *f = insn->frag->fr_literal + insn->where;
2117 if (HAVE_CODE_COMPRESSION)
2118 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2120 write_insn (f, insn->insn_opcode);
2121 mips_record_compressed_mode ();
2124 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2125 and install the opcode in the new location. */
2128 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2133 insn->where = where;
2134 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2135 if (insn->fixp[i] != NULL)
2137 insn->fixp[i]->fx_frag = frag;
2138 insn->fixp[i]->fx_where = where;
2140 install_insn (insn);
2143 /* Add INSN to the end of the output. */
2146 add_fixed_insn (struct mips_cl_insn *insn)
2148 char *f = frag_more (insn_length (insn));
2149 move_insn (insn, frag_now, f - frag_now->fr_literal);
2152 /* Start a variant frag and move INSN to the start of the variant part,
2153 marking it as fixed. The other arguments are as for frag_var. */
2156 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2157 relax_substateT subtype, symbolS *symbol, offsetT offset)
2159 frag_grow (max_chars);
2160 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2162 frag_var (rs_machine_dependent, max_chars, var,
2163 subtype, symbol, offset, NULL);
2166 /* Insert N copies of INSN into the history buffer, starting at
2167 position FIRST. Neither FIRST nor N need to be clipped. */
2170 insert_into_history (unsigned int first, unsigned int n,
2171 const struct mips_cl_insn *insn)
2173 if (mips_relax.sequence != 2)
2177 for (i = ARRAY_SIZE (history); i-- > first;)
2179 history[i] = history[i - n];
2185 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2186 the idea is to make it obvious at a glance that each errata is
2190 init_vr4120_conflicts (void)
2192 #define CONFLICT(FIRST, SECOND) \
2193 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2195 /* Errata 21 - [D]DIV[U] after [D]MACC */
2196 CONFLICT (MACC, DIV);
2197 CONFLICT (DMACC, DIV);
2199 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2200 CONFLICT (DMULT, DMULT);
2201 CONFLICT (DMULT, DMACC);
2202 CONFLICT (DMACC, DMULT);
2203 CONFLICT (DMACC, DMACC);
2205 /* Errata 24 - MT{LO,HI} after [D]MACC */
2206 CONFLICT (MACC, MTHILO);
2207 CONFLICT (DMACC, MTHILO);
2209 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2210 instruction is executed immediately after a MACC or DMACC
2211 instruction, the result of [either instruction] is incorrect." */
2212 CONFLICT (MACC, MULT);
2213 CONFLICT (MACC, DMULT);
2214 CONFLICT (DMACC, MULT);
2215 CONFLICT (DMACC, DMULT);
2217 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2218 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2219 DDIV or DDIVU instruction, the result of the MACC or
2220 DMACC instruction is incorrect.". */
2221 CONFLICT (DMULT, MACC);
2222 CONFLICT (DMULT, DMACC);
2223 CONFLICT (DIV, MACC);
2224 CONFLICT (DIV, DMACC);
2234 #define RTYPE_MASK 0x1ff00
2235 #define RTYPE_NUM 0x00100
2236 #define RTYPE_FPU 0x00200
2237 #define RTYPE_FCC 0x00400
2238 #define RTYPE_VEC 0x00800
2239 #define RTYPE_GP 0x01000
2240 #define RTYPE_CP0 0x02000
2241 #define RTYPE_PC 0x04000
2242 #define RTYPE_ACC 0x08000
2243 #define RTYPE_CCC 0x10000
2244 #define RNUM_MASK 0x000ff
2245 #define RWARN 0x80000
2247 #define GENERIC_REGISTER_NUMBERS \
2248 {"$0", RTYPE_NUM | 0}, \
2249 {"$1", RTYPE_NUM | 1}, \
2250 {"$2", RTYPE_NUM | 2}, \
2251 {"$3", RTYPE_NUM | 3}, \
2252 {"$4", RTYPE_NUM | 4}, \
2253 {"$5", RTYPE_NUM | 5}, \
2254 {"$6", RTYPE_NUM | 6}, \
2255 {"$7", RTYPE_NUM | 7}, \
2256 {"$8", RTYPE_NUM | 8}, \
2257 {"$9", RTYPE_NUM | 9}, \
2258 {"$10", RTYPE_NUM | 10}, \
2259 {"$11", RTYPE_NUM | 11}, \
2260 {"$12", RTYPE_NUM | 12}, \
2261 {"$13", RTYPE_NUM | 13}, \
2262 {"$14", RTYPE_NUM | 14}, \
2263 {"$15", RTYPE_NUM | 15}, \
2264 {"$16", RTYPE_NUM | 16}, \
2265 {"$17", RTYPE_NUM | 17}, \
2266 {"$18", RTYPE_NUM | 18}, \
2267 {"$19", RTYPE_NUM | 19}, \
2268 {"$20", RTYPE_NUM | 20}, \
2269 {"$21", RTYPE_NUM | 21}, \
2270 {"$22", RTYPE_NUM | 22}, \
2271 {"$23", RTYPE_NUM | 23}, \
2272 {"$24", RTYPE_NUM | 24}, \
2273 {"$25", RTYPE_NUM | 25}, \
2274 {"$26", RTYPE_NUM | 26}, \
2275 {"$27", RTYPE_NUM | 27}, \
2276 {"$28", RTYPE_NUM | 28}, \
2277 {"$29", RTYPE_NUM | 29}, \
2278 {"$30", RTYPE_NUM | 30}, \
2279 {"$31", RTYPE_NUM | 31}
2281 #define FPU_REGISTER_NAMES \
2282 {"$f0", RTYPE_FPU | 0}, \
2283 {"$f1", RTYPE_FPU | 1}, \
2284 {"$f2", RTYPE_FPU | 2}, \
2285 {"$f3", RTYPE_FPU | 3}, \
2286 {"$f4", RTYPE_FPU | 4}, \
2287 {"$f5", RTYPE_FPU | 5}, \
2288 {"$f6", RTYPE_FPU | 6}, \
2289 {"$f7", RTYPE_FPU | 7}, \
2290 {"$f8", RTYPE_FPU | 8}, \
2291 {"$f9", RTYPE_FPU | 9}, \
2292 {"$f10", RTYPE_FPU | 10}, \
2293 {"$f11", RTYPE_FPU | 11}, \
2294 {"$f12", RTYPE_FPU | 12}, \
2295 {"$f13", RTYPE_FPU | 13}, \
2296 {"$f14", RTYPE_FPU | 14}, \
2297 {"$f15", RTYPE_FPU | 15}, \
2298 {"$f16", RTYPE_FPU | 16}, \
2299 {"$f17", RTYPE_FPU | 17}, \
2300 {"$f18", RTYPE_FPU | 18}, \
2301 {"$f19", RTYPE_FPU | 19}, \
2302 {"$f20", RTYPE_FPU | 20}, \
2303 {"$f21", RTYPE_FPU | 21}, \
2304 {"$f22", RTYPE_FPU | 22}, \
2305 {"$f23", RTYPE_FPU | 23}, \
2306 {"$f24", RTYPE_FPU | 24}, \
2307 {"$f25", RTYPE_FPU | 25}, \
2308 {"$f26", RTYPE_FPU | 26}, \
2309 {"$f27", RTYPE_FPU | 27}, \
2310 {"$f28", RTYPE_FPU | 28}, \
2311 {"$f29", RTYPE_FPU | 29}, \
2312 {"$f30", RTYPE_FPU | 30}, \
2313 {"$f31", RTYPE_FPU | 31}
2315 #define FPU_CONDITION_CODE_NAMES \
2316 {"$fcc0", RTYPE_FCC | 0}, \
2317 {"$fcc1", RTYPE_FCC | 1}, \
2318 {"$fcc2", RTYPE_FCC | 2}, \
2319 {"$fcc3", RTYPE_FCC | 3}, \
2320 {"$fcc4", RTYPE_FCC | 4}, \
2321 {"$fcc5", RTYPE_FCC | 5}, \
2322 {"$fcc6", RTYPE_FCC | 6}, \
2323 {"$fcc7", RTYPE_FCC | 7}
2325 #define COPROC_CONDITION_CODE_NAMES \
2326 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2327 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2328 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2329 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2330 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2331 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2332 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2333 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2335 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2336 {"$a4", RTYPE_GP | 8}, \
2337 {"$a5", RTYPE_GP | 9}, \
2338 {"$a6", RTYPE_GP | 10}, \
2339 {"$a7", RTYPE_GP | 11}, \
2340 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2341 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2342 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2343 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2344 {"$t0", RTYPE_GP | 12}, \
2345 {"$t1", RTYPE_GP | 13}, \
2346 {"$t2", RTYPE_GP | 14}, \
2347 {"$t3", RTYPE_GP | 15}
2349 #define O32_SYMBOLIC_REGISTER_NAMES \
2350 {"$t0", RTYPE_GP | 8}, \
2351 {"$t1", RTYPE_GP | 9}, \
2352 {"$t2", RTYPE_GP | 10}, \
2353 {"$t3", RTYPE_GP | 11}, \
2354 {"$t4", RTYPE_GP | 12}, \
2355 {"$t5", RTYPE_GP | 13}, \
2356 {"$t6", RTYPE_GP | 14}, \
2357 {"$t7", RTYPE_GP | 15}, \
2358 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2359 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2360 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2361 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2363 /* Remaining symbolic register names */
2364 #define SYMBOLIC_REGISTER_NAMES \
2365 {"$zero", RTYPE_GP | 0}, \
2366 {"$at", RTYPE_GP | 1}, \
2367 {"$AT", RTYPE_GP | 1}, \
2368 {"$v0", RTYPE_GP | 2}, \
2369 {"$v1", RTYPE_GP | 3}, \
2370 {"$a0", RTYPE_GP | 4}, \
2371 {"$a1", RTYPE_GP | 5}, \
2372 {"$a2", RTYPE_GP | 6}, \
2373 {"$a3", RTYPE_GP | 7}, \
2374 {"$s0", RTYPE_GP | 16}, \
2375 {"$s1", RTYPE_GP | 17}, \
2376 {"$s2", RTYPE_GP | 18}, \
2377 {"$s3", RTYPE_GP | 19}, \
2378 {"$s4", RTYPE_GP | 20}, \
2379 {"$s5", RTYPE_GP | 21}, \
2380 {"$s6", RTYPE_GP | 22}, \
2381 {"$s7", RTYPE_GP | 23}, \
2382 {"$t8", RTYPE_GP | 24}, \
2383 {"$t9", RTYPE_GP | 25}, \
2384 {"$k0", RTYPE_GP | 26}, \
2385 {"$kt0", RTYPE_GP | 26}, \
2386 {"$k1", RTYPE_GP | 27}, \
2387 {"$kt1", RTYPE_GP | 27}, \
2388 {"$gp", RTYPE_GP | 28}, \
2389 {"$sp", RTYPE_GP | 29}, \
2390 {"$s8", RTYPE_GP | 30}, \
2391 {"$fp", RTYPE_GP | 30}, \
2392 {"$ra", RTYPE_GP | 31}
2394 #define MIPS16_SPECIAL_REGISTER_NAMES \
2395 {"$pc", RTYPE_PC | 0}
2397 #define MDMX_VECTOR_REGISTER_NAMES \
2398 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2399 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2400 {"$v2", RTYPE_VEC | 2}, \
2401 {"$v3", RTYPE_VEC | 3}, \
2402 {"$v4", RTYPE_VEC | 4}, \
2403 {"$v5", RTYPE_VEC | 5}, \
2404 {"$v6", RTYPE_VEC | 6}, \
2405 {"$v7", RTYPE_VEC | 7}, \
2406 {"$v8", RTYPE_VEC | 8}, \
2407 {"$v9", RTYPE_VEC | 9}, \
2408 {"$v10", RTYPE_VEC | 10}, \
2409 {"$v11", RTYPE_VEC | 11}, \
2410 {"$v12", RTYPE_VEC | 12}, \
2411 {"$v13", RTYPE_VEC | 13}, \
2412 {"$v14", RTYPE_VEC | 14}, \
2413 {"$v15", RTYPE_VEC | 15}, \
2414 {"$v16", RTYPE_VEC | 16}, \
2415 {"$v17", RTYPE_VEC | 17}, \
2416 {"$v18", RTYPE_VEC | 18}, \
2417 {"$v19", RTYPE_VEC | 19}, \
2418 {"$v20", RTYPE_VEC | 20}, \
2419 {"$v21", RTYPE_VEC | 21}, \
2420 {"$v22", RTYPE_VEC | 22}, \
2421 {"$v23", RTYPE_VEC | 23}, \
2422 {"$v24", RTYPE_VEC | 24}, \
2423 {"$v25", RTYPE_VEC | 25}, \
2424 {"$v26", RTYPE_VEC | 26}, \
2425 {"$v27", RTYPE_VEC | 27}, \
2426 {"$v28", RTYPE_VEC | 28}, \
2427 {"$v29", RTYPE_VEC | 29}, \
2428 {"$v30", RTYPE_VEC | 30}, \
2429 {"$v31", RTYPE_VEC | 31}
2431 #define MIPS_DSP_ACCUMULATOR_NAMES \
2432 {"$ac0", RTYPE_ACC | 0}, \
2433 {"$ac1", RTYPE_ACC | 1}, \
2434 {"$ac2", RTYPE_ACC | 2}, \
2435 {"$ac3", RTYPE_ACC | 3}
2437 static const struct regname reg_names[] = {
2438 GENERIC_REGISTER_NUMBERS,
2440 FPU_CONDITION_CODE_NAMES,
2441 COPROC_CONDITION_CODE_NAMES,
2443 /* The $txx registers depends on the abi,
2444 these will be added later into the symbol table from
2445 one of the tables below once mips_abi is set after
2446 parsing of arguments from the command line. */
2447 SYMBOLIC_REGISTER_NAMES,
2449 MIPS16_SPECIAL_REGISTER_NAMES,
2450 MDMX_VECTOR_REGISTER_NAMES,
2451 MIPS_DSP_ACCUMULATOR_NAMES,
2455 static const struct regname reg_names_o32[] = {
2456 O32_SYMBOLIC_REGISTER_NAMES,
2460 static const struct regname reg_names_n32n64[] = {
2461 N32N64_SYMBOLIC_REGISTER_NAMES,
2465 /* Check if S points at a valid register specifier according to TYPES.
2466 If so, then return 1, advance S to consume the specifier and store
2467 the register's number in REGNOP, otherwise return 0. */
2470 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2477 /* Find end of name. */
2479 if (is_name_beginner (*e))
2481 while (is_part_of_name (*e))
2484 /* Terminate name. */
2488 /* Look for a register symbol. */
2489 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2491 int r = S_GET_VALUE (symbolP);
2493 reg = r & RNUM_MASK;
2494 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2495 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2496 reg = (r & RNUM_MASK) - 2;
2498 /* Else see if this is a register defined in an itbl entry. */
2499 else if ((types & RTYPE_GP) && itbl_have_entries)
2506 if (itbl_get_reg_val (n, &r))
2507 reg = r & RNUM_MASK;
2510 /* Advance to next token if a register was recognised. */
2513 else if (types & RWARN)
2514 as_warn (_("Unrecognized register name `%s'"), *s);
2522 /* Check if S points at a valid register list according to TYPES.
2523 If so, then return 1, advance S to consume the list and store
2524 the registers present on the list as a bitmask of ones in REGLISTP,
2525 otherwise return 0. A valid list comprises a comma-separated
2526 enumeration of valid single registers and/or dash-separated
2527 contiguous register ranges as determined by their numbers.
2529 As a special exception if one of s0-s7 registers is specified as
2530 the range's lower delimiter and s8 (fp) is its upper one, then no
2531 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2532 are selected; they have to be listed separately if needed. */
2535 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2537 unsigned int reglist = 0;
2538 unsigned int lastregno;
2539 bfd_boolean ok = TRUE;
2540 unsigned int regmask;
2541 char *s_endlist = *s;
2545 while (reg_lookup (s, types, ®no))
2551 ok = reg_lookup (s, types, &lastregno);
2552 if (ok && lastregno < regno)
2558 if (lastregno == FP && regno >= S0 && regno <= S7)
2563 regmask = 1 << lastregno;
2564 regmask = (regmask << 1) - 1;
2565 regmask ^= (1 << regno) - 1;
2579 *reglistp = reglist;
2580 return ok && reglist != 0;
2584 mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
2585 const unsigned int *map1, const unsigned int *map2,
2590 for (i = 0; i < count; i++)
2591 if (map1[i] == regno1 && map2[i] == regno2)
2596 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2597 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2600 is_opcode_valid (const struct mips_opcode *mo)
2602 int isa = mips_opts.isa;
2603 int ase = mips_opts.ase;
2607 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2608 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2609 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2610 ase |= mips_ases[i].flags64;
2612 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2615 /* Check whether the instruction or macro requires single-precision or
2616 double-precision floating-point support. Note that this information is
2617 stored differently in the opcode table for insns and macros. */
2618 if (mo->pinfo == INSN_MACRO)
2620 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2621 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2625 fp_s = mo->pinfo & FP_S;
2626 fp_d = mo->pinfo & FP_D;
2629 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2632 if (fp_s && mips_opts.soft_float)
2638 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2639 selected ISA and architecture. */
2642 is_opcode_valid_16 (const struct mips_opcode *mo)
2644 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2647 /* Return TRUE if the size of the microMIPS opcode MO matches one
2648 explicitly requested. Always TRUE in the standard MIPS mode. */
2651 is_size_valid (const struct mips_opcode *mo)
2653 if (!mips_opts.micromips)
2656 if (mips_opts.insn32)
2658 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2660 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2663 if (!forced_insn_length)
2665 if (mo->pinfo == INSN_MACRO)
2667 return forced_insn_length == micromips_insn_length (mo);
2670 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2671 of the preceding instruction. Always TRUE in the standard MIPS mode.
2673 We don't accept macros in 16-bit delay slots to avoid a case where
2674 a macro expansion fails because it relies on a preceding 32-bit real
2675 instruction to have matched and does not handle the operands correctly.
2676 The only macros that may expand to 16-bit instructions are JAL that
2677 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2678 and BGT (that likewise cannot be placed in a delay slot) that decay to
2679 a NOP. In all these cases the macros precede any corresponding real
2680 instruction definitions in the opcode table, so they will match in the
2681 second pass where the size of the delay slot is ignored and therefore
2682 produce correct code. */
2685 is_delay_slot_valid (const struct mips_opcode *mo)
2687 if (!mips_opts.micromips)
2690 if (mo->pinfo == INSN_MACRO)
2691 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2692 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2693 && micromips_insn_length (mo) != 4)
2695 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2696 && micromips_insn_length (mo) != 2)
2702 /* This function is called once, at assembler startup time. It should set up
2703 all the tables, etc. that the MD part of the assembler will need. */
2708 const char *retval = NULL;
2712 if (mips_pic != NO_PIC)
2714 if (g_switch_seen && g_switch_value != 0)
2715 as_bad (_("-G may not be used in position-independent code"));
2719 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2720 as_warn (_("Could not set architecture and machine"));
2722 op_hash = hash_new ();
2724 for (i = 0; i < NUMOPCODES;)
2726 const char *name = mips_opcodes[i].name;
2728 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2731 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2732 mips_opcodes[i].name, retval);
2733 /* Probably a memory allocation problem? Give up now. */
2734 as_fatal (_("Broken assembler. No assembly attempted."));
2738 if (mips_opcodes[i].pinfo != INSN_MACRO)
2740 if (!validate_mips_insn (&mips_opcodes[i]))
2742 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2744 create_insn (&nop_insn, mips_opcodes + i);
2745 if (mips_fix_loongson2f_nop)
2746 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2747 nop_insn.fixed_p = 1;
2752 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2755 mips16_op_hash = hash_new ();
2758 while (i < bfd_mips16_num_opcodes)
2760 const char *name = mips16_opcodes[i].name;
2762 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2764 as_fatal (_("internal: can't hash `%s': %s"),
2765 mips16_opcodes[i].name, retval);
2768 if (mips16_opcodes[i].pinfo != INSN_MACRO
2769 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2770 != mips16_opcodes[i].match))
2772 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2773 mips16_opcodes[i].name, mips16_opcodes[i].args);
2776 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2778 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2779 mips16_nop_insn.fixed_p = 1;
2783 while (i < bfd_mips16_num_opcodes
2784 && strcmp (mips16_opcodes[i].name, name) == 0);
2787 micromips_op_hash = hash_new ();
2790 while (i < bfd_micromips_num_opcodes)
2792 const char *name = micromips_opcodes[i].name;
2794 retval = hash_insert (micromips_op_hash, name,
2795 (void *) µmips_opcodes[i]);
2797 as_fatal (_("internal: can't hash `%s': %s"),
2798 micromips_opcodes[i].name, retval);
2800 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2802 struct mips_cl_insn *micromips_nop_insn;
2804 if (!validate_micromips_insn (µmips_opcodes[i]))
2807 if (micromips_insn_length (micromips_opcodes + i) == 2)
2808 micromips_nop_insn = µmips_nop16_insn;
2809 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2810 micromips_nop_insn = µmips_nop32_insn;
2814 if (micromips_nop_insn->insn_mo == NULL
2815 && strcmp (name, "nop") == 0)
2817 create_insn (micromips_nop_insn, micromips_opcodes + i);
2818 micromips_nop_insn->fixed_p = 1;
2821 while (++i < bfd_micromips_num_opcodes
2822 && strcmp (micromips_opcodes[i].name, name) == 0);
2826 as_fatal (_("Broken assembler. No assembly attempted."));
2828 /* We add all the general register names to the symbol table. This
2829 helps us detect invalid uses of them. */
2830 for (i = 0; reg_names[i].name; i++)
2831 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2832 reg_names[i].num, /* & RNUM_MASK, */
2833 &zero_address_frag));
2835 for (i = 0; reg_names_n32n64[i].name; i++)
2836 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2837 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2838 &zero_address_frag));
2840 for (i = 0; reg_names_o32[i].name; i++)
2841 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2842 reg_names_o32[i].num, /* & RNUM_MASK, */
2843 &zero_address_frag));
2845 mips_no_prev_insn ();
2848 mips_cprmask[0] = 0;
2849 mips_cprmask[1] = 0;
2850 mips_cprmask[2] = 0;
2851 mips_cprmask[3] = 0;
2853 /* set the default alignment for the text section (2**2) */
2854 record_alignment (text_section, 2);
2856 bfd_set_gp_size (stdoutput, g_switch_value);
2858 /* On a native system other than VxWorks, sections must be aligned
2859 to 16 byte boundaries. When configured for an embedded ELF
2860 target, we don't bother. */
2861 if (strncmp (TARGET_OS, "elf", 3) != 0
2862 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2864 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2865 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2866 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2869 /* Create a .reginfo section for register masks and a .mdebug
2870 section for debugging information. */
2878 subseg = now_subseg;
2880 /* The ABI says this section should be loaded so that the
2881 running program can access it. However, we don't load it
2882 if we are configured for an embedded target */
2883 flags = SEC_READONLY | SEC_DATA;
2884 if (strncmp (TARGET_OS, "elf", 3) != 0)
2885 flags |= SEC_ALLOC | SEC_LOAD;
2887 if (mips_abi != N64_ABI)
2889 sec = subseg_new (".reginfo", (subsegT) 0);
2891 bfd_set_section_flags (stdoutput, sec, flags);
2892 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2894 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2898 /* The 64-bit ABI uses a .MIPS.options section rather than
2899 .reginfo section. */
2900 sec = subseg_new (".MIPS.options", (subsegT) 0);
2901 bfd_set_section_flags (stdoutput, sec, flags);
2902 bfd_set_section_alignment (stdoutput, sec, 3);
2904 /* Set up the option header. */
2906 Elf_Internal_Options opthdr;
2909 opthdr.kind = ODK_REGINFO;
2910 opthdr.size = (sizeof (Elf_External_Options)
2911 + sizeof (Elf64_External_RegInfo));
2914 f = frag_more (sizeof (Elf_External_Options));
2915 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2916 (Elf_External_Options *) f);
2918 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2922 if (ECOFF_DEBUGGING)
2924 sec = subseg_new (".mdebug", (subsegT) 0);
2925 (void) bfd_set_section_flags (stdoutput, sec,
2926 SEC_HAS_CONTENTS | SEC_READONLY);
2927 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2929 else if (mips_flag_pdr)
2931 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2932 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2933 SEC_READONLY | SEC_RELOC
2935 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2938 subseg_set (seg, subseg);
2941 if (! ECOFF_DEBUGGING)
2944 if (mips_fix_vr4120)
2945 init_vr4120_conflicts ();
2951 mips_emit_delays ();
2952 if (! ECOFF_DEBUGGING)
2957 md_assemble (char *str)
2959 struct mips_cl_insn insn;
2960 bfd_reloc_code_real_type unused_reloc[3]
2961 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2963 imm_expr.X_op = O_absent;
2964 imm2_expr.X_op = O_absent;
2965 offset_expr.X_op = O_absent;
2966 imm_reloc[0] = BFD_RELOC_UNUSED;
2967 imm_reloc[1] = BFD_RELOC_UNUSED;
2968 imm_reloc[2] = BFD_RELOC_UNUSED;
2969 offset_reloc[0] = BFD_RELOC_UNUSED;
2970 offset_reloc[1] = BFD_RELOC_UNUSED;
2971 offset_reloc[2] = BFD_RELOC_UNUSED;
2973 mips_mark_labels ();
2974 mips_assembling_insn = TRUE;
2976 if (mips_opts.mips16)
2977 mips16_ip (str, &insn);
2980 mips_ip (str, &insn);
2981 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2982 str, insn.insn_opcode));
2986 as_bad ("%s `%s'", insn_error, str);
2987 else if (insn.insn_mo->pinfo == INSN_MACRO)
2990 if (mips_opts.mips16)
2991 mips16_macro (&insn);
2998 if (imm_expr.X_op != O_absent)
2999 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
3000 else if (offset_expr.X_op != O_absent)
3001 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3003 append_insn (&insn, NULL, unused_reloc, FALSE);
3006 mips_assembling_insn = FALSE;
3009 /* Convenience functions for abstracting away the differences between
3010 MIPS16 and non-MIPS16 relocations. */
3012 static inline bfd_boolean
3013 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3017 case BFD_RELOC_MIPS16_JMP:
3018 case BFD_RELOC_MIPS16_GPREL:
3019 case BFD_RELOC_MIPS16_GOT16:
3020 case BFD_RELOC_MIPS16_CALL16:
3021 case BFD_RELOC_MIPS16_HI16_S:
3022 case BFD_RELOC_MIPS16_HI16:
3023 case BFD_RELOC_MIPS16_LO16:
3031 static inline bfd_boolean
3032 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3036 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3037 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3038 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3039 case BFD_RELOC_MICROMIPS_GPREL16:
3040 case BFD_RELOC_MICROMIPS_JMP:
3041 case BFD_RELOC_MICROMIPS_HI16:
3042 case BFD_RELOC_MICROMIPS_HI16_S:
3043 case BFD_RELOC_MICROMIPS_LO16:
3044 case BFD_RELOC_MICROMIPS_LITERAL:
3045 case BFD_RELOC_MICROMIPS_GOT16:
3046 case BFD_RELOC_MICROMIPS_CALL16:
3047 case BFD_RELOC_MICROMIPS_GOT_HI16:
3048 case BFD_RELOC_MICROMIPS_GOT_LO16:
3049 case BFD_RELOC_MICROMIPS_CALL_HI16:
3050 case BFD_RELOC_MICROMIPS_CALL_LO16:
3051 case BFD_RELOC_MICROMIPS_SUB:
3052 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3053 case BFD_RELOC_MICROMIPS_GOT_OFST:
3054 case BFD_RELOC_MICROMIPS_GOT_DISP:
3055 case BFD_RELOC_MICROMIPS_HIGHEST:
3056 case BFD_RELOC_MICROMIPS_HIGHER:
3057 case BFD_RELOC_MICROMIPS_SCN_DISP:
3058 case BFD_RELOC_MICROMIPS_JALR:
3066 static inline bfd_boolean
3067 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3069 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3072 static inline bfd_boolean
3073 got16_reloc_p (bfd_reloc_code_real_type reloc)
3075 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3076 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3079 static inline bfd_boolean
3080 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3082 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3083 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3086 static inline bfd_boolean
3087 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3089 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3090 || reloc == BFD_RELOC_MICROMIPS_LO16);
3093 static inline bfd_boolean
3094 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3096 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3099 static inline bfd_boolean
3100 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3102 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3103 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3106 /* Return true if RELOC is a PC-relative relocation that does not have
3107 full address range. */
3109 static inline bfd_boolean
3110 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3114 case BFD_RELOC_16_PCREL_S2:
3115 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3116 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3117 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3120 case BFD_RELOC_32_PCREL:
3121 return HAVE_64BIT_ADDRESSES;
3128 /* Return true if the given relocation might need a matching %lo().
3129 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3130 need a matching %lo() when applied to local symbols. */
3132 static inline bfd_boolean
3133 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3135 return (HAVE_IN_PLACE_ADDENDS
3136 && (hi16_reloc_p (reloc)
3137 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3138 all GOT16 relocations evaluate to "G". */
3139 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3142 /* Return the type of %lo() reloc needed by RELOC, given that
3143 reloc_needs_lo_p. */
3145 static inline bfd_reloc_code_real_type
3146 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3148 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3149 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3153 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3156 static inline bfd_boolean
3157 fixup_has_matching_lo_p (fixS *fixp)
3159 return (fixp->fx_next != NULL
3160 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3161 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3162 && fixp->fx_offset == fixp->fx_next->fx_offset);
3165 /* This function returns true if modifying a register requires a
3169 reg_needs_delay (unsigned int reg)
3171 unsigned long prev_pinfo;
3173 prev_pinfo = history[0].insn_mo->pinfo;
3174 if (! mips_opts.noreorder
3175 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3176 && ! gpr_interlocks)
3177 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3178 && ! cop_interlocks)))
3180 /* A load from a coprocessor or from memory. All load delays
3181 delay the use of general register rt for one instruction. */
3182 /* Itbl support may require additional care here. */
3183 know (prev_pinfo & INSN_WRITE_GPR_T);
3184 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3191 /* Move all labels in LABELS to the current insertion point. TEXT_P
3192 says whether the labels refer to text or data. */
3195 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3197 struct insn_label_list *l;
3200 for (l = labels; l != NULL; l = l->next)
3202 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3203 symbol_set_frag (l->label, frag_now);
3204 val = (valueT) frag_now_fix ();
3205 /* MIPS16/microMIPS text labels are stored as odd. */
3206 if (text_p && HAVE_CODE_COMPRESSION)
3208 S_SET_VALUE (l->label, val);
3212 /* Move all labels in insn_labels to the current insertion point
3213 and treat them as text labels. */
3216 mips_move_text_labels (void)
3218 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3222 s_is_linkonce (symbolS *sym, segT from_seg)
3224 bfd_boolean linkonce = FALSE;
3225 segT symseg = S_GET_SEGMENT (sym);
3227 if (symseg != from_seg && !S_IS_LOCAL (sym))
3229 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3231 /* The GNU toolchain uses an extension for ELF: a section
3232 beginning with the magic string .gnu.linkonce is a
3233 linkonce section. */
3234 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3235 sizeof ".gnu.linkonce" - 1) == 0)
3241 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3242 linker to handle them specially, such as generating jalx instructions
3243 when needed. We also make them odd for the duration of the assembly,
3244 in order to generate the right sort of code. We will make them even
3245 in the adjust_symtab routine, while leaving them marked. This is
3246 convenient for the debugger and the disassembler. The linker knows
3247 to make them odd again. */
3250 mips_compressed_mark_label (symbolS *label)
3252 gas_assert (HAVE_CODE_COMPRESSION);
3254 if (mips_opts.mips16)
3255 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3257 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3258 if ((S_GET_VALUE (label) & 1) == 0
3259 /* Don't adjust the address if the label is global or weak, or
3260 in a link-once section, since we'll be emitting symbol reloc
3261 references to it which will be patched up by the linker, and
3262 the final value of the symbol may or may not be MIPS16/microMIPS. */
3263 && !S_IS_WEAK (label)
3264 && !S_IS_EXTERNAL (label)
3265 && !s_is_linkonce (label, now_seg))
3266 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3269 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3272 mips_compressed_mark_labels (void)
3274 struct insn_label_list *l;
3276 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3277 mips_compressed_mark_label (l->label);
3280 /* End the current frag. Make it a variant frag and record the
3284 relax_close_frag (void)
3286 mips_macro_warning.first_frag = frag_now;
3287 frag_var (rs_machine_dependent, 0, 0,
3288 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3289 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3291 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3292 mips_relax.first_fixup = 0;
3295 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3296 See the comment above RELAX_ENCODE for more details. */
3299 relax_start (symbolS *symbol)
3301 gas_assert (mips_relax.sequence == 0);
3302 mips_relax.sequence = 1;
3303 mips_relax.symbol = symbol;
3306 /* Start generating the second version of a relaxable sequence.
3307 See the comment above RELAX_ENCODE for more details. */
3312 gas_assert (mips_relax.sequence == 1);
3313 mips_relax.sequence = 2;
3316 /* End the current relaxable sequence. */
3321 gas_assert (mips_relax.sequence == 2);
3322 relax_close_frag ();
3323 mips_relax.sequence = 0;
3326 /* Return true if IP is a delayed branch or jump. */
3328 static inline bfd_boolean
3329 delayed_branch_p (const struct mips_cl_insn *ip)
3331 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3332 | INSN_COND_BRANCH_DELAY
3333 | INSN_COND_BRANCH_LIKELY)) != 0;
3336 /* Return true if IP is a compact branch or jump. */
3338 static inline bfd_boolean
3339 compact_branch_p (const struct mips_cl_insn *ip)
3341 if (mips_opts.mips16)
3342 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3343 | MIPS16_INSN_COND_BRANCH)) != 0;
3345 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3346 | INSN2_COND_BRANCH)) != 0;
3349 /* Return true if IP is an unconditional branch or jump. */
3351 static inline bfd_boolean
3352 uncond_branch_p (const struct mips_cl_insn *ip)
3354 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3355 || (mips_opts.mips16
3356 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3357 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3360 /* Return true if IP is a branch-likely instruction. */
3362 static inline bfd_boolean
3363 branch_likely_p (const struct mips_cl_insn *ip)
3365 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3368 /* Return the type of nop that should be used to fill the delay slot
3369 of delayed branch IP. */
3371 static struct mips_cl_insn *
3372 get_delay_slot_nop (const struct mips_cl_insn *ip)
3374 if (mips_opts.micromips
3375 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3376 return µmips_nop32_insn;
3380 /* Return the mask of core registers that IP reads or writes. */
3383 gpr_mod_mask (const struct mips_cl_insn *ip)
3385 unsigned long pinfo2;
3389 pinfo2 = ip->insn_mo->pinfo2;
3390 if (mips_opts.micromips)
3392 if (pinfo2 & INSN2_MOD_GPR_MD)
3393 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3394 if (pinfo2 & INSN2_MOD_GPR_MF)
3395 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3396 if (pinfo2 & INSN2_MOD_SP)
3402 /* Return the mask of core registers that IP reads. */
3405 gpr_read_mask (const struct mips_cl_insn *ip)
3407 unsigned long pinfo, pinfo2;
3410 mask = gpr_mod_mask (ip);
3411 pinfo = ip->insn_mo->pinfo;
3412 pinfo2 = ip->insn_mo->pinfo2;
3413 if (mips_opts.mips16)
3415 if (pinfo & MIPS16_INSN_READ_X)
3416 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3417 if (pinfo & MIPS16_INSN_READ_Y)
3418 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3419 if (pinfo & MIPS16_INSN_READ_T)
3421 if (pinfo & MIPS16_INSN_READ_SP)
3423 if (pinfo & MIPS16_INSN_READ_31)
3425 if (pinfo & MIPS16_INSN_READ_Z)
3426 mask |= 1 << (mips16_to_32_reg_map
3427 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3428 if (pinfo & MIPS16_INSN_READ_GPR_X)
3429 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3433 if (pinfo2 & INSN2_READ_GPR_D)
3434 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3435 if (pinfo & INSN_READ_GPR_T)
3436 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3437 if (pinfo & INSN_READ_GPR_S)
3438 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3439 if (pinfo2 & INSN2_READ_GP)
3441 if (pinfo2 & INSN2_READ_GPR_31)
3443 if (pinfo2 & INSN2_READ_GPR_Z)
3444 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3446 if (mips_opts.micromips)
3448 if (pinfo2 & INSN2_READ_GPR_MC)
3449 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3450 if (pinfo2 & INSN2_READ_GPR_ME)
3451 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3452 if (pinfo2 & INSN2_READ_GPR_MG)
3453 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3454 if (pinfo2 & INSN2_READ_GPR_MJ)
3455 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3456 if (pinfo2 & INSN2_READ_GPR_MMN)
3458 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3459 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3461 if (pinfo2 & INSN2_READ_GPR_MP)
3462 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3463 if (pinfo2 & INSN2_READ_GPR_MQ)
3464 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3466 /* Don't include register 0. */
3470 /* Return the mask of core registers that IP writes. */
3473 gpr_write_mask (const struct mips_cl_insn *ip)
3475 unsigned long pinfo, pinfo2;
3478 mask = gpr_mod_mask (ip);
3479 pinfo = ip->insn_mo->pinfo;
3480 pinfo2 = ip->insn_mo->pinfo2;
3481 if (mips_opts.mips16)
3483 if (pinfo & MIPS16_INSN_WRITE_X)
3484 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3485 if (pinfo & MIPS16_INSN_WRITE_Y)
3486 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3487 if (pinfo & MIPS16_INSN_WRITE_Z)
3488 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3489 if (pinfo & MIPS16_INSN_WRITE_T)
3491 if (pinfo & MIPS16_INSN_WRITE_SP)
3493 if (pinfo & MIPS16_INSN_WRITE_31)
3495 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3496 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3500 if (pinfo & INSN_WRITE_GPR_D)
3501 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3502 if (pinfo & INSN_WRITE_GPR_T)
3503 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3504 if (pinfo & INSN_WRITE_GPR_S)
3505 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3506 if (pinfo & INSN_WRITE_GPR_31)
3508 if (pinfo2 & INSN2_WRITE_GPR_Z)
3509 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3511 if (mips_opts.micromips)
3513 if (pinfo2 & INSN2_WRITE_GPR_MB)
3514 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3515 if (pinfo2 & INSN2_WRITE_GPR_MH)
3517 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3518 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3520 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3521 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3522 if (pinfo2 & INSN2_WRITE_GPR_MP)
3523 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3525 /* Don't include register 0. */
3529 /* Return the mask of floating-point registers that IP reads. */
3532 fpr_read_mask (const struct mips_cl_insn *ip)
3534 unsigned long pinfo, pinfo2;
3538 pinfo = ip->insn_mo->pinfo;
3539 pinfo2 = ip->insn_mo->pinfo2;
3540 if (!mips_opts.mips16)
3542 if (pinfo2 & INSN2_READ_FPR_D)
3543 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3544 if (pinfo & INSN_READ_FPR_S)
3545 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3546 if (pinfo & INSN_READ_FPR_T)
3547 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3548 if (pinfo & INSN_READ_FPR_R)
3549 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3550 if (pinfo2 & INSN2_READ_FPR_Z)
3551 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3553 /* Conservatively treat all operands to an FP_D instruction are doubles.
3554 (This is overly pessimistic for things like cvt.d.s.) */
3555 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3560 /* Return the mask of floating-point registers that IP writes. */
3563 fpr_write_mask (const struct mips_cl_insn *ip)
3565 unsigned long pinfo, pinfo2;
3569 pinfo = ip->insn_mo->pinfo;
3570 pinfo2 = ip->insn_mo->pinfo2;
3571 if (!mips_opts.mips16)
3573 if (pinfo & INSN_WRITE_FPR_D)
3574 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3575 if (pinfo & INSN_WRITE_FPR_S)
3576 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3577 if (pinfo & INSN_WRITE_FPR_T)
3578 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3579 if (pinfo2 & INSN2_WRITE_FPR_Z)
3580 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3582 /* Conservatively treat all operands to an FP_D instruction are doubles.
3583 (This is overly pessimistic for things like cvt.s.d.) */
3584 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3589 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3590 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3591 by VR4120 errata. */
3594 classify_vr4120_insn (const char *name)
3596 if (strncmp (name, "macc", 4) == 0)
3597 return FIX_VR4120_MACC;
3598 if (strncmp (name, "dmacc", 5) == 0)
3599 return FIX_VR4120_DMACC;
3600 if (strncmp (name, "mult", 4) == 0)
3601 return FIX_VR4120_MULT;
3602 if (strncmp (name, "dmult", 5) == 0)
3603 return FIX_VR4120_DMULT;
3604 if (strstr (name, "div"))
3605 return FIX_VR4120_DIV;
3606 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3607 return FIX_VR4120_MTHILO;
3608 return NUM_FIX_VR4120_CLASSES;
3611 #define INSN_ERET 0x42000018
3612 #define INSN_DERET 0x4200001f
3614 /* Return the number of instructions that must separate INSN1 and INSN2,
3615 where INSN1 is the earlier instruction. Return the worst-case value
3616 for any INSN2 if INSN2 is null. */
3619 insns_between (const struct mips_cl_insn *insn1,
3620 const struct mips_cl_insn *insn2)
3622 unsigned long pinfo1, pinfo2;
3625 /* This function needs to know which pinfo flags are set for INSN2
3626 and which registers INSN2 uses. The former is stored in PINFO2 and
3627 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3628 will have every flag set and INSN2_USES_GPR will always return true. */
3629 pinfo1 = insn1->insn_mo->pinfo;
3630 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3632 #define INSN2_USES_GPR(REG) \
3633 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3635 /* For most targets, write-after-read dependencies on the HI and LO
3636 registers must be separated by at least two instructions. */
3637 if (!hilo_interlocks)
3639 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3641 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3645 /* If we're working around r7000 errata, there must be two instructions
3646 between an mfhi or mflo and any instruction that uses the result. */
3647 if (mips_7000_hilo_fix
3648 && !mips_opts.micromips
3649 && MF_HILO_INSN (pinfo1)
3650 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3653 /* If we're working around 24K errata, one instruction is required
3654 if an ERET or DERET is followed by a branch instruction. */
3655 if (mips_fix_24k && !mips_opts.micromips)
3657 if (insn1->insn_opcode == INSN_ERET
3658 || insn1->insn_opcode == INSN_DERET)
3661 || insn2->insn_opcode == INSN_ERET
3662 || insn2->insn_opcode == INSN_DERET
3663 || delayed_branch_p (insn2))
3668 /* If working around VR4120 errata, check for combinations that need
3669 a single intervening instruction. */
3670 if (mips_fix_vr4120 && !mips_opts.micromips)
3672 unsigned int class1, class2;
3674 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3675 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3679 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3680 if (vr4120_conflicts[class1] & (1 << class2))
3685 if (!HAVE_CODE_COMPRESSION)
3687 /* Check for GPR or coprocessor load delays. All such delays
3688 are on the RT register. */
3689 /* Itbl support may require additional care here. */
3690 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3691 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3693 know (pinfo1 & INSN_WRITE_GPR_T);
3694 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3698 /* Check for generic coprocessor hazards.
3700 This case is not handled very well. There is no special
3701 knowledge of CP0 handling, and the coprocessors other than
3702 the floating point unit are not distinguished at all. */
3703 /* Itbl support may require additional care here. FIXME!
3704 Need to modify this to include knowledge about
3705 user specified delays! */
3706 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3707 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3709 /* Handle cases where INSN1 writes to a known general coprocessor
3710 register. There must be a one instruction delay before INSN2
3711 if INSN2 reads that register, otherwise no delay is needed. */
3712 mask = fpr_write_mask (insn1);
3715 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3720 /* Read-after-write dependencies on the control registers
3721 require a two-instruction gap. */
3722 if ((pinfo1 & INSN_WRITE_COND_CODE)
3723 && (pinfo2 & INSN_READ_COND_CODE))
3726 /* We don't know exactly what INSN1 does. If INSN2 is
3727 also a coprocessor instruction, assume there must be
3728 a one instruction gap. */
3729 if (pinfo2 & INSN_COP)
3734 /* Check for read-after-write dependencies on the coprocessor
3735 control registers in cases where INSN1 does not need a general
3736 coprocessor delay. This means that INSN1 is a floating point
3737 comparison instruction. */
3738 /* Itbl support may require additional care here. */
3739 else if (!cop_interlocks
3740 && (pinfo1 & INSN_WRITE_COND_CODE)
3741 && (pinfo2 & INSN_READ_COND_CODE))
3745 #undef INSN2_USES_GPR
3750 /* Return the number of nops that would be needed to work around the
3751 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3752 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3753 that are contained within the first IGNORE instructions of HIST. */
3756 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3757 const struct mips_cl_insn *insn)
3762 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3763 are not affected by the errata. */
3765 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3766 || strcmp (insn->insn_mo->name, "mtlo") == 0
3767 || strcmp (insn->insn_mo->name, "mthi") == 0))
3770 /* Search for the first MFLO or MFHI. */
3771 for (i = 0; i < MAX_VR4130_NOPS; i++)
3772 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3774 /* Extract the destination register. */
3775 mask = gpr_write_mask (&hist[i]);
3777 /* No nops are needed if INSN reads that register. */
3778 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3781 /* ...or if any of the intervening instructions do. */
3782 for (j = 0; j < i; j++)
3783 if (gpr_read_mask (&hist[j]) & mask)
3787 return MAX_VR4130_NOPS - i;
3792 #define BASE_REG_EQ(INSN1, INSN2) \
3793 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3794 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3796 /* Return the minimum alignment for this store instruction. */
3799 fix_24k_align_to (const struct mips_opcode *mo)
3801 if (strcmp (mo->name, "sh") == 0)
3804 if (strcmp (mo->name, "swc1") == 0
3805 || strcmp (mo->name, "swc2") == 0
3806 || strcmp (mo->name, "sw") == 0
3807 || strcmp (mo->name, "sc") == 0
3808 || strcmp (mo->name, "s.s") == 0)
3811 if (strcmp (mo->name, "sdc1") == 0
3812 || strcmp (mo->name, "sdc2") == 0
3813 || strcmp (mo->name, "s.d") == 0)
3820 struct fix_24k_store_info
3822 /* Immediate offset, if any, for this store instruction. */
3824 /* Alignment required by this store instruction. */
3826 /* True for register offsets. */
3827 int register_offset;
3830 /* Comparison function used by qsort. */
3833 fix_24k_sort (const void *a, const void *b)
3835 const struct fix_24k_store_info *pos1 = a;
3836 const struct fix_24k_store_info *pos2 = b;
3838 return (pos1->off - pos2->off);
3841 /* INSN is a store instruction. Try to record the store information
3842 in STINFO. Return false if the information isn't known. */
3845 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3846 const struct mips_cl_insn *insn)
3848 /* The instruction must have a known offset. */
3849 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3852 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3853 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3857 /* Return the number of nops that would be needed to work around the 24k
3858 "lost data on stores during refill" errata if instruction INSN
3859 immediately followed the 2 instructions described by HIST.
3860 Ignore hazards that are contained within the first IGNORE
3861 instructions of HIST.
3863 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3864 for the data cache refills and store data. The following describes
3865 the scenario where the store data could be lost.
3867 * A data cache miss, due to either a load or a store, causing fill
3868 data to be supplied by the memory subsystem
3869 * The first three doublewords of fill data are returned and written
3871 * A sequence of four stores occurs in consecutive cycles around the
3872 final doubleword of the fill:
3876 * Zero, One or more instructions
3879 The four stores A-D must be to different doublewords of the line that
3880 is being filled. The fourth instruction in the sequence above permits
3881 the fill of the final doubleword to be transferred from the FSB into
3882 the cache. In the sequence above, the stores may be either integer
3883 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3884 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3885 different doublewords on the line. If the floating point unit is
3886 running in 1:2 mode, it is not possible to create the sequence above
3887 using only floating point store instructions.
3889 In this case, the cache line being filled is incorrectly marked
3890 invalid, thereby losing the data from any store to the line that
3891 occurs between the original miss and the completion of the five
3892 cycle sequence shown above.
3894 The workarounds are:
3896 * Run the data cache in write-through mode.
3897 * Insert a non-store instruction between
3898 Store A and Store B or Store B and Store C. */
3901 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3902 const struct mips_cl_insn *insn)
3904 struct fix_24k_store_info pos[3];
3905 int align, i, base_offset;
3910 /* If the previous instruction wasn't a store, there's nothing to
3912 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3915 /* If the instructions after the previous one are unknown, we have
3916 to assume the worst. */
3920 /* Check whether we are dealing with three consecutive stores. */
3921 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3922 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3925 /* If we don't know the relationship between the store addresses,
3926 assume the worst. */
3927 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3928 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3931 if (!fix_24k_record_store_info (&pos[0], insn)
3932 || !fix_24k_record_store_info (&pos[1], &hist[0])
3933 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3936 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3938 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3939 X bytes and such that the base register + X is known to be aligned
3942 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3946 align = pos[0].align_to;
3947 base_offset = pos[0].off;
3948 for (i = 1; i < 3; i++)
3949 if (align < pos[i].align_to)
3951 align = pos[i].align_to;
3952 base_offset = pos[i].off;
3954 for (i = 0; i < 3; i++)
3955 pos[i].off -= base_offset;
3958 pos[0].off &= ~align + 1;
3959 pos[1].off &= ~align + 1;
3960 pos[2].off &= ~align + 1;
3962 /* If any two stores write to the same chunk, they also write to the
3963 same doubleword. The offsets are still sorted at this point. */
3964 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3967 /* A range of at least 9 bytes is needed for the stores to be in
3968 non-overlapping doublewords. */
3969 if (pos[2].off - pos[0].off <= 8)
3972 if (pos[2].off - pos[1].off >= 24
3973 || pos[1].off - pos[0].off >= 24
3974 || pos[2].off - pos[0].off >= 32)
3980 /* Return the number of nops that would be needed if instruction INSN
3981 immediately followed the MAX_NOPS instructions given by HIST,
3982 where HIST[0] is the most recent instruction. Ignore hazards
3983 between INSN and the first IGNORE instructions in HIST.
3985 If INSN is null, return the worse-case number of nops for any
3989 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3990 const struct mips_cl_insn *insn)
3992 int i, nops, tmp_nops;
3995 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3997 tmp_nops = insns_between (hist + i, insn) - i;
3998 if (tmp_nops > nops)
4002 if (mips_fix_vr4130 && !mips_opts.micromips)
4004 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
4005 if (tmp_nops > nops)
4009 if (mips_fix_24k && !mips_opts.micromips)
4011 tmp_nops = nops_for_24k (ignore, hist, insn);
4012 if (tmp_nops > nops)
4019 /* The variable arguments provide NUM_INSNS extra instructions that
4020 might be added to HIST. Return the largest number of nops that
4021 would be needed after the extended sequence, ignoring hazards
4022 in the first IGNORE instructions. */
4025 nops_for_sequence (int num_insns, int ignore,
4026 const struct mips_cl_insn *hist, ...)
4029 struct mips_cl_insn buffer[MAX_NOPS];
4030 struct mips_cl_insn *cursor;
4033 va_start (args, hist);
4034 cursor = buffer + num_insns;
4035 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4036 while (cursor > buffer)
4037 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4039 nops = nops_for_insn (ignore, buffer, NULL);
4044 /* Like nops_for_insn, but if INSN is a branch, take into account the
4045 worst-case delay for the branch target. */
4048 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4049 const struct mips_cl_insn *insn)
4053 nops = nops_for_insn (ignore, hist, insn);
4054 if (delayed_branch_p (insn))
4056 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4057 hist, insn, get_delay_slot_nop (insn));
4058 if (tmp_nops > nops)
4061 else if (compact_branch_p (insn))
4063 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4064 if (tmp_nops > nops)
4070 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4073 fix_loongson2f_nop (struct mips_cl_insn * ip)
4075 gas_assert (!HAVE_CODE_COMPRESSION);
4076 if (strcmp (ip->insn_mo->name, "nop") == 0)
4077 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4080 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4081 jr target pc &= 'hffff_ffff_cfff_ffff. */
4084 fix_loongson2f_jump (struct mips_cl_insn * ip)
4086 gas_assert (!HAVE_CODE_COMPRESSION);
4087 if (strcmp (ip->insn_mo->name, "j") == 0
4088 || strcmp (ip->insn_mo->name, "jr") == 0
4089 || strcmp (ip->insn_mo->name, "jalr") == 0)
4097 sreg = EXTRACT_OPERAND (0, RS, *ip);
4098 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4101 ep.X_op = O_constant;
4102 ep.X_add_number = 0xcfff0000;
4103 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4104 ep.X_add_number = 0xffff;
4105 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4106 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4111 fix_loongson2f (struct mips_cl_insn * ip)
4113 if (mips_fix_loongson2f_nop)
4114 fix_loongson2f_nop (ip);
4116 if (mips_fix_loongson2f_jump)
4117 fix_loongson2f_jump (ip);
4120 /* IP is a branch that has a delay slot, and we need to fill it
4121 automatically. Return true if we can do that by swapping IP
4122 with the previous instruction.
4123 ADDRESS_EXPR is an operand of the instruction to be used with
4127 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4128 bfd_reloc_code_real_type *reloc_type)
4130 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4131 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4133 /* -O2 and above is required for this optimization. */
4134 if (mips_optimize < 2)
4137 /* If we have seen .set volatile or .set nomove, don't optimize. */
4138 if (mips_opts.nomove)
4141 /* We can't swap if the previous instruction's position is fixed. */
4142 if (history[0].fixed_p)
4145 /* If the previous previous insn was in a .set noreorder, we can't
4146 swap. Actually, the MIPS assembler will swap in this situation.
4147 However, gcc configured -with-gnu-as will generate code like
4155 in which we can not swap the bne and INSN. If gcc is not configured
4156 -with-gnu-as, it does not output the .set pseudo-ops. */
4157 if (history[1].noreorder_p)
4160 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4161 This means that the previous instruction was a 4-byte one anyhow. */
4162 if (mips_opts.mips16 && history[0].fixp[0])
4165 /* If the branch is itself the target of a branch, we can not swap.
4166 We cheat on this; all we check for is whether there is a label on
4167 this instruction. If there are any branches to anything other than
4168 a label, users must use .set noreorder. */
4169 if (seg_info (now_seg)->label_list)
4172 /* If the previous instruction is in a variant frag other than this
4173 branch's one, we cannot do the swap. This does not apply to
4174 MIPS16 code, which uses variant frags for different purposes. */
4175 if (!mips_opts.mips16
4177 && history[0].frag->fr_type == rs_machine_dependent)
4180 /* We do not swap with instructions that cannot architecturally
4181 be placed in a branch delay slot, such as SYNC or ERET. We
4182 also refrain from swapping with a trap instruction, since it
4183 complicates trap handlers to have the trap instruction be in
4185 prev_pinfo = history[0].insn_mo->pinfo;
4186 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4189 /* Check for conflicts between the branch and the instructions
4190 before the candidate delay slot. */
4191 if (nops_for_insn (0, history + 1, ip) > 0)
4194 /* Check for conflicts between the swapped sequence and the
4195 target of the branch. */
4196 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4199 /* If the branch reads a register that the previous
4200 instruction sets, we can not swap. */
4201 gpr_read = gpr_read_mask (ip);
4202 prev_gpr_write = gpr_write_mask (&history[0]);
4203 if (gpr_read & prev_gpr_write)
4206 /* If the branch writes a register that the previous
4207 instruction sets, we can not swap. */
4208 gpr_write = gpr_write_mask (ip);
4209 if (gpr_write & prev_gpr_write)
4212 /* If the branch writes a register that the previous
4213 instruction reads, we can not swap. */
4214 prev_gpr_read = gpr_read_mask (&history[0]);
4215 if (gpr_write & prev_gpr_read)
4218 /* If one instruction sets a condition code and the
4219 other one uses a condition code, we can not swap. */
4220 pinfo = ip->insn_mo->pinfo;
4221 if ((pinfo & INSN_READ_COND_CODE)
4222 && (prev_pinfo & INSN_WRITE_COND_CODE))
4224 if ((pinfo & INSN_WRITE_COND_CODE)
4225 && (prev_pinfo & INSN_READ_COND_CODE))
4228 /* If the previous instruction uses the PC, we can not swap. */
4229 prev_pinfo2 = history[0].insn_mo->pinfo2;
4230 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4232 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4235 /* If the previous instruction has an incorrect size for a fixed
4236 branch delay slot in microMIPS mode, we cannot swap. */
4237 pinfo2 = ip->insn_mo->pinfo2;
4238 if (mips_opts.micromips
4239 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4240 && insn_length (history) != 2)
4242 if (mips_opts.micromips
4243 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4244 && insn_length (history) != 4)
4247 /* On R5900 short loops need to be fixed by inserting a nop in
4248 the branch delay slots.
4249 A short loop can be terminated too early. */
4250 if (mips_opts.arch == CPU_R5900
4251 /* Check if instruction has a parameter, ignore "j $31". */
4252 && (address_expr != NULL)
4253 /* Parameter must be 16 bit. */
4254 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4255 /* Branch to same segment. */
4256 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4257 /* Branch to same code fragment. */
4258 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4259 /* Can only calculate branch offset if value is known. */
4260 && symbol_constant_p(address_expr->X_add_symbol)
4261 /* Check if branch is really conditional. */
4262 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4263 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4264 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4267 /* Check if loop is shorter than 6 instructions including
4268 branch and delay slot. */
4269 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4276 /* When the loop includes branches or jumps,
4277 it is not a short loop. */
4278 for (i = 0; i < (distance / 4); i++)
4280 if ((history[i].cleared_p)
4281 || delayed_branch_p(&history[i]))
4289 /* Insert nop after branch to fix short loop. */
4298 /* Decide how we should add IP to the instruction stream.
4299 ADDRESS_EXPR is an operand of the instruction to be used with
4302 static enum append_method
4303 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4304 bfd_reloc_code_real_type *reloc_type)
4306 unsigned long pinfo;
4308 /* The relaxed version of a macro sequence must be inherently
4310 if (mips_relax.sequence == 2)
4313 /* We must not dabble with instructions in a ".set norerorder" block. */
4314 if (mips_opts.noreorder)
4317 /* Otherwise, it's our responsibility to fill branch delay slots. */
4318 if (delayed_branch_p (ip))
4320 if (!branch_likely_p (ip)
4321 && can_swap_branch_p (ip, address_expr, reloc_type))
4324 pinfo = ip->insn_mo->pinfo;
4325 if (mips_opts.mips16
4326 && ISA_SUPPORTS_MIPS16E
4327 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4328 return APPEND_ADD_COMPACT;
4330 return APPEND_ADD_WITH_NOP;
4336 /* IP is a MIPS16 instruction whose opcode we have just changed.
4337 Point IP->insn_mo to the new opcode's definition. */
4340 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4342 const struct mips_opcode *mo, *end;
4344 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4345 for (mo = ip->insn_mo; mo < end; mo++)
4346 if ((ip->insn_opcode & mo->mask) == mo->match)
4354 /* For microMIPS macros, we need to generate a local number label
4355 as the target of branches. */
4356 #define MICROMIPS_LABEL_CHAR '\037'
4357 static unsigned long micromips_target_label;
4358 static char micromips_target_name[32];
4361 micromips_label_name (void)
4363 char *p = micromips_target_name;
4364 char symbol_name_temporary[24];
4372 l = micromips_target_label;
4373 #ifdef LOCAL_LABEL_PREFIX
4374 *p++ = LOCAL_LABEL_PREFIX;
4377 *p++ = MICROMIPS_LABEL_CHAR;
4380 symbol_name_temporary[i++] = l % 10 + '0';
4385 *p++ = symbol_name_temporary[--i];
4388 return micromips_target_name;
4392 micromips_label_expr (expressionS *label_expr)
4394 label_expr->X_op = O_symbol;
4395 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4396 label_expr->X_add_number = 0;
4400 micromips_label_inc (void)
4402 micromips_target_label++;
4403 *micromips_target_name = '\0';
4407 micromips_add_label (void)
4411 s = colon (micromips_label_name ());
4412 micromips_label_inc ();
4413 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4416 /* If assembling microMIPS code, then return the microMIPS reloc
4417 corresponding to the requested one if any. Otherwise return
4418 the reloc unchanged. */
4420 static bfd_reloc_code_real_type
4421 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4423 static const bfd_reloc_code_real_type relocs[][2] =
4425 /* Keep sorted incrementally by the left-hand key. */
4426 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4427 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4428 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4429 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4430 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4431 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4432 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4433 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4434 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4435 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4436 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4437 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4438 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4439 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4440 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4441 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4442 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4443 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4444 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4445 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4446 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4447 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4448 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4449 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4450 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4451 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4452 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4454 bfd_reloc_code_real_type r;
4457 if (!mips_opts.micromips)
4459 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4465 return relocs[i][1];
4470 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4471 Return true on success, storing the resolved value in RESULT. */
4474 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4479 case BFD_RELOC_MIPS_HIGHEST:
4480 case BFD_RELOC_MICROMIPS_HIGHEST:
4481 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4484 case BFD_RELOC_MIPS_HIGHER:
4485 case BFD_RELOC_MICROMIPS_HIGHER:
4486 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4489 case BFD_RELOC_HI16_S:
4490 case BFD_RELOC_MICROMIPS_HI16_S:
4491 case BFD_RELOC_MIPS16_HI16_S:
4492 *result = ((operand + 0x8000) >> 16) & 0xffff;
4495 case BFD_RELOC_HI16:
4496 case BFD_RELOC_MICROMIPS_HI16:
4497 case BFD_RELOC_MIPS16_HI16:
4498 *result = (operand >> 16) & 0xffff;
4501 case BFD_RELOC_LO16:
4502 case BFD_RELOC_MICROMIPS_LO16:
4503 case BFD_RELOC_MIPS16_LO16:
4504 *result = operand & 0xffff;
4507 case BFD_RELOC_UNUSED:
4516 /* Output an instruction. IP is the instruction information.
4517 ADDRESS_EXPR is an operand of the instruction to be used with
4518 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4519 a macro expansion. */
4522 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4523 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4525 unsigned long prev_pinfo2, pinfo;
4526 bfd_boolean relaxed_branch = FALSE;
4527 enum append_method method;
4528 bfd_boolean relax32;
4531 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4532 fix_loongson2f (ip);
4534 file_ase_mips16 |= mips_opts.mips16;
4535 file_ase_micromips |= mips_opts.micromips;
4537 prev_pinfo2 = history[0].insn_mo->pinfo2;
4538 pinfo = ip->insn_mo->pinfo;
4540 if (mips_opts.micromips
4542 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4543 && micromips_insn_length (ip->insn_mo) != 2)
4544 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4545 && micromips_insn_length (ip->insn_mo) != 4)))
4546 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4547 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4549 if (address_expr == NULL)
4551 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4552 && reloc_type[1] == BFD_RELOC_UNUSED
4553 && reloc_type[2] == BFD_RELOC_UNUSED
4554 && address_expr->X_op == O_constant)
4556 switch (*reloc_type)
4558 case BFD_RELOC_MIPS_JMP:
4562 shift = mips_opts.micromips ? 1 : 2;
4563 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4564 as_bad (_("jump to misaligned address (0x%lx)"),
4565 (unsigned long) address_expr->X_add_number);
4566 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4572 case BFD_RELOC_MIPS16_JMP:
4573 if ((address_expr->X_add_number & 3) != 0)
4574 as_bad (_("jump to misaligned address (0x%lx)"),
4575 (unsigned long) address_expr->X_add_number);
4577 (((address_expr->X_add_number & 0x7c0000) << 3)
4578 | ((address_expr->X_add_number & 0xf800000) >> 7)
4579 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4583 case BFD_RELOC_16_PCREL_S2:
4587 shift = mips_opts.micromips ? 1 : 2;
4588 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4589 as_bad (_("branch to misaligned address (0x%lx)"),
4590 (unsigned long) address_expr->X_add_number);
4591 if (!mips_relax_branch)
4593 if ((address_expr->X_add_number + (1 << (shift + 15)))
4594 & ~((1 << (shift + 16)) - 1))
4595 as_bad (_("branch address range overflow (0x%lx)"),
4596 (unsigned long) address_expr->X_add_number);
4597 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4607 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4610 ip->insn_opcode |= value & 0xffff;
4618 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4620 /* There are a lot of optimizations we could do that we don't.
4621 In particular, we do not, in general, reorder instructions.
4622 If you use gcc with optimization, it will reorder
4623 instructions and generally do much more optimization then we
4624 do here; repeating all that work in the assembler would only
4625 benefit hand written assembly code, and does not seem worth
4627 int nops = (mips_optimize == 0
4628 ? nops_for_insn (0, history, NULL)
4629 : nops_for_insn_or_target (0, history, ip));
4633 unsigned long old_frag_offset;
4636 old_frag = frag_now;
4637 old_frag_offset = frag_now_fix ();
4639 for (i = 0; i < nops; i++)
4640 add_fixed_insn (NOP_INSN);
4641 insert_into_history (0, nops, NOP_INSN);
4645 listing_prev_line ();
4646 /* We may be at the start of a variant frag. In case we
4647 are, make sure there is enough space for the frag
4648 after the frags created by listing_prev_line. The
4649 argument to frag_grow here must be at least as large
4650 as the argument to all other calls to frag_grow in
4651 this file. We don't have to worry about being in the
4652 middle of a variant frag, because the variants insert
4653 all needed nop instructions themselves. */
4657 mips_move_text_labels ();
4659 #ifndef NO_ECOFF_DEBUGGING
4660 if (ECOFF_DEBUGGING)
4661 ecoff_fix_loc (old_frag, old_frag_offset);
4665 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4669 /* Work out how many nops in prev_nop_frag are needed by IP,
4670 ignoring hazards generated by the first prev_nop_frag_since
4672 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4673 gas_assert (nops <= prev_nop_frag_holds);
4675 /* Enforce NOPS as a minimum. */
4676 if (nops > prev_nop_frag_required)
4677 prev_nop_frag_required = nops;
4679 if (prev_nop_frag_holds == prev_nop_frag_required)
4681 /* Settle for the current number of nops. Update the history
4682 accordingly (for the benefit of any future .set reorder code). */
4683 prev_nop_frag = NULL;
4684 insert_into_history (prev_nop_frag_since,
4685 prev_nop_frag_holds, NOP_INSN);
4689 /* Allow this instruction to replace one of the nops that was
4690 tentatively added to prev_nop_frag. */
4691 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4692 prev_nop_frag_holds--;
4693 prev_nop_frag_since++;
4697 method = get_append_method (ip, address_expr, reloc_type);
4698 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4700 dwarf2_emit_insn (0);
4701 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4702 so "move" the instruction address accordingly.
4704 Also, it doesn't seem appropriate for the assembler to reorder .loc
4705 entries. If this instruction is a branch that we are going to swap
4706 with the previous instruction, the two instructions should be
4707 treated as a unit, and the debug information for both instructions
4708 should refer to the start of the branch sequence. Using the
4709 current position is certainly wrong when swapping a 32-bit branch
4710 and a 16-bit delay slot, since the current position would then be
4711 in the middle of a branch. */
4712 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4714 relax32 = (mips_relax_branch
4715 /* Don't try branch relaxation within .set nomacro, or within
4716 .set noat if we use $at for PIC computations. If it turns
4717 out that the branch was out-of-range, we'll get an error. */
4718 && !mips_opts.warn_about_macros
4719 && (mips_opts.at || mips_pic == NO_PIC)
4720 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4721 as they have no complementing branches. */
4722 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4724 if (!HAVE_CODE_COMPRESSION
4727 && *reloc_type == BFD_RELOC_16_PCREL_S2
4728 && delayed_branch_p (ip))
4730 relaxed_branch = TRUE;
4731 add_relaxed_insn (ip, (relaxed_branch_length
4733 uncond_branch_p (ip) ? -1
4734 : branch_likely_p (ip) ? 1
4738 uncond_branch_p (ip),
4739 branch_likely_p (ip),
4740 pinfo & INSN_WRITE_GPR_31,
4742 address_expr->X_add_symbol,
4743 address_expr->X_add_number);
4744 *reloc_type = BFD_RELOC_UNUSED;
4746 else if (mips_opts.micromips
4748 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4749 || *reloc_type > BFD_RELOC_UNUSED)
4750 && (delayed_branch_p (ip) || compact_branch_p (ip))
4751 /* Don't try branch relaxation when users specify
4752 16-bit/32-bit instructions. */
4753 && !forced_insn_length)
4755 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4756 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4757 int uncond = uncond_branch_p (ip) ? -1 : 0;
4758 int compact = compact_branch_p (ip);
4759 int al = pinfo & INSN_WRITE_GPR_31;
4762 gas_assert (address_expr != NULL);
4763 gas_assert (!mips_relax.sequence);
4765 relaxed_branch = TRUE;
4766 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4767 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4768 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4770 address_expr->X_add_symbol,
4771 address_expr->X_add_number);
4772 *reloc_type = BFD_RELOC_UNUSED;
4774 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4776 /* We need to set up a variant frag. */
4777 gas_assert (address_expr != NULL);
4778 add_relaxed_insn (ip, 4, 0,
4780 (*reloc_type - BFD_RELOC_UNUSED,
4781 forced_insn_length == 2, forced_insn_length == 4,
4782 delayed_branch_p (&history[0]),
4783 history[0].mips16_absolute_jump_p),
4784 make_expr_symbol (address_expr), 0);
4786 else if (mips_opts.mips16 && insn_length (ip) == 2)
4788 if (!delayed_branch_p (ip))
4789 /* Make sure there is enough room to swap this instruction with
4790 a following jump instruction. */
4792 add_fixed_insn (ip);
4796 if (mips_opts.mips16
4797 && mips_opts.noreorder
4798 && delayed_branch_p (&history[0]))
4799 as_warn (_("extended instruction in delay slot"));
4801 if (mips_relax.sequence)
4803 /* If we've reached the end of this frag, turn it into a variant
4804 frag and record the information for the instructions we've
4806 if (frag_room () < 4)
4807 relax_close_frag ();
4808 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4811 if (mips_relax.sequence != 2)
4813 if (mips_macro_warning.first_insn_sizes[0] == 0)
4814 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4815 mips_macro_warning.sizes[0] += insn_length (ip);
4816 mips_macro_warning.insns[0]++;
4818 if (mips_relax.sequence != 1)
4820 if (mips_macro_warning.first_insn_sizes[1] == 0)
4821 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4822 mips_macro_warning.sizes[1] += insn_length (ip);
4823 mips_macro_warning.insns[1]++;
4826 if (mips_opts.mips16)
4829 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4831 add_fixed_insn (ip);
4834 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4836 bfd_reloc_code_real_type final_type[3];
4837 reloc_howto_type *howto0;
4838 reloc_howto_type *howto;
4841 /* Perform any necessary conversion to microMIPS relocations
4842 and find out how many relocations there actually are. */
4843 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4844 final_type[i] = micromips_map_reloc (reloc_type[i]);
4846 /* In a compound relocation, it is the final (outermost)
4847 operator that determines the relocated field. */
4848 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4853 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4854 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4855 bfd_get_reloc_size (howto),
4857 howto0 && howto0->pc_relative,
4860 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4861 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4862 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4864 /* These relocations can have an addend that won't fit in
4865 4 octets for 64bit assembly. */
4867 && ! howto->partial_inplace
4868 && (reloc_type[0] == BFD_RELOC_16
4869 || reloc_type[0] == BFD_RELOC_32
4870 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4871 || reloc_type[0] == BFD_RELOC_GPREL16
4872 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4873 || reloc_type[0] == BFD_RELOC_GPREL32
4874 || reloc_type[0] == BFD_RELOC_64
4875 || reloc_type[0] == BFD_RELOC_CTOR
4876 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4877 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4878 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4879 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4880 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4881 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4882 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4883 || hi16_reloc_p (reloc_type[0])
4884 || lo16_reloc_p (reloc_type[0])))
4885 ip->fixp[0]->fx_no_overflow = 1;
4887 /* These relocations can have an addend that won't fit in 2 octets. */
4888 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4889 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4890 ip->fixp[0]->fx_no_overflow = 1;
4892 if (mips_relax.sequence)
4894 if (mips_relax.first_fixup == 0)
4895 mips_relax.first_fixup = ip->fixp[0];
4897 else if (reloc_needs_lo_p (*reloc_type))
4899 struct mips_hi_fixup *hi_fixup;
4901 /* Reuse the last entry if it already has a matching %lo. */
4902 hi_fixup = mips_hi_fixup_list;
4904 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4906 hi_fixup = ((struct mips_hi_fixup *)
4907 xmalloc (sizeof (struct mips_hi_fixup)));
4908 hi_fixup->next = mips_hi_fixup_list;
4909 mips_hi_fixup_list = hi_fixup;
4911 hi_fixup->fixp = ip->fixp[0];
4912 hi_fixup->seg = now_seg;
4915 /* Add fixups for the second and third relocations, if given.
4916 Note that the ABI allows the second relocation to be
4917 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4918 moment we only use RSS_UNDEF, but we could add support
4919 for the others if it ever becomes necessary. */
4920 for (i = 1; i < 3; i++)
4921 if (reloc_type[i] != BFD_RELOC_UNUSED)
4923 ip->fixp[i] = fix_new (ip->frag, ip->where,
4924 ip->fixp[0]->fx_size, NULL, 0,
4925 FALSE, final_type[i]);
4927 /* Use fx_tcbit to mark compound relocs. */
4928 ip->fixp[0]->fx_tcbit = 1;
4929 ip->fixp[i]->fx_tcbit = 1;
4934 /* Update the register mask information. */
4935 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4936 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4941 insert_into_history (0, 1, ip);
4944 case APPEND_ADD_WITH_NOP:
4946 struct mips_cl_insn *nop;
4948 insert_into_history (0, 1, ip);
4949 nop = get_delay_slot_nop (ip);
4950 add_fixed_insn (nop);
4951 insert_into_history (0, 1, nop);
4952 if (mips_relax.sequence)
4953 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4957 case APPEND_ADD_COMPACT:
4958 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4959 gas_assert (mips_opts.mips16);
4960 ip->insn_opcode |= 0x0080;
4961 find_altered_mips16_opcode (ip);
4963 insert_into_history (0, 1, ip);
4968 struct mips_cl_insn delay = history[0];
4969 if (mips_opts.mips16)
4971 know (delay.frag == ip->frag);
4972 move_insn (ip, delay.frag, delay.where);
4973 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4975 else if (relaxed_branch || delay.frag != ip->frag)
4977 /* Add the delay slot instruction to the end of the
4978 current frag and shrink the fixed part of the
4979 original frag. If the branch occupies the tail of
4980 the latter, move it backwards to cover the gap. */
4981 delay.frag->fr_fix -= branch_disp;
4982 if (delay.frag == ip->frag)
4983 move_insn (ip, ip->frag, ip->where - branch_disp);
4984 add_fixed_insn (&delay);
4988 move_insn (&delay, ip->frag,
4989 ip->where - branch_disp + insn_length (ip));
4990 move_insn (ip, history[0].frag, history[0].where);
4994 insert_into_history (0, 1, &delay);
4999 /* If we have just completed an unconditional branch, clear the history. */
5000 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
5001 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
5005 mips_no_prev_insn ();
5007 for (i = 0; i < ARRAY_SIZE (history); i++)
5008 history[i].cleared_p = 1;
5011 /* We need to emit a label at the end of branch-likely macros. */
5012 if (emit_branch_likely_macro)
5014 emit_branch_likely_macro = FALSE;
5015 micromips_add_label ();
5018 /* We just output an insn, so the next one doesn't have a label. */
5019 mips_clear_insn_labels ();
5022 /* Forget that there was any previous instruction or label.
5023 When BRANCH is true, the branch history is also flushed. */
5026 mips_no_prev_insn (void)
5028 prev_nop_frag = NULL;
5029 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
5030 mips_clear_insn_labels ();
5033 /* This function must be called before we emit something other than
5034 instructions. It is like mips_no_prev_insn except that it inserts
5035 any NOPS that might be needed by previous instructions. */
5038 mips_emit_delays (void)
5040 if (! mips_opts.noreorder)
5042 int nops = nops_for_insn (0, history, NULL);
5046 add_fixed_insn (NOP_INSN);
5047 mips_move_text_labels ();
5050 mips_no_prev_insn ();
5053 /* Start a (possibly nested) noreorder block. */
5056 start_noreorder (void)
5058 if (mips_opts.noreorder == 0)
5063 /* None of the instructions before the .set noreorder can be moved. */
5064 for (i = 0; i < ARRAY_SIZE (history); i++)
5065 history[i].fixed_p = 1;
5067 /* Insert any nops that might be needed between the .set noreorder
5068 block and the previous instructions. We will later remove any
5069 nops that turn out not to be needed. */
5070 nops = nops_for_insn (0, history, NULL);
5073 if (mips_optimize != 0)
5075 /* Record the frag which holds the nop instructions, so
5076 that we can remove them if we don't need them. */
5077 frag_grow (nops * NOP_INSN_SIZE);
5078 prev_nop_frag = frag_now;
5079 prev_nop_frag_holds = nops;
5080 prev_nop_frag_required = 0;
5081 prev_nop_frag_since = 0;
5084 for (; nops > 0; --nops)
5085 add_fixed_insn (NOP_INSN);
5087 /* Move on to a new frag, so that it is safe to simply
5088 decrease the size of prev_nop_frag. */
5089 frag_wane (frag_now);
5091 mips_move_text_labels ();
5093 mips_mark_labels ();
5094 mips_clear_insn_labels ();
5096 mips_opts.noreorder++;
5097 mips_any_noreorder = 1;
5100 /* End a nested noreorder block. */
5103 end_noreorder (void)
5105 mips_opts.noreorder--;
5106 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5108 /* Commit to inserting prev_nop_frag_required nops and go back to
5109 handling nop insertion the .set reorder way. */
5110 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5112 insert_into_history (prev_nop_frag_since,
5113 prev_nop_frag_required, NOP_INSN);
5114 prev_nop_frag = NULL;
5118 /* Set up global variables for the start of a new macro. */
5123 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5124 memset (&mips_macro_warning.first_insn_sizes, 0,
5125 sizeof (mips_macro_warning.first_insn_sizes));
5126 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5127 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5128 && delayed_branch_p (&history[0]));
5129 switch (history[0].insn_mo->pinfo2
5130 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5132 case INSN2_BRANCH_DELAY_32BIT:
5133 mips_macro_warning.delay_slot_length = 4;
5135 case INSN2_BRANCH_DELAY_16BIT:
5136 mips_macro_warning.delay_slot_length = 2;
5139 mips_macro_warning.delay_slot_length = 0;
5142 mips_macro_warning.first_frag = NULL;
5145 /* Given that a macro is longer than one instruction or of the wrong size,
5146 return the appropriate warning for it. Return null if no warning is
5147 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5148 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5149 and RELAX_NOMACRO. */
5152 macro_warning (relax_substateT subtype)
5154 if (subtype & RELAX_DELAY_SLOT)
5155 return _("Macro instruction expanded into multiple instructions"
5156 " in a branch delay slot");
5157 else if (subtype & RELAX_NOMACRO)
5158 return _("Macro instruction expanded into multiple instructions");
5159 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5160 | RELAX_DELAY_SLOT_SIZE_SECOND))
5161 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5162 ? _("Macro instruction expanded into a wrong size instruction"
5163 " in a 16-bit branch delay slot")
5164 : _("Macro instruction expanded into a wrong size instruction"
5165 " in a 32-bit branch delay slot"));
5170 /* Finish up a macro. Emit warnings as appropriate. */
5175 /* Relaxation warning flags. */
5176 relax_substateT subtype = 0;
5178 /* Check delay slot size requirements. */
5179 if (mips_macro_warning.delay_slot_length == 2)
5180 subtype |= RELAX_DELAY_SLOT_16BIT;
5181 if (mips_macro_warning.delay_slot_length != 0)
5183 if (mips_macro_warning.delay_slot_length
5184 != mips_macro_warning.first_insn_sizes[0])
5185 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5186 if (mips_macro_warning.delay_slot_length
5187 != mips_macro_warning.first_insn_sizes[1])
5188 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5191 /* Check instruction count requirements. */
5192 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5194 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5195 subtype |= RELAX_SECOND_LONGER;
5196 if (mips_opts.warn_about_macros)
5197 subtype |= RELAX_NOMACRO;
5198 if (mips_macro_warning.delay_slot_p)
5199 subtype |= RELAX_DELAY_SLOT;
5202 /* If both alternatives fail to fill a delay slot correctly,
5203 emit the warning now. */
5204 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5205 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5210 s = subtype & (RELAX_DELAY_SLOT_16BIT
5211 | RELAX_DELAY_SLOT_SIZE_FIRST
5212 | RELAX_DELAY_SLOT_SIZE_SECOND);
5213 msg = macro_warning (s);
5215 as_warn ("%s", msg);
5219 /* If both implementations are longer than 1 instruction, then emit the
5221 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5226 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5227 msg = macro_warning (s);
5229 as_warn ("%s", msg);
5233 /* If any flags still set, then one implementation might need a warning
5234 and the other either will need one of a different kind or none at all.
5235 Pass any remaining flags over to relaxation. */
5236 if (mips_macro_warning.first_frag != NULL)
5237 mips_macro_warning.first_frag->fr_subtype |= subtype;
5240 /* Instruction operand formats used in macros that vary between
5241 standard MIPS and microMIPS code. */
5243 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
5244 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5245 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5246 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5247 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5248 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
5249 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5250 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5252 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5253 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5254 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5255 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5256 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5257 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5258 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5259 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5261 /* Read a macro's relocation codes from *ARGS and store them in *R.
5262 The first argument in *ARGS will be either the code for a single
5263 relocation or -1 followed by the three codes that make up a
5264 composite relocation. */
5267 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5271 next = va_arg (*args, int);
5273 r[0] = (bfd_reloc_code_real_type) next;
5276 for (i = 0; i < 3; i++)
5277 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5278 /* This function is only used for 16-bit relocation fields.
5279 To make the macro code simpler, treat an unrelocated value
5280 in the same way as BFD_RELOC_LO16. */
5281 if (r[0] == BFD_RELOC_UNUSED)
5282 r[0] = BFD_RELOC_LO16;
5286 /* Build an instruction created by a macro expansion. This is passed
5287 a pointer to the count of instructions created so far, an
5288 expression, the name of the instruction to build, an operand format
5289 string, and corresponding arguments. */
5292 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5294 const struct mips_opcode *mo = NULL;
5295 bfd_reloc_code_real_type r[3];
5296 const struct mips_opcode *amo;
5297 struct hash_control *hash;
5298 struct mips_cl_insn insn;
5301 va_start (args, fmt);
5303 if (mips_opts.mips16)
5305 mips16_macro_build (ep, name, fmt, &args);
5310 r[0] = BFD_RELOC_UNUSED;
5311 r[1] = BFD_RELOC_UNUSED;
5312 r[2] = BFD_RELOC_UNUSED;
5313 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5314 amo = (struct mips_opcode *) hash_find (hash, name);
5316 gas_assert (strcmp (name, amo->name) == 0);
5320 /* Search until we get a match for NAME. It is assumed here that
5321 macros will never generate MDMX, MIPS-3D, or MT instructions.
5322 We try to match an instruction that fulfils the branch delay
5323 slot instruction length requirement (if any) of the previous
5324 instruction. While doing this we record the first instruction
5325 seen that matches all the other conditions and use it anyway
5326 if the requirement cannot be met; we will issue an appropriate
5327 warning later on. */
5328 if (strcmp (fmt, amo->args) == 0
5329 && amo->pinfo != INSN_MACRO
5330 && is_opcode_valid (amo)
5331 && is_size_valid (amo))
5333 if (is_delay_slot_valid (amo))
5343 gas_assert (amo->name);
5345 while (strcmp (name, amo->name) == 0);
5348 create_insn (&insn, mo);
5366 INSERT_OPERAND (mips_opts.micromips,
5367 EXTLSB, insn, va_arg (args, int));
5372 /* Note that in the macro case, these arguments are already
5373 in MSB form. (When handling the instruction in the
5374 non-macro case, these arguments are sizes from which
5375 MSB values must be calculated.) */
5376 INSERT_OPERAND (mips_opts.micromips,
5377 INSMSB, insn, va_arg (args, int));
5381 gas_assert (!mips_opts.micromips);
5382 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5388 /* Note that in the macro case, these arguments are already
5389 in MSBD form. (When handling the instruction in the
5390 non-macro case, these arguments are sizes from which
5391 MSBD values must be calculated.) */
5392 INSERT_OPERAND (mips_opts.micromips,
5393 EXTMSBD, insn, va_arg (args, int));
5397 gas_assert (!mips_opts.micromips);
5398 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5402 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5411 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5415 gas_assert (mips_opts.micromips);
5419 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5423 INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int));
5427 gas_assert (!mips_opts.micromips);
5429 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5433 if (mips_opts.micromips)
5434 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5436 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5440 gas_assert (!mips_opts.micromips);
5442 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5446 gas_assert (!mips_opts.micromips);
5448 int tmp = va_arg (args, int);
5450 INSERT_OPERAND (0, RT, insn, tmp);
5451 INSERT_OPERAND (0, RD, insn, tmp);
5457 gas_assert (!mips_opts.micromips);
5458 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5465 INSERT_OPERAND (mips_opts.micromips,
5466 SHAMT, insn, va_arg (args, int));
5470 gas_assert (!mips_opts.micromips);
5471 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5475 gas_assert (!mips_opts.micromips);
5476 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5480 gas_assert (!mips_opts.micromips);
5481 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5485 gas_assert (!mips_opts.micromips);
5486 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5493 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5498 macro_read_relocs (&args, r);
5499 gas_assert (*r == BFD_RELOC_GPREL16
5500 || *r == BFD_RELOC_MIPS_HIGHER
5501 || *r == BFD_RELOC_HI16_S
5502 || *r == BFD_RELOC_LO16
5503 || *r == BFD_RELOC_MIPS_GOT_OFST);
5507 macro_read_relocs (&args, r);
5511 macro_read_relocs (&args, r);
5512 gas_assert (ep != NULL
5513 && (ep->X_op == O_constant
5514 || (ep->X_op == O_symbol
5515 && (*r == BFD_RELOC_MIPS_HIGHEST
5516 || *r == BFD_RELOC_HI16_S
5517 || *r == BFD_RELOC_HI16
5518 || *r == BFD_RELOC_GPREL16
5519 || *r == BFD_RELOC_MIPS_GOT_HI16
5520 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5524 gas_assert (ep != NULL);
5527 * This allows macro() to pass an immediate expression for
5528 * creating short branches without creating a symbol.
5530 * We don't allow branch relaxation for these branches, as
5531 * they should only appear in ".set nomacro" anyway.
5533 if (ep->X_op == O_constant)
5535 /* For microMIPS we always use relocations for branches.
5536 So we should not resolve immediate values. */
5537 gas_assert (!mips_opts.micromips);
5539 if ((ep->X_add_number & 3) != 0)
5540 as_bad (_("branch to misaligned address (0x%lx)"),
5541 (unsigned long) ep->X_add_number);
5542 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5543 as_bad (_("branch address range overflow (0x%lx)"),
5544 (unsigned long) ep->X_add_number);
5545 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5549 *r = BFD_RELOC_16_PCREL_S2;
5553 gas_assert (ep != NULL);
5554 *r = BFD_RELOC_MIPS_JMP;
5558 gas_assert (!mips_opts.micromips);
5559 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5563 INSERT_OPERAND (mips_opts.micromips,
5564 CACHE, insn, va_arg (args, unsigned long));
5568 gas_assert (mips_opts.micromips);
5569 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5573 gas_assert (mips_opts.micromips);
5574 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5578 INSERT_OPERAND (mips_opts.micromips,
5579 3BITPOS, insn, va_arg (args, unsigned int));
5583 INSERT_OPERAND (mips_opts.micromips,
5584 OFFSET12, insn, va_arg (args, unsigned long));
5588 gas_assert (mips_opts.micromips);
5589 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5592 case 'm': /* Opcode extension character. */
5593 gas_assert (mips_opts.micromips);
5597 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5601 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5605 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5619 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5621 append_insn (&insn, ep, r, TRUE);
5625 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5628 struct mips_opcode *mo;
5629 struct mips_cl_insn insn;
5630 bfd_reloc_code_real_type r[3]
5631 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5633 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5635 gas_assert (strcmp (name, mo->name) == 0);
5637 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5640 gas_assert (mo->name);
5641 gas_assert (strcmp (name, mo->name) == 0);
5644 create_insn (&insn, mo);
5662 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5667 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5671 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5675 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5685 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5692 regno = va_arg (*args, int);
5693 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5694 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5717 gas_assert (ep != NULL);
5719 if (ep->X_op != O_constant)
5720 *r = (int) BFD_RELOC_UNUSED + c;
5721 else if (calculate_reloc (*r, ep->X_add_number, &value))
5723 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5725 *r = BFD_RELOC_UNUSED;
5731 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5738 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5740 append_insn (&insn, ep, r, TRUE);
5744 * Sign-extend 32-bit mode constants that have bit 31 set and all
5745 * higher bits unset.
5748 normalize_constant_expr (expressionS *ex)
5750 if (ex->X_op == O_constant
5751 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5752 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5757 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5758 * all higher bits unset.
5761 normalize_address_expr (expressionS *ex)
5763 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5764 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5765 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5766 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5771 * Generate a "jalr" instruction with a relocation hint to the called
5772 * function. This occurs in NewABI PIC code.
5775 macro_build_jalr (expressionS *ep, int cprestore)
5777 static const bfd_reloc_code_real_type jalr_relocs[2]
5778 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5779 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5783 if (MIPS_JALR_HINT_P (ep))
5788 if (mips_opts.micromips)
5790 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
5791 ? "jalr" : "jalrs");
5792 if (MIPS_JALR_HINT_P (ep)
5794 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5795 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5797 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5800 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5801 if (MIPS_JALR_HINT_P (ep))
5802 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5806 * Generate a "lui" instruction.
5809 macro_build_lui (expressionS *ep, int regnum)
5811 gas_assert (! mips_opts.mips16);
5813 if (ep->X_op != O_constant)
5815 gas_assert (ep->X_op == O_symbol);
5816 /* _gp_disp is a special case, used from s_cpload.
5817 __gnu_local_gp is used if mips_no_shared. */
5818 gas_assert (mips_pic == NO_PIC
5820 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5821 || (! mips_in_shared
5822 && strcmp (S_GET_NAME (ep->X_add_symbol),
5823 "__gnu_local_gp") == 0));
5826 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5829 /* Generate a sequence of instructions to do a load or store from a constant
5830 offset off of a base register (breg) into/from a target register (treg),
5831 using AT if necessary. */
5833 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5834 int treg, int breg, int dbl)
5836 gas_assert (ep->X_op == O_constant);
5838 /* Sign-extending 32-bit constants makes their handling easier. */
5840 normalize_constant_expr (ep);
5842 /* Right now, this routine can only handle signed 32-bit constants. */
5843 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5844 as_warn (_("operand overflow"));
5846 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5848 /* Signed 16-bit offset will fit in the op. Easy! */
5849 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5853 /* 32-bit offset, need multiple instructions and AT, like:
5854 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5855 addu $tempreg,$tempreg,$breg
5856 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5857 to handle the complete offset. */
5858 macro_build_lui (ep, AT);
5859 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5860 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5863 as_bad (_("Macro used $at after \".set noat\""));
5868 * Generates code to set the $at register to true (one)
5869 * if reg is less than the immediate expression.
5872 set_at (int reg, int unsignedp)
5874 if (imm_expr.X_op == O_constant
5875 && imm_expr.X_add_number >= -0x8000
5876 && imm_expr.X_add_number < 0x8000)
5877 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5878 AT, reg, BFD_RELOC_LO16);
5881 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5882 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5886 /* Warn if an expression is not a constant. */
5889 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5891 if (ex->X_op == O_big)
5892 as_bad (_("unsupported large constant"));
5893 else if (ex->X_op != O_constant)
5894 as_bad (_("Instruction %s requires absolute expression"),
5897 if (HAVE_32BIT_GPRS)
5898 normalize_constant_expr (ex);
5901 /* Count the leading zeroes by performing a binary chop. This is a
5902 bulky bit of source, but performance is a LOT better for the
5903 majority of values than a simple loop to count the bits:
5904 for (lcnt = 0; (lcnt < 32); lcnt++)
5905 if ((v) & (1 << (31 - lcnt)))
5907 However it is not code size friendly, and the gain will drop a bit
5908 on certain cached systems.
5910 #define COUNT_TOP_ZEROES(v) \
5911 (((v) & ~0xffff) == 0 \
5912 ? ((v) & ~0xff) == 0 \
5913 ? ((v) & ~0xf) == 0 \
5914 ? ((v) & ~0x3) == 0 \
5915 ? ((v) & ~0x1) == 0 \
5920 : ((v) & ~0x7) == 0 \
5923 : ((v) & ~0x3f) == 0 \
5924 ? ((v) & ~0x1f) == 0 \
5927 : ((v) & ~0x7f) == 0 \
5930 : ((v) & ~0xfff) == 0 \
5931 ? ((v) & ~0x3ff) == 0 \
5932 ? ((v) & ~0x1ff) == 0 \
5935 : ((v) & ~0x7ff) == 0 \
5938 : ((v) & ~0x3fff) == 0 \
5939 ? ((v) & ~0x1fff) == 0 \
5942 : ((v) & ~0x7fff) == 0 \
5945 : ((v) & ~0xffffff) == 0 \
5946 ? ((v) & ~0xfffff) == 0 \
5947 ? ((v) & ~0x3ffff) == 0 \
5948 ? ((v) & ~0x1ffff) == 0 \
5951 : ((v) & ~0x7ffff) == 0 \
5954 : ((v) & ~0x3fffff) == 0 \
5955 ? ((v) & ~0x1fffff) == 0 \
5958 : ((v) & ~0x7fffff) == 0 \
5961 : ((v) & ~0xfffffff) == 0 \
5962 ? ((v) & ~0x3ffffff) == 0 \
5963 ? ((v) & ~0x1ffffff) == 0 \
5966 : ((v) & ~0x7ffffff) == 0 \
5969 : ((v) & ~0x3fffffff) == 0 \
5970 ? ((v) & ~0x1fffffff) == 0 \
5973 : ((v) & ~0x7fffffff) == 0 \
5978 * This routine generates the least number of instructions necessary to load
5979 * an absolute expression value into a register.
5982 load_register (int reg, expressionS *ep, int dbl)
5985 expressionS hi32, lo32;
5987 if (ep->X_op != O_big)
5989 gas_assert (ep->X_op == O_constant);
5991 /* Sign-extending 32-bit constants makes their handling easier. */
5993 normalize_constant_expr (ep);
5995 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5997 /* We can handle 16 bit signed values with an addiu to
5998 $zero. No need to ever use daddiu here, since $zero and
5999 the result are always correct in 32 bit mode. */
6000 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6003 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
6005 /* We can handle 16 bit unsigned values with an ori to
6007 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6010 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
6012 /* 32 bit values require an lui. */
6013 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6014 if ((ep->X_add_number & 0xffff) != 0)
6015 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6020 /* The value is larger than 32 bits. */
6022 if (!dbl || HAVE_32BIT_GPRS)
6026 sprintf_vma (value, ep->X_add_number);
6027 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6028 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6032 if (ep->X_op != O_big)
6035 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6036 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6037 hi32.X_add_number &= 0xffffffff;
6039 lo32.X_add_number &= 0xffffffff;
6043 gas_assert (ep->X_add_number > 2);
6044 if (ep->X_add_number == 3)
6045 generic_bignum[3] = 0;
6046 else if (ep->X_add_number > 4)
6047 as_bad (_("Number larger than 64 bits"));
6048 lo32.X_op = O_constant;
6049 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6050 hi32.X_op = O_constant;
6051 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6054 if (hi32.X_add_number == 0)
6059 unsigned long hi, lo;
6061 if (hi32.X_add_number == (offsetT) 0xffffffff)
6063 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6065 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6068 if (lo32.X_add_number & 0x80000000)
6070 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6071 if (lo32.X_add_number & 0xffff)
6072 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6077 /* Check for 16bit shifted constant. We know that hi32 is
6078 non-zero, so start the mask on the first bit of the hi32
6083 unsigned long himask, lomask;
6087 himask = 0xffff >> (32 - shift);
6088 lomask = (0xffff << shift) & 0xffffffff;
6092 himask = 0xffff << (shift - 32);
6095 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6096 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6100 tmp.X_op = O_constant;
6102 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6103 | (lo32.X_add_number >> shift));
6105 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6106 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6107 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6108 reg, reg, (shift >= 32) ? shift - 32 : shift);
6113 while (shift <= (64 - 16));
6115 /* Find the bit number of the lowest one bit, and store the
6116 shifted value in hi/lo. */
6117 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6118 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6122 while ((lo & 1) == 0)
6127 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6133 while ((hi & 1) == 0)
6142 /* Optimize if the shifted value is a (power of 2) - 1. */
6143 if ((hi == 0 && ((lo + 1) & lo) == 0)
6144 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6146 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6151 /* This instruction will set the register to be all
6153 tmp.X_op = O_constant;
6154 tmp.X_add_number = (offsetT) -1;
6155 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6159 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6160 reg, reg, (bit >= 32) ? bit - 32 : bit);
6162 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6163 reg, reg, (shift >= 32) ? shift - 32 : shift);
6168 /* Sign extend hi32 before calling load_register, because we can
6169 generally get better code when we load a sign extended value. */
6170 if ((hi32.X_add_number & 0x80000000) != 0)
6171 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6172 load_register (reg, &hi32, 0);
6175 if ((lo32.X_add_number & 0xffff0000) == 0)
6179 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6187 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6189 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6190 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6196 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6200 mid16.X_add_number >>= 16;
6201 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6202 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6205 if ((lo32.X_add_number & 0xffff) != 0)
6206 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6210 load_delay_nop (void)
6212 if (!gpr_interlocks)
6213 macro_build (NULL, "nop", "");
6216 /* Load an address into a register. */
6219 load_address (int reg, expressionS *ep, int *used_at)
6221 if (ep->X_op != O_constant
6222 && ep->X_op != O_symbol)
6224 as_bad (_("expression too complex"));
6225 ep->X_op = O_constant;
6228 if (ep->X_op == O_constant)
6230 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6234 if (mips_pic == NO_PIC)
6236 /* If this is a reference to a GP relative symbol, we want
6237 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6239 lui $reg,<sym> (BFD_RELOC_HI16_S)
6240 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6241 If we have an addend, we always use the latter form.
6243 With 64bit address space and a usable $at we want
6244 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6245 lui $at,<sym> (BFD_RELOC_HI16_S)
6246 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6247 daddiu $at,<sym> (BFD_RELOC_LO16)
6251 If $at is already in use, we use a path which is suboptimal
6252 on superscalar processors.
6253 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6254 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6256 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6258 daddiu $reg,<sym> (BFD_RELOC_LO16)
6260 For GP relative symbols in 64bit address space we can use
6261 the same sequence as in 32bit address space. */
6262 if (HAVE_64BIT_SYMBOLS)
6264 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6265 && !nopic_need_relax (ep->X_add_symbol, 1))
6267 relax_start (ep->X_add_symbol);
6268 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6269 mips_gp_register, BFD_RELOC_GPREL16);
6273 if (*used_at == 0 && mips_opts.at)
6275 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6276 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6277 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6278 BFD_RELOC_MIPS_HIGHER);
6279 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6280 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6281 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6286 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6287 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6288 BFD_RELOC_MIPS_HIGHER);
6289 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6290 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6291 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6292 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6295 if (mips_relax.sequence)
6300 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6301 && !nopic_need_relax (ep->X_add_symbol, 1))
6303 relax_start (ep->X_add_symbol);
6304 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6305 mips_gp_register, BFD_RELOC_GPREL16);
6308 macro_build_lui (ep, reg);
6309 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6310 reg, reg, BFD_RELOC_LO16);
6311 if (mips_relax.sequence)
6315 else if (!mips_big_got)
6319 /* If this is a reference to an external symbol, we want
6320 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6322 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6324 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6325 If there is a constant, it must be added in after.
6327 If we have NewABI, we want
6328 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6329 unless we're referencing a global symbol with a non-zero
6330 offset, in which case cst must be added separately. */
6333 if (ep->X_add_number)
6335 ex.X_add_number = ep->X_add_number;
6336 ep->X_add_number = 0;
6337 relax_start (ep->X_add_symbol);
6338 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6339 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6340 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6341 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6342 ex.X_op = O_constant;
6343 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6344 reg, reg, BFD_RELOC_LO16);
6345 ep->X_add_number = ex.X_add_number;
6348 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6349 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6350 if (mips_relax.sequence)
6355 ex.X_add_number = ep->X_add_number;
6356 ep->X_add_number = 0;
6357 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6358 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6360 relax_start (ep->X_add_symbol);
6362 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6366 if (ex.X_add_number != 0)
6368 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6369 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6370 ex.X_op = O_constant;
6371 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6372 reg, reg, BFD_RELOC_LO16);
6376 else if (mips_big_got)
6380 /* This is the large GOT case. If this is a reference to an
6381 external symbol, we want
6382 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6384 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6386 Otherwise, for a reference to a local symbol in old ABI, we want
6387 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6389 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6390 If there is a constant, it must be added in after.
6392 In the NewABI, for local symbols, with or without offsets, we want:
6393 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6394 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6398 ex.X_add_number = ep->X_add_number;
6399 ep->X_add_number = 0;
6400 relax_start (ep->X_add_symbol);
6401 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6403 reg, reg, mips_gp_register);
6404 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6405 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6406 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6407 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6408 else if (ex.X_add_number)
6410 ex.X_op = O_constant;
6411 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6415 ep->X_add_number = ex.X_add_number;
6417 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6418 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6419 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6420 BFD_RELOC_MIPS_GOT_OFST);
6425 ex.X_add_number = ep->X_add_number;
6426 ep->X_add_number = 0;
6427 relax_start (ep->X_add_symbol);
6428 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6430 reg, reg, mips_gp_register);
6431 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6432 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6434 if (reg_needs_delay (mips_gp_register))
6436 /* We need a nop before loading from $gp. This special
6437 check is required because the lui which starts the main
6438 instruction stream does not refer to $gp, and so will not
6439 insert the nop which may be required. */
6440 macro_build (NULL, "nop", "");
6442 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6443 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6445 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6449 if (ex.X_add_number != 0)
6451 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6452 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6453 ex.X_op = O_constant;
6454 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6462 if (!mips_opts.at && *used_at == 1)
6463 as_bad (_("Macro used $at after \".set noat\""));
6466 /* Move the contents of register SOURCE into register DEST. */
6469 move_register (int dest, int source)
6471 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6472 instruction specifically requires a 32-bit one. */
6473 if (mips_opts.micromips
6474 && !mips_opts.insn32
6475 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6476 macro_build (NULL, "move", "mp,mj", dest, source);
6478 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6482 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6483 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6484 The two alternatives are:
6486 Global symbol Local sybmol
6487 ------------- ------------
6488 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6490 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6492 load_got_offset emits the first instruction and add_got_offset
6493 emits the second for a 16-bit offset or add_got_offset_hilo emits
6494 a sequence to add a 32-bit offset using a scratch register. */
6497 load_got_offset (int dest, expressionS *local)
6502 global.X_add_number = 0;
6504 relax_start (local->X_add_symbol);
6505 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6506 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6508 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6509 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6514 add_got_offset (int dest, expressionS *local)
6518 global.X_op = O_constant;
6519 global.X_op_symbol = NULL;
6520 global.X_add_symbol = NULL;
6521 global.X_add_number = local->X_add_number;
6523 relax_start (local->X_add_symbol);
6524 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6525 dest, dest, BFD_RELOC_LO16);
6527 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6532 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6535 int hold_mips_optimize;
6537 global.X_op = O_constant;
6538 global.X_op_symbol = NULL;
6539 global.X_add_symbol = NULL;
6540 global.X_add_number = local->X_add_number;
6542 relax_start (local->X_add_symbol);
6543 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6545 /* Set mips_optimize around the lui instruction to avoid
6546 inserting an unnecessary nop after the lw. */
6547 hold_mips_optimize = mips_optimize;
6549 macro_build_lui (&global, tmp);
6550 mips_optimize = hold_mips_optimize;
6551 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6554 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6557 /* Emit a sequence of instructions to emulate a branch likely operation.
6558 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6559 is its complementing branch with the original condition negated.
6560 CALL is set if the original branch specified the link operation.
6561 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6563 Code like this is produced in the noreorder mode:
6568 delay slot (executed only if branch taken)
6576 delay slot (executed only if branch taken)
6579 In the reorder mode the delay slot would be filled with a nop anyway,
6580 so code produced is simply:
6585 This function is used when producing code for the microMIPS ASE that
6586 does not implement branch likely instructions in hardware. */
6589 macro_build_branch_likely (const char *br, const char *brneg,
6590 int call, expressionS *ep, const char *fmt,
6591 unsigned int sreg, unsigned int treg)
6593 int noreorder = mips_opts.noreorder;
6596 gas_assert (mips_opts.micromips);
6600 micromips_label_expr (&expr1);
6601 macro_build (&expr1, brneg, fmt, sreg, treg);
6602 macro_build (NULL, "nop", "");
6603 macro_build (ep, call ? "bal" : "b", "p");
6605 /* Set to true so that append_insn adds a label. */
6606 emit_branch_likely_macro = TRUE;
6610 macro_build (ep, br, fmt, sreg, treg);
6611 macro_build (NULL, "nop", "");
6616 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6617 the condition code tested. EP specifies the branch target. */
6620 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6647 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6650 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6651 the register tested. EP specifies the branch target. */
6654 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6656 const char *brneg = NULL;
6666 br = mips_opts.micromips ? "bgez" : "bgezl";
6670 gas_assert (mips_opts.micromips);
6671 br = mips_opts.insn32 ? "bgezal" : "bgezals";
6679 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6686 br = mips_opts.micromips ? "blez" : "blezl";
6693 br = mips_opts.micromips ? "bltz" : "bltzl";
6697 gas_assert (mips_opts.micromips);
6698 br = mips_opts.insn32 ? "bltzal" : "bltzals";
6705 if (mips_opts.micromips && brneg)
6706 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6708 macro_build (ep, br, "s,p", sreg);
6711 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6712 TREG as the registers tested. EP specifies the branch target. */
6715 macro_build_branch_rsrt (int type, expressionS *ep,
6716 unsigned int sreg, unsigned int treg)
6718 const char *brneg = NULL;
6730 br = mips_opts.micromips ? "beq" : "beql";
6739 br = mips_opts.micromips ? "bne" : "bnel";
6745 if (mips_opts.micromips && brneg)
6746 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6748 macro_build (ep, br, "s,t,p", sreg, treg);
6751 /* Return the high part that should be loaded in order to make the low
6752 part of VALUE accessible using an offset of OFFBITS bits. */
6755 offset_high_part (offsetT value, unsigned int offbits)
6762 bias = 1 << (offbits - 1);
6763 low_mask = bias * 2 - 1;
6764 return (value + bias) & ~low_mask;
6767 /* Return true if the value stored in offset_expr and offset_reloc
6768 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6769 amount that the caller wants to add without inducing overflow
6770 and ALIGN is the known alignment of the value in bytes. */
6773 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
6777 /* Accept any relocation operator if overflow isn't a concern. */
6778 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
6781 /* These relocations are guaranteed not to overflow in correct links. */
6782 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
6783 || gprel16_reloc_p (*offset_reloc))
6786 if (offset_expr.X_op == O_constant
6787 && offset_high_part (offset_expr.X_add_number, offbits) == 0
6788 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
6795 * This routine implements the seemingly endless macro or synthesized
6796 * instructions and addressing modes in the mips assembly language. Many
6797 * of these macros are simple and are similar to each other. These could
6798 * probably be handled by some kind of table or grammar approach instead of
6799 * this verbose method. Others are not simple macros but are more like
6800 * optimizing code generation.
6801 * One interesting optimization is when several store macros appear
6802 * consecutively that would load AT with the upper half of the same address.
6803 * The ensuing load upper instructions are ommited. This implies some kind
6804 * of global optimization. We currently only optimize within a single macro.
6805 * For many of the load and store macros if the address is specified as a
6806 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6807 * first load register 'at' with zero and use it as the base register. The
6808 * mips assembler simply uses register $zero. Just one tiny optimization
6812 macro (struct mips_cl_insn *ip, char *str)
6814 unsigned int treg, sreg, dreg, breg;
6815 unsigned int tempreg;
6818 expressionS label_expr;
6833 bfd_boolean large_offset;
6835 int hold_mips_optimize;
6838 gas_assert (! mips_opts.mips16);
6840 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6841 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6842 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6843 mask = ip->insn_mo->mask;
6845 label_expr.X_op = O_constant;
6846 label_expr.X_op_symbol = NULL;
6847 label_expr.X_add_symbol = NULL;
6848 label_expr.X_add_number = 0;
6850 expr1.X_op = O_constant;
6851 expr1.X_op_symbol = NULL;
6852 expr1.X_add_symbol = NULL;
6853 expr1.X_add_number = 1;
6869 if (mips_opts.micromips)
6870 micromips_label_expr (&label_expr);
6872 label_expr.X_add_number = 8;
6873 macro_build (&label_expr, "bgez", "s,p", sreg);
6875 macro_build (NULL, "nop", "");
6877 move_register (dreg, sreg);
6878 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6879 if (mips_opts.micromips)
6880 micromips_add_label ();
6897 if (!mips_opts.micromips)
6899 if (imm_expr.X_op == O_constant
6900 && imm_expr.X_add_number >= -0x200
6901 && imm_expr.X_add_number < 0x200)
6903 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6912 if (imm_expr.X_op == O_constant
6913 && imm_expr.X_add_number >= -0x8000
6914 && imm_expr.X_add_number < 0x8000)
6916 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6921 load_register (AT, &imm_expr, dbl);
6922 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6941 if (imm_expr.X_op == O_constant
6942 && imm_expr.X_add_number >= 0
6943 && imm_expr.X_add_number < 0x10000)
6945 if (mask != M_NOR_I)
6946 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6949 macro_build (&imm_expr, "ori", "t,r,i",
6950 treg, sreg, BFD_RELOC_LO16);
6951 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6957 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6958 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6962 switch (imm_expr.X_add_number)
6965 macro_build (NULL, "nop", "");
6968 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6972 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6973 (int) imm_expr.X_add_number);
6976 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6977 (unsigned long) imm_expr.X_add_number);
6986 gas_assert (mips_opts.micromips);
6987 macro_build_branch_ccl (mask, &offset_expr,
6988 EXTRACT_OPERAND (1, BCC, *ip));
6995 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7001 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
7006 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
7013 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
7015 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
7019 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7020 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7021 &offset_expr, AT, ZERO);
7031 macro_build_branch_rs (mask, &offset_expr, sreg);
7037 /* Check for > max integer. */
7038 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7041 /* Result is always false. */
7043 macro_build (NULL, "nop", "");
7045 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
7048 if (imm_expr.X_op != O_constant)
7049 as_bad (_("Unsupported large constant"));
7050 ++imm_expr.X_add_number;
7054 if (mask == M_BGEL_I)
7056 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7058 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
7059 &offset_expr, sreg);
7062 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7064 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
7065 &offset_expr, sreg);
7068 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
7071 /* result is always true */
7072 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
7073 macro_build (&offset_expr, "b", "p");
7078 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7079 &offset_expr, AT, ZERO);
7088 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7089 &offset_expr, ZERO, treg);
7093 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7094 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7095 &offset_expr, AT, ZERO);
7104 && imm_expr.X_op == O_constant
7105 && imm_expr.X_add_number == -1))
7107 if (imm_expr.X_op != O_constant)
7108 as_bad (_("Unsupported large constant"));
7109 ++imm_expr.X_add_number;
7113 if (mask == M_BGEUL_I)
7115 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7117 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7118 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7119 &offset_expr, sreg, ZERO);
7124 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7125 &offset_expr, AT, ZERO);
7133 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7135 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7139 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7140 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7141 &offset_expr, AT, ZERO);
7149 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7150 &offset_expr, sreg, ZERO);
7156 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7157 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7158 &offset_expr, AT, ZERO);
7166 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7168 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7172 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7173 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7174 &offset_expr, AT, ZERO);
7181 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7183 if (imm_expr.X_op != O_constant)
7184 as_bad (_("Unsupported large constant"));
7185 ++imm_expr.X_add_number;
7189 if (mask == M_BLTL_I)
7191 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7192 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7193 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7194 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7199 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7200 &offset_expr, AT, ZERO);
7208 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7209 &offset_expr, sreg, ZERO);
7215 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7216 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7217 &offset_expr, AT, ZERO);
7226 && imm_expr.X_op == O_constant
7227 && imm_expr.X_add_number == -1))
7229 if (imm_expr.X_op != O_constant)
7230 as_bad (_("Unsupported large constant"));
7231 ++imm_expr.X_add_number;
7235 if (mask == M_BLTUL_I)
7237 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7239 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7240 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7241 &offset_expr, sreg, ZERO);
7246 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7247 &offset_expr, AT, ZERO);
7255 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7257 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7261 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7262 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7263 &offset_expr, AT, ZERO);
7273 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7274 &offset_expr, ZERO, treg);
7278 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7279 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7280 &offset_expr, AT, ZERO);
7286 /* Use unsigned arithmetic. */
7290 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7292 as_bad (_("Unsupported large constant"));
7297 pos = imm_expr.X_add_number;
7298 size = imm2_expr.X_add_number;
7303 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7306 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7308 as_bad (_("Improper extract size (%lu, position %lu)"),
7309 (unsigned long) size, (unsigned long) pos);
7313 if (size <= 32 && pos < 32)
7318 else if (size <= 32)
7328 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7335 /* Use unsigned arithmetic. */
7339 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7341 as_bad (_("Unsupported large constant"));
7346 pos = imm_expr.X_add_number;
7347 size = imm2_expr.X_add_number;
7352 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7355 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7357 as_bad (_("Improper insert size (%lu, position %lu)"),
7358 (unsigned long) size, (unsigned long) pos);
7362 if (pos < 32 && (pos + size - 1) < 32)
7377 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7378 (int) (pos + size - 1));
7394 as_warn (_("Divide by zero."));
7396 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7398 macro_build (NULL, "break", BRK_FMT, 7);
7405 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7406 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7410 if (mips_opts.micromips)
7411 micromips_label_expr (&label_expr);
7413 label_expr.X_add_number = 8;
7414 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7415 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7416 macro_build (NULL, "break", BRK_FMT, 7);
7417 if (mips_opts.micromips)
7418 micromips_add_label ();
7420 expr1.X_add_number = -1;
7422 load_register (AT, &expr1, dbl);
7423 if (mips_opts.micromips)
7424 micromips_label_expr (&label_expr);
7426 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7427 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7430 expr1.X_add_number = 1;
7431 load_register (AT, &expr1, dbl);
7432 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7436 expr1.X_add_number = 0x80000000;
7437 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7441 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7442 /* We want to close the noreorder block as soon as possible, so
7443 that later insns are available for delay slot filling. */
7448 if (mips_opts.micromips)
7449 micromips_label_expr (&label_expr);
7451 label_expr.X_add_number = 8;
7452 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7453 macro_build (NULL, "nop", "");
7455 /* We want to close the noreorder block as soon as possible, so
7456 that later insns are available for delay slot filling. */
7459 macro_build (NULL, "break", BRK_FMT, 6);
7461 if (mips_opts.micromips)
7462 micromips_add_label ();
7463 macro_build (NULL, s, MFHL_FMT, dreg);
7502 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7504 as_warn (_("Divide by zero."));
7506 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7508 macro_build (NULL, "break", BRK_FMT, 7);
7511 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7513 if (strcmp (s2, "mflo") == 0)
7514 move_register (dreg, sreg);
7516 move_register (dreg, ZERO);
7519 if (imm_expr.X_op == O_constant
7520 && imm_expr.X_add_number == -1
7521 && s[strlen (s) - 1] != 'u')
7523 if (strcmp (s2, "mflo") == 0)
7525 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7528 move_register (dreg, ZERO);
7533 load_register (AT, &imm_expr, dbl);
7534 macro_build (NULL, s, "z,s,t", sreg, AT);
7535 macro_build (NULL, s2, MFHL_FMT, dreg);
7557 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7558 macro_build (NULL, s, "z,s,t", sreg, treg);
7559 /* We want to close the noreorder block as soon as possible, so
7560 that later insns are available for delay slot filling. */
7565 if (mips_opts.micromips)
7566 micromips_label_expr (&label_expr);
7568 label_expr.X_add_number = 8;
7569 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7570 macro_build (NULL, s, "z,s,t", sreg, treg);
7572 /* We want to close the noreorder block as soon as possible, so
7573 that later insns are available for delay slot filling. */
7575 macro_build (NULL, "break", BRK_FMT, 7);
7576 if (mips_opts.micromips)
7577 micromips_add_label ();
7579 macro_build (NULL, s2, MFHL_FMT, dreg);
7591 /* Load the address of a symbol into a register. If breg is not
7592 zero, we then add a base register to it. */
7594 if (dbl && HAVE_32BIT_GPRS)
7595 as_warn (_("dla used to load 32-bit register"));
7597 if (!dbl && HAVE_64BIT_OBJECTS)
7598 as_warn (_("la used to load 64-bit address"));
7600 if (small_offset_p (0, align, 16))
7602 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
7603 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
7607 if (mips_opts.at && (treg == breg))
7617 if (offset_expr.X_op != O_symbol
7618 && offset_expr.X_op != O_constant)
7620 as_bad (_("Expression too complex"));
7621 offset_expr.X_op = O_constant;
7624 if (offset_expr.X_op == O_constant)
7625 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7626 else if (mips_pic == NO_PIC)
7628 /* If this is a reference to a GP relative symbol, we want
7629 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7631 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7632 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7633 If we have a constant, we need two instructions anyhow,
7634 so we may as well always use the latter form.
7636 With 64bit address space and a usable $at we want
7637 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7638 lui $at,<sym> (BFD_RELOC_HI16_S)
7639 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7640 daddiu $at,<sym> (BFD_RELOC_LO16)
7642 daddu $tempreg,$tempreg,$at
7644 If $at is already in use, we use a path which is suboptimal
7645 on superscalar processors.
7646 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7647 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7649 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7651 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7653 For GP relative symbols in 64bit address space we can use
7654 the same sequence as in 32bit address space. */
7655 if (HAVE_64BIT_SYMBOLS)
7657 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7658 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7660 relax_start (offset_expr.X_add_symbol);
7661 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7662 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7666 if (used_at == 0 && mips_opts.at)
7668 macro_build (&offset_expr, "lui", LUI_FMT,
7669 tempreg, BFD_RELOC_MIPS_HIGHEST);
7670 macro_build (&offset_expr, "lui", LUI_FMT,
7671 AT, BFD_RELOC_HI16_S);
7672 macro_build (&offset_expr, "daddiu", "t,r,j",
7673 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7674 macro_build (&offset_expr, "daddiu", "t,r,j",
7675 AT, AT, BFD_RELOC_LO16);
7676 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7677 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7682 macro_build (&offset_expr, "lui", LUI_FMT,
7683 tempreg, BFD_RELOC_MIPS_HIGHEST);
7684 macro_build (&offset_expr, "daddiu", "t,r,j",
7685 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7686 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7687 macro_build (&offset_expr, "daddiu", "t,r,j",
7688 tempreg, tempreg, BFD_RELOC_HI16_S);
7689 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7690 macro_build (&offset_expr, "daddiu", "t,r,j",
7691 tempreg, tempreg, BFD_RELOC_LO16);
7694 if (mips_relax.sequence)
7699 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7700 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7702 relax_start (offset_expr.X_add_symbol);
7703 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7704 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7707 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7708 as_bad (_("Offset too large"));
7709 macro_build_lui (&offset_expr, tempreg);
7710 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7711 tempreg, tempreg, BFD_RELOC_LO16);
7712 if (mips_relax.sequence)
7716 else if (!mips_big_got && !HAVE_NEWABI)
7718 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7720 /* If this is a reference to an external symbol, and there
7721 is no constant, we want
7722 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7723 or for lca or if tempreg is PIC_CALL_REG
7724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7725 For a local symbol, we want
7726 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7728 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7730 If we have a small constant, and this is a reference to
7731 an external symbol, we want
7732 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7734 addiu $tempreg,$tempreg,<constant>
7735 For a local symbol, we want the same instruction
7736 sequence, but we output a BFD_RELOC_LO16 reloc on the
7739 If we have a large constant, and this is a reference to
7740 an external symbol, we want
7741 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7742 lui $at,<hiconstant>
7743 addiu $at,$at,<loconstant>
7744 addu $tempreg,$tempreg,$at
7745 For a local symbol, we want the same instruction
7746 sequence, but we output a BFD_RELOC_LO16 reloc on the
7750 if (offset_expr.X_add_number == 0)
7752 if (mips_pic == SVR4_PIC
7754 && (call || tempreg == PIC_CALL_REG))
7755 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7757 relax_start (offset_expr.X_add_symbol);
7758 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7759 lw_reloc_type, mips_gp_register);
7762 /* We're going to put in an addu instruction using
7763 tempreg, so we may as well insert the nop right
7768 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7769 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7771 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7772 tempreg, tempreg, BFD_RELOC_LO16);
7774 /* FIXME: If breg == 0, and the next instruction uses
7775 $tempreg, then if this variant case is used an extra
7776 nop will be generated. */
7778 else if (offset_expr.X_add_number >= -0x8000
7779 && offset_expr.X_add_number < 0x8000)
7781 load_got_offset (tempreg, &offset_expr);
7783 add_got_offset (tempreg, &offset_expr);
7787 expr1.X_add_number = offset_expr.X_add_number;
7788 offset_expr.X_add_number =
7789 SEXT_16BIT (offset_expr.X_add_number);
7790 load_got_offset (tempreg, &offset_expr);
7791 offset_expr.X_add_number = expr1.X_add_number;
7792 /* If we are going to add in a base register, and the
7793 target register and the base register are the same,
7794 then we are using AT as a temporary register. Since
7795 we want to load the constant into AT, we add our
7796 current AT (from the global offset table) and the
7797 register into the register now, and pretend we were
7798 not using a base register. */
7802 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7807 add_got_offset_hilo (tempreg, &offset_expr, AT);
7811 else if (!mips_big_got && HAVE_NEWABI)
7813 int add_breg_early = 0;
7815 /* If this is a reference to an external, and there is no
7816 constant, or local symbol (*), with or without a
7818 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7819 or for lca or if tempreg is PIC_CALL_REG
7820 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7822 If we have a small constant, and this is a reference to
7823 an external symbol, we want
7824 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7825 addiu $tempreg,$tempreg,<constant>
7827 If we have a large constant, and this is a reference to
7828 an external symbol, we want
7829 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7830 lui $at,<hiconstant>
7831 addiu $at,$at,<loconstant>
7832 addu $tempreg,$tempreg,$at
7834 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7835 local symbols, even though it introduces an additional
7838 if (offset_expr.X_add_number)
7840 expr1.X_add_number = offset_expr.X_add_number;
7841 offset_expr.X_add_number = 0;
7843 relax_start (offset_expr.X_add_symbol);
7844 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7845 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7847 if (expr1.X_add_number >= -0x8000
7848 && expr1.X_add_number < 0x8000)
7850 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7851 tempreg, tempreg, BFD_RELOC_LO16);
7853 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7855 /* If we are going to add in a base register, and the
7856 target register and the base register are the same,
7857 then we are using AT as a temporary register. Since
7858 we want to load the constant into AT, we add our
7859 current AT (from the global offset table) and the
7860 register into the register now, and pretend we were
7861 not using a base register. */
7866 gas_assert (tempreg == AT);
7867 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7873 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7874 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7880 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7883 offset_expr.X_add_number = expr1.X_add_number;
7885 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7886 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7889 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7890 treg, tempreg, breg);
7896 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7898 relax_start (offset_expr.X_add_symbol);
7899 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7900 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7902 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7903 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7908 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7909 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7912 else if (mips_big_got && !HAVE_NEWABI)
7915 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7916 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7917 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7919 /* This is the large GOT case. If this is a reference to an
7920 external symbol, and there is no constant, we want
7921 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7922 addu $tempreg,$tempreg,$gp
7923 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7924 or for lca or if tempreg is PIC_CALL_REG
7925 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7926 addu $tempreg,$tempreg,$gp
7927 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7928 For a local symbol, we want
7929 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7931 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7933 If we have a small constant, and this is a reference to
7934 an external symbol, we want
7935 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7936 addu $tempreg,$tempreg,$gp
7937 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7939 addiu $tempreg,$tempreg,<constant>
7940 For a local symbol, we want
7941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7943 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7945 If we have a large constant, and this is a reference to
7946 an external symbol, we want
7947 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7948 addu $tempreg,$tempreg,$gp
7949 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7950 lui $at,<hiconstant>
7951 addiu $at,$at,<loconstant>
7952 addu $tempreg,$tempreg,$at
7953 For a local symbol, we want
7954 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7955 lui $at,<hiconstant>
7956 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7957 addu $tempreg,$tempreg,$at
7960 expr1.X_add_number = offset_expr.X_add_number;
7961 offset_expr.X_add_number = 0;
7962 relax_start (offset_expr.X_add_symbol);
7963 gpdelay = reg_needs_delay (mips_gp_register);
7964 if (expr1.X_add_number == 0 && breg == 0
7965 && (call || tempreg == PIC_CALL_REG))
7967 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7968 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7970 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7972 tempreg, tempreg, mips_gp_register);
7973 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7974 tempreg, lw_reloc_type, tempreg);
7975 if (expr1.X_add_number == 0)
7979 /* We're going to put in an addu instruction using
7980 tempreg, so we may as well insert the nop right
7985 else if (expr1.X_add_number >= -0x8000
7986 && expr1.X_add_number < 0x8000)
7989 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7990 tempreg, tempreg, BFD_RELOC_LO16);
7994 /* If we are going to add in a base register, and the
7995 target register and the base register are the same,
7996 then we are using AT as a temporary register. Since
7997 we want to load the constant into AT, we add our
7998 current AT (from the global offset table) and the
7999 register into the register now, and pretend we were
8000 not using a base register. */
8005 gas_assert (tempreg == AT);
8007 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8012 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8017 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
8022 /* This is needed because this instruction uses $gp, but
8023 the first instruction on the main stream does not. */
8024 macro_build (NULL, "nop", "");
8027 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8028 local_reloc_type, mips_gp_register);
8029 if (expr1.X_add_number >= -0x8000
8030 && expr1.X_add_number < 0x8000)
8033 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8034 tempreg, tempreg, BFD_RELOC_LO16);
8035 /* FIXME: If add_number is 0, and there was no base
8036 register, the external symbol case ended with a load,
8037 so if the symbol turns out to not be external, and
8038 the next instruction uses tempreg, an unnecessary nop
8039 will be inserted. */
8045 /* We must add in the base register now, as in the
8046 external symbol case. */
8047 gas_assert (tempreg == AT);
8049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8052 /* We set breg to 0 because we have arranged to add
8053 it in in both cases. */
8057 macro_build_lui (&expr1, AT);
8058 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8059 AT, AT, BFD_RELOC_LO16);
8060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8061 tempreg, tempreg, AT);
8066 else if (mips_big_got && HAVE_NEWABI)
8068 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8069 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8070 int add_breg_early = 0;
8072 /* This is the large GOT case. If this is a reference to an
8073 external symbol, and there is no constant, we want
8074 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8075 add $tempreg,$tempreg,$gp
8076 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8077 or for lca or if tempreg is PIC_CALL_REG
8078 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8079 add $tempreg,$tempreg,$gp
8080 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8082 If we have a small constant, and this is a reference to
8083 an external symbol, we want
8084 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8085 add $tempreg,$tempreg,$gp
8086 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8087 addi $tempreg,$tempreg,<constant>
8089 If we have a large constant, and this is a reference to
8090 an external symbol, we want
8091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8092 addu $tempreg,$tempreg,$gp
8093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8094 lui $at,<hiconstant>
8095 addi $at,$at,<loconstant>
8096 add $tempreg,$tempreg,$at
8098 If we have NewABI, and we know it's a local symbol, we want
8099 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8100 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8101 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8103 relax_start (offset_expr.X_add_symbol);
8105 expr1.X_add_number = offset_expr.X_add_number;
8106 offset_expr.X_add_number = 0;
8108 if (expr1.X_add_number == 0 && breg == 0
8109 && (call || tempreg == PIC_CALL_REG))
8111 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8112 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8114 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8116 tempreg, tempreg, mips_gp_register);
8117 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8118 tempreg, lw_reloc_type, tempreg);
8120 if (expr1.X_add_number == 0)
8122 else if (expr1.X_add_number >= -0x8000
8123 && expr1.X_add_number < 0x8000)
8125 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8126 tempreg, tempreg, BFD_RELOC_LO16);
8128 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8130 /* If we are going to add in a base register, and the
8131 target register and the base register are the same,
8132 then we are using AT as a temporary register. Since
8133 we want to load the constant into AT, we add our
8134 current AT (from the global offset table) and the
8135 register into the register now, and pretend we were
8136 not using a base register. */
8141 gas_assert (tempreg == AT);
8142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8148 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8149 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8154 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8157 offset_expr.X_add_number = expr1.X_add_number;
8158 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8159 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8160 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8161 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8164 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8165 treg, tempreg, breg);
8175 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8179 gas_assert (!mips_opts.micromips);
8181 unsigned long temp = (treg << 16) | (0x01);
8182 macro_build (NULL, "c2", "C", temp);
8187 gas_assert (!mips_opts.micromips);
8189 unsigned long temp = (0x02);
8190 macro_build (NULL, "c2", "C", temp);
8195 gas_assert (!mips_opts.micromips);
8197 unsigned long temp = (treg << 16) | (0x02);
8198 macro_build (NULL, "c2", "C", temp);
8203 gas_assert (!mips_opts.micromips);
8204 macro_build (NULL, "c2", "C", 3);
8208 gas_assert (!mips_opts.micromips);
8210 unsigned long temp = (treg << 16) | 0x03;
8211 macro_build (NULL, "c2", "C", temp);
8216 /* The j instruction may not be used in PIC code, since it
8217 requires an absolute address. We convert it to a b
8219 if (mips_pic == NO_PIC)
8220 macro_build (&offset_expr, "j", "a");
8222 macro_build (&offset_expr, "b", "p");
8225 /* The jal instructions must be handled as macros because when
8226 generating PIC code they expand to multi-instruction
8227 sequences. Normally they are simple instructions. */
8232 gas_assert (mips_opts.micromips);
8233 if (mips_opts.insn32)
8235 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8245 if (mips_pic == NO_PIC)
8247 s = jals ? "jalrs" : "jalr";
8248 if (mips_opts.micromips
8249 && !mips_opts.insn32
8251 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8252 macro_build (NULL, s, "mj", sreg);
8254 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8258 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8259 && mips_cprestore_offset >= 0);
8261 if (sreg != PIC_CALL_REG)
8262 as_warn (_("MIPS PIC call to register other than $25"));
8264 s = ((mips_opts.micromips
8265 && !mips_opts.insn32
8266 && (!mips_opts.noreorder || cprestore))
8267 ? "jalrs" : "jalr");
8268 if (mips_opts.micromips
8269 && !mips_opts.insn32
8271 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8272 macro_build (NULL, s, "mj", sreg);
8274 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8275 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8277 if (mips_cprestore_offset < 0)
8278 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8281 if (!mips_frame_reg_valid)
8283 as_warn (_("No .frame pseudo-op used in PIC code"));
8284 /* Quiet this warning. */
8285 mips_frame_reg_valid = 1;
8287 if (!mips_cprestore_valid)
8289 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8290 /* Quiet this warning. */
8291 mips_cprestore_valid = 1;
8293 if (mips_opts.noreorder)
8294 macro_build (NULL, "nop", "");
8295 expr1.X_add_number = mips_cprestore_offset;
8296 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8299 HAVE_64BIT_ADDRESSES);
8307 gas_assert (mips_opts.micromips);
8308 if (mips_opts.insn32)
8310 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8316 if (mips_pic == NO_PIC)
8317 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8318 else if (mips_pic == SVR4_PIC)
8320 /* If this is a reference to an external symbol, and we are
8321 using a small GOT, we want
8322 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8326 lw $gp,cprestore($sp)
8327 The cprestore value is set using the .cprestore
8328 pseudo-op. If we are using a big GOT, we want
8329 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8331 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8335 lw $gp,cprestore($sp)
8336 If the symbol is not external, we want
8337 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8339 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8342 lw $gp,cprestore($sp)
8344 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8345 sequences above, minus nops, unless the symbol is local,
8346 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8352 relax_start (offset_expr.X_add_symbol);
8353 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8354 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8357 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8358 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8364 relax_start (offset_expr.X_add_symbol);
8365 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8366 BFD_RELOC_MIPS_CALL_HI16);
8367 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8368 PIC_CALL_REG, mips_gp_register);
8369 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8370 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8373 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8374 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8376 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8377 PIC_CALL_REG, PIC_CALL_REG,
8378 BFD_RELOC_MIPS_GOT_OFST);
8382 macro_build_jalr (&offset_expr, 0);
8386 relax_start (offset_expr.X_add_symbol);
8389 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8390 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8399 gpdelay = reg_needs_delay (mips_gp_register);
8400 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8401 BFD_RELOC_MIPS_CALL_HI16);
8402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8403 PIC_CALL_REG, mips_gp_register);
8404 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8405 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8410 macro_build (NULL, "nop", "");
8412 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8413 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8416 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8417 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8419 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8421 if (mips_cprestore_offset < 0)
8422 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8425 if (!mips_frame_reg_valid)
8427 as_warn (_("No .frame pseudo-op used in PIC code"));
8428 /* Quiet this warning. */
8429 mips_frame_reg_valid = 1;
8431 if (!mips_cprestore_valid)
8433 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8434 /* Quiet this warning. */
8435 mips_cprestore_valid = 1;
8437 if (mips_opts.noreorder)
8438 macro_build (NULL, "nop", "");
8439 expr1.X_add_number = mips_cprestore_offset;
8440 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8443 HAVE_64BIT_ADDRESSES);
8447 else if (mips_pic == VXWORKS_PIC)
8448 as_bad (_("Non-PIC jump used in PIC library"));
8526 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8532 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8557 gas_assert (!mips_opts.micromips);
8560 /* Itbl support may require additional care here. */
8566 /* Itbl support may require additional care here. */
8572 offbits = (mips_opts.micromips ? 12 : 16);
8573 /* Itbl support may require additional care here. */
8577 gas_assert (!mips_opts.micromips);
8580 /* Itbl support may require additional care here. */
8586 offbits = (mips_opts.micromips ? 12 : 16);
8591 offbits = (mips_opts.micromips ? 12 : 16);
8596 /* Itbl support may require additional care here. */
8602 offbits = (mips_opts.micromips ? 12 : 16);
8603 /* Itbl support may require additional care here. */
8609 /* Itbl support may require additional care here. */
8615 /* Itbl support may require additional care here. */
8621 offbits = (mips_opts.micromips ? 12 : 16);
8626 offbits = (mips_opts.micromips ? 12 : 16);
8631 offbits = (mips_opts.micromips ? 12 : 16);
8636 offbits = (mips_opts.micromips ? 12 : 16);
8641 offbits = (mips_opts.micromips ? 12 : 16);
8644 gas_assert (mips_opts.micromips);
8651 gas_assert (mips_opts.micromips);
8658 gas_assert (mips_opts.micromips);
8664 gas_assert (mips_opts.micromips);
8671 /* We don't want to use $0 as tempreg. */
8672 if (breg == treg + lp || treg + lp == ZERO)
8675 tempreg = treg + lp;
8691 gas_assert (!mips_opts.micromips);
8694 /* Itbl support may require additional care here. */
8700 /* Itbl support may require additional care here. */
8706 offbits = (mips_opts.micromips ? 12 : 16);
8707 /* Itbl support may require additional care here. */
8711 gas_assert (!mips_opts.micromips);
8714 /* Itbl support may require additional care here. */
8720 offbits = (mips_opts.micromips ? 12 : 16);
8725 offbits = (mips_opts.micromips ? 12 : 16);
8730 offbits = (mips_opts.micromips ? 12 : 16);
8735 offbits = (mips_opts.micromips ? 12 : 16);
8739 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8740 offbits = (mips_opts.micromips ? 12 : 16);
8749 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8750 offbits = (mips_opts.micromips ? 12 : 16);
8761 /* Itbl support may require additional care here. */
8766 offbits = (mips_opts.micromips ? 12 : 16);
8767 /* Itbl support may require additional care here. */
8773 /* Itbl support may require additional care here. */
8777 gas_assert (!mips_opts.micromips);
8780 /* Itbl support may require additional care here. */
8786 offbits = (mips_opts.micromips ? 12 : 16);
8791 offbits = (mips_opts.micromips ? 12 : 16);
8794 gas_assert (mips_opts.micromips);
8800 gas_assert (mips_opts.micromips);
8806 gas_assert (mips_opts.micromips);
8812 gas_assert (mips_opts.micromips);
8820 if (small_offset_p (0, align, 16))
8822 /* The first case exists for M_LD_AB and M_SD_AB, which are
8823 macros for o32 but which should act like normal instructions
8826 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
8827 offset_reloc[1], offset_reloc[2], breg);
8828 else if (small_offset_p (0, align, offbits))
8831 macro_build (NULL, s, fmt, treg, breg);
8833 macro_build (NULL, s, fmt, treg,
8834 (unsigned long) offset_expr.X_add_number, breg);
8840 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8841 tempreg, breg, -1, offset_reloc[0],
8842 offset_reloc[1], offset_reloc[2]);
8844 macro_build (NULL, s, fmt, treg, tempreg);
8846 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8854 if (offset_expr.X_op != O_constant
8855 && offset_expr.X_op != O_symbol)
8857 as_bad (_("Expression too complex"));
8858 offset_expr.X_op = O_constant;
8861 if (HAVE_32BIT_ADDRESSES
8862 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8866 sprintf_vma (value, offset_expr.X_add_number);
8867 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8870 /* A constant expression in PIC code can be handled just as it
8871 is in non PIC code. */
8872 if (offset_expr.X_op == O_constant)
8874 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
8875 offbits == 0 ? 16 : offbits);
8876 offset_expr.X_add_number -= expr1.X_add_number;
8878 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8880 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8881 tempreg, tempreg, breg);
8884 if (offset_expr.X_add_number != 0)
8885 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8886 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
8887 macro_build (NULL, s, fmt, treg, tempreg);
8889 else if (offbits == 16)
8890 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8892 macro_build (NULL, s, fmt, treg,
8893 (unsigned long) offset_expr.X_add_number, tempreg);
8895 else if (offbits != 16)
8897 /* The offset field is too narrow to be used for a low-part
8898 relocation, so load the whole address into the auxillary
8900 load_address (tempreg, &offset_expr, &used_at);
8902 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8903 tempreg, tempreg, breg);
8905 macro_build (NULL, s, fmt, treg, tempreg);
8907 macro_build (NULL, s, fmt, treg, 0L, tempreg);
8909 else if (mips_pic == NO_PIC)
8911 /* If this is a reference to a GP relative symbol, and there
8912 is no base register, we want
8913 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8914 Otherwise, if there is no base register, we want
8915 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8916 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8917 If we have a constant, we need two instructions anyhow,
8918 so we always use the latter form.
8920 If we have a base register, and this is a reference to a
8921 GP relative symbol, we want
8922 addu $tempreg,$breg,$gp
8923 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8925 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8926 addu $tempreg,$tempreg,$breg
8927 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8928 With a constant we always use the latter case.
8930 With 64bit address space and no base register and $at usable,
8932 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8933 lui $at,<sym> (BFD_RELOC_HI16_S)
8934 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8937 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8938 If we have a base register, we want
8939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8940 lui $at,<sym> (BFD_RELOC_HI16_S)
8941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8945 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8947 Without $at we can't generate the optimal path for superscalar
8948 processors here since this would require two temporary registers.
8949 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8950 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8952 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8955 If we have a base register, we want
8956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8957 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8959 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8961 daddu $tempreg,$tempreg,$breg
8962 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8964 For GP relative symbols in 64bit address space we can use
8965 the same sequence as in 32bit address space. */
8966 if (HAVE_64BIT_SYMBOLS)
8968 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8969 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8971 relax_start (offset_expr.X_add_symbol);
8974 macro_build (&offset_expr, s, fmt, treg,
8975 BFD_RELOC_GPREL16, mips_gp_register);
8979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8980 tempreg, breg, mips_gp_register);
8981 macro_build (&offset_expr, s, fmt, treg,
8982 BFD_RELOC_GPREL16, tempreg);
8987 if (used_at == 0 && mips_opts.at)
8989 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8990 BFD_RELOC_MIPS_HIGHEST);
8991 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8993 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8994 tempreg, BFD_RELOC_MIPS_HIGHER);
8996 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8997 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8998 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8999 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
9005 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9006 BFD_RELOC_MIPS_HIGHEST);
9007 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9008 tempreg, BFD_RELOC_MIPS_HIGHER);
9009 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9010 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9011 tempreg, BFD_RELOC_HI16_S);
9012 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9014 macro_build (NULL, "daddu", "d,v,t",
9015 tempreg, tempreg, breg);
9016 macro_build (&offset_expr, s, fmt, treg,
9017 BFD_RELOC_LO16, tempreg);
9020 if (mips_relax.sequence)
9027 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9028 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9030 relax_start (offset_expr.X_add_symbol);
9031 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9035 macro_build_lui (&offset_expr, tempreg);
9036 macro_build (&offset_expr, s, fmt, treg,
9037 BFD_RELOC_LO16, tempreg);
9038 if (mips_relax.sequence)
9043 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9044 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9046 relax_start (offset_expr.X_add_symbol);
9047 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9048 tempreg, breg, mips_gp_register);
9049 macro_build (&offset_expr, s, fmt, treg,
9050 BFD_RELOC_GPREL16, tempreg);
9053 macro_build_lui (&offset_expr, tempreg);
9054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9055 tempreg, tempreg, breg);
9056 macro_build (&offset_expr, s, fmt, treg,
9057 BFD_RELOC_LO16, tempreg);
9058 if (mips_relax.sequence)
9062 else if (!mips_big_got)
9064 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9066 /* If this is a reference to an external symbol, we want
9067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9069 <op> $treg,0($tempreg)
9071 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9073 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9074 <op> $treg,0($tempreg)
9077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9078 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9080 If there is a base register, we add it to $tempreg before
9081 the <op>. If there is a constant, we stick it in the
9082 <op> instruction. We don't handle constants larger than
9083 16 bits, because we have no way to load the upper 16 bits
9084 (actually, we could handle them for the subset of cases
9085 in which we are not using $at). */
9086 gas_assert (offset_expr.X_op == O_symbol);
9089 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9090 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9092 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9093 tempreg, tempreg, breg);
9094 macro_build (&offset_expr, s, fmt, treg,
9095 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9098 expr1.X_add_number = offset_expr.X_add_number;
9099 offset_expr.X_add_number = 0;
9100 if (expr1.X_add_number < -0x8000
9101 || expr1.X_add_number >= 0x8000)
9102 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9104 lw_reloc_type, mips_gp_register);
9106 relax_start (offset_expr.X_add_symbol);
9108 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9109 tempreg, BFD_RELOC_LO16);
9112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9113 tempreg, tempreg, breg);
9114 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9116 else if (mips_big_got && !HAVE_NEWABI)
9120 /* If this is a reference to an external symbol, we want
9121 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9122 addu $tempreg,$tempreg,$gp
9123 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9124 <op> $treg,0($tempreg)
9126 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9128 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9129 <op> $treg,0($tempreg)
9130 If there is a base register, we add it to $tempreg before
9131 the <op>. If there is a constant, we stick it in the
9132 <op> instruction. We don't handle constants larger than
9133 16 bits, because we have no way to load the upper 16 bits
9134 (actually, we could handle them for the subset of cases
9135 in which we are not using $at). */
9136 gas_assert (offset_expr.X_op == O_symbol);
9137 expr1.X_add_number = offset_expr.X_add_number;
9138 offset_expr.X_add_number = 0;
9139 if (expr1.X_add_number < -0x8000
9140 || expr1.X_add_number >= 0x8000)
9141 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9142 gpdelay = reg_needs_delay (mips_gp_register);
9143 relax_start (offset_expr.X_add_symbol);
9144 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9145 BFD_RELOC_MIPS_GOT_HI16);
9146 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9148 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9149 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9152 macro_build (NULL, "nop", "");
9153 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9154 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9156 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9157 tempreg, BFD_RELOC_LO16);
9161 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9162 tempreg, tempreg, breg);
9163 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9165 else if (mips_big_got && HAVE_NEWABI)
9167 /* If this is a reference to an external symbol, we want
9168 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9169 add $tempreg,$tempreg,$gp
9170 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9171 <op> $treg,<ofst>($tempreg)
9172 Otherwise, for local symbols, we want:
9173 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9174 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9175 gas_assert (offset_expr.X_op == O_symbol);
9176 expr1.X_add_number = offset_expr.X_add_number;
9177 offset_expr.X_add_number = 0;
9178 if (expr1.X_add_number < -0x8000
9179 || expr1.X_add_number >= 0x8000)
9180 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9181 relax_start (offset_expr.X_add_symbol);
9182 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9183 BFD_RELOC_MIPS_GOT_HI16);
9184 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9186 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9187 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9190 tempreg, tempreg, breg);
9191 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9194 offset_expr.X_add_number = expr1.X_add_number;
9195 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9196 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9198 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9199 tempreg, tempreg, breg);
9200 macro_build (&offset_expr, s, fmt, treg,
9201 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9210 gas_assert (mips_opts.micromips);
9211 gas_assert (mips_opts.insn32);
9213 macro_build (NULL, "jr", "s", RA);
9214 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
9215 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
9220 gas_assert (mips_opts.micromips);
9221 gas_assert (mips_opts.insn32);
9222 macro_build (NULL, "jr", "s", sreg);
9223 if (mips_opts.noreorder)
9224 macro_build (NULL, "nop", "");
9229 load_register (treg, &imm_expr, 0);
9233 load_register (treg, &imm_expr, 1);
9237 if (imm_expr.X_op == O_constant)
9240 load_register (AT, &imm_expr, 0);
9241 macro_build (NULL, "mtc1", "t,G", AT, treg);
9246 gas_assert (offset_expr.X_op == O_symbol
9247 && strcmp (segment_name (S_GET_SEGMENT
9248 (offset_expr.X_add_symbol)),
9250 && offset_expr.X_add_number == 0);
9251 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9252 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9257 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9258 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9259 order 32 bits of the value and the low order 32 bits are either
9260 zero or in OFFSET_EXPR. */
9261 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9263 if (HAVE_64BIT_GPRS)
9264 load_register (treg, &imm_expr, 1);
9269 if (target_big_endian)
9281 load_register (hreg, &imm_expr, 0);
9284 if (offset_expr.X_op == O_absent)
9285 move_register (lreg, 0);
9288 gas_assert (offset_expr.X_op == O_constant);
9289 load_register (lreg, &offset_expr, 0);
9296 /* We know that sym is in the .rdata section. First we get the
9297 upper 16 bits of the address. */
9298 if (mips_pic == NO_PIC)
9300 macro_build_lui (&offset_expr, AT);
9305 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9306 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9310 /* Now we load the register(s). */
9311 if (HAVE_64BIT_GPRS)
9314 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9319 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9322 /* FIXME: How in the world do we deal with the possible
9324 offset_expr.X_add_number += 4;
9325 macro_build (&offset_expr, "lw", "t,o(b)",
9326 treg + 1, BFD_RELOC_LO16, AT);
9332 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9333 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9334 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9335 the value and the low order 32 bits are either zero or in
9337 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9340 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9341 if (HAVE_64BIT_FPRS)
9343 gas_assert (HAVE_64BIT_GPRS);
9344 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9348 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9349 if (offset_expr.X_op == O_absent)
9350 macro_build (NULL, "mtc1", "t,G", 0, treg);
9353 gas_assert (offset_expr.X_op == O_constant);
9354 load_register (AT, &offset_expr, 0);
9355 macro_build (NULL, "mtc1", "t,G", AT, treg);
9361 gas_assert (offset_expr.X_op == O_symbol
9362 && offset_expr.X_add_number == 0);
9363 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9364 if (strcmp (s, ".lit8") == 0)
9366 breg = mips_gp_register;
9367 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
9368 offset_reloc[1] = BFD_RELOC_UNUSED;
9369 offset_reloc[2] = BFD_RELOC_UNUSED;
9373 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9375 if (mips_pic != NO_PIC)
9376 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9377 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9380 /* FIXME: This won't work for a 64 bit address. */
9381 macro_build_lui (&offset_expr, AT);
9385 offset_reloc[0] = BFD_RELOC_LO16;
9386 offset_reloc[1] = BFD_RELOC_UNUSED;
9387 offset_reloc[2] = BFD_RELOC_UNUSED;
9394 * The MIPS assembler seems to check for X_add_number not
9395 * being double aligned and generating:
9398 * addiu at,at,%lo(foo+1)
9401 * But, the resulting address is the same after relocation so why
9402 * generate the extra instruction?
9404 /* Itbl support may require additional care here. */
9407 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9416 gas_assert (!mips_opts.micromips);
9417 /* Itbl support may require additional care here. */
9420 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9440 if (HAVE_64BIT_GPRS)
9450 if (HAVE_64BIT_GPRS)
9458 /* Even on a big endian machine $fn comes before $fn+1. We have
9459 to adjust when loading from memory. We set coproc if we must
9460 load $fn+1 first. */
9461 /* Itbl support may require additional care here. */
9462 if (!target_big_endian)
9465 if (small_offset_p (0, align, 16))
9468 if (!small_offset_p (4, align, 16))
9470 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
9471 -1, offset_reloc[0], offset_reloc[1],
9473 expr1.X_add_number = 0;
9477 offset_reloc[0] = BFD_RELOC_LO16;
9478 offset_reloc[1] = BFD_RELOC_UNUSED;
9479 offset_reloc[2] = BFD_RELOC_UNUSED;
9481 if (strcmp (s, "lw") == 0 && treg == breg)
9483 ep->X_add_number += 4;
9484 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
9485 offset_reloc[1], offset_reloc[2], breg);
9486 ep->X_add_number -= 4;
9487 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
9488 offset_reloc[1], offset_reloc[2], breg);
9492 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
9493 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9495 ep->X_add_number += 4;
9496 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
9497 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9503 if (offset_expr.X_op != O_symbol
9504 && offset_expr.X_op != O_constant)
9506 as_bad (_("Expression too complex"));
9507 offset_expr.X_op = O_constant;
9510 if (HAVE_32BIT_ADDRESSES
9511 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9515 sprintf_vma (value, offset_expr.X_add_number);
9516 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9519 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9521 /* If this is a reference to a GP relative symbol, we want
9522 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9523 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9524 If we have a base register, we use this
9526 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9527 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9528 If this is not a GP relative symbol, we want
9529 lui $at,<sym> (BFD_RELOC_HI16_S)
9530 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9531 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9532 If there is a base register, we add it to $at after the
9533 lui instruction. If there is a constant, we always use
9535 if (offset_expr.X_op == O_symbol
9536 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9537 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9539 relax_start (offset_expr.X_add_symbol);
9542 tempreg = mips_gp_register;
9546 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9547 AT, breg, mips_gp_register);
9552 /* Itbl support may require additional care here. */
9553 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9554 BFD_RELOC_GPREL16, tempreg);
9555 offset_expr.X_add_number += 4;
9557 /* Set mips_optimize to 2 to avoid inserting an
9559 hold_mips_optimize = mips_optimize;
9561 /* Itbl support may require additional care here. */
9562 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9563 BFD_RELOC_GPREL16, tempreg);
9564 mips_optimize = hold_mips_optimize;
9568 offset_expr.X_add_number -= 4;
9571 if (offset_high_part (offset_expr.X_add_number, 16)
9572 != offset_high_part (offset_expr.X_add_number + 4, 16))
9574 load_address (AT, &offset_expr, &used_at);
9575 offset_expr.X_op = O_constant;
9576 offset_expr.X_add_number = 0;
9579 macro_build_lui (&offset_expr, AT);
9581 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9582 /* Itbl support may require additional care here. */
9583 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9584 BFD_RELOC_LO16, AT);
9585 /* FIXME: How do we handle overflow here? */
9586 offset_expr.X_add_number += 4;
9587 /* Itbl support may require additional care here. */
9588 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9589 BFD_RELOC_LO16, AT);
9590 if (mips_relax.sequence)
9593 else if (!mips_big_got)
9595 /* If this is a reference to an external symbol, we want
9596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9601 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9603 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9604 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9605 If there is a base register we add it to $at before the
9606 lwc1 instructions. If there is a constant we include it
9607 in the lwc1 instructions. */
9609 expr1.X_add_number = offset_expr.X_add_number;
9610 if (expr1.X_add_number < -0x8000
9611 || expr1.X_add_number >= 0x8000 - 4)
9612 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9613 load_got_offset (AT, &offset_expr);
9616 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9618 /* Set mips_optimize to 2 to avoid inserting an undesired
9620 hold_mips_optimize = mips_optimize;
9623 /* Itbl support may require additional care here. */
9624 relax_start (offset_expr.X_add_symbol);
9625 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9626 BFD_RELOC_LO16, AT);
9627 expr1.X_add_number += 4;
9628 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9629 BFD_RELOC_LO16, AT);
9631 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9632 BFD_RELOC_LO16, AT);
9633 offset_expr.X_add_number += 4;
9634 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9635 BFD_RELOC_LO16, AT);
9638 mips_optimize = hold_mips_optimize;
9640 else if (mips_big_got)
9644 /* If this is a reference to an external symbol, we want
9645 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9647 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9652 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9654 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9655 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9656 If there is a base register we add it to $at before the
9657 lwc1 instructions. If there is a constant we include it
9658 in the lwc1 instructions. */
9660 expr1.X_add_number = offset_expr.X_add_number;
9661 offset_expr.X_add_number = 0;
9662 if (expr1.X_add_number < -0x8000
9663 || expr1.X_add_number >= 0x8000 - 4)
9664 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9665 gpdelay = reg_needs_delay (mips_gp_register);
9666 relax_start (offset_expr.X_add_symbol);
9667 macro_build (&offset_expr, "lui", LUI_FMT,
9668 AT, BFD_RELOC_MIPS_GOT_HI16);
9669 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9670 AT, AT, mips_gp_register);
9671 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9672 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9676 /* Itbl support may require additional care here. */
9677 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9678 BFD_RELOC_LO16, AT);
9679 expr1.X_add_number += 4;
9681 /* Set mips_optimize to 2 to avoid inserting an undesired
9683 hold_mips_optimize = mips_optimize;
9685 /* Itbl support may require additional care here. */
9686 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9687 BFD_RELOC_LO16, AT);
9688 mips_optimize = hold_mips_optimize;
9689 expr1.X_add_number -= 4;
9692 offset_expr.X_add_number = expr1.X_add_number;
9694 macro_build (NULL, "nop", "");
9695 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9696 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9700 /* Itbl support may require additional care here. */
9701 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9702 BFD_RELOC_LO16, AT);
9703 offset_expr.X_add_number += 4;
9705 /* Set mips_optimize to 2 to avoid inserting an undesired
9707 hold_mips_optimize = mips_optimize;
9709 /* Itbl support may require additional care here. */
9710 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9711 BFD_RELOC_LO16, AT);
9712 mips_optimize = hold_mips_optimize;
9731 /* New code added to support COPZ instructions.
9732 This code builds table entries out of the macros in mip_opcodes.
9733 R4000 uses interlocks to handle coproc delays.
9734 Other chips (like the R3000) require nops to be inserted for delays.
9736 FIXME: Currently, we require that the user handle delays.
9737 In order to fill delay slots for non-interlocked chips,
9738 we must have a way to specify delays based on the coprocessor.
9739 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9740 What are the side-effects of the cop instruction?
9741 What cache support might we have and what are its effects?
9742 Both coprocessor & memory require delays. how long???
9743 What registers are read/set/modified?
9745 If an itbl is provided to interpret cop instructions,
9746 this knowledge can be encoded in the itbl spec. */
9760 gas_assert (!mips_opts.micromips);
9761 /* For now we just do C (same as Cz). The parameter will be
9762 stored in insn_opcode by mips_ip. */
9763 macro_build (NULL, s, "C", ip->insn_opcode);
9767 move_register (dreg, sreg);
9771 gas_assert (mips_opts.micromips);
9772 gas_assert (mips_opts.insn32);
9773 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
9774 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
9775 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
9776 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
9777 move_register (dreg, sreg);
9778 move_register (breg, treg);
9784 if (mips_opts.arch == CPU_R5900)
9786 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9790 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9791 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9798 /* The MIPS assembler some times generates shifts and adds. I'm
9799 not trying to be that fancy. GCC should do this for us
9802 load_register (AT, &imm_expr, dbl);
9803 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9804 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9820 load_register (AT, &imm_expr, dbl);
9821 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9822 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9823 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9824 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9826 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9829 if (mips_opts.micromips)
9830 micromips_label_expr (&label_expr);
9832 label_expr.X_add_number = 8;
9833 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9834 macro_build (NULL, "nop", "");
9835 macro_build (NULL, "break", BRK_FMT, 6);
9836 if (mips_opts.micromips)
9837 micromips_add_label ();
9840 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9856 load_register (AT, &imm_expr, dbl);
9857 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9858 sreg, imm ? AT : treg);
9859 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9860 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9862 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9865 if (mips_opts.micromips)
9866 micromips_label_expr (&label_expr);
9868 label_expr.X_add_number = 8;
9869 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9870 macro_build (NULL, "nop", "");
9871 macro_build (NULL, "break", BRK_FMT, 6);
9872 if (mips_opts.micromips)
9873 micromips_add_label ();
9879 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9890 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9891 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9895 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9896 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9897 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9898 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9902 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9913 macro_build (NULL, "negu", "d,w", tempreg, treg);
9914 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9918 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9919 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9920 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9921 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9930 if (imm_expr.X_op != O_constant)
9931 as_bad (_("Improper rotate count"));
9932 rot = imm_expr.X_add_number & 0x3f;
9933 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9935 rot = (64 - rot) & 0x3f;
9937 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9939 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9944 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9947 l = (rot < 0x20) ? "dsll" : "dsll32";
9948 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9951 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9952 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9953 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9961 if (imm_expr.X_op != O_constant)
9962 as_bad (_("Improper rotate count"));
9963 rot = imm_expr.X_add_number & 0x1f;
9964 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9966 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9971 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9975 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9976 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9977 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9982 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9984 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9988 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9989 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9990 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9991 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9995 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9997 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
10001 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
10002 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
10003 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
10004 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10013 if (imm_expr.X_op != O_constant)
10014 as_bad (_("Improper rotate count"));
10015 rot = imm_expr.X_add_number & 0x3f;
10016 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10019 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10021 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10026 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10029 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10030 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10033 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10034 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10035 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10043 if (imm_expr.X_op != O_constant)
10044 as_bad (_("Improper rotate count"));
10045 rot = imm_expr.X_add_number & 0x1f;
10046 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10048 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10053 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10057 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10058 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10059 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10065 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10066 else if (treg == 0)
10067 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10070 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10071 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10076 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10078 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10083 as_warn (_("Instruction %s: result is always false"),
10084 ip->insn_mo->name);
10085 move_register (dreg, 0);
10088 if (CPU_HAS_SEQ (mips_opts.arch)
10089 && -512 <= imm_expr.X_add_number
10090 && imm_expr.X_add_number < 512)
10092 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10093 (int) imm_expr.X_add_number);
10096 if (imm_expr.X_op == O_constant
10097 && imm_expr.X_add_number >= 0
10098 && imm_expr.X_add_number < 0x10000)
10100 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10102 else if (imm_expr.X_op == O_constant
10103 && imm_expr.X_add_number > -0x8000
10104 && imm_expr.X_add_number < 0)
10106 imm_expr.X_add_number = -imm_expr.X_add_number;
10107 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10108 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10110 else if (CPU_HAS_SEQ (mips_opts.arch))
10113 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10114 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10119 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10120 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10123 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10126 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10132 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10133 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10136 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10138 if (imm_expr.X_op == O_constant
10139 && imm_expr.X_add_number >= -0x8000
10140 && imm_expr.X_add_number < 0x8000)
10142 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10143 dreg, sreg, BFD_RELOC_LO16);
10147 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10148 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10152 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10155 case M_SGT: /* sreg > treg <==> treg < sreg */
10161 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10164 case M_SGT_I: /* sreg > I <==> I < sreg */
10171 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10172 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10175 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10181 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10182 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10185 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10192 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10193 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10194 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10198 if (imm_expr.X_op == O_constant
10199 && imm_expr.X_add_number >= -0x8000
10200 && imm_expr.X_add_number < 0x8000)
10202 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10206 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10207 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10211 if (imm_expr.X_op == O_constant
10212 && imm_expr.X_add_number >= -0x8000
10213 && imm_expr.X_add_number < 0x8000)
10215 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10220 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10221 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10226 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10227 else if (treg == 0)
10228 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10231 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10232 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10237 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10239 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10244 as_warn (_("Instruction %s: result is always true"),
10245 ip->insn_mo->name);
10246 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10247 dreg, 0, BFD_RELOC_LO16);
10250 if (CPU_HAS_SEQ (mips_opts.arch)
10251 && -512 <= imm_expr.X_add_number
10252 && imm_expr.X_add_number < 512)
10254 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10255 (int) imm_expr.X_add_number);
10258 if (imm_expr.X_op == O_constant
10259 && imm_expr.X_add_number >= 0
10260 && imm_expr.X_add_number < 0x10000)
10262 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10264 else if (imm_expr.X_op == O_constant
10265 && imm_expr.X_add_number > -0x8000
10266 && imm_expr.X_add_number < 0)
10268 imm_expr.X_add_number = -imm_expr.X_add_number;
10269 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10270 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10272 else if (CPU_HAS_SEQ (mips_opts.arch))
10275 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10276 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10281 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10282 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10285 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10300 if (!mips_opts.micromips)
10302 if (imm_expr.X_op == O_constant
10303 && imm_expr.X_add_number > -0x200
10304 && imm_expr.X_add_number <= 0x200)
10306 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10315 if (imm_expr.X_op == O_constant
10316 && imm_expr.X_add_number > -0x8000
10317 && imm_expr.X_add_number <= 0x8000)
10319 imm_expr.X_add_number = -imm_expr.X_add_number;
10320 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10325 load_register (AT, &imm_expr, dbl);
10326 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10348 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10349 macro_build (NULL, s, "s,t", sreg, AT);
10354 gas_assert (!mips_opts.micromips);
10355 gas_assert (mips_opts.isa == ISA_MIPS1);
10357 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10358 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10361 * Is the double cfc1 instruction a bug in the mips assembler;
10362 * or is there a reason for it?
10364 start_noreorder ();
10365 macro_build (NULL, "cfc1", "t,G", treg, RA);
10366 macro_build (NULL, "cfc1", "t,G", treg, RA);
10367 macro_build (NULL, "nop", "");
10368 expr1.X_add_number = 3;
10369 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10370 expr1.X_add_number = 2;
10371 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10372 macro_build (NULL, "ctc1", "t,G", AT, RA);
10373 macro_build (NULL, "nop", "");
10374 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10376 macro_build (NULL, "ctc1", "t,G", treg, RA);
10377 macro_build (NULL, "nop", "");
10394 offbits = (mips_opts.micromips ? 12 : 16);
10400 offbits = (mips_opts.micromips ? 12 : 16);
10412 offbits = (mips_opts.micromips ? 12 : 16);
10419 offbits = (mips_opts.micromips ? 12 : 16);
10424 large_offset = !small_offset_p (off, align, offbits);
10426 expr1.X_add_number = 0;
10431 if (small_offset_p (0, align, 16))
10432 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
10433 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10436 load_address (tempreg, ep, &used_at);
10438 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10439 tempreg, tempreg, breg);
10441 offset_reloc[0] = BFD_RELOC_LO16;
10442 offset_reloc[1] = BFD_RELOC_UNUSED;
10443 offset_reloc[2] = BFD_RELOC_UNUSED;
10448 else if (!ust && treg == breg)
10459 if (!target_big_endian)
10460 ep->X_add_number += off;
10462 macro_build (NULL, s, "t,~(b)",
10463 tempreg, (unsigned long) ep->X_add_number, breg);
10465 macro_build (ep, s, "t,o(b)", tempreg, -1,
10466 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10468 if (!target_big_endian)
10469 ep->X_add_number -= off;
10471 ep->X_add_number += off;
10473 macro_build (NULL, s2, "t,~(b)",
10474 tempreg, (unsigned long) ep->X_add_number, breg);
10476 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10477 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10479 /* If necessary, move the result in tempreg to the final destination. */
10480 if (!ust && treg != tempreg)
10482 /* Protect second load's delay slot. */
10484 move_register (treg, tempreg);
10490 if (target_big_endian == ust)
10491 ep->X_add_number += off;
10492 tempreg = ust || large_offset ? treg : AT;
10493 macro_build (ep, s, "t,o(b)", tempreg, -1,
10494 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10496 /* For halfword transfers we need a temporary register to shuffle
10497 bytes. Unfortunately for M_USH_A we have none available before
10498 the next store as AT holds the base address. We deal with this
10499 case by clobbering TREG and then restoring it as with ULH. */
10500 tempreg = ust == large_offset ? treg : AT;
10502 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10504 if (target_big_endian == ust)
10505 ep->X_add_number -= off;
10507 ep->X_add_number += off;
10508 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10509 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10511 /* For M_USH_A re-retrieve the LSB. */
10512 if (ust && large_offset)
10514 if (target_big_endian)
10515 ep->X_add_number += off;
10517 ep->X_add_number -= off;
10518 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
10519 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
10521 /* For ULH and M_USH_A OR the LSB in. */
10522 if (!ust || large_offset)
10524 tempreg = !large_offset ? AT : treg;
10525 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10526 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10531 /* FIXME: Check if this is one of the itbl macros, since they
10532 are added dynamically. */
10533 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10536 if (!mips_opts.at && used_at)
10537 as_bad (_("Macro used $at after \".set noat\""));
10540 /* Implement macros in mips16 mode. */
10543 mips16_macro (struct mips_cl_insn *ip)
10546 int xreg, yreg, zreg, tmp;
10549 const char *s, *s2, *s3;
10551 mask = ip->insn_mo->mask;
10553 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10554 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10555 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10557 expr1.X_op = O_constant;
10558 expr1.X_op_symbol = NULL;
10559 expr1.X_add_symbol = NULL;
10560 expr1.X_add_number = 1;
10579 start_noreorder ();
10580 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10581 expr1.X_add_number = 2;
10582 macro_build (&expr1, "bnez", "x,p", yreg);
10583 macro_build (NULL, "break", "6", 7);
10585 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10586 since that causes an overflow. We should do that as well,
10587 but I don't see how to do the comparisons without a temporary
10590 macro_build (NULL, s, "x", zreg);
10609 start_noreorder ();
10610 macro_build (NULL, s, "0,x,y", xreg, yreg);
10611 expr1.X_add_number = 2;
10612 macro_build (&expr1, "bnez", "x,p", yreg);
10613 macro_build (NULL, "break", "6", 7);
10615 macro_build (NULL, s2, "x", zreg);
10621 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10622 macro_build (NULL, "mflo", "x", zreg);
10630 if (imm_expr.X_op != O_constant)
10631 as_bad (_("Unsupported large constant"));
10632 imm_expr.X_add_number = -imm_expr.X_add_number;
10633 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10637 if (imm_expr.X_op != O_constant)
10638 as_bad (_("Unsupported large constant"));
10639 imm_expr.X_add_number = -imm_expr.X_add_number;
10640 macro_build (&imm_expr, "addiu", "x,k", xreg);
10644 if (imm_expr.X_op != O_constant)
10645 as_bad (_("Unsupported large constant"));
10646 imm_expr.X_add_number = -imm_expr.X_add_number;
10647 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10669 goto do_reverse_branch;
10673 goto do_reverse_branch;
10685 goto do_reverse_branch;
10696 macro_build (NULL, s, "x,y", xreg, yreg);
10697 macro_build (&offset_expr, s2, "p");
10724 goto do_addone_branch_i;
10729 goto do_addone_branch_i;
10744 goto do_addone_branch_i;
10750 do_addone_branch_i:
10751 if (imm_expr.X_op != O_constant)
10752 as_bad (_("Unsupported large constant"));
10753 ++imm_expr.X_add_number;
10756 macro_build (&imm_expr, s, s3, xreg);
10757 macro_build (&offset_expr, s2, "p");
10761 expr1.X_add_number = 0;
10762 macro_build (&expr1, "slti", "x,8", yreg);
10764 move_register (xreg, yreg);
10765 expr1.X_add_number = 2;
10766 macro_build (&expr1, "bteqz", "p");
10767 macro_build (NULL, "neg", "x,w", xreg, xreg);
10771 /* For consistency checking, verify that all bits are specified either
10772 by the match/mask part of the instruction definition, or by the
10775 validate_mips_insn (const struct mips_opcode *opc)
10777 const char *p = opc->args;
10779 unsigned long used_bits = opc->mask;
10781 if ((used_bits & opc->match) != opc->match)
10783 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10784 opc->name, opc->args);
10787 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10797 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10798 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10799 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10800 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10801 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10802 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10803 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10804 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10805 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10806 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10807 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10809 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10810 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10811 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10812 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10813 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10814 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10815 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10816 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10817 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10818 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10819 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10820 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10821 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10822 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10823 case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10824 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10827 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10828 c, opc->name, opc->args);
10832 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10833 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10835 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10836 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10837 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10838 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10840 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10841 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10843 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10844 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10846 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10847 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10848 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10849 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10850 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10851 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10852 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10853 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10854 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10855 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10856 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10857 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10858 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10859 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10860 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10861 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10862 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10864 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10865 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10866 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10867 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10869 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10870 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10871 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10872 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10873 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10874 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10875 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10876 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10877 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10880 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10881 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10882 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10883 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10884 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10885 case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
10886 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10887 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10888 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10889 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10890 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10891 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10892 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10893 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10894 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10895 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10896 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10897 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10898 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10899 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10900 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10901 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10902 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10903 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10904 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10906 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10907 c, opc->name, opc->args);
10911 if (used_bits != 0xffffffff)
10913 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10914 ~used_bits & 0xffffffff, opc->name, opc->args);
10920 /* For consistency checking, verify that the length implied matches the
10921 major opcode and that all bits are specified either by the match/mask
10922 part of the instruction definition, or by the operand list. */
10925 validate_micromips_insn (const struct mips_opcode *opc)
10927 unsigned long match = opc->match;
10928 unsigned long mask = opc->mask;
10929 const char *p = opc->args;
10930 unsigned long insn_bits;
10931 unsigned long used_bits;
10932 unsigned long major;
10933 unsigned int length;
10937 if ((mask & match) != match)
10939 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10940 opc->name, opc->args);
10943 length = micromips_insn_length (opc);
10944 if (length != 2 && length != 4)
10946 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10947 "%s %s"), length, opc->name, opc->args);
10950 major = match >> (10 + 8 * (length - 2));
10951 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10952 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10954 as_bad (_("Internal error: bad microMIPS opcode "
10955 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10959 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10960 insn_bits = 1 << 4 * length;
10961 insn_bits <<= 4 * length;
10964 #define USE_BITS(field) \
10965 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10976 case 'A': USE_BITS (EXTLSB); break;
10977 case 'B': USE_BITS (INSMSB); break;
10978 case 'C': USE_BITS (EXTMSBD); break;
10979 case 'E': USE_BITS (EXTLSB); break;
10980 case 'F': USE_BITS (INSMSB); break;
10981 case 'G': USE_BITS (EXTMSBD); break;
10982 case 'H': USE_BITS (EXTMSBD); break;
10983 case 'i': USE_BITS (TARGET); break;
10984 case 'j': USE_BITS (EVAOFFSET); break;
10986 as_bad (_("Internal error: bad mips opcode "
10987 "(unknown extension operand type `%c%c'): %s %s"),
10988 e, c, opc->name, opc->args);
10996 case 'A': USE_BITS (IMMA); break;
10997 case 'B': USE_BITS (IMMB); break;
10998 case 'C': USE_BITS (IMMC); break;
10999 case 'D': USE_BITS (IMMD); break;
11000 case 'E': USE_BITS (IMME); break;
11001 case 'F': USE_BITS (IMMF); break;
11002 case 'G': USE_BITS (IMMG); break;
11003 case 'H': USE_BITS (IMMH); break;
11004 case 'I': USE_BITS (IMMI); break;
11005 case 'J': USE_BITS (IMMJ); break;
11006 case 'L': USE_BITS (IMML); break;
11007 case 'M': USE_BITS (IMMM); break;
11008 case 'N': USE_BITS (IMMN); break;
11009 case 'O': USE_BITS (IMMO); break;
11010 case 'P': USE_BITS (IMMP); break;
11011 case 'Q': USE_BITS (IMMQ); break;
11012 case 'U': USE_BITS (IMMU); break;
11013 case 'W': USE_BITS (IMMW); break;
11014 case 'X': USE_BITS (IMMX); break;
11015 case 'Y': USE_BITS (IMMY); break;
11018 case 'b': USE_BITS (MB); break;
11019 case 'c': USE_BITS (MC); break;
11020 case 'd': USE_BITS (MD); break;
11021 case 'e': USE_BITS (ME); break;
11022 case 'f': USE_BITS (MF); break;
11023 case 'g': USE_BITS (MG); break;
11024 case 'h': USE_BITS (MH); break;
11025 case 'j': USE_BITS (MJ); break;
11026 case 'l': USE_BITS (ML); break;
11027 case 'm': USE_BITS (MM); break;
11028 case 'n': USE_BITS (MN); break;
11029 case 'p': USE_BITS (MP); break;
11030 case 'q': USE_BITS (MQ); break;
11038 as_bad (_("Internal error: bad mips opcode "
11039 "(unknown extension operand type `%c%c'): %s %s"),
11040 e, c, opc->name, opc->args);
11044 case '.': USE_BITS (OFFSET10); break;
11045 case '1': USE_BITS (STYPE); break;
11046 case '2': USE_BITS (BP); break;
11047 case '3': USE_BITS (SA3); break;
11048 case '4': USE_BITS (SA4); break;
11049 case '5': USE_BITS (IMM8); break;
11050 case '6': USE_BITS (RS); break;
11051 case '7': USE_BITS (DSPACC); break;
11052 case '8': USE_BITS (WRDSP); break;
11053 case '0': USE_BITS (DSPSFT); break;
11054 case '<': USE_BITS (SHAMT); break;
11055 case '>': USE_BITS (SHAMT); break;
11056 case '@': USE_BITS (IMM10); break;
11057 case 'B': USE_BITS (CODE10); break;
11058 case 'C': USE_BITS (COPZ); break;
11059 case 'D': USE_BITS (FD); break;
11060 case 'E': USE_BITS (RT); break;
11061 case 'G': USE_BITS (RS); break;
11062 case 'H': USE_BITS (SEL); break;
11063 case 'K': USE_BITS (RS); break;
11064 case 'M': USE_BITS (CCC); break;
11065 case 'N': USE_BITS (BCC); break;
11066 case 'R': USE_BITS (FR); break;
11067 case 'S': USE_BITS (FS); break;
11068 case 'T': USE_BITS (FT); break;
11069 case 'V': USE_BITS (FS); break;
11070 case '\\': USE_BITS (3BITPOS); break;
11071 case '^': USE_BITS (RD); break;
11072 case 'a': USE_BITS (TARGET); break;
11073 case 'b': USE_BITS (RS); break;
11074 case 'c': USE_BITS (CODE); break;
11075 case 'd': USE_BITS (RD); break;
11076 case 'h': USE_BITS (PREFX); break;
11077 case 'i': USE_BITS (IMMEDIATE); break;
11078 case 'j': USE_BITS (DELTA); break;
11079 case 'k': USE_BITS (CACHE); break;
11080 case 'n': USE_BITS (RT); break;
11081 case 'o': USE_BITS (DELTA); break;
11082 case 'p': USE_BITS (DELTA); break;
11083 case 'q': USE_BITS (CODE2); break;
11084 case 'r': USE_BITS (RS); break;
11085 case 's': USE_BITS (RS); break;
11086 case 't': USE_BITS (RT); break;
11087 case 'u': USE_BITS (IMMEDIATE); break;
11088 case 'v': USE_BITS (RS); break;
11089 case 'w': USE_BITS (RT); break;
11090 case 'y': USE_BITS (RS3); break;
11092 case '|': USE_BITS (TRAP); break;
11093 case '~': USE_BITS (OFFSET12); break;
11095 as_bad (_("Internal error: bad microMIPS opcode "
11096 "(unknown operand type `%c'): %s %s"),
11097 c, opc->name, opc->args);
11101 if (used_bits != insn_bits)
11103 if (~used_bits & insn_bits)
11104 as_bad (_("Internal error: bad microMIPS opcode "
11105 "(bits 0x%lx undefined): %s %s"),
11106 ~used_bits & insn_bits, opc->name, opc->args);
11107 if (used_bits & ~insn_bits)
11108 as_bad (_("Internal error: bad microMIPS opcode "
11109 "(bits 0x%lx defined): %s %s"),
11110 used_bits & ~insn_bits, opc->name, opc->args);
11116 /* UDI immediates. */
11117 struct mips_immed {
11119 unsigned int shift;
11120 unsigned long mask;
11124 static const struct mips_immed mips_immed[] = {
11125 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11126 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11127 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11128 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11132 /* Check whether an odd floating-point register is allowed. */
11134 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11136 const char *s = insn->name;
11138 if (insn->pinfo == INSN_MACRO)
11139 /* Let a macro pass, we'll catch it later when it is expanded. */
11142 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11144 /* Allow odd registers for single-precision ops. */
11145 switch (insn->pinfo & (FP_S | FP_D))
11149 return 1; /* both single precision - ok */
11151 return 0; /* both double precision - fail */
11156 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11157 s = strchr (insn->name, '.');
11159 s = s != NULL ? strchr (s + 1, '.') : NULL;
11160 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11163 /* Single-precision coprocessor loads and moves are OK too. */
11164 if ((insn->pinfo & FP_S)
11165 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11166 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11172 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11173 taking bits from BIT up. */
11175 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11177 return (ep->X_op == O_constant
11178 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11179 && ep->X_add_number >= min << bit
11180 && ep->X_add_number < max << bit);
11183 /* This routine assembles an instruction into its binary format. As a
11184 side effect, it sets one of the global variables imm_reloc or
11185 offset_reloc to the type of relocation to do if one of the operands
11186 is an address expression. */
11189 mips_ip (char *str, struct mips_cl_insn *ip)
11191 bfd_boolean wrong_delay_slot_insns = FALSE;
11192 bfd_boolean need_delay_slot_ok = TRUE;
11193 struct mips_opcode *firstinsn = NULL;
11194 const struct mips_opcode *past;
11195 struct hash_control *hash;
11199 struct mips_opcode *insn;
11201 unsigned int regno, regno2;
11202 unsigned int lastregno;
11203 unsigned int destregno = 0;
11204 unsigned int lastpos = 0;
11205 unsigned int limlo, limhi;
11208 offsetT min_range, max_range;
11212 unsigned int rtype;
11218 if (mips_opts.micromips)
11220 hash = micromips_op_hash;
11221 past = µmips_opcodes[bfd_micromips_num_opcodes];
11226 past = &mips_opcodes[NUMOPCODES];
11228 forced_insn_length = 0;
11231 /* We first try to match an instruction up to a space or to the end. */
11232 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11235 /* Make a copy of the instruction so that we can fiddle with it. */
11236 name = alloca (end + 1);
11237 memcpy (name, str, end);
11242 insn = (struct mips_opcode *) hash_find (hash, name);
11244 if (insn != NULL || !mips_opts.micromips)
11246 if (forced_insn_length)
11249 /* See if there's an instruction size override suffix,
11250 either `16' or `32', at the end of the mnemonic proper,
11251 that defines the operation, i.e. before the first `.'
11252 character if any. Strip it and retry. */
11253 dot = strchr (name, '.');
11254 opend = dot != NULL ? dot - name : end;
11257 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11258 forced_insn_length = 2;
11259 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11260 forced_insn_length = 4;
11263 memcpy (name + opend - 2, name + opend, end - opend + 1);
11267 insn_error = _("Unrecognized opcode");
11271 /* For microMIPS instructions placed in a fixed-length branch delay slot
11272 we make up to two passes over the relevant fragment of the opcode
11273 table. First we try instructions that meet the delay slot's length
11274 requirement. If none matched, then we retry with the remaining ones
11275 and if one matches, then we use it and then issue an appropriate
11276 warning later on. */
11277 argsStart = s = str + end;
11280 bfd_boolean delay_slot_ok;
11281 bfd_boolean size_ok;
11284 gas_assert (strcmp (insn->name, name) == 0);
11286 ok = is_opcode_valid (insn);
11287 size_ok = is_size_valid (insn);
11288 delay_slot_ok = is_delay_slot_valid (insn);
11289 if (!delay_slot_ok && !wrong_delay_slot_insns)
11292 wrong_delay_slot_insns = TRUE;
11294 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11296 static char buf[256];
11298 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11303 if (wrong_delay_slot_insns && need_delay_slot_ok)
11305 gas_assert (firstinsn);
11306 need_delay_slot_ok = FALSE;
11316 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11317 mips_cpu_info_from_arch (mips_opts.arch)->name,
11318 mips_cpu_info_from_isa (mips_opts.isa)->name);
11319 else if (mips_opts.insn32)
11320 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11322 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11323 8 * forced_insn_length);
11329 imm_expr.X_op = O_absent;
11330 imm2_expr.X_op = O_absent;
11331 offset_expr.X_op = O_absent;
11332 imm_reloc[0] = BFD_RELOC_UNUSED;
11333 imm_reloc[1] = BFD_RELOC_UNUSED;
11334 imm_reloc[2] = BFD_RELOC_UNUSED;
11335 offset_reloc[0] = BFD_RELOC_UNUSED;
11336 offset_reloc[1] = BFD_RELOC_UNUSED;
11337 offset_reloc[2] = BFD_RELOC_UNUSED;
11339 create_insn (ip, insn);
11342 lastregno = 0xffffffff;
11343 for (args = insn->args;; ++args)
11347 s += strspn (s, " \t");
11351 case '\0': /* end of args */
11357 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11358 code) or 14 (for microMIPS code). */
11359 my_getExpression (&imm_expr, s);
11360 check_absolute_expr (ip, &imm_expr);
11361 if ((unsigned long) imm_expr.X_add_number != 1
11362 && (unsigned long) imm_expr.X_add_number != 3)
11364 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11365 (unsigned long) imm_expr.X_add_number);
11367 INSERT_OPERAND (mips_opts.micromips,
11368 BP, *ip, imm_expr.X_add_number);
11369 imm_expr.X_op = O_absent;
11374 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11375 code) or 13 (for microMIPS code). */
11377 unsigned long mask = (mips_opts.micromips
11378 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11380 my_getExpression (&imm_expr, s);
11381 check_absolute_expr (ip, &imm_expr);
11382 if ((unsigned long) imm_expr.X_add_number > mask)
11383 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11384 mask, (unsigned long) imm_expr.X_add_number);
11385 INSERT_OPERAND (mips_opts.micromips,
11386 SA3, *ip, imm_expr.X_add_number);
11387 imm_expr.X_op = O_absent;
11393 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11394 code) or 12 (for microMIPS code). */
11396 unsigned long mask = (mips_opts.micromips
11397 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11399 my_getExpression (&imm_expr, s);
11400 check_absolute_expr (ip, &imm_expr);
11401 if ((unsigned long) imm_expr.X_add_number > mask)
11402 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11403 mask, (unsigned long) imm_expr.X_add_number);
11404 INSERT_OPERAND (mips_opts.micromips,
11405 SA4, *ip, imm_expr.X_add_number);
11406 imm_expr.X_op = O_absent;
11412 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11413 code) or 13 (for microMIPS code). */
11415 unsigned long mask = (mips_opts.micromips
11416 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11418 my_getExpression (&imm_expr, s);
11419 check_absolute_expr (ip, &imm_expr);
11420 if ((unsigned long) imm_expr.X_add_number > mask)
11421 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11422 mask, (unsigned long) imm_expr.X_add_number);
11423 INSERT_OPERAND (mips_opts.micromips,
11424 IMM8, *ip, imm_expr.X_add_number);
11425 imm_expr.X_op = O_absent;
11431 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11432 code) or 16 (for microMIPS code). */
11434 unsigned long mask = (mips_opts.micromips
11435 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11437 my_getExpression (&imm_expr, s);
11438 check_absolute_expr (ip, &imm_expr);
11439 if ((unsigned long) imm_expr.X_add_number > mask)
11440 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11441 mask, (unsigned long) imm_expr.X_add_number);
11442 INSERT_OPERAND (mips_opts.micromips,
11443 RS, *ip, imm_expr.X_add_number);
11444 imm_expr.X_op = O_absent;
11450 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11451 or 14 (for microMIPS code). */
11452 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11453 && s[3] >= '0' && s[3] <= '3')
11455 regno = s[3] - '0';
11457 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11461 as_bad (_("Invalid dsp acc register"));
11465 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11466 code) or 14 (for microMIPS code). */
11468 unsigned long mask = (mips_opts.micromips
11469 ? MICROMIPSOP_MASK_WRDSP
11472 my_getExpression (&imm_expr, s);
11473 check_absolute_expr (ip, &imm_expr);
11474 if ((unsigned long) imm_expr.X_add_number > mask)
11475 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11476 mask, (unsigned long) imm_expr.X_add_number);
11477 INSERT_OPERAND (mips_opts.micromips,
11478 WRDSP, *ip, imm_expr.X_add_number);
11479 imm_expr.X_op = O_absent;
11484 case '9': /* Four DSP accumulators in bits 21,22. */
11485 gas_assert (!mips_opts.micromips);
11486 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11487 && s[3] >= '0' && s[3] <= '3')
11489 regno = s[3] - '0';
11491 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11495 as_bad (_("Invalid dsp acc register"));
11499 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11500 code) or 16 (for microMIPS code). */
11502 long mask = (mips_opts.micromips
11503 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11505 my_getExpression (&imm_expr, s);
11506 check_absolute_expr (ip, &imm_expr);
11507 min_range = -((mask + 1) >> 1);
11508 max_range = ((mask + 1) >> 1) - 1;
11509 if (imm_expr.X_add_number < min_range
11510 || imm_expr.X_add_number > max_range)
11511 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11512 (long) min_range, (long) max_range,
11513 (long) imm_expr.X_add_number);
11514 INSERT_OPERAND (mips_opts.micromips,
11515 DSPSFT, *ip, imm_expr.X_add_number);
11516 imm_expr.X_op = O_absent;
11521 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11522 gas_assert (!mips_opts.micromips);
11523 my_getExpression (&imm_expr, s);
11524 check_absolute_expr (ip, &imm_expr);
11525 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11527 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11529 (unsigned long) imm_expr.X_add_number);
11531 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11532 imm_expr.X_op = O_absent;
11536 case ':': /* DSP 7-bit signed immediate in bit 19. */
11537 gas_assert (!mips_opts.micromips);
11538 my_getExpression (&imm_expr, s);
11539 check_absolute_expr (ip, &imm_expr);
11540 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11541 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11542 if (imm_expr.X_add_number < min_range ||
11543 imm_expr.X_add_number > max_range)
11545 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11546 (long) min_range, (long) max_range,
11547 (long) imm_expr.X_add_number);
11549 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11550 imm_expr.X_op = O_absent;
11554 case '@': /* DSP 10-bit signed immediate in bit 16. */
11556 long mask = (mips_opts.micromips
11557 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11559 my_getExpression (&imm_expr, s);
11560 check_absolute_expr (ip, &imm_expr);
11561 min_range = -((mask + 1) >> 1);
11562 max_range = ((mask + 1) >> 1) - 1;
11563 if (imm_expr.X_add_number < min_range
11564 || imm_expr.X_add_number > max_range)
11565 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11566 (long) min_range, (long) max_range,
11567 (long) imm_expr.X_add_number);
11568 INSERT_OPERAND (mips_opts.micromips,
11569 IMM10, *ip, imm_expr.X_add_number);
11570 imm_expr.X_op = O_absent;
11575 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11576 gas_assert (mips_opts.micromips);
11577 my_getExpression (&imm_expr, s);
11578 check_absolute_expr (ip, &imm_expr);
11579 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11580 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11581 MICROMIPSOP_MASK_RD,
11582 (unsigned long) imm_expr.X_add_number);
11583 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11584 imm_expr.X_op = O_absent;
11588 case '!': /* MT usermode flag bit. */
11589 gas_assert (!mips_opts.micromips);
11590 my_getExpression (&imm_expr, s);
11591 check_absolute_expr (ip, &imm_expr);
11592 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11593 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11594 (unsigned long) imm_expr.X_add_number);
11595 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11596 imm_expr.X_op = O_absent;
11600 case '$': /* MT load high flag bit. */
11601 gas_assert (!mips_opts.micromips);
11602 my_getExpression (&imm_expr, s);
11603 check_absolute_expr (ip, &imm_expr);
11604 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11605 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11606 (unsigned long) imm_expr.X_add_number);
11607 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11608 imm_expr.X_op = O_absent;
11612 case '*': /* Four DSP accumulators in bits 18,19. */
11613 gas_assert (!mips_opts.micromips);
11614 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11615 s[3] >= '0' && s[3] <= '3')
11617 regno = s[3] - '0';
11619 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11623 as_bad (_("Invalid dsp/smartmips acc register"));
11626 case '&': /* Four DSP accumulators in bits 13,14. */
11627 gas_assert (!mips_opts.micromips);
11628 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11629 s[3] >= '0' && s[3] <= '3')
11631 regno = s[3] - '0';
11633 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11637 as_bad (_("Invalid dsp/smartmips acc register"));
11640 case '\\': /* 3-bit bit position. */
11642 unsigned long mask = (mips_opts.micromips
11643 ? MICROMIPSOP_MASK_3BITPOS
11644 : OP_MASK_3BITPOS);
11646 my_getExpression (&imm_expr, s);
11647 check_absolute_expr (ip, &imm_expr);
11648 if ((unsigned long) imm_expr.X_add_number > mask)
11649 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11651 mask, (unsigned long) imm_expr.X_add_number);
11652 INSERT_OPERAND (mips_opts.micromips,
11653 3BITPOS, *ip, imm_expr.X_add_number);
11654 imm_expr.X_op = O_absent;
11668 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11672 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11676 gas_assert (!mips_opts.micromips);
11677 INSERT_OPERAND (0, FT, *ip, lastregno);
11681 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11687 /* Handle optional base register.
11688 Either the base register is omitted or
11689 we must have a left paren. */
11690 /* This is dependent on the next operand specifier
11691 is a base register specification. */
11692 gas_assert (args[1] == 'b'
11693 || (mips_opts.micromips
11695 && (args[2] == 'l' || args[2] == 'n'
11696 || args[2] == 's' || args[2] == 'a')));
11697 if (*s == '\0' && args[1] == 'b')
11699 /* Fall through. */
11701 case ')': /* These must match exactly. */
11706 case '+': /* Opcode extension character. */
11709 case '1': /* UDI immediates. */
11713 gas_assert (!mips_opts.micromips);
11715 const struct mips_immed *imm = mips_immed;
11717 while (imm->type && imm->type != *args)
11721 my_getExpression (&imm_expr, s);
11722 check_absolute_expr (ip, &imm_expr);
11723 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11725 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11726 imm->desc ? imm->desc : ip->insn_mo->name,
11727 (unsigned long) imm_expr.X_add_number,
11728 (unsigned long) imm_expr.X_add_number);
11729 imm_expr.X_add_number &= imm->mask;
11731 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11733 imm_expr.X_op = O_absent;
11738 case 'J': /* 10-bit hypcall code. */
11739 gas_assert (!mips_opts.micromips);
11741 unsigned long mask = OP_MASK_CODE10;
11743 my_getExpression (&imm_expr, s);
11744 check_absolute_expr (ip, &imm_expr);
11745 if ((unsigned long) imm_expr.X_add_number > mask)
11746 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11748 mask, (unsigned long) imm_expr.X_add_number);
11749 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11750 imm_expr.X_op = O_absent;
11755 case 'A': /* ins/ext position, becomes LSB. */
11764 my_getExpression (&imm_expr, s);
11765 check_absolute_expr (ip, &imm_expr);
11766 if ((unsigned long) imm_expr.X_add_number < limlo
11767 || (unsigned long) imm_expr.X_add_number > limhi)
11769 as_bad (_("Improper position (%lu)"),
11770 (unsigned long) imm_expr.X_add_number);
11771 imm_expr.X_add_number = limlo;
11773 lastpos = imm_expr.X_add_number;
11774 INSERT_OPERAND (mips_opts.micromips,
11775 EXTLSB, *ip, imm_expr.X_add_number);
11776 imm_expr.X_op = O_absent;
11780 case 'B': /* ins size, becomes MSB. */
11789 my_getExpression (&imm_expr, s);
11790 check_absolute_expr (ip, &imm_expr);
11791 /* Check for negative input so that small negative numbers
11792 will not succeed incorrectly. The checks against
11793 (pos+size) transitively check "size" itself,
11794 assuming that "pos" is reasonable. */
11795 if ((long) imm_expr.X_add_number < 0
11796 || ((unsigned long) imm_expr.X_add_number
11798 || ((unsigned long) imm_expr.X_add_number
11799 + lastpos) > limhi)
11801 as_bad (_("Improper insert size (%lu, position %lu)"),
11802 (unsigned long) imm_expr.X_add_number,
11803 (unsigned long) lastpos);
11804 imm_expr.X_add_number = limlo - lastpos;
11806 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11807 lastpos + imm_expr.X_add_number - 1);
11808 imm_expr.X_op = O_absent;
11812 case 'C': /* ext size, becomes MSBD. */
11828 my_getExpression (&imm_expr, s);
11829 check_absolute_expr (ip, &imm_expr);
11830 /* The checks against (pos+size) don't transitively check
11831 "size" itself, assuming that "pos" is reasonable.
11832 We also need to check the lower bound of "size". */
11833 if ((long) imm_expr.X_add_number < sizelo
11834 || ((unsigned long) imm_expr.X_add_number
11836 || ((unsigned long) imm_expr.X_add_number
11837 + lastpos) > limhi)
11839 as_bad (_("Improper extract size (%lu, position %lu)"),
11840 (unsigned long) imm_expr.X_add_number,
11841 (unsigned long) lastpos);
11842 imm_expr.X_add_number = limlo - lastpos;
11844 INSERT_OPERAND (mips_opts.micromips,
11845 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11846 imm_expr.X_op = O_absent;
11851 /* "+I" is like "I", except that imm2_expr is used. */
11852 my_getExpression (&imm2_expr, s);
11853 if (imm2_expr.X_op != O_big
11854 && imm2_expr.X_op != O_constant)
11855 insn_error = _("absolute expression required");
11856 if (HAVE_32BIT_GPRS)
11857 normalize_constant_expr (&imm2_expr);
11861 case 't': /* Coprocessor register number. */
11862 gas_assert (!mips_opts.micromips);
11863 if (s[0] == '$' && ISDIGIT (s[1]))
11873 while (ISDIGIT (*s));
11875 as_bad (_("Invalid register number (%d)"), regno);
11878 INSERT_OPERAND (0, RT, *ip, regno);
11883 as_bad (_("Invalid coprocessor 0 register number"));
11887 /* bbit[01] and bbit[01]32 bit index. Give error if index
11888 is not in the valid range. */
11889 gas_assert (!mips_opts.micromips);
11890 my_getExpression (&imm_expr, s);
11891 check_absolute_expr (ip, &imm_expr);
11892 if ((unsigned) imm_expr.X_add_number > 31)
11894 as_bad (_("Improper bit index (%lu)"),
11895 (unsigned long) imm_expr.X_add_number);
11896 imm_expr.X_add_number = 0;
11898 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11899 imm_expr.X_op = O_absent;
11904 /* bbit[01] bit index when bbit is used but we generate
11905 bbit[01]32 because the index is over 32. Move to the
11906 next candidate if index is not in the valid range. */
11907 gas_assert (!mips_opts.micromips);
11908 my_getExpression (&imm_expr, s);
11909 check_absolute_expr (ip, &imm_expr);
11910 if ((unsigned) imm_expr.X_add_number < 32
11911 || (unsigned) imm_expr.X_add_number > 63)
11913 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11914 imm_expr.X_op = O_absent;
11919 /* cins, cins32, exts and exts32 position field. Give error
11920 if it's not in the valid range. */
11921 gas_assert (!mips_opts.micromips);
11922 my_getExpression (&imm_expr, s);
11923 check_absolute_expr (ip, &imm_expr);
11924 if ((unsigned) imm_expr.X_add_number > 31)
11926 as_bad (_("Improper position (%lu)"),
11927 (unsigned long) imm_expr.X_add_number);
11928 imm_expr.X_add_number = 0;
11930 lastpos = imm_expr.X_add_number;
11931 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11932 imm_expr.X_op = O_absent;
11937 /* cins, cins32, exts and exts32 position field. Move to
11938 the next candidate if it's not in the valid range. */
11939 gas_assert (!mips_opts.micromips);
11940 my_getExpression (&imm_expr, s);
11941 check_absolute_expr (ip, &imm_expr);
11942 if ((unsigned) imm_expr.X_add_number < 32
11943 || (unsigned) imm_expr.X_add_number > 63)
11945 lastpos = imm_expr.X_add_number;
11946 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11947 imm_expr.X_op = O_absent;
11952 /* cins32 and exts32 length-minus-one field. */
11953 gas_assert (!mips_opts.micromips);
11954 my_getExpression (&imm_expr, s);
11955 check_absolute_expr (ip, &imm_expr);
11956 if ((unsigned long) imm_expr.X_add_number > 31
11957 || (unsigned long) imm_expr.X_add_number + lastpos > 31)
11959 as_bad (_("Improper size (%lu)"),
11960 (unsigned long) imm_expr.X_add_number);
11961 imm_expr.X_add_number = 0;
11963 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11964 imm_expr.X_op = O_absent;
11969 /* cins/exts length-minus-one field. */
11970 gas_assert (!mips_opts.micromips);
11971 my_getExpression (&imm_expr, s);
11972 check_absolute_expr (ip, &imm_expr);
11973 if ((unsigned long) imm_expr.X_add_number > 31
11974 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11976 as_bad (_("Improper size (%lu)"),
11977 (unsigned long) imm_expr.X_add_number);
11978 imm_expr.X_add_number = 0;
11980 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11981 imm_expr.X_op = O_absent;
11986 /* seqi/snei immediate field. */
11987 gas_assert (!mips_opts.micromips);
11988 my_getExpression (&imm_expr, s);
11989 check_absolute_expr (ip, &imm_expr);
11990 if ((long) imm_expr.X_add_number < -512
11991 || (long) imm_expr.X_add_number >= 512)
11993 as_bad (_("Improper immediate (%ld)"),
11994 (long) imm_expr.X_add_number);
11995 imm_expr.X_add_number = 0;
11997 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11998 imm_expr.X_op = O_absent;
12002 case 'a': /* 8-bit signed offset in bit 6 */
12003 gas_assert (!mips_opts.micromips);
12004 my_getExpression (&imm_expr, s);
12005 check_absolute_expr (ip, &imm_expr);
12006 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
12007 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
12008 if (imm_expr.X_add_number < min_range
12009 || imm_expr.X_add_number > max_range)
12011 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12012 (long) min_range, (long) max_range,
12013 (long) imm_expr.X_add_number);
12015 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
12016 imm_expr.X_op = O_absent;
12020 case 'b': /* 8-bit signed offset in bit 3 */
12021 gas_assert (!mips_opts.micromips);
12022 my_getExpression (&imm_expr, s);
12023 check_absolute_expr (ip, &imm_expr);
12024 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12025 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12026 if (imm_expr.X_add_number < min_range
12027 || imm_expr.X_add_number > max_range)
12029 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12030 (long) min_range, (long) max_range,
12031 (long) imm_expr.X_add_number);
12033 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12034 imm_expr.X_op = O_absent;
12038 case 'c': /* 9-bit signed offset in bit 6 */
12039 gas_assert (!mips_opts.micromips);
12040 my_getExpression (&imm_expr, s);
12041 check_absolute_expr (ip, &imm_expr);
12042 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12043 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12044 /* We check the offset range before adjusted. */
12047 if (imm_expr.X_add_number < min_range
12048 || imm_expr.X_add_number > max_range)
12050 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12051 (long) min_range, (long) max_range,
12052 (long) imm_expr.X_add_number);
12054 if (imm_expr.X_add_number & 0xf)
12056 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12057 (long) imm_expr.X_add_number);
12059 /* Right shift 4 bits to adjust the offset operand. */
12060 INSERT_OPERAND (0, OFFSET_C, *ip,
12061 imm_expr.X_add_number >> 4);
12062 imm_expr.X_op = O_absent;
12067 gas_assert (!mips_opts.micromips);
12068 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12070 if (regno == AT && mips_opts.at)
12072 if (mips_opts.at == ATREG)
12073 as_warn (_("used $at without \".set noat\""));
12075 as_warn (_("used $%u with \".set at=$%u\""),
12076 regno, mips_opts.at);
12078 INSERT_OPERAND (0, RZ, *ip, regno);
12082 gas_assert (!mips_opts.micromips);
12083 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12085 INSERT_OPERAND (0, FZ, *ip, regno);
12095 /* Check whether there is only a single bracketed expression
12096 left. If so, it must be the base register and the
12097 constant must be zero. */
12098 if (*s == '(' && strchr (s + 1, '(') == 0)
12101 /* If this value won't fit into the offset, then go find
12102 a macro that will generate a 16- or 32-bit offset code
12104 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12105 if ((i == 0 && (imm_expr.X_op != O_constant
12106 || imm_expr.X_add_number >= 1 << shift
12107 || imm_expr.X_add_number < -1 << shift))
12110 imm_expr.X_op = O_absent;
12113 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12114 imm_expr.X_add_number);
12115 imm_expr.X_op = O_absent;
12121 as_bad (_("Internal error: bad %s opcode "
12122 "(unknown extension operand type `+%c'): %s %s"),
12123 mips_opts.micromips ? "microMIPS" : "MIPS",
12124 *args, insn->name, insn->args);
12125 /* Further processing is fruitless. */
12130 case '.': /* 10-bit offset. */
12131 gas_assert (mips_opts.micromips);
12132 case '~': /* 12-bit offset. */
12134 int shift = *args == '.' ? 9 : 11;
12137 /* Check whether there is only a single bracketed expression
12138 left. If so, it must be the base register and the
12139 constant must be zero. */
12140 if (*s == '(' && strchr (s + 1, '(') == 0)
12143 /* If this value won't fit into the offset, then go find
12144 a macro that will generate a 16- or 32-bit offset code
12146 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12147 if ((i == 0 && (imm_expr.X_op != O_constant
12148 || imm_expr.X_add_number >= 1 << shift
12149 || imm_expr.X_add_number < -1 << shift))
12152 imm_expr.X_op = O_absent;
12156 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12158 INSERT_OPERAND (mips_opts.micromips,
12159 OFFSET12, *ip, imm_expr.X_add_number);
12160 imm_expr.X_op = O_absent;
12165 case '<': /* must be at least one digit */
12167 * According to the manual, if the shift amount is greater
12168 * than 31 or less than 0, then the shift amount should be
12169 * mod 32. In reality the mips assembler issues an error.
12170 * We issue a warning and mask out all but the low 5 bits.
12172 my_getExpression (&imm_expr, s);
12173 check_absolute_expr (ip, &imm_expr);
12174 if ((unsigned long) imm_expr.X_add_number > 31)
12175 as_warn (_("Improper shift amount (%lu)"),
12176 (unsigned long) imm_expr.X_add_number);
12177 INSERT_OPERAND (mips_opts.micromips,
12178 SHAMT, *ip, imm_expr.X_add_number);
12179 imm_expr.X_op = O_absent;
12183 case '>': /* shift amount minus 32 */
12184 my_getExpression (&imm_expr, s);
12185 check_absolute_expr (ip, &imm_expr);
12186 if ((unsigned long) imm_expr.X_add_number < 32
12187 || (unsigned long) imm_expr.X_add_number > 63)
12189 INSERT_OPERAND (mips_opts.micromips,
12190 SHAMT, *ip, imm_expr.X_add_number - 32);
12191 imm_expr.X_op = O_absent;
12195 case 'k': /* CACHE code. */
12196 case 'h': /* PREFX code. */
12197 case '1': /* SYNC type. */
12198 my_getExpression (&imm_expr, s);
12199 check_absolute_expr (ip, &imm_expr);
12200 if ((unsigned long) imm_expr.X_add_number > 31)
12201 as_warn (_("Invalid value for `%s' (%lu)"),
12203 (unsigned long) imm_expr.X_add_number);
12207 if (mips_fix_cn63xxp1
12208 && !mips_opts.micromips
12209 && strcmp ("pref", insn->name) == 0)
12210 switch (imm_expr.X_add_number)
12219 case 31: /* These are ok. */
12222 default: /* The rest must be changed to 28. */
12223 imm_expr.X_add_number = 28;
12226 INSERT_OPERAND (mips_opts.micromips,
12227 CACHE, *ip, imm_expr.X_add_number);
12230 INSERT_OPERAND (mips_opts.micromips,
12231 PREFX, *ip, imm_expr.X_add_number);
12234 INSERT_OPERAND (mips_opts.micromips,
12235 STYPE, *ip, imm_expr.X_add_number);
12238 imm_expr.X_op = O_absent;
12242 case 'c': /* BREAK code. */
12244 unsigned long mask = (mips_opts.micromips
12245 ? MICROMIPSOP_MASK_CODE
12248 my_getExpression (&imm_expr, s);
12249 check_absolute_expr (ip, &imm_expr);
12250 if ((unsigned long) imm_expr.X_add_number > mask)
12251 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12253 mask, (unsigned long) imm_expr.X_add_number);
12254 INSERT_OPERAND (mips_opts.micromips,
12255 CODE, *ip, imm_expr.X_add_number);
12256 imm_expr.X_op = O_absent;
12261 case 'q': /* Lower BREAK code. */
12263 unsigned long mask = (mips_opts.micromips
12264 ? MICROMIPSOP_MASK_CODE2
12267 my_getExpression (&imm_expr, s);
12268 check_absolute_expr (ip, &imm_expr);
12269 if ((unsigned long) imm_expr.X_add_number > mask)
12270 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12272 mask, (unsigned long) imm_expr.X_add_number);
12273 INSERT_OPERAND (mips_opts.micromips,
12274 CODE2, *ip, imm_expr.X_add_number);
12275 imm_expr.X_op = O_absent;
12280 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12282 unsigned long mask = (mips_opts.micromips
12283 ? MICROMIPSOP_MASK_CODE10
12286 my_getExpression (&imm_expr, s);
12287 check_absolute_expr (ip, &imm_expr);
12288 if ((unsigned long) imm_expr.X_add_number > mask)
12289 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12291 mask, (unsigned long) imm_expr.X_add_number);
12292 if (mips_opts.micromips)
12293 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12295 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12296 imm_expr.X_op = O_absent;
12301 case 'C': /* 25- or 23-bit coprocessor code. */
12303 unsigned long mask = (mips_opts.micromips
12304 ? MICROMIPSOP_MASK_COPZ
12307 my_getExpression (&imm_expr, s);
12308 check_absolute_expr (ip, &imm_expr);
12309 if ((unsigned long) imm_expr.X_add_number > mask)
12310 as_warn (_("Coproccesor code > %u bits (%lu)"),
12311 mips_opts.micromips ? 23U : 25U,
12312 (unsigned long) imm_expr.X_add_number);
12313 INSERT_OPERAND (mips_opts.micromips,
12314 COPZ, *ip, imm_expr.X_add_number);
12315 imm_expr.X_op = O_absent;
12320 case 'J': /* 19-bit WAIT code. */
12321 gas_assert (!mips_opts.micromips);
12322 my_getExpression (&imm_expr, s);
12323 check_absolute_expr (ip, &imm_expr);
12324 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12326 as_warn (_("Illegal 19-bit code (%lu)"),
12327 (unsigned long) imm_expr.X_add_number);
12328 imm_expr.X_add_number &= OP_MASK_CODE19;
12330 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12331 imm_expr.X_op = O_absent;
12335 case 'P': /* Performance register. */
12336 gas_assert (!mips_opts.micromips);
12337 my_getExpression (&imm_expr, s);
12338 check_absolute_expr (ip, &imm_expr);
12339 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12340 as_warn (_("Invalid performance register (%lu)"),
12341 (unsigned long) imm_expr.X_add_number);
12342 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12343 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12344 as_warn (_("Invalid performance register (%lu)"),
12345 (unsigned long) imm_expr.X_add_number);
12346 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12347 imm_expr.X_op = O_absent;
12351 case 'G': /* Coprocessor destination register. */
12353 unsigned long opcode = ip->insn_opcode;
12354 unsigned long mask;
12355 unsigned int types;
12358 if (mips_opts.micromips)
12360 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12361 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12362 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12366 case 0x000000fc: /* mfc0 */
12367 case 0x000002fc: /* mtc0 */
12368 case 0x580000fc: /* dmfc0 */
12369 case 0x580002fc: /* dmtc0 */
12379 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12380 cop0 = opcode == OP_OP_COP0;
12382 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12383 ok = reg_lookup (&s, types, ®no);
12384 if (mips_opts.micromips)
12385 INSERT_OPERAND (1, RS, *ip, regno);
12387 INSERT_OPERAND (0, RD, *ip, regno);
12396 case 'y': /* ALNV.PS source register. */
12397 gas_assert (mips_opts.micromips);
12399 case 'x': /* Ignore register name. */
12400 case 'U': /* Destination register (CLO/CLZ). */
12401 case 'g': /* Coprocessor destination register. */
12402 gas_assert (!mips_opts.micromips);
12403 case 'b': /* Base register. */
12404 case 'd': /* Destination register. */
12405 case 's': /* Source register. */
12406 case 't': /* Target register. */
12407 case 'r': /* Both target and source. */
12408 case 'v': /* Both dest and source. */
12409 case 'w': /* Both dest and target. */
12410 case 'E': /* Coprocessor target register. */
12411 case 'K': /* RDHWR destination register. */
12412 case 'z': /* Must be zero register. */
12415 if (*args == 'E' || *args == 'K')
12416 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12419 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12420 if (regno == AT && mips_opts.at)
12422 if (mips_opts.at == ATREG)
12423 as_warn (_("Used $at without \".set noat\""));
12425 as_warn (_("Used $%u with \".set at=$%u\""),
12426 regno, mips_opts.at);
12436 if (c == 'r' || c == 'v' || c == 'w')
12443 /* 'z' only matches $0. */
12444 if (c == 'z' && regno != 0)
12447 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12449 if (regno == lastregno)
12452 = _("Source and destination must be different");
12455 if (regno == 31 && lastregno == 0xffffffff)
12458 = _("A destination register must be supplied");
12462 /* Now that we have assembled one operand, we use the args
12463 string to figure out where it goes in the instruction. */
12470 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12474 if (mips_opts.micromips)
12475 INSERT_OPERAND (1, RS, *ip, regno);
12477 INSERT_OPERAND (0, RD, *ip, regno);
12482 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12486 gas_assert (!mips_opts.micromips);
12487 INSERT_OPERAND (0, RD, *ip, regno);
12488 INSERT_OPERAND (0, RT, *ip, regno);
12494 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12498 gas_assert (mips_opts.micromips);
12499 INSERT_OPERAND (1, RS3, *ip, regno);
12503 /* This case exists because on the r3000 trunc
12504 expands into a macro which requires a gp
12505 register. On the r6000 or r4000 it is
12506 assembled into a single instruction which
12507 ignores the register. Thus the insn version
12508 is MIPS_ISA2 and uses 'x', and the macro
12509 version is MIPS_ISA1 and uses 't'. */
12513 /* This case is for the div instruction, which
12514 acts differently if the destination argument
12515 is $0. This only matches $0, and is checked
12516 outside the switch. */
12526 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12530 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12535 case 'O': /* MDMX alignment immediate constant. */
12536 gas_assert (!mips_opts.micromips);
12537 my_getExpression (&imm_expr, s);
12538 check_absolute_expr (ip, &imm_expr);
12539 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12540 as_warn (_("Improper align amount (%ld), using low bits"),
12541 (long) imm_expr.X_add_number);
12542 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12543 imm_expr.X_op = O_absent;
12547 case 'Q': /* MDMX vector, element sel, or const. */
12550 /* MDMX Immediate. */
12551 gas_assert (!mips_opts.micromips);
12552 my_getExpression (&imm_expr, s);
12553 check_absolute_expr (ip, &imm_expr);
12554 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12555 as_warn (_("Invalid MDMX Immediate (%ld)"),
12556 (long) imm_expr.X_add_number);
12557 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12558 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12559 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12561 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12562 imm_expr.X_op = O_absent;
12566 /* Not MDMX Immediate. Fall through. */
12567 case 'X': /* MDMX destination register. */
12568 case 'Y': /* MDMX source register. */
12569 case 'Z': /* MDMX target register. */
12570 is_mdmx = !(insn->membership & INSN_5400);
12572 gas_assert (!mips_opts.micromips);
12573 case 'D': /* Floating point destination register. */
12574 case 'S': /* Floating point source register. */
12575 case 'T': /* Floating point target register. */
12576 case 'R': /* Floating point source register. */
12580 || ((mips_opts.ase & ASE_MDMX)
12581 && (ip->insn_mo->pinfo & FP_D)
12582 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12583 | INSN_COPROC_MEMORY_DELAY
12584 | INSN_LOAD_COPROC_DELAY
12585 | INSN_LOAD_MEMORY_DELAY
12586 | INSN_STORE_MEMORY))))
12587 rtype |= RTYPE_VEC;
12589 if (reg_lookup (&s, rtype, ®no))
12591 if ((regno & 1) != 0
12593 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12594 as_warn (_("Float register should be even, was %d"),
12602 if (c == 'V' || c == 'W')
12613 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12619 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12623 /* This is like 'Z', but also needs to fix the MDMX
12624 vector/scalar select bits. Note that the
12625 scalar immediate case is handled above. */
12626 if ((ip->insn_mo->membership & INSN_5400)
12627 && strcmp (insn->name, "rzu.ob") == 0)
12628 as_bad (_("Operand %d of `%s' must be an immediate"),
12629 argnum, ip->insn_mo->name);
12633 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12634 int max_el = (is_qh ? 3 : 7);
12636 my_getExpression(&imm_expr, s);
12637 check_absolute_expr (ip, &imm_expr);
12639 if (imm_expr.X_add_number > max_el)
12640 as_bad (_("Bad element selector %ld"),
12641 (long) imm_expr.X_add_number);
12642 imm_expr.X_add_number &= max_el;
12643 ip->insn_opcode |= (imm_expr.X_add_number
12646 imm_expr.X_op = O_absent;
12648 as_warn (_("Expecting ']' found '%s'"), s);
12654 if ((ip->insn_mo->membership & INSN_5400)
12655 && (strcmp (insn->name, "sll.ob") == 0
12656 || strcmp (insn->name, "srl.ob") == 0))
12657 as_bad (_("Operand %d of `%s' must be scalar"),
12658 argnum, ip->insn_mo->name);
12660 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12661 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12664 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12667 /* Fall through. */
12671 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12675 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12685 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12689 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12695 my_getExpression (&imm_expr, s);
12696 if (imm_expr.X_op != O_big
12697 && imm_expr.X_op != O_constant)
12698 insn_error = _("absolute expression required");
12699 if (HAVE_32BIT_GPRS)
12700 normalize_constant_expr (&imm_expr);
12705 /* If we expect a base register, check whether there is only
12706 a single bracketed expression left. If so, it must be the
12707 base register and the constant must be zero. */
12708 if (args[1] == '(' && *s == '(' && strchr (s + 1, '(') == 0)
12710 offset_expr.X_op = O_constant;
12711 offset_expr.X_add_number = 0;
12715 my_getSmallExpression (&offset_expr, offset_reloc, s);
12716 normalize_address_expr (&offset_expr);
12730 unsigned char temp[8];
12732 unsigned int length;
12737 /* These only appear as the last operand in an
12738 instruction, and every instruction that accepts
12739 them in any variant accepts them in all variants.
12740 This means we don't have to worry about backing out
12741 any changes if the instruction does not match.
12743 The difference between them is the size of the
12744 floating point constant and where it goes. For 'F'
12745 and 'L' the constant is 64 bits; for 'f' and 'l' it
12746 is 32 bits. Where the constant is placed is based
12747 on how the MIPS assembler does things:
12750 f -- immediate value
12753 The .lit4 and .lit8 sections are only used if
12754 permitted by the -G argument.
12756 The code below needs to know whether the target register
12757 is 32 or 64 bits wide. It relies on the fact 'f' and
12758 'F' are used with GPR-based instructions and 'l' and
12759 'L' are used with FPR-based instructions. */
12761 f64 = *args == 'F' || *args == 'L';
12762 using_gprs = *args == 'F' || *args == 'f';
12764 save_in = input_line_pointer;
12765 input_line_pointer = s;
12766 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12768 s = input_line_pointer;
12769 input_line_pointer = save_in;
12770 if (err != NULL && *err != '\0')
12772 as_bad (_("Bad floating point constant: %s"), err);
12773 memset (temp, '\0', sizeof temp);
12774 length = f64 ? 8 : 4;
12777 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12781 && (g_switch_value < 4
12782 || (temp[0] == 0 && temp[1] == 0)
12783 || (temp[2] == 0 && temp[3] == 0))))
12785 imm_expr.X_op = O_constant;
12786 if (!target_big_endian)
12787 imm_expr.X_add_number = bfd_getl32 (temp);
12789 imm_expr.X_add_number = bfd_getb32 (temp);
12791 else if (length > 4
12792 && !mips_disable_float_construction
12793 /* Constants can only be constructed in GPRs and
12794 copied to FPRs if the GPRs are at least as wide
12795 as the FPRs. Force the constant into memory if
12796 we are using 64-bit FPRs but the GPRs are only
12799 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12800 && ((temp[0] == 0 && temp[1] == 0)
12801 || (temp[2] == 0 && temp[3] == 0))
12802 && ((temp[4] == 0 && temp[5] == 0)
12803 || (temp[6] == 0 && temp[7] == 0)))
12805 /* The value is simple enough to load with a couple of
12806 instructions. If using 32-bit registers, set
12807 imm_expr to the high order 32 bits and offset_expr to
12808 the low order 32 bits. Otherwise, set imm_expr to
12809 the entire 64 bit constant. */
12810 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12812 imm_expr.X_op = O_constant;
12813 offset_expr.X_op = O_constant;
12814 if (!target_big_endian)
12816 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12817 offset_expr.X_add_number = bfd_getl32 (temp);
12821 imm_expr.X_add_number = bfd_getb32 (temp);
12822 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12824 if (offset_expr.X_add_number == 0)
12825 offset_expr.X_op = O_absent;
12829 imm_expr.X_op = O_constant;
12830 if (!target_big_endian)
12831 imm_expr.X_add_number = bfd_getl64 (temp);
12833 imm_expr.X_add_number = bfd_getb64 (temp);
12838 const char *newname;
12841 /* Switch to the right section. */
12843 subseg = now_subseg;
12846 default: /* unused default case avoids warnings. */
12848 newname = RDATA_SECTION_NAME;
12849 if (g_switch_value >= 8)
12853 newname = RDATA_SECTION_NAME;
12856 gas_assert (g_switch_value >= 4);
12860 new_seg = subseg_new (newname, (subsegT) 0);
12861 bfd_set_section_flags (stdoutput, new_seg,
12866 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12867 if (strncmp (TARGET_OS, "elf", 3) != 0)
12868 record_alignment (new_seg, 4);
12870 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12871 if (seg == now_seg)
12872 as_bad (_("Can't use floating point insn in this section"));
12874 /* Set the argument to the current address in the
12876 offset_expr.X_op = O_symbol;
12877 offset_expr.X_add_symbol = symbol_temp_new_now ();
12878 offset_expr.X_add_number = 0;
12880 /* Put the floating point number into the section. */
12881 p = frag_more ((int) length);
12882 memcpy (p, temp, length);
12884 /* Switch back to the original section. */
12885 subseg_set (seg, subseg);
12890 case 'i': /* 16-bit unsigned immediate. */
12891 case 'j': /* 16-bit signed immediate. */
12892 *imm_reloc = BFD_RELOC_LO16;
12893 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12896 offsetT minval, maxval;
12898 more = (insn + 1 < past
12899 && strcmp (insn->name, insn[1].name) == 0);
12901 /* For compatibility with older assemblers, we accept
12902 0x8000-0xffff as signed 16-bit numbers when only
12903 signed numbers are allowed. */
12905 minval = 0, maxval = 0xffff;
12907 minval = -0x8000, maxval = 0x7fff;
12909 minval = -0x8000, maxval = 0xffff;
12911 if (imm_expr.X_op != O_constant
12912 || imm_expr.X_add_number < minval
12913 || imm_expr.X_add_number > maxval)
12917 if (imm_expr.X_op == O_constant
12918 || imm_expr.X_op == O_big)
12919 as_bad (_("Expression out of range"));
12925 case 'o': /* 16-bit offset. */
12926 offset_reloc[0] = BFD_RELOC_LO16;
12927 offset_reloc[1] = BFD_RELOC_UNUSED;
12928 offset_reloc[2] = BFD_RELOC_UNUSED;
12930 /* Check whether there is only a single bracketed expression
12931 left. If so, it must be the base register and the
12932 constant must be zero. */
12933 if (*s == '(' && strchr (s + 1, '(') == 0)
12935 offset_expr.X_op = O_constant;
12936 offset_expr.X_add_number = 0;
12940 /* If this value won't fit into a 16 bit offset, then go
12941 find a macro that will generate the 32 bit offset
12943 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12944 && (offset_expr.X_op != O_constant
12945 || offset_expr.X_add_number >= 0x8000
12946 || offset_expr.X_add_number < -0x8000))
12952 case 'p': /* PC-relative offset. */
12953 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12954 my_getExpression (&offset_expr, s);
12958 case 'u': /* Upper 16 bits. */
12959 *imm_reloc = BFD_RELOC_LO16;
12960 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12961 && imm_expr.X_op == O_constant
12962 && (imm_expr.X_add_number < 0
12963 || imm_expr.X_add_number >= 0x10000))
12964 as_bad (_("lui expression (%lu) not in range 0..65535"),
12965 (unsigned long) imm_expr.X_add_number);
12969 case 'a': /* 26-bit address. */
12971 *offset_reloc = BFD_RELOC_MIPS_JMP;
12972 my_getExpression (&offset_expr, s);
12976 case 'N': /* 3-bit branch condition code. */
12977 case 'M': /* 3-bit compare condition code. */
12979 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12980 rtype |= RTYPE_FCC;
12981 if (!reg_lookup (&s, rtype, ®no))
12983 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12984 || strcmp (str + strlen (str) - 5, "any2f") == 0
12985 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12986 && (regno & 1) != 0)
12987 as_warn (_("Condition code register should be even for %s, "
12990 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12991 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12992 && (regno & 3) != 0)
12993 as_warn (_("Condition code register should be 0 or 4 for %s, "
12997 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12999 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
13003 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
13014 while (ISDIGIT (*s));
13017 c = 8; /* Invalid sel value. */
13020 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13021 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13025 gas_assert (!mips_opts.micromips);
13026 /* Must be at least one digit. */
13027 my_getExpression (&imm_expr, s);
13028 check_absolute_expr (ip, &imm_expr);
13030 if ((unsigned long) imm_expr.X_add_number
13031 > (unsigned long) OP_MASK_VECBYTE)
13033 as_bad (_("bad byte vector index (%ld)"),
13034 (long) imm_expr.X_add_number);
13035 imm_expr.X_add_number = 0;
13038 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13039 imm_expr.X_op = O_absent;
13044 gas_assert (!mips_opts.micromips);
13045 my_getExpression (&imm_expr, s);
13046 check_absolute_expr (ip, &imm_expr);
13048 if ((unsigned long) imm_expr.X_add_number
13049 > (unsigned long) OP_MASK_VECALIGN)
13051 as_bad (_("bad byte vector index (%ld)"),
13052 (long) imm_expr.X_add_number);
13053 imm_expr.X_add_number = 0;
13056 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13057 imm_expr.X_op = O_absent;
13061 case 'm': /* Opcode extension character. */
13062 gas_assert (mips_opts.micromips);
13067 if (strncmp (s, "$pc", 3) == 0)
13094 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13095 if (regno == AT && mips_opts.at)
13097 if (mips_opts.at == ATREG)
13098 as_warn (_("Used $at without \".set noat\""));
13100 as_warn (_("Used $%u with \".set at=$%u\""),
13101 regno, mips_opts.at);
13107 gas_assert (args[1] == ',');
13113 gas_assert (args[1] == ',');
13115 continue; /* Nothing to do. */
13121 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13123 if (regno == lastregno)
13126 = _("Source and destination must be different");
13129 if (regno == 31 && lastregno == 0xffffffff)
13132 = _("A destination register must be supplied");
13143 gas_assert (args[1] == ',');
13150 gas_assert (args[1] == ',');
13153 continue; /* Nothing to do. */
13157 /* Make sure regno is the same as lastregno. */
13158 if (c == 't' && regno != lastregno)
13161 /* Make sure regno is the same as destregno. */
13162 if (c == 'x' && regno != destregno)
13165 /* We need to save regno, before regno maps to the
13166 microMIPS register encoding. */
13176 regno = ILLEGAL_REG;
13180 regno = mips32_to_micromips_reg_b_map[regno];
13184 regno = mips32_to_micromips_reg_c_map[regno];
13188 regno = mips32_to_micromips_reg_d_map[regno];
13192 regno = mips32_to_micromips_reg_e_map[regno];
13196 regno = mips32_to_micromips_reg_f_map[regno];
13200 regno = mips32_to_micromips_reg_g_map[regno];
13204 s += strspn (s, " \t");
13207 regno = ILLEGAL_REG;
13211 s += strspn (s, " \t");
13212 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
13215 regno = ILLEGAL_REG;
13218 if (regno2 == AT && mips_opts.at)
13220 if (mips_opts.at == ATREG)
13221 as_warn (_("Used $at without \".set noat\""));
13223 as_warn (_("Used $%u with \".set at=$%u\""),
13224 regno2, mips_opts.at);
13226 regno = (mips_lookup_reg_pair
13228 micromips_to_32_reg_h_map1,
13229 micromips_to_32_reg_h_map2, 8));
13233 regno = mips32_to_micromips_reg_l_map[regno];
13237 regno = mips32_to_micromips_reg_m_map[regno];
13241 regno = mips32_to_micromips_reg_n_map[regno];
13245 regno = mips32_to_micromips_reg_q_map[regno];
13250 regno = ILLEGAL_REG;
13255 regno = ILLEGAL_REG;
13260 regno = ILLEGAL_REG;
13263 case 'j': /* Do nothing. */
13273 if (regno == ILLEGAL_REG)
13279 INSERT_OPERAND (1, MB, *ip, regno);
13283 INSERT_OPERAND (1, MC, *ip, regno);
13287 INSERT_OPERAND (1, MD, *ip, regno);
13291 INSERT_OPERAND (1, ME, *ip, regno);
13295 INSERT_OPERAND (1, MF, *ip, regno);
13299 INSERT_OPERAND (1, MG, *ip, regno);
13303 INSERT_OPERAND (1, MH, *ip, regno);
13307 INSERT_OPERAND (1, MJ, *ip, regno);
13311 INSERT_OPERAND (1, ML, *ip, regno);
13315 INSERT_OPERAND (1, MM, *ip, regno);
13319 INSERT_OPERAND (1, MN, *ip, regno);
13323 INSERT_OPERAND (1, MP, *ip, regno);
13327 INSERT_OPERAND (1, MQ, *ip, regno);
13330 case 'a': /* Do nothing. */
13331 case 's': /* Do nothing. */
13332 case 't': /* Do nothing. */
13333 case 'x': /* Do nothing. */
13334 case 'y': /* Do nothing. */
13335 case 'z': /* Do nothing. */
13345 bfd_reloc_code_real_type r[3];
13349 /* Check whether there is only a single bracketed
13350 expression left. If so, it must be the base register
13351 and the constant must be zero. */
13352 if (*s == '(' && strchr (s + 1, '(') == 0)
13354 INSERT_OPERAND (1, IMMA, *ip, 0);
13358 if (my_getSmallExpression (&ep, r, s) > 0
13359 || !expr_const_in_range (&ep, -64, 64, 2))
13362 imm = ep.X_add_number >> 2;
13363 INSERT_OPERAND (1, IMMA, *ip, imm);
13370 bfd_reloc_code_real_type r[3];
13374 if (my_getSmallExpression (&ep, r, s) > 0
13375 || ep.X_op != O_constant)
13378 for (imm = 0; imm < 8; imm++)
13379 if (micromips_imm_b_map[imm] == ep.X_add_number)
13384 INSERT_OPERAND (1, IMMB, *ip, imm);
13391 bfd_reloc_code_real_type r[3];
13395 if (my_getSmallExpression (&ep, r, s) > 0
13396 || ep.X_op != O_constant)
13399 for (imm = 0; imm < 16; imm++)
13400 if (micromips_imm_c_map[imm] == ep.X_add_number)
13405 INSERT_OPERAND (1, IMMC, *ip, imm);
13410 case 'D': /* pc relative offset */
13411 case 'E': /* pc relative offset */
13412 my_getExpression (&offset_expr, s);
13413 if (offset_expr.X_op == O_register)
13416 if (!forced_insn_length)
13417 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13419 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13421 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13427 bfd_reloc_code_real_type r[3];
13431 if (my_getSmallExpression (&ep, r, s) > 0
13432 || !expr_const_in_range (&ep, 0, 16, 0))
13435 imm = ep.X_add_number;
13436 INSERT_OPERAND (1, IMMF, *ip, imm);
13443 bfd_reloc_code_real_type r[3];
13447 /* Check whether there is only a single bracketed
13448 expression left. If so, it must be the base register
13449 and the constant must be zero. */
13450 if (*s == '(' && strchr (s + 1, '(') == 0)
13452 INSERT_OPERAND (1, IMMG, *ip, 0);
13456 if (my_getSmallExpression (&ep, r, s) > 0
13457 || !expr_const_in_range (&ep, -1, 15, 0))
13460 imm = ep.X_add_number & 15;
13461 INSERT_OPERAND (1, IMMG, *ip, imm);
13468 bfd_reloc_code_real_type r[3];
13472 /* Check whether there is only a single bracketed
13473 expression left. If so, it must be the base register
13474 and the constant must be zero. */
13475 if (*s == '(' && strchr (s + 1, '(') == 0)
13477 INSERT_OPERAND (1, IMMH, *ip, 0);
13481 if (my_getSmallExpression (&ep, r, s) > 0
13482 || !expr_const_in_range (&ep, 0, 16, 1))
13485 imm = ep.X_add_number >> 1;
13486 INSERT_OPERAND (1, IMMH, *ip, imm);
13493 bfd_reloc_code_real_type r[3];
13497 if (my_getSmallExpression (&ep, r, s) > 0
13498 || !expr_const_in_range (&ep, -1, 127, 0))
13501 imm = ep.X_add_number & 127;
13502 INSERT_OPERAND (1, IMMI, *ip, imm);
13509 bfd_reloc_code_real_type r[3];
13513 /* Check whether there is only a single bracketed
13514 expression left. If so, it must be the base register
13515 and the constant must be zero. */
13516 if (*s == '(' && strchr (s + 1, '(') == 0)
13518 INSERT_OPERAND (1, IMMJ, *ip, 0);
13522 if (my_getSmallExpression (&ep, r, s) > 0
13523 || !expr_const_in_range (&ep, 0, 16, 2))
13526 imm = ep.X_add_number >> 2;
13527 INSERT_OPERAND (1, IMMJ, *ip, imm);
13534 bfd_reloc_code_real_type r[3];
13538 /* Check whether there is only a single bracketed
13539 expression left. If so, it must be the base register
13540 and the constant must be zero. */
13541 if (*s == '(' && strchr (s + 1, '(') == 0)
13543 INSERT_OPERAND (1, IMML, *ip, 0);
13547 if (my_getSmallExpression (&ep, r, s) > 0
13548 || !expr_const_in_range (&ep, 0, 16, 0))
13551 imm = ep.X_add_number;
13552 INSERT_OPERAND (1, IMML, *ip, imm);
13559 bfd_reloc_code_real_type r[3];
13563 if (my_getSmallExpression (&ep, r, s) > 0
13564 || !expr_const_in_range (&ep, 1, 9, 0))
13567 imm = ep.X_add_number & 7;
13568 INSERT_OPERAND (1, IMMM, *ip, imm);
13573 case 'N': /* Register list for lwm and swm. */
13575 /* A comma-separated list of registers and/or
13576 dash-separated contiguous ranges including
13577 both ra and a set of one or more registers
13578 starting at s0 up to s3 which have to be
13585 and any permutations of these. */
13586 unsigned int reglist;
13589 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13592 if ((reglist & 0xfff1ffff) != 0x80010000)
13595 reglist = (reglist >> 17) & 7;
13597 if ((reglist & -reglist) != reglist)
13600 imm = ffs (reglist) - 1;
13601 INSERT_OPERAND (1, IMMN, *ip, imm);
13605 case 'O': /* sdbbp 4-bit code. */
13607 bfd_reloc_code_real_type r[3];
13611 if (my_getSmallExpression (&ep, r, s) > 0
13612 || !expr_const_in_range (&ep, 0, 16, 0))
13615 imm = ep.X_add_number;
13616 INSERT_OPERAND (1, IMMO, *ip, imm);
13623 bfd_reloc_code_real_type r[3];
13627 if (my_getSmallExpression (&ep, r, s) > 0
13628 || !expr_const_in_range (&ep, 0, 32, 2))
13631 imm = ep.X_add_number >> 2;
13632 INSERT_OPERAND (1, IMMP, *ip, imm);
13639 bfd_reloc_code_real_type r[3];
13643 if (my_getSmallExpression (&ep, r, s) > 0
13644 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13647 imm = ep.X_add_number >> 2;
13648 INSERT_OPERAND (1, IMMQ, *ip, imm);
13655 bfd_reloc_code_real_type r[3];
13659 /* Check whether there is only a single bracketed
13660 expression left. If so, it must be the base register
13661 and the constant must be zero. */
13662 if (*s == '(' && strchr (s + 1, '(') == 0)
13664 INSERT_OPERAND (1, IMMU, *ip, 0);
13668 if (my_getSmallExpression (&ep, r, s) > 0
13669 || !expr_const_in_range (&ep, 0, 32, 2))
13672 imm = ep.X_add_number >> 2;
13673 INSERT_OPERAND (1, IMMU, *ip, imm);
13680 bfd_reloc_code_real_type r[3];
13684 if (my_getSmallExpression (&ep, r, s) > 0
13685 || !expr_const_in_range (&ep, 0, 64, 2))
13688 imm = ep.X_add_number >> 2;
13689 INSERT_OPERAND (1, IMMW, *ip, imm);
13696 bfd_reloc_code_real_type r[3];
13700 if (my_getSmallExpression (&ep, r, s) > 0
13701 || !expr_const_in_range (&ep, -8, 8, 0))
13704 imm = ep.X_add_number;
13705 INSERT_OPERAND (1, IMMX, *ip, imm);
13712 bfd_reloc_code_real_type r[3];
13716 if (my_getSmallExpression (&ep, r, s) > 0
13717 || expr_const_in_range (&ep, -2, 2, 2)
13718 || !expr_const_in_range (&ep, -258, 258, 2))
13721 imm = ep.X_add_number >> 2;
13722 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13723 INSERT_OPERAND (1, IMMY, *ip, imm);
13730 bfd_reloc_code_real_type r[3];
13733 if (my_getSmallExpression (&ep, r, s) > 0
13734 || !expr_const_in_range (&ep, 0, 1, 0))
13741 as_bad (_("Internal error: bad microMIPS opcode "
13742 "(unknown extension operand type `m%c'): %s %s"),
13743 *args, insn->name, insn->args);
13744 /* Further processing is fruitless. */
13749 case 'n': /* Register list for 32-bit lwm and swm. */
13750 gas_assert (mips_opts.micromips);
13752 /* A comma-separated list of registers and/or
13753 dash-separated contiguous ranges including
13754 at least one of ra and a set of one or more
13755 registers starting at s0 up to s7 and then
13756 s8 which have to be consecutive, e.g.:
13764 and any permutations of these. */
13765 unsigned int reglist;
13769 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13772 if ((reglist & 0x3f00ffff) != 0)
13775 ra = (reglist >> 27) & 0x10;
13776 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13778 if ((reglist & -reglist) != reglist)
13781 imm = (ffs (reglist) - 1) | ra;
13782 INSERT_OPERAND (1, RT, *ip, imm);
13783 imm_expr.X_op = O_absent;
13787 case '|': /* 4-bit trap code. */
13788 gas_assert (mips_opts.micromips);
13789 my_getExpression (&imm_expr, s);
13790 check_absolute_expr (ip, &imm_expr);
13791 if ((unsigned long) imm_expr.X_add_number
13792 > MICROMIPSOP_MASK_TRAP)
13793 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13794 (unsigned long) imm_expr.X_add_number,
13795 ip->insn_mo->name);
13796 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13797 imm_expr.X_op = O_absent;
13802 as_bad (_("Bad char = '%c'\n"), *args);
13807 /* Args don't match. */
13809 insn_error = _("Illegal operands");
13810 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13815 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13817 gas_assert (firstinsn);
13818 need_delay_slot_ok = FALSE;
13827 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13829 /* This routine assembles an instruction into its binary format when
13830 assembling for the mips16. As a side effect, it sets one of the
13831 global variables imm_reloc or offset_reloc to the type of relocation
13832 to do if one of the operands is an address expression. It also sets
13833 forced_insn_length to the resulting instruction size in bytes if the
13834 user explicitly requested a small or extended instruction. */
13837 mips16_ip (char *str, struct mips_cl_insn *ip)
13841 struct mips_opcode *insn;
13843 unsigned int regno;
13844 unsigned int lastregno = 0;
13850 forced_insn_length = 0;
13852 for (s = str; ISLOWER (*s); ++s)
13864 if (s[1] == 't' && s[2] == ' ')
13867 forced_insn_length = 2;
13871 else if (s[1] == 'e' && s[2] == ' ')
13874 forced_insn_length = 4;
13878 /* Fall through. */
13880 insn_error = _("unknown opcode");
13884 if (mips_opts.noautoextend && !forced_insn_length)
13885 forced_insn_length = 2;
13887 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13889 insn_error = _("unrecognized opcode");
13898 gas_assert (strcmp (insn->name, str) == 0);
13900 ok = is_opcode_valid_16 (insn);
13903 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13904 && strcmp (insn->name, insn[1].name) == 0)
13913 static char buf[100];
13915 _("Opcode not supported on this processor: %s (%s)"),
13916 mips_cpu_info_from_arch (mips_opts.arch)->name,
13917 mips_cpu_info_from_isa (mips_opts.isa)->name);
13924 create_insn (ip, insn);
13925 imm_expr.X_op = O_absent;
13926 imm_reloc[0] = BFD_RELOC_UNUSED;
13927 imm_reloc[1] = BFD_RELOC_UNUSED;
13928 imm_reloc[2] = BFD_RELOC_UNUSED;
13929 imm2_expr.X_op = O_absent;
13930 offset_expr.X_op = O_absent;
13931 offset_reloc[0] = BFD_RELOC_UNUSED;
13932 offset_reloc[1] = BFD_RELOC_UNUSED;
13933 offset_reloc[2] = BFD_RELOC_UNUSED;
13934 for (args = insn->args; 1; ++args)
13941 /* In this switch statement we call break if we did not find
13942 a match, continue if we did find a match, or return if we
13953 /* Stuff the immediate value in now, if we can. */
13954 if (imm_expr.X_op == O_constant
13955 && *imm_reloc > BFD_RELOC_UNUSED
13956 && insn->pinfo != INSN_MACRO
13957 && calculate_reloc (*offset_reloc,
13958 imm_expr.X_add_number, &value))
13960 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13961 *offset_reloc, value, forced_insn_length,
13963 imm_expr.X_op = O_absent;
13964 *imm_reloc = BFD_RELOC_UNUSED;
13965 *offset_reloc = BFD_RELOC_UNUSED;
13979 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13982 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13998 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14000 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14004 /* Fall through. */
14015 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14017 if (c == 'v' || c == 'w')
14020 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14022 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14033 if (c == 'v' || c == 'w')
14035 regno = mips16_to_32_reg_map[lastregno];
14049 regno = mips32_to_16_reg_map[regno];
14054 regno = ILLEGAL_REG;
14059 regno = ILLEGAL_REG;
14064 regno = ILLEGAL_REG;
14069 if (regno == AT && mips_opts.at)
14071 if (mips_opts.at == ATREG)
14072 as_warn (_("used $at without \".set noat\""));
14074 as_warn (_("used $%u with \".set at=$%u\""),
14075 regno, mips_opts.at);
14083 if (regno == ILLEGAL_REG)
14090 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14094 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14097 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14100 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14106 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14109 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14110 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14120 if (strncmp (s, "$pc", 3) == 0)
14137 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
14140 if (imm_expr.X_op != O_constant)
14142 forced_insn_length = 4;
14143 ip->insn_opcode |= MIPS16_EXTEND;
14147 /* We need to relax this instruction. */
14148 *offset_reloc = *imm_reloc;
14149 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14154 *imm_reloc = BFD_RELOC_UNUSED;
14155 /* Fall through. */
14162 my_getExpression (&imm_expr, s);
14163 if (imm_expr.X_op == O_register)
14165 /* What we thought was an expression turned out to
14168 if (s[0] == '(' && args[1] == '(')
14170 /* It looks like the expression was omitted
14171 before a register indirection, which means
14172 that the expression is implicitly zero. We
14173 still set up imm_expr, so that we handle
14174 explicit extensions correctly. */
14175 imm_expr.X_op = O_constant;
14176 imm_expr.X_add_number = 0;
14177 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14184 /* We need to relax this instruction. */
14185 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14194 /* We use offset_reloc rather than imm_reloc for the PC
14195 relative operands. This lets macros with both
14196 immediate and address operands work correctly. */
14197 my_getExpression (&offset_expr, s);
14199 if (offset_expr.X_op == O_register)
14202 /* We need to relax this instruction. */
14203 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
14207 case '6': /* break code */
14208 my_getExpression (&imm_expr, s);
14209 check_absolute_expr (ip, &imm_expr);
14210 if ((unsigned long) imm_expr.X_add_number > 63)
14211 as_warn (_("Invalid value for `%s' (%lu)"),
14213 (unsigned long) imm_expr.X_add_number);
14214 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14215 imm_expr.X_op = O_absent;
14219 case 'a': /* 26 bit address */
14221 my_getExpression (&offset_expr, s);
14223 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14224 ip->insn_opcode <<= 16;
14227 case 'l': /* register list for entry macro */
14228 case 'L': /* register list for exit macro */
14238 unsigned int freg, reg1, reg2;
14240 while (*s == ' ' || *s == ',')
14242 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14244 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14248 as_bad (_("can't parse register list"));
14258 if (!reg_lookup (&s, freg ? RTYPE_FPU
14259 : (RTYPE_GP | RTYPE_NUM), ®2))
14261 as_bad (_("invalid register list"));
14265 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14267 mask &= ~ (7 << 3);
14270 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14272 mask &= ~ (7 << 3);
14275 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14276 mask |= (reg2 - 3) << 3;
14277 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14278 mask |= (reg2 - 15) << 1;
14279 else if (reg1 == RA && reg2 == RA)
14283 as_bad (_("invalid register list"));
14287 /* The mask is filled in in the opcode table for the
14288 benefit of the disassembler. We remove it before
14289 applying the actual mask. */
14290 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14291 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14295 case 'm': /* Register list for save insn. */
14296 case 'M': /* Register list for restore insn. */
14298 int opcode = ip->insn_opcode;
14299 int framesz = 0, seen_framesz = 0;
14300 int nargs = 0, statics = 0, sregs = 0;
14304 unsigned int reg1, reg2;
14306 SKIP_SPACE_TABS (s);
14309 SKIP_SPACE_TABS (s);
14311 my_getExpression (&imm_expr, s);
14312 if (imm_expr.X_op == O_constant)
14314 /* Handle the frame size. */
14317 as_bad (_("more than one frame size in list"));
14321 framesz = imm_expr.X_add_number;
14322 imm_expr.X_op = O_absent;
14327 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14329 as_bad (_("can't parse register list"));
14341 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14344 as_bad (_("can't parse register list"));
14349 while (reg1 <= reg2)
14351 if (reg1 >= 4 && reg1 <= 7)
14355 nargs |= 1 << (reg1 - 4);
14357 /* statics $a0-$a3 */
14358 statics |= 1 << (reg1 - 4);
14360 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14363 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14365 else if (reg1 == 31)
14367 /* Add $ra to insn. */
14372 as_bad (_("unexpected register in list"));
14380 /* Encode args/statics combination. */
14381 if (nargs & statics)
14382 as_bad (_("arg/static registers overlap"));
14383 else if (nargs == 0xf)
14384 /* All $a0-$a3 are args. */
14385 opcode |= MIPS16_ALL_ARGS << 16;
14386 else if (statics == 0xf)
14387 /* All $a0-$a3 are statics. */
14388 opcode |= MIPS16_ALL_STATICS << 16;
14391 int narg = 0, nstat = 0;
14393 /* Count arg registers. */
14394 while (nargs & 0x1)
14400 as_bad (_("invalid arg register list"));
14402 /* Count static registers. */
14403 while (statics & 0x8)
14405 statics = (statics << 1) & 0xf;
14409 as_bad (_("invalid static register list"));
14411 /* Encode args/statics. */
14412 opcode |= ((narg << 2) | nstat) << 16;
14415 /* Encode $s0/$s1. */
14416 if (sregs & (1 << 0)) /* $s0 */
14418 if (sregs & (1 << 1)) /* $s1 */
14424 /* Count regs $s2-$s8. */
14432 as_bad (_("invalid static register list"));
14433 /* Encode $s2-$s8. */
14434 opcode |= nsreg << 24;
14437 /* Encode frame size. */
14439 as_bad (_("missing frame size"));
14440 else if ((framesz & 7) != 0 || framesz < 0
14441 || framesz > 0xff * 8)
14442 as_bad (_("invalid frame size"));
14443 else if (framesz != 128 || (opcode >> 16) != 0)
14446 opcode |= (((framesz & 0xf0) << 16)
14447 | (framesz & 0x0f));
14450 /* Finally build the instruction. */
14451 if ((opcode >> 16) != 0 || framesz == 0)
14452 opcode |= MIPS16_EXTEND;
14453 ip->insn_opcode = opcode;
14457 case 'e': /* extend code */
14458 my_getExpression (&imm_expr, s);
14459 check_absolute_expr (ip, &imm_expr);
14460 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14462 as_warn (_("Invalid value for `%s' (%lu)"),
14464 (unsigned long) imm_expr.X_add_number);
14465 imm_expr.X_add_number &= 0x7ff;
14467 ip->insn_opcode |= imm_expr.X_add_number;
14468 imm_expr.X_op = O_absent;
14478 /* Args don't match. */
14479 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14480 strcmp (insn->name, insn[1].name) == 0)
14487 insn_error = _("illegal operands");
14493 /* This structure holds information we know about a mips16 immediate
14496 struct mips16_immed_operand
14498 /* The type code used in the argument string in the opcode table. */
14500 /* The number of bits in the short form of the opcode. */
14502 /* The number of bits in the extended form of the opcode. */
14504 /* The amount by which the short form is shifted when it is used;
14505 for example, the sw instruction has a shift count of 2. */
14507 /* The amount by which the short form is shifted when it is stored
14508 into the instruction code. */
14510 /* Non-zero if the short form is unsigned. */
14512 /* Non-zero if the extended form is unsigned. */
14514 /* Non-zero if the value is PC relative. */
14518 /* The mips16 immediate operand types. */
14520 static const struct mips16_immed_operand mips16_immed_operands[] =
14522 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14523 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14524 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14525 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14526 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14527 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14528 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14529 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14530 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14531 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14532 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14533 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14534 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14535 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14536 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14537 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14538 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14539 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14540 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14541 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14542 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14545 #define MIPS16_NUM_IMMED \
14546 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14548 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14549 NBITS is the number of significant bits in VAL. */
14551 static unsigned long
14552 mips16_immed_extend (offsetT val, unsigned int nbits)
14557 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14560 else if (nbits == 15)
14562 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14567 extval = ((val & 0x1f) << 6) | (val & 0x20);
14570 return (extval << 16) | val;
14573 /* Install immediate value VAL into MIPS16 instruction *INSN,
14574 extending it if necessary. The instruction in *INSN may
14575 already be extended.
14577 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14578 if none. In the former case, VAL is a 16-bit number with no
14579 defined signedness.
14581 TYPE is the type of the immediate field. USER_INSN_LENGTH
14582 is the length that the user requested, or 0 if none. */
14585 mips16_immed (char *file, unsigned int line, int type,
14586 bfd_reloc_code_real_type reloc, offsetT val,
14587 unsigned int user_insn_length, unsigned long *insn)
14589 const struct mips16_immed_operand *op;
14590 int mintiny, maxtiny;
14592 op = mips16_immed_operands;
14593 while (op->type != type)
14596 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14601 if (type == '<' || type == '>' || type == '[' || type == ']')
14604 maxtiny = 1 << op->nbits;
14609 maxtiny = (1 << op->nbits) - 1;
14611 if (reloc != BFD_RELOC_UNUSED)
14616 mintiny = - (1 << (op->nbits - 1));
14617 maxtiny = (1 << (op->nbits - 1)) - 1;
14618 if (reloc != BFD_RELOC_UNUSED)
14619 val = SEXT_16BIT (val);
14622 /* Branch offsets have an implicit 0 in the lowest bit. */
14623 if (type == 'p' || type == 'q')
14626 if ((val & ((1 << op->shift) - 1)) != 0
14627 || val < (mintiny << op->shift)
14628 || val > (maxtiny << op->shift))
14630 /* We need an extended instruction. */
14631 if (user_insn_length == 2)
14632 as_bad_where (file, line, _("invalid unextended operand value"));
14634 *insn |= MIPS16_EXTEND;
14636 else if (user_insn_length == 4)
14638 /* The operand doesn't force an unextended instruction to be extended.
14639 Warn if the user wanted an extended instruction anyway. */
14640 *insn |= MIPS16_EXTEND;
14641 as_warn_where (file, line,
14642 _("extended operand requested but not required"));
14645 if (mips16_opcode_length (*insn) == 2)
14649 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14650 insnval <<= op->op_shift;
14655 long minext, maxext;
14657 if (reloc == BFD_RELOC_UNUSED)
14662 maxext = (1 << op->extbits) - 1;
14666 minext = - (1 << (op->extbits - 1));
14667 maxext = (1 << (op->extbits - 1)) - 1;
14669 if (val < minext || val > maxext)
14670 as_bad_where (file, line,
14671 _("operand value out of range for instruction"));
14674 *insn |= mips16_immed_extend (val, op->extbits);
14678 struct percent_op_match
14681 bfd_reloc_code_real_type reloc;
14684 static const struct percent_op_match mips_percent_op[] =
14686 {"%lo", BFD_RELOC_LO16},
14687 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14688 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14689 {"%call16", BFD_RELOC_MIPS_CALL16},
14690 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14691 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14692 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14693 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14694 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14695 {"%got", BFD_RELOC_MIPS_GOT16},
14696 {"%gp_rel", BFD_RELOC_GPREL16},
14697 {"%half", BFD_RELOC_16},
14698 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14699 {"%higher", BFD_RELOC_MIPS_HIGHER},
14700 {"%neg", BFD_RELOC_MIPS_SUB},
14701 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14702 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14703 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14704 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14705 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14706 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14707 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14708 {"%hi", BFD_RELOC_HI16_S}
14711 static const struct percent_op_match mips16_percent_op[] =
14713 {"%lo", BFD_RELOC_MIPS16_LO16},
14714 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14715 {"%got", BFD_RELOC_MIPS16_GOT16},
14716 {"%call16", BFD_RELOC_MIPS16_CALL16},
14717 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14718 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14719 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14720 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14721 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14722 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14723 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14724 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14728 /* Return true if *STR points to a relocation operator. When returning true,
14729 move *STR over the operator and store its relocation code in *RELOC.
14730 Leave both *STR and *RELOC alone when returning false. */
14733 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14735 const struct percent_op_match *percent_op;
14738 if (mips_opts.mips16)
14740 percent_op = mips16_percent_op;
14741 limit = ARRAY_SIZE (mips16_percent_op);
14745 percent_op = mips_percent_op;
14746 limit = ARRAY_SIZE (mips_percent_op);
14749 for (i = 0; i < limit; i++)
14750 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14752 int len = strlen (percent_op[i].str);
14754 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14757 *str += strlen (percent_op[i].str);
14758 *reloc = percent_op[i].reloc;
14760 /* Check whether the output BFD supports this relocation.
14761 If not, issue an error and fall back on something safe. */
14762 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14764 as_bad (_("relocation %s isn't supported by the current ABI"),
14765 percent_op[i].str);
14766 *reloc = BFD_RELOC_UNUSED;
14774 /* Parse string STR as a 16-bit relocatable operand. Store the
14775 expression in *EP and the relocations in the array starting
14776 at RELOC. Return the number of relocation operators used.
14778 On exit, EXPR_END points to the first character after the expression. */
14781 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14784 bfd_reloc_code_real_type reversed_reloc[3];
14785 size_t reloc_index, i;
14786 int crux_depth, str_depth;
14789 /* Search for the start of the main expression, recoding relocations
14790 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14791 of the main expression and with CRUX_DEPTH containing the number
14792 of open brackets at that point. */
14799 crux_depth = str_depth;
14801 /* Skip over whitespace and brackets, keeping count of the number
14803 while (*str == ' ' || *str == '\t' || *str == '(')
14808 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14809 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14811 my_getExpression (ep, crux);
14814 /* Match every open bracket. */
14815 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14819 if (crux_depth > 0)
14820 as_bad (_("unclosed '('"));
14824 if (reloc_index != 0)
14826 prev_reloc_op_frag = frag_now;
14827 for (i = 0; i < reloc_index; i++)
14828 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14831 return reloc_index;
14835 my_getExpression (expressionS *ep, char *str)
14839 save_in = input_line_pointer;
14840 input_line_pointer = str;
14842 expr_end = input_line_pointer;
14843 input_line_pointer = save_in;
14847 md_atof (int type, char *litP, int *sizeP)
14849 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14853 md_number_to_chars (char *buf, valueT val, int n)
14855 if (target_big_endian)
14856 number_to_chars_bigendian (buf, val, n);
14858 number_to_chars_littleendian (buf, val, n);
14861 static int support_64bit_objects(void)
14863 const char **list, **l;
14866 list = bfd_target_list ();
14867 for (l = list; *l != NULL; l++)
14868 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14869 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14871 yes = (*l != NULL);
14876 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14877 NEW_VALUE. Warn if another value was already specified. Note:
14878 we have to defer parsing the -march and -mtune arguments in order
14879 to handle 'from-abi' correctly, since the ABI might be specified
14880 in a later argument. */
14883 mips_set_option_string (const char **string_ptr, const char *new_value)
14885 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14886 as_warn (_("A different %s was already specified, is now %s"),
14887 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14890 *string_ptr = new_value;
14894 md_parse_option (int c, char *arg)
14898 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14899 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14901 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14902 c == mips_ases[i].option_on);
14908 case OPTION_CONSTRUCT_FLOATS:
14909 mips_disable_float_construction = 0;
14912 case OPTION_NO_CONSTRUCT_FLOATS:
14913 mips_disable_float_construction = 1;
14925 target_big_endian = 1;
14929 target_big_endian = 0;
14935 else if (arg[0] == '0')
14937 else if (arg[0] == '1')
14947 mips_debug = atoi (arg);
14951 file_mips_isa = ISA_MIPS1;
14955 file_mips_isa = ISA_MIPS2;
14959 file_mips_isa = ISA_MIPS3;
14963 file_mips_isa = ISA_MIPS4;
14967 file_mips_isa = ISA_MIPS5;
14970 case OPTION_MIPS32:
14971 file_mips_isa = ISA_MIPS32;
14974 case OPTION_MIPS32R2:
14975 file_mips_isa = ISA_MIPS32R2;
14978 case OPTION_MIPS64R2:
14979 file_mips_isa = ISA_MIPS64R2;
14982 case OPTION_MIPS64:
14983 file_mips_isa = ISA_MIPS64;
14987 mips_set_option_string (&mips_tune_string, arg);
14991 mips_set_option_string (&mips_arch_string, arg);
14995 mips_set_option_string (&mips_arch_string, "4650");
14996 mips_set_option_string (&mips_tune_string, "4650");
14999 case OPTION_NO_M4650:
15003 mips_set_option_string (&mips_arch_string, "4010");
15004 mips_set_option_string (&mips_tune_string, "4010");
15007 case OPTION_NO_M4010:
15011 mips_set_option_string (&mips_arch_string, "4100");
15012 mips_set_option_string (&mips_tune_string, "4100");
15015 case OPTION_NO_M4100:
15019 mips_set_option_string (&mips_arch_string, "3900");
15020 mips_set_option_string (&mips_tune_string, "3900");
15023 case OPTION_NO_M3900:
15026 case OPTION_MICROMIPS:
15027 if (mips_opts.mips16 == 1)
15029 as_bad (_("-mmicromips cannot be used with -mips16"));
15032 mips_opts.micromips = 1;
15033 mips_no_prev_insn ();
15036 case OPTION_NO_MICROMIPS:
15037 mips_opts.micromips = 0;
15038 mips_no_prev_insn ();
15041 case OPTION_MIPS16:
15042 if (mips_opts.micromips == 1)
15044 as_bad (_("-mips16 cannot be used with -micromips"));
15047 mips_opts.mips16 = 1;
15048 mips_no_prev_insn ();
15051 case OPTION_NO_MIPS16:
15052 mips_opts.mips16 = 0;
15053 mips_no_prev_insn ();
15056 case OPTION_FIX_24K:
15060 case OPTION_NO_FIX_24K:
15064 case OPTION_FIX_LOONGSON2F_JUMP:
15065 mips_fix_loongson2f_jump = TRUE;
15068 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15069 mips_fix_loongson2f_jump = FALSE;
15072 case OPTION_FIX_LOONGSON2F_NOP:
15073 mips_fix_loongson2f_nop = TRUE;
15076 case OPTION_NO_FIX_LOONGSON2F_NOP:
15077 mips_fix_loongson2f_nop = FALSE;
15080 case OPTION_FIX_VR4120:
15081 mips_fix_vr4120 = 1;
15084 case OPTION_NO_FIX_VR4120:
15085 mips_fix_vr4120 = 0;
15088 case OPTION_FIX_VR4130:
15089 mips_fix_vr4130 = 1;
15092 case OPTION_NO_FIX_VR4130:
15093 mips_fix_vr4130 = 0;
15096 case OPTION_FIX_CN63XXP1:
15097 mips_fix_cn63xxp1 = TRUE;
15100 case OPTION_NO_FIX_CN63XXP1:
15101 mips_fix_cn63xxp1 = FALSE;
15104 case OPTION_RELAX_BRANCH:
15105 mips_relax_branch = 1;
15108 case OPTION_NO_RELAX_BRANCH:
15109 mips_relax_branch = 0;
15112 case OPTION_INSN32:
15113 mips_opts.insn32 = TRUE;
15116 case OPTION_NO_INSN32:
15117 mips_opts.insn32 = FALSE;
15120 case OPTION_MSHARED:
15121 mips_in_shared = TRUE;
15124 case OPTION_MNO_SHARED:
15125 mips_in_shared = FALSE;
15128 case OPTION_MSYM32:
15129 mips_opts.sym32 = TRUE;
15132 case OPTION_MNO_SYM32:
15133 mips_opts.sym32 = FALSE;
15136 /* When generating ELF code, we permit -KPIC and -call_shared to
15137 select SVR4_PIC, and -non_shared to select no PIC. This is
15138 intended to be compatible with Irix 5. */
15139 case OPTION_CALL_SHARED:
15140 mips_pic = SVR4_PIC;
15141 mips_abicalls = TRUE;
15144 case OPTION_CALL_NONPIC:
15146 mips_abicalls = TRUE;
15149 case OPTION_NON_SHARED:
15151 mips_abicalls = FALSE;
15154 /* The -xgot option tells the assembler to use 32 bit offsets
15155 when accessing the got in SVR4_PIC mode. It is for Irix
15162 g_switch_value = atoi (arg);
15166 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15169 mips_abi = O32_ABI;
15173 mips_abi = N32_ABI;
15177 mips_abi = N64_ABI;
15178 if (!support_64bit_objects())
15179 as_fatal (_("No compiled in support for 64 bit object file format"));
15183 file_mips_gp32 = 1;
15187 file_mips_gp32 = 0;
15191 file_mips_fp32 = 1;
15195 file_mips_fp32 = 0;
15198 case OPTION_SINGLE_FLOAT:
15199 file_mips_single_float = 1;
15202 case OPTION_DOUBLE_FLOAT:
15203 file_mips_single_float = 0;
15206 case OPTION_SOFT_FLOAT:
15207 file_mips_soft_float = 1;
15210 case OPTION_HARD_FLOAT:
15211 file_mips_soft_float = 0;
15215 if (strcmp (arg, "32") == 0)
15216 mips_abi = O32_ABI;
15217 else if (strcmp (arg, "o64") == 0)
15218 mips_abi = O64_ABI;
15219 else if (strcmp (arg, "n32") == 0)
15220 mips_abi = N32_ABI;
15221 else if (strcmp (arg, "64") == 0)
15223 mips_abi = N64_ABI;
15224 if (! support_64bit_objects())
15225 as_fatal (_("No compiled in support for 64 bit object file "
15228 else if (strcmp (arg, "eabi") == 0)
15229 mips_abi = EABI_ABI;
15232 as_fatal (_("invalid abi -mabi=%s"), arg);
15237 case OPTION_M7000_HILO_FIX:
15238 mips_7000_hilo_fix = TRUE;
15241 case OPTION_MNO_7000_HILO_FIX:
15242 mips_7000_hilo_fix = FALSE;
15245 case OPTION_MDEBUG:
15246 mips_flag_mdebug = TRUE;
15249 case OPTION_NO_MDEBUG:
15250 mips_flag_mdebug = FALSE;
15254 mips_flag_pdr = TRUE;
15257 case OPTION_NO_PDR:
15258 mips_flag_pdr = FALSE;
15261 case OPTION_MVXWORKS_PIC:
15262 mips_pic = VXWORKS_PIC;
15269 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15274 /* Set up globals to generate code for the ISA or processor
15275 described by INFO. */
15278 mips_set_architecture (const struct mips_cpu_info *info)
15282 file_mips_arch = info->cpu;
15283 mips_opts.arch = info->cpu;
15284 mips_opts.isa = info->isa;
15289 /* Likewise for tuning. */
15292 mips_set_tune (const struct mips_cpu_info *info)
15295 mips_tune = info->cpu;
15300 mips_after_parse_args (void)
15302 const struct mips_cpu_info *arch_info = 0;
15303 const struct mips_cpu_info *tune_info = 0;
15305 /* GP relative stuff not working for PE */
15306 if (strncmp (TARGET_OS, "pe", 2) == 0)
15308 if (g_switch_seen && g_switch_value != 0)
15309 as_bad (_("-G not supported in this configuration."));
15310 g_switch_value = 0;
15313 if (mips_abi == NO_ABI)
15314 mips_abi = MIPS_DEFAULT_ABI;
15316 /* The following code determines the architecture and register size.
15317 Similar code was added to GCC 3.3 (see override_options() in
15318 config/mips/mips.c). The GAS and GCC code should be kept in sync
15319 as much as possible. */
15321 if (mips_arch_string != 0)
15322 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15324 if (file_mips_isa != ISA_UNKNOWN)
15326 /* Handle -mipsN. At this point, file_mips_isa contains the
15327 ISA level specified by -mipsN, while arch_info->isa contains
15328 the -march selection (if any). */
15329 if (arch_info != 0)
15331 /* -march takes precedence over -mipsN, since it is more descriptive.
15332 There's no harm in specifying both as long as the ISA levels
15334 if (file_mips_isa != arch_info->isa)
15335 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15336 mips_cpu_info_from_isa (file_mips_isa)->name,
15337 mips_cpu_info_from_isa (arch_info->isa)->name);
15340 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15343 if (arch_info == 0)
15345 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15346 gas_assert (arch_info);
15349 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15350 as_bad (_("-march=%s is not compatible with the selected ABI"),
15353 mips_set_architecture (arch_info);
15355 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15356 if (mips_tune_string != 0)
15357 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15359 if (tune_info == 0)
15360 mips_set_tune (arch_info);
15362 mips_set_tune (tune_info);
15364 if (file_mips_gp32 >= 0)
15366 /* The user specified the size of the integer registers. Make sure
15367 it agrees with the ABI and ISA. */
15368 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15369 as_bad (_("-mgp64 used with a 32-bit processor"));
15370 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15371 as_bad (_("-mgp32 used with a 64-bit ABI"));
15372 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15373 as_bad (_("-mgp64 used with a 32-bit ABI"));
15377 /* Infer the integer register size from the ABI and processor.
15378 Restrict ourselves to 32-bit registers if that's all the
15379 processor has, or if the ABI cannot handle 64-bit registers. */
15380 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15381 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15384 switch (file_mips_fp32)
15388 /* No user specified float register size.
15389 ??? GAS treats single-float processors as though they had 64-bit
15390 float registers (although it complains when double-precision
15391 instructions are used). As things stand, saying they have 32-bit
15392 registers would lead to spurious "register must be even" messages.
15393 So here we assume float registers are never smaller than the
15395 if (file_mips_gp32 == 0)
15396 /* 64-bit integer registers implies 64-bit float registers. */
15397 file_mips_fp32 = 0;
15398 else if ((mips_opts.ase & FP64_ASES)
15399 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15400 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15401 file_mips_fp32 = 0;
15403 /* 32-bit float registers. */
15404 file_mips_fp32 = 1;
15407 /* The user specified the size of the float registers. Check if it
15408 agrees with the ABI and ISA. */
15410 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15411 as_bad (_("-mfp64 used with a 32-bit fpu"));
15412 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15413 && !ISA_HAS_MXHC1 (mips_opts.isa))
15414 as_warn (_("-mfp64 used with a 32-bit ABI"));
15417 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15418 as_warn (_("-mfp32 used with a 64-bit ABI"));
15422 /* End of GCC-shared inference code. */
15424 /* This flag is set when we have a 64-bit capable CPU but use only
15425 32-bit wide registers. Note that EABI does not use it. */
15426 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15427 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15428 || mips_abi == O32_ABI))
15429 mips_32bitmode = 1;
15431 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15432 as_bad (_("trap exception not supported at ISA 1"));
15434 /* If the selected architecture includes support for ASEs, enable
15435 generation of code for them. */
15436 if (mips_opts.mips16 == -1)
15437 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15438 if (mips_opts.micromips == -1)
15439 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15441 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15442 ASEs from being selected implicitly. */
15443 if (file_mips_fp32 == 1)
15444 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15446 /* If the user didn't explicitly select or deselect a particular ASE,
15447 use the default setting for the CPU. */
15448 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15450 file_mips_isa = mips_opts.isa;
15451 file_ase = mips_opts.ase;
15452 mips_opts.gp32 = file_mips_gp32;
15453 mips_opts.fp32 = file_mips_fp32;
15454 mips_opts.soft_float = file_mips_soft_float;
15455 mips_opts.single_float = file_mips_single_float;
15457 mips_check_isa_supports_ases ();
15459 if (mips_flag_mdebug < 0)
15460 mips_flag_mdebug = 0;
15464 mips_init_after_args (void)
15466 /* initialize opcodes */
15467 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15468 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15472 md_pcrel_from (fixS *fixP)
15474 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15475 switch (fixP->fx_r_type)
15477 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15478 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15479 /* Return the address of the delay slot. */
15482 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15483 case BFD_RELOC_MICROMIPS_JMP:
15484 case BFD_RELOC_16_PCREL_S2:
15485 case BFD_RELOC_MIPS_JMP:
15486 /* Return the address of the delay slot. */
15489 case BFD_RELOC_32_PCREL:
15493 /* We have no relocation type for PC relative MIPS16 instructions. */
15494 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15495 as_bad_where (fixP->fx_file, fixP->fx_line,
15496 _("PC relative MIPS16 instruction references a different section"));
15501 /* This is called before the symbol table is processed. In order to
15502 work with gcc when using mips-tfile, we must keep all local labels.
15503 However, in other cases, we want to discard them. If we were
15504 called with -g, but we didn't see any debugging information, it may
15505 mean that gcc is smuggling debugging information through to
15506 mips-tfile, in which case we must generate all local labels. */
15509 mips_frob_file_before_adjust (void)
15511 #ifndef NO_ECOFF_DEBUGGING
15512 if (ECOFF_DEBUGGING
15514 && ! ecoff_debugging_seen)
15515 flag_keep_locals = 1;
15519 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15520 the corresponding LO16 reloc. This is called before md_apply_fix and
15521 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15522 relocation operators.
15524 For our purposes, a %lo() expression matches a %got() or %hi()
15527 (a) it refers to the same symbol; and
15528 (b) the offset applied in the %lo() expression is no lower than
15529 the offset applied in the %got() or %hi().
15531 (b) allows us to cope with code like:
15534 lh $4,%lo(foo+2)($4)
15536 ...which is legal on RELA targets, and has a well-defined behaviour
15537 if the user knows that adding 2 to "foo" will not induce a carry to
15540 When several %lo()s match a particular %got() or %hi(), we use the
15541 following rules to distinguish them:
15543 (1) %lo()s with smaller offsets are a better match than %lo()s with
15546 (2) %lo()s with no matching %got() or %hi() are better than those
15547 that already have a matching %got() or %hi().
15549 (3) later %lo()s are better than earlier %lo()s.
15551 These rules are applied in order.
15553 (1) means, among other things, that %lo()s with identical offsets are
15554 chosen if they exist.
15556 (2) means that we won't associate several high-part relocations with
15557 the same low-part relocation unless there's no alternative. Having
15558 several high parts for the same low part is a GNU extension; this rule
15559 allows careful users to avoid it.
15561 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15562 with the last high-part relocation being at the front of the list.
15563 It therefore makes sense to choose the last matching low-part
15564 relocation, all other things being equal. It's also easier
15565 to code that way. */
15568 mips_frob_file (void)
15570 struct mips_hi_fixup *l;
15571 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15573 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15575 segment_info_type *seginfo;
15576 bfd_boolean matched_lo_p;
15577 fixS **hi_pos, **lo_pos, **pos;
15579 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15581 /* If a GOT16 relocation turns out to be against a global symbol,
15582 there isn't supposed to be a matching LO. Ignore %gots against
15583 constants; we'll report an error for those later. */
15584 if (got16_reloc_p (l->fixp->fx_r_type)
15585 && !(l->fixp->fx_addsy
15586 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15589 /* Check quickly whether the next fixup happens to be a matching %lo. */
15590 if (fixup_has_matching_lo_p (l->fixp))
15593 seginfo = seg_info (l->seg);
15595 /* Set HI_POS to the position of this relocation in the chain.
15596 Set LO_POS to the position of the chosen low-part relocation.
15597 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15598 relocation that matches an immediately-preceding high-part
15602 matched_lo_p = FALSE;
15603 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15605 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15607 if (*pos == l->fixp)
15610 if ((*pos)->fx_r_type == looking_for_rtype
15611 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15612 && (*pos)->fx_offset >= l->fixp->fx_offset
15614 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15616 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15619 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15620 && fixup_has_matching_lo_p (*pos));
15623 /* If we found a match, remove the high-part relocation from its
15624 current position and insert it before the low-part relocation.
15625 Make the offsets match so that fixup_has_matching_lo_p()
15628 We don't warn about unmatched high-part relocations since some
15629 versions of gcc have been known to emit dead "lui ...%hi(...)"
15631 if (lo_pos != NULL)
15633 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15634 if (l->fixp->fx_next != *lo_pos)
15636 *hi_pos = l->fixp->fx_next;
15637 l->fixp->fx_next = *lo_pos;
15645 mips_force_relocation (fixS *fixp)
15647 if (generic_force_reloc (fixp))
15650 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15651 so that the linker relaxation can update targets. */
15652 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15653 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15654 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15660 /* Read the instruction associated with RELOC from BUF. */
15662 static unsigned int
15663 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15665 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15666 return read_compressed_insn (buf, 4);
15668 return read_insn (buf);
15671 /* Write instruction INSN to BUF, given that it has been relocated
15675 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15676 unsigned long insn)
15678 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15679 write_compressed_insn (buf, insn, 4);
15681 write_insn (buf, insn);
15684 /* Apply a fixup to the object file. */
15687 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15690 unsigned long insn;
15691 reloc_howto_type *howto;
15693 /* We ignore generic BFD relocations we don't know about. */
15694 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15698 gas_assert (fixP->fx_size == 2
15699 || fixP->fx_size == 4
15700 || fixP->fx_r_type == BFD_RELOC_16
15701 || fixP->fx_r_type == BFD_RELOC_64
15702 || fixP->fx_r_type == BFD_RELOC_CTOR
15703 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15704 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15705 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15706 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15707 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15709 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15711 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15712 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15713 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15714 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15715 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15717 /* Don't treat parts of a composite relocation as done. There are two
15720 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15721 should nevertheless be emitted if the first part is.
15723 (2) In normal usage, composite relocations are never assembly-time
15724 constants. The easiest way of dealing with the pathological
15725 exceptions is to generate a relocation against STN_UNDEF and
15726 leave everything up to the linker. */
15727 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15730 switch (fixP->fx_r_type)
15732 case BFD_RELOC_MIPS_TLS_GD:
15733 case BFD_RELOC_MIPS_TLS_LDM:
15734 case BFD_RELOC_MIPS_TLS_DTPREL32:
15735 case BFD_RELOC_MIPS_TLS_DTPREL64:
15736 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15737 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15738 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15739 case BFD_RELOC_MIPS_TLS_TPREL32:
15740 case BFD_RELOC_MIPS_TLS_TPREL64:
15741 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15742 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15743 case BFD_RELOC_MICROMIPS_TLS_GD:
15744 case BFD_RELOC_MICROMIPS_TLS_LDM:
15745 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15746 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15747 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15748 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15749 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15750 case BFD_RELOC_MIPS16_TLS_GD:
15751 case BFD_RELOC_MIPS16_TLS_LDM:
15752 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15753 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15754 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15755 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15756 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15757 if (!fixP->fx_addsy)
15759 as_bad_where (fixP->fx_file, fixP->fx_line,
15760 _("TLS relocation against a constant"));
15763 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15766 case BFD_RELOC_MIPS_JMP:
15767 case BFD_RELOC_MIPS_SHIFT5:
15768 case BFD_RELOC_MIPS_SHIFT6:
15769 case BFD_RELOC_MIPS_GOT_DISP:
15770 case BFD_RELOC_MIPS_GOT_PAGE:
15771 case BFD_RELOC_MIPS_GOT_OFST:
15772 case BFD_RELOC_MIPS_SUB:
15773 case BFD_RELOC_MIPS_INSERT_A:
15774 case BFD_RELOC_MIPS_INSERT_B:
15775 case BFD_RELOC_MIPS_DELETE:
15776 case BFD_RELOC_MIPS_HIGHEST:
15777 case BFD_RELOC_MIPS_HIGHER:
15778 case BFD_RELOC_MIPS_SCN_DISP:
15779 case BFD_RELOC_MIPS_REL16:
15780 case BFD_RELOC_MIPS_RELGOT:
15781 case BFD_RELOC_MIPS_JALR:
15782 case BFD_RELOC_HI16:
15783 case BFD_RELOC_HI16_S:
15784 case BFD_RELOC_LO16:
15785 case BFD_RELOC_GPREL16:
15786 case BFD_RELOC_MIPS_LITERAL:
15787 case BFD_RELOC_MIPS_CALL16:
15788 case BFD_RELOC_MIPS_GOT16:
15789 case BFD_RELOC_GPREL32:
15790 case BFD_RELOC_MIPS_GOT_HI16:
15791 case BFD_RELOC_MIPS_GOT_LO16:
15792 case BFD_RELOC_MIPS_CALL_HI16:
15793 case BFD_RELOC_MIPS_CALL_LO16:
15794 case BFD_RELOC_MIPS16_GPREL:
15795 case BFD_RELOC_MIPS16_GOT16:
15796 case BFD_RELOC_MIPS16_CALL16:
15797 case BFD_RELOC_MIPS16_HI16:
15798 case BFD_RELOC_MIPS16_HI16_S:
15799 case BFD_RELOC_MIPS16_LO16:
15800 case BFD_RELOC_MIPS16_JMP:
15801 case BFD_RELOC_MICROMIPS_JMP:
15802 case BFD_RELOC_MICROMIPS_GOT_DISP:
15803 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15804 case BFD_RELOC_MICROMIPS_GOT_OFST:
15805 case BFD_RELOC_MICROMIPS_SUB:
15806 case BFD_RELOC_MICROMIPS_HIGHEST:
15807 case BFD_RELOC_MICROMIPS_HIGHER:
15808 case BFD_RELOC_MICROMIPS_SCN_DISP:
15809 case BFD_RELOC_MICROMIPS_JALR:
15810 case BFD_RELOC_MICROMIPS_HI16:
15811 case BFD_RELOC_MICROMIPS_HI16_S:
15812 case BFD_RELOC_MICROMIPS_LO16:
15813 case BFD_RELOC_MICROMIPS_GPREL16:
15814 case BFD_RELOC_MICROMIPS_LITERAL:
15815 case BFD_RELOC_MICROMIPS_CALL16:
15816 case BFD_RELOC_MICROMIPS_GOT16:
15817 case BFD_RELOC_MICROMIPS_GOT_HI16:
15818 case BFD_RELOC_MICROMIPS_GOT_LO16:
15819 case BFD_RELOC_MICROMIPS_CALL_HI16:
15820 case BFD_RELOC_MICROMIPS_CALL_LO16:
15821 case BFD_RELOC_MIPS_EH:
15826 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15828 insn = read_reloc_insn (buf, fixP->fx_r_type);
15829 if (mips16_reloc_p (fixP->fx_r_type))
15830 insn |= mips16_immed_extend (value, 16);
15832 insn |= (value & 0xffff);
15833 write_reloc_insn (buf, fixP->fx_r_type, insn);
15836 as_bad_where (fixP->fx_file, fixP->fx_line,
15837 _("Unsupported constant in relocation"));
15842 /* This is handled like BFD_RELOC_32, but we output a sign
15843 extended value if we are only 32 bits. */
15846 if (8 <= sizeof (valueT))
15847 md_number_to_chars (buf, *valP, 8);
15852 if ((*valP & 0x80000000) != 0)
15856 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15857 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15862 case BFD_RELOC_RVA:
15864 case BFD_RELOC_32_PCREL:
15866 /* If we are deleting this reloc entry, we must fill in the
15867 value now. This can happen if we have a .word which is not
15868 resolved when it appears but is later defined. */
15870 md_number_to_chars (buf, *valP, fixP->fx_size);
15873 case BFD_RELOC_16_PCREL_S2:
15874 if ((*valP & 0x3) != 0)
15875 as_bad_where (fixP->fx_file, fixP->fx_line,
15876 _("Branch to misaligned address (%lx)"), (long) *valP);
15878 /* We need to save the bits in the instruction since fixup_segment()
15879 might be deleting the relocation entry (i.e., a branch within
15880 the current segment). */
15881 if (! fixP->fx_done)
15884 /* Update old instruction data. */
15885 insn = read_insn (buf);
15887 if (*valP + 0x20000 <= 0x3ffff)
15889 insn |= (*valP >> 2) & 0xffff;
15890 write_insn (buf, insn);
15892 else if (mips_pic == NO_PIC
15894 && fixP->fx_frag->fr_address >= text_section->vma
15895 && (fixP->fx_frag->fr_address
15896 < text_section->vma + bfd_get_section_size (text_section))
15897 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15898 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15899 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15901 /* The branch offset is too large. If this is an
15902 unconditional branch, and we are not generating PIC code,
15903 we can convert it to an absolute jump instruction. */
15904 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15905 insn = 0x0c000000; /* jal */
15907 insn = 0x08000000; /* j */
15908 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15910 fixP->fx_addsy = section_symbol (text_section);
15911 *valP += md_pcrel_from (fixP);
15912 write_insn (buf, insn);
15916 /* If we got here, we have branch-relaxation disabled,
15917 and there's nothing we can do to fix this instruction
15918 without turning it into a longer sequence. */
15919 as_bad_where (fixP->fx_file, fixP->fx_line,
15920 _("Branch out of range"));
15924 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15925 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15926 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15927 /* We adjust the offset back to even. */
15928 if ((*valP & 0x1) != 0)
15931 if (! fixP->fx_done)
15934 /* Should never visit here, because we keep the relocation. */
15938 case BFD_RELOC_VTABLE_INHERIT:
15941 && !S_IS_DEFINED (fixP->fx_addsy)
15942 && !S_IS_WEAK (fixP->fx_addsy))
15943 S_SET_WEAK (fixP->fx_addsy);
15946 case BFD_RELOC_VTABLE_ENTRY:
15954 /* Remember value for tc_gen_reloc. */
15955 fixP->fx_addnumber = *valP;
15965 name = input_line_pointer;
15966 c = get_symbol_end ();
15967 p = (symbolS *) symbol_find_or_make (name);
15968 *input_line_pointer = c;
15972 /* Align the current frag to a given power of two. If a particular
15973 fill byte should be used, FILL points to an integer that contains
15974 that byte, otherwise FILL is null.
15976 This function used to have the comment:
15978 The MIPS assembler also automatically adjusts any preceding label.
15980 The implementation therefore applied the adjustment to a maximum of
15981 one label. However, other label adjustments are applied to batches
15982 of labels, and adjusting just one caused problems when new labels
15983 were added for the sake of debugging or unwind information.
15984 We therefore adjust all preceding labels (given as LABELS) instead. */
15987 mips_align (int to, int *fill, struct insn_label_list *labels)
15989 mips_emit_delays ();
15990 mips_record_compressed_mode ();
15991 if (fill == NULL && subseg_text_p (now_seg))
15992 frag_align_code (to, 0);
15994 frag_align (to, fill ? *fill : 0, 0);
15995 record_alignment (now_seg, to);
15996 mips_move_labels (labels, FALSE);
15999 /* Align to a given power of two. .align 0 turns off the automatic
16000 alignment used by the data creating pseudo-ops. */
16003 s_align (int x ATTRIBUTE_UNUSED)
16005 int temp, fill_value, *fill_ptr;
16006 long max_alignment = 28;
16008 /* o Note that the assembler pulls down any immediately preceding label
16009 to the aligned address.
16010 o It's not documented but auto alignment is reinstated by
16011 a .align pseudo instruction.
16012 o Note also that after auto alignment is turned off the mips assembler
16013 issues an error on attempt to assemble an improperly aligned data item.
16016 temp = get_absolute_expression ();
16017 if (temp > max_alignment)
16018 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16021 as_warn (_("Alignment negative: 0 assumed."));
16024 if (*input_line_pointer == ',')
16026 ++input_line_pointer;
16027 fill_value = get_absolute_expression ();
16028 fill_ptr = &fill_value;
16034 segment_info_type *si = seg_info (now_seg);
16035 struct insn_label_list *l = si->label_list;
16036 /* Auto alignment should be switched on by next section change. */
16038 mips_align (temp, fill_ptr, l);
16045 demand_empty_rest_of_line ();
16049 s_change_sec (int sec)
16053 /* The ELF backend needs to know that we are changing sections, so
16054 that .previous works correctly. We could do something like check
16055 for an obj_section_change_hook macro, but that might be confusing
16056 as it would not be appropriate to use it in the section changing
16057 functions in read.c, since obj-elf.c intercepts those. FIXME:
16058 This should be cleaner, somehow. */
16059 obj_elf_section_change_hook ();
16061 mips_emit_delays ();
16072 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16073 demand_empty_rest_of_line ();
16077 seg = subseg_new (RDATA_SECTION_NAME,
16078 (subsegT) get_absolute_expression ());
16079 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16080 | SEC_READONLY | SEC_RELOC
16082 if (strncmp (TARGET_OS, "elf", 3) != 0)
16083 record_alignment (seg, 4);
16084 demand_empty_rest_of_line ();
16088 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16089 bfd_set_section_flags (stdoutput, seg,
16090 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16091 if (strncmp (TARGET_OS, "elf", 3) != 0)
16092 record_alignment (seg, 4);
16093 demand_empty_rest_of_line ();
16097 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16098 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16099 if (strncmp (TARGET_OS, "elf", 3) != 0)
16100 record_alignment (seg, 4);
16101 demand_empty_rest_of_line ();
16109 s_change_section (int ignore ATTRIBUTE_UNUSED)
16111 char *section_name;
16116 int section_entry_size;
16117 int section_alignment;
16119 section_name = input_line_pointer;
16120 c = get_symbol_end ();
16122 next_c = *(input_line_pointer + 1);
16124 /* Do we have .section Name<,"flags">? */
16125 if (c != ',' || (c == ',' && next_c == '"'))
16127 /* just after name is now '\0'. */
16128 *input_line_pointer = c;
16129 input_line_pointer = section_name;
16130 obj_elf_section (ignore);
16133 input_line_pointer++;
16135 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16137 section_type = get_absolute_expression ();
16140 if (*input_line_pointer++ == ',')
16141 section_flag = get_absolute_expression ();
16144 if (*input_line_pointer++ == ',')
16145 section_entry_size = get_absolute_expression ();
16147 section_entry_size = 0;
16148 if (*input_line_pointer++ == ',')
16149 section_alignment = get_absolute_expression ();
16151 section_alignment = 0;
16152 /* FIXME: really ignore? */
16153 (void) section_alignment;
16155 section_name = xstrdup (section_name);
16157 /* When using the generic form of .section (as implemented by obj-elf.c),
16158 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16159 traditionally had to fall back on the more common @progbits instead.
16161 There's nothing really harmful in this, since bfd will correct
16162 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16163 means that, for backwards compatibility, the special_section entries
16164 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16166 Even so, we shouldn't force users of the MIPS .section syntax to
16167 incorrectly label the sections as SHT_PROGBITS. The best compromise
16168 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16169 generic type-checking code. */
16170 if (section_type == SHT_MIPS_DWARF)
16171 section_type = SHT_PROGBITS;
16173 obj_elf_change_section (section_name, section_type, section_flag,
16174 section_entry_size, 0, 0, 0);
16176 if (now_seg->name != section_name)
16177 free (section_name);
16181 mips_enable_auto_align (void)
16187 s_cons (int log_size)
16189 segment_info_type *si = seg_info (now_seg);
16190 struct insn_label_list *l = si->label_list;
16192 mips_emit_delays ();
16193 if (log_size > 0 && auto_align)
16194 mips_align (log_size, 0, l);
16195 cons (1 << log_size);
16196 mips_clear_insn_labels ();
16200 s_float_cons (int type)
16202 segment_info_type *si = seg_info (now_seg);
16203 struct insn_label_list *l = si->label_list;
16205 mips_emit_delays ();
16210 mips_align (3, 0, l);
16212 mips_align (2, 0, l);
16216 mips_clear_insn_labels ();
16219 /* Handle .globl. We need to override it because on Irix 5 you are
16222 where foo is an undefined symbol, to mean that foo should be
16223 considered to be the address of a function. */
16226 s_mips_globl (int x ATTRIBUTE_UNUSED)
16235 name = input_line_pointer;
16236 c = get_symbol_end ();
16237 symbolP = symbol_find_or_make (name);
16238 S_SET_EXTERNAL (symbolP);
16240 *input_line_pointer = c;
16241 SKIP_WHITESPACE ();
16243 /* On Irix 5, every global symbol that is not explicitly labelled as
16244 being a function is apparently labelled as being an object. */
16247 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16248 && (*input_line_pointer != ','))
16253 secname = input_line_pointer;
16254 c = get_symbol_end ();
16255 sec = bfd_get_section_by_name (stdoutput, secname);
16257 as_bad (_("%s: no such section"), secname);
16258 *input_line_pointer = c;
16260 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16261 flag = BSF_FUNCTION;
16264 symbol_get_bfdsym (symbolP)->flags |= flag;
16266 c = *input_line_pointer;
16269 input_line_pointer++;
16270 SKIP_WHITESPACE ();
16271 if (is_end_of_line[(unsigned char) *input_line_pointer])
16277 demand_empty_rest_of_line ();
16281 s_option (int x ATTRIBUTE_UNUSED)
16286 opt = input_line_pointer;
16287 c = get_symbol_end ();
16291 /* FIXME: What does this mean? */
16293 else if (strncmp (opt, "pic", 3) == 0)
16297 i = atoi (opt + 3);
16302 mips_pic = SVR4_PIC;
16303 mips_abicalls = TRUE;
16306 as_bad (_(".option pic%d not supported"), i);
16308 if (mips_pic == SVR4_PIC)
16310 if (g_switch_seen && g_switch_value != 0)
16311 as_warn (_("-G may not be used with SVR4 PIC code"));
16312 g_switch_value = 0;
16313 bfd_set_gp_size (stdoutput, 0);
16317 as_warn (_("Unrecognized option \"%s\""), opt);
16319 *input_line_pointer = c;
16320 demand_empty_rest_of_line ();
16323 /* This structure is used to hold a stack of .set values. */
16325 struct mips_option_stack
16327 struct mips_option_stack *next;
16328 struct mips_set_options options;
16331 static struct mips_option_stack *mips_opts_stack;
16333 /* Handle the .set pseudo-op. */
16336 s_mipsset (int x ATTRIBUTE_UNUSED)
16338 char *name = input_line_pointer, ch;
16339 const struct mips_ase *ase;
16341 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16342 ++input_line_pointer;
16343 ch = *input_line_pointer;
16344 *input_line_pointer = '\0';
16346 if (strcmp (name, "reorder") == 0)
16348 if (mips_opts.noreorder)
16351 else if (strcmp (name, "noreorder") == 0)
16353 if (!mips_opts.noreorder)
16354 start_noreorder ();
16356 else if (strncmp (name, "at=", 3) == 0)
16358 char *s = name + 3;
16360 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16361 as_bad (_("Unrecognized register name `%s'"), s);
16363 else if (strcmp (name, "at") == 0)
16365 mips_opts.at = ATREG;
16367 else if (strcmp (name, "noat") == 0)
16369 mips_opts.at = ZERO;
16371 else if (strcmp (name, "macro") == 0)
16373 mips_opts.warn_about_macros = 0;
16375 else if (strcmp (name, "nomacro") == 0)
16377 if (mips_opts.noreorder == 0)
16378 as_bad (_("`noreorder' must be set before `nomacro'"));
16379 mips_opts.warn_about_macros = 1;
16381 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16383 mips_opts.nomove = 0;
16385 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16387 mips_opts.nomove = 1;
16389 else if (strcmp (name, "bopt") == 0)
16391 mips_opts.nobopt = 0;
16393 else if (strcmp (name, "nobopt") == 0)
16395 mips_opts.nobopt = 1;
16397 else if (strcmp (name, "gp=default") == 0)
16398 mips_opts.gp32 = file_mips_gp32;
16399 else if (strcmp (name, "gp=32") == 0)
16400 mips_opts.gp32 = 1;
16401 else if (strcmp (name, "gp=64") == 0)
16403 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16404 as_warn (_("%s isa does not support 64-bit registers"),
16405 mips_cpu_info_from_isa (mips_opts.isa)->name);
16406 mips_opts.gp32 = 0;
16408 else if (strcmp (name, "fp=default") == 0)
16409 mips_opts.fp32 = file_mips_fp32;
16410 else if (strcmp (name, "fp=32") == 0)
16411 mips_opts.fp32 = 1;
16412 else if (strcmp (name, "fp=64") == 0)
16414 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16415 as_warn (_("%s isa does not support 64-bit floating point registers"),
16416 mips_cpu_info_from_isa (mips_opts.isa)->name);
16417 mips_opts.fp32 = 0;
16419 else if (strcmp (name, "softfloat") == 0)
16420 mips_opts.soft_float = 1;
16421 else if (strcmp (name, "hardfloat") == 0)
16422 mips_opts.soft_float = 0;
16423 else if (strcmp (name, "singlefloat") == 0)
16424 mips_opts.single_float = 1;
16425 else if (strcmp (name, "doublefloat") == 0)
16426 mips_opts.single_float = 0;
16427 else if (strcmp (name, "mips16") == 0
16428 || strcmp (name, "MIPS-16") == 0)
16430 if (mips_opts.micromips == 1)
16431 as_fatal (_("`mips16' cannot be used with `micromips'"));
16432 mips_opts.mips16 = 1;
16434 else if (strcmp (name, "nomips16") == 0
16435 || strcmp (name, "noMIPS-16") == 0)
16436 mips_opts.mips16 = 0;
16437 else if (strcmp (name, "micromips") == 0)
16439 if (mips_opts.mips16 == 1)
16440 as_fatal (_("`micromips' cannot be used with `mips16'"));
16441 mips_opts.micromips = 1;
16443 else if (strcmp (name, "nomicromips") == 0)
16444 mips_opts.micromips = 0;
16445 else if (name[0] == 'n'
16447 && (ase = mips_lookup_ase (name + 2)))
16448 mips_set_ase (ase, FALSE);
16449 else if ((ase = mips_lookup_ase (name)))
16450 mips_set_ase (ase, TRUE);
16451 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16455 /* Permit the user to change the ISA and architecture on the fly.
16456 Needless to say, misuse can cause serious problems. */
16457 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16460 mips_opts.isa = file_mips_isa;
16461 mips_opts.arch = file_mips_arch;
16463 else if (strncmp (name, "arch=", 5) == 0)
16465 const struct mips_cpu_info *p;
16467 p = mips_parse_cpu("internal use", name + 5);
16469 as_bad (_("unknown architecture %s"), name + 5);
16472 mips_opts.arch = p->cpu;
16473 mips_opts.isa = p->isa;
16476 else if (strncmp (name, "mips", 4) == 0)
16478 const struct mips_cpu_info *p;
16480 p = mips_parse_cpu("internal use", name);
16482 as_bad (_("unknown ISA level %s"), name + 4);
16485 mips_opts.arch = p->cpu;
16486 mips_opts.isa = p->isa;
16490 as_bad (_("unknown ISA or architecture %s"), name);
16492 switch (mips_opts.isa)
16500 mips_opts.gp32 = 1;
16501 mips_opts.fp32 = 1;
16508 mips_opts.gp32 = 0;
16509 if (mips_opts.arch == CPU_R5900)
16511 mips_opts.fp32 = 1;
16515 mips_opts.fp32 = 0;
16519 as_bad (_("unknown ISA level %s"), name + 4);
16524 mips_opts.gp32 = file_mips_gp32;
16525 mips_opts.fp32 = file_mips_fp32;
16528 else if (strcmp (name, "autoextend") == 0)
16529 mips_opts.noautoextend = 0;
16530 else if (strcmp (name, "noautoextend") == 0)
16531 mips_opts.noautoextend = 1;
16532 else if (strcmp (name, "insn32") == 0)
16533 mips_opts.insn32 = TRUE;
16534 else if (strcmp (name, "noinsn32") == 0)
16535 mips_opts.insn32 = FALSE;
16536 else if (strcmp (name, "push") == 0)
16538 struct mips_option_stack *s;
16540 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16541 s->next = mips_opts_stack;
16542 s->options = mips_opts;
16543 mips_opts_stack = s;
16545 else if (strcmp (name, "pop") == 0)
16547 struct mips_option_stack *s;
16549 s = mips_opts_stack;
16551 as_bad (_(".set pop with no .set push"));
16554 /* If we're changing the reorder mode we need to handle
16555 delay slots correctly. */
16556 if (s->options.noreorder && ! mips_opts.noreorder)
16557 start_noreorder ();
16558 else if (! s->options.noreorder && mips_opts.noreorder)
16561 mips_opts = s->options;
16562 mips_opts_stack = s->next;
16566 else if (strcmp (name, "sym32") == 0)
16567 mips_opts.sym32 = TRUE;
16568 else if (strcmp (name, "nosym32") == 0)
16569 mips_opts.sym32 = FALSE;
16570 else if (strchr (name, ','))
16572 /* Generic ".set" directive; use the generic handler. */
16573 *input_line_pointer = ch;
16574 input_line_pointer = name;
16580 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16582 mips_check_isa_supports_ases ();
16583 *input_line_pointer = ch;
16584 demand_empty_rest_of_line ();
16587 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16588 .option pic2. It means to generate SVR4 PIC calls. */
16591 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16593 mips_pic = SVR4_PIC;
16594 mips_abicalls = TRUE;
16596 if (g_switch_seen && g_switch_value != 0)
16597 as_warn (_("-G may not be used with SVR4 PIC code"));
16598 g_switch_value = 0;
16600 bfd_set_gp_size (stdoutput, 0);
16601 demand_empty_rest_of_line ();
16604 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16605 PIC code. It sets the $gp register for the function based on the
16606 function address, which is in the register named in the argument.
16607 This uses a relocation against _gp_disp, which is handled specially
16608 by the linker. The result is:
16609 lui $gp,%hi(_gp_disp)
16610 addiu $gp,$gp,%lo(_gp_disp)
16611 addu $gp,$gp,.cpload argument
16612 The .cpload argument is normally $25 == $t9.
16614 The -mno-shared option changes this to:
16615 lui $gp,%hi(__gnu_local_gp)
16616 addiu $gp,$gp,%lo(__gnu_local_gp)
16617 and the argument is ignored. This saves an instruction, but the
16618 resulting code is not position independent; it uses an absolute
16619 address for __gnu_local_gp. Thus code assembled with -mno-shared
16620 can go into an ordinary executable, but not into a shared library. */
16623 s_cpload (int ignore ATTRIBUTE_UNUSED)
16629 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16630 .cpload is ignored. */
16631 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16637 if (mips_opts.mips16)
16639 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16640 ignore_rest_of_line ();
16644 /* .cpload should be in a .set noreorder section. */
16645 if (mips_opts.noreorder == 0)
16646 as_warn (_(".cpload not in noreorder section"));
16648 reg = tc_get_register (0);
16650 /* If we need to produce a 64-bit address, we are better off using
16651 the default instruction sequence. */
16652 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16654 ex.X_op = O_symbol;
16655 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16657 ex.X_op_symbol = NULL;
16658 ex.X_add_number = 0;
16660 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16661 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16663 mips_mark_labels ();
16664 mips_assembling_insn = TRUE;
16667 macro_build_lui (&ex, mips_gp_register);
16668 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16669 mips_gp_register, BFD_RELOC_LO16);
16671 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16672 mips_gp_register, reg);
16675 mips_assembling_insn = FALSE;
16676 demand_empty_rest_of_line ();
16679 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16680 .cpsetup $reg1, offset|$reg2, label
16682 If offset is given, this results in:
16683 sd $gp, offset($sp)
16684 lui $gp, %hi(%neg(%gp_rel(label)))
16685 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16686 daddu $gp, $gp, $reg1
16688 If $reg2 is given, this results in:
16689 daddu $reg2, $gp, $0
16690 lui $gp, %hi(%neg(%gp_rel(label)))
16691 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16692 daddu $gp, $gp, $reg1
16693 $reg1 is normally $25 == $t9.
16695 The -mno-shared option replaces the last three instructions with
16697 addiu $gp,$gp,%lo(_gp) */
16700 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16702 expressionS ex_off;
16703 expressionS ex_sym;
16706 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16707 We also need NewABI support. */
16708 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16714 if (mips_opts.mips16)
16716 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16717 ignore_rest_of_line ();
16721 reg1 = tc_get_register (0);
16722 SKIP_WHITESPACE ();
16723 if (*input_line_pointer != ',')
16725 as_bad (_("missing argument separator ',' for .cpsetup"));
16729 ++input_line_pointer;
16730 SKIP_WHITESPACE ();
16731 if (*input_line_pointer == '$')
16733 mips_cpreturn_register = tc_get_register (0);
16734 mips_cpreturn_offset = -1;
16738 mips_cpreturn_offset = get_absolute_expression ();
16739 mips_cpreturn_register = -1;
16741 SKIP_WHITESPACE ();
16742 if (*input_line_pointer != ',')
16744 as_bad (_("missing argument separator ',' for .cpsetup"));
16748 ++input_line_pointer;
16749 SKIP_WHITESPACE ();
16750 expression (&ex_sym);
16752 mips_mark_labels ();
16753 mips_assembling_insn = TRUE;
16756 if (mips_cpreturn_register == -1)
16758 ex_off.X_op = O_constant;
16759 ex_off.X_add_symbol = NULL;
16760 ex_off.X_op_symbol = NULL;
16761 ex_off.X_add_number = mips_cpreturn_offset;
16763 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16764 BFD_RELOC_LO16, SP);
16767 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16768 mips_gp_register, 0);
16770 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16772 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16773 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16776 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16777 mips_gp_register, -1, BFD_RELOC_GPREL16,
16778 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16780 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16781 mips_gp_register, reg1);
16787 ex.X_op = O_symbol;
16788 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16789 ex.X_op_symbol = NULL;
16790 ex.X_add_number = 0;
16792 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16793 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16795 macro_build_lui (&ex, mips_gp_register);
16796 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16797 mips_gp_register, BFD_RELOC_LO16);
16802 mips_assembling_insn = FALSE;
16803 demand_empty_rest_of_line ();
16807 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16809 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16810 .cplocal is ignored. */
16811 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16817 if (mips_opts.mips16)
16819 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16820 ignore_rest_of_line ();
16824 mips_gp_register = tc_get_register (0);
16825 demand_empty_rest_of_line ();
16828 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16829 offset from $sp. The offset is remembered, and after making a PIC
16830 call $gp is restored from that location. */
16833 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16837 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16838 .cprestore is ignored. */
16839 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16845 if (mips_opts.mips16)
16847 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16848 ignore_rest_of_line ();
16852 mips_cprestore_offset = get_absolute_expression ();
16853 mips_cprestore_valid = 1;
16855 ex.X_op = O_constant;
16856 ex.X_add_symbol = NULL;
16857 ex.X_op_symbol = NULL;
16858 ex.X_add_number = mips_cprestore_offset;
16860 mips_mark_labels ();
16861 mips_assembling_insn = TRUE;
16864 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16865 SP, HAVE_64BIT_ADDRESSES);
16868 mips_assembling_insn = FALSE;
16869 demand_empty_rest_of_line ();
16872 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16873 was given in the preceding .cpsetup, it results in:
16874 ld $gp, offset($sp)
16876 If a register $reg2 was given there, it results in:
16877 daddu $gp, $reg2, $0 */
16880 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16884 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16885 We also need NewABI support. */
16886 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16892 if (mips_opts.mips16)
16894 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16895 ignore_rest_of_line ();
16899 mips_mark_labels ();
16900 mips_assembling_insn = TRUE;
16903 if (mips_cpreturn_register == -1)
16905 ex.X_op = O_constant;
16906 ex.X_add_symbol = NULL;
16907 ex.X_op_symbol = NULL;
16908 ex.X_add_number = mips_cpreturn_offset;
16910 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16913 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16914 mips_cpreturn_register, 0);
16917 mips_assembling_insn = FALSE;
16918 demand_empty_rest_of_line ();
16921 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16922 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16923 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16924 debug information or MIPS16 TLS. */
16927 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16928 bfd_reloc_code_real_type rtype)
16935 if (ex.X_op != O_symbol)
16937 as_bad (_("Unsupported use of %s"), dirstr);
16938 ignore_rest_of_line ();
16941 p = frag_more (bytes);
16942 md_number_to_chars (p, 0, bytes);
16943 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16944 demand_empty_rest_of_line ();
16945 mips_clear_insn_labels ();
16948 /* Handle .dtprelword. */
16951 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16953 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16956 /* Handle .dtpreldword. */
16959 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16961 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16964 /* Handle .tprelword. */
16967 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16969 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16972 /* Handle .tpreldword. */
16975 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16977 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16980 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16981 code. It sets the offset to use in gp_rel relocations. */
16984 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16986 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16987 We also need NewABI support. */
16988 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16994 mips_gprel_offset = get_absolute_expression ();
16996 demand_empty_rest_of_line ();
16999 /* Handle the .gpword pseudo-op. This is used when generating PIC
17000 code. It generates a 32 bit GP relative reloc. */
17003 s_gpword (int ignore ATTRIBUTE_UNUSED)
17005 segment_info_type *si;
17006 struct insn_label_list *l;
17010 /* When not generating PIC code, this is treated as .word. */
17011 if (mips_pic != SVR4_PIC)
17017 si = seg_info (now_seg);
17018 l = si->label_list;
17019 mips_emit_delays ();
17021 mips_align (2, 0, l);
17024 mips_clear_insn_labels ();
17026 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17028 as_bad (_("Unsupported use of .gpword"));
17029 ignore_rest_of_line ();
17033 md_number_to_chars (p, 0, 4);
17034 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17035 BFD_RELOC_GPREL32);
17037 demand_empty_rest_of_line ();
17041 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17043 segment_info_type *si;
17044 struct insn_label_list *l;
17048 /* When not generating PIC code, this is treated as .dword. */
17049 if (mips_pic != SVR4_PIC)
17055 si = seg_info (now_seg);
17056 l = si->label_list;
17057 mips_emit_delays ();
17059 mips_align (3, 0, l);
17062 mips_clear_insn_labels ();
17064 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17066 as_bad (_("Unsupported use of .gpdword"));
17067 ignore_rest_of_line ();
17071 md_number_to_chars (p, 0, 8);
17072 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17073 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17075 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17076 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17077 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17079 demand_empty_rest_of_line ();
17082 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17083 tables. It generates a R_MIPS_EH reloc. */
17086 s_ehword (int ignore ATTRIBUTE_UNUSED)
17091 mips_emit_delays ();
17094 mips_clear_insn_labels ();
17096 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17098 as_bad (_("Unsupported use of .ehword"));
17099 ignore_rest_of_line ();
17103 md_number_to_chars (p, 0, 4);
17104 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17105 BFD_RELOC_MIPS_EH);
17107 demand_empty_rest_of_line ();
17110 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17111 tables in SVR4 PIC code. */
17114 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17118 /* This is ignored when not generating SVR4 PIC code. */
17119 if (mips_pic != SVR4_PIC)
17125 mips_mark_labels ();
17126 mips_assembling_insn = TRUE;
17128 /* Add $gp to the register named as an argument. */
17130 reg = tc_get_register (0);
17131 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17134 mips_assembling_insn = FALSE;
17135 demand_empty_rest_of_line ();
17138 /* Handle the .insn pseudo-op. This marks instruction labels in
17139 mips16/micromips mode. This permits the linker to handle them specially,
17140 such as generating jalx instructions when needed. We also make
17141 them odd for the duration of the assembly, in order to generate the
17142 right sort of code. We will make them even in the adjust_symtab
17143 routine, while leaving them marked. This is convenient for the
17144 debugger and the disassembler. The linker knows to make them odd
17148 s_insn (int ignore ATTRIBUTE_UNUSED)
17150 mips_mark_labels ();
17152 demand_empty_rest_of_line ();
17155 /* Handle a .stab[snd] directive. Ideally these directives would be
17156 implemented in a transparent way, so that removing them would not
17157 have any effect on the generated instructions. However, s_stab
17158 internally changes the section, so in practice we need to decide
17159 now whether the preceding label marks compressed code. We do not
17160 support changing the compression mode of a label after a .stab*
17161 directive, such as in:
17167 so the current mode wins. */
17170 s_mips_stab (int type)
17172 mips_mark_labels ();
17176 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17179 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17186 name = input_line_pointer;
17187 c = get_symbol_end ();
17188 symbolP = symbol_find_or_make (name);
17189 S_SET_WEAK (symbolP);
17190 *input_line_pointer = c;
17192 SKIP_WHITESPACE ();
17194 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17196 if (S_IS_DEFINED (symbolP))
17198 as_bad (_("ignoring attempt to redefine symbol %s"),
17199 S_GET_NAME (symbolP));
17200 ignore_rest_of_line ();
17204 if (*input_line_pointer == ',')
17206 ++input_line_pointer;
17207 SKIP_WHITESPACE ();
17211 if (exp.X_op != O_symbol)
17213 as_bad (_("bad .weakext directive"));
17214 ignore_rest_of_line ();
17217 symbol_set_value_expression (symbolP, &exp);
17220 demand_empty_rest_of_line ();
17223 /* Parse a register string into a number. Called from the ECOFF code
17224 to parse .frame. The argument is non-zero if this is the frame
17225 register, so that we can record it in mips_frame_reg. */
17228 tc_get_register (int frame)
17232 SKIP_WHITESPACE ();
17233 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17237 mips_frame_reg = reg != 0 ? reg : SP;
17238 mips_frame_reg_valid = 1;
17239 mips_cprestore_valid = 0;
17245 md_section_align (asection *seg, valueT addr)
17247 int align = bfd_get_section_alignment (stdoutput, seg);
17249 /* We don't need to align ELF sections to the full alignment.
17250 However, Irix 5 may prefer that we align them at least to a 16
17251 byte boundary. We don't bother to align the sections if we
17252 are targeted for an embedded system. */
17253 if (strncmp (TARGET_OS, "elf", 3) == 0)
17258 return ((addr + (1 << align) - 1) & (-1 << align));
17261 /* Utility routine, called from above as well. If called while the
17262 input file is still being read, it's only an approximation. (For
17263 example, a symbol may later become defined which appeared to be
17264 undefined earlier.) */
17267 nopic_need_relax (symbolS *sym, int before_relaxing)
17272 if (g_switch_value > 0)
17274 const char *symname;
17277 /* Find out whether this symbol can be referenced off the $gp
17278 register. It can be if it is smaller than the -G size or if
17279 it is in the .sdata or .sbss section. Certain symbols can
17280 not be referenced off the $gp, although it appears as though
17282 symname = S_GET_NAME (sym);
17283 if (symname != (const char *) NULL
17284 && (strcmp (symname, "eprol") == 0
17285 || strcmp (symname, "etext") == 0
17286 || strcmp (symname, "_gp") == 0
17287 || strcmp (symname, "edata") == 0
17288 || strcmp (symname, "_fbss") == 0
17289 || strcmp (symname, "_fdata") == 0
17290 || strcmp (symname, "_ftext") == 0
17291 || strcmp (symname, "end") == 0
17292 || strcmp (symname, "_gp_disp") == 0))
17294 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17296 #ifndef NO_ECOFF_DEBUGGING
17297 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17298 && (symbol_get_obj (sym)->ecoff_extern_size
17299 <= g_switch_value))
17301 /* We must defer this decision until after the whole
17302 file has been read, since there might be a .extern
17303 after the first use of this symbol. */
17304 || (before_relaxing
17305 #ifndef NO_ECOFF_DEBUGGING
17306 && symbol_get_obj (sym)->ecoff_extern_size == 0
17308 && S_GET_VALUE (sym) == 0)
17309 || (S_GET_VALUE (sym) != 0
17310 && S_GET_VALUE (sym) <= g_switch_value)))
17314 const char *segname;
17316 segname = segment_name (S_GET_SEGMENT (sym));
17317 gas_assert (strcmp (segname, ".lit8") != 0
17318 && strcmp (segname, ".lit4") != 0);
17319 change = (strcmp (segname, ".sdata") != 0
17320 && strcmp (segname, ".sbss") != 0
17321 && strncmp (segname, ".sdata.", 7) != 0
17322 && strncmp (segname, ".sbss.", 6) != 0
17323 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17324 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17329 /* We are not optimizing for the $gp register. */
17334 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17337 pic_need_relax (symbolS *sym, asection *segtype)
17341 /* Handle the case of a symbol equated to another symbol. */
17342 while (symbol_equated_reloc_p (sym))
17346 /* It's possible to get a loop here in a badly written program. */
17347 n = symbol_get_value_expression (sym)->X_add_symbol;
17353 if (symbol_section_p (sym))
17356 symsec = S_GET_SEGMENT (sym);
17358 /* This must duplicate the test in adjust_reloc_syms. */
17359 return (!bfd_is_und_section (symsec)
17360 && !bfd_is_abs_section (symsec)
17361 && !bfd_is_com_section (symsec)
17362 && !s_is_linkonce (sym, segtype)
17363 /* A global or weak symbol is treated as external. */
17364 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17368 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17369 extended opcode. SEC is the section the frag is in. */
17372 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17375 const struct mips16_immed_operand *op;
17377 int mintiny, maxtiny;
17381 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17383 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17386 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17387 op = mips16_immed_operands;
17388 while (op->type != type)
17391 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17396 if (type == '<' || type == '>' || type == '[' || type == ']')
17399 maxtiny = 1 << op->nbits;
17404 maxtiny = (1 << op->nbits) - 1;
17409 mintiny = - (1 << (op->nbits - 1));
17410 maxtiny = (1 << (op->nbits - 1)) - 1;
17413 sym_frag = symbol_get_frag (fragp->fr_symbol);
17414 val = S_GET_VALUE (fragp->fr_symbol);
17415 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17421 /* We won't have the section when we are called from
17422 mips_relax_frag. However, we will always have been called
17423 from md_estimate_size_before_relax first. If this is a
17424 branch to a different section, we mark it as such. If SEC is
17425 NULL, and the frag is not marked, then it must be a branch to
17426 the same section. */
17429 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17434 /* Must have been called from md_estimate_size_before_relax. */
17437 fragp->fr_subtype =
17438 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17440 /* FIXME: We should support this, and let the linker
17441 catch branches and loads that are out of range. */
17442 as_bad_where (fragp->fr_file, fragp->fr_line,
17443 _("unsupported PC relative reference to different section"));
17447 if (fragp != sym_frag && sym_frag->fr_address == 0)
17448 /* Assume non-extended on the first relaxation pass.
17449 The address we have calculated will be bogus if this is
17450 a forward branch to another frag, as the forward frag
17451 will have fr_address == 0. */
17455 /* In this case, we know for sure that the symbol fragment is in
17456 the same section. If the relax_marker of the symbol fragment
17457 differs from the relax_marker of this fragment, we have not
17458 yet adjusted the symbol fragment fr_address. We want to add
17459 in STRETCH in order to get a better estimate of the address.
17460 This particularly matters because of the shift bits. */
17462 && sym_frag->relax_marker != fragp->relax_marker)
17466 /* Adjust stretch for any alignment frag. Note that if have
17467 been expanding the earlier code, the symbol may be
17468 defined in what appears to be an earlier frag. FIXME:
17469 This doesn't handle the fr_subtype field, which specifies
17470 a maximum number of bytes to skip when doing an
17472 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17474 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17477 stretch = - ((- stretch)
17478 & ~ ((1 << (int) f->fr_offset) - 1));
17480 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17489 addr = fragp->fr_address + fragp->fr_fix;
17491 /* The base address rules are complicated. The base address of
17492 a branch is the following instruction. The base address of a
17493 PC relative load or add is the instruction itself, but if it
17494 is in a delay slot (in which case it can not be extended) use
17495 the address of the instruction whose delay slot it is in. */
17496 if (type == 'p' || type == 'q')
17500 /* If we are currently assuming that this frag should be
17501 extended, then, the current address is two bytes
17503 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17506 /* Ignore the low bit in the target, since it will be set
17507 for a text label. */
17508 if ((val & 1) != 0)
17511 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17513 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17516 val -= addr & ~ ((1 << op->shift) - 1);
17518 /* Branch offsets have an implicit 0 in the lowest bit. */
17519 if (type == 'p' || type == 'q')
17522 /* If any of the shifted bits are set, we must use an extended
17523 opcode. If the address depends on the size of this
17524 instruction, this can lead to a loop, so we arrange to always
17525 use an extended opcode. We only check this when we are in
17526 the main relaxation loop, when SEC is NULL. */
17527 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17529 fragp->fr_subtype =
17530 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17534 /* If we are about to mark a frag as extended because the value
17535 is precisely maxtiny + 1, then there is a chance of an
17536 infinite loop as in the following code:
17541 In this case when the la is extended, foo is 0x3fc bytes
17542 away, so the la can be shrunk, but then foo is 0x400 away, so
17543 the la must be extended. To avoid this loop, we mark the
17544 frag as extended if it was small, and is about to become
17545 extended with a value of maxtiny + 1. */
17546 if (val == ((maxtiny + 1) << op->shift)
17547 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17550 fragp->fr_subtype =
17551 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17555 else if (symsec != absolute_section && sec != NULL)
17556 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17558 if ((val & ((1 << op->shift) - 1)) != 0
17559 || val < (mintiny << op->shift)
17560 || val > (maxtiny << op->shift))
17566 /* Compute the length of a branch sequence, and adjust the
17567 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17568 worst-case length is computed, with UPDATE being used to indicate
17569 whether an unconditional (-1), branch-likely (+1) or regular (0)
17570 branch is to be computed. */
17572 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17574 bfd_boolean toofar;
17578 && S_IS_DEFINED (fragp->fr_symbol)
17579 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17584 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17586 addr = fragp->fr_address + fragp->fr_fix + 4;
17590 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17593 /* If the symbol is not defined or it's in a different segment,
17594 assume the user knows what's going on and emit a short
17600 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17602 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17603 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17604 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17605 RELAX_BRANCH_LINK (fragp->fr_subtype),
17611 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17614 if (mips_pic != NO_PIC)
17616 /* Additional space for PIC loading of target address. */
17618 if (mips_opts.isa == ISA_MIPS1)
17619 /* Additional space for $at-stabilizing nop. */
17623 /* If branch is conditional. */
17624 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17631 /* Compute the length of a branch sequence, and adjust the
17632 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17633 worst-case length is computed, with UPDATE being used to indicate
17634 whether an unconditional (-1), or regular (0) branch is to be
17638 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17640 bfd_boolean toofar;
17644 && S_IS_DEFINED (fragp->fr_symbol)
17645 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17650 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17651 /* Ignore the low bit in the target, since it will be set
17652 for a text label. */
17653 if ((val & 1) != 0)
17656 addr = fragp->fr_address + fragp->fr_fix + 4;
17660 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17663 /* If the symbol is not defined or it's in a different segment,
17664 assume the user knows what's going on and emit a short
17670 if (fragp && update
17671 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17672 fragp->fr_subtype = (toofar
17673 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17674 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17679 bfd_boolean compact_known = fragp != NULL;
17680 bfd_boolean compact = FALSE;
17681 bfd_boolean uncond;
17684 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17686 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17688 uncond = update < 0;
17690 /* If label is out of range, we turn branch <br>:
17692 <br> label # 4 bytes
17698 nop # 2 bytes if compact && !PIC
17701 if (mips_pic == NO_PIC && (!compact_known || compact))
17704 /* If assembling PIC code, we further turn:
17710 lw/ld at, %got(label)(gp) # 4 bytes
17711 d/addiu at, %lo(label) # 4 bytes
17714 if (mips_pic != NO_PIC)
17717 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17719 <brneg> 0f # 4 bytes
17720 nop # 2 bytes if !compact
17723 length += (compact_known && compact) ? 4 : 6;
17729 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17730 bit accordingly. */
17733 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17735 bfd_boolean toofar;
17738 && S_IS_DEFINED (fragp->fr_symbol)
17739 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17745 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17746 /* Ignore the low bit in the target, since it will be set
17747 for a text label. */
17748 if ((val & 1) != 0)
17751 /* Assume this is a 2-byte branch. */
17752 addr = fragp->fr_address + fragp->fr_fix + 2;
17754 /* We try to avoid the infinite loop by not adding 2 more bytes for
17759 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17761 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17762 else if (type == 'E')
17763 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17768 /* If the symbol is not defined or it's in a different segment,
17769 we emit a normal 32-bit branch. */
17772 if (fragp && update
17773 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17775 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17776 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17784 /* Estimate the size of a frag before relaxing. Unless this is the
17785 mips16, we are not really relaxing here, and the final size is
17786 encoded in the subtype information. For the mips16, we have to
17787 decide whether we are using an extended opcode or not. */
17790 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17794 if (RELAX_BRANCH_P (fragp->fr_subtype))
17797 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17799 return fragp->fr_var;
17802 if (RELAX_MIPS16_P (fragp->fr_subtype))
17803 /* We don't want to modify the EXTENDED bit here; it might get us
17804 into infinite loops. We change it only in mips_relax_frag(). */
17805 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17807 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17811 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17812 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17813 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17814 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17815 fragp->fr_var = length;
17820 if (mips_pic == NO_PIC)
17821 change = nopic_need_relax (fragp->fr_symbol, 0);
17822 else if (mips_pic == SVR4_PIC)
17823 change = pic_need_relax (fragp->fr_symbol, segtype);
17824 else if (mips_pic == VXWORKS_PIC)
17825 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17832 fragp->fr_subtype |= RELAX_USE_SECOND;
17833 return -RELAX_FIRST (fragp->fr_subtype);
17836 return -RELAX_SECOND (fragp->fr_subtype);
17839 /* This is called to see whether a reloc against a defined symbol
17840 should be converted into a reloc against a section. */
17843 mips_fix_adjustable (fixS *fixp)
17845 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17846 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17849 if (fixp->fx_addsy == NULL)
17852 /* If symbol SYM is in a mergeable section, relocations of the form
17853 SYM + 0 can usually be made section-relative. The mergeable data
17854 is then identified by the section offset rather than by the symbol.
17856 However, if we're generating REL LO16 relocations, the offset is split
17857 between the LO16 and parterning high part relocation. The linker will
17858 need to recalculate the complete offset in order to correctly identify
17861 The linker has traditionally not looked for the parterning high part
17862 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17863 placed anywhere. Rather than break backwards compatibility by changing
17864 this, it seems better not to force the issue, and instead keep the
17865 original symbol. This will work with either linker behavior. */
17866 if ((lo16_reloc_p (fixp->fx_r_type)
17867 || reloc_needs_lo_p (fixp->fx_r_type))
17868 && HAVE_IN_PLACE_ADDENDS
17869 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17872 /* There is no place to store an in-place offset for JALR relocations.
17873 Likewise an in-range offset of limited PC-relative relocations may
17874 overflow the in-place relocatable field if recalculated against the
17875 start address of the symbol's containing section. */
17876 if (HAVE_IN_PLACE_ADDENDS
17877 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17878 || jalr_reloc_p (fixp->fx_r_type)))
17881 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17882 to a floating-point stub. The same is true for non-R_MIPS16_26
17883 relocations against MIPS16 functions; in this case, the stub becomes
17884 the function's canonical address.
17886 Floating-point stubs are stored in unique .mips16.call.* or
17887 .mips16.fn.* sections. If a stub T for function F is in section S,
17888 the first relocation in section S must be against F; this is how the
17889 linker determines the target function. All relocations that might
17890 resolve to T must also be against F. We therefore have the following
17891 restrictions, which are given in an intentionally-redundant way:
17893 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17896 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17897 if that stub might be used.
17899 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17902 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17903 that stub might be used.
17905 There is a further restriction:
17907 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17908 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17909 targets with in-place addends; the relocation field cannot
17910 encode the low bit.
17912 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17913 against a MIPS16 symbol. We deal with (5) by by not reducing any
17914 such relocations on REL targets.
17916 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17917 relocation against some symbol R, no relocation against R may be
17918 reduced. (Note that this deals with (2) as well as (1) because
17919 relocations against global symbols will never be reduced on ELF
17920 targets.) This approach is a little simpler than trying to detect
17921 stub sections, and gives the "all or nothing" per-symbol consistency
17922 that we have for MIPS16 symbols. */
17923 if (fixp->fx_subsy == NULL
17924 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17925 || *symbol_get_tc (fixp->fx_addsy)
17926 || (HAVE_IN_PLACE_ADDENDS
17927 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17928 && jmp_reloc_p (fixp->fx_r_type))))
17934 /* Translate internal representation of relocation info to BFD target
17938 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17940 static arelent *retval[4];
17942 bfd_reloc_code_real_type code;
17944 memset (retval, 0, sizeof(retval));
17945 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17946 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17947 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17948 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17950 if (fixp->fx_pcrel)
17952 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17953 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17954 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17955 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17956 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
17958 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17959 Relocations want only the symbol offset. */
17960 reloc->addend = fixp->fx_addnumber + reloc->address;
17963 reloc->addend = fixp->fx_addnumber;
17965 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17966 entry to be used in the relocation's section offset. */
17967 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17969 reloc->address = reloc->addend;
17973 code = fixp->fx_r_type;
17975 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17976 if (reloc->howto == NULL)
17978 as_bad_where (fixp->fx_file, fixp->fx_line,
17979 _("Can not represent %s relocation in this object file format"),
17980 bfd_get_reloc_code_name (code));
17987 /* Relax a machine dependent frag. This returns the amount by which
17988 the current size of the frag should change. */
17991 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17993 if (RELAX_BRANCH_P (fragp->fr_subtype))
17995 offsetT old_var = fragp->fr_var;
17997 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17999 return fragp->fr_var - old_var;
18002 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18004 offsetT old_var = fragp->fr_var;
18005 offsetT new_var = 4;
18007 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18008 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18009 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18010 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18011 fragp->fr_var = new_var;
18013 return new_var - old_var;
18016 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18019 if (mips16_extended_frag (fragp, NULL, stretch))
18021 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18023 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18028 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18030 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18037 /* Convert a machine dependent frag. */
18040 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18042 if (RELAX_BRANCH_P (fragp->fr_subtype))
18045 unsigned long insn;
18049 buf = fragp->fr_literal + fragp->fr_fix;
18050 insn = read_insn (buf);
18052 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18054 /* We generate a fixup instead of applying it right now
18055 because, if there are linker relaxations, we're going to
18056 need the relocations. */
18057 exp.X_op = O_symbol;
18058 exp.X_add_symbol = fragp->fr_symbol;
18059 exp.X_add_number = fragp->fr_offset;
18061 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18062 BFD_RELOC_16_PCREL_S2);
18063 fixp->fx_file = fragp->fr_file;
18064 fixp->fx_line = fragp->fr_line;
18066 buf = write_insn (buf, insn);
18072 as_warn_where (fragp->fr_file, fragp->fr_line,
18073 _("Relaxed out-of-range branch into a jump"));
18075 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18078 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18080 /* Reverse the branch. */
18081 switch ((insn >> 28) & 0xf)
18084 /* bc[0-3][tf]l? instructions can have the condition
18085 reversed by tweaking a single TF bit, and their
18086 opcodes all have 0x4???????. */
18087 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18088 insn ^= 0x00010000;
18092 /* bltz 0x04000000 bgez 0x04010000
18093 bltzal 0x04100000 bgezal 0x04110000 */
18094 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18095 insn ^= 0x00010000;
18099 /* beq 0x10000000 bne 0x14000000
18100 blez 0x18000000 bgtz 0x1c000000 */
18101 insn ^= 0x04000000;
18109 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18111 /* Clear the and-link bit. */
18112 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18114 /* bltzal 0x04100000 bgezal 0x04110000
18115 bltzall 0x04120000 bgezall 0x04130000 */
18116 insn &= ~0x00100000;
18119 /* Branch over the branch (if the branch was likely) or the
18120 full jump (not likely case). Compute the offset from the
18121 current instruction to branch to. */
18122 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18126 /* How many bytes in instructions we've already emitted? */
18127 i = buf - fragp->fr_literal - fragp->fr_fix;
18128 /* How many bytes in instructions from here to the end? */
18129 i = fragp->fr_var - i;
18131 /* Convert to instruction count. */
18133 /* Branch counts from the next instruction. */
18136 /* Branch over the jump. */
18137 buf = write_insn (buf, insn);
18140 buf = write_insn (buf, 0);
18142 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18144 /* beql $0, $0, 2f */
18146 /* Compute the PC offset from the current instruction to
18147 the end of the variable frag. */
18148 /* How many bytes in instructions we've already emitted? */
18149 i = buf - fragp->fr_literal - fragp->fr_fix;
18150 /* How many bytes in instructions from here to the end? */
18151 i = fragp->fr_var - i;
18152 /* Convert to instruction count. */
18154 /* Don't decrement i, because we want to branch over the
18158 buf = write_insn (buf, insn);
18159 buf = write_insn (buf, 0);
18163 if (mips_pic == NO_PIC)
18166 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18167 ? 0x0c000000 : 0x08000000);
18168 exp.X_op = O_symbol;
18169 exp.X_add_symbol = fragp->fr_symbol;
18170 exp.X_add_number = fragp->fr_offset;
18172 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18173 FALSE, BFD_RELOC_MIPS_JMP);
18174 fixp->fx_file = fragp->fr_file;
18175 fixp->fx_line = fragp->fr_line;
18177 buf = write_insn (buf, insn);
18181 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18183 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18184 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18185 insn |= at << OP_SH_RT;
18186 exp.X_op = O_symbol;
18187 exp.X_add_symbol = fragp->fr_symbol;
18188 exp.X_add_number = fragp->fr_offset;
18190 if (fragp->fr_offset)
18192 exp.X_add_symbol = make_expr_symbol (&exp);
18193 exp.X_add_number = 0;
18196 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18197 FALSE, BFD_RELOC_MIPS_GOT16);
18198 fixp->fx_file = fragp->fr_file;
18199 fixp->fx_line = fragp->fr_line;
18201 buf = write_insn (buf, insn);
18203 if (mips_opts.isa == ISA_MIPS1)
18205 buf = write_insn (buf, 0);
18207 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18208 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18209 insn |= at << OP_SH_RS | at << OP_SH_RT;
18211 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18212 FALSE, BFD_RELOC_LO16);
18213 fixp->fx_file = fragp->fr_file;
18214 fixp->fx_line = fragp->fr_line;
18216 buf = write_insn (buf, insn);
18219 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18223 insn |= at << OP_SH_RS;
18225 buf = write_insn (buf, insn);
18229 fragp->fr_fix += fragp->fr_var;
18230 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18234 /* Relax microMIPS branches. */
18235 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18237 char *buf = fragp->fr_literal + fragp->fr_fix;
18238 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18239 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18240 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18241 bfd_boolean short_ds;
18242 unsigned long insn;
18246 exp.X_op = O_symbol;
18247 exp.X_add_symbol = fragp->fr_symbol;
18248 exp.X_add_number = fragp->fr_offset;
18250 fragp->fr_fix += fragp->fr_var;
18252 /* Handle 16-bit branches that fit or are forced to fit. */
18253 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18255 /* We generate a fixup instead of applying it right now,
18256 because if there is linker relaxation, we're going to
18257 need the relocations. */
18259 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18260 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18261 else if (type == 'E')
18262 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18263 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18267 fixp->fx_file = fragp->fr_file;
18268 fixp->fx_line = fragp->fr_line;
18270 /* These relocations can have an addend that won't fit in
18272 fixp->fx_no_overflow = 1;
18277 /* Handle 32-bit branches that fit or are forced to fit. */
18278 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18279 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18281 /* We generate a fixup instead of applying it right now,
18282 because if there is linker relaxation, we're going to
18283 need the relocations. */
18284 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18285 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18286 fixp->fx_file = fragp->fr_file;
18287 fixp->fx_line = fragp->fr_line;
18293 /* Relax 16-bit branches to 32-bit branches. */
18296 insn = read_compressed_insn (buf, 2);
18298 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18299 insn = 0x94000000; /* beq */
18300 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18302 unsigned long regno;
18304 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18305 regno = micromips_to_32_reg_d_map [regno];
18306 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18307 insn |= regno << MICROMIPSOP_SH_RS;
18312 /* Nothing else to do, just write it out. */
18313 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18314 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18316 buf = write_compressed_insn (buf, insn, 4);
18317 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18322 insn = read_compressed_insn (buf, 4);
18324 /* Relax 32-bit branches to a sequence of instructions. */
18325 as_warn_where (fragp->fr_file, fragp->fr_line,
18326 _("Relaxed out-of-range branch into a jump"));
18328 /* Set the short-delay-slot bit. */
18329 short_ds = al && (insn & 0x02000000) != 0;
18331 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18335 /* Reverse the branch. */
18336 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18337 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18338 insn ^= 0x20000000;
18339 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18340 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18341 || (insn & 0xffe00000) == 0x40800000 /* blez */
18342 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18343 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18344 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18345 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18346 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18347 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18348 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18349 insn ^= 0x00400000;
18350 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18351 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18352 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18353 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18354 insn ^= 0x00200000;
18360 /* Clear the and-link and short-delay-slot bits. */
18361 gas_assert ((insn & 0xfda00000) == 0x40200000);
18363 /* bltzal 0x40200000 bgezal 0x40600000 */
18364 /* bltzals 0x42200000 bgezals 0x42600000 */
18365 insn &= ~0x02200000;
18368 /* Make a label at the end for use with the branch. */
18369 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18370 micromips_label_inc ();
18371 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18374 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18375 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18376 fixp->fx_file = fragp->fr_file;
18377 fixp->fx_line = fragp->fr_line;
18379 /* Branch over the jump. */
18380 buf = write_compressed_insn (buf, insn, 4);
18383 buf = write_compressed_insn (buf, 0x0c00, 2);
18386 if (mips_pic == NO_PIC)
18388 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18390 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18391 insn = al ? jal : 0xd4000000;
18393 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18394 BFD_RELOC_MICROMIPS_JMP);
18395 fixp->fx_file = fragp->fr_file;
18396 fixp->fx_line = fragp->fr_line;
18398 buf = write_compressed_insn (buf, insn, 4);
18401 buf = write_compressed_insn (buf, 0x0c00, 2);
18405 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18406 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18407 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18409 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18410 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18411 insn |= at << MICROMIPSOP_SH_RT;
18413 if (exp.X_add_number)
18415 exp.X_add_symbol = make_expr_symbol (&exp);
18416 exp.X_add_number = 0;
18419 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18420 BFD_RELOC_MICROMIPS_GOT16);
18421 fixp->fx_file = fragp->fr_file;
18422 fixp->fx_line = fragp->fr_line;
18424 buf = write_compressed_insn (buf, insn, 4);
18426 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18427 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18428 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18430 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18431 BFD_RELOC_MICROMIPS_LO16);
18432 fixp->fx_file = fragp->fr_file;
18433 fixp->fx_line = fragp->fr_line;
18435 buf = write_compressed_insn (buf, insn, 4);
18437 /* jr/jrc/jalr/jalrs $at */
18438 insn = al ? jalr : jr;
18439 insn |= at << MICROMIPSOP_SH_MJ;
18441 buf = write_compressed_insn (buf, insn, 2);
18444 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18448 if (RELAX_MIPS16_P (fragp->fr_subtype))
18451 const struct mips16_immed_operand *op;
18454 unsigned int user_length, length;
18455 unsigned long insn;
18458 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18459 op = mips16_immed_operands;
18460 while (op->type != type)
18463 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18464 val = resolve_symbol_value (fragp->fr_symbol);
18469 addr = fragp->fr_address + fragp->fr_fix;
18471 /* The rules for the base address of a PC relative reloc are
18472 complicated; see mips16_extended_frag. */
18473 if (type == 'p' || type == 'q')
18478 /* Ignore the low bit in the target, since it will be
18479 set for a text label. */
18480 if ((val & 1) != 0)
18483 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18485 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18488 addr &= ~ (addressT) ((1 << op->shift) - 1);
18491 /* Make sure the section winds up with the alignment we have
18494 record_alignment (asec, op->shift);
18498 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18499 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18500 as_warn_where (fragp->fr_file, fragp->fr_line,
18501 _("extended instruction in delay slot"));
18503 buf = fragp->fr_literal + fragp->fr_fix;
18505 insn = read_compressed_insn (buf, 2);
18507 insn |= MIPS16_EXTEND;
18509 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18511 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18516 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18517 BFD_RELOC_UNUSED, val, user_length, &insn);
18519 length = (ext ? 4 : 2);
18520 gas_assert (mips16_opcode_length (insn) == length);
18521 write_compressed_insn (buf, insn, length);
18522 fragp->fr_fix += length;
18526 relax_substateT subtype = fragp->fr_subtype;
18527 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18528 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18532 first = RELAX_FIRST (subtype);
18533 second = RELAX_SECOND (subtype);
18534 fixp = (fixS *) fragp->fr_opcode;
18536 /* If the delay slot chosen does not match the size of the instruction,
18537 then emit a warning. */
18538 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18539 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18544 s = subtype & (RELAX_DELAY_SLOT_16BIT
18545 | RELAX_DELAY_SLOT_SIZE_FIRST
18546 | RELAX_DELAY_SLOT_SIZE_SECOND);
18547 msg = macro_warning (s);
18549 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18553 /* Possibly emit a warning if we've chosen the longer option. */
18554 if (use_second == second_longer)
18560 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18561 msg = macro_warning (s);
18563 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18567 /* Go through all the fixups for the first sequence. Disable them
18568 (by marking them as done) if we're going to use the second
18569 sequence instead. */
18571 && fixp->fx_frag == fragp
18572 && fixp->fx_where < fragp->fr_fix - second)
18574 if (subtype & RELAX_USE_SECOND)
18576 fixp = fixp->fx_next;
18579 /* Go through the fixups for the second sequence. Disable them if
18580 we're going to use the first sequence, otherwise adjust their
18581 addresses to account for the relaxation. */
18582 while (fixp && fixp->fx_frag == fragp)
18584 if (subtype & RELAX_USE_SECOND)
18585 fixp->fx_where -= first;
18588 fixp = fixp->fx_next;
18591 /* Now modify the frag contents. */
18592 if (subtype & RELAX_USE_SECOND)
18596 start = fragp->fr_literal + fragp->fr_fix - first - second;
18597 memmove (start, start + first, second);
18598 fragp->fr_fix -= first;
18601 fragp->fr_fix -= second;
18605 /* This function is called after the relocs have been generated.
18606 We've been storing mips16 text labels as odd. Here we convert them
18607 back to even for the convenience of the debugger. */
18610 mips_frob_file_after_relocs (void)
18613 unsigned int count, i;
18615 syms = bfd_get_outsymbols (stdoutput);
18616 count = bfd_get_symcount (stdoutput);
18617 for (i = 0; i < count; i++, syms++)
18618 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18619 && ((*syms)->value & 1) != 0)
18621 (*syms)->value &= ~1;
18622 /* If the symbol has an odd size, it was probably computed
18623 incorrectly, so adjust that as well. */
18624 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18625 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18629 /* This function is called whenever a label is defined, including fake
18630 labels instantiated off the dot special symbol. It is used when
18631 handling branch delays; if a branch has a label, we assume we cannot
18632 move it. This also bumps the value of the symbol by 1 in compressed
18636 mips_record_label (symbolS *sym)
18638 segment_info_type *si = seg_info (now_seg);
18639 struct insn_label_list *l;
18641 if (free_insn_labels == NULL)
18642 l = (struct insn_label_list *) xmalloc (sizeof *l);
18645 l = free_insn_labels;
18646 free_insn_labels = l->next;
18650 l->next = si->label_list;
18651 si->label_list = l;
18654 /* This function is called as tc_frob_label() whenever a label is defined
18655 and adds a DWARF-2 record we only want for true labels. */
18658 mips_define_label (symbolS *sym)
18660 mips_record_label (sym);
18661 dwarf2_emit_label (sym);
18664 /* This function is called by tc_new_dot_label whenever a new dot symbol
18668 mips_add_dot_label (symbolS *sym)
18670 mips_record_label (sym);
18671 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18672 mips_compressed_mark_label (sym);
18675 /* Some special processing for a MIPS ELF file. */
18678 mips_elf_final_processing (void)
18680 /* Write out the register information. */
18681 if (mips_abi != N64_ABI)
18685 s.ri_gprmask = mips_gprmask;
18686 s.ri_cprmask[0] = mips_cprmask[0];
18687 s.ri_cprmask[1] = mips_cprmask[1];
18688 s.ri_cprmask[2] = mips_cprmask[2];
18689 s.ri_cprmask[3] = mips_cprmask[3];
18690 /* The gp_value field is set by the MIPS ELF backend. */
18692 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18693 ((Elf32_External_RegInfo *)
18694 mips_regmask_frag));
18698 Elf64_Internal_RegInfo s;
18700 s.ri_gprmask = mips_gprmask;
18702 s.ri_cprmask[0] = mips_cprmask[0];
18703 s.ri_cprmask[1] = mips_cprmask[1];
18704 s.ri_cprmask[2] = mips_cprmask[2];
18705 s.ri_cprmask[3] = mips_cprmask[3];
18706 /* The gp_value field is set by the MIPS ELF backend. */
18708 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18709 ((Elf64_External_RegInfo *)
18710 mips_regmask_frag));
18713 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18714 sort of BFD interface for this. */
18715 if (mips_any_noreorder)
18716 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18717 if (mips_pic != NO_PIC)
18719 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18720 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18723 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18725 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18726 defined at present; this might need to change in future. */
18727 if (file_ase_mips16)
18728 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18729 if (file_ase_micromips)
18730 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18731 if (file_ase & ASE_MDMX)
18732 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18734 /* Set the MIPS ELF ABI flags. */
18735 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18736 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18737 else if (mips_abi == O64_ABI)
18738 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18739 else if (mips_abi == EABI_ABI)
18741 if (!file_mips_gp32)
18742 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18744 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18746 else if (mips_abi == N32_ABI)
18747 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18749 /* Nothing to do for N64_ABI. */
18751 if (mips_32bitmode)
18752 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18754 #if 0 /* XXX FIXME */
18755 /* 32 bit code with 64 bit FP registers. */
18756 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18757 elf_elfheader (stdoutput)->e_flags |= ???;
18761 typedef struct proc {
18763 symbolS *func_end_sym;
18764 unsigned long reg_mask;
18765 unsigned long reg_offset;
18766 unsigned long fpreg_mask;
18767 unsigned long fpreg_offset;
18768 unsigned long frame_offset;
18769 unsigned long frame_reg;
18770 unsigned long pc_reg;
18773 static procS cur_proc;
18774 static procS *cur_proc_ptr;
18775 static int numprocs;
18777 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18778 as "2", and a normal nop as "0". */
18780 #define NOP_OPCODE_MIPS 0
18781 #define NOP_OPCODE_MIPS16 1
18782 #define NOP_OPCODE_MICROMIPS 2
18785 mips_nop_opcode (void)
18787 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18788 return NOP_OPCODE_MICROMIPS;
18789 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18790 return NOP_OPCODE_MIPS16;
18792 return NOP_OPCODE_MIPS;
18795 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18796 32-bit microMIPS NOPs here (if applicable). */
18799 mips_handle_align (fragS *fragp)
18803 int bytes, size, excess;
18806 if (fragp->fr_type != rs_align_code)
18809 p = fragp->fr_literal + fragp->fr_fix;
18811 switch (nop_opcode)
18813 case NOP_OPCODE_MICROMIPS:
18814 opcode = micromips_nop32_insn.insn_opcode;
18817 case NOP_OPCODE_MIPS16:
18818 opcode = mips16_nop_insn.insn_opcode;
18821 case NOP_OPCODE_MIPS:
18823 opcode = nop_insn.insn_opcode;
18828 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18829 excess = bytes % size;
18831 /* Handle the leading part if we're not inserting a whole number of
18832 instructions, and make it the end of the fixed part of the frag.
18833 Try to fit in a short microMIPS NOP if applicable and possible,
18834 and use zeroes otherwise. */
18835 gas_assert (excess < 4);
18836 fragp->fr_fix += excess;
18841 /* Fall through. */
18843 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18845 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18849 /* Fall through. */
18852 /* Fall through. */
18857 md_number_to_chars (p, opcode, size);
18858 fragp->fr_var = size;
18862 md_obj_begin (void)
18869 /* Check for premature end, nesting errors, etc. */
18871 as_warn (_("missing .end at end of assembly"));
18880 if (*input_line_pointer == '-')
18882 ++input_line_pointer;
18885 if (!ISDIGIT (*input_line_pointer))
18886 as_bad (_("expected simple number"));
18887 if (input_line_pointer[0] == '0')
18889 if (input_line_pointer[1] == 'x')
18891 input_line_pointer += 2;
18892 while (ISXDIGIT (*input_line_pointer))
18895 val |= hex_value (*input_line_pointer++);
18897 return negative ? -val : val;
18901 ++input_line_pointer;
18902 while (ISDIGIT (*input_line_pointer))
18905 val |= *input_line_pointer++ - '0';
18907 return negative ? -val : val;
18910 if (!ISDIGIT (*input_line_pointer))
18912 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18913 *input_line_pointer, *input_line_pointer);
18914 as_warn (_("invalid number"));
18917 while (ISDIGIT (*input_line_pointer))
18920 val += *input_line_pointer++ - '0';
18922 return negative ? -val : val;
18925 /* The .file directive; just like the usual .file directive, but there
18926 is an initial number which is the ECOFF file index. In the non-ECOFF
18927 case .file implies DWARF-2. */
18930 s_mips_file (int x ATTRIBUTE_UNUSED)
18932 static int first_file_directive = 0;
18934 if (ECOFF_DEBUGGING)
18943 filename = dwarf2_directive_file (0);
18945 /* Versions of GCC up to 3.1 start files with a ".file"
18946 directive even for stabs output. Make sure that this
18947 ".file" is handled. Note that you need a version of GCC
18948 after 3.1 in order to support DWARF-2 on MIPS. */
18949 if (filename != NULL && ! first_file_directive)
18951 (void) new_logical_line (filename, -1);
18952 s_app_file_string (filename, 0);
18954 first_file_directive = 1;
18958 /* The .loc directive, implying DWARF-2. */
18961 s_mips_loc (int x ATTRIBUTE_UNUSED)
18963 if (!ECOFF_DEBUGGING)
18964 dwarf2_directive_loc (0);
18967 /* The .end directive. */
18970 s_mips_end (int x ATTRIBUTE_UNUSED)
18974 /* Following functions need their own .frame and .cprestore directives. */
18975 mips_frame_reg_valid = 0;
18976 mips_cprestore_valid = 0;
18978 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18981 demand_empty_rest_of_line ();
18986 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18987 as_warn (_(".end not in text section"));
18991 as_warn (_(".end directive without a preceding .ent directive."));
18992 demand_empty_rest_of_line ();
18998 gas_assert (S_GET_NAME (p));
18999 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19000 as_warn (_(".end symbol does not match .ent symbol."));
19002 if (debug_type == DEBUG_STABS)
19003 stabs_generate_asm_endfunc (S_GET_NAME (p),
19007 as_warn (_(".end directive missing or unknown symbol"));
19009 /* Create an expression to calculate the size of the function. */
19010 if (p && cur_proc_ptr)
19012 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19013 expressionS *exp = xmalloc (sizeof (expressionS));
19016 exp->X_op = O_subtract;
19017 exp->X_add_symbol = symbol_temp_new_now ();
19018 exp->X_op_symbol = p;
19019 exp->X_add_number = 0;
19021 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19024 /* Generate a .pdr section. */
19025 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19027 segT saved_seg = now_seg;
19028 subsegT saved_subseg = now_subseg;
19032 #ifdef md_flush_pending_output
19033 md_flush_pending_output ();
19036 gas_assert (pdr_seg);
19037 subseg_set (pdr_seg, 0);
19039 /* Write the symbol. */
19040 exp.X_op = O_symbol;
19041 exp.X_add_symbol = p;
19042 exp.X_add_number = 0;
19043 emit_expr (&exp, 4);
19045 fragp = frag_more (7 * 4);
19047 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19048 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19049 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19050 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19051 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19052 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19053 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19055 subseg_set (saved_seg, saved_subseg);
19058 cur_proc_ptr = NULL;
19061 /* The .aent and .ent directives. */
19064 s_mips_ent (int aent)
19068 symbolP = get_symbol ();
19069 if (*input_line_pointer == ',')
19070 ++input_line_pointer;
19071 SKIP_WHITESPACE ();
19072 if (ISDIGIT (*input_line_pointer)
19073 || *input_line_pointer == '-')
19076 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19077 as_warn (_(".ent or .aent not in text section."));
19079 if (!aent && cur_proc_ptr)
19080 as_warn (_("missing .end"));
19084 /* This function needs its own .frame and .cprestore directives. */
19085 mips_frame_reg_valid = 0;
19086 mips_cprestore_valid = 0;
19088 cur_proc_ptr = &cur_proc;
19089 memset (cur_proc_ptr, '\0', sizeof (procS));
19091 cur_proc_ptr->func_sym = symbolP;
19095 if (debug_type == DEBUG_STABS)
19096 stabs_generate_asm_func (S_GET_NAME (symbolP),
19097 S_GET_NAME (symbolP));
19100 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19102 demand_empty_rest_of_line ();
19105 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19106 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19107 s_mips_frame is used so that we can set the PDR information correctly.
19108 We can't use the ecoff routines because they make reference to the ecoff
19109 symbol table (in the mdebug section). */
19112 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19114 if (ECOFF_DEBUGGING)
19120 if (cur_proc_ptr == (procS *) NULL)
19122 as_warn (_(".frame outside of .ent"));
19123 demand_empty_rest_of_line ();
19127 cur_proc_ptr->frame_reg = tc_get_register (1);
19129 SKIP_WHITESPACE ();
19130 if (*input_line_pointer++ != ','
19131 || get_absolute_expression_and_terminator (&val) != ',')
19133 as_warn (_("Bad .frame directive"));
19134 --input_line_pointer;
19135 demand_empty_rest_of_line ();
19139 cur_proc_ptr->frame_offset = val;
19140 cur_proc_ptr->pc_reg = tc_get_register (0);
19142 demand_empty_rest_of_line ();
19146 /* The .fmask and .mask directives. If the mdebug section is present
19147 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19148 embedded targets, s_mips_mask is used so that we can set the PDR
19149 information correctly. We can't use the ecoff routines because they
19150 make reference to the ecoff symbol table (in the mdebug section). */
19153 s_mips_mask (int reg_type)
19155 if (ECOFF_DEBUGGING)
19156 s_ignore (reg_type);
19161 if (cur_proc_ptr == (procS *) NULL)
19163 as_warn (_(".mask/.fmask outside of .ent"));
19164 demand_empty_rest_of_line ();
19168 if (get_absolute_expression_and_terminator (&mask) != ',')
19170 as_warn (_("Bad .mask/.fmask directive"));
19171 --input_line_pointer;
19172 demand_empty_rest_of_line ();
19176 off = get_absolute_expression ();
19178 if (reg_type == 'F')
19180 cur_proc_ptr->fpreg_mask = mask;
19181 cur_proc_ptr->fpreg_offset = off;
19185 cur_proc_ptr->reg_mask = mask;
19186 cur_proc_ptr->reg_offset = off;
19189 demand_empty_rest_of_line ();
19193 /* A table describing all the processors gas knows about. Names are
19194 matched in the order listed.
19196 To ease comparison, please keep this table in the same order as
19197 gcc's mips_cpu_info_table[]. */
19198 static const struct mips_cpu_info mips_cpu_info_table[] =
19200 /* Entries for generic ISAs */
19201 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19202 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19203 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19204 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19205 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19206 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19207 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19208 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19209 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19212 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19213 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19214 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19217 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19220 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19221 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19222 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19223 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19224 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19225 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19226 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19227 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19228 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19229 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19230 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19231 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19232 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19233 /* ST Microelectronics Loongson 2E and 2F cores */
19234 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19235 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19238 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19239 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19240 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19241 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19242 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19243 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19244 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19245 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19246 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19247 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19248 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19249 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19250 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19251 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19252 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19255 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19256 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19257 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19258 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19260 /* MIPS 32 Release 2 */
19261 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19262 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19263 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19264 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19265 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19266 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19267 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19268 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19269 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19270 ISA_MIPS32R2, CPU_MIPS32R2 },
19271 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19272 ISA_MIPS32R2, CPU_MIPS32R2 },
19273 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19274 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19275 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19276 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19277 /* Deprecated forms of the above. */
19278 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19279 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19280 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19281 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19282 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19283 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19284 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19285 /* Deprecated forms of the above. */
19286 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19287 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19288 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19289 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19290 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19291 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19292 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19293 /* Deprecated forms of the above. */
19294 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19295 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19296 /* 34Kn is a 34kc without DSP. */
19297 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19298 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19299 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19300 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19301 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19302 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19303 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 /* Deprecated forms of the above. */
19305 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19307 /* 1004K cores are multiprocessor versions of the 34K. */
19308 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19310 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19311 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19315 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19316 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19317 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19319 /* Broadcom SB-1 CPU core */
19320 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19321 /* Broadcom SB-1A CPU core */
19322 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19324 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19326 /* MIPS 64 Release 2 */
19328 /* Cavium Networks Octeon CPU core */
19329 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19330 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19331 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19334 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19337 XLP is mostly like XLR, with the prominent exception that it is
19338 MIPS64R2 rather than MIPS64. */
19339 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19342 { NULL, 0, 0, 0, 0 }
19346 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19347 with a final "000" replaced by "k". Ignore case.
19349 Note: this function is shared between GCC and GAS. */
19352 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19354 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19355 given++, canonical++;
19357 return ((*given == 0 && *canonical == 0)
19358 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19362 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19363 CPU name. We've traditionally allowed a lot of variation here.
19365 Note: this function is shared between GCC and GAS. */
19368 mips_matching_cpu_name_p (const char *canonical, const char *given)
19370 /* First see if the name matches exactly, or with a final "000"
19371 turned into "k". */
19372 if (mips_strict_matching_cpu_name_p (canonical, given))
19375 /* If not, try comparing based on numerical designation alone.
19376 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19377 if (TOLOWER (*given) == 'r')
19379 if (!ISDIGIT (*given))
19382 /* Skip over some well-known prefixes in the canonical name,
19383 hoping to find a number there too. */
19384 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19386 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19388 else if (TOLOWER (canonical[0]) == 'r')
19391 return mips_strict_matching_cpu_name_p (canonical, given);
19395 /* Parse an option that takes the name of a processor as its argument.
19396 OPTION is the name of the option and CPU_STRING is the argument.
19397 Return the corresponding processor enumeration if the CPU_STRING is
19398 recognized, otherwise report an error and return null.
19400 A similar function exists in GCC. */
19402 static const struct mips_cpu_info *
19403 mips_parse_cpu (const char *option, const char *cpu_string)
19405 const struct mips_cpu_info *p;
19407 /* 'from-abi' selects the most compatible architecture for the given
19408 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19409 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19410 version. Look first at the -mgp options, if given, otherwise base
19411 the choice on MIPS_DEFAULT_64BIT.
19413 Treat NO_ABI like the EABIs. One reason to do this is that the
19414 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19415 architecture. This code picks MIPS I for 'mips' and MIPS III for
19416 'mips64', just as we did in the days before 'from-abi'. */
19417 if (strcasecmp (cpu_string, "from-abi") == 0)
19419 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19420 return mips_cpu_info_from_isa (ISA_MIPS1);
19422 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19423 return mips_cpu_info_from_isa (ISA_MIPS3);
19425 if (file_mips_gp32 >= 0)
19426 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19428 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19433 /* 'default' has traditionally been a no-op. Probably not very useful. */
19434 if (strcasecmp (cpu_string, "default") == 0)
19437 for (p = mips_cpu_info_table; p->name != 0; p++)
19438 if (mips_matching_cpu_name_p (p->name, cpu_string))
19441 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19445 /* Return the canonical processor information for ISA (a member of the
19446 ISA_MIPS* enumeration). */
19448 static const struct mips_cpu_info *
19449 mips_cpu_info_from_isa (int isa)
19453 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19454 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19455 && isa == mips_cpu_info_table[i].isa)
19456 return (&mips_cpu_info_table[i]);
19461 static const struct mips_cpu_info *
19462 mips_cpu_info_from_arch (int arch)
19466 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19467 if (arch == mips_cpu_info_table[i].cpu)
19468 return (&mips_cpu_info_table[i]);
19474 show (FILE *stream, const char *string, int *col_p, int *first_p)
19478 fprintf (stream, "%24s", "");
19483 fprintf (stream, ", ");
19487 if (*col_p + strlen (string) > 72)
19489 fprintf (stream, "\n%24s", "");
19493 fprintf (stream, "%s", string);
19494 *col_p += strlen (string);
19500 md_show_usage (FILE *stream)
19505 fprintf (stream, _("\
19507 -EB generate big endian output\n\
19508 -EL generate little endian output\n\
19509 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19510 -G NUM allow referencing objects up to NUM bytes\n\
19511 implicitly with the gp register [default 8]\n"));
19512 fprintf (stream, _("\
19513 -mips1 generate MIPS ISA I instructions\n\
19514 -mips2 generate MIPS ISA II instructions\n\
19515 -mips3 generate MIPS ISA III instructions\n\
19516 -mips4 generate MIPS ISA IV instructions\n\
19517 -mips5 generate MIPS ISA V instructions\n\
19518 -mips32 generate MIPS32 ISA instructions\n\
19519 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19520 -mips64 generate MIPS64 ISA instructions\n\
19521 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19522 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19526 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19527 show (stream, mips_cpu_info_table[i].name, &column, &first);
19528 show (stream, "from-abi", &column, &first);
19529 fputc ('\n', stream);
19531 fprintf (stream, _("\
19532 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19533 -no-mCPU don't generate code specific to CPU.\n\
19534 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19538 show (stream, "3900", &column, &first);
19539 show (stream, "4010", &column, &first);
19540 show (stream, "4100", &column, &first);
19541 show (stream, "4650", &column, &first);
19542 fputc ('\n', stream);
19544 fprintf (stream, _("\
19545 -mips16 generate mips16 instructions\n\
19546 -no-mips16 do not generate mips16 instructions\n"));
19547 fprintf (stream, _("\
19548 -mmicromips generate microMIPS instructions\n\
19549 -mno-micromips do not generate microMIPS instructions\n"));
19550 fprintf (stream, _("\
19551 -msmartmips generate smartmips instructions\n\
19552 -mno-smartmips do not generate smartmips instructions\n"));
19553 fprintf (stream, _("\
19554 -mdsp generate DSP instructions\n\
19555 -mno-dsp do not generate DSP instructions\n"));
19556 fprintf (stream, _("\
19557 -mdspr2 generate DSP R2 instructions\n\
19558 -mno-dspr2 do not generate DSP R2 instructions\n"));
19559 fprintf (stream, _("\
19560 -mmt generate MT instructions\n\
19561 -mno-mt do not generate MT instructions\n"));
19562 fprintf (stream, _("\
19563 -mmcu generate MCU instructions\n\
19564 -mno-mcu do not generate MCU instructions\n"));
19565 fprintf (stream, _("\
19566 -mvirt generate Virtualization instructions\n\
19567 -mno-virt do not generate Virtualization instructions\n"));
19568 fprintf (stream, _("\
19569 -minsn32 only generate 32-bit microMIPS instructions\n\
19570 -mno-insn32 generate all microMIPS instructions\n"));
19571 fprintf (stream, _("\
19572 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19573 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19574 -mfix-vr4120 work around certain VR4120 errata\n\
19575 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19576 -mfix-24k insert a nop after ERET and DERET instructions\n\
19577 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19578 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19579 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19580 -msym32 assume all symbols have 32-bit values\n\
19581 -O0 remove unneeded NOPs, do not swap branches\n\
19582 -O remove unneeded NOPs and swap branches\n\
19583 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19584 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19585 fprintf (stream, _("\
19586 -mhard-float allow floating-point instructions\n\
19587 -msoft-float do not allow floating-point instructions\n\
19588 -msingle-float only allow 32-bit floating-point operations\n\
19589 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19590 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19591 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19593 fprintf (stream, _("\
19594 -KPIC, -call_shared generate SVR4 position independent code\n\
19595 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19596 -mvxworks-pic generate VxWorks position independent code\n\
19597 -non_shared do not generate code that can operate with DSOs\n\
19598 -xgot assume a 32 bit GOT\n\
19599 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19600 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19601 position dependent (non shared) code\n\
19602 -mabi=ABI create ABI conformant object file for:\n"));
19606 show (stream, "32", &column, &first);
19607 show (stream, "o64", &column, &first);
19608 show (stream, "n32", &column, &first);
19609 show (stream, "64", &column, &first);
19610 show (stream, "eabi", &column, &first);
19612 fputc ('\n', stream);
19614 fprintf (stream, _("\
19615 -32 create o32 ABI object file (default)\n\
19616 -n32 create n32 ABI object file\n\
19617 -64 create 64 ABI object file\n"));
19622 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19624 if (HAVE_64BIT_SYMBOLS)
19625 return dwarf2_format_64bit_irix;
19627 return dwarf2_format_32bit;
19632 mips_dwarf2_addr_size (void)
19634 if (HAVE_64BIT_OBJECTS)
19640 /* Standard calling conventions leave the CFA at SP on entry. */
19642 mips_cfi_frame_initial_instructions (void)
19644 cfi_add_CFA_def_cfa_register (SP);
19648 tc_mips_regname_to_dw2regnum (char *regname)
19650 unsigned int regnum = -1;
19653 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))