1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
299 /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
300 /* soft_float */ FALSE, /* single_float */ FALSE
303 /* These variables are filled in with the masks of registers used.
304 The object format code reads them and puts them in the appropriate
306 unsigned long mips_gprmask;
307 unsigned long mips_cprmask[4];
309 /* MIPS ISA we are using for this output file. */
310 static int file_mips_isa = ISA_UNKNOWN;
312 /* True if any MIPS16 code was produced. */
313 static int file_ase_mips16;
315 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
316 || mips_opts.isa == ISA_MIPS32R2 \
317 || mips_opts.isa == ISA_MIPS64 \
318 || mips_opts.isa == ISA_MIPS64R2)
320 /* True if any microMIPS code was produced. */
321 static int file_ase_micromips;
323 /* True if we want to create R_MIPS_JALR for jalr $25. */
325 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
327 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
328 because there's no place for any addend, the only acceptable
329 expression is a bare symbol. */
330 #define MIPS_JALR_HINT_P(EXPR) \
331 (!HAVE_IN_PLACE_ADDENDS \
332 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
335 /* True if -mips3d was passed or implied by arguments passed on the
336 command line (e.g., by -march). */
337 static int file_ase_mips3d;
339 /* True if -mdmx was passed or implied by arguments passed on the
340 command line (e.g., by -march). */
341 static int file_ase_mdmx;
343 /* True if -msmartmips was passed or implied by arguments passed on the
344 command line (e.g., by -march). */
345 static int file_ase_smartmips;
347 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
348 || mips_opts.isa == ISA_MIPS32R2)
350 /* True if -mdsp was passed or implied by arguments passed on the
351 command line (e.g., by -march). */
352 static int file_ase_dsp;
354 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
355 || mips_opts.isa == ISA_MIPS64R2 \
356 || mips_opts.micromips)
358 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
360 /* True if -mdspr2 was passed or implied by arguments passed on the
361 command line (e.g., by -march). */
362 static int file_ase_dspr2;
364 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
365 || mips_opts.isa == ISA_MIPS64R2 \
366 || mips_opts.micromips)
368 /* True if -mmt was passed or implied by arguments passed on the
369 command line (e.g., by -march). */
370 static int file_ase_mt;
372 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
376 || mips_opts.isa == ISA_MIPS64R2 \
377 || mips_opts.micromips)
379 /* True if -mvirt was passed or implied by arguments passed on the
380 command line (e.g., by -march). */
381 static int file_ase_virt;
383 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
384 || mips_opts.isa == ISA_MIPS64R2 \
385 || mips_opts.micromips)
387 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \
388 || (mips_opts.micromips \
389 && ISA_HAS_64BIT_REGS (mips_opts.isa)))
391 /* The argument of the -march= flag. The architecture we are assembling. */
392 static int file_mips_arch = CPU_UNKNOWN;
393 static const char *mips_arch_string;
395 /* The argument of the -mtune= flag. The architecture for which we
397 static int mips_tune = CPU_UNKNOWN;
398 static const char *mips_tune_string;
400 /* True when generating 32-bit code for a 64-bit processor. */
401 static int mips_32bitmode = 0;
403 /* True if the given ABI requires 32-bit registers. */
404 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
406 /* Likewise 64-bit registers. */
407 #define ABI_NEEDS_64BIT_REGS(ABI) \
409 || (ABI) == N64_ABI \
412 /* Return true if ISA supports 64 bit wide gp registers. */
413 #define ISA_HAS_64BIT_REGS(ISA) \
414 ((ISA) == ISA_MIPS3 \
415 || (ISA) == ISA_MIPS4 \
416 || (ISA) == ISA_MIPS5 \
417 || (ISA) == ISA_MIPS64 \
418 || (ISA) == ISA_MIPS64R2)
420 /* Return true if ISA supports 64 bit wide float registers. */
421 #define ISA_HAS_64BIT_FPRS(ISA) \
422 ((ISA) == ISA_MIPS3 \
423 || (ISA) == ISA_MIPS4 \
424 || (ISA) == ISA_MIPS5 \
425 || (ISA) == ISA_MIPS32R2 \
426 || (ISA) == ISA_MIPS64 \
427 || (ISA) == ISA_MIPS64R2)
429 /* Return true if ISA supports 64-bit right rotate (dror et al.)
431 #define ISA_HAS_DROR(ISA) \
432 ((ISA) == ISA_MIPS64R2 \
433 || (mips_opts.micromips \
434 && ISA_HAS_64BIT_REGS (ISA)) \
437 /* Return true if ISA supports 32-bit right rotate (ror et al.)
439 #define ISA_HAS_ROR(ISA) \
440 ((ISA) == ISA_MIPS32R2 \
441 || (ISA) == ISA_MIPS64R2 \
442 || mips_opts.ase_smartmips \
443 || mips_opts.micromips \
446 /* Return true if ISA supports single-precision floats in odd registers. */
447 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
448 ((ISA) == ISA_MIPS32 \
449 || (ISA) == ISA_MIPS32R2 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2)
453 /* Return true if ISA supports move to/from high part of a 64-bit
454 floating-point register. */
455 #define ISA_HAS_MXHC1(ISA) \
456 ((ISA) == ISA_MIPS32R2 \
457 || (ISA) == ISA_MIPS64R2)
459 #define HAVE_32BIT_GPRS \
460 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
462 #define HAVE_32BIT_FPRS \
463 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
465 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
466 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
468 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
470 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
472 /* True if relocations are stored in-place. */
473 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
475 /* The ABI-derived address size. */
476 #define HAVE_64BIT_ADDRESSES \
477 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
478 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
480 /* The size of symbolic constants (i.e., expressions of the form
481 "SYMBOL" or "SYMBOL + OFFSET"). */
482 #define HAVE_32BIT_SYMBOLS \
483 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
484 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
486 /* Addresses are loaded in different ways, depending on the address size
487 in use. The n32 ABI Documentation also mandates the use of additions
488 with overflow checking, but existing implementations don't follow it. */
489 #define ADDRESS_ADD_INSN \
490 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
492 #define ADDRESS_ADDI_INSN \
493 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
495 #define ADDRESS_LOAD_INSN \
496 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
498 #define ADDRESS_STORE_INSN \
499 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
501 /* Return true if the given CPU supports the MIPS16 ASE. */
502 #define CPU_HAS_MIPS16(cpu) \
503 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
504 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
506 /* Return true if the given CPU supports the microMIPS ASE. */
507 #define CPU_HAS_MICROMIPS(cpu) 0
509 /* True if CPU has a dror instruction. */
510 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
512 /* True if CPU has a ror instruction. */
513 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
515 /* True if CPU is in the Octeon family */
516 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
518 /* True if CPU has seq/sne and seqi/snei instructions. */
519 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
521 /* True, if CPU has support for ldc1 and sdc1. */
522 #define CPU_HAS_LDC1_SDC1(CPU) \
523 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
525 /* True if mflo and mfhi can be immediately followed by instructions
526 which write to the HI and LO registers.
528 According to MIPS specifications, MIPS ISAs I, II, and III need
529 (at least) two instructions between the reads of HI/LO and
530 instructions which write them, and later ISAs do not. Contradicting
531 the MIPS specifications, some MIPS IV processor user manuals (e.g.
532 the UM for the NEC Vr5000) document needing the instructions between
533 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
534 MIPS64 and later ISAs to have the interlocks, plus any specific
535 earlier-ISA CPUs for which CPU documentation declares that the
536 instructions are really interlocked. */
537 #define hilo_interlocks \
538 (mips_opts.isa == ISA_MIPS32 \
539 || mips_opts.isa == ISA_MIPS32R2 \
540 || mips_opts.isa == ISA_MIPS64 \
541 || mips_opts.isa == ISA_MIPS64R2 \
542 || mips_opts.arch == CPU_R4010 \
543 || mips_opts.arch == CPU_R5900 \
544 || mips_opts.arch == CPU_R10000 \
545 || mips_opts.arch == CPU_R12000 \
546 || mips_opts.arch == CPU_R14000 \
547 || mips_opts.arch == CPU_R16000 \
548 || mips_opts.arch == CPU_RM7000 \
549 || mips_opts.arch == CPU_VR5500 \
550 || mips_opts.micromips \
553 /* Whether the processor uses hardware interlocks to protect reads
554 from the GPRs after they are loaded from memory, and thus does not
555 require nops to be inserted. This applies to instructions marked
556 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
557 level I and microMIPS mode instructions are always interlocked. */
558 #define gpr_interlocks \
559 (mips_opts.isa != ISA_MIPS1 \
560 || mips_opts.arch == CPU_R3900 \
561 || mips_opts.arch == CPU_R5900 \
562 || mips_opts.micromips \
565 /* Whether the processor uses hardware interlocks to avoid delays
566 required by coprocessor instructions, and thus does not require
567 nops to be inserted. This applies to instructions marked
568 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
569 between instructions marked INSN_WRITE_COND_CODE and ones marked
570 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
571 levels I, II, and III and microMIPS mode instructions are always
573 /* Itbl support may require additional care here. */
574 #define cop_interlocks \
575 ((mips_opts.isa != ISA_MIPS1 \
576 && mips_opts.isa != ISA_MIPS2 \
577 && mips_opts.isa != ISA_MIPS3) \
578 || mips_opts.arch == CPU_R4300 \
579 || mips_opts.micromips \
582 /* Whether the processor uses hardware interlocks to protect reads
583 from coprocessor registers after they are loaded from memory, and
584 thus does not require nops to be inserted. This applies to
585 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
586 requires at MIPS ISA level I and microMIPS mode instructions are
587 always interlocked. */
588 #define cop_mem_interlocks \
589 (mips_opts.isa != ISA_MIPS1 \
590 || mips_opts.micromips \
593 /* Is this a mfhi or mflo instruction? */
594 #define MF_HILO_INSN(PINFO) \
595 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
597 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
598 has been selected. This implies, in particular, that addresses of text
599 labels have their LSB set. */
600 #define HAVE_CODE_COMPRESSION \
601 ((mips_opts.mips16 | mips_opts.micromips) != 0)
603 /* MIPS PIC level. */
605 enum mips_pic_level mips_pic;
607 /* 1 if we should generate 32 bit offsets from the $gp register in
608 SVR4_PIC mode. Currently has no meaning in other modes. */
609 static int mips_big_got = 0;
611 /* 1 if trap instructions should used for overflow rather than break
613 static int mips_trap = 0;
615 /* 1 if double width floating point constants should not be constructed
616 by assembling two single width halves into two single width floating
617 point registers which just happen to alias the double width destination
618 register. On some architectures this aliasing can be disabled by a bit
619 in the status register, and the setting of this bit cannot be determined
620 automatically at assemble time. */
621 static int mips_disable_float_construction;
623 /* Non-zero if any .set noreorder directives were used. */
625 static int mips_any_noreorder;
627 /* Non-zero if nops should be inserted when the register referenced in
628 an mfhi/mflo instruction is read in the next two instructions. */
629 static int mips_7000_hilo_fix;
631 /* The size of objects in the small data section. */
632 static unsigned int g_switch_value = 8;
633 /* Whether the -G option was used. */
634 static int g_switch_seen = 0;
639 /* If we can determine in advance that GP optimization won't be
640 possible, we can skip the relaxation stuff that tries to produce
641 GP-relative references. This makes delay slot optimization work
644 This function can only provide a guess, but it seems to work for
645 gcc output. It needs to guess right for gcc, otherwise gcc
646 will put what it thinks is a GP-relative instruction in a branch
649 I don't know if a fix is needed for the SVR4_PIC mode. I've only
650 fixed it for the non-PIC mode. KR 95/04/07 */
651 static int nopic_need_relax (symbolS *, int);
653 /* handle of the OPCODE hash table */
654 static struct hash_control *op_hash = NULL;
656 /* The opcode hash table we use for the mips16. */
657 static struct hash_control *mips16_op_hash = NULL;
659 /* The opcode hash table we use for the microMIPS ASE. */
660 static struct hash_control *micromips_op_hash = NULL;
662 /* This array holds the chars that always start a comment. If the
663 pre-processor is disabled, these aren't very useful */
664 const char comment_chars[] = "#";
666 /* This array holds the chars that only start a comment at the beginning of
667 a line. If the line seems to have the form '# 123 filename'
668 .line and .file directives will appear in the pre-processed output */
669 /* Note that input_file.c hand checks for '#' at the beginning of the
670 first line of the input file. This is because the compiler outputs
671 #NO_APP at the beginning of its output. */
672 /* Also note that C style comments are always supported. */
673 const char line_comment_chars[] = "#";
675 /* This array holds machine specific line separator characters. */
676 const char line_separator_chars[] = ";";
678 /* Chars that can be used to separate mant from exp in floating point nums */
679 const char EXP_CHARS[] = "eE";
681 /* Chars that mean this number is a floating point constant */
684 const char FLT_CHARS[] = "rRsSfFdDxXpP";
686 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
687 changed in read.c . Ideally it shouldn't have to know about it at all,
688 but nothing is ideal around here.
691 static char *insn_error;
693 static int auto_align = 1;
695 /* When outputting SVR4 PIC code, the assembler needs to know the
696 offset in the stack frame from which to restore the $gp register.
697 This is set by the .cprestore pseudo-op, and saved in this
699 static offsetT mips_cprestore_offset = -1;
701 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
702 more optimizations, it can use a register value instead of a memory-saved
703 offset and even an other register than $gp as global pointer. */
704 static offsetT mips_cpreturn_offset = -1;
705 static int mips_cpreturn_register = -1;
706 static int mips_gp_register = GP;
707 static int mips_gprel_offset = 0;
709 /* Whether mips_cprestore_offset has been set in the current function
710 (or whether it has already been warned about, if not). */
711 static int mips_cprestore_valid = 0;
713 /* This is the register which holds the stack frame, as set by the
714 .frame pseudo-op. This is needed to implement .cprestore. */
715 static int mips_frame_reg = SP;
717 /* Whether mips_frame_reg has been set in the current function
718 (or whether it has already been warned about, if not). */
719 static int mips_frame_reg_valid = 0;
721 /* To output NOP instructions correctly, we need to keep information
722 about the previous two instructions. */
724 /* Whether we are optimizing. The default value of 2 means to remove
725 unneeded NOPs and swap branch instructions when possible. A value
726 of 1 means to not swap branches. A value of 0 means to always
728 static int mips_optimize = 2;
730 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
731 equivalent to seeing no -g option at all. */
732 static int mips_debug = 0;
734 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
735 #define MAX_VR4130_NOPS 4
737 /* The maximum number of NOPs needed to fill delay slots. */
738 #define MAX_DELAY_NOPS 2
740 /* The maximum number of NOPs needed for any purpose. */
743 /* A list of previous instructions, with index 0 being the most recent.
744 We need to look back MAX_NOPS instructions when filling delay slots
745 or working around processor errata. We need to look back one
746 instruction further if we're thinking about using history[0] to
747 fill a branch delay slot. */
748 static struct mips_cl_insn history[1 + MAX_NOPS];
750 /* Nop instructions used by emit_nop. */
751 static struct mips_cl_insn nop_insn;
752 static struct mips_cl_insn mips16_nop_insn;
753 static struct mips_cl_insn micromips_nop16_insn;
754 static struct mips_cl_insn micromips_nop32_insn;
756 /* The appropriate nop for the current mode. */
757 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
758 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
760 /* The size of NOP_INSN in bytes. */
761 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
763 /* If this is set, it points to a frag holding nop instructions which
764 were inserted before the start of a noreorder section. If those
765 nops turn out to be unnecessary, the size of the frag can be
767 static fragS *prev_nop_frag;
769 /* The number of nop instructions we created in prev_nop_frag. */
770 static int prev_nop_frag_holds;
772 /* The number of nop instructions that we know we need in
774 static int prev_nop_frag_required;
776 /* The number of instructions we've seen since prev_nop_frag. */
777 static int prev_nop_frag_since;
779 /* For ECOFF and ELF, relocations against symbols are done in two
780 parts, with a HI relocation and a LO relocation. Each relocation
781 has only 16 bits of space to store an addend. This means that in
782 order for the linker to handle carries correctly, it must be able
783 to locate both the HI and the LO relocation. This means that the
784 relocations must appear in order in the relocation table.
786 In order to implement this, we keep track of each unmatched HI
787 relocation. We then sort them so that they immediately precede the
788 corresponding LO relocation. */
793 struct mips_hi_fixup *next;
796 /* The section this fixup is in. */
800 /* The list of unmatched HI relocs. */
802 static struct mips_hi_fixup *mips_hi_fixup_list;
804 /* The frag containing the last explicit relocation operator.
805 Null if explicit relocations have not been used. */
807 static fragS *prev_reloc_op_frag;
809 /* Map normal MIPS register numbers to mips16 register numbers. */
811 #define X ILLEGAL_REG
812 static const int mips32_to_16_reg_map[] =
814 X, X, 2, 3, 4, 5, 6, 7,
815 X, X, X, X, X, X, X, X,
816 0, 1, X, X, X, X, X, X,
817 X, X, X, X, X, X, X, X
821 /* Map mips16 register numbers to normal MIPS register numbers. */
823 static const unsigned int mips16_to_32_reg_map[] =
825 16, 17, 2, 3, 4, 5, 6, 7
828 /* Map normal MIPS register numbers to microMIPS register numbers. */
830 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
831 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
832 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
833 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
834 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
835 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
836 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
838 #define X ILLEGAL_REG
839 /* reg type h: 4, 5, 6. */
840 static const int mips32_to_micromips_reg_h_map[] =
842 X, X, X, X, 4, 5, 6, X,
843 X, X, X, X, X, X, X, X,
844 X, X, X, X, X, X, X, X,
845 X, X, X, X, X, X, X, X
848 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
849 static const int mips32_to_micromips_reg_m_map[] =
851 0, X, 2, 3, X, X, X, X,
852 X, X, X, X, X, X, X, X,
853 4, 1, 5, 6, 7, X, X, X,
854 X, X, X, X, X, X, X, X
857 /* reg type q: 0, 2-7. 17. */
858 static const int mips32_to_micromips_reg_q_map[] =
860 0, X, 2, 3, 4, 5, 6, 7,
861 X, X, X, X, X, X, X, X,
862 X, 1, X, X, X, X, X, X,
863 X, X, X, X, X, X, X, X
866 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
869 /* Map microMIPS register numbers to normal MIPS register numbers. */
871 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
872 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
873 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
874 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
875 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
876 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
878 /* The microMIPS registers with type h. */
879 static const unsigned int micromips_to_32_reg_h_map[] =
881 5, 5, 6, 4, 4, 4, 4, 4
884 /* The microMIPS registers with type i. */
885 static const unsigned int micromips_to_32_reg_i_map[] =
887 6, 7, 7, 21, 22, 5, 6, 7
890 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
892 /* The microMIPS registers with type m. */
893 static const unsigned int micromips_to_32_reg_m_map[] =
895 0, 17, 2, 3, 16, 18, 19, 20
898 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
900 /* The microMIPS registers with type q. */
901 static const unsigned int micromips_to_32_reg_q_map[] =
903 0, 17, 2, 3, 4, 5, 6, 7
906 /* microMIPS imm type B. */
907 static const int micromips_imm_b_map[] =
909 1, 4, 8, 12, 16, 20, 24, -1
912 /* microMIPS imm type C. */
913 static const int micromips_imm_c_map[] =
915 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
918 /* Classifies the kind of instructions we're interested in when
919 implementing -mfix-vr4120. */
920 enum fix_vr4120_class
928 NUM_FIX_VR4120_CLASSES
931 /* ...likewise -mfix-loongson2f-jump. */
932 static bfd_boolean mips_fix_loongson2f_jump;
934 /* ...likewise -mfix-loongson2f-nop. */
935 static bfd_boolean mips_fix_loongson2f_nop;
937 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
938 static bfd_boolean mips_fix_loongson2f;
940 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
941 there must be at least one other instruction between an instruction
942 of type X and an instruction of type Y. */
943 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
945 /* True if -mfix-vr4120 is in force. */
946 static int mips_fix_vr4120;
948 /* ...likewise -mfix-vr4130. */
949 static int mips_fix_vr4130;
951 /* ...likewise -mfix-24k. */
952 static int mips_fix_24k;
954 /* ...likewise -mfix-cn63xxp1 */
955 static bfd_boolean mips_fix_cn63xxp1;
957 /* We don't relax branches by default, since this causes us to expand
958 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
959 fail to compute the offset before expanding the macro to the most
960 efficient expansion. */
962 static int mips_relax_branch;
964 /* The expansion of many macros depends on the type of symbol that
965 they refer to. For example, when generating position-dependent code,
966 a macro that refers to a symbol may have two different expansions,
967 one which uses GP-relative addresses and one which uses absolute
968 addresses. When generating SVR4-style PIC, a macro may have
969 different expansions for local and global symbols.
971 We handle these situations by generating both sequences and putting
972 them in variant frags. In position-dependent code, the first sequence
973 will be the GP-relative one and the second sequence will be the
974 absolute one. In SVR4 PIC, the first sequence will be for global
975 symbols and the second will be for local symbols.
977 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
978 SECOND are the lengths of the two sequences in bytes. These fields
979 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
980 the subtype has the following flags:
983 Set if it has been decided that we should use the second
984 sequence instead of the first.
987 Set in the first variant frag if the macro's second implementation
988 is longer than its first. This refers to the macro as a whole,
989 not an individual relaxation.
992 Set in the first variant frag if the macro appeared in a .set nomacro
993 block and if one alternative requires a warning but the other does not.
996 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
999 RELAX_DELAY_SLOT_16BIT
1000 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1003 RELAX_DELAY_SLOT_SIZE_FIRST
1004 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1005 the macro is of the wrong size for the branch delay slot.
1007 RELAX_DELAY_SLOT_SIZE_SECOND
1008 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1009 the macro is of the wrong size for the branch delay slot.
1011 The frag's "opcode" points to the first fixup for relaxable code.
1013 Relaxable macros are generated using a sequence such as:
1015 relax_start (SYMBOL);
1016 ... generate first expansion ...
1018 ... generate second expansion ...
1021 The code and fixups for the unwanted alternative are discarded
1022 by md_convert_frag. */
1023 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1025 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1026 #define RELAX_SECOND(X) ((X) & 0xff)
1027 #define RELAX_USE_SECOND 0x10000
1028 #define RELAX_SECOND_LONGER 0x20000
1029 #define RELAX_NOMACRO 0x40000
1030 #define RELAX_DELAY_SLOT 0x80000
1031 #define RELAX_DELAY_SLOT_16BIT 0x100000
1032 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1033 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1035 /* Branch without likely bit. If label is out of range, we turn:
1037 beq reg1, reg2, label
1047 with the following opcode replacements:
1054 bltzal <-> bgezal (with jal label instead of j label)
1056 Even though keeping the delay slot instruction in the delay slot of
1057 the branch would be more efficient, it would be very tricky to do
1058 correctly, because we'd have to introduce a variable frag *after*
1059 the delay slot instruction, and expand that instead. Let's do it
1060 the easy way for now, even if the branch-not-taken case now costs
1061 one additional instruction. Out-of-range branches are not supposed
1062 to be common, anyway.
1064 Branch likely. If label is out of range, we turn:
1066 beql reg1, reg2, label
1067 delay slot (annulled if branch not taken)
1076 delay slot (executed only if branch taken)
1079 It would be possible to generate a shorter sequence by losing the
1080 likely bit, generating something like:
1085 delay slot (executed only if branch taken)
1097 bltzall -> bgezal (with jal label instead of j label)
1098 bgezall -> bltzal (ditto)
1101 but it's not clear that it would actually improve performance. */
1102 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1103 ((relax_substateT) \
1106 | ((toofar) ? 0x20 : 0) \
1107 | ((link) ? 0x40 : 0) \
1108 | ((likely) ? 0x80 : 0) \
1109 | ((uncond) ? 0x100 : 0)))
1110 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1111 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1112 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1113 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1114 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1115 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1117 /* For mips16 code, we use an entirely different form of relaxation.
1118 mips16 supports two versions of most instructions which take
1119 immediate values: a small one which takes some small value, and a
1120 larger one which takes a 16 bit value. Since branches also follow
1121 this pattern, relaxing these values is required.
1123 We can assemble both mips16 and normal MIPS code in a single
1124 object. Therefore, we need to support this type of relaxation at
1125 the same time that we support the relaxation described above. We
1126 use the high bit of the subtype field to distinguish these cases.
1128 The information we store for this type of relaxation is the
1129 argument code found in the opcode file for this relocation, whether
1130 the user explicitly requested a small or extended form, and whether
1131 the relocation is in a jump or jal delay slot. That tells us the
1132 size of the value, and how it should be stored. We also store
1133 whether the fragment is considered to be extended or not. We also
1134 store whether this is known to be a branch to a different section,
1135 whether we have tried to relax this frag yet, and whether we have
1136 ever extended a PC relative fragment because of a shift count. */
1137 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1140 | ((small) ? 0x100 : 0) \
1141 | ((ext) ? 0x200 : 0) \
1142 | ((dslot) ? 0x400 : 0) \
1143 | ((jal_dslot) ? 0x800 : 0))
1144 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1145 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1146 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1147 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1148 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1149 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1150 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1151 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1152 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1153 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1154 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1155 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1157 /* For microMIPS code, we use relaxation similar to one we use for
1158 MIPS16 code. Some instructions that take immediate values support
1159 two encodings: a small one which takes some small value, and a
1160 larger one which takes a 16 bit value. As some branches also follow
1161 this pattern, relaxing these values is required.
1163 We can assemble both microMIPS and normal MIPS code in a single
1164 object. Therefore, we need to support this type of relaxation at
1165 the same time that we support the relaxation described above. We
1166 use one of the high bits of the subtype field to distinguish these
1169 The information we store for this type of relaxation is the argument
1170 code found in the opcode file for this relocation, the register
1171 selected as the assembler temporary, whether the branch is
1172 unconditional, whether it is compact, whether it stores the link
1173 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1174 branches to a sequence of instructions is enabled, and whether the
1175 displacement of a branch is too large to fit as an immediate argument
1176 of a 16-bit and a 32-bit branch, respectively. */
1177 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1178 relax32, toofar16, toofar32) \
1181 | (((at) & 0x1f) << 8) \
1182 | ((uncond) ? 0x2000 : 0) \
1183 | ((compact) ? 0x4000 : 0) \
1184 | ((link) ? 0x8000 : 0) \
1185 | ((relax32) ? 0x10000 : 0) \
1186 | ((toofar16) ? 0x20000 : 0) \
1187 | ((toofar32) ? 0x40000 : 0))
1188 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1189 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1190 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1191 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1192 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1193 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1194 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1196 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1197 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1198 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1199 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1200 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1201 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1203 /* Sign-extend 16-bit value X. */
1204 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1206 /* Is the given value a sign-extended 32-bit value? */
1207 #define IS_SEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1209 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1211 /* Is the given value a sign-extended 16-bit value? */
1212 #define IS_SEXT_16BIT_NUM(x) \
1213 (((x) &~ (offsetT) 0x7fff) == 0 \
1214 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1216 /* Is the given value a sign-extended 12-bit value? */
1217 #define IS_SEXT_12BIT_NUM(x) \
1218 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1220 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1221 #define IS_ZEXT_32BIT_NUM(x) \
1222 (((x) &~ (offsetT) 0xffffffff) == 0 \
1223 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1225 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1226 VALUE << SHIFT. VALUE is evaluated exactly once. */
1227 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1228 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1229 | (((VALUE) & (MASK)) << (SHIFT)))
1231 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1233 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1234 (((STRUCT) >> (SHIFT)) & (MASK))
1236 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1237 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1239 include/opcode/mips.h specifies operand fields using the macros
1240 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1241 with "MIPS16OP" instead of "OP". */
1242 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1245 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1246 OP_MASK_##FIELD, OP_SH_##FIELD); \
1248 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1249 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1251 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1252 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1253 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1255 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1256 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1258 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1259 : EXTRACT_BITS ((INSN).insn_opcode, \
1260 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1261 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1262 EXTRACT_BITS ((INSN).insn_opcode, \
1263 MIPS16OP_MASK_##FIELD, \
1264 MIPS16OP_SH_##FIELD)
1266 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1267 #define MIPS16_EXTEND (0xf000U << 16)
1269 /* Whether or not we are emitting a branch-likely macro. */
1270 static bfd_boolean emit_branch_likely_macro = FALSE;
1272 /* Global variables used when generating relaxable macros. See the
1273 comment above RELAX_ENCODE for more details about how relaxation
1276 /* 0 if we're not emitting a relaxable macro.
1277 1 if we're emitting the first of the two relaxation alternatives.
1278 2 if we're emitting the second alternative. */
1281 /* The first relaxable fixup in the current frag. (In other words,
1282 the first fixup that refers to relaxable code.) */
1285 /* sizes[0] says how many bytes of the first alternative are stored in
1286 the current frag. Likewise sizes[1] for the second alternative. */
1287 unsigned int sizes[2];
1289 /* The symbol on which the choice of sequence depends. */
1293 /* Global variables used to decide whether a macro needs a warning. */
1295 /* True if the macro is in a branch delay slot. */
1296 bfd_boolean delay_slot_p;
1298 /* Set to the length in bytes required if the macro is in a delay slot
1299 that requires a specific length of instruction, otherwise zero. */
1300 unsigned int delay_slot_length;
1302 /* For relaxable macros, sizes[0] is the length of the first alternative
1303 in bytes and sizes[1] is the length of the second alternative.
1304 For non-relaxable macros, both elements give the length of the
1306 unsigned int sizes[2];
1308 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1309 instruction of the first alternative in bytes and first_insn_sizes[1]
1310 is the length of the first instruction of the second alternative.
1311 For non-relaxable macros, both elements give the length of the first
1312 instruction in bytes.
1314 Set to zero if we haven't yet seen the first instruction. */
1315 unsigned int first_insn_sizes[2];
1317 /* For relaxable macros, insns[0] is the number of instructions for the
1318 first alternative and insns[1] is the number of instructions for the
1321 For non-relaxable macros, both elements give the number of
1322 instructions for the macro. */
1323 unsigned int insns[2];
1325 /* The first variant frag for this macro. */
1327 } mips_macro_warning;
1329 /* Prototypes for static functions. */
1331 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1333 static void append_insn
1334 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1335 bfd_boolean expansionp);
1336 static void mips_no_prev_insn (void);
1337 static void macro_build (expressionS *, const char *, const char *, ...);
1338 static void mips16_macro_build
1339 (expressionS *, const char *, const char *, va_list *);
1340 static void load_register (int, expressionS *, int);
1341 static void macro_start (void);
1342 static void macro_end (void);
1343 static void macro (struct mips_cl_insn * ip);
1344 static void mips16_macro (struct mips_cl_insn * ip);
1345 static void mips_ip (char *str, struct mips_cl_insn * ip);
1346 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1347 static void mips16_immed
1348 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1349 unsigned int, unsigned long *);
1350 static size_t my_getSmallExpression
1351 (expressionS *, bfd_reloc_code_real_type *, char *);
1352 static void my_getExpression (expressionS *, char *);
1353 static void s_align (int);
1354 static void s_change_sec (int);
1355 static void s_change_section (int);
1356 static void s_cons (int);
1357 static void s_float_cons (int);
1358 static void s_mips_globl (int);
1359 static void s_option (int);
1360 static void s_mipsset (int);
1361 static void s_abicalls (int);
1362 static void s_cpload (int);
1363 static void s_cpsetup (int);
1364 static void s_cplocal (int);
1365 static void s_cprestore (int);
1366 static void s_cpreturn (int);
1367 static void s_dtprelword (int);
1368 static void s_dtpreldword (int);
1369 static void s_tprelword (int);
1370 static void s_tpreldword (int);
1371 static void s_gpvalue (int);
1372 static void s_gpword (int);
1373 static void s_gpdword (int);
1374 static void s_ehword (int);
1375 static void s_cpadd (int);
1376 static void s_insn (int);
1377 static void md_obj_begin (void);
1378 static void md_obj_end (void);
1379 static void s_mips_ent (int);
1380 static void s_mips_end (int);
1381 static void s_mips_frame (int);
1382 static void s_mips_mask (int reg_type);
1383 static void s_mips_stab (int);
1384 static void s_mips_weakext (int);
1385 static void s_mips_file (int);
1386 static void s_mips_loc (int);
1387 static bfd_boolean pic_need_relax (symbolS *, asection *);
1388 static int relaxed_branch_length (fragS *, asection *, int);
1389 static int validate_mips_insn (const struct mips_opcode *);
1390 static int validate_micromips_insn (const struct mips_opcode *);
1391 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1392 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1394 /* Table and functions used to map between CPU/ISA names, and
1395 ISA levels, and CPU numbers. */
1397 struct mips_cpu_info
1399 const char *name; /* CPU or ISA name. */
1400 int flags; /* ASEs available, or ISA flag. */
1401 int isa; /* ISA level. */
1402 int cpu; /* CPU number (default CPU if ISA). */
1405 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1406 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1407 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1408 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1409 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1410 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1411 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1412 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1413 #define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
1415 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1416 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1417 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1421 The following pseudo-ops from the Kane and Heinrich MIPS book
1422 should be defined here, but are currently unsupported: .alias,
1423 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1425 The following pseudo-ops from the Kane and Heinrich MIPS book are
1426 specific to the type of debugging information being generated, and
1427 should be defined by the object format: .aent, .begin, .bend,
1428 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1431 The following pseudo-ops from the Kane and Heinrich MIPS book are
1432 not MIPS CPU specific, but are also not specific to the object file
1433 format. This file is probably the best place to define them, but
1434 they are not currently supported: .asm0, .endr, .lab, .struct. */
1436 static const pseudo_typeS mips_pseudo_table[] =
1438 /* MIPS specific pseudo-ops. */
1439 {"option", s_option, 0},
1440 {"set", s_mipsset, 0},
1441 {"rdata", s_change_sec, 'r'},
1442 {"sdata", s_change_sec, 's'},
1443 {"livereg", s_ignore, 0},
1444 {"abicalls", s_abicalls, 0},
1445 {"cpload", s_cpload, 0},
1446 {"cpsetup", s_cpsetup, 0},
1447 {"cplocal", s_cplocal, 0},
1448 {"cprestore", s_cprestore, 0},
1449 {"cpreturn", s_cpreturn, 0},
1450 {"dtprelword", s_dtprelword, 0},
1451 {"dtpreldword", s_dtpreldword, 0},
1452 {"tprelword", s_tprelword, 0},
1453 {"tpreldword", s_tpreldword, 0},
1454 {"gpvalue", s_gpvalue, 0},
1455 {"gpword", s_gpword, 0},
1456 {"gpdword", s_gpdword, 0},
1457 {"ehword", s_ehword, 0},
1458 {"cpadd", s_cpadd, 0},
1459 {"insn", s_insn, 0},
1461 /* Relatively generic pseudo-ops that happen to be used on MIPS
1463 {"asciiz", stringer, 8 + 1},
1464 {"bss", s_change_sec, 'b'},
1466 {"half", s_cons, 1},
1467 {"dword", s_cons, 3},
1468 {"weakext", s_mips_weakext, 0},
1469 {"origin", s_org, 0},
1470 {"repeat", s_rept, 0},
1472 /* For MIPS this is non-standard, but we define it for consistency. */
1473 {"sbss", s_change_sec, 'B'},
1475 /* These pseudo-ops are defined in read.c, but must be overridden
1476 here for one reason or another. */
1477 {"align", s_align, 0},
1478 {"byte", s_cons, 0},
1479 {"data", s_change_sec, 'd'},
1480 {"double", s_float_cons, 'd'},
1481 {"float", s_float_cons, 'f'},
1482 {"globl", s_mips_globl, 0},
1483 {"global", s_mips_globl, 0},
1484 {"hword", s_cons, 1},
1486 {"long", s_cons, 2},
1487 {"octa", s_cons, 4},
1488 {"quad", s_cons, 3},
1489 {"section", s_change_section, 0},
1490 {"short", s_cons, 1},
1491 {"single", s_float_cons, 'f'},
1492 {"stabd", s_mips_stab, 'd'},
1493 {"stabn", s_mips_stab, 'n'},
1494 {"stabs", s_mips_stab, 's'},
1495 {"text", s_change_sec, 't'},
1496 {"word", s_cons, 2},
1498 { "extern", ecoff_directive_extern, 0},
1503 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1505 /* These pseudo-ops should be defined by the object file format.
1506 However, a.out doesn't support them, so we have versions here. */
1507 {"aent", s_mips_ent, 1},
1508 {"bgnb", s_ignore, 0},
1509 {"end", s_mips_end, 0},
1510 {"endb", s_ignore, 0},
1511 {"ent", s_mips_ent, 0},
1512 {"file", s_mips_file, 0},
1513 {"fmask", s_mips_mask, 'F'},
1514 {"frame", s_mips_frame, 0},
1515 {"loc", s_mips_loc, 0},
1516 {"mask", s_mips_mask, 'R'},
1517 {"verstamp", s_ignore, 0},
1521 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1522 purpose of the `.dc.a' internal pseudo-op. */
1525 mips_address_bytes (void)
1527 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1530 extern void pop_insert (const pseudo_typeS *);
1533 mips_pop_insert (void)
1535 pop_insert (mips_pseudo_table);
1536 if (! ECOFF_DEBUGGING)
1537 pop_insert (mips_nonecoff_pseudo_table);
1540 /* Symbols labelling the current insn. */
1542 struct insn_label_list
1544 struct insn_label_list *next;
1548 static struct insn_label_list *free_insn_labels;
1549 #define label_list tc_segment_info_data.labels
1551 static void mips_clear_insn_labels (void);
1552 static void mips_mark_labels (void);
1553 static void mips_compressed_mark_labels (void);
1556 mips_clear_insn_labels (void)
1558 register struct insn_label_list **pl;
1559 segment_info_type *si;
1563 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1566 si = seg_info (now_seg);
1567 *pl = si->label_list;
1568 si->label_list = NULL;
1572 /* Mark instruction labels in MIPS16/microMIPS mode. */
1575 mips_mark_labels (void)
1577 if (HAVE_CODE_COMPRESSION)
1578 mips_compressed_mark_labels ();
1581 static char *expr_end;
1583 /* Expressions which appear in instructions. These are set by
1586 static expressionS imm_expr;
1587 static expressionS imm2_expr;
1588 static expressionS offset_expr;
1590 /* Relocs associated with imm_expr and offset_expr. */
1592 static bfd_reloc_code_real_type imm_reloc[3]
1593 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1594 static bfd_reloc_code_real_type offset_reloc[3]
1595 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1597 /* This is set to the resulting size of the instruction to be produced
1598 by mips16_ip if an explicit extension is used or by mips_ip if an
1599 explicit size is supplied. */
1601 static unsigned int forced_insn_length;
1603 /* True if we are assembling an instruction. All dot symbols defined during
1604 this time should be treated as code labels. */
1606 static bfd_boolean mips_assembling_insn;
1609 /* The pdr segment for per procedure frame/regmask info. Not used for
1612 static segT pdr_seg;
1615 /* The default target format to use. */
1617 #if defined (TE_FreeBSD)
1618 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1619 #elif defined (TE_TMIPS)
1620 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1622 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1626 mips_target_format (void)
1628 switch (OUTPUT_FLAVOR)
1630 case bfd_target_ecoff_flavour:
1631 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1632 case bfd_target_coff_flavour:
1634 case bfd_target_elf_flavour:
1636 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1637 return (target_big_endian
1638 ? "elf32-bigmips-vxworks"
1639 : "elf32-littlemips-vxworks");
1641 return (target_big_endian
1642 ? (HAVE_64BIT_OBJECTS
1643 ? ELF_TARGET ("elf64-", "big")
1645 ? ELF_TARGET ("elf32-n", "big")
1646 : ELF_TARGET ("elf32-", "big")))
1647 : (HAVE_64BIT_OBJECTS
1648 ? ELF_TARGET ("elf64-", "little")
1650 ? ELF_TARGET ("elf32-n", "little")
1651 : ELF_TARGET ("elf32-", "little"))));
1658 /* Return the length of a microMIPS instruction in bytes. If bits of
1659 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1660 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1661 major opcode) will require further modifications to the opcode
1664 static inline unsigned int
1665 micromips_insn_length (const struct mips_opcode *mo)
1667 return (mo->mask >> 16) == 0 ? 2 : 4;
1670 /* Return the length of MIPS16 instruction OPCODE. */
1672 static inline unsigned int
1673 mips16_opcode_length (unsigned long opcode)
1675 return (opcode >> 16) == 0 ? 2 : 4;
1678 /* Return the length of instruction INSN. */
1680 static inline unsigned int
1681 insn_length (const struct mips_cl_insn *insn)
1683 if (mips_opts.micromips)
1684 return micromips_insn_length (insn->insn_mo);
1685 else if (mips_opts.mips16)
1686 return mips16_opcode_length (insn->insn_opcode);
1691 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1694 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1699 insn->insn_opcode = mo->match;
1702 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1703 insn->fixp[i] = NULL;
1704 insn->fixed_p = (mips_opts.noreorder > 0);
1705 insn->noreorder_p = (mips_opts.noreorder > 0);
1706 insn->mips16_absolute_jump_p = 0;
1707 insn->complete_p = 0;
1708 insn->cleared_p = 0;
1711 /* Record the current MIPS16/microMIPS mode in now_seg. */
1714 mips_record_compressed_mode (void)
1716 segment_info_type *si;
1718 si = seg_info (now_seg);
1719 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1720 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1721 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1722 si->tc_segment_info_data.micromips = mips_opts.micromips;
1725 /* Read a standard MIPS instruction from BUF. */
1727 static unsigned long
1728 read_insn (char *buf)
1730 if (target_big_endian)
1731 return bfd_getb32 ((bfd_byte *) buf);
1733 return bfd_getl32 ((bfd_byte *) buf);
1736 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1740 write_insn (char *buf, unsigned int insn)
1742 md_number_to_chars (buf, insn, 4);
1746 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1747 has length LENGTH. */
1749 static unsigned long
1750 read_compressed_insn (char *buf, unsigned int length)
1756 for (i = 0; i < length; i += 2)
1759 if (target_big_endian)
1760 insn |= bfd_getb16 ((char *) buf);
1762 insn |= bfd_getl16 ((char *) buf);
1768 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1769 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1772 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1776 for (i = 0; i < length; i += 2)
1777 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1778 return buf + length;
1781 /* Install INSN at the location specified by its "frag" and "where" fields. */
1784 install_insn (const struct mips_cl_insn *insn)
1786 char *f = insn->frag->fr_literal + insn->where;
1787 if (HAVE_CODE_COMPRESSION)
1788 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1790 write_insn (f, insn->insn_opcode);
1791 mips_record_compressed_mode ();
1794 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1795 and install the opcode in the new location. */
1798 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1803 insn->where = where;
1804 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1805 if (insn->fixp[i] != NULL)
1807 insn->fixp[i]->fx_frag = frag;
1808 insn->fixp[i]->fx_where = where;
1810 install_insn (insn);
1813 /* Add INSN to the end of the output. */
1816 add_fixed_insn (struct mips_cl_insn *insn)
1818 char *f = frag_more (insn_length (insn));
1819 move_insn (insn, frag_now, f - frag_now->fr_literal);
1822 /* Start a variant frag and move INSN to the start of the variant part,
1823 marking it as fixed. The other arguments are as for frag_var. */
1826 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1827 relax_substateT subtype, symbolS *symbol, offsetT offset)
1829 frag_grow (max_chars);
1830 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1832 frag_var (rs_machine_dependent, max_chars, var,
1833 subtype, symbol, offset, NULL);
1836 /* Insert N copies of INSN into the history buffer, starting at
1837 position FIRST. Neither FIRST nor N need to be clipped. */
1840 insert_into_history (unsigned int first, unsigned int n,
1841 const struct mips_cl_insn *insn)
1843 if (mips_relax.sequence != 2)
1847 for (i = ARRAY_SIZE (history); i-- > first;)
1849 history[i] = history[i - n];
1855 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1856 the idea is to make it obvious at a glance that each errata is
1860 init_vr4120_conflicts (void)
1862 #define CONFLICT(FIRST, SECOND) \
1863 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1865 /* Errata 21 - [D]DIV[U] after [D]MACC */
1866 CONFLICT (MACC, DIV);
1867 CONFLICT (DMACC, DIV);
1869 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1870 CONFLICT (DMULT, DMULT);
1871 CONFLICT (DMULT, DMACC);
1872 CONFLICT (DMACC, DMULT);
1873 CONFLICT (DMACC, DMACC);
1875 /* Errata 24 - MT{LO,HI} after [D]MACC */
1876 CONFLICT (MACC, MTHILO);
1877 CONFLICT (DMACC, MTHILO);
1879 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1880 instruction is executed immediately after a MACC or DMACC
1881 instruction, the result of [either instruction] is incorrect." */
1882 CONFLICT (MACC, MULT);
1883 CONFLICT (MACC, DMULT);
1884 CONFLICT (DMACC, MULT);
1885 CONFLICT (DMACC, DMULT);
1887 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1888 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1889 DDIV or DDIVU instruction, the result of the MACC or
1890 DMACC instruction is incorrect.". */
1891 CONFLICT (DMULT, MACC);
1892 CONFLICT (DMULT, DMACC);
1893 CONFLICT (DIV, MACC);
1894 CONFLICT (DIV, DMACC);
1904 #define RTYPE_MASK 0x1ff00
1905 #define RTYPE_NUM 0x00100
1906 #define RTYPE_FPU 0x00200
1907 #define RTYPE_FCC 0x00400
1908 #define RTYPE_VEC 0x00800
1909 #define RTYPE_GP 0x01000
1910 #define RTYPE_CP0 0x02000
1911 #define RTYPE_PC 0x04000
1912 #define RTYPE_ACC 0x08000
1913 #define RTYPE_CCC 0x10000
1914 #define RNUM_MASK 0x000ff
1915 #define RWARN 0x80000
1917 #define GENERIC_REGISTER_NUMBERS \
1918 {"$0", RTYPE_NUM | 0}, \
1919 {"$1", RTYPE_NUM | 1}, \
1920 {"$2", RTYPE_NUM | 2}, \
1921 {"$3", RTYPE_NUM | 3}, \
1922 {"$4", RTYPE_NUM | 4}, \
1923 {"$5", RTYPE_NUM | 5}, \
1924 {"$6", RTYPE_NUM | 6}, \
1925 {"$7", RTYPE_NUM | 7}, \
1926 {"$8", RTYPE_NUM | 8}, \
1927 {"$9", RTYPE_NUM | 9}, \
1928 {"$10", RTYPE_NUM | 10}, \
1929 {"$11", RTYPE_NUM | 11}, \
1930 {"$12", RTYPE_NUM | 12}, \
1931 {"$13", RTYPE_NUM | 13}, \
1932 {"$14", RTYPE_NUM | 14}, \
1933 {"$15", RTYPE_NUM | 15}, \
1934 {"$16", RTYPE_NUM | 16}, \
1935 {"$17", RTYPE_NUM | 17}, \
1936 {"$18", RTYPE_NUM | 18}, \
1937 {"$19", RTYPE_NUM | 19}, \
1938 {"$20", RTYPE_NUM | 20}, \
1939 {"$21", RTYPE_NUM | 21}, \
1940 {"$22", RTYPE_NUM | 22}, \
1941 {"$23", RTYPE_NUM | 23}, \
1942 {"$24", RTYPE_NUM | 24}, \
1943 {"$25", RTYPE_NUM | 25}, \
1944 {"$26", RTYPE_NUM | 26}, \
1945 {"$27", RTYPE_NUM | 27}, \
1946 {"$28", RTYPE_NUM | 28}, \
1947 {"$29", RTYPE_NUM | 29}, \
1948 {"$30", RTYPE_NUM | 30}, \
1949 {"$31", RTYPE_NUM | 31}
1951 #define FPU_REGISTER_NAMES \
1952 {"$f0", RTYPE_FPU | 0}, \
1953 {"$f1", RTYPE_FPU | 1}, \
1954 {"$f2", RTYPE_FPU | 2}, \
1955 {"$f3", RTYPE_FPU | 3}, \
1956 {"$f4", RTYPE_FPU | 4}, \
1957 {"$f5", RTYPE_FPU | 5}, \
1958 {"$f6", RTYPE_FPU | 6}, \
1959 {"$f7", RTYPE_FPU | 7}, \
1960 {"$f8", RTYPE_FPU | 8}, \
1961 {"$f9", RTYPE_FPU | 9}, \
1962 {"$f10", RTYPE_FPU | 10}, \
1963 {"$f11", RTYPE_FPU | 11}, \
1964 {"$f12", RTYPE_FPU | 12}, \
1965 {"$f13", RTYPE_FPU | 13}, \
1966 {"$f14", RTYPE_FPU | 14}, \
1967 {"$f15", RTYPE_FPU | 15}, \
1968 {"$f16", RTYPE_FPU | 16}, \
1969 {"$f17", RTYPE_FPU | 17}, \
1970 {"$f18", RTYPE_FPU | 18}, \
1971 {"$f19", RTYPE_FPU | 19}, \
1972 {"$f20", RTYPE_FPU | 20}, \
1973 {"$f21", RTYPE_FPU | 21}, \
1974 {"$f22", RTYPE_FPU | 22}, \
1975 {"$f23", RTYPE_FPU | 23}, \
1976 {"$f24", RTYPE_FPU | 24}, \
1977 {"$f25", RTYPE_FPU | 25}, \
1978 {"$f26", RTYPE_FPU | 26}, \
1979 {"$f27", RTYPE_FPU | 27}, \
1980 {"$f28", RTYPE_FPU | 28}, \
1981 {"$f29", RTYPE_FPU | 29}, \
1982 {"$f30", RTYPE_FPU | 30}, \
1983 {"$f31", RTYPE_FPU | 31}
1985 #define FPU_CONDITION_CODE_NAMES \
1986 {"$fcc0", RTYPE_FCC | 0}, \
1987 {"$fcc1", RTYPE_FCC | 1}, \
1988 {"$fcc2", RTYPE_FCC | 2}, \
1989 {"$fcc3", RTYPE_FCC | 3}, \
1990 {"$fcc4", RTYPE_FCC | 4}, \
1991 {"$fcc5", RTYPE_FCC | 5}, \
1992 {"$fcc6", RTYPE_FCC | 6}, \
1993 {"$fcc7", RTYPE_FCC | 7}
1995 #define COPROC_CONDITION_CODE_NAMES \
1996 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1997 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1998 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1999 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2000 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2001 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2002 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2003 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2005 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2006 {"$a4", RTYPE_GP | 8}, \
2007 {"$a5", RTYPE_GP | 9}, \
2008 {"$a6", RTYPE_GP | 10}, \
2009 {"$a7", RTYPE_GP | 11}, \
2010 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2011 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2012 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2013 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2014 {"$t0", RTYPE_GP | 12}, \
2015 {"$t1", RTYPE_GP | 13}, \
2016 {"$t2", RTYPE_GP | 14}, \
2017 {"$t3", RTYPE_GP | 15}
2019 #define O32_SYMBOLIC_REGISTER_NAMES \
2020 {"$t0", RTYPE_GP | 8}, \
2021 {"$t1", RTYPE_GP | 9}, \
2022 {"$t2", RTYPE_GP | 10}, \
2023 {"$t3", RTYPE_GP | 11}, \
2024 {"$t4", RTYPE_GP | 12}, \
2025 {"$t5", RTYPE_GP | 13}, \
2026 {"$t6", RTYPE_GP | 14}, \
2027 {"$t7", RTYPE_GP | 15}, \
2028 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2029 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2030 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2031 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2033 /* Remaining symbolic register names */
2034 #define SYMBOLIC_REGISTER_NAMES \
2035 {"$zero", RTYPE_GP | 0}, \
2036 {"$at", RTYPE_GP | 1}, \
2037 {"$AT", RTYPE_GP | 1}, \
2038 {"$v0", RTYPE_GP | 2}, \
2039 {"$v1", RTYPE_GP | 3}, \
2040 {"$a0", RTYPE_GP | 4}, \
2041 {"$a1", RTYPE_GP | 5}, \
2042 {"$a2", RTYPE_GP | 6}, \
2043 {"$a3", RTYPE_GP | 7}, \
2044 {"$s0", RTYPE_GP | 16}, \
2045 {"$s1", RTYPE_GP | 17}, \
2046 {"$s2", RTYPE_GP | 18}, \
2047 {"$s3", RTYPE_GP | 19}, \
2048 {"$s4", RTYPE_GP | 20}, \
2049 {"$s5", RTYPE_GP | 21}, \
2050 {"$s6", RTYPE_GP | 22}, \
2051 {"$s7", RTYPE_GP | 23}, \
2052 {"$t8", RTYPE_GP | 24}, \
2053 {"$t9", RTYPE_GP | 25}, \
2054 {"$k0", RTYPE_GP | 26}, \
2055 {"$kt0", RTYPE_GP | 26}, \
2056 {"$k1", RTYPE_GP | 27}, \
2057 {"$kt1", RTYPE_GP | 27}, \
2058 {"$gp", RTYPE_GP | 28}, \
2059 {"$sp", RTYPE_GP | 29}, \
2060 {"$s8", RTYPE_GP | 30}, \
2061 {"$fp", RTYPE_GP | 30}, \
2062 {"$ra", RTYPE_GP | 31}
2064 #define MIPS16_SPECIAL_REGISTER_NAMES \
2065 {"$pc", RTYPE_PC | 0}
2067 #define MDMX_VECTOR_REGISTER_NAMES \
2068 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2069 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2070 {"$v2", RTYPE_VEC | 2}, \
2071 {"$v3", RTYPE_VEC | 3}, \
2072 {"$v4", RTYPE_VEC | 4}, \
2073 {"$v5", RTYPE_VEC | 5}, \
2074 {"$v6", RTYPE_VEC | 6}, \
2075 {"$v7", RTYPE_VEC | 7}, \
2076 {"$v8", RTYPE_VEC | 8}, \
2077 {"$v9", RTYPE_VEC | 9}, \
2078 {"$v10", RTYPE_VEC | 10}, \
2079 {"$v11", RTYPE_VEC | 11}, \
2080 {"$v12", RTYPE_VEC | 12}, \
2081 {"$v13", RTYPE_VEC | 13}, \
2082 {"$v14", RTYPE_VEC | 14}, \
2083 {"$v15", RTYPE_VEC | 15}, \
2084 {"$v16", RTYPE_VEC | 16}, \
2085 {"$v17", RTYPE_VEC | 17}, \
2086 {"$v18", RTYPE_VEC | 18}, \
2087 {"$v19", RTYPE_VEC | 19}, \
2088 {"$v20", RTYPE_VEC | 20}, \
2089 {"$v21", RTYPE_VEC | 21}, \
2090 {"$v22", RTYPE_VEC | 22}, \
2091 {"$v23", RTYPE_VEC | 23}, \
2092 {"$v24", RTYPE_VEC | 24}, \
2093 {"$v25", RTYPE_VEC | 25}, \
2094 {"$v26", RTYPE_VEC | 26}, \
2095 {"$v27", RTYPE_VEC | 27}, \
2096 {"$v28", RTYPE_VEC | 28}, \
2097 {"$v29", RTYPE_VEC | 29}, \
2098 {"$v30", RTYPE_VEC | 30}, \
2099 {"$v31", RTYPE_VEC | 31}
2101 #define MIPS_DSP_ACCUMULATOR_NAMES \
2102 {"$ac0", RTYPE_ACC | 0}, \
2103 {"$ac1", RTYPE_ACC | 1}, \
2104 {"$ac2", RTYPE_ACC | 2}, \
2105 {"$ac3", RTYPE_ACC | 3}
2107 static const struct regname reg_names[] = {
2108 GENERIC_REGISTER_NUMBERS,
2110 FPU_CONDITION_CODE_NAMES,
2111 COPROC_CONDITION_CODE_NAMES,
2113 /* The $txx registers depends on the abi,
2114 these will be added later into the symbol table from
2115 one of the tables below once mips_abi is set after
2116 parsing of arguments from the command line. */
2117 SYMBOLIC_REGISTER_NAMES,
2119 MIPS16_SPECIAL_REGISTER_NAMES,
2120 MDMX_VECTOR_REGISTER_NAMES,
2121 MIPS_DSP_ACCUMULATOR_NAMES,
2125 static const struct regname reg_names_o32[] = {
2126 O32_SYMBOLIC_REGISTER_NAMES,
2130 static const struct regname reg_names_n32n64[] = {
2131 N32N64_SYMBOLIC_REGISTER_NAMES,
2135 /* Check if S points at a valid register specifier according to TYPES.
2136 If so, then return 1, advance S to consume the specifier and store
2137 the register's number in REGNOP, otherwise return 0. */
2140 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2147 /* Find end of name. */
2149 if (is_name_beginner (*e))
2151 while (is_part_of_name (*e))
2154 /* Terminate name. */
2158 /* Look for a register symbol. */
2159 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2161 int r = S_GET_VALUE (symbolP);
2163 reg = r & RNUM_MASK;
2164 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2165 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2166 reg = (r & RNUM_MASK) - 2;
2168 /* Else see if this is a register defined in an itbl entry. */
2169 else if ((types & RTYPE_GP) && itbl_have_entries)
2176 if (itbl_get_reg_val (n, &r))
2177 reg = r & RNUM_MASK;
2180 /* Advance to next token if a register was recognised. */
2183 else if (types & RWARN)
2184 as_warn (_("Unrecognized register name `%s'"), *s);
2192 /* Check if S points at a valid register list according to TYPES.
2193 If so, then return 1, advance S to consume the list and store
2194 the registers present on the list as a bitmask of ones in REGLISTP,
2195 otherwise return 0. A valid list comprises a comma-separated
2196 enumeration of valid single registers and/or dash-separated
2197 contiguous register ranges as determined by their numbers.
2199 As a special exception if one of s0-s7 registers is specified as
2200 the range's lower delimiter and s8 (fp) is its upper one, then no
2201 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2202 are selected; they have to be listed separately if needed. */
2205 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2207 unsigned int reglist = 0;
2208 unsigned int lastregno;
2209 bfd_boolean ok = TRUE;
2210 unsigned int regmask;
2211 char *s_endlist = *s;
2215 while (reg_lookup (s, types, ®no))
2221 ok = reg_lookup (s, types, &lastregno);
2222 if (ok && lastregno < regno)
2228 if (lastregno == FP && regno >= S0 && regno <= S7)
2233 regmask = 1 << lastregno;
2234 regmask = (regmask << 1) - 1;
2235 regmask ^= (1 << regno) - 1;
2249 *reglistp = reglist;
2250 return ok && reglist != 0;
2253 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2254 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2257 is_opcode_valid (const struct mips_opcode *mo)
2259 int isa = mips_opts.isa;
2263 if (mips_opts.ase_mdmx)
2265 if (mips_opts.ase_dsp)
2267 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2269 if (mips_opts.ase_dspr2)
2271 if (mips_opts.ase_mt)
2273 if (mips_opts.ase_mips3d)
2275 if (mips_opts.ase_smartmips)
2276 ase |= ASE_SMARTMIPS;
2277 if (mips_opts.ase_mcu)
2279 if (mips_opts.ase_virt)
2281 if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
2284 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2287 /* Check whether the instruction or macro requires single-precision or
2288 double-precision floating-point support. Note that this information is
2289 stored differently in the opcode table for insns and macros. */
2290 if (mo->pinfo == INSN_MACRO)
2292 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2293 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2297 fp_s = mo->pinfo & FP_S;
2298 fp_d = mo->pinfo & FP_D;
2301 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2304 if (fp_s && mips_opts.soft_float)
2310 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2311 selected ISA and architecture. */
2314 is_opcode_valid_16 (const struct mips_opcode *mo)
2316 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2319 /* Return TRUE if the size of the microMIPS opcode MO matches one
2320 explicitly requested. Always TRUE in the standard MIPS mode. */
2323 is_size_valid (const struct mips_opcode *mo)
2325 if (!mips_opts.micromips)
2328 if (!forced_insn_length)
2330 if (mo->pinfo == INSN_MACRO)
2332 return forced_insn_length == micromips_insn_length (mo);
2335 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2336 of the preceding instruction. Always TRUE in the standard MIPS mode.
2338 We don't accept macros in 16-bit delay slots to avoid a case where
2339 a macro expansion fails because it relies on a preceding 32-bit real
2340 instruction to have matched and does not handle the operands correctly.
2341 The only macros that may expand to 16-bit instructions are JAL that
2342 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2343 and BGT (that likewise cannot be placed in a delay slot) that decay to
2344 a NOP. In all these cases the macros precede any corresponding real
2345 instruction definitions in the opcode table, so they will match in the
2346 second pass where the size of the delay slot is ignored and therefore
2347 produce correct code. */
2350 is_delay_slot_valid (const struct mips_opcode *mo)
2352 if (!mips_opts.micromips)
2355 if (mo->pinfo == INSN_MACRO)
2356 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2357 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2358 && micromips_insn_length (mo) != 4)
2360 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2361 && micromips_insn_length (mo) != 2)
2367 /* This function is called once, at assembler startup time. It should set up
2368 all the tables, etc. that the MD part of the assembler will need. */
2373 const char *retval = NULL;
2377 if (mips_pic != NO_PIC)
2379 if (g_switch_seen && g_switch_value != 0)
2380 as_bad (_("-G may not be used in position-independent code"));
2384 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2385 as_warn (_("Could not set architecture and machine"));
2387 op_hash = hash_new ();
2389 for (i = 0; i < NUMOPCODES;)
2391 const char *name = mips_opcodes[i].name;
2393 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2396 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2397 mips_opcodes[i].name, retval);
2398 /* Probably a memory allocation problem? Give up now. */
2399 as_fatal (_("Broken assembler. No assembly attempted."));
2403 if (mips_opcodes[i].pinfo != INSN_MACRO)
2405 if (!validate_mips_insn (&mips_opcodes[i]))
2407 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2409 create_insn (&nop_insn, mips_opcodes + i);
2410 if (mips_fix_loongson2f_nop)
2411 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2412 nop_insn.fixed_p = 1;
2417 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2420 mips16_op_hash = hash_new ();
2423 while (i < bfd_mips16_num_opcodes)
2425 const char *name = mips16_opcodes[i].name;
2427 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2429 as_fatal (_("internal: can't hash `%s': %s"),
2430 mips16_opcodes[i].name, retval);
2433 if (mips16_opcodes[i].pinfo != INSN_MACRO
2434 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2435 != mips16_opcodes[i].match))
2437 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2438 mips16_opcodes[i].name, mips16_opcodes[i].args);
2441 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2443 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2444 mips16_nop_insn.fixed_p = 1;
2448 while (i < bfd_mips16_num_opcodes
2449 && strcmp (mips16_opcodes[i].name, name) == 0);
2452 micromips_op_hash = hash_new ();
2455 while (i < bfd_micromips_num_opcodes)
2457 const char *name = micromips_opcodes[i].name;
2459 retval = hash_insert (micromips_op_hash, name,
2460 (void *) µmips_opcodes[i]);
2462 as_fatal (_("internal: can't hash `%s': %s"),
2463 micromips_opcodes[i].name, retval);
2465 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2467 struct mips_cl_insn *micromips_nop_insn;
2469 if (!validate_micromips_insn (µmips_opcodes[i]))
2472 if (micromips_insn_length (micromips_opcodes + i) == 2)
2473 micromips_nop_insn = µmips_nop16_insn;
2474 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2475 micromips_nop_insn = µmips_nop32_insn;
2479 if (micromips_nop_insn->insn_mo == NULL
2480 && strcmp (name, "nop") == 0)
2482 create_insn (micromips_nop_insn, micromips_opcodes + i);
2483 micromips_nop_insn->fixed_p = 1;
2486 while (++i < bfd_micromips_num_opcodes
2487 && strcmp (micromips_opcodes[i].name, name) == 0);
2491 as_fatal (_("Broken assembler. No assembly attempted."));
2493 /* We add all the general register names to the symbol table. This
2494 helps us detect invalid uses of them. */
2495 for (i = 0; reg_names[i].name; i++)
2496 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2497 reg_names[i].num, /* & RNUM_MASK, */
2498 &zero_address_frag));
2500 for (i = 0; reg_names_n32n64[i].name; i++)
2501 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2502 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2503 &zero_address_frag));
2505 for (i = 0; reg_names_o32[i].name; i++)
2506 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2507 reg_names_o32[i].num, /* & RNUM_MASK, */
2508 &zero_address_frag));
2510 mips_no_prev_insn ();
2513 mips_cprmask[0] = 0;
2514 mips_cprmask[1] = 0;
2515 mips_cprmask[2] = 0;
2516 mips_cprmask[3] = 0;
2518 /* set the default alignment for the text section (2**2) */
2519 record_alignment (text_section, 2);
2521 bfd_set_gp_size (stdoutput, g_switch_value);
2526 /* On a native system other than VxWorks, sections must be aligned
2527 to 16 byte boundaries. When configured for an embedded ELF
2528 target, we don't bother. */
2529 if (strncmp (TARGET_OS, "elf", 3) != 0
2530 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2532 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2533 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2534 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2537 /* Create a .reginfo section for register masks and a .mdebug
2538 section for debugging information. */
2546 subseg = now_subseg;
2548 /* The ABI says this section should be loaded so that the
2549 running program can access it. However, we don't load it
2550 if we are configured for an embedded target */
2551 flags = SEC_READONLY | SEC_DATA;
2552 if (strncmp (TARGET_OS, "elf", 3) != 0)
2553 flags |= SEC_ALLOC | SEC_LOAD;
2555 if (mips_abi != N64_ABI)
2557 sec = subseg_new (".reginfo", (subsegT) 0);
2559 bfd_set_section_flags (stdoutput, sec, flags);
2560 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2562 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2566 /* The 64-bit ABI uses a .MIPS.options section rather than
2567 .reginfo section. */
2568 sec = subseg_new (".MIPS.options", (subsegT) 0);
2569 bfd_set_section_flags (stdoutput, sec, flags);
2570 bfd_set_section_alignment (stdoutput, sec, 3);
2572 /* Set up the option header. */
2574 Elf_Internal_Options opthdr;
2577 opthdr.kind = ODK_REGINFO;
2578 opthdr.size = (sizeof (Elf_External_Options)
2579 + sizeof (Elf64_External_RegInfo));
2582 f = frag_more (sizeof (Elf_External_Options));
2583 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2584 (Elf_External_Options *) f);
2586 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2590 if (ECOFF_DEBUGGING)
2592 sec = subseg_new (".mdebug", (subsegT) 0);
2593 (void) bfd_set_section_flags (stdoutput, sec,
2594 SEC_HAS_CONTENTS | SEC_READONLY);
2595 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2597 else if (mips_flag_pdr)
2599 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2600 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2601 SEC_READONLY | SEC_RELOC
2603 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2606 subseg_set (seg, subseg);
2609 #endif /* OBJ_ELF */
2611 if (! ECOFF_DEBUGGING)
2614 if (mips_fix_vr4120)
2615 init_vr4120_conflicts ();
2621 mips_emit_delays ();
2622 if (! ECOFF_DEBUGGING)
2627 md_assemble (char *str)
2629 struct mips_cl_insn insn;
2630 bfd_reloc_code_real_type unused_reloc[3]
2631 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2633 imm_expr.X_op = O_absent;
2634 imm2_expr.X_op = O_absent;
2635 offset_expr.X_op = O_absent;
2636 imm_reloc[0] = BFD_RELOC_UNUSED;
2637 imm_reloc[1] = BFD_RELOC_UNUSED;
2638 imm_reloc[2] = BFD_RELOC_UNUSED;
2639 offset_reloc[0] = BFD_RELOC_UNUSED;
2640 offset_reloc[1] = BFD_RELOC_UNUSED;
2641 offset_reloc[2] = BFD_RELOC_UNUSED;
2643 mips_mark_labels ();
2644 mips_assembling_insn = TRUE;
2646 if (mips_opts.mips16)
2647 mips16_ip (str, &insn);
2650 mips_ip (str, &insn);
2651 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2652 str, insn.insn_opcode));
2656 as_bad ("%s `%s'", insn_error, str);
2657 else if (insn.insn_mo->pinfo == INSN_MACRO)
2660 if (mips_opts.mips16)
2661 mips16_macro (&insn);
2668 if (imm_expr.X_op != O_absent)
2669 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2670 else if (offset_expr.X_op != O_absent)
2671 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2673 append_insn (&insn, NULL, unused_reloc, FALSE);
2676 mips_assembling_insn = FALSE;
2679 /* Convenience functions for abstracting away the differences between
2680 MIPS16 and non-MIPS16 relocations. */
2682 static inline bfd_boolean
2683 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2687 case BFD_RELOC_MIPS16_JMP:
2688 case BFD_RELOC_MIPS16_GPREL:
2689 case BFD_RELOC_MIPS16_GOT16:
2690 case BFD_RELOC_MIPS16_CALL16:
2691 case BFD_RELOC_MIPS16_HI16_S:
2692 case BFD_RELOC_MIPS16_HI16:
2693 case BFD_RELOC_MIPS16_LO16:
2701 static inline bfd_boolean
2702 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2706 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2707 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2708 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2709 case BFD_RELOC_MICROMIPS_GPREL16:
2710 case BFD_RELOC_MICROMIPS_JMP:
2711 case BFD_RELOC_MICROMIPS_HI16:
2712 case BFD_RELOC_MICROMIPS_HI16_S:
2713 case BFD_RELOC_MICROMIPS_LO16:
2714 case BFD_RELOC_MICROMIPS_LITERAL:
2715 case BFD_RELOC_MICROMIPS_GOT16:
2716 case BFD_RELOC_MICROMIPS_CALL16:
2717 case BFD_RELOC_MICROMIPS_GOT_HI16:
2718 case BFD_RELOC_MICROMIPS_GOT_LO16:
2719 case BFD_RELOC_MICROMIPS_CALL_HI16:
2720 case BFD_RELOC_MICROMIPS_CALL_LO16:
2721 case BFD_RELOC_MICROMIPS_SUB:
2722 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2723 case BFD_RELOC_MICROMIPS_GOT_OFST:
2724 case BFD_RELOC_MICROMIPS_GOT_DISP:
2725 case BFD_RELOC_MICROMIPS_HIGHEST:
2726 case BFD_RELOC_MICROMIPS_HIGHER:
2727 case BFD_RELOC_MICROMIPS_SCN_DISP:
2728 case BFD_RELOC_MICROMIPS_JALR:
2736 static inline bfd_boolean
2737 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2739 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2742 static inline bfd_boolean
2743 got16_reloc_p (bfd_reloc_code_real_type reloc)
2745 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2746 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2749 static inline bfd_boolean
2750 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2752 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2753 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2756 static inline bfd_boolean
2757 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2759 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2760 || reloc == BFD_RELOC_MICROMIPS_LO16);
2763 static inline bfd_boolean
2764 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2766 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2769 /* Return true if RELOC is a PC-relative relocation that does not have
2770 full address range. */
2772 static inline bfd_boolean
2773 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
2777 case BFD_RELOC_16_PCREL_S2:
2778 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2779 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2780 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2783 case BFD_RELOC_32_PCREL:
2784 return HAVE_64BIT_ADDRESSES;
2791 /* Return true if the given relocation might need a matching %lo().
2792 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2793 need a matching %lo() when applied to local symbols. */
2795 static inline bfd_boolean
2796 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2798 return (HAVE_IN_PLACE_ADDENDS
2799 && (hi16_reloc_p (reloc)
2800 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2801 all GOT16 relocations evaluate to "G". */
2802 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2805 /* Return the type of %lo() reloc needed by RELOC, given that
2806 reloc_needs_lo_p. */
2808 static inline bfd_reloc_code_real_type
2809 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2811 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2812 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2816 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2819 static inline bfd_boolean
2820 fixup_has_matching_lo_p (fixS *fixp)
2822 return (fixp->fx_next != NULL
2823 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2824 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2825 && fixp->fx_offset == fixp->fx_next->fx_offset);
2828 /* This function returns true if modifying a register requires a
2832 reg_needs_delay (unsigned int reg)
2834 unsigned long prev_pinfo;
2836 prev_pinfo = history[0].insn_mo->pinfo;
2837 if (! mips_opts.noreorder
2838 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2839 && ! gpr_interlocks)
2840 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2841 && ! cop_interlocks)))
2843 /* A load from a coprocessor or from memory. All load delays
2844 delay the use of general register rt for one instruction. */
2845 /* Itbl support may require additional care here. */
2846 know (prev_pinfo & INSN_WRITE_GPR_T);
2847 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2854 /* Move all labels in LABELS to the current insertion point. TEXT_P
2855 says whether the labels refer to text or data. */
2858 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2860 struct insn_label_list *l;
2863 for (l = labels; l != NULL; l = l->next)
2865 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2866 symbol_set_frag (l->label, frag_now);
2867 val = (valueT) frag_now_fix ();
2868 /* MIPS16/microMIPS text labels are stored as odd. */
2869 if (text_p && HAVE_CODE_COMPRESSION)
2871 S_SET_VALUE (l->label, val);
2875 /* Move all labels in insn_labels to the current insertion point
2876 and treat them as text labels. */
2879 mips_move_text_labels (void)
2881 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2885 s_is_linkonce (symbolS *sym, segT from_seg)
2887 bfd_boolean linkonce = FALSE;
2888 segT symseg = S_GET_SEGMENT (sym);
2890 if (symseg != from_seg && !S_IS_LOCAL (sym))
2892 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2895 /* The GNU toolchain uses an extension for ELF: a section
2896 beginning with the magic string .gnu.linkonce is a
2897 linkonce section. */
2898 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2899 sizeof ".gnu.linkonce" - 1) == 0)
2906 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2907 linker to handle them specially, such as generating jalx instructions
2908 when needed. We also make them odd for the duration of the assembly,
2909 in order to generate the right sort of code. We will make them even
2910 in the adjust_symtab routine, while leaving them marked. This is
2911 convenient for the debugger and the disassembler. The linker knows
2912 to make them odd again. */
2915 mips_compressed_mark_label (symbolS *label)
2917 gas_assert (HAVE_CODE_COMPRESSION);
2919 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2922 if (mips_opts.mips16)
2923 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2925 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2928 if ((S_GET_VALUE (label) & 1) == 0
2929 /* Don't adjust the address if the label is global or weak, or
2930 in a link-once section, since we'll be emitting symbol reloc
2931 references to it which will be patched up by the linker, and
2932 the final value of the symbol may or may not be MIPS16/microMIPS. */
2933 && !S_IS_WEAK (label)
2934 && !S_IS_EXTERNAL (label)
2935 && !s_is_linkonce (label, now_seg))
2936 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2939 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2942 mips_compressed_mark_labels (void)
2944 struct insn_label_list *l;
2946 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2947 mips_compressed_mark_label (l->label);
2950 /* End the current frag. Make it a variant frag and record the
2954 relax_close_frag (void)
2956 mips_macro_warning.first_frag = frag_now;
2957 frag_var (rs_machine_dependent, 0, 0,
2958 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2959 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2961 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2962 mips_relax.first_fixup = 0;
2965 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2966 See the comment above RELAX_ENCODE for more details. */
2969 relax_start (symbolS *symbol)
2971 gas_assert (mips_relax.sequence == 0);
2972 mips_relax.sequence = 1;
2973 mips_relax.symbol = symbol;
2976 /* Start generating the second version of a relaxable sequence.
2977 See the comment above RELAX_ENCODE for more details. */
2982 gas_assert (mips_relax.sequence == 1);
2983 mips_relax.sequence = 2;
2986 /* End the current relaxable sequence. */
2991 gas_assert (mips_relax.sequence == 2);
2992 relax_close_frag ();
2993 mips_relax.sequence = 0;
2996 /* Return true if IP is a delayed branch or jump. */
2998 static inline bfd_boolean
2999 delayed_branch_p (const struct mips_cl_insn *ip)
3001 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3002 | INSN_COND_BRANCH_DELAY
3003 | INSN_COND_BRANCH_LIKELY)) != 0;
3006 /* Return true if IP is a compact branch or jump. */
3008 static inline bfd_boolean
3009 compact_branch_p (const struct mips_cl_insn *ip)
3011 if (mips_opts.mips16)
3012 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3013 | MIPS16_INSN_COND_BRANCH)) != 0;
3015 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3016 | INSN2_COND_BRANCH)) != 0;
3019 /* Return true if IP is an unconditional branch or jump. */
3021 static inline bfd_boolean
3022 uncond_branch_p (const struct mips_cl_insn *ip)
3024 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3025 || (mips_opts.mips16
3026 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3027 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3030 /* Return true if IP is a branch-likely instruction. */
3032 static inline bfd_boolean
3033 branch_likely_p (const struct mips_cl_insn *ip)
3035 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3038 /* Return the type of nop that should be used to fill the delay slot
3039 of delayed branch IP. */
3041 static struct mips_cl_insn *
3042 get_delay_slot_nop (const struct mips_cl_insn *ip)
3044 if (mips_opts.micromips
3045 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3046 return µmips_nop32_insn;
3050 /* Return the mask of core registers that IP reads or writes. */
3053 gpr_mod_mask (const struct mips_cl_insn *ip)
3055 unsigned long pinfo2;
3059 pinfo2 = ip->insn_mo->pinfo2;
3060 if (mips_opts.micromips)
3062 if (pinfo2 & INSN2_MOD_GPR_MD)
3063 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3064 if (pinfo2 & INSN2_MOD_GPR_MF)
3065 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3066 if (pinfo2 & INSN2_MOD_SP)
3072 /* Return the mask of core registers that IP reads. */
3075 gpr_read_mask (const struct mips_cl_insn *ip)
3077 unsigned long pinfo, pinfo2;
3080 mask = gpr_mod_mask (ip);
3081 pinfo = ip->insn_mo->pinfo;
3082 pinfo2 = ip->insn_mo->pinfo2;
3083 if (mips_opts.mips16)
3085 if (pinfo & MIPS16_INSN_READ_X)
3086 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3087 if (pinfo & MIPS16_INSN_READ_Y)
3088 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3089 if (pinfo & MIPS16_INSN_READ_T)
3091 if (pinfo & MIPS16_INSN_READ_SP)
3093 if (pinfo & MIPS16_INSN_READ_31)
3095 if (pinfo & MIPS16_INSN_READ_Z)
3096 mask |= 1 << (mips16_to_32_reg_map
3097 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3098 if (pinfo & MIPS16_INSN_READ_GPR_X)
3099 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3103 if (pinfo2 & INSN2_READ_GPR_D)
3104 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3105 if (pinfo & INSN_READ_GPR_T)
3106 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3107 if (pinfo & INSN_READ_GPR_S)
3108 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3109 if (pinfo2 & INSN2_READ_GP)
3111 if (pinfo2 & INSN2_READ_GPR_31)
3113 if (pinfo2 & INSN2_READ_GPR_Z)
3114 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3116 if (mips_opts.micromips)
3118 if (pinfo2 & INSN2_READ_GPR_MC)
3119 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3120 if (pinfo2 & INSN2_READ_GPR_ME)
3121 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3122 if (pinfo2 & INSN2_READ_GPR_MG)
3123 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3124 if (pinfo2 & INSN2_READ_GPR_MJ)
3125 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3126 if (pinfo2 & INSN2_READ_GPR_MMN)
3128 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3129 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3131 if (pinfo2 & INSN2_READ_GPR_MP)
3132 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3133 if (pinfo2 & INSN2_READ_GPR_MQ)
3134 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3136 /* Don't include register 0. */
3140 /* Return the mask of core registers that IP writes. */
3143 gpr_write_mask (const struct mips_cl_insn *ip)
3145 unsigned long pinfo, pinfo2;
3148 mask = gpr_mod_mask (ip);
3149 pinfo = ip->insn_mo->pinfo;
3150 pinfo2 = ip->insn_mo->pinfo2;
3151 if (mips_opts.mips16)
3153 if (pinfo & MIPS16_INSN_WRITE_X)
3154 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3155 if (pinfo & MIPS16_INSN_WRITE_Y)
3156 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3157 if (pinfo & MIPS16_INSN_WRITE_Z)
3158 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3159 if (pinfo & MIPS16_INSN_WRITE_T)
3161 if (pinfo & MIPS16_INSN_WRITE_SP)
3163 if (pinfo & MIPS16_INSN_WRITE_31)
3165 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3166 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3170 if (pinfo & INSN_WRITE_GPR_D)
3171 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3172 if (pinfo & INSN_WRITE_GPR_T)
3173 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3174 if (pinfo & INSN_WRITE_GPR_S)
3175 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3176 if (pinfo & INSN_WRITE_GPR_31)
3178 if (pinfo2 & INSN2_WRITE_GPR_Z)
3179 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3181 if (mips_opts.micromips)
3183 if (pinfo2 & INSN2_WRITE_GPR_MB)
3184 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3185 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3187 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3188 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3190 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3191 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3192 if (pinfo2 & INSN2_WRITE_GPR_MP)
3193 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3195 /* Don't include register 0. */
3199 /* Return the mask of floating-point registers that IP reads. */
3202 fpr_read_mask (const struct mips_cl_insn *ip)
3204 unsigned long pinfo, pinfo2;
3208 pinfo = ip->insn_mo->pinfo;
3209 pinfo2 = ip->insn_mo->pinfo2;
3210 if (!mips_opts.mips16)
3212 if (pinfo2 & INSN2_READ_FPR_D)
3213 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3214 if (pinfo & INSN_READ_FPR_S)
3215 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3216 if (pinfo & INSN_READ_FPR_T)
3217 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3218 if (pinfo & INSN_READ_FPR_R)
3219 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3220 if (pinfo2 & INSN2_READ_FPR_Z)
3221 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3223 /* Conservatively treat all operands to an FP_D instruction are doubles.
3224 (This is overly pessimistic for things like cvt.d.s.) */
3225 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3230 /* Return the mask of floating-point registers that IP writes. */
3233 fpr_write_mask (const struct mips_cl_insn *ip)
3235 unsigned long pinfo, pinfo2;
3239 pinfo = ip->insn_mo->pinfo;
3240 pinfo2 = ip->insn_mo->pinfo2;
3241 if (!mips_opts.mips16)
3243 if (pinfo & INSN_WRITE_FPR_D)
3244 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3245 if (pinfo & INSN_WRITE_FPR_S)
3246 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3247 if (pinfo & INSN_WRITE_FPR_T)
3248 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3249 if (pinfo2 & INSN2_WRITE_FPR_Z)
3250 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3252 /* Conservatively treat all operands to an FP_D instruction are doubles.
3253 (This is overly pessimistic for things like cvt.s.d.) */
3254 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3259 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3260 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3261 by VR4120 errata. */
3264 classify_vr4120_insn (const char *name)
3266 if (strncmp (name, "macc", 4) == 0)
3267 return FIX_VR4120_MACC;
3268 if (strncmp (name, "dmacc", 5) == 0)
3269 return FIX_VR4120_DMACC;
3270 if (strncmp (name, "mult", 4) == 0)
3271 return FIX_VR4120_MULT;
3272 if (strncmp (name, "dmult", 5) == 0)
3273 return FIX_VR4120_DMULT;
3274 if (strstr (name, "div"))
3275 return FIX_VR4120_DIV;
3276 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3277 return FIX_VR4120_MTHILO;
3278 return NUM_FIX_VR4120_CLASSES;
3281 #define INSN_ERET 0x42000018
3282 #define INSN_DERET 0x4200001f
3284 /* Return the number of instructions that must separate INSN1 and INSN2,
3285 where INSN1 is the earlier instruction. Return the worst-case value
3286 for any INSN2 if INSN2 is null. */
3289 insns_between (const struct mips_cl_insn *insn1,
3290 const struct mips_cl_insn *insn2)
3292 unsigned long pinfo1, pinfo2;
3295 /* This function needs to know which pinfo flags are set for INSN2
3296 and which registers INSN2 uses. The former is stored in PINFO2 and
3297 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3298 will have every flag set and INSN2_USES_GPR will always return true. */
3299 pinfo1 = insn1->insn_mo->pinfo;
3300 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3302 #define INSN2_USES_GPR(REG) \
3303 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3305 /* For most targets, write-after-read dependencies on the HI and LO
3306 registers must be separated by at least two instructions. */
3307 if (!hilo_interlocks)
3309 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3311 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3315 /* If we're working around r7000 errata, there must be two instructions
3316 between an mfhi or mflo and any instruction that uses the result. */
3317 if (mips_7000_hilo_fix
3318 && !mips_opts.micromips
3319 && MF_HILO_INSN (pinfo1)
3320 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3323 /* If we're working around 24K errata, one instruction is required
3324 if an ERET or DERET is followed by a branch instruction. */
3325 if (mips_fix_24k && !mips_opts.micromips)
3327 if (insn1->insn_opcode == INSN_ERET
3328 || insn1->insn_opcode == INSN_DERET)
3331 || insn2->insn_opcode == INSN_ERET
3332 || insn2->insn_opcode == INSN_DERET
3333 || delayed_branch_p (insn2))
3338 /* If working around VR4120 errata, check for combinations that need
3339 a single intervening instruction. */
3340 if (mips_fix_vr4120 && !mips_opts.micromips)
3342 unsigned int class1, class2;
3344 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3345 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3349 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3350 if (vr4120_conflicts[class1] & (1 << class2))
3355 if (!HAVE_CODE_COMPRESSION)
3357 /* Check for GPR or coprocessor load delays. All such delays
3358 are on the RT register. */
3359 /* Itbl support may require additional care here. */
3360 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3361 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3363 know (pinfo1 & INSN_WRITE_GPR_T);
3364 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3368 /* Check for generic coprocessor hazards.
3370 This case is not handled very well. There is no special
3371 knowledge of CP0 handling, and the coprocessors other than
3372 the floating point unit are not distinguished at all. */
3373 /* Itbl support may require additional care here. FIXME!
3374 Need to modify this to include knowledge about
3375 user specified delays! */
3376 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3377 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3379 /* Handle cases where INSN1 writes to a known general coprocessor
3380 register. There must be a one instruction delay before INSN2
3381 if INSN2 reads that register, otherwise no delay is needed. */
3382 mask = fpr_write_mask (insn1);
3385 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3390 /* Read-after-write dependencies on the control registers
3391 require a two-instruction gap. */
3392 if ((pinfo1 & INSN_WRITE_COND_CODE)
3393 && (pinfo2 & INSN_READ_COND_CODE))
3396 /* We don't know exactly what INSN1 does. If INSN2 is
3397 also a coprocessor instruction, assume there must be
3398 a one instruction gap. */
3399 if (pinfo2 & INSN_COP)
3404 /* Check for read-after-write dependencies on the coprocessor
3405 control registers in cases where INSN1 does not need a general
3406 coprocessor delay. This means that INSN1 is a floating point
3407 comparison instruction. */
3408 /* Itbl support may require additional care here. */
3409 else if (!cop_interlocks
3410 && (pinfo1 & INSN_WRITE_COND_CODE)
3411 && (pinfo2 & INSN_READ_COND_CODE))
3415 #undef INSN2_USES_GPR
3420 /* Return the number of nops that would be needed to work around the
3421 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3422 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3423 that are contained within the first IGNORE instructions of HIST. */
3426 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3427 const struct mips_cl_insn *insn)
3432 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3433 are not affected by the errata. */
3435 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3436 || strcmp (insn->insn_mo->name, "mtlo") == 0
3437 || strcmp (insn->insn_mo->name, "mthi") == 0))
3440 /* Search for the first MFLO or MFHI. */
3441 for (i = 0; i < MAX_VR4130_NOPS; i++)
3442 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3444 /* Extract the destination register. */
3445 mask = gpr_write_mask (&hist[i]);
3447 /* No nops are needed if INSN reads that register. */
3448 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3451 /* ...or if any of the intervening instructions do. */
3452 for (j = 0; j < i; j++)
3453 if (gpr_read_mask (&hist[j]) & mask)
3457 return MAX_VR4130_NOPS - i;
3462 #define BASE_REG_EQ(INSN1, INSN2) \
3463 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3464 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3466 /* Return the minimum alignment for this store instruction. */
3469 fix_24k_align_to (const struct mips_opcode *mo)
3471 if (strcmp (mo->name, "sh") == 0)
3474 if (strcmp (mo->name, "swc1") == 0
3475 || strcmp (mo->name, "swc2") == 0
3476 || strcmp (mo->name, "sw") == 0
3477 || strcmp (mo->name, "sc") == 0
3478 || strcmp (mo->name, "s.s") == 0)
3481 if (strcmp (mo->name, "sdc1") == 0
3482 || strcmp (mo->name, "sdc2") == 0
3483 || strcmp (mo->name, "s.d") == 0)
3490 struct fix_24k_store_info
3492 /* Immediate offset, if any, for this store instruction. */
3494 /* Alignment required by this store instruction. */
3496 /* True for register offsets. */
3497 int register_offset;
3500 /* Comparison function used by qsort. */
3503 fix_24k_sort (const void *a, const void *b)
3505 const struct fix_24k_store_info *pos1 = a;
3506 const struct fix_24k_store_info *pos2 = b;
3508 return (pos1->off - pos2->off);
3511 /* INSN is a store instruction. Try to record the store information
3512 in STINFO. Return false if the information isn't known. */
3515 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3516 const struct mips_cl_insn *insn)
3518 /* The instruction must have a known offset. */
3519 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3522 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3523 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3527 /* Return the number of nops that would be needed to work around the 24k
3528 "lost data on stores during refill" errata if instruction INSN
3529 immediately followed the 2 instructions described by HIST.
3530 Ignore hazards that are contained within the first IGNORE
3531 instructions of HIST.
3533 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3534 for the data cache refills and store data. The following describes
3535 the scenario where the store data could be lost.
3537 * A data cache miss, due to either a load or a store, causing fill
3538 data to be supplied by the memory subsystem
3539 * The first three doublewords of fill data are returned and written
3541 * A sequence of four stores occurs in consecutive cycles around the
3542 final doubleword of the fill:
3546 * Zero, One or more instructions
3549 The four stores A-D must be to different doublewords of the line that
3550 is being filled. The fourth instruction in the sequence above permits
3551 the fill of the final doubleword to be transferred from the FSB into
3552 the cache. In the sequence above, the stores may be either integer
3553 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3554 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3555 different doublewords on the line. If the floating point unit is
3556 running in 1:2 mode, it is not possible to create the sequence above
3557 using only floating point store instructions.
3559 In this case, the cache line being filled is incorrectly marked
3560 invalid, thereby losing the data from any store to the line that
3561 occurs between the original miss and the completion of the five
3562 cycle sequence shown above.
3564 The workarounds are:
3566 * Run the data cache in write-through mode.
3567 * Insert a non-store instruction between
3568 Store A and Store B or Store B and Store C. */
3571 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3572 const struct mips_cl_insn *insn)
3574 struct fix_24k_store_info pos[3];
3575 int align, i, base_offset;
3580 /* If the previous instruction wasn't a store, there's nothing to
3582 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3585 /* If the instructions after the previous one are unknown, we have
3586 to assume the worst. */
3590 /* Check whether we are dealing with three consecutive stores. */
3591 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3592 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3595 /* If we don't know the relationship between the store addresses,
3596 assume the worst. */
3597 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3598 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3601 if (!fix_24k_record_store_info (&pos[0], insn)
3602 || !fix_24k_record_store_info (&pos[1], &hist[0])
3603 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3606 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3608 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3609 X bytes and such that the base register + X is known to be aligned
3612 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3616 align = pos[0].align_to;
3617 base_offset = pos[0].off;
3618 for (i = 1; i < 3; i++)
3619 if (align < pos[i].align_to)
3621 align = pos[i].align_to;
3622 base_offset = pos[i].off;
3624 for (i = 0; i < 3; i++)
3625 pos[i].off -= base_offset;
3628 pos[0].off &= ~align + 1;
3629 pos[1].off &= ~align + 1;
3630 pos[2].off &= ~align + 1;
3632 /* If any two stores write to the same chunk, they also write to the
3633 same doubleword. The offsets are still sorted at this point. */
3634 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3637 /* A range of at least 9 bytes is needed for the stores to be in
3638 non-overlapping doublewords. */
3639 if (pos[2].off - pos[0].off <= 8)
3642 if (pos[2].off - pos[1].off >= 24
3643 || pos[1].off - pos[0].off >= 24
3644 || pos[2].off - pos[0].off >= 32)
3650 /* Return the number of nops that would be needed if instruction INSN
3651 immediately followed the MAX_NOPS instructions given by HIST,
3652 where HIST[0] is the most recent instruction. Ignore hazards
3653 between INSN and the first IGNORE instructions in HIST.
3655 If INSN is null, return the worse-case number of nops for any
3659 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3660 const struct mips_cl_insn *insn)
3662 int i, nops, tmp_nops;
3665 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3667 tmp_nops = insns_between (hist + i, insn) - i;
3668 if (tmp_nops > nops)
3672 if (mips_fix_vr4130 && !mips_opts.micromips)
3674 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3675 if (tmp_nops > nops)
3679 if (mips_fix_24k && !mips_opts.micromips)
3681 tmp_nops = nops_for_24k (ignore, hist, insn);
3682 if (tmp_nops > nops)
3689 /* The variable arguments provide NUM_INSNS extra instructions that
3690 might be added to HIST. Return the largest number of nops that
3691 would be needed after the extended sequence, ignoring hazards
3692 in the first IGNORE instructions. */
3695 nops_for_sequence (int num_insns, int ignore,
3696 const struct mips_cl_insn *hist, ...)
3699 struct mips_cl_insn buffer[MAX_NOPS];
3700 struct mips_cl_insn *cursor;
3703 va_start (args, hist);
3704 cursor = buffer + num_insns;
3705 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3706 while (cursor > buffer)
3707 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3709 nops = nops_for_insn (ignore, buffer, NULL);
3714 /* Like nops_for_insn, but if INSN is a branch, take into account the
3715 worst-case delay for the branch target. */
3718 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3719 const struct mips_cl_insn *insn)
3723 nops = nops_for_insn (ignore, hist, insn);
3724 if (delayed_branch_p (insn))
3726 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3727 hist, insn, get_delay_slot_nop (insn));
3728 if (tmp_nops > nops)
3731 else if (compact_branch_p (insn))
3733 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3734 if (tmp_nops > nops)
3740 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3743 fix_loongson2f_nop (struct mips_cl_insn * ip)
3745 gas_assert (!HAVE_CODE_COMPRESSION);
3746 if (strcmp (ip->insn_mo->name, "nop") == 0)
3747 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3750 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3751 jr target pc &= 'hffff_ffff_cfff_ffff. */
3754 fix_loongson2f_jump (struct mips_cl_insn * ip)
3756 gas_assert (!HAVE_CODE_COMPRESSION);
3757 if (strcmp (ip->insn_mo->name, "j") == 0
3758 || strcmp (ip->insn_mo->name, "jr") == 0
3759 || strcmp (ip->insn_mo->name, "jalr") == 0)
3767 sreg = EXTRACT_OPERAND (0, RS, *ip);
3768 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3771 ep.X_op = O_constant;
3772 ep.X_add_number = 0xcfff0000;
3773 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3774 ep.X_add_number = 0xffff;
3775 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3776 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3781 fix_loongson2f (struct mips_cl_insn * ip)
3783 if (mips_fix_loongson2f_nop)
3784 fix_loongson2f_nop (ip);
3786 if (mips_fix_loongson2f_jump)
3787 fix_loongson2f_jump (ip);
3790 /* IP is a branch that has a delay slot, and we need to fill it
3791 automatically. Return true if we can do that by swapping IP
3792 with the previous instruction.
3793 ADDRESS_EXPR is an operand of the instruction to be used with
3797 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3798 bfd_reloc_code_real_type *reloc_type)
3800 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3801 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3803 /* -O2 and above is required for this optimization. */
3804 if (mips_optimize < 2)
3807 /* If we have seen .set volatile or .set nomove, don't optimize. */
3808 if (mips_opts.nomove)
3811 /* We can't swap if the previous instruction's position is fixed. */
3812 if (history[0].fixed_p)
3815 /* If the previous previous insn was in a .set noreorder, we can't
3816 swap. Actually, the MIPS assembler will swap in this situation.
3817 However, gcc configured -with-gnu-as will generate code like
3825 in which we can not swap the bne and INSN. If gcc is not configured
3826 -with-gnu-as, it does not output the .set pseudo-ops. */
3827 if (history[1].noreorder_p)
3830 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3831 This means that the previous instruction was a 4-byte one anyhow. */
3832 if (mips_opts.mips16 && history[0].fixp[0])
3835 /* If the branch is itself the target of a branch, we can not swap.
3836 We cheat on this; all we check for is whether there is a label on
3837 this instruction. If there are any branches to anything other than
3838 a label, users must use .set noreorder. */
3839 if (seg_info (now_seg)->label_list)
3842 /* If the previous instruction is in a variant frag other than this
3843 branch's one, we cannot do the swap. This does not apply to
3844 MIPS16 code, which uses variant frags for different purposes. */
3845 if (!mips_opts.mips16
3847 && history[0].frag->fr_type == rs_machine_dependent)
3850 /* We do not swap with instructions that cannot architecturally
3851 be placed in a branch delay slot, such as SYNC or ERET. We
3852 also refrain from swapping with a trap instruction, since it
3853 complicates trap handlers to have the trap instruction be in
3855 prev_pinfo = history[0].insn_mo->pinfo;
3856 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3859 /* Check for conflicts between the branch and the instructions
3860 before the candidate delay slot. */
3861 if (nops_for_insn (0, history + 1, ip) > 0)
3864 /* Check for conflicts between the swapped sequence and the
3865 target of the branch. */
3866 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3869 /* If the branch reads a register that the previous
3870 instruction sets, we can not swap. */
3871 gpr_read = gpr_read_mask (ip);
3872 prev_gpr_write = gpr_write_mask (&history[0]);
3873 if (gpr_read & prev_gpr_write)
3876 /* If the branch writes a register that the previous
3877 instruction sets, we can not swap. */
3878 gpr_write = gpr_write_mask (ip);
3879 if (gpr_write & prev_gpr_write)
3882 /* If the branch writes a register that the previous
3883 instruction reads, we can not swap. */
3884 prev_gpr_read = gpr_read_mask (&history[0]);
3885 if (gpr_write & prev_gpr_read)
3888 /* If one instruction sets a condition code and the
3889 other one uses a condition code, we can not swap. */
3890 pinfo = ip->insn_mo->pinfo;
3891 if ((pinfo & INSN_READ_COND_CODE)
3892 && (prev_pinfo & INSN_WRITE_COND_CODE))
3894 if ((pinfo & INSN_WRITE_COND_CODE)
3895 && (prev_pinfo & INSN_READ_COND_CODE))
3898 /* If the previous instruction uses the PC, we can not swap. */
3899 prev_pinfo2 = history[0].insn_mo->pinfo2;
3900 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3902 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3905 /* If the previous instruction has an incorrect size for a fixed
3906 branch delay slot in microMIPS mode, we cannot swap. */
3907 pinfo2 = ip->insn_mo->pinfo2;
3908 if (mips_opts.micromips
3909 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3910 && insn_length (history) != 2)
3912 if (mips_opts.micromips
3913 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3914 && insn_length (history) != 4)
3917 /* On R5900 short loops need to be fixed by inserting a nop in
3918 the branch delay slots.
3919 A short loop can be terminated too early. */
3920 if (mips_opts.arch == CPU_R5900
3921 /* Check if instruction has a parameter, ignore "j $31". */
3922 && (address_expr != NULL)
3923 /* Parameter must be 16 bit. */
3924 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3925 /* Branch to same segment. */
3926 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3927 /* Branch to same code fragment. */
3928 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3929 /* Can only calculate branch offset if value is known. */
3930 && symbol_constant_p(address_expr->X_add_symbol)
3931 /* Check if branch is really conditional. */
3932 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3933 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3934 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3937 /* Check if loop is shorter than 6 instructions including
3938 branch and delay slot. */
3939 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3946 /* When the loop includes branches or jumps,
3947 it is not a short loop. */
3948 for (i = 0; i < (distance / 4); i++)
3950 if ((history[i].cleared_p)
3951 || delayed_branch_p(&history[i]))
3959 /* Insert nop after branch to fix short loop. */
3968 /* Decide how we should add IP to the instruction stream.
3969 ADDRESS_EXPR is an operand of the instruction to be used with
3972 static enum append_method
3973 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3974 bfd_reloc_code_real_type *reloc_type)
3976 unsigned long pinfo;
3978 /* The relaxed version of a macro sequence must be inherently
3980 if (mips_relax.sequence == 2)
3983 /* We must not dabble with instructions in a ".set norerorder" block. */
3984 if (mips_opts.noreorder)
3987 /* Otherwise, it's our responsibility to fill branch delay slots. */
3988 if (delayed_branch_p (ip))
3990 if (!branch_likely_p (ip)
3991 && can_swap_branch_p (ip, address_expr, reloc_type))
3994 pinfo = ip->insn_mo->pinfo;
3995 if (mips_opts.mips16
3996 && ISA_SUPPORTS_MIPS16E
3997 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3998 return APPEND_ADD_COMPACT;
4000 return APPEND_ADD_WITH_NOP;
4006 /* IP is a MIPS16 instruction whose opcode we have just changed.
4007 Point IP->insn_mo to the new opcode's definition. */
4010 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4012 const struct mips_opcode *mo, *end;
4014 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4015 for (mo = ip->insn_mo; mo < end; mo++)
4016 if ((ip->insn_opcode & mo->mask) == mo->match)
4024 /* For microMIPS macros, we need to generate a local number label
4025 as the target of branches. */
4026 #define MICROMIPS_LABEL_CHAR '\037'
4027 static unsigned long micromips_target_label;
4028 static char micromips_target_name[32];
4031 micromips_label_name (void)
4033 char *p = micromips_target_name;
4034 char symbol_name_temporary[24];
4042 l = micromips_target_label;
4043 #ifdef LOCAL_LABEL_PREFIX
4044 *p++ = LOCAL_LABEL_PREFIX;
4047 *p++ = MICROMIPS_LABEL_CHAR;
4050 symbol_name_temporary[i++] = l % 10 + '0';
4055 *p++ = symbol_name_temporary[--i];
4058 return micromips_target_name;
4062 micromips_label_expr (expressionS *label_expr)
4064 label_expr->X_op = O_symbol;
4065 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4066 label_expr->X_add_number = 0;
4070 micromips_label_inc (void)
4072 micromips_target_label++;
4073 *micromips_target_name = '\0';
4077 micromips_add_label (void)
4081 s = colon (micromips_label_name ());
4082 micromips_label_inc ();
4083 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4085 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4091 /* If assembling microMIPS code, then return the microMIPS reloc
4092 corresponding to the requested one if any. Otherwise return
4093 the reloc unchanged. */
4095 static bfd_reloc_code_real_type
4096 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4098 static const bfd_reloc_code_real_type relocs[][2] =
4100 /* Keep sorted incrementally by the left-hand key. */
4101 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4102 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4103 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4104 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4105 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4106 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4107 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4108 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4109 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4110 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4111 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4112 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4113 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4114 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4115 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4116 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4117 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4118 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4119 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4120 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4121 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4122 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4123 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4124 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4125 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4126 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4127 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4129 bfd_reloc_code_real_type r;
4132 if (!mips_opts.micromips)
4134 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4140 return relocs[i][1];
4145 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4146 Return true on success, storing the resolved value in RESULT. */
4149 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4154 case BFD_RELOC_MIPS_HIGHEST:
4155 case BFD_RELOC_MICROMIPS_HIGHEST:
4156 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4159 case BFD_RELOC_MIPS_HIGHER:
4160 case BFD_RELOC_MICROMIPS_HIGHER:
4161 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4164 case BFD_RELOC_HI16_S:
4165 case BFD_RELOC_MICROMIPS_HI16_S:
4166 case BFD_RELOC_MIPS16_HI16_S:
4167 *result = ((operand + 0x8000) >> 16) & 0xffff;
4170 case BFD_RELOC_HI16:
4171 case BFD_RELOC_MICROMIPS_HI16:
4172 case BFD_RELOC_MIPS16_HI16:
4173 *result = (operand >> 16) & 0xffff;
4176 case BFD_RELOC_LO16:
4177 case BFD_RELOC_MICROMIPS_LO16:
4178 case BFD_RELOC_MIPS16_LO16:
4179 *result = operand & 0xffff;
4182 case BFD_RELOC_UNUSED:
4191 /* Output an instruction. IP is the instruction information.
4192 ADDRESS_EXPR is an operand of the instruction to be used with
4193 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4194 a macro expansion. */
4197 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4198 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4200 unsigned long prev_pinfo2, pinfo;
4201 bfd_boolean relaxed_branch = FALSE;
4202 enum append_method method;
4203 bfd_boolean relax32;
4206 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4207 fix_loongson2f (ip);
4209 file_ase_mips16 |= mips_opts.mips16;
4210 file_ase_micromips |= mips_opts.micromips;
4212 prev_pinfo2 = history[0].insn_mo->pinfo2;
4213 pinfo = ip->insn_mo->pinfo;
4215 if (mips_opts.micromips
4217 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4218 && micromips_insn_length (ip->insn_mo) != 2)
4219 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4220 && micromips_insn_length (ip->insn_mo) != 4)))
4221 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4222 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4224 if (address_expr == NULL)
4226 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4227 && reloc_type[1] == BFD_RELOC_UNUSED
4228 && reloc_type[2] == BFD_RELOC_UNUSED
4229 && address_expr->X_op == O_constant)
4231 switch (*reloc_type)
4233 case BFD_RELOC_MIPS_JMP:
4237 shift = mips_opts.micromips ? 1 : 2;
4238 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4239 as_bad (_("jump to misaligned address (0x%lx)"),
4240 (unsigned long) address_expr->X_add_number);
4241 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4247 case BFD_RELOC_MIPS16_JMP:
4248 if ((address_expr->X_add_number & 3) != 0)
4249 as_bad (_("jump to misaligned address (0x%lx)"),
4250 (unsigned long) address_expr->X_add_number);
4252 (((address_expr->X_add_number & 0x7c0000) << 3)
4253 | ((address_expr->X_add_number & 0xf800000) >> 7)
4254 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4258 case BFD_RELOC_16_PCREL_S2:
4262 shift = mips_opts.micromips ? 1 : 2;
4263 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4264 as_bad (_("branch to misaligned address (0x%lx)"),
4265 (unsigned long) address_expr->X_add_number);
4266 if (!mips_relax_branch)
4268 if ((address_expr->X_add_number + (1 << (shift + 15)))
4269 & ~((1 << (shift + 16)) - 1))
4270 as_bad (_("branch address range overflow (0x%lx)"),
4271 (unsigned long) address_expr->X_add_number);
4272 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4282 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4285 ip->insn_opcode |= value & 0xffff;
4293 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4295 /* There are a lot of optimizations we could do that we don't.
4296 In particular, we do not, in general, reorder instructions.
4297 If you use gcc with optimization, it will reorder
4298 instructions and generally do much more optimization then we
4299 do here; repeating all that work in the assembler would only
4300 benefit hand written assembly code, and does not seem worth
4302 int nops = (mips_optimize == 0
4303 ? nops_for_insn (0, history, NULL)
4304 : nops_for_insn_or_target (0, history, ip));
4308 unsigned long old_frag_offset;
4311 old_frag = frag_now;
4312 old_frag_offset = frag_now_fix ();
4314 for (i = 0; i < nops; i++)
4315 add_fixed_insn (NOP_INSN);
4316 insert_into_history (0, nops, NOP_INSN);
4320 listing_prev_line ();
4321 /* We may be at the start of a variant frag. In case we
4322 are, make sure there is enough space for the frag
4323 after the frags created by listing_prev_line. The
4324 argument to frag_grow here must be at least as large
4325 as the argument to all other calls to frag_grow in
4326 this file. We don't have to worry about being in the
4327 middle of a variant frag, because the variants insert
4328 all needed nop instructions themselves. */
4332 mips_move_text_labels ();
4334 #ifndef NO_ECOFF_DEBUGGING
4335 if (ECOFF_DEBUGGING)
4336 ecoff_fix_loc (old_frag, old_frag_offset);
4340 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4344 /* Work out how many nops in prev_nop_frag are needed by IP,
4345 ignoring hazards generated by the first prev_nop_frag_since
4347 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4348 gas_assert (nops <= prev_nop_frag_holds);
4350 /* Enforce NOPS as a minimum. */
4351 if (nops > prev_nop_frag_required)
4352 prev_nop_frag_required = nops;
4354 if (prev_nop_frag_holds == prev_nop_frag_required)
4356 /* Settle for the current number of nops. Update the history
4357 accordingly (for the benefit of any future .set reorder code). */
4358 prev_nop_frag = NULL;
4359 insert_into_history (prev_nop_frag_since,
4360 prev_nop_frag_holds, NOP_INSN);
4364 /* Allow this instruction to replace one of the nops that was
4365 tentatively added to prev_nop_frag. */
4366 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4367 prev_nop_frag_holds--;
4368 prev_nop_frag_since++;
4372 method = get_append_method (ip, address_expr, reloc_type);
4373 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4376 /* The value passed to dwarf2_emit_insn is the distance between
4377 the beginning of the current instruction and the address that
4378 should be recorded in the debug tables. This is normally the
4381 For MIPS16/microMIPS debug info we want to use ISA-encoded
4382 addresses, so we use -1 for an address higher by one than the
4385 If the instruction produced is a branch that we will swap with
4386 the preceding instruction, then we add the displacement by which
4387 the branch will be moved backwards. This is more appropriate
4388 and for MIPS16/microMIPS code also prevents a debugger from
4389 placing a breakpoint in the middle of the branch (and corrupting
4390 code if software breakpoints are used). */
4391 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4394 relax32 = (mips_relax_branch
4395 /* Don't try branch relaxation within .set nomacro, or within
4396 .set noat if we use $at for PIC computations. If it turns
4397 out that the branch was out-of-range, we'll get an error. */
4398 && !mips_opts.warn_about_macros
4399 && (mips_opts.at || mips_pic == NO_PIC)
4400 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4401 as they have no complementing branches. */
4402 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4404 if (!HAVE_CODE_COMPRESSION
4407 && *reloc_type == BFD_RELOC_16_PCREL_S2
4408 && delayed_branch_p (ip))
4410 relaxed_branch = TRUE;
4411 add_relaxed_insn (ip, (relaxed_branch_length
4413 uncond_branch_p (ip) ? -1
4414 : branch_likely_p (ip) ? 1
4418 uncond_branch_p (ip),
4419 branch_likely_p (ip),
4420 pinfo & INSN_WRITE_GPR_31,
4422 address_expr->X_add_symbol,
4423 address_expr->X_add_number);
4424 *reloc_type = BFD_RELOC_UNUSED;
4426 else if (mips_opts.micromips
4428 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4429 || *reloc_type > BFD_RELOC_UNUSED)
4430 && (delayed_branch_p (ip) || compact_branch_p (ip))
4431 /* Don't try branch relaxation when users specify
4432 16-bit/32-bit instructions. */
4433 && !forced_insn_length)
4435 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4436 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4437 int uncond = uncond_branch_p (ip) ? -1 : 0;
4438 int compact = compact_branch_p (ip);
4439 int al = pinfo & INSN_WRITE_GPR_31;
4442 gas_assert (address_expr != NULL);
4443 gas_assert (!mips_relax.sequence);
4445 relaxed_branch = TRUE;
4446 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4447 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4448 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4450 address_expr->X_add_symbol,
4451 address_expr->X_add_number);
4452 *reloc_type = BFD_RELOC_UNUSED;
4454 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4456 /* We need to set up a variant frag. */
4457 gas_assert (address_expr != NULL);
4458 add_relaxed_insn (ip, 4, 0,
4460 (*reloc_type - BFD_RELOC_UNUSED,
4461 forced_insn_length == 2, forced_insn_length == 4,
4462 delayed_branch_p (&history[0]),
4463 history[0].mips16_absolute_jump_p),
4464 make_expr_symbol (address_expr), 0);
4466 else if (mips_opts.mips16 && insn_length (ip) == 2)
4468 if (!delayed_branch_p (ip))
4469 /* Make sure there is enough room to swap this instruction with
4470 a following jump instruction. */
4472 add_fixed_insn (ip);
4476 if (mips_opts.mips16
4477 && mips_opts.noreorder
4478 && delayed_branch_p (&history[0]))
4479 as_warn (_("extended instruction in delay slot"));
4481 if (mips_relax.sequence)
4483 /* If we've reached the end of this frag, turn it into a variant
4484 frag and record the information for the instructions we've
4486 if (frag_room () < 4)
4487 relax_close_frag ();
4488 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4491 if (mips_relax.sequence != 2)
4493 if (mips_macro_warning.first_insn_sizes[0] == 0)
4494 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4495 mips_macro_warning.sizes[0] += insn_length (ip);
4496 mips_macro_warning.insns[0]++;
4498 if (mips_relax.sequence != 1)
4500 if (mips_macro_warning.first_insn_sizes[1] == 0)
4501 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4502 mips_macro_warning.sizes[1] += insn_length (ip);
4503 mips_macro_warning.insns[1]++;
4506 if (mips_opts.mips16)
4509 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4511 add_fixed_insn (ip);
4514 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4516 bfd_reloc_code_real_type final_type[3];
4517 reloc_howto_type *howto0;
4518 reloc_howto_type *howto;
4521 /* Perform any necessary conversion to microMIPS relocations
4522 and find out how many relocations there actually are. */
4523 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4524 final_type[i] = micromips_map_reloc (reloc_type[i]);
4526 /* In a compound relocation, it is the final (outermost)
4527 operator that determines the relocated field. */
4528 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4532 /* To reproduce this failure try assembling gas/testsuites/
4533 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4535 as_bad (_("Unsupported MIPS relocation number %d"),
4537 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4541 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4542 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4543 bfd_get_reloc_size (howto),
4545 howto0 && howto0->pc_relative,
4548 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4549 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4550 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4552 /* These relocations can have an addend that won't fit in
4553 4 octets for 64bit assembly. */
4555 && ! howto->partial_inplace
4556 && (reloc_type[0] == BFD_RELOC_16
4557 || reloc_type[0] == BFD_RELOC_32
4558 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4559 || reloc_type[0] == BFD_RELOC_GPREL16
4560 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4561 || reloc_type[0] == BFD_RELOC_GPREL32
4562 || reloc_type[0] == BFD_RELOC_64
4563 || reloc_type[0] == BFD_RELOC_CTOR
4564 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4565 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4566 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4567 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4568 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4569 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4570 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4571 || hi16_reloc_p (reloc_type[0])
4572 || lo16_reloc_p (reloc_type[0])))
4573 ip->fixp[0]->fx_no_overflow = 1;
4575 /* These relocations can have an addend that won't fit in 2 octets. */
4576 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4577 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4578 ip->fixp[0]->fx_no_overflow = 1;
4580 if (mips_relax.sequence)
4582 if (mips_relax.first_fixup == 0)
4583 mips_relax.first_fixup = ip->fixp[0];
4585 else if (reloc_needs_lo_p (*reloc_type))
4587 struct mips_hi_fixup *hi_fixup;
4589 /* Reuse the last entry if it already has a matching %lo. */
4590 hi_fixup = mips_hi_fixup_list;
4592 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4594 hi_fixup = ((struct mips_hi_fixup *)
4595 xmalloc (sizeof (struct mips_hi_fixup)));
4596 hi_fixup->next = mips_hi_fixup_list;
4597 mips_hi_fixup_list = hi_fixup;
4599 hi_fixup->fixp = ip->fixp[0];
4600 hi_fixup->seg = now_seg;
4603 /* Add fixups for the second and third relocations, if given.
4604 Note that the ABI allows the second relocation to be
4605 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4606 moment we only use RSS_UNDEF, but we could add support
4607 for the others if it ever becomes necessary. */
4608 for (i = 1; i < 3; i++)
4609 if (reloc_type[i] != BFD_RELOC_UNUSED)
4611 ip->fixp[i] = fix_new (ip->frag, ip->where,
4612 ip->fixp[0]->fx_size, NULL, 0,
4613 FALSE, final_type[i]);
4615 /* Use fx_tcbit to mark compound relocs. */
4616 ip->fixp[0]->fx_tcbit = 1;
4617 ip->fixp[i]->fx_tcbit = 1;
4622 /* Update the register mask information. */
4623 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4624 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4629 insert_into_history (0, 1, ip);
4632 case APPEND_ADD_WITH_NOP:
4634 struct mips_cl_insn *nop;
4636 insert_into_history (0, 1, ip);
4637 nop = get_delay_slot_nop (ip);
4638 add_fixed_insn (nop);
4639 insert_into_history (0, 1, nop);
4640 if (mips_relax.sequence)
4641 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4645 case APPEND_ADD_COMPACT:
4646 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4647 gas_assert (mips_opts.mips16);
4648 ip->insn_opcode |= 0x0080;
4649 find_altered_mips16_opcode (ip);
4651 insert_into_history (0, 1, ip);
4656 struct mips_cl_insn delay = history[0];
4657 if (mips_opts.mips16)
4659 know (delay.frag == ip->frag);
4660 move_insn (ip, delay.frag, delay.where);
4661 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4663 else if (relaxed_branch || delay.frag != ip->frag)
4665 /* Add the delay slot instruction to the end of the
4666 current frag and shrink the fixed part of the
4667 original frag. If the branch occupies the tail of
4668 the latter, move it backwards to cover the gap. */
4669 delay.frag->fr_fix -= branch_disp;
4670 if (delay.frag == ip->frag)
4671 move_insn (ip, ip->frag, ip->where - branch_disp);
4672 add_fixed_insn (&delay);
4676 move_insn (&delay, ip->frag,
4677 ip->where - branch_disp + insn_length (ip));
4678 move_insn (ip, history[0].frag, history[0].where);
4682 insert_into_history (0, 1, &delay);
4687 /* If we have just completed an unconditional branch, clear the history. */
4688 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4689 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4693 mips_no_prev_insn ();
4695 for (i = 0; i < ARRAY_SIZE (history); i++)
4696 history[i].cleared_p = 1;
4699 /* We need to emit a label at the end of branch-likely macros. */
4700 if (emit_branch_likely_macro)
4702 emit_branch_likely_macro = FALSE;
4703 micromips_add_label ();
4706 /* We just output an insn, so the next one doesn't have a label. */
4707 mips_clear_insn_labels ();
4710 /* Forget that there was any previous instruction or label.
4711 When BRANCH is true, the branch history is also flushed. */
4714 mips_no_prev_insn (void)
4716 prev_nop_frag = NULL;
4717 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4718 mips_clear_insn_labels ();
4721 /* This function must be called before we emit something other than
4722 instructions. It is like mips_no_prev_insn except that it inserts
4723 any NOPS that might be needed by previous instructions. */
4726 mips_emit_delays (void)
4728 if (! mips_opts.noreorder)
4730 int nops = nops_for_insn (0, history, NULL);
4734 add_fixed_insn (NOP_INSN);
4735 mips_move_text_labels ();
4738 mips_no_prev_insn ();
4741 /* Start a (possibly nested) noreorder block. */
4744 start_noreorder (void)
4746 if (mips_opts.noreorder == 0)
4751 /* None of the instructions before the .set noreorder can be moved. */
4752 for (i = 0; i < ARRAY_SIZE (history); i++)
4753 history[i].fixed_p = 1;
4755 /* Insert any nops that might be needed between the .set noreorder
4756 block and the previous instructions. We will later remove any
4757 nops that turn out not to be needed. */
4758 nops = nops_for_insn (0, history, NULL);
4761 if (mips_optimize != 0)
4763 /* Record the frag which holds the nop instructions, so
4764 that we can remove them if we don't need them. */
4765 frag_grow (nops * NOP_INSN_SIZE);
4766 prev_nop_frag = frag_now;
4767 prev_nop_frag_holds = nops;
4768 prev_nop_frag_required = 0;
4769 prev_nop_frag_since = 0;
4772 for (; nops > 0; --nops)
4773 add_fixed_insn (NOP_INSN);
4775 /* Move on to a new frag, so that it is safe to simply
4776 decrease the size of prev_nop_frag. */
4777 frag_wane (frag_now);
4779 mips_move_text_labels ();
4781 mips_mark_labels ();
4782 mips_clear_insn_labels ();
4784 mips_opts.noreorder++;
4785 mips_any_noreorder = 1;
4788 /* End a nested noreorder block. */
4791 end_noreorder (void)
4793 mips_opts.noreorder--;
4794 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4796 /* Commit to inserting prev_nop_frag_required nops and go back to
4797 handling nop insertion the .set reorder way. */
4798 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4800 insert_into_history (prev_nop_frag_since,
4801 prev_nop_frag_required, NOP_INSN);
4802 prev_nop_frag = NULL;
4806 /* Set up global variables for the start of a new macro. */
4811 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4812 memset (&mips_macro_warning.first_insn_sizes, 0,
4813 sizeof (mips_macro_warning.first_insn_sizes));
4814 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4815 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4816 && delayed_branch_p (&history[0]));
4817 switch (history[0].insn_mo->pinfo2
4818 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4820 case INSN2_BRANCH_DELAY_32BIT:
4821 mips_macro_warning.delay_slot_length = 4;
4823 case INSN2_BRANCH_DELAY_16BIT:
4824 mips_macro_warning.delay_slot_length = 2;
4827 mips_macro_warning.delay_slot_length = 0;
4830 mips_macro_warning.first_frag = NULL;
4833 /* Given that a macro is longer than one instruction or of the wrong size,
4834 return the appropriate warning for it. Return null if no warning is
4835 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4836 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4837 and RELAX_NOMACRO. */
4840 macro_warning (relax_substateT subtype)
4842 if (subtype & RELAX_DELAY_SLOT)
4843 return _("Macro instruction expanded into multiple instructions"
4844 " in a branch delay slot");
4845 else if (subtype & RELAX_NOMACRO)
4846 return _("Macro instruction expanded into multiple instructions");
4847 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4848 | RELAX_DELAY_SLOT_SIZE_SECOND))
4849 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4850 ? _("Macro instruction expanded into a wrong size instruction"
4851 " in a 16-bit branch delay slot")
4852 : _("Macro instruction expanded into a wrong size instruction"
4853 " in a 32-bit branch delay slot"));
4858 /* Finish up a macro. Emit warnings as appropriate. */
4863 /* Relaxation warning flags. */
4864 relax_substateT subtype = 0;
4866 /* Check delay slot size requirements. */
4867 if (mips_macro_warning.delay_slot_length == 2)
4868 subtype |= RELAX_DELAY_SLOT_16BIT;
4869 if (mips_macro_warning.delay_slot_length != 0)
4871 if (mips_macro_warning.delay_slot_length
4872 != mips_macro_warning.first_insn_sizes[0])
4873 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4874 if (mips_macro_warning.delay_slot_length
4875 != mips_macro_warning.first_insn_sizes[1])
4876 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4879 /* Check instruction count requirements. */
4880 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4882 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4883 subtype |= RELAX_SECOND_LONGER;
4884 if (mips_opts.warn_about_macros)
4885 subtype |= RELAX_NOMACRO;
4886 if (mips_macro_warning.delay_slot_p)
4887 subtype |= RELAX_DELAY_SLOT;
4890 /* If both alternatives fail to fill a delay slot correctly,
4891 emit the warning now. */
4892 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4893 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4898 s = subtype & (RELAX_DELAY_SLOT_16BIT
4899 | RELAX_DELAY_SLOT_SIZE_FIRST
4900 | RELAX_DELAY_SLOT_SIZE_SECOND);
4901 msg = macro_warning (s);
4903 as_warn ("%s", msg);
4907 /* If both implementations are longer than 1 instruction, then emit the
4909 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4914 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4915 msg = macro_warning (s);
4917 as_warn ("%s", msg);
4921 /* If any flags still set, then one implementation might need a warning
4922 and the other either will need one of a different kind or none at all.
4923 Pass any remaining flags over to relaxation. */
4924 if (mips_macro_warning.first_frag != NULL)
4925 mips_macro_warning.first_frag->fr_subtype |= subtype;
4928 /* Instruction operand formats used in macros that vary between
4929 standard MIPS and microMIPS code. */
4931 static const char * const brk_fmt[2] = { "c", "mF" };
4932 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4933 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4934 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4935 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4936 static const char * const mfhl_fmt[2] = { "d", "mj" };
4937 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4938 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4940 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4941 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4942 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4943 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4944 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4945 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4946 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4947 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4949 /* Read a macro's relocation codes from *ARGS and store them in *R.
4950 The first argument in *ARGS will be either the code for a single
4951 relocation or -1 followed by the three codes that make up a
4952 composite relocation. */
4955 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4959 next = va_arg (*args, int);
4961 r[0] = (bfd_reloc_code_real_type) next;
4963 for (i = 0; i < 3; i++)
4964 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4967 /* Build an instruction created by a macro expansion. This is passed
4968 a pointer to the count of instructions created so far, an
4969 expression, the name of the instruction to build, an operand format
4970 string, and corresponding arguments. */
4973 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4975 const struct mips_opcode *mo = NULL;
4976 bfd_reloc_code_real_type r[3];
4977 const struct mips_opcode *amo;
4978 struct hash_control *hash;
4979 struct mips_cl_insn insn;
4982 va_start (args, fmt);
4984 if (mips_opts.mips16)
4986 mips16_macro_build (ep, name, fmt, &args);
4991 r[0] = BFD_RELOC_UNUSED;
4992 r[1] = BFD_RELOC_UNUSED;
4993 r[2] = BFD_RELOC_UNUSED;
4994 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4995 amo = (struct mips_opcode *) hash_find (hash, name);
4997 gas_assert (strcmp (name, amo->name) == 0);
5001 /* Search until we get a match for NAME. It is assumed here that
5002 macros will never generate MDMX, MIPS-3D, or MT instructions.
5003 We try to match an instruction that fulfils the branch delay
5004 slot instruction length requirement (if any) of the previous
5005 instruction. While doing this we record the first instruction
5006 seen that matches all the other conditions and use it anyway
5007 if the requirement cannot be met; we will issue an appropriate
5008 warning later on. */
5009 if (strcmp (fmt, amo->args) == 0
5010 && amo->pinfo != INSN_MACRO
5011 && is_opcode_valid (amo)
5012 && is_size_valid (amo))
5014 if (is_delay_slot_valid (amo))
5024 gas_assert (amo->name);
5026 while (strcmp (name, amo->name) == 0);
5029 create_insn (&insn, mo);
5047 INSERT_OPERAND (mips_opts.micromips,
5048 EXTLSB, insn, va_arg (args, int));
5053 /* Note that in the macro case, these arguments are already
5054 in MSB form. (When handling the instruction in the
5055 non-macro case, these arguments are sizes from which
5056 MSB values must be calculated.) */
5057 INSERT_OPERAND (mips_opts.micromips,
5058 INSMSB, insn, va_arg (args, int));
5062 gas_assert (!mips_opts.micromips);
5063 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5069 /* Note that in the macro case, these arguments are already
5070 in MSBD form. (When handling the instruction in the
5071 non-macro case, these arguments are sizes from which
5072 MSBD values must be calculated.) */
5073 INSERT_OPERAND (mips_opts.micromips,
5074 EXTMSBD, insn, va_arg (args, int));
5078 gas_assert (!mips_opts.micromips);
5079 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5088 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5092 gas_assert (mips_opts.micromips);
5096 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5100 gas_assert (!mips_opts.micromips);
5101 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5105 gas_assert (!mips_opts.micromips);
5107 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5111 if (mips_opts.micromips)
5112 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5114 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5118 gas_assert (!mips_opts.micromips);
5120 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5124 gas_assert (!mips_opts.micromips);
5126 int tmp = va_arg (args, int);
5128 INSERT_OPERAND (0, RT, insn, tmp);
5129 INSERT_OPERAND (0, RD, insn, tmp);
5135 gas_assert (!mips_opts.micromips);
5136 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5143 INSERT_OPERAND (mips_opts.micromips,
5144 SHAMT, insn, va_arg (args, int));
5148 gas_assert (!mips_opts.micromips);
5149 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5153 gas_assert (!mips_opts.micromips);
5154 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5158 gas_assert (!mips_opts.micromips);
5159 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5163 gas_assert (!mips_opts.micromips);
5164 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5171 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5176 macro_read_relocs (&args, r);
5177 gas_assert (*r == BFD_RELOC_GPREL16
5178 || *r == BFD_RELOC_MIPS_HIGHER
5179 || *r == BFD_RELOC_HI16_S
5180 || *r == BFD_RELOC_LO16
5181 || *r == BFD_RELOC_MIPS_GOT_OFST);
5185 macro_read_relocs (&args, r);
5189 macro_read_relocs (&args, r);
5190 gas_assert (ep != NULL
5191 && (ep->X_op == O_constant
5192 || (ep->X_op == O_symbol
5193 && (*r == BFD_RELOC_MIPS_HIGHEST
5194 || *r == BFD_RELOC_HI16_S
5195 || *r == BFD_RELOC_HI16
5196 || *r == BFD_RELOC_GPREL16
5197 || *r == BFD_RELOC_MIPS_GOT_HI16
5198 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5202 gas_assert (ep != NULL);
5205 * This allows macro() to pass an immediate expression for
5206 * creating short branches without creating a symbol.
5208 * We don't allow branch relaxation for these branches, as
5209 * they should only appear in ".set nomacro" anyway.
5211 if (ep->X_op == O_constant)
5213 /* For microMIPS we always use relocations for branches.
5214 So we should not resolve immediate values. */
5215 gas_assert (!mips_opts.micromips);
5217 if ((ep->X_add_number & 3) != 0)
5218 as_bad (_("branch to misaligned address (0x%lx)"),
5219 (unsigned long) ep->X_add_number);
5220 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5221 as_bad (_("branch address range overflow (0x%lx)"),
5222 (unsigned long) ep->X_add_number);
5223 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5227 *r = BFD_RELOC_16_PCREL_S2;
5231 gas_assert (ep != NULL);
5232 *r = BFD_RELOC_MIPS_JMP;
5236 gas_assert (!mips_opts.micromips);
5237 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5241 INSERT_OPERAND (mips_opts.micromips,
5242 CACHE, insn, va_arg (args, unsigned long));
5246 gas_assert (mips_opts.micromips);
5247 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5251 gas_assert (mips_opts.micromips);
5252 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5256 INSERT_OPERAND (mips_opts.micromips,
5257 3BITPOS, insn, va_arg (args, unsigned int));
5261 INSERT_OPERAND (mips_opts.micromips,
5262 OFFSET12, insn, va_arg (args, unsigned long));
5266 gas_assert (mips_opts.micromips);
5267 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5270 case 'm': /* Opcode extension character. */
5271 gas_assert (mips_opts.micromips);
5275 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5279 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5283 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5297 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5299 append_insn (&insn, ep, r, TRUE);
5303 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5306 struct mips_opcode *mo;
5307 struct mips_cl_insn insn;
5308 bfd_reloc_code_real_type r[3]
5309 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5311 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5313 gas_assert (strcmp (name, mo->name) == 0);
5315 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5318 gas_assert (mo->name);
5319 gas_assert (strcmp (name, mo->name) == 0);
5322 create_insn (&insn, mo);
5340 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5345 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5349 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5353 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5363 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5370 regno = va_arg (*args, int);
5371 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5372 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5395 gas_assert (ep != NULL);
5397 if (ep->X_op != O_constant)
5398 *r = (int) BFD_RELOC_UNUSED + c;
5399 else if (calculate_reloc (*r, ep->X_add_number, &value))
5401 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5403 *r = BFD_RELOC_UNUSED;
5409 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5416 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5418 append_insn (&insn, ep, r, TRUE);
5422 * Sign-extend 32-bit mode constants that have bit 31 set and all
5423 * higher bits unset.
5426 normalize_constant_expr (expressionS *ex)
5428 if (ex->X_op == O_constant
5429 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5430 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5435 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5436 * all higher bits unset.
5439 normalize_address_expr (expressionS *ex)
5441 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5442 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5443 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5444 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5449 * Generate a "jalr" instruction with a relocation hint to the called
5450 * function. This occurs in NewABI PIC code.
5453 macro_build_jalr (expressionS *ep, int cprestore)
5455 static const bfd_reloc_code_real_type jalr_relocs[2]
5456 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5457 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5461 if (MIPS_JALR_HINT_P (ep))
5466 if (mips_opts.micromips)
5468 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5469 if (MIPS_JALR_HINT_P (ep)
5470 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5471 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5473 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5476 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5477 if (MIPS_JALR_HINT_P (ep))
5478 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5482 * Generate a "lui" instruction.
5485 macro_build_lui (expressionS *ep, int regnum)
5487 gas_assert (! mips_opts.mips16);
5489 if (ep->X_op != O_constant)
5491 gas_assert (ep->X_op == O_symbol);
5492 /* _gp_disp is a special case, used from s_cpload.
5493 __gnu_local_gp is used if mips_no_shared. */
5494 gas_assert (mips_pic == NO_PIC
5496 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5497 || (! mips_in_shared
5498 && strcmp (S_GET_NAME (ep->X_add_symbol),
5499 "__gnu_local_gp") == 0));
5502 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5505 /* Generate a sequence of instructions to do a load or store from a constant
5506 offset off of a base register (breg) into/from a target register (treg),
5507 using AT if necessary. */
5509 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5510 int treg, int breg, int dbl)
5512 gas_assert (ep->X_op == O_constant);
5514 /* Sign-extending 32-bit constants makes their handling easier. */
5516 normalize_constant_expr (ep);
5518 /* Right now, this routine can only handle signed 32-bit constants. */
5519 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5520 as_warn (_("operand overflow"));
5522 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5524 /* Signed 16-bit offset will fit in the op. Easy! */
5525 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5529 /* 32-bit offset, need multiple instructions and AT, like:
5530 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5531 addu $tempreg,$tempreg,$breg
5532 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5533 to handle the complete offset. */
5534 macro_build_lui (ep, AT);
5535 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5536 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5539 as_bad (_("Macro used $at after \".set noat\""));
5544 * Generates code to set the $at register to true (one)
5545 * if reg is less than the immediate expression.
5548 set_at (int reg, int unsignedp)
5550 if (imm_expr.X_op == O_constant
5551 && imm_expr.X_add_number >= -0x8000
5552 && imm_expr.X_add_number < 0x8000)
5553 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5554 AT, reg, BFD_RELOC_LO16);
5557 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5558 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5562 /* Warn if an expression is not a constant. */
5565 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5567 if (ex->X_op == O_big)
5568 as_bad (_("unsupported large constant"));
5569 else if (ex->X_op != O_constant)
5570 as_bad (_("Instruction %s requires absolute expression"),
5573 if (HAVE_32BIT_GPRS)
5574 normalize_constant_expr (ex);
5577 /* Count the leading zeroes by performing a binary chop. This is a
5578 bulky bit of source, but performance is a LOT better for the
5579 majority of values than a simple loop to count the bits:
5580 for (lcnt = 0; (lcnt < 32); lcnt++)
5581 if ((v) & (1 << (31 - lcnt)))
5583 However it is not code size friendly, and the gain will drop a bit
5584 on certain cached systems.
5586 #define COUNT_TOP_ZEROES(v) \
5587 (((v) & ~0xffff) == 0 \
5588 ? ((v) & ~0xff) == 0 \
5589 ? ((v) & ~0xf) == 0 \
5590 ? ((v) & ~0x3) == 0 \
5591 ? ((v) & ~0x1) == 0 \
5596 : ((v) & ~0x7) == 0 \
5599 : ((v) & ~0x3f) == 0 \
5600 ? ((v) & ~0x1f) == 0 \
5603 : ((v) & ~0x7f) == 0 \
5606 : ((v) & ~0xfff) == 0 \
5607 ? ((v) & ~0x3ff) == 0 \
5608 ? ((v) & ~0x1ff) == 0 \
5611 : ((v) & ~0x7ff) == 0 \
5614 : ((v) & ~0x3fff) == 0 \
5615 ? ((v) & ~0x1fff) == 0 \
5618 : ((v) & ~0x7fff) == 0 \
5621 : ((v) & ~0xffffff) == 0 \
5622 ? ((v) & ~0xfffff) == 0 \
5623 ? ((v) & ~0x3ffff) == 0 \
5624 ? ((v) & ~0x1ffff) == 0 \
5627 : ((v) & ~0x7ffff) == 0 \
5630 : ((v) & ~0x3fffff) == 0 \
5631 ? ((v) & ~0x1fffff) == 0 \
5634 : ((v) & ~0x7fffff) == 0 \
5637 : ((v) & ~0xfffffff) == 0 \
5638 ? ((v) & ~0x3ffffff) == 0 \
5639 ? ((v) & ~0x1ffffff) == 0 \
5642 : ((v) & ~0x7ffffff) == 0 \
5645 : ((v) & ~0x3fffffff) == 0 \
5646 ? ((v) & ~0x1fffffff) == 0 \
5649 : ((v) & ~0x7fffffff) == 0 \
5654 * This routine generates the least number of instructions necessary to load
5655 * an absolute expression value into a register.
5658 load_register (int reg, expressionS *ep, int dbl)
5661 expressionS hi32, lo32;
5663 if (ep->X_op != O_big)
5665 gas_assert (ep->X_op == O_constant);
5667 /* Sign-extending 32-bit constants makes their handling easier. */
5669 normalize_constant_expr (ep);
5671 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5673 /* We can handle 16 bit signed values with an addiu to
5674 $zero. No need to ever use daddiu here, since $zero and
5675 the result are always correct in 32 bit mode. */
5676 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5679 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5681 /* We can handle 16 bit unsigned values with an ori to
5683 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5686 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5688 /* 32 bit values require an lui. */
5689 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5690 if ((ep->X_add_number & 0xffff) != 0)
5691 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5696 /* The value is larger than 32 bits. */
5698 if (!dbl || HAVE_32BIT_GPRS)
5702 sprintf_vma (value, ep->X_add_number);
5703 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5704 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5708 if (ep->X_op != O_big)
5711 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5712 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5713 hi32.X_add_number &= 0xffffffff;
5715 lo32.X_add_number &= 0xffffffff;
5719 gas_assert (ep->X_add_number > 2);
5720 if (ep->X_add_number == 3)
5721 generic_bignum[3] = 0;
5722 else if (ep->X_add_number > 4)
5723 as_bad (_("Number larger than 64 bits"));
5724 lo32.X_op = O_constant;
5725 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5726 hi32.X_op = O_constant;
5727 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5730 if (hi32.X_add_number == 0)
5735 unsigned long hi, lo;
5737 if (hi32.X_add_number == (offsetT) 0xffffffff)
5739 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5741 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5744 if (lo32.X_add_number & 0x80000000)
5746 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5747 if (lo32.X_add_number & 0xffff)
5748 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5753 /* Check for 16bit shifted constant. We know that hi32 is
5754 non-zero, so start the mask on the first bit of the hi32
5759 unsigned long himask, lomask;
5763 himask = 0xffff >> (32 - shift);
5764 lomask = (0xffff << shift) & 0xffffffff;
5768 himask = 0xffff << (shift - 32);
5771 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5772 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5776 tmp.X_op = O_constant;
5778 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5779 | (lo32.X_add_number >> shift));
5781 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5782 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5783 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5784 reg, reg, (shift >= 32) ? shift - 32 : shift);
5789 while (shift <= (64 - 16));
5791 /* Find the bit number of the lowest one bit, and store the
5792 shifted value in hi/lo. */
5793 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5794 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5798 while ((lo & 1) == 0)
5803 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5809 while ((hi & 1) == 0)
5818 /* Optimize if the shifted value is a (power of 2) - 1. */
5819 if ((hi == 0 && ((lo + 1) & lo) == 0)
5820 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5822 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5827 /* This instruction will set the register to be all
5829 tmp.X_op = O_constant;
5830 tmp.X_add_number = (offsetT) -1;
5831 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5835 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5836 reg, reg, (bit >= 32) ? bit - 32 : bit);
5838 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5839 reg, reg, (shift >= 32) ? shift - 32 : shift);
5844 /* Sign extend hi32 before calling load_register, because we can
5845 generally get better code when we load a sign extended value. */
5846 if ((hi32.X_add_number & 0x80000000) != 0)
5847 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5848 load_register (reg, &hi32, 0);
5851 if ((lo32.X_add_number & 0xffff0000) == 0)
5855 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5863 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5865 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5866 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5872 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5876 mid16.X_add_number >>= 16;
5877 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5878 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5881 if ((lo32.X_add_number & 0xffff) != 0)
5882 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5886 load_delay_nop (void)
5888 if (!gpr_interlocks)
5889 macro_build (NULL, "nop", "");
5892 /* Load an address into a register. */
5895 load_address (int reg, expressionS *ep, int *used_at)
5897 if (ep->X_op != O_constant
5898 && ep->X_op != O_symbol)
5900 as_bad (_("expression too complex"));
5901 ep->X_op = O_constant;
5904 if (ep->X_op == O_constant)
5906 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5910 if (mips_pic == NO_PIC)
5912 /* If this is a reference to a GP relative symbol, we want
5913 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5915 lui $reg,<sym> (BFD_RELOC_HI16_S)
5916 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5917 If we have an addend, we always use the latter form.
5919 With 64bit address space and a usable $at we want
5920 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5921 lui $at,<sym> (BFD_RELOC_HI16_S)
5922 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5923 daddiu $at,<sym> (BFD_RELOC_LO16)
5927 If $at is already in use, we use a path which is suboptimal
5928 on superscalar processors.
5929 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5930 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5932 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5934 daddiu $reg,<sym> (BFD_RELOC_LO16)
5936 For GP relative symbols in 64bit address space we can use
5937 the same sequence as in 32bit address space. */
5938 if (HAVE_64BIT_SYMBOLS)
5940 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5941 && !nopic_need_relax (ep->X_add_symbol, 1))
5943 relax_start (ep->X_add_symbol);
5944 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5945 mips_gp_register, BFD_RELOC_GPREL16);
5949 if (*used_at == 0 && mips_opts.at)
5951 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5952 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5953 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5954 BFD_RELOC_MIPS_HIGHER);
5955 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5956 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5957 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5962 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5963 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5964 BFD_RELOC_MIPS_HIGHER);
5965 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5966 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5967 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5968 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5971 if (mips_relax.sequence)
5976 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5977 && !nopic_need_relax (ep->X_add_symbol, 1))
5979 relax_start (ep->X_add_symbol);
5980 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5981 mips_gp_register, BFD_RELOC_GPREL16);
5984 macro_build_lui (ep, reg);
5985 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5986 reg, reg, BFD_RELOC_LO16);
5987 if (mips_relax.sequence)
5991 else if (!mips_big_got)
5995 /* If this is a reference to an external symbol, we want
5996 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5998 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6000 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6001 If there is a constant, it must be added in after.
6003 If we have NewABI, we want
6004 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6005 unless we're referencing a global symbol with a non-zero
6006 offset, in which case cst must be added separately. */
6009 if (ep->X_add_number)
6011 ex.X_add_number = ep->X_add_number;
6012 ep->X_add_number = 0;
6013 relax_start (ep->X_add_symbol);
6014 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6015 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6016 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6017 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6018 ex.X_op = O_constant;
6019 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6020 reg, reg, BFD_RELOC_LO16);
6021 ep->X_add_number = ex.X_add_number;
6024 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6025 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6026 if (mips_relax.sequence)
6031 ex.X_add_number = ep->X_add_number;
6032 ep->X_add_number = 0;
6033 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6034 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6036 relax_start (ep->X_add_symbol);
6038 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6042 if (ex.X_add_number != 0)
6044 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6045 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6046 ex.X_op = O_constant;
6047 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6048 reg, reg, BFD_RELOC_LO16);
6052 else if (mips_big_got)
6056 /* This is the large GOT case. If this is a reference to an
6057 external symbol, we want
6058 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6060 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6062 Otherwise, for a reference to a local symbol in old ABI, we want
6063 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6065 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6066 If there is a constant, it must be added in after.
6068 In the NewABI, for local symbols, with or without offsets, we want:
6069 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6070 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6074 ex.X_add_number = ep->X_add_number;
6075 ep->X_add_number = 0;
6076 relax_start (ep->X_add_symbol);
6077 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6078 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6079 reg, reg, mips_gp_register);
6080 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6081 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6082 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6083 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6084 else if (ex.X_add_number)
6086 ex.X_op = O_constant;
6087 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6091 ep->X_add_number = ex.X_add_number;
6093 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6094 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6095 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6096 BFD_RELOC_MIPS_GOT_OFST);
6101 ex.X_add_number = ep->X_add_number;
6102 ep->X_add_number = 0;
6103 relax_start (ep->X_add_symbol);
6104 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6105 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6106 reg, reg, mips_gp_register);
6107 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6108 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6110 if (reg_needs_delay (mips_gp_register))
6112 /* We need a nop before loading from $gp. This special
6113 check is required because the lui which starts the main
6114 instruction stream does not refer to $gp, and so will not
6115 insert the nop which may be required. */
6116 macro_build (NULL, "nop", "");
6118 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6119 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6121 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6125 if (ex.X_add_number != 0)
6127 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6128 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6129 ex.X_op = O_constant;
6130 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6138 if (!mips_opts.at && *used_at == 1)
6139 as_bad (_("Macro used $at after \".set noat\""));
6142 /* Move the contents of register SOURCE into register DEST. */
6145 move_register (int dest, int source)
6147 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6148 instruction specifically requires a 32-bit one. */
6149 if (mips_opts.micromips
6150 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6151 macro_build (NULL, "move", "mp,mj", dest, source);
6153 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6157 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6158 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6159 The two alternatives are:
6161 Global symbol Local sybmol
6162 ------------- ------------
6163 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6165 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6167 load_got_offset emits the first instruction and add_got_offset
6168 emits the second for a 16-bit offset or add_got_offset_hilo emits
6169 a sequence to add a 32-bit offset using a scratch register. */
6172 load_got_offset (int dest, expressionS *local)
6177 global.X_add_number = 0;
6179 relax_start (local->X_add_symbol);
6180 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6181 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6183 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6184 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6189 add_got_offset (int dest, expressionS *local)
6193 global.X_op = O_constant;
6194 global.X_op_symbol = NULL;
6195 global.X_add_symbol = NULL;
6196 global.X_add_number = local->X_add_number;
6198 relax_start (local->X_add_symbol);
6199 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6200 dest, dest, BFD_RELOC_LO16);
6202 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6207 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6210 int hold_mips_optimize;
6212 global.X_op = O_constant;
6213 global.X_op_symbol = NULL;
6214 global.X_add_symbol = NULL;
6215 global.X_add_number = local->X_add_number;
6217 relax_start (local->X_add_symbol);
6218 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6220 /* Set mips_optimize around the lui instruction to avoid
6221 inserting an unnecessary nop after the lw. */
6222 hold_mips_optimize = mips_optimize;
6224 macro_build_lui (&global, tmp);
6225 mips_optimize = hold_mips_optimize;
6226 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6229 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6232 /* Emit a sequence of instructions to emulate a branch likely operation.
6233 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6234 is its complementing branch with the original condition negated.
6235 CALL is set if the original branch specified the link operation.
6236 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6238 Code like this is produced in the noreorder mode:
6243 delay slot (executed only if branch taken)
6251 delay slot (executed only if branch taken)
6254 In the reorder mode the delay slot would be filled with a nop anyway,
6255 so code produced is simply:
6260 This function is used when producing code for the microMIPS ASE that
6261 does not implement branch likely instructions in hardware. */
6264 macro_build_branch_likely (const char *br, const char *brneg,
6265 int call, expressionS *ep, const char *fmt,
6266 unsigned int sreg, unsigned int treg)
6268 int noreorder = mips_opts.noreorder;
6271 gas_assert (mips_opts.micromips);
6275 micromips_label_expr (&expr1);
6276 macro_build (&expr1, brneg, fmt, sreg, treg);
6277 macro_build (NULL, "nop", "");
6278 macro_build (ep, call ? "bal" : "b", "p");
6280 /* Set to true so that append_insn adds a label. */
6281 emit_branch_likely_macro = TRUE;
6285 macro_build (ep, br, fmt, sreg, treg);
6286 macro_build (NULL, "nop", "");
6291 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6292 the condition code tested. EP specifies the branch target. */
6295 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6322 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6325 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6326 the register tested. EP specifies the branch target. */
6329 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6331 const char *brneg = NULL;
6341 br = mips_opts.micromips ? "bgez" : "bgezl";
6345 gas_assert (mips_opts.micromips);
6354 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6361 br = mips_opts.micromips ? "blez" : "blezl";
6368 br = mips_opts.micromips ? "bltz" : "bltzl";
6372 gas_assert (mips_opts.micromips);
6380 if (mips_opts.micromips && brneg)
6381 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6383 macro_build (ep, br, "s,p", sreg);
6386 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6387 TREG as the registers tested. EP specifies the branch target. */
6390 macro_build_branch_rsrt (int type, expressionS *ep,
6391 unsigned int sreg, unsigned int treg)
6393 const char *brneg = NULL;
6405 br = mips_opts.micromips ? "beq" : "beql";
6414 br = mips_opts.micromips ? "bne" : "bnel";
6420 if (mips_opts.micromips && brneg)
6421 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6423 macro_build (ep, br, "s,t,p", sreg, treg);
6428 * This routine implements the seemingly endless macro or synthesized
6429 * instructions and addressing modes in the mips assembly language. Many
6430 * of these macros are simple and are similar to each other. These could
6431 * probably be handled by some kind of table or grammar approach instead of
6432 * this verbose method. Others are not simple macros but are more like
6433 * optimizing code generation.
6434 * One interesting optimization is when several store macros appear
6435 * consecutively that would load AT with the upper half of the same address.
6436 * The ensuing load upper instructions are ommited. This implies some kind
6437 * of global optimization. We currently only optimize within a single macro.
6438 * For many of the load and store macros if the address is specified as a
6439 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6440 * first load register 'at' with zero and use it as the base register. The
6441 * mips assembler simply uses register $zero. Just one tiny optimization
6445 macro (struct mips_cl_insn *ip)
6447 unsigned int treg, sreg, dreg, breg;
6448 unsigned int tempreg;
6451 expressionS label_expr;
6470 bfd_reloc_code_real_type r;
6471 int hold_mips_optimize;
6473 gas_assert (! mips_opts.mips16);
6475 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6476 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6477 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6478 mask = ip->insn_mo->mask;
6480 label_expr.X_op = O_constant;
6481 label_expr.X_op_symbol = NULL;
6482 label_expr.X_add_symbol = NULL;
6483 label_expr.X_add_number = 0;
6485 expr1.X_op = O_constant;
6486 expr1.X_op_symbol = NULL;
6487 expr1.X_add_symbol = NULL;
6488 expr1.X_add_number = 1;
6503 if (mips_opts.micromips)
6504 micromips_label_expr (&label_expr);
6506 label_expr.X_add_number = 8;
6507 macro_build (&label_expr, "bgez", "s,p", sreg);
6509 macro_build (NULL, "nop", "");
6511 move_register (dreg, sreg);
6512 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6513 if (mips_opts.micromips)
6514 micromips_add_label ();
6531 if (!mips_opts.micromips)
6533 if (imm_expr.X_op == O_constant
6534 && imm_expr.X_add_number >= -0x200
6535 && imm_expr.X_add_number < 0x200)
6537 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6546 if (imm_expr.X_op == O_constant
6547 && imm_expr.X_add_number >= -0x8000
6548 && imm_expr.X_add_number < 0x8000)
6550 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6555 load_register (AT, &imm_expr, dbl);
6556 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6575 if (imm_expr.X_op == O_constant
6576 && imm_expr.X_add_number >= 0
6577 && imm_expr.X_add_number < 0x10000)
6579 if (mask != M_NOR_I)
6580 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6583 macro_build (&imm_expr, "ori", "t,r,i",
6584 treg, sreg, BFD_RELOC_LO16);
6585 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6591 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6592 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6596 switch (imm_expr.X_add_number)
6599 macro_build (NULL, "nop", "");
6602 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6606 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6607 (int) imm_expr.X_add_number);
6610 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6611 (unsigned long) imm_expr.X_add_number);
6620 gas_assert (mips_opts.micromips);
6621 macro_build_branch_ccl (mask, &offset_expr,
6622 EXTRACT_OPERAND (1, BCC, *ip));
6629 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6635 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6640 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6647 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6649 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6653 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6654 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6655 &offset_expr, AT, ZERO);
6665 macro_build_branch_rs (mask, &offset_expr, sreg);
6671 /* Check for > max integer. */
6672 maxnum = 0x7fffffff;
6673 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6680 if (imm_expr.X_op == O_constant
6681 && imm_expr.X_add_number >= maxnum
6682 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6685 /* Result is always false. */
6687 macro_build (NULL, "nop", "");
6689 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6692 if (imm_expr.X_op != O_constant)
6693 as_bad (_("Unsupported large constant"));
6694 ++imm_expr.X_add_number;
6698 if (mask == M_BGEL_I)
6700 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6702 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6703 &offset_expr, sreg);
6706 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6708 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6709 &offset_expr, sreg);
6712 maxnum = 0x7fffffff;
6713 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6720 maxnum = - maxnum - 1;
6721 if (imm_expr.X_op == O_constant
6722 && imm_expr.X_add_number <= maxnum
6723 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6726 /* result is always true */
6727 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6728 macro_build (&offset_expr, "b", "p");
6733 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6734 &offset_expr, AT, ZERO);
6743 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6744 &offset_expr, ZERO, treg);
6748 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6749 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6750 &offset_expr, AT, ZERO);
6759 && imm_expr.X_op == O_constant
6760 && imm_expr.X_add_number == -1))
6762 if (imm_expr.X_op != O_constant)
6763 as_bad (_("Unsupported large constant"));
6764 ++imm_expr.X_add_number;
6768 if (mask == M_BGEUL_I)
6770 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6772 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6773 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6774 &offset_expr, sreg, ZERO);
6779 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6780 &offset_expr, AT, ZERO);
6788 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6790 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6794 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6795 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6796 &offset_expr, AT, ZERO);
6804 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6805 &offset_expr, sreg, ZERO);
6811 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6812 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6813 &offset_expr, AT, ZERO);
6821 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6823 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6827 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6828 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6829 &offset_expr, AT, ZERO);
6836 maxnum = 0x7fffffff;
6837 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6844 if (imm_expr.X_op == O_constant
6845 && imm_expr.X_add_number >= maxnum
6846 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6848 if (imm_expr.X_op != O_constant)
6849 as_bad (_("Unsupported large constant"));
6850 ++imm_expr.X_add_number;
6854 if (mask == M_BLTL_I)
6856 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6857 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6858 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6859 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6864 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6865 &offset_expr, AT, ZERO);
6873 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6874 &offset_expr, sreg, ZERO);
6880 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6881 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6882 &offset_expr, AT, ZERO);
6891 && imm_expr.X_op == O_constant
6892 && imm_expr.X_add_number == -1))
6894 if (imm_expr.X_op != O_constant)
6895 as_bad (_("Unsupported large constant"));
6896 ++imm_expr.X_add_number;
6900 if (mask == M_BLTUL_I)
6902 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6904 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6905 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6906 &offset_expr, sreg, ZERO);
6911 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6912 &offset_expr, AT, ZERO);
6920 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6922 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6926 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6927 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6928 &offset_expr, AT, ZERO);
6938 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6939 &offset_expr, ZERO, treg);
6943 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6944 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6945 &offset_expr, AT, ZERO);
6951 /* Use unsigned arithmetic. */
6955 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6957 as_bad (_("Unsupported large constant"));
6962 pos = imm_expr.X_add_number;
6963 size = imm2_expr.X_add_number;
6968 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6971 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6973 as_bad (_("Improper extract size (%lu, position %lu)"),
6974 (unsigned long) size, (unsigned long) pos);
6978 if (size <= 32 && pos < 32)
6983 else if (size <= 32)
6993 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7000 /* Use unsigned arithmetic. */
7004 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7006 as_bad (_("Unsupported large constant"));
7011 pos = imm_expr.X_add_number;
7012 size = imm2_expr.X_add_number;
7017 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7020 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7022 as_bad (_("Improper insert size (%lu, position %lu)"),
7023 (unsigned long) size, (unsigned long) pos);
7027 if (pos < 32 && (pos + size - 1) < 32)
7042 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7043 (int) (pos + size - 1));
7059 as_warn (_("Divide by zero."));
7061 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7063 macro_build (NULL, "break", BRK_FMT, 7);
7070 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7071 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7075 if (mips_opts.micromips)
7076 micromips_label_expr (&label_expr);
7078 label_expr.X_add_number = 8;
7079 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7080 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7081 macro_build (NULL, "break", BRK_FMT, 7);
7082 if (mips_opts.micromips)
7083 micromips_add_label ();
7085 expr1.X_add_number = -1;
7087 load_register (AT, &expr1, dbl);
7088 if (mips_opts.micromips)
7089 micromips_label_expr (&label_expr);
7091 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7092 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7095 expr1.X_add_number = 1;
7096 load_register (AT, &expr1, dbl);
7097 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7101 expr1.X_add_number = 0x80000000;
7102 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7106 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7107 /* We want to close the noreorder block as soon as possible, so
7108 that later insns are available for delay slot filling. */
7113 if (mips_opts.micromips)
7114 micromips_label_expr (&label_expr);
7116 label_expr.X_add_number = 8;
7117 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7118 macro_build (NULL, "nop", "");
7120 /* We want to close the noreorder block as soon as possible, so
7121 that later insns are available for delay slot filling. */
7124 macro_build (NULL, "break", BRK_FMT, 6);
7126 if (mips_opts.micromips)
7127 micromips_add_label ();
7128 macro_build (NULL, s, MFHL_FMT, dreg);
7167 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7169 as_warn (_("Divide by zero."));
7171 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7173 macro_build (NULL, "break", BRK_FMT, 7);
7176 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7178 if (strcmp (s2, "mflo") == 0)
7179 move_register (dreg, sreg);
7181 move_register (dreg, ZERO);
7184 if (imm_expr.X_op == O_constant
7185 && imm_expr.X_add_number == -1
7186 && s[strlen (s) - 1] != 'u')
7188 if (strcmp (s2, "mflo") == 0)
7190 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7193 move_register (dreg, ZERO);
7198 load_register (AT, &imm_expr, dbl);
7199 macro_build (NULL, s, "z,s,t", sreg, AT);
7200 macro_build (NULL, s2, MFHL_FMT, dreg);
7222 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7223 macro_build (NULL, s, "z,s,t", sreg, treg);
7224 /* We want to close the noreorder block as soon as possible, so
7225 that later insns are available for delay slot filling. */
7230 if (mips_opts.micromips)
7231 micromips_label_expr (&label_expr);
7233 label_expr.X_add_number = 8;
7234 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7235 macro_build (NULL, s, "z,s,t", sreg, treg);
7237 /* We want to close the noreorder block as soon as possible, so
7238 that later insns are available for delay slot filling. */
7240 macro_build (NULL, "break", BRK_FMT, 7);
7241 if (mips_opts.micromips)
7242 micromips_add_label ();
7244 macro_build (NULL, s2, MFHL_FMT, dreg);
7256 /* Load the address of a symbol into a register. If breg is not
7257 zero, we then add a base register to it. */
7259 if (dbl && HAVE_32BIT_GPRS)
7260 as_warn (_("dla used to load 32-bit register"));
7262 if (!dbl && HAVE_64BIT_OBJECTS)
7263 as_warn (_("la used to load 64-bit address"));
7265 if (offset_expr.X_op == O_constant
7266 && offset_expr.X_add_number >= -0x8000
7267 && offset_expr.X_add_number < 0x8000)
7269 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7270 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7274 if (mips_opts.at && (treg == breg))
7284 if (offset_expr.X_op != O_symbol
7285 && offset_expr.X_op != O_constant)
7287 as_bad (_("Expression too complex"));
7288 offset_expr.X_op = O_constant;
7291 if (offset_expr.X_op == O_constant)
7292 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7293 else if (mips_pic == NO_PIC)
7295 /* If this is a reference to a GP relative symbol, we want
7296 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7298 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7299 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7300 If we have a constant, we need two instructions anyhow,
7301 so we may as well always use the latter form.
7303 With 64bit address space and a usable $at we want
7304 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7305 lui $at,<sym> (BFD_RELOC_HI16_S)
7306 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7307 daddiu $at,<sym> (BFD_RELOC_LO16)
7309 daddu $tempreg,$tempreg,$at
7311 If $at is already in use, we use a path which is suboptimal
7312 on superscalar processors.
7313 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7314 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7316 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7318 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7320 For GP relative symbols in 64bit address space we can use
7321 the same sequence as in 32bit address space. */
7322 if (HAVE_64BIT_SYMBOLS)
7324 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7325 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7327 relax_start (offset_expr.X_add_symbol);
7328 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7329 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7333 if (used_at == 0 && mips_opts.at)
7335 macro_build (&offset_expr, "lui", LUI_FMT,
7336 tempreg, BFD_RELOC_MIPS_HIGHEST);
7337 macro_build (&offset_expr, "lui", LUI_FMT,
7338 AT, BFD_RELOC_HI16_S);
7339 macro_build (&offset_expr, "daddiu", "t,r,j",
7340 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7341 macro_build (&offset_expr, "daddiu", "t,r,j",
7342 AT, AT, BFD_RELOC_LO16);
7343 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7344 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7349 macro_build (&offset_expr, "lui", LUI_FMT,
7350 tempreg, BFD_RELOC_MIPS_HIGHEST);
7351 macro_build (&offset_expr, "daddiu", "t,r,j",
7352 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7353 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7354 macro_build (&offset_expr, "daddiu", "t,r,j",
7355 tempreg, tempreg, BFD_RELOC_HI16_S);
7356 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7357 macro_build (&offset_expr, "daddiu", "t,r,j",
7358 tempreg, tempreg, BFD_RELOC_LO16);
7361 if (mips_relax.sequence)
7366 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7367 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7369 relax_start (offset_expr.X_add_symbol);
7370 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7371 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7374 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7375 as_bad (_("Offset too large"));
7376 macro_build_lui (&offset_expr, tempreg);
7377 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7378 tempreg, tempreg, BFD_RELOC_LO16);
7379 if (mips_relax.sequence)
7383 else if (!mips_big_got && !HAVE_NEWABI)
7385 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7387 /* If this is a reference to an external symbol, and there
7388 is no constant, we want
7389 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7390 or for lca or if tempreg is PIC_CALL_REG
7391 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7392 For a local symbol, we want
7393 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7395 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7397 If we have a small constant, and this is a reference to
7398 an external symbol, we want
7399 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7401 addiu $tempreg,$tempreg,<constant>
7402 For a local symbol, we want the same instruction
7403 sequence, but we output a BFD_RELOC_LO16 reloc on the
7406 If we have a large constant, and this is a reference to
7407 an external symbol, we want
7408 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7409 lui $at,<hiconstant>
7410 addiu $at,$at,<loconstant>
7411 addu $tempreg,$tempreg,$at
7412 For a local symbol, we want the same instruction
7413 sequence, but we output a BFD_RELOC_LO16 reloc on the
7417 if (offset_expr.X_add_number == 0)
7419 if (mips_pic == SVR4_PIC
7421 && (call || tempreg == PIC_CALL_REG))
7422 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7424 relax_start (offset_expr.X_add_symbol);
7425 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7426 lw_reloc_type, mips_gp_register);
7429 /* We're going to put in an addu instruction using
7430 tempreg, so we may as well insert the nop right
7435 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7436 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7438 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7439 tempreg, tempreg, BFD_RELOC_LO16);
7441 /* FIXME: If breg == 0, and the next instruction uses
7442 $tempreg, then if this variant case is used an extra
7443 nop will be generated. */
7445 else if (offset_expr.X_add_number >= -0x8000
7446 && offset_expr.X_add_number < 0x8000)
7448 load_got_offset (tempreg, &offset_expr);
7450 add_got_offset (tempreg, &offset_expr);
7454 expr1.X_add_number = offset_expr.X_add_number;
7455 offset_expr.X_add_number =
7456 SEXT_16BIT (offset_expr.X_add_number);
7457 load_got_offset (tempreg, &offset_expr);
7458 offset_expr.X_add_number = expr1.X_add_number;
7459 /* If we are going to add in a base register, and the
7460 target register and the base register are the same,
7461 then we are using AT as a temporary register. Since
7462 we want to load the constant into AT, we add our
7463 current AT (from the global offset table) and the
7464 register into the register now, and pretend we were
7465 not using a base register. */
7469 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7474 add_got_offset_hilo (tempreg, &offset_expr, AT);
7478 else if (!mips_big_got && HAVE_NEWABI)
7480 int add_breg_early = 0;
7482 /* If this is a reference to an external, and there is no
7483 constant, or local symbol (*), with or without a
7485 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7486 or for lca or if tempreg is PIC_CALL_REG
7487 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7489 If we have a small constant, and this is a reference to
7490 an external symbol, we want
7491 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7492 addiu $tempreg,$tempreg,<constant>
7494 If we have a large constant, and this is a reference to
7495 an external symbol, we want
7496 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7497 lui $at,<hiconstant>
7498 addiu $at,$at,<loconstant>
7499 addu $tempreg,$tempreg,$at
7501 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7502 local symbols, even though it introduces an additional
7505 if (offset_expr.X_add_number)
7507 expr1.X_add_number = offset_expr.X_add_number;
7508 offset_expr.X_add_number = 0;
7510 relax_start (offset_expr.X_add_symbol);
7511 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7512 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7514 if (expr1.X_add_number >= -0x8000
7515 && expr1.X_add_number < 0x8000)
7517 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7518 tempreg, tempreg, BFD_RELOC_LO16);
7520 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7522 /* If we are going to add in a base register, and the
7523 target register and the base register are the same,
7524 then we are using AT as a temporary register. Since
7525 we want to load the constant into AT, we add our
7526 current AT (from the global offset table) and the
7527 register into the register now, and pretend we were
7528 not using a base register. */
7533 gas_assert (tempreg == AT);
7534 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7540 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7541 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7547 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7550 offset_expr.X_add_number = expr1.X_add_number;
7552 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7553 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7556 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7557 treg, tempreg, breg);
7563 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7565 relax_start (offset_expr.X_add_symbol);
7566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7567 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7569 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7570 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7575 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7576 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7579 else if (mips_big_got && !HAVE_NEWABI)
7582 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7583 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7584 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7586 /* This is the large GOT case. If this is a reference to an
7587 external symbol, and there is no constant, we want
7588 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7589 addu $tempreg,$tempreg,$gp
7590 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7591 or for lca or if tempreg is PIC_CALL_REG
7592 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7593 addu $tempreg,$tempreg,$gp
7594 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7595 For a local symbol, we want
7596 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7598 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7600 If we have a small constant, and this is a reference to
7601 an external symbol, we want
7602 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7603 addu $tempreg,$tempreg,$gp
7604 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7606 addiu $tempreg,$tempreg,<constant>
7607 For a local symbol, we want
7608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7610 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7612 If we have a large constant, and this is a reference to
7613 an external symbol, we want
7614 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7615 addu $tempreg,$tempreg,$gp
7616 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7617 lui $at,<hiconstant>
7618 addiu $at,$at,<loconstant>
7619 addu $tempreg,$tempreg,$at
7620 For a local symbol, we want
7621 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7622 lui $at,<hiconstant>
7623 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7624 addu $tempreg,$tempreg,$at
7627 expr1.X_add_number = offset_expr.X_add_number;
7628 offset_expr.X_add_number = 0;
7629 relax_start (offset_expr.X_add_symbol);
7630 gpdelay = reg_needs_delay (mips_gp_register);
7631 if (expr1.X_add_number == 0 && breg == 0
7632 && (call || tempreg == PIC_CALL_REG))
7634 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7635 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7637 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7638 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7639 tempreg, tempreg, mips_gp_register);
7640 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7641 tempreg, lw_reloc_type, tempreg);
7642 if (expr1.X_add_number == 0)
7646 /* We're going to put in an addu instruction using
7647 tempreg, so we may as well insert the nop right
7652 else if (expr1.X_add_number >= -0x8000
7653 && expr1.X_add_number < 0x8000)
7656 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7657 tempreg, tempreg, BFD_RELOC_LO16);
7661 /* If we are going to add in a base register, and the
7662 target register and the base register are the same,
7663 then we are using AT as a temporary register. Since
7664 we want to load the constant into AT, we add our
7665 current AT (from the global offset table) and the
7666 register into the register now, and pretend we were
7667 not using a base register. */
7672 gas_assert (tempreg == AT);
7674 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7679 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7680 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7684 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7689 /* This is needed because this instruction uses $gp, but
7690 the first instruction on the main stream does not. */
7691 macro_build (NULL, "nop", "");
7694 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7695 local_reloc_type, mips_gp_register);
7696 if (expr1.X_add_number >= -0x8000
7697 && expr1.X_add_number < 0x8000)
7700 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7701 tempreg, tempreg, BFD_RELOC_LO16);
7702 /* FIXME: If add_number is 0, and there was no base
7703 register, the external symbol case ended with a load,
7704 so if the symbol turns out to not be external, and
7705 the next instruction uses tempreg, an unnecessary nop
7706 will be inserted. */
7712 /* We must add in the base register now, as in the
7713 external symbol case. */
7714 gas_assert (tempreg == AT);
7716 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7719 /* We set breg to 0 because we have arranged to add
7720 it in in both cases. */
7724 macro_build_lui (&expr1, AT);
7725 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7726 AT, AT, BFD_RELOC_LO16);
7727 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7728 tempreg, tempreg, AT);
7733 else if (mips_big_got && HAVE_NEWABI)
7735 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7736 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7737 int add_breg_early = 0;
7739 /* This is the large GOT case. If this is a reference to an
7740 external symbol, and there is no constant, we want
7741 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7742 add $tempreg,$tempreg,$gp
7743 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7744 or for lca or if tempreg is PIC_CALL_REG
7745 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7746 add $tempreg,$tempreg,$gp
7747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7749 If we have a small constant, and this is a reference to
7750 an external symbol, we want
7751 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7752 add $tempreg,$tempreg,$gp
7753 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7754 addi $tempreg,$tempreg,<constant>
7756 If we have a large constant, and this is a reference to
7757 an external symbol, we want
7758 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7759 addu $tempreg,$tempreg,$gp
7760 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7761 lui $at,<hiconstant>
7762 addi $at,$at,<loconstant>
7763 add $tempreg,$tempreg,$at
7765 If we have NewABI, and we know it's a local symbol, we want
7766 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7767 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7768 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7770 relax_start (offset_expr.X_add_symbol);
7772 expr1.X_add_number = offset_expr.X_add_number;
7773 offset_expr.X_add_number = 0;
7775 if (expr1.X_add_number == 0 && breg == 0
7776 && (call || tempreg == PIC_CALL_REG))
7778 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7779 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7781 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7783 tempreg, tempreg, mips_gp_register);
7784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7785 tempreg, lw_reloc_type, tempreg);
7787 if (expr1.X_add_number == 0)
7789 else if (expr1.X_add_number >= -0x8000
7790 && expr1.X_add_number < 0x8000)
7792 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7793 tempreg, tempreg, BFD_RELOC_LO16);
7795 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7797 /* If we are going to add in a base register, and the
7798 target register and the base register are the same,
7799 then we are using AT as a temporary register. Since
7800 we want to load the constant into AT, we add our
7801 current AT (from the global offset table) and the
7802 register into the register now, and pretend we were
7803 not using a base register. */
7808 gas_assert (tempreg == AT);
7809 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7815 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7816 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7821 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7824 offset_expr.X_add_number = expr1.X_add_number;
7825 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7826 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7827 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7828 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7831 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7832 treg, tempreg, breg);
7842 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7846 gas_assert (!mips_opts.micromips);
7848 unsigned long temp = (treg << 16) | (0x01);
7849 macro_build (NULL, "c2", "C", temp);
7854 gas_assert (!mips_opts.micromips);
7856 unsigned long temp = (0x02);
7857 macro_build (NULL, "c2", "C", temp);
7862 gas_assert (!mips_opts.micromips);
7864 unsigned long temp = (treg << 16) | (0x02);
7865 macro_build (NULL, "c2", "C", temp);
7870 gas_assert (!mips_opts.micromips);
7871 macro_build (NULL, "c2", "C", 3);
7875 gas_assert (!mips_opts.micromips);
7877 unsigned long temp = (treg << 16) | 0x03;
7878 macro_build (NULL, "c2", "C", temp);
7883 /* The j instruction may not be used in PIC code, since it
7884 requires an absolute address. We convert it to a b
7886 if (mips_pic == NO_PIC)
7887 macro_build (&offset_expr, "j", "a");
7889 macro_build (&offset_expr, "b", "p");
7892 /* The jal instructions must be handled as macros because when
7893 generating PIC code they expand to multi-instruction
7894 sequences. Normally they are simple instructions. */
7899 gas_assert (mips_opts.micromips);
7907 if (mips_pic == NO_PIC)
7909 s = jals ? "jalrs" : "jalr";
7910 if (mips_opts.micromips
7912 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7913 macro_build (NULL, s, "mj", sreg);
7915 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7919 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7920 && mips_cprestore_offset >= 0);
7922 if (sreg != PIC_CALL_REG)
7923 as_warn (_("MIPS PIC call to register other than $25"));
7925 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7926 ? "jalrs" : "jalr");
7927 if (mips_opts.micromips
7929 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7930 macro_build (NULL, s, "mj", sreg);
7932 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7933 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7935 if (mips_cprestore_offset < 0)
7936 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7939 if (!mips_frame_reg_valid)
7941 as_warn (_("No .frame pseudo-op used in PIC code"));
7942 /* Quiet this warning. */
7943 mips_frame_reg_valid = 1;
7945 if (!mips_cprestore_valid)
7947 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7948 /* Quiet this warning. */
7949 mips_cprestore_valid = 1;
7951 if (mips_opts.noreorder)
7952 macro_build (NULL, "nop", "");
7953 expr1.X_add_number = mips_cprestore_offset;
7954 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7957 HAVE_64BIT_ADDRESSES);
7965 gas_assert (mips_opts.micromips);
7969 if (mips_pic == NO_PIC)
7970 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7971 else if (mips_pic == SVR4_PIC)
7973 /* If this is a reference to an external symbol, and we are
7974 using a small GOT, we want
7975 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7979 lw $gp,cprestore($sp)
7980 The cprestore value is set using the .cprestore
7981 pseudo-op. If we are using a big GOT, we want
7982 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7984 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7988 lw $gp,cprestore($sp)
7989 If the symbol is not external, we want
7990 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7992 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7995 lw $gp,cprestore($sp)
7997 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7998 sequences above, minus nops, unless the symbol is local,
7999 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8005 relax_start (offset_expr.X_add_symbol);
8006 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8007 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8010 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8011 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8017 relax_start (offset_expr.X_add_symbol);
8018 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8019 BFD_RELOC_MIPS_CALL_HI16);
8020 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8021 PIC_CALL_REG, mips_gp_register);
8022 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8023 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8026 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8027 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8029 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8030 PIC_CALL_REG, PIC_CALL_REG,
8031 BFD_RELOC_MIPS_GOT_OFST);
8035 macro_build_jalr (&offset_expr, 0);
8039 relax_start (offset_expr.X_add_symbol);
8042 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8043 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8052 gpdelay = reg_needs_delay (mips_gp_register);
8053 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8054 BFD_RELOC_MIPS_CALL_HI16);
8055 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8056 PIC_CALL_REG, mips_gp_register);
8057 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8058 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8063 macro_build (NULL, "nop", "");
8065 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8066 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8069 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8070 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8072 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8074 if (mips_cprestore_offset < 0)
8075 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8078 if (!mips_frame_reg_valid)
8080 as_warn (_("No .frame pseudo-op used in PIC code"));
8081 /* Quiet this warning. */
8082 mips_frame_reg_valid = 1;
8084 if (!mips_cprestore_valid)
8086 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8087 /* Quiet this warning. */
8088 mips_cprestore_valid = 1;
8090 if (mips_opts.noreorder)
8091 macro_build (NULL, "nop", "");
8092 expr1.X_add_number = mips_cprestore_offset;
8093 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8096 HAVE_64BIT_ADDRESSES);
8100 else if (mips_pic == VXWORKS_PIC)
8101 as_bad (_("Non-PIC jump used in PIC library"));
8111 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8119 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8150 gas_assert (!mips_opts.micromips);
8153 /* Itbl support may require additional care here. */
8160 /* Itbl support may require additional care here. */
8168 off12 = mips_opts.micromips;
8169 /* Itbl support may require additional care here. */
8174 gas_assert (!mips_opts.micromips);
8177 /* Itbl support may require additional care here. */
8185 off12 = mips_opts.micromips;
8192 off12 = mips_opts.micromips;
8198 /* Itbl support may require additional care here. */
8206 off12 = mips_opts.micromips;
8207 /* Itbl support may require additional care here. */
8214 /* Itbl support may require additional care here. */
8221 /* Itbl support may require additional care here. */
8229 off12 = mips_opts.micromips;
8236 off12 = mips_opts.micromips;
8243 off12 = mips_opts.micromips;
8250 off12 = mips_opts.micromips;
8257 off12 = mips_opts.micromips;
8262 gas_assert (mips_opts.micromips);
8271 gas_assert (mips_opts.micromips);
8280 gas_assert (mips_opts.micromips);
8288 gas_assert (mips_opts.micromips);
8295 /* We don't want to use $0 as tempreg. */
8296 if (breg == treg + lp || treg + lp == ZERO)
8299 tempreg = treg + lp;
8319 gas_assert (!mips_opts.micromips);
8322 /* Itbl support may require additional care here. */
8329 /* Itbl support may require additional care here. */
8337 off12 = mips_opts.micromips;
8338 /* Itbl support may require additional care here. */
8343 gas_assert (!mips_opts.micromips);
8346 /* Itbl support may require additional care here. */
8354 off12 = mips_opts.micromips;
8361 off12 = mips_opts.micromips;
8368 off12 = mips_opts.micromips;
8375 off12 = mips_opts.micromips;
8381 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8382 off12 = mips_opts.micromips;
8388 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8389 off12 = mips_opts.micromips;
8396 /* Itbl support may require additional care here. */
8403 off12 = mips_opts.micromips;
8404 /* Itbl support may require additional care here. */
8411 /* Itbl support may require additional care here. */
8416 gas_assert (!mips_opts.micromips);
8419 /* Itbl support may require additional care here. */
8427 off12 = mips_opts.micromips;
8434 off12 = mips_opts.micromips;
8439 gas_assert (mips_opts.micromips);
8447 gas_assert (mips_opts.micromips);
8455 gas_assert (mips_opts.micromips);
8463 gas_assert (mips_opts.micromips);
8472 if (offset_expr.X_op != O_constant
8473 && offset_expr.X_op != O_symbol)
8475 as_bad (_("Expression too complex"));
8476 offset_expr.X_op = O_constant;
8479 if (HAVE_32BIT_ADDRESSES
8480 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8484 sprintf_vma (value, offset_expr.X_add_number);
8485 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8488 /* A constant expression in PIC code can be handled just as it
8489 is in non PIC code. */
8490 if (offset_expr.X_op == O_constant)
8494 expr1.X_add_number = offset_expr.X_add_number;
8495 normalize_address_expr (&expr1);
8496 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8498 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8499 & ~(bfd_vma) 0xffff);
8502 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8504 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8505 & ~(bfd_vma) 0xfff);
8510 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8512 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8513 tempreg, tempreg, breg);
8518 if (offset_expr.X_add_number == 0)
8521 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8522 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8523 macro_build (NULL, s, fmt, treg, tempreg);
8526 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8528 macro_build (NULL, s, fmt,
8529 treg, (unsigned long) offset_expr.X_add_number, breg);
8531 else if (off12 || off0)
8533 /* A 12-bit or 0-bit offset field is too narrow to be used
8534 for a low-part relocation, so load the whole address into
8535 the auxillary register. In the case of "A(b)" addresses,
8536 we first load absolute address "A" into the register and
8537 then add base register "b". In the case of "o(b)" addresses,
8538 we simply need to add 16-bit offset "o" to base register "b", and
8539 offset_reloc already contains the relocations associated
8543 load_address (tempreg, &offset_expr, &used_at);
8545 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8546 tempreg, tempreg, breg);
8549 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8551 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8552 expr1.X_add_number = 0;
8554 macro_build (NULL, s, fmt, treg, tempreg);
8556 macro_build (NULL, s, fmt,
8557 treg, (unsigned long) expr1.X_add_number, tempreg);
8559 else if (mips_pic == NO_PIC)
8561 /* If this is a reference to a GP relative symbol, and there
8562 is no base register, we want
8563 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8564 Otherwise, if there is no base register, we want
8565 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8566 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8567 If we have a constant, we need two instructions anyhow,
8568 so we always use the latter form.
8570 If we have a base register, and this is a reference to a
8571 GP relative symbol, we want
8572 addu $tempreg,$breg,$gp
8573 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8575 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8576 addu $tempreg,$tempreg,$breg
8577 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8578 With a constant we always use the latter case.
8580 With 64bit address space and no base register and $at usable,
8582 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8583 lui $at,<sym> (BFD_RELOC_HI16_S)
8584 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8587 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8588 If we have a base register, we want
8589 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8590 lui $at,<sym> (BFD_RELOC_HI16_S)
8591 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8595 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8597 Without $at we can't generate the optimal path for superscalar
8598 processors here since this would require two temporary registers.
8599 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8600 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8602 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8604 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8605 If we have a base register, we want
8606 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8607 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8609 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8611 daddu $tempreg,$tempreg,$breg
8612 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8614 For GP relative symbols in 64bit address space we can use
8615 the same sequence as in 32bit address space. */
8616 if (HAVE_64BIT_SYMBOLS)
8618 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8619 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8621 relax_start (offset_expr.X_add_symbol);
8624 macro_build (&offset_expr, s, fmt, treg,
8625 BFD_RELOC_GPREL16, mips_gp_register);
8629 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8630 tempreg, breg, mips_gp_register);
8631 macro_build (&offset_expr, s, fmt, treg,
8632 BFD_RELOC_GPREL16, tempreg);
8637 if (used_at == 0 && mips_opts.at)
8639 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8640 BFD_RELOC_MIPS_HIGHEST);
8641 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8643 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8644 tempreg, BFD_RELOC_MIPS_HIGHER);
8646 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8647 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8648 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8649 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8655 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8656 BFD_RELOC_MIPS_HIGHEST);
8657 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8658 tempreg, BFD_RELOC_MIPS_HIGHER);
8659 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8660 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8661 tempreg, BFD_RELOC_HI16_S);
8662 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8664 macro_build (NULL, "daddu", "d,v,t",
8665 tempreg, tempreg, breg);
8666 macro_build (&offset_expr, s, fmt, treg,
8667 BFD_RELOC_LO16, tempreg);
8670 if (mips_relax.sequence)
8677 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8678 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8680 relax_start (offset_expr.X_add_symbol);
8681 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8685 macro_build_lui (&offset_expr, tempreg);
8686 macro_build (&offset_expr, s, fmt, treg,
8687 BFD_RELOC_LO16, tempreg);
8688 if (mips_relax.sequence)
8693 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8694 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8696 relax_start (offset_expr.X_add_symbol);
8697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8698 tempreg, breg, mips_gp_register);
8699 macro_build (&offset_expr, s, fmt, treg,
8700 BFD_RELOC_GPREL16, tempreg);
8703 macro_build_lui (&offset_expr, tempreg);
8704 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8705 tempreg, tempreg, breg);
8706 macro_build (&offset_expr, s, fmt, treg,
8707 BFD_RELOC_LO16, tempreg);
8708 if (mips_relax.sequence)
8712 else if (!mips_big_got)
8714 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8716 /* If this is a reference to an external symbol, we want
8717 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8719 <op> $treg,0($tempreg)
8721 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8723 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8724 <op> $treg,0($tempreg)
8727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8728 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8730 If there is a base register, we add it to $tempreg before
8731 the <op>. If there is a constant, we stick it in the
8732 <op> instruction. We don't handle constants larger than
8733 16 bits, because we have no way to load the upper 16 bits
8734 (actually, we could handle them for the subset of cases
8735 in which we are not using $at). */
8736 gas_assert (offset_expr.X_op == O_symbol);
8739 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8740 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8742 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8743 tempreg, tempreg, breg);
8744 macro_build (&offset_expr, s, fmt, treg,
8745 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8748 expr1.X_add_number = offset_expr.X_add_number;
8749 offset_expr.X_add_number = 0;
8750 if (expr1.X_add_number < -0x8000
8751 || expr1.X_add_number >= 0x8000)
8752 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8753 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8754 lw_reloc_type, mips_gp_register);
8756 relax_start (offset_expr.X_add_symbol);
8758 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8759 tempreg, BFD_RELOC_LO16);
8762 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8763 tempreg, tempreg, breg);
8764 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8766 else if (mips_big_got && !HAVE_NEWABI)
8770 /* If this is a reference to an external symbol, we want
8771 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8772 addu $tempreg,$tempreg,$gp
8773 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8774 <op> $treg,0($tempreg)
8776 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8778 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8779 <op> $treg,0($tempreg)
8780 If there is a base register, we add it to $tempreg before
8781 the <op>. If there is a constant, we stick it in the
8782 <op> instruction. We don't handle constants larger than
8783 16 bits, because we have no way to load the upper 16 bits
8784 (actually, we could handle them for the subset of cases
8785 in which we are not using $at). */
8786 gas_assert (offset_expr.X_op == O_symbol);
8787 expr1.X_add_number = offset_expr.X_add_number;
8788 offset_expr.X_add_number = 0;
8789 if (expr1.X_add_number < -0x8000
8790 || expr1.X_add_number >= 0x8000)
8791 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8792 gpdelay = reg_needs_delay (mips_gp_register);
8793 relax_start (offset_expr.X_add_symbol);
8794 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8795 BFD_RELOC_MIPS_GOT_HI16);
8796 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8798 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8799 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8802 macro_build (NULL, "nop", "");
8803 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8804 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8806 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8807 tempreg, BFD_RELOC_LO16);
8811 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8812 tempreg, tempreg, breg);
8813 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8815 else if (mips_big_got && HAVE_NEWABI)
8817 /* If this is a reference to an external symbol, we want
8818 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8819 add $tempreg,$tempreg,$gp
8820 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8821 <op> $treg,<ofst>($tempreg)
8822 Otherwise, for local symbols, we want:
8823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8824 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8825 gas_assert (offset_expr.X_op == O_symbol);
8826 expr1.X_add_number = offset_expr.X_add_number;
8827 offset_expr.X_add_number = 0;
8828 if (expr1.X_add_number < -0x8000
8829 || expr1.X_add_number >= 0x8000)
8830 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8831 relax_start (offset_expr.X_add_symbol);
8832 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8833 BFD_RELOC_MIPS_GOT_HI16);
8834 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8836 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8837 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8839 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8840 tempreg, tempreg, breg);
8841 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8844 offset_expr.X_add_number = expr1.X_add_number;
8845 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8846 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8848 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8849 tempreg, tempreg, breg);
8850 macro_build (&offset_expr, s, fmt, treg,
8851 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8861 load_register (treg, &imm_expr, 0);
8865 load_register (treg, &imm_expr, 1);
8869 if (imm_expr.X_op == O_constant)
8872 load_register (AT, &imm_expr, 0);
8873 macro_build (NULL, "mtc1", "t,G", AT, treg);
8878 gas_assert (offset_expr.X_op == O_symbol
8879 && strcmp (segment_name (S_GET_SEGMENT
8880 (offset_expr.X_add_symbol)),
8882 && offset_expr.X_add_number == 0);
8883 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8884 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8889 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8890 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8891 order 32 bits of the value and the low order 32 bits are either
8892 zero or in OFFSET_EXPR. */
8893 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8895 if (HAVE_64BIT_GPRS)
8896 load_register (treg, &imm_expr, 1);
8901 if (target_big_endian)
8913 load_register (hreg, &imm_expr, 0);
8916 if (offset_expr.X_op == O_absent)
8917 move_register (lreg, 0);
8920 gas_assert (offset_expr.X_op == O_constant);
8921 load_register (lreg, &offset_expr, 0);
8928 /* We know that sym is in the .rdata section. First we get the
8929 upper 16 bits of the address. */
8930 if (mips_pic == NO_PIC)
8932 macro_build_lui (&offset_expr, AT);
8937 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8938 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8942 /* Now we load the register(s). */
8943 if (HAVE_64BIT_GPRS)
8946 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8951 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8954 /* FIXME: How in the world do we deal with the possible
8956 offset_expr.X_add_number += 4;
8957 macro_build (&offset_expr, "lw", "t,o(b)",
8958 treg + 1, BFD_RELOC_LO16, AT);
8964 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8965 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8966 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8967 the value and the low order 32 bits are either zero or in
8969 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8972 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8973 if (HAVE_64BIT_FPRS)
8975 gas_assert (HAVE_64BIT_GPRS);
8976 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8980 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8981 if (offset_expr.X_op == O_absent)
8982 macro_build (NULL, "mtc1", "t,G", 0, treg);
8985 gas_assert (offset_expr.X_op == O_constant);
8986 load_register (AT, &offset_expr, 0);
8987 macro_build (NULL, "mtc1", "t,G", AT, treg);
8993 gas_assert (offset_expr.X_op == O_symbol
8994 && offset_expr.X_add_number == 0);
8995 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8996 if (strcmp (s, ".lit8") == 0)
8998 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9000 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
9001 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9004 breg = mips_gp_register;
9005 r = BFD_RELOC_MIPS_LITERAL;
9010 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9012 if (mips_pic != NO_PIC)
9013 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9014 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9017 /* FIXME: This won't work for a 64 bit address. */
9018 macro_build_lui (&offset_expr, AT);
9021 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9023 macro_build (&offset_expr, "ldc1", "T,o(b)",
9024 treg, BFD_RELOC_LO16, AT);
9033 /* Even on a big endian machine $fn comes before $fn+1. We have
9034 to adjust when loading from memory. */
9037 gas_assert (!mips_opts.micromips);
9038 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9039 macro_build (&offset_expr, "lwc1", "T,o(b)",
9040 target_big_endian ? treg + 1 : treg, r, breg);
9041 /* FIXME: A possible overflow which I don't know how to deal
9043 offset_expr.X_add_number += 4;
9044 macro_build (&offset_expr, "lwc1", "T,o(b)",
9045 target_big_endian ? treg : treg + 1, r, breg);
9049 gas_assert (!mips_opts.micromips);
9050 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9051 /* Even on a big endian machine $fn comes before $fn+1. We have
9052 to adjust when storing to memory. */
9053 macro_build (&offset_expr, "swc1", "T,o(b)",
9054 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
9055 offset_expr.X_add_number += 4;
9056 macro_build (&offset_expr, "swc1", "T,o(b)",
9057 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
9061 gas_assert (!mips_opts.micromips);
9063 * The MIPS assembler seems to check for X_add_number not
9064 * being double aligned and generating:
9067 * addiu at,at,%lo(foo+1)
9070 * But, the resulting address is the same after relocation so why
9071 * generate the extra instruction?
9073 /* Itbl support may require additional care here. */
9076 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9085 gas_assert (!mips_opts.micromips);
9086 /* Itbl support may require additional care here. */
9089 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9109 if (HAVE_64BIT_GPRS)
9119 if (HAVE_64BIT_GPRS)
9127 if (offset_expr.X_op != O_symbol
9128 && offset_expr.X_op != O_constant)
9130 as_bad (_("Expression too complex"));
9131 offset_expr.X_op = O_constant;
9134 if (HAVE_32BIT_ADDRESSES
9135 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9139 sprintf_vma (value, offset_expr.X_add_number);
9140 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9143 /* Even on a big endian machine $fn comes before $fn+1. We have
9144 to adjust when loading from memory. We set coproc if we must
9145 load $fn+1 first. */
9146 /* Itbl support may require additional care here. */
9147 if (!target_big_endian)
9150 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9152 /* If this is a reference to a GP relative symbol, we want
9153 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9154 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9155 If we have a base register, we use this
9157 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9158 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9159 If this is not a GP relative symbol, we want
9160 lui $at,<sym> (BFD_RELOC_HI16_S)
9161 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9162 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9163 If there is a base register, we add it to $at after the
9164 lui instruction. If there is a constant, we always use
9166 if (offset_expr.X_op == O_symbol
9167 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9168 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9170 relax_start (offset_expr.X_add_symbol);
9173 tempreg = mips_gp_register;
9177 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9178 AT, breg, mips_gp_register);
9183 /* Itbl support may require additional care here. */
9184 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9185 BFD_RELOC_GPREL16, tempreg);
9186 offset_expr.X_add_number += 4;
9188 /* Set mips_optimize to 2 to avoid inserting an
9190 hold_mips_optimize = mips_optimize;
9192 /* Itbl support may require additional care here. */
9193 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9194 BFD_RELOC_GPREL16, tempreg);
9195 mips_optimize = hold_mips_optimize;
9199 offset_expr.X_add_number -= 4;
9202 macro_build_lui (&offset_expr, AT);
9204 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9205 /* Itbl support may require additional care here. */
9206 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9207 BFD_RELOC_LO16, AT);
9208 /* FIXME: How do we handle overflow here? */
9209 offset_expr.X_add_number += 4;
9210 /* Itbl support may require additional care here. */
9211 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9212 BFD_RELOC_LO16, AT);
9213 if (mips_relax.sequence)
9216 else if (!mips_big_got)
9218 /* If this is a reference to an external symbol, we want
9219 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9224 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9226 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9227 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9228 If there is a base register we add it to $at before the
9229 lwc1 instructions. If there is a constant we include it
9230 in the lwc1 instructions. */
9232 expr1.X_add_number = offset_expr.X_add_number;
9233 if (expr1.X_add_number < -0x8000
9234 || expr1.X_add_number >= 0x8000 - 4)
9235 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9236 load_got_offset (AT, &offset_expr);
9239 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9241 /* Set mips_optimize to 2 to avoid inserting an undesired
9243 hold_mips_optimize = mips_optimize;
9246 /* Itbl support may require additional care here. */
9247 relax_start (offset_expr.X_add_symbol);
9248 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9249 BFD_RELOC_LO16, AT);
9250 expr1.X_add_number += 4;
9251 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9252 BFD_RELOC_LO16, AT);
9254 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9255 BFD_RELOC_LO16, AT);
9256 offset_expr.X_add_number += 4;
9257 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9258 BFD_RELOC_LO16, AT);
9261 mips_optimize = hold_mips_optimize;
9263 else if (mips_big_got)
9267 /* If this is a reference to an external symbol, we want
9268 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9270 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9275 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9277 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9278 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9279 If there is a base register we add it to $at before the
9280 lwc1 instructions. If there is a constant we include it
9281 in the lwc1 instructions. */
9283 expr1.X_add_number = offset_expr.X_add_number;
9284 offset_expr.X_add_number = 0;
9285 if (expr1.X_add_number < -0x8000
9286 || expr1.X_add_number >= 0x8000 - 4)
9287 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9288 gpdelay = reg_needs_delay (mips_gp_register);
9289 relax_start (offset_expr.X_add_symbol);
9290 macro_build (&offset_expr, "lui", LUI_FMT,
9291 AT, BFD_RELOC_MIPS_GOT_HI16);
9292 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9293 AT, AT, mips_gp_register);
9294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9295 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9298 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9299 /* Itbl support may require additional care here. */
9300 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9301 BFD_RELOC_LO16, AT);
9302 expr1.X_add_number += 4;
9304 /* Set mips_optimize to 2 to avoid inserting an undesired
9306 hold_mips_optimize = mips_optimize;
9308 /* Itbl support may require additional care here. */
9309 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9310 BFD_RELOC_LO16, AT);
9311 mips_optimize = hold_mips_optimize;
9312 expr1.X_add_number -= 4;
9315 offset_expr.X_add_number = expr1.X_add_number;
9317 macro_build (NULL, "nop", "");
9318 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9319 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9322 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9323 /* Itbl support may require additional care here. */
9324 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9325 BFD_RELOC_LO16, AT);
9326 offset_expr.X_add_number += 4;
9328 /* Set mips_optimize to 2 to avoid inserting an undesired
9330 hold_mips_optimize = mips_optimize;
9332 /* Itbl support may require additional care here. */
9333 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9334 BFD_RELOC_LO16, AT);
9335 mips_optimize = hold_mips_optimize;
9344 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9347 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9349 macro_build (&offset_expr, s, "t,o(b)", treg,
9350 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9352 if (!HAVE_64BIT_GPRS)
9354 offset_expr.X_add_number += 4;
9355 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9356 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9377 /* New code added to support COPZ instructions.
9378 This code builds table entries out of the macros in mip_opcodes.
9379 R4000 uses interlocks to handle coproc delays.
9380 Other chips (like the R3000) require nops to be inserted for delays.
9382 FIXME: Currently, we require that the user handle delays.
9383 In order to fill delay slots for non-interlocked chips,
9384 we must have a way to specify delays based on the coprocessor.
9385 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9386 What are the side-effects of the cop instruction?
9387 What cache support might we have and what are its effects?
9388 Both coprocessor & memory require delays. how long???
9389 What registers are read/set/modified?
9391 If an itbl is provided to interpret cop instructions,
9392 this knowledge can be encoded in the itbl spec. */
9406 gas_assert (!mips_opts.micromips);
9407 /* For now we just do C (same as Cz). The parameter will be
9408 stored in insn_opcode by mips_ip. */
9409 macro_build (NULL, s, "C", ip->insn_opcode);
9413 move_register (dreg, sreg);
9419 if (mips_opts.arch == CPU_R5900)
9421 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9425 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9426 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9433 /* The MIPS assembler some times generates shifts and adds. I'm
9434 not trying to be that fancy. GCC should do this for us
9437 load_register (AT, &imm_expr, dbl);
9438 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9439 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9455 load_register (AT, &imm_expr, dbl);
9456 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9457 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9458 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9459 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9461 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9464 if (mips_opts.micromips)
9465 micromips_label_expr (&label_expr);
9467 label_expr.X_add_number = 8;
9468 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9469 macro_build (NULL, "nop", "");
9470 macro_build (NULL, "break", BRK_FMT, 6);
9471 if (mips_opts.micromips)
9472 micromips_add_label ();
9475 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9491 load_register (AT, &imm_expr, dbl);
9492 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9493 sreg, imm ? AT : treg);
9494 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9495 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9497 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9500 if (mips_opts.micromips)
9501 micromips_label_expr (&label_expr);
9503 label_expr.X_add_number = 8;
9504 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9505 macro_build (NULL, "nop", "");
9506 macro_build (NULL, "break", BRK_FMT, 6);
9507 if (mips_opts.micromips)
9508 micromips_add_label ();
9514 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9525 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9526 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9530 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9531 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9532 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9533 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9537 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9548 macro_build (NULL, "negu", "d,w", tempreg, treg);
9549 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9553 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9554 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9555 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9556 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9565 if (imm_expr.X_op != O_constant)
9566 as_bad (_("Improper rotate count"));
9567 rot = imm_expr.X_add_number & 0x3f;
9568 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9570 rot = (64 - rot) & 0x3f;
9572 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9574 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9579 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9582 l = (rot < 0x20) ? "dsll" : "dsll32";
9583 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9586 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9587 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9588 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9596 if (imm_expr.X_op != O_constant)
9597 as_bad (_("Improper rotate count"));
9598 rot = imm_expr.X_add_number & 0x1f;
9599 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9601 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9606 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9610 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9611 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9612 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9617 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9619 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9623 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9624 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9625 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9626 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9630 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9632 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9636 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9637 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9638 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9639 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9648 if (imm_expr.X_op != O_constant)
9649 as_bad (_("Improper rotate count"));
9650 rot = imm_expr.X_add_number & 0x3f;
9651 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9654 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9656 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9661 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9664 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9665 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9668 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9669 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9670 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9678 if (imm_expr.X_op != O_constant)
9679 as_bad (_("Improper rotate count"));
9680 rot = imm_expr.X_add_number & 0x1f;
9681 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9683 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9688 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9692 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9693 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9694 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9700 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9702 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9705 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9706 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9711 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9713 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9718 as_warn (_("Instruction %s: result is always false"),
9720 move_register (dreg, 0);
9723 if (CPU_HAS_SEQ (mips_opts.arch)
9724 && -512 <= imm_expr.X_add_number
9725 && imm_expr.X_add_number < 512)
9727 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9728 (int) imm_expr.X_add_number);
9731 if (imm_expr.X_op == O_constant
9732 && imm_expr.X_add_number >= 0
9733 && imm_expr.X_add_number < 0x10000)
9735 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9737 else if (imm_expr.X_op == O_constant
9738 && imm_expr.X_add_number > -0x8000
9739 && imm_expr.X_add_number < 0)
9741 imm_expr.X_add_number = -imm_expr.X_add_number;
9742 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9743 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9745 else if (CPU_HAS_SEQ (mips_opts.arch))
9748 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9749 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9754 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9755 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9758 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9761 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9767 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9768 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9771 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9773 if (imm_expr.X_op == O_constant
9774 && imm_expr.X_add_number >= -0x8000
9775 && imm_expr.X_add_number < 0x8000)
9777 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9778 dreg, sreg, BFD_RELOC_LO16);
9782 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9783 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9787 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9790 case M_SGT: /* sreg > treg <==> treg < sreg */
9796 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9799 case M_SGT_I: /* sreg > I <==> I < sreg */
9806 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9807 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9810 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9816 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9817 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9820 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9827 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9828 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9829 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9833 if (imm_expr.X_op == O_constant
9834 && imm_expr.X_add_number >= -0x8000
9835 && imm_expr.X_add_number < 0x8000)
9837 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9841 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9842 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9846 if (imm_expr.X_op == O_constant
9847 && imm_expr.X_add_number >= -0x8000
9848 && imm_expr.X_add_number < 0x8000)
9850 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9855 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9856 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9861 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9863 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9866 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9867 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9872 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9874 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9879 as_warn (_("Instruction %s: result is always true"),
9881 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9882 dreg, 0, BFD_RELOC_LO16);
9885 if (CPU_HAS_SEQ (mips_opts.arch)
9886 && -512 <= imm_expr.X_add_number
9887 && imm_expr.X_add_number < 512)
9889 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9890 (int) imm_expr.X_add_number);
9893 if (imm_expr.X_op == O_constant
9894 && imm_expr.X_add_number >= 0
9895 && imm_expr.X_add_number < 0x10000)
9897 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9899 else if (imm_expr.X_op == O_constant
9900 && imm_expr.X_add_number > -0x8000
9901 && imm_expr.X_add_number < 0)
9903 imm_expr.X_add_number = -imm_expr.X_add_number;
9904 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9905 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9907 else if (CPU_HAS_SEQ (mips_opts.arch))
9910 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9911 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9916 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9917 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9920 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9935 if (!mips_opts.micromips)
9937 if (imm_expr.X_op == O_constant
9938 && imm_expr.X_add_number > -0x200
9939 && imm_expr.X_add_number <= 0x200)
9941 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9950 if (imm_expr.X_op == O_constant
9951 && imm_expr.X_add_number > -0x8000
9952 && imm_expr.X_add_number <= 0x8000)
9954 imm_expr.X_add_number = -imm_expr.X_add_number;
9955 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9960 load_register (AT, &imm_expr, dbl);
9961 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9983 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9984 macro_build (NULL, s, "s,t", sreg, AT);
9989 gas_assert (!mips_opts.micromips);
9990 gas_assert (mips_opts.isa == ISA_MIPS1);
9992 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9993 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9996 * Is the double cfc1 instruction a bug in the mips assembler;
9997 * or is there a reason for it?
10000 macro_build (NULL, "cfc1", "t,G", treg, RA);
10001 macro_build (NULL, "cfc1", "t,G", treg, RA);
10002 macro_build (NULL, "nop", "");
10003 expr1.X_add_number = 3;
10004 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10005 expr1.X_add_number = 2;
10006 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10007 macro_build (NULL, "ctc1", "t,G", AT, RA);
10008 macro_build (NULL, "nop", "");
10009 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10011 macro_build (NULL, "ctc1", "t,G", treg, RA);
10012 macro_build (NULL, "nop", "");
10035 off12 = mips_opts.micromips;
10043 off12 = mips_opts.micromips;
10059 off12 = mips_opts.micromips;
10068 off12 = mips_opts.micromips;
10073 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10074 as_bad (_("Operand overflow"));
10077 expr1.X_add_number = 0;
10082 load_address (tempreg, ep, &used_at);
10084 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10085 tempreg, tempreg, breg);
10091 && (offset_expr.X_op != O_constant
10092 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10093 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10097 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10098 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10103 else if (!ust && treg == breg)
10114 if (!target_big_endian)
10115 ep->X_add_number += off;
10117 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10119 macro_build (NULL, s, "t,~(b)",
10120 tempreg, (unsigned long) ep->X_add_number, breg);
10122 if (!target_big_endian)
10123 ep->X_add_number -= off;
10125 ep->X_add_number += off;
10127 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10129 macro_build (NULL, s2, "t,~(b)",
10130 tempreg, (unsigned long) ep->X_add_number, breg);
10132 /* If necessary, move the result in tempreg to the final destination. */
10133 if (!ust && treg != tempreg)
10135 /* Protect second load's delay slot. */
10137 move_register (treg, tempreg);
10143 if (target_big_endian == ust)
10144 ep->X_add_number += off;
10145 tempreg = ust || ab ? treg : AT;
10146 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10148 /* For halfword transfers we need a temporary register to shuffle
10149 bytes. Unfortunately for M_USH_A we have none available before
10150 the next store as AT holds the base address. We deal with this
10151 case by clobbering TREG and then restoring it as with ULH. */
10152 tempreg = ust == ab ? treg : AT;
10154 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10156 if (target_big_endian == ust)
10157 ep->X_add_number -= off;
10159 ep->X_add_number += off;
10160 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10162 /* For M_USH_A re-retrieve the LSB. */
10165 if (target_big_endian)
10166 ep->X_add_number += off;
10168 ep->X_add_number -= off;
10169 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10171 /* For ULH and M_USH_A OR the LSB in. */
10174 tempreg = !ab ? AT : treg;
10175 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10176 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10181 /* FIXME: Check if this is one of the itbl macros, since they
10182 are added dynamically. */
10183 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10186 if (!mips_opts.at && used_at)
10187 as_bad (_("Macro used $at after \".set noat\""));
10190 /* Implement macros in mips16 mode. */
10193 mips16_macro (struct mips_cl_insn *ip)
10196 int xreg, yreg, zreg, tmp;
10199 const char *s, *s2, *s3;
10201 mask = ip->insn_mo->mask;
10203 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10204 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10205 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10207 expr1.X_op = O_constant;
10208 expr1.X_op_symbol = NULL;
10209 expr1.X_add_symbol = NULL;
10210 expr1.X_add_number = 1;
10229 start_noreorder ();
10230 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10231 expr1.X_add_number = 2;
10232 macro_build (&expr1, "bnez", "x,p", yreg);
10233 macro_build (NULL, "break", "6", 7);
10235 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10236 since that causes an overflow. We should do that as well,
10237 but I don't see how to do the comparisons without a temporary
10240 macro_build (NULL, s, "x", zreg);
10259 start_noreorder ();
10260 macro_build (NULL, s, "0,x,y", xreg, yreg);
10261 expr1.X_add_number = 2;
10262 macro_build (&expr1, "bnez", "x,p", yreg);
10263 macro_build (NULL, "break", "6", 7);
10265 macro_build (NULL, s2, "x", zreg);
10271 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10272 macro_build (NULL, "mflo", "x", zreg);
10280 if (imm_expr.X_op != O_constant)
10281 as_bad (_("Unsupported large constant"));
10282 imm_expr.X_add_number = -imm_expr.X_add_number;
10283 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10287 if (imm_expr.X_op != O_constant)
10288 as_bad (_("Unsupported large constant"));
10289 imm_expr.X_add_number = -imm_expr.X_add_number;
10290 macro_build (&imm_expr, "addiu", "x,k", xreg);
10294 if (imm_expr.X_op != O_constant)
10295 as_bad (_("Unsupported large constant"));
10296 imm_expr.X_add_number = -imm_expr.X_add_number;
10297 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10319 goto do_reverse_branch;
10323 goto do_reverse_branch;
10335 goto do_reverse_branch;
10346 macro_build (NULL, s, "x,y", xreg, yreg);
10347 macro_build (&offset_expr, s2, "p");
10374 goto do_addone_branch_i;
10379 goto do_addone_branch_i;
10394 goto do_addone_branch_i;
10400 do_addone_branch_i:
10401 if (imm_expr.X_op != O_constant)
10402 as_bad (_("Unsupported large constant"));
10403 ++imm_expr.X_add_number;
10406 macro_build (&imm_expr, s, s3, xreg);
10407 macro_build (&offset_expr, s2, "p");
10411 expr1.X_add_number = 0;
10412 macro_build (&expr1, "slti", "x,8", yreg);
10414 move_register (xreg, yreg);
10415 expr1.X_add_number = 2;
10416 macro_build (&expr1, "bteqz", "p");
10417 macro_build (NULL, "neg", "x,w", xreg, xreg);
10421 /* For consistency checking, verify that all bits are specified either
10422 by the match/mask part of the instruction definition, or by the
10425 validate_mips_insn (const struct mips_opcode *opc)
10427 const char *p = opc->args;
10429 unsigned long used_bits = opc->mask;
10431 if ((used_bits & opc->match) != opc->match)
10433 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10434 opc->name, opc->args);
10437 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10447 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10448 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10449 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10450 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10451 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10452 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10453 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10454 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10455 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10456 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10457 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10458 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10459 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10461 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10462 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10463 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10464 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10465 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10466 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10467 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10468 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10469 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10470 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10471 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10472 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10473 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10474 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10475 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10476 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10479 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10480 c, opc->name, opc->args);
10484 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10485 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10487 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10488 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10489 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10490 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10492 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10493 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10495 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10496 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10498 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10499 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10500 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10501 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10502 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10503 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10504 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10505 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10506 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10507 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10508 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10509 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10510 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10511 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10512 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10513 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10514 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10516 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10517 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10518 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10519 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10521 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10522 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10523 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10524 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10525 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10526 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10527 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10528 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10529 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10532 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10533 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10534 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10535 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10536 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10539 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10540 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10541 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10542 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10543 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10544 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10545 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10546 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10547 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10548 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10549 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10550 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10551 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10552 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10553 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10554 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10555 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10556 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10557 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10558 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10560 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10561 c, opc->name, opc->args);
10565 if (used_bits != 0xffffffff)
10567 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10568 ~used_bits & 0xffffffff, opc->name, opc->args);
10574 /* For consistency checking, verify that the length implied matches the
10575 major opcode and that all bits are specified either by the match/mask
10576 part of the instruction definition, or by the operand list. */
10579 validate_micromips_insn (const struct mips_opcode *opc)
10581 unsigned long match = opc->match;
10582 unsigned long mask = opc->mask;
10583 const char *p = opc->args;
10584 unsigned long insn_bits;
10585 unsigned long used_bits;
10586 unsigned long major;
10587 unsigned int length;
10591 if ((mask & match) != match)
10593 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10594 opc->name, opc->args);
10597 length = micromips_insn_length (opc);
10598 if (length != 2 && length != 4)
10600 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10601 "%s %s"), length, opc->name, opc->args);
10604 major = match >> (10 + 8 * (length - 2));
10605 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10606 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10608 as_bad (_("Internal error: bad microMIPS opcode "
10609 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10613 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10614 insn_bits = 1 << 4 * length;
10615 insn_bits <<= 4 * length;
10618 #define USE_BITS(field) \
10619 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10630 case 'A': USE_BITS (EXTLSB); break;
10631 case 'B': USE_BITS (INSMSB); break;
10632 case 'C': USE_BITS (EXTMSBD); break;
10633 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10634 case 'E': USE_BITS (EXTLSB); break;
10635 case 'F': USE_BITS (INSMSB); break;
10636 case 'G': USE_BITS (EXTMSBD); break;
10637 case 'H': USE_BITS (EXTMSBD); break;
10639 as_bad (_("Internal error: bad mips opcode "
10640 "(unknown extension operand type `%c%c'): %s %s"),
10641 e, c, opc->name, opc->args);
10649 case 'A': USE_BITS (IMMA); break;
10650 case 'B': USE_BITS (IMMB); break;
10651 case 'C': USE_BITS (IMMC); break;
10652 case 'D': USE_BITS (IMMD); break;
10653 case 'E': USE_BITS (IMME); break;
10654 case 'F': USE_BITS (IMMF); break;
10655 case 'G': USE_BITS (IMMG); break;
10656 case 'H': USE_BITS (IMMH); break;
10657 case 'I': USE_BITS (IMMI); break;
10658 case 'J': USE_BITS (IMMJ); break;
10659 case 'L': USE_BITS (IMML); break;
10660 case 'M': USE_BITS (IMMM); break;
10661 case 'N': USE_BITS (IMMN); break;
10662 case 'O': USE_BITS (IMMO); break;
10663 case 'P': USE_BITS (IMMP); break;
10664 case 'Q': USE_BITS (IMMQ); break;
10665 case 'U': USE_BITS (IMMU); break;
10666 case 'W': USE_BITS (IMMW); break;
10667 case 'X': USE_BITS (IMMX); break;
10668 case 'Y': USE_BITS (IMMY); break;
10671 case 'b': USE_BITS (MB); break;
10672 case 'c': USE_BITS (MC); break;
10673 case 'd': USE_BITS (MD); break;
10674 case 'e': USE_BITS (ME); break;
10675 case 'f': USE_BITS (MF); break;
10676 case 'g': USE_BITS (MG); break;
10677 case 'h': USE_BITS (MH); break;
10678 case 'i': USE_BITS (MI); break;
10679 case 'j': USE_BITS (MJ); break;
10680 case 'l': USE_BITS (ML); break;
10681 case 'm': USE_BITS (MM); break;
10682 case 'n': USE_BITS (MN); break;
10683 case 'p': USE_BITS (MP); break;
10684 case 'q': USE_BITS (MQ); break;
10692 as_bad (_("Internal error: bad mips opcode "
10693 "(unknown extension operand type `%c%c'): %s %s"),
10694 e, c, opc->name, opc->args);
10698 case '.': USE_BITS (OFFSET10); break;
10699 case '1': USE_BITS (STYPE); break;
10700 case '2': USE_BITS (BP); break;
10701 case '3': USE_BITS (SA3); break;
10702 case '4': USE_BITS (SA4); break;
10703 case '5': USE_BITS (IMM8); break;
10704 case '6': USE_BITS (RS); break;
10705 case '7': USE_BITS (DSPACC); break;
10706 case '8': USE_BITS (WRDSP); break;
10707 case '0': USE_BITS (DSPSFT); break;
10708 case '<': USE_BITS (SHAMT); break;
10709 case '>': USE_BITS (SHAMT); break;
10710 case '@': USE_BITS (IMM10); break;
10711 case 'B': USE_BITS (CODE10); break;
10712 case 'C': USE_BITS (COPZ); break;
10713 case 'D': USE_BITS (FD); break;
10714 case 'E': USE_BITS (RT); break;
10715 case 'G': USE_BITS (RS); break;
10716 case 'H': USE_BITS (SEL); break;
10717 case 'K': USE_BITS (RS); break;
10718 case 'M': USE_BITS (CCC); break;
10719 case 'N': USE_BITS (BCC); break;
10720 case 'R': USE_BITS (FR); break;
10721 case 'S': USE_BITS (FS); break;
10722 case 'T': USE_BITS (FT); break;
10723 case 'V': USE_BITS (FS); break;
10724 case '\\': USE_BITS (3BITPOS); break;
10725 case '^': USE_BITS (RD); break;
10726 case 'a': USE_BITS (TARGET); break;
10727 case 'b': USE_BITS (RS); break;
10728 case 'c': USE_BITS (CODE); break;
10729 case 'd': USE_BITS (RD); break;
10730 case 'h': USE_BITS (PREFX); break;
10731 case 'i': USE_BITS (IMMEDIATE); break;
10732 case 'j': USE_BITS (DELTA); break;
10733 case 'k': USE_BITS (CACHE); break;
10734 case 'n': USE_BITS (RT); break;
10735 case 'o': USE_BITS (DELTA); break;
10736 case 'p': USE_BITS (DELTA); break;
10737 case 'q': USE_BITS (CODE2); break;
10738 case 'r': USE_BITS (RS); break;
10739 case 's': USE_BITS (RS); break;
10740 case 't': USE_BITS (RT); break;
10741 case 'u': USE_BITS (IMMEDIATE); break;
10742 case 'v': USE_BITS (RS); break;
10743 case 'w': USE_BITS (RT); break;
10744 case 'y': USE_BITS (RS3); break;
10746 case '|': USE_BITS (TRAP); break;
10747 case '~': USE_BITS (OFFSET12); break;
10749 as_bad (_("Internal error: bad microMIPS opcode "
10750 "(unknown operand type `%c'): %s %s"),
10751 c, opc->name, opc->args);
10755 if (used_bits != insn_bits)
10757 if (~used_bits & insn_bits)
10758 as_bad (_("Internal error: bad microMIPS opcode "
10759 "(bits 0x%lx undefined): %s %s"),
10760 ~used_bits & insn_bits, opc->name, opc->args);
10761 if (used_bits & ~insn_bits)
10762 as_bad (_("Internal error: bad microMIPS opcode "
10763 "(bits 0x%lx defined): %s %s"),
10764 used_bits & ~insn_bits, opc->name, opc->args);
10770 /* UDI immediates. */
10771 struct mips_immed {
10773 unsigned int shift;
10774 unsigned long mask;
10778 static const struct mips_immed mips_immed[] = {
10779 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10780 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10781 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10782 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10786 /* Check whether an odd floating-point register is allowed. */
10788 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10790 const char *s = insn->name;
10792 if (insn->pinfo == INSN_MACRO)
10793 /* Let a macro pass, we'll catch it later when it is expanded. */
10796 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10798 /* Allow odd registers for single-precision ops. */
10799 switch (insn->pinfo & (FP_S | FP_D))
10803 return 1; /* both single precision - ok */
10805 return 0; /* both double precision - fail */
10810 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10811 s = strchr (insn->name, '.');
10813 s = s != NULL ? strchr (s + 1, '.') : NULL;
10814 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10817 /* Single-precision coprocessor loads and moves are OK too. */
10818 if ((insn->pinfo & FP_S)
10819 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10820 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10826 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10827 taking bits from BIT up. */
10829 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10831 return (ep->X_op == O_constant
10832 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10833 && ep->X_add_number >= min << bit
10834 && ep->X_add_number < max << bit);
10837 /* This routine assembles an instruction into its binary format. As a
10838 side effect, it sets one of the global variables imm_reloc or
10839 offset_reloc to the type of relocation to do if one of the operands
10840 is an address expression. */
10843 mips_ip (char *str, struct mips_cl_insn *ip)
10845 bfd_boolean wrong_delay_slot_insns = FALSE;
10846 bfd_boolean need_delay_slot_ok = TRUE;
10847 struct mips_opcode *firstinsn = NULL;
10848 const struct mips_opcode *past;
10849 struct hash_control *hash;
10853 struct mips_opcode *insn;
10855 unsigned int regno;
10856 unsigned int lastregno;
10857 unsigned int destregno = 0;
10858 unsigned int lastpos = 0;
10859 unsigned int limlo, limhi;
10862 offsetT min_range, max_range;
10866 unsigned int rtype;
10872 if (mips_opts.micromips)
10874 hash = micromips_op_hash;
10875 past = µmips_opcodes[bfd_micromips_num_opcodes];
10880 past = &mips_opcodes[NUMOPCODES];
10882 forced_insn_length = 0;
10885 /* We first try to match an instruction up to a space or to the end. */
10886 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10889 /* Make a copy of the instruction so that we can fiddle with it. */
10890 name = alloca (end + 1);
10891 memcpy (name, str, end);
10896 insn = (struct mips_opcode *) hash_find (hash, name);
10898 if (insn != NULL || !mips_opts.micromips)
10900 if (forced_insn_length)
10903 /* See if there's an instruction size override suffix,
10904 either `16' or `32', at the end of the mnemonic proper,
10905 that defines the operation, i.e. before the first `.'
10906 character if any. Strip it and retry. */
10907 dot = strchr (name, '.');
10908 opend = dot != NULL ? dot - name : end;
10911 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10912 forced_insn_length = 2;
10913 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10914 forced_insn_length = 4;
10917 memcpy (name + opend - 2, name + opend, end - opend + 1);
10921 insn_error = _("Unrecognized opcode");
10925 /* For microMIPS instructions placed in a fixed-length branch delay slot
10926 we make up to two passes over the relevant fragment of the opcode
10927 table. First we try instructions that meet the delay slot's length
10928 requirement. If none matched, then we retry with the remaining ones
10929 and if one matches, then we use it and then issue an appropriate
10930 warning later on. */
10931 argsStart = s = str + end;
10934 bfd_boolean delay_slot_ok;
10935 bfd_boolean size_ok;
10938 gas_assert (strcmp (insn->name, name) == 0);
10940 ok = is_opcode_valid (insn);
10941 size_ok = is_size_valid (insn);
10942 delay_slot_ok = is_delay_slot_valid (insn);
10943 if (!delay_slot_ok && !wrong_delay_slot_insns)
10946 wrong_delay_slot_insns = TRUE;
10948 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10950 static char buf[256];
10952 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10957 if (wrong_delay_slot_insns && need_delay_slot_ok)
10959 gas_assert (firstinsn);
10960 need_delay_slot_ok = FALSE;
10970 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10971 mips_cpu_info_from_arch (mips_opts.arch)->name,
10972 mips_cpu_info_from_isa (mips_opts.isa)->name);
10974 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10975 8 * forced_insn_length);
10981 create_insn (ip, insn);
10984 lastregno = 0xffffffff;
10985 for (args = insn->args;; ++args)
10989 s += strspn (s, " \t");
10993 case '\0': /* end of args */
10999 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11000 code) or 14 (for microMIPS code). */
11001 my_getExpression (&imm_expr, s);
11002 check_absolute_expr (ip, &imm_expr);
11003 if ((unsigned long) imm_expr.X_add_number != 1
11004 && (unsigned long) imm_expr.X_add_number != 3)
11006 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11007 (unsigned long) imm_expr.X_add_number);
11009 INSERT_OPERAND (mips_opts.micromips,
11010 BP, *ip, imm_expr.X_add_number);
11011 imm_expr.X_op = O_absent;
11016 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
11017 code) or 21 (for microMIPS code). */
11019 unsigned long mask = (mips_opts.micromips
11020 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11022 my_getExpression (&imm_expr, s);
11023 check_absolute_expr (ip, &imm_expr);
11024 if ((unsigned long) imm_expr.X_add_number > mask)
11025 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11026 mask, (unsigned long) imm_expr.X_add_number);
11027 INSERT_OPERAND (mips_opts.micromips,
11028 SA3, *ip, imm_expr.X_add_number);
11029 imm_expr.X_op = O_absent;
11035 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
11036 code) or 21 (for microMIPS code). */
11038 unsigned long mask = (mips_opts.micromips
11039 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11041 my_getExpression (&imm_expr, s);
11042 check_absolute_expr (ip, &imm_expr);
11043 if ((unsigned long) imm_expr.X_add_number > mask)
11044 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11045 mask, (unsigned long) imm_expr.X_add_number);
11046 INSERT_OPERAND (mips_opts.micromips,
11047 SA4, *ip, imm_expr.X_add_number);
11048 imm_expr.X_op = O_absent;
11054 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
11055 code) or 16 (for microMIPS code). */
11057 unsigned long mask = (mips_opts.micromips
11058 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11060 my_getExpression (&imm_expr, s);
11061 check_absolute_expr (ip, &imm_expr);
11062 if ((unsigned long) imm_expr.X_add_number > mask)
11063 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11064 mask, (unsigned long) imm_expr.X_add_number);
11065 INSERT_OPERAND (mips_opts.micromips,
11066 IMM8, *ip, imm_expr.X_add_number);
11067 imm_expr.X_op = O_absent;
11073 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11074 code) or 21 (for microMIPS code). */
11076 unsigned long mask = (mips_opts.micromips
11077 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11079 my_getExpression (&imm_expr, s);
11080 check_absolute_expr (ip, &imm_expr);
11081 if ((unsigned long) imm_expr.X_add_number > mask)
11082 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11083 mask, (unsigned long) imm_expr.X_add_number);
11084 INSERT_OPERAND (mips_opts.micromips,
11085 RS, *ip, imm_expr.X_add_number);
11086 imm_expr.X_op = O_absent;
11091 case '7': /* Four DSP accumulators in bits 11,12. */
11092 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11093 && s[3] >= '0' && s[3] <= '3')
11095 regno = s[3] - '0';
11097 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11101 as_bad (_("Invalid dsp acc register"));
11105 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11106 code) or 14 (for microMIPS code). */
11108 unsigned long mask = (mips_opts.micromips
11109 ? MICROMIPSOP_MASK_WRDSP
11112 my_getExpression (&imm_expr, s);
11113 check_absolute_expr (ip, &imm_expr);
11114 if ((unsigned long) imm_expr.X_add_number > mask)
11115 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11116 mask, (unsigned long) imm_expr.X_add_number);
11117 INSERT_OPERAND (mips_opts.micromips,
11118 WRDSP, *ip, imm_expr.X_add_number);
11119 imm_expr.X_op = O_absent;
11124 case '9': /* Four DSP accumulators in bits 21,22. */
11125 gas_assert (!mips_opts.micromips);
11126 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11127 && s[3] >= '0' && s[3] <= '3')
11129 regno = s[3] - '0';
11131 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11135 as_bad (_("Invalid dsp acc register"));
11139 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11140 code) or 20 (for microMIPS code). */
11142 long mask = (mips_opts.micromips
11143 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11145 my_getExpression (&imm_expr, s);
11146 check_absolute_expr (ip, &imm_expr);
11147 min_range = -((mask + 1) >> 1);
11148 max_range = ((mask + 1) >> 1) - 1;
11149 if (imm_expr.X_add_number < min_range
11150 || imm_expr.X_add_number > max_range)
11151 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11152 (long) min_range, (long) max_range,
11153 (long) imm_expr.X_add_number);
11154 INSERT_OPERAND (mips_opts.micromips,
11155 DSPSFT, *ip, imm_expr.X_add_number);
11156 imm_expr.X_op = O_absent;
11161 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11162 gas_assert (!mips_opts.micromips);
11163 my_getExpression (&imm_expr, s);
11164 check_absolute_expr (ip, &imm_expr);
11165 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11167 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11169 (unsigned long) imm_expr.X_add_number);
11171 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11172 imm_expr.X_op = O_absent;
11176 case ':': /* DSP 7-bit signed immediate in bit 19. */
11177 gas_assert (!mips_opts.micromips);
11178 my_getExpression (&imm_expr, s);
11179 check_absolute_expr (ip, &imm_expr);
11180 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11181 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11182 if (imm_expr.X_add_number < min_range ||
11183 imm_expr.X_add_number > max_range)
11185 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11186 (long) min_range, (long) max_range,
11187 (long) imm_expr.X_add_number);
11189 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11190 imm_expr.X_op = O_absent;
11194 case '@': /* DSP 10-bit signed immediate in bit 16. */
11196 long mask = (mips_opts.micromips
11197 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11199 my_getExpression (&imm_expr, s);
11200 check_absolute_expr (ip, &imm_expr);
11201 min_range = -((mask + 1) >> 1);
11202 max_range = ((mask + 1) >> 1) - 1;
11203 if (imm_expr.X_add_number < min_range
11204 || imm_expr.X_add_number > max_range)
11205 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11206 (long) min_range, (long) max_range,
11207 (long) imm_expr.X_add_number);
11208 INSERT_OPERAND (mips_opts.micromips,
11209 IMM10, *ip, imm_expr.X_add_number);
11210 imm_expr.X_op = O_absent;
11215 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11216 gas_assert (mips_opts.micromips);
11217 my_getExpression (&imm_expr, s);
11218 check_absolute_expr (ip, &imm_expr);
11219 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11220 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11221 MICROMIPSOP_MASK_RD,
11222 (unsigned long) imm_expr.X_add_number);
11223 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11224 imm_expr.X_op = O_absent;
11228 case '!': /* MT usermode flag bit. */
11229 gas_assert (!mips_opts.micromips);
11230 my_getExpression (&imm_expr, s);
11231 check_absolute_expr (ip, &imm_expr);
11232 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11233 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11234 (unsigned long) imm_expr.X_add_number);
11235 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11236 imm_expr.X_op = O_absent;
11240 case '$': /* MT load high flag bit. */
11241 gas_assert (!mips_opts.micromips);
11242 my_getExpression (&imm_expr, s);
11243 check_absolute_expr (ip, &imm_expr);
11244 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11245 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11246 (unsigned long) imm_expr.X_add_number);
11247 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11248 imm_expr.X_op = O_absent;
11252 case '*': /* Four DSP accumulators in bits 18,19. */
11253 gas_assert (!mips_opts.micromips);
11254 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11255 s[3] >= '0' && s[3] <= '3')
11257 regno = s[3] - '0';
11259 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11263 as_bad (_("Invalid dsp/smartmips acc register"));
11266 case '&': /* Four DSP accumulators in bits 13,14. */
11267 gas_assert (!mips_opts.micromips);
11268 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11269 s[3] >= '0' && s[3] <= '3')
11271 regno = s[3] - '0';
11273 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11277 as_bad (_("Invalid dsp/smartmips acc register"));
11280 case '\\': /* 3-bit bit position. */
11282 unsigned long mask = (mips_opts.micromips
11283 ? MICROMIPSOP_MASK_3BITPOS
11284 : OP_MASK_3BITPOS);
11286 my_getExpression (&imm_expr, s);
11287 check_absolute_expr (ip, &imm_expr);
11288 if ((unsigned long) imm_expr.X_add_number > mask)
11289 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11291 mask, (unsigned long) imm_expr.X_add_number);
11292 INSERT_OPERAND (mips_opts.micromips,
11293 3BITPOS, *ip, imm_expr.X_add_number);
11294 imm_expr.X_op = O_absent;
11308 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11312 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11316 gas_assert (!mips_opts.micromips);
11317 INSERT_OPERAND (0, FT, *ip, lastregno);
11321 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11327 /* Handle optional base register.
11328 Either the base register is omitted or
11329 we must have a left paren. */
11330 /* This is dependent on the next operand specifier
11331 is a base register specification. */
11332 gas_assert (args[1] == 'b'
11333 || (mips_opts.micromips
11335 && (args[2] == 'l' || args[2] == 'n'
11336 || args[2] == 's' || args[2] == 'a')));
11337 if (*s == '\0' && args[1] == 'b')
11339 /* Fall through. */
11341 case ')': /* These must match exactly. */
11346 case '[': /* These must match exactly. */
11348 gas_assert (!mips_opts.micromips);
11353 case '+': /* Opcode extension character. */
11356 case '1': /* UDI immediates. */
11360 gas_assert (!mips_opts.micromips);
11362 const struct mips_immed *imm = mips_immed;
11364 while (imm->type && imm->type != *args)
11368 my_getExpression (&imm_expr, s);
11369 check_absolute_expr (ip, &imm_expr);
11370 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11372 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11373 imm->desc ? imm->desc : ip->insn_mo->name,
11374 (unsigned long) imm_expr.X_add_number,
11375 (unsigned long) imm_expr.X_add_number);
11376 imm_expr.X_add_number &= imm->mask;
11378 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11380 imm_expr.X_op = O_absent;
11385 case 'J': /* 10-bit hypcall code. */
11386 gas_assert (!mips_opts.micromips);
11388 unsigned long mask = OP_MASK_CODE10;
11390 my_getExpression (&imm_expr, s);
11391 check_absolute_expr (ip, &imm_expr);
11392 if ((unsigned long) imm_expr.X_add_number > mask)
11393 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11395 mask, (unsigned long) imm_expr.X_add_number);
11396 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11397 imm_expr.X_op = O_absent;
11402 case 'A': /* ins/ext position, becomes LSB. */
11411 my_getExpression (&imm_expr, s);
11412 check_absolute_expr (ip, &imm_expr);
11413 if ((unsigned long) imm_expr.X_add_number < limlo
11414 || (unsigned long) imm_expr.X_add_number > limhi)
11416 as_bad (_("Improper position (%lu)"),
11417 (unsigned long) imm_expr.X_add_number);
11418 imm_expr.X_add_number = limlo;
11420 lastpos = imm_expr.X_add_number;
11421 INSERT_OPERAND (mips_opts.micromips,
11422 EXTLSB, *ip, imm_expr.X_add_number);
11423 imm_expr.X_op = O_absent;
11427 case 'B': /* ins size, becomes MSB. */
11436 my_getExpression (&imm_expr, s);
11437 check_absolute_expr (ip, &imm_expr);
11438 /* Check for negative input so that small negative numbers
11439 will not succeed incorrectly. The checks against
11440 (pos+size) transitively check "size" itself,
11441 assuming that "pos" is reasonable. */
11442 if ((long) imm_expr.X_add_number < 0
11443 || ((unsigned long) imm_expr.X_add_number
11445 || ((unsigned long) imm_expr.X_add_number
11446 + lastpos) > limhi)
11448 as_bad (_("Improper insert size (%lu, position %lu)"),
11449 (unsigned long) imm_expr.X_add_number,
11450 (unsigned long) lastpos);
11451 imm_expr.X_add_number = limlo - lastpos;
11453 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11454 lastpos + imm_expr.X_add_number - 1);
11455 imm_expr.X_op = O_absent;
11459 case 'C': /* ext size, becomes MSBD. */
11475 my_getExpression (&imm_expr, s);
11476 check_absolute_expr (ip, &imm_expr);
11477 /* The checks against (pos+size) don't transitively check
11478 "size" itself, assuming that "pos" is reasonable.
11479 We also need to check the lower bound of "size". */
11480 if ((long) imm_expr.X_add_number < sizelo
11481 || ((unsigned long) imm_expr.X_add_number
11483 || ((unsigned long) imm_expr.X_add_number
11484 + lastpos) > limhi)
11486 as_bad (_("Improper extract size (%lu, position %lu)"),
11487 (unsigned long) imm_expr.X_add_number,
11488 (unsigned long) lastpos);
11489 imm_expr.X_add_number = limlo - lastpos;
11491 INSERT_OPERAND (mips_opts.micromips,
11492 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11493 imm_expr.X_op = O_absent;
11498 /* +D is for disassembly only; never match. */
11502 /* "+I" is like "I", except that imm2_expr is used. */
11503 my_getExpression (&imm2_expr, s);
11504 if (imm2_expr.X_op != O_big
11505 && imm2_expr.X_op != O_constant)
11506 insn_error = _("absolute expression required");
11507 if (HAVE_32BIT_GPRS)
11508 normalize_constant_expr (&imm2_expr);
11512 case 'T': /* Coprocessor register. */
11513 gas_assert (!mips_opts.micromips);
11514 /* +T is for disassembly only; never match. */
11517 case 't': /* Coprocessor register number. */
11518 gas_assert (!mips_opts.micromips);
11519 if (s[0] == '$' && ISDIGIT (s[1]))
11529 while (ISDIGIT (*s));
11531 as_bad (_("Invalid register number (%d)"), regno);
11534 INSERT_OPERAND (0, RT, *ip, regno);
11539 as_bad (_("Invalid coprocessor 0 register number"));
11543 /* bbit[01] and bbit[01]32 bit index. Give error if index
11544 is not in the valid range. */
11545 gas_assert (!mips_opts.micromips);
11546 my_getExpression (&imm_expr, s);
11547 check_absolute_expr (ip, &imm_expr);
11548 if ((unsigned) imm_expr.X_add_number > 31)
11550 as_bad (_("Improper bit index (%lu)"),
11551 (unsigned long) imm_expr.X_add_number);
11552 imm_expr.X_add_number = 0;
11554 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11555 imm_expr.X_op = O_absent;
11560 /* bbit[01] bit index when bbit is used but we generate
11561 bbit[01]32 because the index is over 32. Move to the
11562 next candidate if index is not in the valid range. */
11563 gas_assert (!mips_opts.micromips);
11564 my_getExpression (&imm_expr, s);
11565 check_absolute_expr (ip, &imm_expr);
11566 if ((unsigned) imm_expr.X_add_number < 32
11567 || (unsigned) imm_expr.X_add_number > 63)
11569 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11570 imm_expr.X_op = O_absent;
11575 /* cins, cins32, exts and exts32 position field. Give error
11576 if it's not in the valid range. */
11577 gas_assert (!mips_opts.micromips);
11578 my_getExpression (&imm_expr, s);
11579 check_absolute_expr (ip, &imm_expr);
11580 if ((unsigned) imm_expr.X_add_number > 31)
11582 as_bad (_("Improper position (%lu)"),
11583 (unsigned long) imm_expr.X_add_number);
11584 imm_expr.X_add_number = 0;
11586 /* Make the pos explicit to simplify +S. */
11587 lastpos = imm_expr.X_add_number + 32;
11588 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11589 imm_expr.X_op = O_absent;
11594 /* cins, cins32, exts and exts32 position field. Move to
11595 the next candidate if it's not in the valid range. */
11596 gas_assert (!mips_opts.micromips);
11597 my_getExpression (&imm_expr, s);
11598 check_absolute_expr (ip, &imm_expr);
11599 if ((unsigned) imm_expr.X_add_number < 32
11600 || (unsigned) imm_expr.X_add_number > 63)
11602 lastpos = imm_expr.X_add_number;
11603 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11604 imm_expr.X_op = O_absent;
11609 /* cins and exts length-minus-one field. */
11610 gas_assert (!mips_opts.micromips);
11611 my_getExpression (&imm_expr, s);
11612 check_absolute_expr (ip, &imm_expr);
11613 if ((unsigned long) imm_expr.X_add_number > 31)
11615 as_bad (_("Improper size (%lu)"),
11616 (unsigned long) imm_expr.X_add_number);
11617 imm_expr.X_add_number = 0;
11619 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11620 imm_expr.X_op = O_absent;
11625 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11626 length-minus-one field. */
11627 gas_assert (!mips_opts.micromips);
11628 my_getExpression (&imm_expr, s);
11629 check_absolute_expr (ip, &imm_expr);
11630 if ((long) imm_expr.X_add_number < 0
11631 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11633 as_bad (_("Improper size (%lu)"),
11634 (unsigned long) imm_expr.X_add_number);
11635 imm_expr.X_add_number = 0;
11637 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11638 imm_expr.X_op = O_absent;
11643 /* seqi/snei immediate field. */
11644 gas_assert (!mips_opts.micromips);
11645 my_getExpression (&imm_expr, s);
11646 check_absolute_expr (ip, &imm_expr);
11647 if ((long) imm_expr.X_add_number < -512
11648 || (long) imm_expr.X_add_number >= 512)
11650 as_bad (_("Improper immediate (%ld)"),
11651 (long) imm_expr.X_add_number);
11652 imm_expr.X_add_number = 0;
11654 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11655 imm_expr.X_op = O_absent;
11659 case 'a': /* 8-bit signed offset in bit 6 */
11660 gas_assert (!mips_opts.micromips);
11661 my_getExpression (&imm_expr, s);
11662 check_absolute_expr (ip, &imm_expr);
11663 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11664 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11665 if (imm_expr.X_add_number < min_range
11666 || imm_expr.X_add_number > max_range)
11668 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11669 (long) min_range, (long) max_range,
11670 (long) imm_expr.X_add_number);
11672 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11673 imm_expr.X_op = O_absent;
11677 case 'b': /* 8-bit signed offset in bit 3 */
11678 gas_assert (!mips_opts.micromips);
11679 my_getExpression (&imm_expr, s);
11680 check_absolute_expr (ip, &imm_expr);
11681 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11682 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11683 if (imm_expr.X_add_number < min_range
11684 || imm_expr.X_add_number > max_range)
11686 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11687 (long) min_range, (long) max_range,
11688 (long) imm_expr.X_add_number);
11690 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11691 imm_expr.X_op = O_absent;
11695 case 'c': /* 9-bit signed offset in bit 6 */
11696 gas_assert (!mips_opts.micromips);
11697 my_getExpression (&imm_expr, s);
11698 check_absolute_expr (ip, &imm_expr);
11699 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11700 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11701 /* We check the offset range before adjusted. */
11704 if (imm_expr.X_add_number < min_range
11705 || imm_expr.X_add_number > max_range)
11707 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11708 (long) min_range, (long) max_range,
11709 (long) imm_expr.X_add_number);
11711 if (imm_expr.X_add_number & 0xf)
11713 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11714 (long) imm_expr.X_add_number);
11716 /* Right shift 4 bits to adjust the offset operand. */
11717 INSERT_OPERAND (0, OFFSET_C, *ip,
11718 imm_expr.X_add_number >> 4);
11719 imm_expr.X_op = O_absent;
11724 gas_assert (!mips_opts.micromips);
11725 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11727 if (regno == AT && mips_opts.at)
11729 if (mips_opts.at == ATREG)
11730 as_warn (_("used $at without \".set noat\""));
11732 as_warn (_("used $%u with \".set at=$%u\""),
11733 regno, mips_opts.at);
11735 INSERT_OPERAND (0, RZ, *ip, regno);
11739 gas_assert (!mips_opts.micromips);
11740 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11742 INSERT_OPERAND (0, FZ, *ip, regno);
11746 as_bad (_("Internal error: bad %s opcode "
11747 "(unknown extension operand type `+%c'): %s %s"),
11748 mips_opts.micromips ? "microMIPS" : "MIPS",
11749 *args, insn->name, insn->args);
11750 /* Further processing is fruitless. */
11755 case '.': /* 10-bit offset. */
11756 gas_assert (mips_opts.micromips);
11757 case '~': /* 12-bit offset. */
11759 int shift = *args == '.' ? 9 : 11;
11762 /* Check whether there is only a single bracketed expression
11763 left. If so, it must be the base register and the
11764 constant must be zero. */
11765 if (*s == '(' && strchr (s + 1, '(') == 0)
11768 /* If this value won't fit into the offset, then go find
11769 a macro that will generate a 16- or 32-bit offset code
11771 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11772 if ((i == 0 && (imm_expr.X_op != O_constant
11773 || imm_expr.X_add_number >= 1 << shift
11774 || imm_expr.X_add_number < -1 << shift))
11777 imm_expr.X_op = O_absent;
11781 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11783 INSERT_OPERAND (mips_opts.micromips,
11784 OFFSET12, *ip, imm_expr.X_add_number);
11785 imm_expr.X_op = O_absent;
11790 case '<': /* must be at least one digit */
11792 * According to the manual, if the shift amount is greater
11793 * than 31 or less than 0, then the shift amount should be
11794 * mod 32. In reality the mips assembler issues an error.
11795 * We issue a warning and mask out all but the low 5 bits.
11797 my_getExpression (&imm_expr, s);
11798 check_absolute_expr (ip, &imm_expr);
11799 if ((unsigned long) imm_expr.X_add_number > 31)
11800 as_warn (_("Improper shift amount (%lu)"),
11801 (unsigned long) imm_expr.X_add_number);
11802 INSERT_OPERAND (mips_opts.micromips,
11803 SHAMT, *ip, imm_expr.X_add_number);
11804 imm_expr.X_op = O_absent;
11808 case '>': /* shift amount minus 32 */
11809 my_getExpression (&imm_expr, s);
11810 check_absolute_expr (ip, &imm_expr);
11811 if ((unsigned long) imm_expr.X_add_number < 32
11812 || (unsigned long) imm_expr.X_add_number > 63)
11814 INSERT_OPERAND (mips_opts.micromips,
11815 SHAMT, *ip, imm_expr.X_add_number - 32);
11816 imm_expr.X_op = O_absent;
11820 case 'k': /* CACHE code. */
11821 case 'h': /* PREFX code. */
11822 case '1': /* SYNC type. */
11823 my_getExpression (&imm_expr, s);
11824 check_absolute_expr (ip, &imm_expr);
11825 if ((unsigned long) imm_expr.X_add_number > 31)
11826 as_warn (_("Invalid value for `%s' (%lu)"),
11828 (unsigned long) imm_expr.X_add_number);
11832 if (mips_fix_cn63xxp1
11833 && !mips_opts.micromips
11834 && strcmp ("pref", insn->name) == 0)
11835 switch (imm_expr.X_add_number)
11844 case 31: /* These are ok. */
11847 default: /* The rest must be changed to 28. */
11848 imm_expr.X_add_number = 28;
11851 INSERT_OPERAND (mips_opts.micromips,
11852 CACHE, *ip, imm_expr.X_add_number);
11855 INSERT_OPERAND (mips_opts.micromips,
11856 PREFX, *ip, imm_expr.X_add_number);
11859 INSERT_OPERAND (mips_opts.micromips,
11860 STYPE, *ip, imm_expr.X_add_number);
11863 imm_expr.X_op = O_absent;
11867 case 'c': /* BREAK code. */
11869 unsigned long mask = (mips_opts.micromips
11870 ? MICROMIPSOP_MASK_CODE
11873 my_getExpression (&imm_expr, s);
11874 check_absolute_expr (ip, &imm_expr);
11875 if ((unsigned long) imm_expr.X_add_number > mask)
11876 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11878 mask, (unsigned long) imm_expr.X_add_number);
11879 INSERT_OPERAND (mips_opts.micromips,
11880 CODE, *ip, imm_expr.X_add_number);
11881 imm_expr.X_op = O_absent;
11886 case 'q': /* Lower BREAK code. */
11888 unsigned long mask = (mips_opts.micromips
11889 ? MICROMIPSOP_MASK_CODE2
11892 my_getExpression (&imm_expr, s);
11893 check_absolute_expr (ip, &imm_expr);
11894 if ((unsigned long) imm_expr.X_add_number > mask)
11895 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11897 mask, (unsigned long) imm_expr.X_add_number);
11898 INSERT_OPERAND (mips_opts.micromips,
11899 CODE2, *ip, imm_expr.X_add_number);
11900 imm_expr.X_op = O_absent;
11905 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11907 unsigned long mask = (mips_opts.micromips
11908 ? MICROMIPSOP_MASK_CODE10
11911 my_getExpression (&imm_expr, s);
11912 check_absolute_expr (ip, &imm_expr);
11913 if ((unsigned long) imm_expr.X_add_number > mask)
11914 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11916 mask, (unsigned long) imm_expr.X_add_number);
11917 if (mips_opts.micromips)
11918 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11920 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11921 imm_expr.X_op = O_absent;
11926 case 'C': /* 25- or 23-bit coprocessor code. */
11928 unsigned long mask = (mips_opts.micromips
11929 ? MICROMIPSOP_MASK_COPZ
11932 my_getExpression (&imm_expr, s);
11933 check_absolute_expr (ip, &imm_expr);
11934 if ((unsigned long) imm_expr.X_add_number > mask)
11935 as_warn (_("Coproccesor code > %u bits (%lu)"),
11936 mips_opts.micromips ? 23U : 25U,
11937 (unsigned long) imm_expr.X_add_number);
11938 INSERT_OPERAND (mips_opts.micromips,
11939 COPZ, *ip, imm_expr.X_add_number);
11940 imm_expr.X_op = O_absent;
11945 case 'J': /* 19-bit WAIT code. */
11946 gas_assert (!mips_opts.micromips);
11947 my_getExpression (&imm_expr, s);
11948 check_absolute_expr (ip, &imm_expr);
11949 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11951 as_warn (_("Illegal 19-bit code (%lu)"),
11952 (unsigned long) imm_expr.X_add_number);
11953 imm_expr.X_add_number &= OP_MASK_CODE19;
11955 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11956 imm_expr.X_op = O_absent;
11960 case 'P': /* Performance register. */
11961 gas_assert (!mips_opts.micromips);
11962 my_getExpression (&imm_expr, s);
11963 check_absolute_expr (ip, &imm_expr);
11964 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11965 as_warn (_("Invalid performance register (%lu)"),
11966 (unsigned long) imm_expr.X_add_number);
11967 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
11968 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
11969 as_warn (_("Invalid performance register (%lu)"),
11970 (unsigned long) imm_expr.X_add_number);
11971 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11972 imm_expr.X_op = O_absent;
11976 case 'G': /* Coprocessor destination register. */
11978 unsigned long opcode = ip->insn_opcode;
11979 unsigned long mask;
11980 unsigned int types;
11983 if (mips_opts.micromips)
11985 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11986 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11987 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11991 case 0x000000fc: /* mfc0 */
11992 case 0x000002fc: /* mtc0 */
11993 case 0x580000fc: /* dmfc0 */
11994 case 0x580002fc: /* dmtc0 */
12004 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12005 cop0 = opcode == OP_OP_COP0;
12007 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12008 ok = reg_lookup (&s, types, ®no);
12009 if (mips_opts.micromips)
12010 INSERT_OPERAND (1, RS, *ip, regno);
12012 INSERT_OPERAND (0, RD, *ip, regno);
12021 case 'y': /* ALNV.PS source register. */
12022 gas_assert (mips_opts.micromips);
12024 case 'x': /* Ignore register name. */
12025 case 'U': /* Destination register (CLO/CLZ). */
12026 case 'g': /* Coprocessor destination register. */
12027 gas_assert (!mips_opts.micromips);
12028 case 'b': /* Base register. */
12029 case 'd': /* Destination register. */
12030 case 's': /* Source register. */
12031 case 't': /* Target register. */
12032 case 'r': /* Both target and source. */
12033 case 'v': /* Both dest and source. */
12034 case 'w': /* Both dest and target. */
12035 case 'E': /* Coprocessor target register. */
12036 case 'K': /* RDHWR destination register. */
12037 case 'z': /* Must be zero register. */
12040 if (*args == 'E' || *args == 'K')
12041 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12044 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12045 if (regno == AT && mips_opts.at)
12047 if (mips_opts.at == ATREG)
12048 as_warn (_("Used $at without \".set noat\""));
12050 as_warn (_("Used $%u with \".set at=$%u\""),
12051 regno, mips_opts.at);
12061 if (c == 'r' || c == 'v' || c == 'w')
12068 /* 'z' only matches $0. */
12069 if (c == 'z' && regno != 0)
12072 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12074 if (regno == lastregno)
12077 = _("Source and destination must be different");
12080 if (regno == 31 && lastregno == 0xffffffff)
12083 = _("A destination register must be supplied");
12087 /* Now that we have assembled one operand, we use the args
12088 string to figure out where it goes in the instruction. */
12095 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12099 if (mips_opts.micromips)
12100 INSERT_OPERAND (1, RS, *ip, regno);
12102 INSERT_OPERAND (0, RD, *ip, regno);
12107 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12111 gas_assert (!mips_opts.micromips);
12112 INSERT_OPERAND (0, RD, *ip, regno);
12113 INSERT_OPERAND (0, RT, *ip, regno);
12119 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12123 gas_assert (mips_opts.micromips);
12124 INSERT_OPERAND (1, RS3, *ip, regno);
12128 /* This case exists because on the r3000 trunc
12129 expands into a macro which requires a gp
12130 register. On the r6000 or r4000 it is
12131 assembled into a single instruction which
12132 ignores the register. Thus the insn version
12133 is MIPS_ISA2 and uses 'x', and the macro
12134 version is MIPS_ISA1 and uses 't'. */
12138 /* This case is for the div instruction, which
12139 acts differently if the destination argument
12140 is $0. This only matches $0, and is checked
12141 outside the switch. */
12151 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12155 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12160 case 'O': /* MDMX alignment immediate constant. */
12161 gas_assert (!mips_opts.micromips);
12162 my_getExpression (&imm_expr, s);
12163 check_absolute_expr (ip, &imm_expr);
12164 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12165 as_warn (_("Improper align amount (%ld), using low bits"),
12166 (long) imm_expr.X_add_number);
12167 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12168 imm_expr.X_op = O_absent;
12172 case 'Q': /* MDMX vector, element sel, or const. */
12175 /* MDMX Immediate. */
12176 gas_assert (!mips_opts.micromips);
12177 my_getExpression (&imm_expr, s);
12178 check_absolute_expr (ip, &imm_expr);
12179 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12180 as_warn (_("Invalid MDMX Immediate (%ld)"),
12181 (long) imm_expr.X_add_number);
12182 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12183 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12184 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12186 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12187 imm_expr.X_op = O_absent;
12191 /* Not MDMX Immediate. Fall through. */
12192 case 'X': /* MDMX destination register. */
12193 case 'Y': /* MDMX source register. */
12194 case 'Z': /* MDMX target register. */
12197 gas_assert (!mips_opts.micromips);
12198 case 'D': /* Floating point destination register. */
12199 case 'S': /* Floating point source register. */
12200 case 'T': /* Floating point target register. */
12201 case 'R': /* Floating point source register. */
12205 || (mips_opts.ase_mdmx
12206 && (ip->insn_mo->pinfo & FP_D)
12207 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12208 | INSN_COPROC_MEMORY_DELAY
12209 | INSN_LOAD_COPROC_DELAY
12210 | INSN_LOAD_MEMORY_DELAY
12211 | INSN_STORE_MEMORY))))
12212 rtype |= RTYPE_VEC;
12214 if (reg_lookup (&s, rtype, ®no))
12216 if ((regno & 1) != 0
12218 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12219 as_warn (_("Float register should be even, was %d"),
12227 if (c == 'V' || c == 'W')
12238 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12244 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12248 /* This is like 'Z', but also needs to fix the MDMX
12249 vector/scalar select bits. Note that the
12250 scalar immediate case is handled above. */
12253 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12254 int max_el = (is_qh ? 3 : 7);
12256 my_getExpression(&imm_expr, s);
12257 check_absolute_expr (ip, &imm_expr);
12259 if (imm_expr.X_add_number > max_el)
12260 as_bad (_("Bad element selector %ld"),
12261 (long) imm_expr.X_add_number);
12262 imm_expr.X_add_number &= max_el;
12263 ip->insn_opcode |= (imm_expr.X_add_number
12266 imm_expr.X_op = O_absent;
12268 as_warn (_("Expecting ']' found '%s'"), s);
12274 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12275 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12278 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12281 /* Fall through. */
12285 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12289 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12299 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12303 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12309 my_getExpression (&imm_expr, s);
12310 if (imm_expr.X_op != O_big
12311 && imm_expr.X_op != O_constant)
12312 insn_error = _("absolute expression required");
12313 if (HAVE_32BIT_GPRS)
12314 normalize_constant_expr (&imm_expr);
12319 my_getExpression (&offset_expr, s);
12320 normalize_address_expr (&offset_expr);
12321 *imm_reloc = BFD_RELOC_32;
12334 unsigned char temp[8];
12336 unsigned int length;
12341 /* These only appear as the last operand in an
12342 instruction, and every instruction that accepts
12343 them in any variant accepts them in all variants.
12344 This means we don't have to worry about backing out
12345 any changes if the instruction does not match.
12347 The difference between them is the size of the
12348 floating point constant and where it goes. For 'F'
12349 and 'L' the constant is 64 bits; for 'f' and 'l' it
12350 is 32 bits. Where the constant is placed is based
12351 on how the MIPS assembler does things:
12354 f -- immediate value
12357 The .lit4 and .lit8 sections are only used if
12358 permitted by the -G argument.
12360 The code below needs to know whether the target register
12361 is 32 or 64 bits wide. It relies on the fact 'f' and
12362 'F' are used with GPR-based instructions and 'l' and
12363 'L' are used with FPR-based instructions. */
12365 f64 = *args == 'F' || *args == 'L';
12366 using_gprs = *args == 'F' || *args == 'f';
12368 save_in = input_line_pointer;
12369 input_line_pointer = s;
12370 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12372 s = input_line_pointer;
12373 input_line_pointer = save_in;
12374 if (err != NULL && *err != '\0')
12376 as_bad (_("Bad floating point constant: %s"), err);
12377 memset (temp, '\0', sizeof temp);
12378 length = f64 ? 8 : 4;
12381 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12385 && (g_switch_value < 4
12386 || (temp[0] == 0 && temp[1] == 0)
12387 || (temp[2] == 0 && temp[3] == 0))))
12389 imm_expr.X_op = O_constant;
12390 if (!target_big_endian)
12391 imm_expr.X_add_number = bfd_getl32 (temp);
12393 imm_expr.X_add_number = bfd_getb32 (temp);
12395 else if (length > 4
12396 && !mips_disable_float_construction
12397 /* Constants can only be constructed in GPRs and
12398 copied to FPRs if the GPRs are at least as wide
12399 as the FPRs. Force the constant into memory if
12400 we are using 64-bit FPRs but the GPRs are only
12403 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12404 && ((temp[0] == 0 && temp[1] == 0)
12405 || (temp[2] == 0 && temp[3] == 0))
12406 && ((temp[4] == 0 && temp[5] == 0)
12407 || (temp[6] == 0 && temp[7] == 0)))
12409 /* The value is simple enough to load with a couple of
12410 instructions. If using 32-bit registers, set
12411 imm_expr to the high order 32 bits and offset_expr to
12412 the low order 32 bits. Otherwise, set imm_expr to
12413 the entire 64 bit constant. */
12414 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12416 imm_expr.X_op = O_constant;
12417 offset_expr.X_op = O_constant;
12418 if (!target_big_endian)
12420 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12421 offset_expr.X_add_number = bfd_getl32 (temp);
12425 imm_expr.X_add_number = bfd_getb32 (temp);
12426 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12428 if (offset_expr.X_add_number == 0)
12429 offset_expr.X_op = O_absent;
12431 else if (sizeof (imm_expr.X_add_number) > 4)
12433 imm_expr.X_op = O_constant;
12434 if (!target_big_endian)
12435 imm_expr.X_add_number = bfd_getl64 (temp);
12437 imm_expr.X_add_number = bfd_getb64 (temp);
12441 imm_expr.X_op = O_big;
12442 imm_expr.X_add_number = 4;
12443 if (!target_big_endian)
12445 generic_bignum[0] = bfd_getl16 (temp);
12446 generic_bignum[1] = bfd_getl16 (temp + 2);
12447 generic_bignum[2] = bfd_getl16 (temp + 4);
12448 generic_bignum[3] = bfd_getl16 (temp + 6);
12452 generic_bignum[0] = bfd_getb16 (temp + 6);
12453 generic_bignum[1] = bfd_getb16 (temp + 4);
12454 generic_bignum[2] = bfd_getb16 (temp + 2);
12455 generic_bignum[3] = bfd_getb16 (temp);
12461 const char *newname;
12464 /* Switch to the right section. */
12466 subseg = now_subseg;
12469 default: /* unused default case avoids warnings. */
12471 newname = RDATA_SECTION_NAME;
12472 if (g_switch_value >= 8)
12476 newname = RDATA_SECTION_NAME;
12479 gas_assert (g_switch_value >= 4);
12483 new_seg = subseg_new (newname, (subsegT) 0);
12485 bfd_set_section_flags (stdoutput, new_seg,
12490 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12491 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12492 record_alignment (new_seg, 4);
12494 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12495 if (seg == now_seg)
12496 as_bad (_("Can't use floating point insn in this section"));
12498 /* Set the argument to the current address in the
12500 offset_expr.X_op = O_symbol;
12501 offset_expr.X_add_symbol = symbol_temp_new_now ();
12502 offset_expr.X_add_number = 0;
12504 /* Put the floating point number into the section. */
12505 p = frag_more ((int) length);
12506 memcpy (p, temp, length);
12508 /* Switch back to the original section. */
12509 subseg_set (seg, subseg);
12514 case 'i': /* 16-bit unsigned immediate. */
12515 case 'j': /* 16-bit signed immediate. */
12516 *imm_reloc = BFD_RELOC_LO16;
12517 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12520 offsetT minval, maxval;
12522 more = (insn + 1 < past
12523 && strcmp (insn->name, insn[1].name) == 0);
12525 /* If the expression was written as an unsigned number,
12526 only treat it as signed if there are no more
12530 && sizeof (imm_expr.X_add_number) <= 4
12531 && imm_expr.X_op == O_constant
12532 && imm_expr.X_add_number < 0
12533 && imm_expr.X_unsigned
12534 && HAVE_64BIT_GPRS)
12537 /* For compatibility with older assemblers, we accept
12538 0x8000-0xffff as signed 16-bit numbers when only
12539 signed numbers are allowed. */
12541 minval = 0, maxval = 0xffff;
12543 minval = -0x8000, maxval = 0x7fff;
12545 minval = -0x8000, maxval = 0xffff;
12547 if (imm_expr.X_op != O_constant
12548 || imm_expr.X_add_number < minval
12549 || imm_expr.X_add_number > maxval)
12553 if (imm_expr.X_op == O_constant
12554 || imm_expr.X_op == O_big)
12555 as_bad (_("Expression out of range"));
12561 case 'o': /* 16-bit offset. */
12562 offset_reloc[0] = BFD_RELOC_LO16;
12563 offset_reloc[1] = BFD_RELOC_UNUSED;
12564 offset_reloc[2] = BFD_RELOC_UNUSED;
12566 /* Check whether there is only a single bracketed expression
12567 left. If so, it must be the base register and the
12568 constant must be zero. */
12569 if (*s == '(' && strchr (s + 1, '(') == 0)
12571 offset_expr.X_op = O_constant;
12572 offset_expr.X_add_number = 0;
12576 /* If this value won't fit into a 16 bit offset, then go
12577 find a macro that will generate the 32 bit offset
12579 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12580 && (offset_expr.X_op != O_constant
12581 || offset_expr.X_add_number >= 0x8000
12582 || offset_expr.X_add_number < -0x8000))
12588 case 'p': /* PC-relative offset. */
12589 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12590 my_getExpression (&offset_expr, s);
12594 case 'u': /* Upper 16 bits. */
12595 *imm_reloc = BFD_RELOC_LO16;
12596 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12597 && imm_expr.X_op == O_constant
12598 && (imm_expr.X_add_number < 0
12599 || imm_expr.X_add_number >= 0x10000))
12600 as_bad (_("lui expression (%lu) not in range 0..65535"),
12601 (unsigned long) imm_expr.X_add_number);
12605 case 'a': /* 26-bit address. */
12606 *offset_reloc = BFD_RELOC_MIPS_JMP;
12607 my_getExpression (&offset_expr, s);
12611 case 'N': /* 3-bit branch condition code. */
12612 case 'M': /* 3-bit compare condition code. */
12614 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12615 rtype |= RTYPE_FCC;
12616 if (!reg_lookup (&s, rtype, ®no))
12618 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12619 || strcmp (str + strlen (str) - 5, "any2f") == 0
12620 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12621 && (regno & 1) != 0)
12622 as_warn (_("Condition code register should be even for %s, "
12625 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12626 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12627 && (regno & 3) != 0)
12628 as_warn (_("Condition code register should be 0 or 4 for %s, "
12632 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12634 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12638 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12649 while (ISDIGIT (*s));
12652 c = 8; /* Invalid sel value. */
12655 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12656 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12660 gas_assert (!mips_opts.micromips);
12661 /* Must be at least one digit. */
12662 my_getExpression (&imm_expr, s);
12663 check_absolute_expr (ip, &imm_expr);
12665 if ((unsigned long) imm_expr.X_add_number
12666 > (unsigned long) OP_MASK_VECBYTE)
12668 as_bad (_("bad byte vector index (%ld)"),
12669 (long) imm_expr.X_add_number);
12670 imm_expr.X_add_number = 0;
12673 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12674 imm_expr.X_op = O_absent;
12679 gas_assert (!mips_opts.micromips);
12680 my_getExpression (&imm_expr, s);
12681 check_absolute_expr (ip, &imm_expr);
12683 if ((unsigned long) imm_expr.X_add_number
12684 > (unsigned long) OP_MASK_VECALIGN)
12686 as_bad (_("bad byte vector index (%ld)"),
12687 (long) imm_expr.X_add_number);
12688 imm_expr.X_add_number = 0;
12691 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12692 imm_expr.X_op = O_absent;
12696 case 'm': /* Opcode extension character. */
12697 gas_assert (mips_opts.micromips);
12702 if (strncmp (s, "$pc", 3) == 0)
12730 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12731 if (regno == AT && mips_opts.at)
12733 if (mips_opts.at == ATREG)
12734 as_warn (_("Used $at without \".set noat\""));
12736 as_warn (_("Used $%u with \".set at=$%u\""),
12737 regno, mips_opts.at);
12743 gas_assert (args[1] == ',');
12749 gas_assert (args[1] == ',');
12751 continue; /* Nothing to do. */
12757 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12759 if (regno == lastregno)
12762 = _("Source and destination must be different");
12765 if (regno == 31 && lastregno == 0xffffffff)
12768 = _("A destination register must be supplied");
12779 gas_assert (args[1] == ',');
12786 gas_assert (args[1] == ',');
12789 continue; /* Nothing to do. */
12793 /* Make sure regno is the same as lastregno. */
12794 if (c == 't' && regno != lastregno)
12797 /* Make sure regno is the same as destregno. */
12798 if (c == 'x' && regno != destregno)
12801 /* We need to save regno, before regno maps to the
12802 microMIPS register encoding. */
12812 regno = ILLEGAL_REG;
12816 regno = mips32_to_micromips_reg_b_map[regno];
12820 regno = mips32_to_micromips_reg_c_map[regno];
12824 regno = mips32_to_micromips_reg_d_map[regno];
12828 regno = mips32_to_micromips_reg_e_map[regno];
12832 regno = mips32_to_micromips_reg_f_map[regno];
12836 regno = mips32_to_micromips_reg_g_map[regno];
12840 regno = mips32_to_micromips_reg_h_map[regno];
12844 switch (EXTRACT_OPERAND (1, MI, *ip))
12849 else if (regno == 22)
12851 else if (regno == 5)
12853 else if (regno == 6)
12855 else if (regno == 7)
12858 regno = ILLEGAL_REG;
12864 else if (regno == 7)
12867 regno = ILLEGAL_REG;
12874 regno = ILLEGAL_REG;
12878 regno = ILLEGAL_REG;
12884 regno = mips32_to_micromips_reg_l_map[regno];
12888 regno = mips32_to_micromips_reg_m_map[regno];
12892 regno = mips32_to_micromips_reg_n_map[regno];
12896 regno = mips32_to_micromips_reg_q_map[regno];
12901 regno = ILLEGAL_REG;
12906 regno = ILLEGAL_REG;
12911 regno = ILLEGAL_REG;
12914 case 'j': /* Do nothing. */
12924 if (regno == ILLEGAL_REG)
12930 INSERT_OPERAND (1, MB, *ip, regno);
12934 INSERT_OPERAND (1, MC, *ip, regno);
12938 INSERT_OPERAND (1, MD, *ip, regno);
12942 INSERT_OPERAND (1, ME, *ip, regno);
12946 INSERT_OPERAND (1, MF, *ip, regno);
12950 INSERT_OPERAND (1, MG, *ip, regno);
12954 INSERT_OPERAND (1, MH, *ip, regno);
12958 INSERT_OPERAND (1, MI, *ip, regno);
12962 INSERT_OPERAND (1, MJ, *ip, regno);
12966 INSERT_OPERAND (1, ML, *ip, regno);
12970 INSERT_OPERAND (1, MM, *ip, regno);
12974 INSERT_OPERAND (1, MN, *ip, regno);
12978 INSERT_OPERAND (1, MP, *ip, regno);
12982 INSERT_OPERAND (1, MQ, *ip, regno);
12985 case 'a': /* Do nothing. */
12986 case 's': /* Do nothing. */
12987 case 't': /* Do nothing. */
12988 case 'x': /* Do nothing. */
12989 case 'y': /* Do nothing. */
12990 case 'z': /* Do nothing. */
13000 bfd_reloc_code_real_type r[3];
13004 /* Check whether there is only a single bracketed
13005 expression left. If so, it must be the base register
13006 and the constant must be zero. */
13007 if (*s == '(' && strchr (s + 1, '(') == 0)
13009 INSERT_OPERAND (1, IMMA, *ip, 0);
13013 if (my_getSmallExpression (&ep, r, s) > 0
13014 || !expr_const_in_range (&ep, -64, 64, 2))
13017 imm = ep.X_add_number >> 2;
13018 INSERT_OPERAND (1, IMMA, *ip, imm);
13025 bfd_reloc_code_real_type r[3];
13029 if (my_getSmallExpression (&ep, r, s) > 0
13030 || ep.X_op != O_constant)
13033 for (imm = 0; imm < 8; imm++)
13034 if (micromips_imm_b_map[imm] == ep.X_add_number)
13039 INSERT_OPERAND (1, IMMB, *ip, imm);
13046 bfd_reloc_code_real_type r[3];
13050 if (my_getSmallExpression (&ep, r, s) > 0
13051 || ep.X_op != O_constant)
13054 for (imm = 0; imm < 16; imm++)
13055 if (micromips_imm_c_map[imm] == ep.X_add_number)
13060 INSERT_OPERAND (1, IMMC, *ip, imm);
13065 case 'D': /* pc relative offset */
13066 case 'E': /* pc relative offset */
13067 my_getExpression (&offset_expr, s);
13068 if (offset_expr.X_op == O_register)
13071 if (!forced_insn_length)
13072 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13074 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13076 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13082 bfd_reloc_code_real_type r[3];
13086 if (my_getSmallExpression (&ep, r, s) > 0
13087 || !expr_const_in_range (&ep, 0, 16, 0))
13090 imm = ep.X_add_number;
13091 INSERT_OPERAND (1, IMMF, *ip, imm);
13098 bfd_reloc_code_real_type r[3];
13102 /* Check whether there is only a single bracketed
13103 expression left. If so, it must be the base register
13104 and the constant must be zero. */
13105 if (*s == '(' && strchr (s + 1, '(') == 0)
13107 INSERT_OPERAND (1, IMMG, *ip, 0);
13111 if (my_getSmallExpression (&ep, r, s) > 0
13112 || !expr_const_in_range (&ep, -1, 15, 0))
13115 imm = ep.X_add_number & 15;
13116 INSERT_OPERAND (1, IMMG, *ip, imm);
13123 bfd_reloc_code_real_type r[3];
13127 /* Check whether there is only a single bracketed
13128 expression left. If so, it must be the base register
13129 and the constant must be zero. */
13130 if (*s == '(' && strchr (s + 1, '(') == 0)
13132 INSERT_OPERAND (1, IMMH, *ip, 0);
13136 if (my_getSmallExpression (&ep, r, s) > 0
13137 || !expr_const_in_range (&ep, 0, 16, 1))
13140 imm = ep.X_add_number >> 1;
13141 INSERT_OPERAND (1, IMMH, *ip, imm);
13148 bfd_reloc_code_real_type r[3];
13152 if (my_getSmallExpression (&ep, r, s) > 0
13153 || !expr_const_in_range (&ep, -1, 127, 0))
13156 imm = ep.X_add_number & 127;
13157 INSERT_OPERAND (1, IMMI, *ip, imm);
13164 bfd_reloc_code_real_type r[3];
13168 /* Check whether there is only a single bracketed
13169 expression left. If so, it must be the base register
13170 and the constant must be zero. */
13171 if (*s == '(' && strchr (s + 1, '(') == 0)
13173 INSERT_OPERAND (1, IMMJ, *ip, 0);
13177 if (my_getSmallExpression (&ep, r, s) > 0
13178 || !expr_const_in_range (&ep, 0, 16, 2))
13181 imm = ep.X_add_number >> 2;
13182 INSERT_OPERAND (1, IMMJ, *ip, imm);
13189 bfd_reloc_code_real_type r[3];
13193 /* Check whether there is only a single bracketed
13194 expression left. If so, it must be the base register
13195 and the constant must be zero. */
13196 if (*s == '(' && strchr (s + 1, '(') == 0)
13198 INSERT_OPERAND (1, IMML, *ip, 0);
13202 if (my_getSmallExpression (&ep, r, s) > 0
13203 || !expr_const_in_range (&ep, 0, 16, 0))
13206 imm = ep.X_add_number;
13207 INSERT_OPERAND (1, IMML, *ip, imm);
13214 bfd_reloc_code_real_type r[3];
13218 if (my_getSmallExpression (&ep, r, s) > 0
13219 || !expr_const_in_range (&ep, 1, 9, 0))
13222 imm = ep.X_add_number & 7;
13223 INSERT_OPERAND (1, IMMM, *ip, imm);
13228 case 'N': /* Register list for lwm and swm. */
13230 /* A comma-separated list of registers and/or
13231 dash-separated contiguous ranges including
13232 both ra and a set of one or more registers
13233 starting at s0 up to s3 which have to be
13240 and any permutations of these. */
13241 unsigned int reglist;
13244 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13247 if ((reglist & 0xfff1ffff) != 0x80010000)
13250 reglist = (reglist >> 17) & 7;
13252 if ((reglist & -reglist) != reglist)
13255 imm = ffs (reglist) - 1;
13256 INSERT_OPERAND (1, IMMN, *ip, imm);
13260 case 'O': /* sdbbp 4-bit code. */
13262 bfd_reloc_code_real_type r[3];
13266 if (my_getSmallExpression (&ep, r, s) > 0
13267 || !expr_const_in_range (&ep, 0, 16, 0))
13270 imm = ep.X_add_number;
13271 INSERT_OPERAND (1, IMMO, *ip, imm);
13278 bfd_reloc_code_real_type r[3];
13282 if (my_getSmallExpression (&ep, r, s) > 0
13283 || !expr_const_in_range (&ep, 0, 32, 2))
13286 imm = ep.X_add_number >> 2;
13287 INSERT_OPERAND (1, IMMP, *ip, imm);
13294 bfd_reloc_code_real_type r[3];
13298 if (my_getSmallExpression (&ep, r, s) > 0
13299 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13302 imm = ep.X_add_number >> 2;
13303 INSERT_OPERAND (1, IMMQ, *ip, imm);
13310 bfd_reloc_code_real_type r[3];
13314 /* Check whether there is only a single bracketed
13315 expression left. If so, it must be the base register
13316 and the constant must be zero. */
13317 if (*s == '(' && strchr (s + 1, '(') == 0)
13319 INSERT_OPERAND (1, IMMU, *ip, 0);
13323 if (my_getSmallExpression (&ep, r, s) > 0
13324 || !expr_const_in_range (&ep, 0, 32, 2))
13327 imm = ep.X_add_number >> 2;
13328 INSERT_OPERAND (1, IMMU, *ip, imm);
13335 bfd_reloc_code_real_type r[3];
13339 if (my_getSmallExpression (&ep, r, s) > 0
13340 || !expr_const_in_range (&ep, 0, 64, 2))
13343 imm = ep.X_add_number >> 2;
13344 INSERT_OPERAND (1, IMMW, *ip, imm);
13351 bfd_reloc_code_real_type r[3];
13355 if (my_getSmallExpression (&ep, r, s) > 0
13356 || !expr_const_in_range (&ep, -8, 8, 0))
13359 imm = ep.X_add_number;
13360 INSERT_OPERAND (1, IMMX, *ip, imm);
13367 bfd_reloc_code_real_type r[3];
13371 if (my_getSmallExpression (&ep, r, s) > 0
13372 || expr_const_in_range (&ep, -2, 2, 2)
13373 || !expr_const_in_range (&ep, -258, 258, 2))
13376 imm = ep.X_add_number >> 2;
13377 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13378 INSERT_OPERAND (1, IMMY, *ip, imm);
13385 bfd_reloc_code_real_type r[3];
13388 if (my_getSmallExpression (&ep, r, s) > 0
13389 || !expr_const_in_range (&ep, 0, 1, 0))
13396 as_bad (_("Internal error: bad microMIPS opcode "
13397 "(unknown extension operand type `m%c'): %s %s"),
13398 *args, insn->name, insn->args);
13399 /* Further processing is fruitless. */
13404 case 'n': /* Register list for 32-bit lwm and swm. */
13405 gas_assert (mips_opts.micromips);
13407 /* A comma-separated list of registers and/or
13408 dash-separated contiguous ranges including
13409 at least one of ra and a set of one or more
13410 registers starting at s0 up to s7 and then
13411 s8 which have to be consecutive, e.g.:
13419 and any permutations of these. */
13420 unsigned int reglist;
13424 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13427 if ((reglist & 0x3f00ffff) != 0)
13430 ra = (reglist >> 27) & 0x10;
13431 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13433 if ((reglist & -reglist) != reglist)
13436 imm = (ffs (reglist) - 1) | ra;
13437 INSERT_OPERAND (1, RT, *ip, imm);
13438 imm_expr.X_op = O_absent;
13442 case '|': /* 4-bit trap code. */
13443 gas_assert (mips_opts.micromips);
13444 my_getExpression (&imm_expr, s);
13445 check_absolute_expr (ip, &imm_expr);
13446 if ((unsigned long) imm_expr.X_add_number
13447 > MICROMIPSOP_MASK_TRAP)
13448 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13449 (unsigned long) imm_expr.X_add_number,
13450 ip->insn_mo->name);
13451 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13452 imm_expr.X_op = O_absent;
13457 as_bad (_("Bad char = '%c'\n"), *args);
13462 /* Args don't match. */
13464 insn_error = _("Illegal operands");
13465 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13470 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13472 gas_assert (firstinsn);
13473 need_delay_slot_ok = FALSE;
13482 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13484 /* This routine assembles an instruction into its binary format when
13485 assembling for the mips16. As a side effect, it sets one of the
13486 global variables imm_reloc or offset_reloc to the type of relocation
13487 to do if one of the operands is an address expression. It also sets
13488 forced_insn_length to the resulting instruction size in bytes if the
13489 user explicitly requested a small or extended instruction. */
13492 mips16_ip (char *str, struct mips_cl_insn *ip)
13496 struct mips_opcode *insn;
13498 unsigned int regno;
13499 unsigned int lastregno = 0;
13505 forced_insn_length = 0;
13507 for (s = str; ISLOWER (*s); ++s)
13519 if (s[1] == 't' && s[2] == ' ')
13522 forced_insn_length = 2;
13526 else if (s[1] == 'e' && s[2] == ' ')
13529 forced_insn_length = 4;
13533 /* Fall through. */
13535 insn_error = _("unknown opcode");
13539 if (mips_opts.noautoextend && !forced_insn_length)
13540 forced_insn_length = 2;
13542 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13544 insn_error = _("unrecognized opcode");
13553 gas_assert (strcmp (insn->name, str) == 0);
13555 ok = is_opcode_valid_16 (insn);
13558 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13559 && strcmp (insn->name, insn[1].name) == 0)
13568 static char buf[100];
13570 _("Opcode not supported on this processor: %s (%s)"),
13571 mips_cpu_info_from_arch (mips_opts.arch)->name,
13572 mips_cpu_info_from_isa (mips_opts.isa)->name);
13579 create_insn (ip, insn);
13580 imm_expr.X_op = O_absent;
13581 imm_reloc[0] = BFD_RELOC_UNUSED;
13582 imm_reloc[1] = BFD_RELOC_UNUSED;
13583 imm_reloc[2] = BFD_RELOC_UNUSED;
13584 imm2_expr.X_op = O_absent;
13585 offset_expr.X_op = O_absent;
13586 offset_reloc[0] = BFD_RELOC_UNUSED;
13587 offset_reloc[1] = BFD_RELOC_UNUSED;
13588 offset_reloc[2] = BFD_RELOC_UNUSED;
13589 for (args = insn->args; 1; ++args)
13596 /* In this switch statement we call break if we did not find
13597 a match, continue if we did find a match, or return if we
13608 /* Stuff the immediate value in now, if we can. */
13609 if (imm_expr.X_op == O_constant
13610 && *imm_reloc > BFD_RELOC_UNUSED
13611 && insn->pinfo != INSN_MACRO
13612 && calculate_reloc (*offset_reloc,
13613 imm_expr.X_add_number, &value))
13615 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13616 *offset_reloc, value, forced_insn_length,
13618 imm_expr.X_op = O_absent;
13619 *imm_reloc = BFD_RELOC_UNUSED;
13620 *offset_reloc = BFD_RELOC_UNUSED;
13634 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13637 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13653 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13655 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13659 /* Fall through. */
13670 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13672 if (c == 'v' || c == 'w')
13675 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13677 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13688 if (c == 'v' || c == 'w')
13690 regno = mips16_to_32_reg_map[lastregno];
13704 regno = mips32_to_16_reg_map[regno];
13709 regno = ILLEGAL_REG;
13714 regno = ILLEGAL_REG;
13719 regno = ILLEGAL_REG;
13724 if (regno == AT && mips_opts.at)
13726 if (mips_opts.at == ATREG)
13727 as_warn (_("used $at without \".set noat\""));
13729 as_warn (_("used $%u with \".set at=$%u\""),
13730 regno, mips_opts.at);
13738 if (regno == ILLEGAL_REG)
13745 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13749 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13752 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13755 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13761 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13764 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13765 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13775 if (strncmp (s, "$pc", 3) == 0)
13792 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13795 if (imm_expr.X_op != O_constant)
13797 forced_insn_length = 4;
13798 ip->insn_opcode |= MIPS16_EXTEND;
13802 /* We need to relax this instruction. */
13803 *offset_reloc = *imm_reloc;
13804 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13809 *imm_reloc = BFD_RELOC_UNUSED;
13810 /* Fall through. */
13817 my_getExpression (&imm_expr, s);
13818 if (imm_expr.X_op == O_register)
13820 /* What we thought was an expression turned out to
13823 if (s[0] == '(' && args[1] == '(')
13825 /* It looks like the expression was omitted
13826 before a register indirection, which means
13827 that the expression is implicitly zero. We
13828 still set up imm_expr, so that we handle
13829 explicit extensions correctly. */
13830 imm_expr.X_op = O_constant;
13831 imm_expr.X_add_number = 0;
13832 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13839 /* We need to relax this instruction. */
13840 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13849 /* We use offset_reloc rather than imm_reloc for the PC
13850 relative operands. This lets macros with both
13851 immediate and address operands work correctly. */
13852 my_getExpression (&offset_expr, s);
13854 if (offset_expr.X_op == O_register)
13857 /* We need to relax this instruction. */
13858 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13862 case '6': /* break code */
13863 my_getExpression (&imm_expr, s);
13864 check_absolute_expr (ip, &imm_expr);
13865 if ((unsigned long) imm_expr.X_add_number > 63)
13866 as_warn (_("Invalid value for `%s' (%lu)"),
13868 (unsigned long) imm_expr.X_add_number);
13869 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13870 imm_expr.X_op = O_absent;
13874 case 'a': /* 26 bit address */
13875 my_getExpression (&offset_expr, s);
13877 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13878 ip->insn_opcode <<= 16;
13881 case 'l': /* register list for entry macro */
13882 case 'L': /* register list for exit macro */
13892 unsigned int freg, reg1, reg2;
13894 while (*s == ' ' || *s == ',')
13896 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13898 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13902 as_bad (_("can't parse register list"));
13912 if (!reg_lookup (&s, freg ? RTYPE_FPU
13913 : (RTYPE_GP | RTYPE_NUM), ®2))
13915 as_bad (_("invalid register list"));
13919 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13921 mask &= ~ (7 << 3);
13924 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13926 mask &= ~ (7 << 3);
13929 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13930 mask |= (reg2 - 3) << 3;
13931 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13932 mask |= (reg2 - 15) << 1;
13933 else if (reg1 == RA && reg2 == RA)
13937 as_bad (_("invalid register list"));
13941 /* The mask is filled in in the opcode table for the
13942 benefit of the disassembler. We remove it before
13943 applying the actual mask. */
13944 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13945 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13949 case 'm': /* Register list for save insn. */
13950 case 'M': /* Register list for restore insn. */
13952 int opcode = ip->insn_opcode;
13953 int framesz = 0, seen_framesz = 0;
13954 int nargs = 0, statics = 0, sregs = 0;
13958 unsigned int reg1, reg2;
13960 SKIP_SPACE_TABS (s);
13963 SKIP_SPACE_TABS (s);
13965 my_getExpression (&imm_expr, s);
13966 if (imm_expr.X_op == O_constant)
13968 /* Handle the frame size. */
13971 as_bad (_("more than one frame size in list"));
13975 framesz = imm_expr.X_add_number;
13976 imm_expr.X_op = O_absent;
13981 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13983 as_bad (_("can't parse register list"));
13995 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13998 as_bad (_("can't parse register list"));
14003 while (reg1 <= reg2)
14005 if (reg1 >= 4 && reg1 <= 7)
14009 nargs |= 1 << (reg1 - 4);
14011 /* statics $a0-$a3 */
14012 statics |= 1 << (reg1 - 4);
14014 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14017 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14019 else if (reg1 == 31)
14021 /* Add $ra to insn. */
14026 as_bad (_("unexpected register in list"));
14034 /* Encode args/statics combination. */
14035 if (nargs & statics)
14036 as_bad (_("arg/static registers overlap"));
14037 else if (nargs == 0xf)
14038 /* All $a0-$a3 are args. */
14039 opcode |= MIPS16_ALL_ARGS << 16;
14040 else if (statics == 0xf)
14041 /* All $a0-$a3 are statics. */
14042 opcode |= MIPS16_ALL_STATICS << 16;
14045 int narg = 0, nstat = 0;
14047 /* Count arg registers. */
14048 while (nargs & 0x1)
14054 as_bad (_("invalid arg register list"));
14056 /* Count static registers. */
14057 while (statics & 0x8)
14059 statics = (statics << 1) & 0xf;
14063 as_bad (_("invalid static register list"));
14065 /* Encode args/statics. */
14066 opcode |= ((narg << 2) | nstat) << 16;
14069 /* Encode $s0/$s1. */
14070 if (sregs & (1 << 0)) /* $s0 */
14072 if (sregs & (1 << 1)) /* $s1 */
14078 /* Count regs $s2-$s8. */
14086 as_bad (_("invalid static register list"));
14087 /* Encode $s2-$s8. */
14088 opcode |= nsreg << 24;
14091 /* Encode frame size. */
14093 as_bad (_("missing frame size"));
14094 else if ((framesz & 7) != 0 || framesz < 0
14095 || framesz > 0xff * 8)
14096 as_bad (_("invalid frame size"));
14097 else if (framesz != 128 || (opcode >> 16) != 0)
14100 opcode |= (((framesz & 0xf0) << 16)
14101 | (framesz & 0x0f));
14104 /* Finally build the instruction. */
14105 if ((opcode >> 16) != 0 || framesz == 0)
14106 opcode |= MIPS16_EXTEND;
14107 ip->insn_opcode = opcode;
14111 case 'e': /* extend code */
14112 my_getExpression (&imm_expr, s);
14113 check_absolute_expr (ip, &imm_expr);
14114 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14116 as_warn (_("Invalid value for `%s' (%lu)"),
14118 (unsigned long) imm_expr.X_add_number);
14119 imm_expr.X_add_number &= 0x7ff;
14121 ip->insn_opcode |= imm_expr.X_add_number;
14122 imm_expr.X_op = O_absent;
14132 /* Args don't match. */
14133 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14134 strcmp (insn->name, insn[1].name) == 0)
14141 insn_error = _("illegal operands");
14147 /* This structure holds information we know about a mips16 immediate
14150 struct mips16_immed_operand
14152 /* The type code used in the argument string in the opcode table. */
14154 /* The number of bits in the short form of the opcode. */
14156 /* The number of bits in the extended form of the opcode. */
14158 /* The amount by which the short form is shifted when it is used;
14159 for example, the sw instruction has a shift count of 2. */
14161 /* The amount by which the short form is shifted when it is stored
14162 into the instruction code. */
14164 /* Non-zero if the short form is unsigned. */
14166 /* Non-zero if the extended form is unsigned. */
14168 /* Non-zero if the value is PC relative. */
14172 /* The mips16 immediate operand types. */
14174 static const struct mips16_immed_operand mips16_immed_operands[] =
14176 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14177 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14178 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14179 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14180 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14181 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14182 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14183 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14184 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14185 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14186 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14187 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14188 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14189 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14190 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14191 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14192 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14193 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14194 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14195 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14196 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14199 #define MIPS16_NUM_IMMED \
14200 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14202 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14203 NBITS is the number of significant bits in VAL. */
14205 static unsigned long
14206 mips16_immed_extend (offsetT val, unsigned int nbits)
14211 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14214 else if (nbits == 15)
14216 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14221 extval = ((val & 0x1f) << 6) | (val & 0x20);
14224 return (extval << 16) | val;
14227 /* Install immediate value VAL into MIPS16 instruction *INSN,
14228 extending it if necessary. The instruction in *INSN may
14229 already be extended.
14231 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14232 if none. In the former case, VAL is a 16-bit number with no
14233 defined signedness.
14235 TYPE is the type of the immediate field. USER_INSN_LENGTH
14236 is the length that the user requested, or 0 if none. */
14239 mips16_immed (char *file, unsigned int line, int type,
14240 bfd_reloc_code_real_type reloc, offsetT val,
14241 unsigned int user_insn_length, unsigned long *insn)
14243 const struct mips16_immed_operand *op;
14244 int mintiny, maxtiny;
14246 op = mips16_immed_operands;
14247 while (op->type != type)
14250 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14255 if (type == '<' || type == '>' || type == '[' || type == ']')
14258 maxtiny = 1 << op->nbits;
14263 maxtiny = (1 << op->nbits) - 1;
14265 if (reloc != BFD_RELOC_UNUSED)
14270 mintiny = - (1 << (op->nbits - 1));
14271 maxtiny = (1 << (op->nbits - 1)) - 1;
14272 if (reloc != BFD_RELOC_UNUSED)
14273 val = SEXT_16BIT (val);
14276 /* Branch offsets have an implicit 0 in the lowest bit. */
14277 if (type == 'p' || type == 'q')
14280 if ((val & ((1 << op->shift) - 1)) != 0
14281 || val < (mintiny << op->shift)
14282 || val > (maxtiny << op->shift))
14284 /* We need an extended instruction. */
14285 if (user_insn_length == 2)
14286 as_bad_where (file, line, _("invalid unextended operand value"));
14288 *insn |= MIPS16_EXTEND;
14290 else if (user_insn_length == 4)
14292 /* The operand doesn't force an unextended instruction to be extended.
14293 Warn if the user wanted an extended instruction anyway. */
14294 *insn |= MIPS16_EXTEND;
14295 as_warn_where (file, line,
14296 _("extended operand requested but not required"));
14299 if (mips16_opcode_length (*insn) == 2)
14303 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14304 insnval <<= op->op_shift;
14309 long minext, maxext;
14311 if (reloc == BFD_RELOC_UNUSED)
14316 maxext = (1 << op->extbits) - 1;
14320 minext = - (1 << (op->extbits - 1));
14321 maxext = (1 << (op->extbits - 1)) - 1;
14323 if (val < minext || val > maxext)
14324 as_bad_where (file, line,
14325 _("operand value out of range for instruction"));
14328 *insn |= mips16_immed_extend (val, op->extbits);
14332 struct percent_op_match
14335 bfd_reloc_code_real_type reloc;
14338 static const struct percent_op_match mips_percent_op[] =
14340 {"%lo", BFD_RELOC_LO16},
14342 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14343 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14344 {"%call16", BFD_RELOC_MIPS_CALL16},
14345 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14346 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14347 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14348 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14349 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14350 {"%got", BFD_RELOC_MIPS_GOT16},
14351 {"%gp_rel", BFD_RELOC_GPREL16},
14352 {"%half", BFD_RELOC_16},
14353 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14354 {"%higher", BFD_RELOC_MIPS_HIGHER},
14355 {"%neg", BFD_RELOC_MIPS_SUB},
14356 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14357 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14358 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14359 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14360 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14361 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14362 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14364 {"%hi", BFD_RELOC_HI16_S}
14367 static const struct percent_op_match mips16_percent_op[] =
14369 {"%lo", BFD_RELOC_MIPS16_LO16},
14370 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14371 {"%got", BFD_RELOC_MIPS16_GOT16},
14372 {"%call16", BFD_RELOC_MIPS16_CALL16},
14373 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14374 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14375 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14376 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14377 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14378 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14379 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14380 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14384 /* Return true if *STR points to a relocation operator. When returning true,
14385 move *STR over the operator and store its relocation code in *RELOC.
14386 Leave both *STR and *RELOC alone when returning false. */
14389 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14391 const struct percent_op_match *percent_op;
14394 if (mips_opts.mips16)
14396 percent_op = mips16_percent_op;
14397 limit = ARRAY_SIZE (mips16_percent_op);
14401 percent_op = mips_percent_op;
14402 limit = ARRAY_SIZE (mips_percent_op);
14405 for (i = 0; i < limit; i++)
14406 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14408 int len = strlen (percent_op[i].str);
14410 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14413 *str += strlen (percent_op[i].str);
14414 *reloc = percent_op[i].reloc;
14416 /* Check whether the output BFD supports this relocation.
14417 If not, issue an error and fall back on something safe. */
14418 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14420 as_bad (_("relocation %s isn't supported by the current ABI"),
14421 percent_op[i].str);
14422 *reloc = BFD_RELOC_UNUSED;
14430 /* Parse string STR as a 16-bit relocatable operand. Store the
14431 expression in *EP and the relocations in the array starting
14432 at RELOC. Return the number of relocation operators used.
14434 On exit, EXPR_END points to the first character after the expression. */
14437 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14440 bfd_reloc_code_real_type reversed_reloc[3];
14441 size_t reloc_index, i;
14442 int crux_depth, str_depth;
14445 /* Search for the start of the main expression, recoding relocations
14446 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14447 of the main expression and with CRUX_DEPTH containing the number
14448 of open brackets at that point. */
14455 crux_depth = str_depth;
14457 /* Skip over whitespace and brackets, keeping count of the number
14459 while (*str == ' ' || *str == '\t' || *str == '(')
14464 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14465 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14467 my_getExpression (ep, crux);
14470 /* Match every open bracket. */
14471 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14475 if (crux_depth > 0)
14476 as_bad (_("unclosed '('"));
14480 if (reloc_index != 0)
14482 prev_reloc_op_frag = frag_now;
14483 for (i = 0; i < reloc_index; i++)
14484 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14487 return reloc_index;
14491 my_getExpression (expressionS *ep, char *str)
14495 save_in = input_line_pointer;
14496 input_line_pointer = str;
14498 expr_end = input_line_pointer;
14499 input_line_pointer = save_in;
14503 md_atof (int type, char *litP, int *sizeP)
14505 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14509 md_number_to_chars (char *buf, valueT val, int n)
14511 if (target_big_endian)
14512 number_to_chars_bigendian (buf, val, n);
14514 number_to_chars_littleendian (buf, val, n);
14518 static int support_64bit_objects(void)
14520 const char **list, **l;
14523 list = bfd_target_list ();
14524 for (l = list; *l != NULL; l++)
14525 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14526 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14528 yes = (*l != NULL);
14532 #endif /* OBJ_ELF */
14534 const char *md_shortopts = "O::g::G:";
14538 OPTION_MARCH = OPTION_MD_BASE,
14562 OPTION_NO_SMARTMIPS,
14566 OPTION_NO_MICROMIPS,
14569 OPTION_COMPAT_ARCH_BASE,
14578 OPTION_M7000_HILO_FIX,
14579 OPTION_MNO_7000_HILO_FIX,
14582 OPTION_FIX_LOONGSON2F_JUMP,
14583 OPTION_NO_FIX_LOONGSON2F_JUMP,
14584 OPTION_FIX_LOONGSON2F_NOP,
14585 OPTION_NO_FIX_LOONGSON2F_NOP,
14587 OPTION_NO_FIX_VR4120,
14589 OPTION_NO_FIX_VR4130,
14590 OPTION_FIX_CN63XXP1,
14591 OPTION_NO_FIX_CN63XXP1,
14598 OPTION_CONSTRUCT_FLOATS,
14599 OPTION_NO_CONSTRUCT_FLOATS,
14602 OPTION_RELAX_BRANCH,
14603 OPTION_NO_RELAX_BRANCH,
14610 OPTION_SINGLE_FLOAT,
14611 OPTION_DOUBLE_FLOAT,
14614 OPTION_CALL_SHARED,
14615 OPTION_CALL_NONPIC,
14625 OPTION_MVXWORKS_PIC,
14626 #endif /* OBJ_ELF */
14630 struct option md_longopts[] =
14632 /* Options which specify architecture. */
14633 {"march", required_argument, NULL, OPTION_MARCH},
14634 {"mtune", required_argument, NULL, OPTION_MTUNE},
14635 {"mips0", no_argument, NULL, OPTION_MIPS1},
14636 {"mips1", no_argument, NULL, OPTION_MIPS1},
14637 {"mips2", no_argument, NULL, OPTION_MIPS2},
14638 {"mips3", no_argument, NULL, OPTION_MIPS3},
14639 {"mips4", no_argument, NULL, OPTION_MIPS4},
14640 {"mips5", no_argument, NULL, OPTION_MIPS5},
14641 {"mips32", no_argument, NULL, OPTION_MIPS32},
14642 {"mips64", no_argument, NULL, OPTION_MIPS64},
14643 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14644 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14646 /* Options which specify Application Specific Extensions (ASEs). */
14647 {"mips16", no_argument, NULL, OPTION_MIPS16},
14648 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14649 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14650 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14651 {"mdmx", no_argument, NULL, OPTION_MDMX},
14652 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14653 {"mdsp", no_argument, NULL, OPTION_DSP},
14654 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14655 {"mmt", no_argument, NULL, OPTION_MT},
14656 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14657 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14658 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14659 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14660 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14661 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14662 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14663 {"mmcu", no_argument, NULL, OPTION_MCU},
14664 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14665 {"mvirt", no_argument, NULL, OPTION_VIRT},
14666 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
14668 /* Old-style architecture options. Don't add more of these. */
14669 {"m4650", no_argument, NULL, OPTION_M4650},
14670 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14671 {"m4010", no_argument, NULL, OPTION_M4010},
14672 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14673 {"m4100", no_argument, NULL, OPTION_M4100},
14674 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14675 {"m3900", no_argument, NULL, OPTION_M3900},
14676 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14678 /* Options which enable bug fixes. */
14679 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14680 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14681 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14682 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14683 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14684 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14685 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14686 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14687 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14688 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14689 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14690 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14691 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14692 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14693 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14695 /* Miscellaneous options. */
14696 {"trap", no_argument, NULL, OPTION_TRAP},
14697 {"no-break", no_argument, NULL, OPTION_TRAP},
14698 {"break", no_argument, NULL, OPTION_BREAK},
14699 {"no-trap", no_argument, NULL, OPTION_BREAK},
14700 {"EB", no_argument, NULL, OPTION_EB},
14701 {"EL", no_argument, NULL, OPTION_EL},
14702 {"mfp32", no_argument, NULL, OPTION_FP32},
14703 {"mgp32", no_argument, NULL, OPTION_GP32},
14704 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14705 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14706 {"mfp64", no_argument, NULL, OPTION_FP64},
14707 {"mgp64", no_argument, NULL, OPTION_GP64},
14708 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14709 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14710 {"mshared", no_argument, NULL, OPTION_MSHARED},
14711 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14712 {"msym32", no_argument, NULL, OPTION_MSYM32},
14713 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14714 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14715 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14716 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14717 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14719 /* Strictly speaking this next option is ELF specific,
14720 but we allow it for other ports as well in order to
14721 make testing easier. */
14722 {"32", no_argument, NULL, OPTION_32},
14724 /* ELF-specific options. */
14726 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14727 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14728 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14729 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14730 {"xgot", no_argument, NULL, OPTION_XGOT},
14731 {"mabi", required_argument, NULL, OPTION_MABI},
14732 {"n32", no_argument, NULL, OPTION_N32},
14733 {"64", no_argument, NULL, OPTION_64},
14734 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14735 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14736 {"mpdr", no_argument, NULL, OPTION_PDR},
14737 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14738 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14739 #endif /* OBJ_ELF */
14741 {NULL, no_argument, NULL, 0}
14743 size_t md_longopts_size = sizeof (md_longopts);
14745 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14746 NEW_VALUE. Warn if another value was already specified. Note:
14747 we have to defer parsing the -march and -mtune arguments in order
14748 to handle 'from-abi' correctly, since the ABI might be specified
14749 in a later argument. */
14752 mips_set_option_string (const char **string_ptr, const char *new_value)
14754 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14755 as_warn (_("A different %s was already specified, is now %s"),
14756 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14759 *string_ptr = new_value;
14763 md_parse_option (int c, char *arg)
14767 case OPTION_CONSTRUCT_FLOATS:
14768 mips_disable_float_construction = 0;
14771 case OPTION_NO_CONSTRUCT_FLOATS:
14772 mips_disable_float_construction = 1;
14784 target_big_endian = 1;
14788 target_big_endian = 0;
14794 else if (arg[0] == '0')
14796 else if (arg[0] == '1')
14806 mips_debug = atoi (arg);
14810 file_mips_isa = ISA_MIPS1;
14814 file_mips_isa = ISA_MIPS2;
14818 file_mips_isa = ISA_MIPS3;
14822 file_mips_isa = ISA_MIPS4;
14826 file_mips_isa = ISA_MIPS5;
14829 case OPTION_MIPS32:
14830 file_mips_isa = ISA_MIPS32;
14833 case OPTION_MIPS32R2:
14834 file_mips_isa = ISA_MIPS32R2;
14837 case OPTION_MIPS64R2:
14838 file_mips_isa = ISA_MIPS64R2;
14841 case OPTION_MIPS64:
14842 file_mips_isa = ISA_MIPS64;
14846 mips_set_option_string (&mips_tune_string, arg);
14850 mips_set_option_string (&mips_arch_string, arg);
14854 mips_set_option_string (&mips_arch_string, "4650");
14855 mips_set_option_string (&mips_tune_string, "4650");
14858 case OPTION_NO_M4650:
14862 mips_set_option_string (&mips_arch_string, "4010");
14863 mips_set_option_string (&mips_tune_string, "4010");
14866 case OPTION_NO_M4010:
14870 mips_set_option_string (&mips_arch_string, "4100");
14871 mips_set_option_string (&mips_tune_string, "4100");
14874 case OPTION_NO_M4100:
14878 mips_set_option_string (&mips_arch_string, "3900");
14879 mips_set_option_string (&mips_tune_string, "3900");
14882 case OPTION_NO_M3900:
14886 mips_opts.ase_mdmx = 1;
14889 case OPTION_NO_MDMX:
14890 mips_opts.ase_mdmx = 0;
14894 mips_opts.ase_dsp = 1;
14895 mips_opts.ase_dspr2 = 0;
14898 case OPTION_NO_DSP:
14899 mips_opts.ase_dsp = 0;
14900 mips_opts.ase_dspr2 = 0;
14904 mips_opts.ase_dspr2 = 1;
14905 mips_opts.ase_dsp = 1;
14908 case OPTION_NO_DSPR2:
14909 mips_opts.ase_dspr2 = 0;
14910 mips_opts.ase_dsp = 0;
14914 mips_opts.ase_mt = 1;
14918 mips_opts.ase_mt = 0;
14922 mips_opts.ase_mcu = 1;
14925 case OPTION_NO_MCU:
14926 mips_opts.ase_mcu = 0;
14929 case OPTION_MICROMIPS:
14930 if (mips_opts.mips16 == 1)
14932 as_bad (_("-mmicromips cannot be used with -mips16"));
14935 mips_opts.micromips = 1;
14936 mips_no_prev_insn ();
14939 case OPTION_NO_MICROMIPS:
14940 mips_opts.micromips = 0;
14941 mips_no_prev_insn ();
14945 mips_opts.ase_virt = 1;
14948 case OPTION_NO_VIRT:
14949 mips_opts.ase_virt = 0;
14952 case OPTION_MIPS16:
14953 if (mips_opts.micromips == 1)
14955 as_bad (_("-mips16 cannot be used with -micromips"));
14958 mips_opts.mips16 = 1;
14959 mips_no_prev_insn ();
14962 case OPTION_NO_MIPS16:
14963 mips_opts.mips16 = 0;
14964 mips_no_prev_insn ();
14967 case OPTION_MIPS3D:
14968 mips_opts.ase_mips3d = 1;
14971 case OPTION_NO_MIPS3D:
14972 mips_opts.ase_mips3d = 0;
14975 case OPTION_SMARTMIPS:
14976 mips_opts.ase_smartmips = 1;
14979 case OPTION_NO_SMARTMIPS:
14980 mips_opts.ase_smartmips = 0;
14983 case OPTION_FIX_24K:
14987 case OPTION_NO_FIX_24K:
14991 case OPTION_FIX_LOONGSON2F_JUMP:
14992 mips_fix_loongson2f_jump = TRUE;
14995 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14996 mips_fix_loongson2f_jump = FALSE;
14999 case OPTION_FIX_LOONGSON2F_NOP:
15000 mips_fix_loongson2f_nop = TRUE;
15003 case OPTION_NO_FIX_LOONGSON2F_NOP:
15004 mips_fix_loongson2f_nop = FALSE;
15007 case OPTION_FIX_VR4120:
15008 mips_fix_vr4120 = 1;
15011 case OPTION_NO_FIX_VR4120:
15012 mips_fix_vr4120 = 0;
15015 case OPTION_FIX_VR4130:
15016 mips_fix_vr4130 = 1;
15019 case OPTION_NO_FIX_VR4130:
15020 mips_fix_vr4130 = 0;
15023 case OPTION_FIX_CN63XXP1:
15024 mips_fix_cn63xxp1 = TRUE;
15027 case OPTION_NO_FIX_CN63XXP1:
15028 mips_fix_cn63xxp1 = FALSE;
15031 case OPTION_RELAX_BRANCH:
15032 mips_relax_branch = 1;
15035 case OPTION_NO_RELAX_BRANCH:
15036 mips_relax_branch = 0;
15039 case OPTION_MSHARED:
15040 mips_in_shared = TRUE;
15043 case OPTION_MNO_SHARED:
15044 mips_in_shared = FALSE;
15047 case OPTION_MSYM32:
15048 mips_opts.sym32 = TRUE;
15051 case OPTION_MNO_SYM32:
15052 mips_opts.sym32 = FALSE;
15056 /* When generating ELF code, we permit -KPIC and -call_shared to
15057 select SVR4_PIC, and -non_shared to select no PIC. This is
15058 intended to be compatible with Irix 5. */
15059 case OPTION_CALL_SHARED:
15062 as_bad (_("-call_shared is supported only for ELF format"));
15065 mips_pic = SVR4_PIC;
15066 mips_abicalls = TRUE;
15069 case OPTION_CALL_NONPIC:
15072 as_bad (_("-call_nonpic is supported only for ELF format"));
15076 mips_abicalls = TRUE;
15079 case OPTION_NON_SHARED:
15082 as_bad (_("-non_shared is supported only for ELF format"));
15086 mips_abicalls = FALSE;
15089 /* The -xgot option tells the assembler to use 32 bit offsets
15090 when accessing the got in SVR4_PIC mode. It is for Irix
15095 #endif /* OBJ_ELF */
15098 g_switch_value = atoi (arg);
15102 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15106 mips_abi = O32_ABI;
15107 /* We silently ignore -32 for non-ELF targets. This greatly
15108 simplifies the construction of the MIPS GAS test cases. */
15115 as_bad (_("-n32 is supported for ELF format only"));
15118 mips_abi = N32_ABI;
15124 as_bad (_("-64 is supported for ELF format only"));
15127 mips_abi = N64_ABI;
15128 if (!support_64bit_objects())
15129 as_fatal (_("No compiled in support for 64 bit object file format"));
15131 #endif /* OBJ_ELF */
15134 file_mips_gp32 = 1;
15138 file_mips_gp32 = 0;
15142 file_mips_fp32 = 1;
15146 file_mips_fp32 = 0;
15149 case OPTION_SINGLE_FLOAT:
15150 file_mips_single_float = 1;
15153 case OPTION_DOUBLE_FLOAT:
15154 file_mips_single_float = 0;
15157 case OPTION_SOFT_FLOAT:
15158 file_mips_soft_float = 1;
15161 case OPTION_HARD_FLOAT:
15162 file_mips_soft_float = 0;
15169 as_bad (_("-mabi is supported for ELF format only"));
15172 if (strcmp (arg, "32") == 0)
15173 mips_abi = O32_ABI;
15174 else if (strcmp (arg, "o64") == 0)
15175 mips_abi = O64_ABI;
15176 else if (strcmp (arg, "n32") == 0)
15177 mips_abi = N32_ABI;
15178 else if (strcmp (arg, "64") == 0)
15180 mips_abi = N64_ABI;
15181 if (! support_64bit_objects())
15182 as_fatal (_("No compiled in support for 64 bit object file "
15185 else if (strcmp (arg, "eabi") == 0)
15186 mips_abi = EABI_ABI;
15189 as_fatal (_("invalid abi -mabi=%s"), arg);
15193 #endif /* OBJ_ELF */
15195 case OPTION_M7000_HILO_FIX:
15196 mips_7000_hilo_fix = TRUE;
15199 case OPTION_MNO_7000_HILO_FIX:
15200 mips_7000_hilo_fix = FALSE;
15204 case OPTION_MDEBUG:
15205 mips_flag_mdebug = TRUE;
15208 case OPTION_NO_MDEBUG:
15209 mips_flag_mdebug = FALSE;
15213 mips_flag_pdr = TRUE;
15216 case OPTION_NO_PDR:
15217 mips_flag_pdr = FALSE;
15220 case OPTION_MVXWORKS_PIC:
15221 mips_pic = VXWORKS_PIC;
15223 #endif /* OBJ_ELF */
15229 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15234 /* Set up globals to generate code for the ISA or processor
15235 described by INFO. */
15238 mips_set_architecture (const struct mips_cpu_info *info)
15242 file_mips_arch = info->cpu;
15243 mips_opts.arch = info->cpu;
15244 mips_opts.isa = info->isa;
15249 /* Likewise for tuning. */
15252 mips_set_tune (const struct mips_cpu_info *info)
15255 mips_tune = info->cpu;
15260 mips_after_parse_args (void)
15262 const struct mips_cpu_info *arch_info = 0;
15263 const struct mips_cpu_info *tune_info = 0;
15265 /* GP relative stuff not working for PE */
15266 if (strncmp (TARGET_OS, "pe", 2) == 0)
15268 if (g_switch_seen && g_switch_value != 0)
15269 as_bad (_("-G not supported in this configuration."));
15270 g_switch_value = 0;
15273 if (mips_abi == NO_ABI)
15274 mips_abi = MIPS_DEFAULT_ABI;
15276 /* The following code determines the architecture and register size.
15277 Similar code was added to GCC 3.3 (see override_options() in
15278 config/mips/mips.c). The GAS and GCC code should be kept in sync
15279 as much as possible. */
15281 if (mips_arch_string != 0)
15282 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15284 if (file_mips_isa != ISA_UNKNOWN)
15286 /* Handle -mipsN. At this point, file_mips_isa contains the
15287 ISA level specified by -mipsN, while arch_info->isa contains
15288 the -march selection (if any). */
15289 if (arch_info != 0)
15291 /* -march takes precedence over -mipsN, since it is more descriptive.
15292 There's no harm in specifying both as long as the ISA levels
15294 if (file_mips_isa != arch_info->isa)
15295 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15296 mips_cpu_info_from_isa (file_mips_isa)->name,
15297 mips_cpu_info_from_isa (arch_info->isa)->name);
15300 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15303 if (arch_info == 0)
15305 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15306 gas_assert (arch_info);
15309 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15310 as_bad (_("-march=%s is not compatible with the selected ABI"),
15313 mips_set_architecture (arch_info);
15315 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15316 if (mips_tune_string != 0)
15317 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15319 if (tune_info == 0)
15320 mips_set_tune (arch_info);
15322 mips_set_tune (tune_info);
15324 if (file_mips_gp32 >= 0)
15326 /* The user specified the size of the integer registers. Make sure
15327 it agrees with the ABI and ISA. */
15328 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15329 as_bad (_("-mgp64 used with a 32-bit processor"));
15330 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15331 as_bad (_("-mgp32 used with a 64-bit ABI"));
15332 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15333 as_bad (_("-mgp64 used with a 32-bit ABI"));
15337 /* Infer the integer register size from the ABI and processor.
15338 Restrict ourselves to 32-bit registers if that's all the
15339 processor has, or if the ABI cannot handle 64-bit registers. */
15340 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15341 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15344 switch (file_mips_fp32)
15348 /* No user specified float register size.
15349 ??? GAS treats single-float processors as though they had 64-bit
15350 float registers (although it complains when double-precision
15351 instructions are used). As things stand, saying they have 32-bit
15352 registers would lead to spurious "register must be even" messages.
15353 So here we assume float registers are never smaller than the
15355 if (file_mips_gp32 == 0)
15356 /* 64-bit integer registers implies 64-bit float registers. */
15357 file_mips_fp32 = 0;
15358 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15359 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15360 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15361 file_mips_fp32 = 0;
15363 /* 32-bit float registers. */
15364 file_mips_fp32 = 1;
15367 /* The user specified the size of the float registers. Check if it
15368 agrees with the ABI and ISA. */
15370 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15371 as_bad (_("-mfp64 used with a 32-bit fpu"));
15372 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15373 && !ISA_HAS_MXHC1 (mips_opts.isa))
15374 as_warn (_("-mfp64 used with a 32-bit ABI"));
15377 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15378 as_warn (_("-mfp32 used with a 64-bit ABI"));
15382 /* End of GCC-shared inference code. */
15384 /* This flag is set when we have a 64-bit capable CPU but use only
15385 32-bit wide registers. Note that EABI does not use it. */
15386 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15387 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15388 || mips_abi == O32_ABI))
15389 mips_32bitmode = 1;
15391 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15392 as_bad (_("trap exception not supported at ISA 1"));
15394 /* If the selected architecture includes support for ASEs, enable
15395 generation of code for them. */
15396 if (mips_opts.mips16 == -1)
15397 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15398 if (mips_opts.micromips == -1)
15399 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15400 if (mips_opts.ase_mips3d == -1)
15401 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15402 && file_mips_fp32 == 0) ? 1 : 0;
15403 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15404 as_bad (_("-mfp32 used with -mips3d"));
15406 if (mips_opts.ase_mdmx == -1)
15407 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15408 && file_mips_fp32 == 0) ? 1 : 0;
15409 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15410 as_bad (_("-mfp32 used with -mdmx"));
15412 if (mips_opts.ase_smartmips == -1)
15413 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15414 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15415 as_warn (_("%s ISA does not support SmartMIPS"),
15416 mips_cpu_info_from_isa (mips_opts.isa)->name);
15418 if (mips_opts.ase_dsp == -1)
15419 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15420 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15421 as_warn (_("%s ISA does not support DSP ASE"),
15422 mips_cpu_info_from_isa (mips_opts.isa)->name);
15424 if (mips_opts.ase_dspr2 == -1)
15426 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15427 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15429 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15430 as_warn (_("%s ISA does not support DSP R2 ASE"),
15431 mips_cpu_info_from_isa (mips_opts.isa)->name);
15433 if (mips_opts.ase_mt == -1)
15434 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15435 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15436 as_warn (_("%s ISA does not support MT ASE"),
15437 mips_cpu_info_from_isa (mips_opts.isa)->name);
15439 if (mips_opts.ase_mcu == -1)
15440 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15441 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15442 as_warn (_("%s ISA does not support MCU ASE"),
15443 mips_cpu_info_from_isa (mips_opts.isa)->name);
15445 if (mips_opts.ase_virt == -1)
15446 mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0;
15447 if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE)
15448 as_warn (_("%s ISA does not support Virtualization ASE"),
15449 mips_cpu_info_from_isa (mips_opts.isa)->name);
15451 file_mips_isa = mips_opts.isa;
15452 file_ase_mips3d = mips_opts.ase_mips3d;
15453 file_ase_mdmx = mips_opts.ase_mdmx;
15454 file_ase_smartmips = mips_opts.ase_smartmips;
15455 file_ase_dsp = mips_opts.ase_dsp;
15456 file_ase_dspr2 = mips_opts.ase_dspr2;
15457 file_ase_mt = mips_opts.ase_mt;
15458 file_ase_virt = mips_opts.ase_virt;
15459 mips_opts.gp32 = file_mips_gp32;
15460 mips_opts.fp32 = file_mips_fp32;
15461 mips_opts.soft_float = file_mips_soft_float;
15462 mips_opts.single_float = file_mips_single_float;
15464 if (mips_flag_mdebug < 0)
15466 #ifdef OBJ_MAYBE_ECOFF
15467 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15468 mips_flag_mdebug = 1;
15470 #endif /* OBJ_MAYBE_ECOFF */
15471 mips_flag_mdebug = 0;
15476 mips_init_after_args (void)
15478 /* initialize opcodes */
15479 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15480 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15484 md_pcrel_from (fixS *fixP)
15486 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15487 switch (fixP->fx_r_type)
15489 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15490 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15491 /* Return the address of the delay slot. */
15494 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15495 case BFD_RELOC_MICROMIPS_JMP:
15496 case BFD_RELOC_16_PCREL_S2:
15497 case BFD_RELOC_MIPS_JMP:
15498 /* Return the address of the delay slot. */
15501 case BFD_RELOC_32_PCREL:
15505 /* We have no relocation type for PC relative MIPS16 instructions. */
15506 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15507 as_bad_where (fixP->fx_file, fixP->fx_line,
15508 _("PC relative MIPS16 instruction references a different section"));
15513 /* This is called before the symbol table is processed. In order to
15514 work with gcc when using mips-tfile, we must keep all local labels.
15515 However, in other cases, we want to discard them. If we were
15516 called with -g, but we didn't see any debugging information, it may
15517 mean that gcc is smuggling debugging information through to
15518 mips-tfile, in which case we must generate all local labels. */
15521 mips_frob_file_before_adjust (void)
15523 #ifndef NO_ECOFF_DEBUGGING
15524 if (ECOFF_DEBUGGING
15526 && ! ecoff_debugging_seen)
15527 flag_keep_locals = 1;
15531 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15532 the corresponding LO16 reloc. This is called before md_apply_fix and
15533 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15534 relocation operators.
15536 For our purposes, a %lo() expression matches a %got() or %hi()
15539 (a) it refers to the same symbol; and
15540 (b) the offset applied in the %lo() expression is no lower than
15541 the offset applied in the %got() or %hi().
15543 (b) allows us to cope with code like:
15546 lh $4,%lo(foo+2)($4)
15548 ...which is legal on RELA targets, and has a well-defined behaviour
15549 if the user knows that adding 2 to "foo" will not induce a carry to
15552 When several %lo()s match a particular %got() or %hi(), we use the
15553 following rules to distinguish them:
15555 (1) %lo()s with smaller offsets are a better match than %lo()s with
15558 (2) %lo()s with no matching %got() or %hi() are better than those
15559 that already have a matching %got() or %hi().
15561 (3) later %lo()s are better than earlier %lo()s.
15563 These rules are applied in order.
15565 (1) means, among other things, that %lo()s with identical offsets are
15566 chosen if they exist.
15568 (2) means that we won't associate several high-part relocations with
15569 the same low-part relocation unless there's no alternative. Having
15570 several high parts for the same low part is a GNU extension; this rule
15571 allows careful users to avoid it.
15573 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15574 with the last high-part relocation being at the front of the list.
15575 It therefore makes sense to choose the last matching low-part
15576 relocation, all other things being equal. It's also easier
15577 to code that way. */
15580 mips_frob_file (void)
15582 struct mips_hi_fixup *l;
15583 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15585 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15587 segment_info_type *seginfo;
15588 bfd_boolean matched_lo_p;
15589 fixS **hi_pos, **lo_pos, **pos;
15591 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15593 /* If a GOT16 relocation turns out to be against a global symbol,
15594 there isn't supposed to be a matching LO. Ignore %gots against
15595 constants; we'll report an error for those later. */
15596 if (got16_reloc_p (l->fixp->fx_r_type)
15597 && !(l->fixp->fx_addsy
15598 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15601 /* Check quickly whether the next fixup happens to be a matching %lo. */
15602 if (fixup_has_matching_lo_p (l->fixp))
15605 seginfo = seg_info (l->seg);
15607 /* Set HI_POS to the position of this relocation in the chain.
15608 Set LO_POS to the position of the chosen low-part relocation.
15609 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15610 relocation that matches an immediately-preceding high-part
15614 matched_lo_p = FALSE;
15615 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15617 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15619 if (*pos == l->fixp)
15622 if ((*pos)->fx_r_type == looking_for_rtype
15623 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15624 && (*pos)->fx_offset >= l->fixp->fx_offset
15626 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15628 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15631 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15632 && fixup_has_matching_lo_p (*pos));
15635 /* If we found a match, remove the high-part relocation from its
15636 current position and insert it before the low-part relocation.
15637 Make the offsets match so that fixup_has_matching_lo_p()
15640 We don't warn about unmatched high-part relocations since some
15641 versions of gcc have been known to emit dead "lui ...%hi(...)"
15643 if (lo_pos != NULL)
15645 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15646 if (l->fixp->fx_next != *lo_pos)
15648 *hi_pos = l->fixp->fx_next;
15649 l->fixp->fx_next = *lo_pos;
15657 mips_force_relocation (fixS *fixp)
15659 if (generic_force_reloc (fixp))
15662 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15663 so that the linker relaxation can update targets. */
15664 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15665 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15666 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15672 /* Read the instruction associated with RELOC from BUF. */
15674 static unsigned int
15675 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15677 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15678 return read_compressed_insn (buf, 4);
15680 return read_insn (buf);
15683 /* Write instruction INSN to BUF, given that it has been relocated
15687 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15688 unsigned long insn)
15690 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15691 write_compressed_insn (buf, insn, 4);
15693 write_insn (buf, insn);
15696 /* Apply a fixup to the object file. */
15699 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15702 unsigned long insn;
15703 reloc_howto_type *howto;
15705 /* We ignore generic BFD relocations we don't know about. */
15706 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15710 gas_assert (fixP->fx_size == 2
15711 || fixP->fx_size == 4
15712 || fixP->fx_r_type == BFD_RELOC_16
15713 || fixP->fx_r_type == BFD_RELOC_64
15714 || fixP->fx_r_type == BFD_RELOC_CTOR
15715 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15716 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15717 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15718 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15719 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15721 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15723 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15724 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15725 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15726 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15727 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15729 /* Don't treat parts of a composite relocation as done. There are two
15732 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15733 should nevertheless be emitted if the first part is.
15735 (2) In normal usage, composite relocations are never assembly-time
15736 constants. The easiest way of dealing with the pathological
15737 exceptions is to generate a relocation against STN_UNDEF and
15738 leave everything up to the linker. */
15739 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15742 switch (fixP->fx_r_type)
15744 case BFD_RELOC_MIPS_TLS_GD:
15745 case BFD_RELOC_MIPS_TLS_LDM:
15746 case BFD_RELOC_MIPS_TLS_DTPREL32:
15747 case BFD_RELOC_MIPS_TLS_DTPREL64:
15748 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15749 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15750 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15751 case BFD_RELOC_MIPS_TLS_TPREL32:
15752 case BFD_RELOC_MIPS_TLS_TPREL64:
15753 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15754 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15755 case BFD_RELOC_MICROMIPS_TLS_GD:
15756 case BFD_RELOC_MICROMIPS_TLS_LDM:
15757 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15758 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15759 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15760 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15761 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15762 case BFD_RELOC_MIPS16_TLS_GD:
15763 case BFD_RELOC_MIPS16_TLS_LDM:
15764 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15765 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15766 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15767 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15768 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15769 if (!fixP->fx_addsy)
15771 as_bad_where (fixP->fx_file, fixP->fx_line,
15772 _("TLS relocation against a constant"));
15775 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15778 case BFD_RELOC_MIPS_JMP:
15779 case BFD_RELOC_MIPS_SHIFT5:
15780 case BFD_RELOC_MIPS_SHIFT6:
15781 case BFD_RELOC_MIPS_GOT_DISP:
15782 case BFD_RELOC_MIPS_GOT_PAGE:
15783 case BFD_RELOC_MIPS_GOT_OFST:
15784 case BFD_RELOC_MIPS_SUB:
15785 case BFD_RELOC_MIPS_INSERT_A:
15786 case BFD_RELOC_MIPS_INSERT_B:
15787 case BFD_RELOC_MIPS_DELETE:
15788 case BFD_RELOC_MIPS_HIGHEST:
15789 case BFD_RELOC_MIPS_HIGHER:
15790 case BFD_RELOC_MIPS_SCN_DISP:
15791 case BFD_RELOC_MIPS_REL16:
15792 case BFD_RELOC_MIPS_RELGOT:
15793 case BFD_RELOC_MIPS_JALR:
15794 case BFD_RELOC_HI16:
15795 case BFD_RELOC_HI16_S:
15796 case BFD_RELOC_LO16:
15797 case BFD_RELOC_GPREL16:
15798 case BFD_RELOC_MIPS_LITERAL:
15799 case BFD_RELOC_MIPS_CALL16:
15800 case BFD_RELOC_MIPS_GOT16:
15801 case BFD_RELOC_GPREL32:
15802 case BFD_RELOC_MIPS_GOT_HI16:
15803 case BFD_RELOC_MIPS_GOT_LO16:
15804 case BFD_RELOC_MIPS_CALL_HI16:
15805 case BFD_RELOC_MIPS_CALL_LO16:
15806 case BFD_RELOC_MIPS16_GPREL:
15807 case BFD_RELOC_MIPS16_GOT16:
15808 case BFD_RELOC_MIPS16_CALL16:
15809 case BFD_RELOC_MIPS16_HI16:
15810 case BFD_RELOC_MIPS16_HI16_S:
15811 case BFD_RELOC_MIPS16_LO16:
15812 case BFD_RELOC_MIPS16_JMP:
15813 case BFD_RELOC_MICROMIPS_JMP:
15814 case BFD_RELOC_MICROMIPS_GOT_DISP:
15815 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15816 case BFD_RELOC_MICROMIPS_GOT_OFST:
15817 case BFD_RELOC_MICROMIPS_SUB:
15818 case BFD_RELOC_MICROMIPS_HIGHEST:
15819 case BFD_RELOC_MICROMIPS_HIGHER:
15820 case BFD_RELOC_MICROMIPS_SCN_DISP:
15821 case BFD_RELOC_MICROMIPS_JALR:
15822 case BFD_RELOC_MICROMIPS_HI16:
15823 case BFD_RELOC_MICROMIPS_HI16_S:
15824 case BFD_RELOC_MICROMIPS_LO16:
15825 case BFD_RELOC_MICROMIPS_GPREL16:
15826 case BFD_RELOC_MICROMIPS_LITERAL:
15827 case BFD_RELOC_MICROMIPS_CALL16:
15828 case BFD_RELOC_MICROMIPS_GOT16:
15829 case BFD_RELOC_MICROMIPS_GOT_HI16:
15830 case BFD_RELOC_MICROMIPS_GOT_LO16:
15831 case BFD_RELOC_MICROMIPS_CALL_HI16:
15832 case BFD_RELOC_MICROMIPS_CALL_LO16:
15833 case BFD_RELOC_MIPS_EH:
15838 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15840 insn = read_reloc_insn (buf, fixP->fx_r_type);
15841 if (mips16_reloc_p (fixP->fx_r_type))
15842 insn |= mips16_immed_extend (value, 16);
15844 insn |= (value & 0xffff);
15845 write_reloc_insn (buf, fixP->fx_r_type, insn);
15848 as_bad_where (fixP->fx_file, fixP->fx_line,
15849 _("Unsupported constant in relocation"));
15854 /* This is handled like BFD_RELOC_32, but we output a sign
15855 extended value if we are only 32 bits. */
15858 if (8 <= sizeof (valueT))
15859 md_number_to_chars (buf, *valP, 8);
15864 if ((*valP & 0x80000000) != 0)
15868 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15869 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15874 case BFD_RELOC_RVA:
15876 case BFD_RELOC_32_PCREL:
15878 /* If we are deleting this reloc entry, we must fill in the
15879 value now. This can happen if we have a .word which is not
15880 resolved when it appears but is later defined. */
15882 md_number_to_chars (buf, *valP, fixP->fx_size);
15885 case BFD_RELOC_16_PCREL_S2:
15886 if ((*valP & 0x3) != 0)
15887 as_bad_where (fixP->fx_file, fixP->fx_line,
15888 _("Branch to misaligned address (%lx)"), (long) *valP);
15890 /* We need to save the bits in the instruction since fixup_segment()
15891 might be deleting the relocation entry (i.e., a branch within
15892 the current segment). */
15893 if (! fixP->fx_done)
15896 /* Update old instruction data. */
15897 insn = read_insn (buf);
15899 if (*valP + 0x20000 <= 0x3ffff)
15901 insn |= (*valP >> 2) & 0xffff;
15902 write_insn (buf, insn);
15904 else if (mips_pic == NO_PIC
15906 && fixP->fx_frag->fr_address >= text_section->vma
15907 && (fixP->fx_frag->fr_address
15908 < text_section->vma + bfd_get_section_size (text_section))
15909 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15910 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15911 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15913 /* The branch offset is too large. If this is an
15914 unconditional branch, and we are not generating PIC code,
15915 we can convert it to an absolute jump instruction. */
15916 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15917 insn = 0x0c000000; /* jal */
15919 insn = 0x08000000; /* j */
15920 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15922 fixP->fx_addsy = section_symbol (text_section);
15923 *valP += md_pcrel_from (fixP);
15924 write_insn (buf, insn);
15928 /* If we got here, we have branch-relaxation disabled,
15929 and there's nothing we can do to fix this instruction
15930 without turning it into a longer sequence. */
15931 as_bad_where (fixP->fx_file, fixP->fx_line,
15932 _("Branch out of range"));
15936 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15937 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15938 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15939 /* We adjust the offset back to even. */
15940 if ((*valP & 0x1) != 0)
15943 if (! fixP->fx_done)
15946 /* Should never visit here, because we keep the relocation. */
15950 case BFD_RELOC_VTABLE_INHERIT:
15953 && !S_IS_DEFINED (fixP->fx_addsy)
15954 && !S_IS_WEAK (fixP->fx_addsy))
15955 S_SET_WEAK (fixP->fx_addsy);
15958 case BFD_RELOC_VTABLE_ENTRY:
15966 /* Remember value for tc_gen_reloc. */
15967 fixP->fx_addnumber = *valP;
15977 name = input_line_pointer;
15978 c = get_symbol_end ();
15979 p = (symbolS *) symbol_find_or_make (name);
15980 *input_line_pointer = c;
15984 /* Align the current frag to a given power of two. If a particular
15985 fill byte should be used, FILL points to an integer that contains
15986 that byte, otherwise FILL is null.
15988 This function used to have the comment:
15990 The MIPS assembler also automatically adjusts any preceding label.
15992 The implementation therefore applied the adjustment to a maximum of
15993 one label. However, other label adjustments are applied to batches
15994 of labels, and adjusting just one caused problems when new labels
15995 were added for the sake of debugging or unwind information.
15996 We therefore adjust all preceding labels (given as LABELS) instead. */
15999 mips_align (int to, int *fill, struct insn_label_list *labels)
16001 mips_emit_delays ();
16002 mips_record_compressed_mode ();
16003 if (fill == NULL && subseg_text_p (now_seg))
16004 frag_align_code (to, 0);
16006 frag_align (to, fill ? *fill : 0, 0);
16007 record_alignment (now_seg, to);
16008 mips_move_labels (labels, FALSE);
16011 /* Align to a given power of two. .align 0 turns off the automatic
16012 alignment used by the data creating pseudo-ops. */
16015 s_align (int x ATTRIBUTE_UNUSED)
16017 int temp, fill_value, *fill_ptr;
16018 long max_alignment = 28;
16020 /* o Note that the assembler pulls down any immediately preceding label
16021 to the aligned address.
16022 o It's not documented but auto alignment is reinstated by
16023 a .align pseudo instruction.
16024 o Note also that after auto alignment is turned off the mips assembler
16025 issues an error on attempt to assemble an improperly aligned data item.
16028 temp = get_absolute_expression ();
16029 if (temp > max_alignment)
16030 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16033 as_warn (_("Alignment negative: 0 assumed."));
16036 if (*input_line_pointer == ',')
16038 ++input_line_pointer;
16039 fill_value = get_absolute_expression ();
16040 fill_ptr = &fill_value;
16046 segment_info_type *si = seg_info (now_seg);
16047 struct insn_label_list *l = si->label_list;
16048 /* Auto alignment should be switched on by next section change. */
16050 mips_align (temp, fill_ptr, l);
16057 demand_empty_rest_of_line ();
16061 s_change_sec (int sec)
16066 /* The ELF backend needs to know that we are changing sections, so
16067 that .previous works correctly. We could do something like check
16068 for an obj_section_change_hook macro, but that might be confusing
16069 as it would not be appropriate to use it in the section changing
16070 functions in read.c, since obj-elf.c intercepts those. FIXME:
16071 This should be cleaner, somehow. */
16073 obj_elf_section_change_hook ();
16076 mips_emit_delays ();
16087 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16088 demand_empty_rest_of_line ();
16092 seg = subseg_new (RDATA_SECTION_NAME,
16093 (subsegT) get_absolute_expression ());
16096 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16097 | SEC_READONLY | SEC_RELOC
16099 if (strncmp (TARGET_OS, "elf", 3) != 0)
16100 record_alignment (seg, 4);
16102 demand_empty_rest_of_line ();
16106 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16109 bfd_set_section_flags (stdoutput, seg,
16110 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16111 if (strncmp (TARGET_OS, "elf", 3) != 0)
16112 record_alignment (seg, 4);
16114 demand_empty_rest_of_line ();
16118 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16121 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16122 if (strncmp (TARGET_OS, "elf", 3) != 0)
16123 record_alignment (seg, 4);
16125 demand_empty_rest_of_line ();
16133 s_change_section (int ignore ATTRIBUTE_UNUSED)
16136 char *section_name;
16141 int section_entry_size;
16142 int section_alignment;
16147 section_name = input_line_pointer;
16148 c = get_symbol_end ();
16150 next_c = *(input_line_pointer + 1);
16152 /* Do we have .section Name<,"flags">? */
16153 if (c != ',' || (c == ',' && next_c == '"'))
16155 /* just after name is now '\0'. */
16156 *input_line_pointer = c;
16157 input_line_pointer = section_name;
16158 obj_elf_section (ignore);
16161 input_line_pointer++;
16163 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16165 section_type = get_absolute_expression ();
16168 if (*input_line_pointer++ == ',')
16169 section_flag = get_absolute_expression ();
16172 if (*input_line_pointer++ == ',')
16173 section_entry_size = get_absolute_expression ();
16175 section_entry_size = 0;
16176 if (*input_line_pointer++ == ',')
16177 section_alignment = get_absolute_expression ();
16179 section_alignment = 0;
16180 /* FIXME: really ignore? */
16181 (void) section_alignment;
16183 section_name = xstrdup (section_name);
16185 /* When using the generic form of .section (as implemented by obj-elf.c),
16186 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16187 traditionally had to fall back on the more common @progbits instead.
16189 There's nothing really harmful in this, since bfd will correct
16190 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16191 means that, for backwards compatibility, the special_section entries
16192 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16194 Even so, we shouldn't force users of the MIPS .section syntax to
16195 incorrectly label the sections as SHT_PROGBITS. The best compromise
16196 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16197 generic type-checking code. */
16198 if (section_type == SHT_MIPS_DWARF)
16199 section_type = SHT_PROGBITS;
16201 obj_elf_change_section (section_name, section_type, section_flag,
16202 section_entry_size, 0, 0, 0);
16204 if (now_seg->name != section_name)
16205 free (section_name);
16206 #endif /* OBJ_ELF */
16210 mips_enable_auto_align (void)
16216 s_cons (int log_size)
16218 segment_info_type *si = seg_info (now_seg);
16219 struct insn_label_list *l = si->label_list;
16221 mips_emit_delays ();
16222 if (log_size > 0 && auto_align)
16223 mips_align (log_size, 0, l);
16224 cons (1 << log_size);
16225 mips_clear_insn_labels ();
16229 s_float_cons (int type)
16231 segment_info_type *si = seg_info (now_seg);
16232 struct insn_label_list *l = si->label_list;
16234 mips_emit_delays ();
16239 mips_align (3, 0, l);
16241 mips_align (2, 0, l);
16245 mips_clear_insn_labels ();
16248 /* Handle .globl. We need to override it because on Irix 5 you are
16251 where foo is an undefined symbol, to mean that foo should be
16252 considered to be the address of a function. */
16255 s_mips_globl (int x ATTRIBUTE_UNUSED)
16264 name = input_line_pointer;
16265 c = get_symbol_end ();
16266 symbolP = symbol_find_or_make (name);
16267 S_SET_EXTERNAL (symbolP);
16269 *input_line_pointer = c;
16270 SKIP_WHITESPACE ();
16272 /* On Irix 5, every global symbol that is not explicitly labelled as
16273 being a function is apparently labelled as being an object. */
16276 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16277 && (*input_line_pointer != ','))
16282 secname = input_line_pointer;
16283 c = get_symbol_end ();
16284 sec = bfd_get_section_by_name (stdoutput, secname);
16286 as_bad (_("%s: no such section"), secname);
16287 *input_line_pointer = c;
16289 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16290 flag = BSF_FUNCTION;
16293 symbol_get_bfdsym (symbolP)->flags |= flag;
16295 c = *input_line_pointer;
16298 input_line_pointer++;
16299 SKIP_WHITESPACE ();
16300 if (is_end_of_line[(unsigned char) *input_line_pointer])
16306 demand_empty_rest_of_line ();
16310 s_option (int x ATTRIBUTE_UNUSED)
16315 opt = input_line_pointer;
16316 c = get_symbol_end ();
16320 /* FIXME: What does this mean? */
16322 else if (strncmp (opt, "pic", 3) == 0)
16326 i = atoi (opt + 3);
16331 mips_pic = SVR4_PIC;
16332 mips_abicalls = TRUE;
16335 as_bad (_(".option pic%d not supported"), i);
16337 if (mips_pic == SVR4_PIC)
16339 if (g_switch_seen && g_switch_value != 0)
16340 as_warn (_("-G may not be used with SVR4 PIC code"));
16341 g_switch_value = 0;
16342 bfd_set_gp_size (stdoutput, 0);
16346 as_warn (_("Unrecognized option \"%s\""), opt);
16348 *input_line_pointer = c;
16349 demand_empty_rest_of_line ();
16352 /* This structure is used to hold a stack of .set values. */
16354 struct mips_option_stack
16356 struct mips_option_stack *next;
16357 struct mips_set_options options;
16360 static struct mips_option_stack *mips_opts_stack;
16362 /* Handle the .set pseudo-op. */
16365 s_mipsset (int x ATTRIBUTE_UNUSED)
16367 char *name = input_line_pointer, ch;
16369 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16370 ++input_line_pointer;
16371 ch = *input_line_pointer;
16372 *input_line_pointer = '\0';
16374 if (strcmp (name, "reorder") == 0)
16376 if (mips_opts.noreorder)
16379 else if (strcmp (name, "noreorder") == 0)
16381 if (!mips_opts.noreorder)
16382 start_noreorder ();
16384 else if (strncmp (name, "at=", 3) == 0)
16386 char *s = name + 3;
16388 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16389 as_bad (_("Unrecognized register name `%s'"), s);
16391 else if (strcmp (name, "at") == 0)
16393 mips_opts.at = ATREG;
16395 else if (strcmp (name, "noat") == 0)
16397 mips_opts.at = ZERO;
16399 else if (strcmp (name, "macro") == 0)
16401 mips_opts.warn_about_macros = 0;
16403 else if (strcmp (name, "nomacro") == 0)
16405 if (mips_opts.noreorder == 0)
16406 as_bad (_("`noreorder' must be set before `nomacro'"));
16407 mips_opts.warn_about_macros = 1;
16409 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16411 mips_opts.nomove = 0;
16413 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16415 mips_opts.nomove = 1;
16417 else if (strcmp (name, "bopt") == 0)
16419 mips_opts.nobopt = 0;
16421 else if (strcmp (name, "nobopt") == 0)
16423 mips_opts.nobopt = 1;
16425 else if (strcmp (name, "gp=default") == 0)
16426 mips_opts.gp32 = file_mips_gp32;
16427 else if (strcmp (name, "gp=32") == 0)
16428 mips_opts.gp32 = 1;
16429 else if (strcmp (name, "gp=64") == 0)
16431 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16432 as_warn (_("%s isa does not support 64-bit registers"),
16433 mips_cpu_info_from_isa (mips_opts.isa)->name);
16434 mips_opts.gp32 = 0;
16436 else if (strcmp (name, "fp=default") == 0)
16437 mips_opts.fp32 = file_mips_fp32;
16438 else if (strcmp (name, "fp=32") == 0)
16439 mips_opts.fp32 = 1;
16440 else if (strcmp (name, "fp=64") == 0)
16442 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16443 as_warn (_("%s isa does not support 64-bit floating point registers"),
16444 mips_cpu_info_from_isa (mips_opts.isa)->name);
16445 mips_opts.fp32 = 0;
16447 else if (strcmp (name, "softfloat") == 0)
16448 mips_opts.soft_float = 1;
16449 else if (strcmp (name, "hardfloat") == 0)
16450 mips_opts.soft_float = 0;
16451 else if (strcmp (name, "singlefloat") == 0)
16452 mips_opts.single_float = 1;
16453 else if (strcmp (name, "doublefloat") == 0)
16454 mips_opts.single_float = 0;
16455 else if (strcmp (name, "mips16") == 0
16456 || strcmp (name, "MIPS-16") == 0)
16458 if (mips_opts.micromips == 1)
16459 as_fatal (_("`mips16' cannot be used with `micromips'"));
16460 mips_opts.mips16 = 1;
16462 else if (strcmp (name, "nomips16") == 0
16463 || strcmp (name, "noMIPS-16") == 0)
16464 mips_opts.mips16 = 0;
16465 else if (strcmp (name, "micromips") == 0)
16467 if (mips_opts.mips16 == 1)
16468 as_fatal (_("`micromips' cannot be used with `mips16'"));
16469 mips_opts.micromips = 1;
16471 else if (strcmp (name, "nomicromips") == 0)
16472 mips_opts.micromips = 0;
16473 else if (strcmp (name, "smartmips") == 0)
16475 if (!ISA_SUPPORTS_SMARTMIPS)
16476 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16477 mips_cpu_info_from_isa (mips_opts.isa)->name);
16478 mips_opts.ase_smartmips = 1;
16480 else if (strcmp (name, "nosmartmips") == 0)
16481 mips_opts.ase_smartmips = 0;
16482 else if (strcmp (name, "mips3d") == 0)
16483 mips_opts.ase_mips3d = 1;
16484 else if (strcmp (name, "nomips3d") == 0)
16485 mips_opts.ase_mips3d = 0;
16486 else if (strcmp (name, "mdmx") == 0)
16487 mips_opts.ase_mdmx = 1;
16488 else if (strcmp (name, "nomdmx") == 0)
16489 mips_opts.ase_mdmx = 0;
16490 else if (strcmp (name, "dsp") == 0)
16492 if (!ISA_SUPPORTS_DSP_ASE)
16493 as_warn (_("%s ISA does not support DSP ASE"),
16494 mips_cpu_info_from_isa (mips_opts.isa)->name);
16495 mips_opts.ase_dsp = 1;
16496 mips_opts.ase_dspr2 = 0;
16498 else if (strcmp (name, "nodsp") == 0)
16500 mips_opts.ase_dsp = 0;
16501 mips_opts.ase_dspr2 = 0;
16503 else if (strcmp (name, "dspr2") == 0)
16505 if (!ISA_SUPPORTS_DSPR2_ASE)
16506 as_warn (_("%s ISA does not support DSP R2 ASE"),
16507 mips_cpu_info_from_isa (mips_opts.isa)->name);
16508 mips_opts.ase_dspr2 = 1;
16509 mips_opts.ase_dsp = 1;
16511 else if (strcmp (name, "nodspr2") == 0)
16513 mips_opts.ase_dspr2 = 0;
16514 mips_opts.ase_dsp = 0;
16516 else if (strcmp (name, "mt") == 0)
16518 if (!ISA_SUPPORTS_MT_ASE)
16519 as_warn (_("%s ISA does not support MT ASE"),
16520 mips_cpu_info_from_isa (mips_opts.isa)->name);
16521 mips_opts.ase_mt = 1;
16523 else if (strcmp (name, "nomt") == 0)
16524 mips_opts.ase_mt = 0;
16525 else if (strcmp (name, "mcu") == 0)
16526 mips_opts.ase_mcu = 1;
16527 else if (strcmp (name, "nomcu") == 0)
16528 mips_opts.ase_mcu = 0;
16529 else if (strcmp (name, "virt") == 0)
16531 if (!ISA_SUPPORTS_VIRT_ASE)
16532 as_warn (_("%s ISA does not support Virtualization ASE"),
16533 mips_cpu_info_from_isa (mips_opts.isa)->name);
16534 mips_opts.ase_virt = 1;
16536 else if (strcmp (name, "novirt") == 0)
16537 mips_opts.ase_virt = 0;
16538 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16542 /* Permit the user to change the ISA and architecture on the fly.
16543 Needless to say, misuse can cause serious problems. */
16544 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16547 mips_opts.isa = file_mips_isa;
16548 mips_opts.arch = file_mips_arch;
16550 else if (strncmp (name, "arch=", 5) == 0)
16552 const struct mips_cpu_info *p;
16554 p = mips_parse_cpu("internal use", name + 5);
16556 as_bad (_("unknown architecture %s"), name + 5);
16559 mips_opts.arch = p->cpu;
16560 mips_opts.isa = p->isa;
16563 else if (strncmp (name, "mips", 4) == 0)
16565 const struct mips_cpu_info *p;
16567 p = mips_parse_cpu("internal use", name);
16569 as_bad (_("unknown ISA level %s"), name + 4);
16572 mips_opts.arch = p->cpu;
16573 mips_opts.isa = p->isa;
16577 as_bad (_("unknown ISA or architecture %s"), name);
16579 switch (mips_opts.isa)
16587 mips_opts.gp32 = 1;
16588 mips_opts.fp32 = 1;
16595 mips_opts.gp32 = 0;
16596 if (mips_opts.arch == CPU_R5900)
16598 mips_opts.fp32 = 1;
16602 mips_opts.fp32 = 0;
16606 as_bad (_("unknown ISA level %s"), name + 4);
16611 mips_opts.gp32 = file_mips_gp32;
16612 mips_opts.fp32 = file_mips_fp32;
16615 else if (strcmp (name, "autoextend") == 0)
16616 mips_opts.noautoextend = 0;
16617 else if (strcmp (name, "noautoextend") == 0)
16618 mips_opts.noautoextend = 1;
16619 else if (strcmp (name, "push") == 0)
16621 struct mips_option_stack *s;
16623 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16624 s->next = mips_opts_stack;
16625 s->options = mips_opts;
16626 mips_opts_stack = s;
16628 else if (strcmp (name, "pop") == 0)
16630 struct mips_option_stack *s;
16632 s = mips_opts_stack;
16634 as_bad (_(".set pop with no .set push"));
16637 /* If we're changing the reorder mode we need to handle
16638 delay slots correctly. */
16639 if (s->options.noreorder && ! mips_opts.noreorder)
16640 start_noreorder ();
16641 else if (! s->options.noreorder && mips_opts.noreorder)
16644 mips_opts = s->options;
16645 mips_opts_stack = s->next;
16649 else if (strcmp (name, "sym32") == 0)
16650 mips_opts.sym32 = TRUE;
16651 else if (strcmp (name, "nosym32") == 0)
16652 mips_opts.sym32 = FALSE;
16653 else if (strchr (name, ','))
16655 /* Generic ".set" directive; use the generic handler. */
16656 *input_line_pointer = ch;
16657 input_line_pointer = name;
16663 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16665 *input_line_pointer = ch;
16666 demand_empty_rest_of_line ();
16669 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16670 .option pic2. It means to generate SVR4 PIC calls. */
16673 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16675 mips_pic = SVR4_PIC;
16676 mips_abicalls = TRUE;
16678 if (g_switch_seen && g_switch_value != 0)
16679 as_warn (_("-G may not be used with SVR4 PIC code"));
16680 g_switch_value = 0;
16682 bfd_set_gp_size (stdoutput, 0);
16683 demand_empty_rest_of_line ();
16686 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16687 PIC code. It sets the $gp register for the function based on the
16688 function address, which is in the register named in the argument.
16689 This uses a relocation against _gp_disp, which is handled specially
16690 by the linker. The result is:
16691 lui $gp,%hi(_gp_disp)
16692 addiu $gp,$gp,%lo(_gp_disp)
16693 addu $gp,$gp,.cpload argument
16694 The .cpload argument is normally $25 == $t9.
16696 The -mno-shared option changes this to:
16697 lui $gp,%hi(__gnu_local_gp)
16698 addiu $gp,$gp,%lo(__gnu_local_gp)
16699 and the argument is ignored. This saves an instruction, but the
16700 resulting code is not position independent; it uses an absolute
16701 address for __gnu_local_gp. Thus code assembled with -mno-shared
16702 can go into an ordinary executable, but not into a shared library. */
16705 s_cpload (int ignore ATTRIBUTE_UNUSED)
16711 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16712 .cpload is ignored. */
16713 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16719 if (mips_opts.mips16)
16721 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16722 ignore_rest_of_line ();
16726 /* .cpload should be in a .set noreorder section. */
16727 if (mips_opts.noreorder == 0)
16728 as_warn (_(".cpload not in noreorder section"));
16730 reg = tc_get_register (0);
16732 /* If we need to produce a 64-bit address, we are better off using
16733 the default instruction sequence. */
16734 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16736 ex.X_op = O_symbol;
16737 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16739 ex.X_op_symbol = NULL;
16740 ex.X_add_number = 0;
16742 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16743 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16745 mips_mark_labels ();
16746 mips_assembling_insn = TRUE;
16749 macro_build_lui (&ex, mips_gp_register);
16750 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16751 mips_gp_register, BFD_RELOC_LO16);
16753 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16754 mips_gp_register, reg);
16757 mips_assembling_insn = FALSE;
16758 demand_empty_rest_of_line ();
16761 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16762 .cpsetup $reg1, offset|$reg2, label
16764 If offset is given, this results in:
16765 sd $gp, offset($sp)
16766 lui $gp, %hi(%neg(%gp_rel(label)))
16767 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16768 daddu $gp, $gp, $reg1
16770 If $reg2 is given, this results in:
16771 daddu $reg2, $gp, $0
16772 lui $gp, %hi(%neg(%gp_rel(label)))
16773 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16774 daddu $gp, $gp, $reg1
16775 $reg1 is normally $25 == $t9.
16777 The -mno-shared option replaces the last three instructions with
16779 addiu $gp,$gp,%lo(_gp) */
16782 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16784 expressionS ex_off;
16785 expressionS ex_sym;
16788 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16789 We also need NewABI support. */
16790 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16796 if (mips_opts.mips16)
16798 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16799 ignore_rest_of_line ();
16803 reg1 = tc_get_register (0);
16804 SKIP_WHITESPACE ();
16805 if (*input_line_pointer != ',')
16807 as_bad (_("missing argument separator ',' for .cpsetup"));
16811 ++input_line_pointer;
16812 SKIP_WHITESPACE ();
16813 if (*input_line_pointer == '$')
16815 mips_cpreturn_register = tc_get_register (0);
16816 mips_cpreturn_offset = -1;
16820 mips_cpreturn_offset = get_absolute_expression ();
16821 mips_cpreturn_register = -1;
16823 SKIP_WHITESPACE ();
16824 if (*input_line_pointer != ',')
16826 as_bad (_("missing argument separator ',' for .cpsetup"));
16830 ++input_line_pointer;
16831 SKIP_WHITESPACE ();
16832 expression (&ex_sym);
16834 mips_mark_labels ();
16835 mips_assembling_insn = TRUE;
16838 if (mips_cpreturn_register == -1)
16840 ex_off.X_op = O_constant;
16841 ex_off.X_add_symbol = NULL;
16842 ex_off.X_op_symbol = NULL;
16843 ex_off.X_add_number = mips_cpreturn_offset;
16845 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16846 BFD_RELOC_LO16, SP);
16849 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16850 mips_gp_register, 0);
16852 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16854 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16855 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16858 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16859 mips_gp_register, -1, BFD_RELOC_GPREL16,
16860 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16863 mips_gp_register, reg1);
16869 ex.X_op = O_symbol;
16870 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16871 ex.X_op_symbol = NULL;
16872 ex.X_add_number = 0;
16874 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16875 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16877 macro_build_lui (&ex, mips_gp_register);
16878 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16879 mips_gp_register, BFD_RELOC_LO16);
16884 mips_assembling_insn = FALSE;
16885 demand_empty_rest_of_line ();
16889 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16891 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16892 .cplocal is ignored. */
16893 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16899 if (mips_opts.mips16)
16901 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16902 ignore_rest_of_line ();
16906 mips_gp_register = tc_get_register (0);
16907 demand_empty_rest_of_line ();
16910 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16911 offset from $sp. The offset is remembered, and after making a PIC
16912 call $gp is restored from that location. */
16915 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16919 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16920 .cprestore is ignored. */
16921 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16927 if (mips_opts.mips16)
16929 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16930 ignore_rest_of_line ();
16934 mips_cprestore_offset = get_absolute_expression ();
16935 mips_cprestore_valid = 1;
16937 ex.X_op = O_constant;
16938 ex.X_add_symbol = NULL;
16939 ex.X_op_symbol = NULL;
16940 ex.X_add_number = mips_cprestore_offset;
16942 mips_mark_labels ();
16943 mips_assembling_insn = TRUE;
16946 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16947 SP, HAVE_64BIT_ADDRESSES);
16950 mips_assembling_insn = FALSE;
16951 demand_empty_rest_of_line ();
16954 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16955 was given in the preceding .cpsetup, it results in:
16956 ld $gp, offset($sp)
16958 If a register $reg2 was given there, it results in:
16959 daddu $gp, $reg2, $0 */
16962 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16966 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16967 We also need NewABI support. */
16968 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16974 if (mips_opts.mips16)
16976 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16977 ignore_rest_of_line ();
16981 mips_mark_labels ();
16982 mips_assembling_insn = TRUE;
16985 if (mips_cpreturn_register == -1)
16987 ex.X_op = O_constant;
16988 ex.X_add_symbol = NULL;
16989 ex.X_op_symbol = NULL;
16990 ex.X_add_number = mips_cpreturn_offset;
16992 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16995 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16996 mips_cpreturn_register, 0);
16999 mips_assembling_insn = FALSE;
17000 demand_empty_rest_of_line ();
17003 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17004 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17005 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17006 debug information or MIPS16 TLS. */
17009 s_tls_rel_directive (const size_t bytes, const char *dirstr,
17010 bfd_reloc_code_real_type rtype)
17017 if (ex.X_op != O_symbol)
17019 as_bad (_("Unsupported use of %s"), dirstr);
17020 ignore_rest_of_line ();
17023 p = frag_more (bytes);
17024 md_number_to_chars (p, 0, bytes);
17025 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
17026 demand_empty_rest_of_line ();
17027 mips_clear_insn_labels ();
17030 /* Handle .dtprelword. */
17033 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
17035 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
17038 /* Handle .dtpreldword. */
17041 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
17043 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
17046 /* Handle .tprelword. */
17049 s_tprelword (int ignore ATTRIBUTE_UNUSED)
17051 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
17054 /* Handle .tpreldword. */
17057 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17059 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17062 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17063 code. It sets the offset to use in gp_rel relocations. */
17066 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17068 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17069 We also need NewABI support. */
17070 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17076 mips_gprel_offset = get_absolute_expression ();
17078 demand_empty_rest_of_line ();
17081 /* Handle the .gpword pseudo-op. This is used when generating PIC
17082 code. It generates a 32 bit GP relative reloc. */
17085 s_gpword (int ignore ATTRIBUTE_UNUSED)
17087 segment_info_type *si;
17088 struct insn_label_list *l;
17092 /* When not generating PIC code, this is treated as .word. */
17093 if (mips_pic != SVR4_PIC)
17099 si = seg_info (now_seg);
17100 l = si->label_list;
17101 mips_emit_delays ();
17103 mips_align (2, 0, l);
17106 mips_clear_insn_labels ();
17108 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17110 as_bad (_("Unsupported use of .gpword"));
17111 ignore_rest_of_line ();
17115 md_number_to_chars (p, 0, 4);
17116 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17117 BFD_RELOC_GPREL32);
17119 demand_empty_rest_of_line ();
17123 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17125 segment_info_type *si;
17126 struct insn_label_list *l;
17130 /* When not generating PIC code, this is treated as .dword. */
17131 if (mips_pic != SVR4_PIC)
17137 si = seg_info (now_seg);
17138 l = si->label_list;
17139 mips_emit_delays ();
17141 mips_align (3, 0, l);
17144 mips_clear_insn_labels ();
17146 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17148 as_bad (_("Unsupported use of .gpdword"));
17149 ignore_rest_of_line ();
17153 md_number_to_chars (p, 0, 8);
17154 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17155 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17157 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17158 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17159 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17161 demand_empty_rest_of_line ();
17164 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17165 tables. It generates a R_MIPS_EH reloc. */
17168 s_ehword (int ignore ATTRIBUTE_UNUSED)
17173 mips_emit_delays ();
17176 mips_clear_insn_labels ();
17178 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17180 as_bad (_("Unsupported use of .ehword"));
17181 ignore_rest_of_line ();
17185 md_number_to_chars (p, 0, 4);
17186 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17187 BFD_RELOC_MIPS_EH);
17189 demand_empty_rest_of_line ();
17192 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17193 tables in SVR4 PIC code. */
17196 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17200 /* This is ignored when not generating SVR4 PIC code. */
17201 if (mips_pic != SVR4_PIC)
17207 mips_mark_labels ();
17208 mips_assembling_insn = TRUE;
17210 /* Add $gp to the register named as an argument. */
17212 reg = tc_get_register (0);
17213 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17216 mips_assembling_insn = FALSE;
17217 demand_empty_rest_of_line ();
17220 /* Handle the .insn pseudo-op. This marks instruction labels in
17221 mips16/micromips mode. This permits the linker to handle them specially,
17222 such as generating jalx instructions when needed. We also make
17223 them odd for the duration of the assembly, in order to generate the
17224 right sort of code. We will make them even in the adjust_symtab
17225 routine, while leaving them marked. This is convenient for the
17226 debugger and the disassembler. The linker knows to make them odd
17230 s_insn (int ignore ATTRIBUTE_UNUSED)
17232 mips_mark_labels ();
17234 demand_empty_rest_of_line ();
17237 /* Handle a .stab[snd] directive. Ideally these directives would be
17238 implemented in a transparent way, so that removing them would not
17239 have any effect on the generated instructions. However, s_stab
17240 internally changes the section, so in practice we need to decide
17241 now whether the preceding label marks compressed code. We do not
17242 support changing the compression mode of a label after a .stab*
17243 directive, such as in:
17249 so the current mode wins. */
17252 s_mips_stab (int type)
17254 mips_mark_labels ();
17258 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17261 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17268 name = input_line_pointer;
17269 c = get_symbol_end ();
17270 symbolP = symbol_find_or_make (name);
17271 S_SET_WEAK (symbolP);
17272 *input_line_pointer = c;
17274 SKIP_WHITESPACE ();
17276 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17278 if (S_IS_DEFINED (symbolP))
17280 as_bad (_("ignoring attempt to redefine symbol %s"),
17281 S_GET_NAME (symbolP));
17282 ignore_rest_of_line ();
17286 if (*input_line_pointer == ',')
17288 ++input_line_pointer;
17289 SKIP_WHITESPACE ();
17293 if (exp.X_op != O_symbol)
17295 as_bad (_("bad .weakext directive"));
17296 ignore_rest_of_line ();
17299 symbol_set_value_expression (symbolP, &exp);
17302 demand_empty_rest_of_line ();
17305 /* Parse a register string into a number. Called from the ECOFF code
17306 to parse .frame. The argument is non-zero if this is the frame
17307 register, so that we can record it in mips_frame_reg. */
17310 tc_get_register (int frame)
17314 SKIP_WHITESPACE ();
17315 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17319 mips_frame_reg = reg != 0 ? reg : SP;
17320 mips_frame_reg_valid = 1;
17321 mips_cprestore_valid = 0;
17327 md_section_align (asection *seg, valueT addr)
17329 int align = bfd_get_section_alignment (stdoutput, seg);
17333 /* We don't need to align ELF sections to the full alignment.
17334 However, Irix 5 may prefer that we align them at least to a 16
17335 byte boundary. We don't bother to align the sections if we
17336 are targeted for an embedded system. */
17337 if (strncmp (TARGET_OS, "elf", 3) == 0)
17343 return ((addr + (1 << align) - 1) & (-1 << align));
17346 /* Utility routine, called from above as well. If called while the
17347 input file is still being read, it's only an approximation. (For
17348 example, a symbol may later become defined which appeared to be
17349 undefined earlier.) */
17352 nopic_need_relax (symbolS *sym, int before_relaxing)
17357 if (g_switch_value > 0)
17359 const char *symname;
17362 /* Find out whether this symbol can be referenced off the $gp
17363 register. It can be if it is smaller than the -G size or if
17364 it is in the .sdata or .sbss section. Certain symbols can
17365 not be referenced off the $gp, although it appears as though
17367 symname = S_GET_NAME (sym);
17368 if (symname != (const char *) NULL
17369 && (strcmp (symname, "eprol") == 0
17370 || strcmp (symname, "etext") == 0
17371 || strcmp (symname, "_gp") == 0
17372 || strcmp (symname, "edata") == 0
17373 || strcmp (symname, "_fbss") == 0
17374 || strcmp (symname, "_fdata") == 0
17375 || strcmp (symname, "_ftext") == 0
17376 || strcmp (symname, "end") == 0
17377 || strcmp (symname, "_gp_disp") == 0))
17379 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17381 #ifndef NO_ECOFF_DEBUGGING
17382 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17383 && (symbol_get_obj (sym)->ecoff_extern_size
17384 <= g_switch_value))
17386 /* We must defer this decision until after the whole
17387 file has been read, since there might be a .extern
17388 after the first use of this symbol. */
17389 || (before_relaxing
17390 #ifndef NO_ECOFF_DEBUGGING
17391 && symbol_get_obj (sym)->ecoff_extern_size == 0
17393 && S_GET_VALUE (sym) == 0)
17394 || (S_GET_VALUE (sym) != 0
17395 && S_GET_VALUE (sym) <= g_switch_value)))
17399 const char *segname;
17401 segname = segment_name (S_GET_SEGMENT (sym));
17402 gas_assert (strcmp (segname, ".lit8") != 0
17403 && strcmp (segname, ".lit4") != 0);
17404 change = (strcmp (segname, ".sdata") != 0
17405 && strcmp (segname, ".sbss") != 0
17406 && strncmp (segname, ".sdata.", 7) != 0
17407 && strncmp (segname, ".sbss.", 6) != 0
17408 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17409 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17414 /* We are not optimizing for the $gp register. */
17419 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17422 pic_need_relax (symbolS *sym, asection *segtype)
17426 /* Handle the case of a symbol equated to another symbol. */
17427 while (symbol_equated_reloc_p (sym))
17431 /* It's possible to get a loop here in a badly written program. */
17432 n = symbol_get_value_expression (sym)->X_add_symbol;
17438 if (symbol_section_p (sym))
17441 symsec = S_GET_SEGMENT (sym);
17443 /* This must duplicate the test in adjust_reloc_syms. */
17444 return (!bfd_is_und_section (symsec)
17445 && !bfd_is_abs_section (symsec)
17446 && !bfd_is_com_section (symsec)
17447 && !s_is_linkonce (sym, segtype)
17449 /* A global or weak symbol is treated as external. */
17450 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17456 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17457 extended opcode. SEC is the section the frag is in. */
17460 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17463 const struct mips16_immed_operand *op;
17465 int mintiny, maxtiny;
17469 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17471 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17474 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17475 op = mips16_immed_operands;
17476 while (op->type != type)
17479 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17484 if (type == '<' || type == '>' || type == '[' || type == ']')
17487 maxtiny = 1 << op->nbits;
17492 maxtiny = (1 << op->nbits) - 1;
17497 mintiny = - (1 << (op->nbits - 1));
17498 maxtiny = (1 << (op->nbits - 1)) - 1;
17501 sym_frag = symbol_get_frag (fragp->fr_symbol);
17502 val = S_GET_VALUE (fragp->fr_symbol);
17503 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17509 /* We won't have the section when we are called from
17510 mips_relax_frag. However, we will always have been called
17511 from md_estimate_size_before_relax first. If this is a
17512 branch to a different section, we mark it as such. If SEC is
17513 NULL, and the frag is not marked, then it must be a branch to
17514 the same section. */
17517 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17522 /* Must have been called from md_estimate_size_before_relax. */
17525 fragp->fr_subtype =
17526 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17528 /* FIXME: We should support this, and let the linker
17529 catch branches and loads that are out of range. */
17530 as_bad_where (fragp->fr_file, fragp->fr_line,
17531 _("unsupported PC relative reference to different section"));
17535 if (fragp != sym_frag && sym_frag->fr_address == 0)
17536 /* Assume non-extended on the first relaxation pass.
17537 The address we have calculated will be bogus if this is
17538 a forward branch to another frag, as the forward frag
17539 will have fr_address == 0. */
17543 /* In this case, we know for sure that the symbol fragment is in
17544 the same section. If the relax_marker of the symbol fragment
17545 differs from the relax_marker of this fragment, we have not
17546 yet adjusted the symbol fragment fr_address. We want to add
17547 in STRETCH in order to get a better estimate of the address.
17548 This particularly matters because of the shift bits. */
17550 && sym_frag->relax_marker != fragp->relax_marker)
17554 /* Adjust stretch for any alignment frag. Note that if have
17555 been expanding the earlier code, the symbol may be
17556 defined in what appears to be an earlier frag. FIXME:
17557 This doesn't handle the fr_subtype field, which specifies
17558 a maximum number of bytes to skip when doing an
17560 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17562 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17565 stretch = - ((- stretch)
17566 & ~ ((1 << (int) f->fr_offset) - 1));
17568 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17577 addr = fragp->fr_address + fragp->fr_fix;
17579 /* The base address rules are complicated. The base address of
17580 a branch is the following instruction. The base address of a
17581 PC relative load or add is the instruction itself, but if it
17582 is in a delay slot (in which case it can not be extended) use
17583 the address of the instruction whose delay slot it is in. */
17584 if (type == 'p' || type == 'q')
17588 /* If we are currently assuming that this frag should be
17589 extended, then, the current address is two bytes
17591 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17594 /* Ignore the low bit in the target, since it will be set
17595 for a text label. */
17596 if ((val & 1) != 0)
17599 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17601 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17604 val -= addr & ~ ((1 << op->shift) - 1);
17606 /* Branch offsets have an implicit 0 in the lowest bit. */
17607 if (type == 'p' || type == 'q')
17610 /* If any of the shifted bits are set, we must use an extended
17611 opcode. If the address depends on the size of this
17612 instruction, this can lead to a loop, so we arrange to always
17613 use an extended opcode. We only check this when we are in
17614 the main relaxation loop, when SEC is NULL. */
17615 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17617 fragp->fr_subtype =
17618 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17622 /* If we are about to mark a frag as extended because the value
17623 is precisely maxtiny + 1, then there is a chance of an
17624 infinite loop as in the following code:
17629 In this case when the la is extended, foo is 0x3fc bytes
17630 away, so the la can be shrunk, but then foo is 0x400 away, so
17631 the la must be extended. To avoid this loop, we mark the
17632 frag as extended if it was small, and is about to become
17633 extended with a value of maxtiny + 1. */
17634 if (val == ((maxtiny + 1) << op->shift)
17635 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17638 fragp->fr_subtype =
17639 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17643 else if (symsec != absolute_section && sec != NULL)
17644 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17646 if ((val & ((1 << op->shift) - 1)) != 0
17647 || val < (mintiny << op->shift)
17648 || val > (maxtiny << op->shift))
17654 /* Compute the length of a branch sequence, and adjust the
17655 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17656 worst-case length is computed, with UPDATE being used to indicate
17657 whether an unconditional (-1), branch-likely (+1) or regular (0)
17658 branch is to be computed. */
17660 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17662 bfd_boolean toofar;
17666 && S_IS_DEFINED (fragp->fr_symbol)
17667 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17672 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17674 addr = fragp->fr_address + fragp->fr_fix + 4;
17678 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17681 /* If the symbol is not defined or it's in a different segment,
17682 assume the user knows what's going on and emit a short
17688 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17690 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17691 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17692 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17693 RELAX_BRANCH_LINK (fragp->fr_subtype),
17699 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17702 if (mips_pic != NO_PIC)
17704 /* Additional space for PIC loading of target address. */
17706 if (mips_opts.isa == ISA_MIPS1)
17707 /* Additional space for $at-stabilizing nop. */
17711 /* If branch is conditional. */
17712 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17719 /* Compute the length of a branch sequence, and adjust the
17720 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17721 worst-case length is computed, with UPDATE being used to indicate
17722 whether an unconditional (-1), or regular (0) branch is to be
17726 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17728 bfd_boolean toofar;
17732 && S_IS_DEFINED (fragp->fr_symbol)
17733 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17738 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17739 /* Ignore the low bit in the target, since it will be set
17740 for a text label. */
17741 if ((val & 1) != 0)
17744 addr = fragp->fr_address + fragp->fr_fix + 4;
17748 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17751 /* If the symbol is not defined or it's in a different segment,
17752 assume the user knows what's going on and emit a short
17758 if (fragp && update
17759 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17760 fragp->fr_subtype = (toofar
17761 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17762 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17767 bfd_boolean compact_known = fragp != NULL;
17768 bfd_boolean compact = FALSE;
17769 bfd_boolean uncond;
17772 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17774 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17776 uncond = update < 0;
17778 /* If label is out of range, we turn branch <br>:
17780 <br> label # 4 bytes
17786 nop # 2 bytes if compact && !PIC
17789 if (mips_pic == NO_PIC && (!compact_known || compact))
17792 /* If assembling PIC code, we further turn:
17798 lw/ld at, %got(label)(gp) # 4 bytes
17799 d/addiu at, %lo(label) # 4 bytes
17802 if (mips_pic != NO_PIC)
17805 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17807 <brneg> 0f # 4 bytes
17808 nop # 2 bytes if !compact
17811 length += (compact_known && compact) ? 4 : 6;
17817 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17818 bit accordingly. */
17821 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17823 bfd_boolean toofar;
17826 && S_IS_DEFINED (fragp->fr_symbol)
17827 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17833 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17834 /* Ignore the low bit in the target, since it will be set
17835 for a text label. */
17836 if ((val & 1) != 0)
17839 /* Assume this is a 2-byte branch. */
17840 addr = fragp->fr_address + fragp->fr_fix + 2;
17842 /* We try to avoid the infinite loop by not adding 2 more bytes for
17847 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17849 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17850 else if (type == 'E')
17851 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17856 /* If the symbol is not defined or it's in a different segment,
17857 we emit a normal 32-bit branch. */
17860 if (fragp && update
17861 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17863 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17864 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17872 /* Estimate the size of a frag before relaxing. Unless this is the
17873 mips16, we are not really relaxing here, and the final size is
17874 encoded in the subtype information. For the mips16, we have to
17875 decide whether we are using an extended opcode or not. */
17878 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17882 if (RELAX_BRANCH_P (fragp->fr_subtype))
17885 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17887 return fragp->fr_var;
17890 if (RELAX_MIPS16_P (fragp->fr_subtype))
17891 /* We don't want to modify the EXTENDED bit here; it might get us
17892 into infinite loops. We change it only in mips_relax_frag(). */
17893 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17895 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17899 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17900 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17901 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17902 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17903 fragp->fr_var = length;
17908 if (mips_pic == NO_PIC)
17909 change = nopic_need_relax (fragp->fr_symbol, 0);
17910 else if (mips_pic == SVR4_PIC)
17911 change = pic_need_relax (fragp->fr_symbol, segtype);
17912 else if (mips_pic == VXWORKS_PIC)
17913 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17920 fragp->fr_subtype |= RELAX_USE_SECOND;
17921 return -RELAX_FIRST (fragp->fr_subtype);
17924 return -RELAX_SECOND (fragp->fr_subtype);
17927 /* This is called to see whether a reloc against a defined symbol
17928 should be converted into a reloc against a section. */
17931 mips_fix_adjustable (fixS *fixp)
17933 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17934 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17937 if (fixp->fx_addsy == NULL)
17940 /* If symbol SYM is in a mergeable section, relocations of the form
17941 SYM + 0 can usually be made section-relative. The mergeable data
17942 is then identified by the section offset rather than by the symbol.
17944 However, if we're generating REL LO16 relocations, the offset is split
17945 between the LO16 and parterning high part relocation. The linker will
17946 need to recalculate the complete offset in order to correctly identify
17949 The linker has traditionally not looked for the parterning high part
17950 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17951 placed anywhere. Rather than break backwards compatibility by changing
17952 this, it seems better not to force the issue, and instead keep the
17953 original symbol. This will work with either linker behavior. */
17954 if ((lo16_reloc_p (fixp->fx_r_type)
17955 || reloc_needs_lo_p (fixp->fx_r_type))
17956 && HAVE_IN_PLACE_ADDENDS
17957 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17960 /* There is no place to store an in-place offset for JALR relocations.
17961 Likewise an in-range offset of limited PC-relative relocations may
17962 overflow the in-place relocatable field if recalculated against the
17963 start address of the symbol's containing section. */
17964 if (HAVE_IN_PLACE_ADDENDS
17965 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17966 || jalr_reloc_p (fixp->fx_r_type)))
17970 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17971 to a floating-point stub. The same is true for non-R_MIPS16_26
17972 relocations against MIPS16 functions; in this case, the stub becomes
17973 the function's canonical address.
17975 Floating-point stubs are stored in unique .mips16.call.* or
17976 .mips16.fn.* sections. If a stub T for function F is in section S,
17977 the first relocation in section S must be against F; this is how the
17978 linker determines the target function. All relocations that might
17979 resolve to T must also be against F. We therefore have the following
17980 restrictions, which are given in an intentionally-redundant way:
17982 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17985 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17986 if that stub might be used.
17988 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17991 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17992 that stub might be used.
17994 There is a further restriction:
17996 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17997 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17998 targets with in-place addends; the relocation field cannot
17999 encode the low bit.
18001 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18002 against a MIPS16 symbol. We deal with (5) by by not reducing any
18003 such relocations on REL targets.
18005 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18006 relocation against some symbol R, no relocation against R may be
18007 reduced. (Note that this deals with (2) as well as (1) because
18008 relocations against global symbols will never be reduced on ELF
18009 targets.) This approach is a little simpler than trying to detect
18010 stub sections, and gives the "all or nothing" per-symbol consistency
18011 that we have for MIPS16 symbols. */
18013 && fixp->fx_subsy == NULL
18014 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18015 || *symbol_get_tc (fixp->fx_addsy)
18016 || (HAVE_IN_PLACE_ADDENDS
18017 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18018 && jmp_reloc_p (fixp->fx_r_type))))
18025 /* Translate internal representation of relocation info to BFD target
18029 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18031 static arelent *retval[4];
18033 bfd_reloc_code_real_type code;
18035 memset (retval, 0, sizeof(retval));
18036 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
18037 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
18038 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18039 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18041 if (fixp->fx_pcrel)
18043 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18044 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18045 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18046 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18047 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
18049 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18050 Relocations want only the symbol offset. */
18051 reloc->addend = fixp->fx_addnumber + reloc->address;
18054 /* A gruesome hack which is a result of the gruesome gas
18055 reloc handling. What's worse, for COFF (as opposed to
18056 ECOFF), we might need yet another copy of reloc->address.
18057 See bfd_install_relocation. */
18058 reloc->addend += reloc->address;
18062 reloc->addend = fixp->fx_addnumber;
18064 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18065 entry to be used in the relocation's section offset. */
18066 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18068 reloc->address = reloc->addend;
18072 code = fixp->fx_r_type;
18074 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18075 if (reloc->howto == NULL)
18077 as_bad_where (fixp->fx_file, fixp->fx_line,
18078 _("Can not represent %s relocation in this object file format"),
18079 bfd_get_reloc_code_name (code));
18086 /* Relax a machine dependent frag. This returns the amount by which
18087 the current size of the frag should change. */
18090 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18092 if (RELAX_BRANCH_P (fragp->fr_subtype))
18094 offsetT old_var = fragp->fr_var;
18096 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18098 return fragp->fr_var - old_var;
18101 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18103 offsetT old_var = fragp->fr_var;
18104 offsetT new_var = 4;
18106 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18107 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18108 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18109 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18110 fragp->fr_var = new_var;
18112 return new_var - old_var;
18115 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18118 if (mips16_extended_frag (fragp, NULL, stretch))
18120 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18122 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18127 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18129 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18136 /* Convert a machine dependent frag. */
18139 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18141 if (RELAX_BRANCH_P (fragp->fr_subtype))
18144 unsigned long insn;
18148 buf = fragp->fr_literal + fragp->fr_fix;
18149 insn = read_insn (buf);
18151 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18153 /* We generate a fixup instead of applying it right now
18154 because, if there are linker relaxations, we're going to
18155 need the relocations. */
18156 exp.X_op = O_symbol;
18157 exp.X_add_symbol = fragp->fr_symbol;
18158 exp.X_add_number = fragp->fr_offset;
18160 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18161 BFD_RELOC_16_PCREL_S2);
18162 fixp->fx_file = fragp->fr_file;
18163 fixp->fx_line = fragp->fr_line;
18165 buf = write_insn (buf, insn);
18171 as_warn_where (fragp->fr_file, fragp->fr_line,
18172 _("Relaxed out-of-range branch into a jump"));
18174 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18177 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18179 /* Reverse the branch. */
18180 switch ((insn >> 28) & 0xf)
18183 /* bc[0-3][tf]l? instructions can have the condition
18184 reversed by tweaking a single TF bit, and their
18185 opcodes all have 0x4???????. */
18186 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18187 insn ^= 0x00010000;
18191 /* bltz 0x04000000 bgez 0x04010000
18192 bltzal 0x04100000 bgezal 0x04110000 */
18193 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18194 insn ^= 0x00010000;
18198 /* beq 0x10000000 bne 0x14000000
18199 blez 0x18000000 bgtz 0x1c000000 */
18200 insn ^= 0x04000000;
18208 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18210 /* Clear the and-link bit. */
18211 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18213 /* bltzal 0x04100000 bgezal 0x04110000
18214 bltzall 0x04120000 bgezall 0x04130000 */
18215 insn &= ~0x00100000;
18218 /* Branch over the branch (if the branch was likely) or the
18219 full jump (not likely case). Compute the offset from the
18220 current instruction to branch to. */
18221 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18225 /* How many bytes in instructions we've already emitted? */
18226 i = buf - fragp->fr_literal - fragp->fr_fix;
18227 /* How many bytes in instructions from here to the end? */
18228 i = fragp->fr_var - i;
18230 /* Convert to instruction count. */
18232 /* Branch counts from the next instruction. */
18235 /* Branch over the jump. */
18236 buf = write_insn (buf, insn);
18239 buf = write_insn (buf, 0);
18241 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18243 /* beql $0, $0, 2f */
18245 /* Compute the PC offset from the current instruction to
18246 the end of the variable frag. */
18247 /* How many bytes in instructions we've already emitted? */
18248 i = buf - fragp->fr_literal - fragp->fr_fix;
18249 /* How many bytes in instructions from here to the end? */
18250 i = fragp->fr_var - i;
18251 /* Convert to instruction count. */
18253 /* Don't decrement i, because we want to branch over the
18257 buf = write_insn (buf, insn);
18258 buf = write_insn (buf, 0);
18262 if (mips_pic == NO_PIC)
18265 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18266 ? 0x0c000000 : 0x08000000);
18267 exp.X_op = O_symbol;
18268 exp.X_add_symbol = fragp->fr_symbol;
18269 exp.X_add_number = fragp->fr_offset;
18271 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18272 FALSE, BFD_RELOC_MIPS_JMP);
18273 fixp->fx_file = fragp->fr_file;
18274 fixp->fx_line = fragp->fr_line;
18276 buf = write_insn (buf, insn);
18280 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18282 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18283 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18284 insn |= at << OP_SH_RT;
18285 exp.X_op = O_symbol;
18286 exp.X_add_symbol = fragp->fr_symbol;
18287 exp.X_add_number = fragp->fr_offset;
18289 if (fragp->fr_offset)
18291 exp.X_add_symbol = make_expr_symbol (&exp);
18292 exp.X_add_number = 0;
18295 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18296 FALSE, BFD_RELOC_MIPS_GOT16);
18297 fixp->fx_file = fragp->fr_file;
18298 fixp->fx_line = fragp->fr_line;
18300 buf = write_insn (buf, insn);
18302 if (mips_opts.isa == ISA_MIPS1)
18304 buf = write_insn (buf, 0);
18306 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18307 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18308 insn |= at << OP_SH_RS | at << OP_SH_RT;
18310 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18311 FALSE, BFD_RELOC_LO16);
18312 fixp->fx_file = fragp->fr_file;
18313 fixp->fx_line = fragp->fr_line;
18315 buf = write_insn (buf, insn);
18318 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18322 insn |= at << OP_SH_RS;
18324 buf = write_insn (buf, insn);
18328 fragp->fr_fix += fragp->fr_var;
18329 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18333 /* Relax microMIPS branches. */
18334 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18336 char *buf = fragp->fr_literal + fragp->fr_fix;
18337 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18338 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18339 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18340 bfd_boolean short_ds;
18341 unsigned long insn;
18345 exp.X_op = O_symbol;
18346 exp.X_add_symbol = fragp->fr_symbol;
18347 exp.X_add_number = fragp->fr_offset;
18349 fragp->fr_fix += fragp->fr_var;
18351 /* Handle 16-bit branches that fit or are forced to fit. */
18352 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18354 /* We generate a fixup instead of applying it right now,
18355 because if there is linker relaxation, we're going to
18356 need the relocations. */
18358 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18359 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18360 else if (type == 'E')
18361 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18362 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18366 fixp->fx_file = fragp->fr_file;
18367 fixp->fx_line = fragp->fr_line;
18369 /* These relocations can have an addend that won't fit in
18371 fixp->fx_no_overflow = 1;
18376 /* Handle 32-bit branches that fit or are forced to fit. */
18377 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18378 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18380 /* We generate a fixup instead of applying it right now,
18381 because if there is linker relaxation, we're going to
18382 need the relocations. */
18383 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18384 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18385 fixp->fx_file = fragp->fr_file;
18386 fixp->fx_line = fragp->fr_line;
18392 /* Relax 16-bit branches to 32-bit branches. */
18395 insn = read_compressed_insn (buf, 2);
18397 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18398 insn = 0x94000000; /* beq */
18399 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18401 unsigned long regno;
18403 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18404 regno = micromips_to_32_reg_d_map [regno];
18405 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18406 insn |= regno << MICROMIPSOP_SH_RS;
18411 /* Nothing else to do, just write it out. */
18412 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18413 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18415 buf = write_compressed_insn (buf, insn, 4);
18416 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18421 insn = read_compressed_insn (buf, 4);
18423 /* Relax 32-bit branches to a sequence of instructions. */
18424 as_warn_where (fragp->fr_file, fragp->fr_line,
18425 _("Relaxed out-of-range branch into a jump"));
18427 /* Set the short-delay-slot bit. */
18428 short_ds = al && (insn & 0x02000000) != 0;
18430 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18434 /* Reverse the branch. */
18435 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18436 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18437 insn ^= 0x20000000;
18438 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18439 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18440 || (insn & 0xffe00000) == 0x40800000 /* blez */
18441 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18442 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18443 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18444 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18445 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18446 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18447 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18448 insn ^= 0x00400000;
18449 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18450 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18451 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18452 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18453 insn ^= 0x00200000;
18459 /* Clear the and-link and short-delay-slot bits. */
18460 gas_assert ((insn & 0xfda00000) == 0x40200000);
18462 /* bltzal 0x40200000 bgezal 0x40600000 */
18463 /* bltzals 0x42200000 bgezals 0x42600000 */
18464 insn &= ~0x02200000;
18467 /* Make a label at the end for use with the branch. */
18468 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18469 micromips_label_inc ();
18470 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18472 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18476 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18477 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18478 fixp->fx_file = fragp->fr_file;
18479 fixp->fx_line = fragp->fr_line;
18481 /* Branch over the jump. */
18482 buf = write_compressed_insn (buf, insn, 4);
18485 buf = write_compressed_insn (buf, 0x0c00, 2);
18488 if (mips_pic == NO_PIC)
18490 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18492 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18493 insn = al ? jal : 0xd4000000;
18495 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18496 BFD_RELOC_MICROMIPS_JMP);
18497 fixp->fx_file = fragp->fr_file;
18498 fixp->fx_line = fragp->fr_line;
18500 buf = write_compressed_insn (buf, insn, 4);
18503 buf = write_compressed_insn (buf, 0x0c00, 2);
18507 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18508 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18509 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18511 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18512 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18513 insn |= at << MICROMIPSOP_SH_RT;
18515 if (exp.X_add_number)
18517 exp.X_add_symbol = make_expr_symbol (&exp);
18518 exp.X_add_number = 0;
18521 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18522 BFD_RELOC_MICROMIPS_GOT16);
18523 fixp->fx_file = fragp->fr_file;
18524 fixp->fx_line = fragp->fr_line;
18526 buf = write_compressed_insn (buf, insn, 4);
18528 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18529 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18530 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18532 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18533 BFD_RELOC_MICROMIPS_LO16);
18534 fixp->fx_file = fragp->fr_file;
18535 fixp->fx_line = fragp->fr_line;
18537 buf = write_compressed_insn (buf, insn, 4);
18539 /* jr/jrc/jalr/jalrs $at */
18540 insn = al ? jalr : jr;
18541 insn |= at << MICROMIPSOP_SH_MJ;
18543 buf = write_compressed_insn (buf, insn, 2);
18546 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18550 if (RELAX_MIPS16_P (fragp->fr_subtype))
18553 const struct mips16_immed_operand *op;
18556 unsigned int user_length, length;
18557 unsigned long insn;
18560 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18561 op = mips16_immed_operands;
18562 while (op->type != type)
18565 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18566 val = resolve_symbol_value (fragp->fr_symbol);
18571 addr = fragp->fr_address + fragp->fr_fix;
18573 /* The rules for the base address of a PC relative reloc are
18574 complicated; see mips16_extended_frag. */
18575 if (type == 'p' || type == 'q')
18580 /* Ignore the low bit in the target, since it will be
18581 set for a text label. */
18582 if ((val & 1) != 0)
18585 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18587 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18590 addr &= ~ (addressT) ((1 << op->shift) - 1);
18593 /* Make sure the section winds up with the alignment we have
18596 record_alignment (asec, op->shift);
18600 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18601 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18602 as_warn_where (fragp->fr_file, fragp->fr_line,
18603 _("extended instruction in delay slot"));
18605 buf = fragp->fr_literal + fragp->fr_fix;
18607 insn = read_compressed_insn (buf, 2);
18609 insn |= MIPS16_EXTEND;
18611 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18613 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18618 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18619 BFD_RELOC_UNUSED, val, user_length, &insn);
18621 length = (ext ? 4 : 2);
18622 gas_assert (mips16_opcode_length (insn) == length);
18623 write_compressed_insn (buf, insn, length);
18624 fragp->fr_fix += length;
18628 relax_substateT subtype = fragp->fr_subtype;
18629 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18630 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18634 first = RELAX_FIRST (subtype);
18635 second = RELAX_SECOND (subtype);
18636 fixp = (fixS *) fragp->fr_opcode;
18638 /* If the delay slot chosen does not match the size of the instruction,
18639 then emit a warning. */
18640 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18641 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18646 s = subtype & (RELAX_DELAY_SLOT_16BIT
18647 | RELAX_DELAY_SLOT_SIZE_FIRST
18648 | RELAX_DELAY_SLOT_SIZE_SECOND);
18649 msg = macro_warning (s);
18651 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18655 /* Possibly emit a warning if we've chosen the longer option. */
18656 if (use_second == second_longer)
18662 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18663 msg = macro_warning (s);
18665 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18669 /* Go through all the fixups for the first sequence. Disable them
18670 (by marking them as done) if we're going to use the second
18671 sequence instead. */
18673 && fixp->fx_frag == fragp
18674 && fixp->fx_where < fragp->fr_fix - second)
18676 if (subtype & RELAX_USE_SECOND)
18678 fixp = fixp->fx_next;
18681 /* Go through the fixups for the second sequence. Disable them if
18682 we're going to use the first sequence, otherwise adjust their
18683 addresses to account for the relaxation. */
18684 while (fixp && fixp->fx_frag == fragp)
18686 if (subtype & RELAX_USE_SECOND)
18687 fixp->fx_where -= first;
18690 fixp = fixp->fx_next;
18693 /* Now modify the frag contents. */
18694 if (subtype & RELAX_USE_SECOND)
18698 start = fragp->fr_literal + fragp->fr_fix - first - second;
18699 memmove (start, start + first, second);
18700 fragp->fr_fix -= first;
18703 fragp->fr_fix -= second;
18709 /* This function is called after the relocs have been generated.
18710 We've been storing mips16 text labels as odd. Here we convert them
18711 back to even for the convenience of the debugger. */
18714 mips_frob_file_after_relocs (void)
18717 unsigned int count, i;
18722 syms = bfd_get_outsymbols (stdoutput);
18723 count = bfd_get_symcount (stdoutput);
18724 for (i = 0; i < count; i++, syms++)
18725 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18726 && ((*syms)->value & 1) != 0)
18728 (*syms)->value &= ~1;
18729 /* If the symbol has an odd size, it was probably computed
18730 incorrectly, so adjust that as well. */
18731 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18732 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18738 /* This function is called whenever a label is defined, including fake
18739 labels instantiated off the dot special symbol. It is used when
18740 handling branch delays; if a branch has a label, we assume we cannot
18741 move it. This also bumps the value of the symbol by 1 in compressed
18745 mips_record_label (symbolS *sym)
18747 segment_info_type *si = seg_info (now_seg);
18748 struct insn_label_list *l;
18750 if (free_insn_labels == NULL)
18751 l = (struct insn_label_list *) xmalloc (sizeof *l);
18754 l = free_insn_labels;
18755 free_insn_labels = l->next;
18759 l->next = si->label_list;
18760 si->label_list = l;
18763 /* This function is called as tc_frob_label() whenever a label is defined
18764 and adds a DWARF-2 record we only want for true labels. */
18767 mips_define_label (symbolS *sym)
18769 mips_record_label (sym);
18771 dwarf2_emit_label (sym);
18775 /* This function is called by tc_new_dot_label whenever a new dot symbol
18779 mips_add_dot_label (symbolS *sym)
18781 mips_record_label (sym);
18782 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18783 mips_compressed_mark_label (sym);
18786 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18788 /* Some special processing for a MIPS ELF file. */
18791 mips_elf_final_processing (void)
18793 /* Write out the register information. */
18794 if (mips_abi != N64_ABI)
18798 s.ri_gprmask = mips_gprmask;
18799 s.ri_cprmask[0] = mips_cprmask[0];
18800 s.ri_cprmask[1] = mips_cprmask[1];
18801 s.ri_cprmask[2] = mips_cprmask[2];
18802 s.ri_cprmask[3] = mips_cprmask[3];
18803 /* The gp_value field is set by the MIPS ELF backend. */
18805 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18806 ((Elf32_External_RegInfo *)
18807 mips_regmask_frag));
18811 Elf64_Internal_RegInfo s;
18813 s.ri_gprmask = mips_gprmask;
18815 s.ri_cprmask[0] = mips_cprmask[0];
18816 s.ri_cprmask[1] = mips_cprmask[1];
18817 s.ri_cprmask[2] = mips_cprmask[2];
18818 s.ri_cprmask[3] = mips_cprmask[3];
18819 /* The gp_value field is set by the MIPS ELF backend. */
18821 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18822 ((Elf64_External_RegInfo *)
18823 mips_regmask_frag));
18826 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18827 sort of BFD interface for this. */
18828 if (mips_any_noreorder)
18829 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18830 if (mips_pic != NO_PIC)
18832 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18833 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18836 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18838 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18839 defined at present; this might need to change in future. */
18840 if (file_ase_mips16)
18841 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18842 if (file_ase_micromips)
18843 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18844 #if 0 /* XXX FIXME */
18845 if (file_ase_mips3d)
18846 elf_elfheader (stdoutput)->e_flags |= ???;
18849 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18851 /* Set the MIPS ELF ABI flags. */
18852 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18853 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18854 else if (mips_abi == O64_ABI)
18855 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18856 else if (mips_abi == EABI_ABI)
18858 if (!file_mips_gp32)
18859 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18861 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18863 else if (mips_abi == N32_ABI)
18864 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18866 /* Nothing to do for N64_ABI. */
18868 if (mips_32bitmode)
18869 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18871 #if 0 /* XXX FIXME */
18872 /* 32 bit code with 64 bit FP registers. */
18873 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18874 elf_elfheader (stdoutput)->e_flags |= ???;
18878 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18880 typedef struct proc {
18882 symbolS *func_end_sym;
18883 unsigned long reg_mask;
18884 unsigned long reg_offset;
18885 unsigned long fpreg_mask;
18886 unsigned long fpreg_offset;
18887 unsigned long frame_offset;
18888 unsigned long frame_reg;
18889 unsigned long pc_reg;
18892 static procS cur_proc;
18893 static procS *cur_proc_ptr;
18894 static int numprocs;
18896 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18897 as "2", and a normal nop as "0". */
18899 #define NOP_OPCODE_MIPS 0
18900 #define NOP_OPCODE_MIPS16 1
18901 #define NOP_OPCODE_MICROMIPS 2
18904 mips_nop_opcode (void)
18906 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18907 return NOP_OPCODE_MICROMIPS;
18908 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18909 return NOP_OPCODE_MIPS16;
18911 return NOP_OPCODE_MIPS;
18914 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18915 32-bit microMIPS NOPs here (if applicable). */
18918 mips_handle_align (fragS *fragp)
18922 int bytes, size, excess;
18925 if (fragp->fr_type != rs_align_code)
18928 p = fragp->fr_literal + fragp->fr_fix;
18930 switch (nop_opcode)
18932 case NOP_OPCODE_MICROMIPS:
18933 opcode = micromips_nop32_insn.insn_opcode;
18936 case NOP_OPCODE_MIPS16:
18937 opcode = mips16_nop_insn.insn_opcode;
18940 case NOP_OPCODE_MIPS:
18942 opcode = nop_insn.insn_opcode;
18947 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18948 excess = bytes % size;
18950 /* Handle the leading part if we're not inserting a whole number of
18951 instructions, and make it the end of the fixed part of the frag.
18952 Try to fit in a short microMIPS NOP if applicable and possible,
18953 and use zeroes otherwise. */
18954 gas_assert (excess < 4);
18955 fragp->fr_fix += excess;
18960 /* Fall through. */
18962 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18964 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18968 /* Fall through. */
18971 /* Fall through. */
18976 md_number_to_chars (p, opcode, size);
18977 fragp->fr_var = size;
18981 md_obj_begin (void)
18988 /* Check for premature end, nesting errors, etc. */
18990 as_warn (_("missing .end at end of assembly"));
18999 if (*input_line_pointer == '-')
19001 ++input_line_pointer;
19004 if (!ISDIGIT (*input_line_pointer))
19005 as_bad (_("expected simple number"));
19006 if (input_line_pointer[0] == '0')
19008 if (input_line_pointer[1] == 'x')
19010 input_line_pointer += 2;
19011 while (ISXDIGIT (*input_line_pointer))
19014 val |= hex_value (*input_line_pointer++);
19016 return negative ? -val : val;
19020 ++input_line_pointer;
19021 while (ISDIGIT (*input_line_pointer))
19024 val |= *input_line_pointer++ - '0';
19026 return negative ? -val : val;
19029 if (!ISDIGIT (*input_line_pointer))
19031 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19032 *input_line_pointer, *input_line_pointer);
19033 as_warn (_("invalid number"));
19036 while (ISDIGIT (*input_line_pointer))
19039 val += *input_line_pointer++ - '0';
19041 return negative ? -val : val;
19044 /* The .file directive; just like the usual .file directive, but there
19045 is an initial number which is the ECOFF file index. In the non-ECOFF
19046 case .file implies DWARF-2. */
19049 s_mips_file (int x ATTRIBUTE_UNUSED)
19051 static int first_file_directive = 0;
19053 if (ECOFF_DEBUGGING)
19062 filename = dwarf2_directive_file (0);
19064 /* Versions of GCC up to 3.1 start files with a ".file"
19065 directive even for stabs output. Make sure that this
19066 ".file" is handled. Note that you need a version of GCC
19067 after 3.1 in order to support DWARF-2 on MIPS. */
19068 if (filename != NULL && ! first_file_directive)
19070 (void) new_logical_line (filename, -1);
19071 s_app_file_string (filename, 0);
19073 first_file_directive = 1;
19077 /* The .loc directive, implying DWARF-2. */
19080 s_mips_loc (int x ATTRIBUTE_UNUSED)
19082 if (!ECOFF_DEBUGGING)
19083 dwarf2_directive_loc (0);
19086 /* The .end directive. */
19089 s_mips_end (int x ATTRIBUTE_UNUSED)
19093 /* Following functions need their own .frame and .cprestore directives. */
19094 mips_frame_reg_valid = 0;
19095 mips_cprestore_valid = 0;
19097 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19100 demand_empty_rest_of_line ();
19105 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19106 as_warn (_(".end not in text section"));
19110 as_warn (_(".end directive without a preceding .ent directive."));
19111 demand_empty_rest_of_line ();
19117 gas_assert (S_GET_NAME (p));
19118 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19119 as_warn (_(".end symbol does not match .ent symbol."));
19121 if (debug_type == DEBUG_STABS)
19122 stabs_generate_asm_endfunc (S_GET_NAME (p),
19126 as_warn (_(".end directive missing or unknown symbol"));
19129 /* Create an expression to calculate the size of the function. */
19130 if (p && cur_proc_ptr)
19132 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19133 expressionS *exp = xmalloc (sizeof (expressionS));
19136 exp->X_op = O_subtract;
19137 exp->X_add_symbol = symbol_temp_new_now ();
19138 exp->X_op_symbol = p;
19139 exp->X_add_number = 0;
19141 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19144 /* Generate a .pdr section. */
19145 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
19147 segT saved_seg = now_seg;
19148 subsegT saved_subseg = now_subseg;
19152 #ifdef md_flush_pending_output
19153 md_flush_pending_output ();
19156 gas_assert (pdr_seg);
19157 subseg_set (pdr_seg, 0);
19159 /* Write the symbol. */
19160 exp.X_op = O_symbol;
19161 exp.X_add_symbol = p;
19162 exp.X_add_number = 0;
19163 emit_expr (&exp, 4);
19165 fragp = frag_more (7 * 4);
19167 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19168 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19169 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19170 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19171 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19172 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19173 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19175 subseg_set (saved_seg, saved_subseg);
19177 #endif /* OBJ_ELF */
19179 cur_proc_ptr = NULL;
19182 /* The .aent and .ent directives. */
19185 s_mips_ent (int aent)
19189 symbolP = get_symbol ();
19190 if (*input_line_pointer == ',')
19191 ++input_line_pointer;
19192 SKIP_WHITESPACE ();
19193 if (ISDIGIT (*input_line_pointer)
19194 || *input_line_pointer == '-')
19197 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19198 as_warn (_(".ent or .aent not in text section."));
19200 if (!aent && cur_proc_ptr)
19201 as_warn (_("missing .end"));
19205 /* This function needs its own .frame and .cprestore directives. */
19206 mips_frame_reg_valid = 0;
19207 mips_cprestore_valid = 0;
19209 cur_proc_ptr = &cur_proc;
19210 memset (cur_proc_ptr, '\0', sizeof (procS));
19212 cur_proc_ptr->func_sym = symbolP;
19216 if (debug_type == DEBUG_STABS)
19217 stabs_generate_asm_func (S_GET_NAME (symbolP),
19218 S_GET_NAME (symbolP));
19221 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19223 demand_empty_rest_of_line ();
19226 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19227 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19228 s_mips_frame is used so that we can set the PDR information correctly.
19229 We can't use the ecoff routines because they make reference to the ecoff
19230 symbol table (in the mdebug section). */
19233 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19236 if (IS_ELF && !ECOFF_DEBUGGING)
19240 if (cur_proc_ptr == (procS *) NULL)
19242 as_warn (_(".frame outside of .ent"));
19243 demand_empty_rest_of_line ();
19247 cur_proc_ptr->frame_reg = tc_get_register (1);
19249 SKIP_WHITESPACE ();
19250 if (*input_line_pointer++ != ','
19251 || get_absolute_expression_and_terminator (&val) != ',')
19253 as_warn (_("Bad .frame directive"));
19254 --input_line_pointer;
19255 demand_empty_rest_of_line ();
19259 cur_proc_ptr->frame_offset = val;
19260 cur_proc_ptr->pc_reg = tc_get_register (0);
19262 demand_empty_rest_of_line ();
19265 #endif /* OBJ_ELF */
19269 /* The .fmask and .mask directives. If the mdebug section is present
19270 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19271 embedded targets, s_mips_mask is used so that we can set the PDR
19272 information correctly. We can't use the ecoff routines because they
19273 make reference to the ecoff symbol table (in the mdebug section). */
19276 s_mips_mask (int reg_type)
19279 if (IS_ELF && !ECOFF_DEBUGGING)
19283 if (cur_proc_ptr == (procS *) NULL)
19285 as_warn (_(".mask/.fmask outside of .ent"));
19286 demand_empty_rest_of_line ();
19290 if (get_absolute_expression_and_terminator (&mask) != ',')
19292 as_warn (_("Bad .mask/.fmask directive"));
19293 --input_line_pointer;
19294 demand_empty_rest_of_line ();
19298 off = get_absolute_expression ();
19300 if (reg_type == 'F')
19302 cur_proc_ptr->fpreg_mask = mask;
19303 cur_proc_ptr->fpreg_offset = off;
19307 cur_proc_ptr->reg_mask = mask;
19308 cur_proc_ptr->reg_offset = off;
19311 demand_empty_rest_of_line ();
19314 #endif /* OBJ_ELF */
19315 s_ignore (reg_type);
19318 /* A table describing all the processors gas knows about. Names are
19319 matched in the order listed.
19321 To ease comparison, please keep this table in the same order as
19322 gcc's mips_cpu_info_table[]. */
19323 static const struct mips_cpu_info mips_cpu_info_table[] =
19325 /* Entries for generic ISAs */
19326 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19327 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19328 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19329 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19330 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19331 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19332 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19333 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19334 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19337 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19338 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19339 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19342 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19345 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19346 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19347 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19348 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19349 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19350 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19351 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19352 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19353 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19354 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19355 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19356 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19357 { "r5900", 0, ISA_MIPS3, CPU_R5900 },
19358 /* ST Microelectronics Loongson 2E and 2F cores */
19359 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19360 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19363 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19364 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19365 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19366 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19367 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19368 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19369 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19370 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19371 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19372 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19373 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19374 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19375 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19376 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19377 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19380 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19381 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19382 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19383 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19385 /* MIPS 32 Release 2 */
19386 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19387 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19388 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19389 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19390 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19391 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19392 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19393 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19394 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19395 ISA_MIPS32R2, CPU_MIPS32R2 },
19396 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19397 ISA_MIPS32R2, CPU_MIPS32R2 },
19398 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19399 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19400 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19401 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19402 /* Deprecated forms of the above. */
19403 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19404 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19405 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19406 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19407 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19408 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19409 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19410 /* Deprecated forms of the above. */
19411 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19412 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19413 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19414 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19415 ISA_MIPS32R2, CPU_MIPS32R2 },
19416 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19417 ISA_MIPS32R2, CPU_MIPS32R2 },
19418 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19419 ISA_MIPS32R2, CPU_MIPS32R2 },
19420 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19421 ISA_MIPS32R2, CPU_MIPS32R2 },
19422 /* Deprecated forms of the above. */
19423 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19424 ISA_MIPS32R2, CPU_MIPS32R2 },
19425 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19426 ISA_MIPS32R2, CPU_MIPS32R2 },
19427 /* 34Kn is a 34kc without DSP. */
19428 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19429 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19430 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19431 ISA_MIPS32R2, CPU_MIPS32R2 },
19432 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19433 ISA_MIPS32R2, CPU_MIPS32R2 },
19434 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19435 ISA_MIPS32R2, CPU_MIPS32R2 },
19436 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19437 ISA_MIPS32R2, CPU_MIPS32R2 },
19438 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19439 ISA_MIPS32R2, CPU_MIPS32R2 },
19440 /* Deprecated forms of the above. */
19441 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19442 ISA_MIPS32R2, CPU_MIPS32R2 },
19443 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19444 ISA_MIPS32R2, CPU_MIPS32R2 },
19445 /* 1004K cores are multiprocessor versions of the 34K. */
19446 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19447 ISA_MIPS32R2, CPU_MIPS32R2 },
19448 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19449 ISA_MIPS32R2, CPU_MIPS32R2 },
19450 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19451 ISA_MIPS32R2, CPU_MIPS32R2 },
19452 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19453 ISA_MIPS32R2, CPU_MIPS32R2 },
19456 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19457 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19458 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19459 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19461 /* Broadcom SB-1 CPU core */
19462 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19463 ISA_MIPS64, CPU_SB1 },
19464 /* Broadcom SB-1A CPU core */
19465 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19466 ISA_MIPS64, CPU_SB1 },
19468 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19470 /* MIPS 64 Release 2 */
19472 /* Cavium Networks Octeon CPU core */
19473 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19474 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19475 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19478 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19481 XLP is mostly like XLR, with the prominent exception that it is
19482 MIPS64R2 rather than MIPS64. */
19483 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19490 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19491 with a final "000" replaced by "k". Ignore case.
19493 Note: this function is shared between GCC and GAS. */
19496 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19498 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19499 given++, canonical++;
19501 return ((*given == 0 && *canonical == 0)
19502 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19506 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19507 CPU name. We've traditionally allowed a lot of variation here.
19509 Note: this function is shared between GCC and GAS. */
19512 mips_matching_cpu_name_p (const char *canonical, const char *given)
19514 /* First see if the name matches exactly, or with a final "000"
19515 turned into "k". */
19516 if (mips_strict_matching_cpu_name_p (canonical, given))
19519 /* If not, try comparing based on numerical designation alone.
19520 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19521 if (TOLOWER (*given) == 'r')
19523 if (!ISDIGIT (*given))
19526 /* Skip over some well-known prefixes in the canonical name,
19527 hoping to find a number there too. */
19528 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19530 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19532 else if (TOLOWER (canonical[0]) == 'r')
19535 return mips_strict_matching_cpu_name_p (canonical, given);
19539 /* Parse an option that takes the name of a processor as its argument.
19540 OPTION is the name of the option and CPU_STRING is the argument.
19541 Return the corresponding processor enumeration if the CPU_STRING is
19542 recognized, otherwise report an error and return null.
19544 A similar function exists in GCC. */
19546 static const struct mips_cpu_info *
19547 mips_parse_cpu (const char *option, const char *cpu_string)
19549 const struct mips_cpu_info *p;
19551 /* 'from-abi' selects the most compatible architecture for the given
19552 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19553 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19554 version. Look first at the -mgp options, if given, otherwise base
19555 the choice on MIPS_DEFAULT_64BIT.
19557 Treat NO_ABI like the EABIs. One reason to do this is that the
19558 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19559 architecture. This code picks MIPS I for 'mips' and MIPS III for
19560 'mips64', just as we did in the days before 'from-abi'. */
19561 if (strcasecmp (cpu_string, "from-abi") == 0)
19563 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19564 return mips_cpu_info_from_isa (ISA_MIPS1);
19566 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19567 return mips_cpu_info_from_isa (ISA_MIPS3);
19569 if (file_mips_gp32 >= 0)
19570 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19572 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19577 /* 'default' has traditionally been a no-op. Probably not very useful. */
19578 if (strcasecmp (cpu_string, "default") == 0)
19581 for (p = mips_cpu_info_table; p->name != 0; p++)
19582 if (mips_matching_cpu_name_p (p->name, cpu_string))
19585 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19589 /* Return the canonical processor information for ISA (a member of the
19590 ISA_MIPS* enumeration). */
19592 static const struct mips_cpu_info *
19593 mips_cpu_info_from_isa (int isa)
19597 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19598 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19599 && isa == mips_cpu_info_table[i].isa)
19600 return (&mips_cpu_info_table[i]);
19605 static const struct mips_cpu_info *
19606 mips_cpu_info_from_arch (int arch)
19610 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19611 if (arch == mips_cpu_info_table[i].cpu)
19612 return (&mips_cpu_info_table[i]);
19618 show (FILE *stream, const char *string, int *col_p, int *first_p)
19622 fprintf (stream, "%24s", "");
19627 fprintf (stream, ", ");
19631 if (*col_p + strlen (string) > 72)
19633 fprintf (stream, "\n%24s", "");
19637 fprintf (stream, "%s", string);
19638 *col_p += strlen (string);
19644 md_show_usage (FILE *stream)
19649 fprintf (stream, _("\
19651 -EB generate big endian output\n\
19652 -EL generate little endian output\n\
19653 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19654 -G NUM allow referencing objects up to NUM bytes\n\
19655 implicitly with the gp register [default 8]\n"));
19656 fprintf (stream, _("\
19657 -mips1 generate MIPS ISA I instructions\n\
19658 -mips2 generate MIPS ISA II instructions\n\
19659 -mips3 generate MIPS ISA III instructions\n\
19660 -mips4 generate MIPS ISA IV instructions\n\
19661 -mips5 generate MIPS ISA V instructions\n\
19662 -mips32 generate MIPS32 ISA instructions\n\
19663 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19664 -mips64 generate MIPS64 ISA instructions\n\
19665 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19666 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19670 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19671 show (stream, mips_cpu_info_table[i].name, &column, &first);
19672 show (stream, "from-abi", &column, &first);
19673 fputc ('\n', stream);
19675 fprintf (stream, _("\
19676 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19677 -no-mCPU don't generate code specific to CPU.\n\
19678 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19682 show (stream, "3900", &column, &first);
19683 show (stream, "4010", &column, &first);
19684 show (stream, "4100", &column, &first);
19685 show (stream, "4650", &column, &first);
19686 fputc ('\n', stream);
19688 fprintf (stream, _("\
19689 -mips16 generate mips16 instructions\n\
19690 -no-mips16 do not generate mips16 instructions\n"));
19691 fprintf (stream, _("\
19692 -mmicromips generate microMIPS instructions\n\
19693 -mno-micromips do not generate microMIPS instructions\n"));
19694 fprintf (stream, _("\
19695 -msmartmips generate smartmips instructions\n\
19696 -mno-smartmips do not generate smartmips instructions\n"));
19697 fprintf (stream, _("\
19698 -mdsp generate DSP instructions\n\
19699 -mno-dsp do not generate DSP instructions\n"));
19700 fprintf (stream, _("\
19701 -mdspr2 generate DSP R2 instructions\n\
19702 -mno-dspr2 do not generate DSP R2 instructions\n"));
19703 fprintf (stream, _("\
19704 -mmt generate MT instructions\n\
19705 -mno-mt do not generate MT instructions\n"));
19706 fprintf (stream, _("\
19707 -mmcu generate MCU instructions\n\
19708 -mno-mcu do not generate MCU instructions\n"));
19709 fprintf (stream, _("\
19710 -mvirt generate Virtualization instructions\n\
19711 -mno-virt do not generate Virtualization instructions\n"));
19712 fprintf (stream, _("\
19713 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19714 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19715 -mfix-vr4120 work around certain VR4120 errata\n\
19716 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19717 -mfix-24k insert a nop after ERET and DERET instructions\n\
19718 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19719 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19720 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19721 -msym32 assume all symbols have 32-bit values\n\
19722 -O0 remove unneeded NOPs, do not swap branches\n\
19723 -O remove unneeded NOPs and swap branches\n\
19724 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19725 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19726 fprintf (stream, _("\
19727 -mhard-float allow floating-point instructions\n\
19728 -msoft-float do not allow floating-point instructions\n\
19729 -msingle-float only allow 32-bit floating-point operations\n\
19730 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19731 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19732 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19735 fprintf (stream, _("\
19736 -KPIC, -call_shared generate SVR4 position independent code\n\
19737 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19738 -mvxworks-pic generate VxWorks position independent code\n\
19739 -non_shared do not generate code that can operate with DSOs\n\
19740 -xgot assume a 32 bit GOT\n\
19741 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19742 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19743 position dependent (non shared) code\n\
19744 -mabi=ABI create ABI conformant object file for:\n"));
19748 show (stream, "32", &column, &first);
19749 show (stream, "o64", &column, &first);
19750 show (stream, "n32", &column, &first);
19751 show (stream, "64", &column, &first);
19752 show (stream, "eabi", &column, &first);
19754 fputc ('\n', stream);
19756 fprintf (stream, _("\
19757 -32 create o32 ABI object file (default)\n\
19758 -n32 create n32 ABI object file\n\
19759 -64 create 64 ABI object file\n"));
19765 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19767 if (HAVE_64BIT_SYMBOLS)
19768 return dwarf2_format_64bit_irix;
19770 return dwarf2_format_32bit;
19775 mips_dwarf2_addr_size (void)
19777 if (HAVE_64BIT_OBJECTS)
19783 /* Standard calling conventions leave the CFA at SP on entry. */
19785 mips_cfi_frame_initial_instructions (void)
19787 cfi_add_CFA_def_cfa_register (SP);
19791 tc_mips_regname_to_dw2regnum (char *regname)
19793 unsigned int regnum = -1;
19796 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))