1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi = NO_ABI;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Enabled Application Specific Extensions (ASEs). These are set to -1
141 if they have not been initialized. Changed by `.set <asename>', by
142 command line options, and based on the default architecture. */
145 /* Whether we are assembling for the mips16 processor. 0 if we are
146 not, 1 if we are, and -1 if the value has not been initialized.
147 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
148 -nomips16 command line options, and the default CPU. */
150 /* Non-zero if we should not reorder instructions. Changed by `.set
151 reorder' and `.set noreorder'. */
153 /* Non-zero if we should not permit the $at ($1) register to be used
154 in instructions. Changed by `.set at' and `.set noat'. */
156 /* Non-zero if we should warn when a macro instruction expands into
157 more than one machine instruction. Changed by `.set nomacro' and
159 int warn_about_macros;
160 /* Non-zero if we should not move instructions. Changed by `.set
161 move', `.set volatile', `.set nomove', and `.set novolatile'. */
163 /* Non-zero if we should not optimize branches by moving the target
164 of the branch into the delay slot. Actually, we don't perform
165 this optimization anyhow. Changed by `.set bopt' and `.set
168 /* Non-zero if we should not autoextend mips16 instructions.
169 Changed by `.set autoextend' and `.set noautoextend'. */
171 /* Restrict general purpose registers and floating point registers
172 to 32 bit. This is initially determined when -mgp32 or -mfp32
173 is passed but can changed if the assembler code uses .set mipsN. */
176 /* The ABI currently in use. This is changed by .set mipsN to loosen
177 restrictions and doesn't affect the whole file. */
178 enum mips_abi_level abi;
181 /* True if -mgp32 was passed. */
182 static int file_mips_gp32 = -1;
184 /* True if -mfp32 was passed. */
185 static int file_mips_fp32 = -1;
187 /* This is the struct we use to hold the current set of options. Note
188 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
189 -1 to indicate that they have not been initialized. */
191 static struct mips_set_options mips_opts =
193 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
196 /* These variables are filled in with the masks of registers used.
197 The object format code reads them and puts them in the appropriate
199 unsigned long mips_gprmask;
200 unsigned long mips_cprmask[4];
202 /* MIPS ISA we are using for this output file. */
203 static int file_mips_isa = ISA_UNKNOWN;
205 /* True if -mips3d was passed or implied by arguments passed on the
206 command line (e.g., by -march). */
207 static int file_ase_mips3d;
209 /* True if -mdmx was passed or implied by arguments passed on the
210 command line (e.g., by -march). */
211 static int file_ase_mdmx;
213 /* The argument of the -mcpu= flag. Historical for code generation. */
214 static int mips_cpu = CPU_UNKNOWN;
216 /* The argument of the -march= flag. The architecture we are assembling. */
217 static int mips_arch = CPU_UNKNOWN;
219 /* The argument of the -mtune= flag. The architecture for which we
221 static int mips_tune = CPU_UNKNOWN;
223 /* Whether we should mark the file EABI64 or EABI32. */
224 static int mips_eabi64 = 0;
226 /* If they asked for mips1 or mips2 and a cpu that is
227 mips3 or greater, then mark the object file 32BITMODE. */
228 static int mips_32bitmode = 0;
230 /* Some ISA's have delay slots for instructions which read or write
231 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
232 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
233 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
234 delay slot in this ISA. The uses of this macro assume that any
235 ISA that has delay slots for one of these, has them for all. They
236 also assume that ISAs which don't have delays for these insns, don't
237 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
238 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
240 || (ISA) == ISA_MIPS2 \
241 || (ISA) == ISA_MIPS3 \
244 /* Return true if ISA supports 64 bit gp register instructions. */
245 #define ISA_HAS_64BIT_REGS(ISA) ( \
247 || (ISA) == ISA_MIPS4 \
248 || (ISA) == ISA_MIPS5 \
249 || (ISA) == ISA_MIPS64 \
252 #define HAVE_32BIT_GPRS \
254 || mips_opts.abi == O32_ABI \
255 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
257 #define HAVE_32BIT_FPRS \
259 || mips_opts.abi == O32_ABI \
260 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
262 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
263 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
265 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
267 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
269 /* We can only have 64bit addresses if the object file format
271 #define HAVE_32BIT_ADDRESSES \
273 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
274 || ! HAVE_64BIT_OBJECTS) \
275 && mips_pic != EMBEDDED_PIC))
277 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
279 /* Return true if the given CPU supports the MIPS3D ASE. */
280 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
283 /* Return true if the given CPU supports the MDMX ASE. */
284 #define CPU_HAS_MDMX(cpu) (0 \
287 /* Whether the processor uses hardware interlocks to protect
288 reads from the HI and LO registers, and thus does not
289 require nops to be inserted. */
291 #define hilo_interlocks (mips_arch == CPU_R4010 \
292 || mips_arch == CPU_SB1 \
295 /* Whether the processor uses hardware interlocks to protect reads
296 from the GPRs, and thus does not require nops to be inserted. */
297 #define gpr_interlocks \
298 (mips_opts.isa != ISA_MIPS1 \
299 || mips_arch == CPU_R3900)
301 /* As with other "interlocks" this is used by hardware that has FP
302 (co-processor) interlocks. */
303 /* Itbl support may require additional care here. */
304 #define cop_interlocks (mips_arch == CPU_R4300 \
305 || mips_arch == CPU_SB1 \
308 /* Is this a mfhi or mflo instruction? */
309 #define MF_HILO_INSN(PINFO) \
310 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
312 /* MIPS PIC level. */
316 /* Do not generate PIC code. */
319 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
320 not sure what it is supposed to do. */
323 /* Generate PIC code as in the SVR4 MIPS ABI. */
326 /* Generate PIC code without using a global offset table: the data
327 segment has a maximum size of 64K, all data references are off
328 the $gp register, and all text references are PC relative. This
329 is used on some embedded systems. */
333 static enum mips_pic_level mips_pic;
335 /* Warn about all NOPS that the assembler generates. */
336 static int warn_nops = 0;
338 /* 1 if we should generate 32 bit offsets from the $gp register in
339 SVR4_PIC mode. Currently has no meaning in other modes. */
340 static int mips_big_got = 0;
342 /* 1 if trap instructions should used for overflow rather than break
344 static int mips_trap = 0;
346 /* 1 if double width floating point constants should not be constructed
347 by assembling two single width halves into two single width floating
348 point registers which just happen to alias the double width destination
349 register. On some architectures this aliasing can be disabled by a bit
350 in the status register, and the setting of this bit cannot be determined
351 automatically at assemble time. */
352 static int mips_disable_float_construction;
354 /* Non-zero if any .set noreorder directives were used. */
356 static int mips_any_noreorder;
358 /* Non-zero if nops should be inserted when the register referenced in
359 an mfhi/mflo instruction is read in the next two instructions. */
360 static int mips_7000_hilo_fix;
362 /* The size of the small data section. */
363 static unsigned int g_switch_value = 8;
364 /* Whether the -G option was used. */
365 static int g_switch_seen = 0;
370 /* If we can determine in advance that GP optimization won't be
371 possible, we can skip the relaxation stuff that tries to produce
372 GP-relative references. This makes delay slot optimization work
375 This function can only provide a guess, but it seems to work for
376 gcc output. It needs to guess right for gcc, otherwise gcc
377 will put what it thinks is a GP-relative instruction in a branch
380 I don't know if a fix is needed for the SVR4_PIC mode. I've only
381 fixed it for the non-PIC mode. KR 95/04/07 */
382 static int nopic_need_relax PARAMS ((symbolS *, int));
384 /* handle of the OPCODE hash table */
385 static struct hash_control *op_hash = NULL;
387 /* The opcode hash table we use for the mips16. */
388 static struct hash_control *mips16_op_hash = NULL;
390 /* This array holds the chars that always start a comment. If the
391 pre-processor is disabled, these aren't very useful */
392 const char comment_chars[] = "#";
394 /* This array holds the chars that only start a comment at the beginning of
395 a line. If the line seems to have the form '# 123 filename'
396 .line and .file directives will appear in the pre-processed output */
397 /* Note that input_file.c hand checks for '#' at the beginning of the
398 first line of the input file. This is because the compiler outputs
399 #NO_APP at the beginning of its output. */
400 /* Also note that C style comments are always supported. */
401 const char line_comment_chars[] = "#";
403 /* This array holds machine specific line separator characters. */
404 const char line_separator_chars[] = ";";
406 /* Chars that can be used to separate mant from exp in floating point nums */
407 const char EXP_CHARS[] = "eE";
409 /* Chars that mean this number is a floating point constant */
412 const char FLT_CHARS[] = "rRsSfFdDxXpP";
414 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
415 changed in read.c . Ideally it shouldn't have to know about it at all,
416 but nothing is ideal around here.
419 static char *insn_error;
421 static int auto_align = 1;
423 /* When outputting SVR4 PIC code, the assembler needs to know the
424 offset in the stack frame from which to restore the $gp register.
425 This is set by the .cprestore pseudo-op, and saved in this
427 static offsetT mips_cprestore_offset = -1;
429 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
430 more optimizations, it can use a register value instead of a memory-saved
431 offset and even an other register than $gp as global pointer. */
432 static offsetT mips_cpreturn_offset = -1;
433 static int mips_cpreturn_register = -1;
434 static int mips_gp_register = GP;
435 static int mips_gprel_offset = 0;
437 /* Whether mips_cprestore_offset has been set in the current function
438 (or whether it has already been warned about, if not). */
439 static int mips_cprestore_valid = 0;
441 /* This is the register which holds the stack frame, as set by the
442 .frame pseudo-op. This is needed to implement .cprestore. */
443 static int mips_frame_reg = SP;
445 /* Whether mips_frame_reg has been set in the current function
446 (or whether it has already been warned about, if not). */
447 static int mips_frame_reg_valid = 0;
449 /* To output NOP instructions correctly, we need to keep information
450 about the previous two instructions. */
452 /* Whether we are optimizing. The default value of 2 means to remove
453 unneeded NOPs and swap branch instructions when possible. A value
454 of 1 means to not swap branches. A value of 0 means to always
456 static int mips_optimize = 2;
458 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
459 equivalent to seeing no -g option at all. */
460 static int mips_debug = 0;
462 /* The previous instruction. */
463 static struct mips_cl_insn prev_insn;
465 /* The instruction before prev_insn. */
466 static struct mips_cl_insn prev_prev_insn;
468 /* If we don't want information for prev_insn or prev_prev_insn, we
469 point the insn_mo field at this dummy integer. */
470 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
472 /* Non-zero if prev_insn is valid. */
473 static int prev_insn_valid;
475 /* The frag for the previous instruction. */
476 static struct frag *prev_insn_frag;
478 /* The offset into prev_insn_frag for the previous instruction. */
479 static long prev_insn_where;
481 /* The reloc type for the previous instruction, if any. */
482 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
484 /* The reloc for the previous instruction, if any. */
485 static fixS *prev_insn_fixp[3];
487 /* Non-zero if the previous instruction was in a delay slot. */
488 static int prev_insn_is_delay_slot;
490 /* Non-zero if the previous instruction was in a .set noreorder. */
491 static int prev_insn_unreordered;
493 /* Non-zero if the previous instruction uses an extend opcode (if
495 static int prev_insn_extended;
497 /* Non-zero if the previous previous instruction was in a .set
499 static int prev_prev_insn_unreordered;
501 /* If this is set, it points to a frag holding nop instructions which
502 were inserted before the start of a noreorder section. If those
503 nops turn out to be unnecessary, the size of the frag can be
505 static fragS *prev_nop_frag;
507 /* The number of nop instructions we created in prev_nop_frag. */
508 static int prev_nop_frag_holds;
510 /* The number of nop instructions that we know we need in
512 static int prev_nop_frag_required;
514 /* The number of instructions we've seen since prev_nop_frag. */
515 static int prev_nop_frag_since;
517 /* For ECOFF and ELF, relocations against symbols are done in two
518 parts, with a HI relocation and a LO relocation. Each relocation
519 has only 16 bits of space to store an addend. This means that in
520 order for the linker to handle carries correctly, it must be able
521 to locate both the HI and the LO relocation. This means that the
522 relocations must appear in order in the relocation table.
524 In order to implement this, we keep track of each unmatched HI
525 relocation. We then sort them so that they immediately precede the
526 corresponding LO relocation. */
531 struct mips_hi_fixup *next;
534 /* The section this fixup is in. */
538 /* The list of unmatched HI relocs. */
540 static struct mips_hi_fixup *mips_hi_fixup_list;
542 /* Map normal MIPS register numbers to mips16 register numbers. */
544 #define X ILLEGAL_REG
545 static const int mips32_to_16_reg_map[] =
547 X, X, 2, 3, 4, 5, 6, 7,
548 X, X, X, X, X, X, X, X,
549 0, 1, X, X, X, X, X, X,
550 X, X, X, X, X, X, X, X
554 /* Map mips16 register numbers to normal MIPS register numbers. */
556 static const unsigned int mips16_to_32_reg_map[] =
558 16, 17, 2, 3, 4, 5, 6, 7
561 /* Since the MIPS does not have multiple forms of PC relative
562 instructions, we do not have to do relaxing as is done on other
563 platforms. However, we do have to handle GP relative addressing
564 correctly, which turns out to be a similar problem.
566 Every macro that refers to a symbol can occur in (at least) two
567 forms, one with GP relative addressing and one without. For
568 example, loading a global variable into a register generally uses
569 a macro instruction like this:
571 If i can be addressed off the GP register (this is true if it is in
572 the .sbss or .sdata section, or if it is known to be smaller than
573 the -G argument) this will generate the following instruction:
575 This instruction will use a GPREL reloc. If i can not be addressed
576 off the GP register, the following instruction sequence will be used:
579 In this case the first instruction will have a HI16 reloc, and the
580 second reloc will have a LO16 reloc. Both relocs will be against
583 The issue here is that we may not know whether i is GP addressable
584 until after we see the instruction that uses it. Therefore, we
585 want to be able to choose the final instruction sequence only at
586 the end of the assembly. This is similar to the way other
587 platforms choose the size of a PC relative instruction only at the
590 When generating position independent code we do not use GP
591 addressing in quite the same way, but the issue still arises as
592 external symbols and local symbols must be handled differently.
594 We handle these issues by actually generating both possible
595 instruction sequences. The longer one is put in a frag_var with
596 type rs_machine_dependent. We encode what to do with the frag in
597 the subtype field. We encode (1) the number of existing bytes to
598 replace, (2) the number of new bytes to use, (3) the offset from
599 the start of the existing bytes to the first reloc we must generate
600 (that is, the offset is applied from the start of the existing
601 bytes after they are replaced by the new bytes, if any), (4) the
602 offset from the start of the existing bytes to the second reloc,
603 (5) whether a third reloc is needed (the third reloc is always four
604 bytes after the second reloc), and (6) whether to warn if this
605 variant is used (this is sometimes needed if .set nomacro or .set
606 noat is in effect). All these numbers are reasonably small.
608 Generating two instruction sequences must be handled carefully to
609 ensure that delay slots are handled correctly. Fortunately, there
610 are a limited number of cases. When the second instruction
611 sequence is generated, append_insn is directed to maintain the
612 existing delay slot information, so it continues to apply to any
613 code after the second instruction sequence. This means that the
614 second instruction sequence must not impose any requirements not
615 required by the first instruction sequence.
617 These variant frags are then handled in functions called by the
618 machine independent code. md_estimate_size_before_relax returns
619 the final size of the frag. md_convert_frag sets up the final form
620 of the frag. tc_gen_reloc adjust the first reloc and adds a second
622 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
626 | (((reloc1) + 64) << 9) \
627 | (((reloc2) + 64) << 2) \
628 | ((reloc3) ? (1 << 1) : 0) \
630 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
631 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
632 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
633 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
634 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
635 #define RELAX_WARN(i) ((i) & 1)
637 /* For mips16 code, we use an entirely different form of relaxation.
638 mips16 supports two versions of most instructions which take
639 immediate values: a small one which takes some small value, and a
640 larger one which takes a 16 bit value. Since branches also follow
641 this pattern, relaxing these values is required.
643 We can assemble both mips16 and normal MIPS code in a single
644 object. Therefore, we need to support this type of relaxation at
645 the same time that we support the relaxation described above. We
646 use the high bit of the subtype field to distinguish these cases.
648 The information we store for this type of relaxation is the
649 argument code found in the opcode file for this relocation, whether
650 the user explicitly requested a small or extended form, and whether
651 the relocation is in a jump or jal delay slot. That tells us the
652 size of the value, and how it should be stored. We also store
653 whether the fragment is considered to be extended or not. We also
654 store whether this is known to be a branch to a different section,
655 whether we have tried to relax this frag yet, and whether we have
656 ever extended a PC relative fragment because of a shift count. */
657 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
660 | ((small) ? 0x100 : 0) \
661 | ((ext) ? 0x200 : 0) \
662 | ((dslot) ? 0x400 : 0) \
663 | ((jal_dslot) ? 0x800 : 0))
664 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
665 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
666 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
667 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
668 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
669 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
670 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
671 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
672 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
673 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
674 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
675 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
677 /* Prototypes for static functions. */
680 #define internalError() \
681 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
683 #define internalError() as_fatal (_("MIPS internal Error"));
686 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
688 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
689 unsigned int reg, enum mips_regclass class));
690 static int reg_needs_delay PARAMS ((unsigned int));
691 static void mips16_mark_labels PARAMS ((void));
692 static void append_insn PARAMS ((char *place,
693 struct mips_cl_insn * ip,
695 bfd_reloc_code_real_type *r,
697 static void mips_no_prev_insn PARAMS ((int));
698 static void mips_emit_delays PARAMS ((boolean));
700 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
701 const char *name, const char *fmt,
704 static void macro_build ();
706 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
707 const char *, const char *,
709 static void macro_build_jalr PARAMS ((int, expressionS *));
710 static void macro_build_lui PARAMS ((char *place, int *counter,
711 expressionS * ep, int regnum));
712 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
713 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
715 static void load_register PARAMS ((int *, int, expressionS *, int));
716 static void load_address PARAMS ((int *, int, expressionS *, int *));
717 static void move_register PARAMS ((int *, int, int));
718 static void macro PARAMS ((struct mips_cl_insn * ip));
719 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
720 #ifdef LOSING_COMPILER
721 static void macro2 PARAMS ((struct mips_cl_insn * ip));
723 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
724 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
725 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
726 boolean, boolean, unsigned long *,
727 boolean *, unsigned short *));
728 static int my_getPercentOp PARAMS ((char **, unsigned int *, int *));
729 static int my_getSmallParser PARAMS ((char **, unsigned int *, int *));
730 static int my_getSmallExpression PARAMS ((expressionS *, char *));
731 static void my_getExpression PARAMS ((expressionS *, char *));
733 static int support_64bit_objects PARAMS((void));
735 static symbolS *get_symbol PARAMS ((void));
736 static void mips_align PARAMS ((int to, int fill, symbolS *label));
737 static void s_align PARAMS ((int));
738 static void s_change_sec PARAMS ((int));
739 static void s_cons PARAMS ((int));
740 static void s_float_cons PARAMS ((int));
741 static void s_mips_globl PARAMS ((int));
742 static void s_option PARAMS ((int));
743 static void s_mipsset PARAMS ((int));
744 static void s_abicalls PARAMS ((int));
745 static void s_cpload PARAMS ((int));
746 static void s_cpsetup PARAMS ((int));
747 static void s_cplocal PARAMS ((int));
748 static void s_cprestore PARAMS ((int));
749 static void s_cpreturn PARAMS ((int));
750 static void s_gpvalue PARAMS ((int));
751 static void s_gpword PARAMS ((int));
752 static void s_cpadd PARAMS ((int));
753 static void s_insn PARAMS ((int));
754 static void md_obj_begin PARAMS ((void));
755 static void md_obj_end PARAMS ((void));
756 static long get_number PARAMS ((void));
757 static void s_mips_ent PARAMS ((int));
758 static void s_mips_end PARAMS ((int));
759 static void s_mips_frame PARAMS ((int));
760 static void s_mips_mask PARAMS ((int));
761 static void s_mips_stab PARAMS ((int));
762 static void s_mips_weakext PARAMS ((int));
763 static void s_file PARAMS ((int));
764 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
765 static const char *mips_isa_to_str PARAMS ((int));
766 static const char *mips_cpu_to_str PARAMS ((int));
767 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
768 static void show PARAMS ((FILE *, char *, int *, int *));
770 static int mips_need_elf_addend_fixup PARAMS ((fixS *));
773 /* Return values of my_getSmallExpression(). */
780 /* Direct relocation creation by %percent_op(). */
799 /* Table and functions used to map between CPU/ISA names, and
800 ISA levels, and CPU numbers. */
804 const char *name; /* CPU or ISA name. */
805 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
806 int isa; /* ISA level. */
807 int cpu; /* CPU number (default CPU if ISA). */
810 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
811 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
812 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
816 The following pseudo-ops from the Kane and Heinrich MIPS book
817 should be defined here, but are currently unsupported: .alias,
818 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
820 The following pseudo-ops from the Kane and Heinrich MIPS book are
821 specific to the type of debugging information being generated, and
822 should be defined by the object format: .aent, .begin, .bend,
823 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
826 The following pseudo-ops from the Kane and Heinrich MIPS book are
827 not MIPS CPU specific, but are also not specific to the object file
828 format. This file is probably the best place to define them, but
829 they are not currently supported: .asm0, .endr, .lab, .repeat,
832 static const pseudo_typeS mips_pseudo_table[] =
834 /* MIPS specific pseudo-ops. */
835 {"option", s_option, 0},
836 {"set", s_mipsset, 0},
837 {"rdata", s_change_sec, 'r'},
838 {"sdata", s_change_sec, 's'},
839 {"livereg", s_ignore, 0},
840 {"abicalls", s_abicalls, 0},
841 {"cpload", s_cpload, 0},
842 {"cpsetup", s_cpsetup, 0},
843 {"cplocal", s_cplocal, 0},
844 {"cprestore", s_cprestore, 0},
845 {"cpreturn", s_cpreturn, 0},
846 {"gpvalue", s_gpvalue, 0},
847 {"gpword", s_gpword, 0},
848 {"cpadd", s_cpadd, 0},
851 /* Relatively generic pseudo-ops that happen to be used on MIPS
853 {"asciiz", stringer, 1},
854 {"bss", s_change_sec, 'b'},
857 {"dword", s_cons, 3},
858 {"weakext", s_mips_weakext, 0},
860 /* These pseudo-ops are defined in read.c, but must be overridden
861 here for one reason or another. */
862 {"align", s_align, 0},
864 {"data", s_change_sec, 'd'},
865 {"double", s_float_cons, 'd'},
866 {"float", s_float_cons, 'f'},
867 {"globl", s_mips_globl, 0},
868 {"global", s_mips_globl, 0},
869 {"hword", s_cons, 1},
874 {"short", s_cons, 1},
875 {"single", s_float_cons, 'f'},
876 {"stabn", s_mips_stab, 'n'},
877 {"text", s_change_sec, 't'},
880 #ifdef MIPS_STABS_ELF
881 { "extern", ecoff_directive_extern, 0},
887 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
889 /* These pseudo-ops should be defined by the object file format.
890 However, a.out doesn't support them, so we have versions here. */
891 {"aent", s_mips_ent, 1},
892 {"bgnb", s_ignore, 0},
893 {"end", s_mips_end, 0},
894 {"endb", s_ignore, 0},
895 {"ent", s_mips_ent, 0},
897 {"fmask", s_mips_mask, 'F'},
898 {"frame", s_mips_frame, 0},
899 {"loc", s_ignore, 0},
900 {"mask", s_mips_mask, 'R'},
901 {"verstamp", s_ignore, 0},
905 extern void pop_insert PARAMS ((const pseudo_typeS *));
910 pop_insert (mips_pseudo_table);
911 if (! ECOFF_DEBUGGING)
912 pop_insert (mips_nonecoff_pseudo_table);
915 /* Symbols labelling the current insn. */
917 struct insn_label_list
919 struct insn_label_list *next;
923 static struct insn_label_list *insn_labels;
924 static struct insn_label_list *free_insn_labels;
926 static void mips_clear_insn_labels PARAMS ((void));
929 mips_clear_insn_labels ()
931 register struct insn_label_list **pl;
933 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
939 static char *expr_end;
941 /* Expressions which appear in instructions. These are set by
944 static expressionS imm_expr;
945 static expressionS offset_expr;
947 /* Relocs associated with imm_expr and offset_expr. */
949 static bfd_reloc_code_real_type imm_reloc[3]
950 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
951 static bfd_reloc_code_real_type offset_reloc[3]
952 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
954 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
956 static boolean imm_unmatched_hi;
958 /* These are set by mips16_ip if an explicit extension is used. */
960 static boolean mips16_small, mips16_ext;
962 #ifdef MIPS_STABS_ELF
963 /* The pdr segment for per procedure frame/regmask info */
969 mips_isa_to_str (isa)
972 const struct mips_cpu_info *ci;
975 ci = mips_cpu_info_from_isa (isa);
979 sprintf (s, "ISA#%d", isa);
984 mips_cpu_to_str (cpu)
987 const struct mips_cpu_info *ci;
990 ci = mips_cpu_info_from_cpu (cpu);
994 sprintf (s, "CPU#%d", cpu);
998 /* The default target format to use. */
1001 mips_target_format ()
1003 switch (OUTPUT_FLAVOR)
1005 case bfd_target_aout_flavour:
1006 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1007 case bfd_target_ecoff_flavour:
1008 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1009 case bfd_target_coff_flavour:
1011 case bfd_target_elf_flavour:
1013 /* This is traditional mips */
1014 return (target_big_endian
1015 ? (HAVE_64BIT_OBJECTS ? "elf64-tradbigmips"
1016 : "elf32-tradbigmips")
1017 : (HAVE_64BIT_OBJECTS ? "elf64-tradlittlemips"
1018 : "elf32-tradlittlemips"));
1020 return (target_big_endian
1021 ? (HAVE_64BIT_OBJECTS ? "elf64-bigmips" : "elf32-bigmips")
1022 : (HAVE_64BIT_OBJECTS ? "elf64-littlemips"
1023 : "elf32-littlemips"));
1031 /* This function is called once, at assembler startup time. It should
1032 set up all the tables, etc. that the MD part of the assembler will need. */
1037 register const char *retval = NULL;
1041 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1042 as_warn (_("Could not set architecture and machine"));
1044 op_hash = hash_new ();
1046 for (i = 0; i < NUMOPCODES;)
1048 const char *name = mips_opcodes[i].name;
1050 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1053 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1054 mips_opcodes[i].name, retval);
1055 /* Probably a memory allocation problem? Give up now. */
1056 as_fatal (_("Broken assembler. No assembly attempted."));
1060 if (mips_opcodes[i].pinfo != INSN_MACRO)
1062 if (!validate_mips_insn (&mips_opcodes[i]))
1067 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1070 mips16_op_hash = hash_new ();
1073 while (i < bfd_mips16_num_opcodes)
1075 const char *name = mips16_opcodes[i].name;
1077 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1079 as_fatal (_("internal: can't hash `%s': %s"),
1080 mips16_opcodes[i].name, retval);
1083 if (mips16_opcodes[i].pinfo != INSN_MACRO
1084 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1085 != mips16_opcodes[i].match))
1087 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1088 mips16_opcodes[i].name, mips16_opcodes[i].args);
1093 while (i < bfd_mips16_num_opcodes
1094 && strcmp (mips16_opcodes[i].name, name) == 0);
1098 as_fatal (_("Broken assembler. No assembly attempted."));
1100 /* We add all the general register names to the symbol table. This
1101 helps us detect invalid uses of them. */
1102 for (i = 0; i < 32; i++)
1106 sprintf (buf, "$%d", i);
1107 symbol_table_insert (symbol_new (buf, reg_section, i,
1108 &zero_address_frag));
1110 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1111 &zero_address_frag));
1112 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1113 &zero_address_frag));
1114 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1115 &zero_address_frag));
1116 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1117 &zero_address_frag));
1118 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1119 &zero_address_frag));
1120 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1121 &zero_address_frag));
1122 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1123 &zero_address_frag));
1124 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1125 &zero_address_frag));
1127 mips_no_prev_insn (false);
1130 mips_cprmask[0] = 0;
1131 mips_cprmask[1] = 0;
1132 mips_cprmask[2] = 0;
1133 mips_cprmask[3] = 0;
1135 /* set the default alignment for the text section (2**2) */
1136 record_alignment (text_section, 2);
1138 if (USE_GLOBAL_POINTER_OPT)
1139 bfd_set_gp_size (stdoutput, g_switch_value);
1141 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1143 /* On a native system, sections must be aligned to 16 byte
1144 boundaries. When configured for an embedded ELF target, we
1146 if (strcmp (TARGET_OS, "elf") != 0)
1148 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1149 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1150 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1153 /* Create a .reginfo section for register masks and a .mdebug
1154 section for debugging information. */
1162 subseg = now_subseg;
1164 /* The ABI says this section should be loaded so that the
1165 running program can access it. However, we don't load it
1166 if we are configured for an embedded target */
1167 flags = SEC_READONLY | SEC_DATA;
1168 if (strcmp (TARGET_OS, "elf") != 0)
1169 flags |= SEC_ALLOC | SEC_LOAD;
1171 if (file_mips_abi != N64_ABI)
1173 sec = subseg_new (".reginfo", (subsegT) 0);
1175 bfd_set_section_flags (stdoutput, sec, flags);
1176 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1179 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1184 /* The 64-bit ABI uses a .MIPS.options section rather than
1185 .reginfo section. */
1186 sec = subseg_new (".MIPS.options", (subsegT) 0);
1187 bfd_set_section_flags (stdoutput, sec, flags);
1188 bfd_set_section_alignment (stdoutput, sec, 3);
1191 /* Set up the option header. */
1193 Elf_Internal_Options opthdr;
1196 opthdr.kind = ODK_REGINFO;
1197 opthdr.size = (sizeof (Elf_External_Options)
1198 + sizeof (Elf64_External_RegInfo));
1201 f = frag_more (sizeof (Elf_External_Options));
1202 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1203 (Elf_External_Options *) f);
1205 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1210 if (ECOFF_DEBUGGING)
1212 sec = subseg_new (".mdebug", (subsegT) 0);
1213 (void) bfd_set_section_flags (stdoutput, sec,
1214 SEC_HAS_CONTENTS | SEC_READONLY);
1215 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1218 #ifdef MIPS_STABS_ELF
1219 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1220 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1221 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1222 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1225 subseg_set (seg, subseg);
1229 if (! ECOFF_DEBUGGING)
1236 if (! ECOFF_DEBUGGING)
1244 struct mips_cl_insn insn;
1245 bfd_reloc_code_real_type unused_reloc[3]
1246 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1248 imm_expr.X_op = O_absent;
1249 imm_unmatched_hi = false;
1250 offset_expr.X_op = O_absent;
1251 imm_reloc[0] = BFD_RELOC_UNUSED;
1252 imm_reloc[1] = BFD_RELOC_UNUSED;
1253 imm_reloc[2] = BFD_RELOC_UNUSED;
1254 offset_reloc[0] = BFD_RELOC_UNUSED;
1255 offset_reloc[1] = BFD_RELOC_UNUSED;
1256 offset_reloc[2] = BFD_RELOC_UNUSED;
1258 if (mips_opts.mips16)
1259 mips16_ip (str, &insn);
1262 mips_ip (str, &insn);
1263 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1264 str, insn.insn_opcode));
1269 as_bad ("%s `%s'", insn_error, str);
1273 if (insn.insn_mo->pinfo == INSN_MACRO)
1275 if (mips_opts.mips16)
1276 mips16_macro (&insn);
1282 if (imm_expr.X_op != O_absent)
1283 append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi);
1284 else if (offset_expr.X_op != O_absent)
1285 append_insn (NULL, &insn, &offset_expr, offset_reloc, false);
1287 append_insn (NULL, &insn, NULL, unused_reloc, false);
1291 /* See whether instruction IP reads register REG. CLASS is the type
1295 insn_uses_reg (ip, reg, class)
1296 struct mips_cl_insn *ip;
1298 enum mips_regclass class;
1300 if (class == MIPS16_REG)
1302 assert (mips_opts.mips16);
1303 reg = mips16_to_32_reg_map[reg];
1304 class = MIPS_GR_REG;
1307 /* Don't report on general register 0, since it never changes. */
1308 if (class == MIPS_GR_REG && reg == 0)
1311 if (class == MIPS_FP_REG)
1313 assert (! mips_opts.mips16);
1314 /* If we are called with either $f0 or $f1, we must check $f0.
1315 This is not optimal, because it will introduce an unnecessary
1316 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1317 need to distinguish reading both $f0 and $f1 or just one of
1318 them. Note that we don't have to check the other way,
1319 because there is no instruction that sets both $f0 and $f1
1320 and requires a delay. */
1321 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1322 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1323 == (reg &~ (unsigned) 1)))
1325 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1326 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1327 == (reg &~ (unsigned) 1)))
1330 else if (! mips_opts.mips16)
1332 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1333 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1335 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1336 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1341 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1342 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1343 & MIPS16OP_MASK_RX)]
1346 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1347 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1348 & MIPS16OP_MASK_RY)]
1351 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1352 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1353 & MIPS16OP_MASK_MOVE32Z)]
1356 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1358 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1360 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1362 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1363 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1364 & MIPS16OP_MASK_REGR32) == reg)
1371 /* This function returns true if modifying a register requires a
1375 reg_needs_delay (reg)
1378 unsigned long prev_pinfo;
1380 prev_pinfo = prev_insn.insn_mo->pinfo;
1381 if (! mips_opts.noreorder
1382 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1383 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1384 || (! gpr_interlocks
1385 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1387 /* A load from a coprocessor or from memory. All load
1388 delays delay the use of general register rt for one
1389 instruction on the r3000. The r6000 and r4000 use
1391 /* Itbl support may require additional care here. */
1392 know (prev_pinfo & INSN_WRITE_GPR_T);
1393 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1400 /* Mark instruction labels in mips16 mode. This permits the linker to
1401 handle them specially, such as generating jalx instructions when
1402 needed. We also make them odd for the duration of the assembly, in
1403 order to generate the right sort of code. We will make them even
1404 in the adjust_symtab routine, while leaving them marked. This is
1405 convenient for the debugger and the disassembler. The linker knows
1406 to make them odd again. */
1409 mips16_mark_labels ()
1411 if (mips_opts.mips16)
1413 struct insn_label_list *l;
1416 for (l = insn_labels; l != NULL; l = l->next)
1419 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1420 S_SET_OTHER (l->label, STO_MIPS16);
1422 val = S_GET_VALUE (l->label);
1424 S_SET_VALUE (l->label, val + 1);
1429 /* Output an instruction. PLACE is where to put the instruction; if
1430 it is NULL, this uses frag_more to get room. IP is the instruction
1431 information. ADDRESS_EXPR is an operand of the instruction to be
1432 used with RELOC_TYPE. */
1435 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1437 struct mips_cl_insn *ip;
1438 expressionS *address_expr;
1439 bfd_reloc_code_real_type *reloc_type;
1440 boolean unmatched_hi;
1442 register unsigned long prev_pinfo, pinfo;
1447 /* Mark instruction labels in mips16 mode. */
1448 mips16_mark_labels ();
1450 prev_pinfo = prev_insn.insn_mo->pinfo;
1451 pinfo = ip->insn_mo->pinfo;
1453 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1457 /* If the previous insn required any delay slots, see if we need
1458 to insert a NOP or two. There are eight kinds of possible
1459 hazards, of which an instruction can have at most one type.
1460 (1) a load from memory delay
1461 (2) a load from a coprocessor delay
1462 (3) an unconditional branch delay
1463 (4) a conditional branch delay
1464 (5) a move to coprocessor register delay
1465 (6) a load coprocessor register from memory delay
1466 (7) a coprocessor condition code delay
1467 (8) a HI/LO special register delay
1469 There are a lot of optimizations we could do that we don't.
1470 In particular, we do not, in general, reorder instructions.
1471 If you use gcc with optimization, it will reorder
1472 instructions and generally do much more optimization then we
1473 do here; repeating all that work in the assembler would only
1474 benefit hand written assembly code, and does not seem worth
1477 /* This is how a NOP is emitted. */
1478 #define emit_nop() \
1480 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1481 : md_number_to_chars (frag_more (4), 0, 4))
1483 /* The previous insn might require a delay slot, depending upon
1484 the contents of the current insn. */
1485 if (! mips_opts.mips16
1486 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1487 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1488 && ! cop_interlocks)
1489 || (! gpr_interlocks
1490 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1492 /* A load from a coprocessor or from memory. All load
1493 delays delay the use of general register rt for one
1494 instruction on the r3000. The r6000 and r4000 use
1496 /* Itbl support may require additional care here. */
1497 know (prev_pinfo & INSN_WRITE_GPR_T);
1498 if (mips_optimize == 0
1499 || insn_uses_reg (ip,
1500 ((prev_insn.insn_opcode >> OP_SH_RT)
1505 else if (! mips_opts.mips16
1506 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1507 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1508 && ! cop_interlocks)
1509 || (mips_opts.isa == ISA_MIPS1
1510 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1512 /* A generic coprocessor delay. The previous instruction
1513 modified a coprocessor general or control register. If
1514 it modified a control register, we need to avoid any
1515 coprocessor instruction (this is probably not always
1516 required, but it sometimes is). If it modified a general
1517 register, we avoid using that register.
1519 On the r6000 and r4000 loading a coprocessor register
1520 from memory is interlocked, and does not require a delay.
1522 This case is not handled very well. There is no special
1523 knowledge of CP0 handling, and the coprocessors other
1524 than the floating point unit are not distinguished at
1526 /* Itbl support may require additional care here. FIXME!
1527 Need to modify this to include knowledge about
1528 user specified delays! */
1529 if (prev_pinfo & INSN_WRITE_FPR_T)
1531 if (mips_optimize == 0
1532 || insn_uses_reg (ip,
1533 ((prev_insn.insn_opcode >> OP_SH_FT)
1538 else if (prev_pinfo & INSN_WRITE_FPR_S)
1540 if (mips_optimize == 0
1541 || insn_uses_reg (ip,
1542 ((prev_insn.insn_opcode >> OP_SH_FS)
1549 /* We don't know exactly what the previous instruction
1550 does. If the current instruction uses a coprocessor
1551 register, we must insert a NOP. If previous
1552 instruction may set the condition codes, and the
1553 current instruction uses them, we must insert two
1555 /* Itbl support may require additional care here. */
1556 if (mips_optimize == 0
1557 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1558 && (pinfo & INSN_READ_COND_CODE)))
1560 else if (pinfo & INSN_COP)
1564 else if (! mips_opts.mips16
1565 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1566 && (prev_pinfo & INSN_WRITE_COND_CODE)
1567 && ! cop_interlocks)
1569 /* The previous instruction sets the coprocessor condition
1570 codes, but does not require a general coprocessor delay
1571 (this means it is a floating point comparison
1572 instruction). If this instruction uses the condition
1573 codes, we need to insert a single NOP. */
1574 /* Itbl support may require additional care here. */
1575 if (mips_optimize == 0
1576 || (pinfo & INSN_READ_COND_CODE))
1580 /* If we're fixing up mfhi/mflo for the r7000 and the
1581 previous insn was an mfhi/mflo and the current insn
1582 reads the register that the mfhi/mflo wrote to, then
1585 else if (mips_7000_hilo_fix
1586 && MF_HILO_INSN (prev_pinfo)
1587 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1594 /* If we're fixing up mfhi/mflo for the r7000 and the
1595 2nd previous insn was an mfhi/mflo and the current insn
1596 reads the register that the mfhi/mflo wrote to, then
1599 else if (mips_7000_hilo_fix
1600 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1601 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1609 else if (prev_pinfo & INSN_READ_LO)
1611 /* The previous instruction reads the LO register; if the
1612 current instruction writes to the LO register, we must
1613 insert two NOPS. Some newer processors have interlocks.
1614 Also the tx39's multiply instructions can be exectuted
1615 immediatly after a read from HI/LO (without the delay),
1616 though the tx39's divide insns still do require the
1618 if (! (hilo_interlocks
1619 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1620 && (mips_optimize == 0
1621 || (pinfo & INSN_WRITE_LO)))
1623 /* Most mips16 branch insns don't have a delay slot.
1624 If a read from LO is immediately followed by a branch
1625 to a write to LO we have a read followed by a write
1626 less than 2 insns away. We assume the target of
1627 a branch might be a write to LO, and insert a nop
1628 between a read and an immediately following branch. */
1629 else if (mips_opts.mips16
1630 && (mips_optimize == 0
1631 || (pinfo & MIPS16_INSN_BRANCH)))
1634 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1636 /* The previous instruction reads the HI register; if the
1637 current instruction writes to the HI register, we must
1638 insert a NOP. Some newer processors have interlocks.
1639 Also the note tx39's multiply above. */
1640 if (! (hilo_interlocks
1641 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1642 && (mips_optimize == 0
1643 || (pinfo & INSN_WRITE_HI)))
1645 /* Most mips16 branch insns don't have a delay slot.
1646 If a read from HI is immediately followed by a branch
1647 to a write to HI we have a read followed by a write
1648 less than 2 insns away. We assume the target of
1649 a branch might be a write to HI, and insert a nop
1650 between a read and an immediately following branch. */
1651 else if (mips_opts.mips16
1652 && (mips_optimize == 0
1653 || (pinfo & MIPS16_INSN_BRANCH)))
1657 /* If the previous instruction was in a noreorder section, then
1658 we don't want to insert the nop after all. */
1659 /* Itbl support may require additional care here. */
1660 if (prev_insn_unreordered)
1663 /* There are two cases which require two intervening
1664 instructions: 1) setting the condition codes using a move to
1665 coprocessor instruction which requires a general coprocessor
1666 delay and then reading the condition codes 2) reading the HI
1667 or LO register and then writing to it (except on processors
1668 which have interlocks). If we are not already emitting a NOP
1669 instruction, we must check for these cases compared to the
1670 instruction previous to the previous instruction. */
1671 if ((! mips_opts.mips16
1672 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1673 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1674 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1675 && (pinfo & INSN_READ_COND_CODE)
1676 && ! cop_interlocks)
1677 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1678 && (pinfo & INSN_WRITE_LO)
1679 && ! (hilo_interlocks
1680 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1681 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1682 && (pinfo & INSN_WRITE_HI)
1683 && ! (hilo_interlocks
1684 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1689 if (prev_prev_insn_unreordered)
1692 if (prev_prev_nop && nops == 0)
1695 /* If we are being given a nop instruction, don't bother with
1696 one of the nops we would otherwise output. This will only
1697 happen when a nop instruction is used with mips_optimize set
1700 && ! mips_opts.noreorder
1701 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1704 /* Now emit the right number of NOP instructions. */
1705 if (nops > 0 && ! mips_opts.noreorder)
1708 unsigned long old_frag_offset;
1710 struct insn_label_list *l;
1712 old_frag = frag_now;
1713 old_frag_offset = frag_now_fix ();
1715 for (i = 0; i < nops; i++)
1720 listing_prev_line ();
1721 /* We may be at the start of a variant frag. In case we
1722 are, make sure there is enough space for the frag
1723 after the frags created by listing_prev_line. The
1724 argument to frag_grow here must be at least as large
1725 as the argument to all other calls to frag_grow in
1726 this file. We don't have to worry about being in the
1727 middle of a variant frag, because the variants insert
1728 all needed nop instructions themselves. */
1732 for (l = insn_labels; l != NULL; l = l->next)
1736 assert (S_GET_SEGMENT (l->label) == now_seg);
1737 symbol_set_frag (l->label, frag_now);
1738 val = (valueT) frag_now_fix ();
1739 /* mips16 text labels are stored as odd. */
1740 if (mips_opts.mips16)
1742 S_SET_VALUE (l->label, val);
1745 #ifndef NO_ECOFF_DEBUGGING
1746 if (ECOFF_DEBUGGING)
1747 ecoff_fix_loc (old_frag, old_frag_offset);
1750 else if (prev_nop_frag != NULL)
1752 /* We have a frag holding nops we may be able to remove. If
1753 we don't need any nops, we can decrease the size of
1754 prev_nop_frag by the size of one instruction. If we do
1755 need some nops, we count them in prev_nops_required. */
1756 if (prev_nop_frag_since == 0)
1760 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1761 --prev_nop_frag_holds;
1764 prev_nop_frag_required += nops;
1768 if (prev_prev_nop == 0)
1770 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1771 --prev_nop_frag_holds;
1774 ++prev_nop_frag_required;
1777 if (prev_nop_frag_holds <= prev_nop_frag_required)
1778 prev_nop_frag = NULL;
1780 ++prev_nop_frag_since;
1782 /* Sanity check: by the time we reach the second instruction
1783 after prev_nop_frag, we should have used up all the nops
1784 one way or another. */
1785 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1789 if (*reloc_type > BFD_RELOC_UNUSED)
1791 /* We need to set up a variant frag. */
1792 assert (mips_opts.mips16 && address_expr != NULL);
1793 f = frag_var (rs_machine_dependent, 4, 0,
1794 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
1795 mips16_small, mips16_ext,
1797 & INSN_UNCOND_BRANCH_DELAY),
1798 (*prev_insn_reloc_type
1799 == BFD_RELOC_MIPS16_JMP)),
1800 make_expr_symbol (address_expr), 0, NULL);
1802 else if (place != NULL)
1804 else if (mips_opts.mips16
1806 && *reloc_type != BFD_RELOC_MIPS16_JMP)
1808 /* Make sure there is enough room to swap this instruction with
1809 a following jump instruction. */
1815 if (mips_opts.mips16
1816 && mips_opts.noreorder
1817 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1818 as_warn (_("extended instruction in delay slot"));
1823 fixp[0] = fixp[1] = fixp[2] = NULL;
1824 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
1826 if (address_expr->X_op == O_constant)
1830 switch (*reloc_type)
1833 ip->insn_opcode |= address_expr->X_add_number;
1836 case BFD_RELOC_MIPS_HIGHEST:
1837 tmp = (address_expr->X_add_number + 0x800080008000) >> 16;
1839 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1842 case BFD_RELOC_MIPS_HIGHER:
1843 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
1844 ip->insn_opcode |= (tmp >> 16) & 0xffff;
1847 case BFD_RELOC_HI16_S:
1848 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
1852 case BFD_RELOC_HI16:
1853 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
1856 case BFD_RELOC_LO16:
1857 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1860 case BFD_RELOC_MIPS_JMP:
1861 if ((address_expr->X_add_number & 3) != 0)
1862 as_bad (_("jump to misaligned address (0x%lx)"),
1863 (unsigned long) address_expr->X_add_number);
1864 if (address_expr->X_add_number & ~0xfffffff
1865 || address_expr->X_add_number > 0x7fffffc)
1866 as_bad (_("jump address range overflow (0x%lx)"),
1867 (unsigned long) address_expr->X_add_number);
1868 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1871 case BFD_RELOC_MIPS16_JMP:
1872 if ((address_expr->X_add_number & 3) != 0)
1873 as_bad (_("jump to misaligned address (0x%lx)"),
1874 (unsigned long) address_expr->X_add_number);
1875 if (address_expr->X_add_number & ~0xfffffff
1876 || address_expr->X_add_number > 0x7fffffc)
1877 as_bad (_("jump address range overflow (0x%lx)"),
1878 (unsigned long) address_expr->X_add_number);
1880 (((address_expr->X_add_number & 0x7c0000) << 3)
1881 | ((address_expr->X_add_number & 0xf800000) >> 7)
1882 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1885 case BFD_RELOC_16_PCREL:
1886 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1889 case BFD_RELOC_16_PCREL_S2:
1899 /* Don't generate a reloc if we are writing into a variant frag. */
1902 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1904 (*reloc_type == BFD_RELOC_16_PCREL
1905 || *reloc_type == BFD_RELOC_16_PCREL_S2),
1908 /* These relocations can have an addend that won't fit in
1909 4 octets for 64bit assembly. */
1910 if (HAVE_64BIT_GPRS &&
1911 (*reloc_type == BFD_RELOC_16
1912 || *reloc_type == BFD_RELOC_32
1913 || *reloc_type == BFD_RELOC_MIPS_JMP
1914 || *reloc_type == BFD_RELOC_HI16_S
1915 || *reloc_type == BFD_RELOC_LO16
1916 || *reloc_type == BFD_RELOC_GPREL16
1917 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1918 || *reloc_type == BFD_RELOC_GPREL32
1919 || *reloc_type == BFD_RELOC_64
1920 || *reloc_type == BFD_RELOC_CTOR
1921 || *reloc_type == BFD_RELOC_MIPS_SUB
1922 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1923 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1924 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1925 || *reloc_type == BFD_RELOC_MIPS_REL16
1926 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1927 fixp[0]->fx_no_overflow = 1;
1931 struct mips_hi_fixup *hi_fixup;
1933 assert (*reloc_type == BFD_RELOC_HI16_S);
1934 hi_fixup = ((struct mips_hi_fixup *)
1935 xmalloc (sizeof (struct mips_hi_fixup)));
1936 hi_fixup->fixp = fixp[0];
1937 hi_fixup->seg = now_seg;
1938 hi_fixup->next = mips_hi_fixup_list;
1939 mips_hi_fixup_list = hi_fixup;
1942 if (reloc_type[1] != BFD_RELOC_UNUSED)
1944 /* FIXME: This symbol can be one of
1945 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
1946 address_expr->X_op = O_absent;
1947 address_expr->X_add_symbol = 0;
1948 address_expr->X_add_number = 0;
1950 fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal,
1951 4, address_expr, false,
1954 /* These relocations can have an addend that won't fit in
1955 4 octets for 64bit assembly. */
1956 if (HAVE_64BIT_GPRS &&
1957 (*reloc_type == BFD_RELOC_16
1958 || *reloc_type == BFD_RELOC_32
1959 || *reloc_type == BFD_RELOC_MIPS_JMP
1960 || *reloc_type == BFD_RELOC_HI16_S
1961 || *reloc_type == BFD_RELOC_LO16
1962 || *reloc_type == BFD_RELOC_GPREL16
1963 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1964 || *reloc_type == BFD_RELOC_GPREL32
1965 || *reloc_type == BFD_RELOC_64
1966 || *reloc_type == BFD_RELOC_CTOR
1967 || *reloc_type == BFD_RELOC_MIPS_SUB
1968 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
1969 || *reloc_type == BFD_RELOC_MIPS_HIGHER
1970 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
1971 || *reloc_type == BFD_RELOC_MIPS_REL16
1972 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
1973 fixp[1]->fx_no_overflow = 1;
1975 if (reloc_type[2] != BFD_RELOC_UNUSED)
1977 address_expr->X_op = O_absent;
1978 address_expr->X_add_symbol = 0;
1979 address_expr->X_add_number = 0;
1981 fixp[2] = fix_new_exp (frag_now,
1982 f - frag_now->fr_literal, 4,
1983 address_expr, false,
1986 /* These relocations can have an addend that won't fit in
1987 4 octets for 64bit assembly. */
1988 if (HAVE_64BIT_GPRS &&
1989 (*reloc_type == BFD_RELOC_16
1990 || *reloc_type == BFD_RELOC_32
1991 || *reloc_type == BFD_RELOC_MIPS_JMP
1992 || *reloc_type == BFD_RELOC_HI16_S
1993 || *reloc_type == BFD_RELOC_LO16
1994 || *reloc_type == BFD_RELOC_GPREL16
1995 || *reloc_type == BFD_RELOC_MIPS_LITERAL
1996 || *reloc_type == BFD_RELOC_GPREL32
1997 || *reloc_type == BFD_RELOC_64
1998 || *reloc_type == BFD_RELOC_CTOR
1999 || *reloc_type == BFD_RELOC_MIPS_SUB
2000 || *reloc_type == BFD_RELOC_MIPS_HIGHEST
2001 || *reloc_type == BFD_RELOC_MIPS_HIGHER
2002 || *reloc_type == BFD_RELOC_MIPS_SCN_DISP
2003 || *reloc_type == BFD_RELOC_MIPS_REL16
2004 || *reloc_type == BFD_RELOC_MIPS_RELGOT))
2005 fixp[2]->fx_no_overflow = 1;
2012 if (! mips_opts.mips16)
2013 md_number_to_chars (f, ip->insn_opcode, 4);
2014 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2016 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2017 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2023 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2026 md_number_to_chars (f, ip->insn_opcode, 2);
2029 /* Update the register mask information. */
2030 if (! mips_opts.mips16)
2032 if (pinfo & INSN_WRITE_GPR_D)
2033 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2034 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2035 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2036 if (pinfo & INSN_READ_GPR_S)
2037 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2038 if (pinfo & INSN_WRITE_GPR_31)
2039 mips_gprmask |= 1 << RA;
2040 if (pinfo & INSN_WRITE_FPR_D)
2041 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2042 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2043 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2044 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2045 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2046 if ((pinfo & INSN_READ_FPR_R) != 0)
2047 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2048 if (pinfo & INSN_COP)
2050 /* We don't keep enough information to sort these cases out.
2051 The itbl support does keep this information however, although
2052 we currently don't support itbl fprmats as part of the cop
2053 instruction. May want to add this support in the future. */
2055 /* Never set the bit for $0, which is always zero. */
2056 mips_gprmask &= ~1 << 0;
2060 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2061 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2062 & MIPS16OP_MASK_RX);
2063 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2064 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2065 & MIPS16OP_MASK_RY);
2066 if (pinfo & MIPS16_INSN_WRITE_Z)
2067 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2068 & MIPS16OP_MASK_RZ);
2069 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2070 mips_gprmask |= 1 << TREG;
2071 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2072 mips_gprmask |= 1 << SP;
2073 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2074 mips_gprmask |= 1 << RA;
2075 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2076 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2077 if (pinfo & MIPS16_INSN_READ_Z)
2078 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2079 & MIPS16OP_MASK_MOVE32Z);
2080 if (pinfo & MIPS16_INSN_READ_GPR_X)
2081 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2082 & MIPS16OP_MASK_REGR32);
2085 if (place == NULL && ! mips_opts.noreorder)
2087 /* Filling the branch delay slot is more complex. We try to
2088 switch the branch with the previous instruction, which we can
2089 do if the previous instruction does not set up a condition
2090 that the branch tests and if the branch is not itself the
2091 target of any branch. */
2092 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2093 || (pinfo & INSN_COND_BRANCH_DELAY))
2095 if (mips_optimize < 2
2096 /* If we have seen .set volatile or .set nomove, don't
2098 || mips_opts.nomove != 0
2099 /* If we had to emit any NOP instructions, then we
2100 already know we can not swap. */
2102 /* If we don't even know the previous insn, we can not
2104 || ! prev_insn_valid
2105 /* If the previous insn is already in a branch delay
2106 slot, then we can not swap. */
2107 || prev_insn_is_delay_slot
2108 /* If the previous previous insn was in a .set
2109 noreorder, we can't swap. Actually, the MIPS
2110 assembler will swap in this situation. However, gcc
2111 configured -with-gnu-as will generate code like
2117 in which we can not swap the bne and INSN. If gcc is
2118 not configured -with-gnu-as, it does not output the
2119 .set pseudo-ops. We don't have to check
2120 prev_insn_unreordered, because prev_insn_valid will
2121 be 0 in that case. We don't want to use
2122 prev_prev_insn_valid, because we do want to be able
2123 to swap at the start of a function. */
2124 || prev_prev_insn_unreordered
2125 /* If the branch is itself the target of a branch, we
2126 can not swap. We cheat on this; all we check for is
2127 whether there is a label on this instruction. If
2128 there are any branches to anything other than a
2129 label, users must use .set noreorder. */
2130 || insn_labels != NULL
2131 /* If the previous instruction is in a variant frag, we
2132 can not do the swap. This does not apply to the
2133 mips16, which uses variant frags for different
2135 || (! mips_opts.mips16
2136 && prev_insn_frag->fr_type == rs_machine_dependent)
2137 /* If the branch reads the condition codes, we don't
2138 even try to swap, because in the sequence
2143 we can not swap, and I don't feel like handling that
2145 || (! mips_opts.mips16
2146 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2147 && (pinfo & INSN_READ_COND_CODE))
2148 /* We can not swap with an instruction that requires a
2149 delay slot, becase the target of the branch might
2150 interfere with that instruction. */
2151 || (! mips_opts.mips16
2152 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2154 /* Itbl support may require additional care here. */
2155 & (INSN_LOAD_COPROC_DELAY
2156 | INSN_COPROC_MOVE_DELAY
2157 | INSN_WRITE_COND_CODE)))
2158 || (! (hilo_interlocks
2159 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2163 || (! mips_opts.mips16
2165 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2166 || (! mips_opts.mips16
2167 && mips_opts.isa == ISA_MIPS1
2168 /* Itbl support may require additional care here. */
2169 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2170 /* We can not swap with a branch instruction. */
2172 & (INSN_UNCOND_BRANCH_DELAY
2173 | INSN_COND_BRANCH_DELAY
2174 | INSN_COND_BRANCH_LIKELY))
2175 /* We do not swap with a trap instruction, since it
2176 complicates trap handlers to have the trap
2177 instruction be in a delay slot. */
2178 || (prev_pinfo & INSN_TRAP)
2179 /* If the branch reads a register that the previous
2180 instruction sets, we can not swap. */
2181 || (! mips_opts.mips16
2182 && (prev_pinfo & INSN_WRITE_GPR_T)
2183 && insn_uses_reg (ip,
2184 ((prev_insn.insn_opcode >> OP_SH_RT)
2187 || (! mips_opts.mips16
2188 && (prev_pinfo & INSN_WRITE_GPR_D)
2189 && insn_uses_reg (ip,
2190 ((prev_insn.insn_opcode >> OP_SH_RD)
2193 || (mips_opts.mips16
2194 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2195 && insn_uses_reg (ip,
2196 ((prev_insn.insn_opcode
2198 & MIPS16OP_MASK_RX),
2200 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2201 && insn_uses_reg (ip,
2202 ((prev_insn.insn_opcode
2204 & MIPS16OP_MASK_RY),
2206 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2207 && insn_uses_reg (ip,
2208 ((prev_insn.insn_opcode
2210 & MIPS16OP_MASK_RZ),
2212 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2213 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2214 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2215 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2216 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2217 && insn_uses_reg (ip,
2218 MIPS16OP_EXTRACT_REG32R (prev_insn.
2221 /* If the branch writes a register that the previous
2222 instruction sets, we can not swap (we know that
2223 branches write only to RD or to $31). */
2224 || (! mips_opts.mips16
2225 && (prev_pinfo & INSN_WRITE_GPR_T)
2226 && (((pinfo & INSN_WRITE_GPR_D)
2227 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2228 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2229 || ((pinfo & INSN_WRITE_GPR_31)
2230 && (((prev_insn.insn_opcode >> OP_SH_RT)
2233 || (! mips_opts.mips16
2234 && (prev_pinfo & INSN_WRITE_GPR_D)
2235 && (((pinfo & INSN_WRITE_GPR_D)
2236 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2237 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2238 || ((pinfo & INSN_WRITE_GPR_31)
2239 && (((prev_insn.insn_opcode >> OP_SH_RD)
2242 || (mips_opts.mips16
2243 && (pinfo & MIPS16_INSN_WRITE_31)
2244 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2245 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2246 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2248 /* If the branch writes a register that the previous
2249 instruction reads, we can not swap (we know that
2250 branches only write to RD or to $31). */
2251 || (! mips_opts.mips16
2252 && (pinfo & INSN_WRITE_GPR_D)
2253 && insn_uses_reg (&prev_insn,
2254 ((ip->insn_opcode >> OP_SH_RD)
2257 || (! mips_opts.mips16
2258 && (pinfo & INSN_WRITE_GPR_31)
2259 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2260 || (mips_opts.mips16
2261 && (pinfo & MIPS16_INSN_WRITE_31)
2262 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2263 /* If we are generating embedded PIC code, the branch
2264 might be expanded into a sequence which uses $at, so
2265 we can't swap with an instruction which reads it. */
2266 || (mips_pic == EMBEDDED_PIC
2267 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2268 /* If the previous previous instruction has a load
2269 delay, and sets a register that the branch reads, we
2271 || (! mips_opts.mips16
2272 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2273 /* Itbl support may require additional care here. */
2274 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2275 || (! gpr_interlocks
2276 && (prev_prev_insn.insn_mo->pinfo
2277 & INSN_LOAD_MEMORY_DELAY)))
2278 && insn_uses_reg (ip,
2279 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2282 /* If one instruction sets a condition code and the
2283 other one uses a condition code, we can not swap. */
2284 || ((pinfo & INSN_READ_COND_CODE)
2285 && (prev_pinfo & INSN_WRITE_COND_CODE))
2286 || ((pinfo & INSN_WRITE_COND_CODE)
2287 && (prev_pinfo & INSN_READ_COND_CODE))
2288 /* If the previous instruction uses the PC, we can not
2290 || (mips_opts.mips16
2291 && (prev_pinfo & MIPS16_INSN_READ_PC))
2292 /* If the previous instruction was extended, we can not
2294 || (mips_opts.mips16 && prev_insn_extended)
2295 /* If the previous instruction had a fixup in mips16
2296 mode, we can not swap. This normally means that the
2297 previous instruction was a 4 byte branch anyhow. */
2298 || (mips_opts.mips16 && prev_insn_fixp[0])
2299 /* If the previous instruction is a sync, sync.l, or
2300 sync.p, we can not swap. */
2301 || (prev_pinfo & INSN_SYNC))
2303 /* We could do even better for unconditional branches to
2304 portions of this object file; we could pick up the
2305 instruction at the destination, put it in the delay
2306 slot, and bump the destination address. */
2308 /* Update the previous insn information. */
2309 prev_prev_insn = *ip;
2310 prev_insn.insn_mo = &dummy_opcode;
2314 /* It looks like we can actually do the swap. */
2315 if (! mips_opts.mips16)
2320 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2321 memcpy (temp, prev_f, 4);
2322 memcpy (prev_f, f, 4);
2323 memcpy (f, temp, 4);
2324 if (prev_insn_fixp[0])
2326 prev_insn_fixp[0]->fx_frag = frag_now;
2327 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2329 if (prev_insn_fixp[1])
2331 prev_insn_fixp[1]->fx_frag = frag_now;
2332 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2334 if (prev_insn_fixp[2])
2336 prev_insn_fixp[2]->fx_frag = frag_now;
2337 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2341 fixp[0]->fx_frag = prev_insn_frag;
2342 fixp[0]->fx_where = prev_insn_where;
2346 fixp[1]->fx_frag = prev_insn_frag;
2347 fixp[1]->fx_where = prev_insn_where;
2351 fixp[2]->fx_frag = prev_insn_frag;
2352 fixp[2]->fx_where = prev_insn_where;
2360 assert (prev_insn_fixp[0] == NULL);
2361 assert (prev_insn_fixp[1] == NULL);
2362 assert (prev_insn_fixp[2] == NULL);
2363 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2364 memcpy (temp, prev_f, 2);
2365 memcpy (prev_f, f, 2);
2366 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2368 assert (*reloc_type == BFD_RELOC_UNUSED);
2369 memcpy (f, temp, 2);
2373 memcpy (f, f + 2, 2);
2374 memcpy (f + 2, temp, 2);
2378 fixp[0]->fx_frag = prev_insn_frag;
2379 fixp[0]->fx_where = prev_insn_where;
2383 fixp[1]->fx_frag = prev_insn_frag;
2384 fixp[1]->fx_where = prev_insn_where;
2388 fixp[2]->fx_frag = prev_insn_frag;
2389 fixp[2]->fx_where = prev_insn_where;
2393 /* Update the previous insn information; leave prev_insn
2395 prev_prev_insn = *ip;
2397 prev_insn_is_delay_slot = 1;
2399 /* If that was an unconditional branch, forget the previous
2400 insn information. */
2401 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2403 prev_prev_insn.insn_mo = &dummy_opcode;
2404 prev_insn.insn_mo = &dummy_opcode;
2407 prev_insn_fixp[0] = NULL;
2408 prev_insn_fixp[1] = NULL;
2409 prev_insn_fixp[2] = NULL;
2410 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2411 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2412 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2413 prev_insn_extended = 0;
2415 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2417 /* We don't yet optimize a branch likely. What we should do
2418 is look at the target, copy the instruction found there
2419 into the delay slot, and increment the branch to jump to
2420 the next instruction. */
2422 /* Update the previous insn information. */
2423 prev_prev_insn = *ip;
2424 prev_insn.insn_mo = &dummy_opcode;
2425 prev_insn_fixp[0] = NULL;
2426 prev_insn_fixp[1] = NULL;
2427 prev_insn_fixp[2] = NULL;
2428 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2429 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2430 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2431 prev_insn_extended = 0;
2435 /* Update the previous insn information. */
2437 prev_prev_insn.insn_mo = &dummy_opcode;
2439 prev_prev_insn = prev_insn;
2442 /* Any time we see a branch, we always fill the delay slot
2443 immediately; since this insn is not a branch, we know it
2444 is not in a delay slot. */
2445 prev_insn_is_delay_slot = 0;
2447 prev_insn_fixp[0] = fixp[0];
2448 prev_insn_fixp[1] = fixp[1];
2449 prev_insn_fixp[2] = fixp[2];
2450 prev_insn_reloc_type[0] = reloc_type[0];
2451 prev_insn_reloc_type[1] = reloc_type[1];
2452 prev_insn_reloc_type[2] = reloc_type[2];
2453 if (mips_opts.mips16)
2454 prev_insn_extended = (ip->use_extend
2455 || *reloc_type > BFD_RELOC_UNUSED);
2458 prev_prev_insn_unreordered = prev_insn_unreordered;
2459 prev_insn_unreordered = 0;
2460 prev_insn_frag = frag_now;
2461 prev_insn_where = f - frag_now->fr_literal;
2462 prev_insn_valid = 1;
2464 else if (place == NULL)
2466 /* We need to record a bit of information even when we are not
2467 reordering, in order to determine the base address for mips16
2468 PC relative relocs. */
2469 prev_prev_insn = prev_insn;
2471 prev_insn_reloc_type[0] = reloc_type[0];
2472 prev_insn_reloc_type[1] = reloc_type[1];
2473 prev_insn_reloc_type[2] = reloc_type[2];
2474 prev_prev_insn_unreordered = prev_insn_unreordered;
2475 prev_insn_unreordered = 1;
2478 /* We just output an insn, so the next one doesn't have a label. */
2479 mips_clear_insn_labels ();
2481 /* We must ensure that a fixup associated with an unmatched %hi
2482 reloc does not become a variant frag. Otherwise, the
2483 rearrangement of %hi relocs in frob_file may confuse
2487 frag_wane (frag_now);
2492 /* This function forgets that there was any previous instruction or
2493 label. If PRESERVE is non-zero, it remembers enough information to
2494 know whether nops are needed before a noreorder section. */
2497 mips_no_prev_insn (preserve)
2502 prev_insn.insn_mo = &dummy_opcode;
2503 prev_prev_insn.insn_mo = &dummy_opcode;
2504 prev_nop_frag = NULL;
2505 prev_nop_frag_holds = 0;
2506 prev_nop_frag_required = 0;
2507 prev_nop_frag_since = 0;
2509 prev_insn_valid = 0;
2510 prev_insn_is_delay_slot = 0;
2511 prev_insn_unreordered = 0;
2512 prev_insn_extended = 0;
2513 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2514 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2515 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2516 prev_prev_insn_unreordered = 0;
2517 mips_clear_insn_labels ();
2520 /* This function must be called whenever we turn on noreorder or emit
2521 something other than instructions. It inserts any NOPS which might
2522 be needed by the previous instruction, and clears the information
2523 kept for the previous instructions. The INSNS parameter is true if
2524 instructions are to follow. */
2527 mips_emit_delays (insns)
2530 if (! mips_opts.noreorder)
2535 if ((! mips_opts.mips16
2536 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2537 && (! cop_interlocks
2538 && (prev_insn.insn_mo->pinfo
2539 & (INSN_LOAD_COPROC_DELAY
2540 | INSN_COPROC_MOVE_DELAY
2541 | INSN_WRITE_COND_CODE))))
2542 || (! hilo_interlocks
2543 && (prev_insn.insn_mo->pinfo
2546 || (! mips_opts.mips16
2548 && (prev_insn.insn_mo->pinfo
2549 & INSN_LOAD_MEMORY_DELAY))
2550 || (! mips_opts.mips16
2551 && mips_opts.isa == ISA_MIPS1
2552 && (prev_insn.insn_mo->pinfo
2553 & INSN_COPROC_MEMORY_DELAY)))
2555 /* Itbl support may require additional care here. */
2557 if ((! mips_opts.mips16
2558 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2559 && (! cop_interlocks
2560 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2561 || (! hilo_interlocks
2562 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2563 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2566 if (prev_insn_unreordered)
2569 else if ((! mips_opts.mips16
2570 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2571 && (! cop_interlocks
2572 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2573 || (! hilo_interlocks
2574 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2575 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2577 /* Itbl support may require additional care here. */
2578 if (! prev_prev_insn_unreordered)
2584 struct insn_label_list *l;
2588 /* Record the frag which holds the nop instructions, so
2589 that we can remove them if we don't need them. */
2590 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2591 prev_nop_frag = frag_now;
2592 prev_nop_frag_holds = nops;
2593 prev_nop_frag_required = 0;
2594 prev_nop_frag_since = 0;
2597 for (; nops > 0; --nops)
2602 /* Move on to a new frag, so that it is safe to simply
2603 decrease the size of prev_nop_frag. */
2604 frag_wane (frag_now);
2608 for (l = insn_labels; l != NULL; l = l->next)
2612 assert (S_GET_SEGMENT (l->label) == now_seg);
2613 symbol_set_frag (l->label, frag_now);
2614 val = (valueT) frag_now_fix ();
2615 /* mips16 text labels are stored as odd. */
2616 if (mips_opts.mips16)
2618 S_SET_VALUE (l->label, val);
2623 /* Mark instruction labels in mips16 mode. */
2625 mips16_mark_labels ();
2627 mips_no_prev_insn (insns);
2630 /* Build an instruction created by a macro expansion. This is passed
2631 a pointer to the count of instructions created so far, an
2632 expression, the name of the instruction to build, an operand format
2633 string, and corresponding arguments. */
2637 macro_build (char *place,
2645 macro_build (place, counter, ep, name, fmt, va_alist)
2654 struct mips_cl_insn insn;
2655 bfd_reloc_code_real_type r[3];
2659 va_start (args, fmt);
2665 * If the macro is about to expand into a second instruction,
2666 * print a warning if needed. We need to pass ip as a parameter
2667 * to generate a better warning message here...
2669 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2670 as_warn (_("Macro instruction expanded into multiple instructions"));
2673 * If the macro is about to expand into a second instruction,
2674 * and it is in a delay slot, print a warning.
2678 && mips_opts.noreorder
2679 && (prev_prev_insn.insn_mo->pinfo
2680 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY
2681 | INSN_COND_BRANCH_LIKELY)) != 0)
2682 as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot"));
2685 ++*counter; /* bump instruction counter */
2687 if (mips_opts.mips16)
2689 mips16_macro_build (place, counter, ep, name, fmt, args);
2694 r[0] = BFD_RELOC_UNUSED;
2695 r[1] = BFD_RELOC_UNUSED;
2696 r[2] = BFD_RELOC_UNUSED;
2697 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2698 assert (insn.insn_mo);
2699 assert (strcmp (name, insn.insn_mo->name) == 0);
2701 /* Search until we get a match for NAME. */
2704 /* It is assumed here that macros will never generate
2705 MDMX or MIPS-3D instructions. */
2706 if (strcmp (fmt, insn.insn_mo->args) == 0
2707 && insn.insn_mo->pinfo != INSN_MACRO
2708 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2709 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2713 assert (insn.insn_mo->name);
2714 assert (strcmp (name, insn.insn_mo->name) == 0);
2717 insn.insn_opcode = insn.insn_mo->match;
2733 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2737 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2742 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2747 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2752 int tmp = va_arg (args, int);
2754 insn.insn_opcode |= tmp << OP_SH_RT;
2755 insn.insn_opcode |= tmp << OP_SH_RD;
2761 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2768 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2772 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2776 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2780 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2784 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2791 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2797 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2798 assert (*r == BFD_RELOC_GPREL16
2799 || *r == BFD_RELOC_MIPS_LITERAL
2800 || *r == BFD_RELOC_MIPS_HIGHER
2801 || *r == BFD_RELOC_HI16_S
2802 || *r == BFD_RELOC_LO16
2803 || *r == BFD_RELOC_MIPS_GOT16
2804 || *r == BFD_RELOC_MIPS_CALL16
2805 || *r == BFD_RELOC_MIPS_GOT_DISP
2806 || *r == BFD_RELOC_MIPS_GOT_PAGE
2807 || *r == BFD_RELOC_MIPS_GOT_OFST
2808 || *r == BFD_RELOC_MIPS_GOT_LO16
2809 || *r == BFD_RELOC_MIPS_CALL_LO16
2810 || (ep->X_op == O_subtract
2811 && *r == BFD_RELOC_PCREL_LO16));
2815 *r = (bfd_reloc_code_real_type) va_arg (args, int);
2817 && (ep->X_op == O_constant
2818 || (ep->X_op == O_symbol
2819 && (*r == BFD_RELOC_MIPS_HIGHEST
2820 || *r == BFD_RELOC_HI16_S
2821 || *r == BFD_RELOC_HI16
2822 || *r == BFD_RELOC_GPREL16
2823 || *r == BFD_RELOC_MIPS_GOT_HI16
2824 || *r == BFD_RELOC_MIPS_CALL_HI16))
2825 || (ep->X_op == O_subtract
2826 && *r == BFD_RELOC_PCREL_HI16_S)));
2830 assert (ep != NULL);
2832 * This allows macro() to pass an immediate expression for
2833 * creating short branches without creating a symbol.
2834 * Note that the expression still might come from the assembly
2835 * input, in which case the value is not checked for range nor
2836 * is a relocation entry generated (yuck).
2838 if (ep->X_op == O_constant)
2840 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2844 if (mips_pic == EMBEDDED_PIC)
2845 *r = BFD_RELOC_16_PCREL_S2;
2847 *r = BFD_RELOC_16_PCREL;
2851 assert (ep != NULL);
2852 *r = BFD_RELOC_MIPS_JMP;
2856 insn.insn_opcode |= va_arg (args, unsigned long);
2865 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2867 append_insn (place, &insn, ep, r, false);
2871 mips16_macro_build (place, counter, ep, name, fmt, args)
2873 int *counter ATTRIBUTE_UNUSED;
2879 struct mips_cl_insn insn;
2880 bfd_reloc_code_real_type r[3]
2881 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2883 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2884 assert (insn.insn_mo);
2885 assert (strcmp (name, insn.insn_mo->name) == 0);
2887 while (strcmp (fmt, insn.insn_mo->args) != 0
2888 || insn.insn_mo->pinfo == INSN_MACRO)
2891 assert (insn.insn_mo->name);
2892 assert (strcmp (name, insn.insn_mo->name) == 0);
2895 insn.insn_opcode = insn.insn_mo->match;
2896 insn.use_extend = false;
2915 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2920 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2924 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2928 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2938 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2945 regno = va_arg (args, int);
2946 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2947 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2968 assert (ep != NULL);
2970 if (ep->X_op != O_constant)
2971 *r = (int) BFD_RELOC_UNUSED + c;
2974 mips16_immed (NULL, 0, c, ep->X_add_number, false, false,
2975 false, &insn.insn_opcode, &insn.use_extend,
2978 *r = BFD_RELOC_UNUSED;
2984 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2991 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2993 append_insn (place, &insn, ep, r, false);
2997 * Generate a "jalr" instruction with a relocation hint to the called
2998 * function. This occurs in NewABI PIC code.
3001 macro_build_jalr (icnt, ep)
3007 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s",
3010 fix_new_exp (frag_now, 0, 0, ep, false, BFD_RELOC_MIPS_JALR);
3014 * Generate a "lui" instruction.
3017 macro_build_lui (place, counter, ep, regnum)
3023 expressionS high_expr;
3024 struct mips_cl_insn insn;
3025 bfd_reloc_code_real_type r[3]
3026 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3027 CONST char *name = "lui";
3028 CONST char *fmt = "t,u";
3030 assert (! mips_opts.mips16);
3036 high_expr.X_op = O_constant;
3037 high_expr.X_add_number = ep->X_add_number;
3040 if (high_expr.X_op == O_constant)
3042 /* we can compute the instruction now without a relocation entry */
3043 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3045 *r = BFD_RELOC_UNUSED;
3047 else if (! HAVE_NEWABI)
3049 assert (ep->X_op == O_symbol);
3050 /* _gp_disp is a special case, used from s_cpload. */
3051 assert (mips_pic == NO_PIC
3052 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
3053 *r = BFD_RELOC_HI16_S;
3057 * If the macro is about to expand into a second instruction,
3058 * print a warning if needed. We need to pass ip as a parameter
3059 * to generate a better warning message here...
3061 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
3062 as_warn (_("Macro instruction expanded into multiple instructions"));
3065 ++*counter; /* bump instruction counter */
3067 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3068 assert (insn.insn_mo);
3069 assert (strcmp (name, insn.insn_mo->name) == 0);
3070 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3072 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3073 if (*r == BFD_RELOC_UNUSED)
3075 insn.insn_opcode |= high_expr.X_add_number;
3076 append_insn (place, &insn, NULL, r, false);
3079 append_insn (place, &insn, &high_expr, r, false);
3083 * Generates code to set the $at register to true (one)
3084 * if reg is less than the immediate expression.
3087 set_at (counter, reg, unsignedp)
3092 if (imm_expr.X_op == O_constant
3093 && imm_expr.X_add_number >= -0x8000
3094 && imm_expr.X_add_number < 0x8000)
3095 macro_build ((char *) NULL, counter, &imm_expr,
3096 unsignedp ? "sltiu" : "slti",
3097 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
3100 load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
3101 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3102 unsignedp ? "sltu" : "slt",
3103 "d,v,t", AT, reg, AT);
3107 /* Warn if an expression is not a constant. */
3110 check_absolute_expr (ip, ex)
3111 struct mips_cl_insn *ip;
3114 if (ex->X_op == O_big)
3115 as_bad (_("unsupported large constant"));
3116 else if (ex->X_op != O_constant)
3117 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3120 /* Count the leading zeroes by performing a binary chop. This is a
3121 bulky bit of source, but performance is a LOT better for the
3122 majority of values than a simple loop to count the bits:
3123 for (lcnt = 0; (lcnt < 32); lcnt++)
3124 if ((v) & (1 << (31 - lcnt)))
3126 However it is not code size friendly, and the gain will drop a bit
3127 on certain cached systems.
3129 #define COUNT_TOP_ZEROES(v) \
3130 (((v) & ~0xffff) == 0 \
3131 ? ((v) & ~0xff) == 0 \
3132 ? ((v) & ~0xf) == 0 \
3133 ? ((v) & ~0x3) == 0 \
3134 ? ((v) & ~0x1) == 0 \
3139 : ((v) & ~0x7) == 0 \
3142 : ((v) & ~0x3f) == 0 \
3143 ? ((v) & ~0x1f) == 0 \
3146 : ((v) & ~0x7f) == 0 \
3149 : ((v) & ~0xfff) == 0 \
3150 ? ((v) & ~0x3ff) == 0 \
3151 ? ((v) & ~0x1ff) == 0 \
3154 : ((v) & ~0x7ff) == 0 \
3157 : ((v) & ~0x3fff) == 0 \
3158 ? ((v) & ~0x1fff) == 0 \
3161 : ((v) & ~0x7fff) == 0 \
3164 : ((v) & ~0xffffff) == 0 \
3165 ? ((v) & ~0xfffff) == 0 \
3166 ? ((v) & ~0x3ffff) == 0 \
3167 ? ((v) & ~0x1ffff) == 0 \
3170 : ((v) & ~0x7ffff) == 0 \
3173 : ((v) & ~0x3fffff) == 0 \
3174 ? ((v) & ~0x1fffff) == 0 \
3177 : ((v) & ~0x7fffff) == 0 \
3180 : ((v) & ~0xfffffff) == 0 \
3181 ? ((v) & ~0x3ffffff) == 0 \
3182 ? ((v) & ~0x1ffffff) == 0 \
3185 : ((v) & ~0x7ffffff) == 0 \
3188 : ((v) & ~0x3fffffff) == 0 \
3189 ? ((v) & ~0x1fffffff) == 0 \
3192 : ((v) & ~0x7fffffff) == 0 \
3196 /* Is the given value a sign-extended 32-bit value? */
3197 #define IS_SEXT_32BIT_NUM(x) \
3198 (((x) &~ (offsetT) 0x7fffffff) == 0 \
3199 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
3202 * This routine generates the least number of instructions neccessary to load
3203 * an absolute expression value into a register.
3206 load_register (counter, reg, ep, dbl)
3213 expressionS hi32, lo32;
3215 if (ep->X_op != O_big)
3217 assert (ep->X_op == O_constant);
3218 if (ep->X_add_number < 0x8000
3219 && (ep->X_add_number >= 0
3220 || (ep->X_add_number >= -0x8000
3223 || sizeof (ep->X_add_number) > 4))))
3225 /* We can handle 16 bit signed values with an addiu to
3226 $zero. No need to ever use daddiu here, since $zero and
3227 the result are always correct in 32 bit mode. */
3228 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3229 (int) BFD_RELOC_LO16);
3232 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3234 /* We can handle 16 bit unsigned values with an ori to
3236 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3237 (int) BFD_RELOC_LO16);
3240 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)
3243 || sizeof (ep->X_add_number) > 4
3244 || (ep->X_add_number & 0x80000000) == 0))
3245 || ((HAVE_32BIT_GPRS || ! dbl)
3246 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3249 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3250 == ~ (offsetT) 0xffffffff)))
3252 /* 32 bit values require an lui. */
3253 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3254 (int) BFD_RELOC_HI16);
3255 if ((ep->X_add_number & 0xffff) != 0)
3256 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3257 (int) BFD_RELOC_LO16);
3262 /* The value is larger than 32 bits. */
3264 if (HAVE_32BIT_GPRS)
3266 as_bad (_("Number (0x%lx) larger than 32 bits"),
3267 (unsigned long) ep->X_add_number);
3268 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3269 (int) BFD_RELOC_LO16);
3273 if (ep->X_op != O_big)
3276 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3277 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3278 hi32.X_add_number &= 0xffffffff;
3280 lo32.X_add_number &= 0xffffffff;
3284 assert (ep->X_add_number > 2);
3285 if (ep->X_add_number == 3)
3286 generic_bignum[3] = 0;
3287 else if (ep->X_add_number > 4)
3288 as_bad (_("Number larger than 64 bits"));
3289 lo32.X_op = O_constant;
3290 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3291 hi32.X_op = O_constant;
3292 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3295 if (hi32.X_add_number == 0)
3300 unsigned long hi, lo;
3302 if (hi32.X_add_number == (offsetT) 0xffffffff)
3304 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3306 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3307 reg, 0, (int) BFD_RELOC_LO16);
3310 if (lo32.X_add_number & 0x80000000)
3312 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3313 (int) BFD_RELOC_HI16);
3314 if (lo32.X_add_number & 0xffff)
3315 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3316 reg, reg, (int) BFD_RELOC_LO16);
3321 /* Check for 16bit shifted constant. We know that hi32 is
3322 non-zero, so start the mask on the first bit of the hi32
3327 unsigned long himask, lomask;
3331 himask = 0xffff >> (32 - shift);
3332 lomask = (0xffff << shift) & 0xffffffff;
3336 himask = 0xffff << (shift - 32);
3339 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3340 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3344 tmp.X_op = O_constant;
3346 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3347 | (lo32.X_add_number >> shift));
3349 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3350 macro_build ((char *) NULL, counter, &tmp,
3351 "ori", "t,r,i", reg, 0,
3352 (int) BFD_RELOC_LO16);
3353 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3354 (shift >= 32) ? "dsll32" : "dsll",
3356 (shift >= 32) ? shift - 32 : shift);
3361 while (shift <= (64 - 16));
3363 /* Find the bit number of the lowest one bit, and store the
3364 shifted value in hi/lo. */
3365 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3366 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3370 while ((lo & 1) == 0)
3375 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3381 while ((hi & 1) == 0)
3390 /* Optimize if the shifted value is a (power of 2) - 1. */
3391 if ((hi == 0 && ((lo + 1) & lo) == 0)
3392 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3394 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3399 /* This instruction will set the register to be all
3401 tmp.X_op = O_constant;
3402 tmp.X_add_number = (offsetT) -1;
3403 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3404 reg, 0, (int) BFD_RELOC_LO16);
3408 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3409 (bit >= 32) ? "dsll32" : "dsll",
3411 (bit >= 32) ? bit - 32 : bit);
3413 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3414 (shift >= 32) ? "dsrl32" : "dsrl",
3416 (shift >= 32) ? shift - 32 : shift);
3421 /* Sign extend hi32 before calling load_register, because we can
3422 generally get better code when we load a sign extended value. */
3423 if ((hi32.X_add_number & 0x80000000) != 0)
3424 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3425 load_register (counter, reg, &hi32, 0);
3428 if ((lo32.X_add_number & 0xffff0000) == 0)
3432 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3433 "dsll32", "d,w,<", reg, freg, 0);
3441 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3443 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3444 (int) BFD_RELOC_HI16);
3445 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3446 "dsrl32", "d,w,<", reg, reg, 0);
3452 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3453 "d,w,<", reg, freg, 16);
3457 mid16.X_add_number >>= 16;
3458 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3459 freg, (int) BFD_RELOC_LO16);
3460 macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll",
3461 "d,w,<", reg, reg, 16);
3464 if ((lo32.X_add_number & 0xffff) != 0)
3465 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3466 (int) BFD_RELOC_LO16);
3469 /* Load an address into a register. */
3472 load_address (counter, reg, ep, used_at)
3480 if (ep->X_op != O_constant
3481 && ep->X_op != O_symbol)
3483 as_bad (_("expression too complex"));
3484 ep->X_op = O_constant;
3487 if (ep->X_op == O_constant)
3489 load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
3493 if (mips_pic == NO_PIC)
3495 /* If this is a reference to a GP relative symbol, we want
3496 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3498 lui $reg,<sym> (BFD_RELOC_HI16_S)
3499 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3500 If we have an addend, we always use the latter form.
3502 With 64bit address space and a usable $at we want
3503 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3504 lui $at,<sym> (BFD_RELOC_HI16_S)
3505 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3506 daddiu $at,<sym> (BFD_RELOC_LO16)
3510 If $at is already in use, we use an path which is suboptimal
3511 on superscalar processors.
3512 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3513 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3515 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3517 daddiu $reg,<sym> (BFD_RELOC_LO16)
3519 if (HAVE_64BIT_ADDRESSES)
3521 /* We don't do GP optimization for now because RELAX_ENCODE can't
3522 hold the data for such large chunks. */
3526 macro_build (p, counter, ep, "lui", "t,u",
3527 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3528 macro_build (p, counter, ep, "lui", "t,u",
3529 AT, (int) BFD_RELOC_HI16_S);
3530 macro_build (p, counter, ep, "daddiu", "t,r,j",
3531 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3532 macro_build (p, counter, ep, "daddiu", "t,r,j",
3533 AT, AT, (int) BFD_RELOC_LO16);
3534 macro_build (p, counter, (expressionS *) NULL, "dsll32",
3535 "d,w,<", reg, reg, 0);
3536 macro_build (p, counter, (expressionS *) NULL, "dadd",
3537 "d,v,t", reg, reg, AT);
3542 macro_build (p, counter, ep, "lui", "t,u",
3543 reg, (int) BFD_RELOC_MIPS_HIGHEST);
3544 macro_build (p, counter, ep, "daddiu", "t,r,j",
3545 reg, reg, (int) BFD_RELOC_MIPS_HIGHER);
3546 macro_build (p, counter, (expressionS *) NULL, "dsll",
3547 "d,w,<", reg, reg, 16);
3548 macro_build (p, counter, ep, "daddiu", "t,r,j",
3549 reg, reg, (int) BFD_RELOC_HI16_S);
3550 macro_build (p, counter, (expressionS *) NULL, "dsll",
3551 "d,w,<", reg, reg, 16);
3552 macro_build (p, counter, ep, "daddiu", "t,r,j",
3553 reg, reg, (int) BFD_RELOC_LO16);
3558 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3559 && ! nopic_need_relax (ep->X_add_symbol, 1))
3562 macro_build ((char *) NULL, counter, ep,
3563 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3564 reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3565 p = frag_var (rs_machine_dependent, 8, 0,
3566 RELAX_ENCODE (4, 8, 0, 4, 0,
3567 mips_opts.warn_about_macros),
3568 ep->X_add_symbol, 0, NULL);
3570 macro_build_lui (p, counter, ep, reg);
3573 macro_build (p, counter, ep,
3574 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3575 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3578 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3582 /* If this is a reference to an external symbol, we want
3583 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3585 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3587 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3588 If there is a constant, it must be added in after. */
3589 ex.X_add_number = ep->X_add_number;
3590 ep->X_add_number = 0;
3592 macro_build ((char *) NULL, counter, ep,
3593 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
3594 reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3595 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3596 p = frag_var (rs_machine_dependent, 4, 0,
3597 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3598 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3599 macro_build (p, counter, ep,
3600 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3601 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3602 if (ex.X_add_number != 0)
3604 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3605 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3606 ex.X_op = O_constant;
3607 macro_build ((char *) NULL, counter, &ex,
3608 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3609 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3612 else if (mips_pic == SVR4_PIC)
3617 /* This is the large GOT case. If this is a reference to an
3618 external symbol, we want
3619 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3621 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3622 Otherwise, for a reference to a local symbol, we want
3623 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3625 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3626 If we have NewABI, we want
3627 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3628 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3629 If there is a constant, it must be added in after. */
3630 ex.X_add_number = ep->X_add_number;
3631 ep->X_add_number = 0;
3634 macro_build ((char *) NULL, counter, ep,
3635 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3636 (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3637 macro_build (p, counter, ep,
3638 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
3639 reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST);
3643 if (reg_needs_delay (mips_gp_register))
3648 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3649 (int) BFD_RELOC_MIPS_GOT_HI16);
3650 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3651 HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg,
3652 reg, mips_gp_register);
3653 macro_build ((char *) NULL, counter, ep,
3654 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3655 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3656 p = frag_var (rs_machine_dependent, 12 + off, 0,
3657 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3658 mips_opts.warn_about_macros),
3659 ep->X_add_symbol, 0, NULL);
3662 /* We need a nop before loading from $gp. This special
3663 check is required because the lui which starts the main
3664 instruction stream does not refer to $gp, and so will not
3665 insert the nop which may be required. */
3666 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3669 macro_build (p, counter, ep,
3670 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg,
3671 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
3673 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3675 macro_build (p, counter, ep,
3676 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3677 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3680 if (ex.X_add_number != 0)
3682 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3683 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3684 ex.X_op = O_constant;
3685 macro_build ((char *) NULL, counter, &ex,
3686 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3687 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3690 else if (mips_pic == EMBEDDED_PIC)
3693 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3695 macro_build ((char *) NULL, counter, ep,
3696 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3697 "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16);
3703 /* Move the contents of register SOURCE into register DEST. */
3706 move_register (counter, dest, source)
3711 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3712 HAVE_32BIT_GPRS ? "addu" : "daddu",
3713 "d,v,t", dest, source, 0);
3718 * This routine implements the seemingly endless macro or synthesized
3719 * instructions and addressing modes in the mips assembly language. Many
3720 * of these macros are simple and are similar to each other. These could
3721 * probably be handled by some kind of table or grammer aproach instead of
3722 * this verbose method. Others are not simple macros but are more like
3723 * optimizing code generation.
3724 * One interesting optimization is when several store macros appear
3725 * consecutivly that would load AT with the upper half of the same address.
3726 * The ensuing load upper instructions are ommited. This implies some kind
3727 * of global optimization. We currently only optimize within a single macro.
3728 * For many of the load and store macros if the address is specified as a
3729 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3730 * first load register 'at' with zero and use it as the base register. The
3731 * mips assembler simply uses register $zero. Just one tiny optimization
3736 struct mips_cl_insn *ip;
3738 register int treg, sreg, dreg, breg;
3754 bfd_reloc_code_real_type r;
3755 int hold_mips_optimize;
3757 assert (! mips_opts.mips16);
3759 treg = (ip->insn_opcode >> 16) & 0x1f;
3760 dreg = (ip->insn_opcode >> 11) & 0x1f;
3761 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3762 mask = ip->insn_mo->mask;
3764 expr1.X_op = O_constant;
3765 expr1.X_op_symbol = NULL;
3766 expr1.X_add_symbol = NULL;
3767 expr1.X_add_number = 1;
3779 mips_emit_delays (true);
3780 ++mips_opts.noreorder;
3781 mips_any_noreorder = 1;
3783 expr1.X_add_number = 8;
3784 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3786 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
3789 move_register (&icnt, dreg, sreg);
3790 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
3791 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3793 --mips_opts.noreorder;
3814 if (imm_expr.X_op == O_constant
3815 && imm_expr.X_add_number >= -0x8000
3816 && imm_expr.X_add_number < 0x8000)
3818 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3819 (int) BFD_RELOC_LO16);
3822 load_register (&icnt, AT, &imm_expr, dbl);
3823 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3843 if (imm_expr.X_op == O_constant
3844 && imm_expr.X_add_number >= 0
3845 && imm_expr.X_add_number < 0x10000)
3847 if (mask != M_NOR_I)
3848 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3849 sreg, (int) BFD_RELOC_LO16);
3852 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3853 treg, sreg, (int) BFD_RELOC_LO16);
3854 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor",
3855 "d,v,t", treg, treg, 0);
3860 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3861 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t",
3879 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3881 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3885 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
3886 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3894 macro_build ((char *) NULL, &icnt, &offset_expr,
3895 likely ? "bgezl" : "bgez", "s,p", sreg);
3900 macro_build ((char *) NULL, &icnt, &offset_expr,
3901 likely ? "blezl" : "blez", "s,p", treg);
3904 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
3906 macro_build ((char *) NULL, &icnt, &offset_expr,
3907 likely ? "beql" : "beq", "s,t,p", AT, 0);
3913 /* check for > max integer */
3914 maxnum = 0x7fffffff;
3915 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3922 if (imm_expr.X_op == O_constant
3923 && imm_expr.X_add_number >= maxnum
3924 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3927 /* result is always false */
3931 as_warn (_("Branch %s is always false (nop)"),
3933 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop",
3939 as_warn (_("Branch likely %s is always false"),
3941 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3946 if (imm_expr.X_op != O_constant)
3947 as_bad (_("Unsupported large constant"));
3948 ++imm_expr.X_add_number;
3952 if (mask == M_BGEL_I)
3954 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3956 macro_build ((char *) NULL, &icnt, &offset_expr,
3957 likely ? "bgezl" : "bgez", "s,p", sreg);
3960 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3962 macro_build ((char *) NULL, &icnt, &offset_expr,
3963 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3966 maxnum = 0x7fffffff;
3967 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3974 maxnum = - maxnum - 1;
3975 if (imm_expr.X_op == O_constant
3976 && imm_expr.X_add_number <= maxnum
3977 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3980 /* result is always true */
3981 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3982 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
3985 set_at (&icnt, sreg, 0);
3986 macro_build ((char *) NULL, &icnt, &offset_expr,
3987 likely ? "beql" : "beq", "s,t,p", AT, 0);
3997 macro_build ((char *) NULL, &icnt, &offset_expr,
3998 likely ? "beql" : "beq", "s,t,p", 0, treg);
4001 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4002 "d,v,t", AT, sreg, treg);
4003 macro_build ((char *) NULL, &icnt, &offset_expr,
4004 likely ? "beql" : "beq", "s,t,p", AT, 0);
4012 && imm_expr.X_op == O_constant
4013 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4015 if (imm_expr.X_op != O_constant)
4016 as_bad (_("Unsupported large constant"));
4017 ++imm_expr.X_add_number;
4021 if (mask == M_BGEUL_I)
4023 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4025 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4027 macro_build ((char *) NULL, &icnt, &offset_expr,
4028 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4031 set_at (&icnt, sreg, 1);
4032 macro_build ((char *) NULL, &icnt, &offset_expr,
4033 likely ? "beql" : "beq", "s,t,p", AT, 0);
4041 macro_build ((char *) NULL, &icnt, &offset_expr,
4042 likely ? "bgtzl" : "bgtz", "s,p", sreg);
4047 macro_build ((char *) NULL, &icnt, &offset_expr,
4048 likely ? "bltzl" : "bltz", "s,p", treg);
4051 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4053 macro_build ((char *) NULL, &icnt, &offset_expr,
4054 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4062 macro_build ((char *) NULL, &icnt, &offset_expr,
4063 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
4068 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4069 "d,v,t", AT, treg, sreg);
4070 macro_build ((char *) NULL, &icnt, &offset_expr,
4071 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4079 macro_build ((char *) NULL, &icnt, &offset_expr,
4080 likely ? "blezl" : "blez", "s,p", sreg);
4085 macro_build ((char *) NULL, &icnt, &offset_expr,
4086 likely ? "bgezl" : "bgez", "s,p", treg);
4089 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4091 macro_build ((char *) NULL, &icnt, &offset_expr,
4092 likely ? "beql" : "beq", "s,t,p", AT, 0);
4098 maxnum = 0x7fffffff;
4099 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4106 if (imm_expr.X_op == O_constant
4107 && imm_expr.X_add_number >= maxnum
4108 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4110 if (imm_expr.X_op != O_constant)
4111 as_bad (_("Unsupported large constant"));
4112 ++imm_expr.X_add_number;
4116 if (mask == M_BLTL_I)
4118 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4120 macro_build ((char *) NULL, &icnt, &offset_expr,
4121 likely ? "bltzl" : "bltz", "s,p", sreg);
4124 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4126 macro_build ((char *) NULL, &icnt, &offset_expr,
4127 likely ? "blezl" : "blez", "s,p", sreg);
4130 set_at (&icnt, sreg, 0);
4131 macro_build ((char *) NULL, &icnt, &offset_expr,
4132 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4140 macro_build ((char *) NULL, &icnt, &offset_expr,
4141 likely ? "beql" : "beq", "s,t,p", sreg, 0);
4146 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4147 "d,v,t", AT, treg, sreg);
4148 macro_build ((char *) NULL, &icnt, &offset_expr,
4149 likely ? "beql" : "beq", "s,t,p", AT, 0);
4157 && imm_expr.X_op == O_constant
4158 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4160 if (imm_expr.X_op != O_constant)
4161 as_bad (_("Unsupported large constant"));
4162 ++imm_expr.X_add_number;
4166 if (mask == M_BLTUL_I)
4168 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4170 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4172 macro_build ((char *) NULL, &icnt, &offset_expr,
4173 likely ? "beql" : "beq",
4177 set_at (&icnt, sreg, 1);
4178 macro_build ((char *) NULL, &icnt, &offset_expr,
4179 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4187 macro_build ((char *) NULL, &icnt, &offset_expr,
4188 likely ? "bltzl" : "bltz", "s,p", sreg);
4193 macro_build ((char *) NULL, &icnt, &offset_expr,
4194 likely ? "bgtzl" : "bgtz", "s,p", treg);
4197 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
4199 macro_build ((char *) NULL, &icnt, &offset_expr,
4200 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4210 macro_build ((char *) NULL, &icnt, &offset_expr,
4211 likely ? "bnel" : "bne", "s,t,p", 0, treg);
4214 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
4217 macro_build ((char *) NULL, &icnt, &offset_expr,
4218 likely ? "bnel" : "bne", "s,t,p", AT, 0);
4233 as_warn (_("Divide by zero."));
4235 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4238 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4243 mips_emit_delays (true);
4244 ++mips_opts.noreorder;
4245 mips_any_noreorder = 1;
4248 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4250 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4251 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4255 expr1.X_add_number = 8;
4256 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4257 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4258 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4259 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4262 expr1.X_add_number = -1;
4263 macro_build ((char *) NULL, &icnt, &expr1,
4264 dbl ? "daddiu" : "addiu",
4265 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4266 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4267 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4270 expr1.X_add_number = 1;
4271 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4272 (int) BFD_RELOC_LO16);
4273 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32",
4274 "d,w,<", AT, AT, 31);
4278 expr1.X_add_number = 0x80000000;
4279 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4280 (int) BFD_RELOC_HI16);
4284 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4286 /* We want to close the noreorder block as soon as possible, so
4287 that later insns are available for delay slot filling. */
4288 --mips_opts.noreorder;
4292 expr1.X_add_number = 8;
4293 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4294 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
4297 /* We want to close the noreorder block as soon as possible, so
4298 that later insns are available for delay slot filling. */
4299 --mips_opts.noreorder;
4301 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4304 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg);
4343 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4345 as_warn (_("Divide by zero."));
4347 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4350 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4354 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4356 if (strcmp (s2, "mflo") == 0)
4357 move_register (&icnt, dreg, sreg);
4359 move_register (&icnt, dreg, 0);
4362 if (imm_expr.X_op == O_constant
4363 && imm_expr.X_add_number == -1
4364 && s[strlen (s) - 1] != 'u')
4366 if (strcmp (s2, "mflo") == 0)
4368 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4369 dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4372 move_register (&icnt, dreg, 0);
4376 load_register (&icnt, AT, &imm_expr, dbl);
4377 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4379 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4398 mips_emit_delays (true);
4399 ++mips_opts.noreorder;
4400 mips_any_noreorder = 1;
4403 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq",
4405 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4407 /* We want to close the noreorder block as soon as possible, so
4408 that later insns are available for delay slot filling. */
4409 --mips_opts.noreorder;
4413 expr1.X_add_number = 8;
4414 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4415 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t",
4418 /* We want to close the noreorder block as soon as possible, so
4419 that later insns are available for delay slot filling. */
4420 --mips_opts.noreorder;
4421 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
4424 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg);
4430 /* Load the address of a symbol into a register. If breg is not
4431 zero, we then add a base register to it. */
4433 if (dbl && HAVE_32BIT_GPRS)
4434 as_warn (_("dla used to load 32-bit register"));
4436 if (! dbl && HAVE_64BIT_OBJECTS)
4437 as_warn (_("la used to load 64-bit address"));
4450 /* When generating embedded PIC code, we permit expressions of
4453 la $treg,foo-bar($breg)
4454 where bar is an address in the current section. These are used
4455 when getting the addresses of functions. We don't permit
4456 X_add_number to be non-zero, because if the symbol is
4457 external the relaxing code needs to know that any addend is
4458 purely the offset to X_op_symbol. */
4459 if (mips_pic == EMBEDDED_PIC
4460 && offset_expr.X_op == O_subtract
4461 && (symbol_constant_p (offset_expr.X_op_symbol)
4462 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4463 : (symbol_equated_p (offset_expr.X_op_symbol)
4465 (symbol_get_value_expression (offset_expr.X_op_symbol)
4468 && (offset_expr.X_add_number == 0
4469 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4475 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4476 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4480 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4481 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
4482 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4483 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4484 "d,v,t", tempreg, tempreg, breg);
4486 macro_build ((char *) NULL, &icnt, &offset_expr,
4487 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4488 "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
4494 if (offset_expr.X_op != O_symbol
4495 && offset_expr.X_op != O_constant)
4497 as_bad (_("expression too complex"));
4498 offset_expr.X_op = O_constant;
4501 if (offset_expr.X_op == O_constant)
4502 load_register (&icnt, tempreg, &offset_expr,
4503 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4504 ? (dbl || HAVE_64BIT_ADDRESSES)
4505 : HAVE_64BIT_ADDRESSES));
4506 else if (mips_pic == NO_PIC)
4508 /* If this is a reference to a GP relative symbol, we want
4509 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4511 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4512 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4513 If we have a constant, we need two instructions anyhow,
4514 so we may as well always use the latter form.
4516 With 64bit address space and a usable $at we want
4517 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4518 lui $at,<sym> (BFD_RELOC_HI16_S)
4519 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4520 daddiu $at,<sym> (BFD_RELOC_LO16)
4522 dadd $tempreg,$tempreg,$at
4524 If $at is already in use, we use an path which is suboptimal
4525 on superscalar processors.
4526 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4527 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4529 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4531 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4534 if (HAVE_64BIT_ADDRESSES)
4536 /* We don't do GP optimization for now because RELAX_ENCODE can't
4537 hold the data for such large chunks. */
4541 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4542 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4543 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4544 AT, (int) BFD_RELOC_HI16_S);
4545 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4546 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4547 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4548 AT, AT, (int) BFD_RELOC_LO16);
4549 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
4550 "d,w,<", tempreg, tempreg, 0);
4551 macro_build (p, &icnt, (expressionS *) NULL, "dadd", "d,v,t",
4552 tempreg, tempreg, AT);
4557 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
4558 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
4559 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4560 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
4561 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4562 tempreg, tempreg, 16);
4563 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4564 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
4565 macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<",
4566 tempreg, tempreg, 16);
4567 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
4568 tempreg, tempreg, (int) BFD_RELOC_LO16);
4573 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4574 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
4577 macro_build ((char *) NULL, &icnt, &offset_expr, "addiu",
4578 "t,r,j", tempreg, mips_gp_register,
4579 (int) BFD_RELOC_GPREL16);
4580 p = frag_var (rs_machine_dependent, 8, 0,
4581 RELAX_ENCODE (4, 8, 0, 4, 0,
4582 mips_opts.warn_about_macros),
4583 offset_expr.X_add_symbol, 0, NULL);
4585 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4588 macro_build (p, &icnt, &offset_expr, "addiu",
4589 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4592 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4594 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4596 /* If this is a reference to an external symbol, and there
4597 is no constant, we want
4598 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4599 or if tempreg is PIC_CALL_REG
4600 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4601 For a local symbol, we want
4602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4604 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4606 If we have a small constant, and this is a reference to
4607 an external symbol, we want
4608 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4610 addiu $tempreg,$tempreg,<constant>
4611 For a local symbol, we want the same instruction
4612 sequence, but we output a BFD_RELOC_LO16 reloc on the
4615 If we have a large constant, and this is a reference to
4616 an external symbol, we want
4617 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4618 lui $at,<hiconstant>
4619 addiu $at,$at,<loconstant>
4620 addu $tempreg,$tempreg,$at
4621 For a local symbol, we want the same instruction
4622 sequence, but we output a BFD_RELOC_LO16 reloc on the
4623 addiu instruction. */
4624 expr1.X_add_number = offset_expr.X_add_number;
4625 offset_expr.X_add_number = 0;
4627 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4628 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4629 macro_build ((char *) NULL, &icnt, &offset_expr,
4630 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4631 "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
4632 if (expr1.X_add_number == 0)
4641 /* We're going to put in an addu instruction using
4642 tempreg, so we may as well insert the nop right
4644 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4648 p = frag_var (rs_machine_dependent, 8 - off, 0,
4649 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4651 ? mips_opts.warn_about_macros
4653 offset_expr.X_add_symbol, 0, NULL);
4656 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4659 macro_build (p, &icnt, &expr1,
4660 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4661 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4662 /* FIXME: If breg == 0, and the next instruction uses
4663 $tempreg, then if this variant case is used an extra
4664 nop will be generated. */
4666 else if (expr1.X_add_number >= -0x8000
4667 && expr1.X_add_number < 0x8000)
4669 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4671 macro_build ((char *) NULL, &icnt, &expr1,
4672 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4673 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4674 frag_var (rs_machine_dependent, 0, 0,
4675 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4676 offset_expr.X_add_symbol, 0, NULL);
4682 /* If we are going to add in a base register, and the
4683 target register and the base register are the same,
4684 then we are using AT as a temporary register. Since
4685 we want to load the constant into AT, we add our
4686 current AT (from the global offset table) and the
4687 register into the register now, and pretend we were
4688 not using a base register. */
4693 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4695 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4696 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4697 "d,v,t", treg, AT, breg);
4703 /* Set mips_optimize around the lui instruction to avoid
4704 inserting an unnecessary nop after the lw. */
4705 hold_mips_optimize = mips_optimize;
4707 macro_build_lui (NULL, &icnt, &expr1, AT);
4708 mips_optimize = hold_mips_optimize;
4710 macro_build ((char *) NULL, &icnt, &expr1,
4711 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4712 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4713 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4714 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4715 "d,v,t", tempreg, tempreg, AT);
4716 frag_var (rs_machine_dependent, 0, 0,
4717 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4718 offset_expr.X_add_symbol, 0, NULL);
4722 else if (mips_pic == SVR4_PIC)
4726 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4727 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4729 /* This is the large GOT case. If this is a reference to an
4730 external symbol, and there is no constant, we want
4731 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4732 addu $tempreg,$tempreg,$gp
4733 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4734 or if tempreg is PIC_CALL_REG
4735 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4736 addu $tempreg,$tempreg,$gp
4737 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4738 For a local symbol, we want
4739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4743 If we have a small constant, and this is a reference to
4744 an external symbol, we want
4745 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4746 addu $tempreg,$tempreg,$gp
4747 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4749 addiu $tempreg,$tempreg,<constant>
4750 For a local symbol, we want
4751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4753 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4755 If we have a large constant, and this is a reference to
4756 an external symbol, we want
4757 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4758 addu $tempreg,$tempreg,$gp
4759 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4760 lui $at,<hiconstant>
4761 addiu $at,$at,<loconstant>
4762 addu $tempreg,$tempreg,$at
4763 For a local symbol, we want
4764 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4765 lui $at,<hiconstant>
4766 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4767 addu $tempreg,$tempreg,$at
4769 For NewABI, we want for data addresses
4770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4771 If tempreg is PIC_CALL_REG pointing to a external symbol, we want
4772 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4776 int reloc_type = (tempreg == PIC_CALL_REG
4777 ? BFD_RELOC_MIPS_CALL16
4778 : BFD_RELOC_MIPS_GOT_DISP);
4780 macro_build ((char *) NULL, &icnt, &offset_expr,
4781 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4782 "t,o(b)", tempreg, reloc_type, mips_gp_register);
4785 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4786 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4787 "d,v,t", treg, tempreg, breg);
4794 expr1.X_add_number = offset_expr.X_add_number;
4795 offset_expr.X_add_number = 0;
4797 if (reg_needs_delay (mips_gp_register))
4801 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4803 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4804 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4806 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4807 tempreg, lui_reloc_type);
4808 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4809 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4810 "d,v,t", tempreg, tempreg, mips_gp_register);
4811 macro_build ((char *) NULL, &icnt, &offset_expr,
4812 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4813 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4814 if (expr1.X_add_number == 0)
4822 /* We're going to put in an addu instruction using
4823 tempreg, so we may as well insert the nop right
4825 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4830 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4831 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4834 ? mips_opts.warn_about_macros
4836 offset_expr.X_add_symbol, 0, NULL);
4838 else if (expr1.X_add_number >= -0x8000
4839 && expr1.X_add_number < 0x8000)
4841 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4843 macro_build ((char *) NULL, &icnt, &expr1,
4844 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4845 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4847 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4848 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4850 ? mips_opts.warn_about_macros
4852 offset_expr.X_add_symbol, 0, NULL);
4858 /* If we are going to add in a base register, and the
4859 target register and the base register are the same,
4860 then we are using AT as a temporary register. Since
4861 we want to load the constant into AT, we add our
4862 current AT (from the global offset table) and the
4863 register into the register now, and pretend we were
4864 not using a base register. */
4872 assert (tempreg == AT);
4873 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4875 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4876 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4877 "d,v,t", treg, AT, breg);
4882 /* Set mips_optimize around the lui instruction to avoid
4883 inserting an unnecessary nop after the lw. */
4884 hold_mips_optimize = mips_optimize;
4886 macro_build_lui (NULL, &icnt, &expr1, AT);
4887 mips_optimize = hold_mips_optimize;
4889 macro_build ((char *) NULL, &icnt, &expr1,
4890 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4891 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4892 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4893 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4894 "d,v,t", dreg, dreg, AT);
4896 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4897 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4900 ? mips_opts.warn_about_macros
4902 offset_expr.X_add_symbol, 0, NULL);
4909 /* This is needed because this instruction uses $gp, but
4910 the first instruction on the main stream does not. */
4911 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4914 macro_build (p, &icnt, &offset_expr,
4915 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4916 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
4919 if (expr1.X_add_number >= -0x8000
4920 && expr1.X_add_number < 0x8000)
4922 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4924 macro_build (p, &icnt, &expr1,
4925 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4926 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4927 /* FIXME: If add_number is 0, and there was no base
4928 register, the external symbol case ended with a load,
4929 so if the symbol turns out to not be external, and
4930 the next instruction uses tempreg, an unnecessary nop
4931 will be inserted. */
4937 /* We must add in the base register now, as in the
4938 external symbol case. */
4939 assert (tempreg == AT);
4940 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4942 macro_build (p, &icnt, (expressionS *) NULL,
4943 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4944 "d,v,t", treg, AT, breg);
4947 /* We set breg to 0 because we have arranged to add
4948 it in in both cases. */
4952 macro_build_lui (p, &icnt, &expr1, AT);
4954 macro_build (p, &icnt, &expr1,
4955 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4956 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4958 macro_build (p, &icnt, (expressionS *) NULL,
4959 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4960 "d,v,t", tempreg, tempreg, AT);
4964 else if (mips_pic == EMBEDDED_PIC)
4967 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4969 macro_build ((char *) NULL, &icnt, &offset_expr,
4970 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j",
4971 tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16);
4980 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4981 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
4983 s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu";
4985 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
4986 "d,v,t", treg, tempreg, breg);
4995 /* The j instruction may not be used in PIC code, since it
4996 requires an absolute address. We convert it to a b
4998 if (mips_pic == NO_PIC)
4999 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
5001 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
5004 /* The jal instructions must be handled as macros because when
5005 generating PIC code they expand to multi-instruction
5006 sequences. Normally they are simple instructions. */
5011 if (mips_pic == NO_PIC
5012 || mips_pic == EMBEDDED_PIC)
5013 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5015 else if (mips_pic == SVR4_PIC)
5017 if (sreg != PIC_CALL_REG)
5018 as_warn (_("MIPS PIC call to register other than $25"));
5020 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
5024 if (mips_cprestore_offset < 0)
5025 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5028 if (! mips_frame_reg_valid)
5030 as_warn (_("No .frame pseudo-op used in PIC code"));
5031 /* Quiet this warning. */
5032 mips_frame_reg_valid = 1;
5034 if (! mips_cprestore_valid)
5036 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5037 /* Quiet this warning. */
5038 mips_cprestore_valid = 1;
5040 expr1.X_add_number = mips_cprestore_offset;
5041 macro_build ((char *) NULL, &icnt, &expr1,
5042 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5043 mips_gp_register, (int) BFD_RELOC_LO16,
5054 if (mips_pic == NO_PIC)
5055 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
5056 else if (mips_pic == SVR4_PIC)
5060 /* If this is a reference to an external symbol, and we are
5061 using a small GOT, we want
5062 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5066 lw $gp,cprestore($sp)
5067 The cprestore value is set using the .cprestore
5068 pseudo-op. If we are using a big GOT, we want
5069 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5071 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5075 lw $gp,cprestore($sp)
5076 If the symbol is not external, we want
5077 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5079 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5082 lw $gp,cprestore($sp)
5084 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5085 jalr $ra,$25 (BFD_RELOC_MIPS_JALR)
5089 macro_build ((char *) NULL, &icnt, &offset_expr,
5090 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5091 "t,o(b)", PIC_CALL_REG,
5092 (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5093 macro_build_jalr (icnt, &offset_expr);
5100 macro_build ((char *) NULL, &icnt, &offset_expr,
5101 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5102 "t,o(b)", PIC_CALL_REG,
5103 (int) BFD_RELOC_MIPS_CALL16, mips_gp_register);
5104 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5106 p = frag_var (rs_machine_dependent, 4, 0,
5107 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5108 offset_expr.X_add_symbol, 0, NULL);
5114 if (reg_needs_delay (mips_gp_register))
5118 macro_build ((char *) NULL, &icnt, &offset_expr, "lui",
5119 "t,u", PIC_CALL_REG,
5120 (int) BFD_RELOC_MIPS_CALL_HI16);
5121 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5122 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5123 "d,v,t", PIC_CALL_REG, PIC_CALL_REG,
5125 macro_build ((char *) NULL, &icnt, &offset_expr,
5126 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5127 "t,o(b)", PIC_CALL_REG,
5128 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
5129 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5131 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5132 RELAX_ENCODE (16, 12 + gpdel, gpdel,
5134 offset_expr.X_add_symbol, 0, NULL);
5137 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5140 macro_build (p, &icnt, &offset_expr,
5141 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5142 "t,o(b)", PIC_CALL_REG,
5143 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5145 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5148 macro_build (p, &icnt, &offset_expr,
5149 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5150 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
5151 (int) BFD_RELOC_LO16);
5152 macro_build_jalr (icnt, &offset_expr);
5154 if (mips_cprestore_offset < 0)
5155 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5158 if (! mips_frame_reg_valid)
5160 as_warn (_("No .frame pseudo-op used in PIC code"));
5161 /* Quiet this warning. */
5162 mips_frame_reg_valid = 1;
5164 if (! mips_cprestore_valid)
5166 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5167 /* Quiet this warning. */
5168 mips_cprestore_valid = 1;
5170 if (mips_opts.noreorder)
5171 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5173 expr1.X_add_number = mips_cprestore_offset;
5174 macro_build ((char *) NULL, &icnt, &expr1,
5175 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)",
5176 mips_gp_register, (int) BFD_RELOC_LO16,
5181 else if (mips_pic == EMBEDDED_PIC)
5183 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
5184 /* The linker may expand the call to a longer sequence which
5185 uses $at, so we must break rather than return. */
5210 /* Itbl support may require additional care here. */
5215 /* Itbl support may require additional care here. */
5220 /* Itbl support may require additional care here. */
5225 /* Itbl support may require additional care here. */
5237 if (mips_arch == CPU_R4650)
5239 as_bad (_("opcode not supported on this processor"));
5243 /* Itbl support may require additional care here. */
5248 /* Itbl support may require additional care here. */
5253 /* Itbl support may require additional care here. */
5273 if (breg == treg || coproc || lr)
5295 /* Itbl support may require additional care here. */
5300 /* Itbl support may require additional care here. */
5305 /* Itbl support may require additional care here. */
5310 /* Itbl support may require additional care here. */
5326 if (mips_arch == CPU_R4650)
5328 as_bad (_("opcode not supported on this processor"));
5333 /* Itbl support may require additional care here. */
5337 /* Itbl support may require additional care here. */
5342 /* Itbl support may require additional care here. */
5354 /* Itbl support may require additional care here. */
5355 if (mask == M_LWC1_AB
5356 || mask == M_SWC1_AB
5357 || mask == M_LDC1_AB
5358 || mask == M_SDC1_AB
5367 /* For embedded PIC, we allow loads where the offset is calculated
5368 by subtracting a symbol in the current segment from an unknown
5369 symbol, relative to a base register, e.g.:
5370 <op> $treg, <sym>-<localsym>($breg)
5371 This is used by the compiler for switch statements. */
5372 if (mips_pic == EMBEDDED_PIC
5373 && offset_expr.X_op == O_subtract
5374 && (symbol_constant_p (offset_expr.X_op_symbol)
5375 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5376 : (symbol_equated_p (offset_expr.X_op_symbol)
5378 (symbol_get_value_expression (offset_expr.X_op_symbol)
5382 && (offset_expr.X_add_number == 0
5383 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5385 /* For this case, we output the instructions:
5386 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5387 addiu $tempreg,$tempreg,$breg
5388 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5389 If the relocation would fit entirely in 16 bits, it would be
5391 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5392 instead, but that seems quite difficult. */
5393 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5394 tempreg, (int) BFD_RELOC_PCREL_HI16_S);
5395 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5396 ((bfd_arch_bits_per_address (stdoutput) == 32
5397 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5398 ? "addu" : "daddu"),
5399 "d,v,t", tempreg, tempreg, breg);
5400 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
5401 (int) BFD_RELOC_PCREL_LO16, tempreg);
5407 if (offset_expr.X_op != O_constant
5408 && offset_expr.X_op != O_symbol)
5410 as_bad (_("expression too complex"));
5411 offset_expr.X_op = O_constant;
5414 /* A constant expression in PIC code can be handled just as it
5415 is in non PIC code. */
5416 if (mips_pic == NO_PIC
5417 || offset_expr.X_op == O_constant)
5421 /* If this is a reference to a GP relative symbol, and there
5422 is no base register, we want
5423 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5424 Otherwise, if there is no base register, we want
5425 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5426 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5427 If we have a constant, we need two instructions anyhow,
5428 so we always use the latter form.
5430 If we have a base register, and this is a reference to a
5431 GP relative symbol, we want
5432 addu $tempreg,$breg,$gp
5433 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5435 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5436 addu $tempreg,$tempreg,$breg
5437 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5438 With a constant we always use the latter case.
5440 With 64bit address space and no base register and $at usable,
5442 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5443 lui $at,<sym> (BFD_RELOC_HI16_S)
5444 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5447 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5448 If we have a base register, we want
5449 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5450 lui $at,<sym> (BFD_RELOC_HI16_S)
5451 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5455 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5457 Without $at we can't generate the optimal path for superscalar
5458 processors here since this would require two temporary registers.
5459 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5460 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5462 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5464 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5465 If we have a base register, we want
5466 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5467 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5469 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5471 daddu $tempreg,$tempreg,$breg
5472 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5474 If we have 64-bit addresses, as an optimization, for
5475 addresses which are 32-bit constants (e.g. kseg0/kseg1
5476 addresses) we fall back to the 32-bit address generation
5477 mechanism since it is more efficient. This code should
5478 probably attempt to generate 64-bit constants more
5479 efficiently in general.
5481 if (HAVE_64BIT_ADDRESSES
5482 && !(offset_expr.X_op == O_constant
5483 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number)))
5487 /* We don't do GP optimization for now because RELAX_ENCODE can't
5488 hold the data for such large chunks. */
5492 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5493 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5494 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5495 AT, (int) BFD_RELOC_HI16_S);
5496 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5497 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5499 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5500 "d,v,t", AT, AT, breg);
5501 macro_build (p, &icnt, (expressionS *) NULL, "dsll32",
5502 "d,w,<", tempreg, tempreg, 0);
5503 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5504 "d,v,t", tempreg, tempreg, AT);
5505 macro_build (p, &icnt, &offset_expr, s,
5506 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5511 macro_build (p, &icnt, &offset_expr, "lui", "t,u",
5512 tempreg, (int) BFD_RELOC_MIPS_HIGHEST);
5513 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5514 tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER);
5515 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5516 "d,w,<", tempreg, tempreg, 16);
5517 macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
5518 tempreg, tempreg, (int) BFD_RELOC_HI16_S);
5519 macro_build (p, &icnt, (expressionS *) NULL, "dsll",
5520 "d,w,<", tempreg, tempreg, 16);
5522 macro_build (p, &icnt, (expressionS *) NULL, "daddu",
5523 "d,v,t", tempreg, tempreg, breg);
5524 macro_build (p, &icnt, &offset_expr, s,
5525 fmt, treg, (int) BFD_RELOC_LO16, tempreg);
5533 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5534 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5539 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5540 treg, (int) BFD_RELOC_GPREL16,
5542 p = frag_var (rs_machine_dependent, 8, 0,
5543 RELAX_ENCODE (4, 8, 0, 4, 0,
5544 (mips_opts.warn_about_macros
5546 && mips_opts.noat))),
5547 offset_expr.X_add_symbol, 0, NULL);
5550 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5553 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5554 (int) BFD_RELOC_LO16, tempreg);
5558 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5559 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5564 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5565 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5566 "d,v,t", tempreg, breg, mips_gp_register);
5567 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5568 treg, (int) BFD_RELOC_GPREL16, tempreg);
5569 p = frag_var (rs_machine_dependent, 12, 0,
5570 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5571 offset_expr.X_add_symbol, 0, NULL);
5573 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5576 macro_build (p, &icnt, (expressionS *) NULL,
5577 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5578 "d,v,t", tempreg, tempreg, breg);
5581 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5582 (int) BFD_RELOC_LO16, tempreg);
5585 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5589 /* If this is a reference to an external symbol, we want
5590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5592 <op> $treg,0($tempreg)
5594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5596 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5597 <op> $treg,0($tempreg)
5598 If there is a base register, we add it to $tempreg before
5599 the <op>. If there is a constant, we stick it in the
5600 <op> instruction. We don't handle constants larger than
5601 16 bits, because we have no way to load the upper 16 bits
5602 (actually, we could handle them for the subset of cases
5603 in which we are not using $at). */
5604 assert (offset_expr.X_op == O_symbol);
5605 expr1.X_add_number = offset_expr.X_add_number;
5606 offset_expr.X_add_number = 0;
5607 if (expr1.X_add_number < -0x8000
5608 || expr1.X_add_number >= 0x8000)
5609 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5611 macro_build ((char *) NULL, &icnt, &offset_expr,
5612 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg,
5613 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
5614 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5615 p = frag_var (rs_machine_dependent, 4, 0,
5616 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5617 offset_expr.X_add_symbol, 0, NULL);
5618 macro_build (p, &icnt, &offset_expr,
5619 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5620 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5623 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5624 "d,v,t", tempreg, tempreg, breg);
5625 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5626 (int) BFD_RELOC_LO16, tempreg);
5628 else if (mips_pic == SVR4_PIC)
5633 /* If this is a reference to an external symbol, we want
5634 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5635 addu $tempreg,$tempreg,$gp
5636 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5637 <op> $treg,0($tempreg)
5639 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5641 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5642 <op> $treg,0($tempreg)
5643 If there is a base register, we add it to $tempreg before
5644 the <op>. If there is a constant, we stick it in the
5645 <op> instruction. We don't handle constants larger than
5646 16 bits, because we have no way to load the upper 16 bits
5647 (actually, we could handle them for the subset of cases
5648 in which we are not using $at).
5651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5652 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5653 <op> $treg,0($tempreg)
5655 assert (offset_expr.X_op == O_symbol);
5656 expr1.X_add_number = offset_expr.X_add_number;
5657 offset_expr.X_add_number = 0;
5658 if (expr1.X_add_number < -0x8000
5659 || expr1.X_add_number >= 0x8000)
5660 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5663 macro_build ((char *) NULL, &icnt, &offset_expr,
5664 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5665 "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
5667 macro_build ((char *) NULL, &icnt, &offset_expr,
5668 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5669 "t,r,j", tempreg, tempreg,
5670 BFD_RELOC_MIPS_GOT_OFST);
5672 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5673 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5674 "d,v,t", tempreg, tempreg, breg);
5675 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5676 (int) BFD_RELOC_LO16, tempreg);
5683 if (reg_needs_delay (mips_gp_register))
5688 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5689 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5690 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5691 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5692 "d,v,t", tempreg, tempreg, mips_gp_register);
5693 macro_build ((char *) NULL, &icnt, &offset_expr,
5694 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5695 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5697 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5698 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5699 offset_expr.X_add_symbol, 0, NULL);
5702 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5705 macro_build (p, &icnt, &offset_expr,
5706 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5707 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16,
5710 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5712 macro_build (p, &icnt, &offset_expr,
5713 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5714 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5716 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5717 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5718 "d,v,t", tempreg, tempreg, breg);
5719 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5720 (int) BFD_RELOC_LO16, tempreg);
5722 else if (mips_pic == EMBEDDED_PIC)
5724 /* If there is no base register, we want
5725 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5726 If there is a base register, we want
5727 addu $tempreg,$breg,$gp
5728 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5730 assert (offset_expr.X_op == O_symbol);
5733 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5734 treg, (int) BFD_RELOC_GPREL16, mips_gp_register);
5739 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5740 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5741 "d,v,t", tempreg, breg, mips_gp_register);
5742 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5743 treg, (int) BFD_RELOC_GPREL16, tempreg);
5756 load_register (&icnt, treg, &imm_expr, 0);
5760 load_register (&icnt, treg, &imm_expr, 1);
5764 if (imm_expr.X_op == O_constant)
5766 load_register (&icnt, AT, &imm_expr, 0);
5767 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5768 "mtc1", "t,G", AT, treg);
5773 assert (offset_expr.X_op == O_symbol
5774 && strcmp (segment_name (S_GET_SEGMENT
5775 (offset_expr.X_add_symbol)),
5777 && offset_expr.X_add_number == 0);
5778 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5779 treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register);
5784 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5785 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5786 order 32 bits of the value and the low order 32 bits are either
5787 zero or in OFFSET_EXPR. */
5788 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5790 if (HAVE_64BIT_GPRS)
5791 load_register (&icnt, treg, &imm_expr, 1);
5796 if (target_big_endian)
5808 load_register (&icnt, hreg, &imm_expr, 0);
5811 if (offset_expr.X_op == O_absent)
5812 move_register (&icnt, lreg, 0);
5815 assert (offset_expr.X_op == O_constant);
5816 load_register (&icnt, lreg, &offset_expr, 0);
5823 /* We know that sym is in the .rdata section. First we get the
5824 upper 16 bits of the address. */
5825 if (mips_pic == NO_PIC)
5827 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5829 else if (mips_pic == SVR4_PIC)
5831 macro_build ((char *) NULL, &icnt, &offset_expr,
5832 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5833 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5836 else if (mips_pic == EMBEDDED_PIC)
5838 /* For embedded PIC we pick up the entire address off $gp in
5839 a single instruction. */
5840 macro_build ((char *) NULL, &icnt, &offset_expr,
5841 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT,
5842 mips_gp_register, (int) BFD_RELOC_GPREL16);
5843 offset_expr.X_op = O_constant;
5844 offset_expr.X_add_number = 0;
5849 /* Now we load the register(s). */
5850 if (HAVE_64BIT_GPRS)
5851 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5852 treg, (int) BFD_RELOC_LO16, AT);
5855 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5856 treg, (int) BFD_RELOC_LO16, AT);
5859 /* FIXME: How in the world do we deal with the possible
5861 offset_expr.X_add_number += 4;
5862 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5863 treg + 1, (int) BFD_RELOC_LO16, AT);
5867 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5868 does not become a variant frag. */
5869 frag_wane (frag_now);
5875 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5876 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5877 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5878 the value and the low order 32 bits are either zero or in
5880 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5882 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5883 if (HAVE_64BIT_FPRS)
5885 assert (HAVE_64BIT_GPRS);
5886 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5887 "dmtc1", "t,S", AT, treg);
5891 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5892 "mtc1", "t,G", AT, treg + 1);
5893 if (offset_expr.X_op == O_absent)
5894 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5895 "mtc1", "t,G", 0, treg);
5898 assert (offset_expr.X_op == O_constant);
5899 load_register (&icnt, AT, &offset_expr, 0);
5900 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5901 "mtc1", "t,G", AT, treg);
5907 assert (offset_expr.X_op == O_symbol
5908 && offset_expr.X_add_number == 0);
5909 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5910 if (strcmp (s, ".lit8") == 0)
5912 if (mips_opts.isa != ISA_MIPS1)
5914 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5915 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL,
5919 breg = mips_gp_register;
5920 r = BFD_RELOC_MIPS_LITERAL;
5925 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5926 if (mips_pic == SVR4_PIC)
5927 macro_build ((char *) NULL, &icnt, &offset_expr,
5928 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5929 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
5933 /* FIXME: This won't work for a 64 bit address. */
5934 macro_build_lui (NULL, &icnt, &offset_expr, AT);
5937 if (mips_opts.isa != ISA_MIPS1)
5939 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5940 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5942 /* To avoid confusion in tc_gen_reloc, we must ensure
5943 that this does not become a variant frag. */
5944 frag_wane (frag_now);
5955 if (mips_arch == CPU_R4650)
5957 as_bad (_("opcode not supported on this processor"));
5960 /* Even on a big endian machine $fn comes before $fn+1. We have
5961 to adjust when loading from memory. */
5964 assert (mips_opts.isa == ISA_MIPS1);
5965 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5966 target_big_endian ? treg + 1 : treg,
5968 /* FIXME: A possible overflow which I don't know how to deal
5970 offset_expr.X_add_number += 4;
5971 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5972 target_big_endian ? treg : treg + 1,
5975 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5976 does not become a variant frag. */
5977 frag_wane (frag_now);
5986 * The MIPS assembler seems to check for X_add_number not
5987 * being double aligned and generating:
5990 * addiu at,at,%lo(foo+1)
5993 * But, the resulting address is the same after relocation so why
5994 * generate the extra instruction?
5996 if (mips_arch == CPU_R4650)
5998 as_bad (_("opcode not supported on this processor"));
6001 /* Itbl support may require additional care here. */
6003 if (mips_opts.isa != ISA_MIPS1)
6014 if (mips_arch == CPU_R4650)
6016 as_bad (_("opcode not supported on this processor"));
6020 if (mips_opts.isa != ISA_MIPS1)
6028 /* Itbl support may require additional care here. */
6033 if (HAVE_64BIT_GPRS)
6044 if (HAVE_64BIT_GPRS)
6054 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6055 loads for the case of doing a pair of loads to simulate an 'ld'.
6056 This is not currently done by the compiler, and assembly coders
6057 writing embedded-pic code can cope. */
6059 if (offset_expr.X_op != O_symbol
6060 && offset_expr.X_op != O_constant)
6062 as_bad (_("expression too complex"));
6063 offset_expr.X_op = O_constant;
6066 /* Even on a big endian machine $fn comes before $fn+1. We have
6067 to adjust when loading from memory. We set coproc if we must
6068 load $fn+1 first. */
6069 /* Itbl support may require additional care here. */
6070 if (! target_big_endian)
6073 if (mips_pic == NO_PIC
6074 || offset_expr.X_op == O_constant)
6078 /* If this is a reference to a GP relative symbol, we want
6079 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6080 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6081 If we have a base register, we use this
6083 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6084 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6085 If this is not a GP relative symbol, we want
6086 lui $at,<sym> (BFD_RELOC_HI16_S)
6087 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6088 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6089 If there is a base register, we add it to $at after the
6090 lui instruction. If there is a constant, we always use
6092 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6093 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6105 tempreg = mips_gp_register;
6112 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6113 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6114 "d,v,t", AT, breg, mips_gp_register);
6120 /* Itbl support may require additional care here. */
6121 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6122 coproc ? treg + 1 : treg,
6123 (int) BFD_RELOC_GPREL16, tempreg);
6124 offset_expr.X_add_number += 4;
6126 /* Set mips_optimize to 2 to avoid inserting an
6128 hold_mips_optimize = mips_optimize;
6130 /* Itbl support may require additional care here. */
6131 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6132 coproc ? treg : treg + 1,
6133 (int) BFD_RELOC_GPREL16, tempreg);
6134 mips_optimize = hold_mips_optimize;
6136 p = frag_var (rs_machine_dependent, 12 + off, 0,
6137 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
6138 used_at && mips_opts.noat),
6139 offset_expr.X_add_symbol, 0, NULL);
6141 /* We just generated two relocs. When tc_gen_reloc
6142 handles this case, it will skip the first reloc and
6143 handle the second. The second reloc already has an
6144 extra addend of 4, which we added above. We must
6145 subtract it out, and then subtract another 4 to make
6146 the first reloc come out right. The second reloc
6147 will come out right because we are going to add 4 to
6148 offset_expr when we build its instruction below.
6150 If we have a symbol, then we don't want to include
6151 the offset, because it will wind up being included
6152 when we generate the reloc. */
6154 if (offset_expr.X_op == O_constant)
6155 offset_expr.X_add_number -= 8;
6158 offset_expr.X_add_number = -4;
6159 offset_expr.X_op = O_constant;
6162 macro_build_lui (p, &icnt, &offset_expr, AT);
6167 macro_build (p, &icnt, (expressionS *) NULL,
6168 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6169 "d,v,t", AT, breg, AT);
6173 /* Itbl support may require additional care here. */
6174 macro_build (p, &icnt, &offset_expr, s, fmt,
6175 coproc ? treg + 1 : treg,
6176 (int) BFD_RELOC_LO16, AT);
6179 /* FIXME: How do we handle overflow here? */
6180 offset_expr.X_add_number += 4;
6181 /* Itbl support may require additional care here. */
6182 macro_build (p, &icnt, &offset_expr, s, fmt,
6183 coproc ? treg : treg + 1,
6184 (int) BFD_RELOC_LO16, AT);
6186 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6190 /* If this is a reference to an external symbol, we want
6191 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6196 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6198 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6199 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6200 If there is a base register we add it to $at before the
6201 lwc1 instructions. If there is a constant we include it
6202 in the lwc1 instructions. */
6204 expr1.X_add_number = offset_expr.X_add_number;
6205 offset_expr.X_add_number = 0;
6206 if (expr1.X_add_number < -0x8000
6207 || expr1.X_add_number >= 0x8000 - 4)
6208 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6213 frag_grow (24 + off);
6214 macro_build ((char *) NULL, &icnt, &offset_expr,
6215 HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT,
6216 (int) BFD_RELOC_MIPS_GOT16, mips_gp_register);
6217 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6219 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6220 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6221 "d,v,t", AT, breg, AT);
6222 /* Itbl support may require additional care here. */
6223 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6224 coproc ? treg + 1 : treg,
6225 (int) BFD_RELOC_LO16, AT);
6226 expr1.X_add_number += 4;
6228 /* Set mips_optimize to 2 to avoid inserting an undesired
6230 hold_mips_optimize = mips_optimize;
6232 /* Itbl support may require additional care here. */
6233 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6234 coproc ? treg : treg + 1,
6235 (int) BFD_RELOC_LO16, AT);
6236 mips_optimize = hold_mips_optimize;
6238 (void) frag_var (rs_machine_dependent, 0, 0,
6239 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
6240 offset_expr.X_add_symbol, 0, NULL);
6242 else if (mips_pic == SVR4_PIC)
6247 /* If this is a reference to an external symbol, we want
6248 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6250 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6255 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6257 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6258 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6259 If there is a base register we add it to $at before the
6260 lwc1 instructions. If there is a constant we include it
6261 in the lwc1 instructions. */
6263 expr1.X_add_number = offset_expr.X_add_number;
6264 offset_expr.X_add_number = 0;
6265 if (expr1.X_add_number < -0x8000
6266 || expr1.X_add_number >= 0x8000 - 4)
6267 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6268 if (reg_needs_delay (mips_gp_register))
6277 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
6278 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
6279 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6280 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6281 "d,v,t", AT, AT, mips_gp_register);
6282 macro_build ((char *) NULL, &icnt, &offset_expr,
6283 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6284 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
6285 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
6287 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6288 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6289 "d,v,t", AT, breg, AT);
6290 /* Itbl support may require additional care here. */
6291 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6292 coproc ? treg + 1 : treg,
6293 (int) BFD_RELOC_LO16, AT);
6294 expr1.X_add_number += 4;
6296 /* Set mips_optimize to 2 to avoid inserting an undesired
6298 hold_mips_optimize = mips_optimize;
6300 /* Itbl support may require additional care here. */
6301 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
6302 coproc ? treg : treg + 1,
6303 (int) BFD_RELOC_LO16, AT);
6304 mips_optimize = hold_mips_optimize;
6305 expr1.X_add_number -= 4;
6307 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
6308 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
6309 8 + gpdel + off, 1, 0),
6310 offset_expr.X_add_symbol, 0, NULL);
6313 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6316 macro_build (p, &icnt, &offset_expr,
6317 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
6318 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16,
6321 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
6325 macro_build (p, &icnt, (expressionS *) NULL,
6326 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6327 "d,v,t", AT, breg, AT);
6330 /* Itbl support may require additional care here. */
6331 macro_build (p, &icnt, &expr1, s, fmt,
6332 coproc ? treg + 1 : treg,
6333 (int) BFD_RELOC_LO16, AT);
6335 expr1.X_add_number += 4;
6337 /* Set mips_optimize to 2 to avoid inserting an undesired
6339 hold_mips_optimize = mips_optimize;
6341 /* Itbl support may require additional care here. */
6342 macro_build (p, &icnt, &expr1, s, fmt,
6343 coproc ? treg : treg + 1,
6344 (int) BFD_RELOC_LO16, AT);
6345 mips_optimize = hold_mips_optimize;
6347 else if (mips_pic == EMBEDDED_PIC)
6349 /* If there is no base register, we use
6350 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6351 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6352 If we have a base register, we use
6354 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6355 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6359 tempreg = mips_gp_register;
6364 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6365 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6366 "d,v,t", AT, breg, mips_gp_register);
6371 /* Itbl support may require additional care here. */
6372 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6373 coproc ? treg + 1 : treg,
6374 (int) BFD_RELOC_GPREL16, tempreg);
6375 offset_expr.X_add_number += 4;
6376 /* Itbl support may require additional care here. */
6377 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
6378 coproc ? treg : treg + 1,
6379 (int) BFD_RELOC_GPREL16, tempreg);
6395 assert (HAVE_32BIT_ADDRESSES);
6396 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6397 (int) BFD_RELOC_LO16, breg);
6398 offset_expr.X_add_number += 4;
6399 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
6400 (int) BFD_RELOC_LO16, breg);
6403 /* New code added to support COPZ instructions.
6404 This code builds table entries out of the macros in mip_opcodes.
6405 R4000 uses interlocks to handle coproc delays.
6406 Other chips (like the R3000) require nops to be inserted for delays.
6408 FIXME: Currently, we require that the user handle delays.
6409 In order to fill delay slots for non-interlocked chips,
6410 we must have a way to specify delays based on the coprocessor.
6411 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6412 What are the side-effects of the cop instruction?
6413 What cache support might we have and what are its effects?
6414 Both coprocessor & memory require delays. how long???
6415 What registers are read/set/modified?
6417 If an itbl is provided to interpret cop instructions,
6418 this knowledge can be encoded in the itbl spec. */
6432 /* For now we just do C (same as Cz). The parameter will be
6433 stored in insn_opcode by mips_ip. */
6434 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
6439 move_register (&icnt, dreg, sreg);
6442 #ifdef LOSING_COMPILER
6444 /* Try and see if this is a new itbl instruction.
6445 This code builds table entries out of the macros in mip_opcodes.
6446 FIXME: For now we just assemble the expression and pass it's
6447 value along as a 32-bit immediate.
6448 We may want to have the assembler assemble this value,
6449 so that we gain the assembler's knowledge of delay slots,
6451 Would it be more efficient to use mask (id) here? */
6452 if (itbl_have_entries
6453 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6455 s = ip->insn_mo->name;
6457 coproc = ITBL_DECODE_PNUM (immed_expr);;
6458 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
6465 as_warn (_("Macro used $at after \".set noat\""));
6470 struct mips_cl_insn *ip;
6472 register int treg, sreg, dreg, breg;
6488 bfd_reloc_code_real_type r;
6491 treg = (ip->insn_opcode >> 16) & 0x1f;
6492 dreg = (ip->insn_opcode >> 11) & 0x1f;
6493 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6494 mask = ip->insn_mo->mask;
6496 expr1.X_op = O_constant;
6497 expr1.X_op_symbol = NULL;
6498 expr1.X_add_symbol = NULL;
6499 expr1.X_add_number = 1;
6503 #endif /* LOSING_COMPILER */
6508 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6509 dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6510 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6517 /* The MIPS assembler some times generates shifts and adds. I'm
6518 not trying to be that fancy. GCC should do this for us
6520 load_register (&icnt, AT, &imm_expr, dbl);
6521 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6522 dbl ? "dmult" : "mult", "s,t", sreg, AT);
6523 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6537 mips_emit_delays (true);
6538 ++mips_opts.noreorder;
6539 mips_any_noreorder = 1;
6541 load_register (&icnt, AT, &imm_expr, dbl);
6542 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6543 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6544 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6546 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6547 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6548 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6551 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6555 expr1.X_add_number = 8;
6556 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg,
6558 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6560 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6563 --mips_opts.noreorder;
6564 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg);
6577 mips_emit_delays (true);
6578 ++mips_opts.noreorder;
6579 mips_any_noreorder = 1;
6581 load_register (&icnt, AT, &imm_expr, dbl);
6582 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6583 dbl ? "dmultu" : "multu",
6584 "s,t", sreg, imm ? AT : treg);
6585 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d",
6587 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d",
6590 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", "s,t",
6594 expr1.X_add_number = 8;
6595 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6596 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "",
6598 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
6601 --mips_opts.noreorder;
6605 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6606 "d,v,t", AT, 0, treg);
6607 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6608 "d,t,s", AT, sreg, AT);
6609 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6610 "d,t,s", dreg, sreg, treg);
6611 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6612 "d,v,t", dreg, dreg, AT);
6616 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6617 "d,v,t", AT, 0, treg);
6618 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6619 "d,t,s", AT, sreg, AT);
6620 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6621 "d,t,s", dreg, sreg, treg);
6622 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6623 "d,v,t", dreg, dreg, AT);
6631 if (imm_expr.X_op != O_constant)
6632 as_bad (_("rotate count too large"));
6633 rot = imm_expr.X_add_number & 0x3f;
6636 l = (rot < 0x20) ? "dsll" : "dsll32";
6637 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
6639 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6640 "d,w,<", AT, sreg, rot);
6641 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6642 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6643 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6644 "d,v,t", dreg, dreg, AT);
6652 if (imm_expr.X_op != O_constant)
6653 as_bad (_("rotate count too large"));
6654 rot = imm_expr.X_add_number & 0x1f;
6657 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6658 "d,w,<", AT, sreg, rot);
6659 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6660 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6661 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6662 "d,v,t", dreg, dreg, AT);
6667 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu",
6668 "d,v,t", AT, 0, treg);
6669 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv",
6670 "d,t,s", AT, sreg, AT);
6671 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv",
6672 "d,t,s", dreg, sreg, treg);
6673 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6674 "d,v,t", dreg, dreg, AT);
6678 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu",
6679 "d,v,t", AT, 0, treg);
6680 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv",
6681 "d,t,s", AT, sreg, AT);
6682 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv",
6683 "d,t,s", dreg, sreg, treg);
6684 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6685 "d,v,t", dreg, dreg, AT);
6693 if (imm_expr.X_op != O_constant)
6694 as_bad (_("rotate count too large"));
6695 rot = imm_expr.X_add_number & 0x3f;
6698 r = (rot < 0x20) ? "dsrl" : "dsrl32";
6699 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
6701 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
6702 "d,w,<", AT, sreg, rot);
6703 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
6704 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6705 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6706 "d,v,t", dreg, dreg, AT);
6714 if (imm_expr.X_op != O_constant)
6715 as_bad (_("rotate count too large"));
6716 rot = imm_expr.X_add_number & 0x1f;
6719 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
6720 "d,w,<", AT, sreg, rot);
6721 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
6722 "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
6723 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
6724 "d,v,t", dreg, dreg, AT);
6729 if (mips_arch == CPU_R4650)
6731 as_bad (_("opcode not supported on this processor"));
6734 assert (mips_opts.isa == ISA_MIPS1);
6735 /* Even on a big endian machine $fn comes before $fn+1. We have
6736 to adjust when storing to memory. */
6737 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6738 target_big_endian ? treg + 1 : treg,
6739 (int) BFD_RELOC_LO16, breg);
6740 offset_expr.X_add_number += 4;
6741 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6742 target_big_endian ? treg : treg + 1,
6743 (int) BFD_RELOC_LO16, breg);
6748 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6749 treg, (int) BFD_RELOC_LO16);
6751 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6752 sreg, (int) BFD_RELOC_LO16);
6755 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6756 "d,v,t", dreg, sreg, treg);
6757 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6758 dreg, (int) BFD_RELOC_LO16);
6763 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6765 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6766 sreg, (int) BFD_RELOC_LO16);
6771 as_warn (_("Instruction %s: result is always false"),
6773 move_register (&icnt, dreg, 0);
6776 if (imm_expr.X_op == O_constant
6777 && imm_expr.X_add_number >= 0
6778 && imm_expr.X_add_number < 0x10000)
6780 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6781 sreg, (int) BFD_RELOC_LO16);
6784 else if (imm_expr.X_op == O_constant
6785 && imm_expr.X_add_number > -0x8000
6786 && imm_expr.X_add_number < 0)
6788 imm_expr.X_add_number = -imm_expr.X_add_number;
6789 macro_build ((char *) NULL, &icnt, &imm_expr,
6790 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6791 "t,r,j", dreg, sreg,
6792 (int) BFD_RELOC_LO16);
6797 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6798 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6799 "d,v,t", dreg, sreg, AT);
6802 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6803 (int) BFD_RELOC_LO16);
6808 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6814 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6816 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6817 (int) BFD_RELOC_LO16);
6820 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6822 if (imm_expr.X_op == O_constant
6823 && imm_expr.X_add_number >= -0x8000
6824 && imm_expr.X_add_number < 0x8000)
6826 macro_build ((char *) NULL, &icnt, &imm_expr,
6827 mask == M_SGE_I ? "slti" : "sltiu",
6828 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6833 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6834 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6835 mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg,
6839 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6840 (int) BFD_RELOC_LO16);
6845 case M_SGT: /* sreg > treg <==> treg < sreg */
6851 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6855 case M_SGT_I: /* sreg > I <==> I < sreg */
6861 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6862 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6866 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6872 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6874 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6875 (int) BFD_RELOC_LO16);
6878 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6884 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6885 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t",
6887 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6888 (int) BFD_RELOC_LO16);
6892 if (imm_expr.X_op == O_constant
6893 && imm_expr.X_add_number >= -0x8000
6894 && imm_expr.X_add_number < 0x8000)
6896 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6897 dreg, sreg, (int) BFD_RELOC_LO16);
6900 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6901 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t",
6906 if (imm_expr.X_op == O_constant
6907 && imm_expr.X_add_number >= -0x8000
6908 && imm_expr.X_add_number < 0x8000)
6910 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6911 dreg, sreg, (int) BFD_RELOC_LO16);
6914 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6915 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6916 "d,v,t", dreg, sreg, AT);
6921 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6922 "d,v,t", dreg, 0, treg);
6924 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6925 "d,v,t", dreg, 0, sreg);
6928 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6929 "d,v,t", dreg, sreg, treg);
6930 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6931 "d,v,t", dreg, 0, dreg);
6936 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6938 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6939 "d,v,t", dreg, 0, sreg);
6944 as_warn (_("Instruction %s: result is always true"),
6946 macro_build ((char *) NULL, &icnt, &expr1,
6947 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6948 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6951 if (imm_expr.X_op == O_constant
6952 && imm_expr.X_add_number >= 0
6953 && imm_expr.X_add_number < 0x10000)
6955 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6956 dreg, sreg, (int) BFD_RELOC_LO16);
6959 else if (imm_expr.X_op == O_constant
6960 && imm_expr.X_add_number > -0x8000
6961 && imm_expr.X_add_number < 0)
6963 imm_expr.X_add_number = -imm_expr.X_add_number;
6964 macro_build ((char *) NULL, &icnt, &imm_expr,
6965 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6966 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6971 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
6972 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor",
6973 "d,v,t", dreg, sreg, AT);
6976 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu",
6977 "d,v,t", dreg, 0, dreg);
6985 if (imm_expr.X_op == O_constant
6986 && imm_expr.X_add_number > -0x8000
6987 && imm_expr.X_add_number <= 0x8000)
6989 imm_expr.X_add_number = -imm_expr.X_add_number;
6990 macro_build ((char *) NULL, &icnt, &imm_expr,
6991 dbl ? "daddi" : "addi",
6992 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6995 load_register (&icnt, AT, &imm_expr, dbl);
6996 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6997 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7003 if (imm_expr.X_op == O_constant
7004 && imm_expr.X_add_number > -0x8000
7005 && imm_expr.X_add_number <= 0x8000)
7007 imm_expr.X_add_number = -imm_expr.X_add_number;
7008 macro_build ((char *) NULL, &icnt, &imm_expr,
7009 dbl ? "daddiu" : "addiu",
7010 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
7013 load_register (&icnt, AT, &imm_expr, dbl);
7014 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7015 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7036 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
7037 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg,
7043 assert (mips_opts.isa == ISA_MIPS1);
7044 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7045 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7048 * Is the double cfc1 instruction a bug in the mips assembler;
7049 * or is there a reason for it?
7051 mips_emit_delays (true);
7052 ++mips_opts.noreorder;
7053 mips_any_noreorder = 1;
7054 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7056 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G",
7058 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7059 expr1.X_add_number = 3;
7060 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
7061 (int) BFD_RELOC_LO16);
7062 expr1.X_add_number = 2;
7063 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
7064 (int) BFD_RELOC_LO16);
7065 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7067 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7068 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7069 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
7070 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G",
7072 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
7073 --mips_opts.noreorder;
7082 if (offset_expr.X_add_number >= 0x7fff)
7083 as_bad (_("operand overflow"));
7084 /* avoid load delay */
7085 if (! target_big_endian)
7086 ++offset_expr.X_add_number;
7087 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7088 (int) BFD_RELOC_LO16, breg);
7089 if (! target_big_endian)
7090 --offset_expr.X_add_number;
7092 ++offset_expr.X_add_number;
7093 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
7094 (int) BFD_RELOC_LO16, breg);
7095 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7097 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7111 if (offset_expr.X_add_number >= 0x8000 - off)
7112 as_bad (_("operand overflow"));
7113 if (! target_big_endian)
7114 offset_expr.X_add_number += off;
7115 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7116 (int) BFD_RELOC_LO16, breg);
7117 if (! target_big_endian)
7118 offset_expr.X_add_number -= off;
7120 offset_expr.X_add_number += off;
7121 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7122 (int) BFD_RELOC_LO16, breg);
7136 load_address (&icnt, AT, &offset_expr, &used_at);
7138 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7139 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7140 "d,v,t", AT, AT, breg);
7141 if (! target_big_endian)
7142 expr1.X_add_number = off;
7144 expr1.X_add_number = 0;
7145 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7146 (int) BFD_RELOC_LO16, AT);
7147 if (! target_big_endian)
7148 expr1.X_add_number = 0;
7150 expr1.X_add_number = off;
7151 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7152 (int) BFD_RELOC_LO16, AT);
7158 load_address (&icnt, AT, &offset_expr, &used_at);
7160 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7161 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7162 "d,v,t", AT, AT, breg);
7163 if (target_big_endian)
7164 expr1.X_add_number = 0;
7165 macro_build ((char *) NULL, &icnt, &expr1,
7166 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
7167 (int) BFD_RELOC_LO16, AT);
7168 if (target_big_endian)
7169 expr1.X_add_number = 1;
7171 expr1.X_add_number = 0;
7172 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7173 (int) BFD_RELOC_LO16, AT);
7174 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7176 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7181 if (offset_expr.X_add_number >= 0x7fff)
7182 as_bad (_("operand overflow"));
7183 if (target_big_endian)
7184 ++offset_expr.X_add_number;
7185 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
7186 (int) BFD_RELOC_LO16, breg);
7187 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7189 if (target_big_endian)
7190 --offset_expr.X_add_number;
7192 ++offset_expr.X_add_number;
7193 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
7194 (int) BFD_RELOC_LO16, breg);
7207 if (offset_expr.X_add_number >= 0x8000 - off)
7208 as_bad (_("operand overflow"));
7209 if (! target_big_endian)
7210 offset_expr.X_add_number += off;
7211 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
7212 (int) BFD_RELOC_LO16, breg);
7213 if (! target_big_endian)
7214 offset_expr.X_add_number -= off;
7216 offset_expr.X_add_number += off;
7217 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
7218 (int) BFD_RELOC_LO16, breg);
7232 load_address (&icnt, AT, &offset_expr, &used_at);
7234 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7235 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7236 "d,v,t", AT, AT, breg);
7237 if (! target_big_endian)
7238 expr1.X_add_number = off;
7240 expr1.X_add_number = 0;
7241 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
7242 (int) BFD_RELOC_LO16, AT);
7243 if (! target_big_endian)
7244 expr1.X_add_number = 0;
7246 expr1.X_add_number = off;
7247 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
7248 (int) BFD_RELOC_LO16, AT);
7253 load_address (&icnt, AT, &offset_expr, &used_at);
7255 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7256 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
7257 "d,v,t", AT, AT, breg);
7258 if (! target_big_endian)
7259 expr1.X_add_number = 0;
7260 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7261 (int) BFD_RELOC_LO16, AT);
7262 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<",
7264 if (! target_big_endian)
7265 expr1.X_add_number = 1;
7267 expr1.X_add_number = 0;
7268 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
7269 (int) BFD_RELOC_LO16, AT);
7270 if (! target_big_endian)
7271 expr1.X_add_number = 0;
7273 expr1.X_add_number = 1;
7274 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
7275 (int) BFD_RELOC_LO16, AT);
7276 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
7278 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
7283 /* FIXME: Check if this is one of the itbl macros, since they
7284 are added dynamically. */
7285 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7289 as_warn (_("Macro used $at after \".set noat\""));
7292 /* Implement macros in mips16 mode. */
7296 struct mips_cl_insn *ip;
7299 int xreg, yreg, zreg, tmp;
7303 const char *s, *s2, *s3;
7305 mask = ip->insn_mo->mask;
7307 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7308 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7309 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7313 expr1.X_op = O_constant;
7314 expr1.X_op_symbol = NULL;
7315 expr1.X_add_symbol = NULL;
7316 expr1.X_add_number = 1;
7335 mips_emit_delays (true);
7336 ++mips_opts.noreorder;
7337 mips_any_noreorder = 1;
7338 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7339 dbl ? "ddiv" : "div",
7340 "0,x,y", xreg, yreg);
7341 expr1.X_add_number = 2;
7342 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7343 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6",
7346 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7347 since that causes an overflow. We should do that as well,
7348 but I don't see how to do the comparisons without a temporary
7350 --mips_opts.noreorder;
7351 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg);
7370 mips_emit_delays (true);
7371 ++mips_opts.noreorder;
7372 mips_any_noreorder = 1;
7373 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y",
7375 expr1.X_add_number = 2;
7376 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
7377 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break",
7379 --mips_opts.noreorder;
7380 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg);
7386 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7387 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7388 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x",
7397 if (imm_expr.X_op != O_constant)
7398 as_bad (_("Unsupported large constant"));
7399 imm_expr.X_add_number = -imm_expr.X_add_number;
7400 macro_build ((char *) NULL, &icnt, &imm_expr,
7401 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7405 if (imm_expr.X_op != O_constant)
7406 as_bad (_("Unsupported large constant"));
7407 imm_expr.X_add_number = -imm_expr.X_add_number;
7408 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
7413 if (imm_expr.X_op != O_constant)
7414 as_bad (_("Unsupported large constant"));
7415 imm_expr.X_add_number = -imm_expr.X_add_number;
7416 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
7439 goto do_reverse_branch;
7443 goto do_reverse_branch;
7455 goto do_reverse_branch;
7466 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
7468 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7495 goto do_addone_branch_i;
7500 goto do_addone_branch_i;
7515 goto do_addone_branch_i;
7522 if (imm_expr.X_op != O_constant)
7523 as_bad (_("Unsupported large constant"));
7524 ++imm_expr.X_add_number;
7527 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
7528 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
7532 expr1.X_add_number = 0;
7533 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
7535 move_register (&icnt, xreg, yreg);
7536 expr1.X_add_number = 2;
7537 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
7538 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
7539 "neg", "x,w", xreg, xreg);
7543 /* For consistency checking, verify that all bits are specified either
7544 by the match/mask part of the instruction definition, or by the
7547 validate_mips_insn (opc)
7548 const struct mips_opcode *opc;
7550 const char *p = opc->args;
7552 unsigned long used_bits = opc->mask;
7554 if ((used_bits & opc->match) != opc->match)
7556 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7557 opc->name, opc->args);
7560 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7567 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7568 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7570 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7571 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7572 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7573 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7575 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7576 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7578 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7580 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7581 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7582 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7583 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7584 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7585 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
7586 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7587 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7588 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7589 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7590 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7591 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
7592 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
7593 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
7594 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7595 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
7596 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7598 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
7599 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7600 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7601 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
7603 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7604 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
7605 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
7606 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7607 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7608 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7609 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
7610 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
7611 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7614 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
7615 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
7616 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7618 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7619 c, opc->name, opc->args);
7623 if (used_bits != 0xffffffff)
7625 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7626 ~used_bits & 0xffffffff, opc->name, opc->args);
7632 /* This routine assembles an instruction into its binary format. As a
7633 side effect, it sets one of the global variables imm_reloc or
7634 offset_reloc to the type of relocation to do if one of the operands
7635 is an address expression. */
7640 struct mips_cl_insn *ip;
7645 struct mips_opcode *insn;
7648 unsigned int lastregno = 0;
7654 /* If the instruction contains a '.', we first try to match an instruction
7655 including the '.'. Then we try again without the '.'. */
7657 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
7660 /* If we stopped on whitespace, then replace the whitespace with null for
7661 the call to hash_find. Save the character we replaced just in case we
7662 have to re-parse the instruction. */
7669 insn = (struct mips_opcode *) hash_find (op_hash, str);
7671 /* If we didn't find the instruction in the opcode table, try again, but
7672 this time with just the instruction up to, but not including the
7676 /* Restore the character we overwrite above (if any). */
7680 /* Scan up to the first '.' or whitespace. */
7682 *s != '\0' && *s != '.' && !ISSPACE (*s);
7686 /* If we did not find a '.', then we can quit now. */
7689 insn_error = "unrecognized opcode";
7693 /* Lookup the instruction in the hash table. */
7695 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
7697 insn_error = "unrecognized opcode";
7707 assert (strcmp (insn->name, str) == 0);
7709 if (OPCODE_IS_MEMBER (insn,
7711 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
7712 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
7718 if (insn->pinfo != INSN_MACRO)
7720 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7726 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7727 && strcmp (insn->name, insn[1].name) == 0)
7736 static char buf[100];
7738 _("opcode not supported on this processor: %s (%s)"),
7739 mips_cpu_to_str (mips_arch),
7740 mips_isa_to_str (mips_opts.isa));
7751 ip->insn_opcode = insn->match;
7753 for (args = insn->args;; ++args)
7757 s += strspn (s, " \t");
7761 case '\0': /* end of args */
7774 ip->insn_opcode |= lastregno << OP_SH_RS;
7778 ip->insn_opcode |= lastregno << OP_SH_RT;
7782 ip->insn_opcode |= lastregno << OP_SH_FT;
7786 ip->insn_opcode |= lastregno << OP_SH_FS;
7792 /* Handle optional base register.
7793 Either the base register is omitted or
7794 we must have a left paren. */
7795 /* This is dependent on the next operand specifier
7796 is a base register specification. */
7797 assert (args[1] == 'b' || args[1] == '5'
7798 || args[1] == '-' || args[1] == '4');
7802 case ')': /* these must match exactly */
7807 case '<': /* must be at least one digit */
7809 * According to the manual, if the shift amount is greater
7810 * than 31 or less than 0, then the shift amount should be
7811 * mod 32. In reality the mips assembler issues an error.
7812 * We issue a warning and mask out all but the low 5 bits.
7814 my_getExpression (&imm_expr, s);
7815 check_absolute_expr (ip, &imm_expr);
7816 if ((unsigned long) imm_expr.X_add_number > 31)
7818 as_warn (_("Improper shift amount (%lu)"),
7819 (unsigned long) imm_expr.X_add_number);
7820 imm_expr.X_add_number &= OP_MASK_SHAMT;
7822 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7823 imm_expr.X_op = O_absent;
7827 case '>': /* shift amount minus 32 */
7828 my_getExpression (&imm_expr, s);
7829 check_absolute_expr (ip, &imm_expr);
7830 if ((unsigned long) imm_expr.X_add_number < 32
7831 || (unsigned long) imm_expr.X_add_number > 63)
7833 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7834 imm_expr.X_op = O_absent;
7838 case 'k': /* cache code */
7839 case 'h': /* prefx code */
7840 my_getExpression (&imm_expr, s);
7841 check_absolute_expr (ip, &imm_expr);
7842 if ((unsigned long) imm_expr.X_add_number > 31)
7844 as_warn (_("Invalid value for `%s' (%lu)"),
7846 (unsigned long) imm_expr.X_add_number);
7847 imm_expr.X_add_number &= 0x1f;
7850 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7852 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7853 imm_expr.X_op = O_absent;
7857 case 'c': /* break code */
7858 my_getExpression (&imm_expr, s);
7859 check_absolute_expr (ip, &imm_expr);
7860 if ((unsigned long) imm_expr.X_add_number > 1023)
7862 as_warn (_("Illegal break code (%lu)"),
7863 (unsigned long) imm_expr.X_add_number);
7864 imm_expr.X_add_number &= OP_MASK_CODE;
7866 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7867 imm_expr.X_op = O_absent;
7871 case 'q': /* lower break code */
7872 my_getExpression (&imm_expr, s);
7873 check_absolute_expr (ip, &imm_expr);
7874 if ((unsigned long) imm_expr.X_add_number > 1023)
7876 as_warn (_("Illegal lower break code (%lu)"),
7877 (unsigned long) imm_expr.X_add_number);
7878 imm_expr.X_add_number &= OP_MASK_CODE2;
7880 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7881 imm_expr.X_op = O_absent;
7885 case 'B': /* 20-bit syscall/break code. */
7886 my_getExpression (&imm_expr, s);
7887 check_absolute_expr (ip, &imm_expr);
7888 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
7889 as_warn (_("Illegal 20-bit code (%lu)"),
7890 (unsigned long) imm_expr.X_add_number);
7891 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7892 imm_expr.X_op = O_absent;
7896 case 'C': /* Coprocessor code */
7897 my_getExpression (&imm_expr, s);
7898 check_absolute_expr (ip, &imm_expr);
7899 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
7901 as_warn (_("Coproccesor code > 25 bits (%lu)"),
7902 (unsigned long) imm_expr.X_add_number);
7903 imm_expr.X_add_number &= ((1 << 25) - 1);
7905 ip->insn_opcode |= imm_expr.X_add_number;
7906 imm_expr.X_op = O_absent;
7910 case 'J': /* 19-bit wait code. */
7911 my_getExpression (&imm_expr, s);
7912 check_absolute_expr (ip, &imm_expr);
7913 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
7914 as_warn (_("Illegal 19-bit code (%lu)"),
7915 (unsigned long) imm_expr.X_add_number);
7916 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7917 imm_expr.X_op = O_absent;
7921 case 'P': /* Performance register */
7922 my_getExpression (&imm_expr, s);
7923 check_absolute_expr (ip, &imm_expr);
7924 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7926 as_warn (_("Invalid performance register (%lu)"),
7927 (unsigned long) imm_expr.X_add_number);
7928 imm_expr.X_add_number &= OP_MASK_PERFREG;
7930 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7931 imm_expr.X_op = O_absent;
7935 case 'b': /* base register */
7936 case 'd': /* destination register */
7937 case 's': /* source register */
7938 case 't': /* target register */
7939 case 'r': /* both target and source */
7940 case 'v': /* both dest and source */
7941 case 'w': /* both dest and target */
7942 case 'E': /* coprocessor target register */
7943 case 'G': /* coprocessor destination register */
7944 case 'x': /* ignore register name */
7945 case 'z': /* must be zero register */
7946 case 'U': /* destination register (clo/clz). */
7961 while (ISDIGIT (*s));
7963 as_bad (_("Invalid register number (%d)"), regno);
7965 else if (*args == 'E' || *args == 'G')
7969 if (s[1] == 'r' && s[2] == 'a')
7974 else if (s[1] == 'f' && s[2] == 'p')
7979 else if (s[1] == 's' && s[2] == 'p')
7984 else if (s[1] == 'g' && s[2] == 'p')
7989 else if (s[1] == 'a' && s[2] == 't')
7994 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
7999 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8004 else if (itbl_have_entries)
8009 p = s + 1; /* advance past '$' */
8010 n = itbl_get_field (&p); /* n is name */
8012 /* See if this is a register defined in an
8014 if (itbl_get_reg_val (n, &r))
8016 /* Get_field advances to the start of
8017 the next field, so we need to back
8018 rack to the end of the last field. */
8022 s = strchr (s, '\0');
8035 as_warn (_("Used $at without \".set noat\""));
8041 if (c == 'r' || c == 'v' || c == 'w')
8048 /* 'z' only matches $0. */
8049 if (c == 'z' && regno != 0)
8052 /* Now that we have assembled one operand, we use the args string
8053 * to figure out where it goes in the instruction. */
8060 ip->insn_opcode |= regno << OP_SH_RS;
8064 ip->insn_opcode |= regno << OP_SH_RD;
8067 ip->insn_opcode |= regno << OP_SH_RD;
8068 ip->insn_opcode |= regno << OP_SH_RT;
8073 ip->insn_opcode |= regno << OP_SH_RT;
8076 /* This case exists because on the r3000 trunc
8077 expands into a macro which requires a gp
8078 register. On the r6000 or r4000 it is
8079 assembled into a single instruction which
8080 ignores the register. Thus the insn version
8081 is MIPS_ISA2 and uses 'x', and the macro
8082 version is MIPS_ISA1 and uses 't'. */
8085 /* This case is for the div instruction, which
8086 acts differently if the destination argument
8087 is $0. This only matches $0, and is checked
8088 outside the switch. */
8091 /* Itbl operand; not yet implemented. FIXME ?? */
8093 /* What about all other operands like 'i', which
8094 can be specified in the opcode table? */
8104 ip->insn_opcode |= lastregno << OP_SH_RS;
8107 ip->insn_opcode |= lastregno << OP_SH_RT;
8112 case 'O': /* MDMX alignment immediate constant. */
8113 my_getExpression (&imm_expr, s);
8114 check_absolute_expr (ip, &imm_expr);
8115 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8117 as_warn ("Improper align amount (%ld), using low bits",
8118 (long) imm_expr.X_add_number);
8119 imm_expr.X_add_number &= OP_MASK_ALN;
8121 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8122 imm_expr.X_op = O_absent;
8126 case 'Q': /* MDMX vector, element sel, or const. */
8129 /* MDMX Immediate. */
8130 my_getExpression (&imm_expr, s);
8131 check_absolute_expr (ip, &imm_expr);
8132 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8134 as_warn (_("Invalid MDMX Immediate (%ld)"),
8135 (long) imm_expr.X_add_number);
8136 imm_expr.X_add_number &= OP_MASK_FT;
8138 imm_expr.X_add_number &= OP_MASK_FT;
8139 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8140 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8142 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8143 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8144 imm_expr.X_op = O_absent;
8148 /* Not MDMX Immediate. Fall through. */
8149 case 'X': /* MDMX destination register. */
8150 case 'Y': /* MDMX source register. */
8151 case 'Z': /* MDMX target register. */
8153 case 'D': /* floating point destination register */
8154 case 'S': /* floating point source register */
8155 case 'T': /* floating point target register */
8156 case 'R': /* floating point source register */
8160 /* Accept $fN for FP and MDMX register numbers, and in
8161 addition accept $vN for MDMX register numbers. */
8162 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8163 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8174 while (ISDIGIT (*s));
8177 as_bad (_("Invalid float register number (%d)"), regno);
8179 if ((regno & 1) != 0
8181 && ! (strcmp (str, "mtc1") == 0
8182 || strcmp (str, "mfc1") == 0
8183 || strcmp (str, "lwc1") == 0
8184 || strcmp (str, "swc1") == 0
8185 || strcmp (str, "l.s") == 0
8186 || strcmp (str, "s.s") == 0))
8187 as_warn (_("Float register should be even, was %d"),
8195 if (c == 'V' || c == 'W')
8206 ip->insn_opcode |= regno << OP_SH_FD;
8211 ip->insn_opcode |= regno << OP_SH_FS;
8214 /* This is like 'Z', but also needs to fix the MDMX
8215 vector/scalar select bits. Note that the
8216 scalar immediate case is handled above. */
8219 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8220 int max_el = (is_qh ? 3 : 7);
8222 my_getExpression(&imm_expr, s);
8223 check_absolute_expr (ip, &imm_expr);
8225 if (imm_expr.X_add_number > max_el)
8226 as_bad(_("Bad element selector %ld"),
8227 (long) imm_expr.X_add_number);
8228 imm_expr.X_add_number &= max_el;
8229 ip->insn_opcode |= (imm_expr.X_add_number
8233 as_warn(_("Expecting ']' found '%s'"), s);
8239 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8240 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8243 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8250 ip->insn_opcode |= regno << OP_SH_FT;
8253 ip->insn_opcode |= regno << OP_SH_FR;
8263 ip->insn_opcode |= lastregno << OP_SH_FS;
8266 ip->insn_opcode |= lastregno << OP_SH_FT;
8272 my_getExpression (&imm_expr, s);
8273 if (imm_expr.X_op != O_big
8274 && imm_expr.X_op != O_constant)
8275 insn_error = _("absolute expression required");
8280 my_getExpression (&offset_expr, s);
8281 *imm_reloc = BFD_RELOC_32;
8294 unsigned char temp[8];
8296 unsigned int length;
8301 /* These only appear as the last operand in an
8302 instruction, and every instruction that accepts
8303 them in any variant accepts them in all variants.
8304 This means we don't have to worry about backing out
8305 any changes if the instruction does not match.
8307 The difference between them is the size of the
8308 floating point constant and where it goes. For 'F'
8309 and 'L' the constant is 64 bits; for 'f' and 'l' it
8310 is 32 bits. Where the constant is placed is based
8311 on how the MIPS assembler does things:
8314 f -- immediate value
8317 The .lit4 and .lit8 sections are only used if
8318 permitted by the -G argument.
8320 When generating embedded PIC code, we use the
8321 .lit8 section but not the .lit4 section (we can do
8322 .lit4 inline easily; we need to put .lit8
8323 somewhere in the data segment, and using .lit8
8324 permits the linker to eventually combine identical
8327 The code below needs to know whether the target register
8328 is 32 or 64 bits wide. It relies on the fact 'f' and
8329 'F' are used with GPR-based instructions and 'l' and
8330 'L' are used with FPR-based instructions. */
8332 f64 = *args == 'F' || *args == 'L';
8333 using_gprs = *args == 'F' || *args == 'f';
8335 save_in = input_line_pointer;
8336 input_line_pointer = s;
8337 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8339 s = input_line_pointer;
8340 input_line_pointer = save_in;
8341 if (err != NULL && *err != '\0')
8343 as_bad (_("Bad floating point constant: %s"), err);
8344 memset (temp, '\0', sizeof temp);
8345 length = f64 ? 8 : 4;
8348 assert (length == (unsigned) (f64 ? 8 : 4));
8352 && (! USE_GLOBAL_POINTER_OPT
8353 || mips_pic == EMBEDDED_PIC
8354 || g_switch_value < 4
8355 || (temp[0] == 0 && temp[1] == 0)
8356 || (temp[2] == 0 && temp[3] == 0))))
8358 imm_expr.X_op = O_constant;
8359 if (! target_big_endian)
8360 imm_expr.X_add_number = bfd_getl32 (temp);
8362 imm_expr.X_add_number = bfd_getb32 (temp);
8365 && ! mips_disable_float_construction
8366 /* Constants can only be constructed in GPRs and
8367 copied to FPRs if the GPRs are at least as wide
8368 as the FPRs. Force the constant into memory if
8369 we are using 64-bit FPRs but the GPRs are only
8372 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8373 && ((temp[0] == 0 && temp[1] == 0)
8374 || (temp[2] == 0 && temp[3] == 0))
8375 && ((temp[4] == 0 && temp[5] == 0)
8376 || (temp[6] == 0 && temp[7] == 0)))
8378 /* The value is simple enough to load with a couple of
8379 instructions. If using 32-bit registers, set
8380 imm_expr to the high order 32 bits and offset_expr to
8381 the low order 32 bits. Otherwise, set imm_expr to
8382 the entire 64 bit constant. */
8383 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8385 imm_expr.X_op = O_constant;
8386 offset_expr.X_op = O_constant;
8387 if (! target_big_endian)
8389 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8390 offset_expr.X_add_number = bfd_getl32 (temp);
8394 imm_expr.X_add_number = bfd_getb32 (temp);
8395 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8397 if (offset_expr.X_add_number == 0)
8398 offset_expr.X_op = O_absent;
8400 else if (sizeof (imm_expr.X_add_number) > 4)
8402 imm_expr.X_op = O_constant;
8403 if (! target_big_endian)
8404 imm_expr.X_add_number = bfd_getl64 (temp);
8406 imm_expr.X_add_number = bfd_getb64 (temp);
8410 imm_expr.X_op = O_big;
8411 imm_expr.X_add_number = 4;
8412 if (! target_big_endian)
8414 generic_bignum[0] = bfd_getl16 (temp);
8415 generic_bignum[1] = bfd_getl16 (temp + 2);
8416 generic_bignum[2] = bfd_getl16 (temp + 4);
8417 generic_bignum[3] = bfd_getl16 (temp + 6);
8421 generic_bignum[0] = bfd_getb16 (temp + 6);
8422 generic_bignum[1] = bfd_getb16 (temp + 4);
8423 generic_bignum[2] = bfd_getb16 (temp + 2);
8424 generic_bignum[3] = bfd_getb16 (temp);
8430 const char *newname;
8433 /* Switch to the right section. */
8435 subseg = now_subseg;
8438 default: /* unused default case avoids warnings. */
8440 newname = RDATA_SECTION_NAME;
8441 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8442 || mips_pic == EMBEDDED_PIC)
8446 if (mips_pic == EMBEDDED_PIC)
8449 newname = RDATA_SECTION_NAME;
8452 assert (!USE_GLOBAL_POINTER_OPT
8453 || g_switch_value >= 4);
8457 new_seg = subseg_new (newname, (subsegT) 0);
8458 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
8459 bfd_set_section_flags (stdoutput, new_seg,
8464 frag_align (*args == 'l' ? 2 : 3, 0, 0);
8465 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
8466 && strcmp (TARGET_OS, "elf") != 0)
8467 record_alignment (new_seg, 4);
8469 record_alignment (new_seg, *args == 'l' ? 2 : 3);
8471 as_bad (_("Can't use floating point insn in this section"));
8473 /* Set the argument to the current address in the
8475 offset_expr.X_op = O_symbol;
8476 offset_expr.X_add_symbol =
8477 symbol_new ("L0\001", now_seg,
8478 (valueT) frag_now_fix (), frag_now);
8479 offset_expr.X_add_number = 0;
8481 /* Put the floating point number into the section. */
8482 p = frag_more ((int) length);
8483 memcpy (p, temp, length);
8485 /* Switch back to the original section. */
8486 subseg_set (seg, subseg);
8491 case 'i': /* 16 bit unsigned immediate */
8492 case 'j': /* 16 bit signed immediate */
8493 *imm_reloc = BFD_RELOC_LO16;
8494 c = my_getSmallExpression (&imm_expr, s);
8499 if (imm_expr.X_op == O_constant)
8500 imm_expr.X_add_number =
8501 (imm_expr.X_add_number >> 16) & 0xffff;
8503 else if (c == S_EX_HIGHEST)
8504 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8505 else if (c == S_EX_HIGHER)
8506 *imm_reloc = BFD_RELOC_MIPS_HIGHER;
8507 else if (c == S_EX_GP_REL)
8509 /* This occurs in NewABI only. */
8510 c = my_getSmallExpression (&imm_expr, s);
8512 as_bad (_("bad composition of relocations"));
8515 c = my_getSmallExpression (&imm_expr, s);
8517 as_bad (_("bad composition of relocations"));
8520 imm_reloc[0] = BFD_RELOC_GPREL16;
8521 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8522 imm_reloc[2] = BFD_RELOC_LO16;
8527 else if (c == S_EX_HI)
8529 *imm_reloc = BFD_RELOC_HI16_S;
8530 imm_unmatched_hi = true;
8533 *imm_reloc = BFD_RELOC_HI16;
8535 else if (imm_expr.X_op == O_constant)
8536 imm_expr.X_add_number &= 0xffff;
8540 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8541 || ((imm_expr.X_add_number < 0
8542 || imm_expr.X_add_number >= 0x10000)
8543 && imm_expr.X_op == O_constant))
8545 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8546 !strcmp (insn->name, insn[1].name))
8548 if (imm_expr.X_op == O_constant
8549 || imm_expr.X_op == O_big)
8550 as_bad (_("16 bit expression not in range 0..65535"));
8558 /* The upper bound should be 0x8000, but
8559 unfortunately the MIPS assembler accepts numbers
8560 from 0x8000 to 0xffff and sign extends them, and
8561 we want to be compatible. We only permit this
8562 extended range for an instruction which does not
8563 provide any further alternates, since those
8564 alternates may handle other cases. People should
8565 use the numbers they mean, rather than relying on
8566 a mysterious sign extension. */
8567 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8568 strcmp (insn->name, insn[1].name) == 0);
8573 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
8574 || ((imm_expr.X_add_number < -0x8000
8575 || imm_expr.X_add_number >= max)
8576 && imm_expr.X_op == O_constant)
8578 && imm_expr.X_add_number < 0
8580 && imm_expr.X_unsigned
8581 && sizeof (imm_expr.X_add_number) <= 4))
8585 if (imm_expr.X_op == O_constant
8586 || imm_expr.X_op == O_big)
8587 as_bad (_("16 bit expression not in range -32768..32767"));
8593 case 'o': /* 16 bit offset */
8594 c = my_getSmallExpression (&offset_expr, s);
8596 /* If this value won't fit into a 16 bit offset, then go
8597 find a macro that will generate the 32 bit offset
8600 && (offset_expr.X_op != O_constant
8601 || offset_expr.X_add_number >= 0x8000
8602 || offset_expr.X_add_number < -0x8000))
8607 if (offset_expr.X_op != O_constant)
8609 offset_expr.X_add_number =
8610 (offset_expr.X_add_number >> 16) & 0xffff;
8612 *offset_reloc = BFD_RELOC_LO16;
8616 case 'p': /* pc relative offset */
8617 if (mips_pic == EMBEDDED_PIC)
8618 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8620 *offset_reloc = BFD_RELOC_16_PCREL;
8621 my_getExpression (&offset_expr, s);
8625 case 'u': /* upper 16 bits */
8626 c = my_getSmallExpression (&imm_expr, s);
8627 *imm_reloc = BFD_RELOC_LO16;
8632 if (imm_expr.X_op == O_constant)
8633 imm_expr.X_add_number =
8634 (imm_expr.X_add_number >> 16) & 0xffff;
8635 else if (c == S_EX_HI)
8637 *imm_reloc = BFD_RELOC_HI16_S;
8638 imm_unmatched_hi = true;
8641 else if (c == S_EX_HIGHEST)
8642 *imm_reloc = BFD_RELOC_MIPS_HIGHEST;
8643 else if (c == S_EX_GP_REL)
8645 /* This occurs in NewABI only. */
8646 c = my_getSmallExpression (&imm_expr, s);
8648 as_bad (_("bad composition of relocations"));
8651 c = my_getSmallExpression (&imm_expr, s);
8653 as_bad (_("bad composition of relocations"));
8656 imm_reloc[0] = BFD_RELOC_GPREL16;
8657 imm_reloc[1] = BFD_RELOC_MIPS_SUB;
8658 imm_reloc[2] = BFD_RELOC_HI16_S;
8664 *imm_reloc = BFD_RELOC_HI16;
8666 else if (imm_expr.X_op == O_constant)
8667 imm_expr.X_add_number &= 0xffff;
8669 if (imm_expr.X_op == O_constant
8670 && (imm_expr.X_add_number < 0
8671 || imm_expr.X_add_number >= 0x10000))
8672 as_bad (_("lui expression not in range 0..65535"));
8676 case 'a': /* 26 bit address */
8677 my_getExpression (&offset_expr, s);
8679 *offset_reloc = BFD_RELOC_MIPS_JMP;
8682 case 'N': /* 3 bit branch condition code */
8683 case 'M': /* 3 bit compare condition code */
8684 if (strncmp (s, "$fcc", 4) != 0)
8694 while (ISDIGIT (*s));
8696 as_bad (_("invalid condition code register $fcc%d"), regno);
8698 ip->insn_opcode |= regno << OP_SH_BCC;
8700 ip->insn_opcode |= regno << OP_SH_CCC;
8704 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
8715 while (ISDIGIT (*s));
8718 c = 8; /* Invalid sel value. */
8721 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8722 ip->insn_opcode |= c;
8726 as_bad (_("bad char = '%c'\n"), *args);
8731 /* Args don't match. */
8732 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
8733 !strcmp (insn->name, insn[1].name))
8737 insn_error = _("illegal operands");
8742 insn_error = _("illegal operands");
8747 /* This routine assembles an instruction into its binary format when
8748 assembling for the mips16. As a side effect, it sets one of the
8749 global variables imm_reloc or offset_reloc to the type of
8750 relocation to do if one of the operands is an address expression.
8751 It also sets mips16_small and mips16_ext if the user explicitly
8752 requested a small or extended instruction. */
8757 struct mips_cl_insn *ip;
8761 struct mips_opcode *insn;
8764 unsigned int lastregno = 0;
8769 mips16_small = false;
8772 for (s = str; ISLOWER (*s); ++s)
8784 if (s[1] == 't' && s[2] == ' ')
8787 mips16_small = true;
8791 else if (s[1] == 'e' && s[2] == ' ')
8800 insn_error = _("unknown opcode");
8804 if (mips_opts.noautoextend && ! mips16_ext)
8805 mips16_small = true;
8807 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
8809 insn_error = _("unrecognized opcode");
8816 assert (strcmp (insn->name, str) == 0);
8819 ip->insn_opcode = insn->match;
8820 ip->use_extend = false;
8821 imm_expr.X_op = O_absent;
8822 imm_reloc[0] = BFD_RELOC_UNUSED;
8823 imm_reloc[1] = BFD_RELOC_UNUSED;
8824 imm_reloc[2] = BFD_RELOC_UNUSED;
8825 offset_expr.X_op = O_absent;
8826 offset_reloc[0] = BFD_RELOC_UNUSED;
8827 offset_reloc[1] = BFD_RELOC_UNUSED;
8828 offset_reloc[2] = BFD_RELOC_UNUSED;
8829 for (args = insn->args; 1; ++args)
8836 /* In this switch statement we call break if we did not find
8837 a match, continue if we did find a match, or return if we
8846 /* Stuff the immediate value in now, if we can. */
8847 if (imm_expr.X_op == O_constant
8848 && *imm_reloc > BFD_RELOC_UNUSED
8849 && insn->pinfo != INSN_MACRO)
8851 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
8852 imm_expr.X_add_number, true, mips16_small,
8853 mips16_ext, &ip->insn_opcode,
8854 &ip->use_extend, &ip->extend);
8855 imm_expr.X_op = O_absent;
8856 *imm_reloc = BFD_RELOC_UNUSED;
8870 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8873 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8889 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8891 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8918 while (ISDIGIT (*s));
8921 as_bad (_("invalid register number (%d)"), regno);
8927 if (s[1] == 'r' && s[2] == 'a')
8932 else if (s[1] == 'f' && s[2] == 'p')
8937 else if (s[1] == 's' && s[2] == 'p')
8942 else if (s[1] == 'g' && s[2] == 'p')
8947 else if (s[1] == 'a' && s[2] == 't')
8952 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8957 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8970 if (c == 'v' || c == 'w')
8972 regno = mips16_to_32_reg_map[lastregno];
8986 regno = mips32_to_16_reg_map[regno];
8991 regno = ILLEGAL_REG;
8996 regno = ILLEGAL_REG;
9001 regno = ILLEGAL_REG;
9006 if (regno == AT && ! mips_opts.noat)
9007 as_warn (_("used $at without \".set noat\""));
9014 if (regno == ILLEGAL_REG)
9021 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9025 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9028 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9031 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9037 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9040 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9041 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9051 if (strncmp (s, "$pc", 3) == 0)
9075 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9077 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9078 and generate the appropriate reloc. If the text
9079 inside %gprel is not a symbol name with an
9080 optional offset, then we generate a normal reloc
9081 and will probably fail later. */
9082 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9083 if (imm_expr.X_op == O_symbol)
9086 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9088 ip->use_extend = true;
9095 /* Just pick up a normal expression. */
9096 my_getExpression (&imm_expr, s);
9099 if (imm_expr.X_op == O_register)
9101 /* What we thought was an expression turned out to
9104 if (s[0] == '(' && args[1] == '(')
9106 /* It looks like the expression was omitted
9107 before a register indirection, which means
9108 that the expression is implicitly zero. We
9109 still set up imm_expr, so that we handle
9110 explicit extensions correctly. */
9111 imm_expr.X_op = O_constant;
9112 imm_expr.X_add_number = 0;
9113 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9120 /* We need to relax this instruction. */
9121 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9130 /* We use offset_reloc rather than imm_reloc for the PC
9131 relative operands. This lets macros with both
9132 immediate and address operands work correctly. */
9133 my_getExpression (&offset_expr, s);
9135 if (offset_expr.X_op == O_register)
9138 /* We need to relax this instruction. */
9139 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9143 case '6': /* break code */
9144 my_getExpression (&imm_expr, s);
9145 check_absolute_expr (ip, &imm_expr);
9146 if ((unsigned long) imm_expr.X_add_number > 63)
9148 as_warn (_("Invalid value for `%s' (%lu)"),
9150 (unsigned long) imm_expr.X_add_number);
9151 imm_expr.X_add_number &= 0x3f;
9153 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9154 imm_expr.X_op = O_absent;
9158 case 'a': /* 26 bit address */
9159 my_getExpression (&offset_expr, s);
9161 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9162 ip->insn_opcode <<= 16;
9165 case 'l': /* register list for entry macro */
9166 case 'L': /* register list for exit macro */
9176 int freg, reg1, reg2;
9178 while (*s == ' ' || *s == ',')
9182 as_bad (_("can't parse register list"));
9194 while (ISDIGIT (*s))
9216 as_bad (_("invalid register list"));
9221 while (ISDIGIT (*s))
9228 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9233 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9238 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9239 mask |= (reg2 - 3) << 3;
9240 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9241 mask |= (reg2 - 15) << 1;
9242 else if (reg1 == RA && reg2 == RA)
9246 as_bad (_("invalid register list"));
9250 /* The mask is filled in in the opcode table for the
9251 benefit of the disassembler. We remove it before
9252 applying the actual mask. */
9253 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9254 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9258 case 'e': /* extend code */
9259 my_getExpression (&imm_expr, s);
9260 check_absolute_expr (ip, &imm_expr);
9261 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9263 as_warn (_("Invalid value for `%s' (%lu)"),
9265 (unsigned long) imm_expr.X_add_number);
9266 imm_expr.X_add_number &= 0x7ff;
9268 ip->insn_opcode |= imm_expr.X_add_number;
9269 imm_expr.X_op = O_absent;
9279 /* Args don't match. */
9280 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9281 strcmp (insn->name, insn[1].name) == 0)
9288 insn_error = _("illegal operands");
9294 /* This structure holds information we know about a mips16 immediate
9297 struct mips16_immed_operand
9299 /* The type code used in the argument string in the opcode table. */
9301 /* The number of bits in the short form of the opcode. */
9303 /* The number of bits in the extended form of the opcode. */
9305 /* The amount by which the short form is shifted when it is used;
9306 for example, the sw instruction has a shift count of 2. */
9308 /* The amount by which the short form is shifted when it is stored
9309 into the instruction code. */
9311 /* Non-zero if the short form is unsigned. */
9313 /* Non-zero if the extended form is unsigned. */
9315 /* Non-zero if the value is PC relative. */
9319 /* The mips16 immediate operand types. */
9321 static const struct mips16_immed_operand mips16_immed_operands[] =
9323 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9324 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9325 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9326 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9327 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9328 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9329 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9330 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9331 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9332 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9333 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9334 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9335 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9336 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9337 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9338 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9339 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9340 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9341 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9342 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9343 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9346 #define MIPS16_NUM_IMMED \
9347 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9349 /* Handle a mips16 instruction with an immediate value. This or's the
9350 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9351 whether an extended value is needed; if one is needed, it sets
9352 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9353 If SMALL is true, an unextended opcode was explicitly requested.
9354 If EXT is true, an extended opcode was explicitly requested. If
9355 WARN is true, warn if EXT does not match reality. */
9358 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
9367 unsigned long *insn;
9368 boolean *use_extend;
9369 unsigned short *extend;
9371 register const struct mips16_immed_operand *op;
9372 int mintiny, maxtiny;
9375 op = mips16_immed_operands;
9376 while (op->type != type)
9379 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9384 if (type == '<' || type == '>' || type == '[' || type == ']')
9387 maxtiny = 1 << op->nbits;
9392 maxtiny = (1 << op->nbits) - 1;
9397 mintiny = - (1 << (op->nbits - 1));
9398 maxtiny = (1 << (op->nbits - 1)) - 1;
9401 /* Branch offsets have an implicit 0 in the lowest bit. */
9402 if (type == 'p' || type == 'q')
9405 if ((val & ((1 << op->shift) - 1)) != 0
9406 || val < (mintiny << op->shift)
9407 || val > (maxtiny << op->shift))
9412 if (warn && ext && ! needext)
9413 as_warn_where (file, line,
9414 _("extended operand requested but not required"));
9415 if (small && needext)
9416 as_bad_where (file, line, _("invalid unextended operand value"));
9418 if (small || (! ext && ! needext))
9422 *use_extend = false;
9423 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9424 insnval <<= op->op_shift;
9429 long minext, maxext;
9435 maxext = (1 << op->extbits) - 1;
9439 minext = - (1 << (op->extbits - 1));
9440 maxext = (1 << (op->extbits - 1)) - 1;
9442 if (val < minext || val > maxext)
9443 as_bad_where (file, line,
9444 _("operand value out of range for instruction"));
9447 if (op->extbits == 16)
9449 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9452 else if (op->extbits == 15)
9454 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9459 extval = ((val & 0x1f) << 6) | (val & 0x20);
9463 *extend = (unsigned short) extval;
9468 static struct percent_op_match
9471 const enum small_ex_type type;
9476 {"%call_hi", S_EX_CALL_HI},
9477 {"%call_lo", S_EX_CALL_LO},
9478 {"%call16", S_EX_CALL16},
9479 {"%got_disp", S_EX_GOT_DISP},
9480 {"%got_page", S_EX_GOT_PAGE},
9481 {"%got_ofst", S_EX_GOT_OFST},
9482 {"%got_hi", S_EX_GOT_HI},
9483 {"%got_lo", S_EX_GOT_LO},
9485 {"%gp_rel", S_EX_GP_REL},
9486 {"%half", S_EX_HALF},
9487 {"%highest", S_EX_HIGHEST},
9488 {"%higher", S_EX_HIGHER},
9494 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9495 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9496 can be nested, this is handled by blanking the innermost, parsing the
9497 rest by subsequent calls. */
9500 my_getSmallParser (str, len, nestlevel)
9506 *str += strspn (*str, " \t");
9507 /* Check for expression in parentheses. */
9510 char *b = *str + 1 + strspn (*str + 1, " \t");
9513 /* Check for base register. */
9517 && (e = b + strcspn (b, ") \t"))
9518 && e - b > 1 && e - b < 4)
9521 && ((b[1] == 'f' && b[2] == 'p')
9522 || (b[1] == 's' && b[2] == 'p')
9523 || (b[1] == 'g' && b[2] == 'p')
9524 || (b[1] == 'a' && b[2] == 't')
9526 && ISDIGIT (b[2]))))
9527 || (ISDIGIT (b[1])))
9529 *len = strcspn (*str, ")") + 1;
9530 return S_EX_REGISTER;
9534 /* Check for percent_op (in parentheses). */
9535 else if (b[0] == '%')
9538 return my_getPercentOp (str, len, nestlevel);
9541 /* Some other expression in the parentheses, which can contain
9542 parentheses itself. Attempt to find the matching one. */
9548 for (s = *str + 1; *s && pcnt; s++, (*len)++)
9557 /* Check for percent_op (outside of parentheses). */
9558 else if (*str[0] == '%')
9559 return my_getPercentOp (str, len, nestlevel);
9561 /* Any other expression. */
9566 my_getPercentOp (str, len, nestlevel)
9571 char *tmp = *str + 1;
9574 while (ISALPHA (*tmp) || *tmp == '_')
9576 *tmp = TOLOWER (*tmp);
9579 while (i < (sizeof (percent_op) / sizeof (struct percent_op_match)))
9581 if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str)))
9585 int type = percent_op[i].type;
9587 /* Only %hi and %lo are allowed for OldABI. */
9588 if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO)
9591 *len = strlen (percent_op[i].str);
9600 my_getSmallExpression (ep, str)
9604 static char *oldstr = NULL;
9610 /* Don't update oldstr if the last call had nested percent_op's. We need
9611 it to parse the outer ones later. */
9618 c = my_getSmallParser (&str, &len, &nestlevel);
9619 if (c != S_EX_NONE && c != S_EX_REGISTER)
9622 while (c != S_EX_NONE && c != S_EX_REGISTER);
9626 /* A percent_op was encountered. Don't try to get an expression if
9627 it is already blanked out. */
9628 if (*(str + strspn (str + 1, " )")) != ')')
9632 /* Let my_getExpression() stop at the closing parenthesis. */
9633 save = *(str + len);
9634 *(str + len) = '\0';
9635 my_getExpression (ep, str);
9636 *(str + len) = save;
9640 /* Blank out including the % sign and the proper matching
9643 char *s = strrchr (oldstr, '%');
9646 for (end = strchr (s, '(') + 1; *end && pcnt; end++)
9650 else if (*end == ')')
9654 memset (s, ' ', end - s);
9658 expr_end = str + len;
9662 else if (c == S_EX_NONE)
9664 my_getExpression (ep, str);
9666 else if (c == S_EX_REGISTER)
9668 ep->X_op = O_constant;
9670 ep->X_add_symbol = NULL;
9671 ep->X_op_symbol = NULL;
9672 ep->X_add_number = 0;
9676 as_fatal (_("internal error"));
9680 /* All percent_op's have been handled. */
9687 my_getExpression (ep, str)
9694 save_in = input_line_pointer;
9695 input_line_pointer = str;
9697 expr_end = input_line_pointer;
9698 input_line_pointer = save_in;
9700 /* If we are in mips16 mode, and this is an expression based on `.',
9701 then we bump the value of the symbol by 1 since that is how other
9702 text symbols are handled. We don't bother to handle complex
9703 expressions, just `.' plus or minus a constant. */
9704 if (mips_opts.mips16
9705 && ep->X_op == O_symbol
9706 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
9707 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
9708 && symbol_get_frag (ep->X_add_symbol) == frag_now
9709 && symbol_constant_p (ep->X_add_symbol)
9710 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
9711 S_SET_VALUE (ep->X_add_symbol, val + 1);
9714 /* Turn a string in input_line_pointer into a floating point constant
9715 of type TYPE, and store the appropriate bytes in *LITP. The number
9716 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9717 returned, or NULL on OK. */
9720 md_atof (type, litP, sizeP)
9726 LITTLENUM_TYPE words[4];
9742 return _("bad call to md_atof");
9745 t = atof_ieee (input_line_pointer, type, words);
9747 input_line_pointer = t;
9751 if (! target_big_endian)
9753 for (i = prec - 1; i >= 0; i--)
9755 md_number_to_chars (litP, (valueT) words[i], 2);
9761 for (i = 0; i < prec; i++)
9763 md_number_to_chars (litP, (valueT) words[i], 2);
9772 md_number_to_chars (buf, val, n)
9777 if (target_big_endian)
9778 number_to_chars_bigendian (buf, val, n);
9780 number_to_chars_littleendian (buf, val, n);
9784 static int support_64bit_objects(void)
9786 const char **list, **l;
9788 list = bfd_target_list ();
9789 for (l = list; *l != NULL; l++)
9791 /* This is traditional mips */
9792 if (strcmp (*l, "elf64-tradbigmips") == 0
9793 || strcmp (*l, "elf64-tradlittlemips") == 0)
9795 if (strcmp (*l, "elf64-bigmips") == 0
9796 || strcmp (*l, "elf64-littlemips") == 0)
9800 return (*l != NULL);
9802 #endif /* OBJ_ELF */
9804 CONST char *md_shortopts = "nO::g::G:";
9806 struct option md_longopts[] =
9808 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9809 {"mips0", no_argument, NULL, OPTION_MIPS1},
9810 {"mips1", no_argument, NULL, OPTION_MIPS1},
9811 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9812 {"mips2", no_argument, NULL, OPTION_MIPS2},
9813 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9814 {"mips3", no_argument, NULL, OPTION_MIPS3},
9815 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9816 {"mips4", no_argument, NULL, OPTION_MIPS4},
9817 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9818 {"mips5", no_argument, NULL, OPTION_MIPS5},
9819 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9820 {"mips32", no_argument, NULL, OPTION_MIPS32},
9821 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9822 {"mips64", no_argument, NULL, OPTION_MIPS64},
9823 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9824 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
9825 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9826 {"trap", no_argument, NULL, OPTION_TRAP},
9827 {"no-break", no_argument, NULL, OPTION_TRAP},
9828 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9829 {"break", no_argument, NULL, OPTION_BREAK},
9830 {"no-trap", no_argument, NULL, OPTION_BREAK},
9831 #define OPTION_EB (OPTION_MD_BASE + 11)
9832 {"EB", no_argument, NULL, OPTION_EB},
9833 #define OPTION_EL (OPTION_MD_BASE + 12)
9834 {"EL", no_argument, NULL, OPTION_EL},
9835 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9836 {"mips16", no_argument, NULL, OPTION_MIPS16},
9837 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9838 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
9839 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9840 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
9841 #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16)
9842 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9843 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
9844 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9845 {"mfp32", no_argument, NULL, OPTION_FP32},
9846 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9847 {"mgp32", no_argument, NULL, OPTION_GP32},
9848 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9849 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
9850 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9851 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
9852 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9853 {"march", required_argument, NULL, OPTION_MARCH},
9854 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9855 {"mtune", required_argument, NULL, OPTION_MTUNE},
9856 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9857 {"mcpu", required_argument, NULL, OPTION_MCPU},
9858 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9859 {"m4650", no_argument, NULL, OPTION_M4650},
9860 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9861 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
9862 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9863 {"m4010", no_argument, NULL, OPTION_M4010},
9864 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9865 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
9866 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9867 {"m4100", no_argument, NULL, OPTION_M4100},
9868 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9869 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
9870 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9871 {"m3900", no_argument, NULL, OPTION_M3900},
9872 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9873 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
9874 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9875 {"mgp64", no_argument, NULL, OPTION_GP64},
9876 #define OPTION_MIPS3D (OPTION_MD_BASE + 33)
9877 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
9878 #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34)
9879 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
9880 #define OPTION_MDMX (OPTION_MD_BASE + 35)
9881 {"mdmx", no_argument, NULL, OPTION_MDMX},
9882 #define OPTION_NO_MDMX (OPTION_MD_BASE + 36)
9883 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
9885 #define OPTION_ELF_BASE (OPTION_MD_BASE + 37)
9886 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9887 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
9888 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
9889 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9890 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
9891 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9892 {"xgot", no_argument, NULL, OPTION_XGOT},
9893 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9894 {"mabi", required_argument, NULL, OPTION_MABI},
9895 #define OPTION_32 (OPTION_ELF_BASE + 4)
9896 {"32", no_argument, NULL, OPTION_32},
9897 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9898 {"n32", no_argument, NULL, OPTION_N32},
9899 #define OPTION_64 (OPTION_ELF_BASE + 6)
9900 {"64", no_argument, NULL, OPTION_64},
9901 #endif /* OBJ_ELF */
9902 {NULL, no_argument, NULL, 0}
9904 size_t md_longopts_size = sizeof (md_longopts);
9907 md_parse_option (c, arg)
9913 case OPTION_CONSTRUCT_FLOATS:
9914 mips_disable_float_construction = 0;
9917 case OPTION_NO_CONSTRUCT_FLOATS:
9918 mips_disable_float_construction = 1;
9930 target_big_endian = 1;
9934 target_big_endian = 0;
9942 if (arg && arg[1] == '0')
9952 mips_debug = atoi (arg);
9953 /* When the MIPS assembler sees -g or -g2, it does not do
9954 optimizations which limit full symbolic debugging. We take
9955 that to be equivalent to -O0. */
9956 if (mips_debug == 2)
9961 mips_opts.isa = ISA_MIPS1;
9965 mips_opts.isa = ISA_MIPS2;
9969 mips_opts.isa = ISA_MIPS3;
9973 mips_opts.isa = ISA_MIPS4;
9977 mips_opts.isa = ISA_MIPS5;
9981 mips_opts.isa = ISA_MIPS32;
9985 mips_opts.isa = ISA_MIPS64;
9992 int cpu = CPU_UNKNOWN;
9994 /* Identify the processor type. */
9995 if (strcasecmp (arg, "default") != 0)
9997 const struct mips_cpu_info *ci;
9999 ci = mips_cpu_info_from_name (arg);
10000 if (ci == NULL || ci->is_isa)
10005 as_fatal (_("invalid architecture -mtune=%s"), arg);
10008 as_fatal (_("invalid architecture -march=%s"), arg);
10011 as_fatal (_("invalid architecture -mcpu=%s"), arg);
10022 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
10023 as_warn (_("A different -mtune= was already specified, is now "
10024 "-mtune=%s"), arg);
10028 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
10029 as_warn (_("A different -march= was already specified, is now "
10030 "-march=%s"), arg);
10034 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
10035 as_warn (_("A different -mcpu= was already specified, is now "
10043 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
10044 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
10045 as_warn (_("A different -march= or -mtune= was already specified, "
10047 mips_arch = CPU_R4650;
10048 mips_tune = CPU_R4650;
10051 case OPTION_NO_M4650:
10055 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
10056 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
10057 as_warn (_("A different -march= or -mtune= was already specified, "
10059 mips_arch = CPU_R4010;
10060 mips_tune = CPU_R4010;
10063 case OPTION_NO_M4010:
10067 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
10068 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
10069 as_warn (_("A different -march= or -mtune= was already specified, "
10071 mips_arch = CPU_VR4100;
10072 mips_tune = CPU_VR4100;
10075 case OPTION_NO_M4100:
10079 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
10080 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
10081 as_warn (_("A different -march= or -mtune= was already specified, "
10083 mips_arch = CPU_R3900;
10084 mips_tune = CPU_R3900;
10087 case OPTION_NO_M3900:
10091 mips_opts.ase_mdmx = 1;
10094 case OPTION_NO_MDMX:
10095 mips_opts.ase_mdmx = 0;
10098 case OPTION_MIPS16:
10099 mips_opts.mips16 = 1;
10100 mips_no_prev_insn (false);
10103 case OPTION_NO_MIPS16:
10104 mips_opts.mips16 = 0;
10105 mips_no_prev_insn (false);
10108 case OPTION_MIPS3D:
10109 mips_opts.ase_mips3d = 1;
10112 case OPTION_NO_MIPS3D:
10113 mips_opts.ase_mips3d = 0;
10116 case OPTION_MEMBEDDED_PIC:
10117 mips_pic = EMBEDDED_PIC;
10118 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10120 as_bad (_("-G may not be used with embedded PIC code"));
10123 g_switch_value = 0x7fffffff;
10127 /* When generating ELF code, we permit -KPIC and -call_shared to
10128 select SVR4_PIC, and -non_shared to select no PIC. This is
10129 intended to be compatible with Irix 5. */
10130 case OPTION_CALL_SHARED:
10131 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10133 as_bad (_("-call_shared is supported only for ELF format"));
10136 mips_pic = SVR4_PIC;
10137 if (g_switch_seen && g_switch_value != 0)
10139 as_bad (_("-G may not be used with SVR4 PIC code"));
10142 g_switch_value = 0;
10145 case OPTION_NON_SHARED:
10146 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10148 as_bad (_("-non_shared is supported only for ELF format"));
10154 /* The -xgot option tells the assembler to use 32 offsets when
10155 accessing the got in SVR4_PIC mode. It is for Irix
10160 #endif /* OBJ_ELF */
10163 if (! USE_GLOBAL_POINTER_OPT)
10165 as_bad (_("-G is not supported for this configuration"));
10168 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10170 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10174 g_switch_value = atoi (arg);
10179 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10182 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10184 as_bad (_("-32 is supported for ELF format only"));
10187 mips_opts.abi = O32_ABI;
10191 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10193 as_bad (_("-n32 is supported for ELF format only"));
10196 mips_opts.abi = N32_ABI;
10200 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10202 as_bad (_("-64 is supported for ELF format only"));
10205 mips_opts.abi = N64_ABI;
10206 if (! support_64bit_objects())
10207 as_fatal (_("No compiled in support for 64 bit object file format"));
10209 #endif /* OBJ_ELF */
10212 file_mips_gp32 = 1;
10213 if (mips_opts.abi != O32_ABI)
10214 mips_opts.abi = NO_ABI;
10218 file_mips_gp32 = 0;
10219 if (mips_opts.abi == O32_ABI)
10220 mips_opts.abi = NO_ABI;
10224 file_mips_fp32 = 1;
10225 if (mips_opts.abi != O32_ABI)
10226 mips_opts.abi = NO_ABI;
10231 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10233 as_bad (_("-mabi is supported for ELF format only"));
10236 if (strcmp (arg, "32") == 0)
10237 mips_opts.abi = O32_ABI;
10238 else if (strcmp (arg, "o64") == 0)
10239 mips_opts.abi = O64_ABI;
10240 else if (strcmp (arg, "n32") == 0)
10241 mips_opts.abi = N32_ABI;
10242 else if (strcmp (arg, "64") == 0)
10244 mips_opts.abi = N64_ABI;
10245 if (! support_64bit_objects())
10246 as_fatal (_("No compiled in support for 64 bit object file "
10249 else if (strcmp (arg, "eabi") == 0)
10250 mips_opts.abi = EABI_ABI;
10253 as_fatal (_("invalid abi -mabi=%s"), arg);
10257 #endif /* OBJ_ELF */
10259 case OPTION_M7000_HILO_FIX:
10260 mips_7000_hilo_fix = true;
10263 case OPTION_MNO_7000_HILO_FIX:
10264 mips_7000_hilo_fix = false;
10275 show (stream, string, col_p, first_p)
10283 fprintf (stream, "%24s", "");
10288 fprintf (stream, ", ");
10292 if (*col_p + strlen (string) > 72)
10294 fprintf (stream, "\n%24s", "");
10298 fprintf (stream, "%s", string);
10299 *col_p += strlen (string);
10305 md_show_usage (stream)
10310 fprintf (stream, _("\
10312 -membedded-pic generate embedded position independent code\n\
10313 -EB generate big endian output\n\
10314 -EL generate little endian output\n\
10315 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10316 -G NUM allow referencing objects up to NUM bytes\n\
10317 implicitly with the gp register [default 8]\n"));
10318 fprintf (stream, _("\
10319 -mips1 generate MIPS ISA I instructions\n\
10320 -mips2 generate MIPS ISA II instructions\n\
10321 -mips3 generate MIPS ISA III instructions\n\
10322 -mips4 generate MIPS ISA IV instructions\n\
10323 -mips5 generate MIPS ISA V instructions\n\
10324 -mips32 generate MIPS32 ISA instructions\n\
10325 -mips64 generate MIPS64 ISA instructions\n\
10326 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10330 show (stream, "2000", &column, &first);
10331 show (stream, "3000", &column, &first);
10332 show (stream, "3900", &column, &first);
10333 show (stream, "4000", &column, &first);
10334 show (stream, "4010", &column, &first);
10335 show (stream, "4100", &column, &first);
10336 show (stream, "4111", &column, &first);
10337 show (stream, "4300", &column, &first);
10338 show (stream, "4400", &column, &first);
10339 show (stream, "4600", &column, &first);
10340 show (stream, "4650", &column, &first);
10341 show (stream, "5000", &column, &first);
10342 show (stream, "5200", &column, &first);
10343 show (stream, "5230", &column, &first);
10344 show (stream, "5231", &column, &first);
10345 show (stream, "5261", &column, &first);
10346 show (stream, "5721", &column, &first);
10347 show (stream, "6000", &column, &first);
10348 show (stream, "8000", &column, &first);
10349 show (stream, "10000", &column, &first);
10350 show (stream, "12000", &column, &first);
10351 show (stream, "sb1", &column, &first);
10352 fputc ('\n', stream);
10354 fprintf (stream, _("\
10355 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10356 -no-mCPU don't generate code specific to CPU.\n\
10357 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10361 show (stream, "3900", &column, &first);
10362 show (stream, "4010", &column, &first);
10363 show (stream, "4100", &column, &first);
10364 show (stream, "4650", &column, &first);
10365 fputc ('\n', stream);
10367 fprintf (stream, _("\
10368 -mips16 generate mips16 instructions\n\
10369 -no-mips16 do not generate mips16 instructions\n"));
10370 fprintf (stream, _("\
10371 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10372 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10373 -O0 remove unneeded NOPs, do not swap branches\n\
10374 -O remove unneeded NOPs and swap branches\n\
10375 -n warn about NOPs generated from macros\n\
10376 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10377 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10378 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10380 fprintf (stream, _("\
10381 -KPIC, -call_shared generate SVR4 position independent code\n\
10382 -non_shared do not generate position independent code\n\
10383 -xgot assume a 32 bit GOT\n\
10384 -mabi=ABI create ABI conformant object file for:\n"));
10388 show (stream, "32", &column, &first);
10389 show (stream, "o64", &column, &first);
10390 show (stream, "n32", &column, &first);
10391 show (stream, "64", &column, &first);
10392 show (stream, "eabi", &column, &first);
10394 fputc ('\n', stream);
10396 fprintf (stream, _("\
10397 -32 create o32 ABI object file (default)\n\
10398 -n32 create n32 ABI object file\n\
10399 -64 create 64 ABI object file\n"));
10404 mips_after_parse_args ()
10408 int mips_isa_from_cpu;
10409 int target_cpu_had_mips16 = 0;
10410 const struct mips_cpu_info *ci;
10412 /* GP relative stuff not working for PE */
10413 if (strncmp (TARGET_OS, "pe", 2) == 0
10414 && g_switch_value != 0)
10417 as_bad (_("-G not supported in this configuration."));
10418 g_switch_value = 0;
10422 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
10424 a = xmalloc (sizeof TARGET_CPU);
10425 strcpy (a, TARGET_CPU);
10426 a[(sizeof TARGET_CPU) - 3] = '\0';
10430 if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
10432 target_cpu_had_mips16 = 1;
10433 cpu += sizeof "mips16" - 1;
10436 if (mips_opts.mips16 < 0)
10437 mips_opts.mips16 = target_cpu_had_mips16;
10439 /* Backward compatibility for historic -mcpu= option. Check for
10440 incompatible options, warn if -mcpu is used. */
10441 if (mips_cpu != CPU_UNKNOWN
10442 && mips_arch != CPU_UNKNOWN
10443 && mips_cpu != mips_arch)
10445 as_fatal (_("The -mcpu option can't be used together with -march. "
10446 "Use -mtune instead of -mcpu."));
10449 if (mips_cpu != CPU_UNKNOWN
10450 && mips_tune != CPU_UNKNOWN
10451 && mips_cpu != mips_tune)
10453 as_fatal (_("The -mcpu option can't be used together with -mtune. "
10454 "Use -march instead of -mcpu."));
10458 /* For backward compatibility, let -mipsN set various defaults. */
10459 /* This code should go away, to be replaced with something rather more
10460 draconian. Until GCC 3.1 has been released for some reasonable
10461 amount of time, however, we need to support this. */
10462 if (mips_opts.isa != ISA_UNKNOWN)
10464 /* Translate -mipsN to the appropriate settings of file_mips_gp32
10465 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
10466 if (file_mips_gp32 < 0)
10468 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10469 file_mips_gp32 = 0;
10471 file_mips_gp32 = 1;
10473 if (file_mips_fp32 < 0)
10475 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
10476 file_mips_fp32 = 0;
10478 file_mips_fp32 = 1;
10481 ci = mips_cpu_info_from_isa (mips_opts.isa);
10482 assert (ci != NULL);
10483 /* -mipsN has higher priority than -mcpu but lower than -march. */
10484 if (mips_arch == CPU_UNKNOWN)
10485 mips_arch = ci->cpu;
10487 /* Default mips_abi. */
10488 if (mips_opts.abi == NO_ABI)
10490 if (mips_opts.isa == ISA_MIPS1 || mips_opts.isa == ISA_MIPS2)
10491 mips_opts.abi = O32_ABI;
10492 else if (mips_opts.isa == ISA_MIPS3 || mips_opts.isa == ISA_MIPS4)
10493 mips_opts.abi = O64_ABI;
10497 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10499 ci = mips_cpu_info_from_cpu (mips_cpu);
10500 assert (ci != NULL);
10501 mips_arch = ci->cpu;
10502 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10503 "-mtune instead."));
10506 /* Set tune from -mcpu, not from -mipsN. */
10507 if (mips_tune == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10509 ci = mips_cpu_info_from_cpu (mips_cpu);
10510 assert (ci != NULL);
10511 mips_tune = ci->cpu;
10514 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10515 specified on the command line, or some other value if one was.
10516 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10517 the command line, or will be set otherwise if one was. */
10519 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10520 /* Handled above. */;
10522 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
10524 ci = mips_cpu_info_from_cpu (mips_cpu);
10525 assert (ci != NULL);
10526 mips_arch = ci->cpu;
10527 as_warn (_("The -mcpu option is deprecated. Please use -march and "
10528 "-mtune instead."));
10531 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
10532 specified on the command line, or some other value if one was.
10533 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
10534 the command line, or will be set otherwise if one was. */
10536 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10538 /* We have to check if the isa is the default isa of arch. Otherwise
10539 we'll get invalid object file headers. */
10540 ci = mips_cpu_info_from_cpu (mips_arch);
10541 assert (ci != NULL);
10542 if (mips_opts.isa != ci->isa)
10544 /* This really should be an error instead of a warning, but old
10545 compilers only have -mcpu which sets both arch and tune. For
10546 now, we discard arch and preserve tune. */
10547 as_warn (_("The -march option is incompatible to -mipsN and "
10548 "therefore ignored."));
10549 if (mips_tune == CPU_UNKNOWN)
10550 mips_tune = mips_arch;
10551 ci = mips_cpu_info_from_isa (mips_opts.isa);
10552 assert (ci != NULL);
10553 mips_arch = ci->cpu;
10557 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
10559 /* We have ARCH, we need ISA. */
10560 ci = mips_cpu_info_from_cpu (mips_arch);
10561 assert (ci != NULL);
10562 mips_opts.isa = ci->isa;
10564 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
10566 /* We have ISA, we need default ARCH. */
10567 ci = mips_cpu_info_from_isa (mips_opts.isa);
10568 assert (ci != NULL);
10569 mips_arch = ci->cpu;
10573 /* We need to set both ISA and ARCH from target cpu. */
10574 ci = mips_cpu_info_from_name (cpu);
10576 ci = mips_cpu_info_from_cpu (CPU_R3000);
10577 assert (ci != NULL);
10578 mips_opts.isa = ci->isa;
10579 mips_arch = ci->cpu;
10582 if (mips_tune == CPU_UNKNOWN)
10583 mips_tune = mips_arch;
10585 ci = mips_cpu_info_from_cpu (mips_arch);
10586 assert (ci != NULL);
10587 mips_isa_from_cpu = ci->isa;
10589 /* End of TARGET_CPU processing, get rid of malloced memory
10598 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10599 as_bad (_("trap exception not supported at ISA 1"));
10601 /* Set the EABI kind based on the ISA before the user gets
10602 to change the ISA with directives. This isn't really
10603 the best, but then neither is basing the abi on the isa. */
10604 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10605 && mips_opts.abi == EABI_ABI)
10608 /* If they asked for mips1 or mips2 and a cpu that is
10609 mips3 or greater, then mark the object file 32BITMODE. */
10610 if (mips_isa_from_cpu != ISA_UNKNOWN
10611 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
10612 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
10613 mips_32bitmode = 1;
10615 /* If the selected architecture includes support for ASEs, enable
10616 generation of code for them. */
10617 if (mips_opts.ase_mips3d == -1 && CPU_HAS_MIPS3D (mips_arch))
10618 mips_opts.ase_mips3d = 1;
10619 if (mips_opts.ase_mdmx == -1 && CPU_HAS_MDMX (mips_arch))
10620 mips_opts.ase_mdmx = 1;
10622 if (file_mips_gp32 < 0)
10623 file_mips_gp32 = 0;
10624 if (file_mips_fp32 < 0)
10625 file_mips_fp32 = 0;
10627 file_mips_isa = mips_opts.isa;
10628 file_mips_abi = mips_opts.abi;
10629 file_ase_mips3d = mips_opts.ase_mips3d;
10630 file_ase_mdmx = mips_opts.ase_mdmx;
10631 mips_opts.gp32 = file_mips_gp32;
10632 mips_opts.fp32 = file_mips_fp32;
10639 mips_init_after_args ()
10641 /* initialize opcodes */
10642 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10643 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10647 md_pcrel_from (fixP)
10650 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
10651 && fixP->fx_addsy != (symbolS *) NULL
10652 && ! S_IS_DEFINED (fixP->fx_addsy))
10654 /* This makes a branch to an undefined symbol be a branch to the
10655 current location. */
10656 if (mips_pic == EMBEDDED_PIC)
10662 /* Return the address of the delay slot. */
10663 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10666 /* This is called before the symbol table is processed. In order to
10667 work with gcc when using mips-tfile, we must keep all local labels.
10668 However, in other cases, we want to discard them. If we were
10669 called with -g, but we didn't see any debugging information, it may
10670 mean that gcc is smuggling debugging information through to
10671 mips-tfile, in which case we must generate all local labels. */
10674 mips_frob_file_before_adjust ()
10676 #ifndef NO_ECOFF_DEBUGGING
10677 if (ECOFF_DEBUGGING
10679 && ! ecoff_debugging_seen)
10680 flag_keep_locals = 1;
10684 /* Sort any unmatched HI16_S relocs so that they immediately precede
10685 the corresponding LO reloc. This is called before md_apply_fix3 and
10686 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10687 explicit use of the %hi modifier. */
10692 struct mips_hi_fixup *l;
10694 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10696 segment_info_type *seginfo;
10699 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
10701 /* Check quickly whether the next fixup happens to be a matching
10703 if (l->fixp->fx_next != NULL
10704 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
10705 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
10706 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
10709 /* Look through the fixups for this segment for a matching %lo.
10710 When we find one, move the %hi just in front of it. We do
10711 this in two passes. In the first pass, we try to find a
10712 unique %lo. In the second pass, we permit multiple %hi
10713 relocs for a single %lo (this is a GNU extension). */
10714 seginfo = seg_info (l->seg);
10715 for (pass = 0; pass < 2; pass++)
10720 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10722 /* Check whether this is a %lo fixup which matches l->fixp. */
10723 if (f->fx_r_type == BFD_RELOC_LO16
10724 && f->fx_addsy == l->fixp->fx_addsy
10725 && f->fx_offset == l->fixp->fx_offset
10728 || prev->fx_r_type != BFD_RELOC_HI16_S
10729 || prev->fx_addsy != f->fx_addsy
10730 || prev->fx_offset != f->fx_offset))
10734 /* Move l->fixp before f. */
10735 for (pf = &seginfo->fix_root;
10737 pf = &(*pf)->fx_next)
10738 assert (*pf != NULL);
10740 *pf = l->fixp->fx_next;
10742 l->fixp->fx_next = f;
10744 seginfo->fix_root = l->fixp;
10746 prev->fx_next = l->fixp;
10757 #if 0 /* GCC code motion plus incomplete dead code elimination
10758 can leave a %hi without a %lo. */
10760 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10761 _("Unmatched %%hi reloc"));
10767 /* When generating embedded PIC code we need to use a special
10768 relocation to represent the difference of two symbols in the .text
10769 section (switch tables use a difference of this sort). See
10770 include/coff/mips.h for details. This macro checks whether this
10771 fixup requires the special reloc. */
10772 #define SWITCH_TABLE(fixp) \
10773 ((fixp)->fx_r_type == BFD_RELOC_32 \
10774 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10775 && (fixp)->fx_addsy != NULL \
10776 && (fixp)->fx_subsy != NULL \
10777 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10778 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10780 /* When generating embedded PIC code we must keep all PC relative
10781 relocations, in case the linker has to relax a call. We also need
10782 to keep relocations for switch table entries.
10784 We may have combined relocations without symbols in the N32/N64 ABI.
10785 We have to prevent gas from dropping them. */
10788 mips_force_relocation (fixp)
10791 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10792 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10796 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10797 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10798 || fixp->fx_r_type == BFD_RELOC_HI16_S
10799 || fixp->fx_r_type == BFD_RELOC_LO16))
10802 return (mips_pic == EMBEDDED_PIC
10804 || SWITCH_TABLE (fixp)
10805 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
10806 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
10811 mips_need_elf_addend_fixup (fixP)
10814 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16)
10816 if (mips_pic == EMBEDDED_PIC
10817 && S_IS_WEAK (fixP->fx_addsy))
10819 if (mips_pic != EMBEDDED_PIC
10820 && (S_IS_WEAK (fixP->fx_addsy)
10821 || S_IS_EXTERN (fixP->fx_addsy))
10822 && !S_IS_COMMON (fixP->fx_addsy))
10824 if (symbol_used_in_reloc_p (fixP->fx_addsy)
10825 && (((bfd_get_section_flags (stdoutput,
10826 S_GET_SEGMENT (fixP->fx_addsy))
10827 & SEC_LINK_ONCE) != 0)
10828 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
10830 sizeof (".gnu.linkonce") - 1)))
10836 /* Apply a fixup to the object file. */
10839 md_apply_fix3 (fixP, valP, seg)
10842 segT seg ATTRIBUTE_UNUSED;
10848 assert (fixP->fx_size == 4
10849 || fixP->fx_r_type == BFD_RELOC_16
10850 || fixP->fx_r_type == BFD_RELOC_32
10851 || fixP->fx_r_type == BFD_RELOC_MIPS_JMP
10852 || fixP->fx_r_type == BFD_RELOC_HI16_S
10853 || fixP->fx_r_type == BFD_RELOC_LO16
10854 || fixP->fx_r_type == BFD_RELOC_GPREL16
10855 || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL
10856 || fixP->fx_r_type == BFD_RELOC_GPREL32
10857 || fixP->fx_r_type == BFD_RELOC_64
10858 || fixP->fx_r_type == BFD_RELOC_CTOR
10859 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
10860 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST
10861 || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER
10862 || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP
10863 || fixP->fx_r_type == BFD_RELOC_MIPS_REL16
10864 || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT
10865 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
10866 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
10867 || fixP->fx_r_type == BFD_RELOC_MIPS_JALR);
10871 /* If we aren't adjusting this fixup to be against the section
10872 symbol, we need to adjust the value. */
10874 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
10876 if (mips_need_elf_addend_fixup (fixP))
10878 valueT symval = S_GET_VALUE (fixP->fx_addsy);
10881 if (value != 0 && ! fixP->fx_pcrel)
10883 /* In this case, the bfd_install_relocation routine will
10884 incorrectly add the symbol value back in. We just want
10885 the addend to appear in the object file. */
10888 /* Make sure the addend is still non-zero. If it became zero
10889 after the last operation, set it to a spurious value and
10890 subtract the same value from the object file's contents. */
10895 /* The in-place addends for LO16 relocations are signed;
10896 leave the matching HI16 in-place addends as zero. */
10897 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
10899 reloc_howto_type *howto;
10900 bfd_vma contents, mask, field;
10902 howto = bfd_reloc_type_lookup (stdoutput,
10905 contents = bfd_get_bits (fixP->fx_frag->fr_literal
10908 target_big_endian);
10910 /* MASK has bits set where the relocation should go.
10911 FIELD is -value, shifted into the appropriate place
10912 for this relocation. */
10913 mask = 1 << (howto->bitsize - 1);
10914 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
10915 field = (-value >> howto->rightshift) << howto->bitpos;
10917 bfd_put_bits ((field & mask) | (contents & ~mask),
10918 fixP->fx_frag->fr_literal + fixP->fx_where,
10920 target_big_endian);
10926 /* This code was generated using trial and error and so is
10927 fragile and not trustworthy. If you change it, you should
10928 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10929 they still pass. */
10930 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
10932 value += fixP->fx_frag->fr_address + fixP->fx_where;
10934 /* BFD's REL handling, for MIPS, is _very_ weird.
10935 This gives the right results, but it can't possibly
10936 be the way things are supposed to work. */
10937 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
10938 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
10939 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
10940 value += fixP->fx_frag->fr_address + fixP->fx_where;
10945 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */
10947 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
10950 switch (fixP->fx_r_type)
10952 case BFD_RELOC_MIPS_JMP:
10953 case BFD_RELOC_MIPS_SHIFT5:
10954 case BFD_RELOC_MIPS_SHIFT6:
10955 case BFD_RELOC_MIPS_GOT_DISP:
10956 case BFD_RELOC_MIPS_GOT_PAGE:
10957 case BFD_RELOC_MIPS_GOT_OFST:
10958 case BFD_RELOC_MIPS_SUB:
10959 case BFD_RELOC_MIPS_INSERT_A:
10960 case BFD_RELOC_MIPS_INSERT_B:
10961 case BFD_RELOC_MIPS_DELETE:
10962 case BFD_RELOC_MIPS_HIGHEST:
10963 case BFD_RELOC_MIPS_HIGHER:
10964 case BFD_RELOC_MIPS_SCN_DISP:
10965 case BFD_RELOC_MIPS_REL16:
10966 case BFD_RELOC_MIPS_RELGOT:
10967 case BFD_RELOC_MIPS_JALR:
10968 case BFD_RELOC_HI16:
10969 case BFD_RELOC_HI16_S:
10970 case BFD_RELOC_GPREL16:
10971 case BFD_RELOC_MIPS_LITERAL:
10972 case BFD_RELOC_MIPS_CALL16:
10973 case BFD_RELOC_MIPS_GOT16:
10974 case BFD_RELOC_GPREL32:
10975 case BFD_RELOC_MIPS_GOT_HI16:
10976 case BFD_RELOC_MIPS_GOT_LO16:
10977 case BFD_RELOC_MIPS_CALL_HI16:
10978 case BFD_RELOC_MIPS_CALL_LO16:
10979 case BFD_RELOC_MIPS16_GPREL:
10980 if (fixP->fx_pcrel)
10981 as_bad_where (fixP->fx_file, fixP->fx_line,
10982 _("Invalid PC relative reloc"));
10983 /* Nothing needed to do. The value comes from the reloc entry */
10986 case BFD_RELOC_MIPS16_JMP:
10987 /* We currently always generate a reloc against a symbol, which
10988 means that we don't want an addend even if the symbol is
10990 fixP->fx_addnumber = 0;
10993 case BFD_RELOC_PCREL_HI16_S:
10994 /* The addend for this is tricky if it is internal, so we just
10995 do everything here rather than in bfd_install_relocation. */
10996 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11001 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11003 /* For an external symbol adjust by the address to make it
11004 pcrel_offset. We use the address of the RELLO reloc
11005 which follows this one. */
11006 value += (fixP->fx_next->fx_frag->fr_address
11007 + fixP->fx_next->fx_where);
11009 value = ((value + 0x8000) >> 16) & 0xffff;
11010 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11011 if (target_big_endian)
11013 md_number_to_chars ((char *) buf, value, 2);
11016 case BFD_RELOC_PCREL_LO16:
11017 /* The addend for this is tricky if it is internal, so we just
11018 do everything here rather than in bfd_install_relocation. */
11019 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11024 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11025 value += fixP->fx_frag->fr_address + fixP->fx_where;
11026 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11027 if (target_big_endian)
11029 md_number_to_chars ((char *) buf, value, 2);
11033 /* This is handled like BFD_RELOC_32, but we output a sign
11034 extended value if we are only 32 bits. */
11036 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11038 if (8 <= sizeof (valueT))
11039 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11046 w1 = w2 = fixP->fx_where;
11047 if (target_big_endian)
11051 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
11052 if ((value & 0x80000000) != 0)
11056 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
11061 case BFD_RELOC_RVA:
11063 /* If we are deleting this reloc entry, we must fill in the
11064 value now. This can happen if we have a .word which is not
11065 resolved when it appears but is later defined. We also need
11066 to fill in the value if this is an embedded PIC switch table
11069 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11070 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11075 /* If we are deleting this reloc entry, we must fill in the
11077 assert (fixP->fx_size == 2);
11079 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
11083 case BFD_RELOC_LO16:
11084 /* When handling an embedded PIC switch statement, we can wind
11085 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11088 if (value + 0x8000 > 0xffff)
11089 as_bad_where (fixP->fx_file, fixP->fx_line,
11090 _("relocation overflow"));
11091 buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where;
11092 if (target_big_endian)
11094 md_number_to_chars ((char *) buf, value, 2);
11098 case BFD_RELOC_16_PCREL_S2:
11099 if ((value & 0x3) != 0)
11100 as_bad_where (fixP->fx_file, fixP->fx_line,
11101 _("Branch to odd address (%lx)"), (long) value);
11103 /* Fall through. */
11105 case BFD_RELOC_16_PCREL:
11107 * We need to save the bits in the instruction since fixup_segment()
11108 * might be deleting the relocation entry (i.e., a branch within
11109 * the current segment).
11111 if (!fixP->fx_done && value != 0)
11113 /* If 'value' is zero, the remaining reloc code won't actually
11114 do the store, so it must be done here. This is probably
11115 a bug somewhere. */
11117 && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2
11118 || fixP->fx_addsy == NULL /* ??? */
11119 || ! S_IS_DEFINED (fixP->fx_addsy)))
11120 value -= fixP->fx_frag->fr_address + fixP->fx_where;
11122 value = (offsetT) value >> 2;
11124 /* update old instruction data */
11125 buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal);
11126 if (target_big_endian)
11127 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11129 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11131 if (value + 0x8000 <= 0xffff)
11132 insn |= value & 0xffff;
11135 /* The branch offset is too large. If this is an
11136 unconditional branch, and we are not generating PIC code,
11137 we can convert it to an absolute jump instruction. */
11138 if (mips_pic == NO_PIC
11140 && fixP->fx_frag->fr_address >= text_section->vma
11141 && (fixP->fx_frag->fr_address
11142 < text_section->vma + text_section->_raw_size)
11143 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11144 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11145 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11147 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11148 insn = 0x0c000000; /* jal */
11150 insn = 0x08000000; /* j */
11151 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11153 fixP->fx_addsy = section_symbol (text_section);
11154 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
11158 /* FIXME. It would be possible in principle to handle
11159 conditional branches which overflow. They could be
11160 transformed into a branch around a jump. This would
11161 require setting up variant frags for each different
11162 branch type. The native MIPS assembler attempts to
11163 handle these cases, but it appears to do it
11165 as_bad_where (fixP->fx_file, fixP->fx_line,
11166 _("Branch out of range"));
11170 md_number_to_chars ((char *) buf, (valueT) insn, 4);
11173 case BFD_RELOC_VTABLE_INHERIT:
11176 && !S_IS_DEFINED (fixP->fx_addsy)
11177 && !S_IS_WEAK (fixP->fx_addsy))
11178 S_SET_WEAK (fixP->fx_addsy);
11181 case BFD_RELOC_VTABLE_ENTRY:
11195 const struct mips_opcode *p;
11196 int treg, sreg, dreg, shamt;
11201 for (i = 0; i < NUMOPCODES; ++i)
11203 p = &mips_opcodes[i];
11204 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11206 printf ("%08lx %s\t", oc, p->name);
11207 treg = (oc >> 16) & 0x1f;
11208 sreg = (oc >> 21) & 0x1f;
11209 dreg = (oc >> 11) & 0x1f;
11210 shamt = (oc >> 6) & 0x1f;
11212 for (args = p->args;; ++args)
11223 printf ("%c", *args);
11227 assert (treg == sreg);
11228 printf ("$%d,$%d", treg, sreg);
11233 printf ("$%d", dreg);
11238 printf ("$%d", treg);
11242 printf ("0x%x", treg);
11247 printf ("$%d", sreg);
11251 printf ("0x%08lx", oc & 0x1ffffff);
11258 printf ("%d", imm);
11263 printf ("$%d", shamt);
11274 printf (_("%08lx UNDEFINED\n"), oc);
11285 name = input_line_pointer;
11286 c = get_symbol_end ();
11287 p = (symbolS *) symbol_find_or_make (name);
11288 *input_line_pointer = c;
11292 /* Align the current frag to a given power of two. The MIPS assembler
11293 also automatically adjusts any preceding label. */
11296 mips_align (to, fill, label)
11301 mips_emit_delays (false);
11302 frag_align (to, fill, 0);
11303 record_alignment (now_seg, to);
11306 assert (S_GET_SEGMENT (label) == now_seg);
11307 symbol_set_frag (label, frag_now);
11308 S_SET_VALUE (label, (valueT) frag_now_fix ());
11312 /* Align to a given power of two. .align 0 turns off the automatic
11313 alignment used by the data creating pseudo-ops. */
11317 int x ATTRIBUTE_UNUSED;
11320 register long temp_fill;
11321 long max_alignment = 15;
11325 o Note that the assembler pulls down any immediately preceeding label
11326 to the aligned address.
11327 o It's not documented but auto alignment is reinstated by
11328 a .align pseudo instruction.
11329 o Note also that after auto alignment is turned off the mips assembler
11330 issues an error on attempt to assemble an improperly aligned data item.
11335 temp = get_absolute_expression ();
11336 if (temp > max_alignment)
11337 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11340 as_warn (_("Alignment negative: 0 assumed."));
11343 if (*input_line_pointer == ',')
11345 ++input_line_pointer;
11346 temp_fill = get_absolute_expression ();
11353 mips_align (temp, (int) temp_fill,
11354 insn_labels != NULL ? insn_labels->label : NULL);
11361 demand_empty_rest_of_line ();
11365 mips_flush_pending_output ()
11367 mips_emit_delays (false);
11368 mips_clear_insn_labels ();
11377 /* When generating embedded PIC code, we only use the .text, .lit8,
11378 .sdata and .sbss sections. We change the .data and .rdata
11379 pseudo-ops to use .sdata. */
11380 if (mips_pic == EMBEDDED_PIC
11381 && (sec == 'd' || sec == 'r'))
11385 /* The ELF backend needs to know that we are changing sections, so
11386 that .previous works correctly. We could do something like check
11387 for an obj_section_change_hook macro, but that might be confusing
11388 as it would not be appropriate to use it in the section changing
11389 functions in read.c, since obj-elf.c intercepts those. FIXME:
11390 This should be cleaner, somehow. */
11391 obj_elf_section_change_hook ();
11394 mips_emit_delays (false);
11404 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11405 demand_empty_rest_of_line ();
11409 if (USE_GLOBAL_POINTER_OPT)
11411 seg = subseg_new (RDATA_SECTION_NAME,
11412 (subsegT) get_absolute_expression ());
11413 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11415 bfd_set_section_flags (stdoutput, seg,
11421 if (strcmp (TARGET_OS, "elf") != 0)
11422 record_alignment (seg, 4);
11424 demand_empty_rest_of_line ();
11428 as_bad (_("No read only data section in this object file format"));
11429 demand_empty_rest_of_line ();
11435 if (USE_GLOBAL_POINTER_OPT)
11437 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11438 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11440 bfd_set_section_flags (stdoutput, seg,
11441 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11443 if (strcmp (TARGET_OS, "elf") != 0)
11444 record_alignment (seg, 4);
11446 demand_empty_rest_of_line ();
11451 as_bad (_("Global pointers not supported; recompile -G 0"));
11452 demand_empty_rest_of_line ();
11461 mips_enable_auto_align ()
11472 label = insn_labels != NULL ? insn_labels->label : NULL;
11473 mips_emit_delays (false);
11474 if (log_size > 0 && auto_align)
11475 mips_align (log_size, 0, label);
11476 mips_clear_insn_labels ();
11477 cons (1 << log_size);
11481 s_float_cons (type)
11486 label = insn_labels != NULL ? insn_labels->label : NULL;
11488 mips_emit_delays (false);
11493 mips_align (3, 0, label);
11495 mips_align (2, 0, label);
11498 mips_clear_insn_labels ();
11503 /* Handle .globl. We need to override it because on Irix 5 you are
11506 where foo is an undefined symbol, to mean that foo should be
11507 considered to be the address of a function. */
11511 int x ATTRIBUTE_UNUSED;
11518 name = input_line_pointer;
11519 c = get_symbol_end ();
11520 symbolP = symbol_find_or_make (name);
11521 *input_line_pointer = c;
11522 SKIP_WHITESPACE ();
11524 /* On Irix 5, every global symbol that is not explicitly labelled as
11525 being a function is apparently labelled as being an object. */
11528 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11533 secname = input_line_pointer;
11534 c = get_symbol_end ();
11535 sec = bfd_get_section_by_name (stdoutput, secname);
11537 as_bad (_("%s: no such section"), secname);
11538 *input_line_pointer = c;
11540 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11541 flag = BSF_FUNCTION;
11544 symbol_get_bfdsym (symbolP)->flags |= flag;
11546 S_SET_EXTERNAL (symbolP);
11547 demand_empty_rest_of_line ();
11552 int x ATTRIBUTE_UNUSED;
11557 opt = input_line_pointer;
11558 c = get_symbol_end ();
11562 /* FIXME: What does this mean? */
11564 else if (strncmp (opt, "pic", 3) == 0)
11568 i = atoi (opt + 3);
11572 mips_pic = SVR4_PIC;
11574 as_bad (_(".option pic%d not supported"), i);
11576 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11578 if (g_switch_seen && g_switch_value != 0)
11579 as_warn (_("-G may not be used with SVR4 PIC code"));
11580 g_switch_value = 0;
11581 bfd_set_gp_size (stdoutput, 0);
11585 as_warn (_("Unrecognized option \"%s\""), opt);
11587 *input_line_pointer = c;
11588 demand_empty_rest_of_line ();
11591 /* This structure is used to hold a stack of .set values. */
11593 struct mips_option_stack
11595 struct mips_option_stack *next;
11596 struct mips_set_options options;
11599 static struct mips_option_stack *mips_opts_stack;
11601 /* Handle the .set pseudo-op. */
11605 int x ATTRIBUTE_UNUSED;
11607 char *name = input_line_pointer, ch;
11609 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11610 ++input_line_pointer;
11611 ch = *input_line_pointer;
11612 *input_line_pointer = '\0';
11614 if (strcmp (name, "reorder") == 0)
11616 if (mips_opts.noreorder && prev_nop_frag != NULL)
11618 /* If we still have pending nops, we can discard them. The
11619 usual nop handling will insert any that are still
11621 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11622 * (mips_opts.mips16 ? 2 : 4));
11623 prev_nop_frag = NULL;
11625 mips_opts.noreorder = 0;
11627 else if (strcmp (name, "noreorder") == 0)
11629 mips_emit_delays (true);
11630 mips_opts.noreorder = 1;
11631 mips_any_noreorder = 1;
11633 else if (strcmp (name, "at") == 0)
11635 mips_opts.noat = 0;
11637 else if (strcmp (name, "noat") == 0)
11639 mips_opts.noat = 1;
11641 else if (strcmp (name, "macro") == 0)
11643 mips_opts.warn_about_macros = 0;
11645 else if (strcmp (name, "nomacro") == 0)
11647 if (mips_opts.noreorder == 0)
11648 as_bad (_("`noreorder' must be set before `nomacro'"));
11649 mips_opts.warn_about_macros = 1;
11651 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11653 mips_opts.nomove = 0;
11655 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11657 mips_opts.nomove = 1;
11659 else if (strcmp (name, "bopt") == 0)
11661 mips_opts.nobopt = 0;
11663 else if (strcmp (name, "nobopt") == 0)
11665 mips_opts.nobopt = 1;
11667 else if (strcmp (name, "mdmx") == 0)
11668 mips_opts.ase_mdmx = 1;
11669 else if (strcmp (name, "nomdmx") == 0)
11670 mips_opts.ase_mdmx = 0;
11671 else if (strcmp (name, "mips16") == 0
11672 || strcmp (name, "MIPS-16") == 0)
11673 mips_opts.mips16 = 1;
11674 else if (strcmp (name, "nomips16") == 0
11675 || strcmp (name, "noMIPS-16") == 0)
11676 mips_opts.mips16 = 0;
11677 else if (strcmp (name, "mips3d") == 0)
11678 mips_opts.ase_mips3d = 1;
11679 else if (strcmp (name, "nomips3d") == 0)
11680 mips_opts.ase_mips3d = 0;
11681 else if (strncmp (name, "mips", 4) == 0)
11685 /* Permit the user to change the ISA on the fly. Needless to
11686 say, misuse can cause serious problems. */
11687 isa = atoi (name + 4);
11691 mips_opts.gp32 = file_mips_gp32;
11692 mips_opts.fp32 = file_mips_fp32;
11693 mips_opts.abi = file_mips_abi;
11698 mips_opts.gp32 = 1;
11699 mips_opts.fp32 = 1;
11705 /* Loosen ABI register width restriction. */
11706 if (mips_opts.abi == O32_ABI)
11707 mips_opts.abi = NO_ABI;
11708 mips_opts.gp32 = 0;
11709 mips_opts.fp32 = 0;
11712 as_bad (_("unknown ISA level %s"), name + 4);
11718 case 0: mips_opts.isa = file_mips_isa; break;
11719 case 1: mips_opts.isa = ISA_MIPS1; break;
11720 case 2: mips_opts.isa = ISA_MIPS2; break;
11721 case 3: mips_opts.isa = ISA_MIPS3; break;
11722 case 4: mips_opts.isa = ISA_MIPS4; break;
11723 case 5: mips_opts.isa = ISA_MIPS5; break;
11724 case 32: mips_opts.isa = ISA_MIPS32; break;
11725 case 64: mips_opts.isa = ISA_MIPS64; break;
11726 default: as_bad (_("unknown ISA level %s"), name + 4); break;
11729 else if (strcmp (name, "autoextend") == 0)
11730 mips_opts.noautoextend = 0;
11731 else if (strcmp (name, "noautoextend") == 0)
11732 mips_opts.noautoextend = 1;
11733 else if (strcmp (name, "push") == 0)
11735 struct mips_option_stack *s;
11737 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11738 s->next = mips_opts_stack;
11739 s->options = mips_opts;
11740 mips_opts_stack = s;
11742 else if (strcmp (name, "pop") == 0)
11744 struct mips_option_stack *s;
11746 s = mips_opts_stack;
11748 as_bad (_(".set pop with no .set push"));
11751 /* If we're changing the reorder mode we need to handle
11752 delay slots correctly. */
11753 if (s->options.noreorder && ! mips_opts.noreorder)
11754 mips_emit_delays (true);
11755 else if (! s->options.noreorder && mips_opts.noreorder)
11757 if (prev_nop_frag != NULL)
11759 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11760 * (mips_opts.mips16 ? 2 : 4));
11761 prev_nop_frag = NULL;
11765 mips_opts = s->options;
11766 mips_opts_stack = s->next;
11772 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
11774 *input_line_pointer = ch;
11775 demand_empty_rest_of_line ();
11778 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11779 .option pic2. It means to generate SVR4 PIC calls. */
11782 s_abicalls (ignore)
11783 int ignore ATTRIBUTE_UNUSED;
11785 mips_pic = SVR4_PIC;
11786 if (USE_GLOBAL_POINTER_OPT)
11788 if (g_switch_seen && g_switch_value != 0)
11789 as_warn (_("-G may not be used with SVR4 PIC code"));
11790 g_switch_value = 0;
11792 bfd_set_gp_size (stdoutput, 0);
11793 demand_empty_rest_of_line ();
11796 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11797 PIC code. It sets the $gp register for the function based on the
11798 function address, which is in the register named in the argument.
11799 This uses a relocation against _gp_disp, which is handled specially
11800 by the linker. The result is:
11801 lui $gp,%hi(_gp_disp)
11802 addiu $gp,$gp,%lo(_gp_disp)
11803 addu $gp,$gp,.cpload argument
11804 The .cpload argument is normally $25 == $t9. */
11808 int ignore ATTRIBUTE_UNUSED;
11813 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11814 .cpload is ignored. */
11815 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11821 /* .cpload should be in a .set noreorder section. */
11822 if (mips_opts.noreorder == 0)
11823 as_warn (_(".cpload not in noreorder section"));
11825 ex.X_op = O_symbol;
11826 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
11827 ex.X_op_symbol = NULL;
11828 ex.X_add_number = 0;
11830 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11831 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
11833 macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
11834 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j",
11835 mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16);
11837 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
11838 mips_gp_register, mips_gp_register, tc_get_register (0));
11840 demand_empty_rest_of_line ();
11843 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11844 .cpsetup $reg1, offset|$reg2, label
11846 If offset is given, this results in:
11847 sd $gp, offset($sp)
11848 lui $gp, %hi(%neg(%gp_rel(label)))
11849 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11850 daddu $gp, $gp, $reg1
11852 If $reg2 is given, this results in:
11853 daddu $reg2, $gp, $0
11854 lui $gp, %hi(%neg(%gp_rel(label)))
11855 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11856 daddu $gp, $gp, $reg1
11857 $reg1 is normally $25 == $t9. */
11860 int ignore ATTRIBUTE_UNUSED;
11862 expressionS ex_off;
11863 expressionS ex_sym;
11868 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11869 We also need NewABI support. */
11870 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11876 reg1 = tc_get_register (0);
11877 SKIP_WHITESPACE ();
11878 if (*input_line_pointer != ',')
11880 as_bad (_("missing argument separator ',' for .cpsetup"));
11884 ++input_line_pointer;
11885 SKIP_WHITESPACE ();
11886 if (*input_line_pointer == '$')
11888 mips_cpreturn_register = tc_get_register (0);
11889 mips_cpreturn_offset = -1;
11893 mips_cpreturn_offset = get_absolute_expression ();
11894 mips_cpreturn_register = -1;
11896 SKIP_WHITESPACE ();
11897 if (*input_line_pointer != ',')
11899 as_bad (_("missing argument separator ',' for .cpsetup"));
11903 ++input_line_pointer;
11904 SKIP_WHITESPACE ();
11905 sym = input_line_pointer;
11906 while (ISALNUM (*input_line_pointer))
11907 ++input_line_pointer;
11908 *input_line_pointer = 0;
11910 ex_sym.X_op = O_symbol;
11911 ex_sym.X_add_symbol = symbol_find_or_make (sym);
11912 ex_sym.X_op_symbol = NULL;
11913 ex_sym.X_add_number = 0;
11915 if (mips_cpreturn_register == -1)
11917 ex_off.X_op = O_constant;
11918 ex_off.X_add_symbol = NULL;
11919 ex_off.X_op_symbol = NULL;
11920 ex_off.X_add_number = mips_cpreturn_offset;
11922 macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)",
11923 mips_gp_register, (int) BFD_RELOC_LO16, SP);
11926 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
11927 "d,v,t", mips_cpreturn_register, mips_gp_register, 0);
11929 macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
11930 (int) BFD_RELOC_GPREL16);
11931 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11932 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_HI16_S);
11933 macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j",
11934 mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16);
11935 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
11936 fix_new (frag_now, prev_insn_where, 0, NULL, 0, 0, BFD_RELOC_LO16);
11937 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
11938 HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t",
11939 mips_gp_register, mips_gp_register, reg1);
11941 demand_empty_rest_of_line ();
11946 int ignore ATTRIBUTE_UNUSED;
11948 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11949 .cplocal is ignored. */
11950 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
11956 mips_gp_register = tc_get_register (0);
11959 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11960 offset from $sp. The offset is remembered, and after making a PIC
11961 call $gp is restored from that location. */
11964 s_cprestore (ignore)
11965 int ignore ATTRIBUTE_UNUSED;
11970 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11971 .cprestore is ignored. */
11972 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
11978 mips_cprestore_offset = get_absolute_expression ();
11979 mips_cprestore_valid = 1;
11981 ex.X_op = O_constant;
11982 ex.X_add_symbol = NULL;
11983 ex.X_op_symbol = NULL;
11984 ex.X_add_number = mips_cprestore_offset;
11986 macro_build ((char *) NULL, &icnt, &ex, HAVE_32BIT_ADDRESSES ? "sw" : "sd",
11987 "t,o(b)", mips_gp_register, (int) BFD_RELOC_LO16, SP);
11989 demand_empty_rest_of_line ();
11992 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11993 was given in the preceeding .gpsetup, it results in:
11994 ld $gp, offset($sp)
11996 If a register $reg2 was given there, it results in:
11997 daddiu $gp, $gp, $reg2
12000 s_cpreturn (ignore)
12001 int ignore ATTRIBUTE_UNUSED;
12006 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12007 We also need NewABI support. */
12008 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12014 if (mips_cpreturn_register == -1)
12016 ex.X_op = O_constant;
12017 ex.X_add_symbol = NULL;
12018 ex.X_op_symbol = NULL;
12019 ex.X_add_number = mips_cpreturn_offset;
12021 macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)",
12022 mips_gp_register, (int) BFD_RELOC_LO16, SP);
12025 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu",
12026 "d,v,t", mips_gp_register, mips_cpreturn_register, 0);
12028 demand_empty_rest_of_line ();
12031 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12032 code. It sets the offset to use in gp_rel relocations. */
12036 int ignore ATTRIBUTE_UNUSED;
12038 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12039 We also need NewABI support. */
12040 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12046 mips_gprel_offset = get_absolute_expression ();
12048 demand_empty_rest_of_line ();
12051 /* Handle the .gpword pseudo-op. This is used when generating PIC
12052 code. It generates a 32 bit GP relative reloc. */
12056 int ignore ATTRIBUTE_UNUSED;
12062 /* When not generating PIC code, this is treated as .word. */
12063 if (mips_pic != SVR4_PIC)
12069 label = insn_labels != NULL ? insn_labels->label : NULL;
12070 mips_emit_delays (true);
12072 mips_align (2, 0, label);
12073 mips_clear_insn_labels ();
12077 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12079 as_bad (_("Unsupported use of .gpword"));
12080 ignore_rest_of_line ();
12084 md_number_to_chars (p, (valueT) 0, 4);
12085 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
12086 BFD_RELOC_GPREL32);
12088 demand_empty_rest_of_line ();
12091 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12092 tables in SVR4 PIC code. */
12096 int ignore ATTRIBUTE_UNUSED;
12101 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
12103 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12109 /* Add $gp to the register named as an argument. */
12110 reg = tc_get_register (0);
12111 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
12112 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
12113 "d,v,t", reg, reg, mips_gp_register);
12115 demand_empty_rest_of_line ();
12118 /* Handle the .insn pseudo-op. This marks instruction labels in
12119 mips16 mode. This permits the linker to handle them specially,
12120 such as generating jalx instructions when needed. We also make
12121 them odd for the duration of the assembly, in order to generate the
12122 right sort of code. We will make them even in the adjust_symtab
12123 routine, while leaving them marked. This is convenient for the
12124 debugger and the disassembler. The linker knows to make them odd
12129 int ignore ATTRIBUTE_UNUSED;
12131 mips16_mark_labels ();
12133 demand_empty_rest_of_line ();
12136 /* Handle a .stabn directive. We need these in order to mark a label
12137 as being a mips16 text label correctly. Sometimes the compiler
12138 will emit a label, followed by a .stabn, and then switch sections.
12139 If the label and .stabn are in mips16 mode, then the label is
12140 really a mips16 text label. */
12147 mips16_mark_labels ();
12152 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12156 s_mips_weakext (ignore)
12157 int ignore ATTRIBUTE_UNUSED;
12164 name = input_line_pointer;
12165 c = get_symbol_end ();
12166 symbolP = symbol_find_or_make (name);
12167 S_SET_WEAK (symbolP);
12168 *input_line_pointer = c;
12170 SKIP_WHITESPACE ();
12172 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12174 if (S_IS_DEFINED (symbolP))
12176 as_bad ("ignoring attempt to redefine symbol %s",
12177 S_GET_NAME (symbolP));
12178 ignore_rest_of_line ();
12182 if (*input_line_pointer == ',')
12184 ++input_line_pointer;
12185 SKIP_WHITESPACE ();
12189 if (exp.X_op != O_symbol)
12191 as_bad ("bad .weakext directive");
12192 ignore_rest_of_line ();
12195 symbol_set_value_expression (symbolP, &exp);
12198 demand_empty_rest_of_line ();
12201 /* Parse a register string into a number. Called from the ECOFF code
12202 to parse .frame. The argument is non-zero if this is the frame
12203 register, so that we can record it in mips_frame_reg. */
12206 tc_get_register (frame)
12211 SKIP_WHITESPACE ();
12212 if (*input_line_pointer++ != '$')
12214 as_warn (_("expected `$'"));
12217 else if (ISDIGIT (*input_line_pointer))
12219 reg = get_absolute_expression ();
12220 if (reg < 0 || reg >= 32)
12222 as_warn (_("Bad register number"));
12228 if (strncmp (input_line_pointer, "ra", 2) == 0)
12230 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12232 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12234 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12236 else if (strncmp (input_line_pointer, "at", 2) == 0)
12240 as_warn (_("Unrecognized register name"));
12243 input_line_pointer += 2;
12247 mips_frame_reg = reg != 0 ? reg : SP;
12248 mips_frame_reg_valid = 1;
12249 mips_cprestore_valid = 0;
12255 md_section_align (seg, addr)
12259 int align = bfd_get_section_alignment (stdoutput, seg);
12262 /* We don't need to align ELF sections to the full alignment.
12263 However, Irix 5 may prefer that we align them at least to a 16
12264 byte boundary. We don't bother to align the sections if we are
12265 targeted for an embedded system. */
12266 if (strcmp (TARGET_OS, "elf") == 0)
12272 return ((addr + (1 << align) - 1) & (-1 << align));
12275 /* Utility routine, called from above as well. If called while the
12276 input file is still being read, it's only an approximation. (For
12277 example, a symbol may later become defined which appeared to be
12278 undefined earlier.) */
12281 nopic_need_relax (sym, before_relaxing)
12283 int before_relaxing;
12288 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12290 const char *symname;
12293 /* Find out whether this symbol can be referenced off the $gp
12294 register. It can be if it is smaller than the -G size or if
12295 it is in the .sdata or .sbss section. Certain symbols can
12296 not be referenced off the $gp, although it appears as though
12298 symname = S_GET_NAME (sym);
12299 if (symname != (const char *) NULL
12300 && (strcmp (symname, "eprol") == 0
12301 || strcmp (symname, "etext") == 0
12302 || strcmp (symname, "_gp") == 0
12303 || strcmp (symname, "edata") == 0
12304 || strcmp (symname, "_fbss") == 0
12305 || strcmp (symname, "_fdata") == 0
12306 || strcmp (symname, "_ftext") == 0
12307 || strcmp (symname, "end") == 0
12308 || strcmp (symname, "_gp_disp") == 0))
12310 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12312 #ifndef NO_ECOFF_DEBUGGING
12313 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12314 && (symbol_get_obj (sym)->ecoff_extern_size
12315 <= g_switch_value))
12317 /* We must defer this decision until after the whole
12318 file has been read, since there might be a .extern
12319 after the first use of this symbol. */
12320 || (before_relaxing
12321 #ifndef NO_ECOFF_DEBUGGING
12322 && symbol_get_obj (sym)->ecoff_extern_size == 0
12324 && S_GET_VALUE (sym) == 0)
12325 || (S_GET_VALUE (sym) != 0
12326 && S_GET_VALUE (sym) <= g_switch_value)))
12330 const char *segname;
12332 segname = segment_name (S_GET_SEGMENT (sym));
12333 assert (strcmp (segname, ".lit8") != 0
12334 && strcmp (segname, ".lit4") != 0);
12335 change = (strcmp (segname, ".sdata") != 0
12336 && strcmp (segname, ".sbss") != 0
12337 && strncmp (segname, ".sdata.", 7) != 0
12338 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12343 /* We are not optimizing for the $gp register. */
12347 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12348 extended opcode. SEC is the section the frag is in. */
12351 mips16_extended_frag (fragp, sec, stretch)
12357 register const struct mips16_immed_operand *op;
12359 int mintiny, maxtiny;
12363 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12365 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12368 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12369 op = mips16_immed_operands;
12370 while (op->type != type)
12373 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12378 if (type == '<' || type == '>' || type == '[' || type == ']')
12381 maxtiny = 1 << op->nbits;
12386 maxtiny = (1 << op->nbits) - 1;
12391 mintiny = - (1 << (op->nbits - 1));
12392 maxtiny = (1 << (op->nbits - 1)) - 1;
12395 sym_frag = symbol_get_frag (fragp->fr_symbol);
12396 val = S_GET_VALUE (fragp->fr_symbol);
12397 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12403 /* We won't have the section when we are called from
12404 mips_relax_frag. However, we will always have been called
12405 from md_estimate_size_before_relax first. If this is a
12406 branch to a different section, we mark it as such. If SEC is
12407 NULL, and the frag is not marked, then it must be a branch to
12408 the same section. */
12411 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12416 /* Must have been called from md_estimate_size_before_relax. */
12419 fragp->fr_subtype =
12420 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12422 /* FIXME: We should support this, and let the linker
12423 catch branches and loads that are out of range. */
12424 as_bad_where (fragp->fr_file, fragp->fr_line,
12425 _("unsupported PC relative reference to different section"));
12429 if (fragp != sym_frag && sym_frag->fr_address == 0)
12430 /* Assume non-extended on the first relaxation pass.
12431 The address we have calculated will be bogus if this is
12432 a forward branch to another frag, as the forward frag
12433 will have fr_address == 0. */
12437 /* In this case, we know for sure that the symbol fragment is in
12438 the same section. If the relax_marker of the symbol fragment
12439 differs from the relax_marker of this fragment, we have not
12440 yet adjusted the symbol fragment fr_address. We want to add
12441 in STRETCH in order to get a better estimate of the address.
12442 This particularly matters because of the shift bits. */
12444 && sym_frag->relax_marker != fragp->relax_marker)
12448 /* Adjust stretch for any alignment frag. Note that if have
12449 been expanding the earlier code, the symbol may be
12450 defined in what appears to be an earlier frag. FIXME:
12451 This doesn't handle the fr_subtype field, which specifies
12452 a maximum number of bytes to skip when doing an
12454 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12456 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12459 stretch = - ((- stretch)
12460 & ~ ((1 << (int) f->fr_offset) - 1));
12462 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12471 addr = fragp->fr_address + fragp->fr_fix;
12473 /* The base address rules are complicated. The base address of
12474 a branch is the following instruction. The base address of a
12475 PC relative load or add is the instruction itself, but if it
12476 is in a delay slot (in which case it can not be extended) use
12477 the address of the instruction whose delay slot it is in. */
12478 if (type == 'p' || type == 'q')
12482 /* If we are currently assuming that this frag should be
12483 extended, then, the current address is two bytes
12485 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12488 /* Ignore the low bit in the target, since it will be set
12489 for a text label. */
12490 if ((val & 1) != 0)
12493 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12495 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12498 val -= addr & ~ ((1 << op->shift) - 1);
12500 /* Branch offsets have an implicit 0 in the lowest bit. */
12501 if (type == 'p' || type == 'q')
12504 /* If any of the shifted bits are set, we must use an extended
12505 opcode. If the address depends on the size of this
12506 instruction, this can lead to a loop, so we arrange to always
12507 use an extended opcode. We only check this when we are in
12508 the main relaxation loop, when SEC is NULL. */
12509 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12511 fragp->fr_subtype =
12512 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12516 /* If we are about to mark a frag as extended because the value
12517 is precisely maxtiny + 1, then there is a chance of an
12518 infinite loop as in the following code:
12523 In this case when the la is extended, foo is 0x3fc bytes
12524 away, so the la can be shrunk, but then foo is 0x400 away, so
12525 the la must be extended. To avoid this loop, we mark the
12526 frag as extended if it was small, and is about to become
12527 extended with a value of maxtiny + 1. */
12528 if (val == ((maxtiny + 1) << op->shift)
12529 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12532 fragp->fr_subtype =
12533 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12537 else if (symsec != absolute_section && sec != NULL)
12538 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12540 if ((val & ((1 << op->shift) - 1)) != 0
12541 || val < (mintiny << op->shift)
12542 || val > (maxtiny << op->shift))
12548 /* Estimate the size of a frag before relaxing. Unless this is the
12549 mips16, we are not really relaxing here, and the final size is
12550 encoded in the subtype information. For the mips16, we have to
12551 decide whether we are using an extended opcode or not. */
12554 md_estimate_size_before_relax (fragp, segtype)
12559 boolean linkonce = false;
12561 if (RELAX_MIPS16_P (fragp->fr_subtype))
12562 /* We don't want to modify the EXTENDED bit here; it might get us
12563 into infinite loops. We change it only in mips_relax_frag(). */
12564 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12566 if (mips_pic == NO_PIC)
12568 change = nopic_need_relax (fragp->fr_symbol, 0);
12570 else if (mips_pic == SVR4_PIC)
12575 sym = fragp->fr_symbol;
12577 /* Handle the case of a symbol equated to another symbol. */
12578 while (symbol_equated_reloc_p (sym))
12582 /* It's possible to get a loop here in a badly written
12584 n = symbol_get_value_expression (sym)->X_add_symbol;
12590 symsec = S_GET_SEGMENT (sym);
12592 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12593 if (symsec != segtype && ! S_IS_LOCAL (sym))
12595 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12599 /* The GNU toolchain uses an extension for ELF: a section
12600 beginning with the magic string .gnu.linkonce is a linkonce
12602 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12603 sizeof ".gnu.linkonce" - 1) == 0)
12607 /* This must duplicate the test in adjust_reloc_syms. */
12608 change = (symsec != &bfd_und_section
12609 && symsec != &bfd_abs_section
12610 && ! bfd_is_com_section (symsec)
12613 /* A global or weak symbol is treated as external. */
12614 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12615 || (! S_IS_WEAK (sym)
12616 && (! S_IS_EXTERN (sym) || mips_pic == EMBEDDED_PIC)))
12625 /* Record the offset to the first reloc in the fr_opcode field.
12626 This lets md_convert_frag and tc_gen_reloc know that the code
12627 must be expanded. */
12628 fragp->fr_opcode = (fragp->fr_literal
12630 - RELAX_OLD (fragp->fr_subtype)
12631 + RELAX_RELOC1 (fragp->fr_subtype));
12632 /* FIXME: This really needs as_warn_where. */
12633 if (RELAX_WARN (fragp->fr_subtype))
12634 as_warn (_("AT used after \".set noat\" or macro used after "
12635 "\".set nomacro\""));
12637 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
12643 /* This is called to see whether a reloc against a defined symbol
12644 should be converted into a reloc against a section. Don't adjust
12645 MIPS16 jump relocations, so we don't have to worry about the format
12646 of the offset in the .o file. Don't adjust relocations against
12647 mips16 symbols, so that the linker can find them if it needs to set
12651 mips_fix_adjustable (fixp)
12655 /* Prevent all adjustments to global symbols. */
12656 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12657 && mips_pic != EMBEDDED_PIC
12658 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
12661 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
12663 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12664 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12666 if (fixp->fx_addsy == NULL)
12669 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
12670 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
12671 && fixp->fx_subsy == NULL)
12677 /* Translate internal representation of relocation info to BFD target
12681 tc_gen_reloc (section, fixp)
12682 asection *section ATTRIBUTE_UNUSED;
12685 static arelent *retval[4];
12687 bfd_reloc_code_real_type code;
12689 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
12692 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12693 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12694 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12696 if (mips_pic == EMBEDDED_PIC
12697 && SWITCH_TABLE (fixp))
12699 /* For a switch table entry we use a special reloc. The addend
12700 is actually the difference between the reloc address and the
12702 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12703 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
12704 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12705 fixp->fx_r_type = BFD_RELOC_GPREL32;
12707 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
12709 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12710 reloc->addend = fixp->fx_addnumber;
12713 /* We use a special addend for an internal RELLO reloc. */
12714 if (symbol_section_p (fixp->fx_addsy))
12715 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
12717 reloc->addend = fixp->fx_addnumber + reloc->address;
12720 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
12722 assert (fixp->fx_next != NULL
12723 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
12725 /* The reloc is relative to the RELLO; adjust the addend
12727 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12728 reloc->addend = fixp->fx_next->fx_addnumber;
12731 /* We use a special addend for an internal RELHI reloc. */
12732 if (symbol_section_p (fixp->fx_addsy))
12733 reloc->addend = (fixp->fx_next->fx_frag->fr_address
12734 + fixp->fx_next->fx_where
12735 - S_GET_VALUE (fixp->fx_subsy));
12737 reloc->addend = (fixp->fx_addnumber
12738 + fixp->fx_next->fx_frag->fr_address
12739 + fixp->fx_next->fx_where);
12742 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12743 reloc->addend = fixp->fx_addnumber;
12746 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
12747 /* A gruesome hack which is a result of the gruesome gas reloc
12749 reloc->addend = reloc->address;
12751 reloc->addend = -reloc->address;
12754 /* If this is a variant frag, we may need to adjust the existing
12755 reloc and generate a new one. */
12756 if (fixp->fx_frag->fr_opcode != NULL
12757 && (fixp->fx_r_type == BFD_RELOC_GPREL16
12758 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
12759 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
12760 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12761 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
12762 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12763 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)
12768 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
12770 /* If this is not the last reloc in this frag, then we have two
12771 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12772 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12773 the second one handle all of them. */
12774 if (fixp->fx_next != NULL
12775 && fixp->fx_frag == fixp->fx_next->fx_frag)
12777 assert ((fixp->fx_r_type == BFD_RELOC_GPREL16
12778 && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16)
12779 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
12780 && (fixp->fx_next->fx_r_type
12781 == BFD_RELOC_MIPS_GOT_LO16))
12782 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
12783 && (fixp->fx_next->fx_r_type
12784 == BFD_RELOC_MIPS_CALL_LO16)));
12789 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
12790 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12791 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
12793 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
12794 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12795 reloc2->address = (reloc->address
12796 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
12797 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
12798 reloc2->addend = fixp->fx_addnumber;
12799 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
12800 assert (reloc2->howto != NULL);
12802 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
12806 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
12809 reloc3->address += 4;
12812 if (mips_pic == NO_PIC)
12814 assert (fixp->fx_r_type == BFD_RELOC_GPREL16);
12815 fixp->fx_r_type = BFD_RELOC_HI16_S;
12817 else if (mips_pic == SVR4_PIC)
12819 switch (fixp->fx_r_type)
12823 case BFD_RELOC_MIPS_GOT16:
12825 case BFD_RELOC_MIPS_CALL16:
12826 case BFD_RELOC_MIPS_GOT_LO16:
12827 case BFD_RELOC_MIPS_CALL_LO16:
12828 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
12836 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12837 entry to be used in the relocation's section offset. */
12838 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12840 reloc->address = reloc->addend;
12844 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12845 fixup_segment converted a non-PC relative reloc into a PC
12846 relative reloc. In such a case, we need to convert the reloc
12848 code = fixp->fx_r_type;
12849 if (fixp->fx_pcrel)
12854 code = BFD_RELOC_8_PCREL;
12857 code = BFD_RELOC_16_PCREL;
12860 code = BFD_RELOC_32_PCREL;
12863 code = BFD_RELOC_64_PCREL;
12865 case BFD_RELOC_8_PCREL:
12866 case BFD_RELOC_16_PCREL:
12867 case BFD_RELOC_32_PCREL:
12868 case BFD_RELOC_64_PCREL:
12869 case BFD_RELOC_16_PCREL_S2:
12870 case BFD_RELOC_PCREL_HI16_S:
12871 case BFD_RELOC_PCREL_LO16:
12874 as_bad_where (fixp->fx_file, fixp->fx_line,
12875 _("Cannot make %s relocation PC relative"),
12876 bfd_get_reloc_code_name (code));
12881 /* md_apply_fix3 has a double-subtraction hack to get
12882 bfd_install_relocation to behave nicely. GPREL relocations are
12883 handled correctly without this hack, so undo it here. We can't
12884 stop md_apply_fix3 from subtracting twice in the first place since
12885 the fake addend is required for variant frags above. */
12886 if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour
12887 && code == BFD_RELOC_GPREL16
12888 && reloc->addend != 0
12889 && mips_need_elf_addend_fixup (fixp))
12890 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
12893 /* To support a PC relative reloc when generating embedded PIC code
12894 for ECOFF, we use a Cygnus extension. We check for that here to
12895 make sure that we don't let such a reloc escape normally. */
12896 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
12897 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
12898 && code == BFD_RELOC_16_PCREL_S2
12899 && mips_pic != EMBEDDED_PIC)
12900 reloc->howto = NULL;
12902 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12904 if (reloc->howto == NULL)
12906 as_bad_where (fixp->fx_file, fixp->fx_line,
12907 _("Can not represent %s relocation in this object file format"),
12908 bfd_get_reloc_code_name (code));
12915 /* Relax a machine dependent frag. This returns the amount by which
12916 the current size of the frag should change. */
12919 mips_relax_frag (fragp, stretch)
12923 if (! RELAX_MIPS16_P (fragp->fr_subtype))
12926 if (mips16_extended_frag (fragp, NULL, stretch))
12928 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12930 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
12935 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12937 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
12944 /* Convert a machine dependent frag. */
12947 md_convert_frag (abfd, asec, fragp)
12948 bfd *abfd ATTRIBUTE_UNUSED;
12955 if (RELAX_MIPS16_P (fragp->fr_subtype))
12958 register const struct mips16_immed_operand *op;
12959 boolean small, ext;
12962 unsigned long insn;
12963 boolean use_extend;
12964 unsigned short extend;
12966 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12967 op = mips16_immed_operands;
12968 while (op->type != type)
12971 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12982 resolve_symbol_value (fragp->fr_symbol);
12983 val = S_GET_VALUE (fragp->fr_symbol);
12988 addr = fragp->fr_address + fragp->fr_fix;
12990 /* The rules for the base address of a PC relative reloc are
12991 complicated; see mips16_extended_frag. */
12992 if (type == 'p' || type == 'q')
12997 /* Ignore the low bit in the target, since it will be
12998 set for a text label. */
12999 if ((val & 1) != 0)
13002 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13004 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13007 addr &= ~ (addressT) ((1 << op->shift) - 1);
13010 /* Make sure the section winds up with the alignment we have
13013 record_alignment (asec, op->shift);
13017 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13018 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13019 as_warn_where (fragp->fr_file, fragp->fr_line,
13020 _("extended instruction in delay slot"));
13022 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13024 if (target_big_endian)
13025 insn = bfd_getb16 (buf);
13027 insn = bfd_getl16 (buf);
13029 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13030 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13031 small, ext, &insn, &use_extend, &extend);
13035 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13036 fragp->fr_fix += 2;
13040 md_number_to_chars ((char *) buf, insn, 2);
13041 fragp->fr_fix += 2;
13046 if (fragp->fr_opcode == NULL)
13049 old = RELAX_OLD (fragp->fr_subtype);
13050 new = RELAX_NEW (fragp->fr_subtype);
13051 fixptr = fragp->fr_literal + fragp->fr_fix;
13054 memcpy (fixptr - old, fixptr, new);
13056 fragp->fr_fix += new - old;
13062 /* This function is called after the relocs have been generated.
13063 We've been storing mips16 text labels as odd. Here we convert them
13064 back to even for the convenience of the debugger. */
13067 mips_frob_file_after_relocs ()
13070 unsigned int count, i;
13072 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13075 syms = bfd_get_outsymbols (stdoutput);
13076 count = bfd_get_symcount (stdoutput);
13077 for (i = 0; i < count; i++, syms++)
13079 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13080 && ((*syms)->value & 1) != 0)
13082 (*syms)->value &= ~1;
13083 /* If the symbol has an odd size, it was probably computed
13084 incorrectly, so adjust that as well. */
13085 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13086 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13093 /* This function is called whenever a label is defined. It is used
13094 when handling branch delays; if a branch has a label, we assume we
13095 can not move it. */
13098 mips_define_label (sym)
13101 struct insn_label_list *l;
13103 if (free_insn_labels == NULL)
13104 l = (struct insn_label_list *) xmalloc (sizeof *l);
13107 l = free_insn_labels;
13108 free_insn_labels = l->next;
13112 l->next = insn_labels;
13116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13118 /* Some special processing for a MIPS ELF file. */
13121 mips_elf_final_processing ()
13123 /* Write out the register information. */
13124 if (file_mips_abi != N64_ABI)
13128 s.ri_gprmask = mips_gprmask;
13129 s.ri_cprmask[0] = mips_cprmask[0];
13130 s.ri_cprmask[1] = mips_cprmask[1];
13131 s.ri_cprmask[2] = mips_cprmask[2];
13132 s.ri_cprmask[3] = mips_cprmask[3];
13133 /* The gp_value field is set by the MIPS ELF backend. */
13135 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13136 ((Elf32_External_RegInfo *)
13137 mips_regmask_frag));
13141 Elf64_Internal_RegInfo s;
13143 s.ri_gprmask = mips_gprmask;
13145 s.ri_cprmask[0] = mips_cprmask[0];
13146 s.ri_cprmask[1] = mips_cprmask[1];
13147 s.ri_cprmask[2] = mips_cprmask[2];
13148 s.ri_cprmask[3] = mips_cprmask[3];
13149 /* The gp_value field is set by the MIPS ELF backend. */
13151 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13152 ((Elf64_External_RegInfo *)
13153 mips_regmask_frag));
13156 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13157 sort of BFD interface for this. */
13158 if (mips_any_noreorder)
13159 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13160 if (mips_pic != NO_PIC)
13161 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13163 /* Set MIPS ELF flags for ASEs. */
13164 #if 0 /* XXX FIXME */
13165 if (file_ase_mips3d)
13166 elf_elfheader (stdoutput)->e_flags |= ???;
13169 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13171 /* Set the MIPS ELF ABI flags. */
13172 if (file_mips_abi == NO_ABI)
13174 else if (file_mips_abi == O32_ABI)
13175 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13176 else if (file_mips_abi == O64_ABI)
13177 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13178 else if (file_mips_abi == EABI_ABI)
13181 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13183 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13185 else if (file_mips_abi == N32_ABI)
13186 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13188 /* Nothing to do for N64_ABI. */
13190 if (mips_32bitmode)
13191 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13194 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13196 typedef struct proc {
13198 unsigned long reg_mask;
13199 unsigned long reg_offset;
13200 unsigned long fpreg_mask;
13201 unsigned long fpreg_offset;
13202 unsigned long frame_offset;
13203 unsigned long frame_reg;
13204 unsigned long pc_reg;
13207 static procS cur_proc;
13208 static procS *cur_proc_ptr;
13209 static int numprocs;
13211 /* Fill in an rs_align_code fragment. */
13214 mips_handle_align (fragp)
13217 if (fragp->fr_type != rs_align_code)
13220 if (mips_opts.mips16)
13222 static const unsigned char be_nop[] = { 0x65, 0x00 };
13223 static const unsigned char le_nop[] = { 0x00, 0x65 };
13228 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13229 p = fragp->fr_literal + fragp->fr_fix;
13237 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13241 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13252 /* check for premature end, nesting errors, etc */
13254 as_warn (_("missing .end at end of assembly"));
13263 if (*input_line_pointer == '-')
13265 ++input_line_pointer;
13268 if (!ISDIGIT (*input_line_pointer))
13269 as_bad (_("expected simple number"));
13270 if (input_line_pointer[0] == '0')
13272 if (input_line_pointer[1] == 'x')
13274 input_line_pointer += 2;
13275 while (ISXDIGIT (*input_line_pointer))
13278 val |= hex_value (*input_line_pointer++);
13280 return negative ? -val : val;
13284 ++input_line_pointer;
13285 while (ISDIGIT (*input_line_pointer))
13288 val |= *input_line_pointer++ - '0';
13290 return negative ? -val : val;
13293 if (!ISDIGIT (*input_line_pointer))
13295 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13296 *input_line_pointer, *input_line_pointer);
13297 as_warn (_("invalid number"));
13300 while (ISDIGIT (*input_line_pointer))
13303 val += *input_line_pointer++ - '0';
13305 return negative ? -val : val;
13308 /* The .file directive; just like the usual .file directive, but there
13309 is an initial number which is the ECOFF file index. */
13313 int x ATTRIBUTE_UNUSED;
13319 /* The .end directive. */
13323 int x ATTRIBUTE_UNUSED;
13328 /* Following functions need their own .frame and .cprestore directives. */
13329 mips_frame_reg_valid = 0;
13330 mips_cprestore_valid = 0;
13332 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13335 demand_empty_rest_of_line ();
13340 #ifdef BFD_ASSEMBLER
13341 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13346 if (now_seg != data_section && now_seg != bss_section)
13353 as_warn (_(".end not in text section"));
13357 as_warn (_(".end directive without a preceding .ent directive."));
13358 demand_empty_rest_of_line ();
13364 assert (S_GET_NAME (p));
13365 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13366 as_warn (_(".end symbol does not match .ent symbol."));
13369 as_warn (_(".end directive missing or unknown symbol"));
13371 #ifdef MIPS_STABS_ELF
13373 segT saved_seg = now_seg;
13374 subsegT saved_subseg = now_subseg;
13379 dot = frag_now_fix ();
13381 #ifdef md_flush_pending_output
13382 md_flush_pending_output ();
13386 subseg_set (pdr_seg, 0);
13388 /* Write the symbol. */
13389 exp.X_op = O_symbol;
13390 exp.X_add_symbol = p;
13391 exp.X_add_number = 0;
13392 emit_expr (&exp, 4);
13394 fragp = frag_more (7 * 4);
13396 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
13397 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
13398 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
13399 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
13400 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
13401 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
13402 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
13404 subseg_set (saved_seg, saved_subseg);
13406 #endif /* MIPS_STABS_ELF */
13408 cur_proc_ptr = NULL;
13411 /* The .aent and .ent directives. */
13420 symbolP = get_symbol ();
13421 if (*input_line_pointer == ',')
13422 ++input_line_pointer;
13423 SKIP_WHITESPACE ();
13424 if (ISDIGIT (*input_line_pointer)
13425 || *input_line_pointer == '-')
13428 #ifdef BFD_ASSEMBLER
13429 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
13434 if (now_seg != data_section && now_seg != bss_section)
13441 as_warn (_(".ent or .aent not in text section."));
13443 if (!aent && cur_proc_ptr)
13444 as_warn (_("missing .end"));
13448 /* This function needs its own .frame and .cprestore directives. */
13449 mips_frame_reg_valid = 0;
13450 mips_cprestore_valid = 0;
13452 cur_proc_ptr = &cur_proc;
13453 memset (cur_proc_ptr, '\0', sizeof (procS));
13455 cur_proc_ptr->isym = symbolP;
13457 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13462 demand_empty_rest_of_line ();
13465 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13466 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13467 s_mips_frame is used so that we can set the PDR information correctly.
13468 We can't use the ecoff routines because they make reference to the ecoff
13469 symbol table (in the mdebug section). */
13472 s_mips_frame (ignore)
13473 int ignore ATTRIBUTE_UNUSED;
13475 #ifdef MIPS_STABS_ELF
13479 if (cur_proc_ptr == (procS *) NULL)
13481 as_warn (_(".frame outside of .ent"));
13482 demand_empty_rest_of_line ();
13486 cur_proc_ptr->frame_reg = tc_get_register (1);
13488 SKIP_WHITESPACE ();
13489 if (*input_line_pointer++ != ','
13490 || get_absolute_expression_and_terminator (&val) != ',')
13492 as_warn (_("Bad .frame directive"));
13493 --input_line_pointer;
13494 demand_empty_rest_of_line ();
13498 cur_proc_ptr->frame_offset = val;
13499 cur_proc_ptr->pc_reg = tc_get_register (0);
13501 demand_empty_rest_of_line ();
13504 #endif /* MIPS_STABS_ELF */
13507 /* The .fmask and .mask directives. If the mdebug section is present
13508 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13509 embedded targets, s_mips_mask is used so that we can set the PDR
13510 information correctly. We can't use the ecoff routines because they
13511 make reference to the ecoff symbol table (in the mdebug section). */
13514 s_mips_mask (reg_type)
13517 #ifdef MIPS_STABS_ELF
13520 if (cur_proc_ptr == (procS *) NULL)
13522 as_warn (_(".mask/.fmask outside of .ent"));
13523 demand_empty_rest_of_line ();
13527 if (get_absolute_expression_and_terminator (&mask) != ',')
13529 as_warn (_("Bad .mask/.fmask directive"));
13530 --input_line_pointer;
13531 demand_empty_rest_of_line ();
13535 off = get_absolute_expression ();
13537 if (reg_type == 'F')
13539 cur_proc_ptr->fpreg_mask = mask;
13540 cur_proc_ptr->fpreg_offset = off;
13544 cur_proc_ptr->reg_mask = mask;
13545 cur_proc_ptr->reg_offset = off;
13548 demand_empty_rest_of_line ();
13550 s_ignore (reg_type);
13551 #endif /* MIPS_STABS_ELF */
13554 /* The .loc directive. */
13565 assert (now_seg == text_section);
13567 lineno = get_number ();
13568 addroff = frag_now_fix ();
13570 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
13571 S_SET_TYPE (symbolP, N_SLINE);
13572 S_SET_OTHER (symbolP, 0);
13573 S_SET_DESC (symbolP, lineno);
13574 symbolP->sy_segment = now_seg;
13578 /* CPU name/ISA/number mapping table.
13580 Entries are grouped by type. The first matching CPU or ISA entry
13581 gets chosen by CPU or ISA, so it should be the 'canonical' name
13582 for that type. Entries after that within the type are sorted
13585 Case is ignored in comparison, so put the canonical entry in the
13586 appropriate case but everything else in lower case to ease eye pain. */
13587 static const struct mips_cpu_info mips_cpu_info_table[] =
13590 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
13591 { "mips", 1, ISA_MIPS1, CPU_R3000, },
13594 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
13597 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
13600 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
13603 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
13604 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
13607 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
13608 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
13609 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
13610 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
13611 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
13612 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
13614 /* For historical reasons. */
13615 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
13618 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
13619 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
13620 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
13621 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
13624 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
13625 { "2000", 0, ISA_MIPS1, CPU_R2000, },
13626 { "2k", 0, ISA_MIPS1, CPU_R2000, },
13627 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
13630 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
13631 { "3000", 0, ISA_MIPS1, CPU_R3000, },
13632 { "3k", 0, ISA_MIPS1, CPU_R3000, },
13633 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
13636 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
13637 { "3900", 0, ISA_MIPS1, CPU_R3900, },
13638 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
13641 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
13642 { "4000", 0, ISA_MIPS3, CPU_R4000, },
13643 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
13644 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
13647 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
13648 { "4010", 0, ISA_MIPS2, CPU_R4010, },
13651 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
13652 { "4400", 0, ISA_MIPS3, CPU_R4400, },
13655 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
13656 { "4600", 0, ISA_MIPS3, CPU_R4600, },
13657 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
13658 { "orion", 0, ISA_MIPS3, CPU_R4600, },
13661 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
13662 { "4650", 0, ISA_MIPS3, CPU_R4650, },
13665 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
13666 { "6000", 0, ISA_MIPS2, CPU_R6000, },
13667 { "6k", 0, ISA_MIPS2, CPU_R6000, },
13668 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
13671 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
13672 { "8000", 0, ISA_MIPS4, CPU_R8000, },
13673 { "8k", 0, ISA_MIPS4, CPU_R8000, },
13674 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
13677 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
13678 { "10000", 0, ISA_MIPS4, CPU_R10000, },
13679 { "10k", 0, ISA_MIPS4, CPU_R10000, },
13680 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
13683 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
13684 { "12000", 0, ISA_MIPS4, CPU_R12000, },
13685 { "12k", 0, ISA_MIPS4, CPU_R12000, },
13686 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
13689 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
13690 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
13691 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
13692 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
13695 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
13696 { "4111", 0, ISA_MIPS3, CPU_R4111, },
13697 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
13698 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
13701 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
13702 { "4300", 0, ISA_MIPS3, CPU_R4300, },
13703 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
13704 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
13707 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
13708 { "5000", 0, ISA_MIPS4, CPU_R5000, },
13709 { "5k", 0, ISA_MIPS4, CPU_R5000, },
13710 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
13711 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
13712 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
13713 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
13714 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
13715 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
13716 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
13717 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
13718 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
13719 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
13720 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
13721 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
13722 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
13723 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
13725 /* Broadcom SB-1 CPU */
13726 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
13727 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
13728 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
13729 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
13732 { NULL, 0, 0, 0, },
13735 static const struct mips_cpu_info *
13736 mips_cpu_info_from_name (name)
13741 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13742 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
13743 return (&mips_cpu_info_table[i]);
13748 static const struct mips_cpu_info *
13749 mips_cpu_info_from_isa (isa)
13754 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13755 if (mips_cpu_info_table[i].is_isa
13756 && isa == mips_cpu_info_table[i].isa)
13757 return (&mips_cpu_info_table[i]);
13762 static const struct mips_cpu_info *
13763 mips_cpu_info_from_cpu (cpu)
13768 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
13769 if (!mips_cpu_info_table[i].is_isa
13770 && cpu == mips_cpu_info_table[i].cpu)
13771 return (&mips_cpu_info_table[i]);