1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
175 /* True if this instruction is cleared from history by unconditional
177 unsigned int cleared_p : 1;
180 /* The ABI to use. */
191 /* MIPS ABI we are using for this output file. */
192 static enum mips_abi_level mips_abi = NO_ABI;
194 /* Whether or not we have code that can call pic code. */
195 int mips_abicalls = FALSE;
197 /* Whether or not we have code which can be put into a shared
199 static bfd_boolean mips_in_shared = TRUE;
201 /* This is the set of options which may be modified by the .set
202 pseudo-op. We use a struct so that .set push and .set pop are more
205 struct mips_set_options
207 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
208 if it has not been initialized. Changed by `.set mipsN', and the
209 -mipsN command line option, and the default CPU. */
211 /* Enabled Application Specific Extensions (ASEs). These are set to -1
212 if they have not been initialized. Changed by `.set <asename>', by
213 command line options, and based on the default architecture. */
221 /* Whether we are assembling for the mips16 processor. 0 if we are
222 not, 1 if we are, and -1 if the value has not been initialized.
223 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
224 -nomips16 command line options, and the default CPU. */
226 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
227 1 if we are, and -1 if the value has not been initialized. Changed
228 by `.set micromips' and `.set nomicromips', and the -mmicromips
229 and -mno-micromips command line options, and the default CPU. */
231 /* Non-zero if we should not reorder instructions. Changed by `.set
232 reorder' and `.set noreorder'. */
234 /* Non-zero if we should not permit the register designated "assembler
235 temporary" to be used in instructions. The value is the register
236 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
237 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
239 /* Non-zero if we should warn when a macro instruction expands into
240 more than one machine instruction. Changed by `.set nomacro' and
242 int warn_about_macros;
243 /* Non-zero if we should not move instructions. Changed by `.set
244 move', `.set volatile', `.set nomove', and `.set novolatile'. */
246 /* Non-zero if we should not optimize branches by moving the target
247 of the branch into the delay slot. Actually, we don't perform
248 this optimization anyhow. Changed by `.set bopt' and `.set
251 /* Non-zero if we should not autoextend mips16 instructions.
252 Changed by `.set autoextend' and `.set noautoextend'. */
254 /* Restrict general purpose registers and floating point registers
255 to 32 bit. This is initially determined when -mgp32 or -mfp32
256 is passed but can changed if the assembler code uses .set mipsN. */
259 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
260 command line option, and the default CPU. */
262 /* True if ".set sym32" is in effect. */
264 /* True if floating-point operations are not allowed. Changed by .set
265 softfloat or .set hardfloat, by command line options -msoft-float or
266 -mhard-float. The default is false. */
267 bfd_boolean soft_float;
269 /* True if only single-precision floating-point operations are allowed.
270 Changed by .set singlefloat or .set doublefloat, command-line options
271 -msingle-float or -mdouble-float. The default is false. */
272 bfd_boolean single_float;
275 /* This is the struct we use to hold the current set of options. Note
276 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
277 -1 to indicate that they have not been initialized. */
279 /* True if -mgp32 was passed. */
280 static int file_mips_gp32 = -1;
282 /* True if -mfp32 was passed. */
283 static int file_mips_fp32 = -1;
285 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
286 static int file_mips_soft_float = 0;
288 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
289 static int file_mips_single_float = 0;
291 static struct mips_set_options mips_opts =
293 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
294 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
295 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
296 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
297 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
298 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
301 /* These variables are filled in with the masks of registers used.
302 The object format code reads them and puts them in the appropriate
304 unsigned long mips_gprmask;
305 unsigned long mips_cprmask[4];
307 /* MIPS ISA we are using for this output file. */
308 static int file_mips_isa = ISA_UNKNOWN;
310 /* True if any MIPS16 code was produced. */
311 static int file_ase_mips16;
313 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
314 || mips_opts.isa == ISA_MIPS32R2 \
315 || mips_opts.isa == ISA_MIPS64 \
316 || mips_opts.isa == ISA_MIPS64R2)
318 /* True if any microMIPS code was produced. */
319 static int file_ase_micromips;
321 /* True if we want to create R_MIPS_JALR for jalr $25. */
323 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
325 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
326 because there's no place for any addend, the only acceptable
327 expression is a bare symbol. */
328 #define MIPS_JALR_HINT_P(EXPR) \
329 (!HAVE_IN_PLACE_ADDENDS \
330 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
333 /* True if -mips3d was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mips3d;
337 /* True if -mdmx was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mdmx;
341 /* True if -msmartmips was passed or implied by arguments passed on the
342 command line (e.g., by -march). */
343 static int file_ase_smartmips;
345 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
346 || mips_opts.isa == ISA_MIPS32R2)
348 /* True if -mdsp was passed or implied by arguments passed on the
349 command line (e.g., by -march). */
350 static int file_ase_dsp;
352 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
353 || mips_opts.isa == ISA_MIPS64R2 \
354 || mips_opts.micromips)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2 \
364 || mips_opts.micromips)
366 /* True if -mmt was passed or implied by arguments passed on the
367 command line (e.g., by -march). */
368 static int file_ase_mt;
370 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
371 || mips_opts.isa == ISA_MIPS64R2)
373 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
374 || mips_opts.isa == ISA_MIPS64R2 \
375 || mips_opts.micromips)
377 /* The argument of the -march= flag. The architecture we are assembling. */
378 static int file_mips_arch = CPU_UNKNOWN;
379 static const char *mips_arch_string;
381 /* The argument of the -mtune= flag. The architecture for which we
383 static int mips_tune = CPU_UNKNOWN;
384 static const char *mips_tune_string;
386 /* True when generating 32-bit code for a 64-bit processor. */
387 static int mips_32bitmode = 0;
389 /* True if the given ABI requires 32-bit registers. */
390 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
392 /* Likewise 64-bit registers. */
393 #define ABI_NEEDS_64BIT_REGS(ABI) \
395 || (ABI) == N64_ABI \
398 /* Return true if ISA supports 64 bit wide gp registers. */
399 #define ISA_HAS_64BIT_REGS(ISA) \
400 ((ISA) == ISA_MIPS3 \
401 || (ISA) == ISA_MIPS4 \
402 || (ISA) == ISA_MIPS5 \
403 || (ISA) == ISA_MIPS64 \
404 || (ISA) == ISA_MIPS64R2)
406 /* Return true if ISA supports 64 bit wide float registers. */
407 #define ISA_HAS_64BIT_FPRS(ISA) \
408 ((ISA) == ISA_MIPS3 \
409 || (ISA) == ISA_MIPS4 \
410 || (ISA) == ISA_MIPS5 \
411 || (ISA) == ISA_MIPS32R2 \
412 || (ISA) == ISA_MIPS64 \
413 || (ISA) == ISA_MIPS64R2)
415 /* Return true if ISA supports 64-bit right rotate (dror et al.)
417 #define ISA_HAS_DROR(ISA) \
418 ((ISA) == ISA_MIPS64R2 \
419 || (mips_opts.micromips \
420 && ISA_HAS_64BIT_REGS (ISA)) \
423 /* Return true if ISA supports 32-bit right rotate (ror et al.)
425 #define ISA_HAS_ROR(ISA) \
426 ((ISA) == ISA_MIPS32R2 \
427 || (ISA) == ISA_MIPS64R2 \
428 || mips_opts.ase_smartmips \
429 || mips_opts.micromips \
432 /* Return true if ISA supports single-precision floats in odd registers. */
433 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
434 ((ISA) == ISA_MIPS32 \
435 || (ISA) == ISA_MIPS32R2 \
436 || (ISA) == ISA_MIPS64 \
437 || (ISA) == ISA_MIPS64R2)
439 /* Return true if ISA supports move to/from high part of a 64-bit
440 floating-point register. */
441 #define ISA_HAS_MXHC1(ISA) \
442 ((ISA) == ISA_MIPS32R2 \
443 || (ISA) == ISA_MIPS64R2)
445 #define HAVE_32BIT_GPRS \
446 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
448 #define HAVE_32BIT_FPRS \
449 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
451 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
452 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
454 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
456 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
458 /* True if relocations are stored in-place. */
459 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
461 /* The ABI-derived address size. */
462 #define HAVE_64BIT_ADDRESSES \
463 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
464 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
466 /* The size of symbolic constants (i.e., expressions of the form
467 "SYMBOL" or "SYMBOL + OFFSET"). */
468 #define HAVE_32BIT_SYMBOLS \
469 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
470 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
472 /* Addresses are loaded in different ways, depending on the address size
473 in use. The n32 ABI Documentation also mandates the use of additions
474 with overflow checking, but existing implementations don't follow it. */
475 #define ADDRESS_ADD_INSN \
476 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
478 #define ADDRESS_ADDI_INSN \
479 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
481 #define ADDRESS_LOAD_INSN \
482 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
484 #define ADDRESS_STORE_INSN \
485 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
487 /* Return true if the given CPU supports the MIPS16 ASE. */
488 #define CPU_HAS_MIPS16(cpu) \
489 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
490 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
492 /* Return true if the given CPU supports the microMIPS ASE. */
493 #define CPU_HAS_MICROMIPS(cpu) 0
495 /* True if CPU has a dror instruction. */
496 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
498 /* True if CPU has a ror instruction. */
499 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
501 /* True if CPU is in the Octeon family */
502 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
504 /* True if CPU has seq/sne and seqi/snei instructions. */
505 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
507 /* True if mflo and mfhi can be immediately followed by instructions
508 which write to the HI and LO registers.
510 According to MIPS specifications, MIPS ISAs I, II, and III need
511 (at least) two instructions between the reads of HI/LO and
512 instructions which write them, and later ISAs do not. Contradicting
513 the MIPS specifications, some MIPS IV processor user manuals (e.g.
514 the UM for the NEC Vr5000) document needing the instructions between
515 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
516 MIPS64 and later ISAs to have the interlocks, plus any specific
517 earlier-ISA CPUs for which CPU documentation declares that the
518 instructions are really interlocked. */
519 #define hilo_interlocks \
520 (mips_opts.isa == ISA_MIPS32 \
521 || mips_opts.isa == ISA_MIPS32R2 \
522 || mips_opts.isa == ISA_MIPS64 \
523 || mips_opts.isa == ISA_MIPS64R2 \
524 || mips_opts.arch == CPU_R4010 \
525 || mips_opts.arch == CPU_R5900 \
526 || mips_opts.arch == CPU_R10000 \
527 || mips_opts.arch == CPU_R12000 \
528 || mips_opts.arch == CPU_R14000 \
529 || mips_opts.arch == CPU_R16000 \
530 || mips_opts.arch == CPU_RM7000 \
531 || mips_opts.arch == CPU_VR5500 \
532 || mips_opts.micromips \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from the GPRs after they are loaded from memory, and thus does not
537 require nops to be inserted. This applies to instructions marked
538 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
539 level I and microMIPS mode instructions are always interlocked. */
540 #define gpr_interlocks \
541 (mips_opts.isa != ISA_MIPS1 \
542 || mips_opts.arch == CPU_R3900 \
543 || mips_opts.arch == CPU_R5900 \
544 || mips_opts.micromips \
547 /* Whether the processor uses hardware interlocks to avoid delays
548 required by coprocessor instructions, and thus does not require
549 nops to be inserted. This applies to instructions marked
550 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
551 between instructions marked INSN_WRITE_COND_CODE and ones marked
552 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
553 levels I, II, and III and microMIPS mode instructions are always
555 /* Itbl support may require additional care here. */
556 #define cop_interlocks \
557 ((mips_opts.isa != ISA_MIPS1 \
558 && mips_opts.isa != ISA_MIPS2 \
559 && mips_opts.isa != ISA_MIPS3) \
560 || mips_opts.arch == CPU_R4300 \
561 || mips_opts.micromips \
564 /* Whether the processor uses hardware interlocks to protect reads
565 from coprocessor registers after they are loaded from memory, and
566 thus does not require nops to be inserted. This applies to
567 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
568 requires at MIPS ISA level I and microMIPS mode instructions are
569 always interlocked. */
570 #define cop_mem_interlocks \
571 (mips_opts.isa != ISA_MIPS1 \
572 || mips_opts.micromips \
575 /* Is this a mfhi or mflo instruction? */
576 #define MF_HILO_INSN(PINFO) \
577 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
579 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
580 has been selected. This implies, in particular, that addresses of text
581 labels have their LSB set. */
582 #define HAVE_CODE_COMPRESSION \
583 ((mips_opts.mips16 | mips_opts.micromips) != 0)
585 /* MIPS PIC level. */
587 enum mips_pic_level mips_pic;
589 /* 1 if we should generate 32 bit offsets from the $gp register in
590 SVR4_PIC mode. Currently has no meaning in other modes. */
591 static int mips_big_got = 0;
593 /* 1 if trap instructions should used for overflow rather than break
595 static int mips_trap = 0;
597 /* 1 if double width floating point constants should not be constructed
598 by assembling two single width halves into two single width floating
599 point registers which just happen to alias the double width destination
600 register. On some architectures this aliasing can be disabled by a bit
601 in the status register, and the setting of this bit cannot be determined
602 automatically at assemble time. */
603 static int mips_disable_float_construction;
605 /* Non-zero if any .set noreorder directives were used. */
607 static int mips_any_noreorder;
609 /* Non-zero if nops should be inserted when the register referenced in
610 an mfhi/mflo instruction is read in the next two instructions. */
611 static int mips_7000_hilo_fix;
613 /* The size of objects in the small data section. */
614 static unsigned int g_switch_value = 8;
615 /* Whether the -G option was used. */
616 static int g_switch_seen = 0;
621 /* If we can determine in advance that GP optimization won't be
622 possible, we can skip the relaxation stuff that tries to produce
623 GP-relative references. This makes delay slot optimization work
626 This function can only provide a guess, but it seems to work for
627 gcc output. It needs to guess right for gcc, otherwise gcc
628 will put what it thinks is a GP-relative instruction in a branch
631 I don't know if a fix is needed for the SVR4_PIC mode. I've only
632 fixed it for the non-PIC mode. KR 95/04/07 */
633 static int nopic_need_relax (symbolS *, int);
635 /* handle of the OPCODE hash table */
636 static struct hash_control *op_hash = NULL;
638 /* The opcode hash table we use for the mips16. */
639 static struct hash_control *mips16_op_hash = NULL;
641 /* The opcode hash table we use for the microMIPS ASE. */
642 static struct hash_control *micromips_op_hash = NULL;
644 /* This array holds the chars that always start a comment. If the
645 pre-processor is disabled, these aren't very useful */
646 const char comment_chars[] = "#";
648 /* This array holds the chars that only start a comment at the beginning of
649 a line. If the line seems to have the form '# 123 filename'
650 .line and .file directives will appear in the pre-processed output */
651 /* Note that input_file.c hand checks for '#' at the beginning of the
652 first line of the input file. This is because the compiler outputs
653 #NO_APP at the beginning of its output. */
654 /* Also note that C style comments are always supported. */
655 const char line_comment_chars[] = "#";
657 /* This array holds machine specific line separator characters. */
658 const char line_separator_chars[] = ";";
660 /* Chars that can be used to separate mant from exp in floating point nums */
661 const char EXP_CHARS[] = "eE";
663 /* Chars that mean this number is a floating point constant */
666 const char FLT_CHARS[] = "rRsSfFdDxXpP";
668 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
669 changed in read.c . Ideally it shouldn't have to know about it at all,
670 but nothing is ideal around here.
673 static char *insn_error;
675 static int auto_align = 1;
677 /* When outputting SVR4 PIC code, the assembler needs to know the
678 offset in the stack frame from which to restore the $gp register.
679 This is set by the .cprestore pseudo-op, and saved in this
681 static offsetT mips_cprestore_offset = -1;
683 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
684 more optimizations, it can use a register value instead of a memory-saved
685 offset and even an other register than $gp as global pointer. */
686 static offsetT mips_cpreturn_offset = -1;
687 static int mips_cpreturn_register = -1;
688 static int mips_gp_register = GP;
689 static int mips_gprel_offset = 0;
691 /* Whether mips_cprestore_offset has been set in the current function
692 (or whether it has already been warned about, if not). */
693 static int mips_cprestore_valid = 0;
695 /* This is the register which holds the stack frame, as set by the
696 .frame pseudo-op. This is needed to implement .cprestore. */
697 static int mips_frame_reg = SP;
699 /* Whether mips_frame_reg has been set in the current function
700 (or whether it has already been warned about, if not). */
701 static int mips_frame_reg_valid = 0;
703 /* To output NOP instructions correctly, we need to keep information
704 about the previous two instructions. */
706 /* Whether we are optimizing. The default value of 2 means to remove
707 unneeded NOPs and swap branch instructions when possible. A value
708 of 1 means to not swap branches. A value of 0 means to always
710 static int mips_optimize = 2;
712 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
713 equivalent to seeing no -g option at all. */
714 static int mips_debug = 0;
716 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
717 #define MAX_VR4130_NOPS 4
719 /* The maximum number of NOPs needed to fill delay slots. */
720 #define MAX_DELAY_NOPS 2
722 /* The maximum number of NOPs needed for any purpose. */
725 /* A list of previous instructions, with index 0 being the most recent.
726 We need to look back MAX_NOPS instructions when filling delay slots
727 or working around processor errata. We need to look back one
728 instruction further if we're thinking about using history[0] to
729 fill a branch delay slot. */
730 static struct mips_cl_insn history[1 + MAX_NOPS];
732 /* Nop instructions used by emit_nop. */
733 static struct mips_cl_insn nop_insn;
734 static struct mips_cl_insn mips16_nop_insn;
735 static struct mips_cl_insn micromips_nop16_insn;
736 static struct mips_cl_insn micromips_nop32_insn;
738 /* The appropriate nop for the current mode. */
739 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
740 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
742 /* The size of NOP_INSN in bytes. */
743 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
745 /* If this is set, it points to a frag holding nop instructions which
746 were inserted before the start of a noreorder section. If those
747 nops turn out to be unnecessary, the size of the frag can be
749 static fragS *prev_nop_frag;
751 /* The number of nop instructions we created in prev_nop_frag. */
752 static int prev_nop_frag_holds;
754 /* The number of nop instructions that we know we need in
756 static int prev_nop_frag_required;
758 /* The number of instructions we've seen since prev_nop_frag. */
759 static int prev_nop_frag_since;
761 /* For ECOFF and ELF, relocations against symbols are done in two
762 parts, with a HI relocation and a LO relocation. Each relocation
763 has only 16 bits of space to store an addend. This means that in
764 order for the linker to handle carries correctly, it must be able
765 to locate both the HI and the LO relocation. This means that the
766 relocations must appear in order in the relocation table.
768 In order to implement this, we keep track of each unmatched HI
769 relocation. We then sort them so that they immediately precede the
770 corresponding LO relocation. */
775 struct mips_hi_fixup *next;
778 /* The section this fixup is in. */
782 /* The list of unmatched HI relocs. */
784 static struct mips_hi_fixup *mips_hi_fixup_list;
786 /* The frag containing the last explicit relocation operator.
787 Null if explicit relocations have not been used. */
789 static fragS *prev_reloc_op_frag;
791 /* Map normal MIPS register numbers to mips16 register numbers. */
793 #define X ILLEGAL_REG
794 static const int mips32_to_16_reg_map[] =
796 X, X, 2, 3, 4, 5, 6, 7,
797 X, X, X, X, X, X, X, X,
798 0, 1, X, X, X, X, X, X,
799 X, X, X, X, X, X, X, X
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map normal MIPS register numbers to microMIPS register numbers. */
812 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
813 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
814 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
815 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
816 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
817 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
818 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
820 #define X ILLEGAL_REG
821 /* reg type h: 4, 5, 6. */
822 static const int mips32_to_micromips_reg_h_map[] =
824 X, X, X, X, 4, 5, 6, X,
825 X, X, X, X, X, X, X, X,
826 X, X, X, X, X, X, X, X,
827 X, X, X, X, X, X, X, X
830 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
831 static const int mips32_to_micromips_reg_m_map[] =
833 0, X, 2, 3, X, X, X, X,
834 X, X, X, X, X, X, X, X,
835 4, 1, 5, 6, 7, X, X, X,
836 X, X, X, X, X, X, X, X
839 /* reg type q: 0, 2-7. 17. */
840 static const int mips32_to_micromips_reg_q_map[] =
842 0, X, 2, 3, 4, 5, 6, 7,
843 X, X, X, X, X, X, X, X,
844 X, 1, X, X, X, X, X, X,
845 X, X, X, X, X, X, X, X
848 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
851 /* Map microMIPS register numbers to normal MIPS register numbers. */
853 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
854 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
855 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
856 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
857 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
858 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
860 /* The microMIPS registers with type h. */
861 static const unsigned int micromips_to_32_reg_h_map[] =
863 5, 5, 6, 4, 4, 4, 4, 4
866 /* The microMIPS registers with type i. */
867 static const unsigned int micromips_to_32_reg_i_map[] =
869 6, 7, 7, 21, 22, 5, 6, 7
872 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
874 /* The microMIPS registers with type m. */
875 static const unsigned int micromips_to_32_reg_m_map[] =
877 0, 17, 2, 3, 16, 18, 19, 20
880 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
882 /* The microMIPS registers with type q. */
883 static const unsigned int micromips_to_32_reg_q_map[] =
885 0, 17, 2, 3, 4, 5, 6, 7
888 /* microMIPS imm type B. */
889 static const int micromips_imm_b_map[] =
891 1, 4, 8, 12, 16, 20, 24, -1
894 /* microMIPS imm type C. */
895 static const int micromips_imm_c_map[] =
897 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
900 /* Classifies the kind of instructions we're interested in when
901 implementing -mfix-vr4120. */
902 enum fix_vr4120_class
910 NUM_FIX_VR4120_CLASSES
913 /* ...likewise -mfix-loongson2f-jump. */
914 static bfd_boolean mips_fix_loongson2f_jump;
916 /* ...likewise -mfix-loongson2f-nop. */
917 static bfd_boolean mips_fix_loongson2f_nop;
919 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
920 static bfd_boolean mips_fix_loongson2f;
922 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
923 there must be at least one other instruction between an instruction
924 of type X and an instruction of type Y. */
925 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
927 /* True if -mfix-vr4120 is in force. */
928 static int mips_fix_vr4120;
930 /* ...likewise -mfix-vr4130. */
931 static int mips_fix_vr4130;
933 /* ...likewise -mfix-24k. */
934 static int mips_fix_24k;
936 /* ...likewise -mfix-cn63xxp1 */
937 static bfd_boolean mips_fix_cn63xxp1;
939 /* We don't relax branches by default, since this causes us to expand
940 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
941 fail to compute the offset before expanding the macro to the most
942 efficient expansion. */
944 static int mips_relax_branch;
946 /* The expansion of many macros depends on the type of symbol that
947 they refer to. For example, when generating position-dependent code,
948 a macro that refers to a symbol may have two different expansions,
949 one which uses GP-relative addresses and one which uses absolute
950 addresses. When generating SVR4-style PIC, a macro may have
951 different expansions for local and global symbols.
953 We handle these situations by generating both sequences and putting
954 them in variant frags. In position-dependent code, the first sequence
955 will be the GP-relative one and the second sequence will be the
956 absolute one. In SVR4 PIC, the first sequence will be for global
957 symbols and the second will be for local symbols.
959 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
960 SECOND are the lengths of the two sequences in bytes. These fields
961 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
962 the subtype has the following flags:
965 Set if it has been decided that we should use the second
966 sequence instead of the first.
969 Set in the first variant frag if the macro's second implementation
970 is longer than its first. This refers to the macro as a whole,
971 not an individual relaxation.
974 Set in the first variant frag if the macro appeared in a .set nomacro
975 block and if one alternative requires a warning but the other does not.
978 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
981 RELAX_DELAY_SLOT_16BIT
982 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
985 RELAX_DELAY_SLOT_SIZE_FIRST
986 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
987 the macro is of the wrong size for the branch delay slot.
989 RELAX_DELAY_SLOT_SIZE_SECOND
990 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
991 the macro is of the wrong size for the branch delay slot.
993 The frag's "opcode" points to the first fixup for relaxable code.
995 Relaxable macros are generated using a sequence such as:
997 relax_start (SYMBOL);
998 ... generate first expansion ...
1000 ... generate second expansion ...
1003 The code and fixups for the unwanted alternative are discarded
1004 by md_convert_frag. */
1005 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1007 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1008 #define RELAX_SECOND(X) ((X) & 0xff)
1009 #define RELAX_USE_SECOND 0x10000
1010 #define RELAX_SECOND_LONGER 0x20000
1011 #define RELAX_NOMACRO 0x40000
1012 #define RELAX_DELAY_SLOT 0x80000
1013 #define RELAX_DELAY_SLOT_16BIT 0x100000
1014 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1015 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1017 /* Branch without likely bit. If label is out of range, we turn:
1019 beq reg1, reg2, label
1029 with the following opcode replacements:
1036 bltzal <-> bgezal (with jal label instead of j label)
1038 Even though keeping the delay slot instruction in the delay slot of
1039 the branch would be more efficient, it would be very tricky to do
1040 correctly, because we'd have to introduce a variable frag *after*
1041 the delay slot instruction, and expand that instead. Let's do it
1042 the easy way for now, even if the branch-not-taken case now costs
1043 one additional instruction. Out-of-range branches are not supposed
1044 to be common, anyway.
1046 Branch likely. If label is out of range, we turn:
1048 beql reg1, reg2, label
1049 delay slot (annulled if branch not taken)
1058 delay slot (executed only if branch taken)
1061 It would be possible to generate a shorter sequence by losing the
1062 likely bit, generating something like:
1067 delay slot (executed only if branch taken)
1079 bltzall -> bgezal (with jal label instead of j label)
1080 bgezall -> bltzal (ditto)
1083 but it's not clear that it would actually improve performance. */
1084 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1085 ((relax_substateT) \
1088 | ((toofar) ? 0x20 : 0) \
1089 | ((link) ? 0x40 : 0) \
1090 | ((likely) ? 0x80 : 0) \
1091 | ((uncond) ? 0x100 : 0)))
1092 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1093 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1094 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1095 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1096 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1097 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1099 /* For mips16 code, we use an entirely different form of relaxation.
1100 mips16 supports two versions of most instructions which take
1101 immediate values: a small one which takes some small value, and a
1102 larger one which takes a 16 bit value. Since branches also follow
1103 this pattern, relaxing these values is required.
1105 We can assemble both mips16 and normal MIPS code in a single
1106 object. Therefore, we need to support this type of relaxation at
1107 the same time that we support the relaxation described above. We
1108 use the high bit of the subtype field to distinguish these cases.
1110 The information we store for this type of relaxation is the
1111 argument code found in the opcode file for this relocation, whether
1112 the user explicitly requested a small or extended form, and whether
1113 the relocation is in a jump or jal delay slot. That tells us the
1114 size of the value, and how it should be stored. We also store
1115 whether the fragment is considered to be extended or not. We also
1116 store whether this is known to be a branch to a different section,
1117 whether we have tried to relax this frag yet, and whether we have
1118 ever extended a PC relative fragment because of a shift count. */
1119 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1122 | ((small) ? 0x100 : 0) \
1123 | ((ext) ? 0x200 : 0) \
1124 | ((dslot) ? 0x400 : 0) \
1125 | ((jal_dslot) ? 0x800 : 0))
1126 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1127 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1128 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1129 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1130 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1131 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1132 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1133 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1134 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1135 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1136 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1137 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1139 /* For microMIPS code, we use relaxation similar to one we use for
1140 MIPS16 code. Some instructions that take immediate values support
1141 two encodings: a small one which takes some small value, and a
1142 larger one which takes a 16 bit value. As some branches also follow
1143 this pattern, relaxing these values is required.
1145 We can assemble both microMIPS and normal MIPS code in a single
1146 object. Therefore, we need to support this type of relaxation at
1147 the same time that we support the relaxation described above. We
1148 use one of the high bits of the subtype field to distinguish these
1151 The information we store for this type of relaxation is the argument
1152 code found in the opcode file for this relocation, the register
1153 selected as the assembler temporary, whether the branch is
1154 unconditional, whether it is compact, whether it stores the link
1155 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1156 branches to a sequence of instructions is enabled, and whether the
1157 displacement of a branch is too large to fit as an immediate argument
1158 of a 16-bit and a 32-bit branch, respectively. */
1159 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1160 relax32, toofar16, toofar32) \
1163 | (((at) & 0x1f) << 8) \
1164 | ((uncond) ? 0x2000 : 0) \
1165 | ((compact) ? 0x4000 : 0) \
1166 | ((link) ? 0x8000 : 0) \
1167 | ((relax32) ? 0x10000 : 0) \
1168 | ((toofar16) ? 0x20000 : 0) \
1169 | ((toofar32) ? 0x40000 : 0))
1170 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1171 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1172 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1173 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1174 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1175 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1176 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1178 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1179 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1180 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1181 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1182 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1183 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1185 /* Sign-extend 16-bit value X. */
1186 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1188 /* Is the given value a sign-extended 32-bit value? */
1189 #define IS_SEXT_32BIT_NUM(x) \
1190 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1191 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1193 /* Is the given value a sign-extended 16-bit value? */
1194 #define IS_SEXT_16BIT_NUM(x) \
1195 (((x) &~ (offsetT) 0x7fff) == 0 \
1196 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1198 /* Is the given value a sign-extended 12-bit value? */
1199 #define IS_SEXT_12BIT_NUM(x) \
1200 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1202 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1203 #define IS_ZEXT_32BIT_NUM(x) \
1204 (((x) &~ (offsetT) 0xffffffff) == 0 \
1205 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1207 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1208 VALUE << SHIFT. VALUE is evaluated exactly once. */
1209 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1210 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1211 | (((VALUE) & (MASK)) << (SHIFT)))
1213 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1215 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1216 (((STRUCT) >> (SHIFT)) & (MASK))
1218 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1219 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1221 include/opcode/mips.h specifies operand fields using the macros
1222 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1223 with "MIPS16OP" instead of "OP". */
1224 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1227 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1228 OP_MASK_##FIELD, OP_SH_##FIELD); \
1230 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1231 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1233 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1237 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1238 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1240 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1241 : EXTRACT_BITS ((INSN).insn_opcode, \
1242 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1243 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1244 EXTRACT_BITS ((INSN).insn_opcode, \
1245 MIPS16OP_MASK_##FIELD, \
1246 MIPS16OP_SH_##FIELD)
1248 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1249 #define MIPS16_EXTEND (0xf000U << 16)
1251 /* Whether or not we are emitting a branch-likely macro. */
1252 static bfd_boolean emit_branch_likely_macro = FALSE;
1254 /* Global variables used when generating relaxable macros. See the
1255 comment above RELAX_ENCODE for more details about how relaxation
1258 /* 0 if we're not emitting a relaxable macro.
1259 1 if we're emitting the first of the two relaxation alternatives.
1260 2 if we're emitting the second alternative. */
1263 /* The first relaxable fixup in the current frag. (In other words,
1264 the first fixup that refers to relaxable code.) */
1267 /* sizes[0] says how many bytes of the first alternative are stored in
1268 the current frag. Likewise sizes[1] for the second alternative. */
1269 unsigned int sizes[2];
1271 /* The symbol on which the choice of sequence depends. */
1275 /* Global variables used to decide whether a macro needs a warning. */
1277 /* True if the macro is in a branch delay slot. */
1278 bfd_boolean delay_slot_p;
1280 /* Set to the length in bytes required if the macro is in a delay slot
1281 that requires a specific length of instruction, otherwise zero. */
1282 unsigned int delay_slot_length;
1284 /* For relaxable macros, sizes[0] is the length of the first alternative
1285 in bytes and sizes[1] is the length of the second alternative.
1286 For non-relaxable macros, both elements give the length of the
1288 unsigned int sizes[2];
1290 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1291 instruction of the first alternative in bytes and first_insn_sizes[1]
1292 is the length of the first instruction of the second alternative.
1293 For non-relaxable macros, both elements give the length of the first
1294 instruction in bytes.
1296 Set to zero if we haven't yet seen the first instruction. */
1297 unsigned int first_insn_sizes[2];
1299 /* For relaxable macros, insns[0] is the number of instructions for the
1300 first alternative and insns[1] is the number of instructions for the
1303 For non-relaxable macros, both elements give the number of
1304 instructions for the macro. */
1305 unsigned int insns[2];
1307 /* The first variant frag for this macro. */
1309 } mips_macro_warning;
1311 /* Prototypes for static functions. */
1313 #define internalError() \
1314 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1316 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1318 static void append_insn
1319 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1320 bfd_boolean expansionp);
1321 static void mips_no_prev_insn (void);
1322 static void macro_build (expressionS *, const char *, const char *, ...);
1323 static void mips16_macro_build
1324 (expressionS *, const char *, const char *, va_list *);
1325 static void load_register (int, expressionS *, int);
1326 static void macro_start (void);
1327 static void macro_end (void);
1328 static void macro (struct mips_cl_insn * ip);
1329 static void mips16_macro (struct mips_cl_insn * ip);
1330 static void mips_ip (char *str, struct mips_cl_insn * ip);
1331 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_immed
1333 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1334 unsigned int, unsigned long *);
1335 static size_t my_getSmallExpression
1336 (expressionS *, bfd_reloc_code_real_type *, char *);
1337 static void my_getExpression (expressionS *, char *);
1338 static void s_align (int);
1339 static void s_change_sec (int);
1340 static void s_change_section (int);
1341 static void s_cons (int);
1342 static void s_float_cons (int);
1343 static void s_mips_globl (int);
1344 static void s_option (int);
1345 static void s_mipsset (int);
1346 static void s_abicalls (int);
1347 static void s_cpload (int);
1348 static void s_cpsetup (int);
1349 static void s_cplocal (int);
1350 static void s_cprestore (int);
1351 static void s_cpreturn (int);
1352 static void s_dtprelword (int);
1353 static void s_dtpreldword (int);
1354 static void s_tprelword (int);
1355 static void s_tpreldword (int);
1356 static void s_gpvalue (int);
1357 static void s_gpword (int);
1358 static void s_gpdword (int);
1359 static void s_cpadd (int);
1360 static void s_insn (int);
1361 static void md_obj_begin (void);
1362 static void md_obj_end (void);
1363 static void s_mips_ent (int);
1364 static void s_mips_end (int);
1365 static void s_mips_frame (int);
1366 static void s_mips_mask (int reg_type);
1367 static void s_mips_stab (int);
1368 static void s_mips_weakext (int);
1369 static void s_mips_file (int);
1370 static void s_mips_loc (int);
1371 static bfd_boolean pic_need_relax (symbolS *, asection *);
1372 static int relaxed_branch_length (fragS *, asection *, int);
1373 static int validate_mips_insn (const struct mips_opcode *);
1374 static int validate_micromips_insn (const struct mips_opcode *);
1375 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1376 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1378 /* Table and functions used to map between CPU/ISA names, and
1379 ISA levels, and CPU numbers. */
1381 struct mips_cpu_info
1383 const char *name; /* CPU or ISA name. */
1384 int flags; /* ASEs available, or ISA flag. */
1385 int isa; /* ISA level. */
1386 int cpu; /* CPU number (default CPU if ISA). */
1389 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1390 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1391 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1392 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1393 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1394 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1395 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1396 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1398 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1399 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1400 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1404 The following pseudo-ops from the Kane and Heinrich MIPS book
1405 should be defined here, but are currently unsupported: .alias,
1406 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 specific to the type of debugging information being generated, and
1410 should be defined by the object format: .aent, .begin, .bend,
1411 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1414 The following pseudo-ops from the Kane and Heinrich MIPS book are
1415 not MIPS CPU specific, but are also not specific to the object file
1416 format. This file is probably the best place to define them, but
1417 they are not currently supported: .asm0, .endr, .lab, .struct. */
1419 static const pseudo_typeS mips_pseudo_table[] =
1421 /* MIPS specific pseudo-ops. */
1422 {"option", s_option, 0},
1423 {"set", s_mipsset, 0},
1424 {"rdata", s_change_sec, 'r'},
1425 {"sdata", s_change_sec, 's'},
1426 {"livereg", s_ignore, 0},
1427 {"abicalls", s_abicalls, 0},
1428 {"cpload", s_cpload, 0},
1429 {"cpsetup", s_cpsetup, 0},
1430 {"cplocal", s_cplocal, 0},
1431 {"cprestore", s_cprestore, 0},
1432 {"cpreturn", s_cpreturn, 0},
1433 {"dtprelword", s_dtprelword, 0},
1434 {"dtpreldword", s_dtpreldword, 0},
1435 {"tprelword", s_tprelword, 0},
1436 {"tpreldword", s_tpreldword, 0},
1437 {"gpvalue", s_gpvalue, 0},
1438 {"gpword", s_gpword, 0},
1439 {"gpdword", s_gpdword, 0},
1440 {"cpadd", s_cpadd, 0},
1441 {"insn", s_insn, 0},
1443 /* Relatively generic pseudo-ops that happen to be used on MIPS
1445 {"asciiz", stringer, 8 + 1},
1446 {"bss", s_change_sec, 'b'},
1448 {"half", s_cons, 1},
1449 {"dword", s_cons, 3},
1450 {"weakext", s_mips_weakext, 0},
1451 {"origin", s_org, 0},
1452 {"repeat", s_rept, 0},
1454 /* For MIPS this is non-standard, but we define it for consistency. */
1455 {"sbss", s_change_sec, 'B'},
1457 /* These pseudo-ops are defined in read.c, but must be overridden
1458 here for one reason or another. */
1459 {"align", s_align, 0},
1460 {"byte", s_cons, 0},
1461 {"data", s_change_sec, 'd'},
1462 {"double", s_float_cons, 'd'},
1463 {"float", s_float_cons, 'f'},
1464 {"globl", s_mips_globl, 0},
1465 {"global", s_mips_globl, 0},
1466 {"hword", s_cons, 1},
1468 {"long", s_cons, 2},
1469 {"octa", s_cons, 4},
1470 {"quad", s_cons, 3},
1471 {"section", s_change_section, 0},
1472 {"short", s_cons, 1},
1473 {"single", s_float_cons, 'f'},
1474 {"stabn", s_mips_stab, 'n'},
1475 {"text", s_change_sec, 't'},
1476 {"word", s_cons, 2},
1478 { "extern", ecoff_directive_extern, 0},
1483 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1485 /* These pseudo-ops should be defined by the object file format.
1486 However, a.out doesn't support them, so we have versions here. */
1487 {"aent", s_mips_ent, 1},
1488 {"bgnb", s_ignore, 0},
1489 {"end", s_mips_end, 0},
1490 {"endb", s_ignore, 0},
1491 {"ent", s_mips_ent, 0},
1492 {"file", s_mips_file, 0},
1493 {"fmask", s_mips_mask, 'F'},
1494 {"frame", s_mips_frame, 0},
1495 {"loc", s_mips_loc, 0},
1496 {"mask", s_mips_mask, 'R'},
1497 {"verstamp", s_ignore, 0},
1501 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1502 purpose of the `.dc.a' internal pseudo-op. */
1505 mips_address_bytes (void)
1507 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1510 extern void pop_insert (const pseudo_typeS *);
1513 mips_pop_insert (void)
1515 pop_insert (mips_pseudo_table);
1516 if (! ECOFF_DEBUGGING)
1517 pop_insert (mips_nonecoff_pseudo_table);
1520 /* Symbols labelling the current insn. */
1522 struct insn_label_list
1524 struct insn_label_list *next;
1528 static struct insn_label_list *free_insn_labels;
1529 #define label_list tc_segment_info_data.labels
1531 static void mips_clear_insn_labels (void);
1532 static void mips_mark_labels (void);
1533 static void mips_compressed_mark_labels (void);
1536 mips_clear_insn_labels (void)
1538 register struct insn_label_list **pl;
1539 segment_info_type *si;
1543 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1546 si = seg_info (now_seg);
1547 *pl = si->label_list;
1548 si->label_list = NULL;
1552 /* Mark instruction labels in MIPS16/microMIPS mode. */
1555 mips_mark_labels (void)
1557 if (HAVE_CODE_COMPRESSION)
1558 mips_compressed_mark_labels ();
1561 static char *expr_end;
1563 /* Expressions which appear in instructions. These are set by
1566 static expressionS imm_expr;
1567 static expressionS imm2_expr;
1568 static expressionS offset_expr;
1570 /* Relocs associated with imm_expr and offset_expr. */
1572 static bfd_reloc_code_real_type imm_reloc[3]
1573 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1574 static bfd_reloc_code_real_type offset_reloc[3]
1575 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1577 /* This is set to the resulting size of the instruction to be produced
1578 by mips16_ip if an explicit extension is used or by mips_ip if an
1579 explicit size is supplied. */
1581 static unsigned int forced_insn_length;
1583 /* True if we are assembling an instruction. All dot symbols defined during
1584 this time should be treated as code labels. */
1586 static bfd_boolean mips_assembling_insn;
1589 /* The pdr segment for per procedure frame/regmask info. Not used for
1592 static segT pdr_seg;
1595 /* The default target format to use. */
1597 #if defined (TE_FreeBSD)
1598 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1599 #elif defined (TE_TMIPS)
1600 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1602 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1606 mips_target_format (void)
1608 switch (OUTPUT_FLAVOR)
1610 case bfd_target_ecoff_flavour:
1611 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1612 case bfd_target_coff_flavour:
1614 case bfd_target_elf_flavour:
1616 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1617 return (target_big_endian
1618 ? "elf32-bigmips-vxworks"
1619 : "elf32-littlemips-vxworks");
1621 return (target_big_endian
1622 ? (HAVE_64BIT_OBJECTS
1623 ? ELF_TARGET ("elf64-", "big")
1625 ? ELF_TARGET ("elf32-n", "big")
1626 : ELF_TARGET ("elf32-", "big")))
1627 : (HAVE_64BIT_OBJECTS
1628 ? ELF_TARGET ("elf64-", "little")
1630 ? ELF_TARGET ("elf32-n", "little")
1631 : ELF_TARGET ("elf32-", "little"))));
1638 /* Return the length of a microMIPS instruction in bytes. If bits of
1639 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1640 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1641 major opcode) will require further modifications to the opcode
1644 static inline unsigned int
1645 micromips_insn_length (const struct mips_opcode *mo)
1647 return (mo->mask >> 16) == 0 ? 2 : 4;
1650 /* Return the length of MIPS16 instruction OPCODE. */
1652 static inline unsigned int
1653 mips16_opcode_length (unsigned long opcode)
1655 return (opcode >> 16) == 0 ? 2 : 4;
1658 /* Return the length of instruction INSN. */
1660 static inline unsigned int
1661 insn_length (const struct mips_cl_insn *insn)
1663 if (mips_opts.micromips)
1664 return micromips_insn_length (insn->insn_mo);
1665 else if (mips_opts.mips16)
1666 return mips16_opcode_length (insn->insn_opcode);
1671 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1674 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1679 insn->insn_opcode = mo->match;
1682 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1683 insn->fixp[i] = NULL;
1684 insn->fixed_p = (mips_opts.noreorder > 0);
1685 insn->noreorder_p = (mips_opts.noreorder > 0);
1686 insn->mips16_absolute_jump_p = 0;
1687 insn->complete_p = 0;
1688 insn->cleared_p = 0;
1691 /* Record the current MIPS16/microMIPS mode in now_seg. */
1694 mips_record_compressed_mode (void)
1696 segment_info_type *si;
1698 si = seg_info (now_seg);
1699 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1700 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1701 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1702 si->tc_segment_info_data.micromips = mips_opts.micromips;
1705 /* Read a standard MIPS instruction from BUF. */
1707 static unsigned long
1708 read_insn (char *buf)
1710 if (target_big_endian)
1711 return bfd_getb32 ((bfd_byte *) buf);
1713 return bfd_getl32 ((bfd_byte *) buf);
1716 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1720 write_insn (char *buf, unsigned int insn)
1722 md_number_to_chars (buf, insn, 4);
1726 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1727 has length LENGTH. */
1729 static unsigned long
1730 read_compressed_insn (char *buf, unsigned int length)
1736 for (i = 0; i < length; i += 2)
1739 if (target_big_endian)
1740 insn |= bfd_getb16 ((char *) buf);
1742 insn |= bfd_getl16 ((char *) buf);
1748 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1749 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1752 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1756 for (i = 0; i < length; i += 2)
1757 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1758 return buf + length;
1761 /* Install INSN at the location specified by its "frag" and "where" fields. */
1764 install_insn (const struct mips_cl_insn *insn)
1766 char *f = insn->frag->fr_literal + insn->where;
1767 if (HAVE_CODE_COMPRESSION)
1768 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1770 write_insn (f, insn->insn_opcode);
1771 mips_record_compressed_mode ();
1774 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1775 and install the opcode in the new location. */
1778 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1783 insn->where = where;
1784 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1785 if (insn->fixp[i] != NULL)
1787 insn->fixp[i]->fx_frag = frag;
1788 insn->fixp[i]->fx_where = where;
1790 install_insn (insn);
1793 /* Add INSN to the end of the output. */
1796 add_fixed_insn (struct mips_cl_insn *insn)
1798 char *f = frag_more (insn_length (insn));
1799 move_insn (insn, frag_now, f - frag_now->fr_literal);
1802 /* Start a variant frag and move INSN to the start of the variant part,
1803 marking it as fixed. The other arguments are as for frag_var. */
1806 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1807 relax_substateT subtype, symbolS *symbol, offsetT offset)
1809 frag_grow (max_chars);
1810 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1812 frag_var (rs_machine_dependent, max_chars, var,
1813 subtype, symbol, offset, NULL);
1816 /* Insert N copies of INSN into the history buffer, starting at
1817 position FIRST. Neither FIRST nor N need to be clipped. */
1820 insert_into_history (unsigned int first, unsigned int n,
1821 const struct mips_cl_insn *insn)
1823 if (mips_relax.sequence != 2)
1827 for (i = ARRAY_SIZE (history); i-- > first;)
1829 history[i] = history[i - n];
1835 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1836 the idea is to make it obvious at a glance that each errata is
1840 init_vr4120_conflicts (void)
1842 #define CONFLICT(FIRST, SECOND) \
1843 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1845 /* Errata 21 - [D]DIV[U] after [D]MACC */
1846 CONFLICT (MACC, DIV);
1847 CONFLICT (DMACC, DIV);
1849 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1850 CONFLICT (DMULT, DMULT);
1851 CONFLICT (DMULT, DMACC);
1852 CONFLICT (DMACC, DMULT);
1853 CONFLICT (DMACC, DMACC);
1855 /* Errata 24 - MT{LO,HI} after [D]MACC */
1856 CONFLICT (MACC, MTHILO);
1857 CONFLICT (DMACC, MTHILO);
1859 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1860 instruction is executed immediately after a MACC or DMACC
1861 instruction, the result of [either instruction] is incorrect." */
1862 CONFLICT (MACC, MULT);
1863 CONFLICT (MACC, DMULT);
1864 CONFLICT (DMACC, MULT);
1865 CONFLICT (DMACC, DMULT);
1867 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1868 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1869 DDIV or DDIVU instruction, the result of the MACC or
1870 DMACC instruction is incorrect.". */
1871 CONFLICT (DMULT, MACC);
1872 CONFLICT (DMULT, DMACC);
1873 CONFLICT (DIV, MACC);
1874 CONFLICT (DIV, DMACC);
1884 #define RTYPE_MASK 0x1ff00
1885 #define RTYPE_NUM 0x00100
1886 #define RTYPE_FPU 0x00200
1887 #define RTYPE_FCC 0x00400
1888 #define RTYPE_VEC 0x00800
1889 #define RTYPE_GP 0x01000
1890 #define RTYPE_CP0 0x02000
1891 #define RTYPE_PC 0x04000
1892 #define RTYPE_ACC 0x08000
1893 #define RTYPE_CCC 0x10000
1894 #define RNUM_MASK 0x000ff
1895 #define RWARN 0x80000
1897 #define GENERIC_REGISTER_NUMBERS \
1898 {"$0", RTYPE_NUM | 0}, \
1899 {"$1", RTYPE_NUM | 1}, \
1900 {"$2", RTYPE_NUM | 2}, \
1901 {"$3", RTYPE_NUM | 3}, \
1902 {"$4", RTYPE_NUM | 4}, \
1903 {"$5", RTYPE_NUM | 5}, \
1904 {"$6", RTYPE_NUM | 6}, \
1905 {"$7", RTYPE_NUM | 7}, \
1906 {"$8", RTYPE_NUM | 8}, \
1907 {"$9", RTYPE_NUM | 9}, \
1908 {"$10", RTYPE_NUM | 10}, \
1909 {"$11", RTYPE_NUM | 11}, \
1910 {"$12", RTYPE_NUM | 12}, \
1911 {"$13", RTYPE_NUM | 13}, \
1912 {"$14", RTYPE_NUM | 14}, \
1913 {"$15", RTYPE_NUM | 15}, \
1914 {"$16", RTYPE_NUM | 16}, \
1915 {"$17", RTYPE_NUM | 17}, \
1916 {"$18", RTYPE_NUM | 18}, \
1917 {"$19", RTYPE_NUM | 19}, \
1918 {"$20", RTYPE_NUM | 20}, \
1919 {"$21", RTYPE_NUM | 21}, \
1920 {"$22", RTYPE_NUM | 22}, \
1921 {"$23", RTYPE_NUM | 23}, \
1922 {"$24", RTYPE_NUM | 24}, \
1923 {"$25", RTYPE_NUM | 25}, \
1924 {"$26", RTYPE_NUM | 26}, \
1925 {"$27", RTYPE_NUM | 27}, \
1926 {"$28", RTYPE_NUM | 28}, \
1927 {"$29", RTYPE_NUM | 29}, \
1928 {"$30", RTYPE_NUM | 30}, \
1929 {"$31", RTYPE_NUM | 31}
1931 #define FPU_REGISTER_NAMES \
1932 {"$f0", RTYPE_FPU | 0}, \
1933 {"$f1", RTYPE_FPU | 1}, \
1934 {"$f2", RTYPE_FPU | 2}, \
1935 {"$f3", RTYPE_FPU | 3}, \
1936 {"$f4", RTYPE_FPU | 4}, \
1937 {"$f5", RTYPE_FPU | 5}, \
1938 {"$f6", RTYPE_FPU | 6}, \
1939 {"$f7", RTYPE_FPU | 7}, \
1940 {"$f8", RTYPE_FPU | 8}, \
1941 {"$f9", RTYPE_FPU | 9}, \
1942 {"$f10", RTYPE_FPU | 10}, \
1943 {"$f11", RTYPE_FPU | 11}, \
1944 {"$f12", RTYPE_FPU | 12}, \
1945 {"$f13", RTYPE_FPU | 13}, \
1946 {"$f14", RTYPE_FPU | 14}, \
1947 {"$f15", RTYPE_FPU | 15}, \
1948 {"$f16", RTYPE_FPU | 16}, \
1949 {"$f17", RTYPE_FPU | 17}, \
1950 {"$f18", RTYPE_FPU | 18}, \
1951 {"$f19", RTYPE_FPU | 19}, \
1952 {"$f20", RTYPE_FPU | 20}, \
1953 {"$f21", RTYPE_FPU | 21}, \
1954 {"$f22", RTYPE_FPU | 22}, \
1955 {"$f23", RTYPE_FPU | 23}, \
1956 {"$f24", RTYPE_FPU | 24}, \
1957 {"$f25", RTYPE_FPU | 25}, \
1958 {"$f26", RTYPE_FPU | 26}, \
1959 {"$f27", RTYPE_FPU | 27}, \
1960 {"$f28", RTYPE_FPU | 28}, \
1961 {"$f29", RTYPE_FPU | 29}, \
1962 {"$f30", RTYPE_FPU | 30}, \
1963 {"$f31", RTYPE_FPU | 31}
1965 #define FPU_CONDITION_CODE_NAMES \
1966 {"$fcc0", RTYPE_FCC | 0}, \
1967 {"$fcc1", RTYPE_FCC | 1}, \
1968 {"$fcc2", RTYPE_FCC | 2}, \
1969 {"$fcc3", RTYPE_FCC | 3}, \
1970 {"$fcc4", RTYPE_FCC | 4}, \
1971 {"$fcc5", RTYPE_FCC | 5}, \
1972 {"$fcc6", RTYPE_FCC | 6}, \
1973 {"$fcc7", RTYPE_FCC | 7}
1975 #define COPROC_CONDITION_CODE_NAMES \
1976 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1977 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1978 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1979 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1980 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1981 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1982 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1983 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1985 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1986 {"$a4", RTYPE_GP | 8}, \
1987 {"$a5", RTYPE_GP | 9}, \
1988 {"$a6", RTYPE_GP | 10}, \
1989 {"$a7", RTYPE_GP | 11}, \
1990 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1991 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1992 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1993 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1994 {"$t0", RTYPE_GP | 12}, \
1995 {"$t1", RTYPE_GP | 13}, \
1996 {"$t2", RTYPE_GP | 14}, \
1997 {"$t3", RTYPE_GP | 15}
1999 #define O32_SYMBOLIC_REGISTER_NAMES \
2000 {"$t0", RTYPE_GP | 8}, \
2001 {"$t1", RTYPE_GP | 9}, \
2002 {"$t2", RTYPE_GP | 10}, \
2003 {"$t3", RTYPE_GP | 11}, \
2004 {"$t4", RTYPE_GP | 12}, \
2005 {"$t5", RTYPE_GP | 13}, \
2006 {"$t6", RTYPE_GP | 14}, \
2007 {"$t7", RTYPE_GP | 15}, \
2008 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2009 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2010 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2011 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2013 /* Remaining symbolic register names */
2014 #define SYMBOLIC_REGISTER_NAMES \
2015 {"$zero", RTYPE_GP | 0}, \
2016 {"$at", RTYPE_GP | 1}, \
2017 {"$AT", RTYPE_GP | 1}, \
2018 {"$v0", RTYPE_GP | 2}, \
2019 {"$v1", RTYPE_GP | 3}, \
2020 {"$a0", RTYPE_GP | 4}, \
2021 {"$a1", RTYPE_GP | 5}, \
2022 {"$a2", RTYPE_GP | 6}, \
2023 {"$a3", RTYPE_GP | 7}, \
2024 {"$s0", RTYPE_GP | 16}, \
2025 {"$s1", RTYPE_GP | 17}, \
2026 {"$s2", RTYPE_GP | 18}, \
2027 {"$s3", RTYPE_GP | 19}, \
2028 {"$s4", RTYPE_GP | 20}, \
2029 {"$s5", RTYPE_GP | 21}, \
2030 {"$s6", RTYPE_GP | 22}, \
2031 {"$s7", RTYPE_GP | 23}, \
2032 {"$t8", RTYPE_GP | 24}, \
2033 {"$t9", RTYPE_GP | 25}, \
2034 {"$k0", RTYPE_GP | 26}, \
2035 {"$kt0", RTYPE_GP | 26}, \
2036 {"$k1", RTYPE_GP | 27}, \
2037 {"$kt1", RTYPE_GP | 27}, \
2038 {"$gp", RTYPE_GP | 28}, \
2039 {"$sp", RTYPE_GP | 29}, \
2040 {"$s8", RTYPE_GP | 30}, \
2041 {"$fp", RTYPE_GP | 30}, \
2042 {"$ra", RTYPE_GP | 31}
2044 #define MIPS16_SPECIAL_REGISTER_NAMES \
2045 {"$pc", RTYPE_PC | 0}
2047 #define MDMX_VECTOR_REGISTER_NAMES \
2048 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2049 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2050 {"$v2", RTYPE_VEC | 2}, \
2051 {"$v3", RTYPE_VEC | 3}, \
2052 {"$v4", RTYPE_VEC | 4}, \
2053 {"$v5", RTYPE_VEC | 5}, \
2054 {"$v6", RTYPE_VEC | 6}, \
2055 {"$v7", RTYPE_VEC | 7}, \
2056 {"$v8", RTYPE_VEC | 8}, \
2057 {"$v9", RTYPE_VEC | 9}, \
2058 {"$v10", RTYPE_VEC | 10}, \
2059 {"$v11", RTYPE_VEC | 11}, \
2060 {"$v12", RTYPE_VEC | 12}, \
2061 {"$v13", RTYPE_VEC | 13}, \
2062 {"$v14", RTYPE_VEC | 14}, \
2063 {"$v15", RTYPE_VEC | 15}, \
2064 {"$v16", RTYPE_VEC | 16}, \
2065 {"$v17", RTYPE_VEC | 17}, \
2066 {"$v18", RTYPE_VEC | 18}, \
2067 {"$v19", RTYPE_VEC | 19}, \
2068 {"$v20", RTYPE_VEC | 20}, \
2069 {"$v21", RTYPE_VEC | 21}, \
2070 {"$v22", RTYPE_VEC | 22}, \
2071 {"$v23", RTYPE_VEC | 23}, \
2072 {"$v24", RTYPE_VEC | 24}, \
2073 {"$v25", RTYPE_VEC | 25}, \
2074 {"$v26", RTYPE_VEC | 26}, \
2075 {"$v27", RTYPE_VEC | 27}, \
2076 {"$v28", RTYPE_VEC | 28}, \
2077 {"$v29", RTYPE_VEC | 29}, \
2078 {"$v30", RTYPE_VEC | 30}, \
2079 {"$v31", RTYPE_VEC | 31}
2081 #define MIPS_DSP_ACCUMULATOR_NAMES \
2082 {"$ac0", RTYPE_ACC | 0}, \
2083 {"$ac1", RTYPE_ACC | 1}, \
2084 {"$ac2", RTYPE_ACC | 2}, \
2085 {"$ac3", RTYPE_ACC | 3}
2087 static const struct regname reg_names[] = {
2088 GENERIC_REGISTER_NUMBERS,
2090 FPU_CONDITION_CODE_NAMES,
2091 COPROC_CONDITION_CODE_NAMES,
2093 /* The $txx registers depends on the abi,
2094 these will be added later into the symbol table from
2095 one of the tables below once mips_abi is set after
2096 parsing of arguments from the command line. */
2097 SYMBOLIC_REGISTER_NAMES,
2099 MIPS16_SPECIAL_REGISTER_NAMES,
2100 MDMX_VECTOR_REGISTER_NAMES,
2101 MIPS_DSP_ACCUMULATOR_NAMES,
2105 static const struct regname reg_names_o32[] = {
2106 O32_SYMBOLIC_REGISTER_NAMES,
2110 static const struct regname reg_names_n32n64[] = {
2111 N32N64_SYMBOLIC_REGISTER_NAMES,
2115 /* Check if S points at a valid register specifier according to TYPES.
2116 If so, then return 1, advance S to consume the specifier and store
2117 the register's number in REGNOP, otherwise return 0. */
2120 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2127 /* Find end of name. */
2129 if (is_name_beginner (*e))
2131 while (is_part_of_name (*e))
2134 /* Terminate name. */
2138 /* Look for a register symbol. */
2139 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2141 int r = S_GET_VALUE (symbolP);
2143 reg = r & RNUM_MASK;
2144 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2145 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2146 reg = (r & RNUM_MASK) - 2;
2148 /* Else see if this is a register defined in an itbl entry. */
2149 else if ((types & RTYPE_GP) && itbl_have_entries)
2156 if (itbl_get_reg_val (n, &r))
2157 reg = r & RNUM_MASK;
2160 /* Advance to next token if a register was recognised. */
2163 else if (types & RWARN)
2164 as_warn (_("Unrecognized register name `%s'"), *s);
2172 /* Check if S points at a valid register list according to TYPES.
2173 If so, then return 1, advance S to consume the list and store
2174 the registers present on the list as a bitmask of ones in REGLISTP,
2175 otherwise return 0. A valid list comprises a comma-separated
2176 enumeration of valid single registers and/or dash-separated
2177 contiguous register ranges as determined by their numbers.
2179 As a special exception if one of s0-s7 registers is specified as
2180 the range's lower delimiter and s8 (fp) is its upper one, then no
2181 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2182 are selected; they have to be listed separately if needed. */
2185 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2187 unsigned int reglist = 0;
2188 unsigned int lastregno;
2189 bfd_boolean ok = TRUE;
2190 unsigned int regmask;
2191 char *s_endlist = *s;
2195 while (reg_lookup (s, types, ®no))
2201 ok = reg_lookup (s, types, &lastregno);
2202 if (ok && lastregno < regno)
2208 if (lastregno == FP && regno >= S0 && regno <= S7)
2213 regmask = 1 << lastregno;
2214 regmask = (regmask << 1) - 1;
2215 regmask ^= (1 << regno) - 1;
2229 *reglistp = reglist;
2230 return ok && reglist != 0;
2233 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2234 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2237 is_opcode_valid (const struct mips_opcode *mo)
2239 int isa = mips_opts.isa;
2242 if (mips_opts.ase_mdmx)
2244 if (mips_opts.ase_dsp)
2246 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2248 if (mips_opts.ase_dspr2)
2250 if (mips_opts.ase_mt)
2252 if (mips_opts.ase_mips3d)
2254 if (mips_opts.ase_smartmips)
2255 isa |= INSN_SMARTMIPS;
2256 if (mips_opts.ase_mcu)
2259 if (!opcode_is_member (mo, isa, mips_opts.arch))
2262 /* Check whether the instruction or macro requires single-precision or
2263 double-precision floating-point support. Note that this information is
2264 stored differently in the opcode table for insns and macros. */
2265 if (mo->pinfo == INSN_MACRO)
2267 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2268 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2272 fp_s = mo->pinfo & FP_S;
2273 fp_d = mo->pinfo & FP_D;
2276 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2279 if (fp_s && mips_opts.soft_float)
2285 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2286 selected ISA and architecture. */
2289 is_opcode_valid_16 (const struct mips_opcode *mo)
2291 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2294 /* Return TRUE if the size of the microMIPS opcode MO matches one
2295 explicitly requested. Always TRUE in the standard MIPS mode. */
2298 is_size_valid (const struct mips_opcode *mo)
2300 if (!mips_opts.micromips)
2303 if (!forced_insn_length)
2305 if (mo->pinfo == INSN_MACRO)
2307 return forced_insn_length == micromips_insn_length (mo);
2310 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2311 of the preceding instruction. Always TRUE in the standard MIPS mode.
2313 We don't accept macros in 16-bit delay slots to avoid a case where
2314 a macro expansion fails because it relies on a preceding 32-bit real
2315 instruction to have matched and does not handle the operands correctly.
2316 The only macros that may expand to 16-bit instructions are JAL that
2317 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2318 and BGT (that likewise cannot be placed in a delay slot) that decay to
2319 a NOP. In all these cases the macros precede any corresponding real
2320 instruction definitions in the opcode table, so they will match in the
2321 second pass where the size of the delay slot is ignored and therefore
2322 produce correct code. */
2325 is_delay_slot_valid (const struct mips_opcode *mo)
2327 if (!mips_opts.micromips)
2330 if (mo->pinfo == INSN_MACRO)
2331 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2332 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2333 && micromips_insn_length (mo) != 4)
2335 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2336 && micromips_insn_length (mo) != 2)
2342 /* This function is called once, at assembler startup time. It should set up
2343 all the tables, etc. that the MD part of the assembler will need. */
2348 const char *retval = NULL;
2352 if (mips_pic != NO_PIC)
2354 if (g_switch_seen && g_switch_value != 0)
2355 as_bad (_("-G may not be used in position-independent code"));
2359 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2360 as_warn (_("Could not set architecture and machine"));
2362 op_hash = hash_new ();
2364 for (i = 0; i < NUMOPCODES;)
2366 const char *name = mips_opcodes[i].name;
2368 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2371 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2372 mips_opcodes[i].name, retval);
2373 /* Probably a memory allocation problem? Give up now. */
2374 as_fatal (_("Broken assembler. No assembly attempted."));
2378 if (mips_opcodes[i].pinfo != INSN_MACRO)
2380 if (!validate_mips_insn (&mips_opcodes[i]))
2382 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2384 create_insn (&nop_insn, mips_opcodes + i);
2385 if (mips_fix_loongson2f_nop)
2386 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2387 nop_insn.fixed_p = 1;
2392 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2395 mips16_op_hash = hash_new ();
2398 while (i < bfd_mips16_num_opcodes)
2400 const char *name = mips16_opcodes[i].name;
2402 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2404 as_fatal (_("internal: can't hash `%s': %s"),
2405 mips16_opcodes[i].name, retval);
2408 if (mips16_opcodes[i].pinfo != INSN_MACRO
2409 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2410 != mips16_opcodes[i].match))
2412 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2413 mips16_opcodes[i].name, mips16_opcodes[i].args);
2416 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2418 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2419 mips16_nop_insn.fixed_p = 1;
2423 while (i < bfd_mips16_num_opcodes
2424 && strcmp (mips16_opcodes[i].name, name) == 0);
2427 micromips_op_hash = hash_new ();
2430 while (i < bfd_micromips_num_opcodes)
2432 const char *name = micromips_opcodes[i].name;
2434 retval = hash_insert (micromips_op_hash, name,
2435 (void *) µmips_opcodes[i]);
2437 as_fatal (_("internal: can't hash `%s': %s"),
2438 micromips_opcodes[i].name, retval);
2440 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2442 struct mips_cl_insn *micromips_nop_insn;
2444 if (!validate_micromips_insn (µmips_opcodes[i]))
2447 if (micromips_insn_length (micromips_opcodes + i) == 2)
2448 micromips_nop_insn = µmips_nop16_insn;
2449 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2450 micromips_nop_insn = µmips_nop32_insn;
2454 if (micromips_nop_insn->insn_mo == NULL
2455 && strcmp (name, "nop") == 0)
2457 create_insn (micromips_nop_insn, micromips_opcodes + i);
2458 micromips_nop_insn->fixed_p = 1;
2461 while (++i < bfd_micromips_num_opcodes
2462 && strcmp (micromips_opcodes[i].name, name) == 0);
2466 as_fatal (_("Broken assembler. No assembly attempted."));
2468 /* We add all the general register names to the symbol table. This
2469 helps us detect invalid uses of them. */
2470 for (i = 0; reg_names[i].name; i++)
2471 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2472 reg_names[i].num, /* & RNUM_MASK, */
2473 &zero_address_frag));
2475 for (i = 0; reg_names_n32n64[i].name; i++)
2476 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2477 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2478 &zero_address_frag));
2480 for (i = 0; reg_names_o32[i].name; i++)
2481 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2482 reg_names_o32[i].num, /* & RNUM_MASK, */
2483 &zero_address_frag));
2485 mips_no_prev_insn ();
2488 mips_cprmask[0] = 0;
2489 mips_cprmask[1] = 0;
2490 mips_cprmask[2] = 0;
2491 mips_cprmask[3] = 0;
2493 /* set the default alignment for the text section (2**2) */
2494 record_alignment (text_section, 2);
2496 bfd_set_gp_size (stdoutput, g_switch_value);
2501 /* On a native system other than VxWorks, sections must be aligned
2502 to 16 byte boundaries. When configured for an embedded ELF
2503 target, we don't bother. */
2504 if (strncmp (TARGET_OS, "elf", 3) != 0
2505 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2507 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2508 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2509 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2512 /* Create a .reginfo section for register masks and a .mdebug
2513 section for debugging information. */
2521 subseg = now_subseg;
2523 /* The ABI says this section should be loaded so that the
2524 running program can access it. However, we don't load it
2525 if we are configured for an embedded target */
2526 flags = SEC_READONLY | SEC_DATA;
2527 if (strncmp (TARGET_OS, "elf", 3) != 0)
2528 flags |= SEC_ALLOC | SEC_LOAD;
2530 if (mips_abi != N64_ABI)
2532 sec = subseg_new (".reginfo", (subsegT) 0);
2534 bfd_set_section_flags (stdoutput, sec, flags);
2535 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2537 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2541 /* The 64-bit ABI uses a .MIPS.options section rather than
2542 .reginfo section. */
2543 sec = subseg_new (".MIPS.options", (subsegT) 0);
2544 bfd_set_section_flags (stdoutput, sec, flags);
2545 bfd_set_section_alignment (stdoutput, sec, 3);
2547 /* Set up the option header. */
2549 Elf_Internal_Options opthdr;
2552 opthdr.kind = ODK_REGINFO;
2553 opthdr.size = (sizeof (Elf_External_Options)
2554 + sizeof (Elf64_External_RegInfo));
2557 f = frag_more (sizeof (Elf_External_Options));
2558 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2559 (Elf_External_Options *) f);
2561 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2565 if (ECOFF_DEBUGGING)
2567 sec = subseg_new (".mdebug", (subsegT) 0);
2568 (void) bfd_set_section_flags (stdoutput, sec,
2569 SEC_HAS_CONTENTS | SEC_READONLY);
2570 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2572 else if (mips_flag_pdr)
2574 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2575 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2576 SEC_READONLY | SEC_RELOC
2578 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2581 subseg_set (seg, subseg);
2584 #endif /* OBJ_ELF */
2586 if (! ECOFF_DEBUGGING)
2589 if (mips_fix_vr4120)
2590 init_vr4120_conflicts ();
2596 mips_emit_delays ();
2597 if (! ECOFF_DEBUGGING)
2602 md_assemble (char *str)
2604 struct mips_cl_insn insn;
2605 bfd_reloc_code_real_type unused_reloc[3]
2606 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2608 imm_expr.X_op = O_absent;
2609 imm2_expr.X_op = O_absent;
2610 offset_expr.X_op = O_absent;
2611 imm_reloc[0] = BFD_RELOC_UNUSED;
2612 imm_reloc[1] = BFD_RELOC_UNUSED;
2613 imm_reloc[2] = BFD_RELOC_UNUSED;
2614 offset_reloc[0] = BFD_RELOC_UNUSED;
2615 offset_reloc[1] = BFD_RELOC_UNUSED;
2616 offset_reloc[2] = BFD_RELOC_UNUSED;
2618 mips_mark_labels ();
2619 mips_assembling_insn = TRUE;
2621 if (mips_opts.mips16)
2622 mips16_ip (str, &insn);
2625 mips_ip (str, &insn);
2626 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2627 str, insn.insn_opcode));
2631 as_bad ("%s `%s'", insn_error, str);
2632 else if (insn.insn_mo->pinfo == INSN_MACRO)
2635 if (mips_opts.mips16)
2636 mips16_macro (&insn);
2643 if (imm_expr.X_op != O_absent)
2644 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2645 else if (offset_expr.X_op != O_absent)
2646 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2648 append_insn (&insn, NULL, unused_reloc, FALSE);
2651 mips_assembling_insn = FALSE;
2654 /* Convenience functions for abstracting away the differences between
2655 MIPS16 and non-MIPS16 relocations. */
2657 static inline bfd_boolean
2658 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2662 case BFD_RELOC_MIPS16_JMP:
2663 case BFD_RELOC_MIPS16_GPREL:
2664 case BFD_RELOC_MIPS16_GOT16:
2665 case BFD_RELOC_MIPS16_CALL16:
2666 case BFD_RELOC_MIPS16_HI16_S:
2667 case BFD_RELOC_MIPS16_HI16:
2668 case BFD_RELOC_MIPS16_LO16:
2676 static inline bfd_boolean
2677 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2681 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2682 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2683 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2684 case BFD_RELOC_MICROMIPS_GPREL16:
2685 case BFD_RELOC_MICROMIPS_JMP:
2686 case BFD_RELOC_MICROMIPS_HI16:
2687 case BFD_RELOC_MICROMIPS_HI16_S:
2688 case BFD_RELOC_MICROMIPS_LO16:
2689 case BFD_RELOC_MICROMIPS_LITERAL:
2690 case BFD_RELOC_MICROMIPS_GOT16:
2691 case BFD_RELOC_MICROMIPS_CALL16:
2692 case BFD_RELOC_MICROMIPS_GOT_HI16:
2693 case BFD_RELOC_MICROMIPS_GOT_LO16:
2694 case BFD_RELOC_MICROMIPS_CALL_HI16:
2695 case BFD_RELOC_MICROMIPS_CALL_LO16:
2696 case BFD_RELOC_MICROMIPS_SUB:
2697 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2698 case BFD_RELOC_MICROMIPS_GOT_OFST:
2699 case BFD_RELOC_MICROMIPS_GOT_DISP:
2700 case BFD_RELOC_MICROMIPS_HIGHEST:
2701 case BFD_RELOC_MICROMIPS_HIGHER:
2702 case BFD_RELOC_MICROMIPS_SCN_DISP:
2703 case BFD_RELOC_MICROMIPS_JALR:
2711 static inline bfd_boolean
2712 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2714 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2717 static inline bfd_boolean
2718 got16_reloc_p (bfd_reloc_code_real_type reloc)
2720 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2721 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2724 static inline bfd_boolean
2725 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2727 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2728 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2731 static inline bfd_boolean
2732 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2734 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2735 || reloc == BFD_RELOC_MICROMIPS_LO16);
2738 static inline bfd_boolean
2739 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2741 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2744 /* Return true if the given relocation might need a matching %lo().
2745 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2746 need a matching %lo() when applied to local symbols. */
2748 static inline bfd_boolean
2749 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2751 return (HAVE_IN_PLACE_ADDENDS
2752 && (hi16_reloc_p (reloc)
2753 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2754 all GOT16 relocations evaluate to "G". */
2755 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2758 /* Return the type of %lo() reloc needed by RELOC, given that
2759 reloc_needs_lo_p. */
2761 static inline bfd_reloc_code_real_type
2762 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2764 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2765 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2769 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2772 static inline bfd_boolean
2773 fixup_has_matching_lo_p (fixS *fixp)
2775 return (fixp->fx_next != NULL
2776 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2777 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2778 && fixp->fx_offset == fixp->fx_next->fx_offset);
2781 /* This function returns true if modifying a register requires a
2785 reg_needs_delay (unsigned int reg)
2787 unsigned long prev_pinfo;
2789 prev_pinfo = history[0].insn_mo->pinfo;
2790 if (! mips_opts.noreorder
2791 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2792 && ! gpr_interlocks)
2793 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2794 && ! cop_interlocks)))
2796 /* A load from a coprocessor or from memory. All load delays
2797 delay the use of general register rt for one instruction. */
2798 /* Itbl support may require additional care here. */
2799 know (prev_pinfo & INSN_WRITE_GPR_T);
2800 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2807 /* Move all labels in LABELS to the current insertion point. TEXT_P
2808 says whether the labels refer to text or data. */
2811 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2813 struct insn_label_list *l;
2816 for (l = labels; l != NULL; l = l->next)
2818 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2819 symbol_set_frag (l->label, frag_now);
2820 val = (valueT) frag_now_fix ();
2821 /* MIPS16/microMIPS text labels are stored as odd. */
2822 if (text_p && HAVE_CODE_COMPRESSION)
2824 S_SET_VALUE (l->label, val);
2828 /* Move all labels in insn_labels to the current insertion point
2829 and treat them as text labels. */
2832 mips_move_text_labels (void)
2834 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2838 s_is_linkonce (symbolS *sym, segT from_seg)
2840 bfd_boolean linkonce = FALSE;
2841 segT symseg = S_GET_SEGMENT (sym);
2843 if (symseg != from_seg && !S_IS_LOCAL (sym))
2845 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2848 /* The GNU toolchain uses an extension for ELF: a section
2849 beginning with the magic string .gnu.linkonce is a
2850 linkonce section. */
2851 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2852 sizeof ".gnu.linkonce" - 1) == 0)
2859 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2860 linker to handle them specially, such as generating jalx instructions
2861 when needed. We also make them odd for the duration of the assembly,
2862 in order to generate the right sort of code. We will make them even
2863 in the adjust_symtab routine, while leaving them marked. This is
2864 convenient for the debugger and the disassembler. The linker knows
2865 to make them odd again. */
2868 mips_compressed_mark_label (symbolS *label)
2870 gas_assert (HAVE_CODE_COMPRESSION);
2872 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2875 if (mips_opts.mips16)
2876 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2878 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2881 if ((S_GET_VALUE (label) & 1) == 0
2882 /* Don't adjust the address if the label is global or weak, or
2883 in a link-once section, since we'll be emitting symbol reloc
2884 references to it which will be patched up by the linker, and
2885 the final value of the symbol may or may not be MIPS16/microMIPS. */
2886 && !S_IS_WEAK (label)
2887 && !S_IS_EXTERNAL (label)
2888 && !s_is_linkonce (label, now_seg))
2889 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2892 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2895 mips_compressed_mark_labels (void)
2897 struct insn_label_list *l;
2899 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2900 mips_compressed_mark_label (l->label);
2903 /* End the current frag. Make it a variant frag and record the
2907 relax_close_frag (void)
2909 mips_macro_warning.first_frag = frag_now;
2910 frag_var (rs_machine_dependent, 0, 0,
2911 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2912 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2914 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2915 mips_relax.first_fixup = 0;
2918 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2919 See the comment above RELAX_ENCODE for more details. */
2922 relax_start (symbolS *symbol)
2924 gas_assert (mips_relax.sequence == 0);
2925 mips_relax.sequence = 1;
2926 mips_relax.symbol = symbol;
2929 /* Start generating the second version of a relaxable sequence.
2930 See the comment above RELAX_ENCODE for more details. */
2935 gas_assert (mips_relax.sequence == 1);
2936 mips_relax.sequence = 2;
2939 /* End the current relaxable sequence. */
2944 gas_assert (mips_relax.sequence == 2);
2945 relax_close_frag ();
2946 mips_relax.sequence = 0;
2949 /* Return true if IP is a delayed branch or jump. */
2951 static inline bfd_boolean
2952 delayed_branch_p (const struct mips_cl_insn *ip)
2954 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2955 | INSN_COND_BRANCH_DELAY
2956 | INSN_COND_BRANCH_LIKELY)) != 0;
2959 /* Return true if IP is a compact branch or jump. */
2961 static inline bfd_boolean
2962 compact_branch_p (const struct mips_cl_insn *ip)
2964 if (mips_opts.mips16)
2965 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2966 | MIPS16_INSN_COND_BRANCH)) != 0;
2968 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2969 | INSN2_COND_BRANCH)) != 0;
2972 /* Return true if IP is an unconditional branch or jump. */
2974 static inline bfd_boolean
2975 uncond_branch_p (const struct mips_cl_insn *ip)
2977 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2978 || (mips_opts.mips16
2979 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2980 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2983 /* Return true if IP is a branch-likely instruction. */
2985 static inline bfd_boolean
2986 branch_likely_p (const struct mips_cl_insn *ip)
2988 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2991 /* Return the type of nop that should be used to fill the delay slot
2992 of delayed branch IP. */
2994 static struct mips_cl_insn *
2995 get_delay_slot_nop (const struct mips_cl_insn *ip)
2997 if (mips_opts.micromips
2998 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2999 return µmips_nop32_insn;
3003 /* Return the mask of core registers that IP reads or writes. */
3006 gpr_mod_mask (const struct mips_cl_insn *ip)
3008 unsigned long pinfo2;
3012 pinfo2 = ip->insn_mo->pinfo2;
3013 if (mips_opts.micromips)
3015 if (pinfo2 & INSN2_MOD_GPR_MD)
3016 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3017 if (pinfo2 & INSN2_MOD_GPR_MF)
3018 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3019 if (pinfo2 & INSN2_MOD_SP)
3025 /* Return the mask of core registers that IP reads. */
3028 gpr_read_mask (const struct mips_cl_insn *ip)
3030 unsigned long pinfo, pinfo2;
3033 mask = gpr_mod_mask (ip);
3034 pinfo = ip->insn_mo->pinfo;
3035 pinfo2 = ip->insn_mo->pinfo2;
3036 if (mips_opts.mips16)
3038 if (pinfo & MIPS16_INSN_READ_X)
3039 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3040 if (pinfo & MIPS16_INSN_READ_Y)
3041 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3042 if (pinfo & MIPS16_INSN_READ_T)
3044 if (pinfo & MIPS16_INSN_READ_SP)
3046 if (pinfo & MIPS16_INSN_READ_31)
3048 if (pinfo & MIPS16_INSN_READ_Z)
3049 mask |= 1 << (mips16_to_32_reg_map
3050 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3051 if (pinfo & MIPS16_INSN_READ_GPR_X)
3052 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3056 if (pinfo2 & INSN2_READ_GPR_D)
3057 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3058 if (pinfo & INSN_READ_GPR_T)
3059 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3060 if (pinfo & INSN_READ_GPR_S)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3062 if (pinfo2 & INSN2_READ_GP)
3064 if (pinfo2 & INSN2_READ_GPR_31)
3066 if (pinfo2 & INSN2_READ_GPR_Z)
3067 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3069 if (mips_opts.micromips)
3071 if (pinfo2 & INSN2_READ_GPR_MC)
3072 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3073 if (pinfo2 & INSN2_READ_GPR_ME)
3074 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3075 if (pinfo2 & INSN2_READ_GPR_MG)
3076 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3077 if (pinfo2 & INSN2_READ_GPR_MJ)
3078 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3079 if (pinfo2 & INSN2_READ_GPR_MMN)
3081 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3082 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3084 if (pinfo2 & INSN2_READ_GPR_MP)
3085 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3086 if (pinfo2 & INSN2_READ_GPR_MQ)
3087 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3089 /* Don't include register 0. */
3093 /* Return the mask of core registers that IP writes. */
3096 gpr_write_mask (const struct mips_cl_insn *ip)
3098 unsigned long pinfo, pinfo2;
3101 mask = gpr_mod_mask (ip);
3102 pinfo = ip->insn_mo->pinfo;
3103 pinfo2 = ip->insn_mo->pinfo2;
3104 if (mips_opts.mips16)
3106 if (pinfo & MIPS16_INSN_WRITE_X)
3107 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3108 if (pinfo & MIPS16_INSN_WRITE_Y)
3109 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3110 if (pinfo & MIPS16_INSN_WRITE_Z)
3111 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3112 if (pinfo & MIPS16_INSN_WRITE_T)
3114 if (pinfo & MIPS16_INSN_WRITE_SP)
3116 if (pinfo & MIPS16_INSN_WRITE_31)
3118 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3119 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3123 if (pinfo & INSN_WRITE_GPR_D)
3124 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3125 if (pinfo & INSN_WRITE_GPR_T)
3126 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3127 if (pinfo & INSN_WRITE_GPR_S)
3128 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3129 if (pinfo & INSN_WRITE_GPR_31)
3131 if (pinfo2 & INSN2_WRITE_GPR_Z)
3132 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3134 if (mips_opts.micromips)
3136 if (pinfo2 & INSN2_WRITE_GPR_MB)
3137 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3138 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3140 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3141 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3143 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3144 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3145 if (pinfo2 & INSN2_WRITE_GPR_MP)
3146 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3148 /* Don't include register 0. */
3152 /* Return the mask of floating-point registers that IP reads. */
3155 fpr_read_mask (const struct mips_cl_insn *ip)
3157 unsigned long pinfo, pinfo2;
3161 pinfo = ip->insn_mo->pinfo;
3162 pinfo2 = ip->insn_mo->pinfo2;
3163 if (!mips_opts.mips16)
3165 if (pinfo2 & INSN2_READ_FPR_D)
3166 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3167 if (pinfo & INSN_READ_FPR_S)
3168 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3169 if (pinfo & INSN_READ_FPR_T)
3170 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3171 if (pinfo & INSN_READ_FPR_R)
3172 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3173 if (pinfo2 & INSN2_READ_FPR_Z)
3174 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3176 /* Conservatively treat all operands to an FP_D instruction are doubles.
3177 (This is overly pessimistic for things like cvt.d.s.) */
3178 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3183 /* Return the mask of floating-point registers that IP writes. */
3186 fpr_write_mask (const struct mips_cl_insn *ip)
3188 unsigned long pinfo, pinfo2;
3192 pinfo = ip->insn_mo->pinfo;
3193 pinfo2 = ip->insn_mo->pinfo2;
3194 if (!mips_opts.mips16)
3196 if (pinfo & INSN_WRITE_FPR_D)
3197 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3198 if (pinfo & INSN_WRITE_FPR_S)
3199 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3200 if (pinfo & INSN_WRITE_FPR_T)
3201 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3202 if (pinfo2 & INSN2_WRITE_FPR_Z)
3203 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3205 /* Conservatively treat all operands to an FP_D instruction are doubles.
3206 (This is overly pessimistic for things like cvt.s.d.) */
3207 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3212 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3213 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3214 by VR4120 errata. */
3217 classify_vr4120_insn (const char *name)
3219 if (strncmp (name, "macc", 4) == 0)
3220 return FIX_VR4120_MACC;
3221 if (strncmp (name, "dmacc", 5) == 0)
3222 return FIX_VR4120_DMACC;
3223 if (strncmp (name, "mult", 4) == 0)
3224 return FIX_VR4120_MULT;
3225 if (strncmp (name, "dmult", 5) == 0)
3226 return FIX_VR4120_DMULT;
3227 if (strstr (name, "div"))
3228 return FIX_VR4120_DIV;
3229 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3230 return FIX_VR4120_MTHILO;
3231 return NUM_FIX_VR4120_CLASSES;
3234 #define INSN_ERET 0x42000018
3235 #define INSN_DERET 0x4200001f
3237 /* Return the number of instructions that must separate INSN1 and INSN2,
3238 where INSN1 is the earlier instruction. Return the worst-case value
3239 for any INSN2 if INSN2 is null. */
3242 insns_between (const struct mips_cl_insn *insn1,
3243 const struct mips_cl_insn *insn2)
3245 unsigned long pinfo1, pinfo2;
3248 /* This function needs to know which pinfo flags are set for INSN2
3249 and which registers INSN2 uses. The former is stored in PINFO2 and
3250 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3251 will have every flag set and INSN2_USES_GPR will always return true. */
3252 pinfo1 = insn1->insn_mo->pinfo;
3253 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3255 #define INSN2_USES_GPR(REG) \
3256 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3258 /* For most targets, write-after-read dependencies on the HI and LO
3259 registers must be separated by at least two instructions. */
3260 if (!hilo_interlocks)
3262 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3264 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3268 /* If we're working around r7000 errata, there must be two instructions
3269 between an mfhi or mflo and any instruction that uses the result. */
3270 if (mips_7000_hilo_fix
3271 && !mips_opts.micromips
3272 && MF_HILO_INSN (pinfo1)
3273 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3276 /* If we're working around 24K errata, one instruction is required
3277 if an ERET or DERET is followed by a branch instruction. */
3278 if (mips_fix_24k && !mips_opts.micromips)
3280 if (insn1->insn_opcode == INSN_ERET
3281 || insn1->insn_opcode == INSN_DERET)
3284 || insn2->insn_opcode == INSN_ERET
3285 || insn2->insn_opcode == INSN_DERET
3286 || delayed_branch_p (insn2))
3291 /* If working around VR4120 errata, check for combinations that need
3292 a single intervening instruction. */
3293 if (mips_fix_vr4120 && !mips_opts.micromips)
3295 unsigned int class1, class2;
3297 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3298 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3302 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3303 if (vr4120_conflicts[class1] & (1 << class2))
3308 if (!HAVE_CODE_COMPRESSION)
3310 /* Check for GPR or coprocessor load delays. All such delays
3311 are on the RT register. */
3312 /* Itbl support may require additional care here. */
3313 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3314 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3316 know (pinfo1 & INSN_WRITE_GPR_T);
3317 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3321 /* Check for generic coprocessor hazards.
3323 This case is not handled very well. There is no special
3324 knowledge of CP0 handling, and the coprocessors other than
3325 the floating point unit are not distinguished at all. */
3326 /* Itbl support may require additional care here. FIXME!
3327 Need to modify this to include knowledge about
3328 user specified delays! */
3329 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3330 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3332 /* Handle cases where INSN1 writes to a known general coprocessor
3333 register. There must be a one instruction delay before INSN2
3334 if INSN2 reads that register, otherwise no delay is needed. */
3335 mask = fpr_write_mask (insn1);
3338 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3343 /* Read-after-write dependencies on the control registers
3344 require a two-instruction gap. */
3345 if ((pinfo1 & INSN_WRITE_COND_CODE)
3346 && (pinfo2 & INSN_READ_COND_CODE))
3349 /* We don't know exactly what INSN1 does. If INSN2 is
3350 also a coprocessor instruction, assume there must be
3351 a one instruction gap. */
3352 if (pinfo2 & INSN_COP)
3357 /* Check for read-after-write dependencies on the coprocessor
3358 control registers in cases where INSN1 does not need a general
3359 coprocessor delay. This means that INSN1 is a floating point
3360 comparison instruction. */
3361 /* Itbl support may require additional care here. */
3362 else if (!cop_interlocks
3363 && (pinfo1 & INSN_WRITE_COND_CODE)
3364 && (pinfo2 & INSN_READ_COND_CODE))
3368 #undef INSN2_USES_GPR
3373 /* Return the number of nops that would be needed to work around the
3374 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3375 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3376 that are contained within the first IGNORE instructions of HIST. */
3379 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3380 const struct mips_cl_insn *insn)
3385 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3386 are not affected by the errata. */
3388 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3389 || strcmp (insn->insn_mo->name, "mtlo") == 0
3390 || strcmp (insn->insn_mo->name, "mthi") == 0))
3393 /* Search for the first MFLO or MFHI. */
3394 for (i = 0; i < MAX_VR4130_NOPS; i++)
3395 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3397 /* Extract the destination register. */
3398 mask = gpr_write_mask (&hist[i]);
3400 /* No nops are needed if INSN reads that register. */
3401 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3404 /* ...or if any of the intervening instructions do. */
3405 for (j = 0; j < i; j++)
3406 if (gpr_read_mask (&hist[j]) & mask)
3410 return MAX_VR4130_NOPS - i;
3415 #define BASE_REG_EQ(INSN1, INSN2) \
3416 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3417 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3419 /* Return the minimum alignment for this store instruction. */
3422 fix_24k_align_to (const struct mips_opcode *mo)
3424 if (strcmp (mo->name, "sh") == 0)
3427 if (strcmp (mo->name, "swc1") == 0
3428 || strcmp (mo->name, "swc2") == 0
3429 || strcmp (mo->name, "sw") == 0
3430 || strcmp (mo->name, "sc") == 0
3431 || strcmp (mo->name, "s.s") == 0)
3434 if (strcmp (mo->name, "sdc1") == 0
3435 || strcmp (mo->name, "sdc2") == 0
3436 || strcmp (mo->name, "s.d") == 0)
3443 struct fix_24k_store_info
3445 /* Immediate offset, if any, for this store instruction. */
3447 /* Alignment required by this store instruction. */
3449 /* True for register offsets. */
3450 int register_offset;
3453 /* Comparison function used by qsort. */
3456 fix_24k_sort (const void *a, const void *b)
3458 const struct fix_24k_store_info *pos1 = a;
3459 const struct fix_24k_store_info *pos2 = b;
3461 return (pos1->off - pos2->off);
3464 /* INSN is a store instruction. Try to record the store information
3465 in STINFO. Return false if the information isn't known. */
3468 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3469 const struct mips_cl_insn *insn)
3471 /* The instruction must have a known offset. */
3472 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3475 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3476 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3480 /* Return the number of nops that would be needed to work around the 24k
3481 "lost data on stores during refill" errata if instruction INSN
3482 immediately followed the 2 instructions described by HIST.
3483 Ignore hazards that are contained within the first IGNORE
3484 instructions of HIST.
3486 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3487 for the data cache refills and store data. The following describes
3488 the scenario where the store data could be lost.
3490 * A data cache miss, due to either a load or a store, causing fill
3491 data to be supplied by the memory subsystem
3492 * The first three doublewords of fill data are returned and written
3494 * A sequence of four stores occurs in consecutive cycles around the
3495 final doubleword of the fill:
3499 * Zero, One or more instructions
3502 The four stores A-D must be to different doublewords of the line that
3503 is being filled. The fourth instruction in the sequence above permits
3504 the fill of the final doubleword to be transferred from the FSB into
3505 the cache. In the sequence above, the stores may be either integer
3506 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3507 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3508 different doublewords on the line. If the floating point unit is
3509 running in 1:2 mode, it is not possible to create the sequence above
3510 using only floating point store instructions.
3512 In this case, the cache line being filled is incorrectly marked
3513 invalid, thereby losing the data from any store to the line that
3514 occurs between the original miss and the completion of the five
3515 cycle sequence shown above.
3517 The workarounds are:
3519 * Run the data cache in write-through mode.
3520 * Insert a non-store instruction between
3521 Store A and Store B or Store B and Store C. */
3524 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3525 const struct mips_cl_insn *insn)
3527 struct fix_24k_store_info pos[3];
3528 int align, i, base_offset;
3533 /* If the previous instruction wasn't a store, there's nothing to
3535 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3538 /* If the instructions after the previous one are unknown, we have
3539 to assume the worst. */
3543 /* Check whether we are dealing with three consecutive stores. */
3544 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3545 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3548 /* If we don't know the relationship between the store addresses,
3549 assume the worst. */
3550 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3551 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3554 if (!fix_24k_record_store_info (&pos[0], insn)
3555 || !fix_24k_record_store_info (&pos[1], &hist[0])
3556 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3559 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3561 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3562 X bytes and such that the base register + X is known to be aligned
3565 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3569 align = pos[0].align_to;
3570 base_offset = pos[0].off;
3571 for (i = 1; i < 3; i++)
3572 if (align < pos[i].align_to)
3574 align = pos[i].align_to;
3575 base_offset = pos[i].off;
3577 for (i = 0; i < 3; i++)
3578 pos[i].off -= base_offset;
3581 pos[0].off &= ~align + 1;
3582 pos[1].off &= ~align + 1;
3583 pos[2].off &= ~align + 1;
3585 /* If any two stores write to the same chunk, they also write to the
3586 same doubleword. The offsets are still sorted at this point. */
3587 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3590 /* A range of at least 9 bytes is needed for the stores to be in
3591 non-overlapping doublewords. */
3592 if (pos[2].off - pos[0].off <= 8)
3595 if (pos[2].off - pos[1].off >= 24
3596 || pos[1].off - pos[0].off >= 24
3597 || pos[2].off - pos[0].off >= 32)
3603 /* Return the number of nops that would be needed if instruction INSN
3604 immediately followed the MAX_NOPS instructions given by HIST,
3605 where HIST[0] is the most recent instruction. Ignore hazards
3606 between INSN and the first IGNORE instructions in HIST.
3608 If INSN is null, return the worse-case number of nops for any
3612 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3613 const struct mips_cl_insn *insn)
3615 int i, nops, tmp_nops;
3618 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3620 tmp_nops = insns_between (hist + i, insn) - i;
3621 if (tmp_nops > nops)
3625 if (mips_fix_vr4130 && !mips_opts.micromips)
3627 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3628 if (tmp_nops > nops)
3632 if (mips_fix_24k && !mips_opts.micromips)
3634 tmp_nops = nops_for_24k (ignore, hist, insn);
3635 if (tmp_nops > nops)
3642 /* The variable arguments provide NUM_INSNS extra instructions that
3643 might be added to HIST. Return the largest number of nops that
3644 would be needed after the extended sequence, ignoring hazards
3645 in the first IGNORE instructions. */
3648 nops_for_sequence (int num_insns, int ignore,
3649 const struct mips_cl_insn *hist, ...)
3652 struct mips_cl_insn buffer[MAX_NOPS];
3653 struct mips_cl_insn *cursor;
3656 va_start (args, hist);
3657 cursor = buffer + num_insns;
3658 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3659 while (cursor > buffer)
3660 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3662 nops = nops_for_insn (ignore, buffer, NULL);
3667 /* Like nops_for_insn, but if INSN is a branch, take into account the
3668 worst-case delay for the branch target. */
3671 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3672 const struct mips_cl_insn *insn)
3676 nops = nops_for_insn (ignore, hist, insn);
3677 if (delayed_branch_p (insn))
3679 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3680 hist, insn, get_delay_slot_nop (insn));
3681 if (tmp_nops > nops)
3684 else if (compact_branch_p (insn))
3686 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3687 if (tmp_nops > nops)
3693 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3696 fix_loongson2f_nop (struct mips_cl_insn * ip)
3698 gas_assert (!HAVE_CODE_COMPRESSION);
3699 if (strcmp (ip->insn_mo->name, "nop") == 0)
3700 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3703 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3704 jr target pc &= 'hffff_ffff_cfff_ffff. */
3707 fix_loongson2f_jump (struct mips_cl_insn * ip)
3709 gas_assert (!HAVE_CODE_COMPRESSION);
3710 if (strcmp (ip->insn_mo->name, "j") == 0
3711 || strcmp (ip->insn_mo->name, "jr") == 0
3712 || strcmp (ip->insn_mo->name, "jalr") == 0)
3720 sreg = EXTRACT_OPERAND (0, RS, *ip);
3721 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3724 ep.X_op = O_constant;
3725 ep.X_add_number = 0xcfff0000;
3726 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3727 ep.X_add_number = 0xffff;
3728 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3729 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3734 fix_loongson2f (struct mips_cl_insn * ip)
3736 if (mips_fix_loongson2f_nop)
3737 fix_loongson2f_nop (ip);
3739 if (mips_fix_loongson2f_jump)
3740 fix_loongson2f_jump (ip);
3743 /* IP is a branch that has a delay slot, and we need to fill it
3744 automatically. Return true if we can do that by swapping IP
3745 with the previous instruction.
3746 ADDRESS_EXPR is an operand of the instruction to be used with
3750 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
3751 bfd_reloc_code_real_type *reloc_type)
3753 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3754 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3756 /* -O2 and above is required for this optimization. */
3757 if (mips_optimize < 2)
3760 /* If we have seen .set volatile or .set nomove, don't optimize. */
3761 if (mips_opts.nomove)
3764 /* We can't swap if the previous instruction's position is fixed. */
3765 if (history[0].fixed_p)
3768 /* If the previous previous insn was in a .set noreorder, we can't
3769 swap. Actually, the MIPS assembler will swap in this situation.
3770 However, gcc configured -with-gnu-as will generate code like
3778 in which we can not swap the bne and INSN. If gcc is not configured
3779 -with-gnu-as, it does not output the .set pseudo-ops. */
3780 if (history[1].noreorder_p)
3783 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3784 This means that the previous instruction was a 4-byte one anyhow. */
3785 if (mips_opts.mips16 && history[0].fixp[0])
3788 /* If the branch is itself the target of a branch, we can not swap.
3789 We cheat on this; all we check for is whether there is a label on
3790 this instruction. If there are any branches to anything other than
3791 a label, users must use .set noreorder. */
3792 if (seg_info (now_seg)->label_list)
3795 /* If the previous instruction is in a variant frag other than this
3796 branch's one, we cannot do the swap. This does not apply to
3797 MIPS16 code, which uses variant frags for different purposes. */
3798 if (!mips_opts.mips16
3800 && history[0].frag->fr_type == rs_machine_dependent)
3803 /* We do not swap with instructions that cannot architecturally
3804 be placed in a branch delay slot, such as SYNC or ERET. We
3805 also refrain from swapping with a trap instruction, since it
3806 complicates trap handlers to have the trap instruction be in
3808 prev_pinfo = history[0].insn_mo->pinfo;
3809 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3812 /* Check for conflicts between the branch and the instructions
3813 before the candidate delay slot. */
3814 if (nops_for_insn (0, history + 1, ip) > 0)
3817 /* Check for conflicts between the swapped sequence and the
3818 target of the branch. */
3819 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3822 /* If the branch reads a register that the previous
3823 instruction sets, we can not swap. */
3824 gpr_read = gpr_read_mask (ip);
3825 prev_gpr_write = gpr_write_mask (&history[0]);
3826 if (gpr_read & prev_gpr_write)
3829 /* If the branch writes a register that the previous
3830 instruction sets, we can not swap. */
3831 gpr_write = gpr_write_mask (ip);
3832 if (gpr_write & prev_gpr_write)
3835 /* If the branch writes a register that the previous
3836 instruction reads, we can not swap. */
3837 prev_gpr_read = gpr_read_mask (&history[0]);
3838 if (gpr_write & prev_gpr_read)
3841 /* If one instruction sets a condition code and the
3842 other one uses a condition code, we can not swap. */
3843 pinfo = ip->insn_mo->pinfo;
3844 if ((pinfo & INSN_READ_COND_CODE)
3845 && (prev_pinfo & INSN_WRITE_COND_CODE))
3847 if ((pinfo & INSN_WRITE_COND_CODE)
3848 && (prev_pinfo & INSN_READ_COND_CODE))
3851 /* If the previous instruction uses the PC, we can not swap. */
3852 prev_pinfo2 = history[0].insn_mo->pinfo2;
3853 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3855 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3858 /* If the previous instruction has an incorrect size for a fixed
3859 branch delay slot in microMIPS mode, we cannot swap. */
3860 pinfo2 = ip->insn_mo->pinfo2;
3861 if (mips_opts.micromips
3862 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3863 && insn_length (history) != 2)
3865 if (mips_opts.micromips
3866 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3867 && insn_length (history) != 4)
3870 /* On R5900 short loops need to be fixed by inserting a nop in
3871 the branch delay slots.
3872 A short loop can be terminated too early. */
3873 if (mips_opts.arch == CPU_R5900
3874 /* Check if instruction has a parameter, ignore "j $31". */
3875 && (address_expr != NULL)
3876 /* Parameter must be 16 bit. */
3877 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
3878 /* Branch to same segment. */
3879 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
3880 /* Branch to same code fragment. */
3881 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
3882 /* Can only calculate branch offset if value is known. */
3883 && symbol_constant_p(address_expr->X_add_symbol)
3884 /* Check if branch is really conditional. */
3885 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
3886 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
3887 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
3890 /* Check if loop is shorter than 6 instructions including
3891 branch and delay slot. */
3892 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
3899 /* When the loop includes branches or jumps,
3900 it is not a short loop. */
3901 for (i = 0; i < (distance / 4); i++)
3903 if ((history[i].cleared_p)
3904 || delayed_branch_p(&history[i]))
3912 /* Insert nop after branch to fix short loop. */
3921 /* Decide how we should add IP to the instruction stream.
3922 ADDRESS_EXPR is an operand of the instruction to be used with
3925 static enum append_method
3926 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
3927 bfd_reloc_code_real_type *reloc_type)
3929 unsigned long pinfo;
3931 /* The relaxed version of a macro sequence must be inherently
3933 if (mips_relax.sequence == 2)
3936 /* We must not dabble with instructions in a ".set norerorder" block. */
3937 if (mips_opts.noreorder)
3940 /* Otherwise, it's our responsibility to fill branch delay slots. */
3941 if (delayed_branch_p (ip))
3943 if (!branch_likely_p (ip)
3944 && can_swap_branch_p (ip, address_expr, reloc_type))
3947 pinfo = ip->insn_mo->pinfo;
3948 if (mips_opts.mips16
3949 && ISA_SUPPORTS_MIPS16E
3950 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3951 return APPEND_ADD_COMPACT;
3953 return APPEND_ADD_WITH_NOP;
3959 /* IP is a MIPS16 instruction whose opcode we have just changed.
3960 Point IP->insn_mo to the new opcode's definition. */
3963 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3965 const struct mips_opcode *mo, *end;
3967 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3968 for (mo = ip->insn_mo; mo < end; mo++)
3969 if ((ip->insn_opcode & mo->mask) == mo->match)
3977 /* For microMIPS macros, we need to generate a local number label
3978 as the target of branches. */
3979 #define MICROMIPS_LABEL_CHAR '\037'
3980 static unsigned long micromips_target_label;
3981 static char micromips_target_name[32];
3984 micromips_label_name (void)
3986 char *p = micromips_target_name;
3987 char symbol_name_temporary[24];
3995 l = micromips_target_label;
3996 #ifdef LOCAL_LABEL_PREFIX
3997 *p++ = LOCAL_LABEL_PREFIX;
4000 *p++ = MICROMIPS_LABEL_CHAR;
4003 symbol_name_temporary[i++] = l % 10 + '0';
4008 *p++ = symbol_name_temporary[--i];
4011 return micromips_target_name;
4015 micromips_label_expr (expressionS *label_expr)
4017 label_expr->X_op = O_symbol;
4018 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4019 label_expr->X_add_number = 0;
4023 micromips_label_inc (void)
4025 micromips_target_label++;
4026 *micromips_target_name = '\0';
4030 micromips_add_label (void)
4034 s = colon (micromips_label_name ());
4035 micromips_label_inc ();
4036 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
4038 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4044 /* If assembling microMIPS code, then return the microMIPS reloc
4045 corresponding to the requested one if any. Otherwise return
4046 the reloc unchanged. */
4048 static bfd_reloc_code_real_type
4049 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4051 static const bfd_reloc_code_real_type relocs[][2] =
4053 /* Keep sorted incrementally by the left-hand key. */
4054 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4055 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4056 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4057 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4058 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4059 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4060 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4061 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4062 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4063 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4064 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4065 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4066 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4067 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4068 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4069 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4070 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4071 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4072 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4073 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4074 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4075 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4076 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4077 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4078 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4079 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4080 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4082 bfd_reloc_code_real_type r;
4085 if (!mips_opts.micromips)
4087 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4093 return relocs[i][1];
4098 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4099 Return true on success, storing the resolved value in RESULT. */
4102 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4107 case BFD_RELOC_MIPS_HIGHEST:
4108 case BFD_RELOC_MICROMIPS_HIGHEST:
4109 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4112 case BFD_RELOC_MIPS_HIGHER:
4113 case BFD_RELOC_MICROMIPS_HIGHER:
4114 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4117 case BFD_RELOC_HI16_S:
4118 case BFD_RELOC_MICROMIPS_HI16_S:
4119 case BFD_RELOC_MIPS16_HI16_S:
4120 *result = ((operand + 0x8000) >> 16) & 0xffff;
4123 case BFD_RELOC_HI16:
4124 case BFD_RELOC_MICROMIPS_HI16:
4125 case BFD_RELOC_MIPS16_HI16:
4126 *result = (operand >> 16) & 0xffff;
4129 case BFD_RELOC_LO16:
4130 case BFD_RELOC_MICROMIPS_LO16:
4131 case BFD_RELOC_MIPS16_LO16:
4132 *result = operand & 0xffff;
4135 case BFD_RELOC_UNUSED:
4144 /* Output an instruction. IP is the instruction information.
4145 ADDRESS_EXPR is an operand of the instruction to be used with
4146 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4147 a macro expansion. */
4150 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4151 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4153 unsigned long prev_pinfo2, pinfo;
4154 bfd_boolean relaxed_branch = FALSE;
4155 enum append_method method;
4156 bfd_boolean relax32;
4159 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4160 fix_loongson2f (ip);
4162 file_ase_mips16 |= mips_opts.mips16;
4163 file_ase_micromips |= mips_opts.micromips;
4165 prev_pinfo2 = history[0].insn_mo->pinfo2;
4166 pinfo = ip->insn_mo->pinfo;
4168 if (mips_opts.micromips
4170 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4171 && micromips_insn_length (ip->insn_mo) != 2)
4172 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4173 && micromips_insn_length (ip->insn_mo) != 4)))
4174 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4175 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4177 if (address_expr == NULL)
4179 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4180 && reloc_type[1] == BFD_RELOC_UNUSED
4181 && reloc_type[2] == BFD_RELOC_UNUSED
4182 && address_expr->X_op == O_constant)
4184 switch (*reloc_type)
4186 case BFD_RELOC_MIPS_JMP:
4190 shift = mips_opts.micromips ? 1 : 2;
4191 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4192 as_bad (_("jump to misaligned address (0x%lx)"),
4193 (unsigned long) address_expr->X_add_number);
4194 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4200 case BFD_RELOC_MIPS16_JMP:
4201 if ((address_expr->X_add_number & 3) != 0)
4202 as_bad (_("jump to misaligned address (0x%lx)"),
4203 (unsigned long) address_expr->X_add_number);
4205 (((address_expr->X_add_number & 0x7c0000) << 3)
4206 | ((address_expr->X_add_number & 0xf800000) >> 7)
4207 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4211 case BFD_RELOC_16_PCREL_S2:
4215 shift = mips_opts.micromips ? 1 : 2;
4216 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4217 as_bad (_("branch to misaligned address (0x%lx)"),
4218 (unsigned long) address_expr->X_add_number);
4219 if (!mips_relax_branch)
4221 if ((address_expr->X_add_number + (1 << (shift + 15)))
4222 & ~((1 << (shift + 16)) - 1))
4223 as_bad (_("branch address range overflow (0x%lx)"),
4224 (unsigned long) address_expr->X_add_number);
4225 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4235 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4238 ip->insn_opcode |= value & 0xffff;
4246 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4248 /* There are a lot of optimizations we could do that we don't.
4249 In particular, we do not, in general, reorder instructions.
4250 If you use gcc with optimization, it will reorder
4251 instructions and generally do much more optimization then we
4252 do here; repeating all that work in the assembler would only
4253 benefit hand written assembly code, and does not seem worth
4255 int nops = (mips_optimize == 0
4256 ? nops_for_insn (0, history, NULL)
4257 : nops_for_insn_or_target (0, history, ip));
4261 unsigned long old_frag_offset;
4264 old_frag = frag_now;
4265 old_frag_offset = frag_now_fix ();
4267 for (i = 0; i < nops; i++)
4268 add_fixed_insn (NOP_INSN);
4269 insert_into_history (0, nops, NOP_INSN);
4273 listing_prev_line ();
4274 /* We may be at the start of a variant frag. In case we
4275 are, make sure there is enough space for the frag
4276 after the frags created by listing_prev_line. The
4277 argument to frag_grow here must be at least as large
4278 as the argument to all other calls to frag_grow in
4279 this file. We don't have to worry about being in the
4280 middle of a variant frag, because the variants insert
4281 all needed nop instructions themselves. */
4285 mips_move_text_labels ();
4287 #ifndef NO_ECOFF_DEBUGGING
4288 if (ECOFF_DEBUGGING)
4289 ecoff_fix_loc (old_frag, old_frag_offset);
4293 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4297 /* Work out how many nops in prev_nop_frag are needed by IP,
4298 ignoring hazards generated by the first prev_nop_frag_since
4300 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4301 gas_assert (nops <= prev_nop_frag_holds);
4303 /* Enforce NOPS as a minimum. */
4304 if (nops > prev_nop_frag_required)
4305 prev_nop_frag_required = nops;
4307 if (prev_nop_frag_holds == prev_nop_frag_required)
4309 /* Settle for the current number of nops. Update the history
4310 accordingly (for the benefit of any future .set reorder code). */
4311 prev_nop_frag = NULL;
4312 insert_into_history (prev_nop_frag_since,
4313 prev_nop_frag_holds, NOP_INSN);
4317 /* Allow this instruction to replace one of the nops that was
4318 tentatively added to prev_nop_frag. */
4319 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4320 prev_nop_frag_holds--;
4321 prev_nop_frag_since++;
4325 method = get_append_method (ip, address_expr, reloc_type);
4326 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4329 /* The value passed to dwarf2_emit_insn is the distance between
4330 the beginning of the current instruction and the address that
4331 should be recorded in the debug tables. This is normally the
4334 For MIPS16/microMIPS debug info we want to use ISA-encoded
4335 addresses, so we use -1 for an address higher by one than the
4338 If the instruction produced is a branch that we will swap with
4339 the preceding instruction, then we add the displacement by which
4340 the branch will be moved backwards. This is more appropriate
4341 and for MIPS16/microMIPS code also prevents a debugger from
4342 placing a breakpoint in the middle of the branch (and corrupting
4343 code if software breakpoints are used). */
4344 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4347 relax32 = (mips_relax_branch
4348 /* Don't try branch relaxation within .set nomacro, or within
4349 .set noat if we use $at for PIC computations. If it turns
4350 out that the branch was out-of-range, we'll get an error. */
4351 && !mips_opts.warn_about_macros
4352 && (mips_opts.at || mips_pic == NO_PIC)
4353 /* Don't relax BPOSGE32/64 as they have no complementing
4355 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4357 if (!HAVE_CODE_COMPRESSION
4360 && *reloc_type == BFD_RELOC_16_PCREL_S2
4361 && delayed_branch_p (ip))
4363 relaxed_branch = TRUE;
4364 add_relaxed_insn (ip, (relaxed_branch_length
4366 uncond_branch_p (ip) ? -1
4367 : branch_likely_p (ip) ? 1
4371 uncond_branch_p (ip),
4372 branch_likely_p (ip),
4373 pinfo & INSN_WRITE_GPR_31,
4375 address_expr->X_add_symbol,
4376 address_expr->X_add_number);
4377 *reloc_type = BFD_RELOC_UNUSED;
4379 else if (mips_opts.micromips
4381 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4382 || *reloc_type > BFD_RELOC_UNUSED)
4383 && (delayed_branch_p (ip) || compact_branch_p (ip))
4384 /* Don't try branch relaxation when users specify
4385 16-bit/32-bit instructions. */
4386 && !forced_insn_length)
4388 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4389 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4390 int uncond = uncond_branch_p (ip) ? -1 : 0;
4391 int compact = compact_branch_p (ip);
4392 int al = pinfo & INSN_WRITE_GPR_31;
4395 gas_assert (address_expr != NULL);
4396 gas_assert (!mips_relax.sequence);
4398 relaxed_branch = TRUE;
4399 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4400 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4401 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4403 address_expr->X_add_symbol,
4404 address_expr->X_add_number);
4405 *reloc_type = BFD_RELOC_UNUSED;
4407 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4409 /* We need to set up a variant frag. */
4410 gas_assert (address_expr != NULL);
4411 add_relaxed_insn (ip, 4, 0,
4413 (*reloc_type - BFD_RELOC_UNUSED,
4414 forced_insn_length == 2, forced_insn_length == 4,
4415 delayed_branch_p (&history[0]),
4416 history[0].mips16_absolute_jump_p),
4417 make_expr_symbol (address_expr), 0);
4419 else if (mips_opts.mips16 && insn_length (ip) == 2)
4421 if (!delayed_branch_p (ip))
4422 /* Make sure there is enough room to swap this instruction with
4423 a following jump instruction. */
4425 add_fixed_insn (ip);
4429 if (mips_opts.mips16
4430 && mips_opts.noreorder
4431 && delayed_branch_p (&history[0]))
4432 as_warn (_("extended instruction in delay slot"));
4434 if (mips_relax.sequence)
4436 /* If we've reached the end of this frag, turn it into a variant
4437 frag and record the information for the instructions we've
4439 if (frag_room () < 4)
4440 relax_close_frag ();
4441 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4444 if (mips_relax.sequence != 2)
4446 if (mips_macro_warning.first_insn_sizes[0] == 0)
4447 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4448 mips_macro_warning.sizes[0] += insn_length (ip);
4449 mips_macro_warning.insns[0]++;
4451 if (mips_relax.sequence != 1)
4453 if (mips_macro_warning.first_insn_sizes[1] == 0)
4454 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4455 mips_macro_warning.sizes[1] += insn_length (ip);
4456 mips_macro_warning.insns[1]++;
4459 if (mips_opts.mips16)
4462 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4464 add_fixed_insn (ip);
4467 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4469 bfd_reloc_code_real_type final_type[3];
4470 reloc_howto_type *howto0;
4471 reloc_howto_type *howto;
4474 /* Perform any necessary conversion to microMIPS relocations
4475 and find out how many relocations there actually are. */
4476 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4477 final_type[i] = micromips_map_reloc (reloc_type[i]);
4479 /* In a compound relocation, it is the final (outermost)
4480 operator that determines the relocated field. */
4481 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4485 /* To reproduce this failure try assembling gas/testsuites/
4486 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4488 as_bad (_("Unsupported MIPS relocation number %d"),
4490 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4494 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4495 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4496 bfd_get_reloc_size (howto),
4498 howto0 && howto0->pc_relative,
4501 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4502 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4503 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4505 /* These relocations can have an addend that won't fit in
4506 4 octets for 64bit assembly. */
4508 && ! howto->partial_inplace
4509 && (reloc_type[0] == BFD_RELOC_16
4510 || reloc_type[0] == BFD_RELOC_32
4511 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4512 || reloc_type[0] == BFD_RELOC_GPREL16
4513 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4514 || reloc_type[0] == BFD_RELOC_GPREL32
4515 || reloc_type[0] == BFD_RELOC_64
4516 || reloc_type[0] == BFD_RELOC_CTOR
4517 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4518 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4519 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4520 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4521 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4522 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4523 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4524 || hi16_reloc_p (reloc_type[0])
4525 || lo16_reloc_p (reloc_type[0])))
4526 ip->fixp[0]->fx_no_overflow = 1;
4528 /* These relocations can have an addend that won't fit in 2 octets. */
4529 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4530 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4531 ip->fixp[0]->fx_no_overflow = 1;
4533 if (mips_relax.sequence)
4535 if (mips_relax.first_fixup == 0)
4536 mips_relax.first_fixup = ip->fixp[0];
4538 else if (reloc_needs_lo_p (*reloc_type))
4540 struct mips_hi_fixup *hi_fixup;
4542 /* Reuse the last entry if it already has a matching %lo. */
4543 hi_fixup = mips_hi_fixup_list;
4545 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4547 hi_fixup = ((struct mips_hi_fixup *)
4548 xmalloc (sizeof (struct mips_hi_fixup)));
4549 hi_fixup->next = mips_hi_fixup_list;
4550 mips_hi_fixup_list = hi_fixup;
4552 hi_fixup->fixp = ip->fixp[0];
4553 hi_fixup->seg = now_seg;
4556 /* Add fixups for the second and third relocations, if given.
4557 Note that the ABI allows the second relocation to be
4558 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4559 moment we only use RSS_UNDEF, but we could add support
4560 for the others if it ever becomes necessary. */
4561 for (i = 1; i < 3; i++)
4562 if (reloc_type[i] != BFD_RELOC_UNUSED)
4564 ip->fixp[i] = fix_new (ip->frag, ip->where,
4565 ip->fixp[0]->fx_size, NULL, 0,
4566 FALSE, final_type[i]);
4568 /* Use fx_tcbit to mark compound relocs. */
4569 ip->fixp[0]->fx_tcbit = 1;
4570 ip->fixp[i]->fx_tcbit = 1;
4575 /* Update the register mask information. */
4576 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4577 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4582 insert_into_history (0, 1, ip);
4585 case APPEND_ADD_WITH_NOP:
4587 struct mips_cl_insn *nop;
4589 insert_into_history (0, 1, ip);
4590 nop = get_delay_slot_nop (ip);
4591 add_fixed_insn (nop);
4592 insert_into_history (0, 1, nop);
4593 if (mips_relax.sequence)
4594 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4598 case APPEND_ADD_COMPACT:
4599 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4600 gas_assert (mips_opts.mips16);
4601 ip->insn_opcode |= 0x0080;
4602 find_altered_mips16_opcode (ip);
4604 insert_into_history (0, 1, ip);
4609 struct mips_cl_insn delay = history[0];
4610 if (mips_opts.mips16)
4612 know (delay.frag == ip->frag);
4613 move_insn (ip, delay.frag, delay.where);
4614 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4616 else if (relaxed_branch || delay.frag != ip->frag)
4618 /* Add the delay slot instruction to the end of the
4619 current frag and shrink the fixed part of the
4620 original frag. If the branch occupies the tail of
4621 the latter, move it backwards to cover the gap. */
4622 delay.frag->fr_fix -= branch_disp;
4623 if (delay.frag == ip->frag)
4624 move_insn (ip, ip->frag, ip->where - branch_disp);
4625 add_fixed_insn (&delay);
4629 move_insn (&delay, ip->frag,
4630 ip->where - branch_disp + insn_length (ip));
4631 move_insn (ip, history[0].frag, history[0].where);
4635 insert_into_history (0, 1, &delay);
4640 /* If we have just completed an unconditional branch, clear the history. */
4641 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4642 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4646 mips_no_prev_insn ();
4648 for (i = 0; i < ARRAY_SIZE (history); i++)
4650 history[i].cleared_p = 1;
4654 /* We need to emit a label at the end of branch-likely macros. */
4655 if (emit_branch_likely_macro)
4657 emit_branch_likely_macro = FALSE;
4658 micromips_add_label ();
4661 /* We just output an insn, so the next one doesn't have a label. */
4662 mips_clear_insn_labels ();
4665 /* Forget that there was any previous instruction or label.
4666 When BRANCH is true, the branch history is also flushed. */
4669 mips_no_prev_insn (void)
4671 prev_nop_frag = NULL;
4672 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4673 mips_clear_insn_labels ();
4676 /* This function must be called before we emit something other than
4677 instructions. It is like mips_no_prev_insn except that it inserts
4678 any NOPS that might be needed by previous instructions. */
4681 mips_emit_delays (void)
4683 if (! mips_opts.noreorder)
4685 int nops = nops_for_insn (0, history, NULL);
4689 add_fixed_insn (NOP_INSN);
4690 mips_move_text_labels ();
4693 mips_no_prev_insn ();
4696 /* Start a (possibly nested) noreorder block. */
4699 start_noreorder (void)
4701 if (mips_opts.noreorder == 0)
4706 /* None of the instructions before the .set noreorder can be moved. */
4707 for (i = 0; i < ARRAY_SIZE (history); i++)
4708 history[i].fixed_p = 1;
4710 /* Insert any nops that might be needed between the .set noreorder
4711 block and the previous instructions. We will later remove any
4712 nops that turn out not to be needed. */
4713 nops = nops_for_insn (0, history, NULL);
4716 if (mips_optimize != 0)
4718 /* Record the frag which holds the nop instructions, so
4719 that we can remove them if we don't need them. */
4720 frag_grow (nops * NOP_INSN_SIZE);
4721 prev_nop_frag = frag_now;
4722 prev_nop_frag_holds = nops;
4723 prev_nop_frag_required = 0;
4724 prev_nop_frag_since = 0;
4727 for (; nops > 0; --nops)
4728 add_fixed_insn (NOP_INSN);
4730 /* Move on to a new frag, so that it is safe to simply
4731 decrease the size of prev_nop_frag. */
4732 frag_wane (frag_now);
4734 mips_move_text_labels ();
4736 mips_mark_labels ();
4737 mips_clear_insn_labels ();
4739 mips_opts.noreorder++;
4740 mips_any_noreorder = 1;
4743 /* End a nested noreorder block. */
4746 end_noreorder (void)
4748 mips_opts.noreorder--;
4749 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4751 /* Commit to inserting prev_nop_frag_required nops and go back to
4752 handling nop insertion the .set reorder way. */
4753 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4755 insert_into_history (prev_nop_frag_since,
4756 prev_nop_frag_required, NOP_INSN);
4757 prev_nop_frag = NULL;
4761 /* Set up global variables for the start of a new macro. */
4766 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4767 memset (&mips_macro_warning.first_insn_sizes, 0,
4768 sizeof (mips_macro_warning.first_insn_sizes));
4769 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4770 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4771 && delayed_branch_p (&history[0]));
4772 switch (history[0].insn_mo->pinfo2
4773 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4775 case INSN2_BRANCH_DELAY_32BIT:
4776 mips_macro_warning.delay_slot_length = 4;
4778 case INSN2_BRANCH_DELAY_16BIT:
4779 mips_macro_warning.delay_slot_length = 2;
4782 mips_macro_warning.delay_slot_length = 0;
4785 mips_macro_warning.first_frag = NULL;
4788 /* Given that a macro is longer than one instruction or of the wrong size,
4789 return the appropriate warning for it. Return null if no warning is
4790 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4791 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4792 and RELAX_NOMACRO. */
4795 macro_warning (relax_substateT subtype)
4797 if (subtype & RELAX_DELAY_SLOT)
4798 return _("Macro instruction expanded into multiple instructions"
4799 " in a branch delay slot");
4800 else if (subtype & RELAX_NOMACRO)
4801 return _("Macro instruction expanded into multiple instructions");
4802 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4803 | RELAX_DELAY_SLOT_SIZE_SECOND))
4804 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4805 ? _("Macro instruction expanded into a wrong size instruction"
4806 " in a 16-bit branch delay slot")
4807 : _("Macro instruction expanded into a wrong size instruction"
4808 " in a 32-bit branch delay slot"));
4813 /* Finish up a macro. Emit warnings as appropriate. */
4818 /* Relaxation warning flags. */
4819 relax_substateT subtype = 0;
4821 /* Check delay slot size requirements. */
4822 if (mips_macro_warning.delay_slot_length == 2)
4823 subtype |= RELAX_DELAY_SLOT_16BIT;
4824 if (mips_macro_warning.delay_slot_length != 0)
4826 if (mips_macro_warning.delay_slot_length
4827 != mips_macro_warning.first_insn_sizes[0])
4828 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4829 if (mips_macro_warning.delay_slot_length
4830 != mips_macro_warning.first_insn_sizes[1])
4831 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4834 /* Check instruction count requirements. */
4835 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4837 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4838 subtype |= RELAX_SECOND_LONGER;
4839 if (mips_opts.warn_about_macros)
4840 subtype |= RELAX_NOMACRO;
4841 if (mips_macro_warning.delay_slot_p)
4842 subtype |= RELAX_DELAY_SLOT;
4845 /* If both alternatives fail to fill a delay slot correctly,
4846 emit the warning now. */
4847 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4848 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4853 s = subtype & (RELAX_DELAY_SLOT_16BIT
4854 | RELAX_DELAY_SLOT_SIZE_FIRST
4855 | RELAX_DELAY_SLOT_SIZE_SECOND);
4856 msg = macro_warning (s);
4858 as_warn ("%s", msg);
4862 /* If both implementations are longer than 1 instruction, then emit the
4864 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4869 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4870 msg = macro_warning (s);
4872 as_warn ("%s", msg);
4876 /* If any flags still set, then one implementation might need a warning
4877 and the other either will need one of a different kind or none at all.
4878 Pass any remaining flags over to relaxation. */
4879 if (mips_macro_warning.first_frag != NULL)
4880 mips_macro_warning.first_frag->fr_subtype |= subtype;
4883 /* Instruction operand formats used in macros that vary between
4884 standard MIPS and microMIPS code. */
4886 static const char * const brk_fmt[2] = { "c", "mF" };
4887 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4888 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4889 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4890 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4891 static const char * const mfhl_fmt[2] = { "d", "mj" };
4892 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4893 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4895 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4896 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4897 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4898 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4899 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4900 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4901 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4902 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4904 /* Read a macro's relocation codes from *ARGS and store them in *R.
4905 The first argument in *ARGS will be either the code for a single
4906 relocation or -1 followed by the three codes that make up a
4907 composite relocation. */
4910 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4914 next = va_arg (*args, int);
4916 r[0] = (bfd_reloc_code_real_type) next;
4918 for (i = 0; i < 3; i++)
4919 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4922 /* Build an instruction created by a macro expansion. This is passed
4923 a pointer to the count of instructions created so far, an
4924 expression, the name of the instruction to build, an operand format
4925 string, and corresponding arguments. */
4928 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4930 const struct mips_opcode *mo = NULL;
4931 bfd_reloc_code_real_type r[3];
4932 const struct mips_opcode *amo;
4933 struct hash_control *hash;
4934 struct mips_cl_insn insn;
4937 va_start (args, fmt);
4939 if (mips_opts.mips16)
4941 mips16_macro_build (ep, name, fmt, &args);
4946 r[0] = BFD_RELOC_UNUSED;
4947 r[1] = BFD_RELOC_UNUSED;
4948 r[2] = BFD_RELOC_UNUSED;
4949 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4950 amo = (struct mips_opcode *) hash_find (hash, name);
4952 gas_assert (strcmp (name, amo->name) == 0);
4956 /* Search until we get a match for NAME. It is assumed here that
4957 macros will never generate MDMX, MIPS-3D, or MT instructions.
4958 We try to match an instruction that fulfils the branch delay
4959 slot instruction length requirement (if any) of the previous
4960 instruction. While doing this we record the first instruction
4961 seen that matches all the other conditions and use it anyway
4962 if the requirement cannot be met; we will issue an appropriate
4963 warning later on. */
4964 if (strcmp (fmt, amo->args) == 0
4965 && amo->pinfo != INSN_MACRO
4966 && is_opcode_valid (amo)
4967 && is_size_valid (amo))
4969 if (is_delay_slot_valid (amo))
4979 gas_assert (amo->name);
4981 while (strcmp (name, amo->name) == 0);
4984 create_insn (&insn, mo);
5002 INSERT_OPERAND (mips_opts.micromips,
5003 EXTLSB, insn, va_arg (args, int));
5008 /* Note that in the macro case, these arguments are already
5009 in MSB form. (When handling the instruction in the
5010 non-macro case, these arguments are sizes from which
5011 MSB values must be calculated.) */
5012 INSERT_OPERAND (mips_opts.micromips,
5013 INSMSB, insn, va_arg (args, int));
5019 /* Note that in the macro case, these arguments are already
5020 in MSBD form. (When handling the instruction in the
5021 non-macro case, these arguments are sizes from which
5022 MSBD values must be calculated.) */
5023 INSERT_OPERAND (mips_opts.micromips,
5024 EXTMSBD, insn, va_arg (args, int));
5028 gas_assert (!mips_opts.micromips);
5029 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5038 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5042 gas_assert (mips_opts.micromips);
5046 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5050 gas_assert (!mips_opts.micromips);
5051 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5055 gas_assert (!mips_opts.micromips);
5057 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5061 if (mips_opts.micromips)
5062 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5064 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5068 gas_assert (!mips_opts.micromips);
5070 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5074 gas_assert (!mips_opts.micromips);
5076 int tmp = va_arg (args, int);
5078 INSERT_OPERAND (0, RT, insn, tmp);
5079 INSERT_OPERAND (0, RD, insn, tmp);
5085 gas_assert (!mips_opts.micromips);
5086 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5093 INSERT_OPERAND (mips_opts.micromips,
5094 SHAMT, insn, va_arg (args, int));
5098 gas_assert (!mips_opts.micromips);
5099 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5103 gas_assert (!mips_opts.micromips);
5104 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5108 gas_assert (!mips_opts.micromips);
5109 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5113 gas_assert (!mips_opts.micromips);
5114 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5121 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5126 macro_read_relocs (&args, r);
5127 gas_assert (*r == BFD_RELOC_GPREL16
5128 || *r == BFD_RELOC_MIPS_HIGHER
5129 || *r == BFD_RELOC_HI16_S
5130 || *r == BFD_RELOC_LO16
5131 || *r == BFD_RELOC_MIPS_GOT_OFST);
5135 macro_read_relocs (&args, r);
5139 macro_read_relocs (&args, r);
5140 gas_assert (ep != NULL
5141 && (ep->X_op == O_constant
5142 || (ep->X_op == O_symbol
5143 && (*r == BFD_RELOC_MIPS_HIGHEST
5144 || *r == BFD_RELOC_HI16_S
5145 || *r == BFD_RELOC_HI16
5146 || *r == BFD_RELOC_GPREL16
5147 || *r == BFD_RELOC_MIPS_GOT_HI16
5148 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5152 gas_assert (ep != NULL);
5155 * This allows macro() to pass an immediate expression for
5156 * creating short branches without creating a symbol.
5158 * We don't allow branch relaxation for these branches, as
5159 * they should only appear in ".set nomacro" anyway.
5161 if (ep->X_op == O_constant)
5163 /* For microMIPS we always use relocations for branches.
5164 So we should not resolve immediate values. */
5165 gas_assert (!mips_opts.micromips);
5167 if ((ep->X_add_number & 3) != 0)
5168 as_bad (_("branch to misaligned address (0x%lx)"),
5169 (unsigned long) ep->X_add_number);
5170 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5171 as_bad (_("branch address range overflow (0x%lx)"),
5172 (unsigned long) ep->X_add_number);
5173 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5177 *r = BFD_RELOC_16_PCREL_S2;
5181 gas_assert (ep != NULL);
5182 *r = BFD_RELOC_MIPS_JMP;
5186 gas_assert (!mips_opts.micromips);
5187 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5191 INSERT_OPERAND (mips_opts.micromips,
5192 CACHE, insn, va_arg (args, unsigned long));
5196 gas_assert (mips_opts.micromips);
5197 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5201 gas_assert (mips_opts.micromips);
5202 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5206 INSERT_OPERAND (mips_opts.micromips,
5207 3BITPOS, insn, va_arg (args, unsigned int));
5211 INSERT_OPERAND (mips_opts.micromips,
5212 OFFSET12, insn, va_arg (args, unsigned long));
5216 gas_assert (mips_opts.micromips);
5217 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5220 case 'm': /* Opcode extension character. */
5221 gas_assert (mips_opts.micromips);
5225 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5229 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5233 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5247 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5249 append_insn (&insn, ep, r, TRUE);
5253 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5256 struct mips_opcode *mo;
5257 struct mips_cl_insn insn;
5258 bfd_reloc_code_real_type r[3]
5259 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5261 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5263 gas_assert (strcmp (name, mo->name) == 0);
5265 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5268 gas_assert (mo->name);
5269 gas_assert (strcmp (name, mo->name) == 0);
5272 create_insn (&insn, mo);
5290 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5295 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5299 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5303 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5313 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5320 regno = va_arg (*args, int);
5321 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5322 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5345 gas_assert (ep != NULL);
5347 if (ep->X_op != O_constant)
5348 *r = (int) BFD_RELOC_UNUSED + c;
5349 else if (calculate_reloc (*r, ep->X_add_number, &value))
5351 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5353 *r = BFD_RELOC_UNUSED;
5359 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5366 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5368 append_insn (&insn, ep, r, TRUE);
5372 * Sign-extend 32-bit mode constants that have bit 31 set and all
5373 * higher bits unset.
5376 normalize_constant_expr (expressionS *ex)
5378 if (ex->X_op == O_constant
5379 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5380 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5385 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5386 * all higher bits unset.
5389 normalize_address_expr (expressionS *ex)
5391 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5392 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5393 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5394 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5399 * Generate a "jalr" instruction with a relocation hint to the called
5400 * function. This occurs in NewABI PIC code.
5403 macro_build_jalr (expressionS *ep, int cprestore)
5405 static const bfd_reloc_code_real_type jalr_relocs[2]
5406 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5407 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5411 if (MIPS_JALR_HINT_P (ep))
5416 if (mips_opts.micromips)
5418 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5419 if (MIPS_JALR_HINT_P (ep)
5420 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5421 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5423 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5426 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5427 if (MIPS_JALR_HINT_P (ep))
5428 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5432 * Generate a "lui" instruction.
5435 macro_build_lui (expressionS *ep, int regnum)
5437 gas_assert (! mips_opts.mips16);
5439 if (ep->X_op != O_constant)
5441 gas_assert (ep->X_op == O_symbol);
5442 /* _gp_disp is a special case, used from s_cpload.
5443 __gnu_local_gp is used if mips_no_shared. */
5444 gas_assert (mips_pic == NO_PIC
5446 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5447 || (! mips_in_shared
5448 && strcmp (S_GET_NAME (ep->X_add_symbol),
5449 "__gnu_local_gp") == 0));
5452 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5455 /* Generate a sequence of instructions to do a load or store from a constant
5456 offset off of a base register (breg) into/from a target register (treg),
5457 using AT if necessary. */
5459 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5460 int treg, int breg, int dbl)
5462 gas_assert (ep->X_op == O_constant);
5464 /* Sign-extending 32-bit constants makes their handling easier. */
5466 normalize_constant_expr (ep);
5468 /* Right now, this routine can only handle signed 32-bit constants. */
5469 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5470 as_warn (_("operand overflow"));
5472 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5474 /* Signed 16-bit offset will fit in the op. Easy! */
5475 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5479 /* 32-bit offset, need multiple instructions and AT, like:
5480 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5481 addu $tempreg,$tempreg,$breg
5482 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5483 to handle the complete offset. */
5484 macro_build_lui (ep, AT);
5485 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5486 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5489 as_bad (_("Macro used $at after \".set noat\""));
5494 * Generates code to set the $at register to true (one)
5495 * if reg is less than the immediate expression.
5498 set_at (int reg, int unsignedp)
5500 if (imm_expr.X_op == O_constant
5501 && imm_expr.X_add_number >= -0x8000
5502 && imm_expr.X_add_number < 0x8000)
5503 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5504 AT, reg, BFD_RELOC_LO16);
5507 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5508 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5512 /* Warn if an expression is not a constant. */
5515 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5517 if (ex->X_op == O_big)
5518 as_bad (_("unsupported large constant"));
5519 else if (ex->X_op != O_constant)
5520 as_bad (_("Instruction %s requires absolute expression"),
5523 if (HAVE_32BIT_GPRS)
5524 normalize_constant_expr (ex);
5527 /* Count the leading zeroes by performing a binary chop. This is a
5528 bulky bit of source, but performance is a LOT better for the
5529 majority of values than a simple loop to count the bits:
5530 for (lcnt = 0; (lcnt < 32); lcnt++)
5531 if ((v) & (1 << (31 - lcnt)))
5533 However it is not code size friendly, and the gain will drop a bit
5534 on certain cached systems.
5536 #define COUNT_TOP_ZEROES(v) \
5537 (((v) & ~0xffff) == 0 \
5538 ? ((v) & ~0xff) == 0 \
5539 ? ((v) & ~0xf) == 0 \
5540 ? ((v) & ~0x3) == 0 \
5541 ? ((v) & ~0x1) == 0 \
5546 : ((v) & ~0x7) == 0 \
5549 : ((v) & ~0x3f) == 0 \
5550 ? ((v) & ~0x1f) == 0 \
5553 : ((v) & ~0x7f) == 0 \
5556 : ((v) & ~0xfff) == 0 \
5557 ? ((v) & ~0x3ff) == 0 \
5558 ? ((v) & ~0x1ff) == 0 \
5561 : ((v) & ~0x7ff) == 0 \
5564 : ((v) & ~0x3fff) == 0 \
5565 ? ((v) & ~0x1fff) == 0 \
5568 : ((v) & ~0x7fff) == 0 \
5571 : ((v) & ~0xffffff) == 0 \
5572 ? ((v) & ~0xfffff) == 0 \
5573 ? ((v) & ~0x3ffff) == 0 \
5574 ? ((v) & ~0x1ffff) == 0 \
5577 : ((v) & ~0x7ffff) == 0 \
5580 : ((v) & ~0x3fffff) == 0 \
5581 ? ((v) & ~0x1fffff) == 0 \
5584 : ((v) & ~0x7fffff) == 0 \
5587 : ((v) & ~0xfffffff) == 0 \
5588 ? ((v) & ~0x3ffffff) == 0 \
5589 ? ((v) & ~0x1ffffff) == 0 \
5592 : ((v) & ~0x7ffffff) == 0 \
5595 : ((v) & ~0x3fffffff) == 0 \
5596 ? ((v) & ~0x1fffffff) == 0 \
5599 : ((v) & ~0x7fffffff) == 0 \
5604 * This routine generates the least number of instructions necessary to load
5605 * an absolute expression value into a register.
5608 load_register (int reg, expressionS *ep, int dbl)
5611 expressionS hi32, lo32;
5613 if (ep->X_op != O_big)
5615 gas_assert (ep->X_op == O_constant);
5617 /* Sign-extending 32-bit constants makes their handling easier. */
5619 normalize_constant_expr (ep);
5621 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5623 /* We can handle 16 bit signed values with an addiu to
5624 $zero. No need to ever use daddiu here, since $zero and
5625 the result are always correct in 32 bit mode. */
5626 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5629 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5631 /* We can handle 16 bit unsigned values with an ori to
5633 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5636 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5638 /* 32 bit values require an lui. */
5639 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5640 if ((ep->X_add_number & 0xffff) != 0)
5641 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5646 /* The value is larger than 32 bits. */
5648 if (!dbl || HAVE_32BIT_GPRS)
5652 sprintf_vma (value, ep->X_add_number);
5653 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5654 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5658 if (ep->X_op != O_big)
5661 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5662 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5663 hi32.X_add_number &= 0xffffffff;
5665 lo32.X_add_number &= 0xffffffff;
5669 gas_assert (ep->X_add_number > 2);
5670 if (ep->X_add_number == 3)
5671 generic_bignum[3] = 0;
5672 else if (ep->X_add_number > 4)
5673 as_bad (_("Number larger than 64 bits"));
5674 lo32.X_op = O_constant;
5675 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5676 hi32.X_op = O_constant;
5677 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5680 if (hi32.X_add_number == 0)
5685 unsigned long hi, lo;
5687 if (hi32.X_add_number == (offsetT) 0xffffffff)
5689 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5691 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5694 if (lo32.X_add_number & 0x80000000)
5696 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5697 if (lo32.X_add_number & 0xffff)
5698 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5703 /* Check for 16bit shifted constant. We know that hi32 is
5704 non-zero, so start the mask on the first bit of the hi32
5709 unsigned long himask, lomask;
5713 himask = 0xffff >> (32 - shift);
5714 lomask = (0xffff << shift) & 0xffffffff;
5718 himask = 0xffff << (shift - 32);
5721 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5722 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5726 tmp.X_op = O_constant;
5728 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5729 | (lo32.X_add_number >> shift));
5731 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5732 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5733 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5734 reg, reg, (shift >= 32) ? shift - 32 : shift);
5739 while (shift <= (64 - 16));
5741 /* Find the bit number of the lowest one bit, and store the
5742 shifted value in hi/lo. */
5743 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5744 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5748 while ((lo & 1) == 0)
5753 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5759 while ((hi & 1) == 0)
5768 /* Optimize if the shifted value is a (power of 2) - 1. */
5769 if ((hi == 0 && ((lo + 1) & lo) == 0)
5770 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5772 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5777 /* This instruction will set the register to be all
5779 tmp.X_op = O_constant;
5780 tmp.X_add_number = (offsetT) -1;
5781 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5785 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5786 reg, reg, (bit >= 32) ? bit - 32 : bit);
5788 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5789 reg, reg, (shift >= 32) ? shift - 32 : shift);
5794 /* Sign extend hi32 before calling load_register, because we can
5795 generally get better code when we load a sign extended value. */
5796 if ((hi32.X_add_number & 0x80000000) != 0)
5797 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5798 load_register (reg, &hi32, 0);
5801 if ((lo32.X_add_number & 0xffff0000) == 0)
5805 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5813 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5815 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5816 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5822 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5826 mid16.X_add_number >>= 16;
5827 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5828 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5831 if ((lo32.X_add_number & 0xffff) != 0)
5832 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5836 load_delay_nop (void)
5838 if (!gpr_interlocks)
5839 macro_build (NULL, "nop", "");
5842 /* Load an address into a register. */
5845 load_address (int reg, expressionS *ep, int *used_at)
5847 if (ep->X_op != O_constant
5848 && ep->X_op != O_symbol)
5850 as_bad (_("expression too complex"));
5851 ep->X_op = O_constant;
5854 if (ep->X_op == O_constant)
5856 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5860 if (mips_pic == NO_PIC)
5862 /* If this is a reference to a GP relative symbol, we want
5863 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5865 lui $reg,<sym> (BFD_RELOC_HI16_S)
5866 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5867 If we have an addend, we always use the latter form.
5869 With 64bit address space and a usable $at we want
5870 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5871 lui $at,<sym> (BFD_RELOC_HI16_S)
5872 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5873 daddiu $at,<sym> (BFD_RELOC_LO16)
5877 If $at is already in use, we use a path which is suboptimal
5878 on superscalar processors.
5879 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5880 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5882 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5884 daddiu $reg,<sym> (BFD_RELOC_LO16)
5886 For GP relative symbols in 64bit address space we can use
5887 the same sequence as in 32bit address space. */
5888 if (HAVE_64BIT_SYMBOLS)
5890 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5891 && !nopic_need_relax (ep->X_add_symbol, 1))
5893 relax_start (ep->X_add_symbol);
5894 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5895 mips_gp_register, BFD_RELOC_GPREL16);
5899 if (*used_at == 0 && mips_opts.at)
5901 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5902 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5903 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5904 BFD_RELOC_MIPS_HIGHER);
5905 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5906 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5907 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5912 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5913 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5914 BFD_RELOC_MIPS_HIGHER);
5915 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5916 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5917 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5918 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5921 if (mips_relax.sequence)
5926 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5927 && !nopic_need_relax (ep->X_add_symbol, 1))
5929 relax_start (ep->X_add_symbol);
5930 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5931 mips_gp_register, BFD_RELOC_GPREL16);
5934 macro_build_lui (ep, reg);
5935 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5936 reg, reg, BFD_RELOC_LO16);
5937 if (mips_relax.sequence)
5941 else if (!mips_big_got)
5945 /* If this is a reference to an external symbol, we want
5946 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5948 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5950 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5951 If there is a constant, it must be added in after.
5953 If we have NewABI, we want
5954 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5955 unless we're referencing a global symbol with a non-zero
5956 offset, in which case cst must be added separately. */
5959 if (ep->X_add_number)
5961 ex.X_add_number = ep->X_add_number;
5962 ep->X_add_number = 0;
5963 relax_start (ep->X_add_symbol);
5964 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5965 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5966 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5967 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5968 ex.X_op = O_constant;
5969 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5970 reg, reg, BFD_RELOC_LO16);
5971 ep->X_add_number = ex.X_add_number;
5974 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5975 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5976 if (mips_relax.sequence)
5981 ex.X_add_number = ep->X_add_number;
5982 ep->X_add_number = 0;
5983 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5984 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5986 relax_start (ep->X_add_symbol);
5988 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5992 if (ex.X_add_number != 0)
5994 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5995 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5996 ex.X_op = O_constant;
5997 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5998 reg, reg, BFD_RELOC_LO16);
6002 else if (mips_big_got)
6006 /* This is the large GOT case. If this is a reference to an
6007 external symbol, we want
6008 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6010 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6012 Otherwise, for a reference to a local symbol in old ABI, we want
6013 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6015 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6016 If there is a constant, it must be added in after.
6018 In the NewABI, for local symbols, with or without offsets, we want:
6019 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6020 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6024 ex.X_add_number = ep->X_add_number;
6025 ep->X_add_number = 0;
6026 relax_start (ep->X_add_symbol);
6027 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6028 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6029 reg, reg, mips_gp_register);
6030 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6031 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6032 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6033 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6034 else if (ex.X_add_number)
6036 ex.X_op = O_constant;
6037 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6041 ep->X_add_number = ex.X_add_number;
6043 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6044 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6045 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6046 BFD_RELOC_MIPS_GOT_OFST);
6051 ex.X_add_number = ep->X_add_number;
6052 ep->X_add_number = 0;
6053 relax_start (ep->X_add_symbol);
6054 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6055 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6056 reg, reg, mips_gp_register);
6057 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6058 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6060 if (reg_needs_delay (mips_gp_register))
6062 /* We need a nop before loading from $gp. This special
6063 check is required because the lui which starts the main
6064 instruction stream does not refer to $gp, and so will not
6065 insert the nop which may be required. */
6066 macro_build (NULL, "nop", "");
6068 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6069 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6071 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6075 if (ex.X_add_number != 0)
6077 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6078 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6079 ex.X_op = O_constant;
6080 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6088 if (!mips_opts.at && *used_at == 1)
6089 as_bad (_("Macro used $at after \".set noat\""));
6092 /* Move the contents of register SOURCE into register DEST. */
6095 move_register (int dest, int source)
6097 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6098 instruction specifically requires a 32-bit one. */
6099 if (mips_opts.micromips
6100 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6101 macro_build (NULL, "move", "mp,mj", dest, source);
6103 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6107 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6108 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6109 The two alternatives are:
6111 Global symbol Local sybmol
6112 ------------- ------------
6113 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6115 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6117 load_got_offset emits the first instruction and add_got_offset
6118 emits the second for a 16-bit offset or add_got_offset_hilo emits
6119 a sequence to add a 32-bit offset using a scratch register. */
6122 load_got_offset (int dest, expressionS *local)
6127 global.X_add_number = 0;
6129 relax_start (local->X_add_symbol);
6130 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6131 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6133 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6134 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6139 add_got_offset (int dest, expressionS *local)
6143 global.X_op = O_constant;
6144 global.X_op_symbol = NULL;
6145 global.X_add_symbol = NULL;
6146 global.X_add_number = local->X_add_number;
6148 relax_start (local->X_add_symbol);
6149 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6150 dest, dest, BFD_RELOC_LO16);
6152 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6157 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6160 int hold_mips_optimize;
6162 global.X_op = O_constant;
6163 global.X_op_symbol = NULL;
6164 global.X_add_symbol = NULL;
6165 global.X_add_number = local->X_add_number;
6167 relax_start (local->X_add_symbol);
6168 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6170 /* Set mips_optimize around the lui instruction to avoid
6171 inserting an unnecessary nop after the lw. */
6172 hold_mips_optimize = mips_optimize;
6174 macro_build_lui (&global, tmp);
6175 mips_optimize = hold_mips_optimize;
6176 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6182 /* Emit a sequence of instructions to emulate a branch likely operation.
6183 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6184 is its complementing branch with the original condition negated.
6185 CALL is set if the original branch specified the link operation.
6186 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6188 Code like this is produced in the noreorder mode:
6193 delay slot (executed only if branch taken)
6201 delay slot (executed only if branch taken)
6204 In the reorder mode the delay slot would be filled with a nop anyway,
6205 so code produced is simply:
6210 This function is used when producing code for the microMIPS ASE that
6211 does not implement branch likely instructions in hardware. */
6214 macro_build_branch_likely (const char *br, const char *brneg,
6215 int call, expressionS *ep, const char *fmt,
6216 unsigned int sreg, unsigned int treg)
6218 int noreorder = mips_opts.noreorder;
6221 gas_assert (mips_opts.micromips);
6225 micromips_label_expr (&expr1);
6226 macro_build (&expr1, brneg, fmt, sreg, treg);
6227 macro_build (NULL, "nop", "");
6228 macro_build (ep, call ? "bal" : "b", "p");
6230 /* Set to true so that append_insn adds a label. */
6231 emit_branch_likely_macro = TRUE;
6235 macro_build (ep, br, fmt, sreg, treg);
6236 macro_build (NULL, "nop", "");
6241 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6242 the condition code tested. EP specifies the branch target. */
6245 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6272 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6275 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6276 the register tested. EP specifies the branch target. */
6279 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6281 const char *brneg = NULL;
6291 br = mips_opts.micromips ? "bgez" : "bgezl";
6295 gas_assert (mips_opts.micromips);
6304 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6311 br = mips_opts.micromips ? "blez" : "blezl";
6318 br = mips_opts.micromips ? "bltz" : "bltzl";
6322 gas_assert (mips_opts.micromips);
6330 if (mips_opts.micromips && brneg)
6331 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6333 macro_build (ep, br, "s,p", sreg);
6336 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6337 TREG as the registers tested. EP specifies the branch target. */
6340 macro_build_branch_rsrt (int type, expressionS *ep,
6341 unsigned int sreg, unsigned int treg)
6343 const char *brneg = NULL;
6355 br = mips_opts.micromips ? "beq" : "beql";
6364 br = mips_opts.micromips ? "bne" : "bnel";
6370 if (mips_opts.micromips && brneg)
6371 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6373 macro_build (ep, br, "s,t,p", sreg, treg);
6378 * This routine implements the seemingly endless macro or synthesized
6379 * instructions and addressing modes in the mips assembly language. Many
6380 * of these macros are simple and are similar to each other. These could
6381 * probably be handled by some kind of table or grammar approach instead of
6382 * this verbose method. Others are not simple macros but are more like
6383 * optimizing code generation.
6384 * One interesting optimization is when several store macros appear
6385 * consecutively that would load AT with the upper half of the same address.
6386 * The ensuing load upper instructions are ommited. This implies some kind
6387 * of global optimization. We currently only optimize within a single macro.
6388 * For many of the load and store macros if the address is specified as a
6389 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6390 * first load register 'at' with zero and use it as the base register. The
6391 * mips assembler simply uses register $zero. Just one tiny optimization
6395 macro (struct mips_cl_insn *ip)
6397 unsigned int treg, sreg, dreg, breg;
6398 unsigned int tempreg;
6401 expressionS label_expr;
6420 bfd_reloc_code_real_type r;
6421 int hold_mips_optimize;
6423 gas_assert (! mips_opts.mips16);
6425 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6426 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6427 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6428 mask = ip->insn_mo->mask;
6430 label_expr.X_op = O_constant;
6431 label_expr.X_op_symbol = NULL;
6432 label_expr.X_add_symbol = NULL;
6433 label_expr.X_add_number = 0;
6435 expr1.X_op = O_constant;
6436 expr1.X_op_symbol = NULL;
6437 expr1.X_add_symbol = NULL;
6438 expr1.X_add_number = 1;
6453 if (mips_opts.micromips)
6454 micromips_label_expr (&label_expr);
6456 label_expr.X_add_number = 8;
6457 macro_build (&label_expr, "bgez", "s,p", sreg);
6459 macro_build (NULL, "nop", "");
6461 move_register (dreg, sreg);
6462 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6463 if (mips_opts.micromips)
6464 micromips_add_label ();
6481 if (!mips_opts.micromips)
6483 if (imm_expr.X_op == O_constant
6484 && imm_expr.X_add_number >= -0x200
6485 && imm_expr.X_add_number < 0x200)
6487 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6496 if (imm_expr.X_op == O_constant
6497 && imm_expr.X_add_number >= -0x8000
6498 && imm_expr.X_add_number < 0x8000)
6500 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6505 load_register (AT, &imm_expr, dbl);
6506 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6525 if (imm_expr.X_op == O_constant
6526 && imm_expr.X_add_number >= 0
6527 && imm_expr.X_add_number < 0x10000)
6529 if (mask != M_NOR_I)
6530 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6533 macro_build (&imm_expr, "ori", "t,r,i",
6534 treg, sreg, BFD_RELOC_LO16);
6535 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6541 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6542 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6546 switch (imm_expr.X_add_number)
6549 macro_build (NULL, "nop", "");
6552 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6556 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6557 (int) imm_expr.X_add_number);
6560 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6561 (unsigned long) imm_expr.X_add_number);
6570 gas_assert (mips_opts.micromips);
6571 macro_build_branch_ccl (mask, &offset_expr,
6572 EXTRACT_OPERAND (1, BCC, *ip));
6579 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6585 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6590 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6597 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6599 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6603 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6604 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6605 &offset_expr, AT, ZERO);
6615 macro_build_branch_rs (mask, &offset_expr, sreg);
6621 /* Check for > max integer. */
6622 maxnum = 0x7fffffff;
6623 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6630 if (imm_expr.X_op == O_constant
6631 && imm_expr.X_add_number >= maxnum
6632 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6635 /* Result is always false. */
6637 macro_build (NULL, "nop", "");
6639 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6642 if (imm_expr.X_op != O_constant)
6643 as_bad (_("Unsupported large constant"));
6644 ++imm_expr.X_add_number;
6648 if (mask == M_BGEL_I)
6650 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6652 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6653 &offset_expr, sreg);
6656 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6658 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6659 &offset_expr, sreg);
6662 maxnum = 0x7fffffff;
6663 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6670 maxnum = - maxnum - 1;
6671 if (imm_expr.X_op == O_constant
6672 && imm_expr.X_add_number <= maxnum
6673 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6676 /* result is always true */
6677 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6678 macro_build (&offset_expr, "b", "p");
6683 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6684 &offset_expr, AT, ZERO);
6693 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6694 &offset_expr, ZERO, treg);
6698 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6699 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6700 &offset_expr, AT, ZERO);
6709 && imm_expr.X_op == O_constant
6710 && imm_expr.X_add_number == -1))
6712 if (imm_expr.X_op != O_constant)
6713 as_bad (_("Unsupported large constant"));
6714 ++imm_expr.X_add_number;
6718 if (mask == M_BGEUL_I)
6720 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6722 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6723 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6724 &offset_expr, sreg, ZERO);
6729 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6730 &offset_expr, AT, ZERO);
6738 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6740 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6744 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6745 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6746 &offset_expr, AT, ZERO);
6754 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6755 &offset_expr, sreg, ZERO);
6761 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6762 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6763 &offset_expr, AT, ZERO);
6771 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6773 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6777 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6778 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6779 &offset_expr, AT, ZERO);
6786 maxnum = 0x7fffffff;
6787 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6794 if (imm_expr.X_op == O_constant
6795 && imm_expr.X_add_number >= maxnum
6796 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6798 if (imm_expr.X_op != O_constant)
6799 as_bad (_("Unsupported large constant"));
6800 ++imm_expr.X_add_number;
6804 if (mask == M_BLTL_I)
6806 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6807 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6808 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6809 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6814 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6815 &offset_expr, AT, ZERO);
6823 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6824 &offset_expr, sreg, ZERO);
6830 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6831 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6832 &offset_expr, AT, ZERO);
6841 && imm_expr.X_op == O_constant
6842 && imm_expr.X_add_number == -1))
6844 if (imm_expr.X_op != O_constant)
6845 as_bad (_("Unsupported large constant"));
6846 ++imm_expr.X_add_number;
6850 if (mask == M_BLTUL_I)
6852 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6854 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6855 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6856 &offset_expr, sreg, ZERO);
6861 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6862 &offset_expr, AT, ZERO);
6870 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6872 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6876 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6877 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6878 &offset_expr, AT, ZERO);
6888 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6889 &offset_expr, ZERO, treg);
6893 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6894 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6895 &offset_expr, AT, ZERO);
6901 /* Use unsigned arithmetic. */
6905 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6907 as_bad (_("Unsupported large constant"));
6912 pos = imm_expr.X_add_number;
6913 size = imm2_expr.X_add_number;
6918 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6921 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6923 as_bad (_("Improper extract size (%lu, position %lu)"),
6924 (unsigned long) size, (unsigned long) pos);
6928 if (size <= 32 && pos < 32)
6933 else if (size <= 32)
6943 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6950 /* Use unsigned arithmetic. */
6954 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6956 as_bad (_("Unsupported large constant"));
6961 pos = imm_expr.X_add_number;
6962 size = imm2_expr.X_add_number;
6967 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6970 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6972 as_bad (_("Improper insert size (%lu, position %lu)"),
6973 (unsigned long) size, (unsigned long) pos);
6977 if (pos < 32 && (pos + size - 1) < 32)
6992 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6993 (int) (pos + size - 1));
7009 as_warn (_("Divide by zero."));
7011 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7013 macro_build (NULL, "break", BRK_FMT, 7);
7020 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7021 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7025 if (mips_opts.micromips)
7026 micromips_label_expr (&label_expr);
7028 label_expr.X_add_number = 8;
7029 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7030 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7031 macro_build (NULL, "break", BRK_FMT, 7);
7032 if (mips_opts.micromips)
7033 micromips_add_label ();
7035 expr1.X_add_number = -1;
7037 load_register (AT, &expr1, dbl);
7038 if (mips_opts.micromips)
7039 micromips_label_expr (&label_expr);
7041 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7042 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7045 expr1.X_add_number = 1;
7046 load_register (AT, &expr1, dbl);
7047 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7051 expr1.X_add_number = 0x80000000;
7052 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7056 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7057 /* We want to close the noreorder block as soon as possible, so
7058 that later insns are available for delay slot filling. */
7063 if (mips_opts.micromips)
7064 micromips_label_expr (&label_expr);
7066 label_expr.X_add_number = 8;
7067 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7068 macro_build (NULL, "nop", "");
7070 /* We want to close the noreorder block as soon as possible, so
7071 that later insns are available for delay slot filling. */
7074 macro_build (NULL, "break", BRK_FMT, 6);
7076 if (mips_opts.micromips)
7077 micromips_add_label ();
7078 macro_build (NULL, s, MFHL_FMT, dreg);
7117 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7119 as_warn (_("Divide by zero."));
7121 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7123 macro_build (NULL, "break", BRK_FMT, 7);
7126 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7128 if (strcmp (s2, "mflo") == 0)
7129 move_register (dreg, sreg);
7131 move_register (dreg, ZERO);
7134 if (imm_expr.X_op == O_constant
7135 && imm_expr.X_add_number == -1
7136 && s[strlen (s) - 1] != 'u')
7138 if (strcmp (s2, "mflo") == 0)
7140 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7143 move_register (dreg, ZERO);
7148 load_register (AT, &imm_expr, dbl);
7149 macro_build (NULL, s, "z,s,t", sreg, AT);
7150 macro_build (NULL, s2, MFHL_FMT, dreg);
7172 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7173 macro_build (NULL, s, "z,s,t", sreg, treg);
7174 /* We want to close the noreorder block as soon as possible, so
7175 that later insns are available for delay slot filling. */
7180 if (mips_opts.micromips)
7181 micromips_label_expr (&label_expr);
7183 label_expr.X_add_number = 8;
7184 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7185 macro_build (NULL, s, "z,s,t", sreg, treg);
7187 /* We want to close the noreorder block as soon as possible, so
7188 that later insns are available for delay slot filling. */
7190 macro_build (NULL, "break", BRK_FMT, 7);
7191 if (mips_opts.micromips)
7192 micromips_add_label ();
7194 macro_build (NULL, s2, MFHL_FMT, dreg);
7206 /* Load the address of a symbol into a register. If breg is not
7207 zero, we then add a base register to it. */
7209 if (dbl && HAVE_32BIT_GPRS)
7210 as_warn (_("dla used to load 32-bit register"));
7212 if (!dbl && HAVE_64BIT_OBJECTS)
7213 as_warn (_("la used to load 64-bit address"));
7215 if (offset_expr.X_op == O_constant
7216 && offset_expr.X_add_number >= -0x8000
7217 && offset_expr.X_add_number < 0x8000)
7219 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7220 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7224 if (mips_opts.at && (treg == breg))
7234 if (offset_expr.X_op != O_symbol
7235 && offset_expr.X_op != O_constant)
7237 as_bad (_("Expression too complex"));
7238 offset_expr.X_op = O_constant;
7241 if (offset_expr.X_op == O_constant)
7242 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7243 else if (mips_pic == NO_PIC)
7245 /* If this is a reference to a GP relative symbol, we want
7246 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7248 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7249 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7250 If we have a constant, we need two instructions anyhow,
7251 so we may as well always use the latter form.
7253 With 64bit address space and a usable $at we want
7254 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7255 lui $at,<sym> (BFD_RELOC_HI16_S)
7256 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7257 daddiu $at,<sym> (BFD_RELOC_LO16)
7259 daddu $tempreg,$tempreg,$at
7261 If $at is already in use, we use a path which is suboptimal
7262 on superscalar processors.
7263 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7264 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7266 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7268 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7270 For GP relative symbols in 64bit address space we can use
7271 the same sequence as in 32bit address space. */
7272 if (HAVE_64BIT_SYMBOLS)
7274 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7275 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7277 relax_start (offset_expr.X_add_symbol);
7278 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7279 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7283 if (used_at == 0 && mips_opts.at)
7285 macro_build (&offset_expr, "lui", LUI_FMT,
7286 tempreg, BFD_RELOC_MIPS_HIGHEST);
7287 macro_build (&offset_expr, "lui", LUI_FMT,
7288 AT, BFD_RELOC_HI16_S);
7289 macro_build (&offset_expr, "daddiu", "t,r,j",
7290 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7291 macro_build (&offset_expr, "daddiu", "t,r,j",
7292 AT, AT, BFD_RELOC_LO16);
7293 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7294 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7299 macro_build (&offset_expr, "lui", LUI_FMT,
7300 tempreg, BFD_RELOC_MIPS_HIGHEST);
7301 macro_build (&offset_expr, "daddiu", "t,r,j",
7302 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7303 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7304 macro_build (&offset_expr, "daddiu", "t,r,j",
7305 tempreg, tempreg, BFD_RELOC_HI16_S);
7306 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7307 macro_build (&offset_expr, "daddiu", "t,r,j",
7308 tempreg, tempreg, BFD_RELOC_LO16);
7311 if (mips_relax.sequence)
7316 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7317 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7319 relax_start (offset_expr.X_add_symbol);
7320 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7321 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7324 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7325 as_bad (_("Offset too large"));
7326 macro_build_lui (&offset_expr, tempreg);
7327 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7328 tempreg, tempreg, BFD_RELOC_LO16);
7329 if (mips_relax.sequence)
7333 else if (!mips_big_got && !HAVE_NEWABI)
7335 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7337 /* If this is a reference to an external symbol, and there
7338 is no constant, we want
7339 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7340 or for lca or if tempreg is PIC_CALL_REG
7341 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7342 For a local symbol, we want
7343 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7345 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7347 If we have a small constant, and this is a reference to
7348 an external symbol, we want
7349 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7351 addiu $tempreg,$tempreg,<constant>
7352 For a local symbol, we want the same instruction
7353 sequence, but we output a BFD_RELOC_LO16 reloc on the
7356 If we have a large constant, and this is a reference to
7357 an external symbol, we want
7358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7359 lui $at,<hiconstant>
7360 addiu $at,$at,<loconstant>
7361 addu $tempreg,$tempreg,$at
7362 For a local symbol, we want the same instruction
7363 sequence, but we output a BFD_RELOC_LO16 reloc on the
7367 if (offset_expr.X_add_number == 0)
7369 if (mips_pic == SVR4_PIC
7371 && (call || tempreg == PIC_CALL_REG))
7372 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7374 relax_start (offset_expr.X_add_symbol);
7375 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7376 lw_reloc_type, mips_gp_register);
7379 /* We're going to put in an addu instruction using
7380 tempreg, so we may as well insert the nop right
7385 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7386 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7388 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7389 tempreg, tempreg, BFD_RELOC_LO16);
7391 /* FIXME: If breg == 0, and the next instruction uses
7392 $tempreg, then if this variant case is used an extra
7393 nop will be generated. */
7395 else if (offset_expr.X_add_number >= -0x8000
7396 && offset_expr.X_add_number < 0x8000)
7398 load_got_offset (tempreg, &offset_expr);
7400 add_got_offset (tempreg, &offset_expr);
7404 expr1.X_add_number = offset_expr.X_add_number;
7405 offset_expr.X_add_number =
7406 SEXT_16BIT (offset_expr.X_add_number);
7407 load_got_offset (tempreg, &offset_expr);
7408 offset_expr.X_add_number = expr1.X_add_number;
7409 /* If we are going to add in a base register, and the
7410 target register and the base register are the same,
7411 then we are using AT as a temporary register. Since
7412 we want to load the constant into AT, we add our
7413 current AT (from the global offset table) and the
7414 register into the register now, and pretend we were
7415 not using a base register. */
7419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7424 add_got_offset_hilo (tempreg, &offset_expr, AT);
7428 else if (!mips_big_got && HAVE_NEWABI)
7430 int add_breg_early = 0;
7432 /* If this is a reference to an external, and there is no
7433 constant, or local symbol (*), with or without a
7435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7436 or for lca or if tempreg is PIC_CALL_REG
7437 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7439 If we have a small constant, and this is a reference to
7440 an external symbol, we want
7441 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7442 addiu $tempreg,$tempreg,<constant>
7444 If we have a large constant, and this is a reference to
7445 an external symbol, we want
7446 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7447 lui $at,<hiconstant>
7448 addiu $at,$at,<loconstant>
7449 addu $tempreg,$tempreg,$at
7451 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7452 local symbols, even though it introduces an additional
7455 if (offset_expr.X_add_number)
7457 expr1.X_add_number = offset_expr.X_add_number;
7458 offset_expr.X_add_number = 0;
7460 relax_start (offset_expr.X_add_symbol);
7461 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7462 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7464 if (expr1.X_add_number >= -0x8000
7465 && expr1.X_add_number < 0x8000)
7467 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7468 tempreg, tempreg, BFD_RELOC_LO16);
7470 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7472 /* If we are going to add in a base register, and the
7473 target register and the base register are the same,
7474 then we are using AT as a temporary register. Since
7475 we want to load the constant into AT, we add our
7476 current AT (from the global offset table) and the
7477 register into the register now, and pretend we were
7478 not using a base register. */
7483 gas_assert (tempreg == AT);
7484 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7490 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7491 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7497 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7500 offset_expr.X_add_number = expr1.X_add_number;
7502 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7503 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7506 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7507 treg, tempreg, breg);
7513 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7515 relax_start (offset_expr.X_add_symbol);
7516 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7517 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7519 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7520 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7525 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7526 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7529 else if (mips_big_got && !HAVE_NEWABI)
7532 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7533 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7534 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7536 /* This is the large GOT case. If this is a reference to an
7537 external symbol, and there is no constant, we want
7538 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7539 addu $tempreg,$tempreg,$gp
7540 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7541 or for lca or if tempreg is PIC_CALL_REG
7542 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7543 addu $tempreg,$tempreg,$gp
7544 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7545 For a local symbol, we want
7546 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7548 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7550 If we have a small constant, and this is a reference to
7551 an external symbol, we want
7552 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7553 addu $tempreg,$tempreg,$gp
7554 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7556 addiu $tempreg,$tempreg,<constant>
7557 For a local symbol, we want
7558 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7560 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7562 If we have a large constant, and this is a reference to
7563 an external symbol, we want
7564 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7565 addu $tempreg,$tempreg,$gp
7566 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7567 lui $at,<hiconstant>
7568 addiu $at,$at,<loconstant>
7569 addu $tempreg,$tempreg,$at
7570 For a local symbol, we want
7571 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7572 lui $at,<hiconstant>
7573 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7574 addu $tempreg,$tempreg,$at
7577 expr1.X_add_number = offset_expr.X_add_number;
7578 offset_expr.X_add_number = 0;
7579 relax_start (offset_expr.X_add_symbol);
7580 gpdelay = reg_needs_delay (mips_gp_register);
7581 if (expr1.X_add_number == 0 && breg == 0
7582 && (call || tempreg == PIC_CALL_REG))
7584 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7585 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7587 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7588 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7589 tempreg, tempreg, mips_gp_register);
7590 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7591 tempreg, lw_reloc_type, tempreg);
7592 if (expr1.X_add_number == 0)
7596 /* We're going to put in an addu instruction using
7597 tempreg, so we may as well insert the nop right
7602 else if (expr1.X_add_number >= -0x8000
7603 && expr1.X_add_number < 0x8000)
7606 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7607 tempreg, tempreg, BFD_RELOC_LO16);
7611 /* If we are going to add in a base register, and the
7612 target register and the base register are the same,
7613 then we are using AT as a temporary register. Since
7614 we want to load the constant into AT, we add our
7615 current AT (from the global offset table) and the
7616 register into the register now, and pretend we were
7617 not using a base register. */
7622 gas_assert (tempreg == AT);
7624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7629 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7630 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7634 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7639 /* This is needed because this instruction uses $gp, but
7640 the first instruction on the main stream does not. */
7641 macro_build (NULL, "nop", "");
7644 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7645 local_reloc_type, mips_gp_register);
7646 if (expr1.X_add_number >= -0x8000
7647 && expr1.X_add_number < 0x8000)
7650 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7651 tempreg, tempreg, BFD_RELOC_LO16);
7652 /* FIXME: If add_number is 0, and there was no base
7653 register, the external symbol case ended with a load,
7654 so if the symbol turns out to not be external, and
7655 the next instruction uses tempreg, an unnecessary nop
7656 will be inserted. */
7662 /* We must add in the base register now, as in the
7663 external symbol case. */
7664 gas_assert (tempreg == AT);
7666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7669 /* We set breg to 0 because we have arranged to add
7670 it in in both cases. */
7674 macro_build_lui (&expr1, AT);
7675 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7676 AT, AT, BFD_RELOC_LO16);
7677 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7678 tempreg, tempreg, AT);
7683 else if (mips_big_got && HAVE_NEWABI)
7685 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7686 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7687 int add_breg_early = 0;
7689 /* This is the large GOT case. If this is a reference to an
7690 external symbol, and there is no constant, we want
7691 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7692 add $tempreg,$tempreg,$gp
7693 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7694 or for lca or if tempreg is PIC_CALL_REG
7695 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7696 add $tempreg,$tempreg,$gp
7697 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7699 If we have a small constant, and this is a reference to
7700 an external symbol, we want
7701 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7702 add $tempreg,$tempreg,$gp
7703 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7704 addi $tempreg,$tempreg,<constant>
7706 If we have a large constant, and this is a reference to
7707 an external symbol, we want
7708 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7709 addu $tempreg,$tempreg,$gp
7710 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7711 lui $at,<hiconstant>
7712 addi $at,$at,<loconstant>
7713 add $tempreg,$tempreg,$at
7715 If we have NewABI, and we know it's a local symbol, we want
7716 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7717 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7718 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7720 relax_start (offset_expr.X_add_symbol);
7722 expr1.X_add_number = offset_expr.X_add_number;
7723 offset_expr.X_add_number = 0;
7725 if (expr1.X_add_number == 0 && breg == 0
7726 && (call || tempreg == PIC_CALL_REG))
7728 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7729 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7731 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7732 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7733 tempreg, tempreg, mips_gp_register);
7734 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7735 tempreg, lw_reloc_type, tempreg);
7737 if (expr1.X_add_number == 0)
7739 else if (expr1.X_add_number >= -0x8000
7740 && expr1.X_add_number < 0x8000)
7742 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7743 tempreg, tempreg, BFD_RELOC_LO16);
7745 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7747 /* If we are going to add in a base register, and the
7748 target register and the base register are the same,
7749 then we are using AT as a temporary register. Since
7750 we want to load the constant into AT, we add our
7751 current AT (from the global offset table) and the
7752 register into the register now, and pretend we were
7753 not using a base register. */
7758 gas_assert (tempreg == AT);
7759 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7765 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7766 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7771 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7774 offset_expr.X_add_number = expr1.X_add_number;
7775 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7776 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7777 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7778 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7781 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7782 treg, tempreg, breg);
7792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7796 gas_assert (!mips_opts.micromips);
7798 unsigned long temp = (treg << 16) | (0x01);
7799 macro_build (NULL, "c2", "C", temp);
7804 gas_assert (!mips_opts.micromips);
7806 unsigned long temp = (0x02);
7807 macro_build (NULL, "c2", "C", temp);
7812 gas_assert (!mips_opts.micromips);
7814 unsigned long temp = (treg << 16) | (0x02);
7815 macro_build (NULL, "c2", "C", temp);
7820 gas_assert (!mips_opts.micromips);
7821 macro_build (NULL, "c2", "C", 3);
7825 gas_assert (!mips_opts.micromips);
7827 unsigned long temp = (treg << 16) | 0x03;
7828 macro_build (NULL, "c2", "C", temp);
7833 /* The j instruction may not be used in PIC code, since it
7834 requires an absolute address. We convert it to a b
7836 if (mips_pic == NO_PIC)
7837 macro_build (&offset_expr, "j", "a");
7839 macro_build (&offset_expr, "b", "p");
7842 /* The jal instructions must be handled as macros because when
7843 generating PIC code they expand to multi-instruction
7844 sequences. Normally they are simple instructions. */
7849 gas_assert (mips_opts.micromips);
7857 if (mips_pic == NO_PIC)
7859 s = jals ? "jalrs" : "jalr";
7860 if (mips_opts.micromips
7862 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7863 macro_build (NULL, s, "mj", sreg);
7865 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7869 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7870 && mips_cprestore_offset >= 0);
7872 if (sreg != PIC_CALL_REG)
7873 as_warn (_("MIPS PIC call to register other than $25"));
7875 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7876 ? "jalrs" : "jalr");
7877 if (mips_opts.micromips
7879 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7880 macro_build (NULL, s, "mj", sreg);
7882 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7883 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7885 if (mips_cprestore_offset < 0)
7886 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7889 if (!mips_frame_reg_valid)
7891 as_warn (_("No .frame pseudo-op used in PIC code"));
7892 /* Quiet this warning. */
7893 mips_frame_reg_valid = 1;
7895 if (!mips_cprestore_valid)
7897 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7898 /* Quiet this warning. */
7899 mips_cprestore_valid = 1;
7901 if (mips_opts.noreorder)
7902 macro_build (NULL, "nop", "");
7903 expr1.X_add_number = mips_cprestore_offset;
7904 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7907 HAVE_64BIT_ADDRESSES);
7915 gas_assert (mips_opts.micromips);
7919 if (mips_pic == NO_PIC)
7920 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7921 else if (mips_pic == SVR4_PIC)
7923 /* If this is a reference to an external symbol, and we are
7924 using a small GOT, we want
7925 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7929 lw $gp,cprestore($sp)
7930 The cprestore value is set using the .cprestore
7931 pseudo-op. If we are using a big GOT, we want
7932 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7934 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7938 lw $gp,cprestore($sp)
7939 If the symbol is not external, we want
7940 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7942 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7945 lw $gp,cprestore($sp)
7947 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7948 sequences above, minus nops, unless the symbol is local,
7949 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7955 relax_start (offset_expr.X_add_symbol);
7956 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7957 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7960 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7961 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7967 relax_start (offset_expr.X_add_symbol);
7968 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7969 BFD_RELOC_MIPS_CALL_HI16);
7970 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7971 PIC_CALL_REG, mips_gp_register);
7972 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7973 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7976 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7977 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7979 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7980 PIC_CALL_REG, PIC_CALL_REG,
7981 BFD_RELOC_MIPS_GOT_OFST);
7985 macro_build_jalr (&offset_expr, 0);
7989 relax_start (offset_expr.X_add_symbol);
7992 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7993 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8002 gpdelay = reg_needs_delay (mips_gp_register);
8003 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8004 BFD_RELOC_MIPS_CALL_HI16);
8005 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8006 PIC_CALL_REG, mips_gp_register);
8007 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8008 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8013 macro_build (NULL, "nop", "");
8015 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8016 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8019 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8020 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8022 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8024 if (mips_cprestore_offset < 0)
8025 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8028 if (!mips_frame_reg_valid)
8030 as_warn (_("No .frame pseudo-op used in PIC code"));
8031 /* Quiet this warning. */
8032 mips_frame_reg_valid = 1;
8034 if (!mips_cprestore_valid)
8036 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8037 /* Quiet this warning. */
8038 mips_cprestore_valid = 1;
8040 if (mips_opts.noreorder)
8041 macro_build (NULL, "nop", "");
8042 expr1.X_add_number = mips_cprestore_offset;
8043 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8046 HAVE_64BIT_ADDRESSES);
8050 else if (mips_pic == VXWORKS_PIC)
8051 as_bad (_("Non-PIC jump used in PIC library"));
8061 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8069 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8100 gas_assert (!mips_opts.micromips);
8103 /* Itbl support may require additional care here. */
8110 /* Itbl support may require additional care here. */
8118 off12 = mips_opts.micromips;
8119 /* Itbl support may require additional care here. */
8124 gas_assert (!mips_opts.micromips);
8127 /* Itbl support may require additional care here. */
8135 off12 = mips_opts.micromips;
8142 off12 = mips_opts.micromips;
8148 /* Itbl support may require additional care here. */
8156 off12 = mips_opts.micromips;
8157 /* Itbl support may require additional care here. */
8164 /* Itbl support may require additional care here. */
8172 off12 = mips_opts.micromips;
8179 off12 = mips_opts.micromips;
8186 off12 = mips_opts.micromips;
8193 off12 = mips_opts.micromips;
8200 off12 = mips_opts.micromips;
8205 gas_assert (mips_opts.micromips);
8214 gas_assert (mips_opts.micromips);
8223 gas_assert (mips_opts.micromips);
8231 gas_assert (mips_opts.micromips);
8238 if (breg == treg + lp)
8241 tempreg = treg + lp;
8261 gas_assert (!mips_opts.micromips);
8264 /* Itbl support may require additional care here. */
8271 /* Itbl support may require additional care here. */
8279 off12 = mips_opts.micromips;
8280 /* Itbl support may require additional care here. */
8285 gas_assert (!mips_opts.micromips);
8288 /* Itbl support may require additional care here. */
8296 off12 = mips_opts.micromips;
8303 off12 = mips_opts.micromips;
8310 off12 = mips_opts.micromips;
8317 off12 = mips_opts.micromips;
8323 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8324 off12 = mips_opts.micromips;
8330 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8331 off12 = mips_opts.micromips;
8338 /* Itbl support may require additional care here. */
8345 off12 = mips_opts.micromips;
8346 /* Itbl support may require additional care here. */
8351 gas_assert (!mips_opts.micromips);
8354 /* Itbl support may require additional care here. */
8362 off12 = mips_opts.micromips;
8369 off12 = mips_opts.micromips;
8374 gas_assert (mips_opts.micromips);
8382 gas_assert (mips_opts.micromips);
8390 gas_assert (mips_opts.micromips);
8398 gas_assert (mips_opts.micromips);
8407 if (offset_expr.X_op != O_constant
8408 && offset_expr.X_op != O_symbol)
8410 as_bad (_("Expression too complex"));
8411 offset_expr.X_op = O_constant;
8414 if (HAVE_32BIT_ADDRESSES
8415 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8419 sprintf_vma (value, offset_expr.X_add_number);
8420 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8423 /* A constant expression in PIC code can be handled just as it
8424 is in non PIC code. */
8425 if (offset_expr.X_op == O_constant)
8429 expr1.X_add_number = offset_expr.X_add_number;
8430 normalize_address_expr (&expr1);
8431 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8433 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8434 & ~(bfd_vma) 0xffff);
8437 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8439 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8440 & ~(bfd_vma) 0xfff);
8445 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8447 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8448 tempreg, tempreg, breg);
8453 if (offset_expr.X_add_number == 0)
8456 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8457 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8458 macro_build (NULL, s, fmt, treg, tempreg);
8461 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8463 macro_build (NULL, s, fmt,
8464 treg, (unsigned long) offset_expr.X_add_number, breg);
8466 else if (off12 || off0)
8468 /* A 12-bit or 0-bit offset field is too narrow to be used
8469 for a low-part relocation, so load the whole address into
8470 the auxillary register. In the case of "A(b)" addresses,
8471 we first load absolute address "A" into the register and
8472 then add base register "b". In the case of "o(b)" addresses,
8473 we simply need to add 16-bit offset "o" to base register "b", and
8474 offset_reloc already contains the relocations associated
8478 load_address (tempreg, &offset_expr, &used_at);
8480 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8481 tempreg, tempreg, breg);
8484 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8486 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8487 expr1.X_add_number = 0;
8489 macro_build (NULL, s, fmt, treg, tempreg);
8491 macro_build (NULL, s, fmt,
8492 treg, (unsigned long) expr1.X_add_number, tempreg);
8494 else if (mips_pic == NO_PIC)
8496 /* If this is a reference to a GP relative symbol, and there
8497 is no base register, we want
8498 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8499 Otherwise, if there is no base register, we want
8500 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8501 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8502 If we have a constant, we need two instructions anyhow,
8503 so we always use the latter form.
8505 If we have a base register, and this is a reference to a
8506 GP relative symbol, we want
8507 addu $tempreg,$breg,$gp
8508 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8510 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8511 addu $tempreg,$tempreg,$breg
8512 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8513 With a constant we always use the latter case.
8515 With 64bit address space and no base register and $at usable,
8517 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8518 lui $at,<sym> (BFD_RELOC_HI16_S)
8519 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8522 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8523 If we have a base register, we want
8524 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8525 lui $at,<sym> (BFD_RELOC_HI16_S)
8526 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8530 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8532 Without $at we can't generate the optimal path for superscalar
8533 processors here since this would require two temporary registers.
8534 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8535 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8537 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8539 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8540 If we have a base register, we want
8541 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8542 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8544 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8546 daddu $tempreg,$tempreg,$breg
8547 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8549 For GP relative symbols in 64bit address space we can use
8550 the same sequence as in 32bit address space. */
8551 if (HAVE_64BIT_SYMBOLS)
8553 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8554 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8556 relax_start (offset_expr.X_add_symbol);
8559 macro_build (&offset_expr, s, fmt, treg,
8560 BFD_RELOC_GPREL16, mips_gp_register);
8564 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8565 tempreg, breg, mips_gp_register);
8566 macro_build (&offset_expr, s, fmt, treg,
8567 BFD_RELOC_GPREL16, tempreg);
8572 if (used_at == 0 && mips_opts.at)
8574 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8575 BFD_RELOC_MIPS_HIGHEST);
8576 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8578 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8579 tempreg, BFD_RELOC_MIPS_HIGHER);
8581 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8582 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8583 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8584 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8590 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8591 BFD_RELOC_MIPS_HIGHEST);
8592 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8593 tempreg, BFD_RELOC_MIPS_HIGHER);
8594 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8595 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8596 tempreg, BFD_RELOC_HI16_S);
8597 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8599 macro_build (NULL, "daddu", "d,v,t",
8600 tempreg, tempreg, breg);
8601 macro_build (&offset_expr, s, fmt, treg,
8602 BFD_RELOC_LO16, tempreg);
8605 if (mips_relax.sequence)
8612 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8613 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8615 relax_start (offset_expr.X_add_symbol);
8616 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8620 macro_build_lui (&offset_expr, tempreg);
8621 macro_build (&offset_expr, s, fmt, treg,
8622 BFD_RELOC_LO16, tempreg);
8623 if (mips_relax.sequence)
8628 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8629 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8631 relax_start (offset_expr.X_add_symbol);
8632 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8633 tempreg, breg, mips_gp_register);
8634 macro_build (&offset_expr, s, fmt, treg,
8635 BFD_RELOC_GPREL16, tempreg);
8638 macro_build_lui (&offset_expr, tempreg);
8639 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8640 tempreg, tempreg, breg);
8641 macro_build (&offset_expr, s, fmt, treg,
8642 BFD_RELOC_LO16, tempreg);
8643 if (mips_relax.sequence)
8647 else if (!mips_big_got)
8649 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8651 /* If this is a reference to an external symbol, we want
8652 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8654 <op> $treg,0($tempreg)
8656 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8658 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8659 <op> $treg,0($tempreg)
8662 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8663 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8665 If there is a base register, we add it to $tempreg before
8666 the <op>. If there is a constant, we stick it in the
8667 <op> instruction. We don't handle constants larger than
8668 16 bits, because we have no way to load the upper 16 bits
8669 (actually, we could handle them for the subset of cases
8670 in which we are not using $at). */
8671 gas_assert (offset_expr.X_op == O_symbol);
8674 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8675 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8677 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8678 tempreg, tempreg, breg);
8679 macro_build (&offset_expr, s, fmt, treg,
8680 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8683 expr1.X_add_number = offset_expr.X_add_number;
8684 offset_expr.X_add_number = 0;
8685 if (expr1.X_add_number < -0x8000
8686 || expr1.X_add_number >= 0x8000)
8687 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8688 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8689 lw_reloc_type, mips_gp_register);
8691 relax_start (offset_expr.X_add_symbol);
8693 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8694 tempreg, BFD_RELOC_LO16);
8697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8698 tempreg, tempreg, breg);
8699 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8701 else if (mips_big_got && !HAVE_NEWABI)
8705 /* If this is a reference to an external symbol, we want
8706 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8707 addu $tempreg,$tempreg,$gp
8708 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8709 <op> $treg,0($tempreg)
8711 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8713 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8714 <op> $treg,0($tempreg)
8715 If there is a base register, we add it to $tempreg before
8716 the <op>. If there is a constant, we stick it in the
8717 <op> instruction. We don't handle constants larger than
8718 16 bits, because we have no way to load the upper 16 bits
8719 (actually, we could handle them for the subset of cases
8720 in which we are not using $at). */
8721 gas_assert (offset_expr.X_op == O_symbol);
8722 expr1.X_add_number = offset_expr.X_add_number;
8723 offset_expr.X_add_number = 0;
8724 if (expr1.X_add_number < -0x8000
8725 || expr1.X_add_number >= 0x8000)
8726 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8727 gpdelay = reg_needs_delay (mips_gp_register);
8728 relax_start (offset_expr.X_add_symbol);
8729 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8730 BFD_RELOC_MIPS_GOT_HI16);
8731 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8733 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8734 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8737 macro_build (NULL, "nop", "");
8738 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8739 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8741 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8742 tempreg, BFD_RELOC_LO16);
8746 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8747 tempreg, tempreg, breg);
8748 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8750 else if (mips_big_got && HAVE_NEWABI)
8752 /* If this is a reference to an external symbol, we want
8753 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8754 add $tempreg,$tempreg,$gp
8755 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8756 <op> $treg,<ofst>($tempreg)
8757 Otherwise, for local symbols, we want:
8758 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8759 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8760 gas_assert (offset_expr.X_op == O_symbol);
8761 expr1.X_add_number = offset_expr.X_add_number;
8762 offset_expr.X_add_number = 0;
8763 if (expr1.X_add_number < -0x8000
8764 || expr1.X_add_number >= 0x8000)
8765 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8766 relax_start (offset_expr.X_add_symbol);
8767 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8768 BFD_RELOC_MIPS_GOT_HI16);
8769 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8771 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8772 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8774 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8775 tempreg, tempreg, breg);
8776 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8779 offset_expr.X_add_number = expr1.X_add_number;
8780 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8781 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8783 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8784 tempreg, tempreg, breg);
8785 macro_build (&offset_expr, s, fmt, treg,
8786 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8796 load_register (treg, &imm_expr, 0);
8800 load_register (treg, &imm_expr, 1);
8804 if (imm_expr.X_op == O_constant)
8807 load_register (AT, &imm_expr, 0);
8808 macro_build (NULL, "mtc1", "t,G", AT, treg);
8813 gas_assert (offset_expr.X_op == O_symbol
8814 && strcmp (segment_name (S_GET_SEGMENT
8815 (offset_expr.X_add_symbol)),
8817 && offset_expr.X_add_number == 0);
8818 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8819 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8824 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8825 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8826 order 32 bits of the value and the low order 32 bits are either
8827 zero or in OFFSET_EXPR. */
8828 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8830 if (HAVE_64BIT_GPRS)
8831 load_register (treg, &imm_expr, 1);
8836 if (target_big_endian)
8848 load_register (hreg, &imm_expr, 0);
8851 if (offset_expr.X_op == O_absent)
8852 move_register (lreg, 0);
8855 gas_assert (offset_expr.X_op == O_constant);
8856 load_register (lreg, &offset_expr, 0);
8863 /* We know that sym is in the .rdata section. First we get the
8864 upper 16 bits of the address. */
8865 if (mips_pic == NO_PIC)
8867 macro_build_lui (&offset_expr, AT);
8872 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8873 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8877 /* Now we load the register(s). */
8878 if (HAVE_64BIT_GPRS)
8881 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8886 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8889 /* FIXME: How in the world do we deal with the possible
8891 offset_expr.X_add_number += 4;
8892 macro_build (&offset_expr, "lw", "t,o(b)",
8893 treg + 1, BFD_RELOC_LO16, AT);
8899 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8900 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8901 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8902 the value and the low order 32 bits are either zero or in
8904 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8907 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8908 if (HAVE_64BIT_FPRS)
8910 gas_assert (HAVE_64BIT_GPRS);
8911 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8915 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8916 if (offset_expr.X_op == O_absent)
8917 macro_build (NULL, "mtc1", "t,G", 0, treg);
8920 gas_assert (offset_expr.X_op == O_constant);
8921 load_register (AT, &offset_expr, 0);
8922 macro_build (NULL, "mtc1", "t,G", AT, treg);
8928 gas_assert (offset_expr.X_op == O_symbol
8929 && offset_expr.X_add_number == 0);
8930 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8931 if (strcmp (s, ".lit8") == 0)
8933 if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8934 && (mips_opts.arch != CPU_R5900))
8936 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8937 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8940 breg = mips_gp_register;
8941 r = BFD_RELOC_MIPS_LITERAL;
8946 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8948 if (mips_pic != NO_PIC)
8949 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8950 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8953 /* FIXME: This won't work for a 64 bit address. */
8954 macro_build_lui (&offset_expr, AT);
8957 if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8958 && (mips_opts.arch != CPU_R5900))
8960 macro_build (&offset_expr, "ldc1", "T,o(b)",
8961 treg, BFD_RELOC_LO16, AT);
8970 /* Even on a big endian machine $fn comes before $fn+1. We have
8971 to adjust when loading from memory. */
8974 gas_assert (!mips_opts.micromips);
8975 gas_assert ((mips_opts.isa == ISA_MIPS1)
8976 || (mips_opts.arch == CPU_R5900));
8977 macro_build (&offset_expr, "lwc1", "T,o(b)",
8978 target_big_endian ? treg + 1 : treg, r, breg);
8979 /* FIXME: A possible overflow which I don't know how to deal
8981 offset_expr.X_add_number += 4;
8982 macro_build (&offset_expr, "lwc1", "T,o(b)",
8983 target_big_endian ? treg : treg + 1, r, breg);
8987 gas_assert (!mips_opts.micromips);
8988 gas_assert (mips_opts.isa == ISA_MIPS1);
8989 /* Even on a big endian machine $fn comes before $fn+1. We have
8990 to adjust when storing to memory. */
8991 macro_build (&offset_expr, "swc1", "T,o(b)",
8992 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8993 offset_expr.X_add_number += 4;
8994 macro_build (&offset_expr, "swc1", "T,o(b)",
8995 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8999 gas_assert (!mips_opts.micromips);
9001 * The MIPS assembler seems to check for X_add_number not
9002 * being double aligned and generating:
9005 * addiu at,at,%lo(foo+1)
9008 * But, the resulting address is the same after relocation so why
9009 * generate the extra instruction?
9011 /* Itbl support may require additional care here. */
9014 if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
9023 gas_assert (!mips_opts.micromips);
9024 /* Itbl support may require additional care here. */
9027 if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
9047 if (HAVE_64BIT_GPRS)
9057 if (HAVE_64BIT_GPRS)
9065 if (offset_expr.X_op != O_symbol
9066 && offset_expr.X_op != O_constant)
9068 as_bad (_("Expression too complex"));
9069 offset_expr.X_op = O_constant;
9072 if (HAVE_32BIT_ADDRESSES
9073 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9077 sprintf_vma (value, offset_expr.X_add_number);
9078 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9081 /* Even on a big endian machine $fn comes before $fn+1. We have
9082 to adjust when loading from memory. We set coproc if we must
9083 load $fn+1 first. */
9084 /* Itbl support may require additional care here. */
9085 if (!target_big_endian)
9088 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9090 /* If this is a reference to a GP relative symbol, we want
9091 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9092 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9093 If we have a base register, we use this
9095 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9096 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9097 If this is not a GP relative symbol, we want
9098 lui $at,<sym> (BFD_RELOC_HI16_S)
9099 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9100 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9101 If there is a base register, we add it to $at after the
9102 lui instruction. If there is a constant, we always use
9104 if (offset_expr.X_op == O_symbol
9105 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9106 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9108 relax_start (offset_expr.X_add_symbol);
9111 tempreg = mips_gp_register;
9115 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9116 AT, breg, mips_gp_register);
9121 /* Itbl support may require additional care here. */
9122 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9123 BFD_RELOC_GPREL16, tempreg);
9124 offset_expr.X_add_number += 4;
9126 /* Set mips_optimize to 2 to avoid inserting an
9128 hold_mips_optimize = mips_optimize;
9130 /* Itbl support may require additional care here. */
9131 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9132 BFD_RELOC_GPREL16, tempreg);
9133 mips_optimize = hold_mips_optimize;
9137 offset_expr.X_add_number -= 4;
9140 macro_build_lui (&offset_expr, AT);
9142 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9143 /* Itbl support may require additional care here. */
9144 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9145 BFD_RELOC_LO16, AT);
9146 /* FIXME: How do we handle overflow here? */
9147 offset_expr.X_add_number += 4;
9148 /* Itbl support may require additional care here. */
9149 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9150 BFD_RELOC_LO16, AT);
9151 if (mips_relax.sequence)
9154 else if (!mips_big_got)
9156 /* If this is a reference to an external symbol, we want
9157 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9162 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9164 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9165 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9166 If there is a base register we add it to $at before the
9167 lwc1 instructions. If there is a constant we include it
9168 in the lwc1 instructions. */
9170 expr1.X_add_number = offset_expr.X_add_number;
9171 if (expr1.X_add_number < -0x8000
9172 || expr1.X_add_number >= 0x8000 - 4)
9173 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9174 load_got_offset (AT, &offset_expr);
9177 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9179 /* Set mips_optimize to 2 to avoid inserting an undesired
9181 hold_mips_optimize = mips_optimize;
9184 /* Itbl support may require additional care here. */
9185 relax_start (offset_expr.X_add_symbol);
9186 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9187 BFD_RELOC_LO16, AT);
9188 expr1.X_add_number += 4;
9189 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9190 BFD_RELOC_LO16, AT);
9192 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9193 BFD_RELOC_LO16, AT);
9194 offset_expr.X_add_number += 4;
9195 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9196 BFD_RELOC_LO16, AT);
9199 mips_optimize = hold_mips_optimize;
9201 else if (mips_big_got)
9205 /* If this is a reference to an external symbol, we want
9206 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9208 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9213 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9215 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9216 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9217 If there is a base register we add it to $at before the
9218 lwc1 instructions. If there is a constant we include it
9219 in the lwc1 instructions. */
9221 expr1.X_add_number = offset_expr.X_add_number;
9222 offset_expr.X_add_number = 0;
9223 if (expr1.X_add_number < -0x8000
9224 || expr1.X_add_number >= 0x8000 - 4)
9225 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9226 gpdelay = reg_needs_delay (mips_gp_register);
9227 relax_start (offset_expr.X_add_symbol);
9228 macro_build (&offset_expr, "lui", LUI_FMT,
9229 AT, BFD_RELOC_MIPS_GOT_HI16);
9230 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9231 AT, AT, mips_gp_register);
9232 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9233 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9236 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9237 /* Itbl support may require additional care here. */
9238 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9239 BFD_RELOC_LO16, AT);
9240 expr1.X_add_number += 4;
9242 /* Set mips_optimize to 2 to avoid inserting an undesired
9244 hold_mips_optimize = mips_optimize;
9246 /* Itbl support may require additional care here. */
9247 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9248 BFD_RELOC_LO16, AT);
9249 mips_optimize = hold_mips_optimize;
9250 expr1.X_add_number -= 4;
9253 offset_expr.X_add_number = expr1.X_add_number;
9255 macro_build (NULL, "nop", "");
9256 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9257 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9260 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9261 /* Itbl support may require additional care here. */
9262 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9263 BFD_RELOC_LO16, AT);
9264 offset_expr.X_add_number += 4;
9266 /* Set mips_optimize to 2 to avoid inserting an undesired
9268 hold_mips_optimize = mips_optimize;
9270 /* Itbl support may require additional care here. */
9271 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9272 BFD_RELOC_LO16, AT);
9273 mips_optimize = hold_mips_optimize;
9282 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9285 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9287 macro_build (&offset_expr, s, "t,o(b)", treg,
9288 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9290 if (!HAVE_64BIT_GPRS)
9292 offset_expr.X_add_number += 4;
9293 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9294 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9315 /* New code added to support COPZ instructions.
9316 This code builds table entries out of the macros in mip_opcodes.
9317 R4000 uses interlocks to handle coproc delays.
9318 Other chips (like the R3000) require nops to be inserted for delays.
9320 FIXME: Currently, we require that the user handle delays.
9321 In order to fill delay slots for non-interlocked chips,
9322 we must have a way to specify delays based on the coprocessor.
9323 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9324 What are the side-effects of the cop instruction?
9325 What cache support might we have and what are its effects?
9326 Both coprocessor & memory require delays. how long???
9327 What registers are read/set/modified?
9329 If an itbl is provided to interpret cop instructions,
9330 this knowledge can be encoded in the itbl spec. */
9344 gas_assert (!mips_opts.micromips);
9345 /* For now we just do C (same as Cz). The parameter will be
9346 stored in insn_opcode by mips_ip. */
9347 macro_build (NULL, s, "C", ip->insn_opcode);
9351 move_register (dreg, sreg);
9357 if (mips_opts.arch == CPU_R5900)
9359 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9363 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9364 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9371 /* The MIPS assembler some times generates shifts and adds. I'm
9372 not trying to be that fancy. GCC should do this for us
9375 load_register (AT, &imm_expr, dbl);
9376 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9377 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9393 load_register (AT, &imm_expr, dbl);
9394 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9395 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9396 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9397 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9399 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9402 if (mips_opts.micromips)
9403 micromips_label_expr (&label_expr);
9405 label_expr.X_add_number = 8;
9406 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9407 macro_build (NULL, "nop", "");
9408 macro_build (NULL, "break", BRK_FMT, 6);
9409 if (mips_opts.micromips)
9410 micromips_add_label ();
9413 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9429 load_register (AT, &imm_expr, dbl);
9430 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9431 sreg, imm ? AT : treg);
9432 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9433 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9435 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9438 if (mips_opts.micromips)
9439 micromips_label_expr (&label_expr);
9441 label_expr.X_add_number = 8;
9442 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9443 macro_build (NULL, "nop", "");
9444 macro_build (NULL, "break", BRK_FMT, 6);
9445 if (mips_opts.micromips)
9446 micromips_add_label ();
9452 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9463 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9464 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9468 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9469 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9470 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9471 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9475 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9486 macro_build (NULL, "negu", "d,w", tempreg, treg);
9487 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9491 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9492 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9493 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9494 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9503 if (imm_expr.X_op != O_constant)
9504 as_bad (_("Improper rotate count"));
9505 rot = imm_expr.X_add_number & 0x3f;
9506 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9508 rot = (64 - rot) & 0x3f;
9510 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9512 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9517 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9520 l = (rot < 0x20) ? "dsll" : "dsll32";
9521 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9524 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9525 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9526 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9534 if (imm_expr.X_op != O_constant)
9535 as_bad (_("Improper rotate count"));
9536 rot = imm_expr.X_add_number & 0x1f;
9537 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9539 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9544 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9548 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9549 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9550 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9555 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9557 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9561 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9562 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9563 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9564 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9568 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9570 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9574 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9575 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9576 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9577 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9586 if (imm_expr.X_op != O_constant)
9587 as_bad (_("Improper rotate count"));
9588 rot = imm_expr.X_add_number & 0x3f;
9589 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9592 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9594 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9599 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9602 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9603 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9606 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9607 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9608 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9616 if (imm_expr.X_op != O_constant)
9617 as_bad (_("Improper rotate count"));
9618 rot = imm_expr.X_add_number & 0x1f;
9619 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9621 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9626 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9630 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9631 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9632 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9638 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9640 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9643 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9644 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9649 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9651 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9656 as_warn (_("Instruction %s: result is always false"),
9658 move_register (dreg, 0);
9661 if (CPU_HAS_SEQ (mips_opts.arch)
9662 && -512 <= imm_expr.X_add_number
9663 && imm_expr.X_add_number < 512)
9665 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9666 (int) imm_expr.X_add_number);
9669 if (imm_expr.X_op == O_constant
9670 && imm_expr.X_add_number >= 0
9671 && imm_expr.X_add_number < 0x10000)
9673 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9675 else if (imm_expr.X_op == O_constant
9676 && imm_expr.X_add_number > -0x8000
9677 && imm_expr.X_add_number < 0)
9679 imm_expr.X_add_number = -imm_expr.X_add_number;
9680 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9681 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9683 else if (CPU_HAS_SEQ (mips_opts.arch))
9686 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9687 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9692 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9693 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9696 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9699 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9705 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9706 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9709 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9711 if (imm_expr.X_op == O_constant
9712 && imm_expr.X_add_number >= -0x8000
9713 && imm_expr.X_add_number < 0x8000)
9715 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9716 dreg, sreg, BFD_RELOC_LO16);
9720 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9721 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9725 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9728 case M_SGT: /* sreg > treg <==> treg < sreg */
9734 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9737 case M_SGT_I: /* sreg > I <==> I < sreg */
9744 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9745 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9748 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9754 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9755 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9758 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9765 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9766 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9767 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9771 if (imm_expr.X_op == O_constant
9772 && imm_expr.X_add_number >= -0x8000
9773 && imm_expr.X_add_number < 0x8000)
9775 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9779 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9780 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9784 if (imm_expr.X_op == O_constant
9785 && imm_expr.X_add_number >= -0x8000
9786 && imm_expr.X_add_number < 0x8000)
9788 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9793 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9794 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9799 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9801 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9804 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9805 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9810 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9812 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9817 as_warn (_("Instruction %s: result is always true"),
9819 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9820 dreg, 0, BFD_RELOC_LO16);
9823 if (CPU_HAS_SEQ (mips_opts.arch)
9824 && -512 <= imm_expr.X_add_number
9825 && imm_expr.X_add_number < 512)
9827 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9828 (int) imm_expr.X_add_number);
9831 if (imm_expr.X_op == O_constant
9832 && imm_expr.X_add_number >= 0
9833 && imm_expr.X_add_number < 0x10000)
9835 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9837 else if (imm_expr.X_op == O_constant
9838 && imm_expr.X_add_number > -0x8000
9839 && imm_expr.X_add_number < 0)
9841 imm_expr.X_add_number = -imm_expr.X_add_number;
9842 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9843 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9845 else if (CPU_HAS_SEQ (mips_opts.arch))
9848 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9849 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9854 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9855 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9858 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9873 if (!mips_opts.micromips)
9875 if (imm_expr.X_op == O_constant
9876 && imm_expr.X_add_number > -0x200
9877 && imm_expr.X_add_number <= 0x200)
9879 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9888 if (imm_expr.X_op == O_constant
9889 && imm_expr.X_add_number > -0x8000
9890 && imm_expr.X_add_number <= 0x8000)
9892 imm_expr.X_add_number = -imm_expr.X_add_number;
9893 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9898 load_register (AT, &imm_expr, dbl);
9899 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9921 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9922 macro_build (NULL, s, "s,t", sreg, AT);
9927 gas_assert (!mips_opts.micromips);
9928 gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900));
9930 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9931 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9934 * Is the double cfc1 instruction a bug in the mips assembler;
9935 * or is there a reason for it?
9938 macro_build (NULL, "cfc1", "t,G", treg, RA);
9939 macro_build (NULL, "cfc1", "t,G", treg, RA);
9940 macro_build (NULL, "nop", "");
9941 expr1.X_add_number = 3;
9942 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9943 expr1.X_add_number = 2;
9944 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9945 macro_build (NULL, "ctc1", "t,G", AT, RA);
9946 macro_build (NULL, "nop", "");
9947 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9949 macro_build (NULL, "ctc1", "t,G", treg, RA);
9950 macro_build (NULL, "nop", "");
9973 off12 = mips_opts.micromips;
9981 off12 = mips_opts.micromips;
9997 off12 = mips_opts.micromips;
10006 off12 = mips_opts.micromips;
10011 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10012 as_bad (_("Operand overflow"));
10015 expr1.X_add_number = 0;
10020 load_address (tempreg, ep, &used_at);
10022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10023 tempreg, tempreg, breg);
10029 && (offset_expr.X_op != O_constant
10030 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10031 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10035 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10036 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10041 else if (!ust && treg == breg)
10052 if (!target_big_endian)
10053 ep->X_add_number += off;
10055 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10057 macro_build (NULL, s, "t,~(b)",
10058 tempreg, (unsigned long) ep->X_add_number, breg);
10060 if (!target_big_endian)
10061 ep->X_add_number -= off;
10063 ep->X_add_number += off;
10065 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10067 macro_build (NULL, s2, "t,~(b)",
10068 tempreg, (unsigned long) ep->X_add_number, breg);
10070 /* If necessary, move the result in tempreg to the final destination. */
10071 if (!ust && treg != tempreg)
10073 /* Protect second load's delay slot. */
10075 move_register (treg, tempreg);
10081 if (target_big_endian == ust)
10082 ep->X_add_number += off;
10083 tempreg = ust || ab ? treg : AT;
10084 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10086 /* For halfword transfers we need a temporary register to shuffle
10087 bytes. Unfortunately for M_USH_A we have none available before
10088 the next store as AT holds the base address. We deal with this
10089 case by clobbering TREG and then restoring it as with ULH. */
10090 tempreg = ust == ab ? treg : AT;
10092 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10094 if (target_big_endian == ust)
10095 ep->X_add_number -= off;
10097 ep->X_add_number += off;
10098 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10100 /* For M_USH_A re-retrieve the LSB. */
10103 if (target_big_endian)
10104 ep->X_add_number += off;
10106 ep->X_add_number -= off;
10107 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10109 /* For ULH and M_USH_A OR the LSB in. */
10112 tempreg = !ab ? AT : treg;
10113 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10114 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10119 /* FIXME: Check if this is one of the itbl macros, since they
10120 are added dynamically. */
10121 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10124 if (!mips_opts.at && used_at)
10125 as_bad (_("Macro used $at after \".set noat\""));
10128 /* Implement macros in mips16 mode. */
10131 mips16_macro (struct mips_cl_insn *ip)
10134 int xreg, yreg, zreg, tmp;
10137 const char *s, *s2, *s3;
10139 mask = ip->insn_mo->mask;
10141 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10142 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10143 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10145 expr1.X_op = O_constant;
10146 expr1.X_op_symbol = NULL;
10147 expr1.X_add_symbol = NULL;
10148 expr1.X_add_number = 1;
10167 start_noreorder ();
10168 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10169 expr1.X_add_number = 2;
10170 macro_build (&expr1, "bnez", "x,p", yreg);
10171 macro_build (NULL, "break", "6", 7);
10173 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10174 since that causes an overflow. We should do that as well,
10175 but I don't see how to do the comparisons without a temporary
10178 macro_build (NULL, s, "x", zreg);
10197 start_noreorder ();
10198 macro_build (NULL, s, "0,x,y", xreg, yreg);
10199 expr1.X_add_number = 2;
10200 macro_build (&expr1, "bnez", "x,p", yreg);
10201 macro_build (NULL, "break", "6", 7);
10203 macro_build (NULL, s2, "x", zreg);
10209 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10210 macro_build (NULL, "mflo", "x", zreg);
10218 if (imm_expr.X_op != O_constant)
10219 as_bad (_("Unsupported large constant"));
10220 imm_expr.X_add_number = -imm_expr.X_add_number;
10221 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10225 if (imm_expr.X_op != O_constant)
10226 as_bad (_("Unsupported large constant"));
10227 imm_expr.X_add_number = -imm_expr.X_add_number;
10228 macro_build (&imm_expr, "addiu", "x,k", xreg);
10232 if (imm_expr.X_op != O_constant)
10233 as_bad (_("Unsupported large constant"));
10234 imm_expr.X_add_number = -imm_expr.X_add_number;
10235 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10257 goto do_reverse_branch;
10261 goto do_reverse_branch;
10273 goto do_reverse_branch;
10284 macro_build (NULL, s, "x,y", xreg, yreg);
10285 macro_build (&offset_expr, s2, "p");
10312 goto do_addone_branch_i;
10317 goto do_addone_branch_i;
10332 goto do_addone_branch_i;
10338 do_addone_branch_i:
10339 if (imm_expr.X_op != O_constant)
10340 as_bad (_("Unsupported large constant"));
10341 ++imm_expr.X_add_number;
10344 macro_build (&imm_expr, s, s3, xreg);
10345 macro_build (&offset_expr, s2, "p");
10349 expr1.X_add_number = 0;
10350 macro_build (&expr1, "slti", "x,8", yreg);
10352 move_register (xreg, yreg);
10353 expr1.X_add_number = 2;
10354 macro_build (&expr1, "bteqz", "p");
10355 macro_build (NULL, "neg", "x,w", xreg, xreg);
10359 /* For consistency checking, verify that all bits are specified either
10360 by the match/mask part of the instruction definition, or by the
10363 validate_mips_insn (const struct mips_opcode *opc)
10365 const char *p = opc->args;
10367 unsigned long used_bits = opc->mask;
10369 if ((used_bits & opc->match) != opc->match)
10371 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10372 opc->name, opc->args);
10375 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10385 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10386 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10387 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10388 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10389 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10390 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10391 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10392 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10393 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10394 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10395 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10396 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10397 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10399 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10400 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10401 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10402 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10403 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10404 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10405 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10406 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10407 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10408 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10409 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10410 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10411 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10412 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10413 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10416 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10417 c, opc->name, opc->args);
10421 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10422 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10424 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10425 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10426 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10427 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10429 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10430 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10432 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10433 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10435 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10436 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10437 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10438 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10439 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10440 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10441 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10442 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10443 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10444 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10445 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10446 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10447 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10448 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10449 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10450 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10451 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10453 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10454 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10455 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10456 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10458 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10459 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10460 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10461 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10462 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10463 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10464 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10465 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10466 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10469 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10470 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10471 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10472 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10473 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10476 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10477 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10478 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10479 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10480 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10481 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10482 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10483 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10484 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10485 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10486 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10487 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10488 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10489 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10490 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10491 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10492 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10493 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10494 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10495 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10497 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10498 c, opc->name, opc->args);
10502 if (used_bits != 0xffffffff)
10504 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10505 ~used_bits & 0xffffffff, opc->name, opc->args);
10511 /* For consistency checking, verify that the length implied matches the
10512 major opcode and that all bits are specified either by the match/mask
10513 part of the instruction definition, or by the operand list. */
10516 validate_micromips_insn (const struct mips_opcode *opc)
10518 unsigned long match = opc->match;
10519 unsigned long mask = opc->mask;
10520 const char *p = opc->args;
10521 unsigned long insn_bits;
10522 unsigned long used_bits;
10523 unsigned long major;
10524 unsigned int length;
10528 if ((mask & match) != match)
10530 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10531 opc->name, opc->args);
10534 length = micromips_insn_length (opc);
10535 if (length != 2 && length != 4)
10537 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10538 "%s %s"), length, opc->name, opc->args);
10541 major = match >> (10 + 8 * (length - 2));
10542 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10543 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10545 as_bad (_("Internal error: bad microMIPS opcode "
10546 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10550 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10551 insn_bits = 1 << 4 * length;
10552 insn_bits <<= 4 * length;
10555 #define USE_BITS(field) \
10556 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10567 case 'A': USE_BITS (EXTLSB); break;
10568 case 'B': USE_BITS (INSMSB); break;
10569 case 'C': USE_BITS (EXTMSBD); break;
10570 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10571 case 'E': USE_BITS (EXTLSB); break;
10572 case 'F': USE_BITS (INSMSB); break;
10573 case 'G': USE_BITS (EXTMSBD); break;
10574 case 'H': USE_BITS (EXTMSBD); break;
10576 as_bad (_("Internal error: bad mips opcode "
10577 "(unknown extension operand type `%c%c'): %s %s"),
10578 e, c, opc->name, opc->args);
10586 case 'A': USE_BITS (IMMA); break;
10587 case 'B': USE_BITS (IMMB); break;
10588 case 'C': USE_BITS (IMMC); break;
10589 case 'D': USE_BITS (IMMD); break;
10590 case 'E': USE_BITS (IMME); break;
10591 case 'F': USE_BITS (IMMF); break;
10592 case 'G': USE_BITS (IMMG); break;
10593 case 'H': USE_BITS (IMMH); break;
10594 case 'I': USE_BITS (IMMI); break;
10595 case 'J': USE_BITS (IMMJ); break;
10596 case 'L': USE_BITS (IMML); break;
10597 case 'M': USE_BITS (IMMM); break;
10598 case 'N': USE_BITS (IMMN); break;
10599 case 'O': USE_BITS (IMMO); break;
10600 case 'P': USE_BITS (IMMP); break;
10601 case 'Q': USE_BITS (IMMQ); break;
10602 case 'U': USE_BITS (IMMU); break;
10603 case 'W': USE_BITS (IMMW); break;
10604 case 'X': USE_BITS (IMMX); break;
10605 case 'Y': USE_BITS (IMMY); break;
10608 case 'b': USE_BITS (MB); break;
10609 case 'c': USE_BITS (MC); break;
10610 case 'd': USE_BITS (MD); break;
10611 case 'e': USE_BITS (ME); break;
10612 case 'f': USE_BITS (MF); break;
10613 case 'g': USE_BITS (MG); break;
10614 case 'h': USE_BITS (MH); break;
10615 case 'i': USE_BITS (MI); break;
10616 case 'j': USE_BITS (MJ); break;
10617 case 'l': USE_BITS (ML); break;
10618 case 'm': USE_BITS (MM); break;
10619 case 'n': USE_BITS (MN); break;
10620 case 'p': USE_BITS (MP); break;
10621 case 'q': USE_BITS (MQ); break;
10629 as_bad (_("Internal error: bad mips opcode "
10630 "(unknown extension operand type `%c%c'): %s %s"),
10631 e, c, opc->name, opc->args);
10635 case '.': USE_BITS (OFFSET10); break;
10636 case '1': USE_BITS (STYPE); break;
10637 case '2': USE_BITS (BP); break;
10638 case '3': USE_BITS (SA3); break;
10639 case '4': USE_BITS (SA4); break;
10640 case '5': USE_BITS (IMM8); break;
10641 case '6': USE_BITS (RS); break;
10642 case '7': USE_BITS (DSPACC); break;
10643 case '8': USE_BITS (WRDSP); break;
10644 case '0': USE_BITS (DSPSFT); break;
10645 case '<': USE_BITS (SHAMT); break;
10646 case '>': USE_BITS (SHAMT); break;
10647 case '@': USE_BITS (IMM10); break;
10648 case 'B': USE_BITS (CODE10); break;
10649 case 'C': USE_BITS (COPZ); break;
10650 case 'D': USE_BITS (FD); break;
10651 case 'E': USE_BITS (RT); break;
10652 case 'G': USE_BITS (RS); break;
10653 case 'H': USE_BITS (SEL); break;
10654 case 'K': USE_BITS (RS); break;
10655 case 'M': USE_BITS (CCC); break;
10656 case 'N': USE_BITS (BCC); break;
10657 case 'R': USE_BITS (FR); break;
10658 case 'S': USE_BITS (FS); break;
10659 case 'T': USE_BITS (FT); break;
10660 case 'V': USE_BITS (FS); break;
10661 case '\\': USE_BITS (3BITPOS); break;
10662 case '^': USE_BITS (RD); break;
10663 case 'a': USE_BITS (TARGET); break;
10664 case 'b': USE_BITS (RS); break;
10665 case 'c': USE_BITS (CODE); break;
10666 case 'd': USE_BITS (RD); break;
10667 case 'h': USE_BITS (PREFX); break;
10668 case 'i': USE_BITS (IMMEDIATE); break;
10669 case 'j': USE_BITS (DELTA); break;
10670 case 'k': USE_BITS (CACHE); break;
10671 case 'n': USE_BITS (RT); break;
10672 case 'o': USE_BITS (DELTA); break;
10673 case 'p': USE_BITS (DELTA); break;
10674 case 'q': USE_BITS (CODE2); break;
10675 case 'r': USE_BITS (RS); break;
10676 case 's': USE_BITS (RS); break;
10677 case 't': USE_BITS (RT); break;
10678 case 'u': USE_BITS (IMMEDIATE); break;
10679 case 'v': USE_BITS (RS); break;
10680 case 'w': USE_BITS (RT); break;
10681 case 'y': USE_BITS (RS3); break;
10683 case '|': USE_BITS (TRAP); break;
10684 case '~': USE_BITS (OFFSET12); break;
10686 as_bad (_("Internal error: bad microMIPS opcode "
10687 "(unknown operand type `%c'): %s %s"),
10688 c, opc->name, opc->args);
10692 if (used_bits != insn_bits)
10694 if (~used_bits & insn_bits)
10695 as_bad (_("Internal error: bad microMIPS opcode "
10696 "(bits 0x%lx undefined): %s %s"),
10697 ~used_bits & insn_bits, opc->name, opc->args);
10698 if (used_bits & ~insn_bits)
10699 as_bad (_("Internal error: bad microMIPS opcode "
10700 "(bits 0x%lx defined): %s %s"),
10701 used_bits & ~insn_bits, opc->name, opc->args);
10707 /* UDI immediates. */
10708 struct mips_immed {
10710 unsigned int shift;
10711 unsigned long mask;
10715 static const struct mips_immed mips_immed[] = {
10716 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10717 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10718 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10719 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10723 /* Check whether an odd floating-point register is allowed. */
10725 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10727 const char *s = insn->name;
10729 if (insn->pinfo == INSN_MACRO)
10730 /* Let a macro pass, we'll catch it later when it is expanded. */
10733 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
10735 /* Allow odd registers for single-precision ops. */
10736 switch (insn->pinfo & (FP_S | FP_D))
10740 return 1; /* both single precision - ok */
10742 return 0; /* both double precision - fail */
10747 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10748 s = strchr (insn->name, '.');
10750 s = s != NULL ? strchr (s + 1, '.') : NULL;
10751 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10754 /* Single-precision coprocessor loads and moves are OK too. */
10755 if ((insn->pinfo & FP_S)
10756 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10757 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10763 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10764 taking bits from BIT up. */
10766 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10768 return (ep->X_op == O_constant
10769 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10770 && ep->X_add_number >= min << bit
10771 && ep->X_add_number < max << bit);
10774 /* This routine assembles an instruction into its binary format. As a
10775 side effect, it sets one of the global variables imm_reloc or
10776 offset_reloc to the type of relocation to do if one of the operands
10777 is an address expression. */
10780 mips_ip (char *str, struct mips_cl_insn *ip)
10782 bfd_boolean wrong_delay_slot_insns = FALSE;
10783 bfd_boolean need_delay_slot_ok = TRUE;
10784 struct mips_opcode *firstinsn = NULL;
10785 const struct mips_opcode *past;
10786 struct hash_control *hash;
10790 struct mips_opcode *insn;
10792 unsigned int regno;
10793 unsigned int lastregno;
10794 unsigned int destregno = 0;
10795 unsigned int lastpos = 0;
10796 unsigned int limlo, limhi;
10798 offsetT min_range, max_range;
10802 unsigned int rtype;
10808 if (mips_opts.micromips)
10810 hash = micromips_op_hash;
10811 past = µmips_opcodes[bfd_micromips_num_opcodes];
10816 past = &mips_opcodes[NUMOPCODES];
10818 forced_insn_length = 0;
10821 /* We first try to match an instruction up to a space or to the end. */
10822 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10825 /* Make a copy of the instruction so that we can fiddle with it. */
10826 name = alloca (end + 1);
10827 memcpy (name, str, end);
10832 insn = (struct mips_opcode *) hash_find (hash, name);
10834 if (insn != NULL || !mips_opts.micromips)
10836 if (forced_insn_length)
10839 /* See if there's an instruction size override suffix,
10840 either `16' or `32', at the end of the mnemonic proper,
10841 that defines the operation, i.e. before the first `.'
10842 character if any. Strip it and retry. */
10843 dot = strchr (name, '.');
10844 opend = dot != NULL ? dot - name : end;
10847 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10848 forced_insn_length = 2;
10849 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10850 forced_insn_length = 4;
10853 memcpy (name + opend - 2, name + opend, end - opend + 1);
10857 insn_error = _("Unrecognized opcode");
10861 /* For microMIPS instructions placed in a fixed-length branch delay slot
10862 we make up to two passes over the relevant fragment of the opcode
10863 table. First we try instructions that meet the delay slot's length
10864 requirement. If none matched, then we retry with the remaining ones
10865 and if one matches, then we use it and then issue an appropriate
10866 warning later on. */
10867 argsStart = s = str + end;
10870 bfd_boolean delay_slot_ok;
10871 bfd_boolean size_ok;
10874 gas_assert (strcmp (insn->name, name) == 0);
10876 ok = is_opcode_valid (insn);
10877 size_ok = is_size_valid (insn);
10878 delay_slot_ok = is_delay_slot_valid (insn);
10879 if (!delay_slot_ok && !wrong_delay_slot_insns)
10882 wrong_delay_slot_insns = TRUE;
10884 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10886 static char buf[256];
10888 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10893 if (wrong_delay_slot_insns && need_delay_slot_ok)
10895 gas_assert (firstinsn);
10896 need_delay_slot_ok = FALSE;
10906 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10907 mips_cpu_info_from_arch (mips_opts.arch)->name,
10908 mips_cpu_info_from_isa (mips_opts.isa)->name);
10910 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10911 8 * forced_insn_length);
10917 create_insn (ip, insn);
10920 lastregno = 0xffffffff;
10921 for (args = insn->args;; ++args)
10925 s += strspn (s, " \t");
10929 case '\0': /* end of args */
10935 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10936 code) or 14 (for microMIPS code). */
10937 my_getExpression (&imm_expr, s);
10938 check_absolute_expr (ip, &imm_expr);
10939 if ((unsigned long) imm_expr.X_add_number != 1
10940 && (unsigned long) imm_expr.X_add_number != 3)
10942 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10943 (unsigned long) imm_expr.X_add_number);
10945 INSERT_OPERAND (mips_opts.micromips,
10946 BP, *ip, imm_expr.X_add_number);
10947 imm_expr.X_op = O_absent;
10952 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10953 code) or 21 (for microMIPS code). */
10955 unsigned long mask = (mips_opts.micromips
10956 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10958 my_getExpression (&imm_expr, s);
10959 check_absolute_expr (ip, &imm_expr);
10960 if ((unsigned long) imm_expr.X_add_number > mask)
10961 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10962 mask, (unsigned long) imm_expr.X_add_number);
10963 INSERT_OPERAND (mips_opts.micromips,
10964 SA3, *ip, imm_expr.X_add_number);
10965 imm_expr.X_op = O_absent;
10971 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10972 code) or 21 (for microMIPS code). */
10974 unsigned long mask = (mips_opts.micromips
10975 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10977 my_getExpression (&imm_expr, s);
10978 check_absolute_expr (ip, &imm_expr);
10979 if ((unsigned long) imm_expr.X_add_number > mask)
10980 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10981 mask, (unsigned long) imm_expr.X_add_number);
10982 INSERT_OPERAND (mips_opts.micromips,
10983 SA4, *ip, imm_expr.X_add_number);
10984 imm_expr.X_op = O_absent;
10990 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10991 code) or 16 (for microMIPS code). */
10993 unsigned long mask = (mips_opts.micromips
10994 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10996 my_getExpression (&imm_expr, s);
10997 check_absolute_expr (ip, &imm_expr);
10998 if ((unsigned long) imm_expr.X_add_number > mask)
10999 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11000 mask, (unsigned long) imm_expr.X_add_number);
11001 INSERT_OPERAND (mips_opts.micromips,
11002 IMM8, *ip, imm_expr.X_add_number);
11003 imm_expr.X_op = O_absent;
11009 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
11010 code) or 21 (for microMIPS code). */
11012 unsigned long mask = (mips_opts.micromips
11013 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11015 my_getExpression (&imm_expr, s);
11016 check_absolute_expr (ip, &imm_expr);
11017 if ((unsigned long) imm_expr.X_add_number > mask)
11018 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11019 mask, (unsigned long) imm_expr.X_add_number);
11020 INSERT_OPERAND (mips_opts.micromips,
11021 RS, *ip, imm_expr.X_add_number);
11022 imm_expr.X_op = O_absent;
11027 case '7': /* Four DSP accumulators in bits 11,12. */
11028 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11029 && s[3] >= '0' && s[3] <= '3')
11031 regno = s[3] - '0';
11033 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11037 as_bad (_("Invalid dsp acc register"));
11041 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11042 code) or 14 (for microMIPS code). */
11044 unsigned long mask = (mips_opts.micromips
11045 ? MICROMIPSOP_MASK_WRDSP
11048 my_getExpression (&imm_expr, s);
11049 check_absolute_expr (ip, &imm_expr);
11050 if ((unsigned long) imm_expr.X_add_number > mask)
11051 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11052 mask, (unsigned long) imm_expr.X_add_number);
11053 INSERT_OPERAND (mips_opts.micromips,
11054 WRDSP, *ip, imm_expr.X_add_number);
11055 imm_expr.X_op = O_absent;
11060 case '9': /* Four DSP accumulators in bits 21,22. */
11061 gas_assert (!mips_opts.micromips);
11062 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11063 && s[3] >= '0' && s[3] <= '3')
11065 regno = s[3] - '0';
11067 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11071 as_bad (_("Invalid dsp acc register"));
11075 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
11076 code) or 20 (for microMIPS code). */
11078 long mask = (mips_opts.micromips
11079 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11081 my_getExpression (&imm_expr, s);
11082 check_absolute_expr (ip, &imm_expr);
11083 min_range = -((mask + 1) >> 1);
11084 max_range = ((mask + 1) >> 1) - 1;
11085 if (imm_expr.X_add_number < min_range
11086 || imm_expr.X_add_number > max_range)
11087 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11088 (long) min_range, (long) max_range,
11089 (long) imm_expr.X_add_number);
11090 INSERT_OPERAND (mips_opts.micromips,
11091 DSPSFT, *ip, imm_expr.X_add_number);
11092 imm_expr.X_op = O_absent;
11097 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11098 gas_assert (!mips_opts.micromips);
11099 my_getExpression (&imm_expr, s);
11100 check_absolute_expr (ip, &imm_expr);
11101 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11103 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11105 (unsigned long) imm_expr.X_add_number);
11107 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11108 imm_expr.X_op = O_absent;
11112 case ':': /* DSP 7-bit signed immediate in bit 19. */
11113 gas_assert (!mips_opts.micromips);
11114 my_getExpression (&imm_expr, s);
11115 check_absolute_expr (ip, &imm_expr);
11116 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11117 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11118 if (imm_expr.X_add_number < min_range ||
11119 imm_expr.X_add_number > max_range)
11121 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11122 (long) min_range, (long) max_range,
11123 (long) imm_expr.X_add_number);
11125 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11126 imm_expr.X_op = O_absent;
11130 case '@': /* DSP 10-bit signed immediate in bit 16. */
11132 long mask = (mips_opts.micromips
11133 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11135 my_getExpression (&imm_expr, s);
11136 check_absolute_expr (ip, &imm_expr);
11137 min_range = -((mask + 1) >> 1);
11138 max_range = ((mask + 1) >> 1) - 1;
11139 if (imm_expr.X_add_number < min_range
11140 || imm_expr.X_add_number > max_range)
11141 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11142 (long) min_range, (long) max_range,
11143 (long) imm_expr.X_add_number);
11144 INSERT_OPERAND (mips_opts.micromips,
11145 IMM10, *ip, imm_expr.X_add_number);
11146 imm_expr.X_op = O_absent;
11151 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11152 gas_assert (mips_opts.micromips);
11153 my_getExpression (&imm_expr, s);
11154 check_absolute_expr (ip, &imm_expr);
11155 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11156 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11157 MICROMIPSOP_MASK_RD,
11158 (unsigned long) imm_expr.X_add_number);
11159 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11160 imm_expr.X_op = O_absent;
11164 case '!': /* MT usermode flag bit. */
11165 gas_assert (!mips_opts.micromips);
11166 my_getExpression (&imm_expr, s);
11167 check_absolute_expr (ip, &imm_expr);
11168 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11169 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11170 (unsigned long) imm_expr.X_add_number);
11171 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11172 imm_expr.X_op = O_absent;
11176 case '$': /* MT load high flag bit. */
11177 gas_assert (!mips_opts.micromips);
11178 my_getExpression (&imm_expr, s);
11179 check_absolute_expr (ip, &imm_expr);
11180 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11181 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11182 (unsigned long) imm_expr.X_add_number);
11183 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11184 imm_expr.X_op = O_absent;
11188 case '*': /* Four DSP accumulators in bits 18,19. */
11189 gas_assert (!mips_opts.micromips);
11190 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11191 s[3] >= '0' && s[3] <= '3')
11193 regno = s[3] - '0';
11195 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11199 as_bad (_("Invalid dsp/smartmips acc register"));
11202 case '&': /* Four DSP accumulators in bits 13,14. */
11203 gas_assert (!mips_opts.micromips);
11204 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11205 s[3] >= '0' && s[3] <= '3')
11207 regno = s[3] - '0';
11209 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11213 as_bad (_("Invalid dsp/smartmips acc register"));
11216 case '\\': /* 3-bit bit position. */
11218 unsigned long mask = (mips_opts.micromips
11219 ? MICROMIPSOP_MASK_3BITPOS
11220 : OP_MASK_3BITPOS);
11222 my_getExpression (&imm_expr, s);
11223 check_absolute_expr (ip, &imm_expr);
11224 if ((unsigned long) imm_expr.X_add_number > mask)
11225 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11227 mask, (unsigned long) imm_expr.X_add_number);
11228 INSERT_OPERAND (mips_opts.micromips,
11229 3BITPOS, *ip, imm_expr.X_add_number);
11230 imm_expr.X_op = O_absent;
11244 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11248 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11252 gas_assert (!mips_opts.micromips);
11253 INSERT_OPERAND (0, FT, *ip, lastregno);
11257 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11263 /* Handle optional base register.
11264 Either the base register is omitted or
11265 we must have a left paren. */
11266 /* This is dependent on the next operand specifier
11267 is a base register specification. */
11268 gas_assert (args[1] == 'b'
11269 || (mips_opts.micromips
11271 && (args[2] == 'l' || args[2] == 'n'
11272 || args[2] == 's' || args[2] == 'a')));
11273 if (*s == '\0' && args[1] == 'b')
11275 /* Fall through. */
11277 case ')': /* These must match exactly. */
11282 case '[': /* These must match exactly. */
11284 gas_assert (!mips_opts.micromips);
11289 case '+': /* Opcode extension character. */
11292 case '1': /* UDI immediates. */
11296 gas_assert (!mips_opts.micromips);
11298 const struct mips_immed *imm = mips_immed;
11300 while (imm->type && imm->type != *args)
11304 my_getExpression (&imm_expr, s);
11305 check_absolute_expr (ip, &imm_expr);
11306 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11308 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11309 imm->desc ? imm->desc : ip->insn_mo->name,
11310 (unsigned long) imm_expr.X_add_number,
11311 (unsigned long) imm_expr.X_add_number);
11312 imm_expr.X_add_number &= imm->mask;
11314 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11316 imm_expr.X_op = O_absent;
11321 case 'A': /* ins/ext position, becomes LSB. */
11330 my_getExpression (&imm_expr, s);
11331 check_absolute_expr (ip, &imm_expr);
11332 if ((unsigned long) imm_expr.X_add_number < limlo
11333 || (unsigned long) imm_expr.X_add_number > limhi)
11335 as_bad (_("Improper position (%lu)"),
11336 (unsigned long) imm_expr.X_add_number);
11337 imm_expr.X_add_number = limlo;
11339 lastpos = imm_expr.X_add_number;
11340 INSERT_OPERAND (mips_opts.micromips,
11341 EXTLSB, *ip, imm_expr.X_add_number);
11342 imm_expr.X_op = O_absent;
11346 case 'B': /* ins size, becomes MSB. */
11355 my_getExpression (&imm_expr, s);
11356 check_absolute_expr (ip, &imm_expr);
11357 /* Check for negative input so that small negative numbers
11358 will not succeed incorrectly. The checks against
11359 (pos+size) transitively check "size" itself,
11360 assuming that "pos" is reasonable. */
11361 if ((long) imm_expr.X_add_number < 0
11362 || ((unsigned long) imm_expr.X_add_number
11364 || ((unsigned long) imm_expr.X_add_number
11365 + lastpos) > limhi)
11367 as_bad (_("Improper insert size (%lu, position %lu)"),
11368 (unsigned long) imm_expr.X_add_number,
11369 (unsigned long) lastpos);
11370 imm_expr.X_add_number = limlo - lastpos;
11372 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11373 lastpos + imm_expr.X_add_number - 1);
11374 imm_expr.X_op = O_absent;
11378 case 'C': /* ext size, becomes MSBD. */
11391 my_getExpression (&imm_expr, s);
11392 check_absolute_expr (ip, &imm_expr);
11393 /* Check for negative input so that small negative numbers
11394 will not succeed incorrectly. The checks against
11395 (pos+size) transitively check "size" itself,
11396 assuming that "pos" is reasonable. */
11397 if ((long) imm_expr.X_add_number < 0
11398 || ((unsigned long) imm_expr.X_add_number
11400 || ((unsigned long) imm_expr.X_add_number
11401 + lastpos) > limhi)
11403 as_bad (_("Improper extract size (%lu, position %lu)"),
11404 (unsigned long) imm_expr.X_add_number,
11405 (unsigned long) lastpos);
11406 imm_expr.X_add_number = limlo - lastpos;
11408 INSERT_OPERAND (mips_opts.micromips,
11409 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11410 imm_expr.X_op = O_absent;
11415 /* +D is for disassembly only; never match. */
11419 /* "+I" is like "I", except that imm2_expr is used. */
11420 my_getExpression (&imm2_expr, s);
11421 if (imm2_expr.X_op != O_big
11422 && imm2_expr.X_op != O_constant)
11423 insn_error = _("absolute expression required");
11424 if (HAVE_32BIT_GPRS)
11425 normalize_constant_expr (&imm2_expr);
11429 case 'T': /* Coprocessor register. */
11430 gas_assert (!mips_opts.micromips);
11431 /* +T is for disassembly only; never match. */
11434 case 't': /* Coprocessor register number. */
11435 gas_assert (!mips_opts.micromips);
11436 if (s[0] == '$' && ISDIGIT (s[1]))
11446 while (ISDIGIT (*s));
11448 as_bad (_("Invalid register number (%d)"), regno);
11451 INSERT_OPERAND (0, RT, *ip, regno);
11456 as_bad (_("Invalid coprocessor 0 register number"));
11460 /* bbit[01] and bbit[01]32 bit index. Give error if index
11461 is not in the valid range. */
11462 gas_assert (!mips_opts.micromips);
11463 my_getExpression (&imm_expr, s);
11464 check_absolute_expr (ip, &imm_expr);
11465 if ((unsigned) imm_expr.X_add_number > 31)
11467 as_bad (_("Improper bit index (%lu)"),
11468 (unsigned long) imm_expr.X_add_number);
11469 imm_expr.X_add_number = 0;
11471 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11472 imm_expr.X_op = O_absent;
11477 /* bbit[01] bit index when bbit is used but we generate
11478 bbit[01]32 because the index is over 32. Move to the
11479 next candidate if index is not in the valid range. */
11480 gas_assert (!mips_opts.micromips);
11481 my_getExpression (&imm_expr, s);
11482 check_absolute_expr (ip, &imm_expr);
11483 if ((unsigned) imm_expr.X_add_number < 32
11484 || (unsigned) imm_expr.X_add_number > 63)
11486 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11487 imm_expr.X_op = O_absent;
11492 /* cins, cins32, exts and exts32 position field. Give error
11493 if it's not in the valid range. */
11494 gas_assert (!mips_opts.micromips);
11495 my_getExpression (&imm_expr, s);
11496 check_absolute_expr (ip, &imm_expr);
11497 if ((unsigned) imm_expr.X_add_number > 31)
11499 as_bad (_("Improper position (%lu)"),
11500 (unsigned long) imm_expr.X_add_number);
11501 imm_expr.X_add_number = 0;
11503 /* Make the pos explicit to simplify +S. */
11504 lastpos = imm_expr.X_add_number + 32;
11505 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11506 imm_expr.X_op = O_absent;
11511 /* cins, cins32, exts and exts32 position field. Move to
11512 the next candidate if it's not in the valid range. */
11513 gas_assert (!mips_opts.micromips);
11514 my_getExpression (&imm_expr, s);
11515 check_absolute_expr (ip, &imm_expr);
11516 if ((unsigned) imm_expr.X_add_number < 32
11517 || (unsigned) imm_expr.X_add_number > 63)
11519 lastpos = imm_expr.X_add_number;
11520 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11521 imm_expr.X_op = O_absent;
11526 /* cins and exts length-minus-one field. */
11527 gas_assert (!mips_opts.micromips);
11528 my_getExpression (&imm_expr, s);
11529 check_absolute_expr (ip, &imm_expr);
11530 if ((unsigned long) imm_expr.X_add_number > 31)
11532 as_bad (_("Improper size (%lu)"),
11533 (unsigned long) imm_expr.X_add_number);
11534 imm_expr.X_add_number = 0;
11536 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11537 imm_expr.X_op = O_absent;
11542 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11543 length-minus-one field. */
11544 gas_assert (!mips_opts.micromips);
11545 my_getExpression (&imm_expr, s);
11546 check_absolute_expr (ip, &imm_expr);
11547 if ((long) imm_expr.X_add_number < 0
11548 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11550 as_bad (_("Improper size (%lu)"),
11551 (unsigned long) imm_expr.X_add_number);
11552 imm_expr.X_add_number = 0;
11554 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11555 imm_expr.X_op = O_absent;
11560 /* seqi/snei immediate field. */
11561 gas_assert (!mips_opts.micromips);
11562 my_getExpression (&imm_expr, s);
11563 check_absolute_expr (ip, &imm_expr);
11564 if ((long) imm_expr.X_add_number < -512
11565 || (long) imm_expr.X_add_number >= 512)
11567 as_bad (_("Improper immediate (%ld)"),
11568 (long) imm_expr.X_add_number);
11569 imm_expr.X_add_number = 0;
11571 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11572 imm_expr.X_op = O_absent;
11576 case 'a': /* 8-bit signed offset in bit 6 */
11577 gas_assert (!mips_opts.micromips);
11578 my_getExpression (&imm_expr, s);
11579 check_absolute_expr (ip, &imm_expr);
11580 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11581 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11582 if (imm_expr.X_add_number < min_range
11583 || imm_expr.X_add_number > max_range)
11585 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11586 (long) min_range, (long) max_range,
11587 (long) imm_expr.X_add_number);
11589 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11590 imm_expr.X_op = O_absent;
11594 case 'b': /* 8-bit signed offset in bit 3 */
11595 gas_assert (!mips_opts.micromips);
11596 my_getExpression (&imm_expr, s);
11597 check_absolute_expr (ip, &imm_expr);
11598 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11599 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11600 if (imm_expr.X_add_number < min_range
11601 || imm_expr.X_add_number > max_range)
11603 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11604 (long) min_range, (long) max_range,
11605 (long) imm_expr.X_add_number);
11607 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11608 imm_expr.X_op = O_absent;
11612 case 'c': /* 9-bit signed offset in bit 6 */
11613 gas_assert (!mips_opts.micromips);
11614 my_getExpression (&imm_expr, s);
11615 check_absolute_expr (ip, &imm_expr);
11616 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11617 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11618 /* We check the offset range before adjusted. */
11621 if (imm_expr.X_add_number < min_range
11622 || imm_expr.X_add_number > max_range)
11624 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11625 (long) min_range, (long) max_range,
11626 (long) imm_expr.X_add_number);
11628 if (imm_expr.X_add_number & 0xf)
11630 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11631 (long) imm_expr.X_add_number);
11633 /* Right shift 4 bits to adjust the offset operand. */
11634 INSERT_OPERAND (0, OFFSET_C, *ip,
11635 imm_expr.X_add_number >> 4);
11636 imm_expr.X_op = O_absent;
11641 gas_assert (!mips_opts.micromips);
11642 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11644 if (regno == AT && mips_opts.at)
11646 if (mips_opts.at == ATREG)
11647 as_warn (_("used $at without \".set noat\""));
11649 as_warn (_("used $%u with \".set at=$%u\""),
11650 regno, mips_opts.at);
11652 INSERT_OPERAND (0, RZ, *ip, regno);
11656 gas_assert (!mips_opts.micromips);
11657 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11659 INSERT_OPERAND (0, FZ, *ip, regno);
11663 as_bad (_("Internal error: bad %s opcode "
11664 "(unknown extension operand type `+%c'): %s %s"),
11665 mips_opts.micromips ? "microMIPS" : "MIPS",
11666 *args, insn->name, insn->args);
11667 /* Further processing is fruitless. */
11672 case '.': /* 10-bit offset. */
11673 gas_assert (mips_opts.micromips);
11674 case '~': /* 12-bit offset. */
11676 int shift = *args == '.' ? 9 : 11;
11679 /* Check whether there is only a single bracketed expression
11680 left. If so, it must be the base register and the
11681 constant must be zero. */
11682 if (*s == '(' && strchr (s + 1, '(') == 0)
11685 /* If this value won't fit into the offset, then go find
11686 a macro that will generate a 16- or 32-bit offset code
11688 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11689 if ((i == 0 && (imm_expr.X_op != O_constant
11690 || imm_expr.X_add_number >= 1 << shift
11691 || imm_expr.X_add_number < -1 << shift))
11694 imm_expr.X_op = O_absent;
11698 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11700 INSERT_OPERAND (mips_opts.micromips,
11701 OFFSET12, *ip, imm_expr.X_add_number);
11702 imm_expr.X_op = O_absent;
11707 case '<': /* must be at least one digit */
11709 * According to the manual, if the shift amount is greater
11710 * than 31 or less than 0, then the shift amount should be
11711 * mod 32. In reality the mips assembler issues an error.
11712 * We issue a warning and mask out all but the low 5 bits.
11714 my_getExpression (&imm_expr, s);
11715 check_absolute_expr (ip, &imm_expr);
11716 if ((unsigned long) imm_expr.X_add_number > 31)
11717 as_warn (_("Improper shift amount (%lu)"),
11718 (unsigned long) imm_expr.X_add_number);
11719 INSERT_OPERAND (mips_opts.micromips,
11720 SHAMT, *ip, imm_expr.X_add_number);
11721 imm_expr.X_op = O_absent;
11725 case '>': /* shift amount minus 32 */
11726 my_getExpression (&imm_expr, s);
11727 check_absolute_expr (ip, &imm_expr);
11728 if ((unsigned long) imm_expr.X_add_number < 32
11729 || (unsigned long) imm_expr.X_add_number > 63)
11731 INSERT_OPERAND (mips_opts.micromips,
11732 SHAMT, *ip, imm_expr.X_add_number - 32);
11733 imm_expr.X_op = O_absent;
11737 case 'k': /* CACHE code. */
11738 case 'h': /* PREFX code. */
11739 case '1': /* SYNC type. */
11740 my_getExpression (&imm_expr, s);
11741 check_absolute_expr (ip, &imm_expr);
11742 if ((unsigned long) imm_expr.X_add_number > 31)
11743 as_warn (_("Invalid value for `%s' (%lu)"),
11745 (unsigned long) imm_expr.X_add_number);
11749 if (mips_fix_cn63xxp1
11750 && !mips_opts.micromips
11751 && strcmp ("pref", insn->name) == 0)
11752 switch (imm_expr.X_add_number)
11761 case 31: /* These are ok. */
11764 default: /* The rest must be changed to 28. */
11765 imm_expr.X_add_number = 28;
11768 INSERT_OPERAND (mips_opts.micromips,
11769 CACHE, *ip, imm_expr.X_add_number);
11772 INSERT_OPERAND (mips_opts.micromips,
11773 PREFX, *ip, imm_expr.X_add_number);
11776 INSERT_OPERAND (mips_opts.micromips,
11777 STYPE, *ip, imm_expr.X_add_number);
11780 imm_expr.X_op = O_absent;
11784 case 'c': /* BREAK code. */
11786 unsigned long mask = (mips_opts.micromips
11787 ? MICROMIPSOP_MASK_CODE
11790 my_getExpression (&imm_expr, s);
11791 check_absolute_expr (ip, &imm_expr);
11792 if ((unsigned long) imm_expr.X_add_number > mask)
11793 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11795 mask, (unsigned long) imm_expr.X_add_number);
11796 INSERT_OPERAND (mips_opts.micromips,
11797 CODE, *ip, imm_expr.X_add_number);
11798 imm_expr.X_op = O_absent;
11803 case 'q': /* Lower BREAK code. */
11805 unsigned long mask = (mips_opts.micromips
11806 ? MICROMIPSOP_MASK_CODE2
11809 my_getExpression (&imm_expr, s);
11810 check_absolute_expr (ip, &imm_expr);
11811 if ((unsigned long) imm_expr.X_add_number > mask)
11812 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11814 mask, (unsigned long) imm_expr.X_add_number);
11815 INSERT_OPERAND (mips_opts.micromips,
11816 CODE2, *ip, imm_expr.X_add_number);
11817 imm_expr.X_op = O_absent;
11822 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11824 unsigned long mask = (mips_opts.micromips
11825 ? MICROMIPSOP_MASK_CODE10
11828 my_getExpression (&imm_expr, s);
11829 check_absolute_expr (ip, &imm_expr);
11830 if ((unsigned long) imm_expr.X_add_number > mask)
11831 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11833 mask, (unsigned long) imm_expr.X_add_number);
11834 if (mips_opts.micromips)
11835 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11837 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11838 imm_expr.X_op = O_absent;
11843 case 'C': /* 25- or 23-bit coprocessor code. */
11845 unsigned long mask = (mips_opts.micromips
11846 ? MICROMIPSOP_MASK_COPZ
11849 my_getExpression (&imm_expr, s);
11850 check_absolute_expr (ip, &imm_expr);
11851 if ((unsigned long) imm_expr.X_add_number > mask)
11852 as_warn (_("Coproccesor code > %u bits (%lu)"),
11853 mips_opts.micromips ? 23U : 25U,
11854 (unsigned long) imm_expr.X_add_number);
11855 INSERT_OPERAND (mips_opts.micromips,
11856 COPZ, *ip, imm_expr.X_add_number);
11857 imm_expr.X_op = O_absent;
11862 case 'J': /* 19-bit WAIT code. */
11863 gas_assert (!mips_opts.micromips);
11864 my_getExpression (&imm_expr, s);
11865 check_absolute_expr (ip, &imm_expr);
11866 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11868 as_warn (_("Illegal 19-bit code (%lu)"),
11869 (unsigned long) imm_expr.X_add_number);
11870 imm_expr.X_add_number &= OP_MASK_CODE19;
11872 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11873 imm_expr.X_op = O_absent;
11877 case 'P': /* Performance register. */
11878 gas_assert (!mips_opts.micromips);
11879 my_getExpression (&imm_expr, s);
11880 check_absolute_expr (ip, &imm_expr);
11881 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11882 as_warn (_("Invalid performance register (%lu)"),
11883 (unsigned long) imm_expr.X_add_number);
11884 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
11885 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
11886 as_warn (_("Invalid performance register (%lu)"),
11887 (unsigned long) imm_expr.X_add_number);
11888 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11889 imm_expr.X_op = O_absent;
11893 case 'G': /* Coprocessor destination register. */
11895 unsigned long opcode = ip->insn_opcode;
11896 unsigned long mask;
11897 unsigned int types;
11900 if (mips_opts.micromips)
11902 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11903 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11904 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11908 case 0x000000fc: /* mfc0 */
11909 case 0x000002fc: /* mtc0 */
11910 case 0x580000fc: /* dmfc0 */
11911 case 0x580002fc: /* dmtc0 */
11921 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11922 cop0 = opcode == OP_OP_COP0;
11924 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11925 ok = reg_lookup (&s, types, ®no);
11926 if (mips_opts.micromips)
11927 INSERT_OPERAND (1, RS, *ip, regno);
11929 INSERT_OPERAND (0, RD, *ip, regno);
11938 case 'y': /* ALNV.PS source register. */
11939 gas_assert (mips_opts.micromips);
11941 case 'x': /* Ignore register name. */
11942 case 'U': /* Destination register (CLO/CLZ). */
11943 case 'g': /* Coprocessor destination register. */
11944 gas_assert (!mips_opts.micromips);
11945 case 'b': /* Base register. */
11946 case 'd': /* Destination register. */
11947 case 's': /* Source register. */
11948 case 't': /* Target register. */
11949 case 'r': /* Both target and source. */
11950 case 'v': /* Both dest and source. */
11951 case 'w': /* Both dest and target. */
11952 case 'E': /* Coprocessor target register. */
11953 case 'K': /* RDHWR destination register. */
11954 case 'z': /* Must be zero register. */
11957 if (*args == 'E' || *args == 'K')
11958 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11961 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11962 if (regno == AT && mips_opts.at)
11964 if (mips_opts.at == ATREG)
11965 as_warn (_("Used $at without \".set noat\""));
11967 as_warn (_("Used $%u with \".set at=$%u\""),
11968 regno, mips_opts.at);
11978 if (c == 'r' || c == 'v' || c == 'w')
11985 /* 'z' only matches $0. */
11986 if (c == 'z' && regno != 0)
11989 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11991 if (regno == lastregno)
11994 = _("Source and destination must be different");
11997 if (regno == 31 && lastregno == 0xffffffff)
12000 = _("A destination register must be supplied");
12004 /* Now that we have assembled one operand, we use the args
12005 string to figure out where it goes in the instruction. */
12012 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12016 if (mips_opts.micromips)
12017 INSERT_OPERAND (1, RS, *ip, regno);
12019 INSERT_OPERAND (0, RD, *ip, regno);
12024 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12028 gas_assert (!mips_opts.micromips);
12029 INSERT_OPERAND (0, RD, *ip, regno);
12030 INSERT_OPERAND (0, RT, *ip, regno);
12036 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12040 gas_assert (mips_opts.micromips);
12041 INSERT_OPERAND (1, RS3, *ip, regno);
12045 /* This case exists because on the r3000 trunc
12046 expands into a macro which requires a gp
12047 register. On the r6000 or r4000 it is
12048 assembled into a single instruction which
12049 ignores the register. Thus the insn version
12050 is MIPS_ISA2 and uses 'x', and the macro
12051 version is MIPS_ISA1 and uses 't'. */
12055 /* This case is for the div instruction, which
12056 acts differently if the destination argument
12057 is $0. This only matches $0, and is checked
12058 outside the switch. */
12068 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12072 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12077 case 'O': /* MDMX alignment immediate constant. */
12078 gas_assert (!mips_opts.micromips);
12079 my_getExpression (&imm_expr, s);
12080 check_absolute_expr (ip, &imm_expr);
12081 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12082 as_warn (_("Improper align amount (%ld), using low bits"),
12083 (long) imm_expr.X_add_number);
12084 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12085 imm_expr.X_op = O_absent;
12089 case 'Q': /* MDMX vector, element sel, or const. */
12092 /* MDMX Immediate. */
12093 gas_assert (!mips_opts.micromips);
12094 my_getExpression (&imm_expr, s);
12095 check_absolute_expr (ip, &imm_expr);
12096 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12097 as_warn (_("Invalid MDMX Immediate (%ld)"),
12098 (long) imm_expr.X_add_number);
12099 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12100 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12101 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12103 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12104 imm_expr.X_op = O_absent;
12108 /* Not MDMX Immediate. Fall through. */
12109 case 'X': /* MDMX destination register. */
12110 case 'Y': /* MDMX source register. */
12111 case 'Z': /* MDMX target register. */
12114 gas_assert (!mips_opts.micromips);
12115 case 'D': /* Floating point destination register. */
12116 case 'S': /* Floating point source register. */
12117 case 'T': /* Floating point target register. */
12118 case 'R': /* Floating point source register. */
12122 || (mips_opts.ase_mdmx
12123 && (ip->insn_mo->pinfo & FP_D)
12124 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12125 | INSN_COPROC_MEMORY_DELAY
12126 | INSN_LOAD_COPROC_DELAY
12127 | INSN_LOAD_MEMORY_DELAY
12128 | INSN_STORE_MEMORY))))
12129 rtype |= RTYPE_VEC;
12131 if (reg_lookup (&s, rtype, ®no))
12133 if ((regno & 1) != 0
12135 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12136 as_warn (_("Float register should be even, was %d"),
12144 if (c == 'V' || c == 'W')
12155 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12161 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12165 /* This is like 'Z', but also needs to fix the MDMX
12166 vector/scalar select bits. Note that the
12167 scalar immediate case is handled above. */
12170 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12171 int max_el = (is_qh ? 3 : 7);
12173 my_getExpression(&imm_expr, s);
12174 check_absolute_expr (ip, &imm_expr);
12176 if (imm_expr.X_add_number > max_el)
12177 as_bad (_("Bad element selector %ld"),
12178 (long) imm_expr.X_add_number);
12179 imm_expr.X_add_number &= max_el;
12180 ip->insn_opcode |= (imm_expr.X_add_number
12183 imm_expr.X_op = O_absent;
12185 as_warn (_("Expecting ']' found '%s'"), s);
12191 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12192 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12195 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12198 /* Fall through. */
12202 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12206 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12216 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12220 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12226 my_getExpression (&imm_expr, s);
12227 if (imm_expr.X_op != O_big
12228 && imm_expr.X_op != O_constant)
12229 insn_error = _("absolute expression required");
12230 if (HAVE_32BIT_GPRS)
12231 normalize_constant_expr (&imm_expr);
12236 my_getExpression (&offset_expr, s);
12237 normalize_address_expr (&offset_expr);
12238 *imm_reloc = BFD_RELOC_32;
12251 unsigned char temp[8];
12253 unsigned int length;
12258 /* These only appear as the last operand in an
12259 instruction, and every instruction that accepts
12260 them in any variant accepts them in all variants.
12261 This means we don't have to worry about backing out
12262 any changes if the instruction does not match.
12264 The difference between them is the size of the
12265 floating point constant and where it goes. For 'F'
12266 and 'L' the constant is 64 bits; for 'f' and 'l' it
12267 is 32 bits. Where the constant is placed is based
12268 on how the MIPS assembler does things:
12271 f -- immediate value
12274 The .lit4 and .lit8 sections are only used if
12275 permitted by the -G argument.
12277 The code below needs to know whether the target register
12278 is 32 or 64 bits wide. It relies on the fact 'f' and
12279 'F' are used with GPR-based instructions and 'l' and
12280 'L' are used with FPR-based instructions. */
12282 f64 = *args == 'F' || *args == 'L';
12283 using_gprs = *args == 'F' || *args == 'f';
12285 save_in = input_line_pointer;
12286 input_line_pointer = s;
12287 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12289 s = input_line_pointer;
12290 input_line_pointer = save_in;
12291 if (err != NULL && *err != '\0')
12293 as_bad (_("Bad floating point constant: %s"), err);
12294 memset (temp, '\0', sizeof temp);
12295 length = f64 ? 8 : 4;
12298 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12302 && (g_switch_value < 4
12303 || (temp[0] == 0 && temp[1] == 0)
12304 || (temp[2] == 0 && temp[3] == 0))))
12306 imm_expr.X_op = O_constant;
12307 if (!target_big_endian)
12308 imm_expr.X_add_number = bfd_getl32 (temp);
12310 imm_expr.X_add_number = bfd_getb32 (temp);
12312 else if (length > 4
12313 && !mips_disable_float_construction
12314 /* Constants can only be constructed in GPRs and
12315 copied to FPRs if the GPRs are at least as wide
12316 as the FPRs. Force the constant into memory if
12317 we are using 64-bit FPRs but the GPRs are only
12320 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12321 && ((temp[0] == 0 && temp[1] == 0)
12322 || (temp[2] == 0 && temp[3] == 0))
12323 && ((temp[4] == 0 && temp[5] == 0)
12324 || (temp[6] == 0 && temp[7] == 0)))
12326 /* The value is simple enough to load with a couple of
12327 instructions. If using 32-bit registers, set
12328 imm_expr to the high order 32 bits and offset_expr to
12329 the low order 32 bits. Otherwise, set imm_expr to
12330 the entire 64 bit constant. */
12331 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12333 imm_expr.X_op = O_constant;
12334 offset_expr.X_op = O_constant;
12335 if (!target_big_endian)
12337 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12338 offset_expr.X_add_number = bfd_getl32 (temp);
12342 imm_expr.X_add_number = bfd_getb32 (temp);
12343 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12345 if (offset_expr.X_add_number == 0)
12346 offset_expr.X_op = O_absent;
12348 else if (sizeof (imm_expr.X_add_number) > 4)
12350 imm_expr.X_op = O_constant;
12351 if (!target_big_endian)
12352 imm_expr.X_add_number = bfd_getl64 (temp);
12354 imm_expr.X_add_number = bfd_getb64 (temp);
12358 imm_expr.X_op = O_big;
12359 imm_expr.X_add_number = 4;
12360 if (!target_big_endian)
12362 generic_bignum[0] = bfd_getl16 (temp);
12363 generic_bignum[1] = bfd_getl16 (temp + 2);
12364 generic_bignum[2] = bfd_getl16 (temp + 4);
12365 generic_bignum[3] = bfd_getl16 (temp + 6);
12369 generic_bignum[0] = bfd_getb16 (temp + 6);
12370 generic_bignum[1] = bfd_getb16 (temp + 4);
12371 generic_bignum[2] = bfd_getb16 (temp + 2);
12372 generic_bignum[3] = bfd_getb16 (temp);
12378 const char *newname;
12381 /* Switch to the right section. */
12383 subseg = now_subseg;
12386 default: /* unused default case avoids warnings. */
12388 newname = RDATA_SECTION_NAME;
12389 if (g_switch_value >= 8)
12393 newname = RDATA_SECTION_NAME;
12396 gas_assert (g_switch_value >= 4);
12400 new_seg = subseg_new (newname, (subsegT) 0);
12402 bfd_set_section_flags (stdoutput, new_seg,
12407 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12408 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12409 record_alignment (new_seg, 4);
12411 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12412 if (seg == now_seg)
12413 as_bad (_("Can't use floating point insn in this section"));
12415 /* Set the argument to the current address in the
12417 offset_expr.X_op = O_symbol;
12418 offset_expr.X_add_symbol = symbol_temp_new_now ();
12419 offset_expr.X_add_number = 0;
12421 /* Put the floating point number into the section. */
12422 p = frag_more ((int) length);
12423 memcpy (p, temp, length);
12425 /* Switch back to the original section. */
12426 subseg_set (seg, subseg);
12431 case 'i': /* 16-bit unsigned immediate. */
12432 case 'j': /* 16-bit signed immediate. */
12433 *imm_reloc = BFD_RELOC_LO16;
12434 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12437 offsetT minval, maxval;
12439 more = (insn + 1 < past
12440 && strcmp (insn->name, insn[1].name) == 0);
12442 /* If the expression was written as an unsigned number,
12443 only treat it as signed if there are no more
12447 && sizeof (imm_expr.X_add_number) <= 4
12448 && imm_expr.X_op == O_constant
12449 && imm_expr.X_add_number < 0
12450 && imm_expr.X_unsigned
12451 && HAVE_64BIT_GPRS)
12454 /* For compatibility with older assemblers, we accept
12455 0x8000-0xffff as signed 16-bit numbers when only
12456 signed numbers are allowed. */
12458 minval = 0, maxval = 0xffff;
12460 minval = -0x8000, maxval = 0x7fff;
12462 minval = -0x8000, maxval = 0xffff;
12464 if (imm_expr.X_op != O_constant
12465 || imm_expr.X_add_number < minval
12466 || imm_expr.X_add_number > maxval)
12470 if (imm_expr.X_op == O_constant
12471 || imm_expr.X_op == O_big)
12472 as_bad (_("Expression out of range"));
12478 case 'o': /* 16-bit offset. */
12479 offset_reloc[0] = BFD_RELOC_LO16;
12480 offset_reloc[1] = BFD_RELOC_UNUSED;
12481 offset_reloc[2] = BFD_RELOC_UNUSED;
12483 /* Check whether there is only a single bracketed expression
12484 left. If so, it must be the base register and the
12485 constant must be zero. */
12486 if (*s == '(' && strchr (s + 1, '(') == 0)
12488 offset_expr.X_op = O_constant;
12489 offset_expr.X_add_number = 0;
12493 /* If this value won't fit into a 16 bit offset, then go
12494 find a macro that will generate the 32 bit offset
12496 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12497 && (offset_expr.X_op != O_constant
12498 || offset_expr.X_add_number >= 0x8000
12499 || offset_expr.X_add_number < -0x8000))
12505 case 'p': /* PC-relative offset. */
12506 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12507 my_getExpression (&offset_expr, s);
12511 case 'u': /* Upper 16 bits. */
12512 *imm_reloc = BFD_RELOC_LO16;
12513 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12514 && imm_expr.X_op == O_constant
12515 && (imm_expr.X_add_number < 0
12516 || imm_expr.X_add_number >= 0x10000))
12517 as_bad (_("lui expression (%lu) not in range 0..65535"),
12518 (unsigned long) imm_expr.X_add_number);
12522 case 'a': /* 26-bit address. */
12523 *offset_reloc = BFD_RELOC_MIPS_JMP;
12524 my_getExpression (&offset_expr, s);
12528 case 'N': /* 3-bit branch condition code. */
12529 case 'M': /* 3-bit compare condition code. */
12531 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12532 rtype |= RTYPE_FCC;
12533 if (!reg_lookup (&s, rtype, ®no))
12535 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12536 || strcmp (str + strlen (str) - 5, "any2f") == 0
12537 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12538 && (regno & 1) != 0)
12539 as_warn (_("Condition code register should be even for %s, "
12542 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12543 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12544 && (regno & 3) != 0)
12545 as_warn (_("Condition code register should be 0 or 4 for %s, "
12549 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12551 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12555 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12566 while (ISDIGIT (*s));
12569 c = 8; /* Invalid sel value. */
12572 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12573 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12577 gas_assert (!mips_opts.micromips);
12578 /* Must be at least one digit. */
12579 my_getExpression (&imm_expr, s);
12580 check_absolute_expr (ip, &imm_expr);
12582 if ((unsigned long) imm_expr.X_add_number
12583 > (unsigned long) OP_MASK_VECBYTE)
12585 as_bad (_("bad byte vector index (%ld)"),
12586 (long) imm_expr.X_add_number);
12587 imm_expr.X_add_number = 0;
12590 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12591 imm_expr.X_op = O_absent;
12596 gas_assert (!mips_opts.micromips);
12597 my_getExpression (&imm_expr, s);
12598 check_absolute_expr (ip, &imm_expr);
12600 if ((unsigned long) imm_expr.X_add_number
12601 > (unsigned long) OP_MASK_VECALIGN)
12603 as_bad (_("bad byte vector index (%ld)"),
12604 (long) imm_expr.X_add_number);
12605 imm_expr.X_add_number = 0;
12608 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12609 imm_expr.X_op = O_absent;
12613 case 'm': /* Opcode extension character. */
12614 gas_assert (mips_opts.micromips);
12619 if (strncmp (s, "$pc", 3) == 0)
12647 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12648 if (regno == AT && mips_opts.at)
12650 if (mips_opts.at == ATREG)
12651 as_warn (_("Used $at without \".set noat\""));
12653 as_warn (_("Used $%u with \".set at=$%u\""),
12654 regno, mips_opts.at);
12660 gas_assert (args[1] == ',');
12666 gas_assert (args[1] == ',');
12668 continue; /* Nothing to do. */
12674 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12676 if (regno == lastregno)
12679 = _("Source and destination must be different");
12682 if (regno == 31 && lastregno == 0xffffffff)
12685 = _("A destination register must be supplied");
12696 gas_assert (args[1] == ',');
12703 gas_assert (args[1] == ',');
12706 continue; /* Nothing to do. */
12710 /* Make sure regno is the same as lastregno. */
12711 if (c == 't' && regno != lastregno)
12714 /* Make sure regno is the same as destregno. */
12715 if (c == 'x' && regno != destregno)
12718 /* We need to save regno, before regno maps to the
12719 microMIPS register encoding. */
12729 regno = ILLEGAL_REG;
12733 regno = mips32_to_micromips_reg_b_map[regno];
12737 regno = mips32_to_micromips_reg_c_map[regno];
12741 regno = mips32_to_micromips_reg_d_map[regno];
12745 regno = mips32_to_micromips_reg_e_map[regno];
12749 regno = mips32_to_micromips_reg_f_map[regno];
12753 regno = mips32_to_micromips_reg_g_map[regno];
12757 regno = mips32_to_micromips_reg_h_map[regno];
12761 switch (EXTRACT_OPERAND (1, MI, *ip))
12766 else if (regno == 22)
12768 else if (regno == 5)
12770 else if (regno == 6)
12772 else if (regno == 7)
12775 regno = ILLEGAL_REG;
12781 else if (regno == 7)
12784 regno = ILLEGAL_REG;
12791 regno = ILLEGAL_REG;
12795 regno = ILLEGAL_REG;
12801 regno = mips32_to_micromips_reg_l_map[regno];
12805 regno = mips32_to_micromips_reg_m_map[regno];
12809 regno = mips32_to_micromips_reg_n_map[regno];
12813 regno = mips32_to_micromips_reg_q_map[regno];
12818 regno = ILLEGAL_REG;
12823 regno = ILLEGAL_REG;
12828 regno = ILLEGAL_REG;
12831 case 'j': /* Do nothing. */
12841 if (regno == ILLEGAL_REG)
12847 INSERT_OPERAND (1, MB, *ip, regno);
12851 INSERT_OPERAND (1, MC, *ip, regno);
12855 INSERT_OPERAND (1, MD, *ip, regno);
12859 INSERT_OPERAND (1, ME, *ip, regno);
12863 INSERT_OPERAND (1, MF, *ip, regno);
12867 INSERT_OPERAND (1, MG, *ip, regno);
12871 INSERT_OPERAND (1, MH, *ip, regno);
12875 INSERT_OPERAND (1, MI, *ip, regno);
12879 INSERT_OPERAND (1, MJ, *ip, regno);
12883 INSERT_OPERAND (1, ML, *ip, regno);
12887 INSERT_OPERAND (1, MM, *ip, regno);
12891 INSERT_OPERAND (1, MN, *ip, regno);
12895 INSERT_OPERAND (1, MP, *ip, regno);
12899 INSERT_OPERAND (1, MQ, *ip, regno);
12902 case 'a': /* Do nothing. */
12903 case 's': /* Do nothing. */
12904 case 't': /* Do nothing. */
12905 case 'x': /* Do nothing. */
12906 case 'y': /* Do nothing. */
12907 case 'z': /* Do nothing. */
12917 bfd_reloc_code_real_type r[3];
12921 /* Check whether there is only a single bracketed
12922 expression left. If so, it must be the base register
12923 and the constant must be zero. */
12924 if (*s == '(' && strchr (s + 1, '(') == 0)
12926 INSERT_OPERAND (1, IMMA, *ip, 0);
12930 if (my_getSmallExpression (&ep, r, s) > 0
12931 || !expr_const_in_range (&ep, -64, 64, 2))
12934 imm = ep.X_add_number >> 2;
12935 INSERT_OPERAND (1, IMMA, *ip, imm);
12942 bfd_reloc_code_real_type r[3];
12946 if (my_getSmallExpression (&ep, r, s) > 0
12947 || ep.X_op != O_constant)
12950 for (imm = 0; imm < 8; imm++)
12951 if (micromips_imm_b_map[imm] == ep.X_add_number)
12956 INSERT_OPERAND (1, IMMB, *ip, imm);
12963 bfd_reloc_code_real_type r[3];
12967 if (my_getSmallExpression (&ep, r, s) > 0
12968 || ep.X_op != O_constant)
12971 for (imm = 0; imm < 16; imm++)
12972 if (micromips_imm_c_map[imm] == ep.X_add_number)
12977 INSERT_OPERAND (1, IMMC, *ip, imm);
12982 case 'D': /* pc relative offset */
12983 case 'E': /* pc relative offset */
12984 my_getExpression (&offset_expr, s);
12985 if (offset_expr.X_op == O_register)
12988 if (!forced_insn_length)
12989 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12991 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12993 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12999 bfd_reloc_code_real_type r[3];
13003 if (my_getSmallExpression (&ep, r, s) > 0
13004 || !expr_const_in_range (&ep, 0, 16, 0))
13007 imm = ep.X_add_number;
13008 INSERT_OPERAND (1, IMMF, *ip, imm);
13015 bfd_reloc_code_real_type r[3];
13019 /* Check whether there is only a single bracketed
13020 expression left. If so, it must be the base register
13021 and the constant must be zero. */
13022 if (*s == '(' && strchr (s + 1, '(') == 0)
13024 INSERT_OPERAND (1, IMMG, *ip, 0);
13028 if (my_getSmallExpression (&ep, r, s) > 0
13029 || !expr_const_in_range (&ep, -1, 15, 0))
13032 imm = ep.X_add_number & 15;
13033 INSERT_OPERAND (1, IMMG, *ip, imm);
13040 bfd_reloc_code_real_type r[3];
13044 /* Check whether there is only a single bracketed
13045 expression left. If so, it must be the base register
13046 and the constant must be zero. */
13047 if (*s == '(' && strchr (s + 1, '(') == 0)
13049 INSERT_OPERAND (1, IMMH, *ip, 0);
13053 if (my_getSmallExpression (&ep, r, s) > 0
13054 || !expr_const_in_range (&ep, 0, 16, 1))
13057 imm = ep.X_add_number >> 1;
13058 INSERT_OPERAND (1, IMMH, *ip, imm);
13065 bfd_reloc_code_real_type r[3];
13069 if (my_getSmallExpression (&ep, r, s) > 0
13070 || !expr_const_in_range (&ep, -1, 127, 0))
13073 imm = ep.X_add_number & 127;
13074 INSERT_OPERAND (1, IMMI, *ip, imm);
13081 bfd_reloc_code_real_type r[3];
13085 /* Check whether there is only a single bracketed
13086 expression left. If so, it must be the base register
13087 and the constant must be zero. */
13088 if (*s == '(' && strchr (s + 1, '(') == 0)
13090 INSERT_OPERAND (1, IMMJ, *ip, 0);
13094 if (my_getSmallExpression (&ep, r, s) > 0
13095 || !expr_const_in_range (&ep, 0, 16, 2))
13098 imm = ep.X_add_number >> 2;
13099 INSERT_OPERAND (1, IMMJ, *ip, imm);
13106 bfd_reloc_code_real_type r[3];
13110 /* Check whether there is only a single bracketed
13111 expression left. If so, it must be the base register
13112 and the constant must be zero. */
13113 if (*s == '(' && strchr (s + 1, '(') == 0)
13115 INSERT_OPERAND (1, IMML, *ip, 0);
13119 if (my_getSmallExpression (&ep, r, s) > 0
13120 || !expr_const_in_range (&ep, 0, 16, 0))
13123 imm = ep.X_add_number;
13124 INSERT_OPERAND (1, IMML, *ip, imm);
13131 bfd_reloc_code_real_type r[3];
13135 if (my_getSmallExpression (&ep, r, s) > 0
13136 || !expr_const_in_range (&ep, 1, 9, 0))
13139 imm = ep.X_add_number & 7;
13140 INSERT_OPERAND (1, IMMM, *ip, imm);
13145 case 'N': /* Register list for lwm and swm. */
13147 /* A comma-separated list of registers and/or
13148 dash-separated contiguous ranges including
13149 both ra and a set of one or more registers
13150 starting at s0 up to s3 which have to be
13157 and any permutations of these. */
13158 unsigned int reglist;
13161 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13164 if ((reglist & 0xfff1ffff) != 0x80010000)
13167 reglist = (reglist >> 17) & 7;
13169 if ((reglist & -reglist) != reglist)
13172 imm = ffs (reglist) - 1;
13173 INSERT_OPERAND (1, IMMN, *ip, imm);
13177 case 'O': /* sdbbp 4-bit code. */
13179 bfd_reloc_code_real_type r[3];
13183 if (my_getSmallExpression (&ep, r, s) > 0
13184 || !expr_const_in_range (&ep, 0, 16, 0))
13187 imm = ep.X_add_number;
13188 INSERT_OPERAND (1, IMMO, *ip, imm);
13195 bfd_reloc_code_real_type r[3];
13199 if (my_getSmallExpression (&ep, r, s) > 0
13200 || !expr_const_in_range (&ep, 0, 32, 2))
13203 imm = ep.X_add_number >> 2;
13204 INSERT_OPERAND (1, IMMP, *ip, imm);
13211 bfd_reloc_code_real_type r[3];
13215 if (my_getSmallExpression (&ep, r, s) > 0
13216 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13219 imm = ep.X_add_number >> 2;
13220 INSERT_OPERAND (1, IMMQ, *ip, imm);
13227 bfd_reloc_code_real_type r[3];
13231 /* Check whether there is only a single bracketed
13232 expression left. If so, it must be the base register
13233 and the constant must be zero. */
13234 if (*s == '(' && strchr (s + 1, '(') == 0)
13236 INSERT_OPERAND (1, IMMU, *ip, 0);
13240 if (my_getSmallExpression (&ep, r, s) > 0
13241 || !expr_const_in_range (&ep, 0, 32, 2))
13244 imm = ep.X_add_number >> 2;
13245 INSERT_OPERAND (1, IMMU, *ip, imm);
13252 bfd_reloc_code_real_type r[3];
13256 if (my_getSmallExpression (&ep, r, s) > 0
13257 || !expr_const_in_range (&ep, 0, 64, 2))
13260 imm = ep.X_add_number >> 2;
13261 INSERT_OPERAND (1, IMMW, *ip, imm);
13268 bfd_reloc_code_real_type r[3];
13272 if (my_getSmallExpression (&ep, r, s) > 0
13273 || !expr_const_in_range (&ep, -8, 8, 0))
13276 imm = ep.X_add_number;
13277 INSERT_OPERAND (1, IMMX, *ip, imm);
13284 bfd_reloc_code_real_type r[3];
13288 if (my_getSmallExpression (&ep, r, s) > 0
13289 || expr_const_in_range (&ep, -2, 2, 2)
13290 || !expr_const_in_range (&ep, -258, 258, 2))
13293 imm = ep.X_add_number >> 2;
13294 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13295 INSERT_OPERAND (1, IMMY, *ip, imm);
13302 bfd_reloc_code_real_type r[3];
13305 if (my_getSmallExpression (&ep, r, s) > 0
13306 || !expr_const_in_range (&ep, 0, 1, 0))
13313 as_bad (_("Internal error: bad microMIPS opcode "
13314 "(unknown extension operand type `m%c'): %s %s"),
13315 *args, insn->name, insn->args);
13316 /* Further processing is fruitless. */
13321 case 'n': /* Register list for 32-bit lwm and swm. */
13322 gas_assert (mips_opts.micromips);
13324 /* A comma-separated list of registers and/or
13325 dash-separated contiguous ranges including
13326 at least one of ra and a set of one or more
13327 registers starting at s0 up to s7 and then
13328 s8 which have to be consecutive, e.g.:
13336 and any permutations of these. */
13337 unsigned int reglist;
13341 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13344 if ((reglist & 0x3f00ffff) != 0)
13347 ra = (reglist >> 27) & 0x10;
13348 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13350 if ((reglist & -reglist) != reglist)
13353 imm = (ffs (reglist) - 1) | ra;
13354 INSERT_OPERAND (1, RT, *ip, imm);
13355 imm_expr.X_op = O_absent;
13359 case '|': /* 4-bit trap code. */
13360 gas_assert (mips_opts.micromips);
13361 my_getExpression (&imm_expr, s);
13362 check_absolute_expr (ip, &imm_expr);
13363 if ((unsigned long) imm_expr.X_add_number
13364 > MICROMIPSOP_MASK_TRAP)
13365 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13366 (unsigned long) imm_expr.X_add_number,
13367 ip->insn_mo->name);
13368 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13369 imm_expr.X_op = O_absent;
13374 as_bad (_("Bad char = '%c'\n"), *args);
13379 /* Args don't match. */
13381 insn_error = _("Illegal operands");
13382 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13387 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13389 gas_assert (firstinsn);
13390 need_delay_slot_ok = FALSE;
13399 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13401 /* This routine assembles an instruction into its binary format when
13402 assembling for the mips16. As a side effect, it sets one of the
13403 global variables imm_reloc or offset_reloc to the type of relocation
13404 to do if one of the operands is an address expression. It also sets
13405 forced_insn_length to the resulting instruction size in bytes if the
13406 user explicitly requested a small or extended instruction. */
13409 mips16_ip (char *str, struct mips_cl_insn *ip)
13413 struct mips_opcode *insn;
13415 unsigned int regno;
13416 unsigned int lastregno = 0;
13422 forced_insn_length = 0;
13424 for (s = str; ISLOWER (*s); ++s)
13436 if (s[1] == 't' && s[2] == ' ')
13439 forced_insn_length = 2;
13443 else if (s[1] == 'e' && s[2] == ' ')
13446 forced_insn_length = 4;
13450 /* Fall through. */
13452 insn_error = _("unknown opcode");
13456 if (mips_opts.noautoextend && !forced_insn_length)
13457 forced_insn_length = 2;
13459 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13461 insn_error = _("unrecognized opcode");
13470 gas_assert (strcmp (insn->name, str) == 0);
13472 ok = is_opcode_valid_16 (insn);
13475 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13476 && strcmp (insn->name, insn[1].name) == 0)
13485 static char buf[100];
13487 _("Opcode not supported on this processor: %s (%s)"),
13488 mips_cpu_info_from_arch (mips_opts.arch)->name,
13489 mips_cpu_info_from_isa (mips_opts.isa)->name);
13496 create_insn (ip, insn);
13497 imm_expr.X_op = O_absent;
13498 imm_reloc[0] = BFD_RELOC_UNUSED;
13499 imm_reloc[1] = BFD_RELOC_UNUSED;
13500 imm_reloc[2] = BFD_RELOC_UNUSED;
13501 imm2_expr.X_op = O_absent;
13502 offset_expr.X_op = O_absent;
13503 offset_reloc[0] = BFD_RELOC_UNUSED;
13504 offset_reloc[1] = BFD_RELOC_UNUSED;
13505 offset_reloc[2] = BFD_RELOC_UNUSED;
13506 for (args = insn->args; 1; ++args)
13513 /* In this switch statement we call break if we did not find
13514 a match, continue if we did find a match, or return if we
13525 /* Stuff the immediate value in now, if we can. */
13526 if (imm_expr.X_op == O_constant
13527 && *imm_reloc > BFD_RELOC_UNUSED
13528 && insn->pinfo != INSN_MACRO
13529 && calculate_reloc (*offset_reloc,
13530 imm_expr.X_add_number, &value))
13532 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13533 *offset_reloc, value, forced_insn_length,
13535 imm_expr.X_op = O_absent;
13536 *imm_reloc = BFD_RELOC_UNUSED;
13537 *offset_reloc = BFD_RELOC_UNUSED;
13551 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13554 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13570 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13572 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13576 /* Fall through. */
13587 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13589 if (c == 'v' || c == 'w')
13592 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13594 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13605 if (c == 'v' || c == 'w')
13607 regno = mips16_to_32_reg_map[lastregno];
13621 regno = mips32_to_16_reg_map[regno];
13626 regno = ILLEGAL_REG;
13631 regno = ILLEGAL_REG;
13636 regno = ILLEGAL_REG;
13641 if (regno == AT && mips_opts.at)
13643 if (mips_opts.at == ATREG)
13644 as_warn (_("used $at without \".set noat\""));
13646 as_warn (_("used $%u with \".set at=$%u\""),
13647 regno, mips_opts.at);
13655 if (regno == ILLEGAL_REG)
13662 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13666 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13669 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13672 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13678 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13681 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13682 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13692 if (strncmp (s, "$pc", 3) == 0)
13709 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13712 if (imm_expr.X_op != O_constant)
13714 forced_insn_length = 4;
13715 ip->insn_opcode |= MIPS16_EXTEND;
13719 /* We need to relax this instruction. */
13720 *offset_reloc = *imm_reloc;
13721 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13726 *imm_reloc = BFD_RELOC_UNUSED;
13727 /* Fall through. */
13734 my_getExpression (&imm_expr, s);
13735 if (imm_expr.X_op == O_register)
13737 /* What we thought was an expression turned out to
13740 if (s[0] == '(' && args[1] == '(')
13742 /* It looks like the expression was omitted
13743 before a register indirection, which means
13744 that the expression is implicitly zero. We
13745 still set up imm_expr, so that we handle
13746 explicit extensions correctly. */
13747 imm_expr.X_op = O_constant;
13748 imm_expr.X_add_number = 0;
13749 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13756 /* We need to relax this instruction. */
13757 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13766 /* We use offset_reloc rather than imm_reloc for the PC
13767 relative operands. This lets macros with both
13768 immediate and address operands work correctly. */
13769 my_getExpression (&offset_expr, s);
13771 if (offset_expr.X_op == O_register)
13774 /* We need to relax this instruction. */
13775 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13779 case '6': /* break code */
13780 my_getExpression (&imm_expr, s);
13781 check_absolute_expr (ip, &imm_expr);
13782 if ((unsigned long) imm_expr.X_add_number > 63)
13783 as_warn (_("Invalid value for `%s' (%lu)"),
13785 (unsigned long) imm_expr.X_add_number);
13786 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13787 imm_expr.X_op = O_absent;
13791 case 'a': /* 26 bit address */
13792 my_getExpression (&offset_expr, s);
13794 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13795 ip->insn_opcode <<= 16;
13798 case 'l': /* register list for entry macro */
13799 case 'L': /* register list for exit macro */
13809 unsigned int freg, reg1, reg2;
13811 while (*s == ' ' || *s == ',')
13813 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13815 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13819 as_bad (_("can't parse register list"));
13829 if (!reg_lookup (&s, freg ? RTYPE_FPU
13830 : (RTYPE_GP | RTYPE_NUM), ®2))
13832 as_bad (_("invalid register list"));
13836 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13838 mask &= ~ (7 << 3);
13841 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13843 mask &= ~ (7 << 3);
13846 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13847 mask |= (reg2 - 3) << 3;
13848 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13849 mask |= (reg2 - 15) << 1;
13850 else if (reg1 == RA && reg2 == RA)
13854 as_bad (_("invalid register list"));
13858 /* The mask is filled in in the opcode table for the
13859 benefit of the disassembler. We remove it before
13860 applying the actual mask. */
13861 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13862 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13866 case 'm': /* Register list for save insn. */
13867 case 'M': /* Register list for restore insn. */
13869 int opcode = ip->insn_opcode;
13870 int framesz = 0, seen_framesz = 0;
13871 int nargs = 0, statics = 0, sregs = 0;
13875 unsigned int reg1, reg2;
13877 SKIP_SPACE_TABS (s);
13880 SKIP_SPACE_TABS (s);
13882 my_getExpression (&imm_expr, s);
13883 if (imm_expr.X_op == O_constant)
13885 /* Handle the frame size. */
13888 as_bad (_("more than one frame size in list"));
13892 framesz = imm_expr.X_add_number;
13893 imm_expr.X_op = O_absent;
13898 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13900 as_bad (_("can't parse register list"));
13912 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13915 as_bad (_("can't parse register list"));
13920 while (reg1 <= reg2)
13922 if (reg1 >= 4 && reg1 <= 7)
13926 nargs |= 1 << (reg1 - 4);
13928 /* statics $a0-$a3 */
13929 statics |= 1 << (reg1 - 4);
13931 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13934 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13936 else if (reg1 == 31)
13938 /* Add $ra to insn. */
13943 as_bad (_("unexpected register in list"));
13951 /* Encode args/statics combination. */
13952 if (nargs & statics)
13953 as_bad (_("arg/static registers overlap"));
13954 else if (nargs == 0xf)
13955 /* All $a0-$a3 are args. */
13956 opcode |= MIPS16_ALL_ARGS << 16;
13957 else if (statics == 0xf)
13958 /* All $a0-$a3 are statics. */
13959 opcode |= MIPS16_ALL_STATICS << 16;
13962 int narg = 0, nstat = 0;
13964 /* Count arg registers. */
13965 while (nargs & 0x1)
13971 as_bad (_("invalid arg register list"));
13973 /* Count static registers. */
13974 while (statics & 0x8)
13976 statics = (statics << 1) & 0xf;
13980 as_bad (_("invalid static register list"));
13982 /* Encode args/statics. */
13983 opcode |= ((narg << 2) | nstat) << 16;
13986 /* Encode $s0/$s1. */
13987 if (sregs & (1 << 0)) /* $s0 */
13989 if (sregs & (1 << 1)) /* $s1 */
13995 /* Count regs $s2-$s8. */
14003 as_bad (_("invalid static register list"));
14004 /* Encode $s2-$s8. */
14005 opcode |= nsreg << 24;
14008 /* Encode frame size. */
14010 as_bad (_("missing frame size"));
14011 else if ((framesz & 7) != 0 || framesz < 0
14012 || framesz > 0xff * 8)
14013 as_bad (_("invalid frame size"));
14014 else if (framesz != 128 || (opcode >> 16) != 0)
14017 opcode |= (((framesz & 0xf0) << 16)
14018 | (framesz & 0x0f));
14021 /* Finally build the instruction. */
14022 if ((opcode >> 16) != 0 || framesz == 0)
14023 opcode |= MIPS16_EXTEND;
14024 ip->insn_opcode = opcode;
14028 case 'e': /* extend code */
14029 my_getExpression (&imm_expr, s);
14030 check_absolute_expr (ip, &imm_expr);
14031 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14033 as_warn (_("Invalid value for `%s' (%lu)"),
14035 (unsigned long) imm_expr.X_add_number);
14036 imm_expr.X_add_number &= 0x7ff;
14038 ip->insn_opcode |= imm_expr.X_add_number;
14039 imm_expr.X_op = O_absent;
14049 /* Args don't match. */
14050 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14051 strcmp (insn->name, insn[1].name) == 0)
14058 insn_error = _("illegal operands");
14064 /* This structure holds information we know about a mips16 immediate
14067 struct mips16_immed_operand
14069 /* The type code used in the argument string in the opcode table. */
14071 /* The number of bits in the short form of the opcode. */
14073 /* The number of bits in the extended form of the opcode. */
14075 /* The amount by which the short form is shifted when it is used;
14076 for example, the sw instruction has a shift count of 2. */
14078 /* The amount by which the short form is shifted when it is stored
14079 into the instruction code. */
14081 /* Non-zero if the short form is unsigned. */
14083 /* Non-zero if the extended form is unsigned. */
14085 /* Non-zero if the value is PC relative. */
14089 /* The mips16 immediate operand types. */
14091 static const struct mips16_immed_operand mips16_immed_operands[] =
14093 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14094 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14095 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14096 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14097 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14098 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14099 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14100 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14101 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14102 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14103 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14104 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14105 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14106 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14107 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14108 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14109 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14110 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14111 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14112 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14113 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14116 #define MIPS16_NUM_IMMED \
14117 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14119 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14120 NBITS is the number of significant bits in VAL. */
14122 static unsigned long
14123 mips16_immed_extend (offsetT val, unsigned int nbits)
14128 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14131 else if (nbits == 15)
14133 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14138 extval = ((val & 0x1f) << 6) | (val & 0x20);
14141 return (extval << 16) | val;
14144 /* Install immediate value VAL into MIPS16 instruction *INSN,
14145 extending it if necessary. The instruction in *INSN may
14146 already be extended.
14148 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14149 if none. In the former case, VAL is a 16-bit number with no
14150 defined signedness.
14152 TYPE is the type of the immediate field. USER_INSN_LENGTH
14153 is the length that the user requested, or 0 if none. */
14156 mips16_immed (char *file, unsigned int line, int type,
14157 bfd_reloc_code_real_type reloc, offsetT val,
14158 unsigned int user_insn_length, unsigned long *insn)
14160 const struct mips16_immed_operand *op;
14161 int mintiny, maxtiny;
14163 op = mips16_immed_operands;
14164 while (op->type != type)
14167 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14172 if (type == '<' || type == '>' || type == '[' || type == ']')
14175 maxtiny = 1 << op->nbits;
14180 maxtiny = (1 << op->nbits) - 1;
14182 if (reloc != BFD_RELOC_UNUSED)
14187 mintiny = - (1 << (op->nbits - 1));
14188 maxtiny = (1 << (op->nbits - 1)) - 1;
14189 if (reloc != BFD_RELOC_UNUSED)
14190 val = SEXT_16BIT (val);
14193 /* Branch offsets have an implicit 0 in the lowest bit. */
14194 if (type == 'p' || type == 'q')
14197 if ((val & ((1 << op->shift) - 1)) != 0
14198 || val < (mintiny << op->shift)
14199 || val > (maxtiny << op->shift))
14201 /* We need an extended instruction. */
14202 if (user_insn_length == 2)
14203 as_bad_where (file, line, _("invalid unextended operand value"));
14205 *insn |= MIPS16_EXTEND;
14207 else if (user_insn_length == 4)
14209 /* The operand doesn't force an unextended instruction to be extended.
14210 Warn if the user wanted an extended instruction anyway. */
14211 *insn |= MIPS16_EXTEND;
14212 as_warn_where (file, line,
14213 _("extended operand requested but not required"));
14216 if (mips16_opcode_length (*insn) == 2)
14220 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14221 insnval <<= op->op_shift;
14226 long minext, maxext;
14228 if (reloc == BFD_RELOC_UNUSED)
14233 maxext = (1 << op->extbits) - 1;
14237 minext = - (1 << (op->extbits - 1));
14238 maxext = (1 << (op->extbits - 1)) - 1;
14240 if (val < minext || val > maxext)
14241 as_bad_where (file, line,
14242 _("operand value out of range for instruction"));
14245 *insn |= mips16_immed_extend (val, op->extbits);
14249 struct percent_op_match
14252 bfd_reloc_code_real_type reloc;
14255 static const struct percent_op_match mips_percent_op[] =
14257 {"%lo", BFD_RELOC_LO16},
14259 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14260 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14261 {"%call16", BFD_RELOC_MIPS_CALL16},
14262 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14263 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14264 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14265 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14266 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14267 {"%got", BFD_RELOC_MIPS_GOT16},
14268 {"%gp_rel", BFD_RELOC_GPREL16},
14269 {"%half", BFD_RELOC_16},
14270 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14271 {"%higher", BFD_RELOC_MIPS_HIGHER},
14272 {"%neg", BFD_RELOC_MIPS_SUB},
14273 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14274 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14275 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14276 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14277 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14278 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14279 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14281 {"%hi", BFD_RELOC_HI16_S}
14284 static const struct percent_op_match mips16_percent_op[] =
14286 {"%lo", BFD_RELOC_MIPS16_LO16},
14287 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14288 {"%got", BFD_RELOC_MIPS16_GOT16},
14289 {"%call16", BFD_RELOC_MIPS16_CALL16},
14290 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14291 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14292 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14293 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14294 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14295 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14296 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14297 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14301 /* Return true if *STR points to a relocation operator. When returning true,
14302 move *STR over the operator and store its relocation code in *RELOC.
14303 Leave both *STR and *RELOC alone when returning false. */
14306 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14308 const struct percent_op_match *percent_op;
14311 if (mips_opts.mips16)
14313 percent_op = mips16_percent_op;
14314 limit = ARRAY_SIZE (mips16_percent_op);
14318 percent_op = mips_percent_op;
14319 limit = ARRAY_SIZE (mips_percent_op);
14322 for (i = 0; i < limit; i++)
14323 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14325 int len = strlen (percent_op[i].str);
14327 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14330 *str += strlen (percent_op[i].str);
14331 *reloc = percent_op[i].reloc;
14333 /* Check whether the output BFD supports this relocation.
14334 If not, issue an error and fall back on something safe. */
14335 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14337 as_bad (_("relocation %s isn't supported by the current ABI"),
14338 percent_op[i].str);
14339 *reloc = BFD_RELOC_UNUSED;
14347 /* Parse string STR as a 16-bit relocatable operand. Store the
14348 expression in *EP and the relocations in the array starting
14349 at RELOC. Return the number of relocation operators used.
14351 On exit, EXPR_END points to the first character after the expression. */
14354 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14357 bfd_reloc_code_real_type reversed_reloc[3];
14358 size_t reloc_index, i;
14359 int crux_depth, str_depth;
14362 /* Search for the start of the main expression, recoding relocations
14363 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14364 of the main expression and with CRUX_DEPTH containing the number
14365 of open brackets at that point. */
14372 crux_depth = str_depth;
14374 /* Skip over whitespace and brackets, keeping count of the number
14376 while (*str == ' ' || *str == '\t' || *str == '(')
14381 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14382 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14384 my_getExpression (ep, crux);
14387 /* Match every open bracket. */
14388 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14392 if (crux_depth > 0)
14393 as_bad (_("unclosed '('"));
14397 if (reloc_index != 0)
14399 prev_reloc_op_frag = frag_now;
14400 for (i = 0; i < reloc_index; i++)
14401 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14404 return reloc_index;
14408 my_getExpression (expressionS *ep, char *str)
14412 save_in = input_line_pointer;
14413 input_line_pointer = str;
14415 expr_end = input_line_pointer;
14416 input_line_pointer = save_in;
14420 md_atof (int type, char *litP, int *sizeP)
14422 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14426 md_number_to_chars (char *buf, valueT val, int n)
14428 if (target_big_endian)
14429 number_to_chars_bigendian (buf, val, n);
14431 number_to_chars_littleendian (buf, val, n);
14435 static int support_64bit_objects(void)
14437 const char **list, **l;
14440 list = bfd_target_list ();
14441 for (l = list; *l != NULL; l++)
14442 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14443 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14445 yes = (*l != NULL);
14449 #endif /* OBJ_ELF */
14451 const char *md_shortopts = "O::g::G:";
14455 OPTION_MARCH = OPTION_MD_BASE,
14477 OPTION_NO_SMARTMIPS,
14481 OPTION_NO_MICROMIPS,
14484 OPTION_COMPAT_ARCH_BASE,
14493 OPTION_M7000_HILO_FIX,
14494 OPTION_MNO_7000_HILO_FIX,
14497 OPTION_FIX_LOONGSON2F_JUMP,
14498 OPTION_NO_FIX_LOONGSON2F_JUMP,
14499 OPTION_FIX_LOONGSON2F_NOP,
14500 OPTION_NO_FIX_LOONGSON2F_NOP,
14502 OPTION_NO_FIX_VR4120,
14504 OPTION_NO_FIX_VR4130,
14505 OPTION_FIX_CN63XXP1,
14506 OPTION_NO_FIX_CN63XXP1,
14513 OPTION_CONSTRUCT_FLOATS,
14514 OPTION_NO_CONSTRUCT_FLOATS,
14517 OPTION_RELAX_BRANCH,
14518 OPTION_NO_RELAX_BRANCH,
14525 OPTION_SINGLE_FLOAT,
14526 OPTION_DOUBLE_FLOAT,
14529 OPTION_CALL_SHARED,
14530 OPTION_CALL_NONPIC,
14540 OPTION_MVXWORKS_PIC,
14541 #endif /* OBJ_ELF */
14545 struct option md_longopts[] =
14547 /* Options which specify architecture. */
14548 {"march", required_argument, NULL, OPTION_MARCH},
14549 {"mtune", required_argument, NULL, OPTION_MTUNE},
14550 {"mips0", no_argument, NULL, OPTION_MIPS1},
14551 {"mips1", no_argument, NULL, OPTION_MIPS1},
14552 {"mips2", no_argument, NULL, OPTION_MIPS2},
14553 {"mips3", no_argument, NULL, OPTION_MIPS3},
14554 {"mips4", no_argument, NULL, OPTION_MIPS4},
14555 {"mips5", no_argument, NULL, OPTION_MIPS5},
14556 {"mips32", no_argument, NULL, OPTION_MIPS32},
14557 {"mips64", no_argument, NULL, OPTION_MIPS64},
14558 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14559 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14561 /* Options which specify Application Specific Extensions (ASEs). */
14562 {"mips16", no_argument, NULL, OPTION_MIPS16},
14563 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14564 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14565 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14566 {"mdmx", no_argument, NULL, OPTION_MDMX},
14567 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14568 {"mdsp", no_argument, NULL, OPTION_DSP},
14569 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14570 {"mmt", no_argument, NULL, OPTION_MT},
14571 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14572 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14573 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14574 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14575 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14576 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14577 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14578 {"mmcu", no_argument, NULL, OPTION_MCU},
14579 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14581 /* Old-style architecture options. Don't add more of these. */
14582 {"m4650", no_argument, NULL, OPTION_M4650},
14583 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14584 {"m4010", no_argument, NULL, OPTION_M4010},
14585 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14586 {"m4100", no_argument, NULL, OPTION_M4100},
14587 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14588 {"m3900", no_argument, NULL, OPTION_M3900},
14589 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14591 /* Options which enable bug fixes. */
14592 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14593 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14594 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14595 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14596 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14597 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14598 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14599 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14600 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14601 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14602 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14603 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14604 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14605 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14606 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14608 /* Miscellaneous options. */
14609 {"trap", no_argument, NULL, OPTION_TRAP},
14610 {"no-break", no_argument, NULL, OPTION_TRAP},
14611 {"break", no_argument, NULL, OPTION_BREAK},
14612 {"no-trap", no_argument, NULL, OPTION_BREAK},
14613 {"EB", no_argument, NULL, OPTION_EB},
14614 {"EL", no_argument, NULL, OPTION_EL},
14615 {"mfp32", no_argument, NULL, OPTION_FP32},
14616 {"mgp32", no_argument, NULL, OPTION_GP32},
14617 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14618 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14619 {"mfp64", no_argument, NULL, OPTION_FP64},
14620 {"mgp64", no_argument, NULL, OPTION_GP64},
14621 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14622 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14623 {"mshared", no_argument, NULL, OPTION_MSHARED},
14624 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14625 {"msym32", no_argument, NULL, OPTION_MSYM32},
14626 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14627 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14628 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14629 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14630 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14632 /* Strictly speaking this next option is ELF specific,
14633 but we allow it for other ports as well in order to
14634 make testing easier. */
14635 {"32", no_argument, NULL, OPTION_32},
14637 /* ELF-specific options. */
14639 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14640 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14641 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14642 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14643 {"xgot", no_argument, NULL, OPTION_XGOT},
14644 {"mabi", required_argument, NULL, OPTION_MABI},
14645 {"n32", no_argument, NULL, OPTION_N32},
14646 {"64", no_argument, NULL, OPTION_64},
14647 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14648 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14649 {"mpdr", no_argument, NULL, OPTION_PDR},
14650 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14651 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14652 #endif /* OBJ_ELF */
14654 {NULL, no_argument, NULL, 0}
14656 size_t md_longopts_size = sizeof (md_longopts);
14658 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14659 NEW_VALUE. Warn if another value was already specified. Note:
14660 we have to defer parsing the -march and -mtune arguments in order
14661 to handle 'from-abi' correctly, since the ABI might be specified
14662 in a later argument. */
14665 mips_set_option_string (const char **string_ptr, const char *new_value)
14667 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14668 as_warn (_("A different %s was already specified, is now %s"),
14669 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14672 *string_ptr = new_value;
14676 md_parse_option (int c, char *arg)
14680 case OPTION_CONSTRUCT_FLOATS:
14681 mips_disable_float_construction = 0;
14684 case OPTION_NO_CONSTRUCT_FLOATS:
14685 mips_disable_float_construction = 1;
14697 target_big_endian = 1;
14701 target_big_endian = 0;
14707 else if (arg[0] == '0')
14709 else if (arg[0] == '1')
14719 mips_debug = atoi (arg);
14723 file_mips_isa = ISA_MIPS1;
14727 file_mips_isa = ISA_MIPS2;
14731 file_mips_isa = ISA_MIPS3;
14735 file_mips_isa = ISA_MIPS4;
14739 file_mips_isa = ISA_MIPS5;
14742 case OPTION_MIPS32:
14743 file_mips_isa = ISA_MIPS32;
14746 case OPTION_MIPS32R2:
14747 file_mips_isa = ISA_MIPS32R2;
14750 case OPTION_MIPS64R2:
14751 file_mips_isa = ISA_MIPS64R2;
14754 case OPTION_MIPS64:
14755 file_mips_isa = ISA_MIPS64;
14759 mips_set_option_string (&mips_tune_string, arg);
14763 mips_set_option_string (&mips_arch_string, arg);
14767 mips_set_option_string (&mips_arch_string, "4650");
14768 mips_set_option_string (&mips_tune_string, "4650");
14771 case OPTION_NO_M4650:
14775 mips_set_option_string (&mips_arch_string, "4010");
14776 mips_set_option_string (&mips_tune_string, "4010");
14779 case OPTION_NO_M4010:
14783 mips_set_option_string (&mips_arch_string, "4100");
14784 mips_set_option_string (&mips_tune_string, "4100");
14787 case OPTION_NO_M4100:
14791 mips_set_option_string (&mips_arch_string, "3900");
14792 mips_set_option_string (&mips_tune_string, "3900");
14795 case OPTION_NO_M3900:
14799 mips_opts.ase_mdmx = 1;
14802 case OPTION_NO_MDMX:
14803 mips_opts.ase_mdmx = 0;
14807 mips_opts.ase_dsp = 1;
14808 mips_opts.ase_dspr2 = 0;
14811 case OPTION_NO_DSP:
14812 mips_opts.ase_dsp = 0;
14813 mips_opts.ase_dspr2 = 0;
14817 mips_opts.ase_dspr2 = 1;
14818 mips_opts.ase_dsp = 1;
14821 case OPTION_NO_DSPR2:
14822 mips_opts.ase_dspr2 = 0;
14823 mips_opts.ase_dsp = 0;
14827 mips_opts.ase_mt = 1;
14831 mips_opts.ase_mt = 0;
14835 mips_opts.ase_mcu = 1;
14838 case OPTION_NO_MCU:
14839 mips_opts.ase_mcu = 0;
14842 case OPTION_MICROMIPS:
14843 if (mips_opts.mips16 == 1)
14845 as_bad (_("-mmicromips cannot be used with -mips16"));
14848 mips_opts.micromips = 1;
14849 mips_no_prev_insn ();
14852 case OPTION_NO_MICROMIPS:
14853 mips_opts.micromips = 0;
14854 mips_no_prev_insn ();
14857 case OPTION_MIPS16:
14858 if (mips_opts.micromips == 1)
14860 as_bad (_("-mips16 cannot be used with -micromips"));
14863 mips_opts.mips16 = 1;
14864 mips_no_prev_insn ();
14867 case OPTION_NO_MIPS16:
14868 mips_opts.mips16 = 0;
14869 mips_no_prev_insn ();
14872 case OPTION_MIPS3D:
14873 mips_opts.ase_mips3d = 1;
14876 case OPTION_NO_MIPS3D:
14877 mips_opts.ase_mips3d = 0;
14880 case OPTION_SMARTMIPS:
14881 mips_opts.ase_smartmips = 1;
14884 case OPTION_NO_SMARTMIPS:
14885 mips_opts.ase_smartmips = 0;
14888 case OPTION_FIX_24K:
14892 case OPTION_NO_FIX_24K:
14896 case OPTION_FIX_LOONGSON2F_JUMP:
14897 mips_fix_loongson2f_jump = TRUE;
14900 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14901 mips_fix_loongson2f_jump = FALSE;
14904 case OPTION_FIX_LOONGSON2F_NOP:
14905 mips_fix_loongson2f_nop = TRUE;
14908 case OPTION_NO_FIX_LOONGSON2F_NOP:
14909 mips_fix_loongson2f_nop = FALSE;
14912 case OPTION_FIX_VR4120:
14913 mips_fix_vr4120 = 1;
14916 case OPTION_NO_FIX_VR4120:
14917 mips_fix_vr4120 = 0;
14920 case OPTION_FIX_VR4130:
14921 mips_fix_vr4130 = 1;
14924 case OPTION_NO_FIX_VR4130:
14925 mips_fix_vr4130 = 0;
14928 case OPTION_FIX_CN63XXP1:
14929 mips_fix_cn63xxp1 = TRUE;
14932 case OPTION_NO_FIX_CN63XXP1:
14933 mips_fix_cn63xxp1 = FALSE;
14936 case OPTION_RELAX_BRANCH:
14937 mips_relax_branch = 1;
14940 case OPTION_NO_RELAX_BRANCH:
14941 mips_relax_branch = 0;
14944 case OPTION_MSHARED:
14945 mips_in_shared = TRUE;
14948 case OPTION_MNO_SHARED:
14949 mips_in_shared = FALSE;
14952 case OPTION_MSYM32:
14953 mips_opts.sym32 = TRUE;
14956 case OPTION_MNO_SYM32:
14957 mips_opts.sym32 = FALSE;
14961 /* When generating ELF code, we permit -KPIC and -call_shared to
14962 select SVR4_PIC, and -non_shared to select no PIC. This is
14963 intended to be compatible with Irix 5. */
14964 case OPTION_CALL_SHARED:
14967 as_bad (_("-call_shared is supported only for ELF format"));
14970 mips_pic = SVR4_PIC;
14971 mips_abicalls = TRUE;
14974 case OPTION_CALL_NONPIC:
14977 as_bad (_("-call_nonpic is supported only for ELF format"));
14981 mips_abicalls = TRUE;
14984 case OPTION_NON_SHARED:
14987 as_bad (_("-non_shared is supported only for ELF format"));
14991 mips_abicalls = FALSE;
14994 /* The -xgot option tells the assembler to use 32 bit offsets
14995 when accessing the got in SVR4_PIC mode. It is for Irix
15000 #endif /* OBJ_ELF */
15003 g_switch_value = atoi (arg);
15007 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15011 mips_abi = O32_ABI;
15012 /* We silently ignore -32 for non-ELF targets. This greatly
15013 simplifies the construction of the MIPS GAS test cases. */
15020 as_bad (_("-n32 is supported for ELF format only"));
15023 mips_abi = N32_ABI;
15029 as_bad (_("-64 is supported for ELF format only"));
15032 mips_abi = N64_ABI;
15033 if (!support_64bit_objects())
15034 as_fatal (_("No compiled in support for 64 bit object file format"));
15036 #endif /* OBJ_ELF */
15039 file_mips_gp32 = 1;
15043 file_mips_gp32 = 0;
15047 file_mips_fp32 = 1;
15051 file_mips_fp32 = 0;
15054 case OPTION_SINGLE_FLOAT:
15055 file_mips_single_float = 1;
15058 case OPTION_DOUBLE_FLOAT:
15059 file_mips_single_float = 0;
15062 case OPTION_SOFT_FLOAT:
15063 file_mips_soft_float = 1;
15066 case OPTION_HARD_FLOAT:
15067 file_mips_soft_float = 0;
15074 as_bad (_("-mabi is supported for ELF format only"));
15077 if (strcmp (arg, "32") == 0)
15078 mips_abi = O32_ABI;
15079 else if (strcmp (arg, "o64") == 0)
15080 mips_abi = O64_ABI;
15081 else if (strcmp (arg, "n32") == 0)
15082 mips_abi = N32_ABI;
15083 else if (strcmp (arg, "64") == 0)
15085 mips_abi = N64_ABI;
15086 if (! support_64bit_objects())
15087 as_fatal (_("No compiled in support for 64 bit object file "
15090 else if (strcmp (arg, "eabi") == 0)
15091 mips_abi = EABI_ABI;
15094 as_fatal (_("invalid abi -mabi=%s"), arg);
15098 #endif /* OBJ_ELF */
15100 case OPTION_M7000_HILO_FIX:
15101 mips_7000_hilo_fix = TRUE;
15104 case OPTION_MNO_7000_HILO_FIX:
15105 mips_7000_hilo_fix = FALSE;
15109 case OPTION_MDEBUG:
15110 mips_flag_mdebug = TRUE;
15113 case OPTION_NO_MDEBUG:
15114 mips_flag_mdebug = FALSE;
15118 mips_flag_pdr = TRUE;
15121 case OPTION_NO_PDR:
15122 mips_flag_pdr = FALSE;
15125 case OPTION_MVXWORKS_PIC:
15126 mips_pic = VXWORKS_PIC;
15128 #endif /* OBJ_ELF */
15134 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15139 /* Set up globals to generate code for the ISA or processor
15140 described by INFO. */
15143 mips_set_architecture (const struct mips_cpu_info *info)
15147 file_mips_arch = info->cpu;
15148 mips_opts.arch = info->cpu;
15149 mips_opts.isa = info->isa;
15154 /* Likewise for tuning. */
15157 mips_set_tune (const struct mips_cpu_info *info)
15160 mips_tune = info->cpu;
15165 mips_after_parse_args (void)
15167 const struct mips_cpu_info *arch_info = 0;
15168 const struct mips_cpu_info *tune_info = 0;
15170 /* GP relative stuff not working for PE */
15171 if (strncmp (TARGET_OS, "pe", 2) == 0)
15173 if (g_switch_seen && g_switch_value != 0)
15174 as_bad (_("-G not supported in this configuration."));
15175 g_switch_value = 0;
15178 if (mips_abi == NO_ABI)
15179 mips_abi = MIPS_DEFAULT_ABI;
15181 /* The following code determines the architecture and register size.
15182 Similar code was added to GCC 3.3 (see override_options() in
15183 config/mips/mips.c). The GAS and GCC code should be kept in sync
15184 as much as possible. */
15186 if (mips_arch_string != 0)
15187 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15189 if (file_mips_isa != ISA_UNKNOWN)
15191 /* Handle -mipsN. At this point, file_mips_isa contains the
15192 ISA level specified by -mipsN, while arch_info->isa contains
15193 the -march selection (if any). */
15194 if (arch_info != 0)
15196 /* -march takes precedence over -mipsN, since it is more descriptive.
15197 There's no harm in specifying both as long as the ISA levels
15199 if (file_mips_isa != arch_info->isa)
15200 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15201 mips_cpu_info_from_isa (file_mips_isa)->name,
15202 mips_cpu_info_from_isa (arch_info->isa)->name);
15205 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15208 if (arch_info == 0)
15210 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15211 gas_assert (arch_info);
15214 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15215 as_bad (_("-march=%s is not compatible with the selected ABI"),
15218 mips_set_architecture (arch_info);
15220 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15221 if (mips_tune_string != 0)
15222 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15224 if (tune_info == 0)
15225 mips_set_tune (arch_info);
15227 mips_set_tune (tune_info);
15229 if (file_mips_gp32 >= 0)
15231 /* The user specified the size of the integer registers. Make sure
15232 it agrees with the ABI and ISA. */
15233 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15234 as_bad (_("-mgp64 used with a 32-bit processor"));
15235 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15236 as_bad (_("-mgp32 used with a 64-bit ABI"));
15237 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15238 as_bad (_("-mgp64 used with a 32-bit ABI"));
15242 /* Infer the integer register size from the ABI and processor.
15243 Restrict ourselves to 32-bit registers if that's all the
15244 processor has, or if the ABI cannot handle 64-bit registers. */
15245 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15246 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15249 switch (file_mips_fp32)
15253 /* No user specified float register size.
15254 ??? GAS treats single-float processors as though they had 64-bit
15255 float registers (although it complains when double-precision
15256 instructions are used). As things stand, saying they have 32-bit
15257 registers would lead to spurious "register must be even" messages.
15258 So here we assume float registers are never smaller than the
15260 if (file_mips_gp32 == 0)
15261 /* 64-bit integer registers implies 64-bit float registers. */
15262 file_mips_fp32 = 0;
15263 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15264 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15265 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15266 file_mips_fp32 = 0;
15268 /* 32-bit float registers. */
15269 file_mips_fp32 = 1;
15272 /* The user specified the size of the float registers. Check if it
15273 agrees with the ABI and ISA. */
15275 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15276 as_bad (_("-mfp64 used with a 32-bit fpu"));
15277 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15278 && !ISA_HAS_MXHC1 (mips_opts.isa))
15279 as_warn (_("-mfp64 used with a 32-bit ABI"));
15282 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15283 as_warn (_("-mfp32 used with a 64-bit ABI"));
15287 /* End of GCC-shared inference code. */
15289 /* This flag is set when we have a 64-bit capable CPU but use only
15290 32-bit wide registers. Note that EABI does not use it. */
15291 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15292 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15293 || mips_abi == O32_ABI))
15294 mips_32bitmode = 1;
15296 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15297 as_bad (_("trap exception not supported at ISA 1"));
15299 /* If the selected architecture includes support for ASEs, enable
15300 generation of code for them. */
15301 if (mips_opts.mips16 == -1)
15302 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15303 if (mips_opts.micromips == -1)
15304 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15305 if (mips_opts.ase_mips3d == -1)
15306 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15307 && file_mips_fp32 == 0) ? 1 : 0;
15308 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15309 as_bad (_("-mfp32 used with -mips3d"));
15311 if (mips_opts.ase_mdmx == -1)
15312 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15313 && file_mips_fp32 == 0) ? 1 : 0;
15314 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15315 as_bad (_("-mfp32 used with -mdmx"));
15317 if (mips_opts.ase_smartmips == -1)
15318 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15319 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15320 as_warn (_("%s ISA does not support SmartMIPS"),
15321 mips_cpu_info_from_isa (mips_opts.isa)->name);
15323 if (mips_opts.ase_dsp == -1)
15324 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15325 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15326 as_warn (_("%s ISA does not support DSP ASE"),
15327 mips_cpu_info_from_isa (mips_opts.isa)->name);
15329 if (mips_opts.ase_dspr2 == -1)
15331 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15332 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15334 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15335 as_warn (_("%s ISA does not support DSP R2 ASE"),
15336 mips_cpu_info_from_isa (mips_opts.isa)->name);
15338 if (mips_opts.ase_mt == -1)
15339 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15340 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15341 as_warn (_("%s ISA does not support MT ASE"),
15342 mips_cpu_info_from_isa (mips_opts.isa)->name);
15344 if (mips_opts.ase_mcu == -1)
15345 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15346 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15347 as_warn (_("%s ISA does not support MCU ASE"),
15348 mips_cpu_info_from_isa (mips_opts.isa)->name);
15350 file_mips_isa = mips_opts.isa;
15351 file_ase_mips3d = mips_opts.ase_mips3d;
15352 file_ase_mdmx = mips_opts.ase_mdmx;
15353 file_ase_smartmips = mips_opts.ase_smartmips;
15354 file_ase_dsp = mips_opts.ase_dsp;
15355 file_ase_dspr2 = mips_opts.ase_dspr2;
15356 file_ase_mt = mips_opts.ase_mt;
15357 mips_opts.gp32 = file_mips_gp32;
15358 mips_opts.fp32 = file_mips_fp32;
15359 mips_opts.soft_float = file_mips_soft_float;
15360 mips_opts.single_float = file_mips_single_float;
15362 if (mips_flag_mdebug < 0)
15364 #ifdef OBJ_MAYBE_ECOFF
15365 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15366 mips_flag_mdebug = 1;
15368 #endif /* OBJ_MAYBE_ECOFF */
15369 mips_flag_mdebug = 0;
15374 mips_init_after_args (void)
15376 /* initialize opcodes */
15377 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15378 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15382 md_pcrel_from (fixS *fixP)
15384 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15385 switch (fixP->fx_r_type)
15387 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15388 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15389 /* Return the address of the delay slot. */
15392 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15393 case BFD_RELOC_MICROMIPS_JMP:
15394 case BFD_RELOC_16_PCREL_S2:
15395 case BFD_RELOC_MIPS_JMP:
15396 /* Return the address of the delay slot. */
15400 /* We have no relocation type for PC relative MIPS16 instructions. */
15401 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15402 as_bad_where (fixP->fx_file, fixP->fx_line,
15403 _("PC relative MIPS16 instruction references a different section"));
15408 /* This is called before the symbol table is processed. In order to
15409 work with gcc when using mips-tfile, we must keep all local labels.
15410 However, in other cases, we want to discard them. If we were
15411 called with -g, but we didn't see any debugging information, it may
15412 mean that gcc is smuggling debugging information through to
15413 mips-tfile, in which case we must generate all local labels. */
15416 mips_frob_file_before_adjust (void)
15418 #ifndef NO_ECOFF_DEBUGGING
15419 if (ECOFF_DEBUGGING
15421 && ! ecoff_debugging_seen)
15422 flag_keep_locals = 1;
15426 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15427 the corresponding LO16 reloc. This is called before md_apply_fix and
15428 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15429 relocation operators.
15431 For our purposes, a %lo() expression matches a %got() or %hi()
15434 (a) it refers to the same symbol; and
15435 (b) the offset applied in the %lo() expression is no lower than
15436 the offset applied in the %got() or %hi().
15438 (b) allows us to cope with code like:
15441 lh $4,%lo(foo+2)($4)
15443 ...which is legal on RELA targets, and has a well-defined behaviour
15444 if the user knows that adding 2 to "foo" will not induce a carry to
15447 When several %lo()s match a particular %got() or %hi(), we use the
15448 following rules to distinguish them:
15450 (1) %lo()s with smaller offsets are a better match than %lo()s with
15453 (2) %lo()s with no matching %got() or %hi() are better than those
15454 that already have a matching %got() or %hi().
15456 (3) later %lo()s are better than earlier %lo()s.
15458 These rules are applied in order.
15460 (1) means, among other things, that %lo()s with identical offsets are
15461 chosen if they exist.
15463 (2) means that we won't associate several high-part relocations with
15464 the same low-part relocation unless there's no alternative. Having
15465 several high parts for the same low part is a GNU extension; this rule
15466 allows careful users to avoid it.
15468 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15469 with the last high-part relocation being at the front of the list.
15470 It therefore makes sense to choose the last matching low-part
15471 relocation, all other things being equal. It's also easier
15472 to code that way. */
15475 mips_frob_file (void)
15477 struct mips_hi_fixup *l;
15478 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15480 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15482 segment_info_type *seginfo;
15483 bfd_boolean matched_lo_p;
15484 fixS **hi_pos, **lo_pos, **pos;
15486 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15488 /* If a GOT16 relocation turns out to be against a global symbol,
15489 there isn't supposed to be a matching LO. Ignore %gots against
15490 constants; we'll report an error for those later. */
15491 if (got16_reloc_p (l->fixp->fx_r_type)
15492 && !(l->fixp->fx_addsy
15493 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15496 /* Check quickly whether the next fixup happens to be a matching %lo. */
15497 if (fixup_has_matching_lo_p (l->fixp))
15500 seginfo = seg_info (l->seg);
15502 /* Set HI_POS to the position of this relocation in the chain.
15503 Set LO_POS to the position of the chosen low-part relocation.
15504 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15505 relocation that matches an immediately-preceding high-part
15509 matched_lo_p = FALSE;
15510 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15512 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15514 if (*pos == l->fixp)
15517 if ((*pos)->fx_r_type == looking_for_rtype
15518 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15519 && (*pos)->fx_offset >= l->fixp->fx_offset
15521 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15523 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15526 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15527 && fixup_has_matching_lo_p (*pos));
15530 /* If we found a match, remove the high-part relocation from its
15531 current position and insert it before the low-part relocation.
15532 Make the offsets match so that fixup_has_matching_lo_p()
15535 We don't warn about unmatched high-part relocations since some
15536 versions of gcc have been known to emit dead "lui ...%hi(...)"
15538 if (lo_pos != NULL)
15540 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15541 if (l->fixp->fx_next != *lo_pos)
15543 *hi_pos = l->fixp->fx_next;
15544 l->fixp->fx_next = *lo_pos;
15552 mips_force_relocation (fixS *fixp)
15554 if (generic_force_reloc (fixp))
15557 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15558 so that the linker relaxation can update targets. */
15559 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15560 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15561 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15567 /* Read the instruction associated with RELOC from BUF. */
15569 static unsigned int
15570 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15572 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15573 return read_compressed_insn (buf, 4);
15575 return read_insn (buf);
15578 /* Write instruction INSN to BUF, given that it has been relocated
15582 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15583 unsigned long insn)
15585 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15586 write_compressed_insn (buf, insn, 4);
15588 write_insn (buf, insn);
15591 /* Apply a fixup to the object file. */
15594 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15597 unsigned long insn;
15598 reloc_howto_type *howto;
15600 /* We ignore generic BFD relocations we don't know about. */
15601 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15605 gas_assert (fixP->fx_size == 2
15606 || fixP->fx_size == 4
15607 || fixP->fx_r_type == BFD_RELOC_16
15608 || fixP->fx_r_type == BFD_RELOC_64
15609 || fixP->fx_r_type == BFD_RELOC_CTOR
15610 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15611 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15612 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15613 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15614 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15616 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15618 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15619 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15620 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15621 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15623 /* Don't treat parts of a composite relocation as done. There are two
15626 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15627 should nevertheless be emitted if the first part is.
15629 (2) In normal usage, composite relocations are never assembly-time
15630 constants. The easiest way of dealing with the pathological
15631 exceptions is to generate a relocation against STN_UNDEF and
15632 leave everything up to the linker. */
15633 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15636 switch (fixP->fx_r_type)
15638 case BFD_RELOC_MIPS_TLS_GD:
15639 case BFD_RELOC_MIPS_TLS_LDM:
15640 case BFD_RELOC_MIPS_TLS_DTPREL32:
15641 case BFD_RELOC_MIPS_TLS_DTPREL64:
15642 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15643 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15644 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15645 case BFD_RELOC_MIPS_TLS_TPREL32:
15646 case BFD_RELOC_MIPS_TLS_TPREL64:
15647 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15648 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15649 case BFD_RELOC_MICROMIPS_TLS_GD:
15650 case BFD_RELOC_MICROMIPS_TLS_LDM:
15651 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15652 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15653 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15654 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15655 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15656 case BFD_RELOC_MIPS16_TLS_GD:
15657 case BFD_RELOC_MIPS16_TLS_LDM:
15658 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15659 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15660 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15661 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15662 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15663 if (!fixP->fx_addsy)
15665 as_bad_where (fixP->fx_file, fixP->fx_line,
15666 _("TLS relocation against a constant"));
15669 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15672 case BFD_RELOC_MIPS_JMP:
15673 case BFD_RELOC_MIPS_SHIFT5:
15674 case BFD_RELOC_MIPS_SHIFT6:
15675 case BFD_RELOC_MIPS_GOT_DISP:
15676 case BFD_RELOC_MIPS_GOT_PAGE:
15677 case BFD_RELOC_MIPS_GOT_OFST:
15678 case BFD_RELOC_MIPS_SUB:
15679 case BFD_RELOC_MIPS_INSERT_A:
15680 case BFD_RELOC_MIPS_INSERT_B:
15681 case BFD_RELOC_MIPS_DELETE:
15682 case BFD_RELOC_MIPS_HIGHEST:
15683 case BFD_RELOC_MIPS_HIGHER:
15684 case BFD_RELOC_MIPS_SCN_DISP:
15685 case BFD_RELOC_MIPS_REL16:
15686 case BFD_RELOC_MIPS_RELGOT:
15687 case BFD_RELOC_MIPS_JALR:
15688 case BFD_RELOC_HI16:
15689 case BFD_RELOC_HI16_S:
15690 case BFD_RELOC_LO16:
15691 case BFD_RELOC_GPREL16:
15692 case BFD_RELOC_MIPS_LITERAL:
15693 case BFD_RELOC_MIPS_CALL16:
15694 case BFD_RELOC_MIPS_GOT16:
15695 case BFD_RELOC_GPREL32:
15696 case BFD_RELOC_MIPS_GOT_HI16:
15697 case BFD_RELOC_MIPS_GOT_LO16:
15698 case BFD_RELOC_MIPS_CALL_HI16:
15699 case BFD_RELOC_MIPS_CALL_LO16:
15700 case BFD_RELOC_MIPS16_GPREL:
15701 case BFD_RELOC_MIPS16_GOT16:
15702 case BFD_RELOC_MIPS16_CALL16:
15703 case BFD_RELOC_MIPS16_HI16:
15704 case BFD_RELOC_MIPS16_HI16_S:
15705 case BFD_RELOC_MIPS16_LO16:
15706 case BFD_RELOC_MIPS16_JMP:
15707 case BFD_RELOC_MICROMIPS_JMP:
15708 case BFD_RELOC_MICROMIPS_GOT_DISP:
15709 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15710 case BFD_RELOC_MICROMIPS_GOT_OFST:
15711 case BFD_RELOC_MICROMIPS_SUB:
15712 case BFD_RELOC_MICROMIPS_HIGHEST:
15713 case BFD_RELOC_MICROMIPS_HIGHER:
15714 case BFD_RELOC_MICROMIPS_SCN_DISP:
15715 case BFD_RELOC_MICROMIPS_JALR:
15716 case BFD_RELOC_MICROMIPS_HI16:
15717 case BFD_RELOC_MICROMIPS_HI16_S:
15718 case BFD_RELOC_MICROMIPS_LO16:
15719 case BFD_RELOC_MICROMIPS_GPREL16:
15720 case BFD_RELOC_MICROMIPS_LITERAL:
15721 case BFD_RELOC_MICROMIPS_CALL16:
15722 case BFD_RELOC_MICROMIPS_GOT16:
15723 case BFD_RELOC_MICROMIPS_GOT_HI16:
15724 case BFD_RELOC_MICROMIPS_GOT_LO16:
15725 case BFD_RELOC_MICROMIPS_CALL_HI16:
15726 case BFD_RELOC_MICROMIPS_CALL_LO16:
15731 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15733 insn = read_reloc_insn (buf, fixP->fx_r_type);
15734 if (mips16_reloc_p (fixP->fx_r_type))
15735 insn |= mips16_immed_extend (value, 16);
15737 insn |= (value & 0xffff);
15738 write_reloc_insn (buf, fixP->fx_r_type, insn);
15741 as_bad_where (fixP->fx_file, fixP->fx_line,
15742 _("Unsupported constant in relocation"));
15747 /* This is handled like BFD_RELOC_32, but we output a sign
15748 extended value if we are only 32 bits. */
15751 if (8 <= sizeof (valueT))
15752 md_number_to_chars (buf, *valP, 8);
15757 if ((*valP & 0x80000000) != 0)
15761 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15762 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15767 case BFD_RELOC_RVA:
15770 /* If we are deleting this reloc entry, we must fill in the
15771 value now. This can happen if we have a .word which is not
15772 resolved when it appears but is later defined. */
15774 md_number_to_chars (buf, *valP, fixP->fx_size);
15777 case BFD_RELOC_16_PCREL_S2:
15778 if ((*valP & 0x3) != 0)
15779 as_bad_where (fixP->fx_file, fixP->fx_line,
15780 _("Branch to misaligned address (%lx)"), (long) *valP);
15782 /* We need to save the bits in the instruction since fixup_segment()
15783 might be deleting the relocation entry (i.e., a branch within
15784 the current segment). */
15785 if (! fixP->fx_done)
15788 /* Update old instruction data. */
15789 insn = read_insn (buf);
15791 if (*valP + 0x20000 <= 0x3ffff)
15793 insn |= (*valP >> 2) & 0xffff;
15794 write_insn (buf, insn);
15796 else if (mips_pic == NO_PIC
15798 && fixP->fx_frag->fr_address >= text_section->vma
15799 && (fixP->fx_frag->fr_address
15800 < text_section->vma + bfd_get_section_size (text_section))
15801 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15802 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15803 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15805 /* The branch offset is too large. If this is an
15806 unconditional branch, and we are not generating PIC code,
15807 we can convert it to an absolute jump instruction. */
15808 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15809 insn = 0x0c000000; /* jal */
15811 insn = 0x08000000; /* j */
15812 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15814 fixP->fx_addsy = section_symbol (text_section);
15815 *valP += md_pcrel_from (fixP);
15816 write_insn (buf, insn);
15820 /* If we got here, we have branch-relaxation disabled,
15821 and there's nothing we can do to fix this instruction
15822 without turning it into a longer sequence. */
15823 as_bad_where (fixP->fx_file, fixP->fx_line,
15824 _("Branch out of range"));
15828 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15829 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15830 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15831 /* We adjust the offset back to even. */
15832 if ((*valP & 0x1) != 0)
15835 if (! fixP->fx_done)
15838 /* Should never visit here, because we keep the relocation. */
15842 case BFD_RELOC_VTABLE_INHERIT:
15845 && !S_IS_DEFINED (fixP->fx_addsy)
15846 && !S_IS_WEAK (fixP->fx_addsy))
15847 S_SET_WEAK (fixP->fx_addsy);
15850 case BFD_RELOC_VTABLE_ENTRY:
15858 /* Remember value for tc_gen_reloc. */
15859 fixP->fx_addnumber = *valP;
15869 name = input_line_pointer;
15870 c = get_symbol_end ();
15871 p = (symbolS *) symbol_find_or_make (name);
15872 *input_line_pointer = c;
15876 /* Align the current frag to a given power of two. If a particular
15877 fill byte should be used, FILL points to an integer that contains
15878 that byte, otherwise FILL is null.
15880 This function used to have the comment:
15882 The MIPS assembler also automatically adjusts any preceding label.
15884 The implementation therefore applied the adjustment to a maximum of
15885 one label. However, other label adjustments are applied to batches
15886 of labels, and adjusting just one caused problems when new labels
15887 were added for the sake of debugging or unwind information.
15888 We therefore adjust all preceding labels (given as LABELS) instead. */
15891 mips_align (int to, int *fill, struct insn_label_list *labels)
15893 mips_emit_delays ();
15894 mips_record_compressed_mode ();
15895 if (fill == NULL && subseg_text_p (now_seg))
15896 frag_align_code (to, 0);
15898 frag_align (to, fill ? *fill : 0, 0);
15899 record_alignment (now_seg, to);
15900 mips_move_labels (labels, FALSE);
15903 /* Align to a given power of two. .align 0 turns off the automatic
15904 alignment used by the data creating pseudo-ops. */
15907 s_align (int x ATTRIBUTE_UNUSED)
15909 int temp, fill_value, *fill_ptr;
15910 long max_alignment = 28;
15912 /* o Note that the assembler pulls down any immediately preceding label
15913 to the aligned address.
15914 o It's not documented but auto alignment is reinstated by
15915 a .align pseudo instruction.
15916 o Note also that after auto alignment is turned off the mips assembler
15917 issues an error on attempt to assemble an improperly aligned data item.
15920 temp = get_absolute_expression ();
15921 if (temp > max_alignment)
15922 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15925 as_warn (_("Alignment negative: 0 assumed."));
15928 if (*input_line_pointer == ',')
15930 ++input_line_pointer;
15931 fill_value = get_absolute_expression ();
15932 fill_ptr = &fill_value;
15938 segment_info_type *si = seg_info (now_seg);
15939 struct insn_label_list *l = si->label_list;
15940 /* Auto alignment should be switched on by next section change. */
15942 mips_align (temp, fill_ptr, l);
15949 demand_empty_rest_of_line ();
15953 s_change_sec (int sec)
15958 /* The ELF backend needs to know that we are changing sections, so
15959 that .previous works correctly. We could do something like check
15960 for an obj_section_change_hook macro, but that might be confusing
15961 as it would not be appropriate to use it in the section changing
15962 functions in read.c, since obj-elf.c intercepts those. FIXME:
15963 This should be cleaner, somehow. */
15965 obj_elf_section_change_hook ();
15968 mips_emit_delays ();
15979 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15980 demand_empty_rest_of_line ();
15984 seg = subseg_new (RDATA_SECTION_NAME,
15985 (subsegT) get_absolute_expression ());
15988 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15989 | SEC_READONLY | SEC_RELOC
15991 if (strncmp (TARGET_OS, "elf", 3) != 0)
15992 record_alignment (seg, 4);
15994 demand_empty_rest_of_line ();
15998 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16001 bfd_set_section_flags (stdoutput, seg,
16002 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16003 if (strncmp (TARGET_OS, "elf", 3) != 0)
16004 record_alignment (seg, 4);
16006 demand_empty_rest_of_line ();
16010 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16013 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16014 if (strncmp (TARGET_OS, "elf", 3) != 0)
16015 record_alignment (seg, 4);
16017 demand_empty_rest_of_line ();
16025 s_change_section (int ignore ATTRIBUTE_UNUSED)
16028 char *section_name;
16033 int section_entry_size;
16034 int section_alignment;
16039 section_name = input_line_pointer;
16040 c = get_symbol_end ();
16042 next_c = *(input_line_pointer + 1);
16044 /* Do we have .section Name<,"flags">? */
16045 if (c != ',' || (c == ',' && next_c == '"'))
16047 /* just after name is now '\0'. */
16048 *input_line_pointer = c;
16049 input_line_pointer = section_name;
16050 obj_elf_section (ignore);
16053 input_line_pointer++;
16055 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16057 section_type = get_absolute_expression ();
16060 if (*input_line_pointer++ == ',')
16061 section_flag = get_absolute_expression ();
16064 if (*input_line_pointer++ == ',')
16065 section_entry_size = get_absolute_expression ();
16067 section_entry_size = 0;
16068 if (*input_line_pointer++ == ',')
16069 section_alignment = get_absolute_expression ();
16071 section_alignment = 0;
16072 /* FIXME: really ignore? */
16073 (void) section_alignment;
16075 section_name = xstrdup (section_name);
16077 /* When using the generic form of .section (as implemented by obj-elf.c),
16078 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16079 traditionally had to fall back on the more common @progbits instead.
16081 There's nothing really harmful in this, since bfd will correct
16082 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16083 means that, for backwards compatibility, the special_section entries
16084 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16086 Even so, we shouldn't force users of the MIPS .section syntax to
16087 incorrectly label the sections as SHT_PROGBITS. The best compromise
16088 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16089 generic type-checking code. */
16090 if (section_type == SHT_MIPS_DWARF)
16091 section_type = SHT_PROGBITS;
16093 obj_elf_change_section (section_name, section_type, section_flag,
16094 section_entry_size, 0, 0, 0);
16096 if (now_seg->name != section_name)
16097 free (section_name);
16098 #endif /* OBJ_ELF */
16102 mips_enable_auto_align (void)
16108 s_cons (int log_size)
16110 segment_info_type *si = seg_info (now_seg);
16111 struct insn_label_list *l = si->label_list;
16113 mips_emit_delays ();
16114 if (log_size > 0 && auto_align)
16115 mips_align (log_size, 0, l);
16116 cons (1 << log_size);
16117 mips_clear_insn_labels ();
16121 s_float_cons (int type)
16123 segment_info_type *si = seg_info (now_seg);
16124 struct insn_label_list *l = si->label_list;
16126 mips_emit_delays ();
16131 mips_align (3, 0, l);
16133 mips_align (2, 0, l);
16137 mips_clear_insn_labels ();
16140 /* Handle .globl. We need to override it because on Irix 5 you are
16143 where foo is an undefined symbol, to mean that foo should be
16144 considered to be the address of a function. */
16147 s_mips_globl (int x ATTRIBUTE_UNUSED)
16156 name = input_line_pointer;
16157 c = get_symbol_end ();
16158 symbolP = symbol_find_or_make (name);
16159 S_SET_EXTERNAL (symbolP);
16161 *input_line_pointer = c;
16162 SKIP_WHITESPACE ();
16164 /* On Irix 5, every global symbol that is not explicitly labelled as
16165 being a function is apparently labelled as being an object. */
16168 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16169 && (*input_line_pointer != ','))
16174 secname = input_line_pointer;
16175 c = get_symbol_end ();
16176 sec = bfd_get_section_by_name (stdoutput, secname);
16178 as_bad (_("%s: no such section"), secname);
16179 *input_line_pointer = c;
16181 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16182 flag = BSF_FUNCTION;
16185 symbol_get_bfdsym (symbolP)->flags |= flag;
16187 c = *input_line_pointer;
16190 input_line_pointer++;
16191 SKIP_WHITESPACE ();
16192 if (is_end_of_line[(unsigned char) *input_line_pointer])
16198 demand_empty_rest_of_line ();
16202 s_option (int x ATTRIBUTE_UNUSED)
16207 opt = input_line_pointer;
16208 c = get_symbol_end ();
16212 /* FIXME: What does this mean? */
16214 else if (strncmp (opt, "pic", 3) == 0)
16218 i = atoi (opt + 3);
16223 mips_pic = SVR4_PIC;
16224 mips_abicalls = TRUE;
16227 as_bad (_(".option pic%d not supported"), i);
16229 if (mips_pic == SVR4_PIC)
16231 if (g_switch_seen && g_switch_value != 0)
16232 as_warn (_("-G may not be used with SVR4 PIC code"));
16233 g_switch_value = 0;
16234 bfd_set_gp_size (stdoutput, 0);
16238 as_warn (_("Unrecognized option \"%s\""), opt);
16240 *input_line_pointer = c;
16241 demand_empty_rest_of_line ();
16244 /* This structure is used to hold a stack of .set values. */
16246 struct mips_option_stack
16248 struct mips_option_stack *next;
16249 struct mips_set_options options;
16252 static struct mips_option_stack *mips_opts_stack;
16254 /* Handle the .set pseudo-op. */
16257 s_mipsset (int x ATTRIBUTE_UNUSED)
16259 char *name = input_line_pointer, ch;
16261 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16262 ++input_line_pointer;
16263 ch = *input_line_pointer;
16264 *input_line_pointer = '\0';
16266 if (strcmp (name, "reorder") == 0)
16268 if (mips_opts.noreorder)
16271 else if (strcmp (name, "noreorder") == 0)
16273 if (!mips_opts.noreorder)
16274 start_noreorder ();
16276 else if (strncmp (name, "at=", 3) == 0)
16278 char *s = name + 3;
16280 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16281 as_bad (_("Unrecognized register name `%s'"), s);
16283 else if (strcmp (name, "at") == 0)
16285 mips_opts.at = ATREG;
16287 else if (strcmp (name, "noat") == 0)
16289 mips_opts.at = ZERO;
16291 else if (strcmp (name, "macro") == 0)
16293 mips_opts.warn_about_macros = 0;
16295 else if (strcmp (name, "nomacro") == 0)
16297 if (mips_opts.noreorder == 0)
16298 as_bad (_("`noreorder' must be set before `nomacro'"));
16299 mips_opts.warn_about_macros = 1;
16301 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16303 mips_opts.nomove = 0;
16305 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16307 mips_opts.nomove = 1;
16309 else if (strcmp (name, "bopt") == 0)
16311 mips_opts.nobopt = 0;
16313 else if (strcmp (name, "nobopt") == 0)
16315 mips_opts.nobopt = 1;
16317 else if (strcmp (name, "gp=default") == 0)
16318 mips_opts.gp32 = file_mips_gp32;
16319 else if (strcmp (name, "gp=32") == 0)
16320 mips_opts.gp32 = 1;
16321 else if (strcmp (name, "gp=64") == 0)
16323 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16324 as_warn (_("%s isa does not support 64-bit registers"),
16325 mips_cpu_info_from_isa (mips_opts.isa)->name);
16326 mips_opts.gp32 = 0;
16328 else if (strcmp (name, "fp=default") == 0)
16329 mips_opts.fp32 = file_mips_fp32;
16330 else if (strcmp (name, "fp=32") == 0)
16331 mips_opts.fp32 = 1;
16332 else if (strcmp (name, "fp=64") == 0)
16334 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16335 as_warn (_("%s isa does not support 64-bit floating point registers"),
16336 mips_cpu_info_from_isa (mips_opts.isa)->name);
16337 mips_opts.fp32 = 0;
16339 else if (strcmp (name, "softfloat") == 0)
16340 mips_opts.soft_float = 1;
16341 else if (strcmp (name, "hardfloat") == 0)
16342 mips_opts.soft_float = 0;
16343 else if (strcmp (name, "singlefloat") == 0)
16344 mips_opts.single_float = 1;
16345 else if (strcmp (name, "doublefloat") == 0)
16346 mips_opts.single_float = 0;
16347 else if (strcmp (name, "mips16") == 0
16348 || strcmp (name, "MIPS-16") == 0)
16350 if (mips_opts.micromips == 1)
16351 as_fatal (_("`mips16' cannot be used with `micromips'"));
16352 mips_opts.mips16 = 1;
16354 else if (strcmp (name, "nomips16") == 0
16355 || strcmp (name, "noMIPS-16") == 0)
16356 mips_opts.mips16 = 0;
16357 else if (strcmp (name, "micromips") == 0)
16359 if (mips_opts.mips16 == 1)
16360 as_fatal (_("`micromips' cannot be used with `mips16'"));
16361 mips_opts.micromips = 1;
16363 else if (strcmp (name, "nomicromips") == 0)
16364 mips_opts.micromips = 0;
16365 else if (strcmp (name, "smartmips") == 0)
16367 if (!ISA_SUPPORTS_SMARTMIPS)
16368 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16369 mips_cpu_info_from_isa (mips_opts.isa)->name);
16370 mips_opts.ase_smartmips = 1;
16372 else if (strcmp (name, "nosmartmips") == 0)
16373 mips_opts.ase_smartmips = 0;
16374 else if (strcmp (name, "mips3d") == 0)
16375 mips_opts.ase_mips3d = 1;
16376 else if (strcmp (name, "nomips3d") == 0)
16377 mips_opts.ase_mips3d = 0;
16378 else if (strcmp (name, "mdmx") == 0)
16379 mips_opts.ase_mdmx = 1;
16380 else if (strcmp (name, "nomdmx") == 0)
16381 mips_opts.ase_mdmx = 0;
16382 else if (strcmp (name, "dsp") == 0)
16384 if (!ISA_SUPPORTS_DSP_ASE)
16385 as_warn (_("%s ISA does not support DSP ASE"),
16386 mips_cpu_info_from_isa (mips_opts.isa)->name);
16387 mips_opts.ase_dsp = 1;
16388 mips_opts.ase_dspr2 = 0;
16390 else if (strcmp (name, "nodsp") == 0)
16392 mips_opts.ase_dsp = 0;
16393 mips_opts.ase_dspr2 = 0;
16395 else if (strcmp (name, "dspr2") == 0)
16397 if (!ISA_SUPPORTS_DSPR2_ASE)
16398 as_warn (_("%s ISA does not support DSP R2 ASE"),
16399 mips_cpu_info_from_isa (mips_opts.isa)->name);
16400 mips_opts.ase_dspr2 = 1;
16401 mips_opts.ase_dsp = 1;
16403 else if (strcmp (name, "nodspr2") == 0)
16405 mips_opts.ase_dspr2 = 0;
16406 mips_opts.ase_dsp = 0;
16408 else if (strcmp (name, "mt") == 0)
16410 if (!ISA_SUPPORTS_MT_ASE)
16411 as_warn (_("%s ISA does not support MT ASE"),
16412 mips_cpu_info_from_isa (mips_opts.isa)->name);
16413 mips_opts.ase_mt = 1;
16415 else if (strcmp (name, "nomt") == 0)
16416 mips_opts.ase_mt = 0;
16417 else if (strcmp (name, "mcu") == 0)
16418 mips_opts.ase_mcu = 1;
16419 else if (strcmp (name, "nomcu") == 0)
16420 mips_opts.ase_mcu = 0;
16421 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16425 /* Permit the user to change the ISA and architecture on the fly.
16426 Needless to say, misuse can cause serious problems. */
16427 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16430 mips_opts.isa = file_mips_isa;
16431 mips_opts.arch = file_mips_arch;
16433 else if (strncmp (name, "arch=", 5) == 0)
16435 const struct mips_cpu_info *p;
16437 p = mips_parse_cpu("internal use", name + 5);
16439 as_bad (_("unknown architecture %s"), name + 5);
16442 mips_opts.arch = p->cpu;
16443 mips_opts.isa = p->isa;
16446 else if (strncmp (name, "mips", 4) == 0)
16448 const struct mips_cpu_info *p;
16450 p = mips_parse_cpu("internal use", name);
16452 as_bad (_("unknown ISA level %s"), name + 4);
16455 mips_opts.arch = p->cpu;
16456 mips_opts.isa = p->isa;
16460 as_bad (_("unknown ISA or architecture %s"), name);
16462 switch (mips_opts.isa)
16470 mips_opts.gp32 = 1;
16471 mips_opts.fp32 = 1;
16478 mips_opts.gp32 = 0;
16479 if (mips_opts.arch == CPU_R5900)
16481 mips_opts.fp32 = 1;
16485 mips_opts.fp32 = 0;
16489 as_bad (_("unknown ISA level %s"), name + 4);
16494 mips_opts.gp32 = file_mips_gp32;
16495 mips_opts.fp32 = file_mips_fp32;
16498 else if (strcmp (name, "autoextend") == 0)
16499 mips_opts.noautoextend = 0;
16500 else if (strcmp (name, "noautoextend") == 0)
16501 mips_opts.noautoextend = 1;
16502 else if (strcmp (name, "push") == 0)
16504 struct mips_option_stack *s;
16506 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16507 s->next = mips_opts_stack;
16508 s->options = mips_opts;
16509 mips_opts_stack = s;
16511 else if (strcmp (name, "pop") == 0)
16513 struct mips_option_stack *s;
16515 s = mips_opts_stack;
16517 as_bad (_(".set pop with no .set push"));
16520 /* If we're changing the reorder mode we need to handle
16521 delay slots correctly. */
16522 if (s->options.noreorder && ! mips_opts.noreorder)
16523 start_noreorder ();
16524 else if (! s->options.noreorder && mips_opts.noreorder)
16527 mips_opts = s->options;
16528 mips_opts_stack = s->next;
16532 else if (strcmp (name, "sym32") == 0)
16533 mips_opts.sym32 = TRUE;
16534 else if (strcmp (name, "nosym32") == 0)
16535 mips_opts.sym32 = FALSE;
16536 else if (strchr (name, ','))
16538 /* Generic ".set" directive; use the generic handler. */
16539 *input_line_pointer = ch;
16540 input_line_pointer = name;
16546 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16548 *input_line_pointer = ch;
16549 demand_empty_rest_of_line ();
16552 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16553 .option pic2. It means to generate SVR4 PIC calls. */
16556 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16558 mips_pic = SVR4_PIC;
16559 mips_abicalls = TRUE;
16561 if (g_switch_seen && g_switch_value != 0)
16562 as_warn (_("-G may not be used with SVR4 PIC code"));
16563 g_switch_value = 0;
16565 bfd_set_gp_size (stdoutput, 0);
16566 demand_empty_rest_of_line ();
16569 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16570 PIC code. It sets the $gp register for the function based on the
16571 function address, which is in the register named in the argument.
16572 This uses a relocation against _gp_disp, which is handled specially
16573 by the linker. The result is:
16574 lui $gp,%hi(_gp_disp)
16575 addiu $gp,$gp,%lo(_gp_disp)
16576 addu $gp,$gp,.cpload argument
16577 The .cpload argument is normally $25 == $t9.
16579 The -mno-shared option changes this to:
16580 lui $gp,%hi(__gnu_local_gp)
16581 addiu $gp,$gp,%lo(__gnu_local_gp)
16582 and the argument is ignored. This saves an instruction, but the
16583 resulting code is not position independent; it uses an absolute
16584 address for __gnu_local_gp. Thus code assembled with -mno-shared
16585 can go into an ordinary executable, but not into a shared library. */
16588 s_cpload (int ignore ATTRIBUTE_UNUSED)
16594 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16595 .cpload is ignored. */
16596 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16602 if (mips_opts.mips16)
16604 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16605 ignore_rest_of_line ();
16609 /* .cpload should be in a .set noreorder section. */
16610 if (mips_opts.noreorder == 0)
16611 as_warn (_(".cpload not in noreorder section"));
16613 reg = tc_get_register (0);
16615 /* If we need to produce a 64-bit address, we are better off using
16616 the default instruction sequence. */
16617 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16619 ex.X_op = O_symbol;
16620 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16622 ex.X_op_symbol = NULL;
16623 ex.X_add_number = 0;
16625 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16626 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16629 macro_build_lui (&ex, mips_gp_register);
16630 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16631 mips_gp_register, BFD_RELOC_LO16);
16633 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16634 mips_gp_register, reg);
16637 demand_empty_rest_of_line ();
16640 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16641 .cpsetup $reg1, offset|$reg2, label
16643 If offset is given, this results in:
16644 sd $gp, offset($sp)
16645 lui $gp, %hi(%neg(%gp_rel(label)))
16646 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16647 daddu $gp, $gp, $reg1
16649 If $reg2 is given, this results in:
16650 daddu $reg2, $gp, $0
16651 lui $gp, %hi(%neg(%gp_rel(label)))
16652 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16653 daddu $gp, $gp, $reg1
16654 $reg1 is normally $25 == $t9.
16656 The -mno-shared option replaces the last three instructions with
16658 addiu $gp,$gp,%lo(_gp) */
16661 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16663 expressionS ex_off;
16664 expressionS ex_sym;
16667 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16668 We also need NewABI support. */
16669 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16675 if (mips_opts.mips16)
16677 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16678 ignore_rest_of_line ();
16682 reg1 = tc_get_register (0);
16683 SKIP_WHITESPACE ();
16684 if (*input_line_pointer != ',')
16686 as_bad (_("missing argument separator ',' for .cpsetup"));
16690 ++input_line_pointer;
16691 SKIP_WHITESPACE ();
16692 if (*input_line_pointer == '$')
16694 mips_cpreturn_register = tc_get_register (0);
16695 mips_cpreturn_offset = -1;
16699 mips_cpreturn_offset = get_absolute_expression ();
16700 mips_cpreturn_register = -1;
16702 SKIP_WHITESPACE ();
16703 if (*input_line_pointer != ',')
16705 as_bad (_("missing argument separator ',' for .cpsetup"));
16709 ++input_line_pointer;
16710 SKIP_WHITESPACE ();
16711 expression (&ex_sym);
16714 if (mips_cpreturn_register == -1)
16716 ex_off.X_op = O_constant;
16717 ex_off.X_add_symbol = NULL;
16718 ex_off.X_op_symbol = NULL;
16719 ex_off.X_add_number = mips_cpreturn_offset;
16721 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16722 BFD_RELOC_LO16, SP);
16725 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16726 mips_gp_register, 0);
16728 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16730 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16731 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16734 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16735 mips_gp_register, -1, BFD_RELOC_GPREL16,
16736 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16738 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16739 mips_gp_register, reg1);
16745 ex.X_op = O_symbol;
16746 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16747 ex.X_op_symbol = NULL;
16748 ex.X_add_number = 0;
16750 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16751 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16753 macro_build_lui (&ex, mips_gp_register);
16754 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16755 mips_gp_register, BFD_RELOC_LO16);
16760 demand_empty_rest_of_line ();
16764 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16766 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16767 .cplocal is ignored. */
16768 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16774 if (mips_opts.mips16)
16776 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16777 ignore_rest_of_line ();
16781 mips_gp_register = tc_get_register (0);
16782 demand_empty_rest_of_line ();
16785 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16786 offset from $sp. The offset is remembered, and after making a PIC
16787 call $gp is restored from that location. */
16790 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16794 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16795 .cprestore is ignored. */
16796 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16802 if (mips_opts.mips16)
16804 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16805 ignore_rest_of_line ();
16809 mips_cprestore_offset = get_absolute_expression ();
16810 mips_cprestore_valid = 1;
16812 ex.X_op = O_constant;
16813 ex.X_add_symbol = NULL;
16814 ex.X_op_symbol = NULL;
16815 ex.X_add_number = mips_cprestore_offset;
16818 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16819 SP, HAVE_64BIT_ADDRESSES);
16822 demand_empty_rest_of_line ();
16825 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16826 was given in the preceding .cpsetup, it results in:
16827 ld $gp, offset($sp)
16829 If a register $reg2 was given there, it results in:
16830 daddu $gp, $reg2, $0 */
16833 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16837 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16838 We also need NewABI support. */
16839 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16845 if (mips_opts.mips16)
16847 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16848 ignore_rest_of_line ();
16853 if (mips_cpreturn_register == -1)
16855 ex.X_op = O_constant;
16856 ex.X_add_symbol = NULL;
16857 ex.X_op_symbol = NULL;
16858 ex.X_add_number = mips_cpreturn_offset;
16860 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16863 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16864 mips_cpreturn_register, 0);
16867 demand_empty_rest_of_line ();
16870 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16871 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16872 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16873 debug information or MIPS16 TLS. */
16876 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16877 bfd_reloc_code_real_type rtype)
16884 if (ex.X_op != O_symbol)
16886 as_bad (_("Unsupported use of %s"), dirstr);
16887 ignore_rest_of_line ();
16890 p = frag_more (bytes);
16891 md_number_to_chars (p, 0, bytes);
16892 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16893 demand_empty_rest_of_line ();
16894 mips_clear_insn_labels ();
16897 /* Handle .dtprelword. */
16900 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16902 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16905 /* Handle .dtpreldword. */
16908 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16910 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16913 /* Handle .tprelword. */
16916 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16918 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16921 /* Handle .tpreldword. */
16924 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16926 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16929 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16930 code. It sets the offset to use in gp_rel relocations. */
16933 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16935 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16936 We also need NewABI support. */
16937 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16943 mips_gprel_offset = get_absolute_expression ();
16945 demand_empty_rest_of_line ();
16948 /* Handle the .gpword pseudo-op. This is used when generating PIC
16949 code. It generates a 32 bit GP relative reloc. */
16952 s_gpword (int ignore ATTRIBUTE_UNUSED)
16954 segment_info_type *si;
16955 struct insn_label_list *l;
16959 /* When not generating PIC code, this is treated as .word. */
16960 if (mips_pic != SVR4_PIC)
16966 si = seg_info (now_seg);
16967 l = si->label_list;
16968 mips_emit_delays ();
16970 mips_align (2, 0, l);
16973 mips_clear_insn_labels ();
16975 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16977 as_bad (_("Unsupported use of .gpword"));
16978 ignore_rest_of_line ();
16982 md_number_to_chars (p, 0, 4);
16983 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16984 BFD_RELOC_GPREL32);
16986 demand_empty_rest_of_line ();
16990 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16992 segment_info_type *si;
16993 struct insn_label_list *l;
16997 /* When not generating PIC code, this is treated as .dword. */
16998 if (mips_pic != SVR4_PIC)
17004 si = seg_info (now_seg);
17005 l = si->label_list;
17006 mips_emit_delays ();
17008 mips_align (3, 0, l);
17011 mips_clear_insn_labels ();
17013 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17015 as_bad (_("Unsupported use of .gpdword"));
17016 ignore_rest_of_line ();
17020 md_number_to_chars (p, 0, 8);
17021 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17022 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17024 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17025 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17026 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17028 demand_empty_rest_of_line ();
17031 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17032 tables in SVR4 PIC code. */
17035 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17039 /* This is ignored when not generating SVR4 PIC code. */
17040 if (mips_pic != SVR4_PIC)
17046 /* Add $gp to the register named as an argument. */
17048 reg = tc_get_register (0);
17049 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17052 demand_empty_rest_of_line ();
17055 /* Handle the .insn pseudo-op. This marks instruction labels in
17056 mips16/micromips mode. This permits the linker to handle them specially,
17057 such as generating jalx instructions when needed. We also make
17058 them odd for the duration of the assembly, in order to generate the
17059 right sort of code. We will make them even in the adjust_symtab
17060 routine, while leaving them marked. This is convenient for the
17061 debugger and the disassembler. The linker knows to make them odd
17065 s_insn (int ignore ATTRIBUTE_UNUSED)
17067 mips_mark_labels ();
17069 demand_empty_rest_of_line ();
17072 /* Handle a .stabn directive. We need these in order to mark a label
17073 as being a mips16 text label correctly. Sometimes the compiler
17074 will emit a label, followed by a .stabn, and then switch sections.
17075 If the label and .stabn are in mips16 mode, then the label is
17076 really a mips16 text label. */
17079 s_mips_stab (int type)
17082 mips_mark_labels ();
17087 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17090 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17097 name = input_line_pointer;
17098 c = get_symbol_end ();
17099 symbolP = symbol_find_or_make (name);
17100 S_SET_WEAK (symbolP);
17101 *input_line_pointer = c;
17103 SKIP_WHITESPACE ();
17105 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17107 if (S_IS_DEFINED (symbolP))
17109 as_bad (_("ignoring attempt to redefine symbol %s"),
17110 S_GET_NAME (symbolP));
17111 ignore_rest_of_line ();
17115 if (*input_line_pointer == ',')
17117 ++input_line_pointer;
17118 SKIP_WHITESPACE ();
17122 if (exp.X_op != O_symbol)
17124 as_bad (_("bad .weakext directive"));
17125 ignore_rest_of_line ();
17128 symbol_set_value_expression (symbolP, &exp);
17131 demand_empty_rest_of_line ();
17134 /* Parse a register string into a number. Called from the ECOFF code
17135 to parse .frame. The argument is non-zero if this is the frame
17136 register, so that we can record it in mips_frame_reg. */
17139 tc_get_register (int frame)
17143 SKIP_WHITESPACE ();
17144 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17148 mips_frame_reg = reg != 0 ? reg : SP;
17149 mips_frame_reg_valid = 1;
17150 mips_cprestore_valid = 0;
17156 md_section_align (asection *seg, valueT addr)
17158 int align = bfd_get_section_alignment (stdoutput, seg);
17162 /* We don't need to align ELF sections to the full alignment.
17163 However, Irix 5 may prefer that we align them at least to a 16
17164 byte boundary. We don't bother to align the sections if we
17165 are targeted for an embedded system. */
17166 if (strncmp (TARGET_OS, "elf", 3) == 0)
17172 return ((addr + (1 << align) - 1) & (-1 << align));
17175 /* Utility routine, called from above as well. If called while the
17176 input file is still being read, it's only an approximation. (For
17177 example, a symbol may later become defined which appeared to be
17178 undefined earlier.) */
17181 nopic_need_relax (symbolS *sym, int before_relaxing)
17186 if (g_switch_value > 0)
17188 const char *symname;
17191 /* Find out whether this symbol can be referenced off the $gp
17192 register. It can be if it is smaller than the -G size or if
17193 it is in the .sdata or .sbss section. Certain symbols can
17194 not be referenced off the $gp, although it appears as though
17196 symname = S_GET_NAME (sym);
17197 if (symname != (const char *) NULL
17198 && (strcmp (symname, "eprol") == 0
17199 || strcmp (symname, "etext") == 0
17200 || strcmp (symname, "_gp") == 0
17201 || strcmp (symname, "edata") == 0
17202 || strcmp (symname, "_fbss") == 0
17203 || strcmp (symname, "_fdata") == 0
17204 || strcmp (symname, "_ftext") == 0
17205 || strcmp (symname, "end") == 0
17206 || strcmp (symname, "_gp_disp") == 0))
17208 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17210 #ifndef NO_ECOFF_DEBUGGING
17211 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17212 && (symbol_get_obj (sym)->ecoff_extern_size
17213 <= g_switch_value))
17215 /* We must defer this decision until after the whole
17216 file has been read, since there might be a .extern
17217 after the first use of this symbol. */
17218 || (before_relaxing
17219 #ifndef NO_ECOFF_DEBUGGING
17220 && symbol_get_obj (sym)->ecoff_extern_size == 0
17222 && S_GET_VALUE (sym) == 0)
17223 || (S_GET_VALUE (sym) != 0
17224 && S_GET_VALUE (sym) <= g_switch_value)))
17228 const char *segname;
17230 segname = segment_name (S_GET_SEGMENT (sym));
17231 gas_assert (strcmp (segname, ".lit8") != 0
17232 && strcmp (segname, ".lit4") != 0);
17233 change = (strcmp (segname, ".sdata") != 0
17234 && strcmp (segname, ".sbss") != 0
17235 && strncmp (segname, ".sdata.", 7) != 0
17236 && strncmp (segname, ".sbss.", 6) != 0
17237 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17238 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17243 /* We are not optimizing for the $gp register. */
17248 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17251 pic_need_relax (symbolS *sym, asection *segtype)
17255 /* Handle the case of a symbol equated to another symbol. */
17256 while (symbol_equated_reloc_p (sym))
17260 /* It's possible to get a loop here in a badly written program. */
17261 n = symbol_get_value_expression (sym)->X_add_symbol;
17267 if (symbol_section_p (sym))
17270 symsec = S_GET_SEGMENT (sym);
17272 /* This must duplicate the test in adjust_reloc_syms. */
17273 return (!bfd_is_und_section (symsec)
17274 && !bfd_is_abs_section (symsec)
17275 && !bfd_is_com_section (symsec)
17276 && !s_is_linkonce (sym, segtype)
17278 /* A global or weak symbol is treated as external. */
17279 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17285 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17286 extended opcode. SEC is the section the frag is in. */
17289 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17292 const struct mips16_immed_operand *op;
17294 int mintiny, maxtiny;
17298 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17300 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17303 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17304 op = mips16_immed_operands;
17305 while (op->type != type)
17308 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17313 if (type == '<' || type == '>' || type == '[' || type == ']')
17316 maxtiny = 1 << op->nbits;
17321 maxtiny = (1 << op->nbits) - 1;
17326 mintiny = - (1 << (op->nbits - 1));
17327 maxtiny = (1 << (op->nbits - 1)) - 1;
17330 sym_frag = symbol_get_frag (fragp->fr_symbol);
17331 val = S_GET_VALUE (fragp->fr_symbol);
17332 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17338 /* We won't have the section when we are called from
17339 mips_relax_frag. However, we will always have been called
17340 from md_estimate_size_before_relax first. If this is a
17341 branch to a different section, we mark it as such. If SEC is
17342 NULL, and the frag is not marked, then it must be a branch to
17343 the same section. */
17346 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17351 /* Must have been called from md_estimate_size_before_relax. */
17354 fragp->fr_subtype =
17355 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17357 /* FIXME: We should support this, and let the linker
17358 catch branches and loads that are out of range. */
17359 as_bad_where (fragp->fr_file, fragp->fr_line,
17360 _("unsupported PC relative reference to different section"));
17364 if (fragp != sym_frag && sym_frag->fr_address == 0)
17365 /* Assume non-extended on the first relaxation pass.
17366 The address we have calculated will be bogus if this is
17367 a forward branch to another frag, as the forward frag
17368 will have fr_address == 0. */
17372 /* In this case, we know for sure that the symbol fragment is in
17373 the same section. If the relax_marker of the symbol fragment
17374 differs from the relax_marker of this fragment, we have not
17375 yet adjusted the symbol fragment fr_address. We want to add
17376 in STRETCH in order to get a better estimate of the address.
17377 This particularly matters because of the shift bits. */
17379 && sym_frag->relax_marker != fragp->relax_marker)
17383 /* Adjust stretch for any alignment frag. Note that if have
17384 been expanding the earlier code, the symbol may be
17385 defined in what appears to be an earlier frag. FIXME:
17386 This doesn't handle the fr_subtype field, which specifies
17387 a maximum number of bytes to skip when doing an
17389 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17391 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17394 stretch = - ((- stretch)
17395 & ~ ((1 << (int) f->fr_offset) - 1));
17397 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17406 addr = fragp->fr_address + fragp->fr_fix;
17408 /* The base address rules are complicated. The base address of
17409 a branch is the following instruction. The base address of a
17410 PC relative load or add is the instruction itself, but if it
17411 is in a delay slot (in which case it can not be extended) use
17412 the address of the instruction whose delay slot it is in. */
17413 if (type == 'p' || type == 'q')
17417 /* If we are currently assuming that this frag should be
17418 extended, then, the current address is two bytes
17420 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17423 /* Ignore the low bit in the target, since it will be set
17424 for a text label. */
17425 if ((val & 1) != 0)
17428 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17430 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17433 val -= addr & ~ ((1 << op->shift) - 1);
17435 /* Branch offsets have an implicit 0 in the lowest bit. */
17436 if (type == 'p' || type == 'q')
17439 /* If any of the shifted bits are set, we must use an extended
17440 opcode. If the address depends on the size of this
17441 instruction, this can lead to a loop, so we arrange to always
17442 use an extended opcode. We only check this when we are in
17443 the main relaxation loop, when SEC is NULL. */
17444 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17446 fragp->fr_subtype =
17447 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17451 /* If we are about to mark a frag as extended because the value
17452 is precisely maxtiny + 1, then there is a chance of an
17453 infinite loop as in the following code:
17458 In this case when the la is extended, foo is 0x3fc bytes
17459 away, so the la can be shrunk, but then foo is 0x400 away, so
17460 the la must be extended. To avoid this loop, we mark the
17461 frag as extended if it was small, and is about to become
17462 extended with a value of maxtiny + 1. */
17463 if (val == ((maxtiny + 1) << op->shift)
17464 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17467 fragp->fr_subtype =
17468 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17472 else if (symsec != absolute_section && sec != NULL)
17473 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17475 if ((val & ((1 << op->shift) - 1)) != 0
17476 || val < (mintiny << op->shift)
17477 || val > (maxtiny << op->shift))
17483 /* Compute the length of a branch sequence, and adjust the
17484 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17485 worst-case length is computed, with UPDATE being used to indicate
17486 whether an unconditional (-1), branch-likely (+1) or regular (0)
17487 branch is to be computed. */
17489 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17491 bfd_boolean toofar;
17495 && S_IS_DEFINED (fragp->fr_symbol)
17496 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17501 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17503 addr = fragp->fr_address + fragp->fr_fix + 4;
17507 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17510 /* If the symbol is not defined or it's in a different segment,
17511 assume the user knows what's going on and emit a short
17517 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17519 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17520 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17521 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17522 RELAX_BRANCH_LINK (fragp->fr_subtype),
17528 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17531 if (mips_pic != NO_PIC)
17533 /* Additional space for PIC loading of target address. */
17535 if (mips_opts.isa == ISA_MIPS1)
17536 /* Additional space for $at-stabilizing nop. */
17540 /* If branch is conditional. */
17541 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17548 /* Compute the length of a branch sequence, and adjust the
17549 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17550 worst-case length is computed, with UPDATE being used to indicate
17551 whether an unconditional (-1), or regular (0) branch is to be
17555 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17557 bfd_boolean toofar;
17561 && S_IS_DEFINED (fragp->fr_symbol)
17562 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17567 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17568 /* Ignore the low bit in the target, since it will be set
17569 for a text label. */
17570 if ((val & 1) != 0)
17573 addr = fragp->fr_address + fragp->fr_fix + 4;
17577 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17580 /* If the symbol is not defined or it's in a different segment,
17581 assume the user knows what's going on and emit a short
17587 if (fragp && update
17588 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17589 fragp->fr_subtype = (toofar
17590 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17591 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17596 bfd_boolean compact_known = fragp != NULL;
17597 bfd_boolean compact = FALSE;
17598 bfd_boolean uncond;
17601 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17603 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17605 uncond = update < 0;
17607 /* If label is out of range, we turn branch <br>:
17609 <br> label # 4 bytes
17615 nop # 2 bytes if compact && !PIC
17618 if (mips_pic == NO_PIC && (!compact_known || compact))
17621 /* If assembling PIC code, we further turn:
17627 lw/ld at, %got(label)(gp) # 4 bytes
17628 d/addiu at, %lo(label) # 4 bytes
17631 if (mips_pic != NO_PIC)
17634 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17636 <brneg> 0f # 4 bytes
17637 nop # 2 bytes if !compact
17640 length += (compact_known && compact) ? 4 : 6;
17646 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17647 bit accordingly. */
17650 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17652 bfd_boolean toofar;
17655 && S_IS_DEFINED (fragp->fr_symbol)
17656 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17662 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17663 /* Ignore the low bit in the target, since it will be set
17664 for a text label. */
17665 if ((val & 1) != 0)
17668 /* Assume this is a 2-byte branch. */
17669 addr = fragp->fr_address + fragp->fr_fix + 2;
17671 /* We try to avoid the infinite loop by not adding 2 more bytes for
17676 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17678 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17679 else if (type == 'E')
17680 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17685 /* If the symbol is not defined or it's in a different segment,
17686 we emit a normal 32-bit branch. */
17689 if (fragp && update
17690 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17692 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17693 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17701 /* Estimate the size of a frag before relaxing. Unless this is the
17702 mips16, we are not really relaxing here, and the final size is
17703 encoded in the subtype information. For the mips16, we have to
17704 decide whether we are using an extended opcode or not. */
17707 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17711 if (RELAX_BRANCH_P (fragp->fr_subtype))
17714 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17716 return fragp->fr_var;
17719 if (RELAX_MIPS16_P (fragp->fr_subtype))
17720 /* We don't want to modify the EXTENDED bit here; it might get us
17721 into infinite loops. We change it only in mips_relax_frag(). */
17722 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17724 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17728 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17729 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17730 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17731 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17732 fragp->fr_var = length;
17737 if (mips_pic == NO_PIC)
17738 change = nopic_need_relax (fragp->fr_symbol, 0);
17739 else if (mips_pic == SVR4_PIC)
17740 change = pic_need_relax (fragp->fr_symbol, segtype);
17741 else if (mips_pic == VXWORKS_PIC)
17742 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17749 fragp->fr_subtype |= RELAX_USE_SECOND;
17750 return -RELAX_FIRST (fragp->fr_subtype);
17753 return -RELAX_SECOND (fragp->fr_subtype);
17756 /* This is called to see whether a reloc against a defined symbol
17757 should be converted into a reloc against a section. */
17760 mips_fix_adjustable (fixS *fixp)
17762 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17763 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17766 if (fixp->fx_addsy == NULL)
17769 /* If symbol SYM is in a mergeable section, relocations of the form
17770 SYM + 0 can usually be made section-relative. The mergeable data
17771 is then identified by the section offset rather than by the symbol.
17773 However, if we're generating REL LO16 relocations, the offset is split
17774 between the LO16 and parterning high part relocation. The linker will
17775 need to recalculate the complete offset in order to correctly identify
17778 The linker has traditionally not looked for the parterning high part
17779 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17780 placed anywhere. Rather than break backwards compatibility by changing
17781 this, it seems better not to force the issue, and instead keep the
17782 original symbol. This will work with either linker behavior. */
17783 if ((lo16_reloc_p (fixp->fx_r_type)
17784 || reloc_needs_lo_p (fixp->fx_r_type))
17785 && HAVE_IN_PLACE_ADDENDS
17786 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17789 /* There is no place to store an in-place offset for JALR relocations.
17790 Likewise an in-range offset of PC-relative relocations may overflow
17791 the in-place relocatable field if recalculated against the start
17792 address of the symbol's containing section. */
17793 if (HAVE_IN_PLACE_ADDENDS
17794 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17798 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17799 to a floating-point stub. The same is true for non-R_MIPS16_26
17800 relocations against MIPS16 functions; in this case, the stub becomes
17801 the function's canonical address.
17803 Floating-point stubs are stored in unique .mips16.call.* or
17804 .mips16.fn.* sections. If a stub T for function F is in section S,
17805 the first relocation in section S must be against F; this is how the
17806 linker determines the target function. All relocations that might
17807 resolve to T must also be against F. We therefore have the following
17808 restrictions, which are given in an intentionally-redundant way:
17810 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17813 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17814 if that stub might be used.
17816 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17819 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17820 that stub might be used.
17822 There is a further restriction:
17824 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17825 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17826 targets with in-place addends; the relocation field cannot
17827 encode the low bit.
17829 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17830 against a MIPS16 symbol. We deal with (5) by by not reducing any
17831 such relocations on REL targets.
17833 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17834 relocation against some symbol R, no relocation against R may be
17835 reduced. (Note that this deals with (2) as well as (1) because
17836 relocations against global symbols will never be reduced on ELF
17837 targets.) This approach is a little simpler than trying to detect
17838 stub sections, and gives the "all or nothing" per-symbol consistency
17839 that we have for MIPS16 symbols. */
17841 && fixp->fx_subsy == NULL
17842 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17843 || *symbol_get_tc (fixp->fx_addsy)
17844 || (HAVE_IN_PLACE_ADDENDS
17845 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17846 && jmp_reloc_p (fixp->fx_r_type))))
17853 /* Translate internal representation of relocation info to BFD target
17857 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17859 static arelent *retval[4];
17861 bfd_reloc_code_real_type code;
17863 memset (retval, 0, sizeof(retval));
17864 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17865 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17866 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17867 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17869 if (fixp->fx_pcrel)
17871 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17872 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17873 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17874 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17876 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17877 Relocations want only the symbol offset. */
17878 reloc->addend = fixp->fx_addnumber + reloc->address;
17881 /* A gruesome hack which is a result of the gruesome gas
17882 reloc handling. What's worse, for COFF (as opposed to
17883 ECOFF), we might need yet another copy of reloc->address.
17884 See bfd_install_relocation. */
17885 reloc->addend += reloc->address;
17889 reloc->addend = fixp->fx_addnumber;
17891 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17892 entry to be used in the relocation's section offset. */
17893 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17895 reloc->address = reloc->addend;
17899 code = fixp->fx_r_type;
17901 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17902 if (reloc->howto == NULL)
17904 as_bad_where (fixp->fx_file, fixp->fx_line,
17905 _("Can not represent %s relocation in this object file format"),
17906 bfd_get_reloc_code_name (code));
17913 /* Relax a machine dependent frag. This returns the amount by which
17914 the current size of the frag should change. */
17917 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17919 if (RELAX_BRANCH_P (fragp->fr_subtype))
17921 offsetT old_var = fragp->fr_var;
17923 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17925 return fragp->fr_var - old_var;
17928 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17930 offsetT old_var = fragp->fr_var;
17931 offsetT new_var = 4;
17933 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17934 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17935 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17936 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17937 fragp->fr_var = new_var;
17939 return new_var - old_var;
17942 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17945 if (mips16_extended_frag (fragp, NULL, stretch))
17947 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17949 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17954 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17956 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17963 /* Convert a machine dependent frag. */
17966 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17968 if (RELAX_BRANCH_P (fragp->fr_subtype))
17971 unsigned long insn;
17975 buf = fragp->fr_literal + fragp->fr_fix;
17976 insn = read_insn (buf);
17978 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17980 /* We generate a fixup instead of applying it right now
17981 because, if there are linker relaxations, we're going to
17982 need the relocations. */
17983 exp.X_op = O_symbol;
17984 exp.X_add_symbol = fragp->fr_symbol;
17985 exp.X_add_number = fragp->fr_offset;
17987 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17988 BFD_RELOC_16_PCREL_S2);
17989 fixp->fx_file = fragp->fr_file;
17990 fixp->fx_line = fragp->fr_line;
17992 buf = write_insn (buf, insn);
17998 as_warn_where (fragp->fr_file, fragp->fr_line,
17999 _("Relaxed out-of-range branch into a jump"));
18001 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18004 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18006 /* Reverse the branch. */
18007 switch ((insn >> 28) & 0xf)
18010 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
18011 have the condition reversed by tweaking a single
18012 bit, and their opcodes all have 0x4???????. */
18013 gas_assert ((insn & 0xf1000000) == 0x41000000);
18014 insn ^= 0x00010000;
18018 /* bltz 0x04000000 bgez 0x04010000
18019 bltzal 0x04100000 bgezal 0x04110000 */
18020 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18021 insn ^= 0x00010000;
18025 /* beq 0x10000000 bne 0x14000000
18026 blez 0x18000000 bgtz 0x1c000000 */
18027 insn ^= 0x04000000;
18035 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18037 /* Clear the and-link bit. */
18038 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18040 /* bltzal 0x04100000 bgezal 0x04110000
18041 bltzall 0x04120000 bgezall 0x04130000 */
18042 insn &= ~0x00100000;
18045 /* Branch over the branch (if the branch was likely) or the
18046 full jump (not likely case). Compute the offset from the
18047 current instruction to branch to. */
18048 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18052 /* How many bytes in instructions we've already emitted? */
18053 i = buf - fragp->fr_literal - fragp->fr_fix;
18054 /* How many bytes in instructions from here to the end? */
18055 i = fragp->fr_var - i;
18057 /* Convert to instruction count. */
18059 /* Branch counts from the next instruction. */
18062 /* Branch over the jump. */
18063 buf = write_insn (buf, insn);
18066 buf = write_insn (buf, 0);
18068 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18070 /* beql $0, $0, 2f */
18072 /* Compute the PC offset from the current instruction to
18073 the end of the variable frag. */
18074 /* How many bytes in instructions we've already emitted? */
18075 i = buf - fragp->fr_literal - fragp->fr_fix;
18076 /* How many bytes in instructions from here to the end? */
18077 i = fragp->fr_var - i;
18078 /* Convert to instruction count. */
18080 /* Don't decrement i, because we want to branch over the
18084 buf = write_insn (buf, insn);
18085 buf = write_insn (buf, 0);
18089 if (mips_pic == NO_PIC)
18092 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18093 ? 0x0c000000 : 0x08000000);
18094 exp.X_op = O_symbol;
18095 exp.X_add_symbol = fragp->fr_symbol;
18096 exp.X_add_number = fragp->fr_offset;
18098 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18099 FALSE, BFD_RELOC_MIPS_JMP);
18100 fixp->fx_file = fragp->fr_file;
18101 fixp->fx_line = fragp->fr_line;
18103 buf = write_insn (buf, insn);
18107 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18109 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18110 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18111 insn |= at << OP_SH_RT;
18112 exp.X_op = O_symbol;
18113 exp.X_add_symbol = fragp->fr_symbol;
18114 exp.X_add_number = fragp->fr_offset;
18116 if (fragp->fr_offset)
18118 exp.X_add_symbol = make_expr_symbol (&exp);
18119 exp.X_add_number = 0;
18122 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18123 FALSE, BFD_RELOC_MIPS_GOT16);
18124 fixp->fx_file = fragp->fr_file;
18125 fixp->fx_line = fragp->fr_line;
18127 buf = write_insn (buf, insn);
18129 if (mips_opts.isa == ISA_MIPS1)
18131 buf = write_insn (buf, 0);
18133 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18134 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18135 insn |= at << OP_SH_RS | at << OP_SH_RT;
18137 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18138 FALSE, BFD_RELOC_LO16);
18139 fixp->fx_file = fragp->fr_file;
18140 fixp->fx_line = fragp->fr_line;
18142 buf = write_insn (buf, insn);
18145 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18149 insn |= at << OP_SH_RS;
18151 buf = write_insn (buf, insn);
18155 fragp->fr_fix += fragp->fr_var;
18156 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18160 /* Relax microMIPS branches. */
18161 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18163 char *buf = fragp->fr_literal + fragp->fr_fix;
18164 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18165 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18166 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18167 bfd_boolean short_ds;
18168 unsigned long insn;
18172 exp.X_op = O_symbol;
18173 exp.X_add_symbol = fragp->fr_symbol;
18174 exp.X_add_number = fragp->fr_offset;
18176 fragp->fr_fix += fragp->fr_var;
18178 /* Handle 16-bit branches that fit or are forced to fit. */
18179 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18181 /* We generate a fixup instead of applying it right now,
18182 because if there is linker relaxation, we're going to
18183 need the relocations. */
18185 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18186 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18187 else if (type == 'E')
18188 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18189 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18193 fixp->fx_file = fragp->fr_file;
18194 fixp->fx_line = fragp->fr_line;
18196 /* These relocations can have an addend that won't fit in
18198 fixp->fx_no_overflow = 1;
18203 /* Handle 32-bit branches that fit or are forced to fit. */
18204 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18205 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18207 /* We generate a fixup instead of applying it right now,
18208 because if there is linker relaxation, we're going to
18209 need the relocations. */
18210 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18211 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18212 fixp->fx_file = fragp->fr_file;
18213 fixp->fx_line = fragp->fr_line;
18219 /* Relax 16-bit branches to 32-bit branches. */
18222 insn = read_compressed_insn (buf, 2);
18224 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18225 insn = 0x94000000; /* beq */
18226 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18228 unsigned long regno;
18230 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18231 regno = micromips_to_32_reg_d_map [regno];
18232 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18233 insn |= regno << MICROMIPSOP_SH_RS;
18238 /* Nothing else to do, just write it out. */
18239 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18240 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18242 buf = write_compressed_insn (buf, insn, 4);
18243 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18248 insn = read_compressed_insn (buf, 4);
18250 /* Relax 32-bit branches to a sequence of instructions. */
18251 as_warn_where (fragp->fr_file, fragp->fr_line,
18252 _("Relaxed out-of-range branch into a jump"));
18254 /* Set the short-delay-slot bit. */
18255 short_ds = al && (insn & 0x02000000) != 0;
18257 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18261 /* Reverse the branch. */
18262 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18263 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18264 insn ^= 0x20000000;
18265 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18266 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18267 || (insn & 0xffe00000) == 0x40800000 /* blez */
18268 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18269 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18270 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18271 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18272 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18273 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18274 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18275 insn ^= 0x00400000;
18276 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18277 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18278 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18279 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18280 insn ^= 0x00200000;
18286 /* Clear the and-link and short-delay-slot bits. */
18287 gas_assert ((insn & 0xfda00000) == 0x40200000);
18289 /* bltzal 0x40200000 bgezal 0x40600000 */
18290 /* bltzals 0x42200000 bgezals 0x42600000 */
18291 insn &= ~0x02200000;
18294 /* Make a label at the end for use with the branch. */
18295 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18296 micromips_label_inc ();
18297 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18299 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18303 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18304 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18305 fixp->fx_file = fragp->fr_file;
18306 fixp->fx_line = fragp->fr_line;
18308 /* Branch over the jump. */
18309 buf = write_compressed_insn (buf, insn, 4);
18312 buf = write_compressed_insn (buf, 0x0c00, 2);
18315 if (mips_pic == NO_PIC)
18317 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18319 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18320 insn = al ? jal : 0xd4000000;
18322 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18323 BFD_RELOC_MICROMIPS_JMP);
18324 fixp->fx_file = fragp->fr_file;
18325 fixp->fx_line = fragp->fr_line;
18327 buf = write_compressed_insn (buf, insn, 4);
18330 buf = write_compressed_insn (buf, 0x0c00, 2);
18334 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18335 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18336 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18338 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18339 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18340 insn |= at << MICROMIPSOP_SH_RT;
18342 if (exp.X_add_number)
18344 exp.X_add_symbol = make_expr_symbol (&exp);
18345 exp.X_add_number = 0;
18348 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18349 BFD_RELOC_MICROMIPS_GOT16);
18350 fixp->fx_file = fragp->fr_file;
18351 fixp->fx_line = fragp->fr_line;
18353 buf = write_compressed_insn (buf, insn, 4);
18355 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18356 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18357 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18359 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18360 BFD_RELOC_MICROMIPS_LO16);
18361 fixp->fx_file = fragp->fr_file;
18362 fixp->fx_line = fragp->fr_line;
18364 buf = write_compressed_insn (buf, insn, 4);
18366 /* jr/jrc/jalr/jalrs $at */
18367 insn = al ? jalr : jr;
18368 insn |= at << MICROMIPSOP_SH_MJ;
18370 buf = write_compressed_insn (buf, insn, 2);
18373 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18377 if (RELAX_MIPS16_P (fragp->fr_subtype))
18380 const struct mips16_immed_operand *op;
18383 unsigned int user_length, length;
18384 unsigned long insn;
18387 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18388 op = mips16_immed_operands;
18389 while (op->type != type)
18392 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18393 val = resolve_symbol_value (fragp->fr_symbol);
18398 addr = fragp->fr_address + fragp->fr_fix;
18400 /* The rules for the base address of a PC relative reloc are
18401 complicated; see mips16_extended_frag. */
18402 if (type == 'p' || type == 'q')
18407 /* Ignore the low bit in the target, since it will be
18408 set for a text label. */
18409 if ((val & 1) != 0)
18412 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18414 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18417 addr &= ~ (addressT) ((1 << op->shift) - 1);
18420 /* Make sure the section winds up with the alignment we have
18423 record_alignment (asec, op->shift);
18427 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18428 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18429 as_warn_where (fragp->fr_file, fragp->fr_line,
18430 _("extended instruction in delay slot"));
18432 buf = fragp->fr_literal + fragp->fr_fix;
18434 insn = read_compressed_insn (buf, 2);
18436 insn |= MIPS16_EXTEND;
18438 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18440 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18445 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18446 BFD_RELOC_UNUSED, val, user_length, &insn);
18448 length = (ext ? 4 : 2);
18449 gas_assert (mips16_opcode_length (insn) == length);
18450 write_compressed_insn (buf, insn, length);
18451 fragp->fr_fix += length;
18455 relax_substateT subtype = fragp->fr_subtype;
18456 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18457 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18461 first = RELAX_FIRST (subtype);
18462 second = RELAX_SECOND (subtype);
18463 fixp = (fixS *) fragp->fr_opcode;
18465 /* If the delay slot chosen does not match the size of the instruction,
18466 then emit a warning. */
18467 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18468 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18473 s = subtype & (RELAX_DELAY_SLOT_16BIT
18474 | RELAX_DELAY_SLOT_SIZE_FIRST
18475 | RELAX_DELAY_SLOT_SIZE_SECOND);
18476 msg = macro_warning (s);
18478 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18482 /* Possibly emit a warning if we've chosen the longer option. */
18483 if (use_second == second_longer)
18489 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18490 msg = macro_warning (s);
18492 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18496 /* Go through all the fixups for the first sequence. Disable them
18497 (by marking them as done) if we're going to use the second
18498 sequence instead. */
18500 && fixp->fx_frag == fragp
18501 && fixp->fx_where < fragp->fr_fix - second)
18503 if (subtype & RELAX_USE_SECOND)
18505 fixp = fixp->fx_next;
18508 /* Go through the fixups for the second sequence. Disable them if
18509 we're going to use the first sequence, otherwise adjust their
18510 addresses to account for the relaxation. */
18511 while (fixp && fixp->fx_frag == fragp)
18513 if (subtype & RELAX_USE_SECOND)
18514 fixp->fx_where -= first;
18517 fixp = fixp->fx_next;
18520 /* Now modify the frag contents. */
18521 if (subtype & RELAX_USE_SECOND)
18525 start = fragp->fr_literal + fragp->fr_fix - first - second;
18526 memmove (start, start + first, second);
18527 fragp->fr_fix -= first;
18530 fragp->fr_fix -= second;
18536 /* This function is called after the relocs have been generated.
18537 We've been storing mips16 text labels as odd. Here we convert them
18538 back to even for the convenience of the debugger. */
18541 mips_frob_file_after_relocs (void)
18544 unsigned int count, i;
18549 syms = bfd_get_outsymbols (stdoutput);
18550 count = bfd_get_symcount (stdoutput);
18551 for (i = 0; i < count; i++, syms++)
18552 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18553 && ((*syms)->value & 1) != 0)
18555 (*syms)->value &= ~1;
18556 /* If the symbol has an odd size, it was probably computed
18557 incorrectly, so adjust that as well. */
18558 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18559 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18565 /* This function is called whenever a label is defined, including fake
18566 labels instantiated off the dot special symbol. It is used when
18567 handling branch delays; if a branch has a label, we assume we cannot
18568 move it. This also bumps the value of the symbol by 1 in compressed
18572 mips_record_label (symbolS *sym)
18574 segment_info_type *si = seg_info (now_seg);
18575 struct insn_label_list *l;
18577 if (free_insn_labels == NULL)
18578 l = (struct insn_label_list *) xmalloc (sizeof *l);
18581 l = free_insn_labels;
18582 free_insn_labels = l->next;
18586 l->next = si->label_list;
18587 si->label_list = l;
18590 /* This function is called as tc_frob_label() whenever a label is defined
18591 and adds a DWARF-2 record we only want for true labels. */
18594 mips_define_label (symbolS *sym)
18596 mips_record_label (sym);
18598 dwarf2_emit_label (sym);
18602 /* This function is called by tc_new_dot_label whenever a new dot symbol
18606 mips_add_dot_label (symbolS *sym)
18608 mips_record_label (sym);
18609 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18610 mips_compressed_mark_label (sym);
18613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18615 /* Some special processing for a MIPS ELF file. */
18618 mips_elf_final_processing (void)
18620 /* Write out the register information. */
18621 if (mips_abi != N64_ABI)
18625 s.ri_gprmask = mips_gprmask;
18626 s.ri_cprmask[0] = mips_cprmask[0];
18627 s.ri_cprmask[1] = mips_cprmask[1];
18628 s.ri_cprmask[2] = mips_cprmask[2];
18629 s.ri_cprmask[3] = mips_cprmask[3];
18630 /* The gp_value field is set by the MIPS ELF backend. */
18632 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18633 ((Elf32_External_RegInfo *)
18634 mips_regmask_frag));
18638 Elf64_Internal_RegInfo s;
18640 s.ri_gprmask = mips_gprmask;
18642 s.ri_cprmask[0] = mips_cprmask[0];
18643 s.ri_cprmask[1] = mips_cprmask[1];
18644 s.ri_cprmask[2] = mips_cprmask[2];
18645 s.ri_cprmask[3] = mips_cprmask[3];
18646 /* The gp_value field is set by the MIPS ELF backend. */
18648 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18649 ((Elf64_External_RegInfo *)
18650 mips_regmask_frag));
18653 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18654 sort of BFD interface for this. */
18655 if (mips_any_noreorder)
18656 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18657 if (mips_pic != NO_PIC)
18659 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18660 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18663 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18665 /* Set MIPS ELF flags for ASEs. */
18666 /* We may need to define a new flag for DSP ASE, and set this flag when
18667 file_ase_dsp is true. */
18668 /* Same for DSP R2. */
18669 /* We may need to define a new flag for MT ASE, and set this flag when
18670 file_ase_mt is true. */
18671 if (file_ase_mips16)
18672 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18673 if (file_ase_micromips)
18674 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18675 #if 0 /* XXX FIXME */
18676 if (file_ase_mips3d)
18677 elf_elfheader (stdoutput)->e_flags |= ???;
18680 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18682 /* Set the MIPS ELF ABI flags. */
18683 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18684 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18685 else if (mips_abi == O64_ABI)
18686 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18687 else if (mips_abi == EABI_ABI)
18689 if (!file_mips_gp32)
18690 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18692 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18694 else if (mips_abi == N32_ABI)
18695 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18697 /* Nothing to do for N64_ABI. */
18699 if (mips_32bitmode)
18700 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18702 #if 0 /* XXX FIXME */
18703 /* 32 bit code with 64 bit FP registers. */
18704 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18705 elf_elfheader (stdoutput)->e_flags |= ???;
18709 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18711 typedef struct proc {
18713 symbolS *func_end_sym;
18714 unsigned long reg_mask;
18715 unsigned long reg_offset;
18716 unsigned long fpreg_mask;
18717 unsigned long fpreg_offset;
18718 unsigned long frame_offset;
18719 unsigned long frame_reg;
18720 unsigned long pc_reg;
18723 static procS cur_proc;
18724 static procS *cur_proc_ptr;
18725 static int numprocs;
18727 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18728 as "2", and a normal nop as "0". */
18730 #define NOP_OPCODE_MIPS 0
18731 #define NOP_OPCODE_MIPS16 1
18732 #define NOP_OPCODE_MICROMIPS 2
18735 mips_nop_opcode (void)
18737 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18738 return NOP_OPCODE_MICROMIPS;
18739 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18740 return NOP_OPCODE_MIPS16;
18742 return NOP_OPCODE_MIPS;
18745 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18746 32-bit microMIPS NOPs here (if applicable). */
18749 mips_handle_align (fragS *fragp)
18753 int bytes, size, excess;
18756 if (fragp->fr_type != rs_align_code)
18759 p = fragp->fr_literal + fragp->fr_fix;
18761 switch (nop_opcode)
18763 case NOP_OPCODE_MICROMIPS:
18764 opcode = micromips_nop32_insn.insn_opcode;
18767 case NOP_OPCODE_MIPS16:
18768 opcode = mips16_nop_insn.insn_opcode;
18771 case NOP_OPCODE_MIPS:
18773 opcode = nop_insn.insn_opcode;
18778 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18779 excess = bytes % size;
18781 /* Handle the leading part if we're not inserting a whole number of
18782 instructions, and make it the end of the fixed part of the frag.
18783 Try to fit in a short microMIPS NOP if applicable and possible,
18784 and use zeroes otherwise. */
18785 gas_assert (excess < 4);
18786 fragp->fr_fix += excess;
18791 /* Fall through. */
18793 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18795 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18799 /* Fall through. */
18802 /* Fall through. */
18807 md_number_to_chars (p, opcode, size);
18808 fragp->fr_var = size;
18812 md_obj_begin (void)
18819 /* Check for premature end, nesting errors, etc. */
18821 as_warn (_("missing .end at end of assembly"));
18830 if (*input_line_pointer == '-')
18832 ++input_line_pointer;
18835 if (!ISDIGIT (*input_line_pointer))
18836 as_bad (_("expected simple number"));
18837 if (input_line_pointer[0] == '0')
18839 if (input_line_pointer[1] == 'x')
18841 input_line_pointer += 2;
18842 while (ISXDIGIT (*input_line_pointer))
18845 val |= hex_value (*input_line_pointer++);
18847 return negative ? -val : val;
18851 ++input_line_pointer;
18852 while (ISDIGIT (*input_line_pointer))
18855 val |= *input_line_pointer++ - '0';
18857 return negative ? -val : val;
18860 if (!ISDIGIT (*input_line_pointer))
18862 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18863 *input_line_pointer, *input_line_pointer);
18864 as_warn (_("invalid number"));
18867 while (ISDIGIT (*input_line_pointer))
18870 val += *input_line_pointer++ - '0';
18872 return negative ? -val : val;
18875 /* The .file directive; just like the usual .file directive, but there
18876 is an initial number which is the ECOFF file index. In the non-ECOFF
18877 case .file implies DWARF-2. */
18880 s_mips_file (int x ATTRIBUTE_UNUSED)
18882 static int first_file_directive = 0;
18884 if (ECOFF_DEBUGGING)
18893 filename = dwarf2_directive_file (0);
18895 /* Versions of GCC up to 3.1 start files with a ".file"
18896 directive even for stabs output. Make sure that this
18897 ".file" is handled. Note that you need a version of GCC
18898 after 3.1 in order to support DWARF-2 on MIPS. */
18899 if (filename != NULL && ! first_file_directive)
18901 (void) new_logical_line (filename, -1);
18902 s_app_file_string (filename, 0);
18904 first_file_directive = 1;
18908 /* The .loc directive, implying DWARF-2. */
18911 s_mips_loc (int x ATTRIBUTE_UNUSED)
18913 if (!ECOFF_DEBUGGING)
18914 dwarf2_directive_loc (0);
18917 /* The .end directive. */
18920 s_mips_end (int x ATTRIBUTE_UNUSED)
18924 /* Following functions need their own .frame and .cprestore directives. */
18925 mips_frame_reg_valid = 0;
18926 mips_cprestore_valid = 0;
18928 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18931 demand_empty_rest_of_line ();
18936 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18937 as_warn (_(".end not in text section"));
18941 as_warn (_(".end directive without a preceding .ent directive."));
18942 demand_empty_rest_of_line ();
18948 gas_assert (S_GET_NAME (p));
18949 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18950 as_warn (_(".end symbol does not match .ent symbol."));
18952 if (debug_type == DEBUG_STABS)
18953 stabs_generate_asm_endfunc (S_GET_NAME (p),
18957 as_warn (_(".end directive missing or unknown symbol"));
18960 /* Create an expression to calculate the size of the function. */
18961 if (p && cur_proc_ptr)
18963 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18964 expressionS *exp = xmalloc (sizeof (expressionS));
18967 exp->X_op = O_subtract;
18968 exp->X_add_symbol = symbol_temp_new_now ();
18969 exp->X_op_symbol = p;
18970 exp->X_add_number = 0;
18972 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18975 /* Generate a .pdr section. */
18976 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18978 segT saved_seg = now_seg;
18979 subsegT saved_subseg = now_subseg;
18983 #ifdef md_flush_pending_output
18984 md_flush_pending_output ();
18987 gas_assert (pdr_seg);
18988 subseg_set (pdr_seg, 0);
18990 /* Write the symbol. */
18991 exp.X_op = O_symbol;
18992 exp.X_add_symbol = p;
18993 exp.X_add_number = 0;
18994 emit_expr (&exp, 4);
18996 fragp = frag_more (7 * 4);
18998 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18999 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19000 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19001 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19002 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19003 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19004 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19006 subseg_set (saved_seg, saved_subseg);
19008 #endif /* OBJ_ELF */
19010 cur_proc_ptr = NULL;
19013 /* The .aent and .ent directives. */
19016 s_mips_ent (int aent)
19020 symbolP = get_symbol ();
19021 if (*input_line_pointer == ',')
19022 ++input_line_pointer;
19023 SKIP_WHITESPACE ();
19024 if (ISDIGIT (*input_line_pointer)
19025 || *input_line_pointer == '-')
19028 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19029 as_warn (_(".ent or .aent not in text section."));
19031 if (!aent && cur_proc_ptr)
19032 as_warn (_("missing .end"));
19036 /* This function needs its own .frame and .cprestore directives. */
19037 mips_frame_reg_valid = 0;
19038 mips_cprestore_valid = 0;
19040 cur_proc_ptr = &cur_proc;
19041 memset (cur_proc_ptr, '\0', sizeof (procS));
19043 cur_proc_ptr->func_sym = symbolP;
19047 if (debug_type == DEBUG_STABS)
19048 stabs_generate_asm_func (S_GET_NAME (symbolP),
19049 S_GET_NAME (symbolP));
19052 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19054 demand_empty_rest_of_line ();
19057 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19058 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19059 s_mips_frame is used so that we can set the PDR information correctly.
19060 We can't use the ecoff routines because they make reference to the ecoff
19061 symbol table (in the mdebug section). */
19064 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19067 if (IS_ELF && !ECOFF_DEBUGGING)
19071 if (cur_proc_ptr == (procS *) NULL)
19073 as_warn (_(".frame outside of .ent"));
19074 demand_empty_rest_of_line ();
19078 cur_proc_ptr->frame_reg = tc_get_register (1);
19080 SKIP_WHITESPACE ();
19081 if (*input_line_pointer++ != ','
19082 || get_absolute_expression_and_terminator (&val) != ',')
19084 as_warn (_("Bad .frame directive"));
19085 --input_line_pointer;
19086 demand_empty_rest_of_line ();
19090 cur_proc_ptr->frame_offset = val;
19091 cur_proc_ptr->pc_reg = tc_get_register (0);
19093 demand_empty_rest_of_line ();
19096 #endif /* OBJ_ELF */
19100 /* The .fmask and .mask directives. If the mdebug section is present
19101 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19102 embedded targets, s_mips_mask is used so that we can set the PDR
19103 information correctly. We can't use the ecoff routines because they
19104 make reference to the ecoff symbol table (in the mdebug section). */
19107 s_mips_mask (int reg_type)
19110 if (IS_ELF && !ECOFF_DEBUGGING)
19114 if (cur_proc_ptr == (procS *) NULL)
19116 as_warn (_(".mask/.fmask outside of .ent"));
19117 demand_empty_rest_of_line ();
19121 if (get_absolute_expression_and_terminator (&mask) != ',')
19123 as_warn (_("Bad .mask/.fmask directive"));
19124 --input_line_pointer;
19125 demand_empty_rest_of_line ();
19129 off = get_absolute_expression ();
19131 if (reg_type == 'F')
19133 cur_proc_ptr->fpreg_mask = mask;
19134 cur_proc_ptr->fpreg_offset = off;
19138 cur_proc_ptr->reg_mask = mask;
19139 cur_proc_ptr->reg_offset = off;
19142 demand_empty_rest_of_line ();
19145 #endif /* OBJ_ELF */
19146 s_ignore (reg_type);
19149 /* A table describing all the processors gas knows about. Names are
19150 matched in the order listed.
19152 To ease comparison, please keep this table in the same order as
19153 gcc's mips_cpu_info_table[]. */
19154 static const struct mips_cpu_info mips_cpu_info_table[] =
19156 /* Entries for generic ISAs */
19157 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19158 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19159 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19160 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19161 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19162 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19163 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19164 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19165 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19168 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19169 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19170 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19173 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19176 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19177 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19178 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19179 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19180 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19181 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19182 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19183 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19184 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19185 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19186 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19187 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19188 { "r5900", 0, ISA_MIPS3, CPU_R5900 },
19189 /* ST Microelectronics Loongson 2E and 2F cores */
19190 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19191 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19194 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19195 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19196 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19197 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19198 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19199 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19200 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19201 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19202 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19203 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19204 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19205 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19206 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19207 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19208 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19211 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19212 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19213 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19214 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19216 /* MIPS 32 Release 2 */
19217 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19218 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19219 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19220 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19221 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19222 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19223 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19224 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19225 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19226 ISA_MIPS32R2, CPU_MIPS32R2 },
19227 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19228 ISA_MIPS32R2, CPU_MIPS32R2 },
19229 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19230 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19231 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19232 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19233 /* Deprecated forms of the above. */
19234 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19235 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19236 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19237 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19238 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19239 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19240 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19241 /* Deprecated forms of the above. */
19242 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19243 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19244 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19245 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19246 ISA_MIPS32R2, CPU_MIPS32R2 },
19247 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19248 ISA_MIPS32R2, CPU_MIPS32R2 },
19249 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19250 ISA_MIPS32R2, CPU_MIPS32R2 },
19251 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19252 ISA_MIPS32R2, CPU_MIPS32R2 },
19253 /* Deprecated forms of the above. */
19254 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19255 ISA_MIPS32R2, CPU_MIPS32R2 },
19256 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19257 ISA_MIPS32R2, CPU_MIPS32R2 },
19258 /* 34Kn is a 34kc without DSP. */
19259 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19260 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19261 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19262 ISA_MIPS32R2, CPU_MIPS32R2 },
19263 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19264 ISA_MIPS32R2, CPU_MIPS32R2 },
19265 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19266 ISA_MIPS32R2, CPU_MIPS32R2 },
19267 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19268 ISA_MIPS32R2, CPU_MIPS32R2 },
19269 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19270 ISA_MIPS32R2, CPU_MIPS32R2 },
19271 /* Deprecated forms of the above. */
19272 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19273 ISA_MIPS32R2, CPU_MIPS32R2 },
19274 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19275 ISA_MIPS32R2, CPU_MIPS32R2 },
19276 /* 1004K cores are multiprocessor versions of the 34K. */
19277 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19278 ISA_MIPS32R2, CPU_MIPS32R2 },
19279 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19280 ISA_MIPS32R2, CPU_MIPS32R2 },
19281 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19282 ISA_MIPS32R2, CPU_MIPS32R2 },
19283 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19284 ISA_MIPS32R2, CPU_MIPS32R2 },
19287 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19288 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19289 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19290 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19292 /* Broadcom SB-1 CPU core */
19293 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19294 ISA_MIPS64, CPU_SB1 },
19295 /* Broadcom SB-1A CPU core */
19296 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19297 ISA_MIPS64, CPU_SB1 },
19299 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19301 /* MIPS 64 Release 2 */
19303 /* Cavium Networks Octeon CPU core */
19304 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19305 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19306 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19309 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19312 XLP is mostly like XLR, with the prominent exception that it is
19313 MIPS64R2 rather than MIPS64. */
19314 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19321 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19322 with a final "000" replaced by "k". Ignore case.
19324 Note: this function is shared between GCC and GAS. */
19327 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19329 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19330 given++, canonical++;
19332 return ((*given == 0 && *canonical == 0)
19333 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19337 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19338 CPU name. We've traditionally allowed a lot of variation here.
19340 Note: this function is shared between GCC and GAS. */
19343 mips_matching_cpu_name_p (const char *canonical, const char *given)
19345 /* First see if the name matches exactly, or with a final "000"
19346 turned into "k". */
19347 if (mips_strict_matching_cpu_name_p (canonical, given))
19350 /* If not, try comparing based on numerical designation alone.
19351 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19352 if (TOLOWER (*given) == 'r')
19354 if (!ISDIGIT (*given))
19357 /* Skip over some well-known prefixes in the canonical name,
19358 hoping to find a number there too. */
19359 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19361 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19363 else if (TOLOWER (canonical[0]) == 'r')
19366 return mips_strict_matching_cpu_name_p (canonical, given);
19370 /* Parse an option that takes the name of a processor as its argument.
19371 OPTION is the name of the option and CPU_STRING is the argument.
19372 Return the corresponding processor enumeration if the CPU_STRING is
19373 recognized, otherwise report an error and return null.
19375 A similar function exists in GCC. */
19377 static const struct mips_cpu_info *
19378 mips_parse_cpu (const char *option, const char *cpu_string)
19380 const struct mips_cpu_info *p;
19382 /* 'from-abi' selects the most compatible architecture for the given
19383 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19384 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19385 version. Look first at the -mgp options, if given, otherwise base
19386 the choice on MIPS_DEFAULT_64BIT.
19388 Treat NO_ABI like the EABIs. One reason to do this is that the
19389 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19390 architecture. This code picks MIPS I for 'mips' and MIPS III for
19391 'mips64', just as we did in the days before 'from-abi'. */
19392 if (strcasecmp (cpu_string, "from-abi") == 0)
19394 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19395 return mips_cpu_info_from_isa (ISA_MIPS1);
19397 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19398 return mips_cpu_info_from_isa (ISA_MIPS3);
19400 if (file_mips_gp32 >= 0)
19401 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19403 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19408 /* 'default' has traditionally been a no-op. Probably not very useful. */
19409 if (strcasecmp (cpu_string, "default") == 0)
19412 for (p = mips_cpu_info_table; p->name != 0; p++)
19413 if (mips_matching_cpu_name_p (p->name, cpu_string))
19416 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19420 /* Return the canonical processor information for ISA (a member of the
19421 ISA_MIPS* enumeration). */
19423 static const struct mips_cpu_info *
19424 mips_cpu_info_from_isa (int isa)
19428 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19429 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19430 && isa == mips_cpu_info_table[i].isa)
19431 return (&mips_cpu_info_table[i]);
19436 static const struct mips_cpu_info *
19437 mips_cpu_info_from_arch (int arch)
19441 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19442 if (arch == mips_cpu_info_table[i].cpu)
19443 return (&mips_cpu_info_table[i]);
19449 show (FILE *stream, const char *string, int *col_p, int *first_p)
19453 fprintf (stream, "%24s", "");
19458 fprintf (stream, ", ");
19462 if (*col_p + strlen (string) > 72)
19464 fprintf (stream, "\n%24s", "");
19468 fprintf (stream, "%s", string);
19469 *col_p += strlen (string);
19475 md_show_usage (FILE *stream)
19480 fprintf (stream, _("\
19482 -EB generate big endian output\n\
19483 -EL generate little endian output\n\
19484 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19485 -G NUM allow referencing objects up to NUM bytes\n\
19486 implicitly with the gp register [default 8]\n"));
19487 fprintf (stream, _("\
19488 -mips1 generate MIPS ISA I instructions\n\
19489 -mips2 generate MIPS ISA II instructions\n\
19490 -mips3 generate MIPS ISA III instructions\n\
19491 -mips4 generate MIPS ISA IV instructions\n\
19492 -mips5 generate MIPS ISA V instructions\n\
19493 -mips32 generate MIPS32 ISA instructions\n\
19494 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19495 -mips64 generate MIPS64 ISA instructions\n\
19496 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19497 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19501 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19502 show (stream, mips_cpu_info_table[i].name, &column, &first);
19503 show (stream, "from-abi", &column, &first);
19504 fputc ('\n', stream);
19506 fprintf (stream, _("\
19507 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19508 -no-mCPU don't generate code specific to CPU.\n\
19509 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19513 show (stream, "3900", &column, &first);
19514 show (stream, "4010", &column, &first);
19515 show (stream, "4100", &column, &first);
19516 show (stream, "4650", &column, &first);
19517 fputc ('\n', stream);
19519 fprintf (stream, _("\
19520 -mips16 generate mips16 instructions\n\
19521 -no-mips16 do not generate mips16 instructions\n"));
19522 fprintf (stream, _("\
19523 -mmicromips generate microMIPS instructions\n\
19524 -mno-micromips do not generate microMIPS instructions\n"));
19525 fprintf (stream, _("\
19526 -msmartmips generate smartmips instructions\n\
19527 -mno-smartmips do not generate smartmips instructions\n"));
19528 fprintf (stream, _("\
19529 -mdsp generate DSP instructions\n\
19530 -mno-dsp do not generate DSP instructions\n"));
19531 fprintf (stream, _("\
19532 -mdspr2 generate DSP R2 instructions\n\
19533 -mno-dspr2 do not generate DSP R2 instructions\n"));
19534 fprintf (stream, _("\
19535 -mmt generate MT instructions\n\
19536 -mno-mt do not generate MT instructions\n"));
19537 fprintf (stream, _("\
19538 -mmcu generate MCU instructions\n\
19539 -mno-mcu do not generate MCU instructions\n"));
19540 fprintf (stream, _("\
19541 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19542 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19543 -mfix-vr4120 work around certain VR4120 errata\n\
19544 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19545 -mfix-24k insert a nop after ERET and DERET instructions\n\
19546 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19547 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19548 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19549 -msym32 assume all symbols have 32-bit values\n\
19550 -O0 remove unneeded NOPs, do not swap branches\n\
19551 -O remove unneeded NOPs and swap branches\n\
19552 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19553 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19554 fprintf (stream, _("\
19555 -mhard-float allow floating-point instructions\n\
19556 -msoft-float do not allow floating-point instructions\n\
19557 -msingle-float only allow 32-bit floating-point operations\n\
19558 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19559 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19562 fprintf (stream, _("\
19563 -KPIC, -call_shared generate SVR4 position independent code\n\
19564 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19565 -mvxworks-pic generate VxWorks position independent code\n\
19566 -non_shared do not generate code that can operate with DSOs\n\
19567 -xgot assume a 32 bit GOT\n\
19568 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19569 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19570 position dependent (non shared) code\n\
19571 -mabi=ABI create ABI conformant object file for:\n"));
19575 show (stream, "32", &column, &first);
19576 show (stream, "o64", &column, &first);
19577 show (stream, "n32", &column, &first);
19578 show (stream, "64", &column, &first);
19579 show (stream, "eabi", &column, &first);
19581 fputc ('\n', stream);
19583 fprintf (stream, _("\
19584 -32 create o32 ABI object file (default)\n\
19585 -n32 create n32 ABI object file\n\
19586 -64 create 64 ABI object file\n"));
19592 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19594 if (HAVE_64BIT_SYMBOLS)
19595 return dwarf2_format_64bit_irix;
19597 return dwarf2_format_32bit;
19602 mips_dwarf2_addr_size (void)
19604 if (HAVE_64BIT_OBJECTS)
19610 /* Standard calling conventions leave the CFA at SP on entry. */
19612 mips_cfi_frame_initial_instructions (void)
19614 cfi_add_CFA_def_cfa_register (SP);
19618 tc_mips_regname_to_dw2regnum (char *regname)
19620 unsigned int regnum = -1;
19623 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))