1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Ways in which an instruction can be "appended" to the output. */
126 /* Just add it normally. */
129 /* Add it normally and then add a nop. */
132 /* Turn an instruction with a delay slot into a "compact" version. */
135 /* Insert the instruction before the last one. */
139 /* Information about an instruction, including its format, operands
143 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
144 const struct mips_opcode *insn_mo;
146 /* True if this is a mips16 instruction and if we want the extended
148 bfd_boolean use_extend;
150 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
151 unsigned short extend;
153 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
154 a copy of INSN_MO->match with the operands filled in. */
155 unsigned long insn_opcode;
157 /* The frag that contains the instruction. */
160 /* The offset into FRAG of the first instruction byte. */
163 /* The relocs associated with the instruction, if any. */
166 /* True if this entry cannot be moved from its current position. */
167 unsigned int fixed_p : 1;
169 /* True if this instruction occurred in a .set noreorder block. */
170 unsigned int noreorder_p : 1;
172 /* True for mips16 instructions that jump to an absolute address. */
173 unsigned int mips16_absolute_jump_p : 1;
175 /* True if this instruction is complete. */
176 unsigned int complete_p : 1;
179 /* The ABI to use. */
190 /* MIPS ABI we are using for this output file. */
191 static enum mips_abi_level mips_abi = NO_ABI;
193 /* Whether or not we have code that can call pic code. */
194 int mips_abicalls = FALSE;
196 /* Whether or not we have code which can be put into a shared
198 static bfd_boolean mips_in_shared = TRUE;
200 /* This is the set of options which may be modified by the .set
201 pseudo-op. We use a struct so that .set push and .set pop are more
204 struct mips_set_options
206 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
219 /* Whether we are assembling for the mips16 processor. 0 if we are
220 not, 1 if we are, and -1 if the value has not been initialized.
221 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
222 -nomips16 command line options, and the default CPU. */
224 /* Non-zero if we should not reorder instructions. Changed by `.set
225 reorder' and `.set noreorder'. */
227 /* Non-zero if we should not permit the register designated "assembler
228 temporary" to be used in instructions. The value is the register
229 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
230 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
232 /* Non-zero if we should warn when a macro instruction expands into
233 more than one machine instruction. Changed by `.set nomacro' and
235 int warn_about_macros;
236 /* Non-zero if we should not move instructions. Changed by `.set
237 move', `.set volatile', `.set nomove', and `.set novolatile'. */
239 /* Non-zero if we should not optimize branches by moving the target
240 of the branch into the delay slot. Actually, we don't perform
241 this optimization anyhow. Changed by `.set bopt' and `.set
244 /* Non-zero if we should not autoextend mips16 instructions.
245 Changed by `.set autoextend' and `.set noautoextend'. */
247 /* Restrict general purpose registers and floating point registers
248 to 32 bit. This is initially determined when -mgp32 or -mfp32
249 is passed but can changed if the assembler code uses .set mipsN. */
252 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
253 command line option, and the default CPU. */
255 /* True if ".set sym32" is in effect. */
257 /* True if floating-point operations are not allowed. Changed by .set
258 softfloat or .set hardfloat, by command line options -msoft-float or
259 -mhard-float. The default is false. */
260 bfd_boolean soft_float;
262 /* True if only single-precision floating-point operations are allowed.
263 Changed by .set singlefloat or .set doublefloat, command-line options
264 -msingle-float or -mdouble-float. The default is false. */
265 bfd_boolean single_float;
268 /* This is the struct we use to hold the current set of options. Note
269 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
270 -1 to indicate that they have not been initialized. */
272 /* True if -mgp32 was passed. */
273 static int file_mips_gp32 = -1;
275 /* True if -mfp32 was passed. */
276 static int file_mips_fp32 = -1;
278 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
279 static int file_mips_soft_float = 0;
281 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
282 static int file_mips_single_float = 0;
284 static struct mips_set_options mips_opts =
286 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
287 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
288 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
289 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
290 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
291 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if we want to create R_MIPS_JALR for jalr $25. */
313 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
315 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318 #define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
323 /* True if -mips3d was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325 static int file_ase_mips3d;
327 /* True if -mdmx was passed or implied by arguments passed on the
328 command line (e.g., by -march). */
329 static int file_ase_mdmx;
331 /* True if -msmartmips was passed or implied by arguments passed on the
332 command line (e.g., by -march). */
333 static int file_ase_smartmips;
335 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
336 || mips_opts.isa == ISA_MIPS32R2)
338 /* True if -mdsp was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_dsp;
342 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64R2)
345 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
347 /* True if -mdspr2 was passed or implied by arguments passed on the
348 command line (e.g., by -march). */
349 static int file_ase_dspr2;
351 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
352 || mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mmt was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_mt;
358 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2)
361 /* The argument of the -march= flag. The architecture we are assembling. */
362 static int file_mips_arch = CPU_UNKNOWN;
363 static const char *mips_arch_string;
365 /* The argument of the -mtune= flag. The architecture for which we
367 static int mips_tune = CPU_UNKNOWN;
368 static const char *mips_tune_string;
370 /* True when generating 32-bit code for a 64-bit processor. */
371 static int mips_32bitmode = 0;
373 /* True if the given ABI requires 32-bit registers. */
374 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
376 /* Likewise 64-bit registers. */
377 #define ABI_NEEDS_64BIT_REGS(ABI) \
379 || (ABI) == N64_ABI \
382 /* Return true if ISA supports 64 bit wide gp registers. */
383 #define ISA_HAS_64BIT_REGS(ISA) \
384 ((ISA) == ISA_MIPS3 \
385 || (ISA) == ISA_MIPS4 \
386 || (ISA) == ISA_MIPS5 \
387 || (ISA) == ISA_MIPS64 \
388 || (ISA) == ISA_MIPS64R2)
390 /* Return true if ISA supports 64 bit wide float registers. */
391 #define ISA_HAS_64BIT_FPRS(ISA) \
392 ((ISA) == ISA_MIPS3 \
393 || (ISA) == ISA_MIPS4 \
394 || (ISA) == ISA_MIPS5 \
395 || (ISA) == ISA_MIPS32R2 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2)
399 /* Return true if ISA supports 64-bit right rotate (dror et al.)
401 #define ISA_HAS_DROR(ISA) \
402 ((ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 32-bit right rotate (ror et al.)
406 #define ISA_HAS_ROR(ISA) \
407 ((ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64R2 \
409 || mips_opts.ase_smartmips)
411 /* Return true if ISA supports single-precision floats in odd registers. */
412 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
413 ((ISA) == ISA_MIPS32 \
414 || (ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS64 \
416 || (ISA) == ISA_MIPS64R2)
418 /* Return true if ISA supports move to/from high part of a 64-bit
419 floating-point register. */
420 #define ISA_HAS_MXHC1(ISA) \
421 ((ISA) == ISA_MIPS32R2 \
422 || (ISA) == ISA_MIPS64R2)
424 #define HAVE_32BIT_GPRS \
425 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
427 #define HAVE_32BIT_FPRS \
428 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
430 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
431 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
433 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
435 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
437 /* True if relocations are stored in-place. */
438 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
440 /* The ABI-derived address size. */
441 #define HAVE_64BIT_ADDRESSES \
442 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
443 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
445 /* The size of symbolic constants (i.e., expressions of the form
446 "SYMBOL" or "SYMBOL + OFFSET"). */
447 #define HAVE_32BIT_SYMBOLS \
448 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
449 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
451 /* Addresses are loaded in different ways, depending on the address size
452 in use. The n32 ABI Documentation also mandates the use of additions
453 with overflow checking, but existing implementations don't follow it. */
454 #define ADDRESS_ADD_INSN \
455 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
457 #define ADDRESS_ADDI_INSN \
458 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
460 #define ADDRESS_LOAD_INSN \
461 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
463 #define ADDRESS_STORE_INSN \
464 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
466 /* Return true if the given CPU supports the MIPS16 ASE. */
467 #define CPU_HAS_MIPS16(cpu) \
468 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
469 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
471 /* True if CPU has a dror instruction. */
472 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
474 /* True if CPU has a ror instruction. */
475 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
477 /* True if CPU has seq/sne and seqi/snei instructions. */
478 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
480 /* True if CPU does not implement the all the coprocessor insns. For these
481 CPUs only those COP insns are accepted that are explicitly marked to be
482 available on the CPU. ISA membership for COP insns is ignored. */
483 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
485 /* True if mflo and mfhi can be immediately followed by instructions
486 which write to the HI and LO registers.
488 According to MIPS specifications, MIPS ISAs I, II, and III need
489 (at least) two instructions between the reads of HI/LO and
490 instructions which write them, and later ISAs do not. Contradicting
491 the MIPS specifications, some MIPS IV processor user manuals (e.g.
492 the UM for the NEC Vr5000) document needing the instructions between
493 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
494 MIPS64 and later ISAs to have the interlocks, plus any specific
495 earlier-ISA CPUs for which CPU documentation declares that the
496 instructions are really interlocked. */
497 #define hilo_interlocks \
498 (mips_opts.isa == ISA_MIPS32 \
499 || mips_opts.isa == ISA_MIPS32R2 \
500 || mips_opts.isa == ISA_MIPS64 \
501 || mips_opts.isa == ISA_MIPS64R2 \
502 || mips_opts.arch == CPU_R4010 \
503 || mips_opts.arch == CPU_R10000 \
504 || mips_opts.arch == CPU_R12000 \
505 || mips_opts.arch == CPU_R14000 \
506 || mips_opts.arch == CPU_R16000 \
507 || mips_opts.arch == CPU_RM7000 \
508 || mips_opts.arch == CPU_VR5500 \
511 /* Whether the processor uses hardware interlocks to protect reads
512 from the GPRs after they are loaded from memory, and thus does not
513 require nops to be inserted. This applies to instructions marked
514 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
516 #define gpr_interlocks \
517 (mips_opts.isa != ISA_MIPS1 \
518 || mips_opts.arch == CPU_R3900)
520 /* Whether the processor uses hardware interlocks to avoid delays
521 required by coprocessor instructions, and thus does not require
522 nops to be inserted. This applies to instructions marked
523 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
524 between instructions marked INSN_WRITE_COND_CODE and ones marked
525 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
526 levels I, II, and III. */
527 /* Itbl support may require additional care here. */
528 #define cop_interlocks \
529 ((mips_opts.isa != ISA_MIPS1 \
530 && mips_opts.isa != ISA_MIPS2 \
531 && mips_opts.isa != ISA_MIPS3) \
532 || mips_opts.arch == CPU_R4300 \
535 /* Whether the processor uses hardware interlocks to protect reads
536 from coprocessor registers after they are loaded from memory, and
537 thus does not require nops to be inserted. This applies to
538 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
539 requires at MIPS ISA level I. */
540 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
542 /* Is this a mfhi or mflo instruction? */
543 #define MF_HILO_INSN(PINFO) \
544 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
546 /* Returns true for a (non floating-point) coprocessor instruction. Reading
547 or writing the condition code is only possible on the coprocessors and
548 these insns are not marked with INSN_COP. Thus for these insns use the
549 condition-code flags. */
550 #define COP_INSN(PINFO) \
551 (PINFO != INSN_MACRO \
552 && ((PINFO) & (FP_S | FP_D)) == 0 \
553 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
555 /* MIPS PIC level. */
557 enum mips_pic_level mips_pic;
559 /* 1 if we should generate 32 bit offsets from the $gp register in
560 SVR4_PIC mode. Currently has no meaning in other modes. */
561 static int mips_big_got = 0;
563 /* 1 if trap instructions should used for overflow rather than break
565 static int mips_trap = 0;
567 /* 1 if double width floating point constants should not be constructed
568 by assembling two single width halves into two single width floating
569 point registers which just happen to alias the double width destination
570 register. On some architectures this aliasing can be disabled by a bit
571 in the status register, and the setting of this bit cannot be determined
572 automatically at assemble time. */
573 static int mips_disable_float_construction;
575 /* Non-zero if any .set noreorder directives were used. */
577 static int mips_any_noreorder;
579 /* Non-zero if nops should be inserted when the register referenced in
580 an mfhi/mflo instruction is read in the next two instructions. */
581 static int mips_7000_hilo_fix;
583 /* The size of objects in the small data section. */
584 static unsigned int g_switch_value = 8;
585 /* Whether the -G option was used. */
586 static int g_switch_seen = 0;
591 /* If we can determine in advance that GP optimization won't be
592 possible, we can skip the relaxation stuff that tries to produce
593 GP-relative references. This makes delay slot optimization work
596 This function can only provide a guess, but it seems to work for
597 gcc output. It needs to guess right for gcc, otherwise gcc
598 will put what it thinks is a GP-relative instruction in a branch
601 I don't know if a fix is needed for the SVR4_PIC mode. I've only
602 fixed it for the non-PIC mode. KR 95/04/07 */
603 static int nopic_need_relax (symbolS *, int);
605 /* handle of the OPCODE hash table */
606 static struct hash_control *op_hash = NULL;
608 /* The opcode hash table we use for the mips16. */
609 static struct hash_control *mips16_op_hash = NULL;
611 /* This array holds the chars that always start a comment. If the
612 pre-processor is disabled, these aren't very useful */
613 const char comment_chars[] = "#";
615 /* This array holds the chars that only start a comment at the beginning of
616 a line. If the line seems to have the form '# 123 filename'
617 .line and .file directives will appear in the pre-processed output */
618 /* Note that input_file.c hand checks for '#' at the beginning of the
619 first line of the input file. This is because the compiler outputs
620 #NO_APP at the beginning of its output. */
621 /* Also note that C style comments are always supported. */
622 const char line_comment_chars[] = "#";
624 /* This array holds machine specific line separator characters. */
625 const char line_separator_chars[] = ";";
627 /* Chars that can be used to separate mant from exp in floating point nums */
628 const char EXP_CHARS[] = "eE";
630 /* Chars that mean this number is a floating point constant */
633 const char FLT_CHARS[] = "rRsSfFdDxXpP";
635 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
636 changed in read.c . Ideally it shouldn't have to know about it at all,
637 but nothing is ideal around here.
640 static char *insn_error;
642 static int auto_align = 1;
644 /* When outputting SVR4 PIC code, the assembler needs to know the
645 offset in the stack frame from which to restore the $gp register.
646 This is set by the .cprestore pseudo-op, and saved in this
648 static offsetT mips_cprestore_offset = -1;
650 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
651 more optimizations, it can use a register value instead of a memory-saved
652 offset and even an other register than $gp as global pointer. */
653 static offsetT mips_cpreturn_offset = -1;
654 static int mips_cpreturn_register = -1;
655 static int mips_gp_register = GP;
656 static int mips_gprel_offset = 0;
658 /* Whether mips_cprestore_offset has been set in the current function
659 (or whether it has already been warned about, if not). */
660 static int mips_cprestore_valid = 0;
662 /* This is the register which holds the stack frame, as set by the
663 .frame pseudo-op. This is needed to implement .cprestore. */
664 static int mips_frame_reg = SP;
666 /* Whether mips_frame_reg has been set in the current function
667 (or whether it has already been warned about, if not). */
668 static int mips_frame_reg_valid = 0;
670 /* To output NOP instructions correctly, we need to keep information
671 about the previous two instructions. */
673 /* Whether we are optimizing. The default value of 2 means to remove
674 unneeded NOPs and swap branch instructions when possible. A value
675 of 1 means to not swap branches. A value of 0 means to always
677 static int mips_optimize = 2;
679 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
680 equivalent to seeing no -g option at all. */
681 static int mips_debug = 0;
683 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
684 #define MAX_VR4130_NOPS 4
686 /* The maximum number of NOPs needed to fill delay slots. */
687 #define MAX_DELAY_NOPS 2
689 /* The maximum number of NOPs needed for any purpose. */
692 /* A list of previous instructions, with index 0 being the most recent.
693 We need to look back MAX_NOPS instructions when filling delay slots
694 or working around processor errata. We need to look back one
695 instruction further if we're thinking about using history[0] to
696 fill a branch delay slot. */
697 static struct mips_cl_insn history[1 + MAX_NOPS];
699 /* Nop instructions used by emit_nop. */
700 static struct mips_cl_insn nop_insn, mips16_nop_insn;
702 /* The appropriate nop for the current mode. */
703 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
705 /* If this is set, it points to a frag holding nop instructions which
706 were inserted before the start of a noreorder section. If those
707 nops turn out to be unnecessary, the size of the frag can be
709 static fragS *prev_nop_frag;
711 /* The number of nop instructions we created in prev_nop_frag. */
712 static int prev_nop_frag_holds;
714 /* The number of nop instructions that we know we need in
716 static int prev_nop_frag_required;
718 /* The number of instructions we've seen since prev_nop_frag. */
719 static int prev_nop_frag_since;
721 /* For ECOFF and ELF, relocations against symbols are done in two
722 parts, with a HI relocation and a LO relocation. Each relocation
723 has only 16 bits of space to store an addend. This means that in
724 order for the linker to handle carries correctly, it must be able
725 to locate both the HI and the LO relocation. This means that the
726 relocations must appear in order in the relocation table.
728 In order to implement this, we keep track of each unmatched HI
729 relocation. We then sort them so that they immediately precede the
730 corresponding LO relocation. */
735 struct mips_hi_fixup *next;
738 /* The section this fixup is in. */
742 /* The list of unmatched HI relocs. */
744 static struct mips_hi_fixup *mips_hi_fixup_list;
746 /* The frag containing the last explicit relocation operator.
747 Null if explicit relocations have not been used. */
749 static fragS *prev_reloc_op_frag;
751 /* Map normal MIPS register numbers to mips16 register numbers. */
753 #define X ILLEGAL_REG
754 static const int mips32_to_16_reg_map[] =
756 X, X, 2, 3, 4, 5, 6, 7,
757 X, X, X, X, X, X, X, X,
758 0, 1, X, X, X, X, X, X,
759 X, X, X, X, X, X, X, X
763 /* Map mips16 register numbers to normal MIPS register numbers. */
765 static const unsigned int mips16_to_32_reg_map[] =
767 16, 17, 2, 3, 4, 5, 6, 7
770 /* Classifies the kind of instructions we're interested in when
771 implementing -mfix-vr4120. */
772 enum fix_vr4120_class
780 NUM_FIX_VR4120_CLASSES
783 /* ...likewise -mfix-loongson2f-jump. */
784 static bfd_boolean mips_fix_loongson2f_jump;
786 /* ...likewise -mfix-loongson2f-nop. */
787 static bfd_boolean mips_fix_loongson2f_nop;
789 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
790 static bfd_boolean mips_fix_loongson2f;
792 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
793 there must be at least one other instruction between an instruction
794 of type X and an instruction of type Y. */
795 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
797 /* True if -mfix-vr4120 is in force. */
798 static int mips_fix_vr4120;
800 /* ...likewise -mfix-vr4130. */
801 static int mips_fix_vr4130;
803 /* ...likewise -mfix-24k. */
804 static int mips_fix_24k;
806 /* ...likewise -mfix-cn63xxp1 */
807 static bfd_boolean mips_fix_cn63xxp1;
809 /* We don't relax branches by default, since this causes us to expand
810 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
811 fail to compute the offset before expanding the macro to the most
812 efficient expansion. */
814 static int mips_relax_branch;
816 /* The expansion of many macros depends on the type of symbol that
817 they refer to. For example, when generating position-dependent code,
818 a macro that refers to a symbol may have two different expansions,
819 one which uses GP-relative addresses and one which uses absolute
820 addresses. When generating SVR4-style PIC, a macro may have
821 different expansions for local and global symbols.
823 We handle these situations by generating both sequences and putting
824 them in variant frags. In position-dependent code, the first sequence
825 will be the GP-relative one and the second sequence will be the
826 absolute one. In SVR4 PIC, the first sequence will be for global
827 symbols and the second will be for local symbols.
829 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
830 SECOND are the lengths of the two sequences in bytes. These fields
831 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
832 the subtype has the following flags:
835 Set if it has been decided that we should use the second
836 sequence instead of the first.
839 Set in the first variant frag if the macro's second implementation
840 is longer than its first. This refers to the macro as a whole,
841 not an individual relaxation.
844 Set in the first variant frag if the macro appeared in a .set nomacro
845 block and if one alternative requires a warning but the other does not.
848 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
851 The frag's "opcode" points to the first fixup for relaxable code.
853 Relaxable macros are generated using a sequence such as:
855 relax_start (SYMBOL);
856 ... generate first expansion ...
858 ... generate second expansion ...
861 The code and fixups for the unwanted alternative are discarded
862 by md_convert_frag. */
863 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
865 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
866 #define RELAX_SECOND(X) ((X) & 0xff)
867 #define RELAX_USE_SECOND 0x10000
868 #define RELAX_SECOND_LONGER 0x20000
869 #define RELAX_NOMACRO 0x40000
870 #define RELAX_DELAY_SLOT 0x80000
872 /* Branch without likely bit. If label is out of range, we turn:
874 beq reg1, reg2, label
884 with the following opcode replacements:
891 bltzal <-> bgezal (with jal label instead of j label)
893 Even though keeping the delay slot instruction in the delay slot of
894 the branch would be more efficient, it would be very tricky to do
895 correctly, because we'd have to introduce a variable frag *after*
896 the delay slot instruction, and expand that instead. Let's do it
897 the easy way for now, even if the branch-not-taken case now costs
898 one additional instruction. Out-of-range branches are not supposed
899 to be common, anyway.
901 Branch likely. If label is out of range, we turn:
903 beql reg1, reg2, label
904 delay slot (annulled if branch not taken)
913 delay slot (executed only if branch taken)
916 It would be possible to generate a shorter sequence by losing the
917 likely bit, generating something like:
922 delay slot (executed only if branch taken)
934 bltzall -> bgezal (with jal label instead of j label)
935 bgezall -> bltzal (ditto)
938 but it's not clear that it would actually improve performance. */
939 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
943 | ((toofar) ? 0x20 : 0) \
944 | ((link) ? 0x40 : 0) \
945 | ((likely) ? 0x80 : 0) \
946 | ((uncond) ? 0x100 : 0)))
947 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
948 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
949 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
950 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
951 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
952 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
954 /* For mips16 code, we use an entirely different form of relaxation.
955 mips16 supports two versions of most instructions which take
956 immediate values: a small one which takes some small value, and a
957 larger one which takes a 16 bit value. Since branches also follow
958 this pattern, relaxing these values is required.
960 We can assemble both mips16 and normal MIPS code in a single
961 object. Therefore, we need to support this type of relaxation at
962 the same time that we support the relaxation described above. We
963 use the high bit of the subtype field to distinguish these cases.
965 The information we store for this type of relaxation is the
966 argument code found in the opcode file for this relocation, whether
967 the user explicitly requested a small or extended form, and whether
968 the relocation is in a jump or jal delay slot. That tells us the
969 size of the value, and how it should be stored. We also store
970 whether the fragment is considered to be extended or not. We also
971 store whether this is known to be a branch to a different section,
972 whether we have tried to relax this frag yet, and whether we have
973 ever extended a PC relative fragment because of a shift count. */
974 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
977 | ((small) ? 0x100 : 0) \
978 | ((ext) ? 0x200 : 0) \
979 | ((dslot) ? 0x400 : 0) \
980 | ((jal_dslot) ? 0x800 : 0))
981 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
982 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
983 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
984 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
985 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
986 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
987 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
988 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
989 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
990 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
991 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
992 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
994 /* Is the given value a sign-extended 32-bit value? */
995 #define IS_SEXT_32BIT_NUM(x) \
996 (((x) &~ (offsetT) 0x7fffffff) == 0 \
997 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
999 /* Is the given value a sign-extended 16-bit value? */
1000 #define IS_SEXT_16BIT_NUM(x) \
1001 (((x) &~ (offsetT) 0x7fff) == 0 \
1002 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1004 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1005 #define IS_ZEXT_32BIT_NUM(x) \
1006 (((x) &~ (offsetT) 0xffffffff) == 0 \
1007 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1009 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1010 VALUE << SHIFT. VALUE is evaluated exactly once. */
1011 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1012 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1013 | (((VALUE) & (MASK)) << (SHIFT)))
1015 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1017 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1018 (((STRUCT) >> (SHIFT)) & (MASK))
1020 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1021 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1023 include/opcode/mips.h specifies operand fields using the macros
1024 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1025 with "MIPS16OP" instead of "OP". */
1026 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1027 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1028 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1029 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1030 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1032 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1033 #define EXTRACT_OPERAND(FIELD, INSN) \
1034 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1035 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1036 EXTRACT_BITS ((INSN).insn_opcode, \
1037 MIPS16OP_MASK_##FIELD, \
1038 MIPS16OP_SH_##FIELD)
1040 /* Global variables used when generating relaxable macros. See the
1041 comment above RELAX_ENCODE for more details about how relaxation
1044 /* 0 if we're not emitting a relaxable macro.
1045 1 if we're emitting the first of the two relaxation alternatives.
1046 2 if we're emitting the second alternative. */
1049 /* The first relaxable fixup in the current frag. (In other words,
1050 the first fixup that refers to relaxable code.) */
1053 /* sizes[0] says how many bytes of the first alternative are stored in
1054 the current frag. Likewise sizes[1] for the second alternative. */
1055 unsigned int sizes[2];
1057 /* The symbol on which the choice of sequence depends. */
1061 /* Global variables used to decide whether a macro needs a warning. */
1063 /* True if the macro is in a branch delay slot. */
1064 bfd_boolean delay_slot_p;
1066 /* For relaxable macros, sizes[0] is the length of the first alternative
1067 in bytes and sizes[1] is the length of the second alternative.
1068 For non-relaxable macros, both elements give the length of the
1070 unsigned int sizes[2];
1072 /* The first variant frag for this macro. */
1074 } mips_macro_warning;
1076 /* Prototypes for static functions. */
1078 #define internalError() \
1079 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1081 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1083 static void append_insn
1084 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1085 static void mips_no_prev_insn (void);
1086 static void macro_build (expressionS *, const char *, const char *, ...);
1087 static void mips16_macro_build
1088 (expressionS *, const char *, const char *, va_list *);
1089 static void load_register (int, expressionS *, int);
1090 static void macro_start (void);
1091 static void macro_end (void);
1092 static void macro (struct mips_cl_insn * ip);
1093 static void mips16_macro (struct mips_cl_insn * ip);
1094 static void mips_ip (char *str, struct mips_cl_insn * ip);
1095 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1096 static void mips16_immed
1097 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1098 unsigned long *, bfd_boolean *, unsigned short *);
1099 static size_t my_getSmallExpression
1100 (expressionS *, bfd_reloc_code_real_type *, char *);
1101 static void my_getExpression (expressionS *, char *);
1102 static void s_align (int);
1103 static void s_change_sec (int);
1104 static void s_change_section (int);
1105 static void s_cons (int);
1106 static void s_float_cons (int);
1107 static void s_mips_globl (int);
1108 static void s_option (int);
1109 static void s_mipsset (int);
1110 static void s_abicalls (int);
1111 static void s_cpload (int);
1112 static void s_cpsetup (int);
1113 static void s_cplocal (int);
1114 static void s_cprestore (int);
1115 static void s_cpreturn (int);
1116 static void s_dtprelword (int);
1117 static void s_dtpreldword (int);
1118 static void s_gpvalue (int);
1119 static void s_gpword (int);
1120 static void s_gpdword (int);
1121 static void s_cpadd (int);
1122 static void s_insn (int);
1123 static void md_obj_begin (void);
1124 static void md_obj_end (void);
1125 static void s_mips_ent (int);
1126 static void s_mips_end (int);
1127 static void s_mips_frame (int);
1128 static void s_mips_mask (int reg_type);
1129 static void s_mips_stab (int);
1130 static void s_mips_weakext (int);
1131 static void s_mips_file (int);
1132 static void s_mips_loc (int);
1133 static bfd_boolean pic_need_relax (symbolS *, asection *);
1134 static int relaxed_branch_length (fragS *, asection *, int);
1135 static int validate_mips_insn (const struct mips_opcode *);
1137 /* Table and functions used to map between CPU/ISA names, and
1138 ISA levels, and CPU numbers. */
1140 struct mips_cpu_info
1142 const char *name; /* CPU or ISA name. */
1143 int flags; /* ASEs available, or ISA flag. */
1144 int isa; /* ISA level. */
1145 int cpu; /* CPU number (default CPU if ISA). */
1148 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1149 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1150 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1151 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1152 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1153 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1154 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1156 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1157 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1158 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1162 The following pseudo-ops from the Kane and Heinrich MIPS book
1163 should be defined here, but are currently unsupported: .alias,
1164 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1166 The following pseudo-ops from the Kane and Heinrich MIPS book are
1167 specific to the type of debugging information being generated, and
1168 should be defined by the object format: .aent, .begin, .bend,
1169 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1172 The following pseudo-ops from the Kane and Heinrich MIPS book are
1173 not MIPS CPU specific, but are also not specific to the object file
1174 format. This file is probably the best place to define them, but
1175 they are not currently supported: .asm0, .endr, .lab, .struct. */
1177 static const pseudo_typeS mips_pseudo_table[] =
1179 /* MIPS specific pseudo-ops. */
1180 {"option", s_option, 0},
1181 {"set", s_mipsset, 0},
1182 {"rdata", s_change_sec, 'r'},
1183 {"sdata", s_change_sec, 's'},
1184 {"livereg", s_ignore, 0},
1185 {"abicalls", s_abicalls, 0},
1186 {"cpload", s_cpload, 0},
1187 {"cpsetup", s_cpsetup, 0},
1188 {"cplocal", s_cplocal, 0},
1189 {"cprestore", s_cprestore, 0},
1190 {"cpreturn", s_cpreturn, 0},
1191 {"dtprelword", s_dtprelword, 0},
1192 {"dtpreldword", s_dtpreldword, 0},
1193 {"gpvalue", s_gpvalue, 0},
1194 {"gpword", s_gpword, 0},
1195 {"gpdword", s_gpdword, 0},
1196 {"cpadd", s_cpadd, 0},
1197 {"insn", s_insn, 0},
1199 /* Relatively generic pseudo-ops that happen to be used on MIPS
1201 {"asciiz", stringer, 8 + 1},
1202 {"bss", s_change_sec, 'b'},
1204 {"half", s_cons, 1},
1205 {"dword", s_cons, 3},
1206 {"weakext", s_mips_weakext, 0},
1207 {"origin", s_org, 0},
1208 {"repeat", s_rept, 0},
1210 /* For MIPS this is non-standard, but we define it for consistency. */
1211 {"sbss", s_change_sec, 'B'},
1213 /* These pseudo-ops are defined in read.c, but must be overridden
1214 here for one reason or another. */
1215 {"align", s_align, 0},
1216 {"byte", s_cons, 0},
1217 {"data", s_change_sec, 'd'},
1218 {"double", s_float_cons, 'd'},
1219 {"float", s_float_cons, 'f'},
1220 {"globl", s_mips_globl, 0},
1221 {"global", s_mips_globl, 0},
1222 {"hword", s_cons, 1},
1224 {"long", s_cons, 2},
1225 {"octa", s_cons, 4},
1226 {"quad", s_cons, 3},
1227 {"section", s_change_section, 0},
1228 {"short", s_cons, 1},
1229 {"single", s_float_cons, 'f'},
1230 {"stabn", s_mips_stab, 'n'},
1231 {"text", s_change_sec, 't'},
1232 {"word", s_cons, 2},
1234 { "extern", ecoff_directive_extern, 0},
1239 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1241 /* These pseudo-ops should be defined by the object file format.
1242 However, a.out doesn't support them, so we have versions here. */
1243 {"aent", s_mips_ent, 1},
1244 {"bgnb", s_ignore, 0},
1245 {"end", s_mips_end, 0},
1246 {"endb", s_ignore, 0},
1247 {"ent", s_mips_ent, 0},
1248 {"file", s_mips_file, 0},
1249 {"fmask", s_mips_mask, 'F'},
1250 {"frame", s_mips_frame, 0},
1251 {"loc", s_mips_loc, 0},
1252 {"mask", s_mips_mask, 'R'},
1253 {"verstamp", s_ignore, 0},
1257 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1258 purpose of the `.dc.a' internal pseudo-op. */
1261 mips_address_bytes (void)
1263 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1266 extern void pop_insert (const pseudo_typeS *);
1269 mips_pop_insert (void)
1271 pop_insert (mips_pseudo_table);
1272 if (! ECOFF_DEBUGGING)
1273 pop_insert (mips_nonecoff_pseudo_table);
1276 /* Symbols labelling the current insn. */
1278 struct insn_label_list
1280 struct insn_label_list *next;
1284 static struct insn_label_list *free_insn_labels;
1285 #define label_list tc_segment_info_data.labels
1287 static void mips_clear_insn_labels (void);
1290 mips_clear_insn_labels (void)
1292 register struct insn_label_list **pl;
1293 segment_info_type *si;
1297 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1300 si = seg_info (now_seg);
1301 *pl = si->label_list;
1302 si->label_list = NULL;
1307 static char *expr_end;
1309 /* Expressions which appear in instructions. These are set by
1312 static expressionS imm_expr;
1313 static expressionS imm2_expr;
1314 static expressionS offset_expr;
1316 /* Relocs associated with imm_expr and offset_expr. */
1318 static bfd_reloc_code_real_type imm_reloc[3]
1319 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1320 static bfd_reloc_code_real_type offset_reloc[3]
1321 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1323 /* These are set by mips16_ip if an explicit extension is used. */
1325 static bfd_boolean mips16_small, mips16_ext;
1328 /* The pdr segment for per procedure frame/regmask info. Not used for
1331 static segT pdr_seg;
1334 /* The default target format to use. */
1336 #if defined (TE_FreeBSD)
1337 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1338 #elif defined (TE_TMIPS)
1339 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1341 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1345 mips_target_format (void)
1347 switch (OUTPUT_FLAVOR)
1349 case bfd_target_ecoff_flavour:
1350 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1351 case bfd_target_coff_flavour:
1353 case bfd_target_elf_flavour:
1355 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1356 return (target_big_endian
1357 ? "elf32-bigmips-vxworks"
1358 : "elf32-littlemips-vxworks");
1360 return (target_big_endian
1361 ? (HAVE_64BIT_OBJECTS
1362 ? ELF_TARGET ("elf64-", "big")
1364 ? ELF_TARGET ("elf32-n", "big")
1365 : ELF_TARGET ("elf32-", "big")))
1366 : (HAVE_64BIT_OBJECTS
1367 ? ELF_TARGET ("elf64-", "little")
1369 ? ELF_TARGET ("elf32-n", "little")
1370 : ELF_TARGET ("elf32-", "little"))));
1377 /* Return the length of instruction INSN. */
1379 static inline unsigned int
1380 insn_length (const struct mips_cl_insn *insn)
1382 if (!mips_opts.mips16)
1384 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1387 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1390 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1395 insn->use_extend = FALSE;
1397 insn->insn_opcode = mo->match;
1400 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1401 insn->fixp[i] = NULL;
1402 insn->fixed_p = (mips_opts.noreorder > 0);
1403 insn->noreorder_p = (mips_opts.noreorder > 0);
1404 insn->mips16_absolute_jump_p = 0;
1405 insn->complete_p = 0;
1408 /* Record the current MIPS16 mode in now_seg. */
1411 mips_record_mips16_mode (void)
1413 segment_info_type *si;
1415 si = seg_info (now_seg);
1416 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1417 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1420 /* Install INSN at the location specified by its "frag" and "where" fields. */
1423 install_insn (const struct mips_cl_insn *insn)
1425 char *f = insn->frag->fr_literal + insn->where;
1426 if (!mips_opts.mips16)
1427 md_number_to_chars (f, insn->insn_opcode, 4);
1428 else if (insn->mips16_absolute_jump_p)
1430 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1431 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1435 if (insn->use_extend)
1437 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1440 md_number_to_chars (f, insn->insn_opcode, 2);
1442 mips_record_mips16_mode ();
1445 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1446 and install the opcode in the new location. */
1449 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1454 insn->where = where;
1455 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1456 if (insn->fixp[i] != NULL)
1458 insn->fixp[i]->fx_frag = frag;
1459 insn->fixp[i]->fx_where = where;
1461 install_insn (insn);
1464 /* Add INSN to the end of the output. */
1467 add_fixed_insn (struct mips_cl_insn *insn)
1469 char *f = frag_more (insn_length (insn));
1470 move_insn (insn, frag_now, f - frag_now->fr_literal);
1473 /* Start a variant frag and move INSN to the start of the variant part,
1474 marking it as fixed. The other arguments are as for frag_var. */
1477 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1478 relax_substateT subtype, symbolS *symbol, offsetT offset)
1480 frag_grow (max_chars);
1481 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1483 frag_var (rs_machine_dependent, max_chars, var,
1484 subtype, symbol, offset, NULL);
1487 /* Insert N copies of INSN into the history buffer, starting at
1488 position FIRST. Neither FIRST nor N need to be clipped. */
1491 insert_into_history (unsigned int first, unsigned int n,
1492 const struct mips_cl_insn *insn)
1494 if (mips_relax.sequence != 2)
1498 for (i = ARRAY_SIZE (history); i-- > first;)
1500 history[i] = history[i - n];
1506 /* Emit a nop instruction, recording it in the history buffer. */
1511 add_fixed_insn (NOP_INSN);
1512 insert_into_history (0, 1, NOP_INSN);
1515 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1516 the idea is to make it obvious at a glance that each errata is
1520 init_vr4120_conflicts (void)
1522 #define CONFLICT(FIRST, SECOND) \
1523 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1525 /* Errata 21 - [D]DIV[U] after [D]MACC */
1526 CONFLICT (MACC, DIV);
1527 CONFLICT (DMACC, DIV);
1529 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1530 CONFLICT (DMULT, DMULT);
1531 CONFLICT (DMULT, DMACC);
1532 CONFLICT (DMACC, DMULT);
1533 CONFLICT (DMACC, DMACC);
1535 /* Errata 24 - MT{LO,HI} after [D]MACC */
1536 CONFLICT (MACC, MTHILO);
1537 CONFLICT (DMACC, MTHILO);
1539 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1540 instruction is executed immediately after a MACC or DMACC
1541 instruction, the result of [either instruction] is incorrect." */
1542 CONFLICT (MACC, MULT);
1543 CONFLICT (MACC, DMULT);
1544 CONFLICT (DMACC, MULT);
1545 CONFLICT (DMACC, DMULT);
1547 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1548 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1549 DDIV or DDIVU instruction, the result of the MACC or
1550 DMACC instruction is incorrect.". */
1551 CONFLICT (DMULT, MACC);
1552 CONFLICT (DMULT, DMACC);
1553 CONFLICT (DIV, MACC);
1554 CONFLICT (DIV, DMACC);
1564 #define RTYPE_MASK 0x1ff00
1565 #define RTYPE_NUM 0x00100
1566 #define RTYPE_FPU 0x00200
1567 #define RTYPE_FCC 0x00400
1568 #define RTYPE_VEC 0x00800
1569 #define RTYPE_GP 0x01000
1570 #define RTYPE_CP0 0x02000
1571 #define RTYPE_PC 0x04000
1572 #define RTYPE_ACC 0x08000
1573 #define RTYPE_CCC 0x10000
1574 #define RNUM_MASK 0x000ff
1575 #define RWARN 0x80000
1577 #define GENERIC_REGISTER_NUMBERS \
1578 {"$0", RTYPE_NUM | 0}, \
1579 {"$1", RTYPE_NUM | 1}, \
1580 {"$2", RTYPE_NUM | 2}, \
1581 {"$3", RTYPE_NUM | 3}, \
1582 {"$4", RTYPE_NUM | 4}, \
1583 {"$5", RTYPE_NUM | 5}, \
1584 {"$6", RTYPE_NUM | 6}, \
1585 {"$7", RTYPE_NUM | 7}, \
1586 {"$8", RTYPE_NUM | 8}, \
1587 {"$9", RTYPE_NUM | 9}, \
1588 {"$10", RTYPE_NUM | 10}, \
1589 {"$11", RTYPE_NUM | 11}, \
1590 {"$12", RTYPE_NUM | 12}, \
1591 {"$13", RTYPE_NUM | 13}, \
1592 {"$14", RTYPE_NUM | 14}, \
1593 {"$15", RTYPE_NUM | 15}, \
1594 {"$16", RTYPE_NUM | 16}, \
1595 {"$17", RTYPE_NUM | 17}, \
1596 {"$18", RTYPE_NUM | 18}, \
1597 {"$19", RTYPE_NUM | 19}, \
1598 {"$20", RTYPE_NUM | 20}, \
1599 {"$21", RTYPE_NUM | 21}, \
1600 {"$22", RTYPE_NUM | 22}, \
1601 {"$23", RTYPE_NUM | 23}, \
1602 {"$24", RTYPE_NUM | 24}, \
1603 {"$25", RTYPE_NUM | 25}, \
1604 {"$26", RTYPE_NUM | 26}, \
1605 {"$27", RTYPE_NUM | 27}, \
1606 {"$28", RTYPE_NUM | 28}, \
1607 {"$29", RTYPE_NUM | 29}, \
1608 {"$30", RTYPE_NUM | 30}, \
1609 {"$31", RTYPE_NUM | 31}
1611 #define FPU_REGISTER_NAMES \
1612 {"$f0", RTYPE_FPU | 0}, \
1613 {"$f1", RTYPE_FPU | 1}, \
1614 {"$f2", RTYPE_FPU | 2}, \
1615 {"$f3", RTYPE_FPU | 3}, \
1616 {"$f4", RTYPE_FPU | 4}, \
1617 {"$f5", RTYPE_FPU | 5}, \
1618 {"$f6", RTYPE_FPU | 6}, \
1619 {"$f7", RTYPE_FPU | 7}, \
1620 {"$f8", RTYPE_FPU | 8}, \
1621 {"$f9", RTYPE_FPU | 9}, \
1622 {"$f10", RTYPE_FPU | 10}, \
1623 {"$f11", RTYPE_FPU | 11}, \
1624 {"$f12", RTYPE_FPU | 12}, \
1625 {"$f13", RTYPE_FPU | 13}, \
1626 {"$f14", RTYPE_FPU | 14}, \
1627 {"$f15", RTYPE_FPU | 15}, \
1628 {"$f16", RTYPE_FPU | 16}, \
1629 {"$f17", RTYPE_FPU | 17}, \
1630 {"$f18", RTYPE_FPU | 18}, \
1631 {"$f19", RTYPE_FPU | 19}, \
1632 {"$f20", RTYPE_FPU | 20}, \
1633 {"$f21", RTYPE_FPU | 21}, \
1634 {"$f22", RTYPE_FPU | 22}, \
1635 {"$f23", RTYPE_FPU | 23}, \
1636 {"$f24", RTYPE_FPU | 24}, \
1637 {"$f25", RTYPE_FPU | 25}, \
1638 {"$f26", RTYPE_FPU | 26}, \
1639 {"$f27", RTYPE_FPU | 27}, \
1640 {"$f28", RTYPE_FPU | 28}, \
1641 {"$f29", RTYPE_FPU | 29}, \
1642 {"$f30", RTYPE_FPU | 30}, \
1643 {"$f31", RTYPE_FPU | 31}
1645 #define FPU_CONDITION_CODE_NAMES \
1646 {"$fcc0", RTYPE_FCC | 0}, \
1647 {"$fcc1", RTYPE_FCC | 1}, \
1648 {"$fcc2", RTYPE_FCC | 2}, \
1649 {"$fcc3", RTYPE_FCC | 3}, \
1650 {"$fcc4", RTYPE_FCC | 4}, \
1651 {"$fcc5", RTYPE_FCC | 5}, \
1652 {"$fcc6", RTYPE_FCC | 6}, \
1653 {"$fcc7", RTYPE_FCC | 7}
1655 #define COPROC_CONDITION_CODE_NAMES \
1656 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1657 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1658 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1659 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1660 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1661 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1662 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1663 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1665 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1666 {"$a4", RTYPE_GP | 8}, \
1667 {"$a5", RTYPE_GP | 9}, \
1668 {"$a6", RTYPE_GP | 10}, \
1669 {"$a7", RTYPE_GP | 11}, \
1670 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1671 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1672 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1673 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1674 {"$t0", RTYPE_GP | 12}, \
1675 {"$t1", RTYPE_GP | 13}, \
1676 {"$t2", RTYPE_GP | 14}, \
1677 {"$t3", RTYPE_GP | 15}
1679 #define O32_SYMBOLIC_REGISTER_NAMES \
1680 {"$t0", RTYPE_GP | 8}, \
1681 {"$t1", RTYPE_GP | 9}, \
1682 {"$t2", RTYPE_GP | 10}, \
1683 {"$t3", RTYPE_GP | 11}, \
1684 {"$t4", RTYPE_GP | 12}, \
1685 {"$t5", RTYPE_GP | 13}, \
1686 {"$t6", RTYPE_GP | 14}, \
1687 {"$t7", RTYPE_GP | 15}, \
1688 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1689 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1690 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1691 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1693 /* Remaining symbolic register names */
1694 #define SYMBOLIC_REGISTER_NAMES \
1695 {"$zero", RTYPE_GP | 0}, \
1696 {"$at", RTYPE_GP | 1}, \
1697 {"$AT", RTYPE_GP | 1}, \
1698 {"$v0", RTYPE_GP | 2}, \
1699 {"$v1", RTYPE_GP | 3}, \
1700 {"$a0", RTYPE_GP | 4}, \
1701 {"$a1", RTYPE_GP | 5}, \
1702 {"$a2", RTYPE_GP | 6}, \
1703 {"$a3", RTYPE_GP | 7}, \
1704 {"$s0", RTYPE_GP | 16}, \
1705 {"$s1", RTYPE_GP | 17}, \
1706 {"$s2", RTYPE_GP | 18}, \
1707 {"$s3", RTYPE_GP | 19}, \
1708 {"$s4", RTYPE_GP | 20}, \
1709 {"$s5", RTYPE_GP | 21}, \
1710 {"$s6", RTYPE_GP | 22}, \
1711 {"$s7", RTYPE_GP | 23}, \
1712 {"$t8", RTYPE_GP | 24}, \
1713 {"$t9", RTYPE_GP | 25}, \
1714 {"$k0", RTYPE_GP | 26}, \
1715 {"$kt0", RTYPE_GP | 26}, \
1716 {"$k1", RTYPE_GP | 27}, \
1717 {"$kt1", RTYPE_GP | 27}, \
1718 {"$gp", RTYPE_GP | 28}, \
1719 {"$sp", RTYPE_GP | 29}, \
1720 {"$s8", RTYPE_GP | 30}, \
1721 {"$fp", RTYPE_GP | 30}, \
1722 {"$ra", RTYPE_GP | 31}
1724 #define MIPS16_SPECIAL_REGISTER_NAMES \
1725 {"$pc", RTYPE_PC | 0}
1727 #define MDMX_VECTOR_REGISTER_NAMES \
1728 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1729 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1730 {"$v2", RTYPE_VEC | 2}, \
1731 {"$v3", RTYPE_VEC | 3}, \
1732 {"$v4", RTYPE_VEC | 4}, \
1733 {"$v5", RTYPE_VEC | 5}, \
1734 {"$v6", RTYPE_VEC | 6}, \
1735 {"$v7", RTYPE_VEC | 7}, \
1736 {"$v8", RTYPE_VEC | 8}, \
1737 {"$v9", RTYPE_VEC | 9}, \
1738 {"$v10", RTYPE_VEC | 10}, \
1739 {"$v11", RTYPE_VEC | 11}, \
1740 {"$v12", RTYPE_VEC | 12}, \
1741 {"$v13", RTYPE_VEC | 13}, \
1742 {"$v14", RTYPE_VEC | 14}, \
1743 {"$v15", RTYPE_VEC | 15}, \
1744 {"$v16", RTYPE_VEC | 16}, \
1745 {"$v17", RTYPE_VEC | 17}, \
1746 {"$v18", RTYPE_VEC | 18}, \
1747 {"$v19", RTYPE_VEC | 19}, \
1748 {"$v20", RTYPE_VEC | 20}, \
1749 {"$v21", RTYPE_VEC | 21}, \
1750 {"$v22", RTYPE_VEC | 22}, \
1751 {"$v23", RTYPE_VEC | 23}, \
1752 {"$v24", RTYPE_VEC | 24}, \
1753 {"$v25", RTYPE_VEC | 25}, \
1754 {"$v26", RTYPE_VEC | 26}, \
1755 {"$v27", RTYPE_VEC | 27}, \
1756 {"$v28", RTYPE_VEC | 28}, \
1757 {"$v29", RTYPE_VEC | 29}, \
1758 {"$v30", RTYPE_VEC | 30}, \
1759 {"$v31", RTYPE_VEC | 31}
1761 #define MIPS_DSP_ACCUMULATOR_NAMES \
1762 {"$ac0", RTYPE_ACC | 0}, \
1763 {"$ac1", RTYPE_ACC | 1}, \
1764 {"$ac2", RTYPE_ACC | 2}, \
1765 {"$ac3", RTYPE_ACC | 3}
1767 static const struct regname reg_names[] = {
1768 GENERIC_REGISTER_NUMBERS,
1770 FPU_CONDITION_CODE_NAMES,
1771 COPROC_CONDITION_CODE_NAMES,
1773 /* The $txx registers depends on the abi,
1774 these will be added later into the symbol table from
1775 one of the tables below once mips_abi is set after
1776 parsing of arguments from the command line. */
1777 SYMBOLIC_REGISTER_NAMES,
1779 MIPS16_SPECIAL_REGISTER_NAMES,
1780 MDMX_VECTOR_REGISTER_NAMES,
1781 MIPS_DSP_ACCUMULATOR_NAMES,
1785 static const struct regname reg_names_o32[] = {
1786 O32_SYMBOLIC_REGISTER_NAMES,
1790 static const struct regname reg_names_n32n64[] = {
1791 N32N64_SYMBOLIC_REGISTER_NAMES,
1796 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1803 /* Find end of name. */
1805 if (is_name_beginner (*e))
1807 while (is_part_of_name (*e))
1810 /* Terminate name. */
1814 /* Look for a register symbol. */
1815 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1817 int r = S_GET_VALUE (symbolP);
1819 reg = r & RNUM_MASK;
1820 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1821 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1822 reg = (r & RNUM_MASK) - 2;
1824 /* Else see if this is a register defined in an itbl entry. */
1825 else if ((types & RTYPE_GP) && itbl_have_entries)
1832 if (itbl_get_reg_val (n, &r))
1833 reg = r & RNUM_MASK;
1836 /* Advance to next token if a register was recognised. */
1839 else if (types & RWARN)
1840 as_warn (_("Unrecognized register name `%s'"), *s);
1848 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1849 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1852 is_opcode_valid (const struct mips_opcode *mo)
1854 int isa = mips_opts.isa;
1857 if (mips_opts.ase_mdmx)
1859 if (mips_opts.ase_dsp)
1861 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1863 if (mips_opts.ase_dspr2)
1865 if (mips_opts.ase_mt)
1867 if (mips_opts.ase_mips3d)
1869 if (mips_opts.ase_smartmips)
1870 isa |= INSN_SMARTMIPS;
1872 /* Don't accept instructions based on the ISA if the CPU does not implement
1873 all the coprocessor insns. */
1874 if (NO_ISA_COP (mips_opts.arch)
1875 && COP_INSN (mo->pinfo))
1878 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1881 /* Check whether the instruction or macro requires single-precision or
1882 double-precision floating-point support. Note that this information is
1883 stored differently in the opcode table for insns and macros. */
1884 if (mo->pinfo == INSN_MACRO)
1886 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1887 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1891 fp_s = mo->pinfo & FP_S;
1892 fp_d = mo->pinfo & FP_D;
1895 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1898 if (fp_s && mips_opts.soft_float)
1904 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1905 selected ISA and architecture. */
1908 is_opcode_valid_16 (const struct mips_opcode *mo)
1910 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1913 /* This function is called once, at assembler startup time. It should set up
1914 all the tables, etc. that the MD part of the assembler will need. */
1919 const char *retval = NULL;
1923 if (mips_pic != NO_PIC)
1925 if (g_switch_seen && g_switch_value != 0)
1926 as_bad (_("-G may not be used in position-independent code"));
1930 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1931 as_warn (_("Could not set architecture and machine"));
1933 op_hash = hash_new ();
1935 for (i = 0; i < NUMOPCODES;)
1937 const char *name = mips_opcodes[i].name;
1939 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1942 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1943 mips_opcodes[i].name, retval);
1944 /* Probably a memory allocation problem? Give up now. */
1945 as_fatal (_("Broken assembler. No assembly attempted."));
1949 if (mips_opcodes[i].pinfo != INSN_MACRO)
1951 if (!validate_mips_insn (&mips_opcodes[i]))
1953 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1955 create_insn (&nop_insn, mips_opcodes + i);
1956 if (mips_fix_loongson2f_nop)
1957 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1958 nop_insn.fixed_p = 1;
1963 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1966 mips16_op_hash = hash_new ();
1969 while (i < bfd_mips16_num_opcodes)
1971 const char *name = mips16_opcodes[i].name;
1973 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1975 as_fatal (_("internal: can't hash `%s': %s"),
1976 mips16_opcodes[i].name, retval);
1979 if (mips16_opcodes[i].pinfo != INSN_MACRO
1980 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1981 != mips16_opcodes[i].match))
1983 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1984 mips16_opcodes[i].name, mips16_opcodes[i].args);
1987 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1989 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1990 mips16_nop_insn.fixed_p = 1;
1994 while (i < bfd_mips16_num_opcodes
1995 && strcmp (mips16_opcodes[i].name, name) == 0);
1999 as_fatal (_("Broken assembler. No assembly attempted."));
2001 /* We add all the general register names to the symbol table. This
2002 helps us detect invalid uses of them. */
2003 for (i = 0; reg_names[i].name; i++)
2004 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2005 reg_names[i].num, /* & RNUM_MASK, */
2006 &zero_address_frag));
2008 for (i = 0; reg_names_n32n64[i].name; i++)
2009 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2010 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2011 &zero_address_frag));
2013 for (i = 0; reg_names_o32[i].name; i++)
2014 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2015 reg_names_o32[i].num, /* & RNUM_MASK, */
2016 &zero_address_frag));
2018 mips_no_prev_insn ();
2021 mips_cprmask[0] = 0;
2022 mips_cprmask[1] = 0;
2023 mips_cprmask[2] = 0;
2024 mips_cprmask[3] = 0;
2026 /* set the default alignment for the text section (2**2) */
2027 record_alignment (text_section, 2);
2029 bfd_set_gp_size (stdoutput, g_switch_value);
2034 /* On a native system other than VxWorks, sections must be aligned
2035 to 16 byte boundaries. When configured for an embedded ELF
2036 target, we don't bother. */
2037 if (strncmp (TARGET_OS, "elf", 3) != 0
2038 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2040 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2041 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2042 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2045 /* Create a .reginfo section for register masks and a .mdebug
2046 section for debugging information. */
2054 subseg = now_subseg;
2056 /* The ABI says this section should be loaded so that the
2057 running program can access it. However, we don't load it
2058 if we are configured for an embedded target */
2059 flags = SEC_READONLY | SEC_DATA;
2060 if (strncmp (TARGET_OS, "elf", 3) != 0)
2061 flags |= SEC_ALLOC | SEC_LOAD;
2063 if (mips_abi != N64_ABI)
2065 sec = subseg_new (".reginfo", (subsegT) 0);
2067 bfd_set_section_flags (stdoutput, sec, flags);
2068 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2070 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2074 /* The 64-bit ABI uses a .MIPS.options section rather than
2075 .reginfo section. */
2076 sec = subseg_new (".MIPS.options", (subsegT) 0);
2077 bfd_set_section_flags (stdoutput, sec, flags);
2078 bfd_set_section_alignment (stdoutput, sec, 3);
2080 /* Set up the option header. */
2082 Elf_Internal_Options opthdr;
2085 opthdr.kind = ODK_REGINFO;
2086 opthdr.size = (sizeof (Elf_External_Options)
2087 + sizeof (Elf64_External_RegInfo));
2090 f = frag_more (sizeof (Elf_External_Options));
2091 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2092 (Elf_External_Options *) f);
2094 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2098 if (ECOFF_DEBUGGING)
2100 sec = subseg_new (".mdebug", (subsegT) 0);
2101 (void) bfd_set_section_flags (stdoutput, sec,
2102 SEC_HAS_CONTENTS | SEC_READONLY);
2103 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2105 else if (mips_flag_pdr)
2107 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2108 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2109 SEC_READONLY | SEC_RELOC
2111 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2114 subseg_set (seg, subseg);
2117 #endif /* OBJ_ELF */
2119 if (! ECOFF_DEBUGGING)
2122 if (mips_fix_vr4120)
2123 init_vr4120_conflicts ();
2129 mips_emit_delays ();
2130 if (! ECOFF_DEBUGGING)
2135 md_assemble (char *str)
2137 struct mips_cl_insn insn;
2138 bfd_reloc_code_real_type unused_reloc[3]
2139 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2141 imm_expr.X_op = O_absent;
2142 imm2_expr.X_op = O_absent;
2143 offset_expr.X_op = O_absent;
2144 imm_reloc[0] = BFD_RELOC_UNUSED;
2145 imm_reloc[1] = BFD_RELOC_UNUSED;
2146 imm_reloc[2] = BFD_RELOC_UNUSED;
2147 offset_reloc[0] = BFD_RELOC_UNUSED;
2148 offset_reloc[1] = BFD_RELOC_UNUSED;
2149 offset_reloc[2] = BFD_RELOC_UNUSED;
2151 if (mips_opts.mips16)
2152 mips16_ip (str, &insn);
2155 mips_ip (str, &insn);
2156 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2157 str, insn.insn_opcode));
2162 as_bad ("%s `%s'", insn_error, str);
2166 if (insn.insn_mo->pinfo == INSN_MACRO)
2169 if (mips_opts.mips16)
2170 mips16_macro (&insn);
2177 if (imm_expr.X_op != O_absent)
2178 append_insn (&insn, &imm_expr, imm_reloc);
2179 else if (offset_expr.X_op != O_absent)
2180 append_insn (&insn, &offset_expr, offset_reloc);
2182 append_insn (&insn, NULL, unused_reloc);
2186 /* Convenience functions for abstracting away the differences between
2187 MIPS16 and non-MIPS16 relocations. */
2189 static inline bfd_boolean
2190 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2194 case BFD_RELOC_MIPS16_JMP:
2195 case BFD_RELOC_MIPS16_GPREL:
2196 case BFD_RELOC_MIPS16_GOT16:
2197 case BFD_RELOC_MIPS16_CALL16:
2198 case BFD_RELOC_MIPS16_HI16_S:
2199 case BFD_RELOC_MIPS16_HI16:
2200 case BFD_RELOC_MIPS16_LO16:
2208 static inline bfd_boolean
2209 got16_reloc_p (bfd_reloc_code_real_type reloc)
2211 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2214 static inline bfd_boolean
2215 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2217 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2220 static inline bfd_boolean
2221 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2223 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2226 /* Return true if the given relocation might need a matching %lo().
2227 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2228 need a matching %lo() when applied to local symbols. */
2230 static inline bfd_boolean
2231 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2233 return (HAVE_IN_PLACE_ADDENDS
2234 && (hi16_reloc_p (reloc)
2235 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2236 all GOT16 relocations evaluate to "G". */
2237 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2240 /* Return the type of %lo() reloc needed by RELOC, given that
2241 reloc_needs_lo_p. */
2243 static inline bfd_reloc_code_real_type
2244 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2246 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2249 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2252 static inline bfd_boolean
2253 fixup_has_matching_lo_p (fixS *fixp)
2255 return (fixp->fx_next != NULL
2256 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2257 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2258 && fixp->fx_offset == fixp->fx_next->fx_offset);
2261 /* This function returns true if modifying a register requires a
2265 reg_needs_delay (unsigned int reg)
2267 unsigned long prev_pinfo;
2269 prev_pinfo = history[0].insn_mo->pinfo;
2270 if (! mips_opts.noreorder
2271 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2272 && ! gpr_interlocks)
2273 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2274 && ! cop_interlocks)))
2276 /* A load from a coprocessor or from memory. All load delays
2277 delay the use of general register rt for one instruction. */
2278 /* Itbl support may require additional care here. */
2279 know (prev_pinfo & INSN_WRITE_GPR_T);
2280 if (reg == EXTRACT_OPERAND (RT, history[0]))
2287 /* Move all labels in insn_labels to the current insertion point. */
2290 mips_move_labels (void)
2292 segment_info_type *si = seg_info (now_seg);
2293 struct insn_label_list *l;
2296 for (l = si->label_list; l != NULL; l = l->next)
2298 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2299 symbol_set_frag (l->label, frag_now);
2300 val = (valueT) frag_now_fix ();
2301 /* mips16 text labels are stored as odd. */
2302 if (mips_opts.mips16)
2304 S_SET_VALUE (l->label, val);
2309 s_is_linkonce (symbolS *sym, segT from_seg)
2311 bfd_boolean linkonce = FALSE;
2312 segT symseg = S_GET_SEGMENT (sym);
2314 if (symseg != from_seg && !S_IS_LOCAL (sym))
2316 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2319 /* The GNU toolchain uses an extension for ELF: a section
2320 beginning with the magic string .gnu.linkonce is a
2321 linkonce section. */
2322 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2323 sizeof ".gnu.linkonce" - 1) == 0)
2330 /* Mark instruction labels in mips16 mode. This permits the linker to
2331 handle them specially, such as generating jalx instructions when
2332 needed. We also make them odd for the duration of the assembly, in
2333 order to generate the right sort of code. We will make them even
2334 in the adjust_symtab routine, while leaving them marked. This is
2335 convenient for the debugger and the disassembler. The linker knows
2336 to make them odd again. */
2339 mips16_mark_labels (void)
2341 segment_info_type *si = seg_info (now_seg);
2342 struct insn_label_list *l;
2344 if (!mips_opts.mips16)
2347 for (l = si->label_list; l != NULL; l = l->next)
2349 symbolS *label = l->label;
2351 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2353 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2355 if ((S_GET_VALUE (label) & 1) == 0
2356 /* Don't adjust the address if the label is global or weak, or
2357 in a link-once section, since we'll be emitting symbol reloc
2358 references to it which will be patched up by the linker, and
2359 the final value of the symbol may or may not be MIPS16. */
2360 && ! S_IS_WEAK (label)
2361 && ! S_IS_EXTERNAL (label)
2362 && ! s_is_linkonce (label, now_seg))
2363 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2367 /* End the current frag. Make it a variant frag and record the
2371 relax_close_frag (void)
2373 mips_macro_warning.first_frag = frag_now;
2374 frag_var (rs_machine_dependent, 0, 0,
2375 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2376 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2378 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2379 mips_relax.first_fixup = 0;
2382 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2383 See the comment above RELAX_ENCODE for more details. */
2386 relax_start (symbolS *symbol)
2388 gas_assert (mips_relax.sequence == 0);
2389 mips_relax.sequence = 1;
2390 mips_relax.symbol = symbol;
2393 /* Start generating the second version of a relaxable sequence.
2394 See the comment above RELAX_ENCODE for more details. */
2399 gas_assert (mips_relax.sequence == 1);
2400 mips_relax.sequence = 2;
2403 /* End the current relaxable sequence. */
2408 gas_assert (mips_relax.sequence == 2);
2409 relax_close_frag ();
2410 mips_relax.sequence = 0;
2413 /* Return the mask of core registers that IP reads. */
2416 gpr_read_mask (const struct mips_cl_insn *ip)
2418 unsigned long pinfo, pinfo2;
2422 pinfo = ip->insn_mo->pinfo;
2423 pinfo2 = ip->insn_mo->pinfo2;
2424 if (mips_opts.mips16)
2426 if (pinfo & MIPS16_INSN_READ_X)
2427 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2428 if (pinfo & MIPS16_INSN_READ_Y)
2429 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2430 if (pinfo & MIPS16_INSN_READ_T)
2432 if (pinfo & MIPS16_INSN_READ_SP)
2434 if (pinfo & MIPS16_INSN_READ_31)
2436 if (pinfo & MIPS16_INSN_READ_Z)
2437 mask |= 1 << (mips16_to_32_reg_map
2438 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2439 if (pinfo & MIPS16_INSN_READ_GPR_X)
2440 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2444 if (pinfo2 & INSN2_READ_GPR_D)
2445 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2446 if (pinfo & INSN_READ_GPR_T)
2447 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2448 if (pinfo & INSN_READ_GPR_S)
2449 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2450 if (pinfo2 & INSN2_READ_GPR_Z)
2451 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2456 /* Return the mask of core registers that IP writes. */
2459 gpr_write_mask (const struct mips_cl_insn *ip)
2461 unsigned long pinfo, pinfo2;
2465 pinfo = ip->insn_mo->pinfo;
2466 pinfo2 = ip->insn_mo->pinfo2;
2467 if (mips_opts.mips16)
2469 if (pinfo & MIPS16_INSN_WRITE_X)
2470 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2471 if (pinfo & MIPS16_INSN_WRITE_Y)
2472 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2473 if (pinfo & MIPS16_INSN_WRITE_Z)
2474 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2475 if (pinfo & MIPS16_INSN_WRITE_T)
2477 if (pinfo & MIPS16_INSN_WRITE_SP)
2479 if (pinfo & MIPS16_INSN_WRITE_31)
2481 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2482 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2486 if (pinfo & INSN_WRITE_GPR_D)
2487 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2488 if (pinfo & INSN_WRITE_GPR_T)
2489 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2490 if (pinfo & INSN_WRITE_GPR_31)
2492 if (pinfo2 & INSN2_WRITE_GPR_Z)
2493 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2498 /* Return the mask of floating-point registers that IP reads. */
2501 fpr_read_mask (const struct mips_cl_insn *ip)
2503 unsigned long pinfo, pinfo2;
2507 pinfo = ip->insn_mo->pinfo;
2508 pinfo2 = ip->insn_mo->pinfo2;
2509 if (!mips_opts.mips16)
2511 if (pinfo & INSN_READ_FPR_S)
2512 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2513 if (pinfo & INSN_READ_FPR_T)
2514 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2515 if (pinfo & INSN_READ_FPR_R)
2516 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2517 if (pinfo2 & INSN2_READ_FPR_Z)
2518 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2520 /* Conservatively treat all operands to an FP_D instruction are doubles.
2521 (This is overly pessimistic for things like cvt.d.s.) */
2522 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2527 /* Return the mask of floating-point registers that IP writes. */
2530 fpr_write_mask (const struct mips_cl_insn *ip)
2532 unsigned long pinfo, pinfo2;
2536 pinfo = ip->insn_mo->pinfo;
2537 pinfo2 = ip->insn_mo->pinfo2;
2538 if (!mips_opts.mips16)
2540 if (pinfo & INSN_WRITE_FPR_D)
2541 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2542 if (pinfo & INSN_WRITE_FPR_S)
2543 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2544 if (pinfo & INSN_WRITE_FPR_T)
2545 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2546 if (pinfo2 & INSN2_WRITE_FPR_Z)
2547 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2549 /* Conservatively treat all operands to an FP_D instruction are doubles.
2550 (This is overly pessimistic for things like cvt.s.d.) */
2551 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2556 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2557 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2558 by VR4120 errata. */
2561 classify_vr4120_insn (const char *name)
2563 if (strncmp (name, "macc", 4) == 0)
2564 return FIX_VR4120_MACC;
2565 if (strncmp (name, "dmacc", 5) == 0)
2566 return FIX_VR4120_DMACC;
2567 if (strncmp (name, "mult", 4) == 0)
2568 return FIX_VR4120_MULT;
2569 if (strncmp (name, "dmult", 5) == 0)
2570 return FIX_VR4120_DMULT;
2571 if (strstr (name, "div"))
2572 return FIX_VR4120_DIV;
2573 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2574 return FIX_VR4120_MTHILO;
2575 return NUM_FIX_VR4120_CLASSES;
2578 #define INSN_ERET 0x42000018
2579 #define INSN_DERET 0x4200001f
2581 /* Return the number of instructions that must separate INSN1 and INSN2,
2582 where INSN1 is the earlier instruction. Return the worst-case value
2583 for any INSN2 if INSN2 is null. */
2586 insns_between (const struct mips_cl_insn *insn1,
2587 const struct mips_cl_insn *insn2)
2589 unsigned long pinfo1, pinfo2;
2592 /* This function needs to know which pinfo flags are set for INSN2
2593 and which registers INSN2 uses. The former is stored in PINFO2 and
2594 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2595 will have every flag set and INSN2_USES_GPR will always return true. */
2596 pinfo1 = insn1->insn_mo->pinfo;
2597 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2599 #define INSN2_USES_GPR(REG) \
2600 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2602 /* For most targets, write-after-read dependencies on the HI and LO
2603 registers must be separated by at least two instructions. */
2604 if (!hilo_interlocks)
2606 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2608 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2612 /* If we're working around r7000 errata, there must be two instructions
2613 between an mfhi or mflo and any instruction that uses the result. */
2614 if (mips_7000_hilo_fix
2615 && MF_HILO_INSN (pinfo1)
2616 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2619 /* If we're working around 24K errata, one instruction is required
2620 if an ERET or DERET is followed by a branch instruction. */
2623 if (insn1->insn_opcode == INSN_ERET
2624 || insn1->insn_opcode == INSN_DERET)
2627 || insn2->insn_opcode == INSN_ERET
2628 || insn2->insn_opcode == INSN_DERET
2629 || (insn2->insn_mo->pinfo
2630 & (INSN_UNCOND_BRANCH_DELAY
2631 | INSN_COND_BRANCH_DELAY
2632 | INSN_COND_BRANCH_LIKELY)) != 0)
2637 /* If working around VR4120 errata, check for combinations that need
2638 a single intervening instruction. */
2639 if (mips_fix_vr4120)
2641 unsigned int class1, class2;
2643 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2644 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2648 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2649 if (vr4120_conflicts[class1] & (1 << class2))
2654 if (!mips_opts.mips16)
2656 /* Check for GPR or coprocessor load delays. All such delays
2657 are on the RT register. */
2658 /* Itbl support may require additional care here. */
2659 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2660 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2662 know (pinfo1 & INSN_WRITE_GPR_T);
2663 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2667 /* Check for generic coprocessor hazards.
2669 This case is not handled very well. There is no special
2670 knowledge of CP0 handling, and the coprocessors other than
2671 the floating point unit are not distinguished at all. */
2672 /* Itbl support may require additional care here. FIXME!
2673 Need to modify this to include knowledge about
2674 user specified delays! */
2675 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2676 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2678 /* Handle cases where INSN1 writes to a known general coprocessor
2679 register. There must be a one instruction delay before INSN2
2680 if INSN2 reads that register, otherwise no delay is needed. */
2681 mask = fpr_write_mask (insn1);
2684 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2689 /* Read-after-write dependencies on the control registers
2690 require a two-instruction gap. */
2691 if ((pinfo1 & INSN_WRITE_COND_CODE)
2692 && (pinfo2 & INSN_READ_COND_CODE))
2695 /* We don't know exactly what INSN1 does. If INSN2 is
2696 also a coprocessor instruction, assume there must be
2697 a one instruction gap. */
2698 if (pinfo2 & INSN_COP)
2703 /* Check for read-after-write dependencies on the coprocessor
2704 control registers in cases where INSN1 does not need a general
2705 coprocessor delay. This means that INSN1 is a floating point
2706 comparison instruction. */
2707 /* Itbl support may require additional care here. */
2708 else if (!cop_interlocks
2709 && (pinfo1 & INSN_WRITE_COND_CODE)
2710 && (pinfo2 & INSN_READ_COND_CODE))
2714 #undef INSN2_USES_GPR
2719 /* Return the number of nops that would be needed to work around the
2720 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2721 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2722 that are contained within the first IGNORE instructions of HIST. */
2725 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2726 const struct mips_cl_insn *insn)
2731 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2732 are not affected by the errata. */
2734 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2735 || strcmp (insn->insn_mo->name, "mtlo") == 0
2736 || strcmp (insn->insn_mo->name, "mthi") == 0))
2739 /* Search for the first MFLO or MFHI. */
2740 for (i = 0; i < MAX_VR4130_NOPS; i++)
2741 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2743 /* Extract the destination register. */
2744 mask = gpr_write_mask (&hist[i]);
2746 /* No nops are needed if INSN reads that register. */
2747 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2750 /* ...or if any of the intervening instructions do. */
2751 for (j = 0; j < i; j++)
2752 if (gpr_read_mask (&hist[j]) & mask)
2756 return MAX_VR4130_NOPS - i;
2761 #define BASE_REG_EQ(INSN1, INSN2) \
2762 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2763 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2765 /* Return the minimum alignment for this store instruction. */
2768 fix_24k_align_to (const struct mips_opcode *mo)
2770 if (strcmp (mo->name, "sh") == 0)
2773 if (strcmp (mo->name, "swc1") == 0
2774 || strcmp (mo->name, "swc2") == 0
2775 || strcmp (mo->name, "sw") == 0
2776 || strcmp (mo->name, "sc") == 0
2777 || strcmp (mo->name, "s.s") == 0)
2780 if (strcmp (mo->name, "sdc1") == 0
2781 || strcmp (mo->name, "sdc2") == 0
2782 || strcmp (mo->name, "s.d") == 0)
2789 struct fix_24k_store_info
2791 /* Immediate offset, if any, for this store instruction. */
2793 /* Alignment required by this store instruction. */
2795 /* True for register offsets. */
2796 int register_offset;
2799 /* Comparison function used by qsort. */
2802 fix_24k_sort (const void *a, const void *b)
2804 const struct fix_24k_store_info *pos1 = a;
2805 const struct fix_24k_store_info *pos2 = b;
2807 return (pos1->off - pos2->off);
2810 /* INSN is a store instruction. Try to record the store information
2811 in STINFO. Return false if the information isn't known. */
2814 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2815 const struct mips_cl_insn *insn)
2817 /* The instruction must have a known offset. */
2818 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2821 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2822 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2826 /* Return the number of nops that would be needed to work around the 24k
2827 "lost data on stores during refill" errata if instruction INSN
2828 immediately followed the 2 instructions described by HIST.
2829 Ignore hazards that are contained within the first IGNORE
2830 instructions of HIST.
2832 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2833 for the data cache refills and store data. The following describes
2834 the scenario where the store data could be lost.
2836 * A data cache miss, due to either a load or a store, causing fill
2837 data to be supplied by the memory subsystem
2838 * The first three doublewords of fill data are returned and written
2840 * A sequence of four stores occurs in consecutive cycles around the
2841 final doubleword of the fill:
2845 * Zero, One or more instructions
2848 The four stores A-D must be to different doublewords of the line that
2849 is being filled. The fourth instruction in the sequence above permits
2850 the fill of the final doubleword to be transferred from the FSB into
2851 the cache. In the sequence above, the stores may be either integer
2852 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2853 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2854 different doublewords on the line. If the floating point unit is
2855 running in 1:2 mode, it is not possible to create the sequence above
2856 using only floating point store instructions.
2858 In this case, the cache line being filled is incorrectly marked
2859 invalid, thereby losing the data from any store to the line that
2860 occurs between the original miss and the completion of the five
2861 cycle sequence shown above.
2863 The workarounds are:
2865 * Run the data cache in write-through mode.
2866 * Insert a non-store instruction between
2867 Store A and Store B or Store B and Store C. */
2870 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2871 const struct mips_cl_insn *insn)
2873 struct fix_24k_store_info pos[3];
2874 int align, i, base_offset;
2879 /* If the previous instruction wasn't a store, there's nothing to
2881 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2884 /* If the instructions after the previous one are unknown, we have
2885 to assume the worst. */
2889 /* Check whether we are dealing with three consecutive stores. */
2890 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2891 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2894 /* If we don't know the relationship between the store addresses,
2895 assume the worst. */
2896 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2897 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2900 if (!fix_24k_record_store_info (&pos[0], insn)
2901 || !fix_24k_record_store_info (&pos[1], &hist[0])
2902 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2905 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2907 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2908 X bytes and such that the base register + X is known to be aligned
2911 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2915 align = pos[0].align_to;
2916 base_offset = pos[0].off;
2917 for (i = 1; i < 3; i++)
2918 if (align < pos[i].align_to)
2920 align = pos[i].align_to;
2921 base_offset = pos[i].off;
2923 for (i = 0; i < 3; i++)
2924 pos[i].off -= base_offset;
2927 pos[0].off &= ~align + 1;
2928 pos[1].off &= ~align + 1;
2929 pos[2].off &= ~align + 1;
2931 /* If any two stores write to the same chunk, they also write to the
2932 same doubleword. The offsets are still sorted at this point. */
2933 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2936 /* A range of at least 9 bytes is needed for the stores to be in
2937 non-overlapping doublewords. */
2938 if (pos[2].off - pos[0].off <= 8)
2941 if (pos[2].off - pos[1].off >= 24
2942 || pos[1].off - pos[0].off >= 24
2943 || pos[2].off - pos[0].off >= 32)
2949 /* Return the number of nops that would be needed if instruction INSN
2950 immediately followed the MAX_NOPS instructions given by HIST,
2951 where HIST[0] is the most recent instruction. Ignore hazards
2952 between INSN and the first IGNORE instructions in HIST.
2954 If INSN is null, return the worse-case number of nops for any
2958 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2959 const struct mips_cl_insn *insn)
2961 int i, nops, tmp_nops;
2964 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2966 tmp_nops = insns_between (hist + i, insn) - i;
2967 if (tmp_nops > nops)
2971 if (mips_fix_vr4130)
2973 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2974 if (tmp_nops > nops)
2980 tmp_nops = nops_for_24k (ignore, hist, insn);
2981 if (tmp_nops > nops)
2988 /* The variable arguments provide NUM_INSNS extra instructions that
2989 might be added to HIST. Return the largest number of nops that
2990 would be needed after the extended sequence, ignoring hazards
2991 in the first IGNORE instructions. */
2994 nops_for_sequence (int num_insns, int ignore,
2995 const struct mips_cl_insn *hist, ...)
2998 struct mips_cl_insn buffer[MAX_NOPS];
2999 struct mips_cl_insn *cursor;
3002 va_start (args, hist);
3003 cursor = buffer + num_insns;
3004 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3005 while (cursor > buffer)
3006 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3008 nops = nops_for_insn (ignore, buffer, NULL);
3013 /* Like nops_for_insn, but if INSN is a branch, take into account the
3014 worst-case delay for the branch target. */
3017 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3018 const struct mips_cl_insn *insn)
3022 nops = nops_for_insn (ignore, hist, insn);
3023 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3024 | INSN_COND_BRANCH_DELAY
3025 | INSN_COND_BRANCH_LIKELY))
3027 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3028 hist, insn, NOP_INSN);
3029 if (tmp_nops > nops)
3032 else if (mips_opts.mips16
3033 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3034 | MIPS16_INSN_COND_BRANCH)))
3036 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3037 if (tmp_nops > nops)
3043 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3046 fix_loongson2f_nop (struct mips_cl_insn * ip)
3048 if (strcmp (ip->insn_mo->name, "nop") == 0)
3049 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3052 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3053 jr target pc &= 'hffff_ffff_cfff_ffff. */
3056 fix_loongson2f_jump (struct mips_cl_insn * ip)
3058 if (strcmp (ip->insn_mo->name, "j") == 0
3059 || strcmp (ip->insn_mo->name, "jr") == 0
3060 || strcmp (ip->insn_mo->name, "jalr") == 0)
3068 sreg = EXTRACT_OPERAND (RS, *ip);
3069 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3072 ep.X_op = O_constant;
3073 ep.X_add_number = 0xcfff0000;
3074 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3075 ep.X_add_number = 0xffff;
3076 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3077 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3082 fix_loongson2f (struct mips_cl_insn * ip)
3084 if (mips_fix_loongson2f_nop)
3085 fix_loongson2f_nop (ip);
3087 if (mips_fix_loongson2f_jump)
3088 fix_loongson2f_jump (ip);
3091 /* IP is a branch that has a delay slot, and we need to fill it
3092 automatically. Return true if we can do that by swapping IP
3093 with the previous instruction. */
3096 can_swap_branch_p (struct mips_cl_insn *ip)
3098 unsigned long pinfo, prev_pinfo;
3099 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3101 /* -O2 and above is required for this optimization. */
3102 if (mips_optimize < 2)
3105 /* If we have seen .set volatile or .set nomove, don't optimize. */
3106 if (mips_opts.nomove)
3109 /* We can't swap if the previous instruction's position is fixed. */
3110 if (history[0].fixed_p)
3113 /* If the previous previous insn was in a .set noreorder, we can't
3114 swap. Actually, the MIPS assembler will swap in this situation.
3115 However, gcc configured -with-gnu-as will generate code like
3123 in which we can not swap the bne and INSN. If gcc is not configured
3124 -with-gnu-as, it does not output the .set pseudo-ops. */
3125 if (history[1].noreorder_p)
3128 /* If the previous instruction had a fixup in mips16 mode, we can not
3129 swap. This normally means that the previous instruction was a 4
3130 byte branch anyhow. */
3131 if (mips_opts.mips16 && history[0].fixp[0])
3134 /* If the branch is itself the target of a branch, we can not swap.
3135 We cheat on this; all we check for is whether there is a label on
3136 this instruction. If there are any branches to anything other than
3137 a label, users must use .set noreorder. */
3138 if (seg_info (now_seg)->label_list)
3141 /* If the previous instruction is in a variant frag other than this
3142 branch's one, we cannot do the swap. This does not apply to the
3143 mips16, which uses variant frags for different purposes. */
3144 if (!mips_opts.mips16
3146 && history[0].frag->fr_type == rs_machine_dependent)
3149 /* We do not swap with a trap instruction, since it complicates trap
3150 handlers to have the trap instruction be in a delay slot. */
3151 prev_pinfo = history[0].insn_mo->pinfo;
3152 if (prev_pinfo & INSN_TRAP)
3155 /* If the previous instruction is a sync, sync.l, or sync.p, we can
3157 if (prev_pinfo & INSN_SYNC)
3160 /* If the previous instruction is an ERET or DERET, avoid the swap. */
3161 if (history[0].insn_opcode == INSN_ERET)
3163 if (history[0].insn_opcode == INSN_DERET)
3166 /* Check for conflicts between the branch and the instructions
3167 before the candidate delay slot. */
3168 if (nops_for_insn (0, history + 1, ip) > 0)
3171 /* Check for conflicts between the swapped sequence and the
3172 target of the branch. */
3173 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3176 /* If the branch reads a register that the previous
3177 instruction sets, we can not swap. */
3178 gpr_read = gpr_read_mask (ip);
3179 prev_gpr_write = gpr_write_mask (&history[0]);
3180 if (gpr_read & prev_gpr_write)
3183 /* If the branch writes a register that the previous
3184 instruction sets, we can not swap. */
3185 gpr_write = gpr_write_mask (ip);
3186 if (gpr_write & prev_gpr_write)
3189 /* If the branch writes a register that the previous
3190 instruction reads, we can not swap. */
3191 prev_gpr_read = gpr_read_mask (&history[0]);
3192 if (gpr_write & prev_gpr_read)
3195 /* If one instruction sets a condition code and the
3196 other one uses a condition code, we can not swap. */
3197 pinfo = ip->insn_mo->pinfo;
3198 if ((pinfo & INSN_READ_COND_CODE)
3199 && (prev_pinfo & INSN_WRITE_COND_CODE))
3201 if ((pinfo & INSN_WRITE_COND_CODE)
3202 && (prev_pinfo & INSN_READ_COND_CODE))
3205 /* If the previous instruction uses the PC, we can not swap. */
3206 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3212 /* Decide how we should add IP to the instruction stream. */
3214 static enum append_method
3215 get_append_method (struct mips_cl_insn *ip)
3217 unsigned long pinfo;
3219 /* The relaxed version of a macro sequence must be inherently
3221 if (mips_relax.sequence == 2)
3224 /* We must not dabble with instructions in a ".set norerorder" block. */
3225 if (mips_opts.noreorder)
3228 /* Otherwise, it's our responsibility to fill branch delay slots. */
3229 pinfo = ip->insn_mo->pinfo;
3230 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3231 || (pinfo & INSN_COND_BRANCH_DELAY))
3233 if (can_swap_branch_p (ip))
3236 if (mips_opts.mips16
3237 && ISA_SUPPORTS_MIPS16E
3238 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3239 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3240 return APPEND_ADD_COMPACT;
3242 return APPEND_ADD_WITH_NOP;
3245 /* We don't bother trying to track the target of branches, so there's
3246 nothing we can use to fill a branch-likely slot. */
3247 if (pinfo & INSN_COND_BRANCH_LIKELY)
3248 return APPEND_ADD_WITH_NOP;
3253 /* IP is a MIPS16 instruction whose opcode we have just changed.
3254 Point IP->insn_mo to the new opcode's definition. */
3257 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3259 const struct mips_opcode *mo, *end;
3261 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3262 for (mo = ip->insn_mo; mo < end; mo++)
3263 if ((ip->insn_opcode & mo->mask) == mo->match)
3271 /* Output an instruction. IP is the instruction information.
3272 ADDRESS_EXPR is an operand of the instruction to be used with
3276 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3277 bfd_reloc_code_real_type *reloc_type)
3279 unsigned long prev_pinfo, pinfo;
3280 unsigned long prev_pinfo2, pinfo2;
3281 bfd_boolean relaxed_branch = FALSE;
3282 enum append_method method;
3284 if (mips_fix_loongson2f)
3285 fix_loongson2f (ip);
3287 /* Mark instruction labels in mips16 mode. */
3288 mips16_mark_labels ();
3290 file_ase_mips16 |= mips_opts.mips16;
3292 prev_pinfo = history[0].insn_mo->pinfo;
3293 prev_pinfo2 = history[0].insn_mo->pinfo2;
3294 pinfo = ip->insn_mo->pinfo;
3295 pinfo2 = ip->insn_mo->pinfo2;
3297 if (address_expr == NULL)
3299 else if (*reloc_type <= BFD_RELOC_UNUSED
3300 && address_expr->X_op == O_constant)
3305 switch (*reloc_type)
3308 ip->insn_opcode |= address_expr->X_add_number;
3311 case BFD_RELOC_MIPS_HIGHEST:
3312 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3313 ip->insn_opcode |= tmp & 0xffff;
3316 case BFD_RELOC_MIPS_HIGHER:
3317 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3318 ip->insn_opcode |= tmp & 0xffff;
3321 case BFD_RELOC_HI16_S:
3322 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3323 ip->insn_opcode |= tmp & 0xffff;
3326 case BFD_RELOC_HI16:
3327 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3330 case BFD_RELOC_UNUSED:
3331 case BFD_RELOC_LO16:
3332 case BFD_RELOC_MIPS_GOT_DISP:
3333 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3336 case BFD_RELOC_MIPS_JMP:
3337 if ((address_expr->X_add_number & 3) != 0)
3338 as_bad (_("jump to misaligned address (0x%lx)"),
3339 (unsigned long) address_expr->X_add_number);
3340 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3344 case BFD_RELOC_MIPS16_JMP:
3345 if ((address_expr->X_add_number & 3) != 0)
3346 as_bad (_("jump to misaligned address (0x%lx)"),
3347 (unsigned long) address_expr->X_add_number);
3349 (((address_expr->X_add_number & 0x7c0000) << 3)
3350 | ((address_expr->X_add_number & 0xf800000) >> 7)
3351 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3355 case BFD_RELOC_16_PCREL_S2:
3356 if ((address_expr->X_add_number & 3) != 0)
3357 as_bad (_("branch to misaligned address (0x%lx)"),
3358 (unsigned long) address_expr->X_add_number);
3359 if (!mips_relax_branch)
3361 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3362 as_bad (_("branch address range overflow (0x%lx)"),
3363 (unsigned long) address_expr->X_add_number);
3364 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3374 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3376 /* There are a lot of optimizations we could do that we don't.
3377 In particular, we do not, in general, reorder instructions.
3378 If you use gcc with optimization, it will reorder
3379 instructions and generally do much more optimization then we
3380 do here; repeating all that work in the assembler would only
3381 benefit hand written assembly code, and does not seem worth
3383 int nops = (mips_optimize == 0
3384 ? nops_for_insn (0, history, NULL)
3385 : nops_for_insn_or_target (0, history, ip));
3389 unsigned long old_frag_offset;
3392 old_frag = frag_now;
3393 old_frag_offset = frag_now_fix ();
3395 for (i = 0; i < nops; i++)
3400 listing_prev_line ();
3401 /* We may be at the start of a variant frag. In case we
3402 are, make sure there is enough space for the frag
3403 after the frags created by listing_prev_line. The
3404 argument to frag_grow here must be at least as large
3405 as the argument to all other calls to frag_grow in
3406 this file. We don't have to worry about being in the
3407 middle of a variant frag, because the variants insert
3408 all needed nop instructions themselves. */
3412 mips_move_labels ();
3414 #ifndef NO_ECOFF_DEBUGGING
3415 if (ECOFF_DEBUGGING)
3416 ecoff_fix_loc (old_frag, old_frag_offset);
3420 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3424 /* Work out how many nops in prev_nop_frag are needed by IP,
3425 ignoring hazards generated by the first prev_nop_frag_since
3427 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3428 gas_assert (nops <= prev_nop_frag_holds);
3430 /* Enforce NOPS as a minimum. */
3431 if (nops > prev_nop_frag_required)
3432 prev_nop_frag_required = nops;
3434 if (prev_nop_frag_holds == prev_nop_frag_required)
3436 /* Settle for the current number of nops. Update the history
3437 accordingly (for the benefit of any future .set reorder code). */
3438 prev_nop_frag = NULL;
3439 insert_into_history (prev_nop_frag_since,
3440 prev_nop_frag_holds, NOP_INSN);
3444 /* Allow this instruction to replace one of the nops that was
3445 tentatively added to prev_nop_frag. */
3446 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3447 prev_nop_frag_holds--;
3448 prev_nop_frag_since++;
3452 method = get_append_method (ip);
3455 /* The value passed to dwarf2_emit_insn is the distance between
3456 the beginning of the current instruction and the address that
3457 should be recorded in the debug tables. This is normally the
3460 For MIPS16 debug info we want to use ISA-encoded addresses,
3461 so we use -1 for an address higher by one than the current one.
3463 If the instruction produced is a branch that we will swap with
3464 the preceding instruction, then we add the displacement by which
3465 the branch will be moved backwards. This is more appropriate
3466 and for MIPS16 code also prevents a debugger from placing a
3467 breakpoint in the middle of the branch (and corrupting code if
3468 software breakpoints are used). */
3469 dwarf2_emit_insn ((mips_opts.mips16 ? -1 : 0)
3470 + (method == APPEND_SWAP ? insn_length (history) : 0));
3474 && *reloc_type == BFD_RELOC_16_PCREL_S2
3475 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3476 || pinfo & INSN_COND_BRANCH_LIKELY)
3477 && mips_relax_branch
3478 /* Don't try branch relaxation within .set nomacro, or within
3479 .set noat if we use $at for PIC computations. If it turns
3480 out that the branch was out-of-range, we'll get an error. */
3481 && !mips_opts.warn_about_macros
3482 && (mips_opts.at || mips_pic == NO_PIC)
3483 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3484 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3485 && !mips_opts.mips16)
3487 relaxed_branch = TRUE;
3488 add_relaxed_insn (ip, (relaxed_branch_length
3490 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3491 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3495 pinfo & INSN_UNCOND_BRANCH_DELAY,
3496 pinfo & INSN_COND_BRANCH_LIKELY,
3497 pinfo & INSN_WRITE_GPR_31,
3499 address_expr->X_add_symbol,
3500 address_expr->X_add_number);
3501 *reloc_type = BFD_RELOC_UNUSED;
3503 else if (*reloc_type > BFD_RELOC_UNUSED)
3505 /* We need to set up a variant frag. */
3506 gas_assert (mips_opts.mips16 && address_expr != NULL);
3507 add_relaxed_insn (ip, 4, 0,
3509 (*reloc_type - BFD_RELOC_UNUSED,
3510 mips16_small, mips16_ext,
3511 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3512 history[0].mips16_absolute_jump_p),
3513 make_expr_symbol (address_expr), 0);
3515 else if (mips_opts.mips16
3517 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3519 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3520 /* Make sure there is enough room to swap this instruction with
3521 a following jump instruction. */
3523 add_fixed_insn (ip);
3527 if (mips_opts.mips16
3528 && mips_opts.noreorder
3529 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3530 as_warn (_("extended instruction in delay slot"));
3532 if (mips_relax.sequence)
3534 /* If we've reached the end of this frag, turn it into a variant
3535 frag and record the information for the instructions we've
3537 if (frag_room () < 4)
3538 relax_close_frag ();
3539 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3542 if (mips_relax.sequence != 2)
3543 mips_macro_warning.sizes[0] += 4;
3544 if (mips_relax.sequence != 1)
3545 mips_macro_warning.sizes[1] += 4;
3547 if (mips_opts.mips16)
3550 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3552 add_fixed_insn (ip);
3555 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
3557 reloc_howto_type *howto;
3560 /* In a compound relocation, it is the final (outermost)
3561 operator that determines the relocated field. */
3562 for (i = 1; i < 3; i++)
3563 if (reloc_type[i] == BFD_RELOC_UNUSED)
3566 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3569 /* To reproduce this failure try assembling gas/testsuites/
3570 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3572 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3573 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3576 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3577 bfd_get_reloc_size (howto),
3579 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3582 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3583 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3584 && ip->fixp[0]->fx_addsy)
3585 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3587 /* These relocations can have an addend that won't fit in
3588 4 octets for 64bit assembly. */
3590 && ! howto->partial_inplace
3591 && (reloc_type[0] == BFD_RELOC_16
3592 || reloc_type[0] == BFD_RELOC_32
3593 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3594 || reloc_type[0] == BFD_RELOC_GPREL16
3595 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3596 || reloc_type[0] == BFD_RELOC_GPREL32
3597 || reloc_type[0] == BFD_RELOC_64
3598 || reloc_type[0] == BFD_RELOC_CTOR
3599 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3600 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3601 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3602 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3603 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3604 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3605 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3606 || hi16_reloc_p (reloc_type[0])
3607 || lo16_reloc_p (reloc_type[0])))
3608 ip->fixp[0]->fx_no_overflow = 1;
3610 if (mips_relax.sequence)
3612 if (mips_relax.first_fixup == 0)
3613 mips_relax.first_fixup = ip->fixp[0];
3615 else if (reloc_needs_lo_p (*reloc_type))
3617 struct mips_hi_fixup *hi_fixup;
3619 /* Reuse the last entry if it already has a matching %lo. */
3620 hi_fixup = mips_hi_fixup_list;
3622 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3624 hi_fixup = ((struct mips_hi_fixup *)
3625 xmalloc (sizeof (struct mips_hi_fixup)));
3626 hi_fixup->next = mips_hi_fixup_list;
3627 mips_hi_fixup_list = hi_fixup;
3629 hi_fixup->fixp = ip->fixp[0];
3630 hi_fixup->seg = now_seg;
3633 /* Add fixups for the second and third relocations, if given.
3634 Note that the ABI allows the second relocation to be
3635 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3636 moment we only use RSS_UNDEF, but we could add support
3637 for the others if it ever becomes necessary. */
3638 for (i = 1; i < 3; i++)
3639 if (reloc_type[i] != BFD_RELOC_UNUSED)
3641 ip->fixp[i] = fix_new (ip->frag, ip->where,
3642 ip->fixp[0]->fx_size, NULL, 0,
3643 FALSE, reloc_type[i]);
3645 /* Use fx_tcbit to mark compound relocs. */
3646 ip->fixp[0]->fx_tcbit = 1;
3647 ip->fixp[i]->fx_tcbit = 1;
3652 /* Update the register mask information. */
3653 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3654 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3659 insert_into_history (0, 1, ip);
3662 case APPEND_ADD_WITH_NOP:
3663 insert_into_history (0, 1, ip);
3665 if (mips_relax.sequence)
3666 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3669 case APPEND_ADD_COMPACT:
3670 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3671 gas_assert (mips_opts.mips16);
3672 ip->insn_opcode |= 0x0080;
3673 find_altered_mips16_opcode (ip);
3675 insert_into_history (0, 1, ip);
3680 struct mips_cl_insn delay = history[0];
3681 if (mips_opts.mips16)
3683 know (delay.frag == ip->frag);
3684 move_insn (ip, delay.frag, delay.where);
3685 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3687 else if (relaxed_branch)
3689 /* Add the delay slot instruction to the end of the
3690 current frag and shrink the fixed part of the
3691 original frag. If the branch occupies the tail of
3692 the latter, move it backwards to cover the gap. */
3693 delay.frag->fr_fix -= 4;
3694 if (delay.frag == ip->frag)
3695 move_insn (ip, ip->frag, ip->where - 4);
3696 add_fixed_insn (&delay);
3700 move_insn (&delay, ip->frag, ip->where);
3701 move_insn (ip, history[0].frag, history[0].where);
3705 insert_into_history (0, 1, &delay);
3710 /* If we have just completed an unconditional branch, clear the history. */
3711 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
3712 || (mips_opts.mips16
3713 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
3714 mips_no_prev_insn ();
3716 /* We just output an insn, so the next one doesn't have a label. */
3717 mips_clear_insn_labels ();
3720 /* Forget that there was any previous instruction or label. */
3723 mips_no_prev_insn (void)
3725 prev_nop_frag = NULL;
3726 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3727 mips_clear_insn_labels ();
3730 /* This function must be called before we emit something other than
3731 instructions. It is like mips_no_prev_insn except that it inserts
3732 any NOPS that might be needed by previous instructions. */
3735 mips_emit_delays (void)
3737 if (! mips_opts.noreorder)
3739 int nops = nops_for_insn (0, history, NULL);
3743 add_fixed_insn (NOP_INSN);
3744 mips_move_labels ();
3747 mips_no_prev_insn ();
3750 /* Start a (possibly nested) noreorder block. */
3753 start_noreorder (void)
3755 if (mips_opts.noreorder == 0)
3760 /* None of the instructions before the .set noreorder can be moved. */
3761 for (i = 0; i < ARRAY_SIZE (history); i++)
3762 history[i].fixed_p = 1;
3764 /* Insert any nops that might be needed between the .set noreorder
3765 block and the previous instructions. We will later remove any
3766 nops that turn out not to be needed. */
3767 nops = nops_for_insn (0, history, NULL);
3770 if (mips_optimize != 0)
3772 /* Record the frag which holds the nop instructions, so
3773 that we can remove them if we don't need them. */
3774 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3775 prev_nop_frag = frag_now;
3776 prev_nop_frag_holds = nops;
3777 prev_nop_frag_required = 0;
3778 prev_nop_frag_since = 0;
3781 for (; nops > 0; --nops)
3782 add_fixed_insn (NOP_INSN);
3784 /* Move on to a new frag, so that it is safe to simply
3785 decrease the size of prev_nop_frag. */
3786 frag_wane (frag_now);
3788 mips_move_labels ();
3790 mips16_mark_labels ();
3791 mips_clear_insn_labels ();
3793 mips_opts.noreorder++;
3794 mips_any_noreorder = 1;
3797 /* End a nested noreorder block. */
3800 end_noreorder (void)
3803 mips_opts.noreorder--;
3804 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3806 /* Commit to inserting prev_nop_frag_required nops and go back to
3807 handling nop insertion the .set reorder way. */
3808 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3809 * (mips_opts.mips16 ? 2 : 4));
3810 insert_into_history (prev_nop_frag_since,
3811 prev_nop_frag_required, NOP_INSN);
3812 prev_nop_frag = NULL;
3816 /* Set up global variables for the start of a new macro. */
3821 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3822 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3823 && (history[0].insn_mo->pinfo
3824 & (INSN_UNCOND_BRANCH_DELAY
3825 | INSN_COND_BRANCH_DELAY
3826 | INSN_COND_BRANCH_LIKELY)) != 0);
3829 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3830 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3831 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3834 macro_warning (relax_substateT subtype)
3836 if (subtype & RELAX_DELAY_SLOT)
3837 return _("Macro instruction expanded into multiple instructions"
3838 " in a branch delay slot");
3839 else if (subtype & RELAX_NOMACRO)
3840 return _("Macro instruction expanded into multiple instructions");
3845 /* Finish up a macro. Emit warnings as appropriate. */
3850 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3852 relax_substateT subtype;
3854 /* Set up the relaxation warning flags. */
3856 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3857 subtype |= RELAX_SECOND_LONGER;
3858 if (mips_opts.warn_about_macros)
3859 subtype |= RELAX_NOMACRO;
3860 if (mips_macro_warning.delay_slot_p)
3861 subtype |= RELAX_DELAY_SLOT;
3863 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3865 /* Either the macro has a single implementation or both
3866 implementations are longer than 4 bytes. Emit the
3868 const char *msg = macro_warning (subtype);
3870 as_warn ("%s", msg);
3874 /* One implementation might need a warning but the other
3875 definitely doesn't. */
3876 mips_macro_warning.first_frag->fr_subtype |= subtype;
3881 /* Read a macro's relocation codes from *ARGS and store them in *R.
3882 The first argument in *ARGS will be either the code for a single
3883 relocation or -1 followed by the three codes that make up a
3884 composite relocation. */
3887 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3891 next = va_arg (*args, int);
3893 r[0] = (bfd_reloc_code_real_type) next;
3895 for (i = 0; i < 3; i++)
3896 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3899 /* Build an instruction created by a macro expansion. This is passed
3900 a pointer to the count of instructions created so far, an
3901 expression, the name of the instruction to build, an operand format
3902 string, and corresponding arguments. */
3905 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3907 const struct mips_opcode *mo;
3908 struct mips_cl_insn insn;
3909 bfd_reloc_code_real_type r[3];
3912 va_start (args, fmt);
3914 if (mips_opts.mips16)
3916 mips16_macro_build (ep, name, fmt, &args);
3921 r[0] = BFD_RELOC_UNUSED;
3922 r[1] = BFD_RELOC_UNUSED;
3923 r[2] = BFD_RELOC_UNUSED;
3924 mo = (struct mips_opcode *) hash_find (op_hash, name);
3926 gas_assert (strcmp (name, mo->name) == 0);
3930 /* Search until we get a match for NAME. It is assumed here that
3931 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3932 if (strcmp (fmt, mo->args) == 0
3933 && mo->pinfo != INSN_MACRO
3934 && is_opcode_valid (mo))
3938 gas_assert (mo->name);
3939 gas_assert (strcmp (name, mo->name) == 0);
3942 create_insn (&insn, mo);
3960 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3965 /* Note that in the macro case, these arguments are already
3966 in MSB form. (When handling the instruction in the
3967 non-macro case, these arguments are sizes from which
3968 MSB values must be calculated.) */
3969 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3975 /* Note that in the macro case, these arguments are already
3976 in MSBD form. (When handling the instruction in the
3977 non-macro case, these arguments are sizes from which
3978 MSBD values must be calculated.) */
3979 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3983 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3992 INSERT_OPERAND (BP, insn, va_arg (args, int));
3998 INSERT_OPERAND (RT, insn, va_arg (args, int));
4002 INSERT_OPERAND (CODE, insn, va_arg (args, int));
4007 INSERT_OPERAND (FT, insn, va_arg (args, int));
4013 INSERT_OPERAND (RD, insn, va_arg (args, int));
4018 int tmp = va_arg (args, int);
4020 INSERT_OPERAND (RT, insn, tmp);
4021 INSERT_OPERAND (RD, insn, tmp);
4027 INSERT_OPERAND (FS, insn, va_arg (args, int));
4034 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
4038 INSERT_OPERAND (FD, insn, va_arg (args, int));
4042 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4046 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4050 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4057 INSERT_OPERAND (RS, insn, va_arg (args, int));
4062 macro_read_relocs (&args, r);
4063 gas_assert (*r == BFD_RELOC_GPREL16
4064 || *r == BFD_RELOC_MIPS_HIGHER
4065 || *r == BFD_RELOC_HI16_S
4066 || *r == BFD_RELOC_LO16
4067 || *r == BFD_RELOC_MIPS_GOT_OFST);
4071 macro_read_relocs (&args, r);
4075 macro_read_relocs (&args, r);
4076 gas_assert (ep != NULL
4077 && (ep->X_op == O_constant
4078 || (ep->X_op == O_symbol
4079 && (*r == BFD_RELOC_MIPS_HIGHEST
4080 || *r == BFD_RELOC_HI16_S
4081 || *r == BFD_RELOC_HI16
4082 || *r == BFD_RELOC_GPREL16
4083 || *r == BFD_RELOC_MIPS_GOT_HI16
4084 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4088 gas_assert (ep != NULL);
4091 * This allows macro() to pass an immediate expression for
4092 * creating short branches without creating a symbol.
4094 * We don't allow branch relaxation for these branches, as
4095 * they should only appear in ".set nomacro" anyway.
4097 if (ep->X_op == O_constant)
4099 if ((ep->X_add_number & 3) != 0)
4100 as_bad (_("branch to misaligned address (0x%lx)"),
4101 (unsigned long) ep->X_add_number);
4102 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4103 as_bad (_("branch address range overflow (0x%lx)"),
4104 (unsigned long) ep->X_add_number);
4105 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4109 *r = BFD_RELOC_16_PCREL_S2;
4113 gas_assert (ep != NULL);
4114 *r = BFD_RELOC_MIPS_JMP;
4118 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4122 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4131 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4133 append_insn (&insn, ep, r);
4137 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4140 struct mips_opcode *mo;
4141 struct mips_cl_insn insn;
4142 bfd_reloc_code_real_type r[3]
4143 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4145 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4147 gas_assert (strcmp (name, mo->name) == 0);
4149 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4152 gas_assert (mo->name);
4153 gas_assert (strcmp (name, mo->name) == 0);
4156 create_insn (&insn, mo);
4174 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4179 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4183 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4187 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4197 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4204 regno = va_arg (*args, int);
4205 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4206 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4227 gas_assert (ep != NULL);
4229 if (ep->X_op != O_constant)
4230 *r = (int) BFD_RELOC_UNUSED + c;
4233 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4234 FALSE, &insn.insn_opcode, &insn.use_extend,
4237 *r = BFD_RELOC_UNUSED;
4243 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4250 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4252 append_insn (&insn, ep, r);
4256 * Sign-extend 32-bit mode constants that have bit 31 set and all
4257 * higher bits unset.
4260 normalize_constant_expr (expressionS *ex)
4262 if (ex->X_op == O_constant
4263 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4264 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4269 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4270 * all higher bits unset.
4273 normalize_address_expr (expressionS *ex)
4275 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4276 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4277 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4278 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4283 * Generate a "jalr" instruction with a relocation hint to the called
4284 * function. This occurs in NewABI PIC code.
4287 macro_build_jalr (expressionS *ep)
4291 if (MIPS_JALR_HINT_P (ep))
4296 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4297 if (MIPS_JALR_HINT_P (ep))
4298 fix_new_exp (frag_now, f - frag_now->fr_literal,
4299 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4303 * Generate a "lui" instruction.
4306 macro_build_lui (expressionS *ep, int regnum)
4308 expressionS high_expr;
4309 const struct mips_opcode *mo;
4310 struct mips_cl_insn insn;
4311 bfd_reloc_code_real_type r[3]
4312 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4313 const char *name = "lui";
4314 const char *fmt = "t,u";
4316 gas_assert (! mips_opts.mips16);
4320 if (high_expr.X_op == O_constant)
4322 /* We can compute the instruction now without a relocation entry. */
4323 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4325 *r = BFD_RELOC_UNUSED;
4329 gas_assert (ep->X_op == O_symbol);
4330 /* _gp_disp is a special case, used from s_cpload.
4331 __gnu_local_gp is used if mips_no_shared. */
4332 gas_assert (mips_pic == NO_PIC
4334 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4335 || (! mips_in_shared
4336 && strcmp (S_GET_NAME (ep->X_add_symbol),
4337 "__gnu_local_gp") == 0));
4338 *r = BFD_RELOC_HI16_S;
4341 mo = hash_find (op_hash, name);
4342 gas_assert (strcmp (name, mo->name) == 0);
4343 gas_assert (strcmp (fmt, mo->args) == 0);
4344 create_insn (&insn, mo);
4346 insn.insn_opcode = insn.insn_mo->match;
4347 INSERT_OPERAND (RT, insn, regnum);
4348 if (*r == BFD_RELOC_UNUSED)
4350 insn.insn_opcode |= high_expr.X_add_number;
4351 append_insn (&insn, NULL, r);
4354 append_insn (&insn, &high_expr, r);
4357 /* Generate a sequence of instructions to do a load or store from a constant
4358 offset off of a base register (breg) into/from a target register (treg),
4359 using AT if necessary. */
4361 macro_build_ldst_constoffset (expressionS *ep, const char *op,
4362 int treg, int breg, int dbl)
4364 gas_assert (ep->X_op == O_constant);
4366 /* Sign-extending 32-bit constants makes their handling easier. */
4368 normalize_constant_expr (ep);
4370 /* Right now, this routine can only handle signed 32-bit constants. */
4371 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4372 as_warn (_("operand overflow"));
4374 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4376 /* Signed 16-bit offset will fit in the op. Easy! */
4377 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4381 /* 32-bit offset, need multiple instructions and AT, like:
4382 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4383 addu $tempreg,$tempreg,$breg
4384 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4385 to handle the complete offset. */
4386 macro_build_lui (ep, AT);
4387 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4388 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4391 as_bad (_("Macro used $at after \".set noat\""));
4396 * Generates code to set the $at register to true (one)
4397 * if reg is less than the immediate expression.
4400 set_at (int reg, int unsignedp)
4402 if (imm_expr.X_op == O_constant
4403 && imm_expr.X_add_number >= -0x8000
4404 && imm_expr.X_add_number < 0x8000)
4405 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4406 AT, reg, BFD_RELOC_LO16);
4409 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4410 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4414 /* Warn if an expression is not a constant. */
4417 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4419 if (ex->X_op == O_big)
4420 as_bad (_("unsupported large constant"));
4421 else if (ex->X_op != O_constant)
4422 as_bad (_("Instruction %s requires absolute expression"),
4425 if (HAVE_32BIT_GPRS)
4426 normalize_constant_expr (ex);
4429 /* Count the leading zeroes by performing a binary chop. This is a
4430 bulky bit of source, but performance is a LOT better for the
4431 majority of values than a simple loop to count the bits:
4432 for (lcnt = 0; (lcnt < 32); lcnt++)
4433 if ((v) & (1 << (31 - lcnt)))
4435 However it is not code size friendly, and the gain will drop a bit
4436 on certain cached systems.
4438 #define COUNT_TOP_ZEROES(v) \
4439 (((v) & ~0xffff) == 0 \
4440 ? ((v) & ~0xff) == 0 \
4441 ? ((v) & ~0xf) == 0 \
4442 ? ((v) & ~0x3) == 0 \
4443 ? ((v) & ~0x1) == 0 \
4448 : ((v) & ~0x7) == 0 \
4451 : ((v) & ~0x3f) == 0 \
4452 ? ((v) & ~0x1f) == 0 \
4455 : ((v) & ~0x7f) == 0 \
4458 : ((v) & ~0xfff) == 0 \
4459 ? ((v) & ~0x3ff) == 0 \
4460 ? ((v) & ~0x1ff) == 0 \
4463 : ((v) & ~0x7ff) == 0 \
4466 : ((v) & ~0x3fff) == 0 \
4467 ? ((v) & ~0x1fff) == 0 \
4470 : ((v) & ~0x7fff) == 0 \
4473 : ((v) & ~0xffffff) == 0 \
4474 ? ((v) & ~0xfffff) == 0 \
4475 ? ((v) & ~0x3ffff) == 0 \
4476 ? ((v) & ~0x1ffff) == 0 \
4479 : ((v) & ~0x7ffff) == 0 \
4482 : ((v) & ~0x3fffff) == 0 \
4483 ? ((v) & ~0x1fffff) == 0 \
4486 : ((v) & ~0x7fffff) == 0 \
4489 : ((v) & ~0xfffffff) == 0 \
4490 ? ((v) & ~0x3ffffff) == 0 \
4491 ? ((v) & ~0x1ffffff) == 0 \
4494 : ((v) & ~0x7ffffff) == 0 \
4497 : ((v) & ~0x3fffffff) == 0 \
4498 ? ((v) & ~0x1fffffff) == 0 \
4501 : ((v) & ~0x7fffffff) == 0 \
4506 * This routine generates the least number of instructions necessary to load
4507 * an absolute expression value into a register.
4510 load_register (int reg, expressionS *ep, int dbl)
4513 expressionS hi32, lo32;
4515 if (ep->X_op != O_big)
4517 gas_assert (ep->X_op == O_constant);
4519 /* Sign-extending 32-bit constants makes their handling easier. */
4521 normalize_constant_expr (ep);
4523 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4525 /* We can handle 16 bit signed values with an addiu to
4526 $zero. No need to ever use daddiu here, since $zero and
4527 the result are always correct in 32 bit mode. */
4528 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4531 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4533 /* We can handle 16 bit unsigned values with an ori to
4535 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4538 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4540 /* 32 bit values require an lui. */
4541 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4542 if ((ep->X_add_number & 0xffff) != 0)
4543 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4548 /* The value is larger than 32 bits. */
4550 if (!dbl || HAVE_32BIT_GPRS)
4554 sprintf_vma (value, ep->X_add_number);
4555 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4556 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4560 if (ep->X_op != O_big)
4563 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4564 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4565 hi32.X_add_number &= 0xffffffff;
4567 lo32.X_add_number &= 0xffffffff;
4571 gas_assert (ep->X_add_number > 2);
4572 if (ep->X_add_number == 3)
4573 generic_bignum[3] = 0;
4574 else if (ep->X_add_number > 4)
4575 as_bad (_("Number larger than 64 bits"));
4576 lo32.X_op = O_constant;
4577 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4578 hi32.X_op = O_constant;
4579 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4582 if (hi32.X_add_number == 0)
4587 unsigned long hi, lo;
4589 if (hi32.X_add_number == (offsetT) 0xffffffff)
4591 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4593 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4596 if (lo32.X_add_number & 0x80000000)
4598 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4599 if (lo32.X_add_number & 0xffff)
4600 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4605 /* Check for 16bit shifted constant. We know that hi32 is
4606 non-zero, so start the mask on the first bit of the hi32
4611 unsigned long himask, lomask;
4615 himask = 0xffff >> (32 - shift);
4616 lomask = (0xffff << shift) & 0xffffffff;
4620 himask = 0xffff << (shift - 32);
4623 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4624 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4628 tmp.X_op = O_constant;
4630 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4631 | (lo32.X_add_number >> shift));
4633 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4634 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4635 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4636 reg, reg, (shift >= 32) ? shift - 32 : shift);
4641 while (shift <= (64 - 16));
4643 /* Find the bit number of the lowest one bit, and store the
4644 shifted value in hi/lo. */
4645 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4646 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4650 while ((lo & 1) == 0)
4655 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4661 while ((hi & 1) == 0)
4670 /* Optimize if the shifted value is a (power of 2) - 1. */
4671 if ((hi == 0 && ((lo + 1) & lo) == 0)
4672 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4674 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4679 /* This instruction will set the register to be all
4681 tmp.X_op = O_constant;
4682 tmp.X_add_number = (offsetT) -1;
4683 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4687 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4688 reg, reg, (bit >= 32) ? bit - 32 : bit);
4690 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4691 reg, reg, (shift >= 32) ? shift - 32 : shift);
4696 /* Sign extend hi32 before calling load_register, because we can
4697 generally get better code when we load a sign extended value. */
4698 if ((hi32.X_add_number & 0x80000000) != 0)
4699 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4700 load_register (reg, &hi32, 0);
4703 if ((lo32.X_add_number & 0xffff0000) == 0)
4707 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4715 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4717 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4718 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4724 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4728 mid16.X_add_number >>= 16;
4729 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4730 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4733 if ((lo32.X_add_number & 0xffff) != 0)
4734 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4738 load_delay_nop (void)
4740 if (!gpr_interlocks)
4741 macro_build (NULL, "nop", "");
4744 /* Load an address into a register. */
4747 load_address (int reg, expressionS *ep, int *used_at)
4749 if (ep->X_op != O_constant
4750 && ep->X_op != O_symbol)
4752 as_bad (_("expression too complex"));
4753 ep->X_op = O_constant;
4756 if (ep->X_op == O_constant)
4758 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4762 if (mips_pic == NO_PIC)
4764 /* If this is a reference to a GP relative symbol, we want
4765 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4767 lui $reg,<sym> (BFD_RELOC_HI16_S)
4768 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4769 If we have an addend, we always use the latter form.
4771 With 64bit address space and a usable $at we want
4772 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4773 lui $at,<sym> (BFD_RELOC_HI16_S)
4774 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4775 daddiu $at,<sym> (BFD_RELOC_LO16)
4779 If $at is already in use, we use a path which is suboptimal
4780 on superscalar processors.
4781 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4782 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4784 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4786 daddiu $reg,<sym> (BFD_RELOC_LO16)
4788 For GP relative symbols in 64bit address space we can use
4789 the same sequence as in 32bit address space. */
4790 if (HAVE_64BIT_SYMBOLS)
4792 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4793 && !nopic_need_relax (ep->X_add_symbol, 1))
4795 relax_start (ep->X_add_symbol);
4796 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4797 mips_gp_register, BFD_RELOC_GPREL16);
4801 if (*used_at == 0 && mips_opts.at)
4803 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4804 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4805 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4806 BFD_RELOC_MIPS_HIGHER);
4807 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4808 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4809 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4814 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4815 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4816 BFD_RELOC_MIPS_HIGHER);
4817 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4818 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4819 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4820 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4823 if (mips_relax.sequence)
4828 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4829 && !nopic_need_relax (ep->X_add_symbol, 1))
4831 relax_start (ep->X_add_symbol);
4832 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4833 mips_gp_register, BFD_RELOC_GPREL16);
4836 macro_build_lui (ep, reg);
4837 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4838 reg, reg, BFD_RELOC_LO16);
4839 if (mips_relax.sequence)
4843 else if (!mips_big_got)
4847 /* If this is a reference to an external symbol, we want
4848 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4852 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4853 If there is a constant, it must be added in after.
4855 If we have NewABI, we want
4856 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4857 unless we're referencing a global symbol with a non-zero
4858 offset, in which case cst must be added separately. */
4861 if (ep->X_add_number)
4863 ex.X_add_number = ep->X_add_number;
4864 ep->X_add_number = 0;
4865 relax_start (ep->X_add_symbol);
4866 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4867 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4868 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4869 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4870 ex.X_op = O_constant;
4871 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4872 reg, reg, BFD_RELOC_LO16);
4873 ep->X_add_number = ex.X_add_number;
4876 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4877 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4878 if (mips_relax.sequence)
4883 ex.X_add_number = ep->X_add_number;
4884 ep->X_add_number = 0;
4885 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4886 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4888 relax_start (ep->X_add_symbol);
4890 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4894 if (ex.X_add_number != 0)
4896 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4897 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4898 ex.X_op = O_constant;
4899 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4900 reg, reg, BFD_RELOC_LO16);
4904 else if (mips_big_got)
4908 /* This is the large GOT case. If this is a reference to an
4909 external symbol, we want
4910 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4912 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4914 Otherwise, for a reference to a local symbol in old ABI, we want
4915 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4917 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4918 If there is a constant, it must be added in after.
4920 In the NewABI, for local symbols, with or without offsets, we want:
4921 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4922 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4926 ex.X_add_number = ep->X_add_number;
4927 ep->X_add_number = 0;
4928 relax_start (ep->X_add_symbol);
4929 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4930 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4931 reg, reg, mips_gp_register);
4932 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4933 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4934 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4935 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4936 else if (ex.X_add_number)
4938 ex.X_op = O_constant;
4939 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4943 ep->X_add_number = ex.X_add_number;
4945 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4946 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4947 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4948 BFD_RELOC_MIPS_GOT_OFST);
4953 ex.X_add_number = ep->X_add_number;
4954 ep->X_add_number = 0;
4955 relax_start (ep->X_add_symbol);
4956 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4957 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4958 reg, reg, mips_gp_register);
4959 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4960 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4962 if (reg_needs_delay (mips_gp_register))
4964 /* We need a nop before loading from $gp. This special
4965 check is required because the lui which starts the main
4966 instruction stream does not refer to $gp, and so will not
4967 insert the nop which may be required. */
4968 macro_build (NULL, "nop", "");
4970 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4971 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4973 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4977 if (ex.X_add_number != 0)
4979 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4980 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4981 ex.X_op = O_constant;
4982 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4990 if (!mips_opts.at && *used_at == 1)
4991 as_bad (_("Macro used $at after \".set noat\""));
4994 /* Move the contents of register SOURCE into register DEST. */
4997 move_register (int dest, int source)
4999 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5003 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5004 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5005 The two alternatives are:
5007 Global symbol Local sybmol
5008 ------------- ------------
5009 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5011 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5013 load_got_offset emits the first instruction and add_got_offset
5014 emits the second for a 16-bit offset or add_got_offset_hilo emits
5015 a sequence to add a 32-bit offset using a scratch register. */
5018 load_got_offset (int dest, expressionS *local)
5023 global.X_add_number = 0;
5025 relax_start (local->X_add_symbol);
5026 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5027 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5029 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5030 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5035 add_got_offset (int dest, expressionS *local)
5039 global.X_op = O_constant;
5040 global.X_op_symbol = NULL;
5041 global.X_add_symbol = NULL;
5042 global.X_add_number = local->X_add_number;
5044 relax_start (local->X_add_symbol);
5045 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5046 dest, dest, BFD_RELOC_LO16);
5048 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5053 add_got_offset_hilo (int dest, expressionS *local, int tmp)
5056 int hold_mips_optimize;
5058 global.X_op = O_constant;
5059 global.X_op_symbol = NULL;
5060 global.X_add_symbol = NULL;
5061 global.X_add_number = local->X_add_number;
5063 relax_start (local->X_add_symbol);
5064 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5066 /* Set mips_optimize around the lui instruction to avoid
5067 inserting an unnecessary nop after the lw. */
5068 hold_mips_optimize = mips_optimize;
5070 macro_build_lui (&global, tmp);
5071 mips_optimize = hold_mips_optimize;
5072 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5080 * This routine implements the seemingly endless macro or synthesized
5081 * instructions and addressing modes in the mips assembly language. Many
5082 * of these macros are simple and are similar to each other. These could
5083 * probably be handled by some kind of table or grammar approach instead of
5084 * this verbose method. Others are not simple macros but are more like
5085 * optimizing code generation.
5086 * One interesting optimization is when several store macros appear
5087 * consecutively that would load AT with the upper half of the same address.
5088 * The ensuing load upper instructions are ommited. This implies some kind
5089 * of global optimization. We currently only optimize within a single macro.
5090 * For many of the load and store macros if the address is specified as a
5091 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5092 * first load register 'at' with zero and use it as the base register. The
5093 * mips assembler simply uses register $zero. Just one tiny optimization
5097 macro (struct mips_cl_insn *ip)
5099 unsigned int treg, sreg, dreg, breg;
5100 unsigned int tempreg;
5115 bfd_reloc_code_real_type r;
5116 int hold_mips_optimize;
5118 gas_assert (! mips_opts.mips16);
5120 treg = EXTRACT_OPERAND (RT, *ip);
5121 dreg = EXTRACT_OPERAND (RD, *ip);
5122 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5123 mask = ip->insn_mo->mask;
5125 expr1.X_op = O_constant;
5126 expr1.X_op_symbol = NULL;
5127 expr1.X_add_symbol = NULL;
5128 expr1.X_add_number = 1;
5142 expr1.X_add_number = 8;
5143 macro_build (&expr1, "bgez", "s,p", sreg);
5145 macro_build (NULL, "nop", "");
5147 move_register (dreg, sreg);
5148 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5171 if (imm_expr.X_op == O_constant
5172 && imm_expr.X_add_number >= -0x8000
5173 && imm_expr.X_add_number < 0x8000)
5175 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5179 load_register (AT, &imm_expr, dbl);
5180 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5199 if (imm_expr.X_op == O_constant
5200 && imm_expr.X_add_number >= 0
5201 && imm_expr.X_add_number < 0x10000)
5203 if (mask != M_NOR_I)
5204 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5207 macro_build (&imm_expr, "ori", "t,r,i",
5208 treg, sreg, BFD_RELOC_LO16);
5209 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5215 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5216 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5220 switch (imm_expr.X_add_number)
5223 macro_build (NULL, "nop", "");
5226 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5229 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5230 (int) imm_expr.X_add_number);
5249 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5251 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5255 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5256 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5264 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5269 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5273 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5274 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5280 /* Check for > max integer. */
5281 maxnum = 0x7fffffff;
5282 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5289 if (imm_expr.X_op == O_constant
5290 && imm_expr.X_add_number >= maxnum
5291 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5294 /* Result is always false. */
5296 macro_build (NULL, "nop", "");
5298 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5301 if (imm_expr.X_op != O_constant)
5302 as_bad (_("Unsupported large constant"));
5303 ++imm_expr.X_add_number;
5307 if (mask == M_BGEL_I)
5309 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5311 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5314 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5316 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5319 maxnum = 0x7fffffff;
5320 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5327 maxnum = - maxnum - 1;
5328 if (imm_expr.X_op == O_constant
5329 && imm_expr.X_add_number <= maxnum
5330 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5333 /* result is always true */
5334 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5335 macro_build (&offset_expr, "b", "p");
5340 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5350 macro_build (&offset_expr, likely ? "beql" : "beq",
5351 "s,t,p", ZERO, treg);
5355 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5356 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5364 && imm_expr.X_op == O_constant
5365 && imm_expr.X_add_number == -1))
5367 if (imm_expr.X_op != O_constant)
5368 as_bad (_("Unsupported large constant"));
5369 ++imm_expr.X_add_number;
5373 if (mask == M_BGEUL_I)
5375 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5377 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5379 macro_build (&offset_expr, likely ? "bnel" : "bne",
5380 "s,t,p", sreg, ZERO);
5385 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5393 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5398 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5402 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5403 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5411 macro_build (&offset_expr, likely ? "bnel" : "bne",
5412 "s,t,p", sreg, ZERO);
5418 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5419 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5427 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5432 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5436 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5437 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5443 maxnum = 0x7fffffff;
5444 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5451 if (imm_expr.X_op == O_constant
5452 && imm_expr.X_add_number >= maxnum
5453 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5455 if (imm_expr.X_op != O_constant)
5456 as_bad (_("Unsupported large constant"));
5457 ++imm_expr.X_add_number;
5461 if (mask == M_BLTL_I)
5463 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5465 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5468 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5470 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5475 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5483 macro_build (&offset_expr, likely ? "beql" : "beq",
5484 "s,t,p", sreg, ZERO);
5490 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5491 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5499 && imm_expr.X_op == O_constant
5500 && imm_expr.X_add_number == -1))
5502 if (imm_expr.X_op != O_constant)
5503 as_bad (_("Unsupported large constant"));
5504 ++imm_expr.X_add_number;
5508 if (mask == M_BLTUL_I)
5510 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5512 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5514 macro_build (&offset_expr, likely ? "beql" : "beq",
5515 "s,t,p", sreg, ZERO);
5520 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5528 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5533 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5537 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5538 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5548 macro_build (&offset_expr, likely ? "bnel" : "bne",
5549 "s,t,p", ZERO, treg);
5553 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5554 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5559 /* Use unsigned arithmetic. */
5563 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5565 as_bad (_("Unsupported large constant"));
5570 pos = imm_expr.X_add_number;
5571 size = imm2_expr.X_add_number;
5576 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5579 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5581 as_bad (_("Improper extract size (%lu, position %lu)"),
5582 (unsigned long) size, (unsigned long) pos);
5586 if (size <= 32 && pos < 32)
5591 else if (size <= 32)
5601 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5608 /* Use unsigned arithmetic. */
5612 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5614 as_bad (_("Unsupported large constant"));
5619 pos = imm_expr.X_add_number;
5620 size = imm2_expr.X_add_number;
5625 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5628 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5630 as_bad (_("Improper insert size (%lu, position %lu)"),
5631 (unsigned long) size, (unsigned long) pos);
5635 if (pos < 32 && (pos + size - 1) < 32)
5650 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5651 (int) (pos + size - 1));
5667 as_warn (_("Divide by zero."));
5669 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5671 macro_build (NULL, "break", "c", 7);
5678 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5679 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5683 expr1.X_add_number = 8;
5684 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5685 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5686 macro_build (NULL, "break", "c", 7);
5688 expr1.X_add_number = -1;
5690 load_register (AT, &expr1, dbl);
5691 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5692 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5695 expr1.X_add_number = 1;
5696 load_register (AT, &expr1, dbl);
5697 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5701 expr1.X_add_number = 0x80000000;
5702 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5706 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5707 /* We want to close the noreorder block as soon as possible, so
5708 that later insns are available for delay slot filling. */
5713 expr1.X_add_number = 8;
5714 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5715 macro_build (NULL, "nop", "");
5717 /* We want to close the noreorder block as soon as possible, so
5718 that later insns are available for delay slot filling. */
5721 macro_build (NULL, "break", "c", 6);
5723 macro_build (NULL, s, "d", dreg);
5762 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5764 as_warn (_("Divide by zero."));
5766 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5768 macro_build (NULL, "break", "c", 7);
5771 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5773 if (strcmp (s2, "mflo") == 0)
5774 move_register (dreg, sreg);
5776 move_register (dreg, ZERO);
5779 if (imm_expr.X_op == O_constant
5780 && imm_expr.X_add_number == -1
5781 && s[strlen (s) - 1] != 'u')
5783 if (strcmp (s2, "mflo") == 0)
5785 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5788 move_register (dreg, ZERO);
5793 load_register (AT, &imm_expr, dbl);
5794 macro_build (NULL, s, "z,s,t", sreg, AT);
5795 macro_build (NULL, s2, "d", dreg);
5817 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5818 macro_build (NULL, s, "z,s,t", sreg, treg);
5819 /* We want to close the noreorder block as soon as possible, so
5820 that later insns are available for delay slot filling. */
5825 expr1.X_add_number = 8;
5826 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5827 macro_build (NULL, s, "z,s,t", sreg, treg);
5829 /* We want to close the noreorder block as soon as possible, so
5830 that later insns are available for delay slot filling. */
5832 macro_build (NULL, "break", "c", 7);
5834 macro_build (NULL, s2, "d", dreg);
5846 /* Load the address of a symbol into a register. If breg is not
5847 zero, we then add a base register to it. */
5849 if (dbl && HAVE_32BIT_GPRS)
5850 as_warn (_("dla used to load 32-bit register"));
5852 if (!dbl && HAVE_64BIT_OBJECTS)
5853 as_warn (_("la used to load 64-bit address"));
5855 if (offset_expr.X_op == O_constant
5856 && offset_expr.X_add_number >= -0x8000
5857 && offset_expr.X_add_number < 0x8000)
5859 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5860 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5864 if (mips_opts.at && (treg == breg))
5874 if (offset_expr.X_op != O_symbol
5875 && offset_expr.X_op != O_constant)
5877 as_bad (_("Expression too complex"));
5878 offset_expr.X_op = O_constant;
5881 if (offset_expr.X_op == O_constant)
5882 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5883 else if (mips_pic == NO_PIC)
5885 /* If this is a reference to a GP relative symbol, we want
5886 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5888 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5889 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5890 If we have a constant, we need two instructions anyhow,
5891 so we may as well always use the latter form.
5893 With 64bit address space and a usable $at we want
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5895 lui $at,<sym> (BFD_RELOC_HI16_S)
5896 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5897 daddiu $at,<sym> (BFD_RELOC_LO16)
5899 daddu $tempreg,$tempreg,$at
5901 If $at is already in use, we use a path which is suboptimal
5902 on superscalar processors.
5903 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5904 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5906 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5908 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5910 For GP relative symbols in 64bit address space we can use
5911 the same sequence as in 32bit address space. */
5912 if (HAVE_64BIT_SYMBOLS)
5914 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5915 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5917 relax_start (offset_expr.X_add_symbol);
5918 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5919 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5923 if (used_at == 0 && mips_opts.at)
5925 macro_build (&offset_expr, "lui", "t,u",
5926 tempreg, BFD_RELOC_MIPS_HIGHEST);
5927 macro_build (&offset_expr, "lui", "t,u",
5928 AT, BFD_RELOC_HI16_S);
5929 macro_build (&offset_expr, "daddiu", "t,r,j",
5930 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5931 macro_build (&offset_expr, "daddiu", "t,r,j",
5932 AT, AT, BFD_RELOC_LO16);
5933 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5934 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5939 macro_build (&offset_expr, "lui", "t,u",
5940 tempreg, BFD_RELOC_MIPS_HIGHEST);
5941 macro_build (&offset_expr, "daddiu", "t,r,j",
5942 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5943 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5944 macro_build (&offset_expr, "daddiu", "t,r,j",
5945 tempreg, tempreg, BFD_RELOC_HI16_S);
5946 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5947 macro_build (&offset_expr, "daddiu", "t,r,j",
5948 tempreg, tempreg, BFD_RELOC_LO16);
5951 if (mips_relax.sequence)
5956 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5957 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5959 relax_start (offset_expr.X_add_symbol);
5960 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5961 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5964 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5965 as_bad (_("Offset too large"));
5966 macro_build_lui (&offset_expr, tempreg);
5967 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5968 tempreg, tempreg, BFD_RELOC_LO16);
5969 if (mips_relax.sequence)
5973 else if (!mips_big_got && !HAVE_NEWABI)
5975 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5977 /* If this is a reference to an external symbol, and there
5978 is no constant, we want
5979 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5980 or for lca or if tempreg is PIC_CALL_REG
5981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5982 For a local symbol, we want
5983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5985 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5987 If we have a small constant, and this is a reference to
5988 an external symbol, we want
5989 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5991 addiu $tempreg,$tempreg,<constant>
5992 For a local symbol, we want the same instruction
5993 sequence, but we output a BFD_RELOC_LO16 reloc on the
5996 If we have a large constant, and this is a reference to
5997 an external symbol, we want
5998 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5999 lui $at,<hiconstant>
6000 addiu $at,$at,<loconstant>
6001 addu $tempreg,$tempreg,$at
6002 For a local symbol, we want the same instruction
6003 sequence, but we output a BFD_RELOC_LO16 reloc on the
6007 if (offset_expr.X_add_number == 0)
6009 if (mips_pic == SVR4_PIC
6011 && (call || tempreg == PIC_CALL_REG))
6012 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
6014 relax_start (offset_expr.X_add_symbol);
6015 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6016 lw_reloc_type, mips_gp_register);
6019 /* We're going to put in an addu instruction using
6020 tempreg, so we may as well insert the nop right
6025 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6026 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6028 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6029 tempreg, tempreg, BFD_RELOC_LO16);
6031 /* FIXME: If breg == 0, and the next instruction uses
6032 $tempreg, then if this variant case is used an extra
6033 nop will be generated. */
6035 else if (offset_expr.X_add_number >= -0x8000
6036 && offset_expr.X_add_number < 0x8000)
6038 load_got_offset (tempreg, &offset_expr);
6040 add_got_offset (tempreg, &offset_expr);
6044 expr1.X_add_number = offset_expr.X_add_number;
6045 offset_expr.X_add_number =
6046 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6047 load_got_offset (tempreg, &offset_expr);
6048 offset_expr.X_add_number = expr1.X_add_number;
6049 /* If we are going to add in a base register, and the
6050 target register and the base register are the same,
6051 then we are using AT as a temporary register. Since
6052 we want to load the constant into AT, we add our
6053 current AT (from the global offset table) and the
6054 register into the register now, and pretend we were
6055 not using a base register. */
6059 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6064 add_got_offset_hilo (tempreg, &offset_expr, AT);
6068 else if (!mips_big_got && HAVE_NEWABI)
6070 int add_breg_early = 0;
6072 /* If this is a reference to an external, and there is no
6073 constant, or local symbol (*), with or without a
6075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6076 or for lca or if tempreg is PIC_CALL_REG
6077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6079 If we have a small constant, and this is a reference to
6080 an external symbol, we want
6081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6082 addiu $tempreg,$tempreg,<constant>
6084 If we have a large constant, and this is a reference to
6085 an external symbol, we want
6086 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6087 lui $at,<hiconstant>
6088 addiu $at,$at,<loconstant>
6089 addu $tempreg,$tempreg,$at
6091 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6092 local symbols, even though it introduces an additional
6095 if (offset_expr.X_add_number)
6097 expr1.X_add_number = offset_expr.X_add_number;
6098 offset_expr.X_add_number = 0;
6100 relax_start (offset_expr.X_add_symbol);
6101 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6102 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6104 if (expr1.X_add_number >= -0x8000
6105 && expr1.X_add_number < 0x8000)
6107 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6108 tempreg, tempreg, BFD_RELOC_LO16);
6110 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6112 /* If we are going to add in a base register, and the
6113 target register and the base register are the same,
6114 then we are using AT as a temporary register. Since
6115 we want to load the constant into AT, we add our
6116 current AT (from the global offset table) and the
6117 register into the register now, and pretend we were
6118 not using a base register. */
6123 gas_assert (tempreg == AT);
6124 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6130 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6131 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6137 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6140 offset_expr.X_add_number = expr1.X_add_number;
6142 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6143 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6146 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6147 treg, tempreg, breg);
6153 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6155 relax_start (offset_expr.X_add_symbol);
6156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6157 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6159 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6160 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6165 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6166 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6169 else if (mips_big_got && !HAVE_NEWABI)
6172 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6173 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6174 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6176 /* This is the large GOT case. If this is a reference to an
6177 external symbol, and there is no constant, we want
6178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6179 addu $tempreg,$tempreg,$gp
6180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6181 or for lca or if tempreg is PIC_CALL_REG
6182 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6183 addu $tempreg,$tempreg,$gp
6184 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6185 For a local symbol, we want
6186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6190 If we have a small constant, and this is a reference to
6191 an external symbol, we want
6192 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6193 addu $tempreg,$tempreg,$gp
6194 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6196 addiu $tempreg,$tempreg,<constant>
6197 For a local symbol, we want
6198 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6200 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6202 If we have a large constant, and this is a reference to
6203 an external symbol, we want
6204 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6205 addu $tempreg,$tempreg,$gp
6206 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6207 lui $at,<hiconstant>
6208 addiu $at,$at,<loconstant>
6209 addu $tempreg,$tempreg,$at
6210 For a local symbol, we want
6211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6212 lui $at,<hiconstant>
6213 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6214 addu $tempreg,$tempreg,$at
6217 expr1.X_add_number = offset_expr.X_add_number;
6218 offset_expr.X_add_number = 0;
6219 relax_start (offset_expr.X_add_symbol);
6220 gpdelay = reg_needs_delay (mips_gp_register);
6221 if (expr1.X_add_number == 0 && breg == 0
6222 && (call || tempreg == PIC_CALL_REG))
6224 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6225 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6227 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6228 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6229 tempreg, tempreg, mips_gp_register);
6230 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6231 tempreg, lw_reloc_type, tempreg);
6232 if (expr1.X_add_number == 0)
6236 /* We're going to put in an addu instruction using
6237 tempreg, so we may as well insert the nop right
6242 else if (expr1.X_add_number >= -0x8000
6243 && expr1.X_add_number < 0x8000)
6246 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6247 tempreg, tempreg, BFD_RELOC_LO16);
6251 /* If we are going to add in a base register, and the
6252 target register and the base register are the same,
6253 then we are using AT as a temporary register. Since
6254 we want to load the constant into AT, we add our
6255 current AT (from the global offset table) and the
6256 register into the register now, and pretend we were
6257 not using a base register. */
6262 gas_assert (tempreg == AT);
6264 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6269 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6270 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6274 offset_expr.X_add_number =
6275 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6280 /* This is needed because this instruction uses $gp, but
6281 the first instruction on the main stream does not. */
6282 macro_build (NULL, "nop", "");
6285 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6286 local_reloc_type, mips_gp_register);
6287 if (expr1.X_add_number >= -0x8000
6288 && expr1.X_add_number < 0x8000)
6291 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6292 tempreg, tempreg, BFD_RELOC_LO16);
6293 /* FIXME: If add_number is 0, and there was no base
6294 register, the external symbol case ended with a load,
6295 so if the symbol turns out to not be external, and
6296 the next instruction uses tempreg, an unnecessary nop
6297 will be inserted. */
6303 /* We must add in the base register now, as in the
6304 external symbol case. */
6305 gas_assert (tempreg == AT);
6307 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6310 /* We set breg to 0 because we have arranged to add
6311 it in in both cases. */
6315 macro_build_lui (&expr1, AT);
6316 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6317 AT, AT, BFD_RELOC_LO16);
6318 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6319 tempreg, tempreg, AT);
6324 else if (mips_big_got && HAVE_NEWABI)
6326 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6327 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6328 int add_breg_early = 0;
6330 /* This is the large GOT case. If this is a reference to an
6331 external symbol, and there is no constant, we want
6332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6333 add $tempreg,$tempreg,$gp
6334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6335 or for lca or if tempreg is PIC_CALL_REG
6336 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6337 add $tempreg,$tempreg,$gp
6338 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6340 If we have a small constant, and this is a reference to
6341 an external symbol, we want
6342 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6343 add $tempreg,$tempreg,$gp
6344 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6345 addi $tempreg,$tempreg,<constant>
6347 If we have a large constant, and this is a reference to
6348 an external symbol, we want
6349 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6350 addu $tempreg,$tempreg,$gp
6351 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6352 lui $at,<hiconstant>
6353 addi $at,$at,<loconstant>
6354 add $tempreg,$tempreg,$at
6356 If we have NewABI, and we know it's a local symbol, we want
6357 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6358 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6359 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6361 relax_start (offset_expr.X_add_symbol);
6363 expr1.X_add_number = offset_expr.X_add_number;
6364 offset_expr.X_add_number = 0;
6366 if (expr1.X_add_number == 0 && breg == 0
6367 && (call || tempreg == PIC_CALL_REG))
6369 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6370 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6372 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6373 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6374 tempreg, tempreg, mips_gp_register);
6375 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6376 tempreg, lw_reloc_type, tempreg);
6378 if (expr1.X_add_number == 0)
6380 else if (expr1.X_add_number >= -0x8000
6381 && expr1.X_add_number < 0x8000)
6383 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6384 tempreg, tempreg, BFD_RELOC_LO16);
6386 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6388 /* If we are going to add in a base register, and the
6389 target register and the base register are the same,
6390 then we are using AT as a temporary register. Since
6391 we want to load the constant into AT, we add our
6392 current AT (from the global offset table) and the
6393 register into the register now, and pretend we were
6394 not using a base register. */
6399 gas_assert (tempreg == AT);
6400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6406 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6407 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6412 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6415 offset_expr.X_add_number = expr1.X_add_number;
6416 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6417 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6418 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6419 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6422 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6423 treg, tempreg, breg);
6433 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6438 unsigned long temp = (treg << 16) | (0x01);
6439 macro_build (NULL, "c2", "C", temp);
6445 unsigned long temp = (0x02);
6446 macro_build (NULL, "c2", "C", temp);
6452 unsigned long temp = (treg << 16) | (0x02);
6453 macro_build (NULL, "c2", "C", temp);
6458 macro_build (NULL, "c2", "C", 3);
6463 unsigned long temp = (treg << 16) | 0x03;
6464 macro_build (NULL, "c2", "C", temp);
6469 /* The j instruction may not be used in PIC code, since it
6470 requires an absolute address. We convert it to a b
6472 if (mips_pic == NO_PIC)
6473 macro_build (&offset_expr, "j", "a");
6475 macro_build (&offset_expr, "b", "p");
6478 /* The jal instructions must be handled as macros because when
6479 generating PIC code they expand to multi-instruction
6480 sequences. Normally they are simple instructions. */
6485 if (mips_pic == NO_PIC)
6486 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6489 if (sreg != PIC_CALL_REG)
6490 as_warn (_("MIPS PIC call to register other than $25"));
6492 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6493 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6495 if (mips_cprestore_offset < 0)
6496 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6499 if (!mips_frame_reg_valid)
6501 as_warn (_("No .frame pseudo-op used in PIC code"));
6502 /* Quiet this warning. */
6503 mips_frame_reg_valid = 1;
6505 if (!mips_cprestore_valid)
6507 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6508 /* Quiet this warning. */
6509 mips_cprestore_valid = 1;
6511 if (mips_opts.noreorder)
6512 macro_build (NULL, "nop", "");
6513 expr1.X_add_number = mips_cprestore_offset;
6514 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6517 HAVE_64BIT_ADDRESSES);
6525 if (mips_pic == NO_PIC)
6526 macro_build (&offset_expr, "jal", "a");
6527 else if (mips_pic == SVR4_PIC)
6529 /* If this is a reference to an external symbol, and we are
6530 using a small GOT, we want
6531 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6535 lw $gp,cprestore($sp)
6536 The cprestore value is set using the .cprestore
6537 pseudo-op. If we are using a big GOT, we want
6538 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6540 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6544 lw $gp,cprestore($sp)
6545 If the symbol is not external, we want
6546 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6548 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6551 lw $gp,cprestore($sp)
6553 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6554 sequences above, minus nops, unless the symbol is local,
6555 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6561 relax_start (offset_expr.X_add_symbol);
6562 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6563 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6566 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6567 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6573 relax_start (offset_expr.X_add_symbol);
6574 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6575 BFD_RELOC_MIPS_CALL_HI16);
6576 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6577 PIC_CALL_REG, mips_gp_register);
6578 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6579 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6582 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6583 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6585 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6586 PIC_CALL_REG, PIC_CALL_REG,
6587 BFD_RELOC_MIPS_GOT_OFST);
6591 macro_build_jalr (&offset_expr);
6595 relax_start (offset_expr.X_add_symbol);
6598 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6599 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6608 gpdelay = reg_needs_delay (mips_gp_register);
6609 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6610 BFD_RELOC_MIPS_CALL_HI16);
6611 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6612 PIC_CALL_REG, mips_gp_register);
6613 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6614 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6619 macro_build (NULL, "nop", "");
6621 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6622 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6625 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6626 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6628 macro_build_jalr (&offset_expr);
6630 if (mips_cprestore_offset < 0)
6631 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6634 if (!mips_frame_reg_valid)
6636 as_warn (_("No .frame pseudo-op used in PIC code"));
6637 /* Quiet this warning. */
6638 mips_frame_reg_valid = 1;
6640 if (!mips_cprestore_valid)
6642 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6643 /* Quiet this warning. */
6644 mips_cprestore_valid = 1;
6646 if (mips_opts.noreorder)
6647 macro_build (NULL, "nop", "");
6648 expr1.X_add_number = mips_cprestore_offset;
6649 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6652 HAVE_64BIT_ADDRESSES);
6656 else if (mips_pic == VXWORKS_PIC)
6657 as_bad (_("Non-PIC jump used in PIC library"));
6680 /* Itbl support may require additional care here. */
6685 /* Itbl support may require additional care here. */
6690 /* Itbl support may require additional care here. */
6695 /* Itbl support may require additional care here. */
6708 /* Itbl support may require additional care here. */
6713 /* Itbl support may require additional care here. */
6718 /* Itbl support may require additional care here. */
6738 if (breg == treg || coproc || lr)
6759 /* Itbl support may require additional care here. */
6764 /* Itbl support may require additional care here. */
6769 /* Itbl support may require additional care here. */
6774 /* Itbl support may require additional care here. */
6798 /* Itbl support may require additional care here. */
6802 /* Itbl support may require additional care here. */
6807 /* Itbl support may require additional care here. */
6820 && NO_ISA_COP (mips_opts.arch)
6821 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6823 as_bad (_("Opcode not supported on this processor: %s"),
6824 mips_cpu_info_from_arch (mips_opts.arch)->name);
6828 /* Itbl support may require additional care here. */
6829 if (mask == M_LWC1_AB
6830 || mask == M_SWC1_AB
6831 || mask == M_LDC1_AB
6832 || mask == M_SDC1_AB
6836 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6843 if (offset_expr.X_op != O_constant
6844 && offset_expr.X_op != O_symbol)
6846 as_bad (_("Expression too complex"));
6847 offset_expr.X_op = O_constant;
6850 if (HAVE_32BIT_ADDRESSES
6851 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6855 sprintf_vma (value, offset_expr.X_add_number);
6856 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6859 /* A constant expression in PIC code can be handled just as it
6860 is in non PIC code. */
6861 if (offset_expr.X_op == O_constant)
6863 expr1.X_add_number = offset_expr.X_add_number;
6864 normalize_address_expr (&expr1);
6865 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6867 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6868 & ~(bfd_vma) 0xffff);
6869 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6871 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6872 tempreg, tempreg, breg);
6875 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6877 else if (mips_pic == NO_PIC)
6879 /* If this is a reference to a GP relative symbol, and there
6880 is no base register, we want
6881 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6882 Otherwise, if there is no base register, we want
6883 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6884 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6885 If we have a constant, we need two instructions anyhow,
6886 so we always use the latter form.
6888 If we have a base register, and this is a reference to a
6889 GP relative symbol, we want
6890 addu $tempreg,$breg,$gp
6891 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6893 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6894 addu $tempreg,$tempreg,$breg
6895 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6896 With a constant we always use the latter case.
6898 With 64bit address space and no base register and $at usable,
6900 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6901 lui $at,<sym> (BFD_RELOC_HI16_S)
6902 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6905 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6906 If we have a base register, we want
6907 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6908 lui $at,<sym> (BFD_RELOC_HI16_S)
6909 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6913 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6915 Without $at we can't generate the optimal path for superscalar
6916 processors here since this would require two temporary registers.
6917 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6918 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6920 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6922 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6923 If we have a base register, we want
6924 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6925 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6927 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6929 daddu $tempreg,$tempreg,$breg
6930 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6932 For GP relative symbols in 64bit address space we can use
6933 the same sequence as in 32bit address space. */
6934 if (HAVE_64BIT_SYMBOLS)
6936 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6937 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6939 relax_start (offset_expr.X_add_symbol);
6942 macro_build (&offset_expr, s, fmt, treg,
6943 BFD_RELOC_GPREL16, mips_gp_register);
6947 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6948 tempreg, breg, mips_gp_register);
6949 macro_build (&offset_expr, s, fmt, treg,
6950 BFD_RELOC_GPREL16, tempreg);
6955 if (used_at == 0 && mips_opts.at)
6957 macro_build (&offset_expr, "lui", "t,u", tempreg,
6958 BFD_RELOC_MIPS_HIGHEST);
6959 macro_build (&offset_expr, "lui", "t,u", AT,
6961 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6962 tempreg, BFD_RELOC_MIPS_HIGHER);
6964 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6965 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6966 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6967 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6973 macro_build (&offset_expr, "lui", "t,u", tempreg,
6974 BFD_RELOC_MIPS_HIGHEST);
6975 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6976 tempreg, BFD_RELOC_MIPS_HIGHER);
6977 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6978 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6979 tempreg, BFD_RELOC_HI16_S);
6980 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6982 macro_build (NULL, "daddu", "d,v,t",
6983 tempreg, tempreg, breg);
6984 macro_build (&offset_expr, s, fmt, treg,
6985 BFD_RELOC_LO16, tempreg);
6988 if (mips_relax.sequence)
6995 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6996 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6998 relax_start (offset_expr.X_add_symbol);
6999 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
7003 macro_build_lui (&offset_expr, tempreg);
7004 macro_build (&offset_expr, s, fmt, treg,
7005 BFD_RELOC_LO16, tempreg);
7006 if (mips_relax.sequence)
7011 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7012 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7014 relax_start (offset_expr.X_add_symbol);
7015 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7016 tempreg, breg, mips_gp_register);
7017 macro_build (&offset_expr, s, fmt, treg,
7018 BFD_RELOC_GPREL16, tempreg);
7021 macro_build_lui (&offset_expr, tempreg);
7022 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7023 tempreg, tempreg, breg);
7024 macro_build (&offset_expr, s, fmt, treg,
7025 BFD_RELOC_LO16, tempreg);
7026 if (mips_relax.sequence)
7030 else if (!mips_big_got)
7032 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7034 /* If this is a reference to an external symbol, we want
7035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7037 <op> $treg,0($tempreg)
7039 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7041 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7042 <op> $treg,0($tempreg)
7045 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7046 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7048 If there is a base register, we add it to $tempreg before
7049 the <op>. If there is a constant, we stick it in the
7050 <op> instruction. We don't handle constants larger than
7051 16 bits, because we have no way to load the upper 16 bits
7052 (actually, we could handle them for the subset of cases
7053 in which we are not using $at). */
7054 gas_assert (offset_expr.X_op == O_symbol);
7057 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7058 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7060 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7061 tempreg, tempreg, breg);
7062 macro_build (&offset_expr, s, fmt, treg,
7063 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7066 expr1.X_add_number = offset_expr.X_add_number;
7067 offset_expr.X_add_number = 0;
7068 if (expr1.X_add_number < -0x8000
7069 || expr1.X_add_number >= 0x8000)
7070 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7071 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7072 lw_reloc_type, mips_gp_register);
7074 relax_start (offset_expr.X_add_symbol);
7076 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7077 tempreg, BFD_RELOC_LO16);
7080 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7081 tempreg, tempreg, breg);
7082 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7084 else if (mips_big_got && !HAVE_NEWABI)
7088 /* If this is a reference to an external symbol, we want
7089 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7090 addu $tempreg,$tempreg,$gp
7091 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7092 <op> $treg,0($tempreg)
7094 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7096 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7097 <op> $treg,0($tempreg)
7098 If there is a base register, we add it to $tempreg before
7099 the <op>. If there is a constant, we stick it in the
7100 <op> instruction. We don't handle constants larger than
7101 16 bits, because we have no way to load the upper 16 bits
7102 (actually, we could handle them for the subset of cases
7103 in which we are not using $at). */
7104 gas_assert (offset_expr.X_op == O_symbol);
7105 expr1.X_add_number = offset_expr.X_add_number;
7106 offset_expr.X_add_number = 0;
7107 if (expr1.X_add_number < -0x8000
7108 || expr1.X_add_number >= 0x8000)
7109 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7110 gpdelay = reg_needs_delay (mips_gp_register);
7111 relax_start (offset_expr.X_add_symbol);
7112 macro_build (&offset_expr, "lui", "t,u", tempreg,
7113 BFD_RELOC_MIPS_GOT_HI16);
7114 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7116 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7117 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7120 macro_build (NULL, "nop", "");
7121 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7122 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7124 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7125 tempreg, BFD_RELOC_LO16);
7129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7130 tempreg, tempreg, breg);
7131 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7133 else if (mips_big_got && HAVE_NEWABI)
7135 /* If this is a reference to an external symbol, we want
7136 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7137 add $tempreg,$tempreg,$gp
7138 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7139 <op> $treg,<ofst>($tempreg)
7140 Otherwise, for local symbols, we want:
7141 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7142 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7143 gas_assert (offset_expr.X_op == O_symbol);
7144 expr1.X_add_number = offset_expr.X_add_number;
7145 offset_expr.X_add_number = 0;
7146 if (expr1.X_add_number < -0x8000
7147 || expr1.X_add_number >= 0x8000)
7148 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7149 relax_start (offset_expr.X_add_symbol);
7150 macro_build (&offset_expr, "lui", "t,u", tempreg,
7151 BFD_RELOC_MIPS_GOT_HI16);
7152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7155 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7157 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7158 tempreg, tempreg, breg);
7159 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7162 offset_expr.X_add_number = expr1.X_add_number;
7163 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7164 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7166 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7167 tempreg, tempreg, breg);
7168 macro_build (&offset_expr, s, fmt, treg,
7169 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7179 load_register (treg, &imm_expr, 0);
7183 load_register (treg, &imm_expr, 1);
7187 if (imm_expr.X_op == O_constant)
7190 load_register (AT, &imm_expr, 0);
7191 macro_build (NULL, "mtc1", "t,G", AT, treg);
7196 gas_assert (offset_expr.X_op == O_symbol
7197 && strcmp (segment_name (S_GET_SEGMENT
7198 (offset_expr.X_add_symbol)),
7200 && offset_expr.X_add_number == 0);
7201 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7202 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7207 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7208 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7209 order 32 bits of the value and the low order 32 bits are either
7210 zero or in OFFSET_EXPR. */
7211 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7213 if (HAVE_64BIT_GPRS)
7214 load_register (treg, &imm_expr, 1);
7219 if (target_big_endian)
7231 load_register (hreg, &imm_expr, 0);
7234 if (offset_expr.X_op == O_absent)
7235 move_register (lreg, 0);
7238 gas_assert (offset_expr.X_op == O_constant);
7239 load_register (lreg, &offset_expr, 0);
7246 /* We know that sym is in the .rdata section. First we get the
7247 upper 16 bits of the address. */
7248 if (mips_pic == NO_PIC)
7250 macro_build_lui (&offset_expr, AT);
7255 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7256 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7260 /* Now we load the register(s). */
7261 if (HAVE_64BIT_GPRS)
7264 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7269 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7272 /* FIXME: How in the world do we deal with the possible
7274 offset_expr.X_add_number += 4;
7275 macro_build (&offset_expr, "lw", "t,o(b)",
7276 treg + 1, BFD_RELOC_LO16, AT);
7282 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7283 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7284 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7285 the value and the low order 32 bits are either zero or in
7287 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7290 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7291 if (HAVE_64BIT_FPRS)
7293 gas_assert (HAVE_64BIT_GPRS);
7294 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7298 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7299 if (offset_expr.X_op == O_absent)
7300 macro_build (NULL, "mtc1", "t,G", 0, treg);
7303 gas_assert (offset_expr.X_op == O_constant);
7304 load_register (AT, &offset_expr, 0);
7305 macro_build (NULL, "mtc1", "t,G", AT, treg);
7311 gas_assert (offset_expr.X_op == O_symbol
7312 && offset_expr.X_add_number == 0);
7313 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7314 if (strcmp (s, ".lit8") == 0)
7316 if (mips_opts.isa != ISA_MIPS1)
7318 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7319 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7322 breg = mips_gp_register;
7323 r = BFD_RELOC_MIPS_LITERAL;
7328 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7330 if (mips_pic != NO_PIC)
7331 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7332 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7335 /* FIXME: This won't work for a 64 bit address. */
7336 macro_build_lui (&offset_expr, AT);
7339 if (mips_opts.isa != ISA_MIPS1)
7341 macro_build (&offset_expr, "ldc1", "T,o(b)",
7342 treg, BFD_RELOC_LO16, AT);
7351 /* Even on a big endian machine $fn comes before $fn+1. We have
7352 to adjust when loading from memory. */
7355 gas_assert (mips_opts.isa == ISA_MIPS1);
7356 macro_build (&offset_expr, "lwc1", "T,o(b)",
7357 target_big_endian ? treg + 1 : treg, r, breg);
7358 /* FIXME: A possible overflow which I don't know how to deal
7360 offset_expr.X_add_number += 4;
7361 macro_build (&offset_expr, "lwc1", "T,o(b)",
7362 target_big_endian ? treg : treg + 1, r, breg);
7366 gas_assert (mips_opts.isa == ISA_MIPS1);
7367 /* Even on a big endian machine $fn comes before $fn+1. We have
7368 to adjust when storing to memory. */
7369 macro_build (&offset_expr, "swc1", "T,o(b)",
7370 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7371 offset_expr.X_add_number += 4;
7372 macro_build (&offset_expr, "swc1", "T,o(b)",
7373 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7378 * The MIPS assembler seems to check for X_add_number not
7379 * being double aligned and generating:
7382 * addiu at,at,%lo(foo+1)
7385 * But, the resulting address is the same after relocation so why
7386 * generate the extra instruction?
7388 /* Itbl support may require additional care here. */
7390 if (mips_opts.isa != ISA_MIPS1)
7401 if (mips_opts.isa != ISA_MIPS1)
7409 /* Itbl support may require additional care here. */
7414 if (HAVE_64BIT_GPRS)
7425 if (HAVE_64BIT_GPRS)
7435 if (offset_expr.X_op != O_symbol
7436 && offset_expr.X_op != O_constant)
7438 as_bad (_("Expression too complex"));
7439 offset_expr.X_op = O_constant;
7442 if (HAVE_32BIT_ADDRESSES
7443 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7447 sprintf_vma (value, offset_expr.X_add_number);
7448 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7451 /* Even on a big endian machine $fn comes before $fn+1. We have
7452 to adjust when loading from memory. We set coproc if we must
7453 load $fn+1 first. */
7454 /* Itbl support may require additional care here. */
7455 if (!target_big_endian)
7458 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7460 /* If this is a reference to a GP relative symbol, we want
7461 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7462 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7463 If we have a base register, we use this
7465 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7466 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7467 If this is not a GP relative symbol, we want
7468 lui $at,<sym> (BFD_RELOC_HI16_S)
7469 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7470 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7471 If there is a base register, we add it to $at after the
7472 lui instruction. If there is a constant, we always use
7474 if (offset_expr.X_op == O_symbol
7475 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7476 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7478 relax_start (offset_expr.X_add_symbol);
7481 tempreg = mips_gp_register;
7485 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7486 AT, breg, mips_gp_register);
7491 /* Itbl support may require additional care here. */
7492 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7493 BFD_RELOC_GPREL16, tempreg);
7494 offset_expr.X_add_number += 4;
7496 /* Set mips_optimize to 2 to avoid inserting an
7498 hold_mips_optimize = mips_optimize;
7500 /* Itbl support may require additional care here. */
7501 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7502 BFD_RELOC_GPREL16, tempreg);
7503 mips_optimize = hold_mips_optimize;
7507 offset_expr.X_add_number -= 4;
7510 macro_build_lui (&offset_expr, AT);
7512 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7513 /* Itbl support may require additional care here. */
7514 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7515 BFD_RELOC_LO16, AT);
7516 /* FIXME: How do we handle overflow here? */
7517 offset_expr.X_add_number += 4;
7518 /* Itbl support may require additional care here. */
7519 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7520 BFD_RELOC_LO16, AT);
7521 if (mips_relax.sequence)
7524 else if (!mips_big_got)
7526 /* If this is a reference to an external symbol, we want
7527 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7532 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7534 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7535 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7536 If there is a base register we add it to $at before the
7537 lwc1 instructions. If there is a constant we include it
7538 in the lwc1 instructions. */
7540 expr1.X_add_number = offset_expr.X_add_number;
7541 if (expr1.X_add_number < -0x8000
7542 || expr1.X_add_number >= 0x8000 - 4)
7543 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7544 load_got_offset (AT, &offset_expr);
7547 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7549 /* Set mips_optimize to 2 to avoid inserting an undesired
7551 hold_mips_optimize = mips_optimize;
7554 /* Itbl support may require additional care here. */
7555 relax_start (offset_expr.X_add_symbol);
7556 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7557 BFD_RELOC_LO16, AT);
7558 expr1.X_add_number += 4;
7559 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7560 BFD_RELOC_LO16, AT);
7562 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7563 BFD_RELOC_LO16, AT);
7564 offset_expr.X_add_number += 4;
7565 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7566 BFD_RELOC_LO16, AT);
7569 mips_optimize = hold_mips_optimize;
7571 else if (mips_big_got)
7575 /* If this is a reference to an external symbol, we want
7576 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7578 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7583 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7585 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7586 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7587 If there is a base register we add it to $at before the
7588 lwc1 instructions. If there is a constant we include it
7589 in the lwc1 instructions. */
7591 expr1.X_add_number = offset_expr.X_add_number;
7592 offset_expr.X_add_number = 0;
7593 if (expr1.X_add_number < -0x8000
7594 || expr1.X_add_number >= 0x8000 - 4)
7595 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7596 gpdelay = reg_needs_delay (mips_gp_register);
7597 relax_start (offset_expr.X_add_symbol);
7598 macro_build (&offset_expr, "lui", "t,u",
7599 AT, BFD_RELOC_MIPS_GOT_HI16);
7600 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7601 AT, AT, mips_gp_register);
7602 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7603 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7606 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7607 /* Itbl support may require additional care here. */
7608 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7609 BFD_RELOC_LO16, AT);
7610 expr1.X_add_number += 4;
7612 /* Set mips_optimize to 2 to avoid inserting an undesired
7614 hold_mips_optimize = mips_optimize;
7616 /* Itbl support may require additional care here. */
7617 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7618 BFD_RELOC_LO16, AT);
7619 mips_optimize = hold_mips_optimize;
7620 expr1.X_add_number -= 4;
7623 offset_expr.X_add_number = expr1.X_add_number;
7625 macro_build (NULL, "nop", "");
7626 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7627 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7630 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7631 /* Itbl support may require additional care here. */
7632 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7633 BFD_RELOC_LO16, AT);
7634 offset_expr.X_add_number += 4;
7636 /* Set mips_optimize to 2 to avoid inserting an undesired
7638 hold_mips_optimize = mips_optimize;
7640 /* Itbl support may require additional care here. */
7641 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7642 BFD_RELOC_LO16, AT);
7643 mips_optimize = hold_mips_optimize;
7652 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7655 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7657 macro_build (&offset_expr, s, "t,o(b)", treg,
7658 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7660 if (!HAVE_64BIT_GPRS)
7662 offset_expr.X_add_number += 4;
7663 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7664 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7669 /* New code added to support COPZ instructions.
7670 This code builds table entries out of the macros in mip_opcodes.
7671 R4000 uses interlocks to handle coproc delays.
7672 Other chips (like the R3000) require nops to be inserted for delays.
7674 FIXME: Currently, we require that the user handle delays.
7675 In order to fill delay slots for non-interlocked chips,
7676 we must have a way to specify delays based on the coprocessor.
7677 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7678 What are the side-effects of the cop instruction?
7679 What cache support might we have and what are its effects?
7680 Both coprocessor & memory require delays. how long???
7681 What registers are read/set/modified?
7683 If an itbl is provided to interpret cop instructions,
7684 this knowledge can be encoded in the itbl spec. */
7698 if (NO_ISA_COP (mips_opts.arch)
7699 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7701 as_bad (_("opcode not supported on this processor: %s"),
7702 mips_cpu_info_from_arch (mips_opts.arch)->name);
7706 /* For now we just do C (same as Cz). The parameter will be
7707 stored in insn_opcode by mips_ip. */
7708 macro_build (NULL, s, "C", ip->insn_opcode);
7712 move_register (dreg, sreg);
7718 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7719 macro_build (NULL, "mflo", "d", dreg);
7725 /* The MIPS assembler some times generates shifts and adds. I'm
7726 not trying to be that fancy. GCC should do this for us
7729 load_register (AT, &imm_expr, dbl);
7730 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7731 macro_build (NULL, "mflo", "d", dreg);
7747 load_register (AT, &imm_expr, dbl);
7748 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7749 macro_build (NULL, "mflo", "d", dreg);
7750 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7751 macro_build (NULL, "mfhi", "d", AT);
7753 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7756 expr1.X_add_number = 8;
7757 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7758 macro_build (NULL, "nop", "");
7759 macro_build (NULL, "break", "c", 6);
7762 macro_build (NULL, "mflo", "d", dreg);
7778 load_register (AT, &imm_expr, dbl);
7779 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7780 sreg, imm ? AT : treg);
7781 macro_build (NULL, "mfhi", "d", AT);
7782 macro_build (NULL, "mflo", "d", dreg);
7784 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7787 expr1.X_add_number = 8;
7788 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7789 macro_build (NULL, "nop", "");
7790 macro_build (NULL, "break", "c", 6);
7796 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7807 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7808 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7812 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7813 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7814 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7815 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7819 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7830 macro_build (NULL, "negu", "d,w", tempreg, treg);
7831 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7835 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7836 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7837 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7838 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7847 if (imm_expr.X_op != O_constant)
7848 as_bad (_("Improper rotate count"));
7849 rot = imm_expr.X_add_number & 0x3f;
7850 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7852 rot = (64 - rot) & 0x3f;
7854 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7856 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7861 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7864 l = (rot < 0x20) ? "dsll" : "dsll32";
7865 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7868 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7869 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7870 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7878 if (imm_expr.X_op != O_constant)
7879 as_bad (_("Improper rotate count"));
7880 rot = imm_expr.X_add_number & 0x1f;
7881 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7883 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7888 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7892 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7893 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7894 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7899 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7901 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7905 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7906 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7907 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7908 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7912 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7914 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7918 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7919 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7920 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7921 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7930 if (imm_expr.X_op != O_constant)
7931 as_bad (_("Improper rotate count"));
7932 rot = imm_expr.X_add_number & 0x3f;
7933 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7936 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7938 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7943 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7946 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7947 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7950 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7951 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7952 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7960 if (imm_expr.X_op != O_constant)
7961 as_bad (_("Improper rotate count"));
7962 rot = imm_expr.X_add_number & 0x1f;
7963 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7965 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7970 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7974 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7975 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7976 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7982 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7984 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7987 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7988 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7993 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7995 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8000 as_warn (_("Instruction %s: result is always false"),
8002 move_register (dreg, 0);
8005 if (CPU_HAS_SEQ (mips_opts.arch)
8006 && -512 <= imm_expr.X_add_number
8007 && imm_expr.X_add_number < 512)
8009 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
8010 (int) imm_expr.X_add_number);
8013 if (imm_expr.X_op == O_constant
8014 && imm_expr.X_add_number >= 0
8015 && imm_expr.X_add_number < 0x10000)
8017 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8019 else if (imm_expr.X_op == O_constant
8020 && imm_expr.X_add_number > -0x8000
8021 && imm_expr.X_add_number < 0)
8023 imm_expr.X_add_number = -imm_expr.X_add_number;
8024 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8025 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8027 else if (CPU_HAS_SEQ (mips_opts.arch))
8030 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8031 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
8036 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8037 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8040 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8043 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8049 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8050 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8053 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8055 if (imm_expr.X_op == O_constant
8056 && imm_expr.X_add_number >= -0x8000
8057 && imm_expr.X_add_number < 0x8000)
8059 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8060 dreg, sreg, BFD_RELOC_LO16);
8064 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8065 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8069 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8072 case M_SGT: /* sreg > treg <==> treg < sreg */
8078 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8081 case M_SGT_I: /* sreg > I <==> I < sreg */
8088 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8089 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8092 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8098 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8099 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8102 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8109 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8110 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8111 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8115 if (imm_expr.X_op == O_constant
8116 && imm_expr.X_add_number >= -0x8000
8117 && imm_expr.X_add_number < 0x8000)
8119 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8123 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8124 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8128 if (imm_expr.X_op == O_constant
8129 && imm_expr.X_add_number >= -0x8000
8130 && imm_expr.X_add_number < 0x8000)
8132 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8137 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8138 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8143 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8145 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8148 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8149 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8154 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8156 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8161 as_warn (_("Instruction %s: result is always true"),
8163 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8164 dreg, 0, BFD_RELOC_LO16);
8167 if (CPU_HAS_SEQ (mips_opts.arch)
8168 && -512 <= imm_expr.X_add_number
8169 && imm_expr.X_add_number < 512)
8171 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8172 (int) imm_expr.X_add_number);
8175 if (imm_expr.X_op == O_constant
8176 && imm_expr.X_add_number >= 0
8177 && imm_expr.X_add_number < 0x10000)
8179 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8181 else if (imm_expr.X_op == O_constant
8182 && imm_expr.X_add_number > -0x8000
8183 && imm_expr.X_add_number < 0)
8185 imm_expr.X_add_number = -imm_expr.X_add_number;
8186 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8187 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8189 else if (CPU_HAS_SEQ (mips_opts.arch))
8192 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8193 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8198 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8199 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8202 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8208 if (imm_expr.X_op == O_constant
8209 && imm_expr.X_add_number > -0x8000
8210 && imm_expr.X_add_number <= 0x8000)
8212 imm_expr.X_add_number = -imm_expr.X_add_number;
8213 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8214 dreg, sreg, BFD_RELOC_LO16);
8218 load_register (AT, &imm_expr, dbl);
8219 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8225 if (imm_expr.X_op == O_constant
8226 && imm_expr.X_add_number > -0x8000
8227 && imm_expr.X_add_number <= 0x8000)
8229 imm_expr.X_add_number = -imm_expr.X_add_number;
8230 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8231 dreg, sreg, BFD_RELOC_LO16);
8235 load_register (AT, &imm_expr, dbl);
8236 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8258 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8259 macro_build (NULL, s, "s,t", sreg, AT);
8264 gas_assert (mips_opts.isa == ISA_MIPS1);
8266 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8267 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8270 * Is the double cfc1 instruction a bug in the mips assembler;
8271 * or is there a reason for it?
8274 macro_build (NULL, "cfc1", "t,G", treg, RA);
8275 macro_build (NULL, "cfc1", "t,G", treg, RA);
8276 macro_build (NULL, "nop", "");
8277 expr1.X_add_number = 3;
8278 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8279 expr1.X_add_number = 2;
8280 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8281 macro_build (NULL, "ctc1", "t,G", AT, RA);
8282 macro_build (NULL, "nop", "");
8283 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8285 macro_build (NULL, "ctc1", "t,G", treg, RA);
8286 macro_build (NULL, "nop", "");
8297 if (offset_expr.X_add_number >= 0x7fff)
8298 as_bad (_("Operand overflow"));
8299 if (!target_big_endian)
8300 ++offset_expr.X_add_number;
8301 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8302 if (!target_big_endian)
8303 --offset_expr.X_add_number;
8305 ++offset_expr.X_add_number;
8306 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8307 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8308 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8321 if (offset_expr.X_add_number >= 0x8000 - off)
8322 as_bad (_("Operand overflow"));
8330 if (!target_big_endian)
8331 offset_expr.X_add_number += off;
8332 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8333 if (!target_big_endian)
8334 offset_expr.X_add_number -= off;
8336 offset_expr.X_add_number += off;
8337 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8339 /* If necessary, move the result in tempreg to the final destination. */
8340 if (treg == tempreg)
8342 /* Protect second load's delay slot. */
8344 move_register (treg, tempreg);
8358 load_address (AT, &offset_expr, &used_at);
8360 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8361 if (!target_big_endian)
8362 expr1.X_add_number = off;
8364 expr1.X_add_number = 0;
8365 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8366 if (!target_big_endian)
8367 expr1.X_add_number = 0;
8369 expr1.X_add_number = off;
8370 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8376 load_address (AT, &offset_expr, &used_at);
8378 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8379 if (target_big_endian)
8380 expr1.X_add_number = 0;
8381 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8382 treg, BFD_RELOC_LO16, AT);
8383 if (target_big_endian)
8384 expr1.X_add_number = 1;
8386 expr1.X_add_number = 0;
8387 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8388 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8389 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8394 if (offset_expr.X_add_number >= 0x7fff)
8395 as_bad (_("Operand overflow"));
8396 if (target_big_endian)
8397 ++offset_expr.X_add_number;
8398 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8399 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8400 if (target_big_endian)
8401 --offset_expr.X_add_number;
8403 ++offset_expr.X_add_number;
8404 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8417 if (offset_expr.X_add_number >= 0x8000 - off)
8418 as_bad (_("Operand overflow"));
8419 if (!target_big_endian)
8420 offset_expr.X_add_number += off;
8421 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8422 if (!target_big_endian)
8423 offset_expr.X_add_number -= off;
8425 offset_expr.X_add_number += off;
8426 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8440 load_address (AT, &offset_expr, &used_at);
8442 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8443 if (!target_big_endian)
8444 expr1.X_add_number = off;
8446 expr1.X_add_number = 0;
8447 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8448 if (!target_big_endian)
8449 expr1.X_add_number = 0;
8451 expr1.X_add_number = off;
8452 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8457 load_address (AT, &offset_expr, &used_at);
8459 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8460 if (!target_big_endian)
8461 expr1.X_add_number = 0;
8462 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8463 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8464 if (!target_big_endian)
8465 expr1.X_add_number = 1;
8467 expr1.X_add_number = 0;
8468 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8469 if (!target_big_endian)
8470 expr1.X_add_number = 0;
8472 expr1.X_add_number = 1;
8473 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8474 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8475 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8479 /* FIXME: Check if this is one of the itbl macros, since they
8480 are added dynamically. */
8481 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8484 if (!mips_opts.at && used_at)
8485 as_bad (_("Macro used $at after \".set noat\""));
8488 /* Implement macros in mips16 mode. */
8491 mips16_macro (struct mips_cl_insn *ip)
8494 int xreg, yreg, zreg, tmp;
8497 const char *s, *s2, *s3;
8499 mask = ip->insn_mo->mask;
8501 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8502 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8503 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8505 expr1.X_op = O_constant;
8506 expr1.X_op_symbol = NULL;
8507 expr1.X_add_symbol = NULL;
8508 expr1.X_add_number = 1;
8528 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8529 expr1.X_add_number = 2;
8530 macro_build (&expr1, "bnez", "x,p", yreg);
8531 macro_build (NULL, "break", "6", 7);
8533 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8534 since that causes an overflow. We should do that as well,
8535 but I don't see how to do the comparisons without a temporary
8538 macro_build (NULL, s, "x", zreg);
8558 macro_build (NULL, s, "0,x,y", xreg, yreg);
8559 expr1.X_add_number = 2;
8560 macro_build (&expr1, "bnez", "x,p", yreg);
8561 macro_build (NULL, "break", "6", 7);
8563 macro_build (NULL, s2, "x", zreg);
8569 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8570 macro_build (NULL, "mflo", "x", zreg);
8578 if (imm_expr.X_op != O_constant)
8579 as_bad (_("Unsupported large constant"));
8580 imm_expr.X_add_number = -imm_expr.X_add_number;
8581 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8585 if (imm_expr.X_op != O_constant)
8586 as_bad (_("Unsupported large constant"));
8587 imm_expr.X_add_number = -imm_expr.X_add_number;
8588 macro_build (&imm_expr, "addiu", "x,k", xreg);
8592 if (imm_expr.X_op != O_constant)
8593 as_bad (_("Unsupported large constant"));
8594 imm_expr.X_add_number = -imm_expr.X_add_number;
8595 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8617 goto do_reverse_branch;
8621 goto do_reverse_branch;
8633 goto do_reverse_branch;
8644 macro_build (NULL, s, "x,y", xreg, yreg);
8645 macro_build (&offset_expr, s2, "p");
8672 goto do_addone_branch_i;
8677 goto do_addone_branch_i;
8692 goto do_addone_branch_i;
8699 if (imm_expr.X_op != O_constant)
8700 as_bad (_("Unsupported large constant"));
8701 ++imm_expr.X_add_number;
8704 macro_build (&imm_expr, s, s3, xreg);
8705 macro_build (&offset_expr, s2, "p");
8709 expr1.X_add_number = 0;
8710 macro_build (&expr1, "slti", "x,8", yreg);
8712 move_register (xreg, yreg);
8713 expr1.X_add_number = 2;
8714 macro_build (&expr1, "bteqz", "p");
8715 macro_build (NULL, "neg", "x,w", xreg, xreg);
8719 /* For consistency checking, verify that all bits are specified either
8720 by the match/mask part of the instruction definition, or by the
8723 validate_mips_insn (const struct mips_opcode *opc)
8725 const char *p = opc->args;
8727 unsigned long used_bits = opc->mask;
8729 if ((used_bits & opc->match) != opc->match)
8731 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8732 opc->name, opc->args);
8735 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8745 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8746 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8747 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8748 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8749 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8750 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8751 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8752 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8753 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8754 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8755 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8756 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8757 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8759 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8760 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8761 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8762 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8763 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8764 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8765 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8766 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8767 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8768 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8769 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8770 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8771 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8772 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8773 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8776 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8777 c, opc->name, opc->args);
8781 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8782 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8784 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8785 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8786 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8787 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8789 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8790 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8792 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8793 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8795 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8796 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8797 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8798 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8799 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8800 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8801 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8802 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8803 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8804 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8805 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8806 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8807 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8808 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8809 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8810 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8811 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8813 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8814 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8815 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8816 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8818 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8819 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8820 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8821 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8822 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8823 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8824 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8825 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8826 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8829 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8830 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8831 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8832 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8833 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8836 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8837 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8838 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8839 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8840 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8841 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8842 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8843 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8844 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8845 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8846 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8847 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8848 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8849 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8850 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8851 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8852 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8853 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8855 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8856 c, opc->name, opc->args);
8860 if (used_bits != 0xffffffff)
8862 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8863 ~used_bits & 0xffffffff, opc->name, opc->args);
8869 /* UDI immediates. */
8877 static const struct mips_immed mips_immed[] = {
8878 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8879 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8880 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8881 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8885 /* Check whether an odd floating-point register is allowed. */
8887 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8889 const char *s = insn->name;
8891 if (insn->pinfo == INSN_MACRO)
8892 /* Let a macro pass, we'll catch it later when it is expanded. */
8895 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8897 /* Allow odd registers for single-precision ops. */
8898 switch (insn->pinfo & (FP_S | FP_D))
8902 return 1; /* both single precision - ok */
8904 return 0; /* both double precision - fail */
8909 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8910 s = strchr (insn->name, '.');
8912 s = s != NULL ? strchr (s + 1, '.') : NULL;
8913 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8916 /* Single-precision coprocessor loads and moves are OK too. */
8917 if ((insn->pinfo & FP_S)
8918 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8919 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8925 /* This routine assembles an instruction into its binary format. As a
8926 side effect, it sets one of the global variables imm_reloc or
8927 offset_reloc to the type of relocation to do if one of the operands
8928 is an address expression. */
8931 mips_ip (char *str, struct mips_cl_insn *ip)
8936 struct mips_opcode *insn;
8939 unsigned int lastregno;
8940 unsigned int lastpos = 0;
8941 unsigned int limlo, limhi;
8944 offsetT min_range, max_range;
8950 /* If the instruction contains a '.', we first try to match an instruction
8951 including the '.'. Then we try again without the '.'. */
8953 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8956 /* If we stopped on whitespace, then replace the whitespace with null for
8957 the call to hash_find. Save the character we replaced just in case we
8958 have to re-parse the instruction. */
8965 insn = (struct mips_opcode *) hash_find (op_hash, str);
8967 /* If we didn't find the instruction in the opcode table, try again, but
8968 this time with just the instruction up to, but not including the
8972 /* Restore the character we overwrite above (if any). */
8976 /* Scan up to the first '.' or whitespace. */
8978 *s != '\0' && *s != '.' && !ISSPACE (*s);
8982 /* If we did not find a '.', then we can quit now. */
8985 insn_error = _("Unrecognized opcode");
8989 /* Lookup the instruction in the hash table. */
8991 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8993 insn_error = _("Unrecognized opcode");
9003 gas_assert (strcmp (insn->name, str) == 0);
9005 ok = is_opcode_valid (insn);
9008 if (insn + 1 < &mips_opcodes[NUMOPCODES]
9009 && strcmp (insn->name, insn[1].name) == 0)
9018 static char buf[100];
9020 _("opcode not supported on this processor: %s (%s)"),
9021 mips_cpu_info_from_arch (mips_opts.arch)->name,
9022 mips_cpu_info_from_isa (mips_opts.isa)->name);
9031 create_insn (ip, insn);
9034 lastregno = 0xffffffff;
9035 for (args = insn->args;; ++args)
9039 s += strspn (s, " \t");
9043 case '\0': /* end of args */
9048 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9049 my_getExpression (&imm_expr, s);
9050 check_absolute_expr (ip, &imm_expr);
9051 if ((unsigned long) imm_expr.X_add_number != 1
9052 && (unsigned long) imm_expr.X_add_number != 3)
9054 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9055 (unsigned long) imm_expr.X_add_number);
9057 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9058 imm_expr.X_op = O_absent;
9062 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9063 my_getExpression (&imm_expr, s);
9064 check_absolute_expr (ip, &imm_expr);
9065 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9067 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9068 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9070 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9071 imm_expr.X_op = O_absent;
9075 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9076 my_getExpression (&imm_expr, s);
9077 check_absolute_expr (ip, &imm_expr);
9078 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9080 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9081 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9083 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9084 imm_expr.X_op = O_absent;
9088 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9089 my_getExpression (&imm_expr, s);
9090 check_absolute_expr (ip, &imm_expr);
9091 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9093 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9094 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9096 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9097 imm_expr.X_op = O_absent;
9101 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9102 my_getExpression (&imm_expr, s);
9103 check_absolute_expr (ip, &imm_expr);
9104 if (imm_expr.X_add_number & ~OP_MASK_RS)
9106 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9107 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9109 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9110 imm_expr.X_op = O_absent;
9114 case '7': /* Four DSP accumulators in bits 11,12. */
9115 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9116 s[3] >= '0' && s[3] <= '3')
9120 INSERT_OPERAND (DSPACC, *ip, regno);
9124 as_bad (_("Invalid dsp acc register"));
9127 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9128 my_getExpression (&imm_expr, s);
9129 check_absolute_expr (ip, &imm_expr);
9130 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9132 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9134 (unsigned long) imm_expr.X_add_number);
9136 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9137 imm_expr.X_op = O_absent;
9141 case '9': /* Four DSP accumulators in bits 21,22. */
9142 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9143 s[3] >= '0' && s[3] <= '3')
9147 INSERT_OPERAND (DSPACC_S, *ip, regno);
9151 as_bad (_("Invalid dsp acc register"));
9154 case '0': /* DSP 6-bit signed immediate in bit 20. */
9155 my_getExpression (&imm_expr, s);
9156 check_absolute_expr (ip, &imm_expr);
9157 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9158 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9159 if (imm_expr.X_add_number < min_range ||
9160 imm_expr.X_add_number > max_range)
9162 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9163 (long) min_range, (long) max_range,
9164 (long) imm_expr.X_add_number);
9166 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9167 imm_expr.X_op = O_absent;
9171 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9172 my_getExpression (&imm_expr, s);
9173 check_absolute_expr (ip, &imm_expr);
9174 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9176 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9178 (unsigned long) imm_expr.X_add_number);
9180 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9181 imm_expr.X_op = O_absent;
9185 case ':': /* DSP 7-bit signed immediate in bit 19. */
9186 my_getExpression (&imm_expr, s);
9187 check_absolute_expr (ip, &imm_expr);
9188 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9189 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9190 if (imm_expr.X_add_number < min_range ||
9191 imm_expr.X_add_number > max_range)
9193 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9194 (long) min_range, (long) max_range,
9195 (long) imm_expr.X_add_number);
9197 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9198 imm_expr.X_op = O_absent;
9202 case '@': /* DSP 10-bit signed immediate in bit 16. */
9203 my_getExpression (&imm_expr, s);
9204 check_absolute_expr (ip, &imm_expr);
9205 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9206 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9207 if (imm_expr.X_add_number < min_range ||
9208 imm_expr.X_add_number > max_range)
9210 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9211 (long) min_range, (long) max_range,
9212 (long) imm_expr.X_add_number);
9214 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9215 imm_expr.X_op = O_absent;
9219 case '!': /* MT usermode flag bit. */
9220 my_getExpression (&imm_expr, s);
9221 check_absolute_expr (ip, &imm_expr);
9222 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9223 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9224 (unsigned long) imm_expr.X_add_number);
9225 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9226 imm_expr.X_op = O_absent;
9230 case '$': /* MT load high flag bit. */
9231 my_getExpression (&imm_expr, s);
9232 check_absolute_expr (ip, &imm_expr);
9233 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9234 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9235 (unsigned long) imm_expr.X_add_number);
9236 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9237 imm_expr.X_op = O_absent;
9241 case '*': /* Four DSP accumulators in bits 18,19. */
9242 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9243 s[3] >= '0' && s[3] <= '3')
9247 INSERT_OPERAND (MTACC_T, *ip, regno);
9251 as_bad (_("Invalid dsp/smartmips acc register"));
9254 case '&': /* Four DSP accumulators in bits 13,14. */
9255 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9256 s[3] >= '0' && s[3] <= '3')
9260 INSERT_OPERAND (MTACC_D, *ip, regno);
9264 as_bad (_("Invalid dsp/smartmips acc register"));
9276 INSERT_OPERAND (RS, *ip, lastregno);
9280 INSERT_OPERAND (RT, *ip, lastregno);
9284 INSERT_OPERAND (FT, *ip, lastregno);
9288 INSERT_OPERAND (FS, *ip, lastregno);
9294 /* Handle optional base register.
9295 Either the base register is omitted or
9296 we must have a left paren. */
9297 /* This is dependent on the next operand specifier
9298 is a base register specification. */
9299 gas_assert (args[1] == 'b');
9303 case ')': /* These must match exactly. */
9310 case '+': /* Opcode extension character. */
9313 case '1': /* UDI immediates. */
9318 const struct mips_immed *imm = mips_immed;
9320 while (imm->type && imm->type != *args)
9324 my_getExpression (&imm_expr, s);
9325 check_absolute_expr (ip, &imm_expr);
9326 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9328 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9329 imm->desc ? imm->desc : ip->insn_mo->name,
9330 (unsigned long) imm_expr.X_add_number,
9331 (unsigned long) imm_expr.X_add_number);
9332 imm_expr.X_add_number &= imm->mask;
9334 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9336 imm_expr.X_op = O_absent;
9341 case 'A': /* ins/ext position, becomes LSB. */
9350 my_getExpression (&imm_expr, s);
9351 check_absolute_expr (ip, &imm_expr);
9352 if ((unsigned long) imm_expr.X_add_number < limlo
9353 || (unsigned long) imm_expr.X_add_number > limhi)
9355 as_bad (_("Improper position (%lu)"),
9356 (unsigned long) imm_expr.X_add_number);
9357 imm_expr.X_add_number = limlo;
9359 lastpos = imm_expr.X_add_number;
9360 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9361 imm_expr.X_op = O_absent;
9365 case 'B': /* ins size, becomes MSB. */
9374 my_getExpression (&imm_expr, s);
9375 check_absolute_expr (ip, &imm_expr);
9376 /* Check for negative input so that small negative numbers
9377 will not succeed incorrectly. The checks against
9378 (pos+size) transitively check "size" itself,
9379 assuming that "pos" is reasonable. */
9380 if ((long) imm_expr.X_add_number < 0
9381 || ((unsigned long) imm_expr.X_add_number
9383 || ((unsigned long) imm_expr.X_add_number
9386 as_bad (_("Improper insert size (%lu, position %lu)"),
9387 (unsigned long) imm_expr.X_add_number,
9388 (unsigned long) lastpos);
9389 imm_expr.X_add_number = limlo - lastpos;
9391 INSERT_OPERAND (INSMSB, *ip,
9392 lastpos + imm_expr.X_add_number - 1);
9393 imm_expr.X_op = O_absent;
9397 case 'C': /* ext size, becomes MSBD. */
9410 my_getExpression (&imm_expr, s);
9411 check_absolute_expr (ip, &imm_expr);
9412 /* Check for negative input so that small negative numbers
9413 will not succeed incorrectly. The checks against
9414 (pos+size) transitively check "size" itself,
9415 assuming that "pos" is reasonable. */
9416 if ((long) imm_expr.X_add_number < 0
9417 || ((unsigned long) imm_expr.X_add_number
9419 || ((unsigned long) imm_expr.X_add_number
9422 as_bad (_("Improper extract size (%lu, position %lu)"),
9423 (unsigned long) imm_expr.X_add_number,
9424 (unsigned long) lastpos);
9425 imm_expr.X_add_number = limlo - lastpos;
9427 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9428 imm_expr.X_op = O_absent;
9433 /* +D is for disassembly only; never match. */
9437 /* "+I" is like "I", except that imm2_expr is used. */
9438 my_getExpression (&imm2_expr, s);
9439 if (imm2_expr.X_op != O_big
9440 && imm2_expr.X_op != O_constant)
9441 insn_error = _("absolute expression required");
9442 if (HAVE_32BIT_GPRS)
9443 normalize_constant_expr (&imm2_expr);
9447 case 'T': /* Coprocessor register. */
9448 /* +T is for disassembly only; never match. */
9451 case 't': /* Coprocessor register number. */
9452 if (s[0] == '$' && ISDIGIT (s[1]))
9462 while (ISDIGIT (*s));
9464 as_bad (_("Invalid register number (%d)"), regno);
9467 INSERT_OPERAND (RT, *ip, regno);
9472 as_bad (_("Invalid coprocessor 0 register number"));
9476 /* bbit[01] and bbit[01]32 bit index. Give error if index
9477 is not in the valid range. */
9478 my_getExpression (&imm_expr, s);
9479 check_absolute_expr (ip, &imm_expr);
9480 if ((unsigned) imm_expr.X_add_number > 31)
9482 as_bad (_("Improper bit index (%lu)"),
9483 (unsigned long) imm_expr.X_add_number);
9484 imm_expr.X_add_number = 0;
9486 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9487 imm_expr.X_op = O_absent;
9492 /* bbit[01] bit index when bbit is used but we generate
9493 bbit[01]32 because the index is over 32. Move to the
9494 next candidate if index is not in the valid range. */
9495 my_getExpression (&imm_expr, s);
9496 check_absolute_expr (ip, &imm_expr);
9497 if ((unsigned) imm_expr.X_add_number < 32
9498 || (unsigned) imm_expr.X_add_number > 63)
9500 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9501 imm_expr.X_op = O_absent;
9506 /* cins, cins32, exts and exts32 position field. Give error
9507 if it's not in the valid range. */
9508 my_getExpression (&imm_expr, s);
9509 check_absolute_expr (ip, &imm_expr);
9510 if ((unsigned) imm_expr.X_add_number > 31)
9512 as_bad (_("Improper position (%lu)"),
9513 (unsigned long) imm_expr.X_add_number);
9514 imm_expr.X_add_number = 0;
9516 /* Make the pos explicit to simplify +S. */
9517 lastpos = imm_expr.X_add_number + 32;
9518 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9519 imm_expr.X_op = O_absent;
9524 /* cins, cins32, exts and exts32 position field. Move to
9525 the next candidate if it's not in the valid range. */
9526 my_getExpression (&imm_expr, s);
9527 check_absolute_expr (ip, &imm_expr);
9528 if ((unsigned) imm_expr.X_add_number < 32
9529 || (unsigned) imm_expr.X_add_number > 63)
9531 lastpos = imm_expr.X_add_number;
9532 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9533 imm_expr.X_op = O_absent;
9538 /* cins and exts length-minus-one field. */
9539 my_getExpression (&imm_expr, s);
9540 check_absolute_expr (ip, &imm_expr);
9541 if ((unsigned long) imm_expr.X_add_number > 31)
9543 as_bad (_("Improper size (%lu)"),
9544 (unsigned long) imm_expr.X_add_number);
9545 imm_expr.X_add_number = 0;
9547 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9548 imm_expr.X_op = O_absent;
9553 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9554 length-minus-one field. */
9555 my_getExpression (&imm_expr, s);
9556 check_absolute_expr (ip, &imm_expr);
9557 if ((long) imm_expr.X_add_number < 0
9558 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9560 as_bad (_("Improper size (%lu)"),
9561 (unsigned long) imm_expr.X_add_number);
9562 imm_expr.X_add_number = 0;
9564 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9565 imm_expr.X_op = O_absent;
9570 /* seqi/snei immediate field. */
9571 my_getExpression (&imm_expr, s);
9572 check_absolute_expr (ip, &imm_expr);
9573 if ((long) imm_expr.X_add_number < -512
9574 || (long) imm_expr.X_add_number >= 512)
9576 as_bad (_("Improper immediate (%ld)"),
9577 (long) imm_expr.X_add_number);
9578 imm_expr.X_add_number = 0;
9580 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9581 imm_expr.X_op = O_absent;
9585 case 'a': /* 8-bit signed offset in bit 6 */
9586 my_getExpression (&imm_expr, s);
9587 check_absolute_expr (ip, &imm_expr);
9588 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9589 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9590 if (imm_expr.X_add_number < min_range
9591 || imm_expr.X_add_number > max_range)
9593 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9594 (long) min_range, (long) max_range,
9595 (long) imm_expr.X_add_number);
9597 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9598 imm_expr.X_op = O_absent;
9602 case 'b': /* 8-bit signed offset in bit 3 */
9603 my_getExpression (&imm_expr, s);
9604 check_absolute_expr (ip, &imm_expr);
9605 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9606 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9607 if (imm_expr.X_add_number < min_range
9608 || imm_expr.X_add_number > max_range)
9610 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9611 (long) min_range, (long) max_range,
9612 (long) imm_expr.X_add_number);
9614 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9615 imm_expr.X_op = O_absent;
9619 case 'c': /* 9-bit signed offset in bit 6 */
9620 my_getExpression (&imm_expr, s);
9621 check_absolute_expr (ip, &imm_expr);
9622 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9623 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9624 /* We check the offset range before adjusted. */
9627 if (imm_expr.X_add_number < min_range
9628 || imm_expr.X_add_number > max_range)
9630 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9631 (long) min_range, (long) max_range,
9632 (long) imm_expr.X_add_number);
9634 if (imm_expr.X_add_number & 0xf)
9636 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9637 (long) imm_expr.X_add_number);
9639 /* Right shift 4 bits to adjust the offset operand. */
9640 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9641 imm_expr.X_op = O_absent;
9646 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
9648 if (regno == AT && mips_opts.at)
9650 if (mips_opts.at == ATREG)
9651 as_warn (_("used $at without \".set noat\""));
9653 as_warn (_("used $%u with \".set at=$%u\""),
9654 regno, mips_opts.at);
9656 INSERT_OPERAND (RZ, *ip, regno);
9660 if (!reg_lookup (&s, RTYPE_FPU, ®no))
9662 INSERT_OPERAND (FZ, *ip, regno);
9666 as_bad (_("Internal error: bad mips opcode "
9667 "(unknown extension operand type `+%c'): %s %s"),
9668 *args, insn->name, insn->args);
9669 /* Further processing is fruitless. */
9674 case '<': /* must be at least one digit */
9676 * According to the manual, if the shift amount is greater
9677 * than 31 or less than 0, then the shift amount should be
9678 * mod 32. In reality the mips assembler issues an error.
9679 * We issue a warning and mask out all but the low 5 bits.
9681 my_getExpression (&imm_expr, s);
9682 check_absolute_expr (ip, &imm_expr);
9683 if ((unsigned long) imm_expr.X_add_number > 31)
9684 as_warn (_("Improper shift amount (%lu)"),
9685 (unsigned long) imm_expr.X_add_number);
9686 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9687 imm_expr.X_op = O_absent;
9691 case '>': /* shift amount minus 32 */
9692 my_getExpression (&imm_expr, s);
9693 check_absolute_expr (ip, &imm_expr);
9694 if ((unsigned long) imm_expr.X_add_number < 32
9695 || (unsigned long) imm_expr.X_add_number > 63)
9697 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9698 imm_expr.X_op = O_absent;
9702 case 'k': /* CACHE code. */
9703 case 'h': /* PREFX code. */
9704 case '1': /* SYNC type. */
9705 my_getExpression (&imm_expr, s);
9706 check_absolute_expr (ip, &imm_expr);
9707 if ((unsigned long) imm_expr.X_add_number > 31)
9708 as_warn (_("Invalid value for `%s' (%lu)"),
9710 (unsigned long) imm_expr.X_add_number);
9713 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9714 switch (imm_expr.X_add_number)
9723 case 31: /* These are ok. */
9726 default: /* The rest must be changed to 28. */
9727 imm_expr.X_add_number = 28;
9730 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9732 else if (*args == 'h')
9733 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9735 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9736 imm_expr.X_op = O_absent;
9740 case 'c': /* BREAK code. */
9741 my_getExpression (&imm_expr, s);
9742 check_absolute_expr (ip, &imm_expr);
9743 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9744 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9746 (unsigned long) imm_expr.X_add_number);
9747 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9748 imm_expr.X_op = O_absent;
9752 case 'q': /* Lower BREAK code. */
9753 my_getExpression (&imm_expr, s);
9754 check_absolute_expr (ip, &imm_expr);
9755 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9756 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9758 (unsigned long) imm_expr.X_add_number);
9759 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9760 imm_expr.X_op = O_absent;
9764 case 'B': /* 20-bit SYSCALL/BREAK code. */
9765 my_getExpression (&imm_expr, s);
9766 check_absolute_expr (ip, &imm_expr);
9767 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9768 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9770 (unsigned long) imm_expr.X_add_number);
9771 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9772 imm_expr.X_op = O_absent;
9776 case 'C': /* Coprocessor code. */
9777 my_getExpression (&imm_expr, s);
9778 check_absolute_expr (ip, &imm_expr);
9779 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9781 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9782 (unsigned long) imm_expr.X_add_number);
9783 imm_expr.X_add_number &= OP_MASK_COPZ;
9785 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9786 imm_expr.X_op = O_absent;
9790 case 'J': /* 19-bit WAIT code. */
9791 my_getExpression (&imm_expr, s);
9792 check_absolute_expr (ip, &imm_expr);
9793 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9795 as_warn (_("Illegal 19-bit code (%lu)"),
9796 (unsigned long) imm_expr.X_add_number);
9797 imm_expr.X_add_number &= OP_MASK_CODE19;
9799 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9800 imm_expr.X_op = O_absent;
9804 case 'P': /* Performance register. */
9805 my_getExpression (&imm_expr, s);
9806 check_absolute_expr (ip, &imm_expr);
9807 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9808 as_warn (_("Invalid performance register (%lu)"),
9809 (unsigned long) imm_expr.X_add_number);
9810 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9811 imm_expr.X_op = O_absent;
9815 case 'G': /* Coprocessor destination register. */
9816 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9817 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no);
9819 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9820 INSERT_OPERAND (RD, *ip, regno);
9829 case 'b': /* Base register. */
9830 case 'd': /* Destination register. */
9831 case 's': /* Source register. */
9832 case 't': /* Target register. */
9833 case 'r': /* Both target and source. */
9834 case 'v': /* Both dest and source. */
9835 case 'w': /* Both dest and target. */
9836 case 'E': /* Coprocessor target register. */
9837 case 'K': /* RDHWR destination register. */
9838 case 'x': /* Ignore register name. */
9839 case 'z': /* Must be zero register. */
9840 case 'U': /* Destination register (CLO/CLZ). */
9841 case 'g': /* Coprocessor destination register. */
9843 if (*args == 'E' || *args == 'K')
9844 ok = reg_lookup (&s, RTYPE_NUM, ®no);
9847 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
9848 if (regno == AT && mips_opts.at)
9850 if (mips_opts.at == ATREG)
9851 as_warn (_("Used $at without \".set noat\""));
9853 as_warn (_("Used $%u with \".set at=$%u\""),
9854 regno, mips_opts.at);
9864 if (c == 'r' || c == 'v' || c == 'w')
9871 /* 'z' only matches $0. */
9872 if (c == 'z' && regno != 0)
9875 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9877 if (regno == lastregno)
9880 = _("Source and destination must be different");
9883 if (regno == 31 && lastregno == 0xffffffff)
9886 = _("A destination register must be supplied");
9890 /* Now that we have assembled one operand, we use the args
9891 string to figure out where it goes in the instruction. */
9898 INSERT_OPERAND (RS, *ip, regno);
9903 INSERT_OPERAND (RD, *ip, regno);
9906 INSERT_OPERAND (RD, *ip, regno);
9907 INSERT_OPERAND (RT, *ip, regno);
9912 INSERT_OPERAND (RT, *ip, regno);
9915 /* This case exists because on the r3000 trunc
9916 expands into a macro which requires a gp
9917 register. On the r6000 or r4000 it is
9918 assembled into a single instruction which
9919 ignores the register. Thus the insn version
9920 is MIPS_ISA2 and uses 'x', and the macro
9921 version is MIPS_ISA1 and uses 't'. */
9924 /* This case is for the div instruction, which
9925 acts differently if the destination argument
9926 is $0. This only matches $0, and is checked
9927 outside the switch. */
9937 INSERT_OPERAND (RS, *ip, lastregno);
9940 INSERT_OPERAND (RT, *ip, lastregno);
9945 case 'O': /* MDMX alignment immediate constant. */
9946 my_getExpression (&imm_expr, s);
9947 check_absolute_expr (ip, &imm_expr);
9948 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9949 as_warn (_("Improper align amount (%ld), using low bits"),
9950 (long) imm_expr.X_add_number);
9951 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9952 imm_expr.X_op = O_absent;
9956 case 'Q': /* MDMX vector, element sel, or const. */
9959 /* MDMX Immediate. */
9960 my_getExpression (&imm_expr, s);
9961 check_absolute_expr (ip, &imm_expr);
9962 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9963 as_warn (_("Invalid MDMX Immediate (%ld)"),
9964 (long) imm_expr.X_add_number);
9965 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9966 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9967 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9969 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9970 imm_expr.X_op = O_absent;
9974 /* Not MDMX Immediate. Fall through. */
9975 case 'X': /* MDMX destination register. */
9976 case 'Y': /* MDMX source register. */
9977 case 'Z': /* MDMX target register. */
9979 case 'D': /* Floating point destination register. */
9980 case 'S': /* Floating point source register. */
9981 case 'T': /* Floating point target register. */
9982 case 'R': /* Floating point source register. */
9987 || (mips_opts.ase_mdmx
9988 && (ip->insn_mo->pinfo & FP_D)
9989 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9990 | INSN_COPROC_MEMORY_DELAY
9991 | INSN_LOAD_COPROC_DELAY
9992 | INSN_LOAD_MEMORY_DELAY
9993 | INSN_STORE_MEMORY))))
9996 if (reg_lookup (&s, rtype, ®no))
9998 if ((regno & 1) != 0
10000 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
10001 as_warn (_("Float register should be even, was %d"),
10009 if (c == 'V' || c == 'W')
10020 INSERT_OPERAND (FD, *ip, regno);
10025 INSERT_OPERAND (FS, *ip, regno);
10028 /* This is like 'Z', but also needs to fix the MDMX
10029 vector/scalar select bits. Note that the
10030 scalar immediate case is handled above. */
10033 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
10034 int max_el = (is_qh ? 3 : 7);
10036 my_getExpression(&imm_expr, s);
10037 check_absolute_expr (ip, &imm_expr);
10039 if (imm_expr.X_add_number > max_el)
10040 as_bad (_("Bad element selector %ld"),
10041 (long) imm_expr.X_add_number);
10042 imm_expr.X_add_number &= max_el;
10043 ip->insn_opcode |= (imm_expr.X_add_number
10046 imm_expr.X_op = O_absent;
10048 as_warn (_("Expecting ']' found '%s'"), s);
10054 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10055 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10058 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10061 /* Fall through. */
10065 INSERT_OPERAND (FT, *ip, regno);
10068 INSERT_OPERAND (FR, *ip, regno);
10078 INSERT_OPERAND (FS, *ip, lastregno);
10081 INSERT_OPERAND (FT, *ip, lastregno);
10087 my_getExpression (&imm_expr, s);
10088 if (imm_expr.X_op != O_big
10089 && imm_expr.X_op != O_constant)
10090 insn_error = _("absolute expression required");
10091 if (HAVE_32BIT_GPRS)
10092 normalize_constant_expr (&imm_expr);
10097 my_getExpression (&offset_expr, s);
10098 normalize_address_expr (&offset_expr);
10099 *imm_reloc = BFD_RELOC_32;
10112 unsigned char temp[8];
10114 unsigned int length;
10119 /* These only appear as the last operand in an
10120 instruction, and every instruction that accepts
10121 them in any variant accepts them in all variants.
10122 This means we don't have to worry about backing out
10123 any changes if the instruction does not match.
10125 The difference between them is the size of the
10126 floating point constant and where it goes. For 'F'
10127 and 'L' the constant is 64 bits; for 'f' and 'l' it
10128 is 32 bits. Where the constant is placed is based
10129 on how the MIPS assembler does things:
10132 f -- immediate value
10135 The .lit4 and .lit8 sections are only used if
10136 permitted by the -G argument.
10138 The code below needs to know whether the target register
10139 is 32 or 64 bits wide. It relies on the fact 'f' and
10140 'F' are used with GPR-based instructions and 'l' and
10141 'L' are used with FPR-based instructions. */
10143 f64 = *args == 'F' || *args == 'L';
10144 using_gprs = *args == 'F' || *args == 'f';
10146 save_in = input_line_pointer;
10147 input_line_pointer = s;
10148 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10150 s = input_line_pointer;
10151 input_line_pointer = save_in;
10152 if (err != NULL && *err != '\0')
10154 as_bad (_("Bad floating point constant: %s"), err);
10155 memset (temp, '\0', sizeof temp);
10156 length = f64 ? 8 : 4;
10159 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10163 && (g_switch_value < 4
10164 || (temp[0] == 0 && temp[1] == 0)
10165 || (temp[2] == 0 && temp[3] == 0))))
10167 imm_expr.X_op = O_constant;
10168 if (!target_big_endian)
10169 imm_expr.X_add_number = bfd_getl32 (temp);
10171 imm_expr.X_add_number = bfd_getb32 (temp);
10173 else if (length > 4
10174 && !mips_disable_float_construction
10175 /* Constants can only be constructed in GPRs and
10176 copied to FPRs if the GPRs are at least as wide
10177 as the FPRs. Force the constant into memory if
10178 we are using 64-bit FPRs but the GPRs are only
10181 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10182 && ((temp[0] == 0 && temp[1] == 0)
10183 || (temp[2] == 0 && temp[3] == 0))
10184 && ((temp[4] == 0 && temp[5] == 0)
10185 || (temp[6] == 0 && temp[7] == 0)))
10187 /* The value is simple enough to load with a couple of
10188 instructions. If using 32-bit registers, set
10189 imm_expr to the high order 32 bits and offset_expr to
10190 the low order 32 bits. Otherwise, set imm_expr to
10191 the entire 64 bit constant. */
10192 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10194 imm_expr.X_op = O_constant;
10195 offset_expr.X_op = O_constant;
10196 if (!target_big_endian)
10198 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10199 offset_expr.X_add_number = bfd_getl32 (temp);
10203 imm_expr.X_add_number = bfd_getb32 (temp);
10204 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10206 if (offset_expr.X_add_number == 0)
10207 offset_expr.X_op = O_absent;
10209 else if (sizeof (imm_expr.X_add_number) > 4)
10211 imm_expr.X_op = O_constant;
10212 if (!target_big_endian)
10213 imm_expr.X_add_number = bfd_getl64 (temp);
10215 imm_expr.X_add_number = bfd_getb64 (temp);
10219 imm_expr.X_op = O_big;
10220 imm_expr.X_add_number = 4;
10221 if (!target_big_endian)
10223 generic_bignum[0] = bfd_getl16 (temp);
10224 generic_bignum[1] = bfd_getl16 (temp + 2);
10225 generic_bignum[2] = bfd_getl16 (temp + 4);
10226 generic_bignum[3] = bfd_getl16 (temp + 6);
10230 generic_bignum[0] = bfd_getb16 (temp + 6);
10231 generic_bignum[1] = bfd_getb16 (temp + 4);
10232 generic_bignum[2] = bfd_getb16 (temp + 2);
10233 generic_bignum[3] = bfd_getb16 (temp);
10239 const char *newname;
10242 /* Switch to the right section. */
10244 subseg = now_subseg;
10247 default: /* unused default case avoids warnings. */
10249 newname = RDATA_SECTION_NAME;
10250 if (g_switch_value >= 8)
10254 newname = RDATA_SECTION_NAME;
10257 gas_assert (g_switch_value >= 4);
10261 new_seg = subseg_new (newname, (subsegT) 0);
10263 bfd_set_section_flags (stdoutput, new_seg,
10268 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10269 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10270 record_alignment (new_seg, 4);
10272 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10273 if (seg == now_seg)
10274 as_bad (_("Can't use floating point insn in this section"));
10276 /* Set the argument to the current address in the
10278 offset_expr.X_op = O_symbol;
10279 offset_expr.X_add_symbol = symbol_temp_new_now ();
10280 offset_expr.X_add_number = 0;
10282 /* Put the floating point number into the section. */
10283 p = frag_more ((int) length);
10284 memcpy (p, temp, length);
10286 /* Switch back to the original section. */
10287 subseg_set (seg, subseg);
10292 case 'i': /* 16-bit unsigned immediate. */
10293 case 'j': /* 16-bit signed immediate. */
10294 *imm_reloc = BFD_RELOC_LO16;
10295 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10298 offsetT minval, maxval;
10300 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10301 && strcmp (insn->name, insn[1].name) == 0);
10303 /* If the expression was written as an unsigned number,
10304 only treat it as signed if there are no more
10308 && sizeof (imm_expr.X_add_number) <= 4
10309 && imm_expr.X_op == O_constant
10310 && imm_expr.X_add_number < 0
10311 && imm_expr.X_unsigned
10312 && HAVE_64BIT_GPRS)
10315 /* For compatibility with older assemblers, we accept
10316 0x8000-0xffff as signed 16-bit numbers when only
10317 signed numbers are allowed. */
10319 minval = 0, maxval = 0xffff;
10321 minval = -0x8000, maxval = 0x7fff;
10323 minval = -0x8000, maxval = 0xffff;
10325 if (imm_expr.X_op != O_constant
10326 || imm_expr.X_add_number < minval
10327 || imm_expr.X_add_number > maxval)
10331 if (imm_expr.X_op == O_constant
10332 || imm_expr.X_op == O_big)
10333 as_bad (_("Expression out of range"));
10339 case 'o': /* 16-bit offset. */
10340 offset_reloc[0] = BFD_RELOC_LO16;
10341 offset_reloc[1] = BFD_RELOC_UNUSED;
10342 offset_reloc[2] = BFD_RELOC_UNUSED;
10344 /* Check whether there is only a single bracketed expression
10345 left. If so, it must be the base register and the
10346 constant must be zero. */
10347 if (*s == '(' && strchr (s + 1, '(') == 0)
10349 offset_expr.X_op = O_constant;
10350 offset_expr.X_add_number = 0;
10354 /* If this value won't fit into a 16 bit offset, then go
10355 find a macro that will generate the 32 bit offset
10357 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10358 && (offset_expr.X_op != O_constant
10359 || offset_expr.X_add_number >= 0x8000
10360 || offset_expr.X_add_number < -0x8000))
10366 case 'p': /* PC-relative offset. */
10367 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10368 my_getExpression (&offset_expr, s);
10372 case 'u': /* Upper 16 bits. */
10373 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10374 && imm_expr.X_op == O_constant
10375 && (imm_expr.X_add_number < 0
10376 || imm_expr.X_add_number >= 0x10000))
10377 as_bad (_("lui expression (%lu) not in range 0..65535"),
10378 (unsigned long) imm_expr.X_add_number);
10382 case 'a': /* 26-bit address. */
10383 my_getExpression (&offset_expr, s);
10385 *offset_reloc = BFD_RELOC_MIPS_JMP;
10388 case 'N': /* 3-bit branch condition code. */
10389 case 'M': /* 3-bit compare condition code. */
10391 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10392 rtype |= RTYPE_FCC;
10393 if (!reg_lookup (&s, rtype, ®no))
10395 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10396 || strcmp (str + strlen (str) - 5, "any2f") == 0
10397 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10398 && (regno & 1) != 0)
10399 as_warn (_("Condition code register should be even for %s, "
10402 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10403 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10404 && (regno & 3) != 0)
10405 as_warn (_("Condition code register should be 0 or 4 for %s, "
10409 INSERT_OPERAND (BCC, *ip, regno);
10411 INSERT_OPERAND (CCC, *ip, regno);
10415 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10426 while (ISDIGIT (*s));
10429 c = 8; /* Invalid sel value. */
10432 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10433 ip->insn_opcode |= c;
10437 /* Must be at least one digit. */
10438 my_getExpression (&imm_expr, s);
10439 check_absolute_expr (ip, &imm_expr);
10441 if ((unsigned long) imm_expr.X_add_number
10442 > (unsigned long) OP_MASK_VECBYTE)
10444 as_bad (_("bad byte vector index (%ld)"),
10445 (long) imm_expr.X_add_number);
10446 imm_expr.X_add_number = 0;
10449 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10450 imm_expr.X_op = O_absent;
10455 my_getExpression (&imm_expr, s);
10456 check_absolute_expr (ip, &imm_expr);
10458 if ((unsigned long) imm_expr.X_add_number
10459 > (unsigned long) OP_MASK_VECALIGN)
10461 as_bad (_("bad byte vector index (%ld)"),
10462 (long) imm_expr.X_add_number);
10463 imm_expr.X_add_number = 0;
10466 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10467 imm_expr.X_op = O_absent;
10472 as_bad (_("Bad char = '%c'\n"), *args);
10477 /* Args don't match. */
10478 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10479 !strcmp (insn->name, insn[1].name))
10483 insn_error = _("Illegal operands");
10487 *(--argsStart) = save_c;
10488 insn_error = _("Illegal operands");
10493 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10495 /* This routine assembles an instruction into its binary format when
10496 assembling for the mips16. As a side effect, it sets one of the
10497 global variables imm_reloc or offset_reloc to the type of
10498 relocation to do if one of the operands is an address expression.
10499 It also sets mips16_small and mips16_ext if the user explicitly
10500 requested a small or extended instruction. */
10503 mips16_ip (char *str, struct mips_cl_insn *ip)
10507 struct mips_opcode *insn;
10509 unsigned int regno;
10510 unsigned int lastregno = 0;
10516 mips16_small = FALSE;
10517 mips16_ext = FALSE;
10519 for (s = str; ISLOWER (*s); ++s)
10531 if (s[1] == 't' && s[2] == ' ')
10534 mips16_small = TRUE;
10538 else if (s[1] == 'e' && s[2] == ' ')
10545 /* Fall through. */
10547 insn_error = _("unknown opcode");
10551 if (mips_opts.noautoextend && ! mips16_ext)
10552 mips16_small = TRUE;
10554 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10556 insn_error = _("unrecognized opcode");
10565 gas_assert (strcmp (insn->name, str) == 0);
10567 ok = is_opcode_valid_16 (insn);
10570 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10571 && strcmp (insn->name, insn[1].name) == 0)
10580 static char buf[100];
10582 _("opcode not supported on this processor: %s (%s)"),
10583 mips_cpu_info_from_arch (mips_opts.arch)->name,
10584 mips_cpu_info_from_isa (mips_opts.isa)->name);
10591 create_insn (ip, insn);
10592 imm_expr.X_op = O_absent;
10593 imm_reloc[0] = BFD_RELOC_UNUSED;
10594 imm_reloc[1] = BFD_RELOC_UNUSED;
10595 imm_reloc[2] = BFD_RELOC_UNUSED;
10596 imm2_expr.X_op = O_absent;
10597 offset_expr.X_op = O_absent;
10598 offset_reloc[0] = BFD_RELOC_UNUSED;
10599 offset_reloc[1] = BFD_RELOC_UNUSED;
10600 offset_reloc[2] = BFD_RELOC_UNUSED;
10601 for (args = insn->args; 1; ++args)
10608 /* In this switch statement we call break if we did not find
10609 a match, continue if we did find a match, or return if we
10618 /* Stuff the immediate value in now, if we can. */
10619 if (imm_expr.X_op == O_constant
10620 && *imm_reloc > BFD_RELOC_UNUSED
10621 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10622 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10623 && insn->pinfo != INSN_MACRO)
10627 switch (*offset_reloc)
10629 case BFD_RELOC_MIPS16_HI16_S:
10630 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10633 case BFD_RELOC_MIPS16_HI16:
10634 tmp = imm_expr.X_add_number >> 16;
10637 case BFD_RELOC_MIPS16_LO16:
10638 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10642 case BFD_RELOC_UNUSED:
10643 tmp = imm_expr.X_add_number;
10649 *offset_reloc = BFD_RELOC_UNUSED;
10651 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10652 tmp, TRUE, mips16_small,
10653 mips16_ext, &ip->insn_opcode,
10654 &ip->use_extend, &ip->extend);
10655 imm_expr.X_op = O_absent;
10656 *imm_reloc = BFD_RELOC_UNUSED;
10670 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10673 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10689 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10691 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10695 /* Fall through. */
10706 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
10708 if (c == 'v' || c == 'w')
10711 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10713 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10724 if (c == 'v' || c == 'w')
10726 regno = mips16_to_32_reg_map[lastregno];
10740 regno = mips32_to_16_reg_map[regno];
10745 regno = ILLEGAL_REG;
10750 regno = ILLEGAL_REG;
10755 regno = ILLEGAL_REG;
10760 if (regno == AT && mips_opts.at)
10762 if (mips_opts.at == ATREG)
10763 as_warn (_("used $at without \".set noat\""));
10765 as_warn (_("used $%u with \".set at=$%u\""),
10766 regno, mips_opts.at);
10774 if (regno == ILLEGAL_REG)
10781 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10785 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10788 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10791 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10797 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10800 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10801 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10811 if (strncmp (s, "$pc", 3) == 0)
10828 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10831 if (imm_expr.X_op != O_constant)
10834 ip->use_extend = TRUE;
10839 /* We need to relax this instruction. */
10840 *offset_reloc = *imm_reloc;
10841 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10846 *imm_reloc = BFD_RELOC_UNUSED;
10847 /* Fall through. */
10854 my_getExpression (&imm_expr, s);
10855 if (imm_expr.X_op == O_register)
10857 /* What we thought was an expression turned out to
10860 if (s[0] == '(' && args[1] == '(')
10862 /* It looks like the expression was omitted
10863 before a register indirection, which means
10864 that the expression is implicitly zero. We
10865 still set up imm_expr, so that we handle
10866 explicit extensions correctly. */
10867 imm_expr.X_op = O_constant;
10868 imm_expr.X_add_number = 0;
10869 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10876 /* We need to relax this instruction. */
10877 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10886 /* We use offset_reloc rather than imm_reloc for the PC
10887 relative operands. This lets macros with both
10888 immediate and address operands work correctly. */
10889 my_getExpression (&offset_expr, s);
10891 if (offset_expr.X_op == O_register)
10894 /* We need to relax this instruction. */
10895 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10899 case '6': /* break code */
10900 my_getExpression (&imm_expr, s);
10901 check_absolute_expr (ip, &imm_expr);
10902 if ((unsigned long) imm_expr.X_add_number > 63)
10903 as_warn (_("Invalid value for `%s' (%lu)"),
10905 (unsigned long) imm_expr.X_add_number);
10906 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10907 imm_expr.X_op = O_absent;
10911 case 'a': /* 26 bit address */
10912 my_getExpression (&offset_expr, s);
10914 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10915 ip->insn_opcode <<= 16;
10918 case 'l': /* register list for entry macro */
10919 case 'L': /* register list for exit macro */
10929 unsigned int freg, reg1, reg2;
10931 while (*s == ' ' || *s == ',')
10933 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
10935 else if (reg_lookup (&s, RTYPE_FPU, ®1))
10939 as_bad (_("can't parse register list"));
10949 if (!reg_lookup (&s, freg ? RTYPE_FPU
10950 : (RTYPE_GP | RTYPE_NUM), ®2))
10952 as_bad (_("invalid register list"));
10956 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10958 mask &= ~ (7 << 3);
10961 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10963 mask &= ~ (7 << 3);
10966 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10967 mask |= (reg2 - 3) << 3;
10968 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10969 mask |= (reg2 - 15) << 1;
10970 else if (reg1 == RA && reg2 == RA)
10974 as_bad (_("invalid register list"));
10978 /* The mask is filled in in the opcode table for the
10979 benefit of the disassembler. We remove it before
10980 applying the actual mask. */
10981 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10982 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10986 case 'm': /* Register list for save insn. */
10987 case 'M': /* Register list for restore insn. */
10990 int framesz = 0, seen_framesz = 0;
10991 int nargs = 0, statics = 0, sregs = 0;
10995 unsigned int reg1, reg2;
10997 SKIP_SPACE_TABS (s);
11000 SKIP_SPACE_TABS (s);
11002 my_getExpression (&imm_expr, s);
11003 if (imm_expr.X_op == O_constant)
11005 /* Handle the frame size. */
11008 as_bad (_("more than one frame size in list"));
11012 framesz = imm_expr.X_add_number;
11013 imm_expr.X_op = O_absent;
11018 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
11020 as_bad (_("can't parse register list"));
11032 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
11035 as_bad (_("can't parse register list"));
11040 while (reg1 <= reg2)
11042 if (reg1 >= 4 && reg1 <= 7)
11046 nargs |= 1 << (reg1 - 4);
11048 /* statics $a0-$a3 */
11049 statics |= 1 << (reg1 - 4);
11051 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11054 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11056 else if (reg1 == 31)
11058 /* Add $ra to insn. */
11063 as_bad (_("unexpected register in list"));
11071 /* Encode args/statics combination. */
11072 if (nargs & statics)
11073 as_bad (_("arg/static registers overlap"));
11074 else if (nargs == 0xf)
11075 /* All $a0-$a3 are args. */
11076 opcode |= MIPS16_ALL_ARGS << 16;
11077 else if (statics == 0xf)
11078 /* All $a0-$a3 are statics. */
11079 opcode |= MIPS16_ALL_STATICS << 16;
11082 int narg = 0, nstat = 0;
11084 /* Count arg registers. */
11085 while (nargs & 0x1)
11091 as_bad (_("invalid arg register list"));
11093 /* Count static registers. */
11094 while (statics & 0x8)
11096 statics = (statics << 1) & 0xf;
11100 as_bad (_("invalid static register list"));
11102 /* Encode args/statics. */
11103 opcode |= ((narg << 2) | nstat) << 16;
11106 /* Encode $s0/$s1. */
11107 if (sregs & (1 << 0)) /* $s0 */
11109 if (sregs & (1 << 1)) /* $s1 */
11115 /* Count regs $s2-$s8. */
11123 as_bad (_("invalid static register list"));
11124 /* Encode $s2-$s8. */
11125 opcode |= nsreg << 24;
11128 /* Encode frame size. */
11130 as_bad (_("missing frame size"));
11131 else if ((framesz & 7) != 0 || framesz < 0
11132 || framesz > 0xff * 8)
11133 as_bad (_("invalid frame size"));
11134 else if (framesz != 128 || (opcode >> 16) != 0)
11137 opcode |= (((framesz & 0xf0) << 16)
11138 | (framesz & 0x0f));
11141 /* Finally build the instruction. */
11142 if ((opcode >> 16) != 0 || framesz == 0)
11144 ip->use_extend = TRUE;
11145 ip->extend = opcode >> 16;
11147 ip->insn_opcode |= opcode & 0x7f;
11151 case 'e': /* extend code */
11152 my_getExpression (&imm_expr, s);
11153 check_absolute_expr (ip, &imm_expr);
11154 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11156 as_warn (_("Invalid value for `%s' (%lu)"),
11158 (unsigned long) imm_expr.X_add_number);
11159 imm_expr.X_add_number &= 0x7ff;
11161 ip->insn_opcode |= imm_expr.X_add_number;
11162 imm_expr.X_op = O_absent;
11172 /* Args don't match. */
11173 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11174 strcmp (insn->name, insn[1].name) == 0)
11181 insn_error = _("illegal operands");
11187 /* This structure holds information we know about a mips16 immediate
11190 struct mips16_immed_operand
11192 /* The type code used in the argument string in the opcode table. */
11194 /* The number of bits in the short form of the opcode. */
11196 /* The number of bits in the extended form of the opcode. */
11198 /* The amount by which the short form is shifted when it is used;
11199 for example, the sw instruction has a shift count of 2. */
11201 /* The amount by which the short form is shifted when it is stored
11202 into the instruction code. */
11204 /* Non-zero if the short form is unsigned. */
11206 /* Non-zero if the extended form is unsigned. */
11208 /* Non-zero if the value is PC relative. */
11212 /* The mips16 immediate operand types. */
11214 static const struct mips16_immed_operand mips16_immed_operands[] =
11216 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11217 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11218 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11219 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11220 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11221 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11222 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11223 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11224 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11225 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11226 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11227 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11228 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11229 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11230 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11231 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11232 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11233 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11234 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11235 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11236 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11239 #define MIPS16_NUM_IMMED \
11240 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11242 /* Handle a mips16 instruction with an immediate value. This or's the
11243 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11244 whether an extended value is needed; if one is needed, it sets
11245 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11246 If SMALL is true, an unextended opcode was explicitly requested.
11247 If EXT is true, an extended opcode was explicitly requested. If
11248 WARN is true, warn if EXT does not match reality. */
11251 mips16_immed (char *file, unsigned int line, int type, offsetT val,
11252 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11253 unsigned long *insn, bfd_boolean *use_extend,
11254 unsigned short *extend)
11256 const struct mips16_immed_operand *op;
11257 int mintiny, maxtiny;
11258 bfd_boolean needext;
11260 op = mips16_immed_operands;
11261 while (op->type != type)
11264 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11269 if (type == '<' || type == '>' || type == '[' || type == ']')
11272 maxtiny = 1 << op->nbits;
11277 maxtiny = (1 << op->nbits) - 1;
11282 mintiny = - (1 << (op->nbits - 1));
11283 maxtiny = (1 << (op->nbits - 1)) - 1;
11286 /* Branch offsets have an implicit 0 in the lowest bit. */
11287 if (type == 'p' || type == 'q')
11290 if ((val & ((1 << op->shift) - 1)) != 0
11291 || val < (mintiny << op->shift)
11292 || val > (maxtiny << op->shift))
11297 if (warn && ext && ! needext)
11298 as_warn_where (file, line,
11299 _("extended operand requested but not required"));
11300 if (small && needext)
11301 as_bad_where (file, line, _("invalid unextended operand value"));
11303 if (small || (! ext && ! needext))
11307 *use_extend = FALSE;
11308 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11309 insnval <<= op->op_shift;
11314 long minext, maxext;
11320 maxext = (1 << op->extbits) - 1;
11324 minext = - (1 << (op->extbits - 1));
11325 maxext = (1 << (op->extbits - 1)) - 1;
11327 if (val < minext || val > maxext)
11328 as_bad_where (file, line,
11329 _("operand value out of range for instruction"));
11331 *use_extend = TRUE;
11332 if (op->extbits == 16)
11334 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11337 else if (op->extbits == 15)
11339 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11344 extval = ((val & 0x1f) << 6) | (val & 0x20);
11348 *extend = (unsigned short) extval;
11353 struct percent_op_match
11356 bfd_reloc_code_real_type reloc;
11359 static const struct percent_op_match mips_percent_op[] =
11361 {"%lo", BFD_RELOC_LO16},
11363 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11364 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11365 {"%call16", BFD_RELOC_MIPS_CALL16},
11366 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11367 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11368 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11369 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11370 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11371 {"%got", BFD_RELOC_MIPS_GOT16},
11372 {"%gp_rel", BFD_RELOC_GPREL16},
11373 {"%half", BFD_RELOC_16},
11374 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11375 {"%higher", BFD_RELOC_MIPS_HIGHER},
11376 {"%neg", BFD_RELOC_MIPS_SUB},
11377 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11378 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11379 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11380 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11381 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11382 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11383 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11385 {"%hi", BFD_RELOC_HI16_S}
11388 static const struct percent_op_match mips16_percent_op[] =
11390 {"%lo", BFD_RELOC_MIPS16_LO16},
11391 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11392 {"%got", BFD_RELOC_MIPS16_GOT16},
11393 {"%call16", BFD_RELOC_MIPS16_CALL16},
11394 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11398 /* Return true if *STR points to a relocation operator. When returning true,
11399 move *STR over the operator and store its relocation code in *RELOC.
11400 Leave both *STR and *RELOC alone when returning false. */
11403 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11405 const struct percent_op_match *percent_op;
11408 if (mips_opts.mips16)
11410 percent_op = mips16_percent_op;
11411 limit = ARRAY_SIZE (mips16_percent_op);
11415 percent_op = mips_percent_op;
11416 limit = ARRAY_SIZE (mips_percent_op);
11419 for (i = 0; i < limit; i++)
11420 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11422 int len = strlen (percent_op[i].str);
11424 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11427 *str += strlen (percent_op[i].str);
11428 *reloc = percent_op[i].reloc;
11430 /* Check whether the output BFD supports this relocation.
11431 If not, issue an error and fall back on something safe. */
11432 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11434 as_bad (_("relocation %s isn't supported by the current ABI"),
11435 percent_op[i].str);
11436 *reloc = BFD_RELOC_UNUSED;
11444 /* Parse string STR as a 16-bit relocatable operand. Store the
11445 expression in *EP and the relocations in the array starting
11446 at RELOC. Return the number of relocation operators used.
11448 On exit, EXPR_END points to the first character after the expression. */
11451 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11454 bfd_reloc_code_real_type reversed_reloc[3];
11455 size_t reloc_index, i;
11456 int crux_depth, str_depth;
11459 /* Search for the start of the main expression, recoding relocations
11460 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11461 of the main expression and with CRUX_DEPTH containing the number
11462 of open brackets at that point. */
11469 crux_depth = str_depth;
11471 /* Skip over whitespace and brackets, keeping count of the number
11473 while (*str == ' ' || *str == '\t' || *str == '(')
11478 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11479 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11481 my_getExpression (ep, crux);
11484 /* Match every open bracket. */
11485 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11489 if (crux_depth > 0)
11490 as_bad (_("unclosed '('"));
11494 if (reloc_index != 0)
11496 prev_reloc_op_frag = frag_now;
11497 for (i = 0; i < reloc_index; i++)
11498 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11501 return reloc_index;
11505 my_getExpression (expressionS *ep, char *str)
11509 save_in = input_line_pointer;
11510 input_line_pointer = str;
11512 expr_end = input_line_pointer;
11513 input_line_pointer = save_in;
11517 md_atof (int type, char *litP, int *sizeP)
11519 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11523 md_number_to_chars (char *buf, valueT val, int n)
11525 if (target_big_endian)
11526 number_to_chars_bigendian (buf, val, n);
11528 number_to_chars_littleendian (buf, val, n);
11532 static int support_64bit_objects(void)
11534 const char **list, **l;
11537 list = bfd_target_list ();
11538 for (l = list; *l != NULL; l++)
11539 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11540 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11542 yes = (*l != NULL);
11546 #endif /* OBJ_ELF */
11548 const char *md_shortopts = "O::g::G:";
11552 OPTION_MARCH = OPTION_MD_BASE,
11574 OPTION_NO_SMARTMIPS,
11577 OPTION_COMPAT_ARCH_BASE,
11586 OPTION_M7000_HILO_FIX,
11587 OPTION_MNO_7000_HILO_FIX,
11590 OPTION_FIX_LOONGSON2F_JUMP,
11591 OPTION_NO_FIX_LOONGSON2F_JUMP,
11592 OPTION_FIX_LOONGSON2F_NOP,
11593 OPTION_NO_FIX_LOONGSON2F_NOP,
11595 OPTION_NO_FIX_VR4120,
11597 OPTION_NO_FIX_VR4130,
11598 OPTION_FIX_CN63XXP1,
11599 OPTION_NO_FIX_CN63XXP1,
11606 OPTION_CONSTRUCT_FLOATS,
11607 OPTION_NO_CONSTRUCT_FLOATS,
11610 OPTION_RELAX_BRANCH,
11611 OPTION_NO_RELAX_BRANCH,
11618 OPTION_SINGLE_FLOAT,
11619 OPTION_DOUBLE_FLOAT,
11622 OPTION_CALL_SHARED,
11623 OPTION_CALL_NONPIC,
11633 OPTION_MVXWORKS_PIC,
11634 #endif /* OBJ_ELF */
11638 struct option md_longopts[] =
11640 /* Options which specify architecture. */
11641 {"march", required_argument, NULL, OPTION_MARCH},
11642 {"mtune", required_argument, NULL, OPTION_MTUNE},
11643 {"mips0", no_argument, NULL, OPTION_MIPS1},
11644 {"mips1", no_argument, NULL, OPTION_MIPS1},
11645 {"mips2", no_argument, NULL, OPTION_MIPS2},
11646 {"mips3", no_argument, NULL, OPTION_MIPS3},
11647 {"mips4", no_argument, NULL, OPTION_MIPS4},
11648 {"mips5", no_argument, NULL, OPTION_MIPS5},
11649 {"mips32", no_argument, NULL, OPTION_MIPS32},
11650 {"mips64", no_argument, NULL, OPTION_MIPS64},
11651 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11652 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11654 /* Options which specify Application Specific Extensions (ASEs). */
11655 {"mips16", no_argument, NULL, OPTION_MIPS16},
11656 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11657 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11658 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11659 {"mdmx", no_argument, NULL, OPTION_MDMX},
11660 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11661 {"mdsp", no_argument, NULL, OPTION_DSP},
11662 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11663 {"mmt", no_argument, NULL, OPTION_MT},
11664 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11665 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11666 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11667 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11668 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11670 /* Old-style architecture options. Don't add more of these. */
11671 {"m4650", no_argument, NULL, OPTION_M4650},
11672 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11673 {"m4010", no_argument, NULL, OPTION_M4010},
11674 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11675 {"m4100", no_argument, NULL, OPTION_M4100},
11676 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11677 {"m3900", no_argument, NULL, OPTION_M3900},
11678 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11680 /* Options which enable bug fixes. */
11681 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11682 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11683 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11684 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11685 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11686 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11687 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11688 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11689 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11690 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11691 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11692 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11693 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11694 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11695 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11697 /* Miscellaneous options. */
11698 {"trap", no_argument, NULL, OPTION_TRAP},
11699 {"no-break", no_argument, NULL, OPTION_TRAP},
11700 {"break", no_argument, NULL, OPTION_BREAK},
11701 {"no-trap", no_argument, NULL, OPTION_BREAK},
11702 {"EB", no_argument, NULL, OPTION_EB},
11703 {"EL", no_argument, NULL, OPTION_EL},
11704 {"mfp32", no_argument, NULL, OPTION_FP32},
11705 {"mgp32", no_argument, NULL, OPTION_GP32},
11706 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11707 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11708 {"mfp64", no_argument, NULL, OPTION_FP64},
11709 {"mgp64", no_argument, NULL, OPTION_GP64},
11710 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11711 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11712 {"mshared", no_argument, NULL, OPTION_MSHARED},
11713 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11714 {"msym32", no_argument, NULL, OPTION_MSYM32},
11715 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11716 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11717 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11718 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11719 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11721 /* Strictly speaking this next option is ELF specific,
11722 but we allow it for other ports as well in order to
11723 make testing easier. */
11724 {"32", no_argument, NULL, OPTION_32},
11726 /* ELF-specific options. */
11728 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11729 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11730 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11731 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11732 {"xgot", no_argument, NULL, OPTION_XGOT},
11733 {"mabi", required_argument, NULL, OPTION_MABI},
11734 {"n32", no_argument, NULL, OPTION_N32},
11735 {"64", no_argument, NULL, OPTION_64},
11736 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11737 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11738 {"mpdr", no_argument, NULL, OPTION_PDR},
11739 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11740 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11741 #endif /* OBJ_ELF */
11743 {NULL, no_argument, NULL, 0}
11745 size_t md_longopts_size = sizeof (md_longopts);
11747 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11748 NEW_VALUE. Warn if another value was already specified. Note:
11749 we have to defer parsing the -march and -mtune arguments in order
11750 to handle 'from-abi' correctly, since the ABI might be specified
11751 in a later argument. */
11754 mips_set_option_string (const char **string_ptr, const char *new_value)
11756 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11757 as_warn (_("A different %s was already specified, is now %s"),
11758 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11761 *string_ptr = new_value;
11765 md_parse_option (int c, char *arg)
11769 case OPTION_CONSTRUCT_FLOATS:
11770 mips_disable_float_construction = 0;
11773 case OPTION_NO_CONSTRUCT_FLOATS:
11774 mips_disable_float_construction = 1;
11786 target_big_endian = 1;
11790 target_big_endian = 0;
11796 else if (arg[0] == '0')
11798 else if (arg[0] == '1')
11808 mips_debug = atoi (arg);
11812 file_mips_isa = ISA_MIPS1;
11816 file_mips_isa = ISA_MIPS2;
11820 file_mips_isa = ISA_MIPS3;
11824 file_mips_isa = ISA_MIPS4;
11828 file_mips_isa = ISA_MIPS5;
11831 case OPTION_MIPS32:
11832 file_mips_isa = ISA_MIPS32;
11835 case OPTION_MIPS32R2:
11836 file_mips_isa = ISA_MIPS32R2;
11839 case OPTION_MIPS64R2:
11840 file_mips_isa = ISA_MIPS64R2;
11843 case OPTION_MIPS64:
11844 file_mips_isa = ISA_MIPS64;
11848 mips_set_option_string (&mips_tune_string, arg);
11852 mips_set_option_string (&mips_arch_string, arg);
11856 mips_set_option_string (&mips_arch_string, "4650");
11857 mips_set_option_string (&mips_tune_string, "4650");
11860 case OPTION_NO_M4650:
11864 mips_set_option_string (&mips_arch_string, "4010");
11865 mips_set_option_string (&mips_tune_string, "4010");
11868 case OPTION_NO_M4010:
11872 mips_set_option_string (&mips_arch_string, "4100");
11873 mips_set_option_string (&mips_tune_string, "4100");
11876 case OPTION_NO_M4100:
11880 mips_set_option_string (&mips_arch_string, "3900");
11881 mips_set_option_string (&mips_tune_string, "3900");
11884 case OPTION_NO_M3900:
11888 mips_opts.ase_mdmx = 1;
11891 case OPTION_NO_MDMX:
11892 mips_opts.ase_mdmx = 0;
11896 mips_opts.ase_dsp = 1;
11897 mips_opts.ase_dspr2 = 0;
11900 case OPTION_NO_DSP:
11901 mips_opts.ase_dsp = 0;
11902 mips_opts.ase_dspr2 = 0;
11906 mips_opts.ase_dspr2 = 1;
11907 mips_opts.ase_dsp = 1;
11910 case OPTION_NO_DSPR2:
11911 mips_opts.ase_dspr2 = 0;
11912 mips_opts.ase_dsp = 0;
11916 mips_opts.ase_mt = 1;
11920 mips_opts.ase_mt = 0;
11923 case OPTION_MIPS16:
11924 mips_opts.mips16 = 1;
11925 mips_no_prev_insn ();
11928 case OPTION_NO_MIPS16:
11929 mips_opts.mips16 = 0;
11930 mips_no_prev_insn ();
11933 case OPTION_MIPS3D:
11934 mips_opts.ase_mips3d = 1;
11937 case OPTION_NO_MIPS3D:
11938 mips_opts.ase_mips3d = 0;
11941 case OPTION_SMARTMIPS:
11942 mips_opts.ase_smartmips = 1;
11945 case OPTION_NO_SMARTMIPS:
11946 mips_opts.ase_smartmips = 0;
11949 case OPTION_FIX_24K:
11953 case OPTION_NO_FIX_24K:
11957 case OPTION_FIX_LOONGSON2F_JUMP:
11958 mips_fix_loongson2f_jump = TRUE;
11961 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11962 mips_fix_loongson2f_jump = FALSE;
11965 case OPTION_FIX_LOONGSON2F_NOP:
11966 mips_fix_loongson2f_nop = TRUE;
11969 case OPTION_NO_FIX_LOONGSON2F_NOP:
11970 mips_fix_loongson2f_nop = FALSE;
11973 case OPTION_FIX_VR4120:
11974 mips_fix_vr4120 = 1;
11977 case OPTION_NO_FIX_VR4120:
11978 mips_fix_vr4120 = 0;
11981 case OPTION_FIX_VR4130:
11982 mips_fix_vr4130 = 1;
11985 case OPTION_NO_FIX_VR4130:
11986 mips_fix_vr4130 = 0;
11989 case OPTION_FIX_CN63XXP1:
11990 mips_fix_cn63xxp1 = TRUE;
11993 case OPTION_NO_FIX_CN63XXP1:
11994 mips_fix_cn63xxp1 = FALSE;
11997 case OPTION_RELAX_BRANCH:
11998 mips_relax_branch = 1;
12001 case OPTION_NO_RELAX_BRANCH:
12002 mips_relax_branch = 0;
12005 case OPTION_MSHARED:
12006 mips_in_shared = TRUE;
12009 case OPTION_MNO_SHARED:
12010 mips_in_shared = FALSE;
12013 case OPTION_MSYM32:
12014 mips_opts.sym32 = TRUE;
12017 case OPTION_MNO_SYM32:
12018 mips_opts.sym32 = FALSE;
12022 /* When generating ELF code, we permit -KPIC and -call_shared to
12023 select SVR4_PIC, and -non_shared to select no PIC. This is
12024 intended to be compatible with Irix 5. */
12025 case OPTION_CALL_SHARED:
12028 as_bad (_("-call_shared is supported only for ELF format"));
12031 mips_pic = SVR4_PIC;
12032 mips_abicalls = TRUE;
12035 case OPTION_CALL_NONPIC:
12038 as_bad (_("-call_nonpic is supported only for ELF format"));
12042 mips_abicalls = TRUE;
12045 case OPTION_NON_SHARED:
12048 as_bad (_("-non_shared is supported only for ELF format"));
12052 mips_abicalls = FALSE;
12055 /* The -xgot option tells the assembler to use 32 bit offsets
12056 when accessing the got in SVR4_PIC mode. It is for Irix
12061 #endif /* OBJ_ELF */
12064 g_switch_value = atoi (arg);
12068 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12072 mips_abi = O32_ABI;
12073 /* We silently ignore -32 for non-ELF targets. This greatly
12074 simplifies the construction of the MIPS GAS test cases. */
12081 as_bad (_("-n32 is supported for ELF format only"));
12084 mips_abi = N32_ABI;
12090 as_bad (_("-64 is supported for ELF format only"));
12093 mips_abi = N64_ABI;
12094 if (!support_64bit_objects())
12095 as_fatal (_("No compiled in support for 64 bit object file format"));
12097 #endif /* OBJ_ELF */
12100 file_mips_gp32 = 1;
12104 file_mips_gp32 = 0;
12108 file_mips_fp32 = 1;
12112 file_mips_fp32 = 0;
12115 case OPTION_SINGLE_FLOAT:
12116 file_mips_single_float = 1;
12119 case OPTION_DOUBLE_FLOAT:
12120 file_mips_single_float = 0;
12123 case OPTION_SOFT_FLOAT:
12124 file_mips_soft_float = 1;
12127 case OPTION_HARD_FLOAT:
12128 file_mips_soft_float = 0;
12135 as_bad (_("-mabi is supported for ELF format only"));
12138 if (strcmp (arg, "32") == 0)
12139 mips_abi = O32_ABI;
12140 else if (strcmp (arg, "o64") == 0)
12141 mips_abi = O64_ABI;
12142 else if (strcmp (arg, "n32") == 0)
12143 mips_abi = N32_ABI;
12144 else if (strcmp (arg, "64") == 0)
12146 mips_abi = N64_ABI;
12147 if (! support_64bit_objects())
12148 as_fatal (_("No compiled in support for 64 bit object file "
12151 else if (strcmp (arg, "eabi") == 0)
12152 mips_abi = EABI_ABI;
12155 as_fatal (_("invalid abi -mabi=%s"), arg);
12159 #endif /* OBJ_ELF */
12161 case OPTION_M7000_HILO_FIX:
12162 mips_7000_hilo_fix = TRUE;
12165 case OPTION_MNO_7000_HILO_FIX:
12166 mips_7000_hilo_fix = FALSE;
12170 case OPTION_MDEBUG:
12171 mips_flag_mdebug = TRUE;
12174 case OPTION_NO_MDEBUG:
12175 mips_flag_mdebug = FALSE;
12179 mips_flag_pdr = TRUE;
12182 case OPTION_NO_PDR:
12183 mips_flag_pdr = FALSE;
12186 case OPTION_MVXWORKS_PIC:
12187 mips_pic = VXWORKS_PIC;
12189 #endif /* OBJ_ELF */
12195 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12200 /* Set up globals to generate code for the ISA or processor
12201 described by INFO. */
12204 mips_set_architecture (const struct mips_cpu_info *info)
12208 file_mips_arch = info->cpu;
12209 mips_opts.arch = info->cpu;
12210 mips_opts.isa = info->isa;
12215 /* Likewise for tuning. */
12218 mips_set_tune (const struct mips_cpu_info *info)
12221 mips_tune = info->cpu;
12226 mips_after_parse_args (void)
12228 const struct mips_cpu_info *arch_info = 0;
12229 const struct mips_cpu_info *tune_info = 0;
12231 /* GP relative stuff not working for PE */
12232 if (strncmp (TARGET_OS, "pe", 2) == 0)
12234 if (g_switch_seen && g_switch_value != 0)
12235 as_bad (_("-G not supported in this configuration."));
12236 g_switch_value = 0;
12239 if (mips_abi == NO_ABI)
12240 mips_abi = MIPS_DEFAULT_ABI;
12242 /* The following code determines the architecture and register size.
12243 Similar code was added to GCC 3.3 (see override_options() in
12244 config/mips/mips.c). The GAS and GCC code should be kept in sync
12245 as much as possible. */
12247 if (mips_arch_string != 0)
12248 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12250 if (file_mips_isa != ISA_UNKNOWN)
12252 /* Handle -mipsN. At this point, file_mips_isa contains the
12253 ISA level specified by -mipsN, while arch_info->isa contains
12254 the -march selection (if any). */
12255 if (arch_info != 0)
12257 /* -march takes precedence over -mipsN, since it is more descriptive.
12258 There's no harm in specifying both as long as the ISA levels
12260 if (file_mips_isa != arch_info->isa)
12261 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12262 mips_cpu_info_from_isa (file_mips_isa)->name,
12263 mips_cpu_info_from_isa (arch_info->isa)->name);
12266 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12269 if (arch_info == 0)
12270 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12272 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12273 as_bad (_("-march=%s is not compatible with the selected ABI"),
12276 mips_set_architecture (arch_info);
12278 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12279 if (mips_tune_string != 0)
12280 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12282 if (tune_info == 0)
12283 mips_set_tune (arch_info);
12285 mips_set_tune (tune_info);
12287 if (file_mips_gp32 >= 0)
12289 /* The user specified the size of the integer registers. Make sure
12290 it agrees with the ABI and ISA. */
12291 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12292 as_bad (_("-mgp64 used with a 32-bit processor"));
12293 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12294 as_bad (_("-mgp32 used with a 64-bit ABI"));
12295 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12296 as_bad (_("-mgp64 used with a 32-bit ABI"));
12300 /* Infer the integer register size from the ABI and processor.
12301 Restrict ourselves to 32-bit registers if that's all the
12302 processor has, or if the ABI cannot handle 64-bit registers. */
12303 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12304 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12307 switch (file_mips_fp32)
12311 /* No user specified float register size.
12312 ??? GAS treats single-float processors as though they had 64-bit
12313 float registers (although it complains when double-precision
12314 instructions are used). As things stand, saying they have 32-bit
12315 registers would lead to spurious "register must be even" messages.
12316 So here we assume float registers are never smaller than the
12318 if (file_mips_gp32 == 0)
12319 /* 64-bit integer registers implies 64-bit float registers. */
12320 file_mips_fp32 = 0;
12321 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12322 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12323 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12324 file_mips_fp32 = 0;
12326 /* 32-bit float registers. */
12327 file_mips_fp32 = 1;
12330 /* The user specified the size of the float registers. Check if it
12331 agrees with the ABI and ISA. */
12333 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12334 as_bad (_("-mfp64 used with a 32-bit fpu"));
12335 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12336 && !ISA_HAS_MXHC1 (mips_opts.isa))
12337 as_warn (_("-mfp64 used with a 32-bit ABI"));
12340 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12341 as_warn (_("-mfp32 used with a 64-bit ABI"));
12345 /* End of GCC-shared inference code. */
12347 /* This flag is set when we have a 64-bit capable CPU but use only
12348 32-bit wide registers. Note that EABI does not use it. */
12349 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12350 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12351 || mips_abi == O32_ABI))
12352 mips_32bitmode = 1;
12354 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12355 as_bad (_("trap exception not supported at ISA 1"));
12357 /* If the selected architecture includes support for ASEs, enable
12358 generation of code for them. */
12359 if (mips_opts.mips16 == -1)
12360 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12361 if (mips_opts.ase_mips3d == -1)
12362 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12363 && file_mips_fp32 == 0) ? 1 : 0;
12364 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12365 as_bad (_("-mfp32 used with -mips3d"));
12367 if (mips_opts.ase_mdmx == -1)
12368 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12369 && file_mips_fp32 == 0) ? 1 : 0;
12370 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12371 as_bad (_("-mfp32 used with -mdmx"));
12373 if (mips_opts.ase_smartmips == -1)
12374 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12375 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12376 as_warn (_("%s ISA does not support SmartMIPS"),
12377 mips_cpu_info_from_isa (mips_opts.isa)->name);
12379 if (mips_opts.ase_dsp == -1)
12380 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12381 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12382 as_warn (_("%s ISA does not support DSP ASE"),
12383 mips_cpu_info_from_isa (mips_opts.isa)->name);
12385 if (mips_opts.ase_dspr2 == -1)
12387 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12388 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12390 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12391 as_warn (_("%s ISA does not support DSP R2 ASE"),
12392 mips_cpu_info_from_isa (mips_opts.isa)->name);
12394 if (mips_opts.ase_mt == -1)
12395 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12396 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12397 as_warn (_("%s ISA does not support MT ASE"),
12398 mips_cpu_info_from_isa (mips_opts.isa)->name);
12400 file_mips_isa = mips_opts.isa;
12401 file_ase_mips3d = mips_opts.ase_mips3d;
12402 file_ase_mdmx = mips_opts.ase_mdmx;
12403 file_ase_smartmips = mips_opts.ase_smartmips;
12404 file_ase_dsp = mips_opts.ase_dsp;
12405 file_ase_dspr2 = mips_opts.ase_dspr2;
12406 file_ase_mt = mips_opts.ase_mt;
12407 mips_opts.gp32 = file_mips_gp32;
12408 mips_opts.fp32 = file_mips_fp32;
12409 mips_opts.soft_float = file_mips_soft_float;
12410 mips_opts.single_float = file_mips_single_float;
12412 if (mips_flag_mdebug < 0)
12414 #ifdef OBJ_MAYBE_ECOFF
12415 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12416 mips_flag_mdebug = 1;
12418 #endif /* OBJ_MAYBE_ECOFF */
12419 mips_flag_mdebug = 0;
12424 mips_init_after_args (void)
12426 /* initialize opcodes */
12427 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12428 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12432 md_pcrel_from (fixS *fixP)
12434 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12435 switch (fixP->fx_r_type)
12437 case BFD_RELOC_16_PCREL_S2:
12438 case BFD_RELOC_MIPS_JMP:
12439 /* Return the address of the delay slot. */
12442 /* We have no relocation type for PC relative MIPS16 instructions. */
12443 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12444 as_bad_where (fixP->fx_file, fixP->fx_line,
12445 _("PC relative MIPS16 instruction references a different section"));
12450 /* This is called before the symbol table is processed. In order to
12451 work with gcc when using mips-tfile, we must keep all local labels.
12452 However, in other cases, we want to discard them. If we were
12453 called with -g, but we didn't see any debugging information, it may
12454 mean that gcc is smuggling debugging information through to
12455 mips-tfile, in which case we must generate all local labels. */
12458 mips_frob_file_before_adjust (void)
12460 #ifndef NO_ECOFF_DEBUGGING
12461 if (ECOFF_DEBUGGING
12463 && ! ecoff_debugging_seen)
12464 flag_keep_locals = 1;
12468 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12469 the corresponding LO16 reloc. This is called before md_apply_fix and
12470 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12471 relocation operators.
12473 For our purposes, a %lo() expression matches a %got() or %hi()
12476 (a) it refers to the same symbol; and
12477 (b) the offset applied in the %lo() expression is no lower than
12478 the offset applied in the %got() or %hi().
12480 (b) allows us to cope with code like:
12483 lh $4,%lo(foo+2)($4)
12485 ...which is legal on RELA targets, and has a well-defined behaviour
12486 if the user knows that adding 2 to "foo" will not induce a carry to
12489 When several %lo()s match a particular %got() or %hi(), we use the
12490 following rules to distinguish them:
12492 (1) %lo()s with smaller offsets are a better match than %lo()s with
12495 (2) %lo()s with no matching %got() or %hi() are better than those
12496 that already have a matching %got() or %hi().
12498 (3) later %lo()s are better than earlier %lo()s.
12500 These rules are applied in order.
12502 (1) means, among other things, that %lo()s with identical offsets are
12503 chosen if they exist.
12505 (2) means that we won't associate several high-part relocations with
12506 the same low-part relocation unless there's no alternative. Having
12507 several high parts for the same low part is a GNU extension; this rule
12508 allows careful users to avoid it.
12510 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12511 with the last high-part relocation being at the front of the list.
12512 It therefore makes sense to choose the last matching low-part
12513 relocation, all other things being equal. It's also easier
12514 to code that way. */
12517 mips_frob_file (void)
12519 struct mips_hi_fixup *l;
12520 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12522 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12524 segment_info_type *seginfo;
12525 bfd_boolean matched_lo_p;
12526 fixS **hi_pos, **lo_pos, **pos;
12528 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12530 /* If a GOT16 relocation turns out to be against a global symbol,
12531 there isn't supposed to be a matching LO. */
12532 if (got16_reloc_p (l->fixp->fx_r_type)
12533 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12536 /* Check quickly whether the next fixup happens to be a matching %lo. */
12537 if (fixup_has_matching_lo_p (l->fixp))
12540 seginfo = seg_info (l->seg);
12542 /* Set HI_POS to the position of this relocation in the chain.
12543 Set LO_POS to the position of the chosen low-part relocation.
12544 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12545 relocation that matches an immediately-preceding high-part
12549 matched_lo_p = FALSE;
12550 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12552 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12554 if (*pos == l->fixp)
12557 if ((*pos)->fx_r_type == looking_for_rtype
12558 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12559 && (*pos)->fx_offset >= l->fixp->fx_offset
12561 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12563 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12566 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12567 && fixup_has_matching_lo_p (*pos));
12570 /* If we found a match, remove the high-part relocation from its
12571 current position and insert it before the low-part relocation.
12572 Make the offsets match so that fixup_has_matching_lo_p()
12575 We don't warn about unmatched high-part relocations since some
12576 versions of gcc have been known to emit dead "lui ...%hi(...)"
12578 if (lo_pos != NULL)
12580 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12581 if (l->fixp->fx_next != *lo_pos)
12583 *hi_pos = l->fixp->fx_next;
12584 l->fixp->fx_next = *lo_pos;
12591 /* We may have combined relocations without symbols in the N32/N64 ABI.
12592 We have to prevent gas from dropping them. */
12595 mips_force_relocation (fixS *fixp)
12597 if (generic_force_reloc (fixp))
12601 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12602 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12603 || hi16_reloc_p (fixp->fx_r_type)
12604 || lo16_reloc_p (fixp->fx_r_type)))
12610 /* Apply a fixup to the object file. */
12613 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12617 reloc_howto_type *howto;
12619 /* We ignore generic BFD relocations we don't know about. */
12620 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12624 gas_assert (fixP->fx_size == 4
12625 || fixP->fx_r_type == BFD_RELOC_16
12626 || fixP->fx_r_type == BFD_RELOC_64
12627 || fixP->fx_r_type == BFD_RELOC_CTOR
12628 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12629 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12630 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12631 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12633 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12635 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12637 /* Don't treat parts of a composite relocation as done. There are two
12640 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12641 should nevertheless be emitted if the first part is.
12643 (2) In normal usage, composite relocations are never assembly-time
12644 constants. The easiest way of dealing with the pathological
12645 exceptions is to generate a relocation against STN_UNDEF and
12646 leave everything up to the linker. */
12647 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12650 switch (fixP->fx_r_type)
12652 case BFD_RELOC_MIPS_TLS_GD:
12653 case BFD_RELOC_MIPS_TLS_LDM:
12654 case BFD_RELOC_MIPS_TLS_DTPREL32:
12655 case BFD_RELOC_MIPS_TLS_DTPREL64:
12656 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12657 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12658 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12659 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12660 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12661 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12664 case BFD_RELOC_MIPS_JMP:
12665 case BFD_RELOC_MIPS_SHIFT5:
12666 case BFD_RELOC_MIPS_SHIFT6:
12667 case BFD_RELOC_MIPS_GOT_DISP:
12668 case BFD_RELOC_MIPS_GOT_PAGE:
12669 case BFD_RELOC_MIPS_GOT_OFST:
12670 case BFD_RELOC_MIPS_SUB:
12671 case BFD_RELOC_MIPS_INSERT_A:
12672 case BFD_RELOC_MIPS_INSERT_B:
12673 case BFD_RELOC_MIPS_DELETE:
12674 case BFD_RELOC_MIPS_HIGHEST:
12675 case BFD_RELOC_MIPS_HIGHER:
12676 case BFD_RELOC_MIPS_SCN_DISP:
12677 case BFD_RELOC_MIPS_REL16:
12678 case BFD_RELOC_MIPS_RELGOT:
12679 case BFD_RELOC_MIPS_JALR:
12680 case BFD_RELOC_HI16:
12681 case BFD_RELOC_HI16_S:
12682 case BFD_RELOC_GPREL16:
12683 case BFD_RELOC_MIPS_LITERAL:
12684 case BFD_RELOC_MIPS_CALL16:
12685 case BFD_RELOC_MIPS_GOT16:
12686 case BFD_RELOC_GPREL32:
12687 case BFD_RELOC_MIPS_GOT_HI16:
12688 case BFD_RELOC_MIPS_GOT_LO16:
12689 case BFD_RELOC_MIPS_CALL_HI16:
12690 case BFD_RELOC_MIPS_CALL_LO16:
12691 case BFD_RELOC_MIPS16_GPREL:
12692 case BFD_RELOC_MIPS16_GOT16:
12693 case BFD_RELOC_MIPS16_CALL16:
12694 case BFD_RELOC_MIPS16_HI16:
12695 case BFD_RELOC_MIPS16_HI16_S:
12696 case BFD_RELOC_MIPS16_JMP:
12697 /* Nothing needed to do. The value comes from the reloc entry. */
12701 /* This is handled like BFD_RELOC_32, but we output a sign
12702 extended value if we are only 32 bits. */
12705 if (8 <= sizeof (valueT))
12706 md_number_to_chars ((char *) buf, *valP, 8);
12711 if ((*valP & 0x80000000) != 0)
12715 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12717 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12723 case BFD_RELOC_RVA:
12726 /* If we are deleting this reloc entry, we must fill in the
12727 value now. This can happen if we have a .word which is not
12728 resolved when it appears but is later defined. */
12730 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12733 case BFD_RELOC_LO16:
12734 case BFD_RELOC_MIPS16_LO16:
12735 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12736 may be safe to remove, but if so it's not obvious. */
12737 /* When handling an embedded PIC switch statement, we can wind
12738 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12741 if (*valP + 0x8000 > 0xffff)
12742 as_bad_where (fixP->fx_file, fixP->fx_line,
12743 _("relocation overflow"));
12744 if (target_big_endian)
12746 md_number_to_chars ((char *) buf, *valP, 2);
12750 case BFD_RELOC_16_PCREL_S2:
12751 if ((*valP & 0x3) != 0)
12752 as_bad_where (fixP->fx_file, fixP->fx_line,
12753 _("Branch to misaligned address (%lx)"), (long) *valP);
12755 /* We need to save the bits in the instruction since fixup_segment()
12756 might be deleting the relocation entry (i.e., a branch within
12757 the current segment). */
12758 if (! fixP->fx_done)
12761 /* Update old instruction data. */
12762 if (target_big_endian)
12763 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12765 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12767 if (*valP + 0x20000 <= 0x3ffff)
12769 insn |= (*valP >> 2) & 0xffff;
12770 md_number_to_chars ((char *) buf, insn, 4);
12772 else if (mips_pic == NO_PIC
12774 && fixP->fx_frag->fr_address >= text_section->vma
12775 && (fixP->fx_frag->fr_address
12776 < text_section->vma + bfd_get_section_size (text_section))
12777 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12778 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12779 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12781 /* The branch offset is too large. If this is an
12782 unconditional branch, and we are not generating PIC code,
12783 we can convert it to an absolute jump instruction. */
12784 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12785 insn = 0x0c000000; /* jal */
12787 insn = 0x08000000; /* j */
12788 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12790 fixP->fx_addsy = section_symbol (text_section);
12791 *valP += md_pcrel_from (fixP);
12792 md_number_to_chars ((char *) buf, insn, 4);
12796 /* If we got here, we have branch-relaxation disabled,
12797 and there's nothing we can do to fix this instruction
12798 without turning it into a longer sequence. */
12799 as_bad_where (fixP->fx_file, fixP->fx_line,
12800 _("Branch out of range"));
12804 case BFD_RELOC_VTABLE_INHERIT:
12807 && !S_IS_DEFINED (fixP->fx_addsy)
12808 && !S_IS_WEAK (fixP->fx_addsy))
12809 S_SET_WEAK (fixP->fx_addsy);
12812 case BFD_RELOC_VTABLE_ENTRY:
12820 /* Remember value for tc_gen_reloc. */
12821 fixP->fx_addnumber = *valP;
12831 name = input_line_pointer;
12832 c = get_symbol_end ();
12833 p = (symbolS *) symbol_find_or_make (name);
12834 *input_line_pointer = c;
12838 /* Align the current frag to a given power of two. If a particular
12839 fill byte should be used, FILL points to an integer that contains
12840 that byte, otherwise FILL is null.
12842 The MIPS assembler also automatically adjusts any preceding
12846 mips_align (int to, int *fill, symbolS *label)
12848 mips_emit_delays ();
12849 mips_record_mips16_mode ();
12850 if (fill == NULL && subseg_text_p (now_seg))
12851 frag_align_code (to, 0);
12853 frag_align (to, fill ? *fill : 0, 0);
12854 record_alignment (now_seg, to);
12857 gas_assert (S_GET_SEGMENT (label) == now_seg);
12858 symbol_set_frag (label, frag_now);
12859 S_SET_VALUE (label, (valueT) frag_now_fix ());
12863 /* Align to a given power of two. .align 0 turns off the automatic
12864 alignment used by the data creating pseudo-ops. */
12867 s_align (int x ATTRIBUTE_UNUSED)
12869 int temp, fill_value, *fill_ptr;
12870 long max_alignment = 28;
12872 /* o Note that the assembler pulls down any immediately preceding label
12873 to the aligned address.
12874 o It's not documented but auto alignment is reinstated by
12875 a .align pseudo instruction.
12876 o Note also that after auto alignment is turned off the mips assembler
12877 issues an error on attempt to assemble an improperly aligned data item.
12880 temp = get_absolute_expression ();
12881 if (temp > max_alignment)
12882 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12885 as_warn (_("Alignment negative: 0 assumed."));
12888 if (*input_line_pointer == ',')
12890 ++input_line_pointer;
12891 fill_value = get_absolute_expression ();
12892 fill_ptr = &fill_value;
12898 segment_info_type *si = seg_info (now_seg);
12899 struct insn_label_list *l = si->label_list;
12900 /* Auto alignment should be switched on by next section change. */
12902 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12909 demand_empty_rest_of_line ();
12913 s_change_sec (int sec)
12918 /* The ELF backend needs to know that we are changing sections, so
12919 that .previous works correctly. We could do something like check
12920 for an obj_section_change_hook macro, but that might be confusing
12921 as it would not be appropriate to use it in the section changing
12922 functions in read.c, since obj-elf.c intercepts those. FIXME:
12923 This should be cleaner, somehow. */
12925 obj_elf_section_change_hook ();
12928 mips_emit_delays ();
12939 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12940 demand_empty_rest_of_line ();
12944 seg = subseg_new (RDATA_SECTION_NAME,
12945 (subsegT) get_absolute_expression ());
12948 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12949 | SEC_READONLY | SEC_RELOC
12951 if (strncmp (TARGET_OS, "elf", 3) != 0)
12952 record_alignment (seg, 4);
12954 demand_empty_rest_of_line ();
12958 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12961 bfd_set_section_flags (stdoutput, seg,
12962 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12963 if (strncmp (TARGET_OS, "elf", 3) != 0)
12964 record_alignment (seg, 4);
12966 demand_empty_rest_of_line ();
12970 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12973 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12974 if (strncmp (TARGET_OS, "elf", 3) != 0)
12975 record_alignment (seg, 4);
12977 demand_empty_rest_of_line ();
12985 s_change_section (int ignore ATTRIBUTE_UNUSED)
12988 char *section_name;
12993 int section_entry_size;
12994 int section_alignment;
12999 section_name = input_line_pointer;
13000 c = get_symbol_end ();
13002 next_c = *(input_line_pointer + 1);
13004 /* Do we have .section Name<,"flags">? */
13005 if (c != ',' || (c == ',' && next_c == '"'))
13007 /* just after name is now '\0'. */
13008 *input_line_pointer = c;
13009 input_line_pointer = section_name;
13010 obj_elf_section (ignore);
13013 input_line_pointer++;
13015 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
13017 section_type = get_absolute_expression ();
13020 if (*input_line_pointer++ == ',')
13021 section_flag = get_absolute_expression ();
13024 if (*input_line_pointer++ == ',')
13025 section_entry_size = get_absolute_expression ();
13027 section_entry_size = 0;
13028 if (*input_line_pointer++ == ',')
13029 section_alignment = get_absolute_expression ();
13031 section_alignment = 0;
13032 /* FIXME: really ignore? */
13033 (void) section_alignment;
13035 section_name = xstrdup (section_name);
13037 /* When using the generic form of .section (as implemented by obj-elf.c),
13038 there's no way to set the section type to SHT_MIPS_DWARF. Users have
13039 traditionally had to fall back on the more common @progbits instead.
13041 There's nothing really harmful in this, since bfd will correct
13042 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13043 means that, for backwards compatibility, the special_section entries
13044 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13046 Even so, we shouldn't force users of the MIPS .section syntax to
13047 incorrectly label the sections as SHT_PROGBITS. The best compromise
13048 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13049 generic type-checking code. */
13050 if (section_type == SHT_MIPS_DWARF)
13051 section_type = SHT_PROGBITS;
13053 obj_elf_change_section (section_name, section_type, section_flag,
13054 section_entry_size, 0, 0, 0);
13056 if (now_seg->name != section_name)
13057 free (section_name);
13058 #endif /* OBJ_ELF */
13062 mips_enable_auto_align (void)
13068 s_cons (int log_size)
13070 segment_info_type *si = seg_info (now_seg);
13071 struct insn_label_list *l = si->label_list;
13074 label = l != NULL ? l->label : NULL;
13075 mips_emit_delays ();
13076 if (log_size > 0 && auto_align)
13077 mips_align (log_size, 0, label);
13078 cons (1 << log_size);
13079 mips_clear_insn_labels ();
13083 s_float_cons (int type)
13085 segment_info_type *si = seg_info (now_seg);
13086 struct insn_label_list *l = si->label_list;
13089 label = l != NULL ? l->label : NULL;
13091 mips_emit_delays ();
13096 mips_align (3, 0, label);
13098 mips_align (2, 0, label);
13102 mips_clear_insn_labels ();
13105 /* Handle .globl. We need to override it because on Irix 5 you are
13108 where foo is an undefined symbol, to mean that foo should be
13109 considered to be the address of a function. */
13112 s_mips_globl (int x ATTRIBUTE_UNUSED)
13121 name = input_line_pointer;
13122 c = get_symbol_end ();
13123 symbolP = symbol_find_or_make (name);
13124 S_SET_EXTERNAL (symbolP);
13126 *input_line_pointer = c;
13127 SKIP_WHITESPACE ();
13129 /* On Irix 5, every global symbol that is not explicitly labelled as
13130 being a function is apparently labelled as being an object. */
13133 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13134 && (*input_line_pointer != ','))
13139 secname = input_line_pointer;
13140 c = get_symbol_end ();
13141 sec = bfd_get_section_by_name (stdoutput, secname);
13143 as_bad (_("%s: no such section"), secname);
13144 *input_line_pointer = c;
13146 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13147 flag = BSF_FUNCTION;
13150 symbol_get_bfdsym (symbolP)->flags |= flag;
13152 c = *input_line_pointer;
13155 input_line_pointer++;
13156 SKIP_WHITESPACE ();
13157 if (is_end_of_line[(unsigned char) *input_line_pointer])
13163 demand_empty_rest_of_line ();
13167 s_option (int x ATTRIBUTE_UNUSED)
13172 opt = input_line_pointer;
13173 c = get_symbol_end ();
13177 /* FIXME: What does this mean? */
13179 else if (strncmp (opt, "pic", 3) == 0)
13183 i = atoi (opt + 3);
13188 mips_pic = SVR4_PIC;
13189 mips_abicalls = TRUE;
13192 as_bad (_(".option pic%d not supported"), i);
13194 if (mips_pic == SVR4_PIC)
13196 if (g_switch_seen && g_switch_value != 0)
13197 as_warn (_("-G may not be used with SVR4 PIC code"));
13198 g_switch_value = 0;
13199 bfd_set_gp_size (stdoutput, 0);
13203 as_warn (_("Unrecognized option \"%s\""), opt);
13205 *input_line_pointer = c;
13206 demand_empty_rest_of_line ();
13209 /* This structure is used to hold a stack of .set values. */
13211 struct mips_option_stack
13213 struct mips_option_stack *next;
13214 struct mips_set_options options;
13217 static struct mips_option_stack *mips_opts_stack;
13219 /* Handle the .set pseudo-op. */
13222 s_mipsset (int x ATTRIBUTE_UNUSED)
13224 char *name = input_line_pointer, ch;
13226 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13227 ++input_line_pointer;
13228 ch = *input_line_pointer;
13229 *input_line_pointer = '\0';
13231 if (strcmp (name, "reorder") == 0)
13233 if (mips_opts.noreorder)
13236 else if (strcmp (name, "noreorder") == 0)
13238 if (!mips_opts.noreorder)
13239 start_noreorder ();
13241 else if (strncmp (name, "at=", 3) == 0)
13243 char *s = name + 3;
13245 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13246 as_bad (_("Unrecognized register name `%s'"), s);
13248 else if (strcmp (name, "at") == 0)
13250 mips_opts.at = ATREG;
13252 else if (strcmp (name, "noat") == 0)
13254 mips_opts.at = ZERO;
13256 else if (strcmp (name, "macro") == 0)
13258 mips_opts.warn_about_macros = 0;
13260 else if (strcmp (name, "nomacro") == 0)
13262 if (mips_opts.noreorder == 0)
13263 as_bad (_("`noreorder' must be set before `nomacro'"));
13264 mips_opts.warn_about_macros = 1;
13266 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13268 mips_opts.nomove = 0;
13270 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13272 mips_opts.nomove = 1;
13274 else if (strcmp (name, "bopt") == 0)
13276 mips_opts.nobopt = 0;
13278 else if (strcmp (name, "nobopt") == 0)
13280 mips_opts.nobopt = 1;
13282 else if (strcmp (name, "gp=default") == 0)
13283 mips_opts.gp32 = file_mips_gp32;
13284 else if (strcmp (name, "gp=32") == 0)
13285 mips_opts.gp32 = 1;
13286 else if (strcmp (name, "gp=64") == 0)
13288 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13289 as_warn (_("%s isa does not support 64-bit registers"),
13290 mips_cpu_info_from_isa (mips_opts.isa)->name);
13291 mips_opts.gp32 = 0;
13293 else if (strcmp (name, "fp=default") == 0)
13294 mips_opts.fp32 = file_mips_fp32;
13295 else if (strcmp (name, "fp=32") == 0)
13296 mips_opts.fp32 = 1;
13297 else if (strcmp (name, "fp=64") == 0)
13299 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13300 as_warn (_("%s isa does not support 64-bit floating point registers"),
13301 mips_cpu_info_from_isa (mips_opts.isa)->name);
13302 mips_opts.fp32 = 0;
13304 else if (strcmp (name, "softfloat") == 0)
13305 mips_opts.soft_float = 1;
13306 else if (strcmp (name, "hardfloat") == 0)
13307 mips_opts.soft_float = 0;
13308 else if (strcmp (name, "singlefloat") == 0)
13309 mips_opts.single_float = 1;
13310 else if (strcmp (name, "doublefloat") == 0)
13311 mips_opts.single_float = 0;
13312 else if (strcmp (name, "mips16") == 0
13313 || strcmp (name, "MIPS-16") == 0)
13314 mips_opts.mips16 = 1;
13315 else if (strcmp (name, "nomips16") == 0
13316 || strcmp (name, "noMIPS-16") == 0)
13317 mips_opts.mips16 = 0;
13318 else if (strcmp (name, "smartmips") == 0)
13320 if (!ISA_SUPPORTS_SMARTMIPS)
13321 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13322 mips_cpu_info_from_isa (mips_opts.isa)->name);
13323 mips_opts.ase_smartmips = 1;
13325 else if (strcmp (name, "nosmartmips") == 0)
13326 mips_opts.ase_smartmips = 0;
13327 else if (strcmp (name, "mips3d") == 0)
13328 mips_opts.ase_mips3d = 1;
13329 else if (strcmp (name, "nomips3d") == 0)
13330 mips_opts.ase_mips3d = 0;
13331 else if (strcmp (name, "mdmx") == 0)
13332 mips_opts.ase_mdmx = 1;
13333 else if (strcmp (name, "nomdmx") == 0)
13334 mips_opts.ase_mdmx = 0;
13335 else if (strcmp (name, "dsp") == 0)
13337 if (!ISA_SUPPORTS_DSP_ASE)
13338 as_warn (_("%s ISA does not support DSP ASE"),
13339 mips_cpu_info_from_isa (mips_opts.isa)->name);
13340 mips_opts.ase_dsp = 1;
13341 mips_opts.ase_dspr2 = 0;
13343 else if (strcmp (name, "nodsp") == 0)
13345 mips_opts.ase_dsp = 0;
13346 mips_opts.ase_dspr2 = 0;
13348 else if (strcmp (name, "dspr2") == 0)
13350 if (!ISA_SUPPORTS_DSPR2_ASE)
13351 as_warn (_("%s ISA does not support DSP R2 ASE"),
13352 mips_cpu_info_from_isa (mips_opts.isa)->name);
13353 mips_opts.ase_dspr2 = 1;
13354 mips_opts.ase_dsp = 1;
13356 else if (strcmp (name, "nodspr2") == 0)
13358 mips_opts.ase_dspr2 = 0;
13359 mips_opts.ase_dsp = 0;
13361 else if (strcmp (name, "mt") == 0)
13363 if (!ISA_SUPPORTS_MT_ASE)
13364 as_warn (_("%s ISA does not support MT ASE"),
13365 mips_cpu_info_from_isa (mips_opts.isa)->name);
13366 mips_opts.ase_mt = 1;
13368 else if (strcmp (name, "nomt") == 0)
13369 mips_opts.ase_mt = 0;
13370 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13374 /* Permit the user to change the ISA and architecture on the fly.
13375 Needless to say, misuse can cause serious problems. */
13376 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13379 mips_opts.isa = file_mips_isa;
13380 mips_opts.arch = file_mips_arch;
13382 else if (strncmp (name, "arch=", 5) == 0)
13384 const struct mips_cpu_info *p;
13386 p = mips_parse_cpu("internal use", name + 5);
13388 as_bad (_("unknown architecture %s"), name + 5);
13391 mips_opts.arch = p->cpu;
13392 mips_opts.isa = p->isa;
13395 else if (strncmp (name, "mips", 4) == 0)
13397 const struct mips_cpu_info *p;
13399 p = mips_parse_cpu("internal use", name);
13401 as_bad (_("unknown ISA level %s"), name + 4);
13404 mips_opts.arch = p->cpu;
13405 mips_opts.isa = p->isa;
13409 as_bad (_("unknown ISA or architecture %s"), name);
13411 switch (mips_opts.isa)
13419 mips_opts.gp32 = 1;
13420 mips_opts.fp32 = 1;
13427 mips_opts.gp32 = 0;
13428 mips_opts.fp32 = 0;
13431 as_bad (_("unknown ISA level %s"), name + 4);
13436 mips_opts.gp32 = file_mips_gp32;
13437 mips_opts.fp32 = file_mips_fp32;
13440 else if (strcmp (name, "autoextend") == 0)
13441 mips_opts.noautoextend = 0;
13442 else if (strcmp (name, "noautoextend") == 0)
13443 mips_opts.noautoextend = 1;
13444 else if (strcmp (name, "push") == 0)
13446 struct mips_option_stack *s;
13448 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13449 s->next = mips_opts_stack;
13450 s->options = mips_opts;
13451 mips_opts_stack = s;
13453 else if (strcmp (name, "pop") == 0)
13455 struct mips_option_stack *s;
13457 s = mips_opts_stack;
13459 as_bad (_(".set pop with no .set push"));
13462 /* If we're changing the reorder mode we need to handle
13463 delay slots correctly. */
13464 if (s->options.noreorder && ! mips_opts.noreorder)
13465 start_noreorder ();
13466 else if (! s->options.noreorder && mips_opts.noreorder)
13469 mips_opts = s->options;
13470 mips_opts_stack = s->next;
13474 else if (strcmp (name, "sym32") == 0)
13475 mips_opts.sym32 = TRUE;
13476 else if (strcmp (name, "nosym32") == 0)
13477 mips_opts.sym32 = FALSE;
13478 else if (strchr (name, ','))
13480 /* Generic ".set" directive; use the generic handler. */
13481 *input_line_pointer = ch;
13482 input_line_pointer = name;
13488 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13490 *input_line_pointer = ch;
13491 demand_empty_rest_of_line ();
13494 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13495 .option pic2. It means to generate SVR4 PIC calls. */
13498 s_abicalls (int ignore ATTRIBUTE_UNUSED)
13500 mips_pic = SVR4_PIC;
13501 mips_abicalls = TRUE;
13503 if (g_switch_seen && g_switch_value != 0)
13504 as_warn (_("-G may not be used with SVR4 PIC code"));
13505 g_switch_value = 0;
13507 bfd_set_gp_size (stdoutput, 0);
13508 demand_empty_rest_of_line ();
13511 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13512 PIC code. It sets the $gp register for the function based on the
13513 function address, which is in the register named in the argument.
13514 This uses a relocation against _gp_disp, which is handled specially
13515 by the linker. The result is:
13516 lui $gp,%hi(_gp_disp)
13517 addiu $gp,$gp,%lo(_gp_disp)
13518 addu $gp,$gp,.cpload argument
13519 The .cpload argument is normally $25 == $t9.
13521 The -mno-shared option changes this to:
13522 lui $gp,%hi(__gnu_local_gp)
13523 addiu $gp,$gp,%lo(__gnu_local_gp)
13524 and the argument is ignored. This saves an instruction, but the
13525 resulting code is not position independent; it uses an absolute
13526 address for __gnu_local_gp. Thus code assembled with -mno-shared
13527 can go into an ordinary executable, but not into a shared library. */
13530 s_cpload (int ignore ATTRIBUTE_UNUSED)
13536 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13537 .cpload is ignored. */
13538 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13544 /* .cpload should be in a .set noreorder section. */
13545 if (mips_opts.noreorder == 0)
13546 as_warn (_(".cpload not in noreorder section"));
13548 reg = tc_get_register (0);
13550 /* If we need to produce a 64-bit address, we are better off using
13551 the default instruction sequence. */
13552 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13554 ex.X_op = O_symbol;
13555 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13557 ex.X_op_symbol = NULL;
13558 ex.X_add_number = 0;
13560 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13561 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13564 macro_build_lui (&ex, mips_gp_register);
13565 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13566 mips_gp_register, BFD_RELOC_LO16);
13568 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13569 mips_gp_register, reg);
13572 demand_empty_rest_of_line ();
13575 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13576 .cpsetup $reg1, offset|$reg2, label
13578 If offset is given, this results in:
13579 sd $gp, offset($sp)
13580 lui $gp, %hi(%neg(%gp_rel(label)))
13581 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13582 daddu $gp, $gp, $reg1
13584 If $reg2 is given, this results in:
13585 daddu $reg2, $gp, $0
13586 lui $gp, %hi(%neg(%gp_rel(label)))
13587 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13588 daddu $gp, $gp, $reg1
13589 $reg1 is normally $25 == $t9.
13591 The -mno-shared option replaces the last three instructions with
13593 addiu $gp,$gp,%lo(_gp) */
13596 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13598 expressionS ex_off;
13599 expressionS ex_sym;
13602 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13603 We also need NewABI support. */
13604 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13610 reg1 = tc_get_register (0);
13611 SKIP_WHITESPACE ();
13612 if (*input_line_pointer != ',')
13614 as_bad (_("missing argument separator ',' for .cpsetup"));
13618 ++input_line_pointer;
13619 SKIP_WHITESPACE ();
13620 if (*input_line_pointer == '$')
13622 mips_cpreturn_register = tc_get_register (0);
13623 mips_cpreturn_offset = -1;
13627 mips_cpreturn_offset = get_absolute_expression ();
13628 mips_cpreturn_register = -1;
13630 SKIP_WHITESPACE ();
13631 if (*input_line_pointer != ',')
13633 as_bad (_("missing argument separator ',' for .cpsetup"));
13637 ++input_line_pointer;
13638 SKIP_WHITESPACE ();
13639 expression (&ex_sym);
13642 if (mips_cpreturn_register == -1)
13644 ex_off.X_op = O_constant;
13645 ex_off.X_add_symbol = NULL;
13646 ex_off.X_op_symbol = NULL;
13647 ex_off.X_add_number = mips_cpreturn_offset;
13649 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13650 BFD_RELOC_LO16, SP);
13653 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13654 mips_gp_register, 0);
13656 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13658 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13659 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13662 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13663 mips_gp_register, -1, BFD_RELOC_GPREL16,
13664 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13667 mips_gp_register, reg1);
13673 ex.X_op = O_symbol;
13674 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13675 ex.X_op_symbol = NULL;
13676 ex.X_add_number = 0;
13678 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13679 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13681 macro_build_lui (&ex, mips_gp_register);
13682 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13683 mips_gp_register, BFD_RELOC_LO16);
13688 demand_empty_rest_of_line ();
13692 s_cplocal (int ignore ATTRIBUTE_UNUSED)
13694 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13695 .cplocal is ignored. */
13696 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13702 mips_gp_register = tc_get_register (0);
13703 demand_empty_rest_of_line ();
13706 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13707 offset from $sp. The offset is remembered, and after making a PIC
13708 call $gp is restored from that location. */
13711 s_cprestore (int ignore ATTRIBUTE_UNUSED)
13715 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13716 .cprestore is ignored. */
13717 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13723 mips_cprestore_offset = get_absolute_expression ();
13724 mips_cprestore_valid = 1;
13726 ex.X_op = O_constant;
13727 ex.X_add_symbol = NULL;
13728 ex.X_op_symbol = NULL;
13729 ex.X_add_number = mips_cprestore_offset;
13732 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13733 SP, HAVE_64BIT_ADDRESSES);
13736 demand_empty_rest_of_line ();
13739 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13740 was given in the preceding .cpsetup, it results in:
13741 ld $gp, offset($sp)
13743 If a register $reg2 was given there, it results in:
13744 daddu $gp, $reg2, $0 */
13747 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13751 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13752 We also need NewABI support. */
13753 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13760 if (mips_cpreturn_register == -1)
13762 ex.X_op = O_constant;
13763 ex.X_add_symbol = NULL;
13764 ex.X_op_symbol = NULL;
13765 ex.X_add_number = mips_cpreturn_offset;
13767 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13770 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13771 mips_cpreturn_register, 0);
13774 demand_empty_rest_of_line ();
13777 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13778 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13779 use in DWARF debug information. */
13782 s_dtprel_internal (size_t bytes)
13789 if (ex.X_op != O_symbol)
13791 as_bad (_("Unsupported use of %s"), (bytes == 8
13794 ignore_rest_of_line ();
13797 p = frag_more (bytes);
13798 md_number_to_chars (p, 0, bytes);
13799 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13801 ? BFD_RELOC_MIPS_TLS_DTPREL64
13802 : BFD_RELOC_MIPS_TLS_DTPREL32));
13804 demand_empty_rest_of_line ();
13807 /* Handle .dtprelword. */
13810 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13812 s_dtprel_internal (4);
13815 /* Handle .dtpreldword. */
13818 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13820 s_dtprel_internal (8);
13823 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13824 code. It sets the offset to use in gp_rel relocations. */
13827 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13829 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13830 We also need NewABI support. */
13831 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13837 mips_gprel_offset = get_absolute_expression ();
13839 demand_empty_rest_of_line ();
13842 /* Handle the .gpword pseudo-op. This is used when generating PIC
13843 code. It generates a 32 bit GP relative reloc. */
13846 s_gpword (int ignore ATTRIBUTE_UNUSED)
13848 segment_info_type *si;
13849 struct insn_label_list *l;
13854 /* When not generating PIC code, this is treated as .word. */
13855 if (mips_pic != SVR4_PIC)
13861 si = seg_info (now_seg);
13862 l = si->label_list;
13863 label = l != NULL ? l->label : NULL;
13864 mips_emit_delays ();
13866 mips_align (2, 0, label);
13869 mips_clear_insn_labels ();
13871 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13873 as_bad (_("Unsupported use of .gpword"));
13874 ignore_rest_of_line ();
13878 md_number_to_chars (p, 0, 4);
13879 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13880 BFD_RELOC_GPREL32);
13882 demand_empty_rest_of_line ();
13886 s_gpdword (int ignore ATTRIBUTE_UNUSED)
13888 segment_info_type *si;
13889 struct insn_label_list *l;
13894 /* When not generating PIC code, this is treated as .dword. */
13895 if (mips_pic != SVR4_PIC)
13901 si = seg_info (now_seg);
13902 l = si->label_list;
13903 label = l != NULL ? l->label : NULL;
13904 mips_emit_delays ();
13906 mips_align (3, 0, label);
13909 mips_clear_insn_labels ();
13911 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13913 as_bad (_("Unsupported use of .gpdword"));
13914 ignore_rest_of_line ();
13918 md_number_to_chars (p, 0, 8);
13919 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13920 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13922 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13923 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13924 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13926 demand_empty_rest_of_line ();
13929 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13930 tables in SVR4 PIC code. */
13933 s_cpadd (int ignore ATTRIBUTE_UNUSED)
13937 /* This is ignored when not generating SVR4 PIC code. */
13938 if (mips_pic != SVR4_PIC)
13944 /* Add $gp to the register named as an argument. */
13946 reg = tc_get_register (0);
13947 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13950 demand_empty_rest_of_line ();
13953 /* Handle the .insn pseudo-op. This marks instruction labels in
13954 mips16 mode. This permits the linker to handle them specially,
13955 such as generating jalx instructions when needed. We also make
13956 them odd for the duration of the assembly, in order to generate the
13957 right sort of code. We will make them even in the adjust_symtab
13958 routine, while leaving them marked. This is convenient for the
13959 debugger and the disassembler. The linker knows to make them odd
13963 s_insn (int ignore ATTRIBUTE_UNUSED)
13965 mips16_mark_labels ();
13967 demand_empty_rest_of_line ();
13970 /* Handle a .stabn directive. We need these in order to mark a label
13971 as being a mips16 text label correctly. Sometimes the compiler
13972 will emit a label, followed by a .stabn, and then switch sections.
13973 If the label and .stabn are in mips16 mode, then the label is
13974 really a mips16 text label. */
13977 s_mips_stab (int type)
13980 mips16_mark_labels ();
13985 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13988 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13995 name = input_line_pointer;
13996 c = get_symbol_end ();
13997 symbolP = symbol_find_or_make (name);
13998 S_SET_WEAK (symbolP);
13999 *input_line_pointer = c;
14001 SKIP_WHITESPACE ();
14003 if (! is_end_of_line[(unsigned char) *input_line_pointer])
14005 if (S_IS_DEFINED (symbolP))
14007 as_bad (_("ignoring attempt to redefine symbol %s"),
14008 S_GET_NAME (symbolP));
14009 ignore_rest_of_line ();
14013 if (*input_line_pointer == ',')
14015 ++input_line_pointer;
14016 SKIP_WHITESPACE ();
14020 if (exp.X_op != O_symbol)
14022 as_bad (_("bad .weakext directive"));
14023 ignore_rest_of_line ();
14026 symbol_set_value_expression (symbolP, &exp);
14029 demand_empty_rest_of_line ();
14032 /* Parse a register string into a number. Called from the ECOFF code
14033 to parse .frame. The argument is non-zero if this is the frame
14034 register, so that we can record it in mips_frame_reg. */
14037 tc_get_register (int frame)
14041 SKIP_WHITESPACE ();
14042 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
14046 mips_frame_reg = reg != 0 ? reg : SP;
14047 mips_frame_reg_valid = 1;
14048 mips_cprestore_valid = 0;
14054 md_section_align (asection *seg, valueT addr)
14056 int align = bfd_get_section_alignment (stdoutput, seg);
14060 /* We don't need to align ELF sections to the full alignment.
14061 However, Irix 5 may prefer that we align them at least to a 16
14062 byte boundary. We don't bother to align the sections if we
14063 are targeted for an embedded system. */
14064 if (strncmp (TARGET_OS, "elf", 3) == 0)
14070 return ((addr + (1 << align) - 1) & (-1 << align));
14073 /* Utility routine, called from above as well. If called while the
14074 input file is still being read, it's only an approximation. (For
14075 example, a symbol may later become defined which appeared to be
14076 undefined earlier.) */
14079 nopic_need_relax (symbolS *sym, int before_relaxing)
14084 if (g_switch_value > 0)
14086 const char *symname;
14089 /* Find out whether this symbol can be referenced off the $gp
14090 register. It can be if it is smaller than the -G size or if
14091 it is in the .sdata or .sbss section. Certain symbols can
14092 not be referenced off the $gp, although it appears as though
14094 symname = S_GET_NAME (sym);
14095 if (symname != (const char *) NULL
14096 && (strcmp (symname, "eprol") == 0
14097 || strcmp (symname, "etext") == 0
14098 || strcmp (symname, "_gp") == 0
14099 || strcmp (symname, "edata") == 0
14100 || strcmp (symname, "_fbss") == 0
14101 || strcmp (symname, "_fdata") == 0
14102 || strcmp (symname, "_ftext") == 0
14103 || strcmp (symname, "end") == 0
14104 || strcmp (symname, "_gp_disp") == 0))
14106 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14108 #ifndef NO_ECOFF_DEBUGGING
14109 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14110 && (symbol_get_obj (sym)->ecoff_extern_size
14111 <= g_switch_value))
14113 /* We must defer this decision until after the whole
14114 file has been read, since there might be a .extern
14115 after the first use of this symbol. */
14116 || (before_relaxing
14117 #ifndef NO_ECOFF_DEBUGGING
14118 && symbol_get_obj (sym)->ecoff_extern_size == 0
14120 && S_GET_VALUE (sym) == 0)
14121 || (S_GET_VALUE (sym) != 0
14122 && S_GET_VALUE (sym) <= g_switch_value)))
14126 const char *segname;
14128 segname = segment_name (S_GET_SEGMENT (sym));
14129 gas_assert (strcmp (segname, ".lit8") != 0
14130 && strcmp (segname, ".lit4") != 0);
14131 change = (strcmp (segname, ".sdata") != 0
14132 && strcmp (segname, ".sbss") != 0
14133 && strncmp (segname, ".sdata.", 7) != 0
14134 && strncmp (segname, ".sbss.", 6) != 0
14135 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14136 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14141 /* We are not optimizing for the $gp register. */
14146 /* Return true if the given symbol should be considered local for SVR4 PIC. */
14149 pic_need_relax (symbolS *sym, asection *segtype)
14153 /* Handle the case of a symbol equated to another symbol. */
14154 while (symbol_equated_reloc_p (sym))
14158 /* It's possible to get a loop here in a badly written program. */
14159 n = symbol_get_value_expression (sym)->X_add_symbol;
14165 if (symbol_section_p (sym))
14168 symsec = S_GET_SEGMENT (sym);
14170 /* This must duplicate the test in adjust_reloc_syms. */
14171 return (symsec != &bfd_und_section
14172 && symsec != &bfd_abs_section
14173 && !bfd_is_com_section (symsec)
14174 && !s_is_linkonce (sym, segtype)
14176 /* A global or weak symbol is treated as external. */
14177 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14183 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14184 extended opcode. SEC is the section the frag is in. */
14187 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14190 const struct mips16_immed_operand *op;
14192 int mintiny, maxtiny;
14196 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14198 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14201 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14202 op = mips16_immed_operands;
14203 while (op->type != type)
14206 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14211 if (type == '<' || type == '>' || type == '[' || type == ']')
14214 maxtiny = 1 << op->nbits;
14219 maxtiny = (1 << op->nbits) - 1;
14224 mintiny = - (1 << (op->nbits - 1));
14225 maxtiny = (1 << (op->nbits - 1)) - 1;
14228 sym_frag = symbol_get_frag (fragp->fr_symbol);
14229 val = S_GET_VALUE (fragp->fr_symbol);
14230 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14236 /* We won't have the section when we are called from
14237 mips_relax_frag. However, we will always have been called
14238 from md_estimate_size_before_relax first. If this is a
14239 branch to a different section, we mark it as such. If SEC is
14240 NULL, and the frag is not marked, then it must be a branch to
14241 the same section. */
14244 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14249 /* Must have been called from md_estimate_size_before_relax. */
14252 fragp->fr_subtype =
14253 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14255 /* FIXME: We should support this, and let the linker
14256 catch branches and loads that are out of range. */
14257 as_bad_where (fragp->fr_file, fragp->fr_line,
14258 _("unsupported PC relative reference to different section"));
14262 if (fragp != sym_frag && sym_frag->fr_address == 0)
14263 /* Assume non-extended on the first relaxation pass.
14264 The address we have calculated will be bogus if this is
14265 a forward branch to another frag, as the forward frag
14266 will have fr_address == 0. */
14270 /* In this case, we know for sure that the symbol fragment is in
14271 the same section. If the relax_marker of the symbol fragment
14272 differs from the relax_marker of this fragment, we have not
14273 yet adjusted the symbol fragment fr_address. We want to add
14274 in STRETCH in order to get a better estimate of the address.
14275 This particularly matters because of the shift bits. */
14277 && sym_frag->relax_marker != fragp->relax_marker)
14281 /* Adjust stretch for any alignment frag. Note that if have
14282 been expanding the earlier code, the symbol may be
14283 defined in what appears to be an earlier frag. FIXME:
14284 This doesn't handle the fr_subtype field, which specifies
14285 a maximum number of bytes to skip when doing an
14287 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14289 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14292 stretch = - ((- stretch)
14293 & ~ ((1 << (int) f->fr_offset) - 1));
14295 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14304 addr = fragp->fr_address + fragp->fr_fix;
14306 /* The base address rules are complicated. The base address of
14307 a branch is the following instruction. The base address of a
14308 PC relative load or add is the instruction itself, but if it
14309 is in a delay slot (in which case it can not be extended) use
14310 the address of the instruction whose delay slot it is in. */
14311 if (type == 'p' || type == 'q')
14315 /* If we are currently assuming that this frag should be
14316 extended, then, the current address is two bytes
14318 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14321 /* Ignore the low bit in the target, since it will be set
14322 for a text label. */
14323 if ((val & 1) != 0)
14326 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14328 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14331 val -= addr & ~ ((1 << op->shift) - 1);
14333 /* Branch offsets have an implicit 0 in the lowest bit. */
14334 if (type == 'p' || type == 'q')
14337 /* If any of the shifted bits are set, we must use an extended
14338 opcode. If the address depends on the size of this
14339 instruction, this can lead to a loop, so we arrange to always
14340 use an extended opcode. We only check this when we are in
14341 the main relaxation loop, when SEC is NULL. */
14342 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14344 fragp->fr_subtype =
14345 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14349 /* If we are about to mark a frag as extended because the value
14350 is precisely maxtiny + 1, then there is a chance of an
14351 infinite loop as in the following code:
14356 In this case when the la is extended, foo is 0x3fc bytes
14357 away, so the la can be shrunk, but then foo is 0x400 away, so
14358 the la must be extended. To avoid this loop, we mark the
14359 frag as extended if it was small, and is about to become
14360 extended with a value of maxtiny + 1. */
14361 if (val == ((maxtiny + 1) << op->shift)
14362 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14365 fragp->fr_subtype =
14366 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14370 else if (symsec != absolute_section && sec != NULL)
14371 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14373 if ((val & ((1 << op->shift) - 1)) != 0
14374 || val < (mintiny << op->shift)
14375 || val > (maxtiny << op->shift))
14381 /* Compute the length of a branch sequence, and adjust the
14382 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14383 worst-case length is computed, with UPDATE being used to indicate
14384 whether an unconditional (-1), branch-likely (+1) or regular (0)
14385 branch is to be computed. */
14387 relaxed_branch_length (fragS *fragp, asection *sec, int update)
14389 bfd_boolean toofar;
14393 && S_IS_DEFINED (fragp->fr_symbol)
14394 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14399 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14401 addr = fragp->fr_address + fragp->fr_fix + 4;
14405 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14408 /* If the symbol is not defined or it's in a different segment,
14409 assume the user knows what's going on and emit a short
14415 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14417 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14418 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14419 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14420 RELAX_BRANCH_LINK (fragp->fr_subtype),
14426 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14429 if (mips_pic != NO_PIC)
14431 /* Additional space for PIC loading of target address. */
14433 if (mips_opts.isa == ISA_MIPS1)
14434 /* Additional space for $at-stabilizing nop. */
14438 /* If branch is conditional. */
14439 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14446 /* Estimate the size of a frag before relaxing. Unless this is the
14447 mips16, we are not really relaxing here, and the final size is
14448 encoded in the subtype information. For the mips16, we have to
14449 decide whether we are using an extended opcode or not. */
14452 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14456 if (RELAX_BRANCH_P (fragp->fr_subtype))
14459 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14461 return fragp->fr_var;
14464 if (RELAX_MIPS16_P (fragp->fr_subtype))
14465 /* We don't want to modify the EXTENDED bit here; it might get us
14466 into infinite loops. We change it only in mips_relax_frag(). */
14467 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14469 if (mips_pic == NO_PIC)
14470 change = nopic_need_relax (fragp->fr_symbol, 0);
14471 else if (mips_pic == SVR4_PIC)
14472 change = pic_need_relax (fragp->fr_symbol, segtype);
14473 else if (mips_pic == VXWORKS_PIC)
14474 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14481 fragp->fr_subtype |= RELAX_USE_SECOND;
14482 return -RELAX_FIRST (fragp->fr_subtype);
14485 return -RELAX_SECOND (fragp->fr_subtype);
14488 /* This is called to see whether a reloc against a defined symbol
14489 should be converted into a reloc against a section. */
14492 mips_fix_adjustable (fixS *fixp)
14494 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14495 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14498 if (fixp->fx_addsy == NULL)
14501 /* If symbol SYM is in a mergeable section, relocations of the form
14502 SYM + 0 can usually be made section-relative. The mergeable data
14503 is then identified by the section offset rather than by the symbol.
14505 However, if we're generating REL LO16 relocations, the offset is split
14506 between the LO16 and parterning high part relocation. The linker will
14507 need to recalculate the complete offset in order to correctly identify
14510 The linker has traditionally not looked for the parterning high part
14511 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14512 placed anywhere. Rather than break backwards compatibility by changing
14513 this, it seems better not to force the issue, and instead keep the
14514 original symbol. This will work with either linker behavior. */
14515 if ((lo16_reloc_p (fixp->fx_r_type)
14516 || reloc_needs_lo_p (fixp->fx_r_type))
14517 && HAVE_IN_PLACE_ADDENDS
14518 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14521 /* There is no place to store an in-place offset for JALR relocations.
14522 Likewise an in-range offset of PC-relative relocations may overflow
14523 the in-place relocatable field if recalculated against the start
14524 address of the symbol's containing section. */
14525 if (HAVE_IN_PLACE_ADDENDS
14526 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14530 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14531 to a floating-point stub. The same is true for non-R_MIPS16_26
14532 relocations against MIPS16 functions; in this case, the stub becomes
14533 the function's canonical address.
14535 Floating-point stubs are stored in unique .mips16.call.* or
14536 .mips16.fn.* sections. If a stub T for function F is in section S,
14537 the first relocation in section S must be against F; this is how the
14538 linker determines the target function. All relocations that might
14539 resolve to T must also be against F. We therefore have the following
14540 restrictions, which are given in an intentionally-redundant way:
14542 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14545 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14546 if that stub might be used.
14548 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14551 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14552 that stub might be used.
14554 There is a further restriction:
14556 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14557 on targets with in-place addends; the relocation field cannot
14558 encode the low bit.
14560 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14561 against a MIPS16 symbol.
14563 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14564 relocation against some symbol R, no relocation against R may be
14565 reduced. (Note that this deals with (2) as well as (1) because
14566 relocations against global symbols will never be reduced on ELF
14567 targets.) This approach is a little simpler than trying to detect
14568 stub sections, and gives the "all or nothing" per-symbol consistency
14569 that we have for MIPS16 symbols. */
14571 && fixp->fx_subsy == NULL
14572 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14573 || *symbol_get_tc (fixp->fx_addsy)))
14580 /* Translate internal representation of relocation info to BFD target
14584 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14586 static arelent *retval[4];
14588 bfd_reloc_code_real_type code;
14590 memset (retval, 0, sizeof(retval));
14591 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14592 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14593 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14594 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14596 if (fixp->fx_pcrel)
14598 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14600 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14601 Relocations want only the symbol offset. */
14602 reloc->addend = fixp->fx_addnumber + reloc->address;
14605 /* A gruesome hack which is a result of the gruesome gas
14606 reloc handling. What's worse, for COFF (as opposed to
14607 ECOFF), we might need yet another copy of reloc->address.
14608 See bfd_install_relocation. */
14609 reloc->addend += reloc->address;
14613 reloc->addend = fixp->fx_addnumber;
14615 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14616 entry to be used in the relocation's section offset. */
14617 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14619 reloc->address = reloc->addend;
14623 code = fixp->fx_r_type;
14625 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14626 if (reloc->howto == NULL)
14628 as_bad_where (fixp->fx_file, fixp->fx_line,
14629 _("Can not represent %s relocation in this object file format"),
14630 bfd_get_reloc_code_name (code));
14637 /* Relax a machine dependent frag. This returns the amount by which
14638 the current size of the frag should change. */
14641 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14643 if (RELAX_BRANCH_P (fragp->fr_subtype))
14645 offsetT old_var = fragp->fr_var;
14647 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14649 return fragp->fr_var - old_var;
14652 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14655 if (mips16_extended_frag (fragp, NULL, stretch))
14657 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14659 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14664 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14666 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14673 /* Convert a machine dependent frag. */
14676 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14678 if (RELAX_BRANCH_P (fragp->fr_subtype))
14681 unsigned long insn;
14685 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14687 if (target_big_endian)
14688 insn = bfd_getb32 (buf);
14690 insn = bfd_getl32 (buf);
14692 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14694 /* We generate a fixup instead of applying it right now
14695 because, if there are linker relaxations, we're going to
14696 need the relocations. */
14697 exp.X_op = O_symbol;
14698 exp.X_add_symbol = fragp->fr_symbol;
14699 exp.X_add_number = fragp->fr_offset;
14701 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14702 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14703 fixp->fx_file = fragp->fr_file;
14704 fixp->fx_line = fragp->fr_line;
14706 md_number_to_chars ((char *) buf, insn, 4);
14713 as_warn_where (fragp->fr_file, fragp->fr_line,
14714 _("Relaxed out-of-range branch into a jump"));
14716 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14719 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14721 /* Reverse the branch. */
14722 switch ((insn >> 28) & 0xf)
14725 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14726 have the condition reversed by tweaking a single
14727 bit, and their opcodes all have 0x4???????. */
14728 gas_assert ((insn & 0xf1000000) == 0x41000000);
14729 insn ^= 0x00010000;
14733 /* bltz 0x04000000 bgez 0x04010000
14734 bltzal 0x04100000 bgezal 0x04110000 */
14735 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14736 insn ^= 0x00010000;
14740 /* beq 0x10000000 bne 0x14000000
14741 blez 0x18000000 bgtz 0x1c000000 */
14742 insn ^= 0x04000000;
14750 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14752 /* Clear the and-link bit. */
14753 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14755 /* bltzal 0x04100000 bgezal 0x04110000
14756 bltzall 0x04120000 bgezall 0x04130000 */
14757 insn &= ~0x00100000;
14760 /* Branch over the branch (if the branch was likely) or the
14761 full jump (not likely case). Compute the offset from the
14762 current instruction to branch to. */
14763 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14767 /* How many bytes in instructions we've already emitted? */
14768 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14769 /* How many bytes in instructions from here to the end? */
14770 i = fragp->fr_var - i;
14772 /* Convert to instruction count. */
14774 /* Branch counts from the next instruction. */
14777 /* Branch over the jump. */
14778 md_number_to_chars ((char *) buf, insn, 4);
14782 md_number_to_chars ((char *) buf, 0, 4);
14785 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14787 /* beql $0, $0, 2f */
14789 /* Compute the PC offset from the current instruction to
14790 the end of the variable frag. */
14791 /* How many bytes in instructions we've already emitted? */
14792 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14793 /* How many bytes in instructions from here to the end? */
14794 i = fragp->fr_var - i;
14795 /* Convert to instruction count. */
14797 /* Don't decrement i, because we want to branch over the
14801 md_number_to_chars ((char *) buf, insn, 4);
14804 md_number_to_chars ((char *) buf, 0, 4);
14809 if (mips_pic == NO_PIC)
14812 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14813 ? 0x0c000000 : 0x08000000);
14814 exp.X_op = O_symbol;
14815 exp.X_add_symbol = fragp->fr_symbol;
14816 exp.X_add_number = fragp->fr_offset;
14818 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14819 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14820 fixp->fx_file = fragp->fr_file;
14821 fixp->fx_line = fragp->fr_line;
14823 md_number_to_chars ((char *) buf, insn, 4);
14828 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14830 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14831 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14832 insn |= at << OP_SH_RT;
14833 exp.X_op = O_symbol;
14834 exp.X_add_symbol = fragp->fr_symbol;
14835 exp.X_add_number = fragp->fr_offset;
14837 if (fragp->fr_offset)
14839 exp.X_add_symbol = make_expr_symbol (&exp);
14840 exp.X_add_number = 0;
14843 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14844 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14845 fixp->fx_file = fragp->fr_file;
14846 fixp->fx_line = fragp->fr_line;
14848 md_number_to_chars ((char *) buf, insn, 4);
14851 if (mips_opts.isa == ISA_MIPS1)
14854 md_number_to_chars ((char *) buf, 0, 4);
14858 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14859 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14860 insn |= at << OP_SH_RS | at << OP_SH_RT;
14862 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14863 4, &exp, FALSE, BFD_RELOC_LO16);
14864 fixp->fx_file = fragp->fr_file;
14865 fixp->fx_line = fragp->fr_line;
14867 md_number_to_chars ((char *) buf, insn, 4);
14871 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14875 insn |= at << OP_SH_RS;
14877 md_number_to_chars ((char *) buf, insn, 4);
14882 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14883 + fragp->fr_fix + fragp->fr_var);
14885 fragp->fr_fix += fragp->fr_var;
14890 if (RELAX_MIPS16_P (fragp->fr_subtype))
14893 const struct mips16_immed_operand *op;
14894 bfd_boolean small, ext;
14897 unsigned long insn;
14898 bfd_boolean use_extend;
14899 unsigned short extend;
14901 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14902 op = mips16_immed_operands;
14903 while (op->type != type)
14906 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14917 val = resolve_symbol_value (fragp->fr_symbol);
14922 addr = fragp->fr_address + fragp->fr_fix;
14924 /* The rules for the base address of a PC relative reloc are
14925 complicated; see mips16_extended_frag. */
14926 if (type == 'p' || type == 'q')
14931 /* Ignore the low bit in the target, since it will be
14932 set for a text label. */
14933 if ((val & 1) != 0)
14936 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14938 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14941 addr &= ~ (addressT) ((1 << op->shift) - 1);
14944 /* Make sure the section winds up with the alignment we have
14947 record_alignment (asec, op->shift);
14951 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14952 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14953 as_warn_where (fragp->fr_file, fragp->fr_line,
14954 _("extended instruction in delay slot"));
14956 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14958 if (target_big_endian)
14959 insn = bfd_getb16 (buf);
14961 insn = bfd_getl16 (buf);
14963 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14964 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14965 small, ext, &insn, &use_extend, &extend);
14969 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14970 fragp->fr_fix += 2;
14974 md_number_to_chars ((char *) buf, insn, 2);
14975 fragp->fr_fix += 2;
14983 first = RELAX_FIRST (fragp->fr_subtype);
14984 second = RELAX_SECOND (fragp->fr_subtype);
14985 fixp = (fixS *) fragp->fr_opcode;
14987 /* Possibly emit a warning if we've chosen the longer option. */
14988 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14989 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14991 const char *msg = macro_warning (fragp->fr_subtype);
14993 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14996 /* Go through all the fixups for the first sequence. Disable them
14997 (by marking them as done) if we're going to use the second
14998 sequence instead. */
15000 && fixp->fx_frag == fragp
15001 && fixp->fx_where < fragp->fr_fix - second)
15003 if (fragp->fr_subtype & RELAX_USE_SECOND)
15005 fixp = fixp->fx_next;
15008 /* Go through the fixups for the second sequence. Disable them if
15009 we're going to use the first sequence, otherwise adjust their
15010 addresses to account for the relaxation. */
15011 while (fixp && fixp->fx_frag == fragp)
15013 if (fragp->fr_subtype & RELAX_USE_SECOND)
15014 fixp->fx_where -= first;
15017 fixp = fixp->fx_next;
15020 /* Now modify the frag contents. */
15021 if (fragp->fr_subtype & RELAX_USE_SECOND)
15025 start = fragp->fr_literal + fragp->fr_fix - first - second;
15026 memmove (start, start + first, second);
15027 fragp->fr_fix -= first;
15030 fragp->fr_fix -= second;
15036 /* This function is called after the relocs have been generated.
15037 We've been storing mips16 text labels as odd. Here we convert them
15038 back to even for the convenience of the debugger. */
15041 mips_frob_file_after_relocs (void)
15044 unsigned int count, i;
15049 syms = bfd_get_outsymbols (stdoutput);
15050 count = bfd_get_symcount (stdoutput);
15051 for (i = 0; i < count; i++, syms++)
15053 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15054 && ((*syms)->value & 1) != 0)
15056 (*syms)->value &= ~1;
15057 /* If the symbol has an odd size, it was probably computed
15058 incorrectly, so adjust that as well. */
15059 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15060 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15067 /* This function is called whenever a label is defined, including fake
15068 labels instantiated off the dot special symbol. It is used when
15069 handling branch delays; if a branch has a label, we assume we cannot
15070 move it. This also bumps the value of the symbol by 1 in compressed
15074 mips_record_label (symbolS *sym)
15076 segment_info_type *si = seg_info (now_seg);
15077 struct insn_label_list *l;
15079 if (free_insn_labels == NULL)
15080 l = (struct insn_label_list *) xmalloc (sizeof *l);
15083 l = free_insn_labels;
15084 free_insn_labels = l->next;
15088 l->next = si->label_list;
15089 si->label_list = l;
15092 /* This function is called as tc_frob_label() whenever a label is defined
15093 and adds a DWARF-2 record we only want for true labels. */
15096 mips_define_label (symbolS *sym)
15098 mips_record_label (sym);
15100 dwarf2_emit_label (sym);
15104 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15106 /* Some special processing for a MIPS ELF file. */
15109 mips_elf_final_processing (void)
15111 /* Write out the register information. */
15112 if (mips_abi != N64_ABI)
15116 s.ri_gprmask = mips_gprmask;
15117 s.ri_cprmask[0] = mips_cprmask[0];
15118 s.ri_cprmask[1] = mips_cprmask[1];
15119 s.ri_cprmask[2] = mips_cprmask[2];
15120 s.ri_cprmask[3] = mips_cprmask[3];
15121 /* The gp_value field is set by the MIPS ELF backend. */
15123 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15124 ((Elf32_External_RegInfo *)
15125 mips_regmask_frag));
15129 Elf64_Internal_RegInfo s;
15131 s.ri_gprmask = mips_gprmask;
15133 s.ri_cprmask[0] = mips_cprmask[0];
15134 s.ri_cprmask[1] = mips_cprmask[1];
15135 s.ri_cprmask[2] = mips_cprmask[2];
15136 s.ri_cprmask[3] = mips_cprmask[3];
15137 /* The gp_value field is set by the MIPS ELF backend. */
15139 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15140 ((Elf64_External_RegInfo *)
15141 mips_regmask_frag));
15144 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15145 sort of BFD interface for this. */
15146 if (mips_any_noreorder)
15147 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15148 if (mips_pic != NO_PIC)
15150 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15151 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15154 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15156 /* Set MIPS ELF flags for ASEs. */
15157 /* We may need to define a new flag for DSP ASE, and set this flag when
15158 file_ase_dsp is true. */
15159 /* Same for DSP R2. */
15160 /* We may need to define a new flag for MT ASE, and set this flag when
15161 file_ase_mt is true. */
15162 if (file_ase_mips16)
15163 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15164 #if 0 /* XXX FIXME */
15165 if (file_ase_mips3d)
15166 elf_elfheader (stdoutput)->e_flags |= ???;
15169 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15171 /* Set the MIPS ELF ABI flags. */
15172 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15173 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15174 else if (mips_abi == O64_ABI)
15175 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15176 else if (mips_abi == EABI_ABI)
15178 if (!file_mips_gp32)
15179 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15181 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15183 else if (mips_abi == N32_ABI)
15184 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15186 /* Nothing to do for N64_ABI. */
15188 if (mips_32bitmode)
15189 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15191 #if 0 /* XXX FIXME */
15192 /* 32 bit code with 64 bit FP registers. */
15193 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15194 elf_elfheader (stdoutput)->e_flags |= ???;
15198 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15200 typedef struct proc {
15202 symbolS *func_end_sym;
15203 unsigned long reg_mask;
15204 unsigned long reg_offset;
15205 unsigned long fpreg_mask;
15206 unsigned long fpreg_offset;
15207 unsigned long frame_offset;
15208 unsigned long frame_reg;
15209 unsigned long pc_reg;
15212 static procS cur_proc;
15213 static procS *cur_proc_ptr;
15214 static int numprocs;
15216 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15220 mips_nop_opcode (void)
15222 return seg_info (now_seg)->tc_segment_info_data.mips16;
15225 /* Fill in an rs_align_code fragment. This only needs to do something
15226 for MIPS16 code, where 0 is not a nop. */
15229 mips_handle_align (fragS *fragp)
15232 int bytes, size, excess;
15235 if (fragp->fr_type != rs_align_code)
15238 p = fragp->fr_literal + fragp->fr_fix;
15241 opcode = mips16_nop_insn.insn_opcode;
15246 opcode = nop_insn.insn_opcode;
15250 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15251 excess = bytes % size;
15254 /* If we're not inserting a whole number of instructions,
15255 pad the end of the fixed part of the frag with zeros. */
15256 memset (p, 0, excess);
15258 fragp->fr_fix += excess;
15261 md_number_to_chars (p, opcode, size);
15262 fragp->fr_var = size;
15266 md_obj_begin (void)
15273 /* Check for premature end, nesting errors, etc. */
15275 as_warn (_("missing .end at end of assembly"));
15284 if (*input_line_pointer == '-')
15286 ++input_line_pointer;
15289 if (!ISDIGIT (*input_line_pointer))
15290 as_bad (_("expected simple number"));
15291 if (input_line_pointer[0] == '0')
15293 if (input_line_pointer[1] == 'x')
15295 input_line_pointer += 2;
15296 while (ISXDIGIT (*input_line_pointer))
15299 val |= hex_value (*input_line_pointer++);
15301 return negative ? -val : val;
15305 ++input_line_pointer;
15306 while (ISDIGIT (*input_line_pointer))
15309 val |= *input_line_pointer++ - '0';
15311 return negative ? -val : val;
15314 if (!ISDIGIT (*input_line_pointer))
15316 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15317 *input_line_pointer, *input_line_pointer);
15318 as_warn (_("invalid number"));
15321 while (ISDIGIT (*input_line_pointer))
15324 val += *input_line_pointer++ - '0';
15326 return negative ? -val : val;
15329 /* The .file directive; just like the usual .file directive, but there
15330 is an initial number which is the ECOFF file index. In the non-ECOFF
15331 case .file implies DWARF-2. */
15334 s_mips_file (int x ATTRIBUTE_UNUSED)
15336 static int first_file_directive = 0;
15338 if (ECOFF_DEBUGGING)
15347 filename = dwarf2_directive_file (0);
15349 /* Versions of GCC up to 3.1 start files with a ".file"
15350 directive even for stabs output. Make sure that this
15351 ".file" is handled. Note that you need a version of GCC
15352 after 3.1 in order to support DWARF-2 on MIPS. */
15353 if (filename != NULL && ! first_file_directive)
15355 (void) new_logical_line (filename, -1);
15356 s_app_file_string (filename, 0);
15358 first_file_directive = 1;
15362 /* The .loc directive, implying DWARF-2. */
15365 s_mips_loc (int x ATTRIBUTE_UNUSED)
15367 if (!ECOFF_DEBUGGING)
15368 dwarf2_directive_loc (0);
15371 /* The .end directive. */
15374 s_mips_end (int x ATTRIBUTE_UNUSED)
15378 /* Following functions need their own .frame and .cprestore directives. */
15379 mips_frame_reg_valid = 0;
15380 mips_cprestore_valid = 0;
15382 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15385 demand_empty_rest_of_line ();
15390 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15391 as_warn (_(".end not in text section"));
15395 as_warn (_(".end directive without a preceding .ent directive."));
15396 demand_empty_rest_of_line ();
15402 gas_assert (S_GET_NAME (p));
15403 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15404 as_warn (_(".end symbol does not match .ent symbol."));
15406 if (debug_type == DEBUG_STABS)
15407 stabs_generate_asm_endfunc (S_GET_NAME (p),
15411 as_warn (_(".end directive missing or unknown symbol"));
15414 /* Create an expression to calculate the size of the function. */
15415 if (p && cur_proc_ptr)
15417 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15418 expressionS *exp = xmalloc (sizeof (expressionS));
15421 exp->X_op = O_subtract;
15422 exp->X_add_symbol = symbol_temp_new_now ();
15423 exp->X_op_symbol = p;
15424 exp->X_add_number = 0;
15426 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15429 /* Generate a .pdr section. */
15430 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15432 segT saved_seg = now_seg;
15433 subsegT saved_subseg = now_subseg;
15437 #ifdef md_flush_pending_output
15438 md_flush_pending_output ();
15441 gas_assert (pdr_seg);
15442 subseg_set (pdr_seg, 0);
15444 /* Write the symbol. */
15445 exp.X_op = O_symbol;
15446 exp.X_add_symbol = p;
15447 exp.X_add_number = 0;
15448 emit_expr (&exp, 4);
15450 fragp = frag_more (7 * 4);
15452 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15453 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15454 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15455 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15456 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15457 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15458 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15460 subseg_set (saved_seg, saved_subseg);
15462 #endif /* OBJ_ELF */
15464 cur_proc_ptr = NULL;
15467 /* The .aent and .ent directives. */
15470 s_mips_ent (int aent)
15474 symbolP = get_symbol ();
15475 if (*input_line_pointer == ',')
15476 ++input_line_pointer;
15477 SKIP_WHITESPACE ();
15478 if (ISDIGIT (*input_line_pointer)
15479 || *input_line_pointer == '-')
15482 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15483 as_warn (_(".ent or .aent not in text section."));
15485 if (!aent && cur_proc_ptr)
15486 as_warn (_("missing .end"));
15490 /* This function needs its own .frame and .cprestore directives. */
15491 mips_frame_reg_valid = 0;
15492 mips_cprestore_valid = 0;
15494 cur_proc_ptr = &cur_proc;
15495 memset (cur_proc_ptr, '\0', sizeof (procS));
15497 cur_proc_ptr->func_sym = symbolP;
15501 if (debug_type == DEBUG_STABS)
15502 stabs_generate_asm_func (S_GET_NAME (symbolP),
15503 S_GET_NAME (symbolP));
15506 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15508 demand_empty_rest_of_line ();
15511 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15512 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15513 s_mips_frame is used so that we can set the PDR information correctly.
15514 We can't use the ecoff routines because they make reference to the ecoff
15515 symbol table (in the mdebug section). */
15518 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15521 if (IS_ELF && !ECOFF_DEBUGGING)
15525 if (cur_proc_ptr == (procS *) NULL)
15527 as_warn (_(".frame outside of .ent"));
15528 demand_empty_rest_of_line ();
15532 cur_proc_ptr->frame_reg = tc_get_register (1);
15534 SKIP_WHITESPACE ();
15535 if (*input_line_pointer++ != ','
15536 || get_absolute_expression_and_terminator (&val) != ',')
15538 as_warn (_("Bad .frame directive"));
15539 --input_line_pointer;
15540 demand_empty_rest_of_line ();
15544 cur_proc_ptr->frame_offset = val;
15545 cur_proc_ptr->pc_reg = tc_get_register (0);
15547 demand_empty_rest_of_line ();
15550 #endif /* OBJ_ELF */
15554 /* The .fmask and .mask directives. If the mdebug section is present
15555 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15556 embedded targets, s_mips_mask is used so that we can set the PDR
15557 information correctly. We can't use the ecoff routines because they
15558 make reference to the ecoff symbol table (in the mdebug section). */
15561 s_mips_mask (int reg_type)
15564 if (IS_ELF && !ECOFF_DEBUGGING)
15568 if (cur_proc_ptr == (procS *) NULL)
15570 as_warn (_(".mask/.fmask outside of .ent"));
15571 demand_empty_rest_of_line ();
15575 if (get_absolute_expression_and_terminator (&mask) != ',')
15577 as_warn (_("Bad .mask/.fmask directive"));
15578 --input_line_pointer;
15579 demand_empty_rest_of_line ();
15583 off = get_absolute_expression ();
15585 if (reg_type == 'F')
15587 cur_proc_ptr->fpreg_mask = mask;
15588 cur_proc_ptr->fpreg_offset = off;
15592 cur_proc_ptr->reg_mask = mask;
15593 cur_proc_ptr->reg_offset = off;
15596 demand_empty_rest_of_line ();
15599 #endif /* OBJ_ELF */
15600 s_ignore (reg_type);
15603 /* A table describing all the processors gas knows about. Names are
15604 matched in the order listed.
15606 To ease comparison, please keep this table in the same order as
15607 gcc's mips_cpu_info_table[]. */
15608 static const struct mips_cpu_info mips_cpu_info_table[] =
15610 /* Entries for generic ISAs */
15611 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15612 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15613 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15614 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15615 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15616 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15617 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15618 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15619 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15622 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15623 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15624 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15627 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15630 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15631 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15632 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15633 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15634 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15635 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15636 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15637 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15638 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15639 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15640 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15641 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15642 /* ST Microelectronics Loongson 2E and 2F cores */
15643 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15644 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15647 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15648 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15649 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15650 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15651 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15652 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15653 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15654 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15655 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15656 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15657 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15658 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15659 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15660 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15661 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15664 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15665 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15666 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15667 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15669 /* MIPS 32 Release 2 */
15670 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15671 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15672 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15673 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15674 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15675 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15676 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15677 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15678 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15679 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15680 /* Deprecated forms of the above. */
15681 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15682 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15683 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15684 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15685 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15686 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15687 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15688 /* Deprecated forms of the above. */
15689 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15690 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15691 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15692 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15693 ISA_MIPS32R2, CPU_MIPS32R2 },
15694 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15695 ISA_MIPS32R2, CPU_MIPS32R2 },
15696 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15697 ISA_MIPS32R2, CPU_MIPS32R2 },
15698 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15699 ISA_MIPS32R2, CPU_MIPS32R2 },
15700 /* Deprecated forms of the above. */
15701 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15702 ISA_MIPS32R2, CPU_MIPS32R2 },
15703 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15704 ISA_MIPS32R2, CPU_MIPS32R2 },
15705 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15706 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15707 ISA_MIPS32R2, CPU_MIPS32R2 },
15708 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15709 ISA_MIPS32R2, CPU_MIPS32R2 },
15710 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15711 ISA_MIPS32R2, CPU_MIPS32R2 },
15712 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15713 ISA_MIPS32R2, CPU_MIPS32R2 },
15714 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15715 ISA_MIPS32R2, CPU_MIPS32R2 },
15716 /* Deprecated forms of the above. */
15717 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15718 ISA_MIPS32R2, CPU_MIPS32R2 },
15719 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15720 ISA_MIPS32R2, CPU_MIPS32R2 },
15721 /* 1004K cores are multiprocessor versions of the 34K. */
15722 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15723 ISA_MIPS32R2, CPU_MIPS32R2 },
15724 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15725 ISA_MIPS32R2, CPU_MIPS32R2 },
15726 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15727 ISA_MIPS32R2, CPU_MIPS32R2 },
15728 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15729 ISA_MIPS32R2, CPU_MIPS32R2 },
15732 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15733 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15734 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15735 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15737 /* Broadcom SB-1 CPU core */
15738 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15739 ISA_MIPS64, CPU_SB1 },
15740 /* Broadcom SB-1A CPU core */
15741 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15742 ISA_MIPS64, CPU_SB1 },
15744 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15746 /* MIPS 64 Release 2 */
15748 /* Cavium Networks Octeon CPU core */
15749 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15752 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15759 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15760 with a final "000" replaced by "k". Ignore case.
15762 Note: this function is shared between GCC and GAS. */
15765 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15767 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15768 given++, canonical++;
15770 return ((*given == 0 && *canonical == 0)
15771 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15775 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15776 CPU name. We've traditionally allowed a lot of variation here.
15778 Note: this function is shared between GCC and GAS. */
15781 mips_matching_cpu_name_p (const char *canonical, const char *given)
15783 /* First see if the name matches exactly, or with a final "000"
15784 turned into "k". */
15785 if (mips_strict_matching_cpu_name_p (canonical, given))
15788 /* If not, try comparing based on numerical designation alone.
15789 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15790 if (TOLOWER (*given) == 'r')
15792 if (!ISDIGIT (*given))
15795 /* Skip over some well-known prefixes in the canonical name,
15796 hoping to find a number there too. */
15797 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15799 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15801 else if (TOLOWER (canonical[0]) == 'r')
15804 return mips_strict_matching_cpu_name_p (canonical, given);
15808 /* Parse an option that takes the name of a processor as its argument.
15809 OPTION is the name of the option and CPU_STRING is the argument.
15810 Return the corresponding processor enumeration if the CPU_STRING is
15811 recognized, otherwise report an error and return null.
15813 A similar function exists in GCC. */
15815 static const struct mips_cpu_info *
15816 mips_parse_cpu (const char *option, const char *cpu_string)
15818 const struct mips_cpu_info *p;
15820 /* 'from-abi' selects the most compatible architecture for the given
15821 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15822 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15823 version. Look first at the -mgp options, if given, otherwise base
15824 the choice on MIPS_DEFAULT_64BIT.
15826 Treat NO_ABI like the EABIs. One reason to do this is that the
15827 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15828 architecture. This code picks MIPS I for 'mips' and MIPS III for
15829 'mips64', just as we did in the days before 'from-abi'. */
15830 if (strcasecmp (cpu_string, "from-abi") == 0)
15832 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15833 return mips_cpu_info_from_isa (ISA_MIPS1);
15835 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15836 return mips_cpu_info_from_isa (ISA_MIPS3);
15838 if (file_mips_gp32 >= 0)
15839 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15841 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15846 /* 'default' has traditionally been a no-op. Probably not very useful. */
15847 if (strcasecmp (cpu_string, "default") == 0)
15850 for (p = mips_cpu_info_table; p->name != 0; p++)
15851 if (mips_matching_cpu_name_p (p->name, cpu_string))
15854 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15858 /* Return the canonical processor information for ISA (a member of the
15859 ISA_MIPS* enumeration). */
15861 static const struct mips_cpu_info *
15862 mips_cpu_info_from_isa (int isa)
15866 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15867 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15868 && isa == mips_cpu_info_table[i].isa)
15869 return (&mips_cpu_info_table[i]);
15874 static const struct mips_cpu_info *
15875 mips_cpu_info_from_arch (int arch)
15879 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15880 if (arch == mips_cpu_info_table[i].cpu)
15881 return (&mips_cpu_info_table[i]);
15887 show (FILE *stream, const char *string, int *col_p, int *first_p)
15891 fprintf (stream, "%24s", "");
15896 fprintf (stream, ", ");
15900 if (*col_p + strlen (string) > 72)
15902 fprintf (stream, "\n%24s", "");
15906 fprintf (stream, "%s", string);
15907 *col_p += strlen (string);
15913 md_show_usage (FILE *stream)
15918 fprintf (stream, _("\
15920 -EB generate big endian output\n\
15921 -EL generate little endian output\n\
15922 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15923 -G NUM allow referencing objects up to NUM bytes\n\
15924 implicitly with the gp register [default 8]\n"));
15925 fprintf (stream, _("\
15926 -mips1 generate MIPS ISA I instructions\n\
15927 -mips2 generate MIPS ISA II instructions\n\
15928 -mips3 generate MIPS ISA III instructions\n\
15929 -mips4 generate MIPS ISA IV instructions\n\
15930 -mips5 generate MIPS ISA V instructions\n\
15931 -mips32 generate MIPS32 ISA instructions\n\
15932 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15933 -mips64 generate MIPS64 ISA instructions\n\
15934 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15935 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15939 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15940 show (stream, mips_cpu_info_table[i].name, &column, &first);
15941 show (stream, "from-abi", &column, &first);
15942 fputc ('\n', stream);
15944 fprintf (stream, _("\
15945 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15946 -no-mCPU don't generate code specific to CPU.\n\
15947 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15951 show (stream, "3900", &column, &first);
15952 show (stream, "4010", &column, &first);
15953 show (stream, "4100", &column, &first);
15954 show (stream, "4650", &column, &first);
15955 fputc ('\n', stream);
15957 fprintf (stream, _("\
15958 -mips16 generate mips16 instructions\n\
15959 -no-mips16 do not generate mips16 instructions\n"));
15960 fprintf (stream, _("\
15961 -msmartmips generate smartmips instructions\n\
15962 -mno-smartmips do not generate smartmips instructions\n"));
15963 fprintf (stream, _("\
15964 -mdsp generate DSP instructions\n\
15965 -mno-dsp do not generate DSP instructions\n"));
15966 fprintf (stream, _("\
15967 -mdspr2 generate DSP R2 instructions\n\
15968 -mno-dspr2 do not generate DSP R2 instructions\n"));
15969 fprintf (stream, _("\
15970 -mmt generate MT instructions\n\
15971 -mno-mt do not generate MT instructions\n"));
15972 fprintf (stream, _("\
15973 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15974 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15975 -mfix-vr4120 work around certain VR4120 errata\n\
15976 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15977 -mfix-24k insert a nop after ERET and DERET instructions\n\
15978 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15979 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15980 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15981 -msym32 assume all symbols have 32-bit values\n\
15982 -O0 remove unneeded NOPs, do not swap branches\n\
15983 -O remove unneeded NOPs and swap branches\n\
15984 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15985 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15986 fprintf (stream, _("\
15987 -mhard-float allow floating-point instructions\n\
15988 -msoft-float do not allow floating-point instructions\n\
15989 -msingle-float only allow 32-bit floating-point operations\n\
15990 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15991 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15994 fprintf (stream, _("\
15995 -KPIC, -call_shared generate SVR4 position independent code\n\
15996 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15997 -mvxworks-pic generate VxWorks position independent code\n\
15998 -non_shared do not generate code that can operate with DSOs\n\
15999 -xgot assume a 32 bit GOT\n\
16000 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
16001 -mshared, -mno-shared disable/enable .cpload optimization for\n\
16002 position dependent (non shared) code\n\
16003 -mabi=ABI create ABI conformant object file for:\n"));
16007 show (stream, "32", &column, &first);
16008 show (stream, "o64", &column, &first);
16009 show (stream, "n32", &column, &first);
16010 show (stream, "64", &column, &first);
16011 show (stream, "eabi", &column, &first);
16013 fputc ('\n', stream);
16015 fprintf (stream, _("\
16016 -32 create o32 ABI object file (default)\n\
16017 -n32 create n32 ABI object file\n\
16018 -64 create 64 ABI object file\n"));
16024 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
16026 if (HAVE_64BIT_SYMBOLS)
16027 return dwarf2_format_64bit_irix;
16029 return dwarf2_format_32bit;
16034 mips_dwarf2_addr_size (void)
16036 if (HAVE_64BIT_OBJECTS)
16042 /* Standard calling conventions leave the CFA at SP on entry. */
16044 mips_cfi_frame_initial_instructions (void)
16046 cfi_add_CFA_def_cfa_register (SP);
16050 tc_mips_regname_to_dw2regnum (char *regname)
16052 unsigned int regnum = -1;
16055 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))