1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* True if this is a mips16 instruction and if we want the extended
150 bfd_boolean use_extend;
152 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
153 unsigned short extend;
155 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
156 a copy of INSN_MO->match with the operands filled in. */
157 unsigned long insn_opcode;
159 /* The frag that contains the instruction. */
162 /* The offset into FRAG of the first instruction byte. */
165 /* The relocs associated with the instruction, if any. */
168 /* True if this entry cannot be moved from its current position. */
169 unsigned int fixed_p : 1;
171 /* True if this instruction occurred in a .set noreorder block. */
172 unsigned int noreorder_p : 1;
174 /* True for mips16 instructions that jump to an absolute address. */
175 unsigned int mips16_absolute_jump_p : 1;
177 /* True if this instruction is complete. */
178 unsigned int complete_p : 1;
181 /* The ABI to use. */
192 /* MIPS ABI we are using for this output file. */
193 static enum mips_abi_level mips_abi = NO_ABI;
195 /* Whether or not we have code that can call pic code. */
196 int mips_abicalls = FALSE;
198 /* Whether or not we have code which can be put into a shared
200 static bfd_boolean mips_in_shared = TRUE;
202 /* This is the set of options which may be modified by the .set
203 pseudo-op. We use a struct so that .set push and .set pop are more
206 struct mips_set_options
208 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
209 if it has not been initialized. Changed by `.set mipsN', and the
210 -mipsN command line option, and the default CPU. */
212 /* Enabled Application Specific Extensions (ASEs). These are set to -1
213 if they have not been initialized. Changed by `.set <asename>', by
214 command line options, and based on the default architecture. */
222 /* Whether we are assembling for the mips16 processor. 0 if we are
223 not, 1 if we are, and -1 if the value has not been initialized.
224 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
225 -nomips16 command line options, and the default CPU. */
227 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
228 1 if we are, and -1 if the value has not been initialized. Changed
229 by `.set micromips' and `.set nomicromips', and the -mmicromips
230 and -mno-micromips command line options, and the default CPU. */
232 /* Non-zero if we should not reorder instructions. Changed by `.set
233 reorder' and `.set noreorder'. */
235 /* Non-zero if we should not permit the register designated "assembler
236 temporary" to be used in instructions. The value is the register
237 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
238 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
240 /* Non-zero if we should warn when a macro instruction expands into
241 more than one machine instruction. Changed by `.set nomacro' and
243 int warn_about_macros;
244 /* Non-zero if we should not move instructions. Changed by `.set
245 move', `.set volatile', `.set nomove', and `.set novolatile'. */
247 /* Non-zero if we should not optimize branches by moving the target
248 of the branch into the delay slot. Actually, we don't perform
249 this optimization anyhow. Changed by `.set bopt' and `.set
252 /* Non-zero if we should not autoextend mips16 instructions.
253 Changed by `.set autoextend' and `.set noautoextend'. */
255 /* Restrict general purpose registers and floating point registers
256 to 32 bit. This is initially determined when -mgp32 or -mfp32
257 is passed but can changed if the assembler code uses .set mipsN. */
260 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
261 command line option, and the default CPU. */
263 /* True if ".set sym32" is in effect. */
265 /* True if floating-point operations are not allowed. Changed by .set
266 softfloat or .set hardfloat, by command line options -msoft-float or
267 -mhard-float. The default is false. */
268 bfd_boolean soft_float;
270 /* True if only single-precision floating-point operations are allowed.
271 Changed by .set singlefloat or .set doublefloat, command-line options
272 -msingle-float or -mdouble-float. The default is false. */
273 bfd_boolean single_float;
276 /* This is the struct we use to hold the current set of options. Note
277 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
278 -1 to indicate that they have not been initialized. */
280 /* True if -mgp32 was passed. */
281 static int file_mips_gp32 = -1;
283 /* True if -mfp32 was passed. */
284 static int file_mips_fp32 = -1;
286 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
287 static int file_mips_soft_float = 0;
289 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
290 static int file_mips_single_float = 0;
292 static struct mips_set_options mips_opts =
294 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
295 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
296 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
297 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
298 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
299 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
302 /* These variables are filled in with the masks of registers used.
303 The object format code reads them and puts them in the appropriate
305 unsigned long mips_gprmask;
306 unsigned long mips_cprmask[4];
308 /* MIPS ISA we are using for this output file. */
309 static int file_mips_isa = ISA_UNKNOWN;
311 /* True if any MIPS16 code was produced. */
312 static int file_ase_mips16;
314 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
315 || mips_opts.isa == ISA_MIPS32R2 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2)
319 /* True if any microMIPS code was produced. */
320 static int file_ase_micromips;
322 /* True if we want to create R_MIPS_JALR for jalr $25. */
324 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
326 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
327 because there's no place for any addend, the only acceptable
328 expression is a bare symbol. */
329 #define MIPS_JALR_HINT_P(EXPR) \
330 (!HAVE_IN_PLACE_ADDENDS \
331 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
334 /* True if -mips3d was passed or implied by arguments passed on the
335 command line (e.g., by -march). */
336 static int file_ase_mips3d;
338 /* True if -mdmx was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340 static int file_ase_mdmx;
342 /* True if -msmartmips was passed or implied by arguments passed on the
343 command line (e.g., by -march). */
344 static int file_ase_smartmips;
346 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
347 || mips_opts.isa == ISA_MIPS32R2)
349 /* True if -mdsp was passed or implied by arguments passed on the
350 command line (e.g., by -march). */
351 static int file_ase_dsp;
353 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
354 || mips_opts.isa == ISA_MIPS64R2)
356 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
358 /* True if -mdspr2 was passed or implied by arguments passed on the
359 command line (e.g., by -march). */
360 static int file_ase_dspr2;
362 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
363 || mips_opts.isa == ISA_MIPS64R2)
365 /* True if -mmt was passed or implied by arguments passed on the
366 command line (e.g., by -march). */
367 static int file_ase_mt;
369 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2)
372 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
373 || mips_opts.isa == ISA_MIPS64R2)
375 /* The argument of the -march= flag. The architecture we are assembling. */
376 static int file_mips_arch = CPU_UNKNOWN;
377 static const char *mips_arch_string;
379 /* The argument of the -mtune= flag. The architecture for which we
381 static int mips_tune = CPU_UNKNOWN;
382 static const char *mips_tune_string;
384 /* True when generating 32-bit code for a 64-bit processor. */
385 static int mips_32bitmode = 0;
387 /* True if the given ABI requires 32-bit registers. */
388 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
390 /* Likewise 64-bit registers. */
391 #define ABI_NEEDS_64BIT_REGS(ABI) \
393 || (ABI) == N64_ABI \
396 /* Return true if ISA supports 64 bit wide gp registers. */
397 #define ISA_HAS_64BIT_REGS(ISA) \
398 ((ISA) == ISA_MIPS3 \
399 || (ISA) == ISA_MIPS4 \
400 || (ISA) == ISA_MIPS5 \
401 || (ISA) == ISA_MIPS64 \
402 || (ISA) == ISA_MIPS64R2)
404 /* Return true if ISA supports 64 bit wide float registers. */
405 #define ISA_HAS_64BIT_FPRS(ISA) \
406 ((ISA) == ISA_MIPS3 \
407 || (ISA) == ISA_MIPS4 \
408 || (ISA) == ISA_MIPS5 \
409 || (ISA) == ISA_MIPS32R2 \
410 || (ISA) == ISA_MIPS64 \
411 || (ISA) == ISA_MIPS64R2)
413 /* Return true if ISA supports 64-bit right rotate (dror et al.)
415 #define ISA_HAS_DROR(ISA) \
416 ((ISA) == ISA_MIPS64R2 \
417 || (mips_opts.micromips \
418 && ISA_HAS_64BIT_REGS (ISA)) \
421 /* Return true if ISA supports 32-bit right rotate (ror et al.)
423 #define ISA_HAS_ROR(ISA) \
424 ((ISA) == ISA_MIPS32R2 \
425 || (ISA) == ISA_MIPS64R2 \
426 || mips_opts.ase_smartmips \
427 || mips_opts.micromips \
430 /* Return true if ISA supports single-precision floats in odd registers. */
431 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
432 ((ISA) == ISA_MIPS32 \
433 || (ISA) == ISA_MIPS32R2 \
434 || (ISA) == ISA_MIPS64 \
435 || (ISA) == ISA_MIPS64R2)
437 /* Return true if ISA supports move to/from high part of a 64-bit
438 floating-point register. */
439 #define ISA_HAS_MXHC1(ISA) \
440 ((ISA) == ISA_MIPS32R2 \
441 || (ISA) == ISA_MIPS64R2)
443 #define HAVE_32BIT_GPRS \
444 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
446 #define HAVE_32BIT_FPRS \
447 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
449 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
450 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
452 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
454 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
456 /* True if relocations are stored in-place. */
457 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
459 /* The ABI-derived address size. */
460 #define HAVE_64BIT_ADDRESSES \
461 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
462 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
464 /* The size of symbolic constants (i.e., expressions of the form
465 "SYMBOL" or "SYMBOL + OFFSET"). */
466 #define HAVE_32BIT_SYMBOLS \
467 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
468 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
470 /* Addresses are loaded in different ways, depending on the address size
471 in use. The n32 ABI Documentation also mandates the use of additions
472 with overflow checking, but existing implementations don't follow it. */
473 #define ADDRESS_ADD_INSN \
474 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
476 #define ADDRESS_ADDI_INSN \
477 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
479 #define ADDRESS_LOAD_INSN \
480 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
482 #define ADDRESS_STORE_INSN \
483 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
485 /* Return true if the given CPU supports the MIPS16 ASE. */
486 #define CPU_HAS_MIPS16(cpu) \
487 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
488 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
490 /* Return true if the given CPU supports the microMIPS ASE. */
491 #define CPU_HAS_MICROMIPS(cpu) 0
493 /* True if CPU has a dror instruction. */
494 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
496 /* True if CPU has a ror instruction. */
497 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
499 /* True if CPU has seq/sne and seqi/snei instructions. */
500 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
502 /* True if CPU does not implement the all the coprocessor insns. For these
503 CPUs only those COP insns are accepted that are explicitly marked to be
504 available on the CPU. ISA membership for COP insns is ignored. */
505 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
507 /* True if mflo and mfhi can be immediately followed by instructions
508 which write to the HI and LO registers.
510 According to MIPS specifications, MIPS ISAs I, II, and III need
511 (at least) two instructions between the reads of HI/LO and
512 instructions which write them, and later ISAs do not. Contradicting
513 the MIPS specifications, some MIPS IV processor user manuals (e.g.
514 the UM for the NEC Vr5000) document needing the instructions between
515 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
516 MIPS64 and later ISAs to have the interlocks, plus any specific
517 earlier-ISA CPUs for which CPU documentation declares that the
518 instructions are really interlocked. */
519 #define hilo_interlocks \
520 (mips_opts.isa == ISA_MIPS32 \
521 || mips_opts.isa == ISA_MIPS32R2 \
522 || mips_opts.isa == ISA_MIPS64 \
523 || mips_opts.isa == ISA_MIPS64R2 \
524 || mips_opts.arch == CPU_R4010 \
525 || mips_opts.arch == CPU_R10000 \
526 || mips_opts.arch == CPU_R12000 \
527 || mips_opts.arch == CPU_R14000 \
528 || mips_opts.arch == CPU_R16000 \
529 || mips_opts.arch == CPU_RM7000 \
530 || mips_opts.arch == CPU_VR5500 \
531 || mips_opts.micromips \
534 /* Whether the processor uses hardware interlocks to protect reads
535 from the GPRs after they are loaded from memory, and thus does not
536 require nops to be inserted. This applies to instructions marked
537 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
538 level I and microMIPS mode instructions are always interlocked. */
539 #define gpr_interlocks \
540 (mips_opts.isa != ISA_MIPS1 \
541 || mips_opts.arch == CPU_R3900 \
542 || mips_opts.micromips \
545 /* Whether the processor uses hardware interlocks to avoid delays
546 required by coprocessor instructions, and thus does not require
547 nops to be inserted. This applies to instructions marked
548 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
549 between instructions marked INSN_WRITE_COND_CODE and ones marked
550 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
551 levels I, II, and III and microMIPS mode instructions are always
553 /* Itbl support may require additional care here. */
554 #define cop_interlocks \
555 ((mips_opts.isa != ISA_MIPS1 \
556 && mips_opts.isa != ISA_MIPS2 \
557 && mips_opts.isa != ISA_MIPS3) \
558 || mips_opts.arch == CPU_R4300 \
559 || mips_opts.micromips \
562 /* Whether the processor uses hardware interlocks to protect reads
563 from coprocessor registers after they are loaded from memory, and
564 thus does not require nops to be inserted. This applies to
565 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
566 requires at MIPS ISA level I and microMIPS mode instructions are
567 always interlocked. */
568 #define cop_mem_interlocks \
569 (mips_opts.isa != ISA_MIPS1 \
570 || mips_opts.micromips \
573 /* Is this a mfhi or mflo instruction? */
574 #define MF_HILO_INSN(PINFO) \
575 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
577 /* Returns true for a (non floating-point) coprocessor instruction. Reading
578 or writing the condition code is only possible on the coprocessors and
579 these insns are not marked with INSN_COP. Thus for these insns use the
580 condition-code flags. */
581 #define COP_INSN(PINFO) \
582 (PINFO != INSN_MACRO \
583 && ((PINFO) & (FP_S | FP_D)) == 0 \
584 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
586 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
587 has been selected. This implies, in particular, that addresses of text
588 labels have their LSB set. */
589 #define HAVE_CODE_COMPRESSION \
590 ((mips_opts.mips16 | mips_opts.micromips) != 0)
592 /* MIPS PIC level. */
594 enum mips_pic_level mips_pic;
596 /* 1 if we should generate 32 bit offsets from the $gp register in
597 SVR4_PIC mode. Currently has no meaning in other modes. */
598 static int mips_big_got = 0;
600 /* 1 if trap instructions should used for overflow rather than break
602 static int mips_trap = 0;
604 /* 1 if double width floating point constants should not be constructed
605 by assembling two single width halves into two single width floating
606 point registers which just happen to alias the double width destination
607 register. On some architectures this aliasing can be disabled by a bit
608 in the status register, and the setting of this bit cannot be determined
609 automatically at assemble time. */
610 static int mips_disable_float_construction;
612 /* Non-zero if any .set noreorder directives were used. */
614 static int mips_any_noreorder;
616 /* Non-zero if nops should be inserted when the register referenced in
617 an mfhi/mflo instruction is read in the next two instructions. */
618 static int mips_7000_hilo_fix;
620 /* The size of objects in the small data section. */
621 static unsigned int g_switch_value = 8;
622 /* Whether the -G option was used. */
623 static int g_switch_seen = 0;
628 /* If we can determine in advance that GP optimization won't be
629 possible, we can skip the relaxation stuff that tries to produce
630 GP-relative references. This makes delay slot optimization work
633 This function can only provide a guess, but it seems to work for
634 gcc output. It needs to guess right for gcc, otherwise gcc
635 will put what it thinks is a GP-relative instruction in a branch
638 I don't know if a fix is needed for the SVR4_PIC mode. I've only
639 fixed it for the non-PIC mode. KR 95/04/07 */
640 static int nopic_need_relax (symbolS *, int);
642 /* handle of the OPCODE hash table */
643 static struct hash_control *op_hash = NULL;
645 /* The opcode hash table we use for the mips16. */
646 static struct hash_control *mips16_op_hash = NULL;
648 /* The opcode hash table we use for the microMIPS ASE. */
649 static struct hash_control *micromips_op_hash = NULL;
651 /* This array holds the chars that always start a comment. If the
652 pre-processor is disabled, these aren't very useful */
653 const char comment_chars[] = "#";
655 /* This array holds the chars that only start a comment at the beginning of
656 a line. If the line seems to have the form '# 123 filename'
657 .line and .file directives will appear in the pre-processed output */
658 /* Note that input_file.c hand checks for '#' at the beginning of the
659 first line of the input file. This is because the compiler outputs
660 #NO_APP at the beginning of its output. */
661 /* Also note that C style comments are always supported. */
662 const char line_comment_chars[] = "#";
664 /* This array holds machine specific line separator characters. */
665 const char line_separator_chars[] = ";";
667 /* Chars that can be used to separate mant from exp in floating point nums */
668 const char EXP_CHARS[] = "eE";
670 /* Chars that mean this number is a floating point constant */
673 const char FLT_CHARS[] = "rRsSfFdDxXpP";
675 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
676 changed in read.c . Ideally it shouldn't have to know about it at all,
677 but nothing is ideal around here.
680 static char *insn_error;
682 static int auto_align = 1;
684 /* When outputting SVR4 PIC code, the assembler needs to know the
685 offset in the stack frame from which to restore the $gp register.
686 This is set by the .cprestore pseudo-op, and saved in this
688 static offsetT mips_cprestore_offset = -1;
690 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
691 more optimizations, it can use a register value instead of a memory-saved
692 offset and even an other register than $gp as global pointer. */
693 static offsetT mips_cpreturn_offset = -1;
694 static int mips_cpreturn_register = -1;
695 static int mips_gp_register = GP;
696 static int mips_gprel_offset = 0;
698 /* Whether mips_cprestore_offset has been set in the current function
699 (or whether it has already been warned about, if not). */
700 static int mips_cprestore_valid = 0;
702 /* This is the register which holds the stack frame, as set by the
703 .frame pseudo-op. This is needed to implement .cprestore. */
704 static int mips_frame_reg = SP;
706 /* Whether mips_frame_reg has been set in the current function
707 (or whether it has already been warned about, if not). */
708 static int mips_frame_reg_valid = 0;
710 /* To output NOP instructions correctly, we need to keep information
711 about the previous two instructions. */
713 /* Whether we are optimizing. The default value of 2 means to remove
714 unneeded NOPs and swap branch instructions when possible. A value
715 of 1 means to not swap branches. A value of 0 means to always
717 static int mips_optimize = 2;
719 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
720 equivalent to seeing no -g option at all. */
721 static int mips_debug = 0;
723 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
724 #define MAX_VR4130_NOPS 4
726 /* The maximum number of NOPs needed to fill delay slots. */
727 #define MAX_DELAY_NOPS 2
729 /* The maximum number of NOPs needed for any purpose. */
732 /* A list of previous instructions, with index 0 being the most recent.
733 We need to look back MAX_NOPS instructions when filling delay slots
734 or working around processor errata. We need to look back one
735 instruction further if we're thinking about using history[0] to
736 fill a branch delay slot. */
737 static struct mips_cl_insn history[1 + MAX_NOPS];
739 /* Nop instructions used by emit_nop. */
740 static struct mips_cl_insn nop_insn;
741 static struct mips_cl_insn mips16_nop_insn;
742 static struct mips_cl_insn micromips_nop16_insn;
743 static struct mips_cl_insn micromips_nop32_insn;
745 /* The appropriate nop for the current mode. */
746 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
747 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
749 /* The size of NOP_INSN in bytes. */
750 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
752 /* If this is set, it points to a frag holding nop instructions which
753 were inserted before the start of a noreorder section. If those
754 nops turn out to be unnecessary, the size of the frag can be
756 static fragS *prev_nop_frag;
758 /* The number of nop instructions we created in prev_nop_frag. */
759 static int prev_nop_frag_holds;
761 /* The number of nop instructions that we know we need in
763 static int prev_nop_frag_required;
765 /* The number of instructions we've seen since prev_nop_frag. */
766 static int prev_nop_frag_since;
768 /* For ECOFF and ELF, relocations against symbols are done in two
769 parts, with a HI relocation and a LO relocation. Each relocation
770 has only 16 bits of space to store an addend. This means that in
771 order for the linker to handle carries correctly, it must be able
772 to locate both the HI and the LO relocation. This means that the
773 relocations must appear in order in the relocation table.
775 In order to implement this, we keep track of each unmatched HI
776 relocation. We then sort them so that they immediately precede the
777 corresponding LO relocation. */
782 struct mips_hi_fixup *next;
785 /* The section this fixup is in. */
789 /* The list of unmatched HI relocs. */
791 static struct mips_hi_fixup *mips_hi_fixup_list;
793 /* The frag containing the last explicit relocation operator.
794 Null if explicit relocations have not been used. */
796 static fragS *prev_reloc_op_frag;
798 /* Map normal MIPS register numbers to mips16 register numbers. */
800 #define X ILLEGAL_REG
801 static const int mips32_to_16_reg_map[] =
803 X, X, 2, 3, 4, 5, 6, 7,
804 X, X, X, X, X, X, X, X,
805 0, 1, X, X, X, X, X, X,
806 X, X, X, X, X, X, X, X
810 /* Map mips16 register numbers to normal MIPS register numbers. */
812 static const unsigned int mips16_to_32_reg_map[] =
814 16, 17, 2, 3, 4, 5, 6, 7
817 /* Map normal MIPS register numbers to microMIPS register numbers. */
819 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
820 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
821 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
822 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
823 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
824 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
825 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
827 #define X ILLEGAL_REG
828 /* reg type h: 4, 5, 6. */
829 static const int mips32_to_micromips_reg_h_map[] =
831 X, X, X, X, 4, 5, 6, X,
832 X, X, X, X, X, X, X, X,
833 X, X, X, X, X, X, X, X,
834 X, X, X, X, X, X, X, X
837 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
838 static const int mips32_to_micromips_reg_m_map[] =
840 0, X, 2, 3, X, X, X, X,
841 X, X, X, X, X, X, X, X,
842 4, 1, 5, 6, 7, X, X, X,
843 X, X, X, X, X, X, X, X
846 /* reg type q: 0, 2-7. 17. */
847 static const int mips32_to_micromips_reg_q_map[] =
849 0, X, 2, 3, 4, 5, 6, 7,
850 X, X, X, X, X, X, X, X,
851 X, 1, X, X, X, X, X, X,
852 X, X, X, X, X, X, X, X
855 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
858 /* Map microMIPS register numbers to normal MIPS register numbers. */
860 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
861 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
862 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
863 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
864 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
865 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
867 /* The microMIPS registers with type h. */
868 static const unsigned int micromips_to_32_reg_h_map[] =
870 5, 5, 6, 4, 4, 4, 4, 4
873 /* The microMIPS registers with type i. */
874 static const unsigned int micromips_to_32_reg_i_map[] =
876 6, 7, 7, 21, 22, 5, 6, 7
879 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
881 /* The microMIPS registers with type m. */
882 static const unsigned int micromips_to_32_reg_m_map[] =
884 0, 17, 2, 3, 16, 18, 19, 20
887 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
889 /* The microMIPS registers with type q. */
890 static const unsigned int micromips_to_32_reg_q_map[] =
892 0, 17, 2, 3, 4, 5, 6, 7
895 /* microMIPS imm type B. */
896 static const int micromips_imm_b_map[] =
898 1, 4, 8, 12, 16, 20, 24, -1
901 /* microMIPS imm type C. */
902 static const int micromips_imm_c_map[] =
904 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
907 /* Classifies the kind of instructions we're interested in when
908 implementing -mfix-vr4120. */
909 enum fix_vr4120_class
917 NUM_FIX_VR4120_CLASSES
920 /* ...likewise -mfix-loongson2f-jump. */
921 static bfd_boolean mips_fix_loongson2f_jump;
923 /* ...likewise -mfix-loongson2f-nop. */
924 static bfd_boolean mips_fix_loongson2f_nop;
926 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
927 static bfd_boolean mips_fix_loongson2f;
929 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
930 there must be at least one other instruction between an instruction
931 of type X and an instruction of type Y. */
932 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
934 /* True if -mfix-vr4120 is in force. */
935 static int mips_fix_vr4120;
937 /* ...likewise -mfix-vr4130. */
938 static int mips_fix_vr4130;
940 /* ...likewise -mfix-24k. */
941 static int mips_fix_24k;
943 /* ...likewise -mfix-cn63xxp1 */
944 static bfd_boolean mips_fix_cn63xxp1;
946 /* We don't relax branches by default, since this causes us to expand
947 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
948 fail to compute the offset before expanding the macro to the most
949 efficient expansion. */
951 static int mips_relax_branch;
953 /* The expansion of many macros depends on the type of symbol that
954 they refer to. For example, when generating position-dependent code,
955 a macro that refers to a symbol may have two different expansions,
956 one which uses GP-relative addresses and one which uses absolute
957 addresses. When generating SVR4-style PIC, a macro may have
958 different expansions for local and global symbols.
960 We handle these situations by generating both sequences and putting
961 them in variant frags. In position-dependent code, the first sequence
962 will be the GP-relative one and the second sequence will be the
963 absolute one. In SVR4 PIC, the first sequence will be for global
964 symbols and the second will be for local symbols.
966 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
967 SECOND are the lengths of the two sequences in bytes. These fields
968 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
969 the subtype has the following flags:
972 Set if it has been decided that we should use the second
973 sequence instead of the first.
976 Set in the first variant frag if the macro's second implementation
977 is longer than its first. This refers to the macro as a whole,
978 not an individual relaxation.
981 Set in the first variant frag if the macro appeared in a .set nomacro
982 block and if one alternative requires a warning but the other does not.
985 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
988 RELAX_DELAY_SLOT_16BIT
989 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
992 RELAX_DELAY_SLOT_SIZE_FIRST
993 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
994 the macro is of the wrong size for the branch delay slot.
996 RELAX_DELAY_SLOT_SIZE_SECOND
997 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
998 the macro is of the wrong size for the branch delay slot.
1000 The frag's "opcode" points to the first fixup for relaxable code.
1002 Relaxable macros are generated using a sequence such as:
1004 relax_start (SYMBOL);
1005 ... generate first expansion ...
1007 ... generate second expansion ...
1010 The code and fixups for the unwanted alternative are discarded
1011 by md_convert_frag. */
1012 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1014 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1015 #define RELAX_SECOND(X) ((X) & 0xff)
1016 #define RELAX_USE_SECOND 0x10000
1017 #define RELAX_SECOND_LONGER 0x20000
1018 #define RELAX_NOMACRO 0x40000
1019 #define RELAX_DELAY_SLOT 0x80000
1020 #define RELAX_DELAY_SLOT_16BIT 0x100000
1021 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1022 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1024 /* Branch without likely bit. If label is out of range, we turn:
1026 beq reg1, reg2, label
1036 with the following opcode replacements:
1043 bltzal <-> bgezal (with jal label instead of j label)
1045 Even though keeping the delay slot instruction in the delay slot of
1046 the branch would be more efficient, it would be very tricky to do
1047 correctly, because we'd have to introduce a variable frag *after*
1048 the delay slot instruction, and expand that instead. Let's do it
1049 the easy way for now, even if the branch-not-taken case now costs
1050 one additional instruction. Out-of-range branches are not supposed
1051 to be common, anyway.
1053 Branch likely. If label is out of range, we turn:
1055 beql reg1, reg2, label
1056 delay slot (annulled if branch not taken)
1065 delay slot (executed only if branch taken)
1068 It would be possible to generate a shorter sequence by losing the
1069 likely bit, generating something like:
1074 delay slot (executed only if branch taken)
1086 bltzall -> bgezal (with jal label instead of j label)
1087 bgezall -> bltzal (ditto)
1090 but it's not clear that it would actually improve performance. */
1091 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1092 ((relax_substateT) \
1095 | ((toofar) ? 0x20 : 0) \
1096 | ((link) ? 0x40 : 0) \
1097 | ((likely) ? 0x80 : 0) \
1098 | ((uncond) ? 0x100 : 0)))
1099 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1100 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1101 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1102 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1103 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1104 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1106 /* For mips16 code, we use an entirely different form of relaxation.
1107 mips16 supports two versions of most instructions which take
1108 immediate values: a small one which takes some small value, and a
1109 larger one which takes a 16 bit value. Since branches also follow
1110 this pattern, relaxing these values is required.
1112 We can assemble both mips16 and normal MIPS code in a single
1113 object. Therefore, we need to support this type of relaxation at
1114 the same time that we support the relaxation described above. We
1115 use the high bit of the subtype field to distinguish these cases.
1117 The information we store for this type of relaxation is the
1118 argument code found in the opcode file for this relocation, whether
1119 the user explicitly requested a small or extended form, and whether
1120 the relocation is in a jump or jal delay slot. That tells us the
1121 size of the value, and how it should be stored. We also store
1122 whether the fragment is considered to be extended or not. We also
1123 store whether this is known to be a branch to a different section,
1124 whether we have tried to relax this frag yet, and whether we have
1125 ever extended a PC relative fragment because of a shift count. */
1126 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1129 | ((small) ? 0x100 : 0) \
1130 | ((ext) ? 0x200 : 0) \
1131 | ((dslot) ? 0x400 : 0) \
1132 | ((jal_dslot) ? 0x800 : 0))
1133 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1134 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1135 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1136 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1137 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1138 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1139 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1140 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1141 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1142 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1143 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1144 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1146 /* For microMIPS code, we use relaxation similar to one we use for
1147 MIPS16 code. Some instructions that take immediate values support
1148 two encodings: a small one which takes some small value, and a
1149 larger one which takes a 16 bit value. As some branches also follow
1150 this pattern, relaxing these values is required.
1152 We can assemble both microMIPS and normal MIPS code in a single
1153 object. Therefore, we need to support this type of relaxation at
1154 the same time that we support the relaxation described above. We
1155 use one of the high bits of the subtype field to distinguish these
1158 The information we store for this type of relaxation is the argument
1159 code found in the opcode file for this relocation, the register
1160 selected as the assembler temporary, whether the branch is
1161 unconditional, whether it is compact, whether it stores the link
1162 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1163 branches to a sequence of instructions is enabled, and whether the
1164 displacement of a branch is too large to fit as an immediate argument
1165 of a 16-bit and a 32-bit branch, respectively. */
1166 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1167 relax32, toofar16, toofar32) \
1170 | (((at) & 0x1f) << 8) \
1171 | ((uncond) ? 0x2000 : 0) \
1172 | ((compact) ? 0x4000 : 0) \
1173 | ((link) ? 0x8000 : 0) \
1174 | ((relax32) ? 0x10000 : 0) \
1175 | ((toofar16) ? 0x20000 : 0) \
1176 | ((toofar32) ? 0x40000 : 0))
1177 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1178 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1180 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1181 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1182 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1183 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1185 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1186 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1187 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1188 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1189 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1190 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1192 /* Is the given value a sign-extended 32-bit value? */
1193 #define IS_SEXT_32BIT_NUM(x) \
1194 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1195 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1197 /* Is the given value a sign-extended 16-bit value? */
1198 #define IS_SEXT_16BIT_NUM(x) \
1199 (((x) &~ (offsetT) 0x7fff) == 0 \
1200 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1202 /* Is the given value a sign-extended 12-bit value? */
1203 #define IS_SEXT_12BIT_NUM(x) \
1204 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1206 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1207 #define IS_ZEXT_32BIT_NUM(x) \
1208 (((x) &~ (offsetT) 0xffffffff) == 0 \
1209 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1211 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1212 VALUE << SHIFT. VALUE is evaluated exactly once. */
1213 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1214 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1215 | (((VALUE) & (MASK)) << (SHIFT)))
1217 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1219 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1220 (((STRUCT) >> (SHIFT)) & (MASK))
1222 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1223 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1225 include/opcode/mips.h specifies operand fields using the macros
1226 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1227 with "MIPS16OP" instead of "OP". */
1228 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1231 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1232 OP_MASK_##FIELD, OP_SH_##FIELD); \
1234 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1235 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1237 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1238 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1239 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1241 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1242 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1244 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1245 : EXTRACT_BITS ((INSN).insn_opcode, \
1246 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1247 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1248 EXTRACT_BITS ((INSN).insn_opcode, \
1249 MIPS16OP_MASK_##FIELD, \
1250 MIPS16OP_SH_##FIELD)
1252 /* Whether or not we are emitting a branch-likely macro. */
1253 static bfd_boolean emit_branch_likely_macro = FALSE;
1255 /* Global variables used when generating relaxable macros. See the
1256 comment above RELAX_ENCODE for more details about how relaxation
1259 /* 0 if we're not emitting a relaxable macro.
1260 1 if we're emitting the first of the two relaxation alternatives.
1261 2 if we're emitting the second alternative. */
1264 /* The first relaxable fixup in the current frag. (In other words,
1265 the first fixup that refers to relaxable code.) */
1268 /* sizes[0] says how many bytes of the first alternative are stored in
1269 the current frag. Likewise sizes[1] for the second alternative. */
1270 unsigned int sizes[2];
1272 /* The symbol on which the choice of sequence depends. */
1276 /* Global variables used to decide whether a macro needs a warning. */
1278 /* True if the macro is in a branch delay slot. */
1279 bfd_boolean delay_slot_p;
1281 /* Set to the length in bytes required if the macro is in a delay slot
1282 that requires a specific length of instruction, otherwise zero. */
1283 unsigned int delay_slot_length;
1285 /* For relaxable macros, sizes[0] is the length of the first alternative
1286 in bytes and sizes[1] is the length of the second alternative.
1287 For non-relaxable macros, both elements give the length of the
1289 unsigned int sizes[2];
1291 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1292 instruction of the first alternative in bytes and first_insn_sizes[1]
1293 is the length of the first instruction of the second alternative.
1294 For non-relaxable macros, both elements give the length of the first
1295 instruction in bytes.
1297 Set to zero if we haven't yet seen the first instruction. */
1298 unsigned int first_insn_sizes[2];
1300 /* For relaxable macros, insns[0] is the number of instructions for the
1301 first alternative and insns[1] is the number of instructions for the
1304 For non-relaxable macros, both elements give the number of
1305 instructions for the macro. */
1306 unsigned int insns[2];
1308 /* The first variant frag for this macro. */
1310 } mips_macro_warning;
1312 /* Prototypes for static functions. */
1314 #define internalError() \
1315 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1317 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1319 static void append_insn
1320 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1321 bfd_boolean expansionp);
1322 static void mips_no_prev_insn (void);
1323 static void macro_build (expressionS *, const char *, const char *, ...);
1324 static void mips16_macro_build
1325 (expressionS *, const char *, const char *, va_list *);
1326 static void load_register (int, expressionS *, int);
1327 static void macro_start (void);
1328 static void macro_end (void);
1329 static void macro (struct mips_cl_insn * ip);
1330 static void mips16_macro (struct mips_cl_insn * ip);
1331 static void mips_ip (char *str, struct mips_cl_insn * ip);
1332 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1333 static void mips16_immed
1334 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1335 unsigned long *, bfd_boolean *, unsigned short *);
1336 static size_t my_getSmallExpression
1337 (expressionS *, bfd_reloc_code_real_type *, char *);
1338 static void my_getExpression (expressionS *, char *);
1339 static void s_align (int);
1340 static void s_change_sec (int);
1341 static void s_change_section (int);
1342 static void s_cons (int);
1343 static void s_float_cons (int);
1344 static void s_mips_globl (int);
1345 static void s_option (int);
1346 static void s_mipsset (int);
1347 static void s_abicalls (int);
1348 static void s_cpload (int);
1349 static void s_cpsetup (int);
1350 static void s_cplocal (int);
1351 static void s_cprestore (int);
1352 static void s_cpreturn (int);
1353 static void s_dtprelword (int);
1354 static void s_dtpreldword (int);
1355 static void s_gpvalue (int);
1356 static void s_gpword (int);
1357 static void s_gpdword (int);
1358 static void s_cpadd (int);
1359 static void s_insn (int);
1360 static void md_obj_begin (void);
1361 static void md_obj_end (void);
1362 static void s_mips_ent (int);
1363 static void s_mips_end (int);
1364 static void s_mips_frame (int);
1365 static void s_mips_mask (int reg_type);
1366 static void s_mips_stab (int);
1367 static void s_mips_weakext (int);
1368 static void s_mips_file (int);
1369 static void s_mips_loc (int);
1370 static bfd_boolean pic_need_relax (symbolS *, asection *);
1371 static int relaxed_branch_length (fragS *, asection *, int);
1372 static int validate_mips_insn (const struct mips_opcode *);
1373 static int validate_micromips_insn (const struct mips_opcode *);
1374 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1375 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1377 /* Table and functions used to map between CPU/ISA names, and
1378 ISA levels, and CPU numbers. */
1380 struct mips_cpu_info
1382 const char *name; /* CPU or ISA name. */
1383 int flags; /* ASEs available, or ISA flag. */
1384 int isa; /* ISA level. */
1385 int cpu; /* CPU number (default CPU if ISA). */
1388 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1389 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1390 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1391 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1392 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1393 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1394 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1395 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1397 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1398 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1399 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1403 The following pseudo-ops from the Kane and Heinrich MIPS book
1404 should be defined here, but are currently unsupported: .alias,
1405 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1407 The following pseudo-ops from the Kane and Heinrich MIPS book are
1408 specific to the type of debugging information being generated, and
1409 should be defined by the object format: .aent, .begin, .bend,
1410 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1413 The following pseudo-ops from the Kane and Heinrich MIPS book are
1414 not MIPS CPU specific, but are also not specific to the object file
1415 format. This file is probably the best place to define them, but
1416 they are not currently supported: .asm0, .endr, .lab, .struct. */
1418 static const pseudo_typeS mips_pseudo_table[] =
1420 /* MIPS specific pseudo-ops. */
1421 {"option", s_option, 0},
1422 {"set", s_mipsset, 0},
1423 {"rdata", s_change_sec, 'r'},
1424 {"sdata", s_change_sec, 's'},
1425 {"livereg", s_ignore, 0},
1426 {"abicalls", s_abicalls, 0},
1427 {"cpload", s_cpload, 0},
1428 {"cpsetup", s_cpsetup, 0},
1429 {"cplocal", s_cplocal, 0},
1430 {"cprestore", s_cprestore, 0},
1431 {"cpreturn", s_cpreturn, 0},
1432 {"dtprelword", s_dtprelword, 0},
1433 {"dtpreldword", s_dtpreldword, 0},
1434 {"gpvalue", s_gpvalue, 0},
1435 {"gpword", s_gpword, 0},
1436 {"gpdword", s_gpdword, 0},
1437 {"cpadd", s_cpadd, 0},
1438 {"insn", s_insn, 0},
1440 /* Relatively generic pseudo-ops that happen to be used on MIPS
1442 {"asciiz", stringer, 8 + 1},
1443 {"bss", s_change_sec, 'b'},
1445 {"half", s_cons, 1},
1446 {"dword", s_cons, 3},
1447 {"weakext", s_mips_weakext, 0},
1448 {"origin", s_org, 0},
1449 {"repeat", s_rept, 0},
1451 /* For MIPS this is non-standard, but we define it for consistency. */
1452 {"sbss", s_change_sec, 'B'},
1454 /* These pseudo-ops are defined in read.c, but must be overridden
1455 here for one reason or another. */
1456 {"align", s_align, 0},
1457 {"byte", s_cons, 0},
1458 {"data", s_change_sec, 'd'},
1459 {"double", s_float_cons, 'd'},
1460 {"float", s_float_cons, 'f'},
1461 {"globl", s_mips_globl, 0},
1462 {"global", s_mips_globl, 0},
1463 {"hword", s_cons, 1},
1465 {"long", s_cons, 2},
1466 {"octa", s_cons, 4},
1467 {"quad", s_cons, 3},
1468 {"section", s_change_section, 0},
1469 {"short", s_cons, 1},
1470 {"single", s_float_cons, 'f'},
1471 {"stabn", s_mips_stab, 'n'},
1472 {"text", s_change_sec, 't'},
1473 {"word", s_cons, 2},
1475 { "extern", ecoff_directive_extern, 0},
1480 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1482 /* These pseudo-ops should be defined by the object file format.
1483 However, a.out doesn't support them, so we have versions here. */
1484 {"aent", s_mips_ent, 1},
1485 {"bgnb", s_ignore, 0},
1486 {"end", s_mips_end, 0},
1487 {"endb", s_ignore, 0},
1488 {"ent", s_mips_ent, 0},
1489 {"file", s_mips_file, 0},
1490 {"fmask", s_mips_mask, 'F'},
1491 {"frame", s_mips_frame, 0},
1492 {"loc", s_mips_loc, 0},
1493 {"mask", s_mips_mask, 'R'},
1494 {"verstamp", s_ignore, 0},
1498 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1499 purpose of the `.dc.a' internal pseudo-op. */
1502 mips_address_bytes (void)
1504 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1507 extern void pop_insert (const pseudo_typeS *);
1510 mips_pop_insert (void)
1512 pop_insert (mips_pseudo_table);
1513 if (! ECOFF_DEBUGGING)
1514 pop_insert (mips_nonecoff_pseudo_table);
1517 /* Symbols labelling the current insn. */
1519 struct insn_label_list
1521 struct insn_label_list *next;
1525 static struct insn_label_list *free_insn_labels;
1526 #define label_list tc_segment_info_data.labels
1528 static void mips_clear_insn_labels (void);
1529 static void mips_mark_labels (void);
1530 static void mips_compressed_mark_labels (void);
1533 mips_clear_insn_labels (void)
1535 register struct insn_label_list **pl;
1536 segment_info_type *si;
1540 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1543 si = seg_info (now_seg);
1544 *pl = si->label_list;
1545 si->label_list = NULL;
1549 /* Mark instruction labels in MIPS16/microMIPS mode. */
1552 mips_mark_labels (void)
1554 if (HAVE_CODE_COMPRESSION)
1555 mips_compressed_mark_labels ();
1558 static char *expr_end;
1560 /* Expressions which appear in instructions. These are set by
1563 static expressionS imm_expr;
1564 static expressionS imm2_expr;
1565 static expressionS offset_expr;
1567 /* Relocs associated with imm_expr and offset_expr. */
1569 static bfd_reloc_code_real_type imm_reloc[3]
1570 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1571 static bfd_reloc_code_real_type offset_reloc[3]
1572 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1574 /* This is set to the resulting size of the instruction to be produced
1575 by mips16_ip if an explicit extension is used or by mips_ip if an
1576 explicit size is supplied. */
1578 static unsigned int forced_insn_length;
1581 /* The pdr segment for per procedure frame/regmask info. Not used for
1584 static segT pdr_seg;
1587 /* The default target format to use. */
1589 #if defined (TE_FreeBSD)
1590 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1591 #elif defined (TE_TMIPS)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1598 mips_target_format (void)
1600 switch (OUTPUT_FLAVOR)
1602 case bfd_target_ecoff_flavour:
1603 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1604 case bfd_target_coff_flavour:
1606 case bfd_target_elf_flavour:
1608 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1609 return (target_big_endian
1610 ? "elf32-bigmips-vxworks"
1611 : "elf32-littlemips-vxworks");
1613 return (target_big_endian
1614 ? (HAVE_64BIT_OBJECTS
1615 ? ELF_TARGET ("elf64-", "big")
1617 ? ELF_TARGET ("elf32-n", "big")
1618 : ELF_TARGET ("elf32-", "big")))
1619 : (HAVE_64BIT_OBJECTS
1620 ? ELF_TARGET ("elf64-", "little")
1622 ? ELF_TARGET ("elf32-n", "little")
1623 : ELF_TARGET ("elf32-", "little"))));
1630 /* Return the length of a microMIPS instruction in bytes. If bits of
1631 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1632 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1633 major opcode) will require further modifications to the opcode
1636 static inline unsigned int
1637 micromips_insn_length (const struct mips_opcode *mo)
1639 return (mo->mask >> 16) == 0 ? 2 : 4;
1642 /* Return the length of instruction INSN. */
1644 static inline unsigned int
1645 insn_length (const struct mips_cl_insn *insn)
1647 if (mips_opts.micromips)
1648 return micromips_insn_length (insn->insn_mo);
1649 else if (mips_opts.mips16)
1650 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1655 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1658 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1663 insn->use_extend = FALSE;
1665 insn->insn_opcode = mo->match;
1668 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1669 insn->fixp[i] = NULL;
1670 insn->fixed_p = (mips_opts.noreorder > 0);
1671 insn->noreorder_p = (mips_opts.noreorder > 0);
1672 insn->mips16_absolute_jump_p = 0;
1673 insn->complete_p = 0;
1676 /* Record the current MIPS16/microMIPS mode in now_seg. */
1679 mips_record_compressed_mode (void)
1681 segment_info_type *si;
1683 si = seg_info (now_seg);
1684 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1685 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1686 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1687 si->tc_segment_info_data.micromips = mips_opts.micromips;
1690 /* Install INSN at the location specified by its "frag" and "where" fields. */
1693 install_insn (const struct mips_cl_insn *insn)
1695 char *f = insn->frag->fr_literal + insn->where;
1696 if (!HAVE_CODE_COMPRESSION)
1697 md_number_to_chars (f, insn->insn_opcode, 4);
1698 else if (mips_opts.micromips)
1700 unsigned int length = insn_length (insn);
1702 md_number_to_chars (f, insn->insn_opcode, 2);
1703 else if (length == 4)
1705 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1707 md_number_to_chars (f, insn->insn_opcode & 0xffff, 2);
1710 as_bad (_("48-bit microMIPS instructions are not supported"));
1712 else if (insn->mips16_absolute_jump_p)
1714 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1715 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1719 if (insn->use_extend)
1721 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1724 md_number_to_chars (f, insn->insn_opcode, 2);
1726 mips_record_compressed_mode ();
1729 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1730 and install the opcode in the new location. */
1733 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1738 insn->where = where;
1739 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1740 if (insn->fixp[i] != NULL)
1742 insn->fixp[i]->fx_frag = frag;
1743 insn->fixp[i]->fx_where = where;
1745 install_insn (insn);
1748 /* Add INSN to the end of the output. */
1751 add_fixed_insn (struct mips_cl_insn *insn)
1753 char *f = frag_more (insn_length (insn));
1754 move_insn (insn, frag_now, f - frag_now->fr_literal);
1757 /* Start a variant frag and move INSN to the start of the variant part,
1758 marking it as fixed. The other arguments are as for frag_var. */
1761 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1762 relax_substateT subtype, symbolS *symbol, offsetT offset)
1764 frag_grow (max_chars);
1765 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1767 frag_var (rs_machine_dependent, max_chars, var,
1768 subtype, symbol, offset, NULL);
1771 /* Insert N copies of INSN into the history buffer, starting at
1772 position FIRST. Neither FIRST nor N need to be clipped. */
1775 insert_into_history (unsigned int first, unsigned int n,
1776 const struct mips_cl_insn *insn)
1778 if (mips_relax.sequence != 2)
1782 for (i = ARRAY_SIZE (history); i-- > first;)
1784 history[i] = history[i - n];
1790 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1791 the idea is to make it obvious at a glance that each errata is
1795 init_vr4120_conflicts (void)
1797 #define CONFLICT(FIRST, SECOND) \
1798 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1800 /* Errata 21 - [D]DIV[U] after [D]MACC */
1801 CONFLICT (MACC, DIV);
1802 CONFLICT (DMACC, DIV);
1804 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1805 CONFLICT (DMULT, DMULT);
1806 CONFLICT (DMULT, DMACC);
1807 CONFLICT (DMACC, DMULT);
1808 CONFLICT (DMACC, DMACC);
1810 /* Errata 24 - MT{LO,HI} after [D]MACC */
1811 CONFLICT (MACC, MTHILO);
1812 CONFLICT (DMACC, MTHILO);
1814 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1815 instruction is executed immediately after a MACC or DMACC
1816 instruction, the result of [either instruction] is incorrect." */
1817 CONFLICT (MACC, MULT);
1818 CONFLICT (MACC, DMULT);
1819 CONFLICT (DMACC, MULT);
1820 CONFLICT (DMACC, DMULT);
1822 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1823 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1824 DDIV or DDIVU instruction, the result of the MACC or
1825 DMACC instruction is incorrect.". */
1826 CONFLICT (DMULT, MACC);
1827 CONFLICT (DMULT, DMACC);
1828 CONFLICT (DIV, MACC);
1829 CONFLICT (DIV, DMACC);
1839 #define RTYPE_MASK 0x1ff00
1840 #define RTYPE_NUM 0x00100
1841 #define RTYPE_FPU 0x00200
1842 #define RTYPE_FCC 0x00400
1843 #define RTYPE_VEC 0x00800
1844 #define RTYPE_GP 0x01000
1845 #define RTYPE_CP0 0x02000
1846 #define RTYPE_PC 0x04000
1847 #define RTYPE_ACC 0x08000
1848 #define RTYPE_CCC 0x10000
1849 #define RNUM_MASK 0x000ff
1850 #define RWARN 0x80000
1852 #define GENERIC_REGISTER_NUMBERS \
1853 {"$0", RTYPE_NUM | 0}, \
1854 {"$1", RTYPE_NUM | 1}, \
1855 {"$2", RTYPE_NUM | 2}, \
1856 {"$3", RTYPE_NUM | 3}, \
1857 {"$4", RTYPE_NUM | 4}, \
1858 {"$5", RTYPE_NUM | 5}, \
1859 {"$6", RTYPE_NUM | 6}, \
1860 {"$7", RTYPE_NUM | 7}, \
1861 {"$8", RTYPE_NUM | 8}, \
1862 {"$9", RTYPE_NUM | 9}, \
1863 {"$10", RTYPE_NUM | 10}, \
1864 {"$11", RTYPE_NUM | 11}, \
1865 {"$12", RTYPE_NUM | 12}, \
1866 {"$13", RTYPE_NUM | 13}, \
1867 {"$14", RTYPE_NUM | 14}, \
1868 {"$15", RTYPE_NUM | 15}, \
1869 {"$16", RTYPE_NUM | 16}, \
1870 {"$17", RTYPE_NUM | 17}, \
1871 {"$18", RTYPE_NUM | 18}, \
1872 {"$19", RTYPE_NUM | 19}, \
1873 {"$20", RTYPE_NUM | 20}, \
1874 {"$21", RTYPE_NUM | 21}, \
1875 {"$22", RTYPE_NUM | 22}, \
1876 {"$23", RTYPE_NUM | 23}, \
1877 {"$24", RTYPE_NUM | 24}, \
1878 {"$25", RTYPE_NUM | 25}, \
1879 {"$26", RTYPE_NUM | 26}, \
1880 {"$27", RTYPE_NUM | 27}, \
1881 {"$28", RTYPE_NUM | 28}, \
1882 {"$29", RTYPE_NUM | 29}, \
1883 {"$30", RTYPE_NUM | 30}, \
1884 {"$31", RTYPE_NUM | 31}
1886 #define FPU_REGISTER_NAMES \
1887 {"$f0", RTYPE_FPU | 0}, \
1888 {"$f1", RTYPE_FPU | 1}, \
1889 {"$f2", RTYPE_FPU | 2}, \
1890 {"$f3", RTYPE_FPU | 3}, \
1891 {"$f4", RTYPE_FPU | 4}, \
1892 {"$f5", RTYPE_FPU | 5}, \
1893 {"$f6", RTYPE_FPU | 6}, \
1894 {"$f7", RTYPE_FPU | 7}, \
1895 {"$f8", RTYPE_FPU | 8}, \
1896 {"$f9", RTYPE_FPU | 9}, \
1897 {"$f10", RTYPE_FPU | 10}, \
1898 {"$f11", RTYPE_FPU | 11}, \
1899 {"$f12", RTYPE_FPU | 12}, \
1900 {"$f13", RTYPE_FPU | 13}, \
1901 {"$f14", RTYPE_FPU | 14}, \
1902 {"$f15", RTYPE_FPU | 15}, \
1903 {"$f16", RTYPE_FPU | 16}, \
1904 {"$f17", RTYPE_FPU | 17}, \
1905 {"$f18", RTYPE_FPU | 18}, \
1906 {"$f19", RTYPE_FPU | 19}, \
1907 {"$f20", RTYPE_FPU | 20}, \
1908 {"$f21", RTYPE_FPU | 21}, \
1909 {"$f22", RTYPE_FPU | 22}, \
1910 {"$f23", RTYPE_FPU | 23}, \
1911 {"$f24", RTYPE_FPU | 24}, \
1912 {"$f25", RTYPE_FPU | 25}, \
1913 {"$f26", RTYPE_FPU | 26}, \
1914 {"$f27", RTYPE_FPU | 27}, \
1915 {"$f28", RTYPE_FPU | 28}, \
1916 {"$f29", RTYPE_FPU | 29}, \
1917 {"$f30", RTYPE_FPU | 30}, \
1918 {"$f31", RTYPE_FPU | 31}
1920 #define FPU_CONDITION_CODE_NAMES \
1921 {"$fcc0", RTYPE_FCC | 0}, \
1922 {"$fcc1", RTYPE_FCC | 1}, \
1923 {"$fcc2", RTYPE_FCC | 2}, \
1924 {"$fcc3", RTYPE_FCC | 3}, \
1925 {"$fcc4", RTYPE_FCC | 4}, \
1926 {"$fcc5", RTYPE_FCC | 5}, \
1927 {"$fcc6", RTYPE_FCC | 6}, \
1928 {"$fcc7", RTYPE_FCC | 7}
1930 #define COPROC_CONDITION_CODE_NAMES \
1931 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1932 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1933 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1934 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1935 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1936 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1937 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1938 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1940 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1941 {"$a4", RTYPE_GP | 8}, \
1942 {"$a5", RTYPE_GP | 9}, \
1943 {"$a6", RTYPE_GP | 10}, \
1944 {"$a7", RTYPE_GP | 11}, \
1945 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1946 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1947 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1948 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1949 {"$t0", RTYPE_GP | 12}, \
1950 {"$t1", RTYPE_GP | 13}, \
1951 {"$t2", RTYPE_GP | 14}, \
1952 {"$t3", RTYPE_GP | 15}
1954 #define O32_SYMBOLIC_REGISTER_NAMES \
1955 {"$t0", RTYPE_GP | 8}, \
1956 {"$t1", RTYPE_GP | 9}, \
1957 {"$t2", RTYPE_GP | 10}, \
1958 {"$t3", RTYPE_GP | 11}, \
1959 {"$t4", RTYPE_GP | 12}, \
1960 {"$t5", RTYPE_GP | 13}, \
1961 {"$t6", RTYPE_GP | 14}, \
1962 {"$t7", RTYPE_GP | 15}, \
1963 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1964 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1965 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1966 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1968 /* Remaining symbolic register names */
1969 #define SYMBOLIC_REGISTER_NAMES \
1970 {"$zero", RTYPE_GP | 0}, \
1971 {"$at", RTYPE_GP | 1}, \
1972 {"$AT", RTYPE_GP | 1}, \
1973 {"$v0", RTYPE_GP | 2}, \
1974 {"$v1", RTYPE_GP | 3}, \
1975 {"$a0", RTYPE_GP | 4}, \
1976 {"$a1", RTYPE_GP | 5}, \
1977 {"$a2", RTYPE_GP | 6}, \
1978 {"$a3", RTYPE_GP | 7}, \
1979 {"$s0", RTYPE_GP | 16}, \
1980 {"$s1", RTYPE_GP | 17}, \
1981 {"$s2", RTYPE_GP | 18}, \
1982 {"$s3", RTYPE_GP | 19}, \
1983 {"$s4", RTYPE_GP | 20}, \
1984 {"$s5", RTYPE_GP | 21}, \
1985 {"$s6", RTYPE_GP | 22}, \
1986 {"$s7", RTYPE_GP | 23}, \
1987 {"$t8", RTYPE_GP | 24}, \
1988 {"$t9", RTYPE_GP | 25}, \
1989 {"$k0", RTYPE_GP | 26}, \
1990 {"$kt0", RTYPE_GP | 26}, \
1991 {"$k1", RTYPE_GP | 27}, \
1992 {"$kt1", RTYPE_GP | 27}, \
1993 {"$gp", RTYPE_GP | 28}, \
1994 {"$sp", RTYPE_GP | 29}, \
1995 {"$s8", RTYPE_GP | 30}, \
1996 {"$fp", RTYPE_GP | 30}, \
1997 {"$ra", RTYPE_GP | 31}
1999 #define MIPS16_SPECIAL_REGISTER_NAMES \
2000 {"$pc", RTYPE_PC | 0}
2002 #define MDMX_VECTOR_REGISTER_NAMES \
2003 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2004 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2005 {"$v2", RTYPE_VEC | 2}, \
2006 {"$v3", RTYPE_VEC | 3}, \
2007 {"$v4", RTYPE_VEC | 4}, \
2008 {"$v5", RTYPE_VEC | 5}, \
2009 {"$v6", RTYPE_VEC | 6}, \
2010 {"$v7", RTYPE_VEC | 7}, \
2011 {"$v8", RTYPE_VEC | 8}, \
2012 {"$v9", RTYPE_VEC | 9}, \
2013 {"$v10", RTYPE_VEC | 10}, \
2014 {"$v11", RTYPE_VEC | 11}, \
2015 {"$v12", RTYPE_VEC | 12}, \
2016 {"$v13", RTYPE_VEC | 13}, \
2017 {"$v14", RTYPE_VEC | 14}, \
2018 {"$v15", RTYPE_VEC | 15}, \
2019 {"$v16", RTYPE_VEC | 16}, \
2020 {"$v17", RTYPE_VEC | 17}, \
2021 {"$v18", RTYPE_VEC | 18}, \
2022 {"$v19", RTYPE_VEC | 19}, \
2023 {"$v20", RTYPE_VEC | 20}, \
2024 {"$v21", RTYPE_VEC | 21}, \
2025 {"$v22", RTYPE_VEC | 22}, \
2026 {"$v23", RTYPE_VEC | 23}, \
2027 {"$v24", RTYPE_VEC | 24}, \
2028 {"$v25", RTYPE_VEC | 25}, \
2029 {"$v26", RTYPE_VEC | 26}, \
2030 {"$v27", RTYPE_VEC | 27}, \
2031 {"$v28", RTYPE_VEC | 28}, \
2032 {"$v29", RTYPE_VEC | 29}, \
2033 {"$v30", RTYPE_VEC | 30}, \
2034 {"$v31", RTYPE_VEC | 31}
2036 #define MIPS_DSP_ACCUMULATOR_NAMES \
2037 {"$ac0", RTYPE_ACC | 0}, \
2038 {"$ac1", RTYPE_ACC | 1}, \
2039 {"$ac2", RTYPE_ACC | 2}, \
2040 {"$ac3", RTYPE_ACC | 3}
2042 static const struct regname reg_names[] = {
2043 GENERIC_REGISTER_NUMBERS,
2045 FPU_CONDITION_CODE_NAMES,
2046 COPROC_CONDITION_CODE_NAMES,
2048 /* The $txx registers depends on the abi,
2049 these will be added later into the symbol table from
2050 one of the tables below once mips_abi is set after
2051 parsing of arguments from the command line. */
2052 SYMBOLIC_REGISTER_NAMES,
2054 MIPS16_SPECIAL_REGISTER_NAMES,
2055 MDMX_VECTOR_REGISTER_NAMES,
2056 MIPS_DSP_ACCUMULATOR_NAMES,
2060 static const struct regname reg_names_o32[] = {
2061 O32_SYMBOLIC_REGISTER_NAMES,
2065 static const struct regname reg_names_n32n64[] = {
2066 N32N64_SYMBOLIC_REGISTER_NAMES,
2070 /* Check if S points at a valid register specifier according to TYPES.
2071 If so, then return 1, advance S to consume the specifier and store
2072 the register's number in REGNOP, otherwise return 0. */
2075 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2082 /* Find end of name. */
2084 if (is_name_beginner (*e))
2086 while (is_part_of_name (*e))
2089 /* Terminate name. */
2093 /* Look for a register symbol. */
2094 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2096 int r = S_GET_VALUE (symbolP);
2098 reg = r & RNUM_MASK;
2099 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2100 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2101 reg = (r & RNUM_MASK) - 2;
2103 /* Else see if this is a register defined in an itbl entry. */
2104 else if ((types & RTYPE_GP) && itbl_have_entries)
2111 if (itbl_get_reg_val (n, &r))
2112 reg = r & RNUM_MASK;
2115 /* Advance to next token if a register was recognised. */
2118 else if (types & RWARN)
2119 as_warn (_("Unrecognized register name `%s'"), *s);
2127 /* Check if S points at a valid register list according to TYPES.
2128 If so, then return 1, advance S to consume the list and store
2129 the registers present on the list as a bitmask of ones in REGLISTP,
2130 otherwise return 0. A valid list comprises a comma-separated
2131 enumeration of valid single registers and/or dash-separated
2132 contiguous register ranges as determined by their numbers.
2134 As a special exception if one of s0-s7 registers is specified as
2135 the range's lower delimiter and s8 (fp) is its upper one, then no
2136 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2137 are selected; they have to be listed separately if needed. */
2140 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2142 unsigned int reglist = 0;
2143 unsigned int lastregno;
2144 bfd_boolean ok = TRUE;
2145 unsigned int regmask;
2146 char *s_endlist = *s;
2150 while (reg_lookup (s, types, ®no))
2156 ok = reg_lookup (s, types, &lastregno);
2157 if (ok && lastregno < regno)
2163 if (lastregno == FP && regno >= S0 && regno <= S7)
2168 regmask = 1 << lastregno;
2169 regmask = (regmask << 1) - 1;
2170 regmask ^= (1 << regno) - 1;
2184 *reglistp = reglist;
2185 return ok && reglist != 0;
2188 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2189 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2192 is_opcode_valid (const struct mips_opcode *mo)
2194 int isa = mips_opts.isa;
2197 if (mips_opts.ase_mdmx)
2199 if (mips_opts.ase_dsp)
2201 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2203 if (mips_opts.ase_dspr2)
2205 if (mips_opts.ase_mt)
2207 if (mips_opts.ase_mips3d)
2209 if (mips_opts.ase_smartmips)
2210 isa |= INSN_SMARTMIPS;
2211 if (mips_opts.ase_mcu)
2214 /* Don't accept instructions based on the ISA if the CPU does not implement
2215 all the coprocessor insns. */
2216 if (NO_ISA_COP (mips_opts.arch)
2217 && COP_INSN (mo->pinfo))
2220 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
2223 /* Check whether the instruction or macro requires single-precision or
2224 double-precision floating-point support. Note that this information is
2225 stored differently in the opcode table for insns and macros. */
2226 if (mo->pinfo == INSN_MACRO)
2228 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2229 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2233 fp_s = mo->pinfo & FP_S;
2234 fp_d = mo->pinfo & FP_D;
2237 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2240 if (fp_s && mips_opts.soft_float)
2246 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2247 selected ISA and architecture. */
2250 is_opcode_valid_16 (const struct mips_opcode *mo)
2252 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
2255 /* Return TRUE if the size of the microMIPS opcode MO matches one
2256 explicitly requested. Always TRUE in the standard MIPS mode. */
2259 is_size_valid (const struct mips_opcode *mo)
2261 if (!mips_opts.micromips)
2264 if (!forced_insn_length)
2266 if (mo->pinfo == INSN_MACRO)
2268 return forced_insn_length == micromips_insn_length (mo);
2271 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2272 of the preceding instruction. Always TRUE in the standard MIPS mode. */
2275 is_delay_slot_valid (const struct mips_opcode *mo)
2277 if (!mips_opts.micromips)
2280 if (mo->pinfo == INSN_MACRO)
2282 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2283 && micromips_insn_length (mo) != 4)
2285 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2286 && micromips_insn_length (mo) != 2)
2292 /* This function is called once, at assembler startup time. It should set up
2293 all the tables, etc. that the MD part of the assembler will need. */
2298 const char *retval = NULL;
2302 if (mips_pic != NO_PIC)
2304 if (g_switch_seen && g_switch_value != 0)
2305 as_bad (_("-G may not be used in position-independent code"));
2309 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2310 as_warn (_("Could not set architecture and machine"));
2312 op_hash = hash_new ();
2314 for (i = 0; i < NUMOPCODES;)
2316 const char *name = mips_opcodes[i].name;
2318 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2321 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2322 mips_opcodes[i].name, retval);
2323 /* Probably a memory allocation problem? Give up now. */
2324 as_fatal (_("Broken assembler. No assembly attempted."));
2328 if (mips_opcodes[i].pinfo != INSN_MACRO)
2330 if (!validate_mips_insn (&mips_opcodes[i]))
2332 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2334 create_insn (&nop_insn, mips_opcodes + i);
2335 if (mips_fix_loongson2f_nop)
2336 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2337 nop_insn.fixed_p = 1;
2342 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2345 mips16_op_hash = hash_new ();
2348 while (i < bfd_mips16_num_opcodes)
2350 const char *name = mips16_opcodes[i].name;
2352 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2354 as_fatal (_("internal: can't hash `%s': %s"),
2355 mips16_opcodes[i].name, retval);
2358 if (mips16_opcodes[i].pinfo != INSN_MACRO
2359 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2360 != mips16_opcodes[i].match))
2362 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2363 mips16_opcodes[i].name, mips16_opcodes[i].args);
2366 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2368 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2369 mips16_nop_insn.fixed_p = 1;
2373 while (i < bfd_mips16_num_opcodes
2374 && strcmp (mips16_opcodes[i].name, name) == 0);
2377 micromips_op_hash = hash_new ();
2380 while (i < bfd_micromips_num_opcodes)
2382 const char *name = micromips_opcodes[i].name;
2384 retval = hash_insert (micromips_op_hash, name,
2385 (void *) µmips_opcodes[i]);
2387 as_fatal (_("internal: can't hash `%s': %s"),
2388 micromips_opcodes[i].name, retval);
2390 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2392 struct mips_cl_insn *micromips_nop_insn;
2394 if (!validate_micromips_insn (µmips_opcodes[i]))
2397 if (micromips_insn_length (micromips_opcodes + i) == 2)
2398 micromips_nop_insn = µmips_nop16_insn;
2399 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2400 micromips_nop_insn = µmips_nop32_insn;
2404 if (micromips_nop_insn->insn_mo == NULL
2405 && strcmp (name, "nop") == 0)
2407 create_insn (micromips_nop_insn, micromips_opcodes + i);
2408 micromips_nop_insn->fixed_p = 1;
2411 while (++i < bfd_micromips_num_opcodes
2412 && strcmp (micromips_opcodes[i].name, name) == 0);
2416 as_fatal (_("Broken assembler. No assembly attempted."));
2418 /* We add all the general register names to the symbol table. This
2419 helps us detect invalid uses of them. */
2420 for (i = 0; reg_names[i].name; i++)
2421 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2422 reg_names[i].num, /* & RNUM_MASK, */
2423 &zero_address_frag));
2425 for (i = 0; reg_names_n32n64[i].name; i++)
2426 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2427 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2428 &zero_address_frag));
2430 for (i = 0; reg_names_o32[i].name; i++)
2431 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2432 reg_names_o32[i].num, /* & RNUM_MASK, */
2433 &zero_address_frag));
2435 mips_no_prev_insn ();
2438 mips_cprmask[0] = 0;
2439 mips_cprmask[1] = 0;
2440 mips_cprmask[2] = 0;
2441 mips_cprmask[3] = 0;
2443 /* set the default alignment for the text section (2**2) */
2444 record_alignment (text_section, 2);
2446 bfd_set_gp_size (stdoutput, g_switch_value);
2451 /* On a native system other than VxWorks, sections must be aligned
2452 to 16 byte boundaries. When configured for an embedded ELF
2453 target, we don't bother. */
2454 if (strncmp (TARGET_OS, "elf", 3) != 0
2455 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2457 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2458 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2459 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2462 /* Create a .reginfo section for register masks and a .mdebug
2463 section for debugging information. */
2471 subseg = now_subseg;
2473 /* The ABI says this section should be loaded so that the
2474 running program can access it. However, we don't load it
2475 if we are configured for an embedded target */
2476 flags = SEC_READONLY | SEC_DATA;
2477 if (strncmp (TARGET_OS, "elf", 3) != 0)
2478 flags |= SEC_ALLOC | SEC_LOAD;
2480 if (mips_abi != N64_ABI)
2482 sec = subseg_new (".reginfo", (subsegT) 0);
2484 bfd_set_section_flags (stdoutput, sec, flags);
2485 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2487 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2491 /* The 64-bit ABI uses a .MIPS.options section rather than
2492 .reginfo section. */
2493 sec = subseg_new (".MIPS.options", (subsegT) 0);
2494 bfd_set_section_flags (stdoutput, sec, flags);
2495 bfd_set_section_alignment (stdoutput, sec, 3);
2497 /* Set up the option header. */
2499 Elf_Internal_Options opthdr;
2502 opthdr.kind = ODK_REGINFO;
2503 opthdr.size = (sizeof (Elf_External_Options)
2504 + sizeof (Elf64_External_RegInfo));
2507 f = frag_more (sizeof (Elf_External_Options));
2508 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2509 (Elf_External_Options *) f);
2511 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2515 if (ECOFF_DEBUGGING)
2517 sec = subseg_new (".mdebug", (subsegT) 0);
2518 (void) bfd_set_section_flags (stdoutput, sec,
2519 SEC_HAS_CONTENTS | SEC_READONLY);
2520 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2522 else if (mips_flag_pdr)
2524 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2525 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2526 SEC_READONLY | SEC_RELOC
2528 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2531 subseg_set (seg, subseg);
2534 #endif /* OBJ_ELF */
2536 if (! ECOFF_DEBUGGING)
2539 if (mips_fix_vr4120)
2540 init_vr4120_conflicts ();
2546 mips_emit_delays ();
2547 if (! ECOFF_DEBUGGING)
2552 md_assemble (char *str)
2554 struct mips_cl_insn insn;
2555 bfd_reloc_code_real_type unused_reloc[3]
2556 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2558 imm_expr.X_op = O_absent;
2559 imm2_expr.X_op = O_absent;
2560 offset_expr.X_op = O_absent;
2561 imm_reloc[0] = BFD_RELOC_UNUSED;
2562 imm_reloc[1] = BFD_RELOC_UNUSED;
2563 imm_reloc[2] = BFD_RELOC_UNUSED;
2564 offset_reloc[0] = BFD_RELOC_UNUSED;
2565 offset_reloc[1] = BFD_RELOC_UNUSED;
2566 offset_reloc[2] = BFD_RELOC_UNUSED;
2568 if (mips_opts.mips16)
2569 mips16_ip (str, &insn);
2572 mips_ip (str, &insn);
2573 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2574 str, insn.insn_opcode));
2579 as_bad ("%s `%s'", insn_error, str);
2583 if (insn.insn_mo->pinfo == INSN_MACRO)
2586 if (mips_opts.mips16)
2587 mips16_macro (&insn);
2594 if (imm_expr.X_op != O_absent)
2595 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2596 else if (offset_expr.X_op != O_absent)
2597 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2599 append_insn (&insn, NULL, unused_reloc, FALSE);
2603 /* Convenience functions for abstracting away the differences between
2604 MIPS16 and non-MIPS16 relocations. */
2606 static inline bfd_boolean
2607 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2611 case BFD_RELOC_MIPS16_JMP:
2612 case BFD_RELOC_MIPS16_GPREL:
2613 case BFD_RELOC_MIPS16_GOT16:
2614 case BFD_RELOC_MIPS16_CALL16:
2615 case BFD_RELOC_MIPS16_HI16_S:
2616 case BFD_RELOC_MIPS16_HI16:
2617 case BFD_RELOC_MIPS16_LO16:
2625 static inline bfd_boolean
2626 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2630 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2631 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2632 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2633 case BFD_RELOC_MICROMIPS_GPREL16:
2634 case BFD_RELOC_MICROMIPS_JMP:
2635 case BFD_RELOC_MICROMIPS_HI16:
2636 case BFD_RELOC_MICROMIPS_HI16_S:
2637 case BFD_RELOC_MICROMIPS_LO16:
2638 case BFD_RELOC_MICROMIPS_LITERAL:
2639 case BFD_RELOC_MICROMIPS_GOT16:
2640 case BFD_RELOC_MICROMIPS_CALL16:
2641 case BFD_RELOC_MICROMIPS_GOT_HI16:
2642 case BFD_RELOC_MICROMIPS_GOT_LO16:
2643 case BFD_RELOC_MICROMIPS_CALL_HI16:
2644 case BFD_RELOC_MICROMIPS_CALL_LO16:
2645 case BFD_RELOC_MICROMIPS_SUB:
2646 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2647 case BFD_RELOC_MICROMIPS_GOT_OFST:
2648 case BFD_RELOC_MICROMIPS_GOT_DISP:
2649 case BFD_RELOC_MICROMIPS_HIGHEST:
2650 case BFD_RELOC_MICROMIPS_HIGHER:
2651 case BFD_RELOC_MICROMIPS_SCN_DISP:
2652 case BFD_RELOC_MICROMIPS_JALR:
2660 static inline bfd_boolean
2661 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2663 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2666 static inline bfd_boolean
2667 got16_reloc_p (bfd_reloc_code_real_type reloc)
2669 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2670 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2673 static inline bfd_boolean
2674 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2676 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2677 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2680 static inline bfd_boolean
2681 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2683 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2684 || reloc == BFD_RELOC_MICROMIPS_LO16);
2687 static inline bfd_boolean
2688 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2690 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2693 /* Return true if the given relocation might need a matching %lo().
2694 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2695 need a matching %lo() when applied to local symbols. */
2697 static inline bfd_boolean
2698 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2700 return (HAVE_IN_PLACE_ADDENDS
2701 && (hi16_reloc_p (reloc)
2702 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2703 all GOT16 relocations evaluate to "G". */
2704 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2707 /* Return the type of %lo() reloc needed by RELOC, given that
2708 reloc_needs_lo_p. */
2710 static inline bfd_reloc_code_real_type
2711 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2713 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2714 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2718 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2721 static inline bfd_boolean
2722 fixup_has_matching_lo_p (fixS *fixp)
2724 return (fixp->fx_next != NULL
2725 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2726 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2727 && fixp->fx_offset == fixp->fx_next->fx_offset);
2730 /* This function returns true if modifying a register requires a
2734 reg_needs_delay (unsigned int reg)
2736 unsigned long prev_pinfo;
2738 prev_pinfo = history[0].insn_mo->pinfo;
2739 if (! mips_opts.noreorder
2740 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2741 && ! gpr_interlocks)
2742 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2743 && ! cop_interlocks)))
2745 /* A load from a coprocessor or from memory. All load delays
2746 delay the use of general register rt for one instruction. */
2747 /* Itbl support may require additional care here. */
2748 know (prev_pinfo & INSN_WRITE_GPR_T);
2749 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2756 /* Move all labels in insn_labels to the current insertion point. */
2759 mips_move_labels (void)
2761 segment_info_type *si = seg_info (now_seg);
2762 struct insn_label_list *l;
2765 for (l = si->label_list; l != NULL; l = l->next)
2767 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2768 symbol_set_frag (l->label, frag_now);
2769 val = (valueT) frag_now_fix ();
2770 /* MIPS16/microMIPS text labels are stored as odd. */
2771 if (HAVE_CODE_COMPRESSION)
2773 S_SET_VALUE (l->label, val);
2778 s_is_linkonce (symbolS *sym, segT from_seg)
2780 bfd_boolean linkonce = FALSE;
2781 segT symseg = S_GET_SEGMENT (sym);
2783 if (symseg != from_seg && !S_IS_LOCAL (sym))
2785 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2788 /* The GNU toolchain uses an extension for ELF: a section
2789 beginning with the magic string .gnu.linkonce is a
2790 linkonce section. */
2791 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2792 sizeof ".gnu.linkonce" - 1) == 0)
2799 /* Mark instruction labels in MIPS16/microMIPS mode. This permits the
2800 linker to handle them specially, such as generating jalx instructions
2801 when needed. We also make them odd for the duration of the assembly,
2802 in order to generate the right sort of code. We will make them even
2803 in the adjust_symtab routine, while leaving them marked. This is
2804 convenient for the debugger and the disassembler. The linker knows
2805 to make them odd again. */
2808 mips_compressed_mark_labels (void)
2810 segment_info_type *si = seg_info (now_seg);
2811 struct insn_label_list *l;
2813 gas_assert (HAVE_CODE_COMPRESSION);
2815 for (l = si->label_list; l != NULL; l = l->next)
2817 symbolS *label = l->label;
2819 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2822 if (mips_opts.mips16)
2823 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2825 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2828 if ((S_GET_VALUE (label) & 1) == 0
2829 /* Don't adjust the address if the label is global or weak, or
2830 in a link-once section, since we'll be emitting symbol reloc
2831 references to it which will be patched up by the linker, and
2832 the final value of the symbol may or may not be MIPS16/microMIPS. */
2833 && ! S_IS_WEAK (label)
2834 && ! S_IS_EXTERNAL (label)
2835 && ! s_is_linkonce (label, now_seg))
2836 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2840 /* End the current frag. Make it a variant frag and record the
2844 relax_close_frag (void)
2846 mips_macro_warning.first_frag = frag_now;
2847 frag_var (rs_machine_dependent, 0, 0,
2848 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2849 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2851 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2852 mips_relax.first_fixup = 0;
2855 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2856 See the comment above RELAX_ENCODE for more details. */
2859 relax_start (symbolS *symbol)
2861 gas_assert (mips_relax.sequence == 0);
2862 mips_relax.sequence = 1;
2863 mips_relax.symbol = symbol;
2866 /* Start generating the second version of a relaxable sequence.
2867 See the comment above RELAX_ENCODE for more details. */
2872 gas_assert (mips_relax.sequence == 1);
2873 mips_relax.sequence = 2;
2876 /* End the current relaxable sequence. */
2881 gas_assert (mips_relax.sequence == 2);
2882 relax_close_frag ();
2883 mips_relax.sequence = 0;
2886 /* Return true if IP is a delayed branch or jump. */
2888 static inline bfd_boolean
2889 delayed_branch_p (const struct mips_cl_insn *ip)
2891 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2892 | INSN_COND_BRANCH_DELAY
2893 | INSN_COND_BRANCH_LIKELY)) != 0;
2896 /* Return true if IP is a compact branch or jump. */
2898 static inline bfd_boolean
2899 compact_branch_p (const struct mips_cl_insn *ip)
2901 if (mips_opts.mips16)
2902 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2903 | MIPS16_INSN_COND_BRANCH)) != 0;
2905 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2906 | INSN2_COND_BRANCH)) != 0;
2909 /* Return true if IP is an unconditional branch or jump. */
2911 static inline bfd_boolean
2912 uncond_branch_p (const struct mips_cl_insn *ip)
2914 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2915 || (mips_opts.mips16
2916 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2917 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2920 /* Return true if IP is a branch-likely instruction. */
2922 static inline bfd_boolean
2923 branch_likely_p (const struct mips_cl_insn *ip)
2925 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2928 /* Return the type of nop that should be used to fill the delay slot
2929 of delayed branch IP. */
2931 static struct mips_cl_insn *
2932 get_delay_slot_nop (const struct mips_cl_insn *ip)
2934 if (mips_opts.micromips
2935 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2936 return µmips_nop32_insn;
2940 /* Return the mask of core registers that IP reads or writes. */
2943 gpr_mod_mask (const struct mips_cl_insn *ip)
2945 unsigned long pinfo2;
2949 pinfo2 = ip->insn_mo->pinfo2;
2950 if (mips_opts.micromips)
2952 if (pinfo2 & INSN2_MOD_GPR_MD)
2953 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
2954 if (pinfo2 & INSN2_MOD_GPR_MF)
2955 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
2956 if (pinfo2 & INSN2_MOD_SP)
2962 /* Return the mask of core registers that IP reads. */
2965 gpr_read_mask (const struct mips_cl_insn *ip)
2967 unsigned long pinfo, pinfo2;
2970 mask = gpr_mod_mask (ip);
2971 pinfo = ip->insn_mo->pinfo;
2972 pinfo2 = ip->insn_mo->pinfo2;
2973 if (mips_opts.mips16)
2975 if (pinfo & MIPS16_INSN_READ_X)
2976 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2977 if (pinfo & MIPS16_INSN_READ_Y)
2978 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2979 if (pinfo & MIPS16_INSN_READ_T)
2981 if (pinfo & MIPS16_INSN_READ_SP)
2983 if (pinfo & MIPS16_INSN_READ_31)
2985 if (pinfo & MIPS16_INSN_READ_Z)
2986 mask |= 1 << (mips16_to_32_reg_map
2987 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2988 if (pinfo & MIPS16_INSN_READ_GPR_X)
2989 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2993 if (pinfo2 & INSN2_READ_GPR_D)
2994 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
2995 if (pinfo & INSN_READ_GPR_T)
2996 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
2997 if (pinfo & INSN_READ_GPR_S)
2998 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
2999 if (pinfo2 & INSN2_READ_GP)
3001 if (pinfo2 & INSN2_READ_GPR_31)
3003 if (pinfo2 & INSN2_READ_GPR_Z)
3004 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3006 if (mips_opts.micromips)
3008 if (pinfo2 & INSN2_READ_GPR_MC)
3009 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3010 if (pinfo2 & INSN2_READ_GPR_ME)
3011 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3012 if (pinfo2 & INSN2_READ_GPR_MG)
3013 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3014 if (pinfo2 & INSN2_READ_GPR_MJ)
3015 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3016 if (pinfo2 & INSN2_READ_GPR_MMN)
3018 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3019 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3021 if (pinfo2 & INSN2_READ_GPR_MP)
3022 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3023 if (pinfo2 & INSN2_READ_GPR_MQ)
3024 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3026 /* Don't include register 0. */
3030 /* Return the mask of core registers that IP writes. */
3033 gpr_write_mask (const struct mips_cl_insn *ip)
3035 unsigned long pinfo, pinfo2;
3038 mask = gpr_mod_mask (ip);
3039 pinfo = ip->insn_mo->pinfo;
3040 pinfo2 = ip->insn_mo->pinfo2;
3041 if (mips_opts.mips16)
3043 if (pinfo & MIPS16_INSN_WRITE_X)
3044 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3045 if (pinfo & MIPS16_INSN_WRITE_Y)
3046 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3047 if (pinfo & MIPS16_INSN_WRITE_Z)
3048 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3049 if (pinfo & MIPS16_INSN_WRITE_T)
3051 if (pinfo & MIPS16_INSN_WRITE_SP)
3053 if (pinfo & MIPS16_INSN_WRITE_31)
3055 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3056 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3060 if (pinfo & INSN_WRITE_GPR_D)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3062 if (pinfo & INSN_WRITE_GPR_T)
3063 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3064 if (pinfo & INSN_WRITE_GPR_S)
3065 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3066 if (pinfo & INSN_WRITE_GPR_31)
3068 if (pinfo2 & INSN2_WRITE_GPR_Z)
3069 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3071 if (mips_opts.micromips)
3073 if (pinfo2 & INSN2_WRITE_GPR_MB)
3074 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3075 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3077 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3078 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3080 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3081 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3082 if (pinfo2 & INSN2_WRITE_GPR_MP)
3083 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3085 /* Don't include register 0. */
3089 /* Return the mask of floating-point registers that IP reads. */
3092 fpr_read_mask (const struct mips_cl_insn *ip)
3094 unsigned long pinfo, pinfo2;
3098 pinfo = ip->insn_mo->pinfo;
3099 pinfo2 = ip->insn_mo->pinfo2;
3100 if (!mips_opts.mips16)
3102 if (pinfo2 & INSN2_READ_FPR_D)
3103 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3104 if (pinfo & INSN_READ_FPR_S)
3105 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3106 if (pinfo & INSN_READ_FPR_T)
3107 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3108 if (pinfo & INSN_READ_FPR_R)
3109 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3110 if (pinfo2 & INSN2_READ_FPR_Z)
3111 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3113 /* Conservatively treat all operands to an FP_D instruction are doubles.
3114 (This is overly pessimistic for things like cvt.d.s.) */
3115 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3120 /* Return the mask of floating-point registers that IP writes. */
3123 fpr_write_mask (const struct mips_cl_insn *ip)
3125 unsigned long pinfo, pinfo2;
3129 pinfo = ip->insn_mo->pinfo;
3130 pinfo2 = ip->insn_mo->pinfo2;
3131 if (!mips_opts.mips16)
3133 if (pinfo & INSN_WRITE_FPR_D)
3134 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3135 if (pinfo & INSN_WRITE_FPR_S)
3136 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3137 if (pinfo & INSN_WRITE_FPR_T)
3138 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3139 if (pinfo2 & INSN2_WRITE_FPR_Z)
3140 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3142 /* Conservatively treat all operands to an FP_D instruction are doubles.
3143 (This is overly pessimistic for things like cvt.s.d.) */
3144 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3149 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3150 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3151 by VR4120 errata. */
3154 classify_vr4120_insn (const char *name)
3156 if (strncmp (name, "macc", 4) == 0)
3157 return FIX_VR4120_MACC;
3158 if (strncmp (name, "dmacc", 5) == 0)
3159 return FIX_VR4120_DMACC;
3160 if (strncmp (name, "mult", 4) == 0)
3161 return FIX_VR4120_MULT;
3162 if (strncmp (name, "dmult", 5) == 0)
3163 return FIX_VR4120_DMULT;
3164 if (strstr (name, "div"))
3165 return FIX_VR4120_DIV;
3166 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3167 return FIX_VR4120_MTHILO;
3168 return NUM_FIX_VR4120_CLASSES;
3171 #define INSN_ERET 0x42000018
3172 #define INSN_DERET 0x4200001f
3174 /* Return the number of instructions that must separate INSN1 and INSN2,
3175 where INSN1 is the earlier instruction. Return the worst-case value
3176 for any INSN2 if INSN2 is null. */
3179 insns_between (const struct mips_cl_insn *insn1,
3180 const struct mips_cl_insn *insn2)
3182 unsigned long pinfo1, pinfo2;
3185 /* This function needs to know which pinfo flags are set for INSN2
3186 and which registers INSN2 uses. The former is stored in PINFO2 and
3187 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3188 will have every flag set and INSN2_USES_GPR will always return true. */
3189 pinfo1 = insn1->insn_mo->pinfo;
3190 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3192 #define INSN2_USES_GPR(REG) \
3193 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3195 /* For most targets, write-after-read dependencies on the HI and LO
3196 registers must be separated by at least two instructions. */
3197 if (!hilo_interlocks)
3199 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3201 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3205 /* If we're working around r7000 errata, there must be two instructions
3206 between an mfhi or mflo and any instruction that uses the result. */
3207 if (mips_7000_hilo_fix
3208 && !mips_opts.micromips
3209 && MF_HILO_INSN (pinfo1)
3210 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3213 /* If we're working around 24K errata, one instruction is required
3214 if an ERET or DERET is followed by a branch instruction. */
3215 if (mips_fix_24k && !mips_opts.micromips)
3217 if (insn1->insn_opcode == INSN_ERET
3218 || insn1->insn_opcode == INSN_DERET)
3221 || insn2->insn_opcode == INSN_ERET
3222 || insn2->insn_opcode == INSN_DERET
3223 || delayed_branch_p (insn2))
3228 /* If working around VR4120 errata, check for combinations that need
3229 a single intervening instruction. */
3230 if (mips_fix_vr4120 && !mips_opts.micromips)
3232 unsigned int class1, class2;
3234 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3235 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3239 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3240 if (vr4120_conflicts[class1] & (1 << class2))
3245 if (!HAVE_CODE_COMPRESSION)
3247 /* Check for GPR or coprocessor load delays. All such delays
3248 are on the RT register. */
3249 /* Itbl support may require additional care here. */
3250 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3251 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3253 know (pinfo1 & INSN_WRITE_GPR_T);
3254 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3258 /* Check for generic coprocessor hazards.
3260 This case is not handled very well. There is no special
3261 knowledge of CP0 handling, and the coprocessors other than
3262 the floating point unit are not distinguished at all. */
3263 /* Itbl support may require additional care here. FIXME!
3264 Need to modify this to include knowledge about
3265 user specified delays! */
3266 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3267 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3269 /* Handle cases where INSN1 writes to a known general coprocessor
3270 register. There must be a one instruction delay before INSN2
3271 if INSN2 reads that register, otherwise no delay is needed. */
3272 mask = fpr_write_mask (insn1);
3275 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3280 /* Read-after-write dependencies on the control registers
3281 require a two-instruction gap. */
3282 if ((pinfo1 & INSN_WRITE_COND_CODE)
3283 && (pinfo2 & INSN_READ_COND_CODE))
3286 /* We don't know exactly what INSN1 does. If INSN2 is
3287 also a coprocessor instruction, assume there must be
3288 a one instruction gap. */
3289 if (pinfo2 & INSN_COP)
3294 /* Check for read-after-write dependencies on the coprocessor
3295 control registers in cases where INSN1 does not need a general
3296 coprocessor delay. This means that INSN1 is a floating point
3297 comparison instruction. */
3298 /* Itbl support may require additional care here. */
3299 else if (!cop_interlocks
3300 && (pinfo1 & INSN_WRITE_COND_CODE)
3301 && (pinfo2 & INSN_READ_COND_CODE))
3305 #undef INSN2_USES_GPR
3310 /* Return the number of nops that would be needed to work around the
3311 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3312 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3313 that are contained within the first IGNORE instructions of HIST. */
3316 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3317 const struct mips_cl_insn *insn)
3322 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3323 are not affected by the errata. */
3325 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3326 || strcmp (insn->insn_mo->name, "mtlo") == 0
3327 || strcmp (insn->insn_mo->name, "mthi") == 0))
3330 /* Search for the first MFLO or MFHI. */
3331 for (i = 0; i < MAX_VR4130_NOPS; i++)
3332 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3334 /* Extract the destination register. */
3335 mask = gpr_write_mask (&hist[i]);
3337 /* No nops are needed if INSN reads that register. */
3338 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3341 /* ...or if any of the intervening instructions do. */
3342 for (j = 0; j < i; j++)
3343 if (gpr_read_mask (&hist[j]) & mask)
3347 return MAX_VR4130_NOPS - i;
3352 #define BASE_REG_EQ(INSN1, INSN2) \
3353 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3354 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3356 /* Return the minimum alignment for this store instruction. */
3359 fix_24k_align_to (const struct mips_opcode *mo)
3361 if (strcmp (mo->name, "sh") == 0)
3364 if (strcmp (mo->name, "swc1") == 0
3365 || strcmp (mo->name, "swc2") == 0
3366 || strcmp (mo->name, "sw") == 0
3367 || strcmp (mo->name, "sc") == 0
3368 || strcmp (mo->name, "s.s") == 0)
3371 if (strcmp (mo->name, "sdc1") == 0
3372 || strcmp (mo->name, "sdc2") == 0
3373 || strcmp (mo->name, "s.d") == 0)
3380 struct fix_24k_store_info
3382 /* Immediate offset, if any, for this store instruction. */
3384 /* Alignment required by this store instruction. */
3386 /* True for register offsets. */
3387 int register_offset;
3390 /* Comparison function used by qsort. */
3393 fix_24k_sort (const void *a, const void *b)
3395 const struct fix_24k_store_info *pos1 = a;
3396 const struct fix_24k_store_info *pos2 = b;
3398 return (pos1->off - pos2->off);
3401 /* INSN is a store instruction. Try to record the store information
3402 in STINFO. Return false if the information isn't known. */
3405 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3406 const struct mips_cl_insn *insn)
3408 /* The instruction must have a known offset. */
3409 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3412 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3413 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3417 /* Return the number of nops that would be needed to work around the 24k
3418 "lost data on stores during refill" errata if instruction INSN
3419 immediately followed the 2 instructions described by HIST.
3420 Ignore hazards that are contained within the first IGNORE
3421 instructions of HIST.
3423 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3424 for the data cache refills and store data. The following describes
3425 the scenario where the store data could be lost.
3427 * A data cache miss, due to either a load or a store, causing fill
3428 data to be supplied by the memory subsystem
3429 * The first three doublewords of fill data are returned and written
3431 * A sequence of four stores occurs in consecutive cycles around the
3432 final doubleword of the fill:
3436 * Zero, One or more instructions
3439 The four stores A-D must be to different doublewords of the line that
3440 is being filled. The fourth instruction in the sequence above permits
3441 the fill of the final doubleword to be transferred from the FSB into
3442 the cache. In the sequence above, the stores may be either integer
3443 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3444 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3445 different doublewords on the line. If the floating point unit is
3446 running in 1:2 mode, it is not possible to create the sequence above
3447 using only floating point store instructions.
3449 In this case, the cache line being filled is incorrectly marked
3450 invalid, thereby losing the data from any store to the line that
3451 occurs between the original miss and the completion of the five
3452 cycle sequence shown above.
3454 The workarounds are:
3456 * Run the data cache in write-through mode.
3457 * Insert a non-store instruction between
3458 Store A and Store B or Store B and Store C. */
3461 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3462 const struct mips_cl_insn *insn)
3464 struct fix_24k_store_info pos[3];
3465 int align, i, base_offset;
3470 /* If the previous instruction wasn't a store, there's nothing to
3472 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3475 /* If the instructions after the previous one are unknown, we have
3476 to assume the worst. */
3480 /* Check whether we are dealing with three consecutive stores. */
3481 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3482 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3485 /* If we don't know the relationship between the store addresses,
3486 assume the worst. */
3487 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3488 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3491 if (!fix_24k_record_store_info (&pos[0], insn)
3492 || !fix_24k_record_store_info (&pos[1], &hist[0])
3493 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3496 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3498 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3499 X bytes and such that the base register + X is known to be aligned
3502 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3506 align = pos[0].align_to;
3507 base_offset = pos[0].off;
3508 for (i = 1; i < 3; i++)
3509 if (align < pos[i].align_to)
3511 align = pos[i].align_to;
3512 base_offset = pos[i].off;
3514 for (i = 0; i < 3; i++)
3515 pos[i].off -= base_offset;
3518 pos[0].off &= ~align + 1;
3519 pos[1].off &= ~align + 1;
3520 pos[2].off &= ~align + 1;
3522 /* If any two stores write to the same chunk, they also write to the
3523 same doubleword. The offsets are still sorted at this point. */
3524 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3527 /* A range of at least 9 bytes is needed for the stores to be in
3528 non-overlapping doublewords. */
3529 if (pos[2].off - pos[0].off <= 8)
3532 if (pos[2].off - pos[1].off >= 24
3533 || pos[1].off - pos[0].off >= 24
3534 || pos[2].off - pos[0].off >= 32)
3540 /* Return the number of nops that would be needed if instruction INSN
3541 immediately followed the MAX_NOPS instructions given by HIST,
3542 where HIST[0] is the most recent instruction. Ignore hazards
3543 between INSN and the first IGNORE instructions in HIST.
3545 If INSN is null, return the worse-case number of nops for any
3549 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3550 const struct mips_cl_insn *insn)
3552 int i, nops, tmp_nops;
3555 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3557 tmp_nops = insns_between (hist + i, insn) - i;
3558 if (tmp_nops > nops)
3562 if (mips_fix_vr4130 && !mips_opts.micromips)
3564 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3565 if (tmp_nops > nops)
3569 if (mips_fix_24k && !mips_opts.micromips)
3571 tmp_nops = nops_for_24k (ignore, hist, insn);
3572 if (tmp_nops > nops)
3579 /* The variable arguments provide NUM_INSNS extra instructions that
3580 might be added to HIST. Return the largest number of nops that
3581 would be needed after the extended sequence, ignoring hazards
3582 in the first IGNORE instructions. */
3585 nops_for_sequence (int num_insns, int ignore,
3586 const struct mips_cl_insn *hist, ...)
3589 struct mips_cl_insn buffer[MAX_NOPS];
3590 struct mips_cl_insn *cursor;
3593 va_start (args, hist);
3594 cursor = buffer + num_insns;
3595 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3596 while (cursor > buffer)
3597 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3599 nops = nops_for_insn (ignore, buffer, NULL);
3604 /* Like nops_for_insn, but if INSN is a branch, take into account the
3605 worst-case delay for the branch target. */
3608 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3609 const struct mips_cl_insn *insn)
3613 nops = nops_for_insn (ignore, hist, insn);
3614 if (delayed_branch_p (insn))
3616 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3617 hist, insn, get_delay_slot_nop (insn));
3618 if (tmp_nops > nops)
3621 else if (compact_branch_p (insn))
3623 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3624 if (tmp_nops > nops)
3630 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3633 fix_loongson2f_nop (struct mips_cl_insn * ip)
3635 gas_assert (!HAVE_CODE_COMPRESSION);
3636 if (strcmp (ip->insn_mo->name, "nop") == 0)
3637 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3640 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3641 jr target pc &= 'hffff_ffff_cfff_ffff. */
3644 fix_loongson2f_jump (struct mips_cl_insn * ip)
3646 gas_assert (!HAVE_CODE_COMPRESSION);
3647 if (strcmp (ip->insn_mo->name, "j") == 0
3648 || strcmp (ip->insn_mo->name, "jr") == 0
3649 || strcmp (ip->insn_mo->name, "jalr") == 0)
3657 sreg = EXTRACT_OPERAND (0, RS, *ip);
3658 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3661 ep.X_op = O_constant;
3662 ep.X_add_number = 0xcfff0000;
3663 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3664 ep.X_add_number = 0xffff;
3665 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3666 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3671 fix_loongson2f (struct mips_cl_insn * ip)
3673 if (mips_fix_loongson2f_nop)
3674 fix_loongson2f_nop (ip);
3676 if (mips_fix_loongson2f_jump)
3677 fix_loongson2f_jump (ip);
3680 /* IP is a branch that has a delay slot, and we need to fill it
3681 automatically. Return true if we can do that by swapping IP
3682 with the previous instruction. */
3685 can_swap_branch_p (struct mips_cl_insn *ip)
3687 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3688 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3691 /* -O2 and above is required for this optimization. */
3692 if (mips_optimize < 2)
3695 /* If we have seen .set volatile or .set nomove, don't optimize. */
3696 if (mips_opts.nomove)
3699 /* We can't swap if the previous instruction's position is fixed. */
3700 if (history[0].fixed_p)
3703 /* If the previous previous insn was in a .set noreorder, we can't
3704 swap. Actually, the MIPS assembler will swap in this situation.
3705 However, gcc configured -with-gnu-as will generate code like
3713 in which we can not swap the bne and INSN. If gcc is not configured
3714 -with-gnu-as, it does not output the .set pseudo-ops. */
3715 if (history[1].noreorder_p)
3718 /* If the previous instruction had a fixup in mips16 mode, we can not
3719 swap. This normally means that the previous instruction was a 4
3720 byte branch anyhow. */
3721 if (mips_opts.mips16 && history[0].fixp[0])
3724 /* If the branch is itself the target of a branch, we can not swap.
3725 We cheat on this; all we check for is whether there is a label on
3726 this instruction. If there are any branches to anything other than
3727 a label, users must use .set noreorder. */
3728 if (seg_info (now_seg)->label_list)
3731 /* If the previous instruction is in a variant frag other than this
3732 branch's one, we cannot do the swap. This does not apply to
3733 MIPS16/microMIPS code, which uses variant frags for different
3735 if (!HAVE_CODE_COMPRESSION
3737 && history[0].frag->fr_type == rs_machine_dependent)
3740 /* We do not swap with instructions that cannot architecturally
3741 be placed in a branch delay slot, such as SYNC or ERET. We
3742 also refrain from swapping with a trap instruction, since it
3743 complicates trap handlers to have the trap instruction be in
3745 prev_pinfo = history[0].insn_mo->pinfo;
3746 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3749 /* Check for conflicts between the branch and the instructions
3750 before the candidate delay slot. */
3751 if (nops_for_insn (0, history + 1, ip) > 0)
3754 /* Check for conflicts between the swapped sequence and the
3755 target of the branch. */
3756 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3759 /* If the branch reads a register that the previous
3760 instruction sets, we can not swap. */
3761 gpr_read = gpr_read_mask (ip);
3762 prev_gpr_write = gpr_write_mask (&history[0]);
3763 if (gpr_read & prev_gpr_write)
3766 /* If the branch writes a register that the previous
3767 instruction sets, we can not swap. */
3768 gpr_write = gpr_write_mask (ip);
3769 if (gpr_write & prev_gpr_write)
3772 /* If the branch writes a register that the previous
3773 instruction reads, we can not swap. */
3774 prev_gpr_read = gpr_read_mask (&history[0]);
3775 if (gpr_write & prev_gpr_read)
3778 /* If one instruction sets a condition code and the
3779 other one uses a condition code, we can not swap. */
3780 pinfo = ip->insn_mo->pinfo;
3781 if ((pinfo & INSN_READ_COND_CODE)
3782 && (prev_pinfo & INSN_WRITE_COND_CODE))
3784 if ((pinfo & INSN_WRITE_COND_CODE)
3785 && (prev_pinfo & INSN_READ_COND_CODE))
3788 /* If the previous instruction uses the PC, we can not swap. */
3789 prev_pinfo2 = history[0].insn_mo->pinfo2;
3790 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3792 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3795 /* If the previous instruction has an incorrect size for a fixed
3796 branch delay slot in microMIPS mode, we cannot swap. */
3797 pinfo2 = ip->insn_mo->pinfo2;
3798 if (mips_opts.micromips
3799 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3800 && insn_length (history) != 2)
3802 if (mips_opts.micromips
3803 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3804 && insn_length (history) != 4)
3810 /* Decide how we should add IP to the instruction stream. */
3812 static enum append_method
3813 get_append_method (struct mips_cl_insn *ip)
3815 unsigned long pinfo;
3817 /* The relaxed version of a macro sequence must be inherently
3819 if (mips_relax.sequence == 2)
3822 /* We must not dabble with instructions in a ".set norerorder" block. */
3823 if (mips_opts.noreorder)
3826 /* Otherwise, it's our responsibility to fill branch delay slots. */
3827 if (delayed_branch_p (ip))
3829 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3832 pinfo = ip->insn_mo->pinfo;
3833 if (mips_opts.mips16
3834 && ISA_SUPPORTS_MIPS16E
3835 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3836 return APPEND_ADD_COMPACT;
3838 return APPEND_ADD_WITH_NOP;
3844 /* IP is a MIPS16 instruction whose opcode we have just changed.
3845 Point IP->insn_mo to the new opcode's definition. */
3848 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3850 const struct mips_opcode *mo, *end;
3852 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3853 for (mo = ip->insn_mo; mo < end; mo++)
3854 if ((ip->insn_opcode & mo->mask) == mo->match)
3862 /* For microMIPS macros, we need to generate a local number label
3863 as the target of branches. */
3864 #define MICROMIPS_LABEL_CHAR '\037'
3865 static unsigned long micromips_target_label;
3866 static char micromips_target_name[32];
3869 micromips_label_name (void)
3871 char *p = micromips_target_name;
3872 char symbol_name_temporary[24];
3880 l = micromips_target_label;
3881 #ifdef LOCAL_LABEL_PREFIX
3882 *p++ = LOCAL_LABEL_PREFIX;
3885 *p++ = MICROMIPS_LABEL_CHAR;
3888 symbol_name_temporary[i++] = l % 10 + '0';
3893 *p++ = symbol_name_temporary[--i];
3896 return micromips_target_name;
3900 micromips_label_expr (expressionS *label_expr)
3902 label_expr->X_op = O_symbol;
3903 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3904 label_expr->X_add_number = 0;
3908 micromips_label_inc (void)
3910 micromips_target_label++;
3911 *micromips_target_name = '\0';
3915 micromips_add_label (void)
3919 s = colon (micromips_label_name ());
3920 micromips_label_inc ();
3921 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3923 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3927 /* If assembling microMIPS code, then return the microMIPS reloc
3928 corresponding to the requested one if any. Otherwise return
3929 the reloc unchanged. */
3931 static bfd_reloc_code_real_type
3932 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3934 static const bfd_reloc_code_real_type relocs[][2] =
3936 /* Keep sorted incrementally by the left-hand key. */
3937 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3938 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3939 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3940 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3941 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3942 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3943 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
3944 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
3945 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
3946 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
3947 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
3948 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
3949 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
3950 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
3951 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
3952 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
3953 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
3954 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
3955 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
3956 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
3957 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
3958 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
3959 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
3960 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
3961 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
3962 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
3963 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
3965 bfd_reloc_code_real_type r;
3968 if (!mips_opts.micromips)
3970 for (i = 0; i < ARRAY_SIZE (relocs); i++)
3976 return relocs[i][1];
3981 /* Output an instruction. IP is the instruction information.
3982 ADDRESS_EXPR is an operand of the instruction to be used with
3983 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
3984 a macro expansion. */
3987 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3988 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
3990 unsigned long prev_pinfo2, pinfo;
3991 bfd_boolean relaxed_branch = FALSE;
3992 enum append_method method;
3993 bfd_boolean relax32;
3996 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
3997 fix_loongson2f (ip);
3999 mips_mark_labels ();
4001 file_ase_mips16 |= mips_opts.mips16;
4002 file_ase_micromips |= mips_opts.micromips;
4004 prev_pinfo2 = history[0].insn_mo->pinfo2;
4005 pinfo = ip->insn_mo->pinfo;
4007 if (mips_opts.micromips
4009 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4010 && micromips_insn_length (ip->insn_mo) != 2)
4011 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4012 && micromips_insn_length (ip->insn_mo) != 4)))
4013 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4014 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4016 if (address_expr == NULL)
4018 else if (*reloc_type <= BFD_RELOC_UNUSED
4019 && address_expr->X_op == O_constant)
4024 switch (*reloc_type)
4027 ip->insn_opcode |= address_expr->X_add_number;
4030 case BFD_RELOC_MIPS_HIGHEST:
4031 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
4032 ip->insn_opcode |= tmp & 0xffff;
4035 case BFD_RELOC_MIPS_HIGHER:
4036 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
4037 ip->insn_opcode |= tmp & 0xffff;
4040 case BFD_RELOC_HI16_S:
4041 tmp = (address_expr->X_add_number + 0x8000) >> 16;
4042 ip->insn_opcode |= tmp & 0xffff;
4045 case BFD_RELOC_HI16:
4046 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
4049 case BFD_RELOC_UNUSED:
4050 case BFD_RELOC_LO16:
4051 case BFD_RELOC_MIPS_GOT_DISP:
4052 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
4055 case BFD_RELOC_MIPS_JMP:
4059 shift = mips_opts.micromips ? 1 : 2;
4060 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4061 as_bad (_("jump to misaligned address (0x%lx)"),
4062 (unsigned long) address_expr->X_add_number);
4063 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4069 case BFD_RELOC_MIPS16_JMP:
4070 if ((address_expr->X_add_number & 3) != 0)
4071 as_bad (_("jump to misaligned address (0x%lx)"),
4072 (unsigned long) address_expr->X_add_number);
4074 (((address_expr->X_add_number & 0x7c0000) << 3)
4075 | ((address_expr->X_add_number & 0xf800000) >> 7)
4076 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4080 case BFD_RELOC_16_PCREL_S2:
4084 shift = mips_opts.micromips ? 1 : 2;
4085 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4086 as_bad (_("branch to misaligned address (0x%lx)"),
4087 (unsigned long) address_expr->X_add_number);
4088 if (!mips_relax_branch)
4090 if ((address_expr->X_add_number + (1 << (shift + 15)))
4091 & ~((1 << (shift + 16)) - 1))
4092 as_bad (_("branch address range overflow (0x%lx)"),
4093 (unsigned long) address_expr->X_add_number);
4094 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4106 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4108 /* There are a lot of optimizations we could do that we don't.
4109 In particular, we do not, in general, reorder instructions.
4110 If you use gcc with optimization, it will reorder
4111 instructions and generally do much more optimization then we
4112 do here; repeating all that work in the assembler would only
4113 benefit hand written assembly code, and does not seem worth
4115 int nops = (mips_optimize == 0
4116 ? nops_for_insn (0, history, NULL)
4117 : nops_for_insn_or_target (0, history, ip));
4121 unsigned long old_frag_offset;
4124 old_frag = frag_now;
4125 old_frag_offset = frag_now_fix ();
4127 for (i = 0; i < nops; i++)
4128 add_fixed_insn (NOP_INSN);
4129 insert_into_history (0, nops, NOP_INSN);
4133 listing_prev_line ();
4134 /* We may be at the start of a variant frag. In case we
4135 are, make sure there is enough space for the frag
4136 after the frags created by listing_prev_line. The
4137 argument to frag_grow here must be at least as large
4138 as the argument to all other calls to frag_grow in
4139 this file. We don't have to worry about being in the
4140 middle of a variant frag, because the variants insert
4141 all needed nop instructions themselves. */
4145 mips_move_labels ();
4147 #ifndef NO_ECOFF_DEBUGGING
4148 if (ECOFF_DEBUGGING)
4149 ecoff_fix_loc (old_frag, old_frag_offset);
4153 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4157 /* Work out how many nops in prev_nop_frag are needed by IP,
4158 ignoring hazards generated by the first prev_nop_frag_since
4160 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4161 gas_assert (nops <= prev_nop_frag_holds);
4163 /* Enforce NOPS as a minimum. */
4164 if (nops > prev_nop_frag_required)
4165 prev_nop_frag_required = nops;
4167 if (prev_nop_frag_holds == prev_nop_frag_required)
4169 /* Settle for the current number of nops. Update the history
4170 accordingly (for the benefit of any future .set reorder code). */
4171 prev_nop_frag = NULL;
4172 insert_into_history (prev_nop_frag_since,
4173 prev_nop_frag_holds, NOP_INSN);
4177 /* Allow this instruction to replace one of the nops that was
4178 tentatively added to prev_nop_frag. */
4179 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4180 prev_nop_frag_holds--;
4181 prev_nop_frag_since++;
4185 method = get_append_method (ip);
4186 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4189 /* The value passed to dwarf2_emit_insn is the distance between
4190 the beginning of the current instruction and the address that
4191 should be recorded in the debug tables. This is normally the
4194 For MIPS16/microMIPS debug info we want to use ISA-encoded
4195 addresses, so we use -1 for an address higher by one than the
4198 If the instruction produced is a branch that we will swap with
4199 the preceding instruction, then we add the displacement by which
4200 the branch will be moved backwards. This is more appropriate
4201 and for MIPS16/microMIPS code also prevents a debugger from
4202 placing a breakpoint in the middle of the branch (and corrupting
4203 code if software breakpoints are used). */
4204 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4207 relax32 = (mips_relax_branch
4208 /* Don't try branch relaxation within .set nomacro, or within
4209 .set noat if we use $at for PIC computations. If it turns
4210 out that the branch was out-of-range, we'll get an error. */
4211 && !mips_opts.warn_about_macros
4212 && (mips_opts.at || mips_pic == NO_PIC)
4213 /* Don't relax BPOSGE32/64 as they have no complementing
4215 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4217 if (!HAVE_CODE_COMPRESSION
4220 && *reloc_type == BFD_RELOC_16_PCREL_S2
4221 && delayed_branch_p (ip))
4223 relaxed_branch = TRUE;
4224 add_relaxed_insn (ip, (relaxed_branch_length
4226 uncond_branch_p (ip) ? -1
4227 : branch_likely_p (ip) ? 1
4231 uncond_branch_p (ip),
4232 branch_likely_p (ip),
4233 pinfo & INSN_WRITE_GPR_31,
4235 address_expr->X_add_symbol,
4236 address_expr->X_add_number);
4237 *reloc_type = BFD_RELOC_UNUSED;
4239 else if (mips_opts.micromips
4241 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4242 || *reloc_type > BFD_RELOC_UNUSED)
4243 && (delayed_branch_p (ip) || compact_branch_p (ip))
4244 /* Don't try branch relaxation when users specify
4245 16-bit/32-bit instructions. */
4246 && !forced_insn_length)
4248 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4249 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4250 int uncond = uncond_branch_p (ip) ? -1 : 0;
4251 int compact = compact_branch_p (ip);
4252 int al = pinfo & INSN_WRITE_GPR_31;
4255 gas_assert (address_expr != NULL);
4256 gas_assert (!mips_relax.sequence);
4258 relaxed_branch = TRUE;
4259 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4260 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4261 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4263 address_expr->X_add_symbol,
4264 address_expr->X_add_number);
4265 *reloc_type = BFD_RELOC_UNUSED;
4267 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4269 /* We need to set up a variant frag. */
4270 gas_assert (address_expr != NULL);
4271 add_relaxed_insn (ip, 4, 0,
4273 (*reloc_type - BFD_RELOC_UNUSED,
4274 forced_insn_length == 2, forced_insn_length == 4,
4275 delayed_branch_p (&history[0]),
4276 history[0].mips16_absolute_jump_p),
4277 make_expr_symbol (address_expr), 0);
4279 else if (mips_opts.mips16
4281 && *reloc_type != BFD_RELOC_MIPS16_JMP)
4283 if (!delayed_branch_p (ip))
4284 /* Make sure there is enough room to swap this instruction with
4285 a following jump instruction. */
4287 add_fixed_insn (ip);
4291 if (mips_opts.mips16
4292 && mips_opts.noreorder
4293 && delayed_branch_p (&history[0]))
4294 as_warn (_("extended instruction in delay slot"));
4296 if (mips_relax.sequence)
4298 /* If we've reached the end of this frag, turn it into a variant
4299 frag and record the information for the instructions we've
4301 if (frag_room () < 4)
4302 relax_close_frag ();
4303 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4306 if (mips_relax.sequence != 2)
4308 if (mips_macro_warning.first_insn_sizes[0] == 0)
4309 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4310 mips_macro_warning.sizes[0] += insn_length (ip);
4311 mips_macro_warning.insns[0]++;
4313 if (mips_relax.sequence != 1)
4315 if (mips_macro_warning.first_insn_sizes[1] == 0)
4316 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4317 mips_macro_warning.sizes[1] += insn_length (ip);
4318 mips_macro_warning.insns[1]++;
4321 if (mips_opts.mips16)
4324 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4326 add_fixed_insn (ip);
4329 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4331 bfd_reloc_code_real_type final_type[3];
4332 reloc_howto_type *howto0;
4333 reloc_howto_type *howto;
4336 /* Perform any necessary conversion to microMIPS relocations
4337 and find out how many relocations there actually are. */
4338 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4339 final_type[i] = micromips_map_reloc (reloc_type[i]);
4341 /* In a compound relocation, it is the final (outermost)
4342 operator that determines the relocated field. */
4343 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4347 /* To reproduce this failure try assembling gas/testsuites/
4348 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4350 as_bad (_("Unsupported MIPS relocation number %d"),
4352 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4356 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4357 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4358 bfd_get_reloc_size (howto),
4360 howto0 && howto0->pc_relative,
4363 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4364 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4365 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4367 /* These relocations can have an addend that won't fit in
4368 4 octets for 64bit assembly. */
4370 && ! howto->partial_inplace
4371 && (reloc_type[0] == BFD_RELOC_16
4372 || reloc_type[0] == BFD_RELOC_32
4373 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4374 || reloc_type[0] == BFD_RELOC_GPREL16
4375 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4376 || reloc_type[0] == BFD_RELOC_GPREL32
4377 || reloc_type[0] == BFD_RELOC_64
4378 || reloc_type[0] == BFD_RELOC_CTOR
4379 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4380 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4381 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4382 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4383 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4384 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4385 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4386 || hi16_reloc_p (reloc_type[0])
4387 || lo16_reloc_p (reloc_type[0])))
4388 ip->fixp[0]->fx_no_overflow = 1;
4390 if (mips_relax.sequence)
4392 if (mips_relax.first_fixup == 0)
4393 mips_relax.first_fixup = ip->fixp[0];
4395 else if (reloc_needs_lo_p (*reloc_type))
4397 struct mips_hi_fixup *hi_fixup;
4399 /* Reuse the last entry if it already has a matching %lo. */
4400 hi_fixup = mips_hi_fixup_list;
4402 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4404 hi_fixup = ((struct mips_hi_fixup *)
4405 xmalloc (sizeof (struct mips_hi_fixup)));
4406 hi_fixup->next = mips_hi_fixup_list;
4407 mips_hi_fixup_list = hi_fixup;
4409 hi_fixup->fixp = ip->fixp[0];
4410 hi_fixup->seg = now_seg;
4413 /* Add fixups for the second and third relocations, if given.
4414 Note that the ABI allows the second relocation to be
4415 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4416 moment we only use RSS_UNDEF, but we could add support
4417 for the others if it ever becomes necessary. */
4418 for (i = 1; i < 3; i++)
4419 if (reloc_type[i] != BFD_RELOC_UNUSED)
4421 ip->fixp[i] = fix_new (ip->frag, ip->where,
4422 ip->fixp[0]->fx_size, NULL, 0,
4423 FALSE, final_type[i]);
4425 /* Use fx_tcbit to mark compound relocs. */
4426 ip->fixp[0]->fx_tcbit = 1;
4427 ip->fixp[i]->fx_tcbit = 1;
4432 /* Update the register mask information. */
4433 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4434 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4439 insert_into_history (0, 1, ip);
4442 case APPEND_ADD_WITH_NOP:
4444 struct mips_cl_insn *nop;
4446 insert_into_history (0, 1, ip);
4447 nop = get_delay_slot_nop (ip);
4448 add_fixed_insn (nop);
4449 insert_into_history (0, 1, nop);
4450 if (mips_relax.sequence)
4451 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4455 case APPEND_ADD_COMPACT:
4456 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4457 gas_assert (mips_opts.mips16);
4458 ip->insn_opcode |= 0x0080;
4459 find_altered_mips16_opcode (ip);
4461 insert_into_history (0, 1, ip);
4466 struct mips_cl_insn delay = history[0];
4467 if (mips_opts.mips16)
4469 know (delay.frag == ip->frag);
4470 move_insn (ip, delay.frag, delay.where);
4471 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4473 else if (relaxed_branch)
4475 /* Add the delay slot instruction to the end of the
4476 current frag and shrink the fixed part of the
4477 original frag. If the branch occupies the tail of
4478 the latter, move it backwards to cover the gap. */
4479 delay.frag->fr_fix -= branch_disp;
4480 if (delay.frag == ip->frag)
4481 move_insn (ip, ip->frag, ip->where - branch_disp);
4482 add_fixed_insn (&delay);
4486 move_insn (&delay, ip->frag,
4487 ip->where - branch_disp + insn_length (ip));
4488 move_insn (ip, history[0].frag, history[0].where);
4492 insert_into_history (0, 1, &delay);
4497 /* If we have just completed an unconditional branch, clear the history. */
4498 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4499 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4500 mips_no_prev_insn ();
4502 /* We need to emit a label at the end of branch-likely macros. */
4503 if (emit_branch_likely_macro)
4505 emit_branch_likely_macro = FALSE;
4506 micromips_add_label ();
4509 /* We just output an insn, so the next one doesn't have a label. */
4510 mips_clear_insn_labels ();
4513 /* Forget that there was any previous instruction or label. */
4516 mips_no_prev_insn (void)
4518 prev_nop_frag = NULL;
4519 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4520 mips_clear_insn_labels ();
4523 /* This function must be called before we emit something other than
4524 instructions. It is like mips_no_prev_insn except that it inserts
4525 any NOPS that might be needed by previous instructions. */
4528 mips_emit_delays (void)
4530 if (! mips_opts.noreorder)
4532 int nops = nops_for_insn (0, history, NULL);
4536 add_fixed_insn (NOP_INSN);
4537 mips_move_labels ();
4540 mips_no_prev_insn ();
4543 /* Start a (possibly nested) noreorder block. */
4546 start_noreorder (void)
4548 if (mips_opts.noreorder == 0)
4553 /* None of the instructions before the .set noreorder can be moved. */
4554 for (i = 0; i < ARRAY_SIZE (history); i++)
4555 history[i].fixed_p = 1;
4557 /* Insert any nops that might be needed between the .set noreorder
4558 block and the previous instructions. We will later remove any
4559 nops that turn out not to be needed. */
4560 nops = nops_for_insn (0, history, NULL);
4563 if (mips_optimize != 0)
4565 /* Record the frag which holds the nop instructions, so
4566 that we can remove them if we don't need them. */
4567 frag_grow (nops * NOP_INSN_SIZE);
4568 prev_nop_frag = frag_now;
4569 prev_nop_frag_holds = nops;
4570 prev_nop_frag_required = 0;
4571 prev_nop_frag_since = 0;
4574 for (; nops > 0; --nops)
4575 add_fixed_insn (NOP_INSN);
4577 /* Move on to a new frag, so that it is safe to simply
4578 decrease the size of prev_nop_frag. */
4579 frag_wane (frag_now);
4581 mips_move_labels ();
4583 mips_mark_labels ();
4584 mips_clear_insn_labels ();
4586 mips_opts.noreorder++;
4587 mips_any_noreorder = 1;
4590 /* End a nested noreorder block. */
4593 end_noreorder (void)
4596 mips_opts.noreorder--;
4597 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4599 /* Commit to inserting prev_nop_frag_required nops and go back to
4600 handling nop insertion the .set reorder way. */
4601 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4603 insert_into_history (prev_nop_frag_since,
4604 prev_nop_frag_required, NOP_INSN);
4605 prev_nop_frag = NULL;
4609 /* Set up global variables for the start of a new macro. */
4614 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4615 memset (&mips_macro_warning.first_insn_sizes, 0,
4616 sizeof (mips_macro_warning.first_insn_sizes));
4617 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4618 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4619 && delayed_branch_p (&history[0]));
4620 switch (history[0].insn_mo->pinfo2
4621 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4623 case INSN2_BRANCH_DELAY_32BIT:
4624 mips_macro_warning.delay_slot_length = 4;
4626 case INSN2_BRANCH_DELAY_16BIT:
4627 mips_macro_warning.delay_slot_length = 2;
4630 mips_macro_warning.delay_slot_length = 0;
4633 mips_macro_warning.first_frag = NULL;
4636 /* Given that a macro is longer than one instruction or of the wrong size,
4637 return the appropriate warning for it. Return null if no warning is
4638 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4639 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4640 and RELAX_NOMACRO. */
4643 macro_warning (relax_substateT subtype)
4645 if (subtype & RELAX_DELAY_SLOT)
4646 return _("Macro instruction expanded into multiple instructions"
4647 " in a branch delay slot");
4648 else if (subtype & RELAX_NOMACRO)
4649 return _("Macro instruction expanded into multiple instructions");
4650 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4651 | RELAX_DELAY_SLOT_SIZE_SECOND))
4652 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4653 ? _("Macro instruction expanded into a wrong size instruction"
4654 " in a 16-bit branch delay slot")
4655 : _("Macro instruction expanded into a wrong size instruction"
4656 " in a 32-bit branch delay slot"));
4661 /* Finish up a macro. Emit warnings as appropriate. */
4666 /* Relaxation warning flags. */
4667 relax_substateT subtype = 0;
4669 /* Check delay slot size requirements. */
4670 if (mips_macro_warning.delay_slot_length == 2)
4671 subtype |= RELAX_DELAY_SLOT_16BIT;
4672 if (mips_macro_warning.delay_slot_length != 0)
4674 if (mips_macro_warning.delay_slot_length
4675 != mips_macro_warning.first_insn_sizes[0])
4676 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4677 if (mips_macro_warning.delay_slot_length
4678 != mips_macro_warning.first_insn_sizes[1])
4679 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4682 /* Check instruction count requirements. */
4683 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4685 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4686 subtype |= RELAX_SECOND_LONGER;
4687 if (mips_opts.warn_about_macros)
4688 subtype |= RELAX_NOMACRO;
4689 if (mips_macro_warning.delay_slot_p)
4690 subtype |= RELAX_DELAY_SLOT;
4693 /* If both alternatives fail to fill a delay slot correctly,
4694 emit the warning now. */
4695 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4696 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4701 s = subtype & (RELAX_DELAY_SLOT_16BIT
4702 | RELAX_DELAY_SLOT_SIZE_FIRST
4703 | RELAX_DELAY_SLOT_SIZE_SECOND);
4704 msg = macro_warning (s);
4706 as_warn ("%s", msg);
4710 /* If both implementations are longer than 1 instruction, then emit the
4712 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4717 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4718 msg = macro_warning (s);
4720 as_warn ("%s", msg);
4724 /* If any flags still set, then one implementation might need a warning
4725 and the other either will need one of a different kind or none at all.
4726 Pass any remaining flags over to relaxation. */
4727 if (mips_macro_warning.first_frag != NULL)
4728 mips_macro_warning.first_frag->fr_subtype |= subtype;
4731 /* Instruction operand formats used in macros that vary between
4732 standard MIPS and microMIPS code. */
4734 static const char * const brk_fmt[2] = { "c", "mF" };
4735 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4736 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4737 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4738 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4739 static const char * const mfhl_fmt[2] = { "d", "mj" };
4740 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4741 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4743 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4744 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4745 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4746 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4747 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4748 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4749 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4750 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4752 /* Read a macro's relocation codes from *ARGS and store them in *R.
4753 The first argument in *ARGS will be either the code for a single
4754 relocation or -1 followed by the three codes that make up a
4755 composite relocation. */
4758 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4762 next = va_arg (*args, int);
4764 r[0] = (bfd_reloc_code_real_type) next;
4766 for (i = 0; i < 3; i++)
4767 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4770 /* Build an instruction created by a macro expansion. This is passed
4771 a pointer to the count of instructions created so far, an
4772 expression, the name of the instruction to build, an operand format
4773 string, and corresponding arguments. */
4776 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4778 const struct mips_opcode *mo = NULL;
4779 bfd_reloc_code_real_type r[3];
4780 const struct mips_opcode *amo;
4781 struct hash_control *hash;
4782 struct mips_cl_insn insn;
4785 va_start (args, fmt);
4787 if (mips_opts.mips16)
4789 mips16_macro_build (ep, name, fmt, &args);
4794 r[0] = BFD_RELOC_UNUSED;
4795 r[1] = BFD_RELOC_UNUSED;
4796 r[2] = BFD_RELOC_UNUSED;
4797 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4798 amo = (struct mips_opcode *) hash_find (hash, name);
4800 gas_assert (strcmp (name, amo->name) == 0);
4804 /* Search until we get a match for NAME. It is assumed here that
4805 macros will never generate MDMX, MIPS-3D, or MT instructions.
4806 We try to match an instruction that fulfils the branch delay
4807 slot instruction length requirement (if any) of the previous
4808 instruction. While doing this we record the first instruction
4809 seen that matches all the other conditions and use it anyway
4810 if the requirement cannot be met; we will issue an appropriate
4811 warning later on. */
4812 if (strcmp (fmt, amo->args) == 0
4813 && amo->pinfo != INSN_MACRO
4814 && is_opcode_valid (amo)
4815 && is_size_valid (amo))
4817 if (is_delay_slot_valid (amo))
4827 gas_assert (amo->name);
4829 while (strcmp (name, amo->name) == 0);
4832 create_insn (&insn, mo);
4850 INSERT_OPERAND (mips_opts.micromips,
4851 EXTLSB, insn, va_arg (args, int));
4856 /* Note that in the macro case, these arguments are already
4857 in MSB form. (When handling the instruction in the
4858 non-macro case, these arguments are sizes from which
4859 MSB values must be calculated.) */
4860 INSERT_OPERAND (mips_opts.micromips,
4861 INSMSB, insn, va_arg (args, int));
4867 /* Note that in the macro case, these arguments are already
4868 in MSBD form. (When handling the instruction in the
4869 non-macro case, these arguments are sizes from which
4870 MSBD values must be calculated.) */
4871 INSERT_OPERAND (mips_opts.micromips,
4872 EXTMSBD, insn, va_arg (args, int));
4876 gas_assert (!mips_opts.micromips);
4877 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4886 gas_assert (!mips_opts.micromips);
4887 INSERT_OPERAND (0, BP, insn, va_arg (args, int));
4891 gas_assert (mips_opts.micromips);
4895 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4899 gas_assert (!mips_opts.micromips);
4900 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4904 gas_assert (!mips_opts.micromips);
4906 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4910 if (mips_opts.micromips)
4911 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4913 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4917 gas_assert (!mips_opts.micromips);
4919 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
4923 gas_assert (!mips_opts.micromips);
4925 int tmp = va_arg (args, int);
4927 INSERT_OPERAND (0, RT, insn, tmp);
4928 INSERT_OPERAND (0, RD, insn, tmp);
4934 gas_assert (!mips_opts.micromips);
4935 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
4942 INSERT_OPERAND (mips_opts.micromips,
4943 SHAMT, insn, va_arg (args, int));
4947 gas_assert (!mips_opts.micromips);
4948 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
4952 gas_assert (!mips_opts.micromips);
4953 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
4957 gas_assert (!mips_opts.micromips);
4958 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
4962 gas_assert (!mips_opts.micromips);
4963 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
4970 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
4975 macro_read_relocs (&args, r);
4976 gas_assert (*r == BFD_RELOC_GPREL16
4977 || *r == BFD_RELOC_MIPS_HIGHER
4978 || *r == BFD_RELOC_HI16_S
4979 || *r == BFD_RELOC_LO16
4980 || *r == BFD_RELOC_MIPS_GOT_OFST);
4984 macro_read_relocs (&args, r);
4988 macro_read_relocs (&args, r);
4989 gas_assert (ep != NULL
4990 && (ep->X_op == O_constant
4991 || (ep->X_op == O_symbol
4992 && (*r == BFD_RELOC_MIPS_HIGHEST
4993 || *r == BFD_RELOC_HI16_S
4994 || *r == BFD_RELOC_HI16
4995 || *r == BFD_RELOC_GPREL16
4996 || *r == BFD_RELOC_MIPS_GOT_HI16
4997 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5001 gas_assert (ep != NULL);
5004 * This allows macro() to pass an immediate expression for
5005 * creating short branches without creating a symbol.
5007 * We don't allow branch relaxation for these branches, as
5008 * they should only appear in ".set nomacro" anyway.
5010 if (ep->X_op == O_constant)
5012 /* For microMIPS we always use relocations for branches.
5013 So we should not resolve immediate values. */
5014 gas_assert (!mips_opts.micromips);
5016 if ((ep->X_add_number & 3) != 0)
5017 as_bad (_("branch to misaligned address (0x%lx)"),
5018 (unsigned long) ep->X_add_number);
5019 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5020 as_bad (_("branch address range overflow (0x%lx)"),
5021 (unsigned long) ep->X_add_number);
5022 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5026 *r = BFD_RELOC_16_PCREL_S2;
5030 gas_assert (ep != NULL);
5031 *r = BFD_RELOC_MIPS_JMP;
5035 gas_assert (!mips_opts.micromips);
5036 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5040 INSERT_OPERAND (mips_opts.micromips,
5041 CACHE, insn, va_arg (args, unsigned long));
5045 gas_assert (mips_opts.micromips);
5046 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5050 gas_assert (mips_opts.micromips);
5051 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5055 INSERT_OPERAND (mips_opts.micromips,
5056 3BITPOS, insn, va_arg (args, unsigned int));
5060 INSERT_OPERAND (mips_opts.micromips,
5061 OFFSET12, insn, va_arg (args, unsigned long));
5065 gas_assert (mips_opts.micromips);
5066 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5069 case 'm': /* Opcode extension character. */
5070 gas_assert (mips_opts.micromips);
5074 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5078 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5082 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5096 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5098 append_insn (&insn, ep, r, TRUE);
5102 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5105 struct mips_opcode *mo;
5106 struct mips_cl_insn insn;
5107 bfd_reloc_code_real_type r[3]
5108 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5110 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5112 gas_assert (strcmp (name, mo->name) == 0);
5114 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5117 gas_assert (mo->name);
5118 gas_assert (strcmp (name, mo->name) == 0);
5121 create_insn (&insn, mo);
5139 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5144 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5148 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5152 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5162 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5169 regno = va_arg (*args, int);
5170 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5171 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5192 gas_assert (ep != NULL);
5194 if (ep->X_op != O_constant)
5195 *r = (int) BFD_RELOC_UNUSED + c;
5198 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
5199 FALSE, &insn.insn_opcode, &insn.use_extend,
5202 *r = BFD_RELOC_UNUSED;
5208 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5215 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5217 append_insn (&insn, ep, r, TRUE);
5221 * Sign-extend 32-bit mode constants that have bit 31 set and all
5222 * higher bits unset.
5225 normalize_constant_expr (expressionS *ex)
5227 if (ex->X_op == O_constant
5228 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5229 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5234 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5235 * all higher bits unset.
5238 normalize_address_expr (expressionS *ex)
5240 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5241 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5242 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5243 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5248 * Generate a "jalr" instruction with a relocation hint to the called
5249 * function. This occurs in NewABI PIC code.
5252 macro_build_jalr (expressionS *ep, int cprestore)
5254 static const bfd_reloc_code_real_type jalr_relocs[2]
5255 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5256 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5260 if (MIPS_JALR_HINT_P (ep))
5265 if (!mips_opts.micromips)
5266 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5269 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5270 if (MIPS_JALR_HINT_P (ep))
5271 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5273 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5275 if (MIPS_JALR_HINT_P (ep))
5276 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5280 * Generate a "lui" instruction.
5283 macro_build_lui (expressionS *ep, int regnum)
5285 gas_assert (! mips_opts.mips16);
5287 if (ep->X_op != O_constant)
5289 gas_assert (ep->X_op == O_symbol);
5290 /* _gp_disp is a special case, used from s_cpload.
5291 __gnu_local_gp is used if mips_no_shared. */
5292 gas_assert (mips_pic == NO_PIC
5294 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5295 || (! mips_in_shared
5296 && strcmp (S_GET_NAME (ep->X_add_symbol),
5297 "__gnu_local_gp") == 0));
5300 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5303 /* Generate a sequence of instructions to do a load or store from a constant
5304 offset off of a base register (breg) into/from a target register (treg),
5305 using AT if necessary. */
5307 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5308 int treg, int breg, int dbl)
5310 gas_assert (ep->X_op == O_constant);
5312 /* Sign-extending 32-bit constants makes their handling easier. */
5314 normalize_constant_expr (ep);
5316 /* Right now, this routine can only handle signed 32-bit constants. */
5317 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5318 as_warn (_("operand overflow"));
5320 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5322 /* Signed 16-bit offset will fit in the op. Easy! */
5323 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5327 /* 32-bit offset, need multiple instructions and AT, like:
5328 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5329 addu $tempreg,$tempreg,$breg
5330 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5331 to handle the complete offset. */
5332 macro_build_lui (ep, AT);
5333 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5334 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5337 as_bad (_("Macro used $at after \".set noat\""));
5342 * Generates code to set the $at register to true (one)
5343 * if reg is less than the immediate expression.
5346 set_at (int reg, int unsignedp)
5348 if (imm_expr.X_op == O_constant
5349 && imm_expr.X_add_number >= -0x8000
5350 && imm_expr.X_add_number < 0x8000)
5351 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5352 AT, reg, BFD_RELOC_LO16);
5355 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5356 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5360 /* Warn if an expression is not a constant. */
5363 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5365 if (ex->X_op == O_big)
5366 as_bad (_("unsupported large constant"));
5367 else if (ex->X_op != O_constant)
5368 as_bad (_("Instruction %s requires absolute expression"),
5371 if (HAVE_32BIT_GPRS)
5372 normalize_constant_expr (ex);
5375 /* Count the leading zeroes by performing a binary chop. This is a
5376 bulky bit of source, but performance is a LOT better for the
5377 majority of values than a simple loop to count the bits:
5378 for (lcnt = 0; (lcnt < 32); lcnt++)
5379 if ((v) & (1 << (31 - lcnt)))
5381 However it is not code size friendly, and the gain will drop a bit
5382 on certain cached systems.
5384 #define COUNT_TOP_ZEROES(v) \
5385 (((v) & ~0xffff) == 0 \
5386 ? ((v) & ~0xff) == 0 \
5387 ? ((v) & ~0xf) == 0 \
5388 ? ((v) & ~0x3) == 0 \
5389 ? ((v) & ~0x1) == 0 \
5394 : ((v) & ~0x7) == 0 \
5397 : ((v) & ~0x3f) == 0 \
5398 ? ((v) & ~0x1f) == 0 \
5401 : ((v) & ~0x7f) == 0 \
5404 : ((v) & ~0xfff) == 0 \
5405 ? ((v) & ~0x3ff) == 0 \
5406 ? ((v) & ~0x1ff) == 0 \
5409 : ((v) & ~0x7ff) == 0 \
5412 : ((v) & ~0x3fff) == 0 \
5413 ? ((v) & ~0x1fff) == 0 \
5416 : ((v) & ~0x7fff) == 0 \
5419 : ((v) & ~0xffffff) == 0 \
5420 ? ((v) & ~0xfffff) == 0 \
5421 ? ((v) & ~0x3ffff) == 0 \
5422 ? ((v) & ~0x1ffff) == 0 \
5425 : ((v) & ~0x7ffff) == 0 \
5428 : ((v) & ~0x3fffff) == 0 \
5429 ? ((v) & ~0x1fffff) == 0 \
5432 : ((v) & ~0x7fffff) == 0 \
5435 : ((v) & ~0xfffffff) == 0 \
5436 ? ((v) & ~0x3ffffff) == 0 \
5437 ? ((v) & ~0x1ffffff) == 0 \
5440 : ((v) & ~0x7ffffff) == 0 \
5443 : ((v) & ~0x3fffffff) == 0 \
5444 ? ((v) & ~0x1fffffff) == 0 \
5447 : ((v) & ~0x7fffffff) == 0 \
5452 * This routine generates the least number of instructions necessary to load
5453 * an absolute expression value into a register.
5456 load_register (int reg, expressionS *ep, int dbl)
5459 expressionS hi32, lo32;
5461 if (ep->X_op != O_big)
5463 gas_assert (ep->X_op == O_constant);
5465 /* Sign-extending 32-bit constants makes their handling easier. */
5467 normalize_constant_expr (ep);
5469 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5471 /* We can handle 16 bit signed values with an addiu to
5472 $zero. No need to ever use daddiu here, since $zero and
5473 the result are always correct in 32 bit mode. */
5474 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5477 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5479 /* We can handle 16 bit unsigned values with an ori to
5481 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5484 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5486 /* 32 bit values require an lui. */
5487 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5488 if ((ep->X_add_number & 0xffff) != 0)
5489 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5494 /* The value is larger than 32 bits. */
5496 if (!dbl || HAVE_32BIT_GPRS)
5500 sprintf_vma (value, ep->X_add_number);
5501 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5502 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5506 if (ep->X_op != O_big)
5509 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5510 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5511 hi32.X_add_number &= 0xffffffff;
5513 lo32.X_add_number &= 0xffffffff;
5517 gas_assert (ep->X_add_number > 2);
5518 if (ep->X_add_number == 3)
5519 generic_bignum[3] = 0;
5520 else if (ep->X_add_number > 4)
5521 as_bad (_("Number larger than 64 bits"));
5522 lo32.X_op = O_constant;
5523 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5524 hi32.X_op = O_constant;
5525 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5528 if (hi32.X_add_number == 0)
5533 unsigned long hi, lo;
5535 if (hi32.X_add_number == (offsetT) 0xffffffff)
5537 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5539 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5542 if (lo32.X_add_number & 0x80000000)
5544 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5545 if (lo32.X_add_number & 0xffff)
5546 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5551 /* Check for 16bit shifted constant. We know that hi32 is
5552 non-zero, so start the mask on the first bit of the hi32
5557 unsigned long himask, lomask;
5561 himask = 0xffff >> (32 - shift);
5562 lomask = (0xffff << shift) & 0xffffffff;
5566 himask = 0xffff << (shift - 32);
5569 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5570 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5574 tmp.X_op = O_constant;
5576 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5577 | (lo32.X_add_number >> shift));
5579 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5580 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5581 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5582 reg, reg, (shift >= 32) ? shift - 32 : shift);
5587 while (shift <= (64 - 16));
5589 /* Find the bit number of the lowest one bit, and store the
5590 shifted value in hi/lo. */
5591 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5592 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5596 while ((lo & 1) == 0)
5601 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5607 while ((hi & 1) == 0)
5616 /* Optimize if the shifted value is a (power of 2) - 1. */
5617 if ((hi == 0 && ((lo + 1) & lo) == 0)
5618 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5620 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5625 /* This instruction will set the register to be all
5627 tmp.X_op = O_constant;
5628 tmp.X_add_number = (offsetT) -1;
5629 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5633 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5634 reg, reg, (bit >= 32) ? bit - 32 : bit);
5636 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5637 reg, reg, (shift >= 32) ? shift - 32 : shift);
5642 /* Sign extend hi32 before calling load_register, because we can
5643 generally get better code when we load a sign extended value. */
5644 if ((hi32.X_add_number & 0x80000000) != 0)
5645 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5646 load_register (reg, &hi32, 0);
5649 if ((lo32.X_add_number & 0xffff0000) == 0)
5653 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5661 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5663 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5664 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5670 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5674 mid16.X_add_number >>= 16;
5675 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5676 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5679 if ((lo32.X_add_number & 0xffff) != 0)
5680 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5684 load_delay_nop (void)
5686 if (!gpr_interlocks)
5687 macro_build (NULL, "nop", "");
5690 /* Load an address into a register. */
5693 load_address (int reg, expressionS *ep, int *used_at)
5695 if (ep->X_op != O_constant
5696 && ep->X_op != O_symbol)
5698 as_bad (_("expression too complex"));
5699 ep->X_op = O_constant;
5702 if (ep->X_op == O_constant)
5704 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5708 if (mips_pic == NO_PIC)
5710 /* If this is a reference to a GP relative symbol, we want
5711 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5713 lui $reg,<sym> (BFD_RELOC_HI16_S)
5714 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5715 If we have an addend, we always use the latter form.
5717 With 64bit address space and a usable $at we want
5718 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5719 lui $at,<sym> (BFD_RELOC_HI16_S)
5720 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5721 daddiu $at,<sym> (BFD_RELOC_LO16)
5725 If $at is already in use, we use a path which is suboptimal
5726 on superscalar processors.
5727 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5728 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5730 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5732 daddiu $reg,<sym> (BFD_RELOC_LO16)
5734 For GP relative symbols in 64bit address space we can use
5735 the same sequence as in 32bit address space. */
5736 if (HAVE_64BIT_SYMBOLS)
5738 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5739 && !nopic_need_relax (ep->X_add_symbol, 1))
5741 relax_start (ep->X_add_symbol);
5742 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5743 mips_gp_register, BFD_RELOC_GPREL16);
5747 if (*used_at == 0 && mips_opts.at)
5749 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5750 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5751 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5752 BFD_RELOC_MIPS_HIGHER);
5753 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5754 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5755 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5760 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5761 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5762 BFD_RELOC_MIPS_HIGHER);
5763 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5764 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5765 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5766 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5769 if (mips_relax.sequence)
5774 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5775 && !nopic_need_relax (ep->X_add_symbol, 1))
5777 relax_start (ep->X_add_symbol);
5778 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5779 mips_gp_register, BFD_RELOC_GPREL16);
5782 macro_build_lui (ep, reg);
5783 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5784 reg, reg, BFD_RELOC_LO16);
5785 if (mips_relax.sequence)
5789 else if (!mips_big_got)
5793 /* If this is a reference to an external symbol, we want
5794 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5796 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5798 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5799 If there is a constant, it must be added in after.
5801 If we have NewABI, we want
5802 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5803 unless we're referencing a global symbol with a non-zero
5804 offset, in which case cst must be added separately. */
5807 if (ep->X_add_number)
5809 ex.X_add_number = ep->X_add_number;
5810 ep->X_add_number = 0;
5811 relax_start (ep->X_add_symbol);
5812 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5813 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5814 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5815 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5816 ex.X_op = O_constant;
5817 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5818 reg, reg, BFD_RELOC_LO16);
5819 ep->X_add_number = ex.X_add_number;
5822 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5823 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5824 if (mips_relax.sequence)
5829 ex.X_add_number = ep->X_add_number;
5830 ep->X_add_number = 0;
5831 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5832 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5834 relax_start (ep->X_add_symbol);
5836 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5840 if (ex.X_add_number != 0)
5842 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5843 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5844 ex.X_op = O_constant;
5845 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5846 reg, reg, BFD_RELOC_LO16);
5850 else if (mips_big_got)
5854 /* This is the large GOT case. If this is a reference to an
5855 external symbol, we want
5856 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5858 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5860 Otherwise, for a reference to a local symbol in old ABI, we want
5861 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5863 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5864 If there is a constant, it must be added in after.
5866 In the NewABI, for local symbols, with or without offsets, we want:
5867 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5868 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5872 ex.X_add_number = ep->X_add_number;
5873 ep->X_add_number = 0;
5874 relax_start (ep->X_add_symbol);
5875 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5876 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5877 reg, reg, mips_gp_register);
5878 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5879 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5880 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5881 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5882 else if (ex.X_add_number)
5884 ex.X_op = O_constant;
5885 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5889 ep->X_add_number = ex.X_add_number;
5891 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5892 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5893 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5894 BFD_RELOC_MIPS_GOT_OFST);
5899 ex.X_add_number = ep->X_add_number;
5900 ep->X_add_number = 0;
5901 relax_start (ep->X_add_symbol);
5902 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5903 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5904 reg, reg, mips_gp_register);
5905 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5906 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5908 if (reg_needs_delay (mips_gp_register))
5910 /* We need a nop before loading from $gp. This special
5911 check is required because the lui which starts the main
5912 instruction stream does not refer to $gp, and so will not
5913 insert the nop which may be required. */
5914 macro_build (NULL, "nop", "");
5916 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5917 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5919 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5923 if (ex.X_add_number != 0)
5925 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5926 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5927 ex.X_op = O_constant;
5928 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5936 if (!mips_opts.at && *used_at == 1)
5937 as_bad (_("Macro used $at after \".set noat\""));
5940 /* Move the contents of register SOURCE into register DEST. */
5943 move_register (int dest, int source)
5945 /* Prefer to use a 16-bit microMIPS instruction unless the previous
5946 instruction specifically requires a 32-bit one. */
5947 if (mips_opts.micromips
5948 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5949 macro_build (NULL, "move", "mp,mj", dest, source );
5951 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5955 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5956 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5957 The two alternatives are:
5959 Global symbol Local sybmol
5960 ------------- ------------
5961 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5963 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5965 load_got_offset emits the first instruction and add_got_offset
5966 emits the second for a 16-bit offset or add_got_offset_hilo emits
5967 a sequence to add a 32-bit offset using a scratch register. */
5970 load_got_offset (int dest, expressionS *local)
5975 global.X_add_number = 0;
5977 relax_start (local->X_add_symbol);
5978 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5979 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5981 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5982 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5987 add_got_offset (int dest, expressionS *local)
5991 global.X_op = O_constant;
5992 global.X_op_symbol = NULL;
5993 global.X_add_symbol = NULL;
5994 global.X_add_number = local->X_add_number;
5996 relax_start (local->X_add_symbol);
5997 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5998 dest, dest, BFD_RELOC_LO16);
6000 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6005 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6008 int hold_mips_optimize;
6010 global.X_op = O_constant;
6011 global.X_op_symbol = NULL;
6012 global.X_add_symbol = NULL;
6013 global.X_add_number = local->X_add_number;
6015 relax_start (local->X_add_symbol);
6016 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6018 /* Set mips_optimize around the lui instruction to avoid
6019 inserting an unnecessary nop after the lw. */
6020 hold_mips_optimize = mips_optimize;
6022 macro_build_lui (&global, tmp);
6023 mips_optimize = hold_mips_optimize;
6024 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6027 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6030 /* Emit a sequence of instructions to emulate a branch likely operation.
6031 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6032 is its complementing branch with the original condition negated.
6033 CALL is set if the original branch specified the link operation.
6034 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6036 Code like this is produced in the noreorder mode:
6041 delay slot (executed only if branch taken)
6049 delay slot (executed only if branch taken)
6052 In the reorder mode the delay slot would be filled with a nop anyway,
6053 so code produced is simply:
6058 This function is used when producing code for the microMIPS ASE that
6059 does not implement branch likely instructions in hardware. */
6062 macro_build_branch_likely (const char *br, const char *brneg,
6063 int call, expressionS *ep, const char *fmt,
6064 unsigned int sreg, unsigned int treg)
6066 int noreorder = mips_opts.noreorder;
6069 gas_assert (mips_opts.micromips);
6073 micromips_label_expr (&expr1);
6074 macro_build (&expr1, brneg, fmt, sreg, treg);
6075 macro_build (NULL, "nop", "");
6076 macro_build (ep, call ? "bal" : "b", "p");
6078 /* Set to true so that append_insn adds a label. */
6079 emit_branch_likely_macro = TRUE;
6083 macro_build (ep, br, fmt, sreg, treg);
6084 macro_build (NULL, "nop", "");
6089 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6090 the condition code tested. EP specifies the branch target. */
6093 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6120 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6123 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6124 the register tested. EP specifies the branch target. */
6127 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6129 const char *brneg = NULL;
6139 br = mips_opts.micromips ? "bgez" : "bgezl";
6143 gas_assert (mips_opts.micromips);
6152 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6159 br = mips_opts.micromips ? "blez" : "blezl";
6166 br = mips_opts.micromips ? "bltz" : "bltzl";
6170 gas_assert (mips_opts.micromips);
6178 if (mips_opts.micromips && brneg)
6179 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6181 macro_build (ep, br, "s,p", sreg);
6184 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6185 TREG as the registers tested. EP specifies the branch target. */
6188 macro_build_branch_rsrt (int type, expressionS *ep,
6189 unsigned int sreg, unsigned int treg)
6191 const char *brneg = NULL;
6203 br = mips_opts.micromips ? "beq" : "beql";
6212 br = mips_opts.micromips ? "bne" : "bnel";
6218 if (mips_opts.micromips && brneg)
6219 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6221 macro_build (ep, br, "s,t,p", sreg, treg);
6226 * This routine implements the seemingly endless macro or synthesized
6227 * instructions and addressing modes in the mips assembly language. Many
6228 * of these macros are simple and are similar to each other. These could
6229 * probably be handled by some kind of table or grammar approach instead of
6230 * this verbose method. Others are not simple macros but are more like
6231 * optimizing code generation.
6232 * One interesting optimization is when several store macros appear
6233 * consecutively that would load AT with the upper half of the same address.
6234 * The ensuing load upper instructions are ommited. This implies some kind
6235 * of global optimization. We currently only optimize within a single macro.
6236 * For many of the load and store macros if the address is specified as a
6237 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6238 * first load register 'at' with zero and use it as the base register. The
6239 * mips assembler simply uses register $zero. Just one tiny optimization
6243 macro (struct mips_cl_insn *ip)
6245 unsigned int treg, sreg, dreg, breg;
6246 unsigned int tempreg;
6249 expressionS label_expr;
6267 bfd_reloc_code_real_type r;
6268 int hold_mips_optimize;
6270 gas_assert (! mips_opts.mips16);
6272 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6273 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6274 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6275 mask = ip->insn_mo->mask;
6277 label_expr.X_op = O_constant;
6278 label_expr.X_op_symbol = NULL;
6279 label_expr.X_add_symbol = NULL;
6280 label_expr.X_add_number = 0;
6282 expr1.X_op = O_constant;
6283 expr1.X_op_symbol = NULL;
6284 expr1.X_add_symbol = NULL;
6285 expr1.X_add_number = 1;
6300 if (mips_opts.micromips)
6301 micromips_label_expr (&label_expr);
6303 label_expr.X_add_number = 8;
6304 macro_build (&label_expr, "bgez", "s,p", sreg);
6306 macro_build (NULL, "nop", "");
6308 move_register (dreg, sreg);
6309 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6310 if (mips_opts.micromips)
6311 micromips_add_label ();
6328 if (!mips_opts.micromips)
6330 if (imm_expr.X_op == O_constant
6331 && imm_expr.X_add_number >= -0x200
6332 && imm_expr.X_add_number < 0x200)
6334 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6343 if (imm_expr.X_op == O_constant
6344 && imm_expr.X_add_number >= -0x8000
6345 && imm_expr.X_add_number < 0x8000)
6347 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6352 load_register (AT, &imm_expr, dbl);
6353 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6372 if (imm_expr.X_op == O_constant
6373 && imm_expr.X_add_number >= 0
6374 && imm_expr.X_add_number < 0x10000)
6376 if (mask != M_NOR_I)
6377 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6380 macro_build (&imm_expr, "ori", "t,r,i",
6381 treg, sreg, BFD_RELOC_LO16);
6382 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6388 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6389 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6393 switch (imm_expr.X_add_number)
6396 macro_build (NULL, "nop", "");
6399 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6402 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6403 (int) imm_expr.X_add_number);
6412 gas_assert (mips_opts.micromips);
6413 macro_build_branch_ccl (mask, &offset_expr,
6414 EXTRACT_OPERAND (1, BCC, *ip));
6421 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6427 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6432 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6439 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6441 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6445 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6446 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6447 &offset_expr, AT, ZERO);
6457 macro_build_branch_rs (mask, &offset_expr, sreg);
6463 /* Check for > max integer. */
6464 maxnum = 0x7fffffff;
6465 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6472 if (imm_expr.X_op == O_constant
6473 && imm_expr.X_add_number >= maxnum
6474 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6477 /* Result is always false. */
6479 macro_build (NULL, "nop", "");
6481 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6484 if (imm_expr.X_op != O_constant)
6485 as_bad (_("Unsupported large constant"));
6486 ++imm_expr.X_add_number;
6490 if (mask == M_BGEL_I)
6492 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6494 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6495 &offset_expr, sreg);
6498 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6500 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6501 &offset_expr, sreg);
6504 maxnum = 0x7fffffff;
6505 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6512 maxnum = - maxnum - 1;
6513 if (imm_expr.X_op == O_constant
6514 && imm_expr.X_add_number <= maxnum
6515 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6518 /* result is always true */
6519 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6520 macro_build (&offset_expr, "b", "p");
6525 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6526 &offset_expr, AT, ZERO);
6535 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6536 &offset_expr, ZERO, treg);
6540 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6541 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6542 &offset_expr, AT, ZERO);
6551 && imm_expr.X_op == O_constant
6552 && imm_expr.X_add_number == -1))
6554 if (imm_expr.X_op != O_constant)
6555 as_bad (_("Unsupported large constant"));
6556 ++imm_expr.X_add_number;
6560 if (mask == M_BGEUL_I)
6562 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6564 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6565 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6566 &offset_expr, sreg, ZERO);
6571 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6572 &offset_expr, AT, ZERO);
6580 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6582 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6586 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6587 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6588 &offset_expr, AT, ZERO);
6596 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6597 &offset_expr, sreg, ZERO);
6603 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6604 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6605 &offset_expr, AT, ZERO);
6613 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6615 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6619 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6620 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6621 &offset_expr, AT, ZERO);
6628 maxnum = 0x7fffffff;
6629 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6636 if (imm_expr.X_op == O_constant
6637 && imm_expr.X_add_number >= maxnum
6638 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6640 if (imm_expr.X_op != O_constant)
6641 as_bad (_("Unsupported large constant"));
6642 ++imm_expr.X_add_number;
6646 if (mask == M_BLTL_I)
6648 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6649 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6650 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6651 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6656 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6657 &offset_expr, AT, ZERO);
6665 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6666 &offset_expr, sreg, ZERO);
6672 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6673 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6674 &offset_expr, AT, ZERO);
6683 && imm_expr.X_op == O_constant
6684 && imm_expr.X_add_number == -1))
6686 if (imm_expr.X_op != O_constant)
6687 as_bad (_("Unsupported large constant"));
6688 ++imm_expr.X_add_number;
6692 if (mask == M_BLTUL_I)
6694 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6696 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6697 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6698 &offset_expr, sreg, ZERO);
6703 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6704 &offset_expr, AT, ZERO);
6712 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6714 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6718 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6719 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6720 &offset_expr, AT, ZERO);
6730 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6731 &offset_expr, ZERO, treg);
6735 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6736 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6737 &offset_expr, AT, ZERO);
6743 /* Use unsigned arithmetic. */
6747 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6749 as_bad (_("Unsupported large constant"));
6754 pos = imm_expr.X_add_number;
6755 size = imm2_expr.X_add_number;
6760 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6763 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6765 as_bad (_("Improper extract size (%lu, position %lu)"),
6766 (unsigned long) size, (unsigned long) pos);
6770 if (size <= 32 && pos < 32)
6775 else if (size <= 32)
6785 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6792 /* Use unsigned arithmetic. */
6796 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6798 as_bad (_("Unsupported large constant"));
6803 pos = imm_expr.X_add_number;
6804 size = imm2_expr.X_add_number;
6809 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6812 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6814 as_bad (_("Improper insert size (%lu, position %lu)"),
6815 (unsigned long) size, (unsigned long) pos);
6819 if (pos < 32 && (pos + size - 1) < 32)
6834 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6835 (int) (pos + size - 1));
6851 as_warn (_("Divide by zero."));
6853 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6855 macro_build (NULL, "break", BRK_FMT, 7);
6862 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6863 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6867 if (mips_opts.micromips)
6868 micromips_label_expr (&label_expr);
6870 label_expr.X_add_number = 8;
6871 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6872 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6873 macro_build (NULL, "break", BRK_FMT, 7);
6874 if (mips_opts.micromips)
6875 micromips_add_label ();
6877 expr1.X_add_number = -1;
6879 load_register (AT, &expr1, dbl);
6880 if (mips_opts.micromips)
6881 micromips_label_expr (&label_expr);
6883 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6884 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6887 expr1.X_add_number = 1;
6888 load_register (AT, &expr1, dbl);
6889 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6893 expr1.X_add_number = 0x80000000;
6894 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6898 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6899 /* We want to close the noreorder block as soon as possible, so
6900 that later insns are available for delay slot filling. */
6905 if (mips_opts.micromips)
6906 micromips_label_expr (&label_expr);
6908 label_expr.X_add_number = 8;
6909 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6910 macro_build (NULL, "nop", "");
6912 /* We want to close the noreorder block as soon as possible, so
6913 that later insns are available for delay slot filling. */
6916 macro_build (NULL, "break", BRK_FMT, 6);
6918 if (mips_opts.micromips)
6919 micromips_add_label ();
6920 macro_build (NULL, s, MFHL_FMT, dreg);
6959 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6961 as_warn (_("Divide by zero."));
6963 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6965 macro_build (NULL, "break", BRK_FMT, 7);
6968 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6970 if (strcmp (s2, "mflo") == 0)
6971 move_register (dreg, sreg);
6973 move_register (dreg, ZERO);
6976 if (imm_expr.X_op == O_constant
6977 && imm_expr.X_add_number == -1
6978 && s[strlen (s) - 1] != 'u')
6980 if (strcmp (s2, "mflo") == 0)
6982 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
6985 move_register (dreg, ZERO);
6990 load_register (AT, &imm_expr, dbl);
6991 macro_build (NULL, s, "z,s,t", sreg, AT);
6992 macro_build (NULL, s2, MFHL_FMT, dreg);
7014 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7015 macro_build (NULL, s, "z,s,t", sreg, treg);
7016 /* We want to close the noreorder block as soon as possible, so
7017 that later insns are available for delay slot filling. */
7022 if (mips_opts.micromips)
7023 micromips_label_expr (&label_expr);
7025 label_expr.X_add_number = 8;
7026 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7027 macro_build (NULL, s, "z,s,t", sreg, treg);
7029 /* We want to close the noreorder block as soon as possible, so
7030 that later insns are available for delay slot filling. */
7032 macro_build (NULL, "break", BRK_FMT, 7);
7033 if (mips_opts.micromips)
7034 micromips_add_label ();
7036 macro_build (NULL, s2, MFHL_FMT, dreg);
7048 /* Load the address of a symbol into a register. If breg is not
7049 zero, we then add a base register to it. */
7051 if (dbl && HAVE_32BIT_GPRS)
7052 as_warn (_("dla used to load 32-bit register"));
7054 if (!dbl && HAVE_64BIT_OBJECTS)
7055 as_warn (_("la used to load 64-bit address"));
7057 if (offset_expr.X_op == O_constant
7058 && offset_expr.X_add_number >= -0x8000
7059 && offset_expr.X_add_number < 0x8000)
7061 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7062 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7066 if (mips_opts.at && (treg == breg))
7076 if (offset_expr.X_op != O_symbol
7077 && offset_expr.X_op != O_constant)
7079 as_bad (_("Expression too complex"));
7080 offset_expr.X_op = O_constant;
7083 if (offset_expr.X_op == O_constant)
7084 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7085 else if (mips_pic == NO_PIC)
7087 /* If this is a reference to a GP relative symbol, we want
7088 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7090 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7091 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7092 If we have a constant, we need two instructions anyhow,
7093 so we may as well always use the latter form.
7095 With 64bit address space and a usable $at we want
7096 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7097 lui $at,<sym> (BFD_RELOC_HI16_S)
7098 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7099 daddiu $at,<sym> (BFD_RELOC_LO16)
7101 daddu $tempreg,$tempreg,$at
7103 If $at is already in use, we use a path which is suboptimal
7104 on superscalar processors.
7105 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7106 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7108 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7110 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7112 For GP relative symbols in 64bit address space we can use
7113 the same sequence as in 32bit address space. */
7114 if (HAVE_64BIT_SYMBOLS)
7116 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7117 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7119 relax_start (offset_expr.X_add_symbol);
7120 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7121 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7125 if (used_at == 0 && mips_opts.at)
7127 macro_build (&offset_expr, "lui", LUI_FMT,
7128 tempreg, BFD_RELOC_MIPS_HIGHEST);
7129 macro_build (&offset_expr, "lui", LUI_FMT,
7130 AT, BFD_RELOC_HI16_S);
7131 macro_build (&offset_expr, "daddiu", "t,r,j",
7132 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7133 macro_build (&offset_expr, "daddiu", "t,r,j",
7134 AT, AT, BFD_RELOC_LO16);
7135 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7136 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7141 macro_build (&offset_expr, "lui", LUI_FMT,
7142 tempreg, BFD_RELOC_MIPS_HIGHEST);
7143 macro_build (&offset_expr, "daddiu", "t,r,j",
7144 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7145 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7146 macro_build (&offset_expr, "daddiu", "t,r,j",
7147 tempreg, tempreg, BFD_RELOC_HI16_S);
7148 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7149 macro_build (&offset_expr, "daddiu", "t,r,j",
7150 tempreg, tempreg, BFD_RELOC_LO16);
7153 if (mips_relax.sequence)
7158 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7159 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7161 relax_start (offset_expr.X_add_symbol);
7162 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7163 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7166 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7167 as_bad (_("Offset too large"));
7168 macro_build_lui (&offset_expr, tempreg);
7169 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7170 tempreg, tempreg, BFD_RELOC_LO16);
7171 if (mips_relax.sequence)
7175 else if (!mips_big_got && !HAVE_NEWABI)
7177 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7179 /* If this is a reference to an external symbol, and there
7180 is no constant, we want
7181 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7182 or for lca or if tempreg is PIC_CALL_REG
7183 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7184 For a local symbol, we want
7185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7187 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7189 If we have a small constant, and this is a reference to
7190 an external symbol, we want
7191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7193 addiu $tempreg,$tempreg,<constant>
7194 For a local symbol, we want the same instruction
7195 sequence, but we output a BFD_RELOC_LO16 reloc on the
7198 If we have a large constant, and this is a reference to
7199 an external symbol, we want
7200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7201 lui $at,<hiconstant>
7202 addiu $at,$at,<loconstant>
7203 addu $tempreg,$tempreg,$at
7204 For a local symbol, we want the same instruction
7205 sequence, but we output a BFD_RELOC_LO16 reloc on the
7209 if (offset_expr.X_add_number == 0)
7211 if (mips_pic == SVR4_PIC
7213 && (call || tempreg == PIC_CALL_REG))
7214 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7216 relax_start (offset_expr.X_add_symbol);
7217 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7218 lw_reloc_type, mips_gp_register);
7221 /* We're going to put in an addu instruction using
7222 tempreg, so we may as well insert the nop right
7227 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7228 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7230 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7231 tempreg, tempreg, BFD_RELOC_LO16);
7233 /* FIXME: If breg == 0, and the next instruction uses
7234 $tempreg, then if this variant case is used an extra
7235 nop will be generated. */
7237 else if (offset_expr.X_add_number >= -0x8000
7238 && offset_expr.X_add_number < 0x8000)
7240 load_got_offset (tempreg, &offset_expr);
7242 add_got_offset (tempreg, &offset_expr);
7246 expr1.X_add_number = offset_expr.X_add_number;
7247 offset_expr.X_add_number =
7248 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
7249 load_got_offset (tempreg, &offset_expr);
7250 offset_expr.X_add_number = expr1.X_add_number;
7251 /* If we are going to add in a base register, and the
7252 target register and the base register are the same,
7253 then we are using AT as a temporary register. Since
7254 we want to load the constant into AT, we add our
7255 current AT (from the global offset table) and the
7256 register into the register now, and pretend we were
7257 not using a base register. */
7261 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7266 add_got_offset_hilo (tempreg, &offset_expr, AT);
7270 else if (!mips_big_got && HAVE_NEWABI)
7272 int add_breg_early = 0;
7274 /* If this is a reference to an external, and there is no
7275 constant, or local symbol (*), with or without a
7277 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7278 or for lca or if tempreg is PIC_CALL_REG
7279 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7281 If we have a small constant, and this is a reference to
7282 an external symbol, we want
7283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7284 addiu $tempreg,$tempreg,<constant>
7286 If we have a large constant, and this is a reference to
7287 an external symbol, we want
7288 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7289 lui $at,<hiconstant>
7290 addiu $at,$at,<loconstant>
7291 addu $tempreg,$tempreg,$at
7293 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7294 local symbols, even though it introduces an additional
7297 if (offset_expr.X_add_number)
7299 expr1.X_add_number = offset_expr.X_add_number;
7300 offset_expr.X_add_number = 0;
7302 relax_start (offset_expr.X_add_symbol);
7303 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7304 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7306 if (expr1.X_add_number >= -0x8000
7307 && expr1.X_add_number < 0x8000)
7309 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7310 tempreg, tempreg, BFD_RELOC_LO16);
7312 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7314 /* If we are going to add in a base register, and the
7315 target register and the base register are the same,
7316 then we are using AT as a temporary register. Since
7317 we want to load the constant into AT, we add our
7318 current AT (from the global offset table) and the
7319 register into the register now, and pretend we were
7320 not using a base register. */
7325 gas_assert (tempreg == AT);
7326 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7332 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7333 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7339 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7342 offset_expr.X_add_number = expr1.X_add_number;
7344 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7345 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7349 treg, tempreg, breg);
7355 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7357 relax_start (offset_expr.X_add_symbol);
7358 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7359 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7361 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7362 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7367 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7368 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7371 else if (mips_big_got && !HAVE_NEWABI)
7374 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7375 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7376 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7378 /* This is the large GOT case. If this is a reference to an
7379 external symbol, and there is no constant, we want
7380 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7381 addu $tempreg,$tempreg,$gp
7382 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7383 or for lca or if tempreg is PIC_CALL_REG
7384 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7385 addu $tempreg,$tempreg,$gp
7386 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7387 For a local symbol, we want
7388 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7390 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7392 If we have a small constant, and this is a reference to
7393 an external symbol, we want
7394 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7395 addu $tempreg,$tempreg,$gp
7396 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7398 addiu $tempreg,$tempreg,<constant>
7399 For a local symbol, we want
7400 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7402 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7404 If we have a large constant, and this is a reference to
7405 an external symbol, we want
7406 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7407 addu $tempreg,$tempreg,$gp
7408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7409 lui $at,<hiconstant>
7410 addiu $at,$at,<loconstant>
7411 addu $tempreg,$tempreg,$at
7412 For a local symbol, we want
7413 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7414 lui $at,<hiconstant>
7415 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7416 addu $tempreg,$tempreg,$at
7419 expr1.X_add_number = offset_expr.X_add_number;
7420 offset_expr.X_add_number = 0;
7421 relax_start (offset_expr.X_add_symbol);
7422 gpdelay = reg_needs_delay (mips_gp_register);
7423 if (expr1.X_add_number == 0 && breg == 0
7424 && (call || tempreg == PIC_CALL_REG))
7426 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7427 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7429 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7430 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7431 tempreg, tempreg, mips_gp_register);
7432 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7433 tempreg, lw_reloc_type, tempreg);
7434 if (expr1.X_add_number == 0)
7438 /* We're going to put in an addu instruction using
7439 tempreg, so we may as well insert the nop right
7444 else if (expr1.X_add_number >= -0x8000
7445 && expr1.X_add_number < 0x8000)
7448 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7449 tempreg, tempreg, BFD_RELOC_LO16);
7453 /* If we are going to add in a base register, and the
7454 target register and the base register are the same,
7455 then we are using AT as a temporary register. Since
7456 we want to load the constant into AT, we add our
7457 current AT (from the global offset table) and the
7458 register into the register now, and pretend we were
7459 not using a base register. */
7464 gas_assert (tempreg == AT);
7466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7471 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7472 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7476 offset_expr.X_add_number =
7477 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
7482 /* This is needed because this instruction uses $gp, but
7483 the first instruction on the main stream does not. */
7484 macro_build (NULL, "nop", "");
7487 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7488 local_reloc_type, mips_gp_register);
7489 if (expr1.X_add_number >= -0x8000
7490 && expr1.X_add_number < 0x8000)
7493 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7494 tempreg, tempreg, BFD_RELOC_LO16);
7495 /* FIXME: If add_number is 0, and there was no base
7496 register, the external symbol case ended with a load,
7497 so if the symbol turns out to not be external, and
7498 the next instruction uses tempreg, an unnecessary nop
7499 will be inserted. */
7505 /* We must add in the base register now, as in the
7506 external symbol case. */
7507 gas_assert (tempreg == AT);
7509 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7512 /* We set breg to 0 because we have arranged to add
7513 it in in both cases. */
7517 macro_build_lui (&expr1, AT);
7518 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7519 AT, AT, BFD_RELOC_LO16);
7520 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7521 tempreg, tempreg, AT);
7526 else if (mips_big_got && HAVE_NEWABI)
7528 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7529 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7530 int add_breg_early = 0;
7532 /* This is the large GOT case. If this is a reference to an
7533 external symbol, and there is no constant, we want
7534 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7535 add $tempreg,$tempreg,$gp
7536 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7537 or for lca or if tempreg is PIC_CALL_REG
7538 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7539 add $tempreg,$tempreg,$gp
7540 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7542 If we have a small constant, and this is a reference to
7543 an external symbol, we want
7544 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7545 add $tempreg,$tempreg,$gp
7546 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7547 addi $tempreg,$tempreg,<constant>
7549 If we have a large constant, and this is a reference to
7550 an external symbol, we want
7551 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7552 addu $tempreg,$tempreg,$gp
7553 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7554 lui $at,<hiconstant>
7555 addi $at,$at,<loconstant>
7556 add $tempreg,$tempreg,$at
7558 If we have NewABI, and we know it's a local symbol, we want
7559 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7560 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7561 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7563 relax_start (offset_expr.X_add_symbol);
7565 expr1.X_add_number = offset_expr.X_add_number;
7566 offset_expr.X_add_number = 0;
7568 if (expr1.X_add_number == 0 && breg == 0
7569 && (call || tempreg == PIC_CALL_REG))
7571 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7572 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7574 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7575 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7576 tempreg, tempreg, mips_gp_register);
7577 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7578 tempreg, lw_reloc_type, tempreg);
7580 if (expr1.X_add_number == 0)
7582 else if (expr1.X_add_number >= -0x8000
7583 && expr1.X_add_number < 0x8000)
7585 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7586 tempreg, tempreg, BFD_RELOC_LO16);
7588 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7590 /* If we are going to add in a base register, and the
7591 target register and the base register are the same,
7592 then we are using AT as a temporary register. Since
7593 we want to load the constant into AT, we add our
7594 current AT (from the global offset table) and the
7595 register into the register now, and pretend we were
7596 not using a base register. */
7601 gas_assert (tempreg == AT);
7602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7608 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7609 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7614 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7617 offset_expr.X_add_number = expr1.X_add_number;
7618 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7619 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7620 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7621 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7625 treg, tempreg, breg);
7635 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7639 gas_assert (!mips_opts.micromips);
7641 unsigned long temp = (treg << 16) | (0x01);
7642 macro_build (NULL, "c2", "C", temp);
7647 gas_assert (!mips_opts.micromips);
7649 unsigned long temp = (0x02);
7650 macro_build (NULL, "c2", "C", temp);
7655 gas_assert (!mips_opts.micromips);
7657 unsigned long temp = (treg << 16) | (0x02);
7658 macro_build (NULL, "c2", "C", temp);
7663 gas_assert (!mips_opts.micromips);
7664 macro_build (NULL, "c2", "C", 3);
7668 gas_assert (!mips_opts.micromips);
7670 unsigned long temp = (treg << 16) | 0x03;
7671 macro_build (NULL, "c2", "C", temp);
7676 /* The j instruction may not be used in PIC code, since it
7677 requires an absolute address. We convert it to a b
7679 if (mips_pic == NO_PIC)
7680 macro_build (&offset_expr, "j", "a");
7682 macro_build (&offset_expr, "b", "p");
7685 /* The jal instructions must be handled as macros because when
7686 generating PIC code they expand to multi-instruction
7687 sequences. Normally they are simple instructions. */
7692 gas_assert (mips_opts.micromips);
7700 if (mips_pic == NO_PIC)
7702 s = jals ? "jalrs" : "jalr";
7703 if (mips_opts.micromips && dreg == RA)
7704 macro_build (NULL, s, "mj", sreg);
7706 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7710 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7711 && mips_cprestore_offset >= 0);
7713 if (sreg != PIC_CALL_REG)
7714 as_warn (_("MIPS PIC call to register other than $25"));
7716 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7717 ? "jalrs" : "jalr");
7718 if (mips_opts.micromips && dreg == RA)
7719 macro_build (NULL, s, "mj", sreg);
7721 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7722 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7724 if (mips_cprestore_offset < 0)
7725 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7728 if (!mips_frame_reg_valid)
7730 as_warn (_("No .frame pseudo-op used in PIC code"));
7731 /* Quiet this warning. */
7732 mips_frame_reg_valid = 1;
7734 if (!mips_cprestore_valid)
7736 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7737 /* Quiet this warning. */
7738 mips_cprestore_valid = 1;
7740 if (mips_opts.noreorder)
7741 macro_build (NULL, "nop", "");
7742 expr1.X_add_number = mips_cprestore_offset;
7743 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7746 HAVE_64BIT_ADDRESSES);
7754 gas_assert (mips_opts.micromips);
7758 if (mips_pic == NO_PIC)
7759 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7760 else if (mips_pic == SVR4_PIC)
7762 /* If this is a reference to an external symbol, and we are
7763 using a small GOT, we want
7764 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7768 lw $gp,cprestore($sp)
7769 The cprestore value is set using the .cprestore
7770 pseudo-op. If we are using a big GOT, we want
7771 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7773 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7777 lw $gp,cprestore($sp)
7778 If the symbol is not external, we want
7779 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7781 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7784 lw $gp,cprestore($sp)
7786 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7787 sequences above, minus nops, unless the symbol is local,
7788 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7794 relax_start (offset_expr.X_add_symbol);
7795 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7796 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7799 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7800 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7806 relax_start (offset_expr.X_add_symbol);
7807 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7808 BFD_RELOC_MIPS_CALL_HI16);
7809 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7810 PIC_CALL_REG, mips_gp_register);
7811 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7812 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7815 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7816 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7818 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7819 PIC_CALL_REG, PIC_CALL_REG,
7820 BFD_RELOC_MIPS_GOT_OFST);
7824 macro_build_jalr (&offset_expr, 0);
7828 relax_start (offset_expr.X_add_symbol);
7831 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7832 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7841 gpdelay = reg_needs_delay (mips_gp_register);
7842 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7843 BFD_RELOC_MIPS_CALL_HI16);
7844 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7845 PIC_CALL_REG, mips_gp_register);
7846 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7847 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7852 macro_build (NULL, "nop", "");
7854 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7855 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7858 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7859 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7861 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7863 if (mips_cprestore_offset < 0)
7864 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7867 if (!mips_frame_reg_valid)
7869 as_warn (_("No .frame pseudo-op used in PIC code"));
7870 /* Quiet this warning. */
7871 mips_frame_reg_valid = 1;
7873 if (!mips_cprestore_valid)
7875 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7876 /* Quiet this warning. */
7877 mips_cprestore_valid = 1;
7879 if (mips_opts.noreorder)
7880 macro_build (NULL, "nop", "");
7881 expr1.X_add_number = mips_cprestore_offset;
7882 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7885 HAVE_64BIT_ADDRESSES);
7889 else if (mips_pic == VXWORKS_PIC)
7890 as_bad (_("Non-PIC jump used in PIC library"));
7900 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7908 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7939 gas_assert (!mips_opts.micromips);
7942 /* Itbl support may require additional care here. */
7949 /* Itbl support may require additional care here. */
7957 off12 = mips_opts.micromips;
7958 /* Itbl support may require additional care here. */
7963 gas_assert (!mips_opts.micromips);
7966 /* Itbl support may require additional care here. */
7974 off12 = mips_opts.micromips;
7981 off12 = mips_opts.micromips;
7987 /* Itbl support may require additional care here. */
7995 off12 = mips_opts.micromips;
7996 /* Itbl support may require additional care here. */
8003 /* Itbl support may require additional care here. */
8011 off12 = mips_opts.micromips;
8018 off12 = mips_opts.micromips;
8025 off12 = mips_opts.micromips;
8032 off12 = mips_opts.micromips;
8039 off12 = mips_opts.micromips;
8044 gas_assert (mips_opts.micromips);
8053 gas_assert (mips_opts.micromips);
8062 gas_assert (mips_opts.micromips);
8070 gas_assert (mips_opts.micromips);
8077 if (breg == treg + lp)
8080 tempreg = treg + lp;
8100 gas_assert (!mips_opts.micromips);
8103 /* Itbl support may require additional care here. */
8110 /* Itbl support may require additional care here. */
8118 off12 = mips_opts.micromips;
8119 /* Itbl support may require additional care here. */
8124 gas_assert (!mips_opts.micromips);
8127 /* Itbl support may require additional care here. */
8135 off12 = mips_opts.micromips;
8142 off12 = mips_opts.micromips;
8149 off12 = mips_opts.micromips;
8156 off12 = mips_opts.micromips;
8162 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8163 off12 = mips_opts.micromips;
8169 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8170 off12 = mips_opts.micromips;
8177 /* Itbl support may require additional care here. */
8184 off12 = mips_opts.micromips;
8185 /* Itbl support may require additional care here. */
8190 gas_assert (!mips_opts.micromips);
8193 /* Itbl support may require additional care here. */
8201 off12 = mips_opts.micromips;
8208 off12 = mips_opts.micromips;
8213 gas_assert (mips_opts.micromips);
8221 gas_assert (mips_opts.micromips);
8229 gas_assert (mips_opts.micromips);
8237 gas_assert (mips_opts.micromips);
8247 && NO_ISA_COP (mips_opts.arch)
8248 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
8250 as_bad (_("Opcode not supported on this processor: %s"),
8251 mips_cpu_info_from_arch (mips_opts.arch)->name);
8255 if (offset_expr.X_op != O_constant
8256 && offset_expr.X_op != O_symbol)
8258 as_bad (_("Expression too complex"));
8259 offset_expr.X_op = O_constant;
8262 if (HAVE_32BIT_ADDRESSES
8263 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8267 sprintf_vma (value, offset_expr.X_add_number);
8268 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8271 /* A constant expression in PIC code can be handled just as it
8272 is in non PIC code. */
8273 if (offset_expr.X_op == O_constant)
8277 expr1.X_add_number = offset_expr.X_add_number;
8278 normalize_address_expr (&expr1);
8279 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8281 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8282 & ~(bfd_vma) 0xffff);
8285 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8287 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8288 & ~(bfd_vma) 0xfff);
8293 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8295 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8296 tempreg, tempreg, breg);
8300 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8302 macro_build (NULL, s, fmt,
8303 treg, (unsigned long) offset_expr.X_add_number, breg);
8307 /* A 12-bit offset field is too narrow to be used for a low-part
8308 relocation, so load the whole address into the auxillary
8309 register. In the case of "A(b)" addresses, we first load
8310 absolute address "A" into the register and then add base
8311 register "b". In the case of "o(b)" addresses, we simply
8312 need to add 16-bit offset "o" to base register "b", and
8313 offset_reloc already contains the relocations associated
8317 load_address (tempreg, &offset_expr, &used_at);
8319 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8320 tempreg, tempreg, breg);
8323 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8325 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8326 expr1.X_add_number = 0;
8327 macro_build (NULL, s, fmt,
8328 treg, (unsigned long) expr1.X_add_number, tempreg);
8330 else if (mips_pic == NO_PIC)
8332 /* If this is a reference to a GP relative symbol, and there
8333 is no base register, we want
8334 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8335 Otherwise, if there is no base register, we want
8336 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8337 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8338 If we have a constant, we need two instructions anyhow,
8339 so we always use the latter form.
8341 If we have a base register, and this is a reference to a
8342 GP relative symbol, we want
8343 addu $tempreg,$breg,$gp
8344 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8346 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8347 addu $tempreg,$tempreg,$breg
8348 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8349 With a constant we always use the latter case.
8351 With 64bit address space and no base register and $at usable,
8353 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8354 lui $at,<sym> (BFD_RELOC_HI16_S)
8355 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8358 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8359 If we have a base register, we want
8360 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8361 lui $at,<sym> (BFD_RELOC_HI16_S)
8362 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8366 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8368 Without $at we can't generate the optimal path for superscalar
8369 processors here since this would require two temporary registers.
8370 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8371 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8373 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8375 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8376 If we have a base register, we want
8377 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8378 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8380 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8382 daddu $tempreg,$tempreg,$breg
8383 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8385 For GP relative symbols in 64bit address space we can use
8386 the same sequence as in 32bit address space. */
8387 if (HAVE_64BIT_SYMBOLS)
8389 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8390 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8392 relax_start (offset_expr.X_add_symbol);
8395 macro_build (&offset_expr, s, fmt, treg,
8396 BFD_RELOC_GPREL16, mips_gp_register);
8400 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8401 tempreg, breg, mips_gp_register);
8402 macro_build (&offset_expr, s, fmt, treg,
8403 BFD_RELOC_GPREL16, tempreg);
8408 if (used_at == 0 && mips_opts.at)
8410 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8411 BFD_RELOC_MIPS_HIGHEST);
8412 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8414 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8415 tempreg, BFD_RELOC_MIPS_HIGHER);
8417 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8418 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8419 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8420 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8426 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8427 BFD_RELOC_MIPS_HIGHEST);
8428 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8429 tempreg, BFD_RELOC_MIPS_HIGHER);
8430 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8431 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8432 tempreg, BFD_RELOC_HI16_S);
8433 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8435 macro_build (NULL, "daddu", "d,v,t",
8436 tempreg, tempreg, breg);
8437 macro_build (&offset_expr, s, fmt, treg,
8438 BFD_RELOC_LO16, tempreg);
8441 if (mips_relax.sequence)
8448 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8449 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8451 relax_start (offset_expr.X_add_symbol);
8452 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8456 macro_build_lui (&offset_expr, tempreg);
8457 macro_build (&offset_expr, s, fmt, treg,
8458 BFD_RELOC_LO16, tempreg);
8459 if (mips_relax.sequence)
8464 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8465 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8467 relax_start (offset_expr.X_add_symbol);
8468 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8469 tempreg, breg, mips_gp_register);
8470 macro_build (&offset_expr, s, fmt, treg,
8471 BFD_RELOC_GPREL16, tempreg);
8474 macro_build_lui (&offset_expr, tempreg);
8475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8476 tempreg, tempreg, breg);
8477 macro_build (&offset_expr, s, fmt, treg,
8478 BFD_RELOC_LO16, tempreg);
8479 if (mips_relax.sequence)
8483 else if (!mips_big_got)
8485 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8487 /* If this is a reference to an external symbol, we want
8488 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8490 <op> $treg,0($tempreg)
8492 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8494 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8495 <op> $treg,0($tempreg)
8498 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8499 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8501 If there is a base register, we add it to $tempreg before
8502 the <op>. If there is a constant, we stick it in the
8503 <op> instruction. We don't handle constants larger than
8504 16 bits, because we have no way to load the upper 16 bits
8505 (actually, we could handle them for the subset of cases
8506 in which we are not using $at). */
8507 gas_assert (offset_expr.X_op == O_symbol);
8510 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8511 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8513 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8514 tempreg, tempreg, breg);
8515 macro_build (&offset_expr, s, fmt, treg,
8516 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8519 expr1.X_add_number = offset_expr.X_add_number;
8520 offset_expr.X_add_number = 0;
8521 if (expr1.X_add_number < -0x8000
8522 || expr1.X_add_number >= 0x8000)
8523 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8524 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8525 lw_reloc_type, mips_gp_register);
8527 relax_start (offset_expr.X_add_symbol);
8529 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8530 tempreg, BFD_RELOC_LO16);
8533 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8534 tempreg, tempreg, breg);
8535 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8537 else if (mips_big_got && !HAVE_NEWABI)
8541 /* If this is a reference to an external symbol, we want
8542 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8543 addu $tempreg,$tempreg,$gp
8544 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8545 <op> $treg,0($tempreg)
8547 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8549 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8550 <op> $treg,0($tempreg)
8551 If there is a base register, we add it to $tempreg before
8552 the <op>. If there is a constant, we stick it in the
8553 <op> instruction. We don't handle constants larger than
8554 16 bits, because we have no way to load the upper 16 bits
8555 (actually, we could handle them for the subset of cases
8556 in which we are not using $at). */
8557 gas_assert (offset_expr.X_op == O_symbol);
8558 expr1.X_add_number = offset_expr.X_add_number;
8559 offset_expr.X_add_number = 0;
8560 if (expr1.X_add_number < -0x8000
8561 || expr1.X_add_number >= 0x8000)
8562 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8563 gpdelay = reg_needs_delay (mips_gp_register);
8564 relax_start (offset_expr.X_add_symbol);
8565 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8566 BFD_RELOC_MIPS_GOT_HI16);
8567 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8569 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8570 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8573 macro_build (NULL, "nop", "");
8574 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8575 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8577 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8578 tempreg, BFD_RELOC_LO16);
8582 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8583 tempreg, tempreg, breg);
8584 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8586 else if (mips_big_got && HAVE_NEWABI)
8588 /* If this is a reference to an external symbol, we want
8589 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8590 add $tempreg,$tempreg,$gp
8591 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8592 <op> $treg,<ofst>($tempreg)
8593 Otherwise, for local symbols, we want:
8594 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8595 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8596 gas_assert (offset_expr.X_op == O_symbol);
8597 expr1.X_add_number = offset_expr.X_add_number;
8598 offset_expr.X_add_number = 0;
8599 if (expr1.X_add_number < -0x8000
8600 || expr1.X_add_number >= 0x8000)
8601 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8602 relax_start (offset_expr.X_add_symbol);
8603 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8604 BFD_RELOC_MIPS_GOT_HI16);
8605 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8607 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8608 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8610 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8611 tempreg, tempreg, breg);
8612 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8615 offset_expr.X_add_number = expr1.X_add_number;
8616 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8617 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8620 tempreg, tempreg, breg);
8621 macro_build (&offset_expr, s, fmt, treg,
8622 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8632 load_register (treg, &imm_expr, 0);
8636 load_register (treg, &imm_expr, 1);
8640 if (imm_expr.X_op == O_constant)
8643 load_register (AT, &imm_expr, 0);
8644 macro_build (NULL, "mtc1", "t,G", AT, treg);
8649 gas_assert (offset_expr.X_op == O_symbol
8650 && strcmp (segment_name (S_GET_SEGMENT
8651 (offset_expr.X_add_symbol)),
8653 && offset_expr.X_add_number == 0);
8654 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8655 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8660 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8661 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8662 order 32 bits of the value and the low order 32 bits are either
8663 zero or in OFFSET_EXPR. */
8664 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8666 if (HAVE_64BIT_GPRS)
8667 load_register (treg, &imm_expr, 1);
8672 if (target_big_endian)
8684 load_register (hreg, &imm_expr, 0);
8687 if (offset_expr.X_op == O_absent)
8688 move_register (lreg, 0);
8691 gas_assert (offset_expr.X_op == O_constant);
8692 load_register (lreg, &offset_expr, 0);
8699 /* We know that sym is in the .rdata section. First we get the
8700 upper 16 bits of the address. */
8701 if (mips_pic == NO_PIC)
8703 macro_build_lui (&offset_expr, AT);
8708 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8709 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8713 /* Now we load the register(s). */
8714 if (HAVE_64BIT_GPRS)
8717 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8722 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8725 /* FIXME: How in the world do we deal with the possible
8727 offset_expr.X_add_number += 4;
8728 macro_build (&offset_expr, "lw", "t,o(b)",
8729 treg + 1, BFD_RELOC_LO16, AT);
8735 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8736 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8737 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8738 the value and the low order 32 bits are either zero or in
8740 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8743 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8744 if (HAVE_64BIT_FPRS)
8746 gas_assert (HAVE_64BIT_GPRS);
8747 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8751 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8752 if (offset_expr.X_op == O_absent)
8753 macro_build (NULL, "mtc1", "t,G", 0, treg);
8756 gas_assert (offset_expr.X_op == O_constant);
8757 load_register (AT, &offset_expr, 0);
8758 macro_build (NULL, "mtc1", "t,G", AT, treg);
8764 gas_assert (offset_expr.X_op == O_symbol
8765 && offset_expr.X_add_number == 0);
8766 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8767 if (strcmp (s, ".lit8") == 0)
8769 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8771 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8772 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8775 breg = mips_gp_register;
8776 r = BFD_RELOC_MIPS_LITERAL;
8781 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8783 if (mips_pic != NO_PIC)
8784 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8785 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8788 /* FIXME: This won't work for a 64 bit address. */
8789 macro_build_lui (&offset_expr, AT);
8792 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8794 macro_build (&offset_expr, "ldc1", "T,o(b)",
8795 treg, BFD_RELOC_LO16, AT);
8804 /* Even on a big endian machine $fn comes before $fn+1. We have
8805 to adjust when loading from memory. */
8808 gas_assert (!mips_opts.micromips);
8809 gas_assert (mips_opts.isa == ISA_MIPS1);
8810 macro_build (&offset_expr, "lwc1", "T,o(b)",
8811 target_big_endian ? treg + 1 : treg, r, breg);
8812 /* FIXME: A possible overflow which I don't know how to deal
8814 offset_expr.X_add_number += 4;
8815 macro_build (&offset_expr, "lwc1", "T,o(b)",
8816 target_big_endian ? treg : treg + 1, r, breg);
8820 gas_assert (!mips_opts.micromips);
8821 gas_assert (mips_opts.isa == ISA_MIPS1);
8822 /* Even on a big endian machine $fn comes before $fn+1. We have
8823 to adjust when storing to memory. */
8824 macro_build (&offset_expr, "swc1", "T,o(b)",
8825 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8826 offset_expr.X_add_number += 4;
8827 macro_build (&offset_expr, "swc1", "T,o(b)",
8828 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8832 gas_assert (!mips_opts.micromips);
8834 * The MIPS assembler seems to check for X_add_number not
8835 * being double aligned and generating:
8838 * addiu at,at,%lo(foo+1)
8841 * But, the resulting address is the same after relocation so why
8842 * generate the extra instruction?
8844 /* Itbl support may require additional care here. */
8847 if (mips_opts.isa != ISA_MIPS1)
8856 gas_assert (!mips_opts.micromips);
8857 /* Itbl support may require additional care here. */
8860 if (mips_opts.isa != ISA_MIPS1)
8870 if (HAVE_64BIT_GPRS)
8880 if (HAVE_64BIT_GPRS)
8888 if (offset_expr.X_op != O_symbol
8889 && offset_expr.X_op != O_constant)
8891 as_bad (_("Expression too complex"));
8892 offset_expr.X_op = O_constant;
8895 if (HAVE_32BIT_ADDRESSES
8896 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8900 sprintf_vma (value, offset_expr.X_add_number);
8901 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8904 /* Even on a big endian machine $fn comes before $fn+1. We have
8905 to adjust when loading from memory. We set coproc if we must
8906 load $fn+1 first. */
8907 /* Itbl support may require additional care here. */
8908 if (!target_big_endian)
8911 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
8913 /* If this is a reference to a GP relative symbol, we want
8914 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8915 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
8916 If we have a base register, we use this
8918 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
8919 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
8920 If this is not a GP relative symbol, we want
8921 lui $at,<sym> (BFD_RELOC_HI16_S)
8922 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8923 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8924 If there is a base register, we add it to $at after the
8925 lui instruction. If there is a constant, we always use
8927 if (offset_expr.X_op == O_symbol
8928 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8929 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8931 relax_start (offset_expr.X_add_symbol);
8934 tempreg = mips_gp_register;
8938 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8939 AT, breg, mips_gp_register);
8944 /* Itbl support may require additional care here. */
8945 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8946 BFD_RELOC_GPREL16, tempreg);
8947 offset_expr.X_add_number += 4;
8949 /* Set mips_optimize to 2 to avoid inserting an
8951 hold_mips_optimize = mips_optimize;
8953 /* Itbl support may require additional care here. */
8954 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8955 BFD_RELOC_GPREL16, tempreg);
8956 mips_optimize = hold_mips_optimize;
8960 offset_expr.X_add_number -= 4;
8963 macro_build_lui (&offset_expr, AT);
8965 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
8966 /* Itbl support may require additional care here. */
8967 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
8968 BFD_RELOC_LO16, AT);
8969 /* FIXME: How do we handle overflow here? */
8970 offset_expr.X_add_number += 4;
8971 /* Itbl support may require additional care here. */
8972 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
8973 BFD_RELOC_LO16, AT);
8974 if (mips_relax.sequence)
8977 else if (!mips_big_got)
8979 /* If this is a reference to an external symbol, we want
8980 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8985 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8987 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
8988 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
8989 If there is a base register we add it to $at before the
8990 lwc1 instructions. If there is a constant we include it
8991 in the lwc1 instructions. */
8993 expr1.X_add_number = offset_expr.X_add_number;
8994 if (expr1.X_add_number < -0x8000
8995 || expr1.X_add_number >= 0x8000 - 4)
8996 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8997 load_got_offset (AT, &offset_expr);
9000 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9002 /* Set mips_optimize to 2 to avoid inserting an undesired
9004 hold_mips_optimize = mips_optimize;
9007 /* Itbl support may require additional care here. */
9008 relax_start (offset_expr.X_add_symbol);
9009 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9010 BFD_RELOC_LO16, AT);
9011 expr1.X_add_number += 4;
9012 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9013 BFD_RELOC_LO16, AT);
9015 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9016 BFD_RELOC_LO16, AT);
9017 offset_expr.X_add_number += 4;
9018 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9019 BFD_RELOC_LO16, AT);
9022 mips_optimize = hold_mips_optimize;
9024 else if (mips_big_got)
9028 /* If this is a reference to an external symbol, we want
9029 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9031 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9036 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9038 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9039 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9040 If there is a base register we add it to $at before the
9041 lwc1 instructions. If there is a constant we include it
9042 in the lwc1 instructions. */
9044 expr1.X_add_number = offset_expr.X_add_number;
9045 offset_expr.X_add_number = 0;
9046 if (expr1.X_add_number < -0x8000
9047 || expr1.X_add_number >= 0x8000 - 4)
9048 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9049 gpdelay = reg_needs_delay (mips_gp_register);
9050 relax_start (offset_expr.X_add_symbol);
9051 macro_build (&offset_expr, "lui", LUI_FMT,
9052 AT, BFD_RELOC_MIPS_GOT_HI16);
9053 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9054 AT, AT, mips_gp_register);
9055 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9056 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9059 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9060 /* Itbl support may require additional care here. */
9061 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9062 BFD_RELOC_LO16, AT);
9063 expr1.X_add_number += 4;
9065 /* Set mips_optimize to 2 to avoid inserting an undesired
9067 hold_mips_optimize = mips_optimize;
9069 /* Itbl support may require additional care here. */
9070 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9071 BFD_RELOC_LO16, AT);
9072 mips_optimize = hold_mips_optimize;
9073 expr1.X_add_number -= 4;
9076 offset_expr.X_add_number = expr1.X_add_number;
9078 macro_build (NULL, "nop", "");
9079 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9080 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9084 /* Itbl support may require additional care here. */
9085 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9086 BFD_RELOC_LO16, AT);
9087 offset_expr.X_add_number += 4;
9089 /* Set mips_optimize to 2 to avoid inserting an undesired
9091 hold_mips_optimize = mips_optimize;
9093 /* Itbl support may require additional care here. */
9094 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9095 BFD_RELOC_LO16, AT);
9096 mips_optimize = hold_mips_optimize;
9105 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9108 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9110 macro_build (&offset_expr, s, "t,o(b)", treg,
9111 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9113 if (!HAVE_64BIT_GPRS)
9115 offset_expr.X_add_number += 4;
9116 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9117 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9122 /* New code added to support COPZ instructions.
9123 This code builds table entries out of the macros in mip_opcodes.
9124 R4000 uses interlocks to handle coproc delays.
9125 Other chips (like the R3000) require nops to be inserted for delays.
9127 FIXME: Currently, we require that the user handle delays.
9128 In order to fill delay slots for non-interlocked chips,
9129 we must have a way to specify delays based on the coprocessor.
9130 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9131 What are the side-effects of the cop instruction?
9132 What cache support might we have and what are its effects?
9133 Both coprocessor & memory require delays. how long???
9134 What registers are read/set/modified?
9136 If an itbl is provided to interpret cop instructions,
9137 this knowledge can be encoded in the itbl spec. */
9151 gas_assert (!mips_opts.micromips);
9152 if (NO_ISA_COP (mips_opts.arch)
9153 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
9155 as_bad (_("opcode not supported on this processor: %s"),
9156 mips_cpu_info_from_arch (mips_opts.arch)->name);
9160 /* For now we just do C (same as Cz). The parameter will be
9161 stored in insn_opcode by mips_ip. */
9162 macro_build (NULL, s, "C", ip->insn_opcode);
9166 move_register (dreg, sreg);
9172 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9173 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9179 /* The MIPS assembler some times generates shifts and adds. I'm
9180 not trying to be that fancy. GCC should do this for us
9183 load_register (AT, &imm_expr, dbl);
9184 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9185 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9201 load_register (AT, &imm_expr, dbl);
9202 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9203 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9204 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9205 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9207 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9210 if (mips_opts.micromips)
9211 micromips_label_expr (&label_expr);
9213 label_expr.X_add_number = 8;
9214 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9215 macro_build (NULL, "nop", "");
9216 macro_build (NULL, "break", BRK_FMT, 6);
9217 if (mips_opts.micromips)
9218 micromips_add_label ();
9221 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9237 load_register (AT, &imm_expr, dbl);
9238 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9239 sreg, imm ? AT : treg);
9240 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9241 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9243 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9246 if (mips_opts.micromips)
9247 micromips_label_expr (&label_expr);
9249 label_expr.X_add_number = 8;
9250 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9251 macro_build (NULL, "nop", "");
9252 macro_build (NULL, "break", BRK_FMT, 6);
9253 if (mips_opts.micromips)
9254 micromips_add_label ();
9260 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9271 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9272 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9276 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9277 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9278 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9279 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9283 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9294 macro_build (NULL, "negu", "d,w", tempreg, treg);
9295 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9299 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9300 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9301 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9302 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9311 if (imm_expr.X_op != O_constant)
9312 as_bad (_("Improper rotate count"));
9313 rot = imm_expr.X_add_number & 0x3f;
9314 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9316 rot = (64 - rot) & 0x3f;
9318 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9320 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9325 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9328 l = (rot < 0x20) ? "dsll" : "dsll32";
9329 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9332 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9333 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9334 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9342 if (imm_expr.X_op != O_constant)
9343 as_bad (_("Improper rotate count"));
9344 rot = imm_expr.X_add_number & 0x1f;
9345 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9347 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9352 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9356 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9357 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9358 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9363 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9365 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9369 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9370 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9371 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9372 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9376 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9378 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9382 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9383 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9384 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9385 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9394 if (imm_expr.X_op != O_constant)
9395 as_bad (_("Improper rotate count"));
9396 rot = imm_expr.X_add_number & 0x3f;
9397 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9400 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9402 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9407 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9410 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9411 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9414 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9415 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9416 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9424 if (imm_expr.X_op != O_constant)
9425 as_bad (_("Improper rotate count"));
9426 rot = imm_expr.X_add_number & 0x1f;
9427 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9429 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9434 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9438 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9439 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9440 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9446 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9448 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9451 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9452 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9457 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9459 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9464 as_warn (_("Instruction %s: result is always false"),
9466 move_register (dreg, 0);
9469 if (CPU_HAS_SEQ (mips_opts.arch)
9470 && -512 <= imm_expr.X_add_number
9471 && imm_expr.X_add_number < 512)
9473 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9474 (int) imm_expr.X_add_number);
9477 if (imm_expr.X_op == O_constant
9478 && imm_expr.X_add_number >= 0
9479 && imm_expr.X_add_number < 0x10000)
9481 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9483 else if (imm_expr.X_op == O_constant
9484 && imm_expr.X_add_number > -0x8000
9485 && imm_expr.X_add_number < 0)
9487 imm_expr.X_add_number = -imm_expr.X_add_number;
9488 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9489 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9491 else if (CPU_HAS_SEQ (mips_opts.arch))
9494 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9495 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9500 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9501 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9504 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9507 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9513 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9514 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9517 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9519 if (imm_expr.X_op == O_constant
9520 && imm_expr.X_add_number >= -0x8000
9521 && imm_expr.X_add_number < 0x8000)
9523 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9524 dreg, sreg, BFD_RELOC_LO16);
9528 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9529 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9533 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9536 case M_SGT: /* sreg > treg <==> treg < sreg */
9542 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9545 case M_SGT_I: /* sreg > I <==> I < sreg */
9552 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9553 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9556 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9562 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9563 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9566 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9573 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9574 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9575 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9579 if (imm_expr.X_op == O_constant
9580 && imm_expr.X_add_number >= -0x8000
9581 && imm_expr.X_add_number < 0x8000)
9583 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9587 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9588 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9592 if (imm_expr.X_op == O_constant
9593 && imm_expr.X_add_number >= -0x8000
9594 && imm_expr.X_add_number < 0x8000)
9596 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9601 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9602 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9607 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9609 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9612 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9613 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9618 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9620 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9625 as_warn (_("Instruction %s: result is always true"),
9627 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9628 dreg, 0, BFD_RELOC_LO16);
9631 if (CPU_HAS_SEQ (mips_opts.arch)
9632 && -512 <= imm_expr.X_add_number
9633 && imm_expr.X_add_number < 512)
9635 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9636 (int) imm_expr.X_add_number);
9639 if (imm_expr.X_op == O_constant
9640 && imm_expr.X_add_number >= 0
9641 && imm_expr.X_add_number < 0x10000)
9643 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9645 else if (imm_expr.X_op == O_constant
9646 && imm_expr.X_add_number > -0x8000
9647 && imm_expr.X_add_number < 0)
9649 imm_expr.X_add_number = -imm_expr.X_add_number;
9650 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9651 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9653 else if (CPU_HAS_SEQ (mips_opts.arch))
9656 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9657 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9662 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9663 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9666 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9681 if (!mips_opts.micromips)
9683 if (imm_expr.X_op == O_constant
9684 && imm_expr.X_add_number > -0x200
9685 && imm_expr.X_add_number <= 0x200)
9687 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9696 if (imm_expr.X_op == O_constant
9697 && imm_expr.X_add_number > -0x8000
9698 && imm_expr.X_add_number <= 0x8000)
9700 imm_expr.X_add_number = -imm_expr.X_add_number;
9701 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9706 load_register (AT, &imm_expr, dbl);
9707 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9729 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9730 macro_build (NULL, s, "s,t", sreg, AT);
9735 gas_assert (!mips_opts.micromips);
9736 gas_assert (mips_opts.isa == ISA_MIPS1);
9738 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9739 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9742 * Is the double cfc1 instruction a bug in the mips assembler;
9743 * or is there a reason for it?
9746 macro_build (NULL, "cfc1", "t,G", treg, RA);
9747 macro_build (NULL, "cfc1", "t,G", treg, RA);
9748 macro_build (NULL, "nop", "");
9749 expr1.X_add_number = 3;
9750 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9751 expr1.X_add_number = 2;
9752 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9753 macro_build (NULL, "ctc1", "t,G", AT, RA);
9754 macro_build (NULL, "nop", "");
9755 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9757 macro_build (NULL, "ctc1", "t,G", treg, RA);
9758 macro_build (NULL, "nop", "");
9781 off12 = mips_opts.micromips;
9789 off12 = mips_opts.micromips;
9805 off12 = mips_opts.micromips;
9814 off12 = mips_opts.micromips;
9819 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9820 as_bad (_("Operand overflow"));
9823 expr1.X_add_number = 0;
9828 load_address (tempreg, ep, &used_at);
9830 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9831 tempreg, tempreg, breg);
9837 && (offset_expr.X_op != O_constant
9838 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9839 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9843 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9844 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9849 else if (!ust && treg == breg)
9860 if (!target_big_endian)
9861 ep->X_add_number += off;
9863 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9865 macro_build (NULL, s, "t,~(b)",
9866 tempreg, (unsigned long) ep->X_add_number, breg);
9868 if (!target_big_endian)
9869 ep->X_add_number -= off;
9871 ep->X_add_number += off;
9873 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9875 macro_build (NULL, s2, "t,~(b)",
9876 tempreg, (unsigned long) ep->X_add_number, breg);
9878 /* If necessary, move the result in tempreg to the final destination. */
9879 if (!ust && treg != tempreg)
9881 /* Protect second load's delay slot. */
9883 move_register (treg, tempreg);
9889 if (target_big_endian == ust)
9890 ep->X_add_number += off;
9891 tempreg = ust || ab ? treg : AT;
9892 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9894 /* For halfword transfers we need a temporary register to shuffle
9895 bytes. Unfortunately for M_USH_A we have none available before
9896 the next store as AT holds the base address. We deal with this
9897 case by clobbering TREG and then restoring it as with ULH. */
9898 tempreg = ust == ab ? treg : AT;
9900 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
9902 if (target_big_endian == ust)
9903 ep->X_add_number -= off;
9905 ep->X_add_number += off;
9906 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9908 /* For M_USH_A re-retrieve the LSB. */
9911 if (target_big_endian)
9912 ep->X_add_number += off;
9914 ep->X_add_number -= off;
9915 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
9917 /* For ULH and M_USH_A OR the LSB in. */
9920 tempreg = !ab ? AT : treg;
9921 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
9922 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
9927 /* FIXME: Check if this is one of the itbl macros, since they
9928 are added dynamically. */
9929 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
9932 if (!mips_opts.at && used_at)
9933 as_bad (_("Macro used $at after \".set noat\""));
9936 /* Implement macros in mips16 mode. */
9939 mips16_macro (struct mips_cl_insn *ip)
9942 int xreg, yreg, zreg, tmp;
9945 const char *s, *s2, *s3;
9947 mask = ip->insn_mo->mask;
9949 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
9950 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
9951 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
9953 expr1.X_op = O_constant;
9954 expr1.X_op_symbol = NULL;
9955 expr1.X_add_symbol = NULL;
9956 expr1.X_add_number = 1;
9976 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
9977 expr1.X_add_number = 2;
9978 macro_build (&expr1, "bnez", "x,p", yreg);
9979 macro_build (NULL, "break", "6", 7);
9981 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
9982 since that causes an overflow. We should do that as well,
9983 but I don't see how to do the comparisons without a temporary
9986 macro_build (NULL, s, "x", zreg);
10005 start_noreorder ();
10006 macro_build (NULL, s, "0,x,y", xreg, yreg);
10007 expr1.X_add_number = 2;
10008 macro_build (&expr1, "bnez", "x,p", yreg);
10009 macro_build (NULL, "break", "6", 7);
10011 macro_build (NULL, s2, "x", zreg);
10017 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10018 macro_build (NULL, "mflo", "x", zreg);
10026 if (imm_expr.X_op != O_constant)
10027 as_bad (_("Unsupported large constant"));
10028 imm_expr.X_add_number = -imm_expr.X_add_number;
10029 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10033 if (imm_expr.X_op != O_constant)
10034 as_bad (_("Unsupported large constant"));
10035 imm_expr.X_add_number = -imm_expr.X_add_number;
10036 macro_build (&imm_expr, "addiu", "x,k", xreg);
10040 if (imm_expr.X_op != O_constant)
10041 as_bad (_("Unsupported large constant"));
10042 imm_expr.X_add_number = -imm_expr.X_add_number;
10043 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10065 goto do_reverse_branch;
10069 goto do_reverse_branch;
10081 goto do_reverse_branch;
10092 macro_build (NULL, s, "x,y", xreg, yreg);
10093 macro_build (&offset_expr, s2, "p");
10120 goto do_addone_branch_i;
10125 goto do_addone_branch_i;
10140 goto do_addone_branch_i;
10146 do_addone_branch_i:
10147 if (imm_expr.X_op != O_constant)
10148 as_bad (_("Unsupported large constant"));
10149 ++imm_expr.X_add_number;
10152 macro_build (&imm_expr, s, s3, xreg);
10153 macro_build (&offset_expr, s2, "p");
10157 expr1.X_add_number = 0;
10158 macro_build (&expr1, "slti", "x,8", yreg);
10160 move_register (xreg, yreg);
10161 expr1.X_add_number = 2;
10162 macro_build (&expr1, "bteqz", "p");
10163 macro_build (NULL, "neg", "x,w", xreg, xreg);
10167 /* For consistency checking, verify that all bits are specified either
10168 by the match/mask part of the instruction definition, or by the
10171 validate_mips_insn (const struct mips_opcode *opc)
10173 const char *p = opc->args;
10175 unsigned long used_bits = opc->mask;
10177 if ((used_bits & opc->match) != opc->match)
10179 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10180 opc->name, opc->args);
10183 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10193 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10194 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10195 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10196 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10197 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10198 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10199 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10200 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10201 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10202 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10203 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10204 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10205 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10207 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10208 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10209 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10210 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10211 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10212 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10213 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10214 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10215 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10216 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10217 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10218 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10219 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10220 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10221 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10224 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10225 c, opc->name, opc->args);
10229 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10230 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10232 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10233 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10234 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10235 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10237 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10238 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10240 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10241 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10243 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10244 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10245 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10246 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10247 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10248 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10249 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10250 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10251 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10252 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10253 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10254 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10255 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10256 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10257 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10258 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10259 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10261 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10262 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10263 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10264 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10266 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10267 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10268 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10269 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10270 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10271 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10272 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10273 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10274 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10277 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10278 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10279 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10280 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10281 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10284 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10285 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10286 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10287 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10288 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10289 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10290 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10291 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10292 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10293 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10294 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10295 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10296 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10297 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10298 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10299 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10300 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10301 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10302 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10303 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10305 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10306 c, opc->name, opc->args);
10310 if (used_bits != 0xffffffff)
10312 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10313 ~used_bits & 0xffffffff, opc->name, opc->args);
10319 /* For consistency checking, verify that the length implied matches the
10320 major opcode and that all bits are specified either by the match/mask
10321 part of the instruction definition, or by the operand list. */
10324 validate_micromips_insn (const struct mips_opcode *opc)
10326 unsigned long match = opc->match;
10327 unsigned long mask = opc->mask;
10328 const char *p = opc->args;
10329 unsigned long insn_bits;
10330 unsigned long used_bits;
10331 unsigned long major;
10332 unsigned int length;
10336 if ((mask & match) != match)
10338 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10339 opc->name, opc->args);
10342 length = micromips_insn_length (opc);
10343 if (length != 2 && length != 4)
10345 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10346 "%s %s"), length, opc->name, opc->args);
10349 major = match >> (10 + 8 * (length - 2));
10350 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10351 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10353 as_bad (_("Internal error: bad microMIPS opcode "
10354 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10358 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10359 insn_bits = 1 << 4 * length;
10360 insn_bits <<= 4 * length;
10363 #define USE_BITS(field) \
10364 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10375 case 'A': USE_BITS (EXTLSB); break;
10376 case 'B': USE_BITS (INSMSB); break;
10377 case 'C': USE_BITS (EXTMSBD); break;
10378 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10379 case 'E': USE_BITS (EXTLSB); break;
10380 case 'F': USE_BITS (INSMSB); break;
10381 case 'G': USE_BITS (EXTMSBD); break;
10382 case 'H': USE_BITS (EXTMSBD); break;
10384 as_bad (_("Internal error: bad mips opcode "
10385 "(unknown extension operand type `%c%c'): %s %s"),
10386 e, c, opc->name, opc->args);
10394 case 'A': USE_BITS (IMMA); break;
10395 case 'B': USE_BITS (IMMB); break;
10396 case 'C': USE_BITS (IMMC); break;
10397 case 'D': USE_BITS (IMMD); break;
10398 case 'E': USE_BITS (IMME); break;
10399 case 'F': USE_BITS (IMMF); break;
10400 case 'G': USE_BITS (IMMG); break;
10401 case 'H': USE_BITS (IMMH); break;
10402 case 'I': USE_BITS (IMMI); break;
10403 case 'J': USE_BITS (IMMJ); break;
10404 case 'L': USE_BITS (IMML); break;
10405 case 'M': USE_BITS (IMMM); break;
10406 case 'N': USE_BITS (IMMN); break;
10407 case 'O': USE_BITS (IMMO); break;
10408 case 'P': USE_BITS (IMMP); break;
10409 case 'Q': USE_BITS (IMMQ); break;
10410 case 'U': USE_BITS (IMMU); break;
10411 case 'W': USE_BITS (IMMW); break;
10412 case 'X': USE_BITS (IMMX); break;
10413 case 'Y': USE_BITS (IMMY); break;
10416 case 'b': USE_BITS (MB); break;
10417 case 'c': USE_BITS (MC); break;
10418 case 'd': USE_BITS (MD); break;
10419 case 'e': USE_BITS (ME); break;
10420 case 'f': USE_BITS (MF); break;
10421 case 'g': USE_BITS (MG); break;
10422 case 'h': USE_BITS (MH); break;
10423 case 'i': USE_BITS (MI); break;
10424 case 'j': USE_BITS (MJ); break;
10425 case 'l': USE_BITS (ML); break;
10426 case 'm': USE_BITS (MM); break;
10427 case 'n': USE_BITS (MN); break;
10428 case 'p': USE_BITS (MP); break;
10429 case 'q': USE_BITS (MQ); break;
10437 as_bad (_("Internal error: bad mips opcode "
10438 "(unknown extension operand type `%c%c'): %s %s"),
10439 e, c, opc->name, opc->args);
10443 case '.': USE_BITS (OFFSET10); break;
10444 case '1': USE_BITS (STYPE); break;
10445 case '<': USE_BITS (SHAMT); break;
10446 case '>': USE_BITS (SHAMT); break;
10447 case 'B': USE_BITS (CODE10); break;
10448 case 'C': USE_BITS (COPZ); break;
10449 case 'D': USE_BITS (FD); break;
10450 case 'E': USE_BITS (RT); break;
10451 case 'G': USE_BITS (RS); break;
10452 case 'H': USE_BITS (SEL); break;
10453 case 'K': USE_BITS (RS); break;
10454 case 'M': USE_BITS (CCC); break;
10455 case 'N': USE_BITS (BCC); break;
10456 case 'R': USE_BITS (FR); break;
10457 case 'S': USE_BITS (FS); break;
10458 case 'T': USE_BITS (FT); break;
10459 case 'V': USE_BITS (FS); break;
10460 case '\\': USE_BITS (3BITPOS); break;
10461 case 'a': USE_BITS (TARGET); break;
10462 case 'b': USE_BITS (RS); break;
10463 case 'c': USE_BITS (CODE); break;
10464 case 'd': USE_BITS (RD); break;
10465 case 'h': USE_BITS (PREFX); break;
10466 case 'i': USE_BITS (IMMEDIATE); break;
10467 case 'j': USE_BITS (DELTA); break;
10468 case 'k': USE_BITS (CACHE); break;
10469 case 'n': USE_BITS (RT); break;
10470 case 'o': USE_BITS (DELTA); break;
10471 case 'p': USE_BITS (DELTA); break;
10472 case 'q': USE_BITS (CODE2); break;
10473 case 'r': USE_BITS (RS); break;
10474 case 's': USE_BITS (RS); break;
10475 case 't': USE_BITS (RT); break;
10476 case 'u': USE_BITS (IMMEDIATE); break;
10477 case 'v': USE_BITS (RS); break;
10478 case 'w': USE_BITS (RT); break;
10479 case 'y': USE_BITS (RS3); break;
10481 case '|': USE_BITS (TRAP); break;
10482 case '~': USE_BITS (OFFSET12); break;
10484 as_bad (_("Internal error: bad microMIPS opcode "
10485 "(unknown operand type `%c'): %s %s"),
10486 c, opc->name, opc->args);
10490 if (used_bits != insn_bits)
10492 if (~used_bits & insn_bits)
10493 as_bad (_("Internal error: bad microMIPS opcode "
10494 "(bits 0x%lx undefined): %s %s"),
10495 ~used_bits & insn_bits, opc->name, opc->args);
10496 if (used_bits & ~insn_bits)
10497 as_bad (_("Internal error: bad microMIPS opcode "
10498 "(bits 0x%lx defined): %s %s"),
10499 used_bits & ~insn_bits, opc->name, opc->args);
10505 /* UDI immediates. */
10506 struct mips_immed {
10508 unsigned int shift;
10509 unsigned long mask;
10513 static const struct mips_immed mips_immed[] = {
10514 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10515 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10516 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10517 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10521 /* Check whether an odd floating-point register is allowed. */
10523 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10525 const char *s = insn->name;
10527 if (insn->pinfo == INSN_MACRO)
10528 /* Let a macro pass, we'll catch it later when it is expanded. */
10531 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10533 /* Allow odd registers for single-precision ops. */
10534 switch (insn->pinfo & (FP_S | FP_D))
10538 return 1; /* both single precision - ok */
10540 return 0; /* both double precision - fail */
10545 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10546 s = strchr (insn->name, '.');
10548 s = s != NULL ? strchr (s + 1, '.') : NULL;
10549 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10552 /* Single-precision coprocessor loads and moves are OK too. */
10553 if ((insn->pinfo & FP_S)
10554 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10555 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10561 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10562 taking bits from BIT up. */
10564 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10566 return (ep->X_op == O_constant
10567 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10568 && ep->X_add_number >= min << bit
10569 && ep->X_add_number < max << bit);
10572 /* This routine assembles an instruction into its binary format. As a
10573 side effect, it sets one of the global variables imm_reloc or
10574 offset_reloc to the type of relocation to do if one of the operands
10575 is an address expression. */
10578 mips_ip (char *str, struct mips_cl_insn *ip)
10580 bfd_boolean wrong_delay_slot_insns = FALSE;
10581 bfd_boolean need_delay_slot_ok = TRUE;
10582 struct mips_opcode *firstinsn = NULL;
10583 const struct mips_opcode *past;
10584 struct hash_control *hash;
10588 struct mips_opcode *insn;
10590 unsigned int regno;
10591 unsigned int lastregno;
10592 unsigned int destregno = 0;
10593 unsigned int lastpos = 0;
10594 unsigned int limlo, limhi;
10596 offsetT min_range, max_range;
10600 unsigned int rtype;
10606 if (mips_opts.micromips)
10608 hash = micromips_op_hash;
10609 past = µmips_opcodes[bfd_micromips_num_opcodes];
10614 past = &mips_opcodes[NUMOPCODES];
10616 forced_insn_length = 0;
10619 /* We first try to match an instruction up to a space or to the end. */
10620 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10623 /* Make a copy of the instruction so that we can fiddle with it. */
10624 name = alloca (end + 1);
10625 memcpy (name, str, end);
10630 insn = (struct mips_opcode *) hash_find (hash, name);
10632 if (insn != NULL || !mips_opts.micromips)
10634 if (forced_insn_length)
10637 /* See if there's an instruction size override suffix,
10638 either `16' or `32', at the end of the mnemonic proper,
10639 that defines the operation, i.e. before the first `.'
10640 character if any. Strip it and retry. */
10641 dot = strchr (name, '.');
10642 opend = dot != NULL ? dot - name : end;
10645 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10646 forced_insn_length = 2;
10647 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10648 forced_insn_length = 4;
10651 memcpy (name + opend - 2, name + opend, end - opend + 1);
10655 insn_error = _("Unrecognized opcode");
10659 /* For microMIPS instructions placed in a fixed-length branch delay slot
10660 we make up to two passes over the relevant fragment of the opcode
10661 table. First we try instructions that meet the delay slot's length
10662 requirement. If none matched, then we retry with the remaining ones
10663 and if one matches, then we use it and then issue an appropriate
10664 warning later on. */
10665 argsStart = s = str + end;
10668 bfd_boolean delay_slot_ok;
10669 bfd_boolean size_ok;
10672 gas_assert (strcmp (insn->name, name) == 0);
10674 ok = is_opcode_valid (insn);
10675 size_ok = is_size_valid (insn);
10676 delay_slot_ok = is_delay_slot_valid (insn);
10677 if (!delay_slot_ok && !wrong_delay_slot_insns)
10680 wrong_delay_slot_insns = TRUE;
10682 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10684 static char buf[256];
10686 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10691 if (wrong_delay_slot_insns && need_delay_slot_ok)
10693 gas_assert (firstinsn);
10694 need_delay_slot_ok = FALSE;
10704 sprintf (buf, _("opcode not supported on this processor: %s (%s)"),
10705 mips_cpu_info_from_arch (mips_opts.arch)->name,
10706 mips_cpu_info_from_isa (mips_opts.isa)->name);
10708 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10709 8 * forced_insn_length);
10715 create_insn (ip, insn);
10718 lastregno = 0xffffffff;
10719 for (args = insn->args;; ++args)
10723 s += strspn (s, " \t");
10727 case '\0': /* end of args */
10732 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
10733 gas_assert (!mips_opts.micromips);
10734 my_getExpression (&imm_expr, s);
10735 check_absolute_expr (ip, &imm_expr);
10736 if ((unsigned long) imm_expr.X_add_number != 1
10737 && (unsigned long) imm_expr.X_add_number != 3)
10739 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10740 (unsigned long) imm_expr.X_add_number);
10742 INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number);
10743 imm_expr.X_op = O_absent;
10747 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
10748 gas_assert (!mips_opts.micromips);
10749 my_getExpression (&imm_expr, s);
10750 check_absolute_expr (ip, &imm_expr);
10751 if (imm_expr.X_add_number & ~OP_MASK_SA3)
10753 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10754 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
10756 INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number);
10757 imm_expr.X_op = O_absent;
10761 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
10762 gas_assert (!mips_opts.micromips);
10763 my_getExpression (&imm_expr, s);
10764 check_absolute_expr (ip, &imm_expr);
10765 if (imm_expr.X_add_number & ~OP_MASK_SA4)
10767 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10768 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
10770 INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number);
10771 imm_expr.X_op = O_absent;
10775 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
10776 gas_assert (!mips_opts.micromips);
10777 my_getExpression (&imm_expr, s);
10778 check_absolute_expr (ip, &imm_expr);
10779 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
10781 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10782 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
10784 INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number);
10785 imm_expr.X_op = O_absent;
10789 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
10790 gas_assert (!mips_opts.micromips);
10791 my_getExpression (&imm_expr, s);
10792 check_absolute_expr (ip, &imm_expr);
10793 if (imm_expr.X_add_number & ~OP_MASK_RS)
10795 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10796 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
10798 INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number);
10799 imm_expr.X_op = O_absent;
10803 case '7': /* Four DSP accumulators in bits 11,12. */
10804 gas_assert (!mips_opts.micromips);
10805 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10806 s[3] >= '0' && s[3] <= '3')
10808 regno = s[3] - '0';
10810 INSERT_OPERAND (0, DSPACC, *ip, regno);
10814 as_bad (_("Invalid dsp acc register"));
10817 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
10818 gas_assert (!mips_opts.micromips);
10819 my_getExpression (&imm_expr, s);
10820 check_absolute_expr (ip, &imm_expr);
10821 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
10823 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10825 (unsigned long) imm_expr.X_add_number);
10827 INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number);
10828 imm_expr.X_op = O_absent;
10832 case '9': /* Four DSP accumulators in bits 21,22. */
10833 gas_assert (!mips_opts.micromips);
10834 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10835 s[3] >= '0' && s[3] <= '3')
10837 regno = s[3] - '0';
10839 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10843 as_bad (_("Invalid dsp acc register"));
10846 case '0': /* DSP 6-bit signed immediate in bit 20. */
10847 gas_assert (!mips_opts.micromips);
10848 my_getExpression (&imm_expr, s);
10849 check_absolute_expr (ip, &imm_expr);
10850 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
10851 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
10852 if (imm_expr.X_add_number < min_range ||
10853 imm_expr.X_add_number > max_range)
10855 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10856 (long) min_range, (long) max_range,
10857 (long) imm_expr.X_add_number);
10859 INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number);
10860 imm_expr.X_op = O_absent;
10864 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
10865 gas_assert (!mips_opts.micromips);
10866 my_getExpression (&imm_expr, s);
10867 check_absolute_expr (ip, &imm_expr);
10868 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
10870 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
10872 (unsigned long) imm_expr.X_add_number);
10874 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
10875 imm_expr.X_op = O_absent;
10879 case ':': /* DSP 7-bit signed immediate in bit 19. */
10880 gas_assert (!mips_opts.micromips);
10881 my_getExpression (&imm_expr, s);
10882 check_absolute_expr (ip, &imm_expr);
10883 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
10884 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
10885 if (imm_expr.X_add_number < min_range ||
10886 imm_expr.X_add_number > max_range)
10888 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10889 (long) min_range, (long) max_range,
10890 (long) imm_expr.X_add_number);
10892 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
10893 imm_expr.X_op = O_absent;
10897 case '@': /* DSP 10-bit signed immediate in bit 16. */
10898 gas_assert (!mips_opts.micromips);
10899 my_getExpression (&imm_expr, s);
10900 check_absolute_expr (ip, &imm_expr);
10901 min_range = -((OP_MASK_IMM10 + 1) >> 1);
10902 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
10903 if (imm_expr.X_add_number < min_range ||
10904 imm_expr.X_add_number > max_range)
10906 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10907 (long) min_range, (long) max_range,
10908 (long) imm_expr.X_add_number);
10910 INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number);
10911 imm_expr.X_op = O_absent;
10915 case '!': /* MT usermode flag bit. */
10916 gas_assert (!mips_opts.micromips);
10917 my_getExpression (&imm_expr, s);
10918 check_absolute_expr (ip, &imm_expr);
10919 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
10920 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
10921 (unsigned long) imm_expr.X_add_number);
10922 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
10923 imm_expr.X_op = O_absent;
10927 case '$': /* MT load high flag bit. */
10928 gas_assert (!mips_opts.micromips);
10929 my_getExpression (&imm_expr, s);
10930 check_absolute_expr (ip, &imm_expr);
10931 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
10932 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
10933 (unsigned long) imm_expr.X_add_number);
10934 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
10935 imm_expr.X_op = O_absent;
10939 case '*': /* Four DSP accumulators in bits 18,19. */
10940 gas_assert (!mips_opts.micromips);
10941 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10942 s[3] >= '0' && s[3] <= '3')
10944 regno = s[3] - '0';
10946 INSERT_OPERAND (0, MTACC_T, *ip, regno);
10950 as_bad (_("Invalid dsp/smartmips acc register"));
10953 case '&': /* Four DSP accumulators in bits 13,14. */
10954 gas_assert (!mips_opts.micromips);
10955 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
10956 s[3] >= '0' && s[3] <= '3')
10958 regno = s[3] - '0';
10960 INSERT_OPERAND (0, MTACC_D, *ip, regno);
10964 as_bad (_("Invalid dsp/smartmips acc register"));
10967 case '\\': /* 3-bit bit position. */
10969 unsigned long mask = (!mips_opts.micromips
10971 : MICROMIPSOP_MASK_3BITPOS);
10973 my_getExpression (&imm_expr, s);
10974 check_absolute_expr (ip, &imm_expr);
10975 if ((unsigned long) imm_expr.X_add_number > mask)
10976 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
10978 mask, (unsigned long) imm_expr.X_add_number);
10979 INSERT_OPERAND (mips_opts.micromips,
10980 3BITPOS, *ip, imm_expr.X_add_number);
10981 imm_expr.X_op = O_absent;
10995 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
10999 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11003 gas_assert (!mips_opts.micromips);
11004 INSERT_OPERAND (0, FT, *ip, lastregno);
11008 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11014 /* Handle optional base register.
11015 Either the base register is omitted or
11016 we must have a left paren. */
11017 /* This is dependent on the next operand specifier
11018 is a base register specification. */
11019 gas_assert (args[1] == 'b'
11020 || (mips_opts.micromips
11022 && (args[2] == 'l' || args[2] == 'n'
11023 || args[2] == 's' || args[2] == 'a')));
11024 if (*s == '\0' && args[1] == 'b')
11026 /* Fall through. */
11028 case ')': /* These must match exactly. */
11033 case '[': /* These must match exactly. */
11035 gas_assert (!mips_opts.micromips);
11040 case '+': /* Opcode extension character. */
11043 case '1': /* UDI immediates. */
11047 gas_assert (!mips_opts.micromips);
11049 const struct mips_immed *imm = mips_immed;
11051 while (imm->type && imm->type != *args)
11055 my_getExpression (&imm_expr, s);
11056 check_absolute_expr (ip, &imm_expr);
11057 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11059 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11060 imm->desc ? imm->desc : ip->insn_mo->name,
11061 (unsigned long) imm_expr.X_add_number,
11062 (unsigned long) imm_expr.X_add_number);
11063 imm_expr.X_add_number &= imm->mask;
11065 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11067 imm_expr.X_op = O_absent;
11072 case 'A': /* ins/ext position, becomes LSB. */
11081 my_getExpression (&imm_expr, s);
11082 check_absolute_expr (ip, &imm_expr);
11083 if ((unsigned long) imm_expr.X_add_number < limlo
11084 || (unsigned long) imm_expr.X_add_number > limhi)
11086 as_bad (_("Improper position (%lu)"),
11087 (unsigned long) imm_expr.X_add_number);
11088 imm_expr.X_add_number = limlo;
11090 lastpos = imm_expr.X_add_number;
11091 INSERT_OPERAND (mips_opts.micromips,
11092 EXTLSB, *ip, imm_expr.X_add_number);
11093 imm_expr.X_op = O_absent;
11097 case 'B': /* ins size, becomes MSB. */
11106 my_getExpression (&imm_expr, s);
11107 check_absolute_expr (ip, &imm_expr);
11108 /* Check for negative input so that small negative numbers
11109 will not succeed incorrectly. The checks against
11110 (pos+size) transitively check "size" itself,
11111 assuming that "pos" is reasonable. */
11112 if ((long) imm_expr.X_add_number < 0
11113 || ((unsigned long) imm_expr.X_add_number
11115 || ((unsigned long) imm_expr.X_add_number
11116 + lastpos) > limhi)
11118 as_bad (_("Improper insert size (%lu, position %lu)"),
11119 (unsigned long) imm_expr.X_add_number,
11120 (unsigned long) lastpos);
11121 imm_expr.X_add_number = limlo - lastpos;
11123 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11124 lastpos + imm_expr.X_add_number - 1);
11125 imm_expr.X_op = O_absent;
11129 case 'C': /* ext size, becomes MSBD. */
11142 my_getExpression (&imm_expr, s);
11143 check_absolute_expr (ip, &imm_expr);
11144 /* Check for negative input so that small negative numbers
11145 will not succeed incorrectly. The checks against
11146 (pos+size) transitively check "size" itself,
11147 assuming that "pos" is reasonable. */
11148 if ((long) imm_expr.X_add_number < 0
11149 || ((unsigned long) imm_expr.X_add_number
11151 || ((unsigned long) imm_expr.X_add_number
11152 + lastpos) > limhi)
11154 as_bad (_("Improper extract size (%lu, position %lu)"),
11155 (unsigned long) imm_expr.X_add_number,
11156 (unsigned long) lastpos);
11157 imm_expr.X_add_number = limlo - lastpos;
11159 INSERT_OPERAND (mips_opts.micromips,
11160 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11161 imm_expr.X_op = O_absent;
11166 /* +D is for disassembly only; never match. */
11170 /* "+I" is like "I", except that imm2_expr is used. */
11171 my_getExpression (&imm2_expr, s);
11172 if (imm2_expr.X_op != O_big
11173 && imm2_expr.X_op != O_constant)
11174 insn_error = _("absolute expression required");
11175 if (HAVE_32BIT_GPRS)
11176 normalize_constant_expr (&imm2_expr);
11180 case 'T': /* Coprocessor register. */
11181 gas_assert (!mips_opts.micromips);
11182 /* +T is for disassembly only; never match. */
11185 case 't': /* Coprocessor register number. */
11186 gas_assert (!mips_opts.micromips);
11187 if (s[0] == '$' && ISDIGIT (s[1]))
11197 while (ISDIGIT (*s));
11199 as_bad (_("Invalid register number (%d)"), regno);
11202 INSERT_OPERAND (0, RT, *ip, regno);
11207 as_bad (_("Invalid coprocessor 0 register number"));
11211 /* bbit[01] and bbit[01]32 bit index. Give error if index
11212 is not in the valid range. */
11213 gas_assert (!mips_opts.micromips);
11214 my_getExpression (&imm_expr, s);
11215 check_absolute_expr (ip, &imm_expr);
11216 if ((unsigned) imm_expr.X_add_number > 31)
11218 as_bad (_("Improper bit index (%lu)"),
11219 (unsigned long) imm_expr.X_add_number);
11220 imm_expr.X_add_number = 0;
11222 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11223 imm_expr.X_op = O_absent;
11228 /* bbit[01] bit index when bbit is used but we generate
11229 bbit[01]32 because the index is over 32. Move to the
11230 next candidate if index is not in the valid range. */
11231 gas_assert (!mips_opts.micromips);
11232 my_getExpression (&imm_expr, s);
11233 check_absolute_expr (ip, &imm_expr);
11234 if ((unsigned) imm_expr.X_add_number < 32
11235 || (unsigned) imm_expr.X_add_number > 63)
11237 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11238 imm_expr.X_op = O_absent;
11243 /* cins, cins32, exts and exts32 position field. Give error
11244 if it's not in the valid range. */
11245 gas_assert (!mips_opts.micromips);
11246 my_getExpression (&imm_expr, s);
11247 check_absolute_expr (ip, &imm_expr);
11248 if ((unsigned) imm_expr.X_add_number > 31)
11250 as_bad (_("Improper position (%lu)"),
11251 (unsigned long) imm_expr.X_add_number);
11252 imm_expr.X_add_number = 0;
11254 /* Make the pos explicit to simplify +S. */
11255 lastpos = imm_expr.X_add_number + 32;
11256 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11257 imm_expr.X_op = O_absent;
11262 /* cins, cins32, exts and exts32 position field. Move to
11263 the next candidate if it's not in the valid range. */
11264 gas_assert (!mips_opts.micromips);
11265 my_getExpression (&imm_expr, s);
11266 check_absolute_expr (ip, &imm_expr);
11267 if ((unsigned) imm_expr.X_add_number < 32
11268 || (unsigned) imm_expr.X_add_number > 63)
11270 lastpos = imm_expr.X_add_number;
11271 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11272 imm_expr.X_op = O_absent;
11277 /* cins and exts length-minus-one field. */
11278 gas_assert (!mips_opts.micromips);
11279 my_getExpression (&imm_expr, s);
11280 check_absolute_expr (ip, &imm_expr);
11281 if ((unsigned long) imm_expr.X_add_number > 31)
11283 as_bad (_("Improper size (%lu)"),
11284 (unsigned long) imm_expr.X_add_number);
11285 imm_expr.X_add_number = 0;
11287 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11288 imm_expr.X_op = O_absent;
11293 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11294 length-minus-one field. */
11295 gas_assert (!mips_opts.micromips);
11296 my_getExpression (&imm_expr, s);
11297 check_absolute_expr (ip, &imm_expr);
11298 if ((long) imm_expr.X_add_number < 0
11299 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11301 as_bad (_("Improper size (%lu)"),
11302 (unsigned long) imm_expr.X_add_number);
11303 imm_expr.X_add_number = 0;
11305 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11306 imm_expr.X_op = O_absent;
11311 /* seqi/snei immediate field. */
11312 gas_assert (!mips_opts.micromips);
11313 my_getExpression (&imm_expr, s);
11314 check_absolute_expr (ip, &imm_expr);
11315 if ((long) imm_expr.X_add_number < -512
11316 || (long) imm_expr.X_add_number >= 512)
11318 as_bad (_("Improper immediate (%ld)"),
11319 (long) imm_expr.X_add_number);
11320 imm_expr.X_add_number = 0;
11322 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11323 imm_expr.X_op = O_absent;
11327 case 'a': /* 8-bit signed offset in bit 6 */
11328 gas_assert (!mips_opts.micromips);
11329 my_getExpression (&imm_expr, s);
11330 check_absolute_expr (ip, &imm_expr);
11331 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11332 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11333 if (imm_expr.X_add_number < min_range
11334 || imm_expr.X_add_number > max_range)
11336 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11337 (long) min_range, (long) max_range,
11338 (long) imm_expr.X_add_number);
11340 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11341 imm_expr.X_op = O_absent;
11345 case 'b': /* 8-bit signed offset in bit 3 */
11346 gas_assert (!mips_opts.micromips);
11347 my_getExpression (&imm_expr, s);
11348 check_absolute_expr (ip, &imm_expr);
11349 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11350 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11351 if (imm_expr.X_add_number < min_range
11352 || imm_expr.X_add_number > max_range)
11354 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11355 (long) min_range, (long) max_range,
11356 (long) imm_expr.X_add_number);
11358 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11359 imm_expr.X_op = O_absent;
11363 case 'c': /* 9-bit signed offset in bit 6 */
11364 gas_assert (!mips_opts.micromips);
11365 my_getExpression (&imm_expr, s);
11366 check_absolute_expr (ip, &imm_expr);
11367 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11368 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11369 /* We check the offset range before adjusted. */
11372 if (imm_expr.X_add_number < min_range
11373 || imm_expr.X_add_number > max_range)
11375 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11376 (long) min_range, (long) max_range,
11377 (long) imm_expr.X_add_number);
11379 if (imm_expr.X_add_number & 0xf)
11381 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11382 (long) imm_expr.X_add_number);
11384 /* Right shift 4 bits to adjust the offset operand. */
11385 INSERT_OPERAND (0, OFFSET_C, *ip,
11386 imm_expr.X_add_number >> 4);
11387 imm_expr.X_op = O_absent;
11392 gas_assert (!mips_opts.micromips);
11393 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11395 if (regno == AT && mips_opts.at)
11397 if (mips_opts.at == ATREG)
11398 as_warn (_("used $at without \".set noat\""));
11400 as_warn (_("used $%u with \".set at=$%u\""),
11401 regno, mips_opts.at);
11403 INSERT_OPERAND (0, RZ, *ip, regno);
11407 gas_assert (!mips_opts.micromips);
11408 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11410 INSERT_OPERAND (0, FZ, *ip, regno);
11414 as_bad (_("Internal error: bad %s opcode "
11415 "(unknown extension operand type `+%c'): %s %s"),
11416 mips_opts.micromips ? "microMIPS" : "MIPS",
11417 *args, insn->name, insn->args);
11418 /* Further processing is fruitless. */
11423 case '.': /* 10-bit offset. */
11424 gas_assert (mips_opts.micromips);
11425 case '~': /* 12-bit offset. */
11427 int shift = *args == '.' ? 9 : 11;
11430 /* Check whether there is only a single bracketed expression
11431 left. If so, it must be the base register and the
11432 constant must be zero. */
11433 if (*s == '(' && strchr (s + 1, '(') == 0)
11436 /* If this value won't fit into the offset, then go find
11437 a macro that will generate a 16- or 32-bit offset code
11439 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11440 if ((i == 0 && (imm_expr.X_op != O_constant
11441 || imm_expr.X_add_number >= 1 << shift
11442 || imm_expr.X_add_number < -1 << shift))
11445 imm_expr.X_op = O_absent;
11449 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11451 INSERT_OPERAND (mips_opts.micromips,
11452 OFFSET12, *ip, imm_expr.X_add_number);
11453 imm_expr.X_op = O_absent;
11458 case '<': /* must be at least one digit */
11460 * According to the manual, if the shift amount is greater
11461 * than 31 or less than 0, then the shift amount should be
11462 * mod 32. In reality the mips assembler issues an error.
11463 * We issue a warning and mask out all but the low 5 bits.
11465 my_getExpression (&imm_expr, s);
11466 check_absolute_expr (ip, &imm_expr);
11467 if ((unsigned long) imm_expr.X_add_number > 31)
11468 as_warn (_("Improper shift amount (%lu)"),
11469 (unsigned long) imm_expr.X_add_number);
11470 INSERT_OPERAND (mips_opts.micromips,
11471 SHAMT, *ip, imm_expr.X_add_number);
11472 imm_expr.X_op = O_absent;
11476 case '>': /* shift amount minus 32 */
11477 my_getExpression (&imm_expr, s);
11478 check_absolute_expr (ip, &imm_expr);
11479 if ((unsigned long) imm_expr.X_add_number < 32
11480 || (unsigned long) imm_expr.X_add_number > 63)
11482 INSERT_OPERAND (mips_opts.micromips,
11483 SHAMT, *ip, imm_expr.X_add_number - 32);
11484 imm_expr.X_op = O_absent;
11488 case 'k': /* CACHE code. */
11489 case 'h': /* PREFX code. */
11490 case '1': /* SYNC type. */
11491 my_getExpression (&imm_expr, s);
11492 check_absolute_expr (ip, &imm_expr);
11493 if ((unsigned long) imm_expr.X_add_number > 31)
11494 as_warn (_("Invalid value for `%s' (%lu)"),
11496 (unsigned long) imm_expr.X_add_number);
11500 if (mips_fix_cn63xxp1
11501 && !mips_opts.micromips
11502 && strcmp ("pref", insn->name) == 0)
11503 switch (imm_expr.X_add_number)
11512 case 31: /* These are ok. */
11515 default: /* The rest must be changed to 28. */
11516 imm_expr.X_add_number = 28;
11519 INSERT_OPERAND (mips_opts.micromips,
11520 CACHE, *ip, imm_expr.X_add_number);
11523 INSERT_OPERAND (mips_opts.micromips,
11524 PREFX, *ip, imm_expr.X_add_number);
11527 INSERT_OPERAND (mips_opts.micromips,
11528 STYPE, *ip, imm_expr.X_add_number);
11531 imm_expr.X_op = O_absent;
11535 case 'c': /* BREAK code. */
11537 unsigned long mask = (mips_opts.micromips
11538 ? MICROMIPSOP_MASK_CODE
11541 my_getExpression (&imm_expr, s);
11542 check_absolute_expr (ip, &imm_expr);
11543 if ((unsigned long) imm_expr.X_add_number > mask)
11544 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11546 mask, (unsigned long) imm_expr.X_add_number);
11547 INSERT_OPERAND (mips_opts.micromips,
11548 CODE, *ip, imm_expr.X_add_number);
11549 imm_expr.X_op = O_absent;
11554 case 'q': /* Lower BREAK code. */
11556 unsigned long mask = (mips_opts.micromips
11557 ? MICROMIPSOP_MASK_CODE2
11560 my_getExpression (&imm_expr, s);
11561 check_absolute_expr (ip, &imm_expr);
11562 if ((unsigned long) imm_expr.X_add_number > mask)
11563 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11565 mask, (unsigned long) imm_expr.X_add_number);
11566 INSERT_OPERAND (mips_opts.micromips,
11567 CODE2, *ip, imm_expr.X_add_number);
11568 imm_expr.X_op = O_absent;
11573 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11575 unsigned long mask = (mips_opts.micromips
11576 ? MICROMIPSOP_MASK_CODE10
11579 my_getExpression (&imm_expr, s);
11580 check_absolute_expr (ip, &imm_expr);
11581 if ((unsigned long) imm_expr.X_add_number > mask)
11582 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11584 mask, (unsigned long) imm_expr.X_add_number);
11585 if (mips_opts.micromips)
11586 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11588 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11589 imm_expr.X_op = O_absent;
11594 case 'C': /* 25- or 23-bit coprocessor code. */
11596 unsigned long mask = (mips_opts.micromips
11597 ? MICROMIPSOP_MASK_COPZ
11600 my_getExpression (&imm_expr, s);
11601 check_absolute_expr (ip, &imm_expr);
11602 if ((unsigned long) imm_expr.X_add_number > mask)
11603 as_warn (_("Coproccesor code > %u bits (%lu)"),
11604 mips_opts.micromips ? 23U : 25U,
11605 (unsigned long) imm_expr.X_add_number);
11606 INSERT_OPERAND (mips_opts.micromips,
11607 COPZ, *ip, imm_expr.X_add_number);
11608 imm_expr.X_op = O_absent;
11613 case 'J': /* 19-bit WAIT code. */
11614 gas_assert (!mips_opts.micromips);
11615 my_getExpression (&imm_expr, s);
11616 check_absolute_expr (ip, &imm_expr);
11617 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11619 as_warn (_("Illegal 19-bit code (%lu)"),
11620 (unsigned long) imm_expr.X_add_number);
11621 imm_expr.X_add_number &= OP_MASK_CODE19;
11623 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11624 imm_expr.X_op = O_absent;
11628 case 'P': /* Performance register. */
11629 gas_assert (!mips_opts.micromips);
11630 my_getExpression (&imm_expr, s);
11631 check_absolute_expr (ip, &imm_expr);
11632 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11633 as_warn (_("Invalid performance register (%lu)"),
11634 (unsigned long) imm_expr.X_add_number);
11635 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11636 imm_expr.X_op = O_absent;
11640 case 'G': /* Coprocessor destination register. */
11642 unsigned long opcode = ip->insn_opcode;
11643 unsigned long mask;
11644 unsigned int types;
11647 if (mips_opts.micromips)
11649 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11650 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11651 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11655 case 0x000000fc: /* mfc0 */
11656 case 0x000002fc: /* mtc0 */
11657 case 0x580000fc: /* dmfc0 */
11658 case 0x580002fc: /* dmtc0 */
11668 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11669 cop0 = opcode == OP_OP_COP0;
11671 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11672 ok = reg_lookup (&s, types, ®no);
11673 if (mips_opts.micromips)
11674 INSERT_OPERAND (1, RS, *ip, regno);
11676 INSERT_OPERAND (0, RD, *ip, regno);
11685 case 'y': /* ALNV.PS source register. */
11686 gas_assert (mips_opts.micromips);
11688 case 'x': /* Ignore register name. */
11689 case 'U': /* Destination register (CLO/CLZ). */
11690 case 'g': /* Coprocessor destination register. */
11691 gas_assert (!mips_opts.micromips);
11692 case 'b': /* Base register. */
11693 case 'd': /* Destination register. */
11694 case 's': /* Source register. */
11695 case 't': /* Target register. */
11696 case 'r': /* Both target and source. */
11697 case 'v': /* Both dest and source. */
11698 case 'w': /* Both dest and target. */
11699 case 'E': /* Coprocessor target register. */
11700 case 'K': /* RDHWR destination register. */
11701 case 'z': /* Must be zero register. */
11704 if (*args == 'E' || *args == 'K')
11705 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11708 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11709 if (regno == AT && mips_opts.at)
11711 if (mips_opts.at == ATREG)
11712 as_warn (_("Used $at without \".set noat\""));
11714 as_warn (_("Used $%u with \".set at=$%u\""),
11715 regno, mips_opts.at);
11725 if (c == 'r' || c == 'v' || c == 'w')
11732 /* 'z' only matches $0. */
11733 if (c == 'z' && regno != 0)
11736 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11738 if (regno == lastregno)
11741 = _("Source and destination must be different");
11744 if (regno == 31 && lastregno == 0xffffffff)
11747 = _("A destination register must be supplied");
11751 /* Now that we have assembled one operand, we use the args
11752 string to figure out where it goes in the instruction. */
11759 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11763 if (mips_opts.micromips)
11764 INSERT_OPERAND (1, RS, *ip, regno);
11766 INSERT_OPERAND (0, RD, *ip, regno);
11771 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11775 gas_assert (!mips_opts.micromips);
11776 INSERT_OPERAND (0, RD, *ip, regno);
11777 INSERT_OPERAND (0, RT, *ip, regno);
11783 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11787 gas_assert (mips_opts.micromips);
11788 INSERT_OPERAND (1, RS3, *ip, regno);
11792 /* This case exists because on the r3000 trunc
11793 expands into a macro which requires a gp
11794 register. On the r6000 or r4000 it is
11795 assembled into a single instruction which
11796 ignores the register. Thus the insn version
11797 is MIPS_ISA2 and uses 'x', and the macro
11798 version is MIPS_ISA1 and uses 't'. */
11802 /* This case is for the div instruction, which
11803 acts differently if the destination argument
11804 is $0. This only matches $0, and is checked
11805 outside the switch. */
11815 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11819 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11824 case 'O': /* MDMX alignment immediate constant. */
11825 gas_assert (!mips_opts.micromips);
11826 my_getExpression (&imm_expr, s);
11827 check_absolute_expr (ip, &imm_expr);
11828 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11829 as_warn (_("Improper align amount (%ld), using low bits"),
11830 (long) imm_expr.X_add_number);
11831 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11832 imm_expr.X_op = O_absent;
11836 case 'Q': /* MDMX vector, element sel, or const. */
11839 /* MDMX Immediate. */
11840 gas_assert (!mips_opts.micromips);
11841 my_getExpression (&imm_expr, s);
11842 check_absolute_expr (ip, &imm_expr);
11843 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
11844 as_warn (_("Invalid MDMX Immediate (%ld)"),
11845 (long) imm_expr.X_add_number);
11846 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
11847 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11848 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
11850 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
11851 imm_expr.X_op = O_absent;
11855 /* Not MDMX Immediate. Fall through. */
11856 case 'X': /* MDMX destination register. */
11857 case 'Y': /* MDMX source register. */
11858 case 'Z': /* MDMX target register. */
11861 gas_assert (!mips_opts.micromips);
11862 case 'D': /* Floating point destination register. */
11863 case 'S': /* Floating point source register. */
11864 case 'T': /* Floating point target register. */
11865 case 'R': /* Floating point source register. */
11869 || (mips_opts.ase_mdmx
11870 && (ip->insn_mo->pinfo & FP_D)
11871 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
11872 | INSN_COPROC_MEMORY_DELAY
11873 | INSN_LOAD_COPROC_DELAY
11874 | INSN_LOAD_MEMORY_DELAY
11875 | INSN_STORE_MEMORY))))
11876 rtype |= RTYPE_VEC;
11878 if (reg_lookup (&s, rtype, ®no))
11880 if ((regno & 1) != 0
11882 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
11883 as_warn (_("Float register should be even, was %d"),
11891 if (c == 'V' || c == 'W')
11902 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
11908 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
11912 /* This is like 'Z', but also needs to fix the MDMX
11913 vector/scalar select bits. Note that the
11914 scalar immediate case is handled above. */
11917 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
11918 int max_el = (is_qh ? 3 : 7);
11920 my_getExpression(&imm_expr, s);
11921 check_absolute_expr (ip, &imm_expr);
11923 if (imm_expr.X_add_number > max_el)
11924 as_bad (_("Bad element selector %ld"),
11925 (long) imm_expr.X_add_number);
11926 imm_expr.X_add_number &= max_el;
11927 ip->insn_opcode |= (imm_expr.X_add_number
11930 imm_expr.X_op = O_absent;
11932 as_warn (_("Expecting ']' found '%s'"), s);
11938 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
11939 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
11942 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
11945 /* Fall through. */
11949 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
11953 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
11963 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11967 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
11973 my_getExpression (&imm_expr, s);
11974 if (imm_expr.X_op != O_big
11975 && imm_expr.X_op != O_constant)
11976 insn_error = _("absolute expression required");
11977 if (HAVE_32BIT_GPRS)
11978 normalize_constant_expr (&imm_expr);
11983 my_getExpression (&offset_expr, s);
11984 normalize_address_expr (&offset_expr);
11985 *imm_reloc = BFD_RELOC_32;
11998 unsigned char temp[8];
12000 unsigned int length;
12005 /* These only appear as the last operand in an
12006 instruction, and every instruction that accepts
12007 them in any variant accepts them in all variants.
12008 This means we don't have to worry about backing out
12009 any changes if the instruction does not match.
12011 The difference between them is the size of the
12012 floating point constant and where it goes. For 'F'
12013 and 'L' the constant is 64 bits; for 'f' and 'l' it
12014 is 32 bits. Where the constant is placed is based
12015 on how the MIPS assembler does things:
12018 f -- immediate value
12021 The .lit4 and .lit8 sections are only used if
12022 permitted by the -G argument.
12024 The code below needs to know whether the target register
12025 is 32 or 64 bits wide. It relies on the fact 'f' and
12026 'F' are used with GPR-based instructions and 'l' and
12027 'L' are used with FPR-based instructions. */
12029 f64 = *args == 'F' || *args == 'L';
12030 using_gprs = *args == 'F' || *args == 'f';
12032 save_in = input_line_pointer;
12033 input_line_pointer = s;
12034 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12036 s = input_line_pointer;
12037 input_line_pointer = save_in;
12038 if (err != NULL && *err != '\0')
12040 as_bad (_("Bad floating point constant: %s"), err);
12041 memset (temp, '\0', sizeof temp);
12042 length = f64 ? 8 : 4;
12045 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12049 && (g_switch_value < 4
12050 || (temp[0] == 0 && temp[1] == 0)
12051 || (temp[2] == 0 && temp[3] == 0))))
12053 imm_expr.X_op = O_constant;
12054 if (!target_big_endian)
12055 imm_expr.X_add_number = bfd_getl32 (temp);
12057 imm_expr.X_add_number = bfd_getb32 (temp);
12059 else if (length > 4
12060 && !mips_disable_float_construction
12061 /* Constants can only be constructed in GPRs and
12062 copied to FPRs if the GPRs are at least as wide
12063 as the FPRs. Force the constant into memory if
12064 we are using 64-bit FPRs but the GPRs are only
12067 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12068 && ((temp[0] == 0 && temp[1] == 0)
12069 || (temp[2] == 0 && temp[3] == 0))
12070 && ((temp[4] == 0 && temp[5] == 0)
12071 || (temp[6] == 0 && temp[7] == 0)))
12073 /* The value is simple enough to load with a couple of
12074 instructions. If using 32-bit registers, set
12075 imm_expr to the high order 32 bits and offset_expr to
12076 the low order 32 bits. Otherwise, set imm_expr to
12077 the entire 64 bit constant. */
12078 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12080 imm_expr.X_op = O_constant;
12081 offset_expr.X_op = O_constant;
12082 if (!target_big_endian)
12084 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12085 offset_expr.X_add_number = bfd_getl32 (temp);
12089 imm_expr.X_add_number = bfd_getb32 (temp);
12090 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12092 if (offset_expr.X_add_number == 0)
12093 offset_expr.X_op = O_absent;
12095 else if (sizeof (imm_expr.X_add_number) > 4)
12097 imm_expr.X_op = O_constant;
12098 if (!target_big_endian)
12099 imm_expr.X_add_number = bfd_getl64 (temp);
12101 imm_expr.X_add_number = bfd_getb64 (temp);
12105 imm_expr.X_op = O_big;
12106 imm_expr.X_add_number = 4;
12107 if (!target_big_endian)
12109 generic_bignum[0] = bfd_getl16 (temp);
12110 generic_bignum[1] = bfd_getl16 (temp + 2);
12111 generic_bignum[2] = bfd_getl16 (temp + 4);
12112 generic_bignum[3] = bfd_getl16 (temp + 6);
12116 generic_bignum[0] = bfd_getb16 (temp + 6);
12117 generic_bignum[1] = bfd_getb16 (temp + 4);
12118 generic_bignum[2] = bfd_getb16 (temp + 2);
12119 generic_bignum[3] = bfd_getb16 (temp);
12125 const char *newname;
12128 /* Switch to the right section. */
12130 subseg = now_subseg;
12133 default: /* unused default case avoids warnings. */
12135 newname = RDATA_SECTION_NAME;
12136 if (g_switch_value >= 8)
12140 newname = RDATA_SECTION_NAME;
12143 gas_assert (g_switch_value >= 4);
12147 new_seg = subseg_new (newname, (subsegT) 0);
12149 bfd_set_section_flags (stdoutput, new_seg,
12154 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12155 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12156 record_alignment (new_seg, 4);
12158 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12159 if (seg == now_seg)
12160 as_bad (_("Can't use floating point insn in this section"));
12162 /* Set the argument to the current address in the
12164 offset_expr.X_op = O_symbol;
12165 offset_expr.X_add_symbol = symbol_temp_new_now ();
12166 offset_expr.X_add_number = 0;
12168 /* Put the floating point number into the section. */
12169 p = frag_more ((int) length);
12170 memcpy (p, temp, length);
12172 /* Switch back to the original section. */
12173 subseg_set (seg, subseg);
12178 case 'i': /* 16-bit unsigned immediate. */
12179 case 'j': /* 16-bit signed immediate. */
12180 *imm_reloc = BFD_RELOC_LO16;
12181 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12184 offsetT minval, maxval;
12186 more = (insn + 1 < past
12187 && strcmp (insn->name, insn[1].name) == 0);
12189 /* If the expression was written as an unsigned number,
12190 only treat it as signed if there are no more
12194 && sizeof (imm_expr.X_add_number) <= 4
12195 && imm_expr.X_op == O_constant
12196 && imm_expr.X_add_number < 0
12197 && imm_expr.X_unsigned
12198 && HAVE_64BIT_GPRS)
12201 /* For compatibility with older assemblers, we accept
12202 0x8000-0xffff as signed 16-bit numbers when only
12203 signed numbers are allowed. */
12205 minval = 0, maxval = 0xffff;
12207 minval = -0x8000, maxval = 0x7fff;
12209 minval = -0x8000, maxval = 0xffff;
12211 if (imm_expr.X_op != O_constant
12212 || imm_expr.X_add_number < minval
12213 || imm_expr.X_add_number > maxval)
12217 if (imm_expr.X_op == O_constant
12218 || imm_expr.X_op == O_big)
12219 as_bad (_("Expression out of range"));
12225 case 'o': /* 16-bit offset. */
12226 offset_reloc[0] = BFD_RELOC_LO16;
12227 offset_reloc[1] = BFD_RELOC_UNUSED;
12228 offset_reloc[2] = BFD_RELOC_UNUSED;
12230 /* Check whether there is only a single bracketed expression
12231 left. If so, it must be the base register and the
12232 constant must be zero. */
12233 if (*s == '(' && strchr (s + 1, '(') == 0)
12235 offset_expr.X_op = O_constant;
12236 offset_expr.X_add_number = 0;
12240 /* If this value won't fit into a 16 bit offset, then go
12241 find a macro that will generate the 32 bit offset
12243 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12244 && (offset_expr.X_op != O_constant
12245 || offset_expr.X_add_number >= 0x8000
12246 || offset_expr.X_add_number < -0x8000))
12252 case 'p': /* PC-relative offset. */
12253 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12254 my_getExpression (&offset_expr, s);
12258 case 'u': /* Upper 16 bits. */
12259 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12260 && imm_expr.X_op == O_constant
12261 && (imm_expr.X_add_number < 0
12262 || imm_expr.X_add_number >= 0x10000))
12263 as_bad (_("lui expression (%lu) not in range 0..65535"),
12264 (unsigned long) imm_expr.X_add_number);
12268 case 'a': /* 26-bit address. */
12269 *offset_reloc = BFD_RELOC_MIPS_JMP;
12270 my_getExpression (&offset_expr, s);
12274 case 'N': /* 3-bit branch condition code. */
12275 case 'M': /* 3-bit compare condition code. */
12277 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12278 rtype |= RTYPE_FCC;
12279 if (!reg_lookup (&s, rtype, ®no))
12281 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12282 || strcmp (str + strlen (str) - 5, "any2f") == 0
12283 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12284 && (regno & 1) != 0)
12285 as_warn (_("Condition code register should be even for %s, "
12288 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12289 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12290 && (regno & 3) != 0)
12291 as_warn (_("Condition code register should be 0 or 4 for %s, "
12295 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12297 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12301 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12312 while (ISDIGIT (*s));
12315 c = 8; /* Invalid sel value. */
12318 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12319 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12323 gas_assert (!mips_opts.micromips);
12324 /* Must be at least one digit. */
12325 my_getExpression (&imm_expr, s);
12326 check_absolute_expr (ip, &imm_expr);
12328 if ((unsigned long) imm_expr.X_add_number
12329 > (unsigned long) OP_MASK_VECBYTE)
12331 as_bad (_("bad byte vector index (%ld)"),
12332 (long) imm_expr.X_add_number);
12333 imm_expr.X_add_number = 0;
12336 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12337 imm_expr.X_op = O_absent;
12342 gas_assert (!mips_opts.micromips);
12343 my_getExpression (&imm_expr, s);
12344 check_absolute_expr (ip, &imm_expr);
12346 if ((unsigned long) imm_expr.X_add_number
12347 > (unsigned long) OP_MASK_VECALIGN)
12349 as_bad (_("bad byte vector index (%ld)"),
12350 (long) imm_expr.X_add_number);
12351 imm_expr.X_add_number = 0;
12354 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12355 imm_expr.X_op = O_absent;
12359 case 'm': /* Opcode extension character. */
12360 gas_assert (mips_opts.micromips);
12365 if (strncmp (s, "$pc", 3) == 0)
12393 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12394 if (regno == AT && mips_opts.at)
12396 if (mips_opts.at == ATREG)
12397 as_warn (_("Used $at without \".set noat\""));
12399 as_warn (_("Used $%u with \".set at=$%u\""),
12400 regno, mips_opts.at);
12406 gas_assert (args[1] == ',');
12412 gas_assert (args[1] == ',');
12414 continue; /* Nothing to do. */
12420 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12422 if (regno == lastregno)
12425 = _("Source and destination must be different");
12428 if (regno == 31 && lastregno == 0xffffffff)
12431 = _("A destination register must be supplied");
12442 gas_assert (args[1] == ',');
12449 gas_assert (args[1] == ',');
12452 continue; /* Nothing to do. */
12456 /* Make sure regno is the same as lastregno. */
12457 if (c == 't' && regno != lastregno)
12460 /* Make sure regno is the same as destregno. */
12461 if (c == 'x' && regno != destregno)
12464 /* We need to save regno, before regno maps to the
12465 microMIPS register encoding. */
12475 regno = ILLEGAL_REG;
12479 regno = mips32_to_micromips_reg_b_map[regno];
12483 regno = mips32_to_micromips_reg_c_map[regno];
12487 regno = mips32_to_micromips_reg_d_map[regno];
12491 regno = mips32_to_micromips_reg_e_map[regno];
12495 regno = mips32_to_micromips_reg_f_map[regno];
12499 regno = mips32_to_micromips_reg_g_map[regno];
12503 regno = mips32_to_micromips_reg_h_map[regno];
12507 switch (EXTRACT_OPERAND (1, MI, *ip))
12512 else if (regno == 22)
12514 else if (regno == 5)
12516 else if (regno == 6)
12518 else if (regno == 7)
12521 regno = ILLEGAL_REG;
12527 else if (regno == 7)
12530 regno = ILLEGAL_REG;
12537 regno = ILLEGAL_REG;
12541 regno = ILLEGAL_REG;
12547 regno = mips32_to_micromips_reg_l_map[regno];
12551 regno = mips32_to_micromips_reg_m_map[regno];
12555 regno = mips32_to_micromips_reg_n_map[regno];
12559 regno = mips32_to_micromips_reg_q_map[regno];
12564 regno = ILLEGAL_REG;
12569 regno = ILLEGAL_REG;
12574 regno = ILLEGAL_REG;
12577 case 'j': /* Do nothing. */
12587 if (regno == ILLEGAL_REG)
12593 INSERT_OPERAND (1, MB, *ip, regno);
12597 INSERT_OPERAND (1, MC, *ip, regno);
12601 INSERT_OPERAND (1, MD, *ip, regno);
12605 INSERT_OPERAND (1, ME, *ip, regno);
12609 INSERT_OPERAND (1, MF, *ip, regno);
12613 INSERT_OPERAND (1, MG, *ip, regno);
12617 INSERT_OPERAND (1, MH, *ip, regno);
12621 INSERT_OPERAND (1, MI, *ip, regno);
12625 INSERT_OPERAND (1, MJ, *ip, regno);
12629 INSERT_OPERAND (1, ML, *ip, regno);
12633 INSERT_OPERAND (1, MM, *ip, regno);
12637 INSERT_OPERAND (1, MN, *ip, regno);
12641 INSERT_OPERAND (1, MP, *ip, regno);
12645 INSERT_OPERAND (1, MQ, *ip, regno);
12648 case 'a': /* Do nothing. */
12649 case 's': /* Do nothing. */
12650 case 't': /* Do nothing. */
12651 case 'x': /* Do nothing. */
12652 case 'y': /* Do nothing. */
12653 case 'z': /* Do nothing. */
12663 bfd_reloc_code_real_type r[3];
12667 /* Check whether there is only a single bracketed
12668 expression left. If so, it must be the base register
12669 and the constant must be zero. */
12670 if (*s == '(' && strchr (s + 1, '(') == 0)
12672 INSERT_OPERAND (1, IMMA, *ip, 0);
12676 if (my_getSmallExpression (&ep, r, s) > 0
12677 || !expr_const_in_range (&ep, -64, 64, 2))
12680 imm = ep.X_add_number >> 2;
12681 INSERT_OPERAND (1, IMMA, *ip, imm);
12688 bfd_reloc_code_real_type r[3];
12692 if (my_getSmallExpression (&ep, r, s) > 0
12693 || ep.X_op != O_constant)
12696 for (imm = 0; imm < 8; imm++)
12697 if (micromips_imm_b_map[imm] == ep.X_add_number)
12702 INSERT_OPERAND (1, IMMB, *ip, imm);
12709 bfd_reloc_code_real_type r[3];
12713 if (my_getSmallExpression (&ep, r, s) > 0
12714 || ep.X_op != O_constant)
12717 for (imm = 0; imm < 16; imm++)
12718 if (micromips_imm_c_map[imm] == ep.X_add_number)
12723 INSERT_OPERAND (1, IMMC, *ip, imm);
12728 case 'D': /* pc relative offset */
12729 case 'E': /* pc relative offset */
12730 my_getExpression (&offset_expr, s);
12731 if (offset_expr.X_op == O_register)
12734 if (!forced_insn_length)
12735 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12737 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12739 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12745 bfd_reloc_code_real_type r[3];
12749 if (my_getSmallExpression (&ep, r, s) > 0
12750 || !expr_const_in_range (&ep, 0, 16, 0))
12753 imm = ep.X_add_number;
12754 INSERT_OPERAND (1, IMMF, *ip, imm);
12761 bfd_reloc_code_real_type r[3];
12765 /* Check whether there is only a single bracketed
12766 expression left. If so, it must be the base register
12767 and the constant must be zero. */
12768 if (*s == '(' && strchr (s + 1, '(') == 0)
12770 INSERT_OPERAND (1, IMMG, *ip, 0);
12774 if (my_getSmallExpression (&ep, r, s) > 0
12775 || !expr_const_in_range (&ep, -1, 15, 0))
12778 imm = ep.X_add_number & 15;
12779 INSERT_OPERAND (1, IMMG, *ip, imm);
12786 bfd_reloc_code_real_type r[3];
12790 /* Check whether there is only a single bracketed
12791 expression left. If so, it must be the base register
12792 and the constant must be zero. */
12793 if (*s == '(' && strchr (s + 1, '(') == 0)
12795 INSERT_OPERAND (1, IMMH, *ip, 0);
12799 if (my_getSmallExpression (&ep, r, s) > 0
12800 || !expr_const_in_range (&ep, 0, 16, 1))
12803 imm = ep.X_add_number >> 1;
12804 INSERT_OPERAND (1, IMMH, *ip, imm);
12811 bfd_reloc_code_real_type r[3];
12815 if (my_getSmallExpression (&ep, r, s) > 0
12816 || !expr_const_in_range (&ep, -1, 127, 0))
12819 imm = ep.X_add_number & 127;
12820 INSERT_OPERAND (1, IMMI, *ip, imm);
12827 bfd_reloc_code_real_type r[3];
12831 /* Check whether there is only a single bracketed
12832 expression left. If so, it must be the base register
12833 and the constant must be zero. */
12834 if (*s == '(' && strchr (s + 1, '(') == 0)
12836 INSERT_OPERAND (1, IMMJ, *ip, 0);
12840 if (my_getSmallExpression (&ep, r, s) > 0
12841 || !expr_const_in_range (&ep, 0, 16, 2))
12844 imm = ep.X_add_number >> 2;
12845 INSERT_OPERAND (1, IMMJ, *ip, imm);
12852 bfd_reloc_code_real_type r[3];
12856 /* Check whether there is only a single bracketed
12857 expression left. If so, it must be the base register
12858 and the constant must be zero. */
12859 if (*s == '(' && strchr (s + 1, '(') == 0)
12861 INSERT_OPERAND (1, IMML, *ip, 0);
12865 if (my_getSmallExpression (&ep, r, s) > 0
12866 || !expr_const_in_range (&ep, 0, 16, 0))
12869 imm = ep.X_add_number;
12870 INSERT_OPERAND (1, IMML, *ip, imm);
12877 bfd_reloc_code_real_type r[3];
12881 if (my_getSmallExpression (&ep, r, s) > 0
12882 || !expr_const_in_range (&ep, 1, 9, 0))
12885 imm = ep.X_add_number & 7;
12886 INSERT_OPERAND (1, IMMM, *ip, imm);
12891 case 'N': /* Register list for lwm and swm. */
12893 /* A comma-separated list of registers and/or
12894 dash-separated contiguous ranges including
12895 both ra and a set of one or more registers
12896 starting at s0 up to s3 which have to be
12903 and any permutations of these. */
12904 unsigned int reglist;
12907 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
12910 if ((reglist & 0xfff1ffff) != 0x80010000)
12913 reglist = (reglist >> 17) & 7;
12915 if ((reglist & -reglist) != reglist)
12918 imm = ffs (reglist) - 1;
12919 INSERT_OPERAND (1, IMMN, *ip, imm);
12923 case 'O': /* sdbbp 4-bit code. */
12925 bfd_reloc_code_real_type r[3];
12929 if (my_getSmallExpression (&ep, r, s) > 0
12930 || !expr_const_in_range (&ep, 0, 16, 0))
12933 imm = ep.X_add_number;
12934 INSERT_OPERAND (1, IMMO, *ip, imm);
12941 bfd_reloc_code_real_type r[3];
12945 if (my_getSmallExpression (&ep, r, s) > 0
12946 || !expr_const_in_range (&ep, 0, 32, 2))
12949 imm = ep.X_add_number >> 2;
12950 INSERT_OPERAND (1, IMMP, *ip, imm);
12957 bfd_reloc_code_real_type r[3];
12961 if (my_getSmallExpression (&ep, r, s) > 0
12962 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
12965 imm = ep.X_add_number >> 2;
12966 INSERT_OPERAND (1, IMMQ, *ip, imm);
12973 bfd_reloc_code_real_type r[3];
12977 /* Check whether there is only a single bracketed
12978 expression left. If so, it must be the base register
12979 and the constant must be zero. */
12980 if (*s == '(' && strchr (s + 1, '(') == 0)
12982 INSERT_OPERAND (1, IMMU, *ip, 0);
12986 if (my_getSmallExpression (&ep, r, s) > 0
12987 || !expr_const_in_range (&ep, 0, 32, 2))
12990 imm = ep.X_add_number >> 2;
12991 INSERT_OPERAND (1, IMMU, *ip, imm);
12998 bfd_reloc_code_real_type r[3];
13002 if (my_getSmallExpression (&ep, r, s) > 0
13003 || !expr_const_in_range (&ep, 0, 64, 2))
13006 imm = ep.X_add_number >> 2;
13007 INSERT_OPERAND (1, IMMW, *ip, imm);
13014 bfd_reloc_code_real_type r[3];
13018 if (my_getSmallExpression (&ep, r, s) > 0
13019 || !expr_const_in_range (&ep, -8, 8, 0))
13022 imm = ep.X_add_number;
13023 INSERT_OPERAND (1, IMMX, *ip, imm);
13030 bfd_reloc_code_real_type r[3];
13034 if (my_getSmallExpression (&ep, r, s) > 0
13035 || expr_const_in_range (&ep, -2, 2, 2)
13036 || !expr_const_in_range (&ep, -258, 258, 2))
13039 imm = ep.X_add_number >> 2;
13040 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13041 INSERT_OPERAND (1, IMMY, *ip, imm);
13048 bfd_reloc_code_real_type r[3];
13051 if (my_getSmallExpression (&ep, r, s) > 0
13052 || !expr_const_in_range (&ep, 0, 1, 0))
13059 as_bad (_("Internal error: bad microMIPS opcode "
13060 "(unknown extension operand type `m%c'): %s %s"),
13061 *args, insn->name, insn->args);
13062 /* Further processing is fruitless. */
13067 case 'n': /* Register list for 32-bit lwm and swm. */
13068 gas_assert (mips_opts.micromips);
13070 /* A comma-separated list of registers and/or
13071 dash-separated contiguous ranges including
13072 at least one of ra and a set of one or more
13073 registers starting at s0 up to s7 and then
13074 s8 which have to be consecutive, e.g.:
13082 and any permutations of these. */
13083 unsigned int reglist;
13087 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13090 if ((reglist & 0x3f00ffff) != 0)
13093 ra = (reglist >> 27) & 0x10;
13094 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13096 if ((reglist & -reglist) != reglist)
13099 imm = (ffs (reglist) - 1) | ra;
13100 INSERT_OPERAND (1, RT, *ip, imm);
13101 imm_expr.X_op = O_absent;
13105 case '|': /* 4-bit trap code. */
13106 gas_assert (mips_opts.micromips);
13107 my_getExpression (&imm_expr, s);
13108 check_absolute_expr (ip, &imm_expr);
13109 if ((unsigned long) imm_expr.X_add_number
13110 > MICROMIPSOP_MASK_TRAP)
13111 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13112 (unsigned long) imm_expr.X_add_number,
13113 ip->insn_mo->name);
13114 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13115 imm_expr.X_op = O_absent;
13120 as_bad (_("Bad char = '%c'\n"), *args);
13125 /* Args don't match. */
13127 insn_error = _("Illegal operands");
13128 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13133 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13135 gas_assert (firstinsn);
13136 need_delay_slot_ok = FALSE;
13145 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13147 /* This routine assembles an instruction into its binary format when
13148 assembling for the mips16. As a side effect, it sets one of the
13149 global variables imm_reloc or offset_reloc to the type of relocation
13150 to do if one of the operands is an address expression. It also sets
13151 forced_insn_length to the resulting instruction size in bytes if the
13152 user explicitly requested a small or extended instruction. */
13155 mips16_ip (char *str, struct mips_cl_insn *ip)
13159 struct mips_opcode *insn;
13161 unsigned int regno;
13162 unsigned int lastregno = 0;
13168 forced_insn_length = 0;
13170 for (s = str; ISLOWER (*s); ++s)
13182 if (s[1] == 't' && s[2] == ' ')
13185 forced_insn_length = 2;
13189 else if (s[1] == 'e' && s[2] == ' ')
13192 forced_insn_length = 4;
13196 /* Fall through. */
13198 insn_error = _("unknown opcode");
13202 if (mips_opts.noautoextend && !forced_insn_length)
13203 forced_insn_length = 2;
13205 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13207 insn_error = _("unrecognized opcode");
13216 gas_assert (strcmp (insn->name, str) == 0);
13218 ok = is_opcode_valid_16 (insn);
13221 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13222 && strcmp (insn->name, insn[1].name) == 0)
13231 static char buf[100];
13233 _("opcode not supported on this processor: %s (%s)"),
13234 mips_cpu_info_from_arch (mips_opts.arch)->name,
13235 mips_cpu_info_from_isa (mips_opts.isa)->name);
13242 create_insn (ip, insn);
13243 imm_expr.X_op = O_absent;
13244 imm_reloc[0] = BFD_RELOC_UNUSED;
13245 imm_reloc[1] = BFD_RELOC_UNUSED;
13246 imm_reloc[2] = BFD_RELOC_UNUSED;
13247 imm2_expr.X_op = O_absent;
13248 offset_expr.X_op = O_absent;
13249 offset_reloc[0] = BFD_RELOC_UNUSED;
13250 offset_reloc[1] = BFD_RELOC_UNUSED;
13251 offset_reloc[2] = BFD_RELOC_UNUSED;
13252 for (args = insn->args; 1; ++args)
13259 /* In this switch statement we call break if we did not find
13260 a match, continue if we did find a match, or return if we
13269 /* Stuff the immediate value in now, if we can. */
13270 if (imm_expr.X_op == O_constant
13271 && *imm_reloc > BFD_RELOC_UNUSED
13272 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
13273 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
13274 && insn->pinfo != INSN_MACRO)
13278 switch (*offset_reloc)
13280 case BFD_RELOC_MIPS16_HI16_S:
13281 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
13284 case BFD_RELOC_MIPS16_HI16:
13285 tmp = imm_expr.X_add_number >> 16;
13288 case BFD_RELOC_MIPS16_LO16:
13289 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
13293 case BFD_RELOC_UNUSED:
13294 tmp = imm_expr.X_add_number;
13300 *offset_reloc = BFD_RELOC_UNUSED;
13302 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13303 tmp, TRUE, forced_insn_length == 2,
13304 forced_insn_length == 4, &ip->insn_opcode,
13305 &ip->use_extend, &ip->extend);
13306 imm_expr.X_op = O_absent;
13307 *imm_reloc = BFD_RELOC_UNUSED;
13321 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13324 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13340 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13342 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13346 /* Fall through. */
13357 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13359 if (c == 'v' || c == 'w')
13362 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13364 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13375 if (c == 'v' || c == 'w')
13377 regno = mips16_to_32_reg_map[lastregno];
13391 regno = mips32_to_16_reg_map[regno];
13396 regno = ILLEGAL_REG;
13401 regno = ILLEGAL_REG;
13406 regno = ILLEGAL_REG;
13411 if (regno == AT && mips_opts.at)
13413 if (mips_opts.at == ATREG)
13414 as_warn (_("used $at without \".set noat\""));
13416 as_warn (_("used $%u with \".set at=$%u\""),
13417 regno, mips_opts.at);
13425 if (regno == ILLEGAL_REG)
13432 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13436 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13439 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13442 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13448 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13451 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13452 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13462 if (strncmp (s, "$pc", 3) == 0)
13479 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13482 if (imm_expr.X_op != O_constant)
13484 forced_insn_length = 4;
13485 ip->use_extend = TRUE;
13490 /* We need to relax this instruction. */
13491 *offset_reloc = *imm_reloc;
13492 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13497 *imm_reloc = BFD_RELOC_UNUSED;
13498 /* Fall through. */
13505 my_getExpression (&imm_expr, s);
13506 if (imm_expr.X_op == O_register)
13508 /* What we thought was an expression turned out to
13511 if (s[0] == '(' && args[1] == '(')
13513 /* It looks like the expression was omitted
13514 before a register indirection, which means
13515 that the expression is implicitly zero. We
13516 still set up imm_expr, so that we handle
13517 explicit extensions correctly. */
13518 imm_expr.X_op = O_constant;
13519 imm_expr.X_add_number = 0;
13520 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13527 /* We need to relax this instruction. */
13528 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13537 /* We use offset_reloc rather than imm_reloc for the PC
13538 relative operands. This lets macros with both
13539 immediate and address operands work correctly. */
13540 my_getExpression (&offset_expr, s);
13542 if (offset_expr.X_op == O_register)
13545 /* We need to relax this instruction. */
13546 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13550 case '6': /* break code */
13551 my_getExpression (&imm_expr, s);
13552 check_absolute_expr (ip, &imm_expr);
13553 if ((unsigned long) imm_expr.X_add_number > 63)
13554 as_warn (_("Invalid value for `%s' (%lu)"),
13556 (unsigned long) imm_expr.X_add_number);
13557 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13558 imm_expr.X_op = O_absent;
13562 case 'a': /* 26 bit address */
13563 my_getExpression (&offset_expr, s);
13565 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13566 ip->insn_opcode <<= 16;
13569 case 'l': /* register list for entry macro */
13570 case 'L': /* register list for exit macro */
13580 unsigned int freg, reg1, reg2;
13582 while (*s == ' ' || *s == ',')
13584 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13586 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13590 as_bad (_("can't parse register list"));
13600 if (!reg_lookup (&s, freg ? RTYPE_FPU
13601 : (RTYPE_GP | RTYPE_NUM), ®2))
13603 as_bad (_("invalid register list"));
13607 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13609 mask &= ~ (7 << 3);
13612 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13614 mask &= ~ (7 << 3);
13617 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13618 mask |= (reg2 - 3) << 3;
13619 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13620 mask |= (reg2 - 15) << 1;
13621 else if (reg1 == RA && reg2 == RA)
13625 as_bad (_("invalid register list"));
13629 /* The mask is filled in in the opcode table for the
13630 benefit of the disassembler. We remove it before
13631 applying the actual mask. */
13632 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13633 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13637 case 'm': /* Register list for save insn. */
13638 case 'M': /* Register list for restore insn. */
13641 int framesz = 0, seen_framesz = 0;
13642 int nargs = 0, statics = 0, sregs = 0;
13646 unsigned int reg1, reg2;
13648 SKIP_SPACE_TABS (s);
13651 SKIP_SPACE_TABS (s);
13653 my_getExpression (&imm_expr, s);
13654 if (imm_expr.X_op == O_constant)
13656 /* Handle the frame size. */
13659 as_bad (_("more than one frame size in list"));
13663 framesz = imm_expr.X_add_number;
13664 imm_expr.X_op = O_absent;
13669 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13671 as_bad (_("can't parse register list"));
13683 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13686 as_bad (_("can't parse register list"));
13691 while (reg1 <= reg2)
13693 if (reg1 >= 4 && reg1 <= 7)
13697 nargs |= 1 << (reg1 - 4);
13699 /* statics $a0-$a3 */
13700 statics |= 1 << (reg1 - 4);
13702 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13705 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13707 else if (reg1 == 31)
13709 /* Add $ra to insn. */
13714 as_bad (_("unexpected register in list"));
13722 /* Encode args/statics combination. */
13723 if (nargs & statics)
13724 as_bad (_("arg/static registers overlap"));
13725 else if (nargs == 0xf)
13726 /* All $a0-$a3 are args. */
13727 opcode |= MIPS16_ALL_ARGS << 16;
13728 else if (statics == 0xf)
13729 /* All $a0-$a3 are statics. */
13730 opcode |= MIPS16_ALL_STATICS << 16;
13733 int narg = 0, nstat = 0;
13735 /* Count arg registers. */
13736 while (nargs & 0x1)
13742 as_bad (_("invalid arg register list"));
13744 /* Count static registers. */
13745 while (statics & 0x8)
13747 statics = (statics << 1) & 0xf;
13751 as_bad (_("invalid static register list"));
13753 /* Encode args/statics. */
13754 opcode |= ((narg << 2) | nstat) << 16;
13757 /* Encode $s0/$s1. */
13758 if (sregs & (1 << 0)) /* $s0 */
13760 if (sregs & (1 << 1)) /* $s1 */
13766 /* Count regs $s2-$s8. */
13774 as_bad (_("invalid static register list"));
13775 /* Encode $s2-$s8. */
13776 opcode |= nsreg << 24;
13779 /* Encode frame size. */
13781 as_bad (_("missing frame size"));
13782 else if ((framesz & 7) != 0 || framesz < 0
13783 || framesz > 0xff * 8)
13784 as_bad (_("invalid frame size"));
13785 else if (framesz != 128 || (opcode >> 16) != 0)
13788 opcode |= (((framesz & 0xf0) << 16)
13789 | (framesz & 0x0f));
13792 /* Finally build the instruction. */
13793 if ((opcode >> 16) != 0 || framesz == 0)
13795 ip->use_extend = TRUE;
13796 ip->extend = opcode >> 16;
13798 ip->insn_opcode |= opcode & 0x7f;
13802 case 'e': /* extend code */
13803 my_getExpression (&imm_expr, s);
13804 check_absolute_expr (ip, &imm_expr);
13805 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13807 as_warn (_("Invalid value for `%s' (%lu)"),
13809 (unsigned long) imm_expr.X_add_number);
13810 imm_expr.X_add_number &= 0x7ff;
13812 ip->insn_opcode |= imm_expr.X_add_number;
13813 imm_expr.X_op = O_absent;
13823 /* Args don't match. */
13824 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13825 strcmp (insn->name, insn[1].name) == 0)
13832 insn_error = _("illegal operands");
13838 /* This structure holds information we know about a mips16 immediate
13841 struct mips16_immed_operand
13843 /* The type code used in the argument string in the opcode table. */
13845 /* The number of bits in the short form of the opcode. */
13847 /* The number of bits in the extended form of the opcode. */
13849 /* The amount by which the short form is shifted when it is used;
13850 for example, the sw instruction has a shift count of 2. */
13852 /* The amount by which the short form is shifted when it is stored
13853 into the instruction code. */
13855 /* Non-zero if the short form is unsigned. */
13857 /* Non-zero if the extended form is unsigned. */
13859 /* Non-zero if the value is PC relative. */
13863 /* The mips16 immediate operand types. */
13865 static const struct mips16_immed_operand mips16_immed_operands[] =
13867 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13868 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13869 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13870 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13871 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
13872 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
13873 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
13874 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
13875 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
13876 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
13877 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
13878 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
13879 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
13880 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
13881 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
13882 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
13883 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13884 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
13885 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
13886 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
13887 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
13890 #define MIPS16_NUM_IMMED \
13891 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
13893 /* Handle a mips16 instruction with an immediate value. This or's the
13894 small immediate value into *INSN. It sets *USE_EXTEND to indicate
13895 whether an extended value is needed; if one is needed, it sets
13896 *EXTEND to the value. The argument type is TYPE. The value is VAL.
13897 If SMALL is true, an unextended opcode was explicitly requested.
13898 If EXT is true, an extended opcode was explicitly requested. If
13899 WARN is true, warn if EXT does not match reality. */
13902 mips16_immed (char *file, unsigned int line, int type, offsetT val,
13903 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
13904 unsigned long *insn, bfd_boolean *use_extend,
13905 unsigned short *extend)
13907 const struct mips16_immed_operand *op;
13908 int mintiny, maxtiny;
13909 bfd_boolean needext;
13911 op = mips16_immed_operands;
13912 while (op->type != type)
13915 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
13920 if (type == '<' || type == '>' || type == '[' || type == ']')
13923 maxtiny = 1 << op->nbits;
13928 maxtiny = (1 << op->nbits) - 1;
13933 mintiny = - (1 << (op->nbits - 1));
13934 maxtiny = (1 << (op->nbits - 1)) - 1;
13937 /* Branch offsets have an implicit 0 in the lowest bit. */
13938 if (type == 'p' || type == 'q')
13941 if ((val & ((1 << op->shift) - 1)) != 0
13942 || val < (mintiny << op->shift)
13943 || val > (maxtiny << op->shift))
13948 if (warn && ext && ! needext)
13949 as_warn_where (file, line,
13950 _("extended operand requested but not required"));
13951 if (small && needext)
13952 as_bad_where (file, line, _("invalid unextended operand value"));
13954 if (small || (! ext && ! needext))
13958 *use_extend = FALSE;
13959 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
13960 insnval <<= op->op_shift;
13965 long minext, maxext;
13971 maxext = (1 << op->extbits) - 1;
13975 minext = - (1 << (op->extbits - 1));
13976 maxext = (1 << (op->extbits - 1)) - 1;
13978 if (val < minext || val > maxext)
13979 as_bad_where (file, line,
13980 _("operand value out of range for instruction"));
13982 *use_extend = TRUE;
13983 if (op->extbits == 16)
13985 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13988 else if (op->extbits == 15)
13990 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13995 extval = ((val & 0x1f) << 6) | (val & 0x20);
13999 *extend = (unsigned short) extval;
14004 struct percent_op_match
14007 bfd_reloc_code_real_type reloc;
14010 static const struct percent_op_match mips_percent_op[] =
14012 {"%lo", BFD_RELOC_LO16},
14014 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14015 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14016 {"%call16", BFD_RELOC_MIPS_CALL16},
14017 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14018 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14019 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14020 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14021 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14022 {"%got", BFD_RELOC_MIPS_GOT16},
14023 {"%gp_rel", BFD_RELOC_GPREL16},
14024 {"%half", BFD_RELOC_16},
14025 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14026 {"%higher", BFD_RELOC_MIPS_HIGHER},
14027 {"%neg", BFD_RELOC_MIPS_SUB},
14028 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14029 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14030 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14031 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14032 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14033 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14034 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14036 {"%hi", BFD_RELOC_HI16_S}
14039 static const struct percent_op_match mips16_percent_op[] =
14041 {"%lo", BFD_RELOC_MIPS16_LO16},
14042 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14043 {"%got", BFD_RELOC_MIPS16_GOT16},
14044 {"%call16", BFD_RELOC_MIPS16_CALL16},
14045 {"%hi", BFD_RELOC_MIPS16_HI16_S}
14049 /* Return true if *STR points to a relocation operator. When returning true,
14050 move *STR over the operator and store its relocation code in *RELOC.
14051 Leave both *STR and *RELOC alone when returning false. */
14054 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14056 const struct percent_op_match *percent_op;
14059 if (mips_opts.mips16)
14061 percent_op = mips16_percent_op;
14062 limit = ARRAY_SIZE (mips16_percent_op);
14066 percent_op = mips_percent_op;
14067 limit = ARRAY_SIZE (mips_percent_op);
14070 for (i = 0; i < limit; i++)
14071 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14073 int len = strlen (percent_op[i].str);
14075 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14078 *str += strlen (percent_op[i].str);
14079 *reloc = percent_op[i].reloc;
14081 /* Check whether the output BFD supports this relocation.
14082 If not, issue an error and fall back on something safe. */
14083 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14085 as_bad (_("relocation %s isn't supported by the current ABI"),
14086 percent_op[i].str);
14087 *reloc = BFD_RELOC_UNUSED;
14095 /* Parse string STR as a 16-bit relocatable operand. Store the
14096 expression in *EP and the relocations in the array starting
14097 at RELOC. Return the number of relocation operators used.
14099 On exit, EXPR_END points to the first character after the expression. */
14102 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14105 bfd_reloc_code_real_type reversed_reloc[3];
14106 size_t reloc_index, i;
14107 int crux_depth, str_depth;
14110 /* Search for the start of the main expression, recoding relocations
14111 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14112 of the main expression and with CRUX_DEPTH containing the number
14113 of open brackets at that point. */
14120 crux_depth = str_depth;
14122 /* Skip over whitespace and brackets, keeping count of the number
14124 while (*str == ' ' || *str == '\t' || *str == '(')
14129 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14130 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14132 my_getExpression (ep, crux);
14135 /* Match every open bracket. */
14136 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14140 if (crux_depth > 0)
14141 as_bad (_("unclosed '('"));
14145 if (reloc_index != 0)
14147 prev_reloc_op_frag = frag_now;
14148 for (i = 0; i < reloc_index; i++)
14149 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14152 return reloc_index;
14156 my_getExpression (expressionS *ep, char *str)
14160 save_in = input_line_pointer;
14161 input_line_pointer = str;
14163 expr_end = input_line_pointer;
14164 input_line_pointer = save_in;
14168 md_atof (int type, char *litP, int *sizeP)
14170 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14174 md_number_to_chars (char *buf, valueT val, int n)
14176 if (target_big_endian)
14177 number_to_chars_bigendian (buf, val, n);
14179 number_to_chars_littleendian (buf, val, n);
14183 static int support_64bit_objects(void)
14185 const char **list, **l;
14188 list = bfd_target_list ();
14189 for (l = list; *l != NULL; l++)
14190 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14191 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14193 yes = (*l != NULL);
14197 #endif /* OBJ_ELF */
14199 const char *md_shortopts = "O::g::G:";
14203 OPTION_MARCH = OPTION_MD_BASE,
14225 OPTION_NO_SMARTMIPS,
14229 OPTION_NO_MICROMIPS,
14232 OPTION_COMPAT_ARCH_BASE,
14241 OPTION_M7000_HILO_FIX,
14242 OPTION_MNO_7000_HILO_FIX,
14245 OPTION_FIX_LOONGSON2F_JUMP,
14246 OPTION_NO_FIX_LOONGSON2F_JUMP,
14247 OPTION_FIX_LOONGSON2F_NOP,
14248 OPTION_NO_FIX_LOONGSON2F_NOP,
14250 OPTION_NO_FIX_VR4120,
14252 OPTION_NO_FIX_VR4130,
14253 OPTION_FIX_CN63XXP1,
14254 OPTION_NO_FIX_CN63XXP1,
14261 OPTION_CONSTRUCT_FLOATS,
14262 OPTION_NO_CONSTRUCT_FLOATS,
14265 OPTION_RELAX_BRANCH,
14266 OPTION_NO_RELAX_BRANCH,
14273 OPTION_SINGLE_FLOAT,
14274 OPTION_DOUBLE_FLOAT,
14277 OPTION_CALL_SHARED,
14278 OPTION_CALL_NONPIC,
14288 OPTION_MVXWORKS_PIC,
14289 #endif /* OBJ_ELF */
14293 struct option md_longopts[] =
14295 /* Options which specify architecture. */
14296 {"march", required_argument, NULL, OPTION_MARCH},
14297 {"mtune", required_argument, NULL, OPTION_MTUNE},
14298 {"mips0", no_argument, NULL, OPTION_MIPS1},
14299 {"mips1", no_argument, NULL, OPTION_MIPS1},
14300 {"mips2", no_argument, NULL, OPTION_MIPS2},
14301 {"mips3", no_argument, NULL, OPTION_MIPS3},
14302 {"mips4", no_argument, NULL, OPTION_MIPS4},
14303 {"mips5", no_argument, NULL, OPTION_MIPS5},
14304 {"mips32", no_argument, NULL, OPTION_MIPS32},
14305 {"mips64", no_argument, NULL, OPTION_MIPS64},
14306 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14307 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14309 /* Options which specify Application Specific Extensions (ASEs). */
14310 {"mips16", no_argument, NULL, OPTION_MIPS16},
14311 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14312 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14313 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14314 {"mdmx", no_argument, NULL, OPTION_MDMX},
14315 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14316 {"mdsp", no_argument, NULL, OPTION_DSP},
14317 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14318 {"mmt", no_argument, NULL, OPTION_MT},
14319 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14320 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14321 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14322 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14323 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14324 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14325 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14326 {"mmcu", no_argument, NULL, OPTION_MCU},
14327 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14329 /* Old-style architecture options. Don't add more of these. */
14330 {"m4650", no_argument, NULL, OPTION_M4650},
14331 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14332 {"m4010", no_argument, NULL, OPTION_M4010},
14333 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14334 {"m4100", no_argument, NULL, OPTION_M4100},
14335 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14336 {"m3900", no_argument, NULL, OPTION_M3900},
14337 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14339 /* Options which enable bug fixes. */
14340 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14341 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14342 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14343 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14344 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14345 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14346 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14347 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14348 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14349 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14350 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14351 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14352 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14353 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14354 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14356 /* Miscellaneous options. */
14357 {"trap", no_argument, NULL, OPTION_TRAP},
14358 {"no-break", no_argument, NULL, OPTION_TRAP},
14359 {"break", no_argument, NULL, OPTION_BREAK},
14360 {"no-trap", no_argument, NULL, OPTION_BREAK},
14361 {"EB", no_argument, NULL, OPTION_EB},
14362 {"EL", no_argument, NULL, OPTION_EL},
14363 {"mfp32", no_argument, NULL, OPTION_FP32},
14364 {"mgp32", no_argument, NULL, OPTION_GP32},
14365 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14366 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14367 {"mfp64", no_argument, NULL, OPTION_FP64},
14368 {"mgp64", no_argument, NULL, OPTION_GP64},
14369 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14370 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14371 {"mshared", no_argument, NULL, OPTION_MSHARED},
14372 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14373 {"msym32", no_argument, NULL, OPTION_MSYM32},
14374 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14375 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14376 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14377 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14378 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14380 /* Strictly speaking this next option is ELF specific,
14381 but we allow it for other ports as well in order to
14382 make testing easier. */
14383 {"32", no_argument, NULL, OPTION_32},
14385 /* ELF-specific options. */
14387 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14388 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14389 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14390 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14391 {"xgot", no_argument, NULL, OPTION_XGOT},
14392 {"mabi", required_argument, NULL, OPTION_MABI},
14393 {"n32", no_argument, NULL, OPTION_N32},
14394 {"64", no_argument, NULL, OPTION_64},
14395 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14396 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14397 {"mpdr", no_argument, NULL, OPTION_PDR},
14398 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14399 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14400 #endif /* OBJ_ELF */
14402 {NULL, no_argument, NULL, 0}
14404 size_t md_longopts_size = sizeof (md_longopts);
14406 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14407 NEW_VALUE. Warn if another value was already specified. Note:
14408 we have to defer parsing the -march and -mtune arguments in order
14409 to handle 'from-abi' correctly, since the ABI might be specified
14410 in a later argument. */
14413 mips_set_option_string (const char **string_ptr, const char *new_value)
14415 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14416 as_warn (_("A different %s was already specified, is now %s"),
14417 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14420 *string_ptr = new_value;
14424 md_parse_option (int c, char *arg)
14428 case OPTION_CONSTRUCT_FLOATS:
14429 mips_disable_float_construction = 0;
14432 case OPTION_NO_CONSTRUCT_FLOATS:
14433 mips_disable_float_construction = 1;
14445 target_big_endian = 1;
14449 target_big_endian = 0;
14455 else if (arg[0] == '0')
14457 else if (arg[0] == '1')
14467 mips_debug = atoi (arg);
14471 file_mips_isa = ISA_MIPS1;
14475 file_mips_isa = ISA_MIPS2;
14479 file_mips_isa = ISA_MIPS3;
14483 file_mips_isa = ISA_MIPS4;
14487 file_mips_isa = ISA_MIPS5;
14490 case OPTION_MIPS32:
14491 file_mips_isa = ISA_MIPS32;
14494 case OPTION_MIPS32R2:
14495 file_mips_isa = ISA_MIPS32R2;
14498 case OPTION_MIPS64R2:
14499 file_mips_isa = ISA_MIPS64R2;
14502 case OPTION_MIPS64:
14503 file_mips_isa = ISA_MIPS64;
14507 mips_set_option_string (&mips_tune_string, arg);
14511 mips_set_option_string (&mips_arch_string, arg);
14515 mips_set_option_string (&mips_arch_string, "4650");
14516 mips_set_option_string (&mips_tune_string, "4650");
14519 case OPTION_NO_M4650:
14523 mips_set_option_string (&mips_arch_string, "4010");
14524 mips_set_option_string (&mips_tune_string, "4010");
14527 case OPTION_NO_M4010:
14531 mips_set_option_string (&mips_arch_string, "4100");
14532 mips_set_option_string (&mips_tune_string, "4100");
14535 case OPTION_NO_M4100:
14539 mips_set_option_string (&mips_arch_string, "3900");
14540 mips_set_option_string (&mips_tune_string, "3900");
14543 case OPTION_NO_M3900:
14547 mips_opts.ase_mdmx = 1;
14550 case OPTION_NO_MDMX:
14551 mips_opts.ase_mdmx = 0;
14555 mips_opts.ase_dsp = 1;
14556 mips_opts.ase_dspr2 = 0;
14559 case OPTION_NO_DSP:
14560 mips_opts.ase_dsp = 0;
14561 mips_opts.ase_dspr2 = 0;
14565 mips_opts.ase_dspr2 = 1;
14566 mips_opts.ase_dsp = 1;
14569 case OPTION_NO_DSPR2:
14570 mips_opts.ase_dspr2 = 0;
14571 mips_opts.ase_dsp = 0;
14575 mips_opts.ase_mt = 1;
14579 mips_opts.ase_mt = 0;
14583 mips_opts.ase_mcu = 1;
14586 case OPTION_NO_MCU:
14587 mips_opts.ase_mcu = 0;
14590 case OPTION_MICROMIPS:
14591 if (mips_opts.mips16 == 1)
14593 as_bad (_("-mmicromips cannot be used with -mips16"));
14596 mips_opts.micromips = 1;
14597 mips_no_prev_insn ();
14600 case OPTION_NO_MICROMIPS:
14601 mips_opts.micromips = 0;
14602 mips_no_prev_insn ();
14605 case OPTION_MIPS16:
14606 if (mips_opts.micromips == 1)
14608 as_bad (_("-mips16 cannot be used with -micromips"));
14611 mips_opts.mips16 = 1;
14612 mips_no_prev_insn ();
14615 case OPTION_NO_MIPS16:
14616 mips_opts.mips16 = 0;
14617 mips_no_prev_insn ();
14620 case OPTION_MIPS3D:
14621 mips_opts.ase_mips3d = 1;
14624 case OPTION_NO_MIPS3D:
14625 mips_opts.ase_mips3d = 0;
14628 case OPTION_SMARTMIPS:
14629 mips_opts.ase_smartmips = 1;
14632 case OPTION_NO_SMARTMIPS:
14633 mips_opts.ase_smartmips = 0;
14636 case OPTION_FIX_24K:
14640 case OPTION_NO_FIX_24K:
14644 case OPTION_FIX_LOONGSON2F_JUMP:
14645 mips_fix_loongson2f_jump = TRUE;
14648 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14649 mips_fix_loongson2f_jump = FALSE;
14652 case OPTION_FIX_LOONGSON2F_NOP:
14653 mips_fix_loongson2f_nop = TRUE;
14656 case OPTION_NO_FIX_LOONGSON2F_NOP:
14657 mips_fix_loongson2f_nop = FALSE;
14660 case OPTION_FIX_VR4120:
14661 mips_fix_vr4120 = 1;
14664 case OPTION_NO_FIX_VR4120:
14665 mips_fix_vr4120 = 0;
14668 case OPTION_FIX_VR4130:
14669 mips_fix_vr4130 = 1;
14672 case OPTION_NO_FIX_VR4130:
14673 mips_fix_vr4130 = 0;
14676 case OPTION_FIX_CN63XXP1:
14677 mips_fix_cn63xxp1 = TRUE;
14680 case OPTION_NO_FIX_CN63XXP1:
14681 mips_fix_cn63xxp1 = FALSE;
14684 case OPTION_RELAX_BRANCH:
14685 mips_relax_branch = 1;
14688 case OPTION_NO_RELAX_BRANCH:
14689 mips_relax_branch = 0;
14692 case OPTION_MSHARED:
14693 mips_in_shared = TRUE;
14696 case OPTION_MNO_SHARED:
14697 mips_in_shared = FALSE;
14700 case OPTION_MSYM32:
14701 mips_opts.sym32 = TRUE;
14704 case OPTION_MNO_SYM32:
14705 mips_opts.sym32 = FALSE;
14709 /* When generating ELF code, we permit -KPIC and -call_shared to
14710 select SVR4_PIC, and -non_shared to select no PIC. This is
14711 intended to be compatible with Irix 5. */
14712 case OPTION_CALL_SHARED:
14715 as_bad (_("-call_shared is supported only for ELF format"));
14718 mips_pic = SVR4_PIC;
14719 mips_abicalls = TRUE;
14722 case OPTION_CALL_NONPIC:
14725 as_bad (_("-call_nonpic is supported only for ELF format"));
14729 mips_abicalls = TRUE;
14732 case OPTION_NON_SHARED:
14735 as_bad (_("-non_shared is supported only for ELF format"));
14739 mips_abicalls = FALSE;
14742 /* The -xgot option tells the assembler to use 32 bit offsets
14743 when accessing the got in SVR4_PIC mode. It is for Irix
14748 #endif /* OBJ_ELF */
14751 g_switch_value = atoi (arg);
14755 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14759 mips_abi = O32_ABI;
14760 /* We silently ignore -32 for non-ELF targets. This greatly
14761 simplifies the construction of the MIPS GAS test cases. */
14768 as_bad (_("-n32 is supported for ELF format only"));
14771 mips_abi = N32_ABI;
14777 as_bad (_("-64 is supported for ELF format only"));
14780 mips_abi = N64_ABI;
14781 if (!support_64bit_objects())
14782 as_fatal (_("No compiled in support for 64 bit object file format"));
14784 #endif /* OBJ_ELF */
14787 file_mips_gp32 = 1;
14791 file_mips_gp32 = 0;
14795 file_mips_fp32 = 1;
14799 file_mips_fp32 = 0;
14802 case OPTION_SINGLE_FLOAT:
14803 file_mips_single_float = 1;
14806 case OPTION_DOUBLE_FLOAT:
14807 file_mips_single_float = 0;
14810 case OPTION_SOFT_FLOAT:
14811 file_mips_soft_float = 1;
14814 case OPTION_HARD_FLOAT:
14815 file_mips_soft_float = 0;
14822 as_bad (_("-mabi is supported for ELF format only"));
14825 if (strcmp (arg, "32") == 0)
14826 mips_abi = O32_ABI;
14827 else if (strcmp (arg, "o64") == 0)
14828 mips_abi = O64_ABI;
14829 else if (strcmp (arg, "n32") == 0)
14830 mips_abi = N32_ABI;
14831 else if (strcmp (arg, "64") == 0)
14833 mips_abi = N64_ABI;
14834 if (! support_64bit_objects())
14835 as_fatal (_("No compiled in support for 64 bit object file "
14838 else if (strcmp (arg, "eabi") == 0)
14839 mips_abi = EABI_ABI;
14842 as_fatal (_("invalid abi -mabi=%s"), arg);
14846 #endif /* OBJ_ELF */
14848 case OPTION_M7000_HILO_FIX:
14849 mips_7000_hilo_fix = TRUE;
14852 case OPTION_MNO_7000_HILO_FIX:
14853 mips_7000_hilo_fix = FALSE;
14857 case OPTION_MDEBUG:
14858 mips_flag_mdebug = TRUE;
14861 case OPTION_NO_MDEBUG:
14862 mips_flag_mdebug = FALSE;
14866 mips_flag_pdr = TRUE;
14869 case OPTION_NO_PDR:
14870 mips_flag_pdr = FALSE;
14873 case OPTION_MVXWORKS_PIC:
14874 mips_pic = VXWORKS_PIC;
14876 #endif /* OBJ_ELF */
14882 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
14887 /* Set up globals to generate code for the ISA or processor
14888 described by INFO. */
14891 mips_set_architecture (const struct mips_cpu_info *info)
14895 file_mips_arch = info->cpu;
14896 mips_opts.arch = info->cpu;
14897 mips_opts.isa = info->isa;
14902 /* Likewise for tuning. */
14905 mips_set_tune (const struct mips_cpu_info *info)
14908 mips_tune = info->cpu;
14913 mips_after_parse_args (void)
14915 const struct mips_cpu_info *arch_info = 0;
14916 const struct mips_cpu_info *tune_info = 0;
14918 /* GP relative stuff not working for PE */
14919 if (strncmp (TARGET_OS, "pe", 2) == 0)
14921 if (g_switch_seen && g_switch_value != 0)
14922 as_bad (_("-G not supported in this configuration."));
14923 g_switch_value = 0;
14926 if (mips_abi == NO_ABI)
14927 mips_abi = MIPS_DEFAULT_ABI;
14929 /* The following code determines the architecture and register size.
14930 Similar code was added to GCC 3.3 (see override_options() in
14931 config/mips/mips.c). The GAS and GCC code should be kept in sync
14932 as much as possible. */
14934 if (mips_arch_string != 0)
14935 arch_info = mips_parse_cpu ("-march", mips_arch_string);
14937 if (file_mips_isa != ISA_UNKNOWN)
14939 /* Handle -mipsN. At this point, file_mips_isa contains the
14940 ISA level specified by -mipsN, while arch_info->isa contains
14941 the -march selection (if any). */
14942 if (arch_info != 0)
14944 /* -march takes precedence over -mipsN, since it is more descriptive.
14945 There's no harm in specifying both as long as the ISA levels
14947 if (file_mips_isa != arch_info->isa)
14948 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
14949 mips_cpu_info_from_isa (file_mips_isa)->name,
14950 mips_cpu_info_from_isa (arch_info->isa)->name);
14953 arch_info = mips_cpu_info_from_isa (file_mips_isa);
14956 if (arch_info == 0)
14957 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
14959 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14960 as_bad (_("-march=%s is not compatible with the selected ABI"),
14963 mips_set_architecture (arch_info);
14965 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
14966 if (mips_tune_string != 0)
14967 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
14969 if (tune_info == 0)
14970 mips_set_tune (arch_info);
14972 mips_set_tune (tune_info);
14974 if (file_mips_gp32 >= 0)
14976 /* The user specified the size of the integer registers. Make sure
14977 it agrees with the ABI and ISA. */
14978 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14979 as_bad (_("-mgp64 used with a 32-bit processor"));
14980 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14981 as_bad (_("-mgp32 used with a 64-bit ABI"));
14982 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14983 as_bad (_("-mgp64 used with a 32-bit ABI"));
14987 /* Infer the integer register size from the ABI and processor.
14988 Restrict ourselves to 32-bit registers if that's all the
14989 processor has, or if the ABI cannot handle 64-bit registers. */
14990 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14991 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14994 switch (file_mips_fp32)
14998 /* No user specified float register size.
14999 ??? GAS treats single-float processors as though they had 64-bit
15000 float registers (although it complains when double-precision
15001 instructions are used). As things stand, saying they have 32-bit
15002 registers would lead to spurious "register must be even" messages.
15003 So here we assume float registers are never smaller than the
15005 if (file_mips_gp32 == 0)
15006 /* 64-bit integer registers implies 64-bit float registers. */
15007 file_mips_fp32 = 0;
15008 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15009 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15010 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15011 file_mips_fp32 = 0;
15013 /* 32-bit float registers. */
15014 file_mips_fp32 = 1;
15017 /* The user specified the size of the float registers. Check if it
15018 agrees with the ABI and ISA. */
15020 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15021 as_bad (_("-mfp64 used with a 32-bit fpu"));
15022 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15023 && !ISA_HAS_MXHC1 (mips_opts.isa))
15024 as_warn (_("-mfp64 used with a 32-bit ABI"));
15027 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15028 as_warn (_("-mfp32 used with a 64-bit ABI"));
15032 /* End of GCC-shared inference code. */
15034 /* This flag is set when we have a 64-bit capable CPU but use only
15035 32-bit wide registers. Note that EABI does not use it. */
15036 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15037 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15038 || mips_abi == O32_ABI))
15039 mips_32bitmode = 1;
15041 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15042 as_bad (_("trap exception not supported at ISA 1"));
15044 /* If the selected architecture includes support for ASEs, enable
15045 generation of code for them. */
15046 if (mips_opts.mips16 == -1)
15047 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15048 if (mips_opts.micromips == -1)
15049 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15050 if (mips_opts.ase_mips3d == -1)
15051 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15052 && file_mips_fp32 == 0) ? 1 : 0;
15053 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15054 as_bad (_("-mfp32 used with -mips3d"));
15056 if (mips_opts.ase_mdmx == -1)
15057 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15058 && file_mips_fp32 == 0) ? 1 : 0;
15059 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15060 as_bad (_("-mfp32 used with -mdmx"));
15062 if (mips_opts.ase_smartmips == -1)
15063 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15064 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15065 as_warn (_("%s ISA does not support SmartMIPS"),
15066 mips_cpu_info_from_isa (mips_opts.isa)->name);
15068 if (mips_opts.ase_dsp == -1)
15069 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15070 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15071 as_warn (_("%s ISA does not support DSP ASE"),
15072 mips_cpu_info_from_isa (mips_opts.isa)->name);
15074 if (mips_opts.ase_dspr2 == -1)
15076 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15077 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15079 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15080 as_warn (_("%s ISA does not support DSP R2 ASE"),
15081 mips_cpu_info_from_isa (mips_opts.isa)->name);
15083 if (mips_opts.ase_mt == -1)
15084 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15085 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15086 as_warn (_("%s ISA does not support MT ASE"),
15087 mips_cpu_info_from_isa (mips_opts.isa)->name);
15089 if (mips_opts.ase_mcu == -1)
15090 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15091 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15092 as_warn (_("%s ISA does not support MCU ASE"),
15093 mips_cpu_info_from_isa (mips_opts.isa)->name);
15095 file_mips_isa = mips_opts.isa;
15096 file_ase_mips3d = mips_opts.ase_mips3d;
15097 file_ase_mdmx = mips_opts.ase_mdmx;
15098 file_ase_smartmips = mips_opts.ase_smartmips;
15099 file_ase_dsp = mips_opts.ase_dsp;
15100 file_ase_dspr2 = mips_opts.ase_dspr2;
15101 file_ase_mt = mips_opts.ase_mt;
15102 mips_opts.gp32 = file_mips_gp32;
15103 mips_opts.fp32 = file_mips_fp32;
15104 mips_opts.soft_float = file_mips_soft_float;
15105 mips_opts.single_float = file_mips_single_float;
15107 if (mips_flag_mdebug < 0)
15109 #ifdef OBJ_MAYBE_ECOFF
15110 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15111 mips_flag_mdebug = 1;
15113 #endif /* OBJ_MAYBE_ECOFF */
15114 mips_flag_mdebug = 0;
15119 mips_init_after_args (void)
15121 /* initialize opcodes */
15122 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15123 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15127 md_pcrel_from (fixS *fixP)
15129 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15130 switch (fixP->fx_r_type)
15132 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15133 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15134 /* Return the address of the delay slot. */
15137 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15138 case BFD_RELOC_MICROMIPS_JMP:
15139 case BFD_RELOC_16_PCREL_S2:
15140 case BFD_RELOC_MIPS_JMP:
15141 /* Return the address of the delay slot. */
15145 /* We have no relocation type for PC relative MIPS16 instructions. */
15146 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15147 as_bad_where (fixP->fx_file, fixP->fx_line,
15148 _("PC relative MIPS16 instruction references a different section"));
15153 /* This is called before the symbol table is processed. In order to
15154 work with gcc when using mips-tfile, we must keep all local labels.
15155 However, in other cases, we want to discard them. If we were
15156 called with -g, but we didn't see any debugging information, it may
15157 mean that gcc is smuggling debugging information through to
15158 mips-tfile, in which case we must generate all local labels. */
15161 mips_frob_file_before_adjust (void)
15163 #ifndef NO_ECOFF_DEBUGGING
15164 if (ECOFF_DEBUGGING
15166 && ! ecoff_debugging_seen)
15167 flag_keep_locals = 1;
15171 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15172 the corresponding LO16 reloc. This is called before md_apply_fix and
15173 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15174 relocation operators.
15176 For our purposes, a %lo() expression matches a %got() or %hi()
15179 (a) it refers to the same symbol; and
15180 (b) the offset applied in the %lo() expression is no lower than
15181 the offset applied in the %got() or %hi().
15183 (b) allows us to cope with code like:
15186 lh $4,%lo(foo+2)($4)
15188 ...which is legal on RELA targets, and has a well-defined behaviour
15189 if the user knows that adding 2 to "foo" will not induce a carry to
15192 When several %lo()s match a particular %got() or %hi(), we use the
15193 following rules to distinguish them:
15195 (1) %lo()s with smaller offsets are a better match than %lo()s with
15198 (2) %lo()s with no matching %got() or %hi() are better than those
15199 that already have a matching %got() or %hi().
15201 (3) later %lo()s are better than earlier %lo()s.
15203 These rules are applied in order.
15205 (1) means, among other things, that %lo()s with identical offsets are
15206 chosen if they exist.
15208 (2) means that we won't associate several high-part relocations with
15209 the same low-part relocation unless there's no alternative. Having
15210 several high parts for the same low part is a GNU extension; this rule
15211 allows careful users to avoid it.
15213 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15214 with the last high-part relocation being at the front of the list.
15215 It therefore makes sense to choose the last matching low-part
15216 relocation, all other things being equal. It's also easier
15217 to code that way. */
15220 mips_frob_file (void)
15222 struct mips_hi_fixup *l;
15223 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15225 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15227 segment_info_type *seginfo;
15228 bfd_boolean matched_lo_p;
15229 fixS **hi_pos, **lo_pos, **pos;
15231 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15233 /* If a GOT16 relocation turns out to be against a global symbol,
15234 there isn't supposed to be a matching LO. */
15235 if (got16_reloc_p (l->fixp->fx_r_type)
15236 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
15239 /* Check quickly whether the next fixup happens to be a matching %lo. */
15240 if (fixup_has_matching_lo_p (l->fixp))
15243 seginfo = seg_info (l->seg);
15245 /* Set HI_POS to the position of this relocation in the chain.
15246 Set LO_POS to the position of the chosen low-part relocation.
15247 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15248 relocation that matches an immediately-preceding high-part
15252 matched_lo_p = FALSE;
15253 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15255 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15257 if (*pos == l->fixp)
15260 if ((*pos)->fx_r_type == looking_for_rtype
15261 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15262 && (*pos)->fx_offset >= l->fixp->fx_offset
15264 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15266 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15269 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15270 && fixup_has_matching_lo_p (*pos));
15273 /* If we found a match, remove the high-part relocation from its
15274 current position and insert it before the low-part relocation.
15275 Make the offsets match so that fixup_has_matching_lo_p()
15278 We don't warn about unmatched high-part relocations since some
15279 versions of gcc have been known to emit dead "lui ...%hi(...)"
15281 if (lo_pos != NULL)
15283 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15284 if (l->fixp->fx_next != *lo_pos)
15286 *hi_pos = l->fixp->fx_next;
15287 l->fixp->fx_next = *lo_pos;
15294 /* We may have combined relocations without symbols in the N32/N64 ABI.
15295 We have to prevent gas from dropping them. */
15298 mips_force_relocation (fixS *fixp)
15300 if (generic_force_reloc (fixp))
15303 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15304 so that the linker relaxation can update targets. */
15305 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15306 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15307 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15311 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
15312 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
15313 || hi16_reloc_p (fixp->fx_r_type)
15314 || lo16_reloc_p (fixp->fx_r_type)))
15320 /* Apply a fixup to the object file. */
15323 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15327 reloc_howto_type *howto;
15329 /* We ignore generic BFD relocations we don't know about. */
15330 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15334 gas_assert (fixP->fx_size == 2
15335 || fixP->fx_size == 4
15336 || fixP->fx_r_type == BFD_RELOC_16
15337 || fixP->fx_r_type == BFD_RELOC_64
15338 || fixP->fx_r_type == BFD_RELOC_CTOR
15339 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15340 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15341 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15342 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15343 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15345 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
15347 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15348 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15349 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15350 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15352 /* Don't treat parts of a composite relocation as done. There are two
15355 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15356 should nevertheless be emitted if the first part is.
15358 (2) In normal usage, composite relocations are never assembly-time
15359 constants. The easiest way of dealing with the pathological
15360 exceptions is to generate a relocation against STN_UNDEF and
15361 leave everything up to the linker. */
15362 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15365 switch (fixP->fx_r_type)
15367 case BFD_RELOC_MIPS_TLS_GD:
15368 case BFD_RELOC_MIPS_TLS_LDM:
15369 case BFD_RELOC_MIPS_TLS_DTPREL32:
15370 case BFD_RELOC_MIPS_TLS_DTPREL64:
15371 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15372 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15373 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15374 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15375 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15376 case BFD_RELOC_MICROMIPS_TLS_GD:
15377 case BFD_RELOC_MICROMIPS_TLS_LDM:
15378 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15379 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15380 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15381 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15382 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15383 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15386 case BFD_RELOC_MIPS_JMP:
15387 case BFD_RELOC_MIPS_SHIFT5:
15388 case BFD_RELOC_MIPS_SHIFT6:
15389 case BFD_RELOC_MIPS_GOT_DISP:
15390 case BFD_RELOC_MIPS_GOT_PAGE:
15391 case BFD_RELOC_MIPS_GOT_OFST:
15392 case BFD_RELOC_MIPS_SUB:
15393 case BFD_RELOC_MIPS_INSERT_A:
15394 case BFD_RELOC_MIPS_INSERT_B:
15395 case BFD_RELOC_MIPS_DELETE:
15396 case BFD_RELOC_MIPS_HIGHEST:
15397 case BFD_RELOC_MIPS_HIGHER:
15398 case BFD_RELOC_MIPS_SCN_DISP:
15399 case BFD_RELOC_MIPS_REL16:
15400 case BFD_RELOC_MIPS_RELGOT:
15401 case BFD_RELOC_MIPS_JALR:
15402 case BFD_RELOC_HI16:
15403 case BFD_RELOC_HI16_S:
15404 case BFD_RELOC_GPREL16:
15405 case BFD_RELOC_MIPS_LITERAL:
15406 case BFD_RELOC_MIPS_CALL16:
15407 case BFD_RELOC_MIPS_GOT16:
15408 case BFD_RELOC_GPREL32:
15409 case BFD_RELOC_MIPS_GOT_HI16:
15410 case BFD_RELOC_MIPS_GOT_LO16:
15411 case BFD_RELOC_MIPS_CALL_HI16:
15412 case BFD_RELOC_MIPS_CALL_LO16:
15413 case BFD_RELOC_MIPS16_GPREL:
15414 case BFD_RELOC_MIPS16_GOT16:
15415 case BFD_RELOC_MIPS16_CALL16:
15416 case BFD_RELOC_MIPS16_HI16:
15417 case BFD_RELOC_MIPS16_HI16_S:
15418 case BFD_RELOC_MIPS16_JMP:
15419 case BFD_RELOC_MICROMIPS_JMP:
15420 case BFD_RELOC_MICROMIPS_GOT_DISP:
15421 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15422 case BFD_RELOC_MICROMIPS_GOT_OFST:
15423 case BFD_RELOC_MICROMIPS_SUB:
15424 case BFD_RELOC_MICROMIPS_HIGHEST:
15425 case BFD_RELOC_MICROMIPS_HIGHER:
15426 case BFD_RELOC_MICROMIPS_SCN_DISP:
15427 case BFD_RELOC_MICROMIPS_JALR:
15428 case BFD_RELOC_MICROMIPS_HI16:
15429 case BFD_RELOC_MICROMIPS_HI16_S:
15430 case BFD_RELOC_MICROMIPS_GPREL16:
15431 case BFD_RELOC_MICROMIPS_LITERAL:
15432 case BFD_RELOC_MICROMIPS_CALL16:
15433 case BFD_RELOC_MICROMIPS_GOT16:
15434 case BFD_RELOC_MICROMIPS_GOT_HI16:
15435 case BFD_RELOC_MICROMIPS_GOT_LO16:
15436 case BFD_RELOC_MICROMIPS_CALL_HI16:
15437 case BFD_RELOC_MICROMIPS_CALL_LO16:
15438 /* Nothing needed to do. The value comes from the reloc entry. */
15442 /* This is handled like BFD_RELOC_32, but we output a sign
15443 extended value if we are only 32 bits. */
15446 if (8 <= sizeof (valueT))
15447 md_number_to_chars ((char *) buf, *valP, 8);
15452 if ((*valP & 0x80000000) != 0)
15456 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
15458 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
15464 case BFD_RELOC_RVA:
15467 /* If we are deleting this reloc entry, we must fill in the
15468 value now. This can happen if we have a .word which is not
15469 resolved when it appears but is later defined. */
15471 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
15474 case BFD_RELOC_LO16:
15475 case BFD_RELOC_MIPS16_LO16:
15476 case BFD_RELOC_MICROMIPS_LO16:
15477 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
15478 may be safe to remove, but if so it's not obvious. */
15479 /* When handling an embedded PIC switch statement, we can wind
15480 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
15483 if (*valP + 0x8000 > 0xffff)
15484 as_bad_where (fixP->fx_file, fixP->fx_line,
15485 _("relocation overflow"));
15486 /* 32-bit microMIPS instructions are divided into two halfwords.
15487 Relocations always refer to the second halfword, regardless
15489 if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16)
15491 md_number_to_chars ((char *) buf, *valP, 2);
15495 case BFD_RELOC_16_PCREL_S2:
15496 if ((*valP & 0x3) != 0)
15497 as_bad_where (fixP->fx_file, fixP->fx_line,
15498 _("Branch to misaligned address (%lx)"), (long) *valP);
15500 /* We need to save the bits in the instruction since fixup_segment()
15501 might be deleting the relocation entry (i.e., a branch within
15502 the current segment). */
15503 if (! fixP->fx_done)
15506 /* Update old instruction data. */
15507 if (target_big_endian)
15508 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
15510 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
15512 if (*valP + 0x20000 <= 0x3ffff)
15514 insn |= (*valP >> 2) & 0xffff;
15515 md_number_to_chars ((char *) buf, insn, 4);
15517 else if (mips_pic == NO_PIC
15519 && fixP->fx_frag->fr_address >= text_section->vma
15520 && (fixP->fx_frag->fr_address
15521 < text_section->vma + bfd_get_section_size (text_section))
15522 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15523 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15524 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15526 /* The branch offset is too large. If this is an
15527 unconditional branch, and we are not generating PIC code,
15528 we can convert it to an absolute jump instruction. */
15529 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15530 insn = 0x0c000000; /* jal */
15532 insn = 0x08000000; /* j */
15533 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15535 fixP->fx_addsy = section_symbol (text_section);
15536 *valP += md_pcrel_from (fixP);
15537 md_number_to_chars ((char *) buf, insn, 4);
15541 /* If we got here, we have branch-relaxation disabled,
15542 and there's nothing we can do to fix this instruction
15543 without turning it into a longer sequence. */
15544 as_bad_where (fixP->fx_file, fixP->fx_line,
15545 _("Branch out of range"));
15549 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15550 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15551 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15552 /* We adjust the offset back to even. */
15553 if ((*valP & 0x1) != 0)
15556 if (! fixP->fx_done)
15559 /* Should never visit here, because we keep the relocation. */
15563 case BFD_RELOC_VTABLE_INHERIT:
15566 && !S_IS_DEFINED (fixP->fx_addsy)
15567 && !S_IS_WEAK (fixP->fx_addsy))
15568 S_SET_WEAK (fixP->fx_addsy);
15571 case BFD_RELOC_VTABLE_ENTRY:
15579 /* Remember value for tc_gen_reloc. */
15580 fixP->fx_addnumber = *valP;
15590 name = input_line_pointer;
15591 c = get_symbol_end ();
15592 p = (symbolS *) symbol_find_or_make (name);
15593 *input_line_pointer = c;
15597 /* Align the current frag to a given power of two. If a particular
15598 fill byte should be used, FILL points to an integer that contains
15599 that byte, otherwise FILL is null.
15601 The MIPS assembler also automatically adjusts any preceding
15605 mips_align (int to, int *fill, symbolS *label)
15607 mips_emit_delays ();
15608 mips_record_compressed_mode ();
15609 if (fill == NULL && subseg_text_p (now_seg))
15610 frag_align_code (to, 0);
15612 frag_align (to, fill ? *fill : 0, 0);
15613 record_alignment (now_seg, to);
15616 gas_assert (S_GET_SEGMENT (label) == now_seg);
15617 symbol_set_frag (label, frag_now);
15618 S_SET_VALUE (label, (valueT) frag_now_fix ());
15622 /* Align to a given power of two. .align 0 turns off the automatic
15623 alignment used by the data creating pseudo-ops. */
15626 s_align (int x ATTRIBUTE_UNUSED)
15628 int temp, fill_value, *fill_ptr;
15629 long max_alignment = 28;
15631 /* o Note that the assembler pulls down any immediately preceding label
15632 to the aligned address.
15633 o It's not documented but auto alignment is reinstated by
15634 a .align pseudo instruction.
15635 o Note also that after auto alignment is turned off the mips assembler
15636 issues an error on attempt to assemble an improperly aligned data item.
15639 temp = get_absolute_expression ();
15640 if (temp > max_alignment)
15641 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15644 as_warn (_("Alignment negative: 0 assumed."));
15647 if (*input_line_pointer == ',')
15649 ++input_line_pointer;
15650 fill_value = get_absolute_expression ();
15651 fill_ptr = &fill_value;
15657 segment_info_type *si = seg_info (now_seg);
15658 struct insn_label_list *l = si->label_list;
15659 /* Auto alignment should be switched on by next section change. */
15661 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
15668 demand_empty_rest_of_line ();
15672 s_change_sec (int sec)
15677 /* The ELF backend needs to know that we are changing sections, so
15678 that .previous works correctly. We could do something like check
15679 for an obj_section_change_hook macro, but that might be confusing
15680 as it would not be appropriate to use it in the section changing
15681 functions in read.c, since obj-elf.c intercepts those. FIXME:
15682 This should be cleaner, somehow. */
15684 obj_elf_section_change_hook ();
15687 mips_emit_delays ();
15698 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15699 demand_empty_rest_of_line ();
15703 seg = subseg_new (RDATA_SECTION_NAME,
15704 (subsegT) get_absolute_expression ());
15707 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15708 | SEC_READONLY | SEC_RELOC
15710 if (strncmp (TARGET_OS, "elf", 3) != 0)
15711 record_alignment (seg, 4);
15713 demand_empty_rest_of_line ();
15717 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15720 bfd_set_section_flags (stdoutput, seg,
15721 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15722 if (strncmp (TARGET_OS, "elf", 3) != 0)
15723 record_alignment (seg, 4);
15725 demand_empty_rest_of_line ();
15729 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15732 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15733 if (strncmp (TARGET_OS, "elf", 3) != 0)
15734 record_alignment (seg, 4);
15736 demand_empty_rest_of_line ();
15744 s_change_section (int ignore ATTRIBUTE_UNUSED)
15747 char *section_name;
15752 int section_entry_size;
15753 int section_alignment;
15758 section_name = input_line_pointer;
15759 c = get_symbol_end ();
15761 next_c = *(input_line_pointer + 1);
15763 /* Do we have .section Name<,"flags">? */
15764 if (c != ',' || (c == ',' && next_c == '"'))
15766 /* just after name is now '\0'. */
15767 *input_line_pointer = c;
15768 input_line_pointer = section_name;
15769 obj_elf_section (ignore);
15772 input_line_pointer++;
15774 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15776 section_type = get_absolute_expression ();
15779 if (*input_line_pointer++ == ',')
15780 section_flag = get_absolute_expression ();
15783 if (*input_line_pointer++ == ',')
15784 section_entry_size = get_absolute_expression ();
15786 section_entry_size = 0;
15787 if (*input_line_pointer++ == ',')
15788 section_alignment = get_absolute_expression ();
15790 section_alignment = 0;
15791 /* FIXME: really ignore? */
15792 (void) section_alignment;
15794 section_name = xstrdup (section_name);
15796 /* When using the generic form of .section (as implemented by obj-elf.c),
15797 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15798 traditionally had to fall back on the more common @progbits instead.
15800 There's nothing really harmful in this, since bfd will correct
15801 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15802 means that, for backwards compatibility, the special_section entries
15803 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15805 Even so, we shouldn't force users of the MIPS .section syntax to
15806 incorrectly label the sections as SHT_PROGBITS. The best compromise
15807 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15808 generic type-checking code. */
15809 if (section_type == SHT_MIPS_DWARF)
15810 section_type = SHT_PROGBITS;
15812 obj_elf_change_section (section_name, section_type, section_flag,
15813 section_entry_size, 0, 0, 0);
15815 if (now_seg->name != section_name)
15816 free (section_name);
15817 #endif /* OBJ_ELF */
15821 mips_enable_auto_align (void)
15827 s_cons (int log_size)
15829 segment_info_type *si = seg_info (now_seg);
15830 struct insn_label_list *l = si->label_list;
15833 label = l != NULL ? l->label : NULL;
15834 mips_emit_delays ();
15835 if (log_size > 0 && auto_align)
15836 mips_align (log_size, 0, label);
15837 cons (1 << log_size);
15838 mips_clear_insn_labels ();
15842 s_float_cons (int type)
15844 segment_info_type *si = seg_info (now_seg);
15845 struct insn_label_list *l = si->label_list;
15848 label = l != NULL ? l->label : NULL;
15850 mips_emit_delays ();
15855 mips_align (3, 0, label);
15857 mips_align (2, 0, label);
15861 mips_clear_insn_labels ();
15864 /* Handle .globl. We need to override it because on Irix 5 you are
15867 where foo is an undefined symbol, to mean that foo should be
15868 considered to be the address of a function. */
15871 s_mips_globl (int x ATTRIBUTE_UNUSED)
15880 name = input_line_pointer;
15881 c = get_symbol_end ();
15882 symbolP = symbol_find_or_make (name);
15883 S_SET_EXTERNAL (symbolP);
15885 *input_line_pointer = c;
15886 SKIP_WHITESPACE ();
15888 /* On Irix 5, every global symbol that is not explicitly labelled as
15889 being a function is apparently labelled as being an object. */
15892 if (!is_end_of_line[(unsigned char) *input_line_pointer]
15893 && (*input_line_pointer != ','))
15898 secname = input_line_pointer;
15899 c = get_symbol_end ();
15900 sec = bfd_get_section_by_name (stdoutput, secname);
15902 as_bad (_("%s: no such section"), secname);
15903 *input_line_pointer = c;
15905 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
15906 flag = BSF_FUNCTION;
15909 symbol_get_bfdsym (symbolP)->flags |= flag;
15911 c = *input_line_pointer;
15914 input_line_pointer++;
15915 SKIP_WHITESPACE ();
15916 if (is_end_of_line[(unsigned char) *input_line_pointer])
15922 demand_empty_rest_of_line ();
15926 s_option (int x ATTRIBUTE_UNUSED)
15931 opt = input_line_pointer;
15932 c = get_symbol_end ();
15936 /* FIXME: What does this mean? */
15938 else if (strncmp (opt, "pic", 3) == 0)
15942 i = atoi (opt + 3);
15947 mips_pic = SVR4_PIC;
15948 mips_abicalls = TRUE;
15951 as_bad (_(".option pic%d not supported"), i);
15953 if (mips_pic == SVR4_PIC)
15955 if (g_switch_seen && g_switch_value != 0)
15956 as_warn (_("-G may not be used with SVR4 PIC code"));
15957 g_switch_value = 0;
15958 bfd_set_gp_size (stdoutput, 0);
15962 as_warn (_("Unrecognized option \"%s\""), opt);
15964 *input_line_pointer = c;
15965 demand_empty_rest_of_line ();
15968 /* This structure is used to hold a stack of .set values. */
15970 struct mips_option_stack
15972 struct mips_option_stack *next;
15973 struct mips_set_options options;
15976 static struct mips_option_stack *mips_opts_stack;
15978 /* Handle the .set pseudo-op. */
15981 s_mipsset (int x ATTRIBUTE_UNUSED)
15983 char *name = input_line_pointer, ch;
15985 while (!is_end_of_line[(unsigned char) *input_line_pointer])
15986 ++input_line_pointer;
15987 ch = *input_line_pointer;
15988 *input_line_pointer = '\0';
15990 if (strcmp (name, "reorder") == 0)
15992 if (mips_opts.noreorder)
15995 else if (strcmp (name, "noreorder") == 0)
15997 if (!mips_opts.noreorder)
15998 start_noreorder ();
16000 else if (strncmp (name, "at=", 3) == 0)
16002 char *s = name + 3;
16004 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16005 as_bad (_("Unrecognized register name `%s'"), s);
16007 else if (strcmp (name, "at") == 0)
16009 mips_opts.at = ATREG;
16011 else if (strcmp (name, "noat") == 0)
16013 mips_opts.at = ZERO;
16015 else if (strcmp (name, "macro") == 0)
16017 mips_opts.warn_about_macros = 0;
16019 else if (strcmp (name, "nomacro") == 0)
16021 if (mips_opts.noreorder == 0)
16022 as_bad (_("`noreorder' must be set before `nomacro'"));
16023 mips_opts.warn_about_macros = 1;
16025 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16027 mips_opts.nomove = 0;
16029 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16031 mips_opts.nomove = 1;
16033 else if (strcmp (name, "bopt") == 0)
16035 mips_opts.nobopt = 0;
16037 else if (strcmp (name, "nobopt") == 0)
16039 mips_opts.nobopt = 1;
16041 else if (strcmp (name, "gp=default") == 0)
16042 mips_opts.gp32 = file_mips_gp32;
16043 else if (strcmp (name, "gp=32") == 0)
16044 mips_opts.gp32 = 1;
16045 else if (strcmp (name, "gp=64") == 0)
16047 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16048 as_warn (_("%s isa does not support 64-bit registers"),
16049 mips_cpu_info_from_isa (mips_opts.isa)->name);
16050 mips_opts.gp32 = 0;
16052 else if (strcmp (name, "fp=default") == 0)
16053 mips_opts.fp32 = file_mips_fp32;
16054 else if (strcmp (name, "fp=32") == 0)
16055 mips_opts.fp32 = 1;
16056 else if (strcmp (name, "fp=64") == 0)
16058 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16059 as_warn (_("%s isa does not support 64-bit floating point registers"),
16060 mips_cpu_info_from_isa (mips_opts.isa)->name);
16061 mips_opts.fp32 = 0;
16063 else if (strcmp (name, "softfloat") == 0)
16064 mips_opts.soft_float = 1;
16065 else if (strcmp (name, "hardfloat") == 0)
16066 mips_opts.soft_float = 0;
16067 else if (strcmp (name, "singlefloat") == 0)
16068 mips_opts.single_float = 1;
16069 else if (strcmp (name, "doublefloat") == 0)
16070 mips_opts.single_float = 0;
16071 else if (strcmp (name, "mips16") == 0
16072 || strcmp (name, "MIPS-16") == 0)
16074 if (mips_opts.micromips == 1)
16075 as_fatal (_("`mips16' cannot be used with `micromips'"));
16076 mips_opts.mips16 = 1;
16078 else if (strcmp (name, "nomips16") == 0
16079 || strcmp (name, "noMIPS-16") == 0)
16080 mips_opts.mips16 = 0;
16081 else if (strcmp (name, "micromips") == 0)
16083 if (mips_opts.mips16 == 1)
16084 as_fatal (_("`micromips' cannot be used with `mips16'"));
16085 mips_opts.micromips = 1;
16087 else if (strcmp (name, "nomicromips") == 0)
16088 mips_opts.micromips = 0;
16089 else if (strcmp (name, "smartmips") == 0)
16091 if (!ISA_SUPPORTS_SMARTMIPS)
16092 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16093 mips_cpu_info_from_isa (mips_opts.isa)->name);
16094 mips_opts.ase_smartmips = 1;
16096 else if (strcmp (name, "nosmartmips") == 0)
16097 mips_opts.ase_smartmips = 0;
16098 else if (strcmp (name, "mips3d") == 0)
16099 mips_opts.ase_mips3d = 1;
16100 else if (strcmp (name, "nomips3d") == 0)
16101 mips_opts.ase_mips3d = 0;
16102 else if (strcmp (name, "mdmx") == 0)
16103 mips_opts.ase_mdmx = 1;
16104 else if (strcmp (name, "nomdmx") == 0)
16105 mips_opts.ase_mdmx = 0;
16106 else if (strcmp (name, "dsp") == 0)
16108 if (!ISA_SUPPORTS_DSP_ASE)
16109 as_warn (_("%s ISA does not support DSP ASE"),
16110 mips_cpu_info_from_isa (mips_opts.isa)->name);
16111 mips_opts.ase_dsp = 1;
16112 mips_opts.ase_dspr2 = 0;
16114 else if (strcmp (name, "nodsp") == 0)
16116 mips_opts.ase_dsp = 0;
16117 mips_opts.ase_dspr2 = 0;
16119 else if (strcmp (name, "dspr2") == 0)
16121 if (!ISA_SUPPORTS_DSPR2_ASE)
16122 as_warn (_("%s ISA does not support DSP R2 ASE"),
16123 mips_cpu_info_from_isa (mips_opts.isa)->name);
16124 mips_opts.ase_dspr2 = 1;
16125 mips_opts.ase_dsp = 1;
16127 else if (strcmp (name, "nodspr2") == 0)
16129 mips_opts.ase_dspr2 = 0;
16130 mips_opts.ase_dsp = 0;
16132 else if (strcmp (name, "mt") == 0)
16134 if (!ISA_SUPPORTS_MT_ASE)
16135 as_warn (_("%s ISA does not support MT ASE"),
16136 mips_cpu_info_from_isa (mips_opts.isa)->name);
16137 mips_opts.ase_mt = 1;
16139 else if (strcmp (name, "nomt") == 0)
16140 mips_opts.ase_mt = 0;
16141 else if (strcmp (name, "mcu") == 0)
16142 mips_opts.ase_mcu = 1;
16143 else if (strcmp (name, "nomcu") == 0)
16144 mips_opts.ase_mcu = 0;
16145 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16149 /* Permit the user to change the ISA and architecture on the fly.
16150 Needless to say, misuse can cause serious problems. */
16151 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16154 mips_opts.isa = file_mips_isa;
16155 mips_opts.arch = file_mips_arch;
16157 else if (strncmp (name, "arch=", 5) == 0)
16159 const struct mips_cpu_info *p;
16161 p = mips_parse_cpu("internal use", name + 5);
16163 as_bad (_("unknown architecture %s"), name + 5);
16166 mips_opts.arch = p->cpu;
16167 mips_opts.isa = p->isa;
16170 else if (strncmp (name, "mips", 4) == 0)
16172 const struct mips_cpu_info *p;
16174 p = mips_parse_cpu("internal use", name);
16176 as_bad (_("unknown ISA level %s"), name + 4);
16179 mips_opts.arch = p->cpu;
16180 mips_opts.isa = p->isa;
16184 as_bad (_("unknown ISA or architecture %s"), name);
16186 switch (mips_opts.isa)
16194 mips_opts.gp32 = 1;
16195 mips_opts.fp32 = 1;
16202 mips_opts.gp32 = 0;
16203 mips_opts.fp32 = 0;
16206 as_bad (_("unknown ISA level %s"), name + 4);
16211 mips_opts.gp32 = file_mips_gp32;
16212 mips_opts.fp32 = file_mips_fp32;
16215 else if (strcmp (name, "autoextend") == 0)
16216 mips_opts.noautoextend = 0;
16217 else if (strcmp (name, "noautoextend") == 0)
16218 mips_opts.noautoextend = 1;
16219 else if (strcmp (name, "push") == 0)
16221 struct mips_option_stack *s;
16223 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16224 s->next = mips_opts_stack;
16225 s->options = mips_opts;
16226 mips_opts_stack = s;
16228 else if (strcmp (name, "pop") == 0)
16230 struct mips_option_stack *s;
16232 s = mips_opts_stack;
16234 as_bad (_(".set pop with no .set push"));
16237 /* If we're changing the reorder mode we need to handle
16238 delay slots correctly. */
16239 if (s->options.noreorder && ! mips_opts.noreorder)
16240 start_noreorder ();
16241 else if (! s->options.noreorder && mips_opts.noreorder)
16244 mips_opts = s->options;
16245 mips_opts_stack = s->next;
16249 else if (strcmp (name, "sym32") == 0)
16250 mips_opts.sym32 = TRUE;
16251 else if (strcmp (name, "nosym32") == 0)
16252 mips_opts.sym32 = FALSE;
16253 else if (strchr (name, ','))
16255 /* Generic ".set" directive; use the generic handler. */
16256 *input_line_pointer = ch;
16257 input_line_pointer = name;
16263 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16265 *input_line_pointer = ch;
16266 demand_empty_rest_of_line ();
16269 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16270 .option pic2. It means to generate SVR4 PIC calls. */
16273 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16275 mips_pic = SVR4_PIC;
16276 mips_abicalls = TRUE;
16278 if (g_switch_seen && g_switch_value != 0)
16279 as_warn (_("-G may not be used with SVR4 PIC code"));
16280 g_switch_value = 0;
16282 bfd_set_gp_size (stdoutput, 0);
16283 demand_empty_rest_of_line ();
16286 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16287 PIC code. It sets the $gp register for the function based on the
16288 function address, which is in the register named in the argument.
16289 This uses a relocation against _gp_disp, which is handled specially
16290 by the linker. The result is:
16291 lui $gp,%hi(_gp_disp)
16292 addiu $gp,$gp,%lo(_gp_disp)
16293 addu $gp,$gp,.cpload argument
16294 The .cpload argument is normally $25 == $t9.
16296 The -mno-shared option changes this to:
16297 lui $gp,%hi(__gnu_local_gp)
16298 addiu $gp,$gp,%lo(__gnu_local_gp)
16299 and the argument is ignored. This saves an instruction, but the
16300 resulting code is not position independent; it uses an absolute
16301 address for __gnu_local_gp. Thus code assembled with -mno-shared
16302 can go into an ordinary executable, but not into a shared library. */
16305 s_cpload (int ignore ATTRIBUTE_UNUSED)
16311 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16312 .cpload is ignored. */
16313 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16319 /* .cpload should be in a .set noreorder section. */
16320 if (mips_opts.noreorder == 0)
16321 as_warn (_(".cpload not in noreorder section"));
16323 reg = tc_get_register (0);
16325 /* If we need to produce a 64-bit address, we are better off using
16326 the default instruction sequence. */
16327 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16329 ex.X_op = O_symbol;
16330 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16332 ex.X_op_symbol = NULL;
16333 ex.X_add_number = 0;
16335 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16336 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16339 macro_build_lui (&ex, mips_gp_register);
16340 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16341 mips_gp_register, BFD_RELOC_LO16);
16343 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16344 mips_gp_register, reg);
16347 demand_empty_rest_of_line ();
16350 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16351 .cpsetup $reg1, offset|$reg2, label
16353 If offset is given, this results in:
16354 sd $gp, offset($sp)
16355 lui $gp, %hi(%neg(%gp_rel(label)))
16356 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16357 daddu $gp, $gp, $reg1
16359 If $reg2 is given, this results in:
16360 daddu $reg2, $gp, $0
16361 lui $gp, %hi(%neg(%gp_rel(label)))
16362 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16363 daddu $gp, $gp, $reg1
16364 $reg1 is normally $25 == $t9.
16366 The -mno-shared option replaces the last three instructions with
16368 addiu $gp,$gp,%lo(_gp) */
16371 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16373 expressionS ex_off;
16374 expressionS ex_sym;
16377 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16378 We also need NewABI support. */
16379 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16385 reg1 = tc_get_register (0);
16386 SKIP_WHITESPACE ();
16387 if (*input_line_pointer != ',')
16389 as_bad (_("missing argument separator ',' for .cpsetup"));
16393 ++input_line_pointer;
16394 SKIP_WHITESPACE ();
16395 if (*input_line_pointer == '$')
16397 mips_cpreturn_register = tc_get_register (0);
16398 mips_cpreturn_offset = -1;
16402 mips_cpreturn_offset = get_absolute_expression ();
16403 mips_cpreturn_register = -1;
16405 SKIP_WHITESPACE ();
16406 if (*input_line_pointer != ',')
16408 as_bad (_("missing argument separator ',' for .cpsetup"));
16412 ++input_line_pointer;
16413 SKIP_WHITESPACE ();
16414 expression (&ex_sym);
16417 if (mips_cpreturn_register == -1)
16419 ex_off.X_op = O_constant;
16420 ex_off.X_add_symbol = NULL;
16421 ex_off.X_op_symbol = NULL;
16422 ex_off.X_add_number = mips_cpreturn_offset;
16424 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16425 BFD_RELOC_LO16, SP);
16428 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16429 mips_gp_register, 0);
16431 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16433 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16434 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16437 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16438 mips_gp_register, -1, BFD_RELOC_GPREL16,
16439 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16441 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16442 mips_gp_register, reg1);
16448 ex.X_op = O_symbol;
16449 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16450 ex.X_op_symbol = NULL;
16451 ex.X_add_number = 0;
16453 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16454 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16456 macro_build_lui (&ex, mips_gp_register);
16457 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16458 mips_gp_register, BFD_RELOC_LO16);
16463 demand_empty_rest_of_line ();
16467 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16469 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16470 .cplocal is ignored. */
16471 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16477 mips_gp_register = tc_get_register (0);
16478 demand_empty_rest_of_line ();
16481 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16482 offset from $sp. The offset is remembered, and after making a PIC
16483 call $gp is restored from that location. */
16486 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16490 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16491 .cprestore is ignored. */
16492 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16498 mips_cprestore_offset = get_absolute_expression ();
16499 mips_cprestore_valid = 1;
16501 ex.X_op = O_constant;
16502 ex.X_add_symbol = NULL;
16503 ex.X_op_symbol = NULL;
16504 ex.X_add_number = mips_cprestore_offset;
16507 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16508 SP, HAVE_64BIT_ADDRESSES);
16511 demand_empty_rest_of_line ();
16514 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16515 was given in the preceding .cpsetup, it results in:
16516 ld $gp, offset($sp)
16518 If a register $reg2 was given there, it results in:
16519 daddu $gp, $reg2, $0 */
16522 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16526 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16527 We also need NewABI support. */
16528 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16535 if (mips_cpreturn_register == -1)
16537 ex.X_op = O_constant;
16538 ex.X_add_symbol = NULL;
16539 ex.X_op_symbol = NULL;
16540 ex.X_add_number = mips_cpreturn_offset;
16542 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16545 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16546 mips_cpreturn_register, 0);
16549 demand_empty_rest_of_line ();
16552 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
16553 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
16554 use in DWARF debug information. */
16557 s_dtprel_internal (size_t bytes)
16564 if (ex.X_op != O_symbol)
16566 as_bad (_("Unsupported use of %s"), (bytes == 8
16569 ignore_rest_of_line ();
16572 p = frag_more (bytes);
16573 md_number_to_chars (p, 0, bytes);
16574 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
16576 ? BFD_RELOC_MIPS_TLS_DTPREL64
16577 : BFD_RELOC_MIPS_TLS_DTPREL32));
16579 demand_empty_rest_of_line ();
16582 /* Handle .dtprelword. */
16585 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16587 s_dtprel_internal (4);
16590 /* Handle .dtpreldword. */
16593 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16595 s_dtprel_internal (8);
16598 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16599 code. It sets the offset to use in gp_rel relocations. */
16602 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16604 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16605 We also need NewABI support. */
16606 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16612 mips_gprel_offset = get_absolute_expression ();
16614 demand_empty_rest_of_line ();
16617 /* Handle the .gpword pseudo-op. This is used when generating PIC
16618 code. It generates a 32 bit GP relative reloc. */
16621 s_gpword (int ignore ATTRIBUTE_UNUSED)
16623 segment_info_type *si;
16624 struct insn_label_list *l;
16629 /* When not generating PIC code, this is treated as .word. */
16630 if (mips_pic != SVR4_PIC)
16636 si = seg_info (now_seg);
16637 l = si->label_list;
16638 label = l != NULL ? l->label : NULL;
16639 mips_emit_delays ();
16641 mips_align (2, 0, label);
16644 mips_clear_insn_labels ();
16646 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16648 as_bad (_("Unsupported use of .gpword"));
16649 ignore_rest_of_line ();
16653 md_number_to_chars (p, 0, 4);
16654 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16655 BFD_RELOC_GPREL32);
16657 demand_empty_rest_of_line ();
16661 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16663 segment_info_type *si;
16664 struct insn_label_list *l;
16669 /* When not generating PIC code, this is treated as .dword. */
16670 if (mips_pic != SVR4_PIC)
16676 si = seg_info (now_seg);
16677 l = si->label_list;
16678 label = l != NULL ? l->label : NULL;
16679 mips_emit_delays ();
16681 mips_align (3, 0, label);
16684 mips_clear_insn_labels ();
16686 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16688 as_bad (_("Unsupported use of .gpdword"));
16689 ignore_rest_of_line ();
16693 md_number_to_chars (p, 0, 8);
16694 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16695 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16697 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16698 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16699 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16701 demand_empty_rest_of_line ();
16704 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16705 tables in SVR4 PIC code. */
16708 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16712 /* This is ignored when not generating SVR4 PIC code. */
16713 if (mips_pic != SVR4_PIC)
16719 /* Add $gp to the register named as an argument. */
16721 reg = tc_get_register (0);
16722 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16725 demand_empty_rest_of_line ();
16728 /* Handle the .insn pseudo-op. This marks instruction labels in
16729 mips16/micromips mode. This permits the linker to handle them specially,
16730 such as generating jalx instructions when needed. We also make
16731 them odd for the duration of the assembly, in order to generate the
16732 right sort of code. We will make them even in the adjust_symtab
16733 routine, while leaving them marked. This is convenient for the
16734 debugger and the disassembler. The linker knows to make them odd
16738 s_insn (int ignore ATTRIBUTE_UNUSED)
16740 mips_mark_labels ();
16742 demand_empty_rest_of_line ();
16745 /* Handle a .stabn directive. We need these in order to mark a label
16746 as being a mips16 text label correctly. Sometimes the compiler
16747 will emit a label, followed by a .stabn, and then switch sections.
16748 If the label and .stabn are in mips16 mode, then the label is
16749 really a mips16 text label. */
16752 s_mips_stab (int type)
16755 mips_mark_labels ();
16760 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16763 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16770 name = input_line_pointer;
16771 c = get_symbol_end ();
16772 symbolP = symbol_find_or_make (name);
16773 S_SET_WEAK (symbolP);
16774 *input_line_pointer = c;
16776 SKIP_WHITESPACE ();
16778 if (! is_end_of_line[(unsigned char) *input_line_pointer])
16780 if (S_IS_DEFINED (symbolP))
16782 as_bad (_("ignoring attempt to redefine symbol %s"),
16783 S_GET_NAME (symbolP));
16784 ignore_rest_of_line ();
16788 if (*input_line_pointer == ',')
16790 ++input_line_pointer;
16791 SKIP_WHITESPACE ();
16795 if (exp.X_op != O_symbol)
16797 as_bad (_("bad .weakext directive"));
16798 ignore_rest_of_line ();
16801 symbol_set_value_expression (symbolP, &exp);
16804 demand_empty_rest_of_line ();
16807 /* Parse a register string into a number. Called from the ECOFF code
16808 to parse .frame. The argument is non-zero if this is the frame
16809 register, so that we can record it in mips_frame_reg. */
16812 tc_get_register (int frame)
16816 SKIP_WHITESPACE ();
16817 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
16821 mips_frame_reg = reg != 0 ? reg : SP;
16822 mips_frame_reg_valid = 1;
16823 mips_cprestore_valid = 0;
16829 md_section_align (asection *seg, valueT addr)
16831 int align = bfd_get_section_alignment (stdoutput, seg);
16835 /* We don't need to align ELF sections to the full alignment.
16836 However, Irix 5 may prefer that we align them at least to a 16
16837 byte boundary. We don't bother to align the sections if we
16838 are targeted for an embedded system. */
16839 if (strncmp (TARGET_OS, "elf", 3) == 0)
16845 return ((addr + (1 << align) - 1) & (-1 << align));
16848 /* Utility routine, called from above as well. If called while the
16849 input file is still being read, it's only an approximation. (For
16850 example, a symbol may later become defined which appeared to be
16851 undefined earlier.) */
16854 nopic_need_relax (symbolS *sym, int before_relaxing)
16859 if (g_switch_value > 0)
16861 const char *symname;
16864 /* Find out whether this symbol can be referenced off the $gp
16865 register. It can be if it is smaller than the -G size or if
16866 it is in the .sdata or .sbss section. Certain symbols can
16867 not be referenced off the $gp, although it appears as though
16869 symname = S_GET_NAME (sym);
16870 if (symname != (const char *) NULL
16871 && (strcmp (symname, "eprol") == 0
16872 || strcmp (symname, "etext") == 0
16873 || strcmp (symname, "_gp") == 0
16874 || strcmp (symname, "edata") == 0
16875 || strcmp (symname, "_fbss") == 0
16876 || strcmp (symname, "_fdata") == 0
16877 || strcmp (symname, "_ftext") == 0
16878 || strcmp (symname, "end") == 0
16879 || strcmp (symname, "_gp_disp") == 0))
16881 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
16883 #ifndef NO_ECOFF_DEBUGGING
16884 || (symbol_get_obj (sym)->ecoff_extern_size != 0
16885 && (symbol_get_obj (sym)->ecoff_extern_size
16886 <= g_switch_value))
16888 /* We must defer this decision until after the whole
16889 file has been read, since there might be a .extern
16890 after the first use of this symbol. */
16891 || (before_relaxing
16892 #ifndef NO_ECOFF_DEBUGGING
16893 && symbol_get_obj (sym)->ecoff_extern_size == 0
16895 && S_GET_VALUE (sym) == 0)
16896 || (S_GET_VALUE (sym) != 0
16897 && S_GET_VALUE (sym) <= g_switch_value)))
16901 const char *segname;
16903 segname = segment_name (S_GET_SEGMENT (sym));
16904 gas_assert (strcmp (segname, ".lit8") != 0
16905 && strcmp (segname, ".lit4") != 0);
16906 change = (strcmp (segname, ".sdata") != 0
16907 && strcmp (segname, ".sbss") != 0
16908 && strncmp (segname, ".sdata.", 7) != 0
16909 && strncmp (segname, ".sbss.", 6) != 0
16910 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
16911 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
16916 /* We are not optimizing for the $gp register. */
16921 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16924 pic_need_relax (symbolS *sym, asection *segtype)
16928 /* Handle the case of a symbol equated to another symbol. */
16929 while (symbol_equated_reloc_p (sym))
16933 /* It's possible to get a loop here in a badly written program. */
16934 n = symbol_get_value_expression (sym)->X_add_symbol;
16940 if (symbol_section_p (sym))
16943 symsec = S_GET_SEGMENT (sym);
16945 /* This must duplicate the test in adjust_reloc_syms. */
16946 return (symsec != &bfd_und_section
16947 && symsec != &bfd_abs_section
16948 && !bfd_is_com_section (symsec)
16949 && !s_is_linkonce (sym, segtype)
16951 /* A global or weak symbol is treated as external. */
16952 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
16958 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16959 extended opcode. SEC is the section the frag is in. */
16962 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16965 const struct mips16_immed_operand *op;
16967 int mintiny, maxtiny;
16971 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16973 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16976 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16977 op = mips16_immed_operands;
16978 while (op->type != type)
16981 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
16986 if (type == '<' || type == '>' || type == '[' || type == ']')
16989 maxtiny = 1 << op->nbits;
16994 maxtiny = (1 << op->nbits) - 1;
16999 mintiny = - (1 << (op->nbits - 1));
17000 maxtiny = (1 << (op->nbits - 1)) - 1;
17003 sym_frag = symbol_get_frag (fragp->fr_symbol);
17004 val = S_GET_VALUE (fragp->fr_symbol);
17005 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17011 /* We won't have the section when we are called from
17012 mips_relax_frag. However, we will always have been called
17013 from md_estimate_size_before_relax first. If this is a
17014 branch to a different section, we mark it as such. If SEC is
17015 NULL, and the frag is not marked, then it must be a branch to
17016 the same section. */
17019 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17024 /* Must have been called from md_estimate_size_before_relax. */
17027 fragp->fr_subtype =
17028 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17030 /* FIXME: We should support this, and let the linker
17031 catch branches and loads that are out of range. */
17032 as_bad_where (fragp->fr_file, fragp->fr_line,
17033 _("unsupported PC relative reference to different section"));
17037 if (fragp != sym_frag && sym_frag->fr_address == 0)
17038 /* Assume non-extended on the first relaxation pass.
17039 The address we have calculated will be bogus if this is
17040 a forward branch to another frag, as the forward frag
17041 will have fr_address == 0. */
17045 /* In this case, we know for sure that the symbol fragment is in
17046 the same section. If the relax_marker of the symbol fragment
17047 differs from the relax_marker of this fragment, we have not
17048 yet adjusted the symbol fragment fr_address. We want to add
17049 in STRETCH in order to get a better estimate of the address.
17050 This particularly matters because of the shift bits. */
17052 && sym_frag->relax_marker != fragp->relax_marker)
17056 /* Adjust stretch for any alignment frag. Note that if have
17057 been expanding the earlier code, the symbol may be
17058 defined in what appears to be an earlier frag. FIXME:
17059 This doesn't handle the fr_subtype field, which specifies
17060 a maximum number of bytes to skip when doing an
17062 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17064 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17067 stretch = - ((- stretch)
17068 & ~ ((1 << (int) f->fr_offset) - 1));
17070 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17079 addr = fragp->fr_address + fragp->fr_fix;
17081 /* The base address rules are complicated. The base address of
17082 a branch is the following instruction. The base address of a
17083 PC relative load or add is the instruction itself, but if it
17084 is in a delay slot (in which case it can not be extended) use
17085 the address of the instruction whose delay slot it is in. */
17086 if (type == 'p' || type == 'q')
17090 /* If we are currently assuming that this frag should be
17091 extended, then, the current address is two bytes
17093 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17096 /* Ignore the low bit in the target, since it will be set
17097 for a text label. */
17098 if ((val & 1) != 0)
17101 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17103 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17106 val -= addr & ~ ((1 << op->shift) - 1);
17108 /* Branch offsets have an implicit 0 in the lowest bit. */
17109 if (type == 'p' || type == 'q')
17112 /* If any of the shifted bits are set, we must use an extended
17113 opcode. If the address depends on the size of this
17114 instruction, this can lead to a loop, so we arrange to always
17115 use an extended opcode. We only check this when we are in
17116 the main relaxation loop, when SEC is NULL. */
17117 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17119 fragp->fr_subtype =
17120 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17124 /* If we are about to mark a frag as extended because the value
17125 is precisely maxtiny + 1, then there is a chance of an
17126 infinite loop as in the following code:
17131 In this case when the la is extended, foo is 0x3fc bytes
17132 away, so the la can be shrunk, but then foo is 0x400 away, so
17133 the la must be extended. To avoid this loop, we mark the
17134 frag as extended if it was small, and is about to become
17135 extended with a value of maxtiny + 1. */
17136 if (val == ((maxtiny + 1) << op->shift)
17137 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17140 fragp->fr_subtype =
17141 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17145 else if (symsec != absolute_section && sec != NULL)
17146 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17148 if ((val & ((1 << op->shift) - 1)) != 0
17149 || val < (mintiny << op->shift)
17150 || val > (maxtiny << op->shift))
17156 /* Compute the length of a branch sequence, and adjust the
17157 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17158 worst-case length is computed, with UPDATE being used to indicate
17159 whether an unconditional (-1), branch-likely (+1) or regular (0)
17160 branch is to be computed. */
17162 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17164 bfd_boolean toofar;
17168 && S_IS_DEFINED (fragp->fr_symbol)
17169 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17174 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17176 addr = fragp->fr_address + fragp->fr_fix + 4;
17180 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17183 /* If the symbol is not defined or it's in a different segment,
17184 assume the user knows what's going on and emit a short
17190 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17192 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17193 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17194 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17195 RELAX_BRANCH_LINK (fragp->fr_subtype),
17201 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17204 if (mips_pic != NO_PIC)
17206 /* Additional space for PIC loading of target address. */
17208 if (mips_opts.isa == ISA_MIPS1)
17209 /* Additional space for $at-stabilizing nop. */
17213 /* If branch is conditional. */
17214 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17221 /* Compute the length of a branch sequence, and adjust the
17222 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17223 worst-case length is computed, with UPDATE being used to indicate
17224 whether an unconditional (-1), or regular (0) branch is to be
17228 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17230 bfd_boolean toofar;
17234 && S_IS_DEFINED (fragp->fr_symbol)
17235 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17240 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17241 /* Ignore the low bit in the target, since it will be set
17242 for a text label. */
17243 if ((val & 1) != 0)
17246 addr = fragp->fr_address + fragp->fr_fix + 4;
17250 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17253 /* If the symbol is not defined or it's in a different segment,
17254 assume the user knows what's going on and emit a short
17260 if (fragp && update
17261 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17262 fragp->fr_subtype = (toofar
17263 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17264 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17269 bfd_boolean compact_known = fragp != NULL;
17270 bfd_boolean compact = FALSE;
17271 bfd_boolean uncond;
17274 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17276 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17278 uncond = update < 0;
17280 /* If label is out of range, we turn branch <br>:
17282 <br> label # 4 bytes
17288 nop # 2 bytes if compact && !PIC
17291 if (mips_pic == NO_PIC && (!compact_known || compact))
17294 /* If assembling PIC code, we further turn:
17300 lw/ld at, %got(label)(gp) # 4 bytes
17301 d/addiu at, %lo(label) # 4 bytes
17304 if (mips_pic != NO_PIC)
17307 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17309 <brneg> 0f # 4 bytes
17310 nop # 2 bytes if !compact
17313 length += (compact_known && compact) ? 4 : 6;
17319 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17320 bit accordingly. */
17323 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17325 bfd_boolean toofar;
17328 && S_IS_DEFINED (fragp->fr_symbol)
17329 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17335 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17336 /* Ignore the low bit in the target, since it will be set
17337 for a text label. */
17338 if ((val & 1) != 0)
17341 /* Assume this is a 2-byte branch. */
17342 addr = fragp->fr_address + fragp->fr_fix + 2;
17344 /* We try to avoid the infinite loop by not adding 2 more bytes for
17349 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17351 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17352 else if (type == 'E')
17353 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17358 /* If the symbol is not defined or it's in a different segment,
17359 we emit a normal 32-bit branch. */
17362 if (fragp && update
17363 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17365 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17366 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17374 /* Estimate the size of a frag before relaxing. Unless this is the
17375 mips16, we are not really relaxing here, and the final size is
17376 encoded in the subtype information. For the mips16, we have to
17377 decide whether we are using an extended opcode or not. */
17380 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17384 if (RELAX_BRANCH_P (fragp->fr_subtype))
17387 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17389 return fragp->fr_var;
17392 if (RELAX_MIPS16_P (fragp->fr_subtype))
17393 /* We don't want to modify the EXTENDED bit here; it might get us
17394 into infinite loops. We change it only in mips_relax_frag(). */
17395 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17397 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17401 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17402 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17403 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17404 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17405 fragp->fr_var = length;
17410 if (mips_pic == NO_PIC)
17411 change = nopic_need_relax (fragp->fr_symbol, 0);
17412 else if (mips_pic == SVR4_PIC)
17413 change = pic_need_relax (fragp->fr_symbol, segtype);
17414 else if (mips_pic == VXWORKS_PIC)
17415 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17422 fragp->fr_subtype |= RELAX_USE_SECOND;
17423 return -RELAX_FIRST (fragp->fr_subtype);
17426 return -RELAX_SECOND (fragp->fr_subtype);
17429 /* This is called to see whether a reloc against a defined symbol
17430 should be converted into a reloc against a section. */
17433 mips_fix_adjustable (fixS *fixp)
17435 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17436 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17439 if (fixp->fx_addsy == NULL)
17442 /* If symbol SYM is in a mergeable section, relocations of the form
17443 SYM + 0 can usually be made section-relative. The mergeable data
17444 is then identified by the section offset rather than by the symbol.
17446 However, if we're generating REL LO16 relocations, the offset is split
17447 between the LO16 and parterning high part relocation. The linker will
17448 need to recalculate the complete offset in order to correctly identify
17451 The linker has traditionally not looked for the parterning high part
17452 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17453 placed anywhere. Rather than break backwards compatibility by changing
17454 this, it seems better not to force the issue, and instead keep the
17455 original symbol. This will work with either linker behavior. */
17456 if ((lo16_reloc_p (fixp->fx_r_type)
17457 || reloc_needs_lo_p (fixp->fx_r_type))
17458 && HAVE_IN_PLACE_ADDENDS
17459 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17462 /* There is no place to store an in-place offset for JALR relocations.
17463 Likewise an in-range offset of PC-relative relocations may overflow
17464 the in-place relocatable field if recalculated against the start
17465 address of the symbol's containing section. */
17466 if (HAVE_IN_PLACE_ADDENDS
17467 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17471 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17472 to a floating-point stub. The same is true for non-R_MIPS16_26
17473 relocations against MIPS16 functions; in this case, the stub becomes
17474 the function's canonical address.
17476 Floating-point stubs are stored in unique .mips16.call.* or
17477 .mips16.fn.* sections. If a stub T for function F is in section S,
17478 the first relocation in section S must be against F; this is how the
17479 linker determines the target function. All relocations that might
17480 resolve to T must also be against F. We therefore have the following
17481 restrictions, which are given in an intentionally-redundant way:
17483 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17486 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17487 if that stub might be used.
17489 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17492 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17493 that stub might be used.
17495 There is a further restriction:
17497 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17498 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17499 targets with in-place addends; the relocation field cannot
17500 encode the low bit.
17502 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17503 against a MIPS16 symbol. We deal with (5) by by not reducing any
17504 such relocations on REL targets.
17506 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17507 relocation against some symbol R, no relocation against R may be
17508 reduced. (Note that this deals with (2) as well as (1) because
17509 relocations against global symbols will never be reduced on ELF
17510 targets.) This approach is a little simpler than trying to detect
17511 stub sections, and gives the "all or nothing" per-symbol consistency
17512 that we have for MIPS16 symbols. */
17514 && fixp->fx_subsy == NULL
17515 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17516 || *symbol_get_tc (fixp->fx_addsy)
17517 || (HAVE_IN_PLACE_ADDENDS
17518 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17519 && jmp_reloc_p (fixp->fx_r_type))))
17526 /* Translate internal representation of relocation info to BFD target
17530 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17532 static arelent *retval[4];
17534 bfd_reloc_code_real_type code;
17536 memset (retval, 0, sizeof(retval));
17537 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17538 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17539 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17540 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17542 if (fixp->fx_pcrel)
17544 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17545 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17546 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17547 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17549 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17550 Relocations want only the symbol offset. */
17551 reloc->addend = fixp->fx_addnumber + reloc->address;
17554 /* A gruesome hack which is a result of the gruesome gas
17555 reloc handling. What's worse, for COFF (as opposed to
17556 ECOFF), we might need yet another copy of reloc->address.
17557 See bfd_install_relocation. */
17558 reloc->addend += reloc->address;
17562 reloc->addend = fixp->fx_addnumber;
17564 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17565 entry to be used in the relocation's section offset. */
17566 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17568 reloc->address = reloc->addend;
17572 code = fixp->fx_r_type;
17574 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17575 if (reloc->howto == NULL)
17577 as_bad_where (fixp->fx_file, fixp->fx_line,
17578 _("Can not represent %s relocation in this object file format"),
17579 bfd_get_reloc_code_name (code));
17586 /* Relax a machine dependent frag. This returns the amount by which
17587 the current size of the frag should change. */
17590 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17592 if (RELAX_BRANCH_P (fragp->fr_subtype))
17594 offsetT old_var = fragp->fr_var;
17596 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17598 return fragp->fr_var - old_var;
17601 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17603 offsetT old_var = fragp->fr_var;
17604 offsetT new_var = 4;
17606 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17607 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17608 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17609 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17610 fragp->fr_var = new_var;
17612 return new_var - old_var;
17615 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17618 if (mips16_extended_frag (fragp, NULL, stretch))
17620 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17622 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17627 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17629 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17636 /* Convert a machine dependent frag. */
17639 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17641 if (RELAX_BRANCH_P (fragp->fr_subtype))
17644 unsigned long insn;
17648 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
17650 if (target_big_endian)
17651 insn = bfd_getb32 (buf);
17653 insn = bfd_getl32 (buf);
17655 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17657 /* We generate a fixup instead of applying it right now
17658 because, if there are linker relaxations, we're going to
17659 need the relocations. */
17660 exp.X_op = O_symbol;
17661 exp.X_add_symbol = fragp->fr_symbol;
17662 exp.X_add_number = fragp->fr_offset;
17664 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17665 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
17666 fixp->fx_file = fragp->fr_file;
17667 fixp->fx_line = fragp->fr_line;
17669 md_number_to_chars ((char *) buf, insn, 4);
17676 as_warn_where (fragp->fr_file, fragp->fr_line,
17677 _("Relaxed out-of-range branch into a jump"));
17679 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17682 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17684 /* Reverse the branch. */
17685 switch ((insn >> 28) & 0xf)
17688 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17689 have the condition reversed by tweaking a single
17690 bit, and their opcodes all have 0x4???????. */
17691 gas_assert ((insn & 0xf1000000) == 0x41000000);
17692 insn ^= 0x00010000;
17696 /* bltz 0x04000000 bgez 0x04010000
17697 bltzal 0x04100000 bgezal 0x04110000 */
17698 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17699 insn ^= 0x00010000;
17703 /* beq 0x10000000 bne 0x14000000
17704 blez 0x18000000 bgtz 0x1c000000 */
17705 insn ^= 0x04000000;
17713 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17715 /* Clear the and-link bit. */
17716 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17718 /* bltzal 0x04100000 bgezal 0x04110000
17719 bltzall 0x04120000 bgezall 0x04130000 */
17720 insn &= ~0x00100000;
17723 /* Branch over the branch (if the branch was likely) or the
17724 full jump (not likely case). Compute the offset from the
17725 current instruction to branch to. */
17726 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17730 /* How many bytes in instructions we've already emitted? */
17731 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17732 /* How many bytes in instructions from here to the end? */
17733 i = fragp->fr_var - i;
17735 /* Convert to instruction count. */
17737 /* Branch counts from the next instruction. */
17740 /* Branch over the jump. */
17741 md_number_to_chars ((char *) buf, insn, 4);
17745 md_number_to_chars ((char *) buf, 0, 4);
17748 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17750 /* beql $0, $0, 2f */
17752 /* Compute the PC offset from the current instruction to
17753 the end of the variable frag. */
17754 /* How many bytes in instructions we've already emitted? */
17755 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
17756 /* How many bytes in instructions from here to the end? */
17757 i = fragp->fr_var - i;
17758 /* Convert to instruction count. */
17760 /* Don't decrement i, because we want to branch over the
17764 md_number_to_chars ((char *) buf, insn, 4);
17767 md_number_to_chars ((char *) buf, 0, 4);
17772 if (mips_pic == NO_PIC)
17775 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17776 ? 0x0c000000 : 0x08000000);
17777 exp.X_op = O_symbol;
17778 exp.X_add_symbol = fragp->fr_symbol;
17779 exp.X_add_number = fragp->fr_offset;
17781 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17782 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
17783 fixp->fx_file = fragp->fr_file;
17784 fixp->fx_line = fragp->fr_line;
17786 md_number_to_chars ((char *) buf, insn, 4);
17791 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
17793 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
17794 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
17795 insn |= at << OP_SH_RT;
17796 exp.X_op = O_symbol;
17797 exp.X_add_symbol = fragp->fr_symbol;
17798 exp.X_add_number = fragp->fr_offset;
17800 if (fragp->fr_offset)
17802 exp.X_add_symbol = make_expr_symbol (&exp);
17803 exp.X_add_number = 0;
17806 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17807 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
17808 fixp->fx_file = fragp->fr_file;
17809 fixp->fx_line = fragp->fr_line;
17811 md_number_to_chars ((char *) buf, insn, 4);
17814 if (mips_opts.isa == ISA_MIPS1)
17817 md_number_to_chars ((char *) buf, 0, 4);
17821 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
17822 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
17823 insn |= at << OP_SH_RS | at << OP_SH_RT;
17825 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
17826 4, &exp, FALSE, BFD_RELOC_LO16);
17827 fixp->fx_file = fragp->fr_file;
17828 fixp->fx_line = fragp->fr_line;
17830 md_number_to_chars ((char *) buf, insn, 4);
17834 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17838 insn |= at << OP_SH_RS;
17840 md_number_to_chars ((char *) buf, insn, 4);
17845 gas_assert (buf == (bfd_byte *)fragp->fr_literal
17846 + fragp->fr_fix + fragp->fr_var);
17848 fragp->fr_fix += fragp->fr_var;
17853 /* Relax microMIPS branches. */
17854 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17856 bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
17857 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17858 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
17859 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17860 bfd_boolean short_ds;
17861 unsigned long insn;
17865 exp.X_op = O_symbol;
17866 exp.X_add_symbol = fragp->fr_symbol;
17867 exp.X_add_number = fragp->fr_offset;
17869 fragp->fr_fix += fragp->fr_var;
17871 /* Handle 16-bit branches that fit or are forced to fit. */
17872 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17874 /* We generate a fixup instead of applying it right now,
17875 because if there is linker relaxation, we're going to
17876 need the relocations. */
17878 fixp = fix_new_exp (fragp,
17879 buf - (bfd_byte *) fragp->fr_literal,
17881 BFD_RELOC_MICROMIPS_10_PCREL_S1);
17882 else if (type == 'E')
17883 fixp = fix_new_exp (fragp,
17884 buf - (bfd_byte *) fragp->fr_literal,
17886 BFD_RELOC_MICROMIPS_7_PCREL_S1);
17890 fixp->fx_file = fragp->fr_file;
17891 fixp->fx_line = fragp->fr_line;
17893 /* These relocations can have an addend that won't fit in
17895 fixp->fx_no_overflow = 1;
17900 /* Handle 32-bit branches that fit or are forced to fit. */
17901 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17902 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17904 /* We generate a fixup instead of applying it right now,
17905 because if there is linker relaxation, we're going to
17906 need the relocations. */
17907 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
17908 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
17909 fixp->fx_file = fragp->fr_file;
17910 fixp->fx_line = fragp->fr_line;
17916 /* Relax 16-bit branches to 32-bit branches. */
17919 if (target_big_endian)
17920 insn = bfd_getb16 (buf);
17922 insn = bfd_getl16 (buf);
17924 if ((insn & 0xfc00) == 0xcc00) /* b16 */
17925 insn = 0x94000000; /* beq */
17926 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
17928 unsigned long regno;
17930 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
17931 regno = micromips_to_32_reg_d_map [regno];
17932 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
17933 insn |= regno << MICROMIPSOP_SH_RS;
17938 /* Nothing else to do, just write it out. */
17939 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
17940 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17942 md_number_to_chars ((char *) buf, insn >> 16, 2);
17944 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
17947 gas_assert (buf == ((bfd_byte *) fragp->fr_literal
17954 unsigned long next;
17956 if (target_big_endian)
17958 insn = bfd_getb16 (buf);
17959 next = bfd_getb16 (buf + 2);
17963 insn = bfd_getl16 (buf);
17964 next = bfd_getl16 (buf + 2);
17966 insn = (insn << 16) | next;
17969 /* Relax 32-bit branches to a sequence of instructions. */
17970 as_warn_where (fragp->fr_file, fragp->fr_line,
17971 _("Relaxed out-of-range branch into a jump"));
17973 /* Set the short-delay-slot bit. */
17974 short_ds = al && (insn & 0x02000000) != 0;
17976 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
17980 /* Reverse the branch. */
17981 if ((insn & 0xfc000000) == 0x94000000 /* beq */
17982 || (insn & 0xfc000000) == 0xb4000000) /* bne */
17983 insn ^= 0x20000000;
17984 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
17985 || (insn & 0xffe00000) == 0x40400000 /* bgez */
17986 || (insn & 0xffe00000) == 0x40800000 /* blez */
17987 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
17988 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
17989 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
17990 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
17991 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
17992 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
17993 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
17994 insn ^= 0x00400000;
17995 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
17996 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
17997 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
17998 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
17999 insn ^= 0x00200000;
18005 /* Clear the and-link and short-delay-slot bits. */
18006 gas_assert ((insn & 0xfda00000) == 0x40200000);
18008 /* bltzal 0x40200000 bgezal 0x40600000 */
18009 /* bltzals 0x42200000 bgezals 0x42600000 */
18010 insn &= ~0x02200000;
18013 /* Make a label at the end for use with the branch. */
18014 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18015 micromips_label_inc ();
18016 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18018 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18022 fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal,
18023 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18024 fixp->fx_file = fragp->fr_file;
18025 fixp->fx_line = fragp->fr_line;
18027 /* Branch over the jump. */
18028 md_number_to_chars ((char *) buf, insn >> 16, 2);
18030 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18037 md_number_to_chars ((char *) buf, insn, 2);
18042 if (mips_pic == NO_PIC)
18044 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18046 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18047 insn = al ? jal : 0xd4000000;
18049 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18050 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP);
18051 fixp->fx_file = fragp->fr_file;
18052 fixp->fx_line = fragp->fr_line;
18054 md_number_to_chars ((char *) buf, insn >> 16, 2);
18056 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18063 md_number_to_chars ((char *) buf, insn, 2);
18069 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18070 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18071 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18073 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18074 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18075 insn |= at << MICROMIPSOP_SH_RT;
18077 if (exp.X_add_number)
18079 exp.X_add_symbol = make_expr_symbol (&exp);
18080 exp.X_add_number = 0;
18083 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18084 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16);
18085 fixp->fx_file = fragp->fr_file;
18086 fixp->fx_line = fragp->fr_line;
18088 md_number_to_chars ((char *) buf, insn >> 16, 2);
18090 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18093 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18094 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18095 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18097 fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal,
18098 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16);
18099 fixp->fx_file = fragp->fr_file;
18100 fixp->fx_line = fragp->fr_line;
18102 md_number_to_chars ((char *) buf, insn >> 16, 2);
18104 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18107 /* jr/jrc/jalr/jalrs $at */
18108 insn = al ? jalr : jr;
18109 insn |= at << MICROMIPSOP_SH_MJ;
18111 md_number_to_chars ((char *) buf, insn & 0xffff, 2);
18115 gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix);
18119 if (RELAX_MIPS16_P (fragp->fr_subtype))
18122 const struct mips16_immed_operand *op;
18123 bfd_boolean small, ext;
18126 unsigned long insn;
18127 bfd_boolean use_extend;
18128 unsigned short extend;
18130 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18131 op = mips16_immed_operands;
18132 while (op->type != type)
18135 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18146 val = resolve_symbol_value (fragp->fr_symbol);
18151 addr = fragp->fr_address + fragp->fr_fix;
18153 /* The rules for the base address of a PC relative reloc are
18154 complicated; see mips16_extended_frag. */
18155 if (type == 'p' || type == 'q')
18160 /* Ignore the low bit in the target, since it will be
18161 set for a text label. */
18162 if ((val & 1) != 0)
18165 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18167 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18170 addr &= ~ (addressT) ((1 << op->shift) - 1);
18173 /* Make sure the section winds up with the alignment we have
18176 record_alignment (asec, op->shift);
18180 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18181 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18182 as_warn_where (fragp->fr_file, fragp->fr_line,
18183 _("extended instruction in delay slot"));
18185 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
18187 if (target_big_endian)
18188 insn = bfd_getb16 (buf);
18190 insn = bfd_getl16 (buf);
18192 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
18193 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
18194 small, ext, &insn, &use_extend, &extend);
18198 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
18199 fragp->fr_fix += 2;
18203 md_number_to_chars ((char *) buf, insn, 2);
18204 fragp->fr_fix += 2;
18209 relax_substateT subtype = fragp->fr_subtype;
18210 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18211 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18215 first = RELAX_FIRST (subtype);
18216 second = RELAX_SECOND (subtype);
18217 fixp = (fixS *) fragp->fr_opcode;
18219 /* If the delay slot chosen does not match the size of the instruction,
18220 then emit a warning. */
18221 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18222 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18227 s = subtype & (RELAX_DELAY_SLOT_16BIT
18228 | RELAX_DELAY_SLOT_SIZE_FIRST
18229 | RELAX_DELAY_SLOT_SIZE_SECOND);
18230 msg = macro_warning (s);
18232 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18236 /* Possibly emit a warning if we've chosen the longer option. */
18237 if (use_second == second_longer)
18243 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18244 msg = macro_warning (s);
18246 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
18250 /* Go through all the fixups for the first sequence. Disable them
18251 (by marking them as done) if we're going to use the second
18252 sequence instead. */
18254 && fixp->fx_frag == fragp
18255 && fixp->fx_where < fragp->fr_fix - second)
18257 if (subtype & RELAX_USE_SECOND)
18259 fixp = fixp->fx_next;
18262 /* Go through the fixups for the second sequence. Disable them if
18263 we're going to use the first sequence, otherwise adjust their
18264 addresses to account for the relaxation. */
18265 while (fixp && fixp->fx_frag == fragp)
18267 if (subtype & RELAX_USE_SECOND)
18268 fixp->fx_where -= first;
18271 fixp = fixp->fx_next;
18274 /* Now modify the frag contents. */
18275 if (subtype & RELAX_USE_SECOND)
18279 start = fragp->fr_literal + fragp->fr_fix - first - second;
18280 memmove (start, start + first, second);
18281 fragp->fr_fix -= first;
18284 fragp->fr_fix -= second;
18290 /* This function is called after the relocs have been generated.
18291 We've been storing mips16 text labels as odd. Here we convert them
18292 back to even for the convenience of the debugger. */
18295 mips_frob_file_after_relocs (void)
18298 unsigned int count, i;
18303 syms = bfd_get_outsymbols (stdoutput);
18304 count = bfd_get_symcount (stdoutput);
18305 for (i = 0; i < count; i++, syms++)
18306 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18307 && ((*syms)->value & 1) != 0)
18309 (*syms)->value &= ~1;
18310 /* If the symbol has an odd size, it was probably computed
18311 incorrectly, so adjust that as well. */
18312 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18313 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18319 /* This function is called whenever a label is defined, including fake
18320 labels instantiated off the dot special symbol. It is used when
18321 handling branch delays; if a branch has a label, we assume we cannot
18322 move it. This also bumps the value of the symbol by 1 in compressed
18326 mips_record_label (symbolS *sym)
18328 segment_info_type *si = seg_info (now_seg);
18329 struct insn_label_list *l;
18331 if (free_insn_labels == NULL)
18332 l = (struct insn_label_list *) xmalloc (sizeof *l);
18335 l = free_insn_labels;
18336 free_insn_labels = l->next;
18340 l->next = si->label_list;
18341 si->label_list = l;
18344 /* This function is called as tc_frob_label() whenever a label is defined
18345 and adds a DWARF-2 record we only want for true labels. */
18348 mips_define_label (symbolS *sym)
18350 mips_record_label (sym);
18352 dwarf2_emit_label (sym);
18356 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18358 /* Some special processing for a MIPS ELF file. */
18361 mips_elf_final_processing (void)
18363 /* Write out the register information. */
18364 if (mips_abi != N64_ABI)
18368 s.ri_gprmask = mips_gprmask;
18369 s.ri_cprmask[0] = mips_cprmask[0];
18370 s.ri_cprmask[1] = mips_cprmask[1];
18371 s.ri_cprmask[2] = mips_cprmask[2];
18372 s.ri_cprmask[3] = mips_cprmask[3];
18373 /* The gp_value field is set by the MIPS ELF backend. */
18375 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18376 ((Elf32_External_RegInfo *)
18377 mips_regmask_frag));
18381 Elf64_Internal_RegInfo s;
18383 s.ri_gprmask = mips_gprmask;
18385 s.ri_cprmask[0] = mips_cprmask[0];
18386 s.ri_cprmask[1] = mips_cprmask[1];
18387 s.ri_cprmask[2] = mips_cprmask[2];
18388 s.ri_cprmask[3] = mips_cprmask[3];
18389 /* The gp_value field is set by the MIPS ELF backend. */
18391 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18392 ((Elf64_External_RegInfo *)
18393 mips_regmask_frag));
18396 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18397 sort of BFD interface for this. */
18398 if (mips_any_noreorder)
18399 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18400 if (mips_pic != NO_PIC)
18402 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18403 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18406 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18408 /* Set MIPS ELF flags for ASEs. */
18409 /* We may need to define a new flag for DSP ASE, and set this flag when
18410 file_ase_dsp is true. */
18411 /* Same for DSP R2. */
18412 /* We may need to define a new flag for MT ASE, and set this flag when
18413 file_ase_mt is true. */
18414 if (file_ase_mips16)
18415 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18416 if (file_ase_micromips)
18417 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18418 #if 0 /* XXX FIXME */
18419 if (file_ase_mips3d)
18420 elf_elfheader (stdoutput)->e_flags |= ???;
18423 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18425 /* Set the MIPS ELF ABI flags. */
18426 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18427 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18428 else if (mips_abi == O64_ABI)
18429 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18430 else if (mips_abi == EABI_ABI)
18432 if (!file_mips_gp32)
18433 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18435 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18437 else if (mips_abi == N32_ABI)
18438 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18440 /* Nothing to do for N64_ABI. */
18442 if (mips_32bitmode)
18443 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18445 #if 0 /* XXX FIXME */
18446 /* 32 bit code with 64 bit FP registers. */
18447 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18448 elf_elfheader (stdoutput)->e_flags |= ???;
18452 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18454 typedef struct proc {
18456 symbolS *func_end_sym;
18457 unsigned long reg_mask;
18458 unsigned long reg_offset;
18459 unsigned long fpreg_mask;
18460 unsigned long fpreg_offset;
18461 unsigned long frame_offset;
18462 unsigned long frame_reg;
18463 unsigned long pc_reg;
18466 static procS cur_proc;
18467 static procS *cur_proc_ptr;
18468 static int numprocs;
18470 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18471 as "2", and a normal nop as "0". */
18473 #define NOP_OPCODE_MIPS 0
18474 #define NOP_OPCODE_MIPS16 1
18475 #define NOP_OPCODE_MICROMIPS 2
18478 mips_nop_opcode (void)
18480 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18481 return NOP_OPCODE_MICROMIPS;
18482 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18483 return NOP_OPCODE_MIPS16;
18485 return NOP_OPCODE_MIPS;
18488 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18489 32-bit microMIPS NOPs here (if applicable). */
18492 mips_handle_align (fragS *fragp)
18496 int bytes, size, excess;
18499 if (fragp->fr_type != rs_align_code)
18502 p = fragp->fr_literal + fragp->fr_fix;
18504 switch (nop_opcode)
18506 case NOP_OPCODE_MICROMIPS:
18507 opcode = micromips_nop32_insn.insn_opcode;
18510 case NOP_OPCODE_MIPS16:
18511 opcode = mips16_nop_insn.insn_opcode;
18514 case NOP_OPCODE_MIPS:
18516 opcode = nop_insn.insn_opcode;
18521 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18522 excess = bytes % size;
18524 /* Handle the leading part if we're not inserting a whole number of
18525 instructions, and make it the end of the fixed part of the frag.
18526 Try to fit in a short microMIPS NOP if applicable and possible,
18527 and use zeroes otherwise. */
18528 gas_assert (excess < 4);
18529 fragp->fr_fix += excess;
18534 /* Fall through. */
18536 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18538 md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2);
18543 /* Fall through. */
18546 /* Fall through. */
18551 md_number_to_chars (p, opcode, size);
18552 fragp->fr_var = size;
18556 md_obj_begin (void)
18563 /* Check for premature end, nesting errors, etc. */
18565 as_warn (_("missing .end at end of assembly"));
18574 if (*input_line_pointer == '-')
18576 ++input_line_pointer;
18579 if (!ISDIGIT (*input_line_pointer))
18580 as_bad (_("expected simple number"));
18581 if (input_line_pointer[0] == '0')
18583 if (input_line_pointer[1] == 'x')
18585 input_line_pointer += 2;
18586 while (ISXDIGIT (*input_line_pointer))
18589 val |= hex_value (*input_line_pointer++);
18591 return negative ? -val : val;
18595 ++input_line_pointer;
18596 while (ISDIGIT (*input_line_pointer))
18599 val |= *input_line_pointer++ - '0';
18601 return negative ? -val : val;
18604 if (!ISDIGIT (*input_line_pointer))
18606 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18607 *input_line_pointer, *input_line_pointer);
18608 as_warn (_("invalid number"));
18611 while (ISDIGIT (*input_line_pointer))
18614 val += *input_line_pointer++ - '0';
18616 return negative ? -val : val;
18619 /* The .file directive; just like the usual .file directive, but there
18620 is an initial number which is the ECOFF file index. In the non-ECOFF
18621 case .file implies DWARF-2. */
18624 s_mips_file (int x ATTRIBUTE_UNUSED)
18626 static int first_file_directive = 0;
18628 if (ECOFF_DEBUGGING)
18637 filename = dwarf2_directive_file (0);
18639 /* Versions of GCC up to 3.1 start files with a ".file"
18640 directive even for stabs output. Make sure that this
18641 ".file" is handled. Note that you need a version of GCC
18642 after 3.1 in order to support DWARF-2 on MIPS. */
18643 if (filename != NULL && ! first_file_directive)
18645 (void) new_logical_line (filename, -1);
18646 s_app_file_string (filename, 0);
18648 first_file_directive = 1;
18652 /* The .loc directive, implying DWARF-2. */
18655 s_mips_loc (int x ATTRIBUTE_UNUSED)
18657 if (!ECOFF_DEBUGGING)
18658 dwarf2_directive_loc (0);
18661 /* The .end directive. */
18664 s_mips_end (int x ATTRIBUTE_UNUSED)
18668 /* Following functions need their own .frame and .cprestore directives. */
18669 mips_frame_reg_valid = 0;
18670 mips_cprestore_valid = 0;
18672 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18675 demand_empty_rest_of_line ();
18680 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18681 as_warn (_(".end not in text section"));
18685 as_warn (_(".end directive without a preceding .ent directive."));
18686 demand_empty_rest_of_line ();
18692 gas_assert (S_GET_NAME (p));
18693 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18694 as_warn (_(".end symbol does not match .ent symbol."));
18696 if (debug_type == DEBUG_STABS)
18697 stabs_generate_asm_endfunc (S_GET_NAME (p),
18701 as_warn (_(".end directive missing or unknown symbol"));
18704 /* Create an expression to calculate the size of the function. */
18705 if (p && cur_proc_ptr)
18707 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18708 expressionS *exp = xmalloc (sizeof (expressionS));
18711 exp->X_op = O_subtract;
18712 exp->X_add_symbol = symbol_temp_new_now ();
18713 exp->X_op_symbol = p;
18714 exp->X_add_number = 0;
18716 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18719 /* Generate a .pdr section. */
18720 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18722 segT saved_seg = now_seg;
18723 subsegT saved_subseg = now_subseg;
18727 #ifdef md_flush_pending_output
18728 md_flush_pending_output ();
18731 gas_assert (pdr_seg);
18732 subseg_set (pdr_seg, 0);
18734 /* Write the symbol. */
18735 exp.X_op = O_symbol;
18736 exp.X_add_symbol = p;
18737 exp.X_add_number = 0;
18738 emit_expr (&exp, 4);
18740 fragp = frag_more (7 * 4);
18742 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18743 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18744 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18745 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18746 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18747 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18748 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18750 subseg_set (saved_seg, saved_subseg);
18752 #endif /* OBJ_ELF */
18754 cur_proc_ptr = NULL;
18757 /* The .aent and .ent directives. */
18760 s_mips_ent (int aent)
18764 symbolP = get_symbol ();
18765 if (*input_line_pointer == ',')
18766 ++input_line_pointer;
18767 SKIP_WHITESPACE ();
18768 if (ISDIGIT (*input_line_pointer)
18769 || *input_line_pointer == '-')
18772 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18773 as_warn (_(".ent or .aent not in text section."));
18775 if (!aent && cur_proc_ptr)
18776 as_warn (_("missing .end"));
18780 /* This function needs its own .frame and .cprestore directives. */
18781 mips_frame_reg_valid = 0;
18782 mips_cprestore_valid = 0;
18784 cur_proc_ptr = &cur_proc;
18785 memset (cur_proc_ptr, '\0', sizeof (procS));
18787 cur_proc_ptr->func_sym = symbolP;
18791 if (debug_type == DEBUG_STABS)
18792 stabs_generate_asm_func (S_GET_NAME (symbolP),
18793 S_GET_NAME (symbolP));
18796 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18798 demand_empty_rest_of_line ();
18801 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18802 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18803 s_mips_frame is used so that we can set the PDR information correctly.
18804 We can't use the ecoff routines because they make reference to the ecoff
18805 symbol table (in the mdebug section). */
18808 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18811 if (IS_ELF && !ECOFF_DEBUGGING)
18815 if (cur_proc_ptr == (procS *) NULL)
18817 as_warn (_(".frame outside of .ent"));
18818 demand_empty_rest_of_line ();
18822 cur_proc_ptr->frame_reg = tc_get_register (1);
18824 SKIP_WHITESPACE ();
18825 if (*input_line_pointer++ != ','
18826 || get_absolute_expression_and_terminator (&val) != ',')
18828 as_warn (_("Bad .frame directive"));
18829 --input_line_pointer;
18830 demand_empty_rest_of_line ();
18834 cur_proc_ptr->frame_offset = val;
18835 cur_proc_ptr->pc_reg = tc_get_register (0);
18837 demand_empty_rest_of_line ();
18840 #endif /* OBJ_ELF */
18844 /* The .fmask and .mask directives. If the mdebug section is present
18845 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18846 embedded targets, s_mips_mask is used so that we can set the PDR
18847 information correctly. We can't use the ecoff routines because they
18848 make reference to the ecoff symbol table (in the mdebug section). */
18851 s_mips_mask (int reg_type)
18854 if (IS_ELF && !ECOFF_DEBUGGING)
18858 if (cur_proc_ptr == (procS *) NULL)
18860 as_warn (_(".mask/.fmask outside of .ent"));
18861 demand_empty_rest_of_line ();
18865 if (get_absolute_expression_and_terminator (&mask) != ',')
18867 as_warn (_("Bad .mask/.fmask directive"));
18868 --input_line_pointer;
18869 demand_empty_rest_of_line ();
18873 off = get_absolute_expression ();
18875 if (reg_type == 'F')
18877 cur_proc_ptr->fpreg_mask = mask;
18878 cur_proc_ptr->fpreg_offset = off;
18882 cur_proc_ptr->reg_mask = mask;
18883 cur_proc_ptr->reg_offset = off;
18886 demand_empty_rest_of_line ();
18889 #endif /* OBJ_ELF */
18890 s_ignore (reg_type);
18893 /* A table describing all the processors gas knows about. Names are
18894 matched in the order listed.
18896 To ease comparison, please keep this table in the same order as
18897 gcc's mips_cpu_info_table[]. */
18898 static const struct mips_cpu_info mips_cpu_info_table[] =
18900 /* Entries for generic ISAs */
18901 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
18902 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
18903 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
18904 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
18905 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
18906 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
18907 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
18908 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
18909 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
18912 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
18913 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
18914 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
18917 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
18920 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
18921 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
18922 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
18923 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
18924 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
18925 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
18926 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
18927 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
18928 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
18929 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
18930 { "orion", 0, ISA_MIPS3, CPU_R4600 },
18931 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
18932 /* ST Microelectronics Loongson 2E and 2F cores */
18933 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
18934 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
18937 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
18938 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
18939 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
18940 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
18941 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
18942 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
18943 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
18944 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
18945 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
18946 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
18947 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
18948 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
18949 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
18950 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
18951 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
18954 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
18955 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
18956 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
18957 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
18959 /* MIPS 32 Release 2 */
18960 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18961 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18962 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18963 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
18964 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18965 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18966 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18967 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18968 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18969 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18970 /* Deprecated forms of the above. */
18971 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18972 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
18973 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
18974 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18975 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18976 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18977 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18978 /* Deprecated forms of the above. */
18979 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18980 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
18981 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
18982 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18983 ISA_MIPS32R2, CPU_MIPS32R2 },
18984 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18985 ISA_MIPS32R2, CPU_MIPS32R2 },
18986 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18987 ISA_MIPS32R2, CPU_MIPS32R2 },
18988 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18989 ISA_MIPS32R2, CPU_MIPS32R2 },
18990 /* Deprecated forms of the above. */
18991 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18992 ISA_MIPS32R2, CPU_MIPS32R2 },
18993 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
18994 ISA_MIPS32R2, CPU_MIPS32R2 },
18995 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
18996 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18997 ISA_MIPS32R2, CPU_MIPS32R2 },
18998 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
18999 ISA_MIPS32R2, CPU_MIPS32R2 },
19000 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19001 ISA_MIPS32R2, CPU_MIPS32R2 },
19002 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19003 ISA_MIPS32R2, CPU_MIPS32R2 },
19004 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19005 ISA_MIPS32R2, CPU_MIPS32R2 },
19006 /* Deprecated forms of the above. */
19007 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19008 ISA_MIPS32R2, CPU_MIPS32R2 },
19009 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19010 ISA_MIPS32R2, CPU_MIPS32R2 },
19011 /* 1004K cores are multiprocessor versions of the 34K. */
19012 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19013 ISA_MIPS32R2, CPU_MIPS32R2 },
19014 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19015 ISA_MIPS32R2, CPU_MIPS32R2 },
19016 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19017 ISA_MIPS32R2, CPU_MIPS32R2 },
19018 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19019 ISA_MIPS32R2, CPU_MIPS32R2 },
19022 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19023 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19024 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19025 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19027 /* Broadcom SB-1 CPU core */
19028 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19029 ISA_MIPS64, CPU_SB1 },
19030 /* Broadcom SB-1A CPU core */
19031 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19032 ISA_MIPS64, CPU_SB1 },
19034 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19036 /* MIPS 64 Release 2 */
19038 /* Cavium Networks Octeon CPU core */
19039 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19042 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19049 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19050 with a final "000" replaced by "k". Ignore case.
19052 Note: this function is shared between GCC and GAS. */
19055 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19057 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19058 given++, canonical++;
19060 return ((*given == 0 && *canonical == 0)
19061 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19065 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19066 CPU name. We've traditionally allowed a lot of variation here.
19068 Note: this function is shared between GCC and GAS. */
19071 mips_matching_cpu_name_p (const char *canonical, const char *given)
19073 /* First see if the name matches exactly, or with a final "000"
19074 turned into "k". */
19075 if (mips_strict_matching_cpu_name_p (canonical, given))
19078 /* If not, try comparing based on numerical designation alone.
19079 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19080 if (TOLOWER (*given) == 'r')
19082 if (!ISDIGIT (*given))
19085 /* Skip over some well-known prefixes in the canonical name,
19086 hoping to find a number there too. */
19087 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19089 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19091 else if (TOLOWER (canonical[0]) == 'r')
19094 return mips_strict_matching_cpu_name_p (canonical, given);
19098 /* Parse an option that takes the name of a processor as its argument.
19099 OPTION is the name of the option and CPU_STRING is the argument.
19100 Return the corresponding processor enumeration if the CPU_STRING is
19101 recognized, otherwise report an error and return null.
19103 A similar function exists in GCC. */
19105 static const struct mips_cpu_info *
19106 mips_parse_cpu (const char *option, const char *cpu_string)
19108 const struct mips_cpu_info *p;
19110 /* 'from-abi' selects the most compatible architecture for the given
19111 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19112 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19113 version. Look first at the -mgp options, if given, otherwise base
19114 the choice on MIPS_DEFAULT_64BIT.
19116 Treat NO_ABI like the EABIs. One reason to do this is that the
19117 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19118 architecture. This code picks MIPS I for 'mips' and MIPS III for
19119 'mips64', just as we did in the days before 'from-abi'. */
19120 if (strcasecmp (cpu_string, "from-abi") == 0)
19122 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19123 return mips_cpu_info_from_isa (ISA_MIPS1);
19125 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19126 return mips_cpu_info_from_isa (ISA_MIPS3);
19128 if (file_mips_gp32 >= 0)
19129 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19131 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19136 /* 'default' has traditionally been a no-op. Probably not very useful. */
19137 if (strcasecmp (cpu_string, "default") == 0)
19140 for (p = mips_cpu_info_table; p->name != 0; p++)
19141 if (mips_matching_cpu_name_p (p->name, cpu_string))
19144 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19148 /* Return the canonical processor information for ISA (a member of the
19149 ISA_MIPS* enumeration). */
19151 static const struct mips_cpu_info *
19152 mips_cpu_info_from_isa (int isa)
19156 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19157 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19158 && isa == mips_cpu_info_table[i].isa)
19159 return (&mips_cpu_info_table[i]);
19164 static const struct mips_cpu_info *
19165 mips_cpu_info_from_arch (int arch)
19169 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19170 if (arch == mips_cpu_info_table[i].cpu)
19171 return (&mips_cpu_info_table[i]);
19177 show (FILE *stream, const char *string, int *col_p, int *first_p)
19181 fprintf (stream, "%24s", "");
19186 fprintf (stream, ", ");
19190 if (*col_p + strlen (string) > 72)
19192 fprintf (stream, "\n%24s", "");
19196 fprintf (stream, "%s", string);
19197 *col_p += strlen (string);
19203 md_show_usage (FILE *stream)
19208 fprintf (stream, _("\
19210 -EB generate big endian output\n\
19211 -EL generate little endian output\n\
19212 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19213 -G NUM allow referencing objects up to NUM bytes\n\
19214 implicitly with the gp register [default 8]\n"));
19215 fprintf (stream, _("\
19216 -mips1 generate MIPS ISA I instructions\n\
19217 -mips2 generate MIPS ISA II instructions\n\
19218 -mips3 generate MIPS ISA III instructions\n\
19219 -mips4 generate MIPS ISA IV instructions\n\
19220 -mips5 generate MIPS ISA V instructions\n\
19221 -mips32 generate MIPS32 ISA instructions\n\
19222 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19223 -mips64 generate MIPS64 ISA instructions\n\
19224 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19225 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19229 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19230 show (stream, mips_cpu_info_table[i].name, &column, &first);
19231 show (stream, "from-abi", &column, &first);
19232 fputc ('\n', stream);
19234 fprintf (stream, _("\
19235 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19236 -no-mCPU don't generate code specific to CPU.\n\
19237 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19241 show (stream, "3900", &column, &first);
19242 show (stream, "4010", &column, &first);
19243 show (stream, "4100", &column, &first);
19244 show (stream, "4650", &column, &first);
19245 fputc ('\n', stream);
19247 fprintf (stream, _("\
19248 -mips16 generate mips16 instructions\n\
19249 -no-mips16 do not generate mips16 instructions\n"));
19250 fprintf (stream, _("\
19251 -mmicromips generate microMIPS instructions\n\
19252 -mno-micromips do not generate microMIPS instructions\n"));
19253 fprintf (stream, _("\
19254 -msmartmips generate smartmips instructions\n\
19255 -mno-smartmips do not generate smartmips instructions\n"));
19256 fprintf (stream, _("\
19257 -mdsp generate DSP instructions\n\
19258 -mno-dsp do not generate DSP instructions\n"));
19259 fprintf (stream, _("\
19260 -mdspr2 generate DSP R2 instructions\n\
19261 -mno-dspr2 do not generate DSP R2 instructions\n"));
19262 fprintf (stream, _("\
19263 -mmt generate MT instructions\n\
19264 -mno-mt do not generate MT instructions\n"));
19265 fprintf (stream, _("\
19266 -mmcu generate MCU instructions\n\
19267 -mno-mcu do not generate MCU instructions\n"));
19268 fprintf (stream, _("\
19269 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19270 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19271 -mfix-vr4120 work around certain VR4120 errata\n\
19272 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19273 -mfix-24k insert a nop after ERET and DERET instructions\n\
19274 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19275 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19276 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19277 -msym32 assume all symbols have 32-bit values\n\
19278 -O0 remove unneeded NOPs, do not swap branches\n\
19279 -O remove unneeded NOPs and swap branches\n\
19280 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19281 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19282 fprintf (stream, _("\
19283 -mhard-float allow floating-point instructions\n\
19284 -msoft-float do not allow floating-point instructions\n\
19285 -msingle-float only allow 32-bit floating-point operations\n\
19286 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19287 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19290 fprintf (stream, _("\
19291 -KPIC, -call_shared generate SVR4 position independent code\n\
19292 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19293 -mvxworks-pic generate VxWorks position independent code\n\
19294 -non_shared do not generate code that can operate with DSOs\n\
19295 -xgot assume a 32 bit GOT\n\
19296 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19297 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19298 position dependent (non shared) code\n\
19299 -mabi=ABI create ABI conformant object file for:\n"));
19303 show (stream, "32", &column, &first);
19304 show (stream, "o64", &column, &first);
19305 show (stream, "n32", &column, &first);
19306 show (stream, "64", &column, &first);
19307 show (stream, "eabi", &column, &first);
19309 fputc ('\n', stream);
19311 fprintf (stream, _("\
19312 -32 create o32 ABI object file (default)\n\
19313 -n32 create n32 ABI object file\n\
19314 -64 create 64 ABI object file\n"));
19320 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19322 if (HAVE_64BIT_SYMBOLS)
19323 return dwarf2_format_64bit_irix;
19325 return dwarf2_format_32bit;
19330 mips_dwarf2_addr_size (void)
19332 if (HAVE_64BIT_OBJECTS)
19338 /* Standard calling conventions leave the CFA at SP on entry. */
19340 mips_cfi_frame_initial_instructions (void)
19342 cfi_add_CFA_def_cfa_register (SP);
19346 tc_mips_regname_to_dw2regnum (char *regname)
19348 unsigned int regnum = -1;
19351 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))