1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
97 #define PIC_CALL_REG 25
105 #define ILLEGAL_REG (32)
107 #define AT mips_opts.at
109 /* Allow override of standard little-endian ECOFF format. */
111 #ifndef ECOFF_LITTLE_FORMAT
112 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
115 extern int target_big_endian;
117 /* The name of the readonly data section. */
118 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
122 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
126 /* Ways in which an instruction can be "appended" to the output. */
128 /* Just add it normally. */
131 /* Add it normally and then add a nop. */
134 /* Turn an instruction with a delay slot into a "compact" version. */
137 /* Insert the instruction before the last one. */
141 /* Information about an instruction, including its format, operands
145 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
146 const struct mips_opcode *insn_mo;
148 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
149 a copy of INSN_MO->match with the operands filled in. If we have
150 decided to use an extended MIPS16 instruction, this includes the
152 unsigned long insn_opcode;
154 /* The frag that contains the instruction. */
157 /* The offset into FRAG of the first instruction byte. */
160 /* The relocs associated with the instruction, if any. */
163 /* True if this entry cannot be moved from its current position. */
164 unsigned int fixed_p : 1;
166 /* True if this instruction occurred in a .set noreorder block. */
167 unsigned int noreorder_p : 1;
169 /* True for mips16 instructions that jump to an absolute address. */
170 unsigned int mips16_absolute_jump_p : 1;
172 /* True if this instruction is complete. */
173 unsigned int complete_p : 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi = NO_ABI;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls = FALSE;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared = TRUE;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). These are set to -1
208 if they have not been initialized. Changed by `.set <asename>', by
209 command line options, and based on the default architecture. */
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
222 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
223 1 if we are, and -1 if the value has not been initialized. Changed
224 by `.set micromips' and `.set nomicromips', and the -mmicromips
225 and -mno-micromips command line options, and the default CPU. */
227 /* Non-zero if we should not reorder instructions. Changed by `.set
228 reorder' and `.set noreorder'. */
230 /* Non-zero if we should not permit the register designated "assembler
231 temporary" to be used in instructions. The value is the register
232 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
233 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
235 /* Non-zero if we should warn when a macro instruction expands into
236 more than one machine instruction. Changed by `.set nomacro' and
238 int warn_about_macros;
239 /* Non-zero if we should not move instructions. Changed by `.set
240 move', `.set volatile', `.set nomove', and `.set novolatile'. */
242 /* Non-zero if we should not optimize branches by moving the target
243 of the branch into the delay slot. Actually, we don't perform
244 this optimization anyhow. Changed by `.set bopt' and `.set
247 /* Non-zero if we should not autoextend mips16 instructions.
248 Changed by `.set autoextend' and `.set noautoextend'. */
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
258 /* True if ".set sym32" is in effect. */
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bfd_boolean soft_float;
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bfd_boolean single_float;
271 /* This is the struct we use to hold the current set of options. Note
272 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
273 -1 to indicate that they have not been initialized. */
275 /* True if -mgp32 was passed. */
276 static int file_mips_gp32 = -1;
278 /* True if -mfp32 was passed. */
279 static int file_mips_fp32 = -1;
281 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
282 static int file_mips_soft_float = 0;
284 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
285 static int file_mips_single_float = 0;
287 static struct mips_set_options mips_opts =
289 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
290 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
291 /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0,
292 /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
293 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
294 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* True if -mips3d was passed or implied by arguments passed on the
330 command line (e.g., by -march). */
331 static int file_ase_mips3d;
333 /* True if -mdmx was passed or implied by arguments passed on the
334 command line (e.g., by -march). */
335 static int file_ase_mdmx;
337 /* True if -msmartmips was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_smartmips;
341 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2)
344 /* True if -mdsp was passed or implied by arguments passed on the
345 command line (e.g., by -march). */
346 static int file_ase_dsp;
348 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
349 || mips_opts.isa == ISA_MIPS64R2 \
350 || mips_opts.micromips)
352 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
354 /* True if -mdspr2 was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356 static int file_ase_dspr2;
358 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2 \
360 || mips_opts.micromips)
362 /* True if -mmt was passed or implied by arguments passed on the
363 command line (e.g., by -march). */
364 static int file_ase_mt;
366 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
367 || mips_opts.isa == ISA_MIPS64R2)
369 #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \
370 || mips_opts.isa == ISA_MIPS64R2 \
371 || mips_opts.micromips)
373 /* The argument of the -march= flag. The architecture we are assembling. */
374 static int file_mips_arch = CPU_UNKNOWN;
375 static const char *mips_arch_string;
377 /* The argument of the -mtune= flag. The architecture for which we
379 static int mips_tune = CPU_UNKNOWN;
380 static const char *mips_tune_string;
382 /* True when generating 32-bit code for a 64-bit processor. */
383 static int mips_32bitmode = 0;
385 /* True if the given ABI requires 32-bit registers. */
386 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
388 /* Likewise 64-bit registers. */
389 #define ABI_NEEDS_64BIT_REGS(ABI) \
391 || (ABI) == N64_ABI \
394 /* Return true if ISA supports 64 bit wide gp registers. */
395 #define ISA_HAS_64BIT_REGS(ISA) \
396 ((ISA) == ISA_MIPS3 \
397 || (ISA) == ISA_MIPS4 \
398 || (ISA) == ISA_MIPS5 \
399 || (ISA) == ISA_MIPS64 \
400 || (ISA) == ISA_MIPS64R2)
402 /* Return true if ISA supports 64 bit wide float registers. */
403 #define ISA_HAS_64BIT_FPRS(ISA) \
404 ((ISA) == ISA_MIPS3 \
405 || (ISA) == ISA_MIPS4 \
406 || (ISA) == ISA_MIPS5 \
407 || (ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64 \
409 || (ISA) == ISA_MIPS64R2)
411 /* Return true if ISA supports 64-bit right rotate (dror et al.)
413 #define ISA_HAS_DROR(ISA) \
414 ((ISA) == ISA_MIPS64R2 \
415 || (mips_opts.micromips \
416 && ISA_HAS_64BIT_REGS (ISA)) \
419 /* Return true if ISA supports 32-bit right rotate (ror et al.)
421 #define ISA_HAS_ROR(ISA) \
422 ((ISA) == ISA_MIPS32R2 \
423 || (ISA) == ISA_MIPS64R2 \
424 || mips_opts.ase_smartmips \
425 || mips_opts.micromips \
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
430 ((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS64 \
433 || (ISA) == ISA_MIPS64R2)
435 /* Return true if ISA supports move to/from high part of a 64-bit
436 floating-point register. */
437 #define ISA_HAS_MXHC1(ISA) \
438 ((ISA) == ISA_MIPS32R2 \
439 || (ISA) == ISA_MIPS64R2)
441 #define HAVE_32BIT_GPRS \
442 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
444 #define HAVE_32BIT_FPRS \
445 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
447 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
448 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
450 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
452 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
454 /* True if relocations are stored in-place. */
455 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
457 /* The ABI-derived address size. */
458 #define HAVE_64BIT_ADDRESSES \
459 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
460 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
462 /* The size of symbolic constants (i.e., expressions of the form
463 "SYMBOL" or "SYMBOL + OFFSET"). */
464 #define HAVE_32BIT_SYMBOLS \
465 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
466 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
468 /* Addresses are loaded in different ways, depending on the address size
469 in use. The n32 ABI Documentation also mandates the use of additions
470 with overflow checking, but existing implementations don't follow it. */
471 #define ADDRESS_ADD_INSN \
472 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
474 #define ADDRESS_ADDI_INSN \
475 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
477 #define ADDRESS_LOAD_INSN \
478 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
480 #define ADDRESS_STORE_INSN \
481 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
483 /* Return true if the given CPU supports the MIPS16 ASE. */
484 #define CPU_HAS_MIPS16(cpu) \
485 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
486 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
488 /* Return true if the given CPU supports the microMIPS ASE. */
489 #define CPU_HAS_MICROMIPS(cpu) 0
491 /* True if CPU has a dror instruction. */
492 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
494 /* True if CPU has a ror instruction. */
495 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
497 /* True if CPU is in the Octeon family */
498 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
500 /* True if CPU has seq/sne and seqi/snei instructions. */
501 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
503 /* True if mflo and mfhi can be immediately followed by instructions
504 which write to the HI and LO registers.
506 According to MIPS specifications, MIPS ISAs I, II, and III need
507 (at least) two instructions between the reads of HI/LO and
508 instructions which write them, and later ISAs do not. Contradicting
509 the MIPS specifications, some MIPS IV processor user manuals (e.g.
510 the UM for the NEC Vr5000) document needing the instructions between
511 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
512 MIPS64 and later ISAs to have the interlocks, plus any specific
513 earlier-ISA CPUs for which CPU documentation declares that the
514 instructions are really interlocked. */
515 #define hilo_interlocks \
516 (mips_opts.isa == ISA_MIPS32 \
517 || mips_opts.isa == ISA_MIPS32R2 \
518 || mips_opts.isa == ISA_MIPS64 \
519 || mips_opts.isa == ISA_MIPS64R2 \
520 || mips_opts.arch == CPU_R4010 \
521 || mips_opts.arch == CPU_R10000 \
522 || mips_opts.arch == CPU_R12000 \
523 || mips_opts.arch == CPU_R14000 \
524 || mips_opts.arch == CPU_R16000 \
525 || mips_opts.arch == CPU_RM7000 \
526 || mips_opts.arch == CPU_VR5500 \
527 || mips_opts.micromips \
530 /* Whether the processor uses hardware interlocks to protect reads
531 from the GPRs after they are loaded from memory, and thus does not
532 require nops to be inserted. This applies to instructions marked
533 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
534 level I and microMIPS mode instructions are always interlocked. */
535 #define gpr_interlocks \
536 (mips_opts.isa != ISA_MIPS1 \
537 || mips_opts.arch == CPU_R3900 \
538 || mips_opts.micromips \
541 /* Whether the processor uses hardware interlocks to avoid delays
542 required by coprocessor instructions, and thus does not require
543 nops to be inserted. This applies to instructions marked
544 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
545 between instructions marked INSN_WRITE_COND_CODE and ones marked
546 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
547 levels I, II, and III and microMIPS mode instructions are always
549 /* Itbl support may require additional care here. */
550 #define cop_interlocks \
551 ((mips_opts.isa != ISA_MIPS1 \
552 && mips_opts.isa != ISA_MIPS2 \
553 && mips_opts.isa != ISA_MIPS3) \
554 || mips_opts.arch == CPU_R4300 \
555 || mips_opts.micromips \
558 /* Whether the processor uses hardware interlocks to protect reads
559 from coprocessor registers after they are loaded from memory, and
560 thus does not require nops to be inserted. This applies to
561 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
562 requires at MIPS ISA level I and microMIPS mode instructions are
563 always interlocked. */
564 #define cop_mem_interlocks \
565 (mips_opts.isa != ISA_MIPS1 \
566 || mips_opts.micromips \
569 /* Is this a mfhi or mflo instruction? */
570 #define MF_HILO_INSN(PINFO) \
571 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
573 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
574 has been selected. This implies, in particular, that addresses of text
575 labels have their LSB set. */
576 #define HAVE_CODE_COMPRESSION \
577 ((mips_opts.mips16 | mips_opts.micromips) != 0)
579 /* MIPS PIC level. */
581 enum mips_pic_level mips_pic;
583 /* 1 if we should generate 32 bit offsets from the $gp register in
584 SVR4_PIC mode. Currently has no meaning in other modes. */
585 static int mips_big_got = 0;
587 /* 1 if trap instructions should used for overflow rather than break
589 static int mips_trap = 0;
591 /* 1 if double width floating point constants should not be constructed
592 by assembling two single width halves into two single width floating
593 point registers which just happen to alias the double width destination
594 register. On some architectures this aliasing can be disabled by a bit
595 in the status register, and the setting of this bit cannot be determined
596 automatically at assemble time. */
597 static int mips_disable_float_construction;
599 /* Non-zero if any .set noreorder directives were used. */
601 static int mips_any_noreorder;
603 /* Non-zero if nops should be inserted when the register referenced in
604 an mfhi/mflo instruction is read in the next two instructions. */
605 static int mips_7000_hilo_fix;
607 /* The size of objects in the small data section. */
608 static unsigned int g_switch_value = 8;
609 /* Whether the -G option was used. */
610 static int g_switch_seen = 0;
615 /* If we can determine in advance that GP optimization won't be
616 possible, we can skip the relaxation stuff that tries to produce
617 GP-relative references. This makes delay slot optimization work
620 This function can only provide a guess, but it seems to work for
621 gcc output. It needs to guess right for gcc, otherwise gcc
622 will put what it thinks is a GP-relative instruction in a branch
625 I don't know if a fix is needed for the SVR4_PIC mode. I've only
626 fixed it for the non-PIC mode. KR 95/04/07 */
627 static int nopic_need_relax (symbolS *, int);
629 /* handle of the OPCODE hash table */
630 static struct hash_control *op_hash = NULL;
632 /* The opcode hash table we use for the mips16. */
633 static struct hash_control *mips16_op_hash = NULL;
635 /* The opcode hash table we use for the microMIPS ASE. */
636 static struct hash_control *micromips_op_hash = NULL;
638 /* This array holds the chars that always start a comment. If the
639 pre-processor is disabled, these aren't very useful */
640 const char comment_chars[] = "#";
642 /* This array holds the chars that only start a comment at the beginning of
643 a line. If the line seems to have the form '# 123 filename'
644 .line and .file directives will appear in the pre-processed output */
645 /* Note that input_file.c hand checks for '#' at the beginning of the
646 first line of the input file. This is because the compiler outputs
647 #NO_APP at the beginning of its output. */
648 /* Also note that C style comments are always supported. */
649 const char line_comment_chars[] = "#";
651 /* This array holds machine specific line separator characters. */
652 const char line_separator_chars[] = ";";
654 /* Chars that can be used to separate mant from exp in floating point nums */
655 const char EXP_CHARS[] = "eE";
657 /* Chars that mean this number is a floating point constant */
660 const char FLT_CHARS[] = "rRsSfFdDxXpP";
662 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
663 changed in read.c . Ideally it shouldn't have to know about it at all,
664 but nothing is ideal around here.
667 static char *insn_error;
669 static int auto_align = 1;
671 /* When outputting SVR4 PIC code, the assembler needs to know the
672 offset in the stack frame from which to restore the $gp register.
673 This is set by the .cprestore pseudo-op, and saved in this
675 static offsetT mips_cprestore_offset = -1;
677 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
678 more optimizations, it can use a register value instead of a memory-saved
679 offset and even an other register than $gp as global pointer. */
680 static offsetT mips_cpreturn_offset = -1;
681 static int mips_cpreturn_register = -1;
682 static int mips_gp_register = GP;
683 static int mips_gprel_offset = 0;
685 /* Whether mips_cprestore_offset has been set in the current function
686 (or whether it has already been warned about, if not). */
687 static int mips_cprestore_valid = 0;
689 /* This is the register which holds the stack frame, as set by the
690 .frame pseudo-op. This is needed to implement .cprestore. */
691 static int mips_frame_reg = SP;
693 /* Whether mips_frame_reg has been set in the current function
694 (or whether it has already been warned about, if not). */
695 static int mips_frame_reg_valid = 0;
697 /* To output NOP instructions correctly, we need to keep information
698 about the previous two instructions. */
700 /* Whether we are optimizing. The default value of 2 means to remove
701 unneeded NOPs and swap branch instructions when possible. A value
702 of 1 means to not swap branches. A value of 0 means to always
704 static int mips_optimize = 2;
706 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
707 equivalent to seeing no -g option at all. */
708 static int mips_debug = 0;
710 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
711 #define MAX_VR4130_NOPS 4
713 /* The maximum number of NOPs needed to fill delay slots. */
714 #define MAX_DELAY_NOPS 2
716 /* The maximum number of NOPs needed for any purpose. */
719 /* A list of previous instructions, with index 0 being the most recent.
720 We need to look back MAX_NOPS instructions when filling delay slots
721 or working around processor errata. We need to look back one
722 instruction further if we're thinking about using history[0] to
723 fill a branch delay slot. */
724 static struct mips_cl_insn history[1 + MAX_NOPS];
726 /* Nop instructions used by emit_nop. */
727 static struct mips_cl_insn nop_insn;
728 static struct mips_cl_insn mips16_nop_insn;
729 static struct mips_cl_insn micromips_nop16_insn;
730 static struct mips_cl_insn micromips_nop32_insn;
732 /* The appropriate nop for the current mode. */
733 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
734 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
736 /* The size of NOP_INSN in bytes. */
737 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
739 /* If this is set, it points to a frag holding nop instructions which
740 were inserted before the start of a noreorder section. If those
741 nops turn out to be unnecessary, the size of the frag can be
743 static fragS *prev_nop_frag;
745 /* The number of nop instructions we created in prev_nop_frag. */
746 static int prev_nop_frag_holds;
748 /* The number of nop instructions that we know we need in
750 static int prev_nop_frag_required;
752 /* The number of instructions we've seen since prev_nop_frag. */
753 static int prev_nop_frag_since;
755 /* For ECOFF and ELF, relocations against symbols are done in two
756 parts, with a HI relocation and a LO relocation. Each relocation
757 has only 16 bits of space to store an addend. This means that in
758 order for the linker to handle carries correctly, it must be able
759 to locate both the HI and the LO relocation. This means that the
760 relocations must appear in order in the relocation table.
762 In order to implement this, we keep track of each unmatched HI
763 relocation. We then sort them so that they immediately precede the
764 corresponding LO relocation. */
769 struct mips_hi_fixup *next;
772 /* The section this fixup is in. */
776 /* The list of unmatched HI relocs. */
778 static struct mips_hi_fixup *mips_hi_fixup_list;
780 /* The frag containing the last explicit relocation operator.
781 Null if explicit relocations have not been used. */
783 static fragS *prev_reloc_op_frag;
785 /* Map normal MIPS register numbers to mips16 register numbers. */
787 #define X ILLEGAL_REG
788 static const int mips32_to_16_reg_map[] =
790 X, X, 2, 3, 4, 5, 6, 7,
791 X, X, X, X, X, X, X, X,
792 0, 1, X, X, X, X, X, X,
793 X, X, X, X, X, X, X, X
797 /* Map mips16 register numbers to normal MIPS register numbers. */
799 static const unsigned int mips16_to_32_reg_map[] =
801 16, 17, 2, 3, 4, 5, 6, 7
804 /* Map normal MIPS register numbers to microMIPS register numbers. */
806 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
807 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
808 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
809 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
810 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
811 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
812 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
814 #define X ILLEGAL_REG
815 /* reg type h: 4, 5, 6. */
816 static const int mips32_to_micromips_reg_h_map[] =
818 X, X, X, X, 4, 5, 6, X,
819 X, X, X, X, X, X, X, X,
820 X, X, X, X, X, X, X, X,
821 X, X, X, X, X, X, X, X
824 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
825 static const int mips32_to_micromips_reg_m_map[] =
827 0, X, 2, 3, X, X, X, X,
828 X, X, X, X, X, X, X, X,
829 4, 1, 5, 6, 7, X, X, X,
830 X, X, X, X, X, X, X, X
833 /* reg type q: 0, 2-7. 17. */
834 static const int mips32_to_micromips_reg_q_map[] =
836 0, X, 2, 3, 4, 5, 6, 7,
837 X, X, X, X, X, X, X, X,
838 X, 1, X, X, X, X, X, X,
839 X, X, X, X, X, X, X, X
842 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
845 /* Map microMIPS register numbers to normal MIPS register numbers. */
847 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
848 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
849 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
850 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
851 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
852 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
854 /* The microMIPS registers with type h. */
855 static const unsigned int micromips_to_32_reg_h_map[] =
857 5, 5, 6, 4, 4, 4, 4, 4
860 /* The microMIPS registers with type i. */
861 static const unsigned int micromips_to_32_reg_i_map[] =
863 6, 7, 7, 21, 22, 5, 6, 7
866 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
868 /* The microMIPS registers with type m. */
869 static const unsigned int micromips_to_32_reg_m_map[] =
871 0, 17, 2, 3, 16, 18, 19, 20
874 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
876 /* The microMIPS registers with type q. */
877 static const unsigned int micromips_to_32_reg_q_map[] =
879 0, 17, 2, 3, 4, 5, 6, 7
882 /* microMIPS imm type B. */
883 static const int micromips_imm_b_map[] =
885 1, 4, 8, 12, 16, 20, 24, -1
888 /* microMIPS imm type C. */
889 static const int micromips_imm_c_map[] =
891 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
894 /* Classifies the kind of instructions we're interested in when
895 implementing -mfix-vr4120. */
896 enum fix_vr4120_class
904 NUM_FIX_VR4120_CLASSES
907 /* ...likewise -mfix-loongson2f-jump. */
908 static bfd_boolean mips_fix_loongson2f_jump;
910 /* ...likewise -mfix-loongson2f-nop. */
911 static bfd_boolean mips_fix_loongson2f_nop;
913 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
914 static bfd_boolean mips_fix_loongson2f;
916 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
917 there must be at least one other instruction between an instruction
918 of type X and an instruction of type Y. */
919 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
921 /* True if -mfix-vr4120 is in force. */
922 static int mips_fix_vr4120;
924 /* ...likewise -mfix-vr4130. */
925 static int mips_fix_vr4130;
927 /* ...likewise -mfix-24k. */
928 static int mips_fix_24k;
930 /* ...likewise -mfix-cn63xxp1 */
931 static bfd_boolean mips_fix_cn63xxp1;
933 /* We don't relax branches by default, since this causes us to expand
934 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
935 fail to compute the offset before expanding the macro to the most
936 efficient expansion. */
938 static int mips_relax_branch;
940 /* The expansion of many macros depends on the type of symbol that
941 they refer to. For example, when generating position-dependent code,
942 a macro that refers to a symbol may have two different expansions,
943 one which uses GP-relative addresses and one which uses absolute
944 addresses. When generating SVR4-style PIC, a macro may have
945 different expansions for local and global symbols.
947 We handle these situations by generating both sequences and putting
948 them in variant frags. In position-dependent code, the first sequence
949 will be the GP-relative one and the second sequence will be the
950 absolute one. In SVR4 PIC, the first sequence will be for global
951 symbols and the second will be for local symbols.
953 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
954 SECOND are the lengths of the two sequences in bytes. These fields
955 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
956 the subtype has the following flags:
959 Set if it has been decided that we should use the second
960 sequence instead of the first.
963 Set in the first variant frag if the macro's second implementation
964 is longer than its first. This refers to the macro as a whole,
965 not an individual relaxation.
968 Set in the first variant frag if the macro appeared in a .set nomacro
969 block and if one alternative requires a warning but the other does not.
972 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
975 RELAX_DELAY_SLOT_16BIT
976 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
979 RELAX_DELAY_SLOT_SIZE_FIRST
980 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
981 the macro is of the wrong size for the branch delay slot.
983 RELAX_DELAY_SLOT_SIZE_SECOND
984 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
985 the macro is of the wrong size for the branch delay slot.
987 The frag's "opcode" points to the first fixup for relaxable code.
989 Relaxable macros are generated using a sequence such as:
991 relax_start (SYMBOL);
992 ... generate first expansion ...
994 ... generate second expansion ...
997 The code and fixups for the unwanted alternative are discarded
998 by md_convert_frag. */
999 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
1001 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1002 #define RELAX_SECOND(X) ((X) & 0xff)
1003 #define RELAX_USE_SECOND 0x10000
1004 #define RELAX_SECOND_LONGER 0x20000
1005 #define RELAX_NOMACRO 0x40000
1006 #define RELAX_DELAY_SLOT 0x80000
1007 #define RELAX_DELAY_SLOT_16BIT 0x100000
1008 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
1009 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
1011 /* Branch without likely bit. If label is out of range, we turn:
1013 beq reg1, reg2, label
1023 with the following opcode replacements:
1030 bltzal <-> bgezal (with jal label instead of j label)
1032 Even though keeping the delay slot instruction in the delay slot of
1033 the branch would be more efficient, it would be very tricky to do
1034 correctly, because we'd have to introduce a variable frag *after*
1035 the delay slot instruction, and expand that instead. Let's do it
1036 the easy way for now, even if the branch-not-taken case now costs
1037 one additional instruction. Out-of-range branches are not supposed
1038 to be common, anyway.
1040 Branch likely. If label is out of range, we turn:
1042 beql reg1, reg2, label
1043 delay slot (annulled if branch not taken)
1052 delay slot (executed only if branch taken)
1055 It would be possible to generate a shorter sequence by losing the
1056 likely bit, generating something like:
1061 delay slot (executed only if branch taken)
1073 bltzall -> bgezal (with jal label instead of j label)
1074 bgezall -> bltzal (ditto)
1077 but it's not clear that it would actually improve performance. */
1078 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1079 ((relax_substateT) \
1082 | ((toofar) ? 0x20 : 0) \
1083 | ((link) ? 0x40 : 0) \
1084 | ((likely) ? 0x80 : 0) \
1085 | ((uncond) ? 0x100 : 0)))
1086 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1087 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1088 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1089 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1090 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1091 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1093 /* For mips16 code, we use an entirely different form of relaxation.
1094 mips16 supports two versions of most instructions which take
1095 immediate values: a small one which takes some small value, and a
1096 larger one which takes a 16 bit value. Since branches also follow
1097 this pattern, relaxing these values is required.
1099 We can assemble both mips16 and normal MIPS code in a single
1100 object. Therefore, we need to support this type of relaxation at
1101 the same time that we support the relaxation described above. We
1102 use the high bit of the subtype field to distinguish these cases.
1104 The information we store for this type of relaxation is the
1105 argument code found in the opcode file for this relocation, whether
1106 the user explicitly requested a small or extended form, and whether
1107 the relocation is in a jump or jal delay slot. That tells us the
1108 size of the value, and how it should be stored. We also store
1109 whether the fragment is considered to be extended or not. We also
1110 store whether this is known to be a branch to a different section,
1111 whether we have tried to relax this frag yet, and whether we have
1112 ever extended a PC relative fragment because of a shift count. */
1113 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1116 | ((small) ? 0x100 : 0) \
1117 | ((ext) ? 0x200 : 0) \
1118 | ((dslot) ? 0x400 : 0) \
1119 | ((jal_dslot) ? 0x800 : 0))
1120 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1121 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1123 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1124 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1125 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1126 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1127 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1128 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1129 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1130 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1131 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1133 /* For microMIPS code, we use relaxation similar to one we use for
1134 MIPS16 code. Some instructions that take immediate values support
1135 two encodings: a small one which takes some small value, and a
1136 larger one which takes a 16 bit value. As some branches also follow
1137 this pattern, relaxing these values is required.
1139 We can assemble both microMIPS and normal MIPS code in a single
1140 object. Therefore, we need to support this type of relaxation at
1141 the same time that we support the relaxation described above. We
1142 use one of the high bits of the subtype field to distinguish these
1145 The information we store for this type of relaxation is the argument
1146 code found in the opcode file for this relocation, the register
1147 selected as the assembler temporary, whether the branch is
1148 unconditional, whether it is compact, whether it stores the link
1149 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1150 branches to a sequence of instructions is enabled, and whether the
1151 displacement of a branch is too large to fit as an immediate argument
1152 of a 16-bit and a 32-bit branch, respectively. */
1153 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1154 relax32, toofar16, toofar32) \
1157 | (((at) & 0x1f) << 8) \
1158 | ((uncond) ? 0x2000 : 0) \
1159 | ((compact) ? 0x4000 : 0) \
1160 | ((link) ? 0x8000 : 0) \
1161 | ((relax32) ? 0x10000 : 0) \
1162 | ((toofar16) ? 0x20000 : 0) \
1163 | ((toofar32) ? 0x40000 : 0))
1164 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1165 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1166 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1167 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1168 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1169 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1170 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1172 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1173 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1174 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1175 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1176 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1177 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1179 /* Sign-extend 16-bit value X. */
1180 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1182 /* Is the given value a sign-extended 32-bit value? */
1183 #define IS_SEXT_32BIT_NUM(x) \
1184 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1185 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1187 /* Is the given value a sign-extended 16-bit value? */
1188 #define IS_SEXT_16BIT_NUM(x) \
1189 (((x) &~ (offsetT) 0x7fff) == 0 \
1190 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1192 /* Is the given value a sign-extended 12-bit value? */
1193 #define IS_SEXT_12BIT_NUM(x) \
1194 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1196 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1197 #define IS_ZEXT_32BIT_NUM(x) \
1198 (((x) &~ (offsetT) 0xffffffff) == 0 \
1199 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1201 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1202 VALUE << SHIFT. VALUE is evaluated exactly once. */
1203 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1204 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1205 | (((VALUE) & (MASK)) << (SHIFT)))
1207 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1209 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1210 (((STRUCT) >> (SHIFT)) & (MASK))
1212 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1213 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1215 include/opcode/mips.h specifies operand fields using the macros
1216 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1217 with "MIPS16OP" instead of "OP". */
1218 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1221 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1222 OP_MASK_##FIELD, OP_SH_##FIELD); \
1224 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1225 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1227 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1228 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1229 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1231 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1232 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1234 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1235 : EXTRACT_BITS ((INSN).insn_opcode, \
1236 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1237 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1238 EXTRACT_BITS ((INSN).insn_opcode, \
1239 MIPS16OP_MASK_##FIELD, \
1240 MIPS16OP_SH_##FIELD)
1242 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1243 #define MIPS16_EXTEND (0xf000U << 16)
1245 /* Whether or not we are emitting a branch-likely macro. */
1246 static bfd_boolean emit_branch_likely_macro = FALSE;
1248 /* Global variables used when generating relaxable macros. See the
1249 comment above RELAX_ENCODE for more details about how relaxation
1252 /* 0 if we're not emitting a relaxable macro.
1253 1 if we're emitting the first of the two relaxation alternatives.
1254 2 if we're emitting the second alternative. */
1257 /* The first relaxable fixup in the current frag. (In other words,
1258 the first fixup that refers to relaxable code.) */
1261 /* sizes[0] says how many bytes of the first alternative are stored in
1262 the current frag. Likewise sizes[1] for the second alternative. */
1263 unsigned int sizes[2];
1265 /* The symbol on which the choice of sequence depends. */
1269 /* Global variables used to decide whether a macro needs a warning. */
1271 /* True if the macro is in a branch delay slot. */
1272 bfd_boolean delay_slot_p;
1274 /* Set to the length in bytes required if the macro is in a delay slot
1275 that requires a specific length of instruction, otherwise zero. */
1276 unsigned int delay_slot_length;
1278 /* For relaxable macros, sizes[0] is the length of the first alternative
1279 in bytes and sizes[1] is the length of the second alternative.
1280 For non-relaxable macros, both elements give the length of the
1282 unsigned int sizes[2];
1284 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1285 instruction of the first alternative in bytes and first_insn_sizes[1]
1286 is the length of the first instruction of the second alternative.
1287 For non-relaxable macros, both elements give the length of the first
1288 instruction in bytes.
1290 Set to zero if we haven't yet seen the first instruction. */
1291 unsigned int first_insn_sizes[2];
1293 /* For relaxable macros, insns[0] is the number of instructions for the
1294 first alternative and insns[1] is the number of instructions for the
1297 For non-relaxable macros, both elements give the number of
1298 instructions for the macro. */
1299 unsigned int insns[2];
1301 /* The first variant frag for this macro. */
1303 } mips_macro_warning;
1305 /* Prototypes for static functions. */
1307 #define internalError() \
1308 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1310 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1312 static void append_insn
1313 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1314 bfd_boolean expansionp);
1315 static void mips_no_prev_insn (void);
1316 static void macro_build (expressionS *, const char *, const char *, ...);
1317 static void mips16_macro_build
1318 (expressionS *, const char *, const char *, va_list *);
1319 static void load_register (int, expressionS *, int);
1320 static void macro_start (void);
1321 static void macro_end (void);
1322 static void macro (struct mips_cl_insn * ip);
1323 static void mips16_macro (struct mips_cl_insn * ip);
1324 static void mips_ip (char *str, struct mips_cl_insn * ip);
1325 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1326 static void mips16_immed
1327 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1328 unsigned int, unsigned long *);
1329 static size_t my_getSmallExpression
1330 (expressionS *, bfd_reloc_code_real_type *, char *);
1331 static void my_getExpression (expressionS *, char *);
1332 static void s_align (int);
1333 static void s_change_sec (int);
1334 static void s_change_section (int);
1335 static void s_cons (int);
1336 static void s_float_cons (int);
1337 static void s_mips_globl (int);
1338 static void s_option (int);
1339 static void s_mipsset (int);
1340 static void s_abicalls (int);
1341 static void s_cpload (int);
1342 static void s_cpsetup (int);
1343 static void s_cplocal (int);
1344 static void s_cprestore (int);
1345 static void s_cpreturn (int);
1346 static void s_dtprelword (int);
1347 static void s_dtpreldword (int);
1348 static void s_tprelword (int);
1349 static void s_tpreldword (int);
1350 static void s_gpvalue (int);
1351 static void s_gpword (int);
1352 static void s_gpdword (int);
1353 static void s_cpadd (int);
1354 static void s_insn (int);
1355 static void md_obj_begin (void);
1356 static void md_obj_end (void);
1357 static void s_mips_ent (int);
1358 static void s_mips_end (int);
1359 static void s_mips_frame (int);
1360 static void s_mips_mask (int reg_type);
1361 static void s_mips_stab (int);
1362 static void s_mips_weakext (int);
1363 static void s_mips_file (int);
1364 static void s_mips_loc (int);
1365 static bfd_boolean pic_need_relax (symbolS *, asection *);
1366 static int relaxed_branch_length (fragS *, asection *, int);
1367 static int validate_mips_insn (const struct mips_opcode *);
1368 static int validate_micromips_insn (const struct mips_opcode *);
1369 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1370 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1372 /* Table and functions used to map between CPU/ISA names, and
1373 ISA levels, and CPU numbers. */
1375 struct mips_cpu_info
1377 const char *name; /* CPU or ISA name. */
1378 int flags; /* ASEs available, or ISA flag. */
1379 int isa; /* ISA level. */
1380 int cpu; /* CPU number (default CPU if ISA). */
1383 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1384 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1385 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1386 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1387 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1388 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1389 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1390 #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
1392 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1393 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1394 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1398 The following pseudo-ops from the Kane and Heinrich MIPS book
1399 should be defined here, but are currently unsupported: .alias,
1400 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1402 The following pseudo-ops from the Kane and Heinrich MIPS book are
1403 specific to the type of debugging information being generated, and
1404 should be defined by the object format: .aent, .begin, .bend,
1405 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1408 The following pseudo-ops from the Kane and Heinrich MIPS book are
1409 not MIPS CPU specific, but are also not specific to the object file
1410 format. This file is probably the best place to define them, but
1411 they are not currently supported: .asm0, .endr, .lab, .struct. */
1413 static const pseudo_typeS mips_pseudo_table[] =
1415 /* MIPS specific pseudo-ops. */
1416 {"option", s_option, 0},
1417 {"set", s_mipsset, 0},
1418 {"rdata", s_change_sec, 'r'},
1419 {"sdata", s_change_sec, 's'},
1420 {"livereg", s_ignore, 0},
1421 {"abicalls", s_abicalls, 0},
1422 {"cpload", s_cpload, 0},
1423 {"cpsetup", s_cpsetup, 0},
1424 {"cplocal", s_cplocal, 0},
1425 {"cprestore", s_cprestore, 0},
1426 {"cpreturn", s_cpreturn, 0},
1427 {"dtprelword", s_dtprelword, 0},
1428 {"dtpreldword", s_dtpreldword, 0},
1429 {"tprelword", s_tprelword, 0},
1430 {"tpreldword", s_tpreldword, 0},
1431 {"gpvalue", s_gpvalue, 0},
1432 {"gpword", s_gpword, 0},
1433 {"gpdword", s_gpdword, 0},
1434 {"cpadd", s_cpadd, 0},
1435 {"insn", s_insn, 0},
1437 /* Relatively generic pseudo-ops that happen to be used on MIPS
1439 {"asciiz", stringer, 8 + 1},
1440 {"bss", s_change_sec, 'b'},
1442 {"half", s_cons, 1},
1443 {"dword", s_cons, 3},
1444 {"weakext", s_mips_weakext, 0},
1445 {"origin", s_org, 0},
1446 {"repeat", s_rept, 0},
1448 /* For MIPS this is non-standard, but we define it for consistency. */
1449 {"sbss", s_change_sec, 'B'},
1451 /* These pseudo-ops are defined in read.c, but must be overridden
1452 here for one reason or another. */
1453 {"align", s_align, 0},
1454 {"byte", s_cons, 0},
1455 {"data", s_change_sec, 'd'},
1456 {"double", s_float_cons, 'd'},
1457 {"float", s_float_cons, 'f'},
1458 {"globl", s_mips_globl, 0},
1459 {"global", s_mips_globl, 0},
1460 {"hword", s_cons, 1},
1462 {"long", s_cons, 2},
1463 {"octa", s_cons, 4},
1464 {"quad", s_cons, 3},
1465 {"section", s_change_section, 0},
1466 {"short", s_cons, 1},
1467 {"single", s_float_cons, 'f'},
1468 {"stabn", s_mips_stab, 'n'},
1469 {"text", s_change_sec, 't'},
1470 {"word", s_cons, 2},
1472 { "extern", ecoff_directive_extern, 0},
1477 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1479 /* These pseudo-ops should be defined by the object file format.
1480 However, a.out doesn't support them, so we have versions here. */
1481 {"aent", s_mips_ent, 1},
1482 {"bgnb", s_ignore, 0},
1483 {"end", s_mips_end, 0},
1484 {"endb", s_ignore, 0},
1485 {"ent", s_mips_ent, 0},
1486 {"file", s_mips_file, 0},
1487 {"fmask", s_mips_mask, 'F'},
1488 {"frame", s_mips_frame, 0},
1489 {"loc", s_mips_loc, 0},
1490 {"mask", s_mips_mask, 'R'},
1491 {"verstamp", s_ignore, 0},
1495 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1496 purpose of the `.dc.a' internal pseudo-op. */
1499 mips_address_bytes (void)
1501 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1504 extern void pop_insert (const pseudo_typeS *);
1507 mips_pop_insert (void)
1509 pop_insert (mips_pseudo_table);
1510 if (! ECOFF_DEBUGGING)
1511 pop_insert (mips_nonecoff_pseudo_table);
1514 /* Symbols labelling the current insn. */
1516 struct insn_label_list
1518 struct insn_label_list *next;
1522 static struct insn_label_list *free_insn_labels;
1523 #define label_list tc_segment_info_data.labels
1525 static void mips_clear_insn_labels (void);
1526 static void mips_mark_labels (void);
1527 static void mips_compressed_mark_labels (void);
1530 mips_clear_insn_labels (void)
1532 register struct insn_label_list **pl;
1533 segment_info_type *si;
1537 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1540 si = seg_info (now_seg);
1541 *pl = si->label_list;
1542 si->label_list = NULL;
1546 /* Mark instruction labels in MIPS16/microMIPS mode. */
1549 mips_mark_labels (void)
1551 if (HAVE_CODE_COMPRESSION)
1552 mips_compressed_mark_labels ();
1555 static char *expr_end;
1557 /* Expressions which appear in instructions. These are set by
1560 static expressionS imm_expr;
1561 static expressionS imm2_expr;
1562 static expressionS offset_expr;
1564 /* Relocs associated with imm_expr and offset_expr. */
1566 static bfd_reloc_code_real_type imm_reloc[3]
1567 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1568 static bfd_reloc_code_real_type offset_reloc[3]
1569 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1571 /* This is set to the resulting size of the instruction to be produced
1572 by mips16_ip if an explicit extension is used or by mips_ip if an
1573 explicit size is supplied. */
1575 static unsigned int forced_insn_length;
1577 /* True if we are assembling an instruction. All dot symbols defined during
1578 this time should be treated as code labels. */
1580 static bfd_boolean mips_assembling_insn;
1583 /* The pdr segment for per procedure frame/regmask info. Not used for
1586 static segT pdr_seg;
1589 /* The default target format to use. */
1591 #if defined (TE_FreeBSD)
1592 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1593 #elif defined (TE_TMIPS)
1594 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1596 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1600 mips_target_format (void)
1602 switch (OUTPUT_FLAVOR)
1604 case bfd_target_ecoff_flavour:
1605 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1606 case bfd_target_coff_flavour:
1608 case bfd_target_elf_flavour:
1610 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1611 return (target_big_endian
1612 ? "elf32-bigmips-vxworks"
1613 : "elf32-littlemips-vxworks");
1615 return (target_big_endian
1616 ? (HAVE_64BIT_OBJECTS
1617 ? ELF_TARGET ("elf64-", "big")
1619 ? ELF_TARGET ("elf32-n", "big")
1620 : ELF_TARGET ("elf32-", "big")))
1621 : (HAVE_64BIT_OBJECTS
1622 ? ELF_TARGET ("elf64-", "little")
1624 ? ELF_TARGET ("elf32-n", "little")
1625 : ELF_TARGET ("elf32-", "little"))));
1632 /* Return the length of a microMIPS instruction in bytes. If bits of
1633 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1634 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1635 major opcode) will require further modifications to the opcode
1638 static inline unsigned int
1639 micromips_insn_length (const struct mips_opcode *mo)
1641 return (mo->mask >> 16) == 0 ? 2 : 4;
1644 /* Return the length of MIPS16 instruction OPCODE. */
1646 static inline unsigned int
1647 mips16_opcode_length (unsigned long opcode)
1649 return (opcode >> 16) == 0 ? 2 : 4;
1652 /* Return the length of instruction INSN. */
1654 static inline unsigned int
1655 insn_length (const struct mips_cl_insn *insn)
1657 if (mips_opts.micromips)
1658 return micromips_insn_length (insn->insn_mo);
1659 else if (mips_opts.mips16)
1660 return mips16_opcode_length (insn->insn_opcode);
1665 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1668 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1673 insn->insn_opcode = mo->match;
1676 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1677 insn->fixp[i] = NULL;
1678 insn->fixed_p = (mips_opts.noreorder > 0);
1679 insn->noreorder_p = (mips_opts.noreorder > 0);
1680 insn->mips16_absolute_jump_p = 0;
1681 insn->complete_p = 0;
1684 /* Record the current MIPS16/microMIPS mode in now_seg. */
1687 mips_record_compressed_mode (void)
1689 segment_info_type *si;
1691 si = seg_info (now_seg);
1692 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1693 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1694 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
1695 si->tc_segment_info_data.micromips = mips_opts.micromips;
1698 /* Read a standard MIPS instruction from BUF. */
1700 static unsigned long
1701 read_insn (char *buf)
1703 if (target_big_endian)
1704 return bfd_getb32 ((bfd_byte *) buf);
1706 return bfd_getl32 ((bfd_byte *) buf);
1709 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
1713 write_insn (char *buf, unsigned int insn)
1715 md_number_to_chars (buf, insn, 4);
1719 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
1720 has length LENGTH. */
1722 static unsigned long
1723 read_compressed_insn (char *buf, unsigned int length)
1729 for (i = 0; i < length; i += 2)
1732 if (target_big_endian)
1733 insn |= bfd_getb16 ((char *) buf);
1735 insn |= bfd_getl16 ((char *) buf);
1741 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
1742 instruction is LENGTH bytes long. Return a pointer to the next byte. */
1745 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
1749 for (i = 0; i < length; i += 2)
1750 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
1751 return buf + length;
1754 /* Install INSN at the location specified by its "frag" and "where" fields. */
1757 install_insn (const struct mips_cl_insn *insn)
1759 char *f = insn->frag->fr_literal + insn->where;
1760 if (HAVE_CODE_COMPRESSION)
1761 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
1763 write_insn (f, insn->insn_opcode);
1764 mips_record_compressed_mode ();
1767 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1768 and install the opcode in the new location. */
1771 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1776 insn->where = where;
1777 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1778 if (insn->fixp[i] != NULL)
1780 insn->fixp[i]->fx_frag = frag;
1781 insn->fixp[i]->fx_where = where;
1783 install_insn (insn);
1786 /* Add INSN to the end of the output. */
1789 add_fixed_insn (struct mips_cl_insn *insn)
1791 char *f = frag_more (insn_length (insn));
1792 move_insn (insn, frag_now, f - frag_now->fr_literal);
1795 /* Start a variant frag and move INSN to the start of the variant part,
1796 marking it as fixed. The other arguments are as for frag_var. */
1799 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1800 relax_substateT subtype, symbolS *symbol, offsetT offset)
1802 frag_grow (max_chars);
1803 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1805 frag_var (rs_machine_dependent, max_chars, var,
1806 subtype, symbol, offset, NULL);
1809 /* Insert N copies of INSN into the history buffer, starting at
1810 position FIRST. Neither FIRST nor N need to be clipped. */
1813 insert_into_history (unsigned int first, unsigned int n,
1814 const struct mips_cl_insn *insn)
1816 if (mips_relax.sequence != 2)
1820 for (i = ARRAY_SIZE (history); i-- > first;)
1822 history[i] = history[i - n];
1828 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1829 the idea is to make it obvious at a glance that each errata is
1833 init_vr4120_conflicts (void)
1835 #define CONFLICT(FIRST, SECOND) \
1836 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1838 /* Errata 21 - [D]DIV[U] after [D]MACC */
1839 CONFLICT (MACC, DIV);
1840 CONFLICT (DMACC, DIV);
1842 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1843 CONFLICT (DMULT, DMULT);
1844 CONFLICT (DMULT, DMACC);
1845 CONFLICT (DMACC, DMULT);
1846 CONFLICT (DMACC, DMACC);
1848 /* Errata 24 - MT{LO,HI} after [D]MACC */
1849 CONFLICT (MACC, MTHILO);
1850 CONFLICT (DMACC, MTHILO);
1852 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1853 instruction is executed immediately after a MACC or DMACC
1854 instruction, the result of [either instruction] is incorrect." */
1855 CONFLICT (MACC, MULT);
1856 CONFLICT (MACC, DMULT);
1857 CONFLICT (DMACC, MULT);
1858 CONFLICT (DMACC, DMULT);
1860 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1861 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1862 DDIV or DDIVU instruction, the result of the MACC or
1863 DMACC instruction is incorrect.". */
1864 CONFLICT (DMULT, MACC);
1865 CONFLICT (DMULT, DMACC);
1866 CONFLICT (DIV, MACC);
1867 CONFLICT (DIV, DMACC);
1877 #define RTYPE_MASK 0x1ff00
1878 #define RTYPE_NUM 0x00100
1879 #define RTYPE_FPU 0x00200
1880 #define RTYPE_FCC 0x00400
1881 #define RTYPE_VEC 0x00800
1882 #define RTYPE_GP 0x01000
1883 #define RTYPE_CP0 0x02000
1884 #define RTYPE_PC 0x04000
1885 #define RTYPE_ACC 0x08000
1886 #define RTYPE_CCC 0x10000
1887 #define RNUM_MASK 0x000ff
1888 #define RWARN 0x80000
1890 #define GENERIC_REGISTER_NUMBERS \
1891 {"$0", RTYPE_NUM | 0}, \
1892 {"$1", RTYPE_NUM | 1}, \
1893 {"$2", RTYPE_NUM | 2}, \
1894 {"$3", RTYPE_NUM | 3}, \
1895 {"$4", RTYPE_NUM | 4}, \
1896 {"$5", RTYPE_NUM | 5}, \
1897 {"$6", RTYPE_NUM | 6}, \
1898 {"$7", RTYPE_NUM | 7}, \
1899 {"$8", RTYPE_NUM | 8}, \
1900 {"$9", RTYPE_NUM | 9}, \
1901 {"$10", RTYPE_NUM | 10}, \
1902 {"$11", RTYPE_NUM | 11}, \
1903 {"$12", RTYPE_NUM | 12}, \
1904 {"$13", RTYPE_NUM | 13}, \
1905 {"$14", RTYPE_NUM | 14}, \
1906 {"$15", RTYPE_NUM | 15}, \
1907 {"$16", RTYPE_NUM | 16}, \
1908 {"$17", RTYPE_NUM | 17}, \
1909 {"$18", RTYPE_NUM | 18}, \
1910 {"$19", RTYPE_NUM | 19}, \
1911 {"$20", RTYPE_NUM | 20}, \
1912 {"$21", RTYPE_NUM | 21}, \
1913 {"$22", RTYPE_NUM | 22}, \
1914 {"$23", RTYPE_NUM | 23}, \
1915 {"$24", RTYPE_NUM | 24}, \
1916 {"$25", RTYPE_NUM | 25}, \
1917 {"$26", RTYPE_NUM | 26}, \
1918 {"$27", RTYPE_NUM | 27}, \
1919 {"$28", RTYPE_NUM | 28}, \
1920 {"$29", RTYPE_NUM | 29}, \
1921 {"$30", RTYPE_NUM | 30}, \
1922 {"$31", RTYPE_NUM | 31}
1924 #define FPU_REGISTER_NAMES \
1925 {"$f0", RTYPE_FPU | 0}, \
1926 {"$f1", RTYPE_FPU | 1}, \
1927 {"$f2", RTYPE_FPU | 2}, \
1928 {"$f3", RTYPE_FPU | 3}, \
1929 {"$f4", RTYPE_FPU | 4}, \
1930 {"$f5", RTYPE_FPU | 5}, \
1931 {"$f6", RTYPE_FPU | 6}, \
1932 {"$f7", RTYPE_FPU | 7}, \
1933 {"$f8", RTYPE_FPU | 8}, \
1934 {"$f9", RTYPE_FPU | 9}, \
1935 {"$f10", RTYPE_FPU | 10}, \
1936 {"$f11", RTYPE_FPU | 11}, \
1937 {"$f12", RTYPE_FPU | 12}, \
1938 {"$f13", RTYPE_FPU | 13}, \
1939 {"$f14", RTYPE_FPU | 14}, \
1940 {"$f15", RTYPE_FPU | 15}, \
1941 {"$f16", RTYPE_FPU | 16}, \
1942 {"$f17", RTYPE_FPU | 17}, \
1943 {"$f18", RTYPE_FPU | 18}, \
1944 {"$f19", RTYPE_FPU | 19}, \
1945 {"$f20", RTYPE_FPU | 20}, \
1946 {"$f21", RTYPE_FPU | 21}, \
1947 {"$f22", RTYPE_FPU | 22}, \
1948 {"$f23", RTYPE_FPU | 23}, \
1949 {"$f24", RTYPE_FPU | 24}, \
1950 {"$f25", RTYPE_FPU | 25}, \
1951 {"$f26", RTYPE_FPU | 26}, \
1952 {"$f27", RTYPE_FPU | 27}, \
1953 {"$f28", RTYPE_FPU | 28}, \
1954 {"$f29", RTYPE_FPU | 29}, \
1955 {"$f30", RTYPE_FPU | 30}, \
1956 {"$f31", RTYPE_FPU | 31}
1958 #define FPU_CONDITION_CODE_NAMES \
1959 {"$fcc0", RTYPE_FCC | 0}, \
1960 {"$fcc1", RTYPE_FCC | 1}, \
1961 {"$fcc2", RTYPE_FCC | 2}, \
1962 {"$fcc3", RTYPE_FCC | 3}, \
1963 {"$fcc4", RTYPE_FCC | 4}, \
1964 {"$fcc5", RTYPE_FCC | 5}, \
1965 {"$fcc6", RTYPE_FCC | 6}, \
1966 {"$fcc7", RTYPE_FCC | 7}
1968 #define COPROC_CONDITION_CODE_NAMES \
1969 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1970 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1971 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1972 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1973 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1974 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1975 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1976 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1978 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1979 {"$a4", RTYPE_GP | 8}, \
1980 {"$a5", RTYPE_GP | 9}, \
1981 {"$a6", RTYPE_GP | 10}, \
1982 {"$a7", RTYPE_GP | 11}, \
1983 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1984 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1985 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1986 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1987 {"$t0", RTYPE_GP | 12}, \
1988 {"$t1", RTYPE_GP | 13}, \
1989 {"$t2", RTYPE_GP | 14}, \
1990 {"$t3", RTYPE_GP | 15}
1992 #define O32_SYMBOLIC_REGISTER_NAMES \
1993 {"$t0", RTYPE_GP | 8}, \
1994 {"$t1", RTYPE_GP | 9}, \
1995 {"$t2", RTYPE_GP | 10}, \
1996 {"$t3", RTYPE_GP | 11}, \
1997 {"$t4", RTYPE_GP | 12}, \
1998 {"$t5", RTYPE_GP | 13}, \
1999 {"$t6", RTYPE_GP | 14}, \
2000 {"$t7", RTYPE_GP | 15}, \
2001 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2002 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2003 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2004 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2006 /* Remaining symbolic register names */
2007 #define SYMBOLIC_REGISTER_NAMES \
2008 {"$zero", RTYPE_GP | 0}, \
2009 {"$at", RTYPE_GP | 1}, \
2010 {"$AT", RTYPE_GP | 1}, \
2011 {"$v0", RTYPE_GP | 2}, \
2012 {"$v1", RTYPE_GP | 3}, \
2013 {"$a0", RTYPE_GP | 4}, \
2014 {"$a1", RTYPE_GP | 5}, \
2015 {"$a2", RTYPE_GP | 6}, \
2016 {"$a3", RTYPE_GP | 7}, \
2017 {"$s0", RTYPE_GP | 16}, \
2018 {"$s1", RTYPE_GP | 17}, \
2019 {"$s2", RTYPE_GP | 18}, \
2020 {"$s3", RTYPE_GP | 19}, \
2021 {"$s4", RTYPE_GP | 20}, \
2022 {"$s5", RTYPE_GP | 21}, \
2023 {"$s6", RTYPE_GP | 22}, \
2024 {"$s7", RTYPE_GP | 23}, \
2025 {"$t8", RTYPE_GP | 24}, \
2026 {"$t9", RTYPE_GP | 25}, \
2027 {"$k0", RTYPE_GP | 26}, \
2028 {"$kt0", RTYPE_GP | 26}, \
2029 {"$k1", RTYPE_GP | 27}, \
2030 {"$kt1", RTYPE_GP | 27}, \
2031 {"$gp", RTYPE_GP | 28}, \
2032 {"$sp", RTYPE_GP | 29}, \
2033 {"$s8", RTYPE_GP | 30}, \
2034 {"$fp", RTYPE_GP | 30}, \
2035 {"$ra", RTYPE_GP | 31}
2037 #define MIPS16_SPECIAL_REGISTER_NAMES \
2038 {"$pc", RTYPE_PC | 0}
2040 #define MDMX_VECTOR_REGISTER_NAMES \
2041 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2042 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2043 {"$v2", RTYPE_VEC | 2}, \
2044 {"$v3", RTYPE_VEC | 3}, \
2045 {"$v4", RTYPE_VEC | 4}, \
2046 {"$v5", RTYPE_VEC | 5}, \
2047 {"$v6", RTYPE_VEC | 6}, \
2048 {"$v7", RTYPE_VEC | 7}, \
2049 {"$v8", RTYPE_VEC | 8}, \
2050 {"$v9", RTYPE_VEC | 9}, \
2051 {"$v10", RTYPE_VEC | 10}, \
2052 {"$v11", RTYPE_VEC | 11}, \
2053 {"$v12", RTYPE_VEC | 12}, \
2054 {"$v13", RTYPE_VEC | 13}, \
2055 {"$v14", RTYPE_VEC | 14}, \
2056 {"$v15", RTYPE_VEC | 15}, \
2057 {"$v16", RTYPE_VEC | 16}, \
2058 {"$v17", RTYPE_VEC | 17}, \
2059 {"$v18", RTYPE_VEC | 18}, \
2060 {"$v19", RTYPE_VEC | 19}, \
2061 {"$v20", RTYPE_VEC | 20}, \
2062 {"$v21", RTYPE_VEC | 21}, \
2063 {"$v22", RTYPE_VEC | 22}, \
2064 {"$v23", RTYPE_VEC | 23}, \
2065 {"$v24", RTYPE_VEC | 24}, \
2066 {"$v25", RTYPE_VEC | 25}, \
2067 {"$v26", RTYPE_VEC | 26}, \
2068 {"$v27", RTYPE_VEC | 27}, \
2069 {"$v28", RTYPE_VEC | 28}, \
2070 {"$v29", RTYPE_VEC | 29}, \
2071 {"$v30", RTYPE_VEC | 30}, \
2072 {"$v31", RTYPE_VEC | 31}
2074 #define MIPS_DSP_ACCUMULATOR_NAMES \
2075 {"$ac0", RTYPE_ACC | 0}, \
2076 {"$ac1", RTYPE_ACC | 1}, \
2077 {"$ac2", RTYPE_ACC | 2}, \
2078 {"$ac3", RTYPE_ACC | 3}
2080 static const struct regname reg_names[] = {
2081 GENERIC_REGISTER_NUMBERS,
2083 FPU_CONDITION_CODE_NAMES,
2084 COPROC_CONDITION_CODE_NAMES,
2086 /* The $txx registers depends on the abi,
2087 these will be added later into the symbol table from
2088 one of the tables below once mips_abi is set after
2089 parsing of arguments from the command line. */
2090 SYMBOLIC_REGISTER_NAMES,
2092 MIPS16_SPECIAL_REGISTER_NAMES,
2093 MDMX_VECTOR_REGISTER_NAMES,
2094 MIPS_DSP_ACCUMULATOR_NAMES,
2098 static const struct regname reg_names_o32[] = {
2099 O32_SYMBOLIC_REGISTER_NAMES,
2103 static const struct regname reg_names_n32n64[] = {
2104 N32N64_SYMBOLIC_REGISTER_NAMES,
2108 /* Check if S points at a valid register specifier according to TYPES.
2109 If so, then return 1, advance S to consume the specifier and store
2110 the register's number in REGNOP, otherwise return 0. */
2113 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2120 /* Find end of name. */
2122 if (is_name_beginner (*e))
2124 while (is_part_of_name (*e))
2127 /* Terminate name. */
2131 /* Look for a register symbol. */
2132 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2134 int r = S_GET_VALUE (symbolP);
2136 reg = r & RNUM_MASK;
2137 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2138 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2139 reg = (r & RNUM_MASK) - 2;
2141 /* Else see if this is a register defined in an itbl entry. */
2142 else if ((types & RTYPE_GP) && itbl_have_entries)
2149 if (itbl_get_reg_val (n, &r))
2150 reg = r & RNUM_MASK;
2153 /* Advance to next token if a register was recognised. */
2156 else if (types & RWARN)
2157 as_warn (_("Unrecognized register name `%s'"), *s);
2165 /* Check if S points at a valid register list according to TYPES.
2166 If so, then return 1, advance S to consume the list and store
2167 the registers present on the list as a bitmask of ones in REGLISTP,
2168 otherwise return 0. A valid list comprises a comma-separated
2169 enumeration of valid single registers and/or dash-separated
2170 contiguous register ranges as determined by their numbers.
2172 As a special exception if one of s0-s7 registers is specified as
2173 the range's lower delimiter and s8 (fp) is its upper one, then no
2174 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2175 are selected; they have to be listed separately if needed. */
2178 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2180 unsigned int reglist = 0;
2181 unsigned int lastregno;
2182 bfd_boolean ok = TRUE;
2183 unsigned int regmask;
2184 char *s_endlist = *s;
2188 while (reg_lookup (s, types, ®no))
2194 ok = reg_lookup (s, types, &lastregno);
2195 if (ok && lastregno < regno)
2201 if (lastregno == FP && regno >= S0 && regno <= S7)
2206 regmask = 1 << lastregno;
2207 regmask = (regmask << 1) - 1;
2208 regmask ^= (1 << regno) - 1;
2222 *reglistp = reglist;
2223 return ok && reglist != 0;
2226 /* Return TRUE if opcode MO is valid on the currently selected ISA and
2227 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2230 is_opcode_valid (const struct mips_opcode *mo)
2232 int isa = mips_opts.isa;
2235 if (mips_opts.ase_mdmx)
2237 if (mips_opts.ase_dsp)
2239 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
2241 if (mips_opts.ase_dspr2)
2243 if (mips_opts.ase_mt)
2245 if (mips_opts.ase_mips3d)
2247 if (mips_opts.ase_smartmips)
2248 isa |= INSN_SMARTMIPS;
2249 if (mips_opts.ase_mcu)
2252 if (!opcode_is_member (mo, isa, mips_opts.arch))
2255 /* Check whether the instruction or macro requires single-precision or
2256 double-precision floating-point support. Note that this information is
2257 stored differently in the opcode table for insns and macros. */
2258 if (mo->pinfo == INSN_MACRO)
2260 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2261 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2265 fp_s = mo->pinfo & FP_S;
2266 fp_d = mo->pinfo & FP_D;
2269 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2272 if (fp_s && mips_opts.soft_float)
2278 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2279 selected ISA and architecture. */
2282 is_opcode_valid_16 (const struct mips_opcode *mo)
2284 return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
2287 /* Return TRUE if the size of the microMIPS opcode MO matches one
2288 explicitly requested. Always TRUE in the standard MIPS mode. */
2291 is_size_valid (const struct mips_opcode *mo)
2293 if (!mips_opts.micromips)
2296 if (!forced_insn_length)
2298 if (mo->pinfo == INSN_MACRO)
2300 return forced_insn_length == micromips_insn_length (mo);
2303 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2304 of the preceding instruction. Always TRUE in the standard MIPS mode.
2306 We don't accept macros in 16-bit delay slots to avoid a case where
2307 a macro expansion fails because it relies on a preceding 32-bit real
2308 instruction to have matched and does not handle the operands correctly.
2309 The only macros that may expand to 16-bit instructions are JAL that
2310 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2311 and BGT (that likewise cannot be placed in a delay slot) that decay to
2312 a NOP. In all these cases the macros precede any corresponding real
2313 instruction definitions in the opcode table, so they will match in the
2314 second pass where the size of the delay slot is ignored and therefore
2315 produce correct code. */
2318 is_delay_slot_valid (const struct mips_opcode *mo)
2320 if (!mips_opts.micromips)
2323 if (mo->pinfo == INSN_MACRO)
2324 return ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0
2326 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2327 && micromips_insn_length (mo) != 4)
2329 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2330 && micromips_insn_length (mo) != 2)
2336 /* This function is called once, at assembler startup time. It should set up
2337 all the tables, etc. that the MD part of the assembler will need. */
2342 const char *retval = NULL;
2346 if (mips_pic != NO_PIC)
2348 if (g_switch_seen && g_switch_value != 0)
2349 as_bad (_("-G may not be used in position-independent code"));
2353 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2354 as_warn (_("Could not set architecture and machine"));
2356 op_hash = hash_new ();
2358 for (i = 0; i < NUMOPCODES;)
2360 const char *name = mips_opcodes[i].name;
2362 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2365 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2366 mips_opcodes[i].name, retval);
2367 /* Probably a memory allocation problem? Give up now. */
2368 as_fatal (_("Broken assembler. No assembly attempted."));
2372 if (mips_opcodes[i].pinfo != INSN_MACRO)
2374 if (!validate_mips_insn (&mips_opcodes[i]))
2376 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2378 create_insn (&nop_insn, mips_opcodes + i);
2379 if (mips_fix_loongson2f_nop)
2380 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2381 nop_insn.fixed_p = 1;
2386 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2389 mips16_op_hash = hash_new ();
2392 while (i < bfd_mips16_num_opcodes)
2394 const char *name = mips16_opcodes[i].name;
2396 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2398 as_fatal (_("internal: can't hash `%s': %s"),
2399 mips16_opcodes[i].name, retval);
2402 if (mips16_opcodes[i].pinfo != INSN_MACRO
2403 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2404 != mips16_opcodes[i].match))
2406 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2407 mips16_opcodes[i].name, mips16_opcodes[i].args);
2410 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2412 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2413 mips16_nop_insn.fixed_p = 1;
2417 while (i < bfd_mips16_num_opcodes
2418 && strcmp (mips16_opcodes[i].name, name) == 0);
2421 micromips_op_hash = hash_new ();
2424 while (i < bfd_micromips_num_opcodes)
2426 const char *name = micromips_opcodes[i].name;
2428 retval = hash_insert (micromips_op_hash, name,
2429 (void *) µmips_opcodes[i]);
2431 as_fatal (_("internal: can't hash `%s': %s"),
2432 micromips_opcodes[i].name, retval);
2434 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2436 struct mips_cl_insn *micromips_nop_insn;
2438 if (!validate_micromips_insn (µmips_opcodes[i]))
2441 if (micromips_insn_length (micromips_opcodes + i) == 2)
2442 micromips_nop_insn = µmips_nop16_insn;
2443 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2444 micromips_nop_insn = µmips_nop32_insn;
2448 if (micromips_nop_insn->insn_mo == NULL
2449 && strcmp (name, "nop") == 0)
2451 create_insn (micromips_nop_insn, micromips_opcodes + i);
2452 micromips_nop_insn->fixed_p = 1;
2455 while (++i < bfd_micromips_num_opcodes
2456 && strcmp (micromips_opcodes[i].name, name) == 0);
2460 as_fatal (_("Broken assembler. No assembly attempted."));
2462 /* We add all the general register names to the symbol table. This
2463 helps us detect invalid uses of them. */
2464 for (i = 0; reg_names[i].name; i++)
2465 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2466 reg_names[i].num, /* & RNUM_MASK, */
2467 &zero_address_frag));
2469 for (i = 0; reg_names_n32n64[i].name; i++)
2470 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2471 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2472 &zero_address_frag));
2474 for (i = 0; reg_names_o32[i].name; i++)
2475 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2476 reg_names_o32[i].num, /* & RNUM_MASK, */
2477 &zero_address_frag));
2479 mips_no_prev_insn ();
2482 mips_cprmask[0] = 0;
2483 mips_cprmask[1] = 0;
2484 mips_cprmask[2] = 0;
2485 mips_cprmask[3] = 0;
2487 /* set the default alignment for the text section (2**2) */
2488 record_alignment (text_section, 2);
2490 bfd_set_gp_size (stdoutput, g_switch_value);
2495 /* On a native system other than VxWorks, sections must be aligned
2496 to 16 byte boundaries. When configured for an embedded ELF
2497 target, we don't bother. */
2498 if (strncmp (TARGET_OS, "elf", 3) != 0
2499 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2501 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2502 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2503 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2506 /* Create a .reginfo section for register masks and a .mdebug
2507 section for debugging information. */
2515 subseg = now_subseg;
2517 /* The ABI says this section should be loaded so that the
2518 running program can access it. However, we don't load it
2519 if we are configured for an embedded target */
2520 flags = SEC_READONLY | SEC_DATA;
2521 if (strncmp (TARGET_OS, "elf", 3) != 0)
2522 flags |= SEC_ALLOC | SEC_LOAD;
2524 if (mips_abi != N64_ABI)
2526 sec = subseg_new (".reginfo", (subsegT) 0);
2528 bfd_set_section_flags (stdoutput, sec, flags);
2529 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2531 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2535 /* The 64-bit ABI uses a .MIPS.options section rather than
2536 .reginfo section. */
2537 sec = subseg_new (".MIPS.options", (subsegT) 0);
2538 bfd_set_section_flags (stdoutput, sec, flags);
2539 bfd_set_section_alignment (stdoutput, sec, 3);
2541 /* Set up the option header. */
2543 Elf_Internal_Options opthdr;
2546 opthdr.kind = ODK_REGINFO;
2547 opthdr.size = (sizeof (Elf_External_Options)
2548 + sizeof (Elf64_External_RegInfo));
2551 f = frag_more (sizeof (Elf_External_Options));
2552 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2553 (Elf_External_Options *) f);
2555 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2559 if (ECOFF_DEBUGGING)
2561 sec = subseg_new (".mdebug", (subsegT) 0);
2562 (void) bfd_set_section_flags (stdoutput, sec,
2563 SEC_HAS_CONTENTS | SEC_READONLY);
2564 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2566 else if (mips_flag_pdr)
2568 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2569 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2570 SEC_READONLY | SEC_RELOC
2572 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2575 subseg_set (seg, subseg);
2578 #endif /* OBJ_ELF */
2580 if (! ECOFF_DEBUGGING)
2583 if (mips_fix_vr4120)
2584 init_vr4120_conflicts ();
2590 mips_emit_delays ();
2591 if (! ECOFF_DEBUGGING)
2596 md_assemble (char *str)
2598 struct mips_cl_insn insn;
2599 bfd_reloc_code_real_type unused_reloc[3]
2600 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2602 imm_expr.X_op = O_absent;
2603 imm2_expr.X_op = O_absent;
2604 offset_expr.X_op = O_absent;
2605 imm_reloc[0] = BFD_RELOC_UNUSED;
2606 imm_reloc[1] = BFD_RELOC_UNUSED;
2607 imm_reloc[2] = BFD_RELOC_UNUSED;
2608 offset_reloc[0] = BFD_RELOC_UNUSED;
2609 offset_reloc[1] = BFD_RELOC_UNUSED;
2610 offset_reloc[2] = BFD_RELOC_UNUSED;
2612 mips_mark_labels ();
2613 mips_assembling_insn = TRUE;
2615 if (mips_opts.mips16)
2616 mips16_ip (str, &insn);
2619 mips_ip (str, &insn);
2620 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2621 str, insn.insn_opcode));
2625 as_bad ("%s `%s'", insn_error, str);
2626 else if (insn.insn_mo->pinfo == INSN_MACRO)
2629 if (mips_opts.mips16)
2630 mips16_macro (&insn);
2637 if (imm_expr.X_op != O_absent)
2638 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2639 else if (offset_expr.X_op != O_absent)
2640 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2642 append_insn (&insn, NULL, unused_reloc, FALSE);
2645 mips_assembling_insn = FALSE;
2648 /* Convenience functions for abstracting away the differences between
2649 MIPS16 and non-MIPS16 relocations. */
2651 static inline bfd_boolean
2652 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2656 case BFD_RELOC_MIPS16_JMP:
2657 case BFD_RELOC_MIPS16_GPREL:
2658 case BFD_RELOC_MIPS16_GOT16:
2659 case BFD_RELOC_MIPS16_CALL16:
2660 case BFD_RELOC_MIPS16_HI16_S:
2661 case BFD_RELOC_MIPS16_HI16:
2662 case BFD_RELOC_MIPS16_LO16:
2670 static inline bfd_boolean
2671 micromips_reloc_p (bfd_reloc_code_real_type reloc)
2675 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
2676 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
2677 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
2678 case BFD_RELOC_MICROMIPS_GPREL16:
2679 case BFD_RELOC_MICROMIPS_JMP:
2680 case BFD_RELOC_MICROMIPS_HI16:
2681 case BFD_RELOC_MICROMIPS_HI16_S:
2682 case BFD_RELOC_MICROMIPS_LO16:
2683 case BFD_RELOC_MICROMIPS_LITERAL:
2684 case BFD_RELOC_MICROMIPS_GOT16:
2685 case BFD_RELOC_MICROMIPS_CALL16:
2686 case BFD_RELOC_MICROMIPS_GOT_HI16:
2687 case BFD_RELOC_MICROMIPS_GOT_LO16:
2688 case BFD_RELOC_MICROMIPS_CALL_HI16:
2689 case BFD_RELOC_MICROMIPS_CALL_LO16:
2690 case BFD_RELOC_MICROMIPS_SUB:
2691 case BFD_RELOC_MICROMIPS_GOT_PAGE:
2692 case BFD_RELOC_MICROMIPS_GOT_OFST:
2693 case BFD_RELOC_MICROMIPS_GOT_DISP:
2694 case BFD_RELOC_MICROMIPS_HIGHEST:
2695 case BFD_RELOC_MICROMIPS_HIGHER:
2696 case BFD_RELOC_MICROMIPS_SCN_DISP:
2697 case BFD_RELOC_MICROMIPS_JALR:
2705 static inline bfd_boolean
2706 jmp_reloc_p (bfd_reloc_code_real_type reloc)
2708 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
2711 static inline bfd_boolean
2712 got16_reloc_p (bfd_reloc_code_real_type reloc)
2714 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
2715 || reloc == BFD_RELOC_MICROMIPS_GOT16);
2718 static inline bfd_boolean
2719 hi16_reloc_p (bfd_reloc_code_real_type reloc)
2721 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
2722 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
2725 static inline bfd_boolean
2726 lo16_reloc_p (bfd_reloc_code_real_type reloc)
2728 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
2729 || reloc == BFD_RELOC_MICROMIPS_LO16);
2732 static inline bfd_boolean
2733 jalr_reloc_p (bfd_reloc_code_real_type reloc)
2735 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
2738 /* Return true if the given relocation might need a matching %lo().
2739 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2740 need a matching %lo() when applied to local symbols. */
2742 static inline bfd_boolean
2743 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2745 return (HAVE_IN_PLACE_ADDENDS
2746 && (hi16_reloc_p (reloc)
2747 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2748 all GOT16 relocations evaluate to "G". */
2749 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2752 /* Return the type of %lo() reloc needed by RELOC, given that
2753 reloc_needs_lo_p. */
2755 static inline bfd_reloc_code_real_type
2756 matching_lo_reloc (bfd_reloc_code_real_type reloc)
2758 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
2759 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
2763 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2766 static inline bfd_boolean
2767 fixup_has_matching_lo_p (fixS *fixp)
2769 return (fixp->fx_next != NULL
2770 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2771 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2772 && fixp->fx_offset == fixp->fx_next->fx_offset);
2775 /* This function returns true if modifying a register requires a
2779 reg_needs_delay (unsigned int reg)
2781 unsigned long prev_pinfo;
2783 prev_pinfo = history[0].insn_mo->pinfo;
2784 if (! mips_opts.noreorder
2785 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2786 && ! gpr_interlocks)
2787 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2788 && ! cop_interlocks)))
2790 /* A load from a coprocessor or from memory. All load delays
2791 delay the use of general register rt for one instruction. */
2792 /* Itbl support may require additional care here. */
2793 know (prev_pinfo & INSN_WRITE_GPR_T);
2794 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
2801 /* Move all labels in LABELS to the current insertion point. TEXT_P
2802 says whether the labels refer to text or data. */
2805 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
2807 struct insn_label_list *l;
2810 for (l = labels; l != NULL; l = l->next)
2812 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2813 symbol_set_frag (l->label, frag_now);
2814 val = (valueT) frag_now_fix ();
2815 /* MIPS16/microMIPS text labels are stored as odd. */
2816 if (text_p && HAVE_CODE_COMPRESSION)
2818 S_SET_VALUE (l->label, val);
2822 /* Move all labels in insn_labels to the current insertion point
2823 and treat them as text labels. */
2826 mips_move_text_labels (void)
2828 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
2832 s_is_linkonce (symbolS *sym, segT from_seg)
2834 bfd_boolean linkonce = FALSE;
2835 segT symseg = S_GET_SEGMENT (sym);
2837 if (symseg != from_seg && !S_IS_LOCAL (sym))
2839 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2842 /* The GNU toolchain uses an extension for ELF: a section
2843 beginning with the magic string .gnu.linkonce is a
2844 linkonce section. */
2845 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2846 sizeof ".gnu.linkonce" - 1) == 0)
2853 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
2854 linker to handle them specially, such as generating jalx instructions
2855 when needed. We also make them odd for the duration of the assembly,
2856 in order to generate the right sort of code. We will make them even
2857 in the adjust_symtab routine, while leaving them marked. This is
2858 convenient for the debugger and the disassembler. The linker knows
2859 to make them odd again. */
2862 mips_compressed_mark_label (symbolS *label)
2864 gas_assert (HAVE_CODE_COMPRESSION);
2866 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2869 if (mips_opts.mips16)
2870 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2872 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
2875 if ((S_GET_VALUE (label) & 1) == 0
2876 /* Don't adjust the address if the label is global or weak, or
2877 in a link-once section, since we'll be emitting symbol reloc
2878 references to it which will be patched up by the linker, and
2879 the final value of the symbol may or may not be MIPS16/microMIPS. */
2880 && !S_IS_WEAK (label)
2881 && !S_IS_EXTERNAL (label)
2882 && !s_is_linkonce (label, now_seg))
2883 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2886 /* Mark preceding MIPS16 or microMIPS instruction labels. */
2889 mips_compressed_mark_labels (void)
2891 struct insn_label_list *l;
2893 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
2894 mips_compressed_mark_label (l->label);
2897 /* End the current frag. Make it a variant frag and record the
2901 relax_close_frag (void)
2903 mips_macro_warning.first_frag = frag_now;
2904 frag_var (rs_machine_dependent, 0, 0,
2905 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2906 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2908 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2909 mips_relax.first_fixup = 0;
2912 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2913 See the comment above RELAX_ENCODE for more details. */
2916 relax_start (symbolS *symbol)
2918 gas_assert (mips_relax.sequence == 0);
2919 mips_relax.sequence = 1;
2920 mips_relax.symbol = symbol;
2923 /* Start generating the second version of a relaxable sequence.
2924 See the comment above RELAX_ENCODE for more details. */
2929 gas_assert (mips_relax.sequence == 1);
2930 mips_relax.sequence = 2;
2933 /* End the current relaxable sequence. */
2938 gas_assert (mips_relax.sequence == 2);
2939 relax_close_frag ();
2940 mips_relax.sequence = 0;
2943 /* Return true if IP is a delayed branch or jump. */
2945 static inline bfd_boolean
2946 delayed_branch_p (const struct mips_cl_insn *ip)
2948 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2949 | INSN_COND_BRANCH_DELAY
2950 | INSN_COND_BRANCH_LIKELY)) != 0;
2953 /* Return true if IP is a compact branch or jump. */
2955 static inline bfd_boolean
2956 compact_branch_p (const struct mips_cl_insn *ip)
2958 if (mips_opts.mips16)
2959 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
2960 | MIPS16_INSN_COND_BRANCH)) != 0;
2962 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
2963 | INSN2_COND_BRANCH)) != 0;
2966 /* Return true if IP is an unconditional branch or jump. */
2968 static inline bfd_boolean
2969 uncond_branch_p (const struct mips_cl_insn *ip)
2971 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
2972 || (mips_opts.mips16
2973 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
2974 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
2977 /* Return true if IP is a branch-likely instruction. */
2979 static inline bfd_boolean
2980 branch_likely_p (const struct mips_cl_insn *ip)
2982 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
2985 /* Return the type of nop that should be used to fill the delay slot
2986 of delayed branch IP. */
2988 static struct mips_cl_insn *
2989 get_delay_slot_nop (const struct mips_cl_insn *ip)
2991 if (mips_opts.micromips
2992 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
2993 return µmips_nop32_insn;
2997 /* Return the mask of core registers that IP reads or writes. */
3000 gpr_mod_mask (const struct mips_cl_insn *ip)
3002 unsigned long pinfo2;
3006 pinfo2 = ip->insn_mo->pinfo2;
3007 if (mips_opts.micromips)
3009 if (pinfo2 & INSN2_MOD_GPR_MD)
3010 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3011 if (pinfo2 & INSN2_MOD_GPR_MF)
3012 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3013 if (pinfo2 & INSN2_MOD_SP)
3019 /* Return the mask of core registers that IP reads. */
3022 gpr_read_mask (const struct mips_cl_insn *ip)
3024 unsigned long pinfo, pinfo2;
3027 mask = gpr_mod_mask (ip);
3028 pinfo = ip->insn_mo->pinfo;
3029 pinfo2 = ip->insn_mo->pinfo2;
3030 if (mips_opts.mips16)
3032 if (pinfo & MIPS16_INSN_READ_X)
3033 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3034 if (pinfo & MIPS16_INSN_READ_Y)
3035 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3036 if (pinfo & MIPS16_INSN_READ_T)
3038 if (pinfo & MIPS16_INSN_READ_SP)
3040 if (pinfo & MIPS16_INSN_READ_31)
3042 if (pinfo & MIPS16_INSN_READ_Z)
3043 mask |= 1 << (mips16_to_32_reg_map
3044 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3045 if (pinfo & MIPS16_INSN_READ_GPR_X)
3046 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3050 if (pinfo2 & INSN2_READ_GPR_D)
3051 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3052 if (pinfo & INSN_READ_GPR_T)
3053 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3054 if (pinfo & INSN_READ_GPR_S)
3055 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3056 if (pinfo2 & INSN2_READ_GP)
3058 if (pinfo2 & INSN2_READ_GPR_31)
3060 if (pinfo2 & INSN2_READ_GPR_Z)
3061 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3063 if (mips_opts.micromips)
3065 if (pinfo2 & INSN2_READ_GPR_MC)
3066 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3067 if (pinfo2 & INSN2_READ_GPR_ME)
3068 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3069 if (pinfo2 & INSN2_READ_GPR_MG)
3070 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3071 if (pinfo2 & INSN2_READ_GPR_MJ)
3072 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3073 if (pinfo2 & INSN2_READ_GPR_MMN)
3075 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3076 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3078 if (pinfo2 & INSN2_READ_GPR_MP)
3079 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3080 if (pinfo2 & INSN2_READ_GPR_MQ)
3081 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3083 /* Don't include register 0. */
3087 /* Return the mask of core registers that IP writes. */
3090 gpr_write_mask (const struct mips_cl_insn *ip)
3092 unsigned long pinfo, pinfo2;
3095 mask = gpr_mod_mask (ip);
3096 pinfo = ip->insn_mo->pinfo;
3097 pinfo2 = ip->insn_mo->pinfo2;
3098 if (mips_opts.mips16)
3100 if (pinfo & MIPS16_INSN_WRITE_X)
3101 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3102 if (pinfo & MIPS16_INSN_WRITE_Y)
3103 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3104 if (pinfo & MIPS16_INSN_WRITE_Z)
3105 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3106 if (pinfo & MIPS16_INSN_WRITE_T)
3108 if (pinfo & MIPS16_INSN_WRITE_SP)
3110 if (pinfo & MIPS16_INSN_WRITE_31)
3112 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3113 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3117 if (pinfo & INSN_WRITE_GPR_D)
3118 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3119 if (pinfo & INSN_WRITE_GPR_T)
3120 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3121 if (pinfo & INSN_WRITE_GPR_S)
3122 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3123 if (pinfo & INSN_WRITE_GPR_31)
3125 if (pinfo2 & INSN2_WRITE_GPR_Z)
3126 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3128 if (mips_opts.micromips)
3130 if (pinfo2 & INSN2_WRITE_GPR_MB)
3131 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3132 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3134 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3135 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3137 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3138 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3139 if (pinfo2 & INSN2_WRITE_GPR_MP)
3140 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3142 /* Don't include register 0. */
3146 /* Return the mask of floating-point registers that IP reads. */
3149 fpr_read_mask (const struct mips_cl_insn *ip)
3151 unsigned long pinfo, pinfo2;
3155 pinfo = ip->insn_mo->pinfo;
3156 pinfo2 = ip->insn_mo->pinfo2;
3157 if (!mips_opts.mips16)
3159 if (pinfo2 & INSN2_READ_FPR_D)
3160 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3161 if (pinfo & INSN_READ_FPR_S)
3162 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3163 if (pinfo & INSN_READ_FPR_T)
3164 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3165 if (pinfo & INSN_READ_FPR_R)
3166 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3167 if (pinfo2 & INSN2_READ_FPR_Z)
3168 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3170 /* Conservatively treat all operands to an FP_D instruction are doubles.
3171 (This is overly pessimistic for things like cvt.d.s.) */
3172 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3177 /* Return the mask of floating-point registers that IP writes. */
3180 fpr_write_mask (const struct mips_cl_insn *ip)
3182 unsigned long pinfo, pinfo2;
3186 pinfo = ip->insn_mo->pinfo;
3187 pinfo2 = ip->insn_mo->pinfo2;
3188 if (!mips_opts.mips16)
3190 if (pinfo & INSN_WRITE_FPR_D)
3191 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3192 if (pinfo & INSN_WRITE_FPR_S)
3193 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3194 if (pinfo & INSN_WRITE_FPR_T)
3195 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3196 if (pinfo2 & INSN2_WRITE_FPR_Z)
3197 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3199 /* Conservatively treat all operands to an FP_D instruction are doubles.
3200 (This is overly pessimistic for things like cvt.s.d.) */
3201 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3206 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3207 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3208 by VR4120 errata. */
3211 classify_vr4120_insn (const char *name)
3213 if (strncmp (name, "macc", 4) == 0)
3214 return FIX_VR4120_MACC;
3215 if (strncmp (name, "dmacc", 5) == 0)
3216 return FIX_VR4120_DMACC;
3217 if (strncmp (name, "mult", 4) == 0)
3218 return FIX_VR4120_MULT;
3219 if (strncmp (name, "dmult", 5) == 0)
3220 return FIX_VR4120_DMULT;
3221 if (strstr (name, "div"))
3222 return FIX_VR4120_DIV;
3223 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3224 return FIX_VR4120_MTHILO;
3225 return NUM_FIX_VR4120_CLASSES;
3228 #define INSN_ERET 0x42000018
3229 #define INSN_DERET 0x4200001f
3231 /* Return the number of instructions that must separate INSN1 and INSN2,
3232 where INSN1 is the earlier instruction. Return the worst-case value
3233 for any INSN2 if INSN2 is null. */
3236 insns_between (const struct mips_cl_insn *insn1,
3237 const struct mips_cl_insn *insn2)
3239 unsigned long pinfo1, pinfo2;
3242 /* This function needs to know which pinfo flags are set for INSN2
3243 and which registers INSN2 uses. The former is stored in PINFO2 and
3244 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3245 will have every flag set and INSN2_USES_GPR will always return true. */
3246 pinfo1 = insn1->insn_mo->pinfo;
3247 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3249 #define INSN2_USES_GPR(REG) \
3250 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3252 /* For most targets, write-after-read dependencies on the HI and LO
3253 registers must be separated by at least two instructions. */
3254 if (!hilo_interlocks)
3256 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3258 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3262 /* If we're working around r7000 errata, there must be two instructions
3263 between an mfhi or mflo and any instruction that uses the result. */
3264 if (mips_7000_hilo_fix
3265 && !mips_opts.micromips
3266 && MF_HILO_INSN (pinfo1)
3267 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3270 /* If we're working around 24K errata, one instruction is required
3271 if an ERET or DERET is followed by a branch instruction. */
3272 if (mips_fix_24k && !mips_opts.micromips)
3274 if (insn1->insn_opcode == INSN_ERET
3275 || insn1->insn_opcode == INSN_DERET)
3278 || insn2->insn_opcode == INSN_ERET
3279 || insn2->insn_opcode == INSN_DERET
3280 || delayed_branch_p (insn2))
3285 /* If working around VR4120 errata, check for combinations that need
3286 a single intervening instruction. */
3287 if (mips_fix_vr4120 && !mips_opts.micromips)
3289 unsigned int class1, class2;
3291 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3292 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3296 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3297 if (vr4120_conflicts[class1] & (1 << class2))
3302 if (!HAVE_CODE_COMPRESSION)
3304 /* Check for GPR or coprocessor load delays. All such delays
3305 are on the RT register. */
3306 /* Itbl support may require additional care here. */
3307 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3308 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3310 know (pinfo1 & INSN_WRITE_GPR_T);
3311 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3315 /* Check for generic coprocessor hazards.
3317 This case is not handled very well. There is no special
3318 knowledge of CP0 handling, and the coprocessors other than
3319 the floating point unit are not distinguished at all. */
3320 /* Itbl support may require additional care here. FIXME!
3321 Need to modify this to include knowledge about
3322 user specified delays! */
3323 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3324 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3326 /* Handle cases where INSN1 writes to a known general coprocessor
3327 register. There must be a one instruction delay before INSN2
3328 if INSN2 reads that register, otherwise no delay is needed. */
3329 mask = fpr_write_mask (insn1);
3332 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3337 /* Read-after-write dependencies on the control registers
3338 require a two-instruction gap. */
3339 if ((pinfo1 & INSN_WRITE_COND_CODE)
3340 && (pinfo2 & INSN_READ_COND_CODE))
3343 /* We don't know exactly what INSN1 does. If INSN2 is
3344 also a coprocessor instruction, assume there must be
3345 a one instruction gap. */
3346 if (pinfo2 & INSN_COP)
3351 /* Check for read-after-write dependencies on the coprocessor
3352 control registers in cases where INSN1 does not need a general
3353 coprocessor delay. This means that INSN1 is a floating point
3354 comparison instruction. */
3355 /* Itbl support may require additional care here. */
3356 else if (!cop_interlocks
3357 && (pinfo1 & INSN_WRITE_COND_CODE)
3358 && (pinfo2 & INSN_READ_COND_CODE))
3362 #undef INSN2_USES_GPR
3367 /* Return the number of nops that would be needed to work around the
3368 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3369 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3370 that are contained within the first IGNORE instructions of HIST. */
3373 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3374 const struct mips_cl_insn *insn)
3379 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3380 are not affected by the errata. */
3382 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3383 || strcmp (insn->insn_mo->name, "mtlo") == 0
3384 || strcmp (insn->insn_mo->name, "mthi") == 0))
3387 /* Search for the first MFLO or MFHI. */
3388 for (i = 0; i < MAX_VR4130_NOPS; i++)
3389 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3391 /* Extract the destination register. */
3392 mask = gpr_write_mask (&hist[i]);
3394 /* No nops are needed if INSN reads that register. */
3395 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3398 /* ...or if any of the intervening instructions do. */
3399 for (j = 0; j < i; j++)
3400 if (gpr_read_mask (&hist[j]) & mask)
3404 return MAX_VR4130_NOPS - i;
3409 #define BASE_REG_EQ(INSN1, INSN2) \
3410 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3411 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3413 /* Return the minimum alignment for this store instruction. */
3416 fix_24k_align_to (const struct mips_opcode *mo)
3418 if (strcmp (mo->name, "sh") == 0)
3421 if (strcmp (mo->name, "swc1") == 0
3422 || strcmp (mo->name, "swc2") == 0
3423 || strcmp (mo->name, "sw") == 0
3424 || strcmp (mo->name, "sc") == 0
3425 || strcmp (mo->name, "s.s") == 0)
3428 if (strcmp (mo->name, "sdc1") == 0
3429 || strcmp (mo->name, "sdc2") == 0
3430 || strcmp (mo->name, "s.d") == 0)
3437 struct fix_24k_store_info
3439 /* Immediate offset, if any, for this store instruction. */
3441 /* Alignment required by this store instruction. */
3443 /* True for register offsets. */
3444 int register_offset;
3447 /* Comparison function used by qsort. */
3450 fix_24k_sort (const void *a, const void *b)
3452 const struct fix_24k_store_info *pos1 = a;
3453 const struct fix_24k_store_info *pos2 = b;
3455 return (pos1->off - pos2->off);
3458 /* INSN is a store instruction. Try to record the store information
3459 in STINFO. Return false if the information isn't known. */
3462 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3463 const struct mips_cl_insn *insn)
3465 /* The instruction must have a known offset. */
3466 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3469 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3470 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3474 /* Return the number of nops that would be needed to work around the 24k
3475 "lost data on stores during refill" errata if instruction INSN
3476 immediately followed the 2 instructions described by HIST.
3477 Ignore hazards that are contained within the first IGNORE
3478 instructions of HIST.
3480 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3481 for the data cache refills and store data. The following describes
3482 the scenario where the store data could be lost.
3484 * A data cache miss, due to either a load or a store, causing fill
3485 data to be supplied by the memory subsystem
3486 * The first three doublewords of fill data are returned and written
3488 * A sequence of four stores occurs in consecutive cycles around the
3489 final doubleword of the fill:
3493 * Zero, One or more instructions
3496 The four stores A-D must be to different doublewords of the line that
3497 is being filled. The fourth instruction in the sequence above permits
3498 the fill of the final doubleword to be transferred from the FSB into
3499 the cache. In the sequence above, the stores may be either integer
3500 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3501 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3502 different doublewords on the line. If the floating point unit is
3503 running in 1:2 mode, it is not possible to create the sequence above
3504 using only floating point store instructions.
3506 In this case, the cache line being filled is incorrectly marked
3507 invalid, thereby losing the data from any store to the line that
3508 occurs between the original miss and the completion of the five
3509 cycle sequence shown above.
3511 The workarounds are:
3513 * Run the data cache in write-through mode.
3514 * Insert a non-store instruction between
3515 Store A and Store B or Store B and Store C. */
3518 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3519 const struct mips_cl_insn *insn)
3521 struct fix_24k_store_info pos[3];
3522 int align, i, base_offset;
3527 /* If the previous instruction wasn't a store, there's nothing to
3529 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3532 /* If the instructions after the previous one are unknown, we have
3533 to assume the worst. */
3537 /* Check whether we are dealing with three consecutive stores. */
3538 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3539 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3542 /* If we don't know the relationship between the store addresses,
3543 assume the worst. */
3544 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3545 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3548 if (!fix_24k_record_store_info (&pos[0], insn)
3549 || !fix_24k_record_store_info (&pos[1], &hist[0])
3550 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3553 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3555 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3556 X bytes and such that the base register + X is known to be aligned
3559 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3563 align = pos[0].align_to;
3564 base_offset = pos[0].off;
3565 for (i = 1; i < 3; i++)
3566 if (align < pos[i].align_to)
3568 align = pos[i].align_to;
3569 base_offset = pos[i].off;
3571 for (i = 0; i < 3; i++)
3572 pos[i].off -= base_offset;
3575 pos[0].off &= ~align + 1;
3576 pos[1].off &= ~align + 1;
3577 pos[2].off &= ~align + 1;
3579 /* If any two stores write to the same chunk, they also write to the
3580 same doubleword. The offsets are still sorted at this point. */
3581 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3584 /* A range of at least 9 bytes is needed for the stores to be in
3585 non-overlapping doublewords. */
3586 if (pos[2].off - pos[0].off <= 8)
3589 if (pos[2].off - pos[1].off >= 24
3590 || pos[1].off - pos[0].off >= 24
3591 || pos[2].off - pos[0].off >= 32)
3597 /* Return the number of nops that would be needed if instruction INSN
3598 immediately followed the MAX_NOPS instructions given by HIST,
3599 where HIST[0] is the most recent instruction. Ignore hazards
3600 between INSN and the first IGNORE instructions in HIST.
3602 If INSN is null, return the worse-case number of nops for any
3606 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3607 const struct mips_cl_insn *insn)
3609 int i, nops, tmp_nops;
3612 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3614 tmp_nops = insns_between (hist + i, insn) - i;
3615 if (tmp_nops > nops)
3619 if (mips_fix_vr4130 && !mips_opts.micromips)
3621 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3622 if (tmp_nops > nops)
3626 if (mips_fix_24k && !mips_opts.micromips)
3628 tmp_nops = nops_for_24k (ignore, hist, insn);
3629 if (tmp_nops > nops)
3636 /* The variable arguments provide NUM_INSNS extra instructions that
3637 might be added to HIST. Return the largest number of nops that
3638 would be needed after the extended sequence, ignoring hazards
3639 in the first IGNORE instructions. */
3642 nops_for_sequence (int num_insns, int ignore,
3643 const struct mips_cl_insn *hist, ...)
3646 struct mips_cl_insn buffer[MAX_NOPS];
3647 struct mips_cl_insn *cursor;
3650 va_start (args, hist);
3651 cursor = buffer + num_insns;
3652 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3653 while (cursor > buffer)
3654 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3656 nops = nops_for_insn (ignore, buffer, NULL);
3661 /* Like nops_for_insn, but if INSN is a branch, take into account the
3662 worst-case delay for the branch target. */
3665 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3666 const struct mips_cl_insn *insn)
3670 nops = nops_for_insn (ignore, hist, insn);
3671 if (delayed_branch_p (insn))
3673 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3674 hist, insn, get_delay_slot_nop (insn));
3675 if (tmp_nops > nops)
3678 else if (compact_branch_p (insn))
3680 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3681 if (tmp_nops > nops)
3687 /* Fix NOP issue: Replace nops by "or at,at,zero". */
3690 fix_loongson2f_nop (struct mips_cl_insn * ip)
3692 gas_assert (!HAVE_CODE_COMPRESSION);
3693 if (strcmp (ip->insn_mo->name, "nop") == 0)
3694 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3697 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3698 jr target pc &= 'hffff_ffff_cfff_ffff. */
3701 fix_loongson2f_jump (struct mips_cl_insn * ip)
3703 gas_assert (!HAVE_CODE_COMPRESSION);
3704 if (strcmp (ip->insn_mo->name, "j") == 0
3705 || strcmp (ip->insn_mo->name, "jr") == 0
3706 || strcmp (ip->insn_mo->name, "jalr") == 0)
3714 sreg = EXTRACT_OPERAND (0, RS, *ip);
3715 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3718 ep.X_op = O_constant;
3719 ep.X_add_number = 0xcfff0000;
3720 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3721 ep.X_add_number = 0xffff;
3722 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3723 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3728 fix_loongson2f (struct mips_cl_insn * ip)
3730 if (mips_fix_loongson2f_nop)
3731 fix_loongson2f_nop (ip);
3733 if (mips_fix_loongson2f_jump)
3734 fix_loongson2f_jump (ip);
3737 /* IP is a branch that has a delay slot, and we need to fill it
3738 automatically. Return true if we can do that by swapping IP
3739 with the previous instruction. */
3742 can_swap_branch_p (struct mips_cl_insn *ip)
3744 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
3745 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3747 /* -O2 and above is required for this optimization. */
3748 if (mips_optimize < 2)
3751 /* If we have seen .set volatile or .set nomove, don't optimize. */
3752 if (mips_opts.nomove)
3755 /* We can't swap if the previous instruction's position is fixed. */
3756 if (history[0].fixed_p)
3759 /* If the previous previous insn was in a .set noreorder, we can't
3760 swap. Actually, the MIPS assembler will swap in this situation.
3761 However, gcc configured -with-gnu-as will generate code like
3769 in which we can not swap the bne and INSN. If gcc is not configured
3770 -with-gnu-as, it does not output the .set pseudo-ops. */
3771 if (history[1].noreorder_p)
3774 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
3775 This means that the previous instruction was a 4-byte one anyhow. */
3776 if (mips_opts.mips16 && history[0].fixp[0])
3779 /* If the branch is itself the target of a branch, we can not swap.
3780 We cheat on this; all we check for is whether there is a label on
3781 this instruction. If there are any branches to anything other than
3782 a label, users must use .set noreorder. */
3783 if (seg_info (now_seg)->label_list)
3786 /* If the previous instruction is in a variant frag other than this
3787 branch's one, we cannot do the swap. This does not apply to
3788 MIPS16 code, which uses variant frags for different purposes. */
3789 if (!mips_opts.mips16
3791 && history[0].frag->fr_type == rs_machine_dependent)
3794 /* We do not swap with instructions that cannot architecturally
3795 be placed in a branch delay slot, such as SYNC or ERET. We
3796 also refrain from swapping with a trap instruction, since it
3797 complicates trap handlers to have the trap instruction be in
3799 prev_pinfo = history[0].insn_mo->pinfo;
3800 if (prev_pinfo & INSN_NO_DELAY_SLOT)
3803 /* Check for conflicts between the branch and the instructions
3804 before the candidate delay slot. */
3805 if (nops_for_insn (0, history + 1, ip) > 0)
3808 /* Check for conflicts between the swapped sequence and the
3809 target of the branch. */
3810 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3813 /* If the branch reads a register that the previous
3814 instruction sets, we can not swap. */
3815 gpr_read = gpr_read_mask (ip);
3816 prev_gpr_write = gpr_write_mask (&history[0]);
3817 if (gpr_read & prev_gpr_write)
3820 /* If the branch writes a register that the previous
3821 instruction sets, we can not swap. */
3822 gpr_write = gpr_write_mask (ip);
3823 if (gpr_write & prev_gpr_write)
3826 /* If the branch writes a register that the previous
3827 instruction reads, we can not swap. */
3828 prev_gpr_read = gpr_read_mask (&history[0]);
3829 if (gpr_write & prev_gpr_read)
3832 /* If one instruction sets a condition code and the
3833 other one uses a condition code, we can not swap. */
3834 pinfo = ip->insn_mo->pinfo;
3835 if ((pinfo & INSN_READ_COND_CODE)
3836 && (prev_pinfo & INSN_WRITE_COND_CODE))
3838 if ((pinfo & INSN_WRITE_COND_CODE)
3839 && (prev_pinfo & INSN_READ_COND_CODE))
3842 /* If the previous instruction uses the PC, we can not swap. */
3843 prev_pinfo2 = history[0].insn_mo->pinfo2;
3844 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3846 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
3849 /* If the previous instruction has an incorrect size for a fixed
3850 branch delay slot in microMIPS mode, we cannot swap. */
3851 pinfo2 = ip->insn_mo->pinfo2;
3852 if (mips_opts.micromips
3853 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
3854 && insn_length (history) != 2)
3856 if (mips_opts.micromips
3857 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
3858 && insn_length (history) != 4)
3864 /* Decide how we should add IP to the instruction stream. */
3866 static enum append_method
3867 get_append_method (struct mips_cl_insn *ip)
3869 unsigned long pinfo;
3871 /* The relaxed version of a macro sequence must be inherently
3873 if (mips_relax.sequence == 2)
3876 /* We must not dabble with instructions in a ".set norerorder" block. */
3877 if (mips_opts.noreorder)
3880 /* Otherwise, it's our responsibility to fill branch delay slots. */
3881 if (delayed_branch_p (ip))
3883 if (!branch_likely_p (ip) && can_swap_branch_p (ip))
3886 pinfo = ip->insn_mo->pinfo;
3887 if (mips_opts.mips16
3888 && ISA_SUPPORTS_MIPS16E
3889 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3890 return APPEND_ADD_COMPACT;
3892 return APPEND_ADD_WITH_NOP;
3898 /* IP is a MIPS16 instruction whose opcode we have just changed.
3899 Point IP->insn_mo to the new opcode's definition. */
3902 find_altered_mips16_opcode (struct mips_cl_insn *ip)
3904 const struct mips_opcode *mo, *end;
3906 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3907 for (mo = ip->insn_mo; mo < end; mo++)
3908 if ((ip->insn_opcode & mo->mask) == mo->match)
3916 /* For microMIPS macros, we need to generate a local number label
3917 as the target of branches. */
3918 #define MICROMIPS_LABEL_CHAR '\037'
3919 static unsigned long micromips_target_label;
3920 static char micromips_target_name[32];
3923 micromips_label_name (void)
3925 char *p = micromips_target_name;
3926 char symbol_name_temporary[24];
3934 l = micromips_target_label;
3935 #ifdef LOCAL_LABEL_PREFIX
3936 *p++ = LOCAL_LABEL_PREFIX;
3939 *p++ = MICROMIPS_LABEL_CHAR;
3942 symbol_name_temporary[i++] = l % 10 + '0';
3947 *p++ = symbol_name_temporary[--i];
3950 return micromips_target_name;
3954 micromips_label_expr (expressionS *label_expr)
3956 label_expr->X_op = O_symbol;
3957 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
3958 label_expr->X_add_number = 0;
3962 micromips_label_inc (void)
3964 micromips_target_label++;
3965 *micromips_target_name = '\0';
3969 micromips_add_label (void)
3973 s = colon (micromips_label_name ());
3974 micromips_label_inc ();
3975 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
3977 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
3983 /* If assembling microMIPS code, then return the microMIPS reloc
3984 corresponding to the requested one if any. Otherwise return
3985 the reloc unchanged. */
3987 static bfd_reloc_code_real_type
3988 micromips_map_reloc (bfd_reloc_code_real_type reloc)
3990 static const bfd_reloc_code_real_type relocs[][2] =
3992 /* Keep sorted incrementally by the left-hand key. */
3993 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
3994 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
3995 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
3996 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
3997 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
3998 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
3999 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4000 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4001 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4002 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4003 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4004 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4005 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4006 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4007 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4008 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4009 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4010 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4011 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4012 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4013 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4014 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4015 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4016 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4017 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4018 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4019 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4021 bfd_reloc_code_real_type r;
4024 if (!mips_opts.micromips)
4026 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4032 return relocs[i][1];
4037 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4038 Return true on success, storing the resolved value in RESULT. */
4041 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4046 case BFD_RELOC_MIPS_HIGHEST:
4047 case BFD_RELOC_MICROMIPS_HIGHEST:
4048 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4051 case BFD_RELOC_MIPS_HIGHER:
4052 case BFD_RELOC_MICROMIPS_HIGHER:
4053 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4056 case BFD_RELOC_HI16_S:
4057 case BFD_RELOC_MICROMIPS_HI16_S:
4058 case BFD_RELOC_MIPS16_HI16_S:
4059 *result = ((operand + 0x8000) >> 16) & 0xffff;
4062 case BFD_RELOC_HI16:
4063 case BFD_RELOC_MICROMIPS_HI16:
4064 case BFD_RELOC_MIPS16_HI16:
4065 *result = (operand >> 16) & 0xffff;
4068 case BFD_RELOC_LO16:
4069 case BFD_RELOC_MICROMIPS_LO16:
4070 case BFD_RELOC_MIPS16_LO16:
4071 *result = operand & 0xffff;
4074 case BFD_RELOC_UNUSED:
4083 /* Output an instruction. IP is the instruction information.
4084 ADDRESS_EXPR is an operand of the instruction to be used with
4085 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4086 a macro expansion. */
4089 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4090 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4092 unsigned long prev_pinfo2, pinfo;
4093 bfd_boolean relaxed_branch = FALSE;
4094 enum append_method method;
4095 bfd_boolean relax32;
4098 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4099 fix_loongson2f (ip);
4101 file_ase_mips16 |= mips_opts.mips16;
4102 file_ase_micromips |= mips_opts.micromips;
4104 prev_pinfo2 = history[0].insn_mo->pinfo2;
4105 pinfo = ip->insn_mo->pinfo;
4107 if (mips_opts.micromips
4109 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4110 && micromips_insn_length (ip->insn_mo) != 2)
4111 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4112 && micromips_insn_length (ip->insn_mo) != 4)))
4113 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4114 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4116 if (address_expr == NULL)
4118 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4119 && reloc_type[1] == BFD_RELOC_UNUSED
4120 && reloc_type[2] == BFD_RELOC_UNUSED
4121 && address_expr->X_op == O_constant)
4123 switch (*reloc_type)
4125 case BFD_RELOC_MIPS_JMP:
4129 shift = mips_opts.micromips ? 1 : 2;
4130 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4131 as_bad (_("jump to misaligned address (0x%lx)"),
4132 (unsigned long) address_expr->X_add_number);
4133 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4139 case BFD_RELOC_MIPS16_JMP:
4140 if ((address_expr->X_add_number & 3) != 0)
4141 as_bad (_("jump to misaligned address (0x%lx)"),
4142 (unsigned long) address_expr->X_add_number);
4144 (((address_expr->X_add_number & 0x7c0000) << 3)
4145 | ((address_expr->X_add_number & 0xf800000) >> 7)
4146 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4150 case BFD_RELOC_16_PCREL_S2:
4154 shift = mips_opts.micromips ? 1 : 2;
4155 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4156 as_bad (_("branch to misaligned address (0x%lx)"),
4157 (unsigned long) address_expr->X_add_number);
4158 if (!mips_relax_branch)
4160 if ((address_expr->X_add_number + (1 << (shift + 15)))
4161 & ~((1 << (shift + 16)) - 1))
4162 as_bad (_("branch address range overflow (0x%lx)"),
4163 (unsigned long) address_expr->X_add_number);
4164 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4174 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4177 ip->insn_opcode |= value & 0xffff;
4185 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4187 /* There are a lot of optimizations we could do that we don't.
4188 In particular, we do not, in general, reorder instructions.
4189 If you use gcc with optimization, it will reorder
4190 instructions and generally do much more optimization then we
4191 do here; repeating all that work in the assembler would only
4192 benefit hand written assembly code, and does not seem worth
4194 int nops = (mips_optimize == 0
4195 ? nops_for_insn (0, history, NULL)
4196 : nops_for_insn_or_target (0, history, ip));
4200 unsigned long old_frag_offset;
4203 old_frag = frag_now;
4204 old_frag_offset = frag_now_fix ();
4206 for (i = 0; i < nops; i++)
4207 add_fixed_insn (NOP_INSN);
4208 insert_into_history (0, nops, NOP_INSN);
4212 listing_prev_line ();
4213 /* We may be at the start of a variant frag. In case we
4214 are, make sure there is enough space for the frag
4215 after the frags created by listing_prev_line. The
4216 argument to frag_grow here must be at least as large
4217 as the argument to all other calls to frag_grow in
4218 this file. We don't have to worry about being in the
4219 middle of a variant frag, because the variants insert
4220 all needed nop instructions themselves. */
4224 mips_move_text_labels ();
4226 #ifndef NO_ECOFF_DEBUGGING
4227 if (ECOFF_DEBUGGING)
4228 ecoff_fix_loc (old_frag, old_frag_offset);
4232 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4236 /* Work out how many nops in prev_nop_frag are needed by IP,
4237 ignoring hazards generated by the first prev_nop_frag_since
4239 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4240 gas_assert (nops <= prev_nop_frag_holds);
4242 /* Enforce NOPS as a minimum. */
4243 if (nops > prev_nop_frag_required)
4244 prev_nop_frag_required = nops;
4246 if (prev_nop_frag_holds == prev_nop_frag_required)
4248 /* Settle for the current number of nops. Update the history
4249 accordingly (for the benefit of any future .set reorder code). */
4250 prev_nop_frag = NULL;
4251 insert_into_history (prev_nop_frag_since,
4252 prev_nop_frag_holds, NOP_INSN);
4256 /* Allow this instruction to replace one of the nops that was
4257 tentatively added to prev_nop_frag. */
4258 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4259 prev_nop_frag_holds--;
4260 prev_nop_frag_since++;
4264 method = get_append_method (ip);
4265 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4268 /* The value passed to dwarf2_emit_insn is the distance between
4269 the beginning of the current instruction and the address that
4270 should be recorded in the debug tables. This is normally the
4273 For MIPS16/microMIPS debug info we want to use ISA-encoded
4274 addresses, so we use -1 for an address higher by one than the
4277 If the instruction produced is a branch that we will swap with
4278 the preceding instruction, then we add the displacement by which
4279 the branch will be moved backwards. This is more appropriate
4280 and for MIPS16/microMIPS code also prevents a debugger from
4281 placing a breakpoint in the middle of the branch (and corrupting
4282 code if software breakpoints are used). */
4283 dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
4286 relax32 = (mips_relax_branch
4287 /* Don't try branch relaxation within .set nomacro, or within
4288 .set noat if we use $at for PIC computations. If it turns
4289 out that the branch was out-of-range, we'll get an error. */
4290 && !mips_opts.warn_about_macros
4291 && (mips_opts.at || mips_pic == NO_PIC)
4292 /* Don't relax BPOSGE32/64 as they have no complementing
4294 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
4296 if (!HAVE_CODE_COMPRESSION
4299 && *reloc_type == BFD_RELOC_16_PCREL_S2
4300 && delayed_branch_p (ip))
4302 relaxed_branch = TRUE;
4303 add_relaxed_insn (ip, (relaxed_branch_length
4305 uncond_branch_p (ip) ? -1
4306 : branch_likely_p (ip) ? 1
4310 uncond_branch_p (ip),
4311 branch_likely_p (ip),
4312 pinfo & INSN_WRITE_GPR_31,
4314 address_expr->X_add_symbol,
4315 address_expr->X_add_number);
4316 *reloc_type = BFD_RELOC_UNUSED;
4318 else if (mips_opts.micromips
4320 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4321 || *reloc_type > BFD_RELOC_UNUSED)
4322 && (delayed_branch_p (ip) || compact_branch_p (ip))
4323 /* Don't try branch relaxation when users specify
4324 16-bit/32-bit instructions. */
4325 && !forced_insn_length)
4327 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4328 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4329 int uncond = uncond_branch_p (ip) ? -1 : 0;
4330 int compact = compact_branch_p (ip);
4331 int al = pinfo & INSN_WRITE_GPR_31;
4334 gas_assert (address_expr != NULL);
4335 gas_assert (!mips_relax.sequence);
4337 relaxed_branch = TRUE;
4338 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4339 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4340 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4342 address_expr->X_add_symbol,
4343 address_expr->X_add_number);
4344 *reloc_type = BFD_RELOC_UNUSED;
4346 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4348 /* We need to set up a variant frag. */
4349 gas_assert (address_expr != NULL);
4350 add_relaxed_insn (ip, 4, 0,
4352 (*reloc_type - BFD_RELOC_UNUSED,
4353 forced_insn_length == 2, forced_insn_length == 4,
4354 delayed_branch_p (&history[0]),
4355 history[0].mips16_absolute_jump_p),
4356 make_expr_symbol (address_expr), 0);
4358 else if (mips_opts.mips16 && insn_length (ip) == 2)
4360 if (!delayed_branch_p (ip))
4361 /* Make sure there is enough room to swap this instruction with
4362 a following jump instruction. */
4364 add_fixed_insn (ip);
4368 if (mips_opts.mips16
4369 && mips_opts.noreorder
4370 && delayed_branch_p (&history[0]))
4371 as_warn (_("extended instruction in delay slot"));
4373 if (mips_relax.sequence)
4375 /* If we've reached the end of this frag, turn it into a variant
4376 frag and record the information for the instructions we've
4378 if (frag_room () < 4)
4379 relax_close_frag ();
4380 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4383 if (mips_relax.sequence != 2)
4385 if (mips_macro_warning.first_insn_sizes[0] == 0)
4386 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4387 mips_macro_warning.sizes[0] += insn_length (ip);
4388 mips_macro_warning.insns[0]++;
4390 if (mips_relax.sequence != 1)
4392 if (mips_macro_warning.first_insn_sizes[1] == 0)
4393 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4394 mips_macro_warning.sizes[1] += insn_length (ip);
4395 mips_macro_warning.insns[1]++;
4398 if (mips_opts.mips16)
4401 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4403 add_fixed_insn (ip);
4406 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4408 bfd_reloc_code_real_type final_type[3];
4409 reloc_howto_type *howto0;
4410 reloc_howto_type *howto;
4413 /* Perform any necessary conversion to microMIPS relocations
4414 and find out how many relocations there actually are. */
4415 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4416 final_type[i] = micromips_map_reloc (reloc_type[i]);
4418 /* In a compound relocation, it is the final (outermost)
4419 operator that determines the relocated field. */
4420 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4424 /* To reproduce this failure try assembling gas/testsuites/
4425 gas/mips/mips16-intermix.s with a mips-ecoff targeted
4427 as_bad (_("Unsupported MIPS relocation number %d"),
4429 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
4433 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4434 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4435 bfd_get_reloc_size (howto),
4437 howto0 && howto0->pc_relative,
4440 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4441 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4442 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4444 /* These relocations can have an addend that won't fit in
4445 4 octets for 64bit assembly. */
4447 && ! howto->partial_inplace
4448 && (reloc_type[0] == BFD_RELOC_16
4449 || reloc_type[0] == BFD_RELOC_32
4450 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4451 || reloc_type[0] == BFD_RELOC_GPREL16
4452 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4453 || reloc_type[0] == BFD_RELOC_GPREL32
4454 || reloc_type[0] == BFD_RELOC_64
4455 || reloc_type[0] == BFD_RELOC_CTOR
4456 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4457 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4458 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4459 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4460 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4461 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4462 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4463 || hi16_reloc_p (reloc_type[0])
4464 || lo16_reloc_p (reloc_type[0])))
4465 ip->fixp[0]->fx_no_overflow = 1;
4467 /* These relocations can have an addend that won't fit in 2 octets. */
4468 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4469 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4470 ip->fixp[0]->fx_no_overflow = 1;
4472 if (mips_relax.sequence)
4474 if (mips_relax.first_fixup == 0)
4475 mips_relax.first_fixup = ip->fixp[0];
4477 else if (reloc_needs_lo_p (*reloc_type))
4479 struct mips_hi_fixup *hi_fixup;
4481 /* Reuse the last entry if it already has a matching %lo. */
4482 hi_fixup = mips_hi_fixup_list;
4484 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4486 hi_fixup = ((struct mips_hi_fixup *)
4487 xmalloc (sizeof (struct mips_hi_fixup)));
4488 hi_fixup->next = mips_hi_fixup_list;
4489 mips_hi_fixup_list = hi_fixup;
4491 hi_fixup->fixp = ip->fixp[0];
4492 hi_fixup->seg = now_seg;
4495 /* Add fixups for the second and third relocations, if given.
4496 Note that the ABI allows the second relocation to be
4497 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4498 moment we only use RSS_UNDEF, but we could add support
4499 for the others if it ever becomes necessary. */
4500 for (i = 1; i < 3; i++)
4501 if (reloc_type[i] != BFD_RELOC_UNUSED)
4503 ip->fixp[i] = fix_new (ip->frag, ip->where,
4504 ip->fixp[0]->fx_size, NULL, 0,
4505 FALSE, final_type[i]);
4507 /* Use fx_tcbit to mark compound relocs. */
4508 ip->fixp[0]->fx_tcbit = 1;
4509 ip->fixp[i]->fx_tcbit = 1;
4514 /* Update the register mask information. */
4515 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4516 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4521 insert_into_history (0, 1, ip);
4524 case APPEND_ADD_WITH_NOP:
4526 struct mips_cl_insn *nop;
4528 insert_into_history (0, 1, ip);
4529 nop = get_delay_slot_nop (ip);
4530 add_fixed_insn (nop);
4531 insert_into_history (0, 1, nop);
4532 if (mips_relax.sequence)
4533 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4537 case APPEND_ADD_COMPACT:
4538 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4539 gas_assert (mips_opts.mips16);
4540 ip->insn_opcode |= 0x0080;
4541 find_altered_mips16_opcode (ip);
4543 insert_into_history (0, 1, ip);
4548 struct mips_cl_insn delay = history[0];
4549 if (mips_opts.mips16)
4551 know (delay.frag == ip->frag);
4552 move_insn (ip, delay.frag, delay.where);
4553 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4555 else if (relaxed_branch || delay.frag != ip->frag)
4557 /* Add the delay slot instruction to the end of the
4558 current frag and shrink the fixed part of the
4559 original frag. If the branch occupies the tail of
4560 the latter, move it backwards to cover the gap. */
4561 delay.frag->fr_fix -= branch_disp;
4562 if (delay.frag == ip->frag)
4563 move_insn (ip, ip->frag, ip->where - branch_disp);
4564 add_fixed_insn (&delay);
4568 move_insn (&delay, ip->frag,
4569 ip->where - branch_disp + insn_length (ip));
4570 move_insn (ip, history[0].frag, history[0].where);
4574 insert_into_history (0, 1, &delay);
4579 /* If we have just completed an unconditional branch, clear the history. */
4580 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4581 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4582 mips_no_prev_insn ();
4584 /* We need to emit a label at the end of branch-likely macros. */
4585 if (emit_branch_likely_macro)
4587 emit_branch_likely_macro = FALSE;
4588 micromips_add_label ();
4591 /* We just output an insn, so the next one doesn't have a label. */
4592 mips_clear_insn_labels ();
4595 /* Forget that there was any previous instruction or label. */
4598 mips_no_prev_insn (void)
4600 prev_nop_frag = NULL;
4601 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4602 mips_clear_insn_labels ();
4605 /* This function must be called before we emit something other than
4606 instructions. It is like mips_no_prev_insn except that it inserts
4607 any NOPS that might be needed by previous instructions. */
4610 mips_emit_delays (void)
4612 if (! mips_opts.noreorder)
4614 int nops = nops_for_insn (0, history, NULL);
4618 add_fixed_insn (NOP_INSN);
4619 mips_move_text_labels ();
4622 mips_no_prev_insn ();
4625 /* Start a (possibly nested) noreorder block. */
4628 start_noreorder (void)
4630 if (mips_opts.noreorder == 0)
4635 /* None of the instructions before the .set noreorder can be moved. */
4636 for (i = 0; i < ARRAY_SIZE (history); i++)
4637 history[i].fixed_p = 1;
4639 /* Insert any nops that might be needed between the .set noreorder
4640 block and the previous instructions. We will later remove any
4641 nops that turn out not to be needed. */
4642 nops = nops_for_insn (0, history, NULL);
4645 if (mips_optimize != 0)
4647 /* Record the frag which holds the nop instructions, so
4648 that we can remove them if we don't need them. */
4649 frag_grow (nops * NOP_INSN_SIZE);
4650 prev_nop_frag = frag_now;
4651 prev_nop_frag_holds = nops;
4652 prev_nop_frag_required = 0;
4653 prev_nop_frag_since = 0;
4656 for (; nops > 0; --nops)
4657 add_fixed_insn (NOP_INSN);
4659 /* Move on to a new frag, so that it is safe to simply
4660 decrease the size of prev_nop_frag. */
4661 frag_wane (frag_now);
4663 mips_move_text_labels ();
4665 mips_mark_labels ();
4666 mips_clear_insn_labels ();
4668 mips_opts.noreorder++;
4669 mips_any_noreorder = 1;
4672 /* End a nested noreorder block. */
4675 end_noreorder (void)
4677 mips_opts.noreorder--;
4678 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
4680 /* Commit to inserting prev_nop_frag_required nops and go back to
4681 handling nop insertion the .set reorder way. */
4682 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
4684 insert_into_history (prev_nop_frag_since,
4685 prev_nop_frag_required, NOP_INSN);
4686 prev_nop_frag = NULL;
4690 /* Set up global variables for the start of a new macro. */
4695 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
4696 memset (&mips_macro_warning.first_insn_sizes, 0,
4697 sizeof (mips_macro_warning.first_insn_sizes));
4698 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
4699 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
4700 && delayed_branch_p (&history[0]));
4701 switch (history[0].insn_mo->pinfo2
4702 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
4704 case INSN2_BRANCH_DELAY_32BIT:
4705 mips_macro_warning.delay_slot_length = 4;
4707 case INSN2_BRANCH_DELAY_16BIT:
4708 mips_macro_warning.delay_slot_length = 2;
4711 mips_macro_warning.delay_slot_length = 0;
4714 mips_macro_warning.first_frag = NULL;
4717 /* Given that a macro is longer than one instruction or of the wrong size,
4718 return the appropriate warning for it. Return null if no warning is
4719 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
4720 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
4721 and RELAX_NOMACRO. */
4724 macro_warning (relax_substateT subtype)
4726 if (subtype & RELAX_DELAY_SLOT)
4727 return _("Macro instruction expanded into multiple instructions"
4728 " in a branch delay slot");
4729 else if (subtype & RELAX_NOMACRO)
4730 return _("Macro instruction expanded into multiple instructions");
4731 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
4732 | RELAX_DELAY_SLOT_SIZE_SECOND))
4733 return ((subtype & RELAX_DELAY_SLOT_16BIT)
4734 ? _("Macro instruction expanded into a wrong size instruction"
4735 " in a 16-bit branch delay slot")
4736 : _("Macro instruction expanded into a wrong size instruction"
4737 " in a 32-bit branch delay slot"));
4742 /* Finish up a macro. Emit warnings as appropriate. */
4747 /* Relaxation warning flags. */
4748 relax_substateT subtype = 0;
4750 /* Check delay slot size requirements. */
4751 if (mips_macro_warning.delay_slot_length == 2)
4752 subtype |= RELAX_DELAY_SLOT_16BIT;
4753 if (mips_macro_warning.delay_slot_length != 0)
4755 if (mips_macro_warning.delay_slot_length
4756 != mips_macro_warning.first_insn_sizes[0])
4757 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
4758 if (mips_macro_warning.delay_slot_length
4759 != mips_macro_warning.first_insn_sizes[1])
4760 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
4763 /* Check instruction count requirements. */
4764 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
4766 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
4767 subtype |= RELAX_SECOND_LONGER;
4768 if (mips_opts.warn_about_macros)
4769 subtype |= RELAX_NOMACRO;
4770 if (mips_macro_warning.delay_slot_p)
4771 subtype |= RELAX_DELAY_SLOT;
4774 /* If both alternatives fail to fill a delay slot correctly,
4775 emit the warning now. */
4776 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
4777 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
4782 s = subtype & (RELAX_DELAY_SLOT_16BIT
4783 | RELAX_DELAY_SLOT_SIZE_FIRST
4784 | RELAX_DELAY_SLOT_SIZE_SECOND);
4785 msg = macro_warning (s);
4787 as_warn ("%s", msg);
4791 /* If both implementations are longer than 1 instruction, then emit the
4793 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
4798 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
4799 msg = macro_warning (s);
4801 as_warn ("%s", msg);
4805 /* If any flags still set, then one implementation might need a warning
4806 and the other either will need one of a different kind or none at all.
4807 Pass any remaining flags over to relaxation. */
4808 if (mips_macro_warning.first_frag != NULL)
4809 mips_macro_warning.first_frag->fr_subtype |= subtype;
4812 /* Instruction operand formats used in macros that vary between
4813 standard MIPS and microMIPS code. */
4815 static const char * const brk_fmt[2] = { "c", "mF" };
4816 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
4817 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
4818 static const char * const lui_fmt[2] = { "t,u", "s,u" };
4819 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
4820 static const char * const mfhl_fmt[2] = { "d", "mj" };
4821 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
4822 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
4824 #define BRK_FMT (brk_fmt[mips_opts.micromips])
4825 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
4826 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
4827 #define LUI_FMT (lui_fmt[mips_opts.micromips])
4828 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
4829 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
4830 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
4831 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
4833 /* Read a macro's relocation codes from *ARGS and store them in *R.
4834 The first argument in *ARGS will be either the code for a single
4835 relocation or -1 followed by the three codes that make up a
4836 composite relocation. */
4839 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
4843 next = va_arg (*args, int);
4845 r[0] = (bfd_reloc_code_real_type) next;
4847 for (i = 0; i < 3; i++)
4848 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
4851 /* Build an instruction created by a macro expansion. This is passed
4852 a pointer to the count of instructions created so far, an
4853 expression, the name of the instruction to build, an operand format
4854 string, and corresponding arguments. */
4857 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
4859 const struct mips_opcode *mo = NULL;
4860 bfd_reloc_code_real_type r[3];
4861 const struct mips_opcode *amo;
4862 struct hash_control *hash;
4863 struct mips_cl_insn insn;
4866 va_start (args, fmt);
4868 if (mips_opts.mips16)
4870 mips16_macro_build (ep, name, fmt, &args);
4875 r[0] = BFD_RELOC_UNUSED;
4876 r[1] = BFD_RELOC_UNUSED;
4877 r[2] = BFD_RELOC_UNUSED;
4878 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
4879 amo = (struct mips_opcode *) hash_find (hash, name);
4881 gas_assert (strcmp (name, amo->name) == 0);
4885 /* Search until we get a match for NAME. It is assumed here that
4886 macros will never generate MDMX, MIPS-3D, or MT instructions.
4887 We try to match an instruction that fulfils the branch delay
4888 slot instruction length requirement (if any) of the previous
4889 instruction. While doing this we record the first instruction
4890 seen that matches all the other conditions and use it anyway
4891 if the requirement cannot be met; we will issue an appropriate
4892 warning later on. */
4893 if (strcmp (fmt, amo->args) == 0
4894 && amo->pinfo != INSN_MACRO
4895 && is_opcode_valid (amo)
4896 && is_size_valid (amo))
4898 if (is_delay_slot_valid (amo))
4908 gas_assert (amo->name);
4910 while (strcmp (name, amo->name) == 0);
4913 create_insn (&insn, mo);
4931 INSERT_OPERAND (mips_opts.micromips,
4932 EXTLSB, insn, va_arg (args, int));
4937 /* Note that in the macro case, these arguments are already
4938 in MSB form. (When handling the instruction in the
4939 non-macro case, these arguments are sizes from which
4940 MSB values must be calculated.) */
4941 INSERT_OPERAND (mips_opts.micromips,
4942 INSMSB, insn, va_arg (args, int));
4948 /* Note that in the macro case, these arguments are already
4949 in MSBD form. (When handling the instruction in the
4950 non-macro case, these arguments are sizes from which
4951 MSBD values must be calculated.) */
4952 INSERT_OPERAND (mips_opts.micromips,
4953 EXTMSBD, insn, va_arg (args, int));
4957 gas_assert (!mips_opts.micromips);
4958 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
4967 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
4971 gas_assert (mips_opts.micromips);
4975 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
4979 gas_assert (!mips_opts.micromips);
4980 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
4984 gas_assert (!mips_opts.micromips);
4986 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
4990 if (mips_opts.micromips)
4991 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
4993 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
4997 gas_assert (!mips_opts.micromips);
4999 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5003 gas_assert (!mips_opts.micromips);
5005 int tmp = va_arg (args, int);
5007 INSERT_OPERAND (0, RT, insn, tmp);
5008 INSERT_OPERAND (0, RD, insn, tmp);
5014 gas_assert (!mips_opts.micromips);
5015 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5022 INSERT_OPERAND (mips_opts.micromips,
5023 SHAMT, insn, va_arg (args, int));
5027 gas_assert (!mips_opts.micromips);
5028 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5032 gas_assert (!mips_opts.micromips);
5033 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5037 gas_assert (!mips_opts.micromips);
5038 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5042 gas_assert (!mips_opts.micromips);
5043 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5050 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5055 macro_read_relocs (&args, r);
5056 gas_assert (*r == BFD_RELOC_GPREL16
5057 || *r == BFD_RELOC_MIPS_HIGHER
5058 || *r == BFD_RELOC_HI16_S
5059 || *r == BFD_RELOC_LO16
5060 || *r == BFD_RELOC_MIPS_GOT_OFST);
5064 macro_read_relocs (&args, r);
5068 macro_read_relocs (&args, r);
5069 gas_assert (ep != NULL
5070 && (ep->X_op == O_constant
5071 || (ep->X_op == O_symbol
5072 && (*r == BFD_RELOC_MIPS_HIGHEST
5073 || *r == BFD_RELOC_HI16_S
5074 || *r == BFD_RELOC_HI16
5075 || *r == BFD_RELOC_GPREL16
5076 || *r == BFD_RELOC_MIPS_GOT_HI16
5077 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5081 gas_assert (ep != NULL);
5084 * This allows macro() to pass an immediate expression for
5085 * creating short branches without creating a symbol.
5087 * We don't allow branch relaxation for these branches, as
5088 * they should only appear in ".set nomacro" anyway.
5090 if (ep->X_op == O_constant)
5092 /* For microMIPS we always use relocations for branches.
5093 So we should not resolve immediate values. */
5094 gas_assert (!mips_opts.micromips);
5096 if ((ep->X_add_number & 3) != 0)
5097 as_bad (_("branch to misaligned address (0x%lx)"),
5098 (unsigned long) ep->X_add_number);
5099 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5100 as_bad (_("branch address range overflow (0x%lx)"),
5101 (unsigned long) ep->X_add_number);
5102 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5106 *r = BFD_RELOC_16_PCREL_S2;
5110 gas_assert (ep != NULL);
5111 *r = BFD_RELOC_MIPS_JMP;
5115 gas_assert (!mips_opts.micromips);
5116 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5120 INSERT_OPERAND (mips_opts.micromips,
5121 CACHE, insn, va_arg (args, unsigned long));
5125 gas_assert (mips_opts.micromips);
5126 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5130 gas_assert (mips_opts.micromips);
5131 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5135 INSERT_OPERAND (mips_opts.micromips,
5136 3BITPOS, insn, va_arg (args, unsigned int));
5140 INSERT_OPERAND (mips_opts.micromips,
5141 OFFSET12, insn, va_arg (args, unsigned long));
5145 gas_assert (mips_opts.micromips);
5146 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5149 case 'm': /* Opcode extension character. */
5150 gas_assert (mips_opts.micromips);
5154 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5158 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5162 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5176 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5178 append_insn (&insn, ep, r, TRUE);
5182 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5185 struct mips_opcode *mo;
5186 struct mips_cl_insn insn;
5187 bfd_reloc_code_real_type r[3]
5188 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5190 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5192 gas_assert (strcmp (name, mo->name) == 0);
5194 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5197 gas_assert (mo->name);
5198 gas_assert (strcmp (name, mo->name) == 0);
5201 create_insn (&insn, mo);
5219 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5224 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5228 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5232 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5242 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5249 regno = va_arg (*args, int);
5250 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5251 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5274 gas_assert (ep != NULL);
5276 if (ep->X_op != O_constant)
5277 *r = (int) BFD_RELOC_UNUSED + c;
5278 else if (calculate_reloc (*r, ep->X_add_number, &value))
5280 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5282 *r = BFD_RELOC_UNUSED;
5288 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5295 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5297 append_insn (&insn, ep, r, TRUE);
5301 * Sign-extend 32-bit mode constants that have bit 31 set and all
5302 * higher bits unset.
5305 normalize_constant_expr (expressionS *ex)
5307 if (ex->X_op == O_constant
5308 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5309 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5314 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5315 * all higher bits unset.
5318 normalize_address_expr (expressionS *ex)
5320 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5321 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5322 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5323 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5328 * Generate a "jalr" instruction with a relocation hint to the called
5329 * function. This occurs in NewABI PIC code.
5332 macro_build_jalr (expressionS *ep, int cprestore)
5334 static const bfd_reloc_code_real_type jalr_relocs[2]
5335 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5336 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5340 if (MIPS_JALR_HINT_P (ep))
5345 if (mips_opts.micromips)
5347 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5348 if (MIPS_JALR_HINT_P (ep)
5349 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5350 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5352 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5355 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5356 if (MIPS_JALR_HINT_P (ep))
5357 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5361 * Generate a "lui" instruction.
5364 macro_build_lui (expressionS *ep, int regnum)
5366 gas_assert (! mips_opts.mips16);
5368 if (ep->X_op != O_constant)
5370 gas_assert (ep->X_op == O_symbol);
5371 /* _gp_disp is a special case, used from s_cpload.
5372 __gnu_local_gp is used if mips_no_shared. */
5373 gas_assert (mips_pic == NO_PIC
5375 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5376 || (! mips_in_shared
5377 && strcmp (S_GET_NAME (ep->X_add_symbol),
5378 "__gnu_local_gp") == 0));
5381 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5384 /* Generate a sequence of instructions to do a load or store from a constant
5385 offset off of a base register (breg) into/from a target register (treg),
5386 using AT if necessary. */
5388 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5389 int treg, int breg, int dbl)
5391 gas_assert (ep->X_op == O_constant);
5393 /* Sign-extending 32-bit constants makes their handling easier. */
5395 normalize_constant_expr (ep);
5397 /* Right now, this routine can only handle signed 32-bit constants. */
5398 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5399 as_warn (_("operand overflow"));
5401 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5403 /* Signed 16-bit offset will fit in the op. Easy! */
5404 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5408 /* 32-bit offset, need multiple instructions and AT, like:
5409 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5410 addu $tempreg,$tempreg,$breg
5411 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5412 to handle the complete offset. */
5413 macro_build_lui (ep, AT);
5414 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5415 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5418 as_bad (_("Macro used $at after \".set noat\""));
5423 * Generates code to set the $at register to true (one)
5424 * if reg is less than the immediate expression.
5427 set_at (int reg, int unsignedp)
5429 if (imm_expr.X_op == O_constant
5430 && imm_expr.X_add_number >= -0x8000
5431 && imm_expr.X_add_number < 0x8000)
5432 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5433 AT, reg, BFD_RELOC_LO16);
5436 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5437 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5441 /* Warn if an expression is not a constant. */
5444 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5446 if (ex->X_op == O_big)
5447 as_bad (_("unsupported large constant"));
5448 else if (ex->X_op != O_constant)
5449 as_bad (_("Instruction %s requires absolute expression"),
5452 if (HAVE_32BIT_GPRS)
5453 normalize_constant_expr (ex);
5456 /* Count the leading zeroes by performing a binary chop. This is a
5457 bulky bit of source, but performance is a LOT better for the
5458 majority of values than a simple loop to count the bits:
5459 for (lcnt = 0; (lcnt < 32); lcnt++)
5460 if ((v) & (1 << (31 - lcnt)))
5462 However it is not code size friendly, and the gain will drop a bit
5463 on certain cached systems.
5465 #define COUNT_TOP_ZEROES(v) \
5466 (((v) & ~0xffff) == 0 \
5467 ? ((v) & ~0xff) == 0 \
5468 ? ((v) & ~0xf) == 0 \
5469 ? ((v) & ~0x3) == 0 \
5470 ? ((v) & ~0x1) == 0 \
5475 : ((v) & ~0x7) == 0 \
5478 : ((v) & ~0x3f) == 0 \
5479 ? ((v) & ~0x1f) == 0 \
5482 : ((v) & ~0x7f) == 0 \
5485 : ((v) & ~0xfff) == 0 \
5486 ? ((v) & ~0x3ff) == 0 \
5487 ? ((v) & ~0x1ff) == 0 \
5490 : ((v) & ~0x7ff) == 0 \
5493 : ((v) & ~0x3fff) == 0 \
5494 ? ((v) & ~0x1fff) == 0 \
5497 : ((v) & ~0x7fff) == 0 \
5500 : ((v) & ~0xffffff) == 0 \
5501 ? ((v) & ~0xfffff) == 0 \
5502 ? ((v) & ~0x3ffff) == 0 \
5503 ? ((v) & ~0x1ffff) == 0 \
5506 : ((v) & ~0x7ffff) == 0 \
5509 : ((v) & ~0x3fffff) == 0 \
5510 ? ((v) & ~0x1fffff) == 0 \
5513 : ((v) & ~0x7fffff) == 0 \
5516 : ((v) & ~0xfffffff) == 0 \
5517 ? ((v) & ~0x3ffffff) == 0 \
5518 ? ((v) & ~0x1ffffff) == 0 \
5521 : ((v) & ~0x7ffffff) == 0 \
5524 : ((v) & ~0x3fffffff) == 0 \
5525 ? ((v) & ~0x1fffffff) == 0 \
5528 : ((v) & ~0x7fffffff) == 0 \
5533 * This routine generates the least number of instructions necessary to load
5534 * an absolute expression value into a register.
5537 load_register (int reg, expressionS *ep, int dbl)
5540 expressionS hi32, lo32;
5542 if (ep->X_op != O_big)
5544 gas_assert (ep->X_op == O_constant);
5546 /* Sign-extending 32-bit constants makes their handling easier. */
5548 normalize_constant_expr (ep);
5550 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5552 /* We can handle 16 bit signed values with an addiu to
5553 $zero. No need to ever use daddiu here, since $zero and
5554 the result are always correct in 32 bit mode. */
5555 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5558 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5560 /* We can handle 16 bit unsigned values with an ori to
5562 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5565 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5567 /* 32 bit values require an lui. */
5568 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5569 if ((ep->X_add_number & 0xffff) != 0)
5570 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5575 /* The value is larger than 32 bits. */
5577 if (!dbl || HAVE_32BIT_GPRS)
5581 sprintf_vma (value, ep->X_add_number);
5582 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5583 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5587 if (ep->X_op != O_big)
5590 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5591 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5592 hi32.X_add_number &= 0xffffffff;
5594 lo32.X_add_number &= 0xffffffff;
5598 gas_assert (ep->X_add_number > 2);
5599 if (ep->X_add_number == 3)
5600 generic_bignum[3] = 0;
5601 else if (ep->X_add_number > 4)
5602 as_bad (_("Number larger than 64 bits"));
5603 lo32.X_op = O_constant;
5604 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
5605 hi32.X_op = O_constant;
5606 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
5609 if (hi32.X_add_number == 0)
5614 unsigned long hi, lo;
5616 if (hi32.X_add_number == (offsetT) 0xffffffff)
5618 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
5620 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5623 if (lo32.X_add_number & 0x80000000)
5625 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5626 if (lo32.X_add_number & 0xffff)
5627 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5632 /* Check for 16bit shifted constant. We know that hi32 is
5633 non-zero, so start the mask on the first bit of the hi32
5638 unsigned long himask, lomask;
5642 himask = 0xffff >> (32 - shift);
5643 lomask = (0xffff << shift) & 0xffffffff;
5647 himask = 0xffff << (shift - 32);
5650 if ((hi32.X_add_number & ~(offsetT) himask) == 0
5651 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
5655 tmp.X_op = O_constant;
5657 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
5658 | (lo32.X_add_number >> shift));
5660 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
5661 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5662 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5663 reg, reg, (shift >= 32) ? shift - 32 : shift);
5668 while (shift <= (64 - 16));
5670 /* Find the bit number of the lowest one bit, and store the
5671 shifted value in hi/lo. */
5672 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
5673 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
5677 while ((lo & 1) == 0)
5682 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
5688 while ((hi & 1) == 0)
5697 /* Optimize if the shifted value is a (power of 2) - 1. */
5698 if ((hi == 0 && ((lo + 1) & lo) == 0)
5699 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
5701 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
5706 /* This instruction will set the register to be all
5708 tmp.X_op = O_constant;
5709 tmp.X_add_number = (offsetT) -1;
5710 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5714 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
5715 reg, reg, (bit >= 32) ? bit - 32 : bit);
5717 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
5718 reg, reg, (shift >= 32) ? shift - 32 : shift);
5723 /* Sign extend hi32 before calling load_register, because we can
5724 generally get better code when we load a sign extended value. */
5725 if ((hi32.X_add_number & 0x80000000) != 0)
5726 hi32.X_add_number |= ~(offsetT) 0xffffffff;
5727 load_register (reg, &hi32, 0);
5730 if ((lo32.X_add_number & 0xffff0000) == 0)
5734 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
5742 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
5744 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5745 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
5751 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
5755 mid16.X_add_number >>= 16;
5756 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5757 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5760 if ((lo32.X_add_number & 0xffff) != 0)
5761 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
5765 load_delay_nop (void)
5767 if (!gpr_interlocks)
5768 macro_build (NULL, "nop", "");
5771 /* Load an address into a register. */
5774 load_address (int reg, expressionS *ep, int *used_at)
5776 if (ep->X_op != O_constant
5777 && ep->X_op != O_symbol)
5779 as_bad (_("expression too complex"));
5780 ep->X_op = O_constant;
5783 if (ep->X_op == O_constant)
5785 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
5789 if (mips_pic == NO_PIC)
5791 /* If this is a reference to a GP relative symbol, we want
5792 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
5794 lui $reg,<sym> (BFD_RELOC_HI16_S)
5795 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5796 If we have an addend, we always use the latter form.
5798 With 64bit address space and a usable $at we want
5799 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5800 lui $at,<sym> (BFD_RELOC_HI16_S)
5801 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5802 daddiu $at,<sym> (BFD_RELOC_LO16)
5806 If $at is already in use, we use a path which is suboptimal
5807 on superscalar processors.
5808 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5809 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
5811 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
5813 daddiu $reg,<sym> (BFD_RELOC_LO16)
5815 For GP relative symbols in 64bit address space we can use
5816 the same sequence as in 32bit address space. */
5817 if (HAVE_64BIT_SYMBOLS)
5819 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5820 && !nopic_need_relax (ep->X_add_symbol, 1))
5822 relax_start (ep->X_add_symbol);
5823 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5824 mips_gp_register, BFD_RELOC_GPREL16);
5828 if (*used_at == 0 && mips_opts.at)
5830 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5831 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
5832 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5833 BFD_RELOC_MIPS_HIGHER);
5834 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
5835 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
5836 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
5841 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
5842 macro_build (ep, "daddiu", "t,r,j", reg, reg,
5843 BFD_RELOC_MIPS_HIGHER);
5844 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5845 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
5846 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
5847 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
5850 if (mips_relax.sequence)
5855 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
5856 && !nopic_need_relax (ep->X_add_symbol, 1))
5858 relax_start (ep->X_add_symbol);
5859 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
5860 mips_gp_register, BFD_RELOC_GPREL16);
5863 macro_build_lui (ep, reg);
5864 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
5865 reg, reg, BFD_RELOC_LO16);
5866 if (mips_relax.sequence)
5870 else if (!mips_big_got)
5874 /* If this is a reference to an external symbol, we want
5875 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5877 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5879 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5880 If there is a constant, it must be added in after.
5882 If we have NewABI, we want
5883 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5884 unless we're referencing a global symbol with a non-zero
5885 offset, in which case cst must be added separately. */
5888 if (ep->X_add_number)
5890 ex.X_add_number = ep->X_add_number;
5891 ep->X_add_number = 0;
5892 relax_start (ep->X_add_symbol);
5893 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5894 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5895 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5896 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5897 ex.X_op = O_constant;
5898 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5899 reg, reg, BFD_RELOC_LO16);
5900 ep->X_add_number = ex.X_add_number;
5903 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5904 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5905 if (mips_relax.sequence)
5910 ex.X_add_number = ep->X_add_number;
5911 ep->X_add_number = 0;
5912 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5913 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5915 relax_start (ep->X_add_symbol);
5917 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5921 if (ex.X_add_number != 0)
5923 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5924 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5925 ex.X_op = O_constant;
5926 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
5927 reg, reg, BFD_RELOC_LO16);
5931 else if (mips_big_got)
5935 /* This is the large GOT case. If this is a reference to an
5936 external symbol, we want
5937 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5939 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
5941 Otherwise, for a reference to a local symbol in old ABI, we want
5942 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5944 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
5945 If there is a constant, it must be added in after.
5947 In the NewABI, for local symbols, with or without offsets, we want:
5948 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5949 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5953 ex.X_add_number = ep->X_add_number;
5954 ep->X_add_number = 0;
5955 relax_start (ep->X_add_symbol);
5956 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5957 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5958 reg, reg, mips_gp_register);
5959 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5960 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5961 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
5962 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5963 else if (ex.X_add_number)
5965 ex.X_op = O_constant;
5966 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5970 ep->X_add_number = ex.X_add_number;
5972 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5973 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5974 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
5975 BFD_RELOC_MIPS_GOT_OFST);
5980 ex.X_add_number = ep->X_add_number;
5981 ep->X_add_number = 0;
5982 relax_start (ep->X_add_symbol);
5983 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
5984 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5985 reg, reg, mips_gp_register);
5986 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
5987 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
5989 if (reg_needs_delay (mips_gp_register))
5991 /* We need a nop before loading from $gp. This special
5992 check is required because the lui which starts the main
5993 instruction stream does not refer to $gp, and so will not
5994 insert the nop which may be required. */
5995 macro_build (NULL, "nop", "");
5997 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
5998 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6000 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6004 if (ex.X_add_number != 0)
6006 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6007 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6008 ex.X_op = O_constant;
6009 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6017 if (!mips_opts.at && *used_at == 1)
6018 as_bad (_("Macro used $at after \".set noat\""));
6021 /* Move the contents of register SOURCE into register DEST. */
6024 move_register (int dest, int source)
6026 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6027 instruction specifically requires a 32-bit one. */
6028 if (mips_opts.micromips
6029 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6030 macro_build (NULL, "move", "mp,mj", dest, source);
6032 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6036 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6037 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6038 The two alternatives are:
6040 Global symbol Local sybmol
6041 ------------- ------------
6042 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6044 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6046 load_got_offset emits the first instruction and add_got_offset
6047 emits the second for a 16-bit offset or add_got_offset_hilo emits
6048 a sequence to add a 32-bit offset using a scratch register. */
6051 load_got_offset (int dest, expressionS *local)
6056 global.X_add_number = 0;
6058 relax_start (local->X_add_symbol);
6059 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6060 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6062 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6063 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6068 add_got_offset (int dest, expressionS *local)
6072 global.X_op = O_constant;
6073 global.X_op_symbol = NULL;
6074 global.X_add_symbol = NULL;
6075 global.X_add_number = local->X_add_number;
6077 relax_start (local->X_add_symbol);
6078 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6079 dest, dest, BFD_RELOC_LO16);
6081 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6086 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6089 int hold_mips_optimize;
6091 global.X_op = O_constant;
6092 global.X_op_symbol = NULL;
6093 global.X_add_symbol = NULL;
6094 global.X_add_number = local->X_add_number;
6096 relax_start (local->X_add_symbol);
6097 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6099 /* Set mips_optimize around the lui instruction to avoid
6100 inserting an unnecessary nop after the lw. */
6101 hold_mips_optimize = mips_optimize;
6103 macro_build_lui (&global, tmp);
6104 mips_optimize = hold_mips_optimize;
6105 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6108 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6111 /* Emit a sequence of instructions to emulate a branch likely operation.
6112 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6113 is its complementing branch with the original condition negated.
6114 CALL is set if the original branch specified the link operation.
6115 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6117 Code like this is produced in the noreorder mode:
6122 delay slot (executed only if branch taken)
6130 delay slot (executed only if branch taken)
6133 In the reorder mode the delay slot would be filled with a nop anyway,
6134 so code produced is simply:
6139 This function is used when producing code for the microMIPS ASE that
6140 does not implement branch likely instructions in hardware. */
6143 macro_build_branch_likely (const char *br, const char *brneg,
6144 int call, expressionS *ep, const char *fmt,
6145 unsigned int sreg, unsigned int treg)
6147 int noreorder = mips_opts.noreorder;
6150 gas_assert (mips_opts.micromips);
6154 micromips_label_expr (&expr1);
6155 macro_build (&expr1, brneg, fmt, sreg, treg);
6156 macro_build (NULL, "nop", "");
6157 macro_build (ep, call ? "bal" : "b", "p");
6159 /* Set to true so that append_insn adds a label. */
6160 emit_branch_likely_macro = TRUE;
6164 macro_build (ep, br, fmt, sreg, treg);
6165 macro_build (NULL, "nop", "");
6170 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6171 the condition code tested. EP specifies the branch target. */
6174 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6201 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6204 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6205 the register tested. EP specifies the branch target. */
6208 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6210 const char *brneg = NULL;
6220 br = mips_opts.micromips ? "bgez" : "bgezl";
6224 gas_assert (mips_opts.micromips);
6233 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6240 br = mips_opts.micromips ? "blez" : "blezl";
6247 br = mips_opts.micromips ? "bltz" : "bltzl";
6251 gas_assert (mips_opts.micromips);
6259 if (mips_opts.micromips && brneg)
6260 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6262 macro_build (ep, br, "s,p", sreg);
6265 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6266 TREG as the registers tested. EP specifies the branch target. */
6269 macro_build_branch_rsrt (int type, expressionS *ep,
6270 unsigned int sreg, unsigned int treg)
6272 const char *brneg = NULL;
6284 br = mips_opts.micromips ? "beq" : "beql";
6293 br = mips_opts.micromips ? "bne" : "bnel";
6299 if (mips_opts.micromips && brneg)
6300 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6302 macro_build (ep, br, "s,t,p", sreg, treg);
6307 * This routine implements the seemingly endless macro or synthesized
6308 * instructions and addressing modes in the mips assembly language. Many
6309 * of these macros are simple and are similar to each other. These could
6310 * probably be handled by some kind of table or grammar approach instead of
6311 * this verbose method. Others are not simple macros but are more like
6312 * optimizing code generation.
6313 * One interesting optimization is when several store macros appear
6314 * consecutively that would load AT with the upper half of the same address.
6315 * The ensuing load upper instructions are ommited. This implies some kind
6316 * of global optimization. We currently only optimize within a single macro.
6317 * For many of the load and store macros if the address is specified as a
6318 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6319 * first load register 'at' with zero and use it as the base register. The
6320 * mips assembler simply uses register $zero. Just one tiny optimization
6324 macro (struct mips_cl_insn *ip)
6326 unsigned int treg, sreg, dreg, breg;
6327 unsigned int tempreg;
6330 expressionS label_expr;
6349 bfd_reloc_code_real_type r;
6350 int hold_mips_optimize;
6352 gas_assert (! mips_opts.mips16);
6354 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6355 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6356 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6357 mask = ip->insn_mo->mask;
6359 label_expr.X_op = O_constant;
6360 label_expr.X_op_symbol = NULL;
6361 label_expr.X_add_symbol = NULL;
6362 label_expr.X_add_number = 0;
6364 expr1.X_op = O_constant;
6365 expr1.X_op_symbol = NULL;
6366 expr1.X_add_symbol = NULL;
6367 expr1.X_add_number = 1;
6382 if (mips_opts.micromips)
6383 micromips_label_expr (&label_expr);
6385 label_expr.X_add_number = 8;
6386 macro_build (&label_expr, "bgez", "s,p", sreg);
6388 macro_build (NULL, "nop", "");
6390 move_register (dreg, sreg);
6391 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6392 if (mips_opts.micromips)
6393 micromips_add_label ();
6410 if (!mips_opts.micromips)
6412 if (imm_expr.X_op == O_constant
6413 && imm_expr.X_add_number >= -0x200
6414 && imm_expr.X_add_number < 0x200)
6416 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6425 if (imm_expr.X_op == O_constant
6426 && imm_expr.X_add_number >= -0x8000
6427 && imm_expr.X_add_number < 0x8000)
6429 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6434 load_register (AT, &imm_expr, dbl);
6435 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6454 if (imm_expr.X_op == O_constant
6455 && imm_expr.X_add_number >= 0
6456 && imm_expr.X_add_number < 0x10000)
6458 if (mask != M_NOR_I)
6459 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6462 macro_build (&imm_expr, "ori", "t,r,i",
6463 treg, sreg, BFD_RELOC_LO16);
6464 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6470 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6471 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6475 switch (imm_expr.X_add_number)
6478 macro_build (NULL, "nop", "");
6481 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6485 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6486 (int) imm_expr.X_add_number);
6489 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6490 (unsigned long) imm_expr.X_add_number);
6499 gas_assert (mips_opts.micromips);
6500 macro_build_branch_ccl (mask, &offset_expr,
6501 EXTRACT_OPERAND (1, BCC, *ip));
6508 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6514 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6519 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6526 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6528 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6532 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6533 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6534 &offset_expr, AT, ZERO);
6544 macro_build_branch_rs (mask, &offset_expr, sreg);
6550 /* Check for > max integer. */
6551 maxnum = 0x7fffffff;
6552 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6559 if (imm_expr.X_op == O_constant
6560 && imm_expr.X_add_number >= maxnum
6561 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6564 /* Result is always false. */
6566 macro_build (NULL, "nop", "");
6568 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6571 if (imm_expr.X_op != O_constant)
6572 as_bad (_("Unsupported large constant"));
6573 ++imm_expr.X_add_number;
6577 if (mask == M_BGEL_I)
6579 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6581 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6582 &offset_expr, sreg);
6585 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6587 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6588 &offset_expr, sreg);
6591 maxnum = 0x7fffffff;
6592 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6599 maxnum = - maxnum - 1;
6600 if (imm_expr.X_op == O_constant
6601 && imm_expr.X_add_number <= maxnum
6602 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6605 /* result is always true */
6606 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6607 macro_build (&offset_expr, "b", "p");
6612 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6613 &offset_expr, AT, ZERO);
6622 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6623 &offset_expr, ZERO, treg);
6627 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6628 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6629 &offset_expr, AT, ZERO);
6638 && imm_expr.X_op == O_constant
6639 && imm_expr.X_add_number == -1))
6641 if (imm_expr.X_op != O_constant)
6642 as_bad (_("Unsupported large constant"));
6643 ++imm_expr.X_add_number;
6647 if (mask == M_BGEUL_I)
6649 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6651 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6652 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6653 &offset_expr, sreg, ZERO);
6658 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6659 &offset_expr, AT, ZERO);
6667 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
6669 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
6673 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6674 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6675 &offset_expr, AT, ZERO);
6683 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6684 &offset_expr, sreg, ZERO);
6690 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6691 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6692 &offset_expr, AT, ZERO);
6700 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6702 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
6706 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
6707 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6708 &offset_expr, AT, ZERO);
6715 maxnum = 0x7fffffff;
6716 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
6723 if (imm_expr.X_op == O_constant
6724 && imm_expr.X_add_number >= maxnum
6725 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
6727 if (imm_expr.X_op != O_constant)
6728 as_bad (_("Unsupported large constant"));
6729 ++imm_expr.X_add_number;
6733 if (mask == M_BLTL_I)
6735 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6736 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6737 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6738 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
6743 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6744 &offset_expr, AT, ZERO);
6752 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6753 &offset_expr, sreg, ZERO);
6759 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
6760 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6761 &offset_expr, AT, ZERO);
6770 && imm_expr.X_op == O_constant
6771 && imm_expr.X_add_number == -1))
6773 if (imm_expr.X_op != O_constant)
6774 as_bad (_("Unsupported large constant"));
6775 ++imm_expr.X_add_number;
6779 if (mask == M_BLTUL_I)
6781 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6783 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6784 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6785 &offset_expr, sreg, ZERO);
6790 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6791 &offset_expr, AT, ZERO);
6799 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
6801 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
6805 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6806 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6807 &offset_expr, AT, ZERO);
6817 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6818 &offset_expr, ZERO, treg);
6822 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
6823 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
6824 &offset_expr, AT, ZERO);
6830 /* Use unsigned arithmetic. */
6834 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6836 as_bad (_("Unsupported large constant"));
6841 pos = imm_expr.X_add_number;
6842 size = imm2_expr.X_add_number;
6847 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6850 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6852 as_bad (_("Improper extract size (%lu, position %lu)"),
6853 (unsigned long) size, (unsigned long) pos);
6857 if (size <= 32 && pos < 32)
6862 else if (size <= 32)
6872 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6879 /* Use unsigned arithmetic. */
6883 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
6885 as_bad (_("Unsupported large constant"));
6890 pos = imm_expr.X_add_number;
6891 size = imm2_expr.X_add_number;
6896 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
6899 if (size == 0 || size > 64 || (pos + size - 1) > 63)
6901 as_bad (_("Improper insert size (%lu, position %lu)"),
6902 (unsigned long) size, (unsigned long) pos);
6906 if (pos < 32 && (pos + size - 1) < 32)
6921 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
6922 (int) (pos + size - 1));
6938 as_warn (_("Divide by zero."));
6940 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
6942 macro_build (NULL, "break", BRK_FMT, 7);
6949 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
6950 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6954 if (mips_opts.micromips)
6955 micromips_label_expr (&label_expr);
6957 label_expr.X_add_number = 8;
6958 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
6959 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
6960 macro_build (NULL, "break", BRK_FMT, 7);
6961 if (mips_opts.micromips)
6962 micromips_add_label ();
6964 expr1.X_add_number = -1;
6966 load_register (AT, &expr1, dbl);
6967 if (mips_opts.micromips)
6968 micromips_label_expr (&label_expr);
6970 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
6971 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
6974 expr1.X_add_number = 1;
6975 load_register (AT, &expr1, dbl);
6976 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
6980 expr1.X_add_number = 0x80000000;
6981 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
6985 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
6986 /* We want to close the noreorder block as soon as possible, so
6987 that later insns are available for delay slot filling. */
6992 if (mips_opts.micromips)
6993 micromips_label_expr (&label_expr);
6995 label_expr.X_add_number = 8;
6996 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
6997 macro_build (NULL, "nop", "");
6999 /* We want to close the noreorder block as soon as possible, so
7000 that later insns are available for delay slot filling. */
7003 macro_build (NULL, "break", BRK_FMT, 6);
7005 if (mips_opts.micromips)
7006 micromips_add_label ();
7007 macro_build (NULL, s, MFHL_FMT, dreg);
7046 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7048 as_warn (_("Divide by zero."));
7050 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7052 macro_build (NULL, "break", BRK_FMT, 7);
7055 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7057 if (strcmp (s2, "mflo") == 0)
7058 move_register (dreg, sreg);
7060 move_register (dreg, ZERO);
7063 if (imm_expr.X_op == O_constant
7064 && imm_expr.X_add_number == -1
7065 && s[strlen (s) - 1] != 'u')
7067 if (strcmp (s2, "mflo") == 0)
7069 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7072 move_register (dreg, ZERO);
7077 load_register (AT, &imm_expr, dbl);
7078 macro_build (NULL, s, "z,s,t", sreg, AT);
7079 macro_build (NULL, s2, MFHL_FMT, dreg);
7101 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7102 macro_build (NULL, s, "z,s,t", sreg, treg);
7103 /* We want to close the noreorder block as soon as possible, so
7104 that later insns are available for delay slot filling. */
7109 if (mips_opts.micromips)
7110 micromips_label_expr (&label_expr);
7112 label_expr.X_add_number = 8;
7113 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7114 macro_build (NULL, s, "z,s,t", sreg, treg);
7116 /* We want to close the noreorder block as soon as possible, so
7117 that later insns are available for delay slot filling. */
7119 macro_build (NULL, "break", BRK_FMT, 7);
7120 if (mips_opts.micromips)
7121 micromips_add_label ();
7123 macro_build (NULL, s2, MFHL_FMT, dreg);
7135 /* Load the address of a symbol into a register. If breg is not
7136 zero, we then add a base register to it. */
7138 if (dbl && HAVE_32BIT_GPRS)
7139 as_warn (_("dla used to load 32-bit register"));
7141 if (!dbl && HAVE_64BIT_OBJECTS)
7142 as_warn (_("la used to load 64-bit address"));
7144 if (offset_expr.X_op == O_constant
7145 && offset_expr.X_add_number >= -0x8000
7146 && offset_expr.X_add_number < 0x8000)
7148 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7149 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7153 if (mips_opts.at && (treg == breg))
7163 if (offset_expr.X_op != O_symbol
7164 && offset_expr.X_op != O_constant)
7166 as_bad (_("Expression too complex"));
7167 offset_expr.X_op = O_constant;
7170 if (offset_expr.X_op == O_constant)
7171 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7172 else if (mips_pic == NO_PIC)
7174 /* If this is a reference to a GP relative symbol, we want
7175 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7177 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7178 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7179 If we have a constant, we need two instructions anyhow,
7180 so we may as well always use the latter form.
7182 With 64bit address space and a usable $at we want
7183 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7184 lui $at,<sym> (BFD_RELOC_HI16_S)
7185 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7186 daddiu $at,<sym> (BFD_RELOC_LO16)
7188 daddu $tempreg,$tempreg,$at
7190 If $at is already in use, we use a path which is suboptimal
7191 on superscalar processors.
7192 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7193 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7195 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7197 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7199 For GP relative symbols in 64bit address space we can use
7200 the same sequence as in 32bit address space. */
7201 if (HAVE_64BIT_SYMBOLS)
7203 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7204 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7206 relax_start (offset_expr.X_add_symbol);
7207 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7208 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7212 if (used_at == 0 && mips_opts.at)
7214 macro_build (&offset_expr, "lui", LUI_FMT,
7215 tempreg, BFD_RELOC_MIPS_HIGHEST);
7216 macro_build (&offset_expr, "lui", LUI_FMT,
7217 AT, BFD_RELOC_HI16_S);
7218 macro_build (&offset_expr, "daddiu", "t,r,j",
7219 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7220 macro_build (&offset_expr, "daddiu", "t,r,j",
7221 AT, AT, BFD_RELOC_LO16);
7222 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7223 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7228 macro_build (&offset_expr, "lui", LUI_FMT,
7229 tempreg, BFD_RELOC_MIPS_HIGHEST);
7230 macro_build (&offset_expr, "daddiu", "t,r,j",
7231 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7232 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7233 macro_build (&offset_expr, "daddiu", "t,r,j",
7234 tempreg, tempreg, BFD_RELOC_HI16_S);
7235 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7236 macro_build (&offset_expr, "daddiu", "t,r,j",
7237 tempreg, tempreg, BFD_RELOC_LO16);
7240 if (mips_relax.sequence)
7245 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7246 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7248 relax_start (offset_expr.X_add_symbol);
7249 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7250 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7253 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7254 as_bad (_("Offset too large"));
7255 macro_build_lui (&offset_expr, tempreg);
7256 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7257 tempreg, tempreg, BFD_RELOC_LO16);
7258 if (mips_relax.sequence)
7262 else if (!mips_big_got && !HAVE_NEWABI)
7264 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7266 /* If this is a reference to an external symbol, and there
7267 is no constant, we want
7268 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7269 or for lca or if tempreg is PIC_CALL_REG
7270 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7271 For a local symbol, we want
7272 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7274 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7276 If we have a small constant, and this is a reference to
7277 an external symbol, we want
7278 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7280 addiu $tempreg,$tempreg,<constant>
7281 For a local symbol, we want the same instruction
7282 sequence, but we output a BFD_RELOC_LO16 reloc on the
7285 If we have a large constant, and this is a reference to
7286 an external symbol, we want
7287 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7288 lui $at,<hiconstant>
7289 addiu $at,$at,<loconstant>
7290 addu $tempreg,$tempreg,$at
7291 For a local symbol, we want the same instruction
7292 sequence, but we output a BFD_RELOC_LO16 reloc on the
7296 if (offset_expr.X_add_number == 0)
7298 if (mips_pic == SVR4_PIC
7300 && (call || tempreg == PIC_CALL_REG))
7301 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7303 relax_start (offset_expr.X_add_symbol);
7304 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7305 lw_reloc_type, mips_gp_register);
7308 /* We're going to put in an addu instruction using
7309 tempreg, so we may as well insert the nop right
7314 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7315 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7317 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7318 tempreg, tempreg, BFD_RELOC_LO16);
7320 /* FIXME: If breg == 0, and the next instruction uses
7321 $tempreg, then if this variant case is used an extra
7322 nop will be generated. */
7324 else if (offset_expr.X_add_number >= -0x8000
7325 && offset_expr.X_add_number < 0x8000)
7327 load_got_offset (tempreg, &offset_expr);
7329 add_got_offset (tempreg, &offset_expr);
7333 expr1.X_add_number = offset_expr.X_add_number;
7334 offset_expr.X_add_number =
7335 SEXT_16BIT (offset_expr.X_add_number);
7336 load_got_offset (tempreg, &offset_expr);
7337 offset_expr.X_add_number = expr1.X_add_number;
7338 /* If we are going to add in a base register, and the
7339 target register and the base register are the same,
7340 then we are using AT as a temporary register. Since
7341 we want to load the constant into AT, we add our
7342 current AT (from the global offset table) and the
7343 register into the register now, and pretend we were
7344 not using a base register. */
7348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7353 add_got_offset_hilo (tempreg, &offset_expr, AT);
7357 else if (!mips_big_got && HAVE_NEWABI)
7359 int add_breg_early = 0;
7361 /* If this is a reference to an external, and there is no
7362 constant, or local symbol (*), with or without a
7364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7365 or for lca or if tempreg is PIC_CALL_REG
7366 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7368 If we have a small constant, and this is a reference to
7369 an external symbol, we want
7370 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7371 addiu $tempreg,$tempreg,<constant>
7373 If we have a large constant, and this is a reference to
7374 an external symbol, we want
7375 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7376 lui $at,<hiconstant>
7377 addiu $at,$at,<loconstant>
7378 addu $tempreg,$tempreg,$at
7380 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7381 local symbols, even though it introduces an additional
7384 if (offset_expr.X_add_number)
7386 expr1.X_add_number = offset_expr.X_add_number;
7387 offset_expr.X_add_number = 0;
7389 relax_start (offset_expr.X_add_symbol);
7390 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7391 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7393 if (expr1.X_add_number >= -0x8000
7394 && expr1.X_add_number < 0x8000)
7396 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7397 tempreg, tempreg, BFD_RELOC_LO16);
7399 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7401 /* If we are going to add in a base register, and the
7402 target register and the base register are the same,
7403 then we are using AT as a temporary register. Since
7404 we want to load the constant into AT, we add our
7405 current AT (from the global offset table) and the
7406 register into the register now, and pretend we were
7407 not using a base register. */
7412 gas_assert (tempreg == AT);
7413 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7419 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7420 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7426 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7429 offset_expr.X_add_number = expr1.X_add_number;
7431 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7432 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7436 treg, tempreg, breg);
7442 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7444 relax_start (offset_expr.X_add_symbol);
7445 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7446 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7448 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7449 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7454 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7455 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7458 else if (mips_big_got && !HAVE_NEWABI)
7461 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7462 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7463 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7465 /* This is the large GOT case. If this is a reference to an
7466 external symbol, and there is no constant, we want
7467 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7468 addu $tempreg,$tempreg,$gp
7469 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7470 or for lca or if tempreg is PIC_CALL_REG
7471 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7472 addu $tempreg,$tempreg,$gp
7473 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7474 For a local symbol, we want
7475 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7477 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7479 If we have a small constant, and this is a reference to
7480 an external symbol, we want
7481 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7482 addu $tempreg,$tempreg,$gp
7483 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7485 addiu $tempreg,$tempreg,<constant>
7486 For a local symbol, we want
7487 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7489 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7491 If we have a large constant, and this is a reference to
7492 an external symbol, we want
7493 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7494 addu $tempreg,$tempreg,$gp
7495 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7496 lui $at,<hiconstant>
7497 addiu $at,$at,<loconstant>
7498 addu $tempreg,$tempreg,$at
7499 For a local symbol, we want
7500 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7501 lui $at,<hiconstant>
7502 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7503 addu $tempreg,$tempreg,$at
7506 expr1.X_add_number = offset_expr.X_add_number;
7507 offset_expr.X_add_number = 0;
7508 relax_start (offset_expr.X_add_symbol);
7509 gpdelay = reg_needs_delay (mips_gp_register);
7510 if (expr1.X_add_number == 0 && breg == 0
7511 && (call || tempreg == PIC_CALL_REG))
7513 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7514 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7516 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7517 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7518 tempreg, tempreg, mips_gp_register);
7519 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7520 tempreg, lw_reloc_type, tempreg);
7521 if (expr1.X_add_number == 0)
7525 /* We're going to put in an addu instruction using
7526 tempreg, so we may as well insert the nop right
7531 else if (expr1.X_add_number >= -0x8000
7532 && expr1.X_add_number < 0x8000)
7535 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7536 tempreg, tempreg, BFD_RELOC_LO16);
7540 /* If we are going to add in a base register, and the
7541 target register and the base register are the same,
7542 then we are using AT as a temporary register. Since
7543 we want to load the constant into AT, we add our
7544 current AT (from the global offset table) and the
7545 register into the register now, and pretend we were
7546 not using a base register. */
7551 gas_assert (tempreg == AT);
7553 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7558 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7559 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7563 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7568 /* This is needed because this instruction uses $gp, but
7569 the first instruction on the main stream does not. */
7570 macro_build (NULL, "nop", "");
7573 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7574 local_reloc_type, mips_gp_register);
7575 if (expr1.X_add_number >= -0x8000
7576 && expr1.X_add_number < 0x8000)
7579 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7580 tempreg, tempreg, BFD_RELOC_LO16);
7581 /* FIXME: If add_number is 0, and there was no base
7582 register, the external symbol case ended with a load,
7583 so if the symbol turns out to not be external, and
7584 the next instruction uses tempreg, an unnecessary nop
7585 will be inserted. */
7591 /* We must add in the base register now, as in the
7592 external symbol case. */
7593 gas_assert (tempreg == AT);
7595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7598 /* We set breg to 0 because we have arranged to add
7599 it in in both cases. */
7603 macro_build_lui (&expr1, AT);
7604 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7605 AT, AT, BFD_RELOC_LO16);
7606 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7607 tempreg, tempreg, AT);
7612 else if (mips_big_got && HAVE_NEWABI)
7614 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7615 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7616 int add_breg_early = 0;
7618 /* This is the large GOT case. If this is a reference to an
7619 external symbol, and there is no constant, we want
7620 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7621 add $tempreg,$tempreg,$gp
7622 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7623 or for lca or if tempreg is PIC_CALL_REG
7624 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7625 add $tempreg,$tempreg,$gp
7626 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7628 If we have a small constant, and this is a reference to
7629 an external symbol, we want
7630 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7631 add $tempreg,$tempreg,$gp
7632 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7633 addi $tempreg,$tempreg,<constant>
7635 If we have a large constant, and this is a reference to
7636 an external symbol, we want
7637 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7638 addu $tempreg,$tempreg,$gp
7639 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7640 lui $at,<hiconstant>
7641 addi $at,$at,<loconstant>
7642 add $tempreg,$tempreg,$at
7644 If we have NewABI, and we know it's a local symbol, we want
7645 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7646 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
7647 otherwise we have to resort to GOT_HI16/GOT_LO16. */
7649 relax_start (offset_expr.X_add_symbol);
7651 expr1.X_add_number = offset_expr.X_add_number;
7652 offset_expr.X_add_number = 0;
7654 if (expr1.X_add_number == 0 && breg == 0
7655 && (call || tempreg == PIC_CALL_REG))
7657 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7658 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7660 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7661 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7662 tempreg, tempreg, mips_gp_register);
7663 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7664 tempreg, lw_reloc_type, tempreg);
7666 if (expr1.X_add_number == 0)
7668 else if (expr1.X_add_number >= -0x8000
7669 && expr1.X_add_number < 0x8000)
7671 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7672 tempreg, tempreg, BFD_RELOC_LO16);
7674 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7676 /* If we are going to add in a base register, and the
7677 target register and the base register are the same,
7678 then we are using AT as a temporary register. Since
7679 we want to load the constant into AT, we add our
7680 current AT (from the global offset table) and the
7681 register into the register now, and pretend we were
7682 not using a base register. */
7687 gas_assert (tempreg == AT);
7688 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7694 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7695 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7700 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7703 offset_expr.X_add_number = expr1.X_add_number;
7704 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7705 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7706 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7707 tempreg, BFD_RELOC_MIPS_GOT_OFST);
7710 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7711 treg, tempreg, breg);
7721 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
7725 gas_assert (!mips_opts.micromips);
7727 unsigned long temp = (treg << 16) | (0x01);
7728 macro_build (NULL, "c2", "C", temp);
7733 gas_assert (!mips_opts.micromips);
7735 unsigned long temp = (0x02);
7736 macro_build (NULL, "c2", "C", temp);
7741 gas_assert (!mips_opts.micromips);
7743 unsigned long temp = (treg << 16) | (0x02);
7744 macro_build (NULL, "c2", "C", temp);
7749 gas_assert (!mips_opts.micromips);
7750 macro_build (NULL, "c2", "C", 3);
7754 gas_assert (!mips_opts.micromips);
7756 unsigned long temp = (treg << 16) | 0x03;
7757 macro_build (NULL, "c2", "C", temp);
7762 /* The j instruction may not be used in PIC code, since it
7763 requires an absolute address. We convert it to a b
7765 if (mips_pic == NO_PIC)
7766 macro_build (&offset_expr, "j", "a");
7768 macro_build (&offset_expr, "b", "p");
7771 /* The jal instructions must be handled as macros because when
7772 generating PIC code they expand to multi-instruction
7773 sequences. Normally they are simple instructions. */
7778 gas_assert (mips_opts.micromips);
7786 if (mips_pic == NO_PIC)
7788 s = jals ? "jalrs" : "jalr";
7789 if (mips_opts.micromips
7791 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7792 macro_build (NULL, s, "mj", sreg);
7794 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7798 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
7799 && mips_cprestore_offset >= 0);
7801 if (sreg != PIC_CALL_REG)
7802 as_warn (_("MIPS PIC call to register other than $25"));
7804 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
7805 ? "jalrs" : "jalr");
7806 if (mips_opts.micromips
7808 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7809 macro_build (NULL, s, "mj", sreg);
7811 macro_build (NULL, s, JALR_FMT, dreg, sreg);
7812 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
7814 if (mips_cprestore_offset < 0)
7815 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7818 if (!mips_frame_reg_valid)
7820 as_warn (_("No .frame pseudo-op used in PIC code"));
7821 /* Quiet this warning. */
7822 mips_frame_reg_valid = 1;
7824 if (!mips_cprestore_valid)
7826 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7827 /* Quiet this warning. */
7828 mips_cprestore_valid = 1;
7830 if (mips_opts.noreorder)
7831 macro_build (NULL, "nop", "");
7832 expr1.X_add_number = mips_cprestore_offset;
7833 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7836 HAVE_64BIT_ADDRESSES);
7844 gas_assert (mips_opts.micromips);
7848 if (mips_pic == NO_PIC)
7849 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
7850 else if (mips_pic == SVR4_PIC)
7852 /* If this is a reference to an external symbol, and we are
7853 using a small GOT, we want
7854 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7858 lw $gp,cprestore($sp)
7859 The cprestore value is set using the .cprestore
7860 pseudo-op. If we are using a big GOT, we want
7861 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7863 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
7867 lw $gp,cprestore($sp)
7868 If the symbol is not external, we want
7869 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7871 addiu $25,$25,<sym> (BFD_RELOC_LO16)
7874 lw $gp,cprestore($sp)
7876 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
7877 sequences above, minus nops, unless the symbol is local,
7878 which enables us to use GOT_PAGE/GOT_OFST (big got) or
7884 relax_start (offset_expr.X_add_symbol);
7885 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7886 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7889 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7890 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
7896 relax_start (offset_expr.X_add_symbol);
7897 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7898 BFD_RELOC_MIPS_CALL_HI16);
7899 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7900 PIC_CALL_REG, mips_gp_register);
7901 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7902 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7905 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7906 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
7908 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7909 PIC_CALL_REG, PIC_CALL_REG,
7910 BFD_RELOC_MIPS_GOT_OFST);
7914 macro_build_jalr (&offset_expr, 0);
7918 relax_start (offset_expr.X_add_symbol);
7921 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7922 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
7931 gpdelay = reg_needs_delay (mips_gp_register);
7932 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
7933 BFD_RELOC_MIPS_CALL_HI16);
7934 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
7935 PIC_CALL_REG, mips_gp_register);
7936 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7937 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
7942 macro_build (NULL, "nop", "");
7944 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7945 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
7948 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7949 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
7951 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
7953 if (mips_cprestore_offset < 0)
7954 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7957 if (!mips_frame_reg_valid)
7959 as_warn (_("No .frame pseudo-op used in PIC code"));
7960 /* Quiet this warning. */
7961 mips_frame_reg_valid = 1;
7963 if (!mips_cprestore_valid)
7965 as_warn (_("No .cprestore pseudo-op used in PIC code"));
7966 /* Quiet this warning. */
7967 mips_cprestore_valid = 1;
7969 if (mips_opts.noreorder)
7970 macro_build (NULL, "nop", "");
7971 expr1.X_add_number = mips_cprestore_offset;
7972 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
7975 HAVE_64BIT_ADDRESSES);
7979 else if (mips_pic == VXWORKS_PIC)
7980 as_bad (_("Non-PIC jump used in PIC library"));
7990 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
7998 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8029 gas_assert (!mips_opts.micromips);
8032 /* Itbl support may require additional care here. */
8039 /* Itbl support may require additional care here. */
8047 off12 = mips_opts.micromips;
8048 /* Itbl support may require additional care here. */
8053 gas_assert (!mips_opts.micromips);
8056 /* Itbl support may require additional care here. */
8064 off12 = mips_opts.micromips;
8071 off12 = mips_opts.micromips;
8077 /* Itbl support may require additional care here. */
8085 off12 = mips_opts.micromips;
8086 /* Itbl support may require additional care here. */
8093 /* Itbl support may require additional care here. */
8101 off12 = mips_opts.micromips;
8108 off12 = mips_opts.micromips;
8115 off12 = mips_opts.micromips;
8122 off12 = mips_opts.micromips;
8129 off12 = mips_opts.micromips;
8134 gas_assert (mips_opts.micromips);
8143 gas_assert (mips_opts.micromips);
8152 gas_assert (mips_opts.micromips);
8160 gas_assert (mips_opts.micromips);
8167 if (breg == treg + lp)
8170 tempreg = treg + lp;
8190 gas_assert (!mips_opts.micromips);
8193 /* Itbl support may require additional care here. */
8200 /* Itbl support may require additional care here. */
8208 off12 = mips_opts.micromips;
8209 /* Itbl support may require additional care here. */
8214 gas_assert (!mips_opts.micromips);
8217 /* Itbl support may require additional care here. */
8225 off12 = mips_opts.micromips;
8232 off12 = mips_opts.micromips;
8239 off12 = mips_opts.micromips;
8246 off12 = mips_opts.micromips;
8252 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8253 off12 = mips_opts.micromips;
8259 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8260 off12 = mips_opts.micromips;
8267 /* Itbl support may require additional care here. */
8274 off12 = mips_opts.micromips;
8275 /* Itbl support may require additional care here. */
8280 gas_assert (!mips_opts.micromips);
8283 /* Itbl support may require additional care here. */
8291 off12 = mips_opts.micromips;
8298 off12 = mips_opts.micromips;
8303 gas_assert (mips_opts.micromips);
8311 gas_assert (mips_opts.micromips);
8319 gas_assert (mips_opts.micromips);
8327 gas_assert (mips_opts.micromips);
8336 if (offset_expr.X_op != O_constant
8337 && offset_expr.X_op != O_symbol)
8339 as_bad (_("Expression too complex"));
8340 offset_expr.X_op = O_constant;
8343 if (HAVE_32BIT_ADDRESSES
8344 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8348 sprintf_vma (value, offset_expr.X_add_number);
8349 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8352 /* A constant expression in PIC code can be handled just as it
8353 is in non PIC code. */
8354 if (offset_expr.X_op == O_constant)
8358 expr1.X_add_number = offset_expr.X_add_number;
8359 normalize_address_expr (&expr1);
8360 if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8362 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8363 & ~(bfd_vma) 0xffff);
8366 else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8368 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8369 & ~(bfd_vma) 0xfff);
8374 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8376 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8377 tempreg, tempreg, breg);
8382 if (offset_expr.X_add_number == 0)
8385 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8386 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8387 macro_build (NULL, s, fmt, treg, tempreg);
8390 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8392 macro_build (NULL, s, fmt,
8393 treg, (unsigned long) offset_expr.X_add_number, breg);
8395 else if (off12 || off0)
8397 /* A 12-bit or 0-bit offset field is too narrow to be used
8398 for a low-part relocation, so load the whole address into
8399 the auxillary register. In the case of "A(b)" addresses,
8400 we first load absolute address "A" into the register and
8401 then add base register "b". In the case of "o(b)" addresses,
8402 we simply need to add 16-bit offset "o" to base register "b", and
8403 offset_reloc already contains the relocations associated
8407 load_address (tempreg, &offset_expr, &used_at);
8409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8410 tempreg, tempreg, breg);
8413 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8415 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8416 expr1.X_add_number = 0;
8418 macro_build (NULL, s, fmt, treg, tempreg);
8420 macro_build (NULL, s, fmt,
8421 treg, (unsigned long) expr1.X_add_number, tempreg);
8423 else if (mips_pic == NO_PIC)
8425 /* If this is a reference to a GP relative symbol, and there
8426 is no base register, we want
8427 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8428 Otherwise, if there is no base register, we want
8429 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8430 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8431 If we have a constant, we need two instructions anyhow,
8432 so we always use the latter form.
8434 If we have a base register, and this is a reference to a
8435 GP relative symbol, we want
8436 addu $tempreg,$breg,$gp
8437 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8439 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8440 addu $tempreg,$tempreg,$breg
8441 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8442 With a constant we always use the latter case.
8444 With 64bit address space and no base register and $at usable,
8446 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8447 lui $at,<sym> (BFD_RELOC_HI16_S)
8448 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8451 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8452 If we have a base register, we want
8453 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8454 lui $at,<sym> (BFD_RELOC_HI16_S)
8455 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8459 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8461 Without $at we can't generate the optimal path for superscalar
8462 processors here since this would require two temporary registers.
8463 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8464 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8466 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8468 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8469 If we have a base register, we want
8470 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8471 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8473 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8475 daddu $tempreg,$tempreg,$breg
8476 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8478 For GP relative symbols in 64bit address space we can use
8479 the same sequence as in 32bit address space. */
8480 if (HAVE_64BIT_SYMBOLS)
8482 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8483 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8485 relax_start (offset_expr.X_add_symbol);
8488 macro_build (&offset_expr, s, fmt, treg,
8489 BFD_RELOC_GPREL16, mips_gp_register);
8493 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8494 tempreg, breg, mips_gp_register);
8495 macro_build (&offset_expr, s, fmt, treg,
8496 BFD_RELOC_GPREL16, tempreg);
8501 if (used_at == 0 && mips_opts.at)
8503 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8504 BFD_RELOC_MIPS_HIGHEST);
8505 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8507 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8508 tempreg, BFD_RELOC_MIPS_HIGHER);
8510 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8511 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8512 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8513 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8519 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8520 BFD_RELOC_MIPS_HIGHEST);
8521 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8522 tempreg, BFD_RELOC_MIPS_HIGHER);
8523 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8524 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8525 tempreg, BFD_RELOC_HI16_S);
8526 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
8528 macro_build (NULL, "daddu", "d,v,t",
8529 tempreg, tempreg, breg);
8530 macro_build (&offset_expr, s, fmt, treg,
8531 BFD_RELOC_LO16, tempreg);
8534 if (mips_relax.sequence)
8541 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8542 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8544 relax_start (offset_expr.X_add_symbol);
8545 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
8549 macro_build_lui (&offset_expr, tempreg);
8550 macro_build (&offset_expr, s, fmt, treg,
8551 BFD_RELOC_LO16, tempreg);
8552 if (mips_relax.sequence)
8557 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8558 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8560 relax_start (offset_expr.X_add_symbol);
8561 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8562 tempreg, breg, mips_gp_register);
8563 macro_build (&offset_expr, s, fmt, treg,
8564 BFD_RELOC_GPREL16, tempreg);
8567 macro_build_lui (&offset_expr, tempreg);
8568 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8569 tempreg, tempreg, breg);
8570 macro_build (&offset_expr, s, fmt, treg,
8571 BFD_RELOC_LO16, tempreg);
8572 if (mips_relax.sequence)
8576 else if (!mips_big_got)
8578 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
8580 /* If this is a reference to an external symbol, we want
8581 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8583 <op> $treg,0($tempreg)
8585 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8587 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8588 <op> $treg,0($tempreg)
8591 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8592 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
8594 If there is a base register, we add it to $tempreg before
8595 the <op>. If there is a constant, we stick it in the
8596 <op> instruction. We don't handle constants larger than
8597 16 bits, because we have no way to load the upper 16 bits
8598 (actually, we could handle them for the subset of cases
8599 in which we are not using $at). */
8600 gas_assert (offset_expr.X_op == O_symbol);
8603 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8604 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8606 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8607 tempreg, tempreg, breg);
8608 macro_build (&offset_expr, s, fmt, treg,
8609 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8612 expr1.X_add_number = offset_expr.X_add_number;
8613 offset_expr.X_add_number = 0;
8614 if (expr1.X_add_number < -0x8000
8615 || expr1.X_add_number >= 0x8000)
8616 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8617 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8618 lw_reloc_type, mips_gp_register);
8620 relax_start (offset_expr.X_add_symbol);
8622 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8623 tempreg, BFD_RELOC_LO16);
8626 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8627 tempreg, tempreg, breg);
8628 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8630 else if (mips_big_got && !HAVE_NEWABI)
8634 /* If this is a reference to an external symbol, we want
8635 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8636 addu $tempreg,$tempreg,$gp
8637 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8638 <op> $treg,0($tempreg)
8640 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8642 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
8643 <op> $treg,0($tempreg)
8644 If there is a base register, we add it to $tempreg before
8645 the <op>. If there is a constant, we stick it in the
8646 <op> instruction. We don't handle constants larger than
8647 16 bits, because we have no way to load the upper 16 bits
8648 (actually, we could handle them for the subset of cases
8649 in which we are not using $at). */
8650 gas_assert (offset_expr.X_op == O_symbol);
8651 expr1.X_add_number = offset_expr.X_add_number;
8652 offset_expr.X_add_number = 0;
8653 if (expr1.X_add_number < -0x8000
8654 || expr1.X_add_number >= 0x8000)
8655 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8656 gpdelay = reg_needs_delay (mips_gp_register);
8657 relax_start (offset_expr.X_add_symbol);
8658 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8659 BFD_RELOC_MIPS_GOT_HI16);
8660 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8662 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8663 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8666 macro_build (NULL, "nop", "");
8667 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8668 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8670 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8671 tempreg, BFD_RELOC_LO16);
8675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8676 tempreg, tempreg, breg);
8677 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8679 else if (mips_big_got && HAVE_NEWABI)
8681 /* If this is a reference to an external symbol, we want
8682 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8683 add $tempreg,$tempreg,$gp
8684 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8685 <op> $treg,<ofst>($tempreg)
8686 Otherwise, for local symbols, we want:
8687 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8688 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
8689 gas_assert (offset_expr.X_op == O_symbol);
8690 expr1.X_add_number = offset_expr.X_add_number;
8691 offset_expr.X_add_number = 0;
8692 if (expr1.X_add_number < -0x8000
8693 || expr1.X_add_number >= 0x8000)
8694 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8695 relax_start (offset_expr.X_add_symbol);
8696 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8697 BFD_RELOC_MIPS_GOT_HI16);
8698 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
8700 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8701 BFD_RELOC_MIPS_GOT_LO16, tempreg);
8703 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8704 tempreg, tempreg, breg);
8705 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8708 offset_expr.X_add_number = expr1.X_add_number;
8709 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8710 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8712 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8713 tempreg, tempreg, breg);
8714 macro_build (&offset_expr, s, fmt, treg,
8715 BFD_RELOC_MIPS_GOT_OFST, tempreg);
8725 load_register (treg, &imm_expr, 0);
8729 load_register (treg, &imm_expr, 1);
8733 if (imm_expr.X_op == O_constant)
8736 load_register (AT, &imm_expr, 0);
8737 macro_build (NULL, "mtc1", "t,G", AT, treg);
8742 gas_assert (offset_expr.X_op == O_symbol
8743 && strcmp (segment_name (S_GET_SEGMENT
8744 (offset_expr.X_add_symbol)),
8746 && offset_expr.X_add_number == 0);
8747 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
8748 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8753 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
8754 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
8755 order 32 bits of the value and the low order 32 bits are either
8756 zero or in OFFSET_EXPR. */
8757 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8759 if (HAVE_64BIT_GPRS)
8760 load_register (treg, &imm_expr, 1);
8765 if (target_big_endian)
8777 load_register (hreg, &imm_expr, 0);
8780 if (offset_expr.X_op == O_absent)
8781 move_register (lreg, 0);
8784 gas_assert (offset_expr.X_op == O_constant);
8785 load_register (lreg, &offset_expr, 0);
8792 /* We know that sym is in the .rdata section. First we get the
8793 upper 16 bits of the address. */
8794 if (mips_pic == NO_PIC)
8796 macro_build_lui (&offset_expr, AT);
8801 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8802 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8806 /* Now we load the register(s). */
8807 if (HAVE_64BIT_GPRS)
8810 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8815 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8818 /* FIXME: How in the world do we deal with the possible
8820 offset_expr.X_add_number += 4;
8821 macro_build (&offset_expr, "lw", "t,o(b)",
8822 treg + 1, BFD_RELOC_LO16, AT);
8828 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
8829 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
8830 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
8831 the value and the low order 32 bits are either zero or in
8833 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
8836 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
8837 if (HAVE_64BIT_FPRS)
8839 gas_assert (HAVE_64BIT_GPRS);
8840 macro_build (NULL, "dmtc1", "t,S", AT, treg);
8844 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
8845 if (offset_expr.X_op == O_absent)
8846 macro_build (NULL, "mtc1", "t,G", 0, treg);
8849 gas_assert (offset_expr.X_op == O_constant);
8850 load_register (AT, &offset_expr, 0);
8851 macro_build (NULL, "mtc1", "t,G", AT, treg);
8857 gas_assert (offset_expr.X_op == O_symbol
8858 && offset_expr.X_add_number == 0);
8859 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
8860 if (strcmp (s, ".lit8") == 0)
8862 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8864 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
8865 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
8868 breg = mips_gp_register;
8869 r = BFD_RELOC_MIPS_LITERAL;
8874 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
8876 if (mips_pic != NO_PIC)
8877 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
8878 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8881 /* FIXME: This won't work for a 64 bit address. */
8882 macro_build_lui (&offset_expr, AT);
8885 if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
8887 macro_build (&offset_expr, "ldc1", "T,o(b)",
8888 treg, BFD_RELOC_LO16, AT);
8897 /* Even on a big endian machine $fn comes before $fn+1. We have
8898 to adjust when loading from memory. */
8901 gas_assert (!mips_opts.micromips);
8902 gas_assert (mips_opts.isa == ISA_MIPS1);
8903 macro_build (&offset_expr, "lwc1", "T,o(b)",
8904 target_big_endian ? treg + 1 : treg, r, breg);
8905 /* FIXME: A possible overflow which I don't know how to deal
8907 offset_expr.X_add_number += 4;
8908 macro_build (&offset_expr, "lwc1", "T,o(b)",
8909 target_big_endian ? treg : treg + 1, r, breg);
8913 gas_assert (!mips_opts.micromips);
8914 gas_assert (mips_opts.isa == ISA_MIPS1);
8915 /* Even on a big endian machine $fn comes before $fn+1. We have
8916 to adjust when storing to memory. */
8917 macro_build (&offset_expr, "swc1", "T,o(b)",
8918 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
8919 offset_expr.X_add_number += 4;
8920 macro_build (&offset_expr, "swc1", "T,o(b)",
8921 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
8925 gas_assert (!mips_opts.micromips);
8927 * The MIPS assembler seems to check for X_add_number not
8928 * being double aligned and generating:
8931 * addiu at,at,%lo(foo+1)
8934 * But, the resulting address is the same after relocation so why
8935 * generate the extra instruction?
8937 /* Itbl support may require additional care here. */
8940 if (mips_opts.isa != ISA_MIPS1)
8949 gas_assert (!mips_opts.micromips);
8950 /* Itbl support may require additional care here. */
8953 if (mips_opts.isa != ISA_MIPS1)
8963 if (HAVE_64BIT_GPRS)
8973 if (HAVE_64BIT_GPRS)
8981 if (offset_expr.X_op != O_symbol
8982 && offset_expr.X_op != O_constant)
8984 as_bad (_("Expression too complex"));
8985 offset_expr.X_op = O_constant;
8988 if (HAVE_32BIT_ADDRESSES
8989 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8993 sprintf_vma (value, offset_expr.X_add_number);
8994 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8997 /* Even on a big endian machine $fn comes before $fn+1. We have
8998 to adjust when loading from memory. We set coproc if we must
8999 load $fn+1 first. */
9000 /* Itbl support may require additional care here. */
9001 if (!target_big_endian)
9004 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9006 /* If this is a reference to a GP relative symbol, we want
9007 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9008 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9009 If we have a base register, we use this
9011 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9012 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9013 If this is not a GP relative symbol, we want
9014 lui $at,<sym> (BFD_RELOC_HI16_S)
9015 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9016 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9017 If there is a base register, we add it to $at after the
9018 lui instruction. If there is a constant, we always use
9020 if (offset_expr.X_op == O_symbol
9021 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9022 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9024 relax_start (offset_expr.X_add_symbol);
9027 tempreg = mips_gp_register;
9031 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9032 AT, breg, mips_gp_register);
9037 /* Itbl support may require additional care here. */
9038 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9039 BFD_RELOC_GPREL16, tempreg);
9040 offset_expr.X_add_number += 4;
9042 /* Set mips_optimize to 2 to avoid inserting an
9044 hold_mips_optimize = mips_optimize;
9046 /* Itbl support may require additional care here. */
9047 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9048 BFD_RELOC_GPREL16, tempreg);
9049 mips_optimize = hold_mips_optimize;
9053 offset_expr.X_add_number -= 4;
9056 macro_build_lui (&offset_expr, AT);
9058 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9059 /* Itbl support may require additional care here. */
9060 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9061 BFD_RELOC_LO16, AT);
9062 /* FIXME: How do we handle overflow here? */
9063 offset_expr.X_add_number += 4;
9064 /* Itbl support may require additional care here. */
9065 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9066 BFD_RELOC_LO16, AT);
9067 if (mips_relax.sequence)
9070 else if (!mips_big_got)
9072 /* If this is a reference to an external symbol, we want
9073 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9078 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9080 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9081 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9082 If there is a base register we add it to $at before the
9083 lwc1 instructions. If there is a constant we include it
9084 in the lwc1 instructions. */
9086 expr1.X_add_number = offset_expr.X_add_number;
9087 if (expr1.X_add_number < -0x8000
9088 || expr1.X_add_number >= 0x8000 - 4)
9089 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9090 load_got_offset (AT, &offset_expr);
9093 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9095 /* Set mips_optimize to 2 to avoid inserting an undesired
9097 hold_mips_optimize = mips_optimize;
9100 /* Itbl support may require additional care here. */
9101 relax_start (offset_expr.X_add_symbol);
9102 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9103 BFD_RELOC_LO16, AT);
9104 expr1.X_add_number += 4;
9105 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9106 BFD_RELOC_LO16, AT);
9108 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9109 BFD_RELOC_LO16, AT);
9110 offset_expr.X_add_number += 4;
9111 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9112 BFD_RELOC_LO16, AT);
9115 mips_optimize = hold_mips_optimize;
9117 else if (mips_big_got)
9121 /* If this is a reference to an external symbol, we want
9122 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9124 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9129 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9131 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9132 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9133 If there is a base register we add it to $at before the
9134 lwc1 instructions. If there is a constant we include it
9135 in the lwc1 instructions. */
9137 expr1.X_add_number = offset_expr.X_add_number;
9138 offset_expr.X_add_number = 0;
9139 if (expr1.X_add_number < -0x8000
9140 || expr1.X_add_number >= 0x8000 - 4)
9141 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9142 gpdelay = reg_needs_delay (mips_gp_register);
9143 relax_start (offset_expr.X_add_symbol);
9144 macro_build (&offset_expr, "lui", LUI_FMT,
9145 AT, BFD_RELOC_MIPS_GOT_HI16);
9146 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9147 AT, AT, mips_gp_register);
9148 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9149 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9153 /* Itbl support may require additional care here. */
9154 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9155 BFD_RELOC_LO16, AT);
9156 expr1.X_add_number += 4;
9158 /* Set mips_optimize to 2 to avoid inserting an undesired
9160 hold_mips_optimize = mips_optimize;
9162 /* Itbl support may require additional care here. */
9163 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9164 BFD_RELOC_LO16, AT);
9165 mips_optimize = hold_mips_optimize;
9166 expr1.X_add_number -= 4;
9169 offset_expr.X_add_number = expr1.X_add_number;
9171 macro_build (NULL, "nop", "");
9172 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9173 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9176 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9177 /* Itbl support may require additional care here. */
9178 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9179 BFD_RELOC_LO16, AT);
9180 offset_expr.X_add_number += 4;
9182 /* Set mips_optimize to 2 to avoid inserting an undesired
9184 hold_mips_optimize = mips_optimize;
9186 /* Itbl support may require additional care here. */
9187 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9188 BFD_RELOC_LO16, AT);
9189 mips_optimize = hold_mips_optimize;
9198 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9201 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9203 macro_build (&offset_expr, s, "t,o(b)", treg,
9204 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9206 if (!HAVE_64BIT_GPRS)
9208 offset_expr.X_add_number += 4;
9209 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9210 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9231 /* New code added to support COPZ instructions.
9232 This code builds table entries out of the macros in mip_opcodes.
9233 R4000 uses interlocks to handle coproc delays.
9234 Other chips (like the R3000) require nops to be inserted for delays.
9236 FIXME: Currently, we require that the user handle delays.
9237 In order to fill delay slots for non-interlocked chips,
9238 we must have a way to specify delays based on the coprocessor.
9239 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9240 What are the side-effects of the cop instruction?
9241 What cache support might we have and what are its effects?
9242 Both coprocessor & memory require delays. how long???
9243 What registers are read/set/modified?
9245 If an itbl is provided to interpret cop instructions,
9246 this knowledge can be encoded in the itbl spec. */
9260 gas_assert (!mips_opts.micromips);
9261 /* For now we just do C (same as Cz). The parameter will be
9262 stored in insn_opcode by mips_ip. */
9263 macro_build (NULL, s, "C", ip->insn_opcode);
9267 move_register (dreg, sreg);
9273 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9274 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9280 /* The MIPS assembler some times generates shifts and adds. I'm
9281 not trying to be that fancy. GCC should do this for us
9284 load_register (AT, &imm_expr, dbl);
9285 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9286 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9302 load_register (AT, &imm_expr, dbl);
9303 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9304 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9305 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9306 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9308 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9311 if (mips_opts.micromips)
9312 micromips_label_expr (&label_expr);
9314 label_expr.X_add_number = 8;
9315 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9316 macro_build (NULL, "nop", "");
9317 macro_build (NULL, "break", BRK_FMT, 6);
9318 if (mips_opts.micromips)
9319 micromips_add_label ();
9322 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9338 load_register (AT, &imm_expr, dbl);
9339 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9340 sreg, imm ? AT : treg);
9341 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9342 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9344 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9347 if (mips_opts.micromips)
9348 micromips_label_expr (&label_expr);
9350 label_expr.X_add_number = 8;
9351 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9352 macro_build (NULL, "nop", "");
9353 macro_build (NULL, "break", BRK_FMT, 6);
9354 if (mips_opts.micromips)
9355 micromips_add_label ();
9361 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9372 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9373 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9377 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9378 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9379 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9380 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9384 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9395 macro_build (NULL, "negu", "d,w", tempreg, treg);
9396 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9400 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9401 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9402 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9403 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9412 if (imm_expr.X_op != O_constant)
9413 as_bad (_("Improper rotate count"));
9414 rot = imm_expr.X_add_number & 0x3f;
9415 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9417 rot = (64 - rot) & 0x3f;
9419 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9421 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9426 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9429 l = (rot < 0x20) ? "dsll" : "dsll32";
9430 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9433 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9434 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9435 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9443 if (imm_expr.X_op != O_constant)
9444 as_bad (_("Improper rotate count"));
9445 rot = imm_expr.X_add_number & 0x1f;
9446 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9448 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9453 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9457 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9458 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9459 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9464 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9466 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9470 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9471 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9472 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9473 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9477 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9479 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9483 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9484 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9485 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9486 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9495 if (imm_expr.X_op != O_constant)
9496 as_bad (_("Improper rotate count"));
9497 rot = imm_expr.X_add_number & 0x3f;
9498 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9501 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9503 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9508 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9511 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
9512 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
9515 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
9516 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9517 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9525 if (imm_expr.X_op != O_constant)
9526 as_bad (_("Improper rotate count"));
9527 rot = imm_expr.X_add_number & 0x1f;
9528 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9530 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
9535 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9539 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
9540 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9541 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9547 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
9549 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9552 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9553 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9558 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9560 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9565 as_warn (_("Instruction %s: result is always false"),
9567 move_register (dreg, 0);
9570 if (CPU_HAS_SEQ (mips_opts.arch)
9571 && -512 <= imm_expr.X_add_number
9572 && imm_expr.X_add_number < 512)
9574 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
9575 (int) imm_expr.X_add_number);
9578 if (imm_expr.X_op == O_constant
9579 && imm_expr.X_add_number >= 0
9580 && imm_expr.X_add_number < 0x10000)
9582 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9584 else if (imm_expr.X_op == O_constant
9585 && imm_expr.X_add_number > -0x8000
9586 && imm_expr.X_add_number < 0)
9588 imm_expr.X_add_number = -imm_expr.X_add_number;
9589 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9590 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9592 else if (CPU_HAS_SEQ (mips_opts.arch))
9595 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9596 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
9601 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9602 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9605 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
9608 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
9614 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
9615 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9618 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
9620 if (imm_expr.X_op == O_constant
9621 && imm_expr.X_add_number >= -0x8000
9622 && imm_expr.X_add_number < 0x8000)
9624 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
9625 dreg, sreg, BFD_RELOC_LO16);
9629 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9630 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
9634 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9637 case M_SGT: /* sreg > treg <==> treg < sreg */
9643 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9646 case M_SGT_I: /* sreg > I <==> I < sreg */
9653 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9654 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9657 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
9663 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
9664 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9667 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
9674 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9675 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
9676 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
9680 if (imm_expr.X_op == O_constant
9681 && imm_expr.X_add_number >= -0x8000
9682 && imm_expr.X_add_number < 0x8000)
9684 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9688 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9689 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
9693 if (imm_expr.X_op == O_constant
9694 && imm_expr.X_add_number >= -0x8000
9695 && imm_expr.X_add_number < 0x8000)
9697 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
9702 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9703 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
9708 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
9710 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9713 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
9714 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9719 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9721 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
9726 as_warn (_("Instruction %s: result is always true"),
9728 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
9729 dreg, 0, BFD_RELOC_LO16);
9732 if (CPU_HAS_SEQ (mips_opts.arch)
9733 && -512 <= imm_expr.X_add_number
9734 && imm_expr.X_add_number < 512)
9736 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
9737 (int) imm_expr.X_add_number);
9740 if (imm_expr.X_op == O_constant
9741 && imm_expr.X_add_number >= 0
9742 && imm_expr.X_add_number < 0x10000)
9744 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
9746 else if (imm_expr.X_op == O_constant
9747 && imm_expr.X_add_number > -0x8000
9748 && imm_expr.X_add_number < 0)
9750 imm_expr.X_add_number = -imm_expr.X_add_number;
9751 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
9752 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9754 else if (CPU_HAS_SEQ (mips_opts.arch))
9757 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9758 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
9763 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9764 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
9767 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
9782 if (!mips_opts.micromips)
9784 if (imm_expr.X_op == O_constant
9785 && imm_expr.X_add_number > -0x200
9786 && imm_expr.X_add_number <= 0x200)
9788 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
9797 if (imm_expr.X_op == O_constant
9798 && imm_expr.X_add_number > -0x8000
9799 && imm_expr.X_add_number <= 0x8000)
9801 imm_expr.X_add_number = -imm_expr.X_add_number;
9802 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
9807 load_register (AT, &imm_expr, dbl);
9808 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
9830 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9831 macro_build (NULL, s, "s,t", sreg, AT);
9836 gas_assert (!mips_opts.micromips);
9837 gas_assert (mips_opts.isa == ISA_MIPS1);
9839 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
9840 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
9843 * Is the double cfc1 instruction a bug in the mips assembler;
9844 * or is there a reason for it?
9847 macro_build (NULL, "cfc1", "t,G", treg, RA);
9848 macro_build (NULL, "cfc1", "t,G", treg, RA);
9849 macro_build (NULL, "nop", "");
9850 expr1.X_add_number = 3;
9851 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
9852 expr1.X_add_number = 2;
9853 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
9854 macro_build (NULL, "ctc1", "t,G", AT, RA);
9855 macro_build (NULL, "nop", "");
9856 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
9858 macro_build (NULL, "ctc1", "t,G", treg, RA);
9859 macro_build (NULL, "nop", "");
9882 off12 = mips_opts.micromips;
9890 off12 = mips_opts.micromips;
9906 off12 = mips_opts.micromips;
9915 off12 = mips_opts.micromips;
9920 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
9921 as_bad (_("Operand overflow"));
9924 expr1.X_add_number = 0;
9929 load_address (tempreg, ep, &used_at);
9931 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9932 tempreg, tempreg, breg);
9938 && (offset_expr.X_op != O_constant
9939 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
9940 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
9944 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
9945 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9950 else if (!ust && treg == breg)
9961 if (!target_big_endian)
9962 ep->X_add_number += off;
9964 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9966 macro_build (NULL, s, "t,~(b)",
9967 tempreg, (unsigned long) ep->X_add_number, breg);
9969 if (!target_big_endian)
9970 ep->X_add_number -= off;
9972 ep->X_add_number += off;
9974 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9976 macro_build (NULL, s2, "t,~(b)",
9977 tempreg, (unsigned long) ep->X_add_number, breg);
9979 /* If necessary, move the result in tempreg to the final destination. */
9980 if (!ust && treg != tempreg)
9982 /* Protect second load's delay slot. */
9984 move_register (treg, tempreg);
9990 if (target_big_endian == ust)
9991 ep->X_add_number += off;
9992 tempreg = ust || ab ? treg : AT;
9993 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
9995 /* For halfword transfers we need a temporary register to shuffle
9996 bytes. Unfortunately for M_USH_A we have none available before
9997 the next store as AT holds the base address. We deal with this
9998 case by clobbering TREG and then restoring it as with ULH. */
9999 tempreg = ust == ab ? treg : AT;
10001 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10003 if (target_big_endian == ust)
10004 ep->X_add_number -= off;
10006 ep->X_add_number += off;
10007 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10009 /* For M_USH_A re-retrieve the LSB. */
10012 if (target_big_endian)
10013 ep->X_add_number += off;
10015 ep->X_add_number -= off;
10016 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10018 /* For ULH and M_USH_A OR the LSB in. */
10021 tempreg = !ab ? AT : treg;
10022 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10023 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10028 /* FIXME: Check if this is one of the itbl macros, since they
10029 are added dynamically. */
10030 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10033 if (!mips_opts.at && used_at)
10034 as_bad (_("Macro used $at after \".set noat\""));
10037 /* Implement macros in mips16 mode. */
10040 mips16_macro (struct mips_cl_insn *ip)
10043 int xreg, yreg, zreg, tmp;
10046 const char *s, *s2, *s3;
10048 mask = ip->insn_mo->mask;
10050 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10051 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10052 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10054 expr1.X_op = O_constant;
10055 expr1.X_op_symbol = NULL;
10056 expr1.X_add_symbol = NULL;
10057 expr1.X_add_number = 1;
10076 start_noreorder ();
10077 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10078 expr1.X_add_number = 2;
10079 macro_build (&expr1, "bnez", "x,p", yreg);
10080 macro_build (NULL, "break", "6", 7);
10082 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10083 since that causes an overflow. We should do that as well,
10084 but I don't see how to do the comparisons without a temporary
10087 macro_build (NULL, s, "x", zreg);
10106 start_noreorder ();
10107 macro_build (NULL, s, "0,x,y", xreg, yreg);
10108 expr1.X_add_number = 2;
10109 macro_build (&expr1, "bnez", "x,p", yreg);
10110 macro_build (NULL, "break", "6", 7);
10112 macro_build (NULL, s2, "x", zreg);
10118 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10119 macro_build (NULL, "mflo", "x", zreg);
10127 if (imm_expr.X_op != O_constant)
10128 as_bad (_("Unsupported large constant"));
10129 imm_expr.X_add_number = -imm_expr.X_add_number;
10130 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10134 if (imm_expr.X_op != O_constant)
10135 as_bad (_("Unsupported large constant"));
10136 imm_expr.X_add_number = -imm_expr.X_add_number;
10137 macro_build (&imm_expr, "addiu", "x,k", xreg);
10141 if (imm_expr.X_op != O_constant)
10142 as_bad (_("Unsupported large constant"));
10143 imm_expr.X_add_number = -imm_expr.X_add_number;
10144 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10166 goto do_reverse_branch;
10170 goto do_reverse_branch;
10182 goto do_reverse_branch;
10193 macro_build (NULL, s, "x,y", xreg, yreg);
10194 macro_build (&offset_expr, s2, "p");
10221 goto do_addone_branch_i;
10226 goto do_addone_branch_i;
10241 goto do_addone_branch_i;
10247 do_addone_branch_i:
10248 if (imm_expr.X_op != O_constant)
10249 as_bad (_("Unsupported large constant"));
10250 ++imm_expr.X_add_number;
10253 macro_build (&imm_expr, s, s3, xreg);
10254 macro_build (&offset_expr, s2, "p");
10258 expr1.X_add_number = 0;
10259 macro_build (&expr1, "slti", "x,8", yreg);
10261 move_register (xreg, yreg);
10262 expr1.X_add_number = 2;
10263 macro_build (&expr1, "bteqz", "p");
10264 macro_build (NULL, "neg", "x,w", xreg, xreg);
10268 /* For consistency checking, verify that all bits are specified either
10269 by the match/mask part of the instruction definition, or by the
10272 validate_mips_insn (const struct mips_opcode *opc)
10274 const char *p = opc->args;
10276 unsigned long used_bits = opc->mask;
10278 if ((used_bits & opc->match) != opc->match)
10280 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10281 opc->name, opc->args);
10284 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10294 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10295 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10296 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10297 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10298 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10299 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10300 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10301 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10302 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10303 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10304 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10305 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10306 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10308 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10309 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10310 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10311 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10312 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10313 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10314 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10315 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10316 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10317 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10318 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10319 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10320 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10321 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10322 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10325 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10326 c, opc->name, opc->args);
10330 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10331 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10333 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10334 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10335 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10336 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10338 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10339 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10341 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10342 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10344 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10345 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10346 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10347 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10348 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10349 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10350 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10351 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10352 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10353 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10354 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10355 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10356 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10357 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10358 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10359 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10360 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10362 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10363 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10364 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10365 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10367 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10368 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10369 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10370 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10371 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10372 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10373 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10374 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10375 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10378 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10379 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10380 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10381 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10382 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10385 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10386 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10387 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10388 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10389 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10390 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10391 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10392 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10393 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10394 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10395 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10396 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10397 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10398 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10399 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10400 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10401 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10402 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10403 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10404 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10406 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10407 c, opc->name, opc->args);
10411 if (used_bits != 0xffffffff)
10413 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10414 ~used_bits & 0xffffffff, opc->name, opc->args);
10420 /* For consistency checking, verify that the length implied matches the
10421 major opcode and that all bits are specified either by the match/mask
10422 part of the instruction definition, or by the operand list. */
10425 validate_micromips_insn (const struct mips_opcode *opc)
10427 unsigned long match = opc->match;
10428 unsigned long mask = opc->mask;
10429 const char *p = opc->args;
10430 unsigned long insn_bits;
10431 unsigned long used_bits;
10432 unsigned long major;
10433 unsigned int length;
10437 if ((mask & match) != match)
10439 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10440 opc->name, opc->args);
10443 length = micromips_insn_length (opc);
10444 if (length != 2 && length != 4)
10446 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10447 "%s %s"), length, opc->name, opc->args);
10450 major = match >> (10 + 8 * (length - 2));
10451 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10452 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10454 as_bad (_("Internal error: bad microMIPS opcode "
10455 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10459 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10460 insn_bits = 1 << 4 * length;
10461 insn_bits <<= 4 * length;
10464 #define USE_BITS(field) \
10465 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10476 case 'A': USE_BITS (EXTLSB); break;
10477 case 'B': USE_BITS (INSMSB); break;
10478 case 'C': USE_BITS (EXTMSBD); break;
10479 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
10480 case 'E': USE_BITS (EXTLSB); break;
10481 case 'F': USE_BITS (INSMSB); break;
10482 case 'G': USE_BITS (EXTMSBD); break;
10483 case 'H': USE_BITS (EXTMSBD); break;
10485 as_bad (_("Internal error: bad mips opcode "
10486 "(unknown extension operand type `%c%c'): %s %s"),
10487 e, c, opc->name, opc->args);
10495 case 'A': USE_BITS (IMMA); break;
10496 case 'B': USE_BITS (IMMB); break;
10497 case 'C': USE_BITS (IMMC); break;
10498 case 'D': USE_BITS (IMMD); break;
10499 case 'E': USE_BITS (IMME); break;
10500 case 'F': USE_BITS (IMMF); break;
10501 case 'G': USE_BITS (IMMG); break;
10502 case 'H': USE_BITS (IMMH); break;
10503 case 'I': USE_BITS (IMMI); break;
10504 case 'J': USE_BITS (IMMJ); break;
10505 case 'L': USE_BITS (IMML); break;
10506 case 'M': USE_BITS (IMMM); break;
10507 case 'N': USE_BITS (IMMN); break;
10508 case 'O': USE_BITS (IMMO); break;
10509 case 'P': USE_BITS (IMMP); break;
10510 case 'Q': USE_BITS (IMMQ); break;
10511 case 'U': USE_BITS (IMMU); break;
10512 case 'W': USE_BITS (IMMW); break;
10513 case 'X': USE_BITS (IMMX); break;
10514 case 'Y': USE_BITS (IMMY); break;
10517 case 'b': USE_BITS (MB); break;
10518 case 'c': USE_BITS (MC); break;
10519 case 'd': USE_BITS (MD); break;
10520 case 'e': USE_BITS (ME); break;
10521 case 'f': USE_BITS (MF); break;
10522 case 'g': USE_BITS (MG); break;
10523 case 'h': USE_BITS (MH); break;
10524 case 'i': USE_BITS (MI); break;
10525 case 'j': USE_BITS (MJ); break;
10526 case 'l': USE_BITS (ML); break;
10527 case 'm': USE_BITS (MM); break;
10528 case 'n': USE_BITS (MN); break;
10529 case 'p': USE_BITS (MP); break;
10530 case 'q': USE_BITS (MQ); break;
10538 as_bad (_("Internal error: bad mips opcode "
10539 "(unknown extension operand type `%c%c'): %s %s"),
10540 e, c, opc->name, opc->args);
10544 case '.': USE_BITS (OFFSET10); break;
10545 case '1': USE_BITS (STYPE); break;
10546 case '2': USE_BITS (BP); break;
10547 case '3': USE_BITS (SA3); break;
10548 case '4': USE_BITS (SA4); break;
10549 case '5': USE_BITS (IMM8); break;
10550 case '6': USE_BITS (RS); break;
10551 case '7': USE_BITS (DSPACC); break;
10552 case '8': USE_BITS (WRDSP); break;
10553 case '0': USE_BITS (DSPSFT); break;
10554 case '<': USE_BITS (SHAMT); break;
10555 case '>': USE_BITS (SHAMT); break;
10556 case '@': USE_BITS (IMM10); break;
10557 case 'B': USE_BITS (CODE10); break;
10558 case 'C': USE_BITS (COPZ); break;
10559 case 'D': USE_BITS (FD); break;
10560 case 'E': USE_BITS (RT); break;
10561 case 'G': USE_BITS (RS); break;
10562 case 'H': USE_BITS (SEL); break;
10563 case 'K': USE_BITS (RS); break;
10564 case 'M': USE_BITS (CCC); break;
10565 case 'N': USE_BITS (BCC); break;
10566 case 'R': USE_BITS (FR); break;
10567 case 'S': USE_BITS (FS); break;
10568 case 'T': USE_BITS (FT); break;
10569 case 'V': USE_BITS (FS); break;
10570 case '\\': USE_BITS (3BITPOS); break;
10571 case '^': USE_BITS (RD); break;
10572 case 'a': USE_BITS (TARGET); break;
10573 case 'b': USE_BITS (RS); break;
10574 case 'c': USE_BITS (CODE); break;
10575 case 'd': USE_BITS (RD); break;
10576 case 'h': USE_BITS (PREFX); break;
10577 case 'i': USE_BITS (IMMEDIATE); break;
10578 case 'j': USE_BITS (DELTA); break;
10579 case 'k': USE_BITS (CACHE); break;
10580 case 'n': USE_BITS (RT); break;
10581 case 'o': USE_BITS (DELTA); break;
10582 case 'p': USE_BITS (DELTA); break;
10583 case 'q': USE_BITS (CODE2); break;
10584 case 'r': USE_BITS (RS); break;
10585 case 's': USE_BITS (RS); break;
10586 case 't': USE_BITS (RT); break;
10587 case 'u': USE_BITS (IMMEDIATE); break;
10588 case 'v': USE_BITS (RS); break;
10589 case 'w': USE_BITS (RT); break;
10590 case 'y': USE_BITS (RS3); break;
10592 case '|': USE_BITS (TRAP); break;
10593 case '~': USE_BITS (OFFSET12); break;
10595 as_bad (_("Internal error: bad microMIPS opcode "
10596 "(unknown operand type `%c'): %s %s"),
10597 c, opc->name, opc->args);
10601 if (used_bits != insn_bits)
10603 if (~used_bits & insn_bits)
10604 as_bad (_("Internal error: bad microMIPS opcode "
10605 "(bits 0x%lx undefined): %s %s"),
10606 ~used_bits & insn_bits, opc->name, opc->args);
10607 if (used_bits & ~insn_bits)
10608 as_bad (_("Internal error: bad microMIPS opcode "
10609 "(bits 0x%lx defined): %s %s"),
10610 used_bits & ~insn_bits, opc->name, opc->args);
10616 /* UDI immediates. */
10617 struct mips_immed {
10619 unsigned int shift;
10620 unsigned long mask;
10624 static const struct mips_immed mips_immed[] = {
10625 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
10626 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
10627 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
10628 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
10632 /* Check whether an odd floating-point register is allowed. */
10634 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
10636 const char *s = insn->name;
10638 if (insn->pinfo == INSN_MACRO)
10639 /* Let a macro pass, we'll catch it later when it is expanded. */
10642 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
10644 /* Allow odd registers for single-precision ops. */
10645 switch (insn->pinfo & (FP_S | FP_D))
10649 return 1; /* both single precision - ok */
10651 return 0; /* both double precision - fail */
10656 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
10657 s = strchr (insn->name, '.');
10659 s = s != NULL ? strchr (s + 1, '.') : NULL;
10660 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
10663 /* Single-precision coprocessor loads and moves are OK too. */
10664 if ((insn->pinfo & FP_S)
10665 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
10666 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
10672 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
10673 taking bits from BIT up. */
10675 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
10677 return (ep->X_op == O_constant
10678 && (ep->X_add_number & ((1 << bit) - 1)) == 0
10679 && ep->X_add_number >= min << bit
10680 && ep->X_add_number < max << bit);
10683 /* This routine assembles an instruction into its binary format. As a
10684 side effect, it sets one of the global variables imm_reloc or
10685 offset_reloc to the type of relocation to do if one of the operands
10686 is an address expression. */
10689 mips_ip (char *str, struct mips_cl_insn *ip)
10691 bfd_boolean wrong_delay_slot_insns = FALSE;
10692 bfd_boolean need_delay_slot_ok = TRUE;
10693 struct mips_opcode *firstinsn = NULL;
10694 const struct mips_opcode *past;
10695 struct hash_control *hash;
10699 struct mips_opcode *insn;
10701 unsigned int regno;
10702 unsigned int lastregno;
10703 unsigned int destregno = 0;
10704 unsigned int lastpos = 0;
10705 unsigned int limlo, limhi;
10707 offsetT min_range, max_range;
10711 unsigned int rtype;
10717 if (mips_opts.micromips)
10719 hash = micromips_op_hash;
10720 past = µmips_opcodes[bfd_micromips_num_opcodes];
10725 past = &mips_opcodes[NUMOPCODES];
10727 forced_insn_length = 0;
10730 /* We first try to match an instruction up to a space or to the end. */
10731 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
10734 /* Make a copy of the instruction so that we can fiddle with it. */
10735 name = alloca (end + 1);
10736 memcpy (name, str, end);
10741 insn = (struct mips_opcode *) hash_find (hash, name);
10743 if (insn != NULL || !mips_opts.micromips)
10745 if (forced_insn_length)
10748 /* See if there's an instruction size override suffix,
10749 either `16' or `32', at the end of the mnemonic proper,
10750 that defines the operation, i.e. before the first `.'
10751 character if any. Strip it and retry. */
10752 dot = strchr (name, '.');
10753 opend = dot != NULL ? dot - name : end;
10756 if (name[opend - 2] == '1' && name[opend - 1] == '6')
10757 forced_insn_length = 2;
10758 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
10759 forced_insn_length = 4;
10762 memcpy (name + opend - 2, name + opend, end - opend + 1);
10766 insn_error = _("Unrecognized opcode");
10770 /* For microMIPS instructions placed in a fixed-length branch delay slot
10771 we make up to two passes over the relevant fragment of the opcode
10772 table. First we try instructions that meet the delay slot's length
10773 requirement. If none matched, then we retry with the remaining ones
10774 and if one matches, then we use it and then issue an appropriate
10775 warning later on. */
10776 argsStart = s = str + end;
10779 bfd_boolean delay_slot_ok;
10780 bfd_boolean size_ok;
10783 gas_assert (strcmp (insn->name, name) == 0);
10785 ok = is_opcode_valid (insn);
10786 size_ok = is_size_valid (insn);
10787 delay_slot_ok = is_delay_slot_valid (insn);
10788 if (!delay_slot_ok && !wrong_delay_slot_insns)
10791 wrong_delay_slot_insns = TRUE;
10793 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
10795 static char buf[256];
10797 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
10802 if (wrong_delay_slot_insns && need_delay_slot_ok)
10804 gas_assert (firstinsn);
10805 need_delay_slot_ok = FALSE;
10815 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
10816 mips_cpu_info_from_arch (mips_opts.arch)->name,
10817 mips_cpu_info_from_isa (mips_opts.isa)->name);
10819 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
10820 8 * forced_insn_length);
10826 create_insn (ip, insn);
10829 lastregno = 0xffffffff;
10830 for (args = insn->args;; ++args)
10834 s += strspn (s, " \t");
10838 case '\0': /* end of args */
10844 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
10845 code) or 14 (for microMIPS code). */
10846 my_getExpression (&imm_expr, s);
10847 check_absolute_expr (ip, &imm_expr);
10848 if ((unsigned long) imm_expr.X_add_number != 1
10849 && (unsigned long) imm_expr.X_add_number != 3)
10851 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
10852 (unsigned long) imm_expr.X_add_number);
10854 INSERT_OPERAND (mips_opts.micromips,
10855 BP, *ip, imm_expr.X_add_number);
10856 imm_expr.X_op = O_absent;
10861 /* DSP 3-bit unsigned immediate in bit 13 (for standard MIPS
10862 code) or 21 (for microMIPS code). */
10864 unsigned long mask = (mips_opts.micromips
10865 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
10867 my_getExpression (&imm_expr, s);
10868 check_absolute_expr (ip, &imm_expr);
10869 if ((unsigned long) imm_expr.X_add_number > mask)
10870 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10871 mask, (unsigned long) imm_expr.X_add_number);
10872 INSERT_OPERAND (mips_opts.micromips,
10873 SA3, *ip, imm_expr.X_add_number);
10874 imm_expr.X_op = O_absent;
10880 /* DSP 4-bit unsigned immediate in bit 12 (for standard MIPS
10881 code) or 21 (for microMIPS code). */
10883 unsigned long mask = (mips_opts.micromips
10884 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
10886 my_getExpression (&imm_expr, s);
10887 check_absolute_expr (ip, &imm_expr);
10888 if ((unsigned long) imm_expr.X_add_number > mask)
10889 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10890 mask, (unsigned long) imm_expr.X_add_number);
10891 INSERT_OPERAND (mips_opts.micromips,
10892 SA4, *ip, imm_expr.X_add_number);
10893 imm_expr.X_op = O_absent;
10899 /* DSP 8-bit unsigned immediate in bit 13 (for standard MIPS
10900 code) or 16 (for microMIPS code). */
10902 unsigned long mask = (mips_opts.micromips
10903 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
10905 my_getExpression (&imm_expr, s);
10906 check_absolute_expr (ip, &imm_expr);
10907 if ((unsigned long) imm_expr.X_add_number > mask)
10908 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10909 mask, (unsigned long) imm_expr.X_add_number);
10910 INSERT_OPERAND (mips_opts.micromips,
10911 IMM8, *ip, imm_expr.X_add_number);
10912 imm_expr.X_op = O_absent;
10918 /* DSP 5-bit unsigned immediate in bit 16 (for standard MIPS
10919 code) or 21 (for microMIPS code). */
10921 unsigned long mask = (mips_opts.micromips
10922 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
10924 my_getExpression (&imm_expr, s);
10925 check_absolute_expr (ip, &imm_expr);
10926 if ((unsigned long) imm_expr.X_add_number > mask)
10927 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10928 mask, (unsigned long) imm_expr.X_add_number);
10929 INSERT_OPERAND (mips_opts.micromips,
10930 RS, *ip, imm_expr.X_add_number);
10931 imm_expr.X_op = O_absent;
10936 case '7': /* Four DSP accumulators in bits 11,12. */
10937 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10938 && s[3] >= '0' && s[3] <= '3')
10940 regno = s[3] - '0';
10942 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
10946 as_bad (_("Invalid dsp acc register"));
10950 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
10951 code) or 14 (for microMIPS code). */
10953 unsigned long mask = (mips_opts.micromips
10954 ? MICROMIPSOP_MASK_WRDSP
10957 my_getExpression (&imm_expr, s);
10958 check_absolute_expr (ip, &imm_expr);
10959 if ((unsigned long) imm_expr.X_add_number > mask)
10960 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
10961 mask, (unsigned long) imm_expr.X_add_number);
10962 INSERT_OPERAND (mips_opts.micromips,
10963 WRDSP, *ip, imm_expr.X_add_number);
10964 imm_expr.X_op = O_absent;
10969 case '9': /* Four DSP accumulators in bits 21,22. */
10970 gas_assert (!mips_opts.micromips);
10971 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
10972 && s[3] >= '0' && s[3] <= '3')
10974 regno = s[3] - '0';
10976 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
10980 as_bad (_("Invalid dsp acc register"));
10984 /* DSP 6-bit signed immediate in bit 16 (for standard MIPS
10985 code) or 20 (for microMIPS code). */
10987 long mask = (mips_opts.micromips
10988 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
10990 my_getExpression (&imm_expr, s);
10991 check_absolute_expr (ip, &imm_expr);
10992 min_range = -((mask + 1) >> 1);
10993 max_range = ((mask + 1) >> 1) - 1;
10994 if (imm_expr.X_add_number < min_range
10995 || imm_expr.X_add_number > max_range)
10996 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
10997 (long) min_range, (long) max_range,
10998 (long) imm_expr.X_add_number);
10999 INSERT_OPERAND (mips_opts.micromips,
11000 DSPSFT, *ip, imm_expr.X_add_number);
11001 imm_expr.X_op = O_absent;
11006 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11007 gas_assert (!mips_opts.micromips);
11008 my_getExpression (&imm_expr, s);
11009 check_absolute_expr (ip, &imm_expr);
11010 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11012 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11014 (unsigned long) imm_expr.X_add_number);
11016 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11017 imm_expr.X_op = O_absent;
11021 case ':': /* DSP 7-bit signed immediate in bit 19. */
11022 gas_assert (!mips_opts.micromips);
11023 my_getExpression (&imm_expr, s);
11024 check_absolute_expr (ip, &imm_expr);
11025 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11026 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11027 if (imm_expr.X_add_number < min_range ||
11028 imm_expr.X_add_number > max_range)
11030 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11031 (long) min_range, (long) max_range,
11032 (long) imm_expr.X_add_number);
11034 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11035 imm_expr.X_op = O_absent;
11039 case '@': /* DSP 10-bit signed immediate in bit 16. */
11041 long mask = (mips_opts.micromips
11042 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11044 my_getExpression (&imm_expr, s);
11045 check_absolute_expr (ip, &imm_expr);
11046 min_range = -((mask + 1) >> 1);
11047 max_range = ((mask + 1) >> 1) - 1;
11048 if (imm_expr.X_add_number < min_range
11049 || imm_expr.X_add_number > max_range)
11050 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11051 (long) min_range, (long) max_range,
11052 (long) imm_expr.X_add_number);
11053 INSERT_OPERAND (mips_opts.micromips,
11054 IMM10, *ip, imm_expr.X_add_number);
11055 imm_expr.X_op = O_absent;
11060 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11061 gas_assert (mips_opts.micromips);
11062 my_getExpression (&imm_expr, s);
11063 check_absolute_expr (ip, &imm_expr);
11064 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11065 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11066 MICROMIPSOP_MASK_RD,
11067 (unsigned long) imm_expr.X_add_number);
11068 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11069 imm_expr.X_op = O_absent;
11073 case '!': /* MT usermode flag bit. */
11074 gas_assert (!mips_opts.micromips);
11075 my_getExpression (&imm_expr, s);
11076 check_absolute_expr (ip, &imm_expr);
11077 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11078 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11079 (unsigned long) imm_expr.X_add_number);
11080 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11081 imm_expr.X_op = O_absent;
11085 case '$': /* MT load high flag bit. */
11086 gas_assert (!mips_opts.micromips);
11087 my_getExpression (&imm_expr, s);
11088 check_absolute_expr (ip, &imm_expr);
11089 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11090 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11091 (unsigned long) imm_expr.X_add_number);
11092 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11093 imm_expr.X_op = O_absent;
11097 case '*': /* Four DSP accumulators in bits 18,19. */
11098 gas_assert (!mips_opts.micromips);
11099 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11100 s[3] >= '0' && s[3] <= '3')
11102 regno = s[3] - '0';
11104 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11108 as_bad (_("Invalid dsp/smartmips acc register"));
11111 case '&': /* Four DSP accumulators in bits 13,14. */
11112 gas_assert (!mips_opts.micromips);
11113 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11114 s[3] >= '0' && s[3] <= '3')
11116 regno = s[3] - '0';
11118 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11122 as_bad (_("Invalid dsp/smartmips acc register"));
11125 case '\\': /* 3-bit bit position. */
11127 unsigned long mask = (mips_opts.micromips
11128 ? MICROMIPSOP_MASK_3BITPOS
11129 : OP_MASK_3BITPOS);
11131 my_getExpression (&imm_expr, s);
11132 check_absolute_expr (ip, &imm_expr);
11133 if ((unsigned long) imm_expr.X_add_number > mask)
11134 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11136 mask, (unsigned long) imm_expr.X_add_number);
11137 INSERT_OPERAND (mips_opts.micromips,
11138 3BITPOS, *ip, imm_expr.X_add_number);
11139 imm_expr.X_op = O_absent;
11153 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11157 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11161 gas_assert (!mips_opts.micromips);
11162 INSERT_OPERAND (0, FT, *ip, lastregno);
11166 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11172 /* Handle optional base register.
11173 Either the base register is omitted or
11174 we must have a left paren. */
11175 /* This is dependent on the next operand specifier
11176 is a base register specification. */
11177 gas_assert (args[1] == 'b'
11178 || (mips_opts.micromips
11180 && (args[2] == 'l' || args[2] == 'n'
11181 || args[2] == 's' || args[2] == 'a')));
11182 if (*s == '\0' && args[1] == 'b')
11184 /* Fall through. */
11186 case ')': /* These must match exactly. */
11191 case '[': /* These must match exactly. */
11193 gas_assert (!mips_opts.micromips);
11198 case '+': /* Opcode extension character. */
11201 case '1': /* UDI immediates. */
11205 gas_assert (!mips_opts.micromips);
11207 const struct mips_immed *imm = mips_immed;
11209 while (imm->type && imm->type != *args)
11213 my_getExpression (&imm_expr, s);
11214 check_absolute_expr (ip, &imm_expr);
11215 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11217 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11218 imm->desc ? imm->desc : ip->insn_mo->name,
11219 (unsigned long) imm_expr.X_add_number,
11220 (unsigned long) imm_expr.X_add_number);
11221 imm_expr.X_add_number &= imm->mask;
11223 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11225 imm_expr.X_op = O_absent;
11230 case 'A': /* ins/ext position, becomes LSB. */
11239 my_getExpression (&imm_expr, s);
11240 check_absolute_expr (ip, &imm_expr);
11241 if ((unsigned long) imm_expr.X_add_number < limlo
11242 || (unsigned long) imm_expr.X_add_number > limhi)
11244 as_bad (_("Improper position (%lu)"),
11245 (unsigned long) imm_expr.X_add_number);
11246 imm_expr.X_add_number = limlo;
11248 lastpos = imm_expr.X_add_number;
11249 INSERT_OPERAND (mips_opts.micromips,
11250 EXTLSB, *ip, imm_expr.X_add_number);
11251 imm_expr.X_op = O_absent;
11255 case 'B': /* ins size, becomes MSB. */
11264 my_getExpression (&imm_expr, s);
11265 check_absolute_expr (ip, &imm_expr);
11266 /* Check for negative input so that small negative numbers
11267 will not succeed incorrectly. The checks against
11268 (pos+size) transitively check "size" itself,
11269 assuming that "pos" is reasonable. */
11270 if ((long) imm_expr.X_add_number < 0
11271 || ((unsigned long) imm_expr.X_add_number
11273 || ((unsigned long) imm_expr.X_add_number
11274 + lastpos) > limhi)
11276 as_bad (_("Improper insert size (%lu, position %lu)"),
11277 (unsigned long) imm_expr.X_add_number,
11278 (unsigned long) lastpos);
11279 imm_expr.X_add_number = limlo - lastpos;
11281 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11282 lastpos + imm_expr.X_add_number - 1);
11283 imm_expr.X_op = O_absent;
11287 case 'C': /* ext size, becomes MSBD. */
11300 my_getExpression (&imm_expr, s);
11301 check_absolute_expr (ip, &imm_expr);
11302 /* Check for negative input so that small negative numbers
11303 will not succeed incorrectly. The checks against
11304 (pos+size) transitively check "size" itself,
11305 assuming that "pos" is reasonable. */
11306 if ((long) imm_expr.X_add_number < 0
11307 || ((unsigned long) imm_expr.X_add_number
11309 || ((unsigned long) imm_expr.X_add_number
11310 + lastpos) > limhi)
11312 as_bad (_("Improper extract size (%lu, position %lu)"),
11313 (unsigned long) imm_expr.X_add_number,
11314 (unsigned long) lastpos);
11315 imm_expr.X_add_number = limlo - lastpos;
11317 INSERT_OPERAND (mips_opts.micromips,
11318 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11319 imm_expr.X_op = O_absent;
11324 /* +D is for disassembly only; never match. */
11328 /* "+I" is like "I", except that imm2_expr is used. */
11329 my_getExpression (&imm2_expr, s);
11330 if (imm2_expr.X_op != O_big
11331 && imm2_expr.X_op != O_constant)
11332 insn_error = _("absolute expression required");
11333 if (HAVE_32BIT_GPRS)
11334 normalize_constant_expr (&imm2_expr);
11338 case 'T': /* Coprocessor register. */
11339 gas_assert (!mips_opts.micromips);
11340 /* +T is for disassembly only; never match. */
11343 case 't': /* Coprocessor register number. */
11344 gas_assert (!mips_opts.micromips);
11345 if (s[0] == '$' && ISDIGIT (s[1]))
11355 while (ISDIGIT (*s));
11357 as_bad (_("Invalid register number (%d)"), regno);
11360 INSERT_OPERAND (0, RT, *ip, regno);
11365 as_bad (_("Invalid coprocessor 0 register number"));
11369 /* bbit[01] and bbit[01]32 bit index. Give error if index
11370 is not in the valid range. */
11371 gas_assert (!mips_opts.micromips);
11372 my_getExpression (&imm_expr, s);
11373 check_absolute_expr (ip, &imm_expr);
11374 if ((unsigned) imm_expr.X_add_number > 31)
11376 as_bad (_("Improper bit index (%lu)"),
11377 (unsigned long) imm_expr.X_add_number);
11378 imm_expr.X_add_number = 0;
11380 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11381 imm_expr.X_op = O_absent;
11386 /* bbit[01] bit index when bbit is used but we generate
11387 bbit[01]32 because the index is over 32. Move to the
11388 next candidate if index is not in the valid range. */
11389 gas_assert (!mips_opts.micromips);
11390 my_getExpression (&imm_expr, s);
11391 check_absolute_expr (ip, &imm_expr);
11392 if ((unsigned) imm_expr.X_add_number < 32
11393 || (unsigned) imm_expr.X_add_number > 63)
11395 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11396 imm_expr.X_op = O_absent;
11401 /* cins, cins32, exts and exts32 position field. Give error
11402 if it's not in the valid range. */
11403 gas_assert (!mips_opts.micromips);
11404 my_getExpression (&imm_expr, s);
11405 check_absolute_expr (ip, &imm_expr);
11406 if ((unsigned) imm_expr.X_add_number > 31)
11408 as_bad (_("Improper position (%lu)"),
11409 (unsigned long) imm_expr.X_add_number);
11410 imm_expr.X_add_number = 0;
11412 /* Make the pos explicit to simplify +S. */
11413 lastpos = imm_expr.X_add_number + 32;
11414 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11415 imm_expr.X_op = O_absent;
11420 /* cins, cins32, exts and exts32 position field. Move to
11421 the next candidate if it's not in the valid range. */
11422 gas_assert (!mips_opts.micromips);
11423 my_getExpression (&imm_expr, s);
11424 check_absolute_expr (ip, &imm_expr);
11425 if ((unsigned) imm_expr.X_add_number < 32
11426 || (unsigned) imm_expr.X_add_number > 63)
11428 lastpos = imm_expr.X_add_number;
11429 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11430 imm_expr.X_op = O_absent;
11435 /* cins and exts length-minus-one field. */
11436 gas_assert (!mips_opts.micromips);
11437 my_getExpression (&imm_expr, s);
11438 check_absolute_expr (ip, &imm_expr);
11439 if ((unsigned long) imm_expr.X_add_number > 31)
11441 as_bad (_("Improper size (%lu)"),
11442 (unsigned long) imm_expr.X_add_number);
11443 imm_expr.X_add_number = 0;
11445 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11446 imm_expr.X_op = O_absent;
11451 /* cins32/exts32 and cins/exts aliasing cint32/exts32
11452 length-minus-one field. */
11453 gas_assert (!mips_opts.micromips);
11454 my_getExpression (&imm_expr, s);
11455 check_absolute_expr (ip, &imm_expr);
11456 if ((long) imm_expr.X_add_number < 0
11457 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11459 as_bad (_("Improper size (%lu)"),
11460 (unsigned long) imm_expr.X_add_number);
11461 imm_expr.X_add_number = 0;
11463 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11464 imm_expr.X_op = O_absent;
11469 /* seqi/snei immediate field. */
11470 gas_assert (!mips_opts.micromips);
11471 my_getExpression (&imm_expr, s);
11472 check_absolute_expr (ip, &imm_expr);
11473 if ((long) imm_expr.X_add_number < -512
11474 || (long) imm_expr.X_add_number >= 512)
11476 as_bad (_("Improper immediate (%ld)"),
11477 (long) imm_expr.X_add_number);
11478 imm_expr.X_add_number = 0;
11480 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11481 imm_expr.X_op = O_absent;
11485 case 'a': /* 8-bit signed offset in bit 6 */
11486 gas_assert (!mips_opts.micromips);
11487 my_getExpression (&imm_expr, s);
11488 check_absolute_expr (ip, &imm_expr);
11489 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11490 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11491 if (imm_expr.X_add_number < min_range
11492 || imm_expr.X_add_number > max_range)
11494 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11495 (long) min_range, (long) max_range,
11496 (long) imm_expr.X_add_number);
11498 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
11499 imm_expr.X_op = O_absent;
11503 case 'b': /* 8-bit signed offset in bit 3 */
11504 gas_assert (!mips_opts.micromips);
11505 my_getExpression (&imm_expr, s);
11506 check_absolute_expr (ip, &imm_expr);
11507 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
11508 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
11509 if (imm_expr.X_add_number < min_range
11510 || imm_expr.X_add_number > max_range)
11512 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11513 (long) min_range, (long) max_range,
11514 (long) imm_expr.X_add_number);
11516 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
11517 imm_expr.X_op = O_absent;
11521 case 'c': /* 9-bit signed offset in bit 6 */
11522 gas_assert (!mips_opts.micromips);
11523 my_getExpression (&imm_expr, s);
11524 check_absolute_expr (ip, &imm_expr);
11525 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
11526 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
11527 /* We check the offset range before adjusted. */
11530 if (imm_expr.X_add_number < min_range
11531 || imm_expr.X_add_number > max_range)
11533 as_bad (_("Offset not in range %ld..%ld (%ld)"),
11534 (long) min_range, (long) max_range,
11535 (long) imm_expr.X_add_number);
11537 if (imm_expr.X_add_number & 0xf)
11539 as_bad (_("Offset not 16 bytes alignment (%ld)"),
11540 (long) imm_expr.X_add_number);
11542 /* Right shift 4 bits to adjust the offset operand. */
11543 INSERT_OPERAND (0, OFFSET_C, *ip,
11544 imm_expr.X_add_number >> 4);
11545 imm_expr.X_op = O_absent;
11550 gas_assert (!mips_opts.micromips);
11551 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
11553 if (regno == AT && mips_opts.at)
11555 if (mips_opts.at == ATREG)
11556 as_warn (_("used $at without \".set noat\""));
11558 as_warn (_("used $%u with \".set at=$%u\""),
11559 regno, mips_opts.at);
11561 INSERT_OPERAND (0, RZ, *ip, regno);
11565 gas_assert (!mips_opts.micromips);
11566 if (!reg_lookup (&s, RTYPE_FPU, ®no))
11568 INSERT_OPERAND (0, FZ, *ip, regno);
11572 as_bad (_("Internal error: bad %s opcode "
11573 "(unknown extension operand type `+%c'): %s %s"),
11574 mips_opts.micromips ? "microMIPS" : "MIPS",
11575 *args, insn->name, insn->args);
11576 /* Further processing is fruitless. */
11581 case '.': /* 10-bit offset. */
11582 gas_assert (mips_opts.micromips);
11583 case '~': /* 12-bit offset. */
11585 int shift = *args == '.' ? 9 : 11;
11588 /* Check whether there is only a single bracketed expression
11589 left. If so, it must be the base register and the
11590 constant must be zero. */
11591 if (*s == '(' && strchr (s + 1, '(') == 0)
11594 /* If this value won't fit into the offset, then go find
11595 a macro that will generate a 16- or 32-bit offset code
11597 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
11598 if ((i == 0 && (imm_expr.X_op != O_constant
11599 || imm_expr.X_add_number >= 1 << shift
11600 || imm_expr.X_add_number < -1 << shift))
11603 imm_expr.X_op = O_absent;
11607 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
11609 INSERT_OPERAND (mips_opts.micromips,
11610 OFFSET12, *ip, imm_expr.X_add_number);
11611 imm_expr.X_op = O_absent;
11616 case '<': /* must be at least one digit */
11618 * According to the manual, if the shift amount is greater
11619 * than 31 or less than 0, then the shift amount should be
11620 * mod 32. In reality the mips assembler issues an error.
11621 * We issue a warning and mask out all but the low 5 bits.
11623 my_getExpression (&imm_expr, s);
11624 check_absolute_expr (ip, &imm_expr);
11625 if ((unsigned long) imm_expr.X_add_number > 31)
11626 as_warn (_("Improper shift amount (%lu)"),
11627 (unsigned long) imm_expr.X_add_number);
11628 INSERT_OPERAND (mips_opts.micromips,
11629 SHAMT, *ip, imm_expr.X_add_number);
11630 imm_expr.X_op = O_absent;
11634 case '>': /* shift amount minus 32 */
11635 my_getExpression (&imm_expr, s);
11636 check_absolute_expr (ip, &imm_expr);
11637 if ((unsigned long) imm_expr.X_add_number < 32
11638 || (unsigned long) imm_expr.X_add_number > 63)
11640 INSERT_OPERAND (mips_opts.micromips,
11641 SHAMT, *ip, imm_expr.X_add_number - 32);
11642 imm_expr.X_op = O_absent;
11646 case 'k': /* CACHE code. */
11647 case 'h': /* PREFX code. */
11648 case '1': /* SYNC type. */
11649 my_getExpression (&imm_expr, s);
11650 check_absolute_expr (ip, &imm_expr);
11651 if ((unsigned long) imm_expr.X_add_number > 31)
11652 as_warn (_("Invalid value for `%s' (%lu)"),
11654 (unsigned long) imm_expr.X_add_number);
11658 if (mips_fix_cn63xxp1
11659 && !mips_opts.micromips
11660 && strcmp ("pref", insn->name) == 0)
11661 switch (imm_expr.X_add_number)
11670 case 31: /* These are ok. */
11673 default: /* The rest must be changed to 28. */
11674 imm_expr.X_add_number = 28;
11677 INSERT_OPERAND (mips_opts.micromips,
11678 CACHE, *ip, imm_expr.X_add_number);
11681 INSERT_OPERAND (mips_opts.micromips,
11682 PREFX, *ip, imm_expr.X_add_number);
11685 INSERT_OPERAND (mips_opts.micromips,
11686 STYPE, *ip, imm_expr.X_add_number);
11689 imm_expr.X_op = O_absent;
11693 case 'c': /* BREAK code. */
11695 unsigned long mask = (mips_opts.micromips
11696 ? MICROMIPSOP_MASK_CODE
11699 my_getExpression (&imm_expr, s);
11700 check_absolute_expr (ip, &imm_expr);
11701 if ((unsigned long) imm_expr.X_add_number > mask)
11702 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11704 mask, (unsigned long) imm_expr.X_add_number);
11705 INSERT_OPERAND (mips_opts.micromips,
11706 CODE, *ip, imm_expr.X_add_number);
11707 imm_expr.X_op = O_absent;
11712 case 'q': /* Lower BREAK code. */
11714 unsigned long mask = (mips_opts.micromips
11715 ? MICROMIPSOP_MASK_CODE2
11718 my_getExpression (&imm_expr, s);
11719 check_absolute_expr (ip, &imm_expr);
11720 if ((unsigned long) imm_expr.X_add_number > mask)
11721 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
11723 mask, (unsigned long) imm_expr.X_add_number);
11724 INSERT_OPERAND (mips_opts.micromips,
11725 CODE2, *ip, imm_expr.X_add_number);
11726 imm_expr.X_op = O_absent;
11731 case 'B': /* 20- or 10-bit syscall/break/wait code. */
11733 unsigned long mask = (mips_opts.micromips
11734 ? MICROMIPSOP_MASK_CODE10
11737 my_getExpression (&imm_expr, s);
11738 check_absolute_expr (ip, &imm_expr);
11739 if ((unsigned long) imm_expr.X_add_number > mask)
11740 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11742 mask, (unsigned long) imm_expr.X_add_number);
11743 if (mips_opts.micromips)
11744 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
11746 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
11747 imm_expr.X_op = O_absent;
11752 case 'C': /* 25- or 23-bit coprocessor code. */
11754 unsigned long mask = (mips_opts.micromips
11755 ? MICROMIPSOP_MASK_COPZ
11758 my_getExpression (&imm_expr, s);
11759 check_absolute_expr (ip, &imm_expr);
11760 if ((unsigned long) imm_expr.X_add_number > mask)
11761 as_warn (_("Coproccesor code > %u bits (%lu)"),
11762 mips_opts.micromips ? 23U : 25U,
11763 (unsigned long) imm_expr.X_add_number);
11764 INSERT_OPERAND (mips_opts.micromips,
11765 COPZ, *ip, imm_expr.X_add_number);
11766 imm_expr.X_op = O_absent;
11771 case 'J': /* 19-bit WAIT code. */
11772 gas_assert (!mips_opts.micromips);
11773 my_getExpression (&imm_expr, s);
11774 check_absolute_expr (ip, &imm_expr);
11775 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
11777 as_warn (_("Illegal 19-bit code (%lu)"),
11778 (unsigned long) imm_expr.X_add_number);
11779 imm_expr.X_add_number &= OP_MASK_CODE19;
11781 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
11782 imm_expr.X_op = O_absent;
11786 case 'P': /* Performance register. */
11787 gas_assert (!mips_opts.micromips);
11788 my_getExpression (&imm_expr, s);
11789 check_absolute_expr (ip, &imm_expr);
11790 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
11791 as_warn (_("Invalid performance register (%lu)"),
11792 (unsigned long) imm_expr.X_add_number);
11793 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
11794 imm_expr.X_op = O_absent;
11798 case 'G': /* Coprocessor destination register. */
11800 unsigned long opcode = ip->insn_opcode;
11801 unsigned long mask;
11802 unsigned int types;
11805 if (mips_opts.micromips)
11807 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
11808 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
11809 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
11813 case 0x000000fc: /* mfc0 */
11814 case 0x000002fc: /* mtc0 */
11815 case 0x580000fc: /* dmfc0 */
11816 case 0x580002fc: /* dmtc0 */
11826 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
11827 cop0 = opcode == OP_OP_COP0;
11829 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
11830 ok = reg_lookup (&s, types, ®no);
11831 if (mips_opts.micromips)
11832 INSERT_OPERAND (1, RS, *ip, regno);
11834 INSERT_OPERAND (0, RD, *ip, regno);
11843 case 'y': /* ALNV.PS source register. */
11844 gas_assert (mips_opts.micromips);
11846 case 'x': /* Ignore register name. */
11847 case 'U': /* Destination register (CLO/CLZ). */
11848 case 'g': /* Coprocessor destination register. */
11849 gas_assert (!mips_opts.micromips);
11850 case 'b': /* Base register. */
11851 case 'd': /* Destination register. */
11852 case 's': /* Source register. */
11853 case 't': /* Target register. */
11854 case 'r': /* Both target and source. */
11855 case 'v': /* Both dest and source. */
11856 case 'w': /* Both dest and target. */
11857 case 'E': /* Coprocessor target register. */
11858 case 'K': /* RDHWR destination register. */
11859 case 'z': /* Must be zero register. */
11862 if (*args == 'E' || *args == 'K')
11863 ok = reg_lookup (&s, RTYPE_NUM, ®no);
11866 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
11867 if (regno == AT && mips_opts.at)
11869 if (mips_opts.at == ATREG)
11870 as_warn (_("Used $at without \".set noat\""));
11872 as_warn (_("Used $%u with \".set at=$%u\""),
11873 regno, mips_opts.at);
11883 if (c == 'r' || c == 'v' || c == 'w')
11890 /* 'z' only matches $0. */
11891 if (c == 'z' && regno != 0)
11894 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
11896 if (regno == lastregno)
11899 = _("Source and destination must be different");
11902 if (regno == 31 && lastregno == 0xffffffff)
11905 = _("A destination register must be supplied");
11909 /* Now that we have assembled one operand, we use the args
11910 string to figure out where it goes in the instruction. */
11917 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
11921 if (mips_opts.micromips)
11922 INSERT_OPERAND (1, RS, *ip, regno);
11924 INSERT_OPERAND (0, RD, *ip, regno);
11929 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
11933 gas_assert (!mips_opts.micromips);
11934 INSERT_OPERAND (0, RD, *ip, regno);
11935 INSERT_OPERAND (0, RT, *ip, regno);
11941 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
11945 gas_assert (mips_opts.micromips);
11946 INSERT_OPERAND (1, RS3, *ip, regno);
11950 /* This case exists because on the r3000 trunc
11951 expands into a macro which requires a gp
11952 register. On the r6000 or r4000 it is
11953 assembled into a single instruction which
11954 ignores the register. Thus the insn version
11955 is MIPS_ISA2 and uses 'x', and the macro
11956 version is MIPS_ISA1 and uses 't'. */
11960 /* This case is for the div instruction, which
11961 acts differently if the destination argument
11962 is $0. This only matches $0, and is checked
11963 outside the switch. */
11973 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11977 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11982 case 'O': /* MDMX alignment immediate constant. */
11983 gas_assert (!mips_opts.micromips);
11984 my_getExpression (&imm_expr, s);
11985 check_absolute_expr (ip, &imm_expr);
11986 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
11987 as_warn (_("Improper align amount (%ld), using low bits"),
11988 (long) imm_expr.X_add_number);
11989 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
11990 imm_expr.X_op = O_absent;
11994 case 'Q': /* MDMX vector, element sel, or const. */
11997 /* MDMX Immediate. */
11998 gas_assert (!mips_opts.micromips);
11999 my_getExpression (&imm_expr, s);
12000 check_absolute_expr (ip, &imm_expr);
12001 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12002 as_warn (_("Invalid MDMX Immediate (%ld)"),
12003 (long) imm_expr.X_add_number);
12004 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12005 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12006 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12008 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12009 imm_expr.X_op = O_absent;
12013 /* Not MDMX Immediate. Fall through. */
12014 case 'X': /* MDMX destination register. */
12015 case 'Y': /* MDMX source register. */
12016 case 'Z': /* MDMX target register. */
12019 gas_assert (!mips_opts.micromips);
12020 case 'D': /* Floating point destination register. */
12021 case 'S': /* Floating point source register. */
12022 case 'T': /* Floating point target register. */
12023 case 'R': /* Floating point source register. */
12027 || (mips_opts.ase_mdmx
12028 && (ip->insn_mo->pinfo & FP_D)
12029 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12030 | INSN_COPROC_MEMORY_DELAY
12031 | INSN_LOAD_COPROC_DELAY
12032 | INSN_LOAD_MEMORY_DELAY
12033 | INSN_STORE_MEMORY))))
12034 rtype |= RTYPE_VEC;
12036 if (reg_lookup (&s, rtype, ®no))
12038 if ((regno & 1) != 0
12040 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12041 as_warn (_("Float register should be even, was %d"),
12049 if (c == 'V' || c == 'W')
12060 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12066 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12070 /* This is like 'Z', but also needs to fix the MDMX
12071 vector/scalar select bits. Note that the
12072 scalar immediate case is handled above. */
12075 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12076 int max_el = (is_qh ? 3 : 7);
12078 my_getExpression(&imm_expr, s);
12079 check_absolute_expr (ip, &imm_expr);
12081 if (imm_expr.X_add_number > max_el)
12082 as_bad (_("Bad element selector %ld"),
12083 (long) imm_expr.X_add_number);
12084 imm_expr.X_add_number &= max_el;
12085 ip->insn_opcode |= (imm_expr.X_add_number
12088 imm_expr.X_op = O_absent;
12090 as_warn (_("Expecting ']' found '%s'"), s);
12096 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12097 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12100 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12103 /* Fall through. */
12107 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12111 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12121 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12125 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12131 my_getExpression (&imm_expr, s);
12132 if (imm_expr.X_op != O_big
12133 && imm_expr.X_op != O_constant)
12134 insn_error = _("absolute expression required");
12135 if (HAVE_32BIT_GPRS)
12136 normalize_constant_expr (&imm_expr);
12141 my_getExpression (&offset_expr, s);
12142 normalize_address_expr (&offset_expr);
12143 *imm_reloc = BFD_RELOC_32;
12156 unsigned char temp[8];
12158 unsigned int length;
12163 /* These only appear as the last operand in an
12164 instruction, and every instruction that accepts
12165 them in any variant accepts them in all variants.
12166 This means we don't have to worry about backing out
12167 any changes if the instruction does not match.
12169 The difference between them is the size of the
12170 floating point constant and where it goes. For 'F'
12171 and 'L' the constant is 64 bits; for 'f' and 'l' it
12172 is 32 bits. Where the constant is placed is based
12173 on how the MIPS assembler does things:
12176 f -- immediate value
12179 The .lit4 and .lit8 sections are only used if
12180 permitted by the -G argument.
12182 The code below needs to know whether the target register
12183 is 32 or 64 bits wide. It relies on the fact 'f' and
12184 'F' are used with GPR-based instructions and 'l' and
12185 'L' are used with FPR-based instructions. */
12187 f64 = *args == 'F' || *args == 'L';
12188 using_gprs = *args == 'F' || *args == 'f';
12190 save_in = input_line_pointer;
12191 input_line_pointer = s;
12192 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12194 s = input_line_pointer;
12195 input_line_pointer = save_in;
12196 if (err != NULL && *err != '\0')
12198 as_bad (_("Bad floating point constant: %s"), err);
12199 memset (temp, '\0', sizeof temp);
12200 length = f64 ? 8 : 4;
12203 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12207 && (g_switch_value < 4
12208 || (temp[0] == 0 && temp[1] == 0)
12209 || (temp[2] == 0 && temp[3] == 0))))
12211 imm_expr.X_op = O_constant;
12212 if (!target_big_endian)
12213 imm_expr.X_add_number = bfd_getl32 (temp);
12215 imm_expr.X_add_number = bfd_getb32 (temp);
12217 else if (length > 4
12218 && !mips_disable_float_construction
12219 /* Constants can only be constructed in GPRs and
12220 copied to FPRs if the GPRs are at least as wide
12221 as the FPRs. Force the constant into memory if
12222 we are using 64-bit FPRs but the GPRs are only
12225 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12226 && ((temp[0] == 0 && temp[1] == 0)
12227 || (temp[2] == 0 && temp[3] == 0))
12228 && ((temp[4] == 0 && temp[5] == 0)
12229 || (temp[6] == 0 && temp[7] == 0)))
12231 /* The value is simple enough to load with a couple of
12232 instructions. If using 32-bit registers, set
12233 imm_expr to the high order 32 bits and offset_expr to
12234 the low order 32 bits. Otherwise, set imm_expr to
12235 the entire 64 bit constant. */
12236 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12238 imm_expr.X_op = O_constant;
12239 offset_expr.X_op = O_constant;
12240 if (!target_big_endian)
12242 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12243 offset_expr.X_add_number = bfd_getl32 (temp);
12247 imm_expr.X_add_number = bfd_getb32 (temp);
12248 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12250 if (offset_expr.X_add_number == 0)
12251 offset_expr.X_op = O_absent;
12253 else if (sizeof (imm_expr.X_add_number) > 4)
12255 imm_expr.X_op = O_constant;
12256 if (!target_big_endian)
12257 imm_expr.X_add_number = bfd_getl64 (temp);
12259 imm_expr.X_add_number = bfd_getb64 (temp);
12263 imm_expr.X_op = O_big;
12264 imm_expr.X_add_number = 4;
12265 if (!target_big_endian)
12267 generic_bignum[0] = bfd_getl16 (temp);
12268 generic_bignum[1] = bfd_getl16 (temp + 2);
12269 generic_bignum[2] = bfd_getl16 (temp + 4);
12270 generic_bignum[3] = bfd_getl16 (temp + 6);
12274 generic_bignum[0] = bfd_getb16 (temp + 6);
12275 generic_bignum[1] = bfd_getb16 (temp + 4);
12276 generic_bignum[2] = bfd_getb16 (temp + 2);
12277 generic_bignum[3] = bfd_getb16 (temp);
12283 const char *newname;
12286 /* Switch to the right section. */
12288 subseg = now_subseg;
12291 default: /* unused default case avoids warnings. */
12293 newname = RDATA_SECTION_NAME;
12294 if (g_switch_value >= 8)
12298 newname = RDATA_SECTION_NAME;
12301 gas_assert (g_switch_value >= 4);
12305 new_seg = subseg_new (newname, (subsegT) 0);
12307 bfd_set_section_flags (stdoutput, new_seg,
12312 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12313 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
12314 record_alignment (new_seg, 4);
12316 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12317 if (seg == now_seg)
12318 as_bad (_("Can't use floating point insn in this section"));
12320 /* Set the argument to the current address in the
12322 offset_expr.X_op = O_symbol;
12323 offset_expr.X_add_symbol = symbol_temp_new_now ();
12324 offset_expr.X_add_number = 0;
12326 /* Put the floating point number into the section. */
12327 p = frag_more ((int) length);
12328 memcpy (p, temp, length);
12330 /* Switch back to the original section. */
12331 subseg_set (seg, subseg);
12336 case 'i': /* 16-bit unsigned immediate. */
12337 case 'j': /* 16-bit signed immediate. */
12338 *imm_reloc = BFD_RELOC_LO16;
12339 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12342 offsetT minval, maxval;
12344 more = (insn + 1 < past
12345 && strcmp (insn->name, insn[1].name) == 0);
12347 /* If the expression was written as an unsigned number,
12348 only treat it as signed if there are no more
12352 && sizeof (imm_expr.X_add_number) <= 4
12353 && imm_expr.X_op == O_constant
12354 && imm_expr.X_add_number < 0
12355 && imm_expr.X_unsigned
12356 && HAVE_64BIT_GPRS)
12359 /* For compatibility with older assemblers, we accept
12360 0x8000-0xffff as signed 16-bit numbers when only
12361 signed numbers are allowed. */
12363 minval = 0, maxval = 0xffff;
12365 minval = -0x8000, maxval = 0x7fff;
12367 minval = -0x8000, maxval = 0xffff;
12369 if (imm_expr.X_op != O_constant
12370 || imm_expr.X_add_number < minval
12371 || imm_expr.X_add_number > maxval)
12375 if (imm_expr.X_op == O_constant
12376 || imm_expr.X_op == O_big)
12377 as_bad (_("Expression out of range"));
12383 case 'o': /* 16-bit offset. */
12384 offset_reloc[0] = BFD_RELOC_LO16;
12385 offset_reloc[1] = BFD_RELOC_UNUSED;
12386 offset_reloc[2] = BFD_RELOC_UNUSED;
12388 /* Check whether there is only a single bracketed expression
12389 left. If so, it must be the base register and the
12390 constant must be zero. */
12391 if (*s == '(' && strchr (s + 1, '(') == 0)
12393 offset_expr.X_op = O_constant;
12394 offset_expr.X_add_number = 0;
12398 /* If this value won't fit into a 16 bit offset, then go
12399 find a macro that will generate the 32 bit offset
12401 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12402 && (offset_expr.X_op != O_constant
12403 || offset_expr.X_add_number >= 0x8000
12404 || offset_expr.X_add_number < -0x8000))
12410 case 'p': /* PC-relative offset. */
12411 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12412 my_getExpression (&offset_expr, s);
12416 case 'u': /* Upper 16 bits. */
12417 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12418 && imm_expr.X_op == O_constant
12419 && (imm_expr.X_add_number < 0
12420 || imm_expr.X_add_number >= 0x10000))
12421 as_bad (_("lui expression (%lu) not in range 0..65535"),
12422 (unsigned long) imm_expr.X_add_number);
12426 case 'a': /* 26-bit address. */
12427 *offset_reloc = BFD_RELOC_MIPS_JMP;
12428 my_getExpression (&offset_expr, s);
12432 case 'N': /* 3-bit branch condition code. */
12433 case 'M': /* 3-bit compare condition code. */
12435 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12436 rtype |= RTYPE_FCC;
12437 if (!reg_lookup (&s, rtype, ®no))
12439 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12440 || strcmp (str + strlen (str) - 5, "any2f") == 0
12441 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12442 && (regno & 1) != 0)
12443 as_warn (_("Condition code register should be even for %s, "
12446 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12447 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12448 && (regno & 3) != 0)
12449 as_warn (_("Condition code register should be 0 or 4 for %s, "
12453 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12455 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12459 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
12470 while (ISDIGIT (*s));
12473 c = 8; /* Invalid sel value. */
12476 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
12477 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
12481 gas_assert (!mips_opts.micromips);
12482 /* Must be at least one digit. */
12483 my_getExpression (&imm_expr, s);
12484 check_absolute_expr (ip, &imm_expr);
12486 if ((unsigned long) imm_expr.X_add_number
12487 > (unsigned long) OP_MASK_VECBYTE)
12489 as_bad (_("bad byte vector index (%ld)"),
12490 (long) imm_expr.X_add_number);
12491 imm_expr.X_add_number = 0;
12494 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
12495 imm_expr.X_op = O_absent;
12500 gas_assert (!mips_opts.micromips);
12501 my_getExpression (&imm_expr, s);
12502 check_absolute_expr (ip, &imm_expr);
12504 if ((unsigned long) imm_expr.X_add_number
12505 > (unsigned long) OP_MASK_VECALIGN)
12507 as_bad (_("bad byte vector index (%ld)"),
12508 (long) imm_expr.X_add_number);
12509 imm_expr.X_add_number = 0;
12512 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
12513 imm_expr.X_op = O_absent;
12517 case 'm': /* Opcode extension character. */
12518 gas_assert (mips_opts.micromips);
12523 if (strncmp (s, "$pc", 3) == 0)
12551 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12552 if (regno == AT && mips_opts.at)
12554 if (mips_opts.at == ATREG)
12555 as_warn (_("Used $at without \".set noat\""));
12557 as_warn (_("Used $%u with \".set at=$%u\""),
12558 regno, mips_opts.at);
12564 gas_assert (args[1] == ',');
12570 gas_assert (args[1] == ',');
12572 continue; /* Nothing to do. */
12578 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
12580 if (regno == lastregno)
12583 = _("Source and destination must be different");
12586 if (regno == 31 && lastregno == 0xffffffff)
12589 = _("A destination register must be supplied");
12600 gas_assert (args[1] == ',');
12607 gas_assert (args[1] == ',');
12610 continue; /* Nothing to do. */
12614 /* Make sure regno is the same as lastregno. */
12615 if (c == 't' && regno != lastregno)
12618 /* Make sure regno is the same as destregno. */
12619 if (c == 'x' && regno != destregno)
12622 /* We need to save regno, before regno maps to the
12623 microMIPS register encoding. */
12633 regno = ILLEGAL_REG;
12637 regno = mips32_to_micromips_reg_b_map[regno];
12641 regno = mips32_to_micromips_reg_c_map[regno];
12645 regno = mips32_to_micromips_reg_d_map[regno];
12649 regno = mips32_to_micromips_reg_e_map[regno];
12653 regno = mips32_to_micromips_reg_f_map[regno];
12657 regno = mips32_to_micromips_reg_g_map[regno];
12661 regno = mips32_to_micromips_reg_h_map[regno];
12665 switch (EXTRACT_OPERAND (1, MI, *ip))
12670 else if (regno == 22)
12672 else if (regno == 5)
12674 else if (regno == 6)
12676 else if (regno == 7)
12679 regno = ILLEGAL_REG;
12685 else if (regno == 7)
12688 regno = ILLEGAL_REG;
12695 regno = ILLEGAL_REG;
12699 regno = ILLEGAL_REG;
12705 regno = mips32_to_micromips_reg_l_map[regno];
12709 regno = mips32_to_micromips_reg_m_map[regno];
12713 regno = mips32_to_micromips_reg_n_map[regno];
12717 regno = mips32_to_micromips_reg_q_map[regno];
12722 regno = ILLEGAL_REG;
12727 regno = ILLEGAL_REG;
12732 regno = ILLEGAL_REG;
12735 case 'j': /* Do nothing. */
12745 if (regno == ILLEGAL_REG)
12751 INSERT_OPERAND (1, MB, *ip, regno);
12755 INSERT_OPERAND (1, MC, *ip, regno);
12759 INSERT_OPERAND (1, MD, *ip, regno);
12763 INSERT_OPERAND (1, ME, *ip, regno);
12767 INSERT_OPERAND (1, MF, *ip, regno);
12771 INSERT_OPERAND (1, MG, *ip, regno);
12775 INSERT_OPERAND (1, MH, *ip, regno);
12779 INSERT_OPERAND (1, MI, *ip, regno);
12783 INSERT_OPERAND (1, MJ, *ip, regno);
12787 INSERT_OPERAND (1, ML, *ip, regno);
12791 INSERT_OPERAND (1, MM, *ip, regno);
12795 INSERT_OPERAND (1, MN, *ip, regno);
12799 INSERT_OPERAND (1, MP, *ip, regno);
12803 INSERT_OPERAND (1, MQ, *ip, regno);
12806 case 'a': /* Do nothing. */
12807 case 's': /* Do nothing. */
12808 case 't': /* Do nothing. */
12809 case 'x': /* Do nothing. */
12810 case 'y': /* Do nothing. */
12811 case 'z': /* Do nothing. */
12821 bfd_reloc_code_real_type r[3];
12825 /* Check whether there is only a single bracketed
12826 expression left. If so, it must be the base register
12827 and the constant must be zero. */
12828 if (*s == '(' && strchr (s + 1, '(') == 0)
12830 INSERT_OPERAND (1, IMMA, *ip, 0);
12834 if (my_getSmallExpression (&ep, r, s) > 0
12835 || !expr_const_in_range (&ep, -64, 64, 2))
12838 imm = ep.X_add_number >> 2;
12839 INSERT_OPERAND (1, IMMA, *ip, imm);
12846 bfd_reloc_code_real_type r[3];
12850 if (my_getSmallExpression (&ep, r, s) > 0
12851 || ep.X_op != O_constant)
12854 for (imm = 0; imm < 8; imm++)
12855 if (micromips_imm_b_map[imm] == ep.X_add_number)
12860 INSERT_OPERAND (1, IMMB, *ip, imm);
12867 bfd_reloc_code_real_type r[3];
12871 if (my_getSmallExpression (&ep, r, s) > 0
12872 || ep.X_op != O_constant)
12875 for (imm = 0; imm < 16; imm++)
12876 if (micromips_imm_c_map[imm] == ep.X_add_number)
12881 INSERT_OPERAND (1, IMMC, *ip, imm);
12886 case 'D': /* pc relative offset */
12887 case 'E': /* pc relative offset */
12888 my_getExpression (&offset_expr, s);
12889 if (offset_expr.X_op == O_register)
12892 if (!forced_insn_length)
12893 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
12895 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
12897 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
12903 bfd_reloc_code_real_type r[3];
12907 if (my_getSmallExpression (&ep, r, s) > 0
12908 || !expr_const_in_range (&ep, 0, 16, 0))
12911 imm = ep.X_add_number;
12912 INSERT_OPERAND (1, IMMF, *ip, imm);
12919 bfd_reloc_code_real_type r[3];
12923 /* Check whether there is only a single bracketed
12924 expression left. If so, it must be the base register
12925 and the constant must be zero. */
12926 if (*s == '(' && strchr (s + 1, '(') == 0)
12928 INSERT_OPERAND (1, IMMG, *ip, 0);
12932 if (my_getSmallExpression (&ep, r, s) > 0
12933 || !expr_const_in_range (&ep, -1, 15, 0))
12936 imm = ep.X_add_number & 15;
12937 INSERT_OPERAND (1, IMMG, *ip, imm);
12944 bfd_reloc_code_real_type r[3];
12948 /* Check whether there is only a single bracketed
12949 expression left. If so, it must be the base register
12950 and the constant must be zero. */
12951 if (*s == '(' && strchr (s + 1, '(') == 0)
12953 INSERT_OPERAND (1, IMMH, *ip, 0);
12957 if (my_getSmallExpression (&ep, r, s) > 0
12958 || !expr_const_in_range (&ep, 0, 16, 1))
12961 imm = ep.X_add_number >> 1;
12962 INSERT_OPERAND (1, IMMH, *ip, imm);
12969 bfd_reloc_code_real_type r[3];
12973 if (my_getSmallExpression (&ep, r, s) > 0
12974 || !expr_const_in_range (&ep, -1, 127, 0))
12977 imm = ep.X_add_number & 127;
12978 INSERT_OPERAND (1, IMMI, *ip, imm);
12985 bfd_reloc_code_real_type r[3];
12989 /* Check whether there is only a single bracketed
12990 expression left. If so, it must be the base register
12991 and the constant must be zero. */
12992 if (*s == '(' && strchr (s + 1, '(') == 0)
12994 INSERT_OPERAND (1, IMMJ, *ip, 0);
12998 if (my_getSmallExpression (&ep, r, s) > 0
12999 || !expr_const_in_range (&ep, 0, 16, 2))
13002 imm = ep.X_add_number >> 2;
13003 INSERT_OPERAND (1, IMMJ, *ip, imm);
13010 bfd_reloc_code_real_type r[3];
13014 /* Check whether there is only a single bracketed
13015 expression left. If so, it must be the base register
13016 and the constant must be zero. */
13017 if (*s == '(' && strchr (s + 1, '(') == 0)
13019 INSERT_OPERAND (1, IMML, *ip, 0);
13023 if (my_getSmallExpression (&ep, r, s) > 0
13024 || !expr_const_in_range (&ep, 0, 16, 0))
13027 imm = ep.X_add_number;
13028 INSERT_OPERAND (1, IMML, *ip, imm);
13035 bfd_reloc_code_real_type r[3];
13039 if (my_getSmallExpression (&ep, r, s) > 0
13040 || !expr_const_in_range (&ep, 1, 9, 0))
13043 imm = ep.X_add_number & 7;
13044 INSERT_OPERAND (1, IMMM, *ip, imm);
13049 case 'N': /* Register list for lwm and swm. */
13051 /* A comma-separated list of registers and/or
13052 dash-separated contiguous ranges including
13053 both ra and a set of one or more registers
13054 starting at s0 up to s3 which have to be
13061 and any permutations of these. */
13062 unsigned int reglist;
13065 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13068 if ((reglist & 0xfff1ffff) != 0x80010000)
13071 reglist = (reglist >> 17) & 7;
13073 if ((reglist & -reglist) != reglist)
13076 imm = ffs (reglist) - 1;
13077 INSERT_OPERAND (1, IMMN, *ip, imm);
13081 case 'O': /* sdbbp 4-bit code. */
13083 bfd_reloc_code_real_type r[3];
13087 if (my_getSmallExpression (&ep, r, s) > 0
13088 || !expr_const_in_range (&ep, 0, 16, 0))
13091 imm = ep.X_add_number;
13092 INSERT_OPERAND (1, IMMO, *ip, imm);
13099 bfd_reloc_code_real_type r[3];
13103 if (my_getSmallExpression (&ep, r, s) > 0
13104 || !expr_const_in_range (&ep, 0, 32, 2))
13107 imm = ep.X_add_number >> 2;
13108 INSERT_OPERAND (1, IMMP, *ip, imm);
13115 bfd_reloc_code_real_type r[3];
13119 if (my_getSmallExpression (&ep, r, s) > 0
13120 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13123 imm = ep.X_add_number >> 2;
13124 INSERT_OPERAND (1, IMMQ, *ip, imm);
13131 bfd_reloc_code_real_type r[3];
13135 /* Check whether there is only a single bracketed
13136 expression left. If so, it must be the base register
13137 and the constant must be zero. */
13138 if (*s == '(' && strchr (s + 1, '(') == 0)
13140 INSERT_OPERAND (1, IMMU, *ip, 0);
13144 if (my_getSmallExpression (&ep, r, s) > 0
13145 || !expr_const_in_range (&ep, 0, 32, 2))
13148 imm = ep.X_add_number >> 2;
13149 INSERT_OPERAND (1, IMMU, *ip, imm);
13156 bfd_reloc_code_real_type r[3];
13160 if (my_getSmallExpression (&ep, r, s) > 0
13161 || !expr_const_in_range (&ep, 0, 64, 2))
13164 imm = ep.X_add_number >> 2;
13165 INSERT_OPERAND (1, IMMW, *ip, imm);
13172 bfd_reloc_code_real_type r[3];
13176 if (my_getSmallExpression (&ep, r, s) > 0
13177 || !expr_const_in_range (&ep, -8, 8, 0))
13180 imm = ep.X_add_number;
13181 INSERT_OPERAND (1, IMMX, *ip, imm);
13188 bfd_reloc_code_real_type r[3];
13192 if (my_getSmallExpression (&ep, r, s) > 0
13193 || expr_const_in_range (&ep, -2, 2, 2)
13194 || !expr_const_in_range (&ep, -258, 258, 2))
13197 imm = ep.X_add_number >> 2;
13198 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13199 INSERT_OPERAND (1, IMMY, *ip, imm);
13206 bfd_reloc_code_real_type r[3];
13209 if (my_getSmallExpression (&ep, r, s) > 0
13210 || !expr_const_in_range (&ep, 0, 1, 0))
13217 as_bad (_("Internal error: bad microMIPS opcode "
13218 "(unknown extension operand type `m%c'): %s %s"),
13219 *args, insn->name, insn->args);
13220 /* Further processing is fruitless. */
13225 case 'n': /* Register list for 32-bit lwm and swm. */
13226 gas_assert (mips_opts.micromips);
13228 /* A comma-separated list of registers and/or
13229 dash-separated contiguous ranges including
13230 at least one of ra and a set of one or more
13231 registers starting at s0 up to s7 and then
13232 s8 which have to be consecutive, e.g.:
13240 and any permutations of these. */
13241 unsigned int reglist;
13245 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13248 if ((reglist & 0x3f00ffff) != 0)
13251 ra = (reglist >> 27) & 0x10;
13252 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13254 if ((reglist & -reglist) != reglist)
13257 imm = (ffs (reglist) - 1) | ra;
13258 INSERT_OPERAND (1, RT, *ip, imm);
13259 imm_expr.X_op = O_absent;
13263 case '|': /* 4-bit trap code. */
13264 gas_assert (mips_opts.micromips);
13265 my_getExpression (&imm_expr, s);
13266 check_absolute_expr (ip, &imm_expr);
13267 if ((unsigned long) imm_expr.X_add_number
13268 > MICROMIPSOP_MASK_TRAP)
13269 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13270 (unsigned long) imm_expr.X_add_number,
13271 ip->insn_mo->name);
13272 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13273 imm_expr.X_op = O_absent;
13278 as_bad (_("Bad char = '%c'\n"), *args);
13283 /* Args don't match. */
13285 insn_error = _("Illegal operands");
13286 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13291 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13293 gas_assert (firstinsn);
13294 need_delay_slot_ok = FALSE;
13303 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13305 /* This routine assembles an instruction into its binary format when
13306 assembling for the mips16. As a side effect, it sets one of the
13307 global variables imm_reloc or offset_reloc to the type of relocation
13308 to do if one of the operands is an address expression. It also sets
13309 forced_insn_length to the resulting instruction size in bytes if the
13310 user explicitly requested a small or extended instruction. */
13313 mips16_ip (char *str, struct mips_cl_insn *ip)
13317 struct mips_opcode *insn;
13319 unsigned int regno;
13320 unsigned int lastregno = 0;
13326 forced_insn_length = 0;
13328 for (s = str; ISLOWER (*s); ++s)
13340 if (s[1] == 't' && s[2] == ' ')
13343 forced_insn_length = 2;
13347 else if (s[1] == 'e' && s[2] == ' ')
13350 forced_insn_length = 4;
13354 /* Fall through. */
13356 insn_error = _("unknown opcode");
13360 if (mips_opts.noautoextend && !forced_insn_length)
13361 forced_insn_length = 2;
13363 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13365 insn_error = _("unrecognized opcode");
13374 gas_assert (strcmp (insn->name, str) == 0);
13376 ok = is_opcode_valid_16 (insn);
13379 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13380 && strcmp (insn->name, insn[1].name) == 0)
13389 static char buf[100];
13391 _("Opcode not supported on this processor: %s (%s)"),
13392 mips_cpu_info_from_arch (mips_opts.arch)->name,
13393 mips_cpu_info_from_isa (mips_opts.isa)->name);
13400 create_insn (ip, insn);
13401 imm_expr.X_op = O_absent;
13402 imm_reloc[0] = BFD_RELOC_UNUSED;
13403 imm_reloc[1] = BFD_RELOC_UNUSED;
13404 imm_reloc[2] = BFD_RELOC_UNUSED;
13405 imm2_expr.X_op = O_absent;
13406 offset_expr.X_op = O_absent;
13407 offset_reloc[0] = BFD_RELOC_UNUSED;
13408 offset_reloc[1] = BFD_RELOC_UNUSED;
13409 offset_reloc[2] = BFD_RELOC_UNUSED;
13410 for (args = insn->args; 1; ++args)
13417 /* In this switch statement we call break if we did not find
13418 a match, continue if we did find a match, or return if we
13429 /* Stuff the immediate value in now, if we can. */
13430 if (imm_expr.X_op == O_constant
13431 && *imm_reloc > BFD_RELOC_UNUSED
13432 && insn->pinfo != INSN_MACRO
13433 && calculate_reloc (*offset_reloc,
13434 imm_expr.X_add_number, &value))
13436 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13437 *offset_reloc, value, forced_insn_length,
13439 imm_expr.X_op = O_absent;
13440 *imm_reloc = BFD_RELOC_UNUSED;
13441 *offset_reloc = BFD_RELOC_UNUSED;
13455 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13458 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13474 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13476 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13480 /* Fall through. */
13491 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
13493 if (c == 'v' || c == 'w')
13496 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13498 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13509 if (c == 'v' || c == 'w')
13511 regno = mips16_to_32_reg_map[lastregno];
13525 regno = mips32_to_16_reg_map[regno];
13530 regno = ILLEGAL_REG;
13535 regno = ILLEGAL_REG;
13540 regno = ILLEGAL_REG;
13545 if (regno == AT && mips_opts.at)
13547 if (mips_opts.at == ATREG)
13548 as_warn (_("used $at without \".set noat\""));
13550 as_warn (_("used $%u with \".set at=$%u\""),
13551 regno, mips_opts.at);
13559 if (regno == ILLEGAL_REG)
13566 MIPS16_INSERT_OPERAND (RX, *ip, regno);
13570 MIPS16_INSERT_OPERAND (RY, *ip, regno);
13573 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
13576 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
13582 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
13585 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
13586 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
13596 if (strncmp (s, "$pc", 3) == 0)
13613 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
13616 if (imm_expr.X_op != O_constant)
13618 forced_insn_length = 4;
13619 ip->insn_opcode |= MIPS16_EXTEND;
13623 /* We need to relax this instruction. */
13624 *offset_reloc = *imm_reloc;
13625 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13630 *imm_reloc = BFD_RELOC_UNUSED;
13631 /* Fall through. */
13638 my_getExpression (&imm_expr, s);
13639 if (imm_expr.X_op == O_register)
13641 /* What we thought was an expression turned out to
13644 if (s[0] == '(' && args[1] == '(')
13646 /* It looks like the expression was omitted
13647 before a register indirection, which means
13648 that the expression is implicitly zero. We
13649 still set up imm_expr, so that we handle
13650 explicit extensions correctly. */
13651 imm_expr.X_op = O_constant;
13652 imm_expr.X_add_number = 0;
13653 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13660 /* We need to relax this instruction. */
13661 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
13670 /* We use offset_reloc rather than imm_reloc for the PC
13671 relative operands. This lets macros with both
13672 immediate and address operands work correctly. */
13673 my_getExpression (&offset_expr, s);
13675 if (offset_expr.X_op == O_register)
13678 /* We need to relax this instruction. */
13679 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13683 case '6': /* break code */
13684 my_getExpression (&imm_expr, s);
13685 check_absolute_expr (ip, &imm_expr);
13686 if ((unsigned long) imm_expr.X_add_number > 63)
13687 as_warn (_("Invalid value for `%s' (%lu)"),
13689 (unsigned long) imm_expr.X_add_number);
13690 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
13691 imm_expr.X_op = O_absent;
13695 case 'a': /* 26 bit address */
13696 my_getExpression (&offset_expr, s);
13698 *offset_reloc = BFD_RELOC_MIPS16_JMP;
13699 ip->insn_opcode <<= 16;
13702 case 'l': /* register list for entry macro */
13703 case 'L': /* register list for exit macro */
13713 unsigned int freg, reg1, reg2;
13715 while (*s == ' ' || *s == ',')
13717 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13719 else if (reg_lookup (&s, RTYPE_FPU, ®1))
13723 as_bad (_("can't parse register list"));
13733 if (!reg_lookup (&s, freg ? RTYPE_FPU
13734 : (RTYPE_GP | RTYPE_NUM), ®2))
13736 as_bad (_("invalid register list"));
13740 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
13742 mask &= ~ (7 << 3);
13745 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
13747 mask &= ~ (7 << 3);
13750 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
13751 mask |= (reg2 - 3) << 3;
13752 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
13753 mask |= (reg2 - 15) << 1;
13754 else if (reg1 == RA && reg2 == RA)
13758 as_bad (_("invalid register list"));
13762 /* The mask is filled in in the opcode table for the
13763 benefit of the disassembler. We remove it before
13764 applying the actual mask. */
13765 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
13766 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
13770 case 'm': /* Register list for save insn. */
13771 case 'M': /* Register list for restore insn. */
13773 int opcode = ip->insn_opcode;
13774 int framesz = 0, seen_framesz = 0;
13775 int nargs = 0, statics = 0, sregs = 0;
13779 unsigned int reg1, reg2;
13781 SKIP_SPACE_TABS (s);
13784 SKIP_SPACE_TABS (s);
13786 my_getExpression (&imm_expr, s);
13787 if (imm_expr.X_op == O_constant)
13789 /* Handle the frame size. */
13792 as_bad (_("more than one frame size in list"));
13796 framesz = imm_expr.X_add_number;
13797 imm_expr.X_op = O_absent;
13802 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
13804 as_bad (_("can't parse register list"));
13816 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
13819 as_bad (_("can't parse register list"));
13824 while (reg1 <= reg2)
13826 if (reg1 >= 4 && reg1 <= 7)
13830 nargs |= 1 << (reg1 - 4);
13832 /* statics $a0-$a3 */
13833 statics |= 1 << (reg1 - 4);
13835 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
13838 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
13840 else if (reg1 == 31)
13842 /* Add $ra to insn. */
13847 as_bad (_("unexpected register in list"));
13855 /* Encode args/statics combination. */
13856 if (nargs & statics)
13857 as_bad (_("arg/static registers overlap"));
13858 else if (nargs == 0xf)
13859 /* All $a0-$a3 are args. */
13860 opcode |= MIPS16_ALL_ARGS << 16;
13861 else if (statics == 0xf)
13862 /* All $a0-$a3 are statics. */
13863 opcode |= MIPS16_ALL_STATICS << 16;
13866 int narg = 0, nstat = 0;
13868 /* Count arg registers. */
13869 while (nargs & 0x1)
13875 as_bad (_("invalid arg register list"));
13877 /* Count static registers. */
13878 while (statics & 0x8)
13880 statics = (statics << 1) & 0xf;
13884 as_bad (_("invalid static register list"));
13886 /* Encode args/statics. */
13887 opcode |= ((narg << 2) | nstat) << 16;
13890 /* Encode $s0/$s1. */
13891 if (sregs & (1 << 0)) /* $s0 */
13893 if (sregs & (1 << 1)) /* $s1 */
13899 /* Count regs $s2-$s8. */
13907 as_bad (_("invalid static register list"));
13908 /* Encode $s2-$s8. */
13909 opcode |= nsreg << 24;
13912 /* Encode frame size. */
13914 as_bad (_("missing frame size"));
13915 else if ((framesz & 7) != 0 || framesz < 0
13916 || framesz > 0xff * 8)
13917 as_bad (_("invalid frame size"));
13918 else if (framesz != 128 || (opcode >> 16) != 0)
13921 opcode |= (((framesz & 0xf0) << 16)
13922 | (framesz & 0x0f));
13925 /* Finally build the instruction. */
13926 if ((opcode >> 16) != 0 || framesz == 0)
13927 opcode |= MIPS16_EXTEND;
13928 ip->insn_opcode = opcode;
13932 case 'e': /* extend code */
13933 my_getExpression (&imm_expr, s);
13934 check_absolute_expr (ip, &imm_expr);
13935 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
13937 as_warn (_("Invalid value for `%s' (%lu)"),
13939 (unsigned long) imm_expr.X_add_number);
13940 imm_expr.X_add_number &= 0x7ff;
13942 ip->insn_opcode |= imm_expr.X_add_number;
13943 imm_expr.X_op = O_absent;
13953 /* Args don't match. */
13954 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
13955 strcmp (insn->name, insn[1].name) == 0)
13962 insn_error = _("illegal operands");
13968 /* This structure holds information we know about a mips16 immediate
13971 struct mips16_immed_operand
13973 /* The type code used in the argument string in the opcode table. */
13975 /* The number of bits in the short form of the opcode. */
13977 /* The number of bits in the extended form of the opcode. */
13979 /* The amount by which the short form is shifted when it is used;
13980 for example, the sw instruction has a shift count of 2. */
13982 /* The amount by which the short form is shifted when it is stored
13983 into the instruction code. */
13985 /* Non-zero if the short form is unsigned. */
13987 /* Non-zero if the extended form is unsigned. */
13989 /* Non-zero if the value is PC relative. */
13993 /* The mips16 immediate operand types. */
13995 static const struct mips16_immed_operand mips16_immed_operands[] =
13997 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
13998 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
13999 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14000 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14001 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14002 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14003 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14004 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14005 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14006 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14007 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14008 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14009 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14010 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14011 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14012 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14013 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14014 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14015 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14016 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14017 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14020 #define MIPS16_NUM_IMMED \
14021 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14023 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14024 NBITS is the number of significant bits in VAL. */
14026 static unsigned long
14027 mips16_immed_extend (offsetT val, unsigned int nbits)
14032 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14035 else if (nbits == 15)
14037 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14042 extval = ((val & 0x1f) << 6) | (val & 0x20);
14045 return (extval << 16) | val;
14048 /* Install immediate value VAL into MIPS16 instruction *INSN,
14049 extending it if necessary. The instruction in *INSN may
14050 already be extended.
14052 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14053 if none. In the former case, VAL is a 16-bit number with no
14054 defined signedness.
14056 TYPE is the type of the immediate field. USER_INSN_LENGTH
14057 is the length that the user requested, or 0 if none. */
14060 mips16_immed (char *file, unsigned int line, int type,
14061 bfd_reloc_code_real_type reloc, offsetT val,
14062 unsigned int user_insn_length, unsigned long *insn)
14064 const struct mips16_immed_operand *op;
14065 int mintiny, maxtiny;
14067 op = mips16_immed_operands;
14068 while (op->type != type)
14071 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14076 if (type == '<' || type == '>' || type == '[' || type == ']')
14079 maxtiny = 1 << op->nbits;
14084 maxtiny = (1 << op->nbits) - 1;
14086 if (reloc != BFD_RELOC_UNUSED)
14091 mintiny = - (1 << (op->nbits - 1));
14092 maxtiny = (1 << (op->nbits - 1)) - 1;
14093 if (reloc != BFD_RELOC_UNUSED)
14094 val = SEXT_16BIT (val);
14097 /* Branch offsets have an implicit 0 in the lowest bit. */
14098 if (type == 'p' || type == 'q')
14101 if ((val & ((1 << op->shift) - 1)) != 0
14102 || val < (mintiny << op->shift)
14103 || val > (maxtiny << op->shift))
14105 /* We need an extended instruction. */
14106 if (user_insn_length == 2)
14107 as_bad_where (file, line, _("invalid unextended operand value"));
14109 *insn |= MIPS16_EXTEND;
14111 else if (user_insn_length == 4)
14113 /* The operand doesn't force an unextended instruction to be extended.
14114 Warn if the user wanted an extended instruction anyway. */
14115 *insn |= MIPS16_EXTEND;
14116 as_warn_where (file, line,
14117 _("extended operand requested but not required"));
14120 if (mips16_opcode_length (*insn) == 2)
14124 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14125 insnval <<= op->op_shift;
14130 long minext, maxext;
14132 if (reloc == BFD_RELOC_UNUSED)
14137 maxext = (1 << op->extbits) - 1;
14141 minext = - (1 << (op->extbits - 1));
14142 maxext = (1 << (op->extbits - 1)) - 1;
14144 if (val < minext || val > maxext)
14145 as_bad_where (file, line,
14146 _("operand value out of range for instruction"));
14149 *insn |= mips16_immed_extend (val, op->extbits);
14153 struct percent_op_match
14156 bfd_reloc_code_real_type reloc;
14159 static const struct percent_op_match mips_percent_op[] =
14161 {"%lo", BFD_RELOC_LO16},
14163 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14164 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14165 {"%call16", BFD_RELOC_MIPS_CALL16},
14166 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14167 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14168 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14169 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14170 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14171 {"%got", BFD_RELOC_MIPS_GOT16},
14172 {"%gp_rel", BFD_RELOC_GPREL16},
14173 {"%half", BFD_RELOC_16},
14174 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14175 {"%higher", BFD_RELOC_MIPS_HIGHER},
14176 {"%neg", BFD_RELOC_MIPS_SUB},
14177 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14178 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14179 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14180 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14181 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14182 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14183 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14185 {"%hi", BFD_RELOC_HI16_S}
14188 static const struct percent_op_match mips16_percent_op[] =
14190 {"%lo", BFD_RELOC_MIPS16_LO16},
14191 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14192 {"%got", BFD_RELOC_MIPS16_GOT16},
14193 {"%call16", BFD_RELOC_MIPS16_CALL16},
14194 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14195 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14196 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14197 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14198 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14199 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14200 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14201 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14205 /* Return true if *STR points to a relocation operator. When returning true,
14206 move *STR over the operator and store its relocation code in *RELOC.
14207 Leave both *STR and *RELOC alone when returning false. */
14210 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14212 const struct percent_op_match *percent_op;
14215 if (mips_opts.mips16)
14217 percent_op = mips16_percent_op;
14218 limit = ARRAY_SIZE (mips16_percent_op);
14222 percent_op = mips_percent_op;
14223 limit = ARRAY_SIZE (mips_percent_op);
14226 for (i = 0; i < limit; i++)
14227 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14229 int len = strlen (percent_op[i].str);
14231 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14234 *str += strlen (percent_op[i].str);
14235 *reloc = percent_op[i].reloc;
14237 /* Check whether the output BFD supports this relocation.
14238 If not, issue an error and fall back on something safe. */
14239 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14241 as_bad (_("relocation %s isn't supported by the current ABI"),
14242 percent_op[i].str);
14243 *reloc = BFD_RELOC_UNUSED;
14251 /* Parse string STR as a 16-bit relocatable operand. Store the
14252 expression in *EP and the relocations in the array starting
14253 at RELOC. Return the number of relocation operators used.
14255 On exit, EXPR_END points to the first character after the expression. */
14258 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14261 bfd_reloc_code_real_type reversed_reloc[3];
14262 size_t reloc_index, i;
14263 int crux_depth, str_depth;
14266 /* Search for the start of the main expression, recoding relocations
14267 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14268 of the main expression and with CRUX_DEPTH containing the number
14269 of open brackets at that point. */
14276 crux_depth = str_depth;
14278 /* Skip over whitespace and brackets, keeping count of the number
14280 while (*str == ' ' || *str == '\t' || *str == '(')
14285 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14286 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14288 my_getExpression (ep, crux);
14291 /* Match every open bracket. */
14292 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14296 if (crux_depth > 0)
14297 as_bad (_("unclosed '('"));
14301 if (reloc_index != 0)
14303 prev_reloc_op_frag = frag_now;
14304 for (i = 0; i < reloc_index; i++)
14305 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14308 return reloc_index;
14312 my_getExpression (expressionS *ep, char *str)
14316 save_in = input_line_pointer;
14317 input_line_pointer = str;
14319 expr_end = input_line_pointer;
14320 input_line_pointer = save_in;
14324 md_atof (int type, char *litP, int *sizeP)
14326 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14330 md_number_to_chars (char *buf, valueT val, int n)
14332 if (target_big_endian)
14333 number_to_chars_bigendian (buf, val, n);
14335 number_to_chars_littleendian (buf, val, n);
14339 static int support_64bit_objects(void)
14341 const char **list, **l;
14344 list = bfd_target_list ();
14345 for (l = list; *l != NULL; l++)
14346 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14347 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14349 yes = (*l != NULL);
14353 #endif /* OBJ_ELF */
14355 const char *md_shortopts = "O::g::G:";
14359 OPTION_MARCH = OPTION_MD_BASE,
14381 OPTION_NO_SMARTMIPS,
14385 OPTION_NO_MICROMIPS,
14388 OPTION_COMPAT_ARCH_BASE,
14397 OPTION_M7000_HILO_FIX,
14398 OPTION_MNO_7000_HILO_FIX,
14401 OPTION_FIX_LOONGSON2F_JUMP,
14402 OPTION_NO_FIX_LOONGSON2F_JUMP,
14403 OPTION_FIX_LOONGSON2F_NOP,
14404 OPTION_NO_FIX_LOONGSON2F_NOP,
14406 OPTION_NO_FIX_VR4120,
14408 OPTION_NO_FIX_VR4130,
14409 OPTION_FIX_CN63XXP1,
14410 OPTION_NO_FIX_CN63XXP1,
14417 OPTION_CONSTRUCT_FLOATS,
14418 OPTION_NO_CONSTRUCT_FLOATS,
14421 OPTION_RELAX_BRANCH,
14422 OPTION_NO_RELAX_BRANCH,
14429 OPTION_SINGLE_FLOAT,
14430 OPTION_DOUBLE_FLOAT,
14433 OPTION_CALL_SHARED,
14434 OPTION_CALL_NONPIC,
14444 OPTION_MVXWORKS_PIC,
14445 #endif /* OBJ_ELF */
14449 struct option md_longopts[] =
14451 /* Options which specify architecture. */
14452 {"march", required_argument, NULL, OPTION_MARCH},
14453 {"mtune", required_argument, NULL, OPTION_MTUNE},
14454 {"mips0", no_argument, NULL, OPTION_MIPS1},
14455 {"mips1", no_argument, NULL, OPTION_MIPS1},
14456 {"mips2", no_argument, NULL, OPTION_MIPS2},
14457 {"mips3", no_argument, NULL, OPTION_MIPS3},
14458 {"mips4", no_argument, NULL, OPTION_MIPS4},
14459 {"mips5", no_argument, NULL, OPTION_MIPS5},
14460 {"mips32", no_argument, NULL, OPTION_MIPS32},
14461 {"mips64", no_argument, NULL, OPTION_MIPS64},
14462 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
14463 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
14465 /* Options which specify Application Specific Extensions (ASEs). */
14466 {"mips16", no_argument, NULL, OPTION_MIPS16},
14467 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
14468 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
14469 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
14470 {"mdmx", no_argument, NULL, OPTION_MDMX},
14471 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
14472 {"mdsp", no_argument, NULL, OPTION_DSP},
14473 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
14474 {"mmt", no_argument, NULL, OPTION_MT},
14475 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
14476 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
14477 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
14478 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
14479 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
14480 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
14481 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
14482 {"mmcu", no_argument, NULL, OPTION_MCU},
14483 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
14485 /* Old-style architecture options. Don't add more of these. */
14486 {"m4650", no_argument, NULL, OPTION_M4650},
14487 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
14488 {"m4010", no_argument, NULL, OPTION_M4010},
14489 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
14490 {"m4100", no_argument, NULL, OPTION_M4100},
14491 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
14492 {"m3900", no_argument, NULL, OPTION_M3900},
14493 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
14495 /* Options which enable bug fixes. */
14496 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
14497 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14498 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
14499 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
14500 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
14501 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
14502 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
14503 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
14504 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
14505 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
14506 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
14507 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
14508 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
14509 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
14510 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
14512 /* Miscellaneous options. */
14513 {"trap", no_argument, NULL, OPTION_TRAP},
14514 {"no-break", no_argument, NULL, OPTION_TRAP},
14515 {"break", no_argument, NULL, OPTION_BREAK},
14516 {"no-trap", no_argument, NULL, OPTION_BREAK},
14517 {"EB", no_argument, NULL, OPTION_EB},
14518 {"EL", no_argument, NULL, OPTION_EL},
14519 {"mfp32", no_argument, NULL, OPTION_FP32},
14520 {"mgp32", no_argument, NULL, OPTION_GP32},
14521 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
14522 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
14523 {"mfp64", no_argument, NULL, OPTION_FP64},
14524 {"mgp64", no_argument, NULL, OPTION_GP64},
14525 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
14526 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
14527 {"mshared", no_argument, NULL, OPTION_MSHARED},
14528 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
14529 {"msym32", no_argument, NULL, OPTION_MSYM32},
14530 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
14531 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
14532 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
14533 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
14534 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
14536 /* Strictly speaking this next option is ELF specific,
14537 but we allow it for other ports as well in order to
14538 make testing easier. */
14539 {"32", no_argument, NULL, OPTION_32},
14541 /* ELF-specific options. */
14543 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
14544 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
14545 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
14546 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
14547 {"xgot", no_argument, NULL, OPTION_XGOT},
14548 {"mabi", required_argument, NULL, OPTION_MABI},
14549 {"n32", no_argument, NULL, OPTION_N32},
14550 {"64", no_argument, NULL, OPTION_64},
14551 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
14552 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
14553 {"mpdr", no_argument, NULL, OPTION_PDR},
14554 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
14555 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
14556 #endif /* OBJ_ELF */
14558 {NULL, no_argument, NULL, 0}
14560 size_t md_longopts_size = sizeof (md_longopts);
14562 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14563 NEW_VALUE. Warn if another value was already specified. Note:
14564 we have to defer parsing the -march and -mtune arguments in order
14565 to handle 'from-abi' correctly, since the ABI might be specified
14566 in a later argument. */
14569 mips_set_option_string (const char **string_ptr, const char *new_value)
14571 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14572 as_warn (_("A different %s was already specified, is now %s"),
14573 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14576 *string_ptr = new_value;
14580 md_parse_option (int c, char *arg)
14584 case OPTION_CONSTRUCT_FLOATS:
14585 mips_disable_float_construction = 0;
14588 case OPTION_NO_CONSTRUCT_FLOATS:
14589 mips_disable_float_construction = 1;
14601 target_big_endian = 1;
14605 target_big_endian = 0;
14611 else if (arg[0] == '0')
14613 else if (arg[0] == '1')
14623 mips_debug = atoi (arg);
14627 file_mips_isa = ISA_MIPS1;
14631 file_mips_isa = ISA_MIPS2;
14635 file_mips_isa = ISA_MIPS3;
14639 file_mips_isa = ISA_MIPS4;
14643 file_mips_isa = ISA_MIPS5;
14646 case OPTION_MIPS32:
14647 file_mips_isa = ISA_MIPS32;
14650 case OPTION_MIPS32R2:
14651 file_mips_isa = ISA_MIPS32R2;
14654 case OPTION_MIPS64R2:
14655 file_mips_isa = ISA_MIPS64R2;
14658 case OPTION_MIPS64:
14659 file_mips_isa = ISA_MIPS64;
14663 mips_set_option_string (&mips_tune_string, arg);
14667 mips_set_option_string (&mips_arch_string, arg);
14671 mips_set_option_string (&mips_arch_string, "4650");
14672 mips_set_option_string (&mips_tune_string, "4650");
14675 case OPTION_NO_M4650:
14679 mips_set_option_string (&mips_arch_string, "4010");
14680 mips_set_option_string (&mips_tune_string, "4010");
14683 case OPTION_NO_M4010:
14687 mips_set_option_string (&mips_arch_string, "4100");
14688 mips_set_option_string (&mips_tune_string, "4100");
14691 case OPTION_NO_M4100:
14695 mips_set_option_string (&mips_arch_string, "3900");
14696 mips_set_option_string (&mips_tune_string, "3900");
14699 case OPTION_NO_M3900:
14703 mips_opts.ase_mdmx = 1;
14706 case OPTION_NO_MDMX:
14707 mips_opts.ase_mdmx = 0;
14711 mips_opts.ase_dsp = 1;
14712 mips_opts.ase_dspr2 = 0;
14715 case OPTION_NO_DSP:
14716 mips_opts.ase_dsp = 0;
14717 mips_opts.ase_dspr2 = 0;
14721 mips_opts.ase_dspr2 = 1;
14722 mips_opts.ase_dsp = 1;
14725 case OPTION_NO_DSPR2:
14726 mips_opts.ase_dspr2 = 0;
14727 mips_opts.ase_dsp = 0;
14731 mips_opts.ase_mt = 1;
14735 mips_opts.ase_mt = 0;
14739 mips_opts.ase_mcu = 1;
14742 case OPTION_NO_MCU:
14743 mips_opts.ase_mcu = 0;
14746 case OPTION_MICROMIPS:
14747 if (mips_opts.mips16 == 1)
14749 as_bad (_("-mmicromips cannot be used with -mips16"));
14752 mips_opts.micromips = 1;
14753 mips_no_prev_insn ();
14756 case OPTION_NO_MICROMIPS:
14757 mips_opts.micromips = 0;
14758 mips_no_prev_insn ();
14761 case OPTION_MIPS16:
14762 if (mips_opts.micromips == 1)
14764 as_bad (_("-mips16 cannot be used with -micromips"));
14767 mips_opts.mips16 = 1;
14768 mips_no_prev_insn ();
14771 case OPTION_NO_MIPS16:
14772 mips_opts.mips16 = 0;
14773 mips_no_prev_insn ();
14776 case OPTION_MIPS3D:
14777 mips_opts.ase_mips3d = 1;
14780 case OPTION_NO_MIPS3D:
14781 mips_opts.ase_mips3d = 0;
14784 case OPTION_SMARTMIPS:
14785 mips_opts.ase_smartmips = 1;
14788 case OPTION_NO_SMARTMIPS:
14789 mips_opts.ase_smartmips = 0;
14792 case OPTION_FIX_24K:
14796 case OPTION_NO_FIX_24K:
14800 case OPTION_FIX_LOONGSON2F_JUMP:
14801 mips_fix_loongson2f_jump = TRUE;
14804 case OPTION_NO_FIX_LOONGSON2F_JUMP:
14805 mips_fix_loongson2f_jump = FALSE;
14808 case OPTION_FIX_LOONGSON2F_NOP:
14809 mips_fix_loongson2f_nop = TRUE;
14812 case OPTION_NO_FIX_LOONGSON2F_NOP:
14813 mips_fix_loongson2f_nop = FALSE;
14816 case OPTION_FIX_VR4120:
14817 mips_fix_vr4120 = 1;
14820 case OPTION_NO_FIX_VR4120:
14821 mips_fix_vr4120 = 0;
14824 case OPTION_FIX_VR4130:
14825 mips_fix_vr4130 = 1;
14828 case OPTION_NO_FIX_VR4130:
14829 mips_fix_vr4130 = 0;
14832 case OPTION_FIX_CN63XXP1:
14833 mips_fix_cn63xxp1 = TRUE;
14836 case OPTION_NO_FIX_CN63XXP1:
14837 mips_fix_cn63xxp1 = FALSE;
14840 case OPTION_RELAX_BRANCH:
14841 mips_relax_branch = 1;
14844 case OPTION_NO_RELAX_BRANCH:
14845 mips_relax_branch = 0;
14848 case OPTION_MSHARED:
14849 mips_in_shared = TRUE;
14852 case OPTION_MNO_SHARED:
14853 mips_in_shared = FALSE;
14856 case OPTION_MSYM32:
14857 mips_opts.sym32 = TRUE;
14860 case OPTION_MNO_SYM32:
14861 mips_opts.sym32 = FALSE;
14865 /* When generating ELF code, we permit -KPIC and -call_shared to
14866 select SVR4_PIC, and -non_shared to select no PIC. This is
14867 intended to be compatible with Irix 5. */
14868 case OPTION_CALL_SHARED:
14871 as_bad (_("-call_shared is supported only for ELF format"));
14874 mips_pic = SVR4_PIC;
14875 mips_abicalls = TRUE;
14878 case OPTION_CALL_NONPIC:
14881 as_bad (_("-call_nonpic is supported only for ELF format"));
14885 mips_abicalls = TRUE;
14888 case OPTION_NON_SHARED:
14891 as_bad (_("-non_shared is supported only for ELF format"));
14895 mips_abicalls = FALSE;
14898 /* The -xgot option tells the assembler to use 32 bit offsets
14899 when accessing the got in SVR4_PIC mode. It is for Irix
14904 #endif /* OBJ_ELF */
14907 g_switch_value = atoi (arg);
14911 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
14915 mips_abi = O32_ABI;
14916 /* We silently ignore -32 for non-ELF targets. This greatly
14917 simplifies the construction of the MIPS GAS test cases. */
14924 as_bad (_("-n32 is supported for ELF format only"));
14927 mips_abi = N32_ABI;
14933 as_bad (_("-64 is supported for ELF format only"));
14936 mips_abi = N64_ABI;
14937 if (!support_64bit_objects())
14938 as_fatal (_("No compiled in support for 64 bit object file format"));
14940 #endif /* OBJ_ELF */
14943 file_mips_gp32 = 1;
14947 file_mips_gp32 = 0;
14951 file_mips_fp32 = 1;
14955 file_mips_fp32 = 0;
14958 case OPTION_SINGLE_FLOAT:
14959 file_mips_single_float = 1;
14962 case OPTION_DOUBLE_FLOAT:
14963 file_mips_single_float = 0;
14966 case OPTION_SOFT_FLOAT:
14967 file_mips_soft_float = 1;
14970 case OPTION_HARD_FLOAT:
14971 file_mips_soft_float = 0;
14978 as_bad (_("-mabi is supported for ELF format only"));
14981 if (strcmp (arg, "32") == 0)
14982 mips_abi = O32_ABI;
14983 else if (strcmp (arg, "o64") == 0)
14984 mips_abi = O64_ABI;
14985 else if (strcmp (arg, "n32") == 0)
14986 mips_abi = N32_ABI;
14987 else if (strcmp (arg, "64") == 0)
14989 mips_abi = N64_ABI;
14990 if (! support_64bit_objects())
14991 as_fatal (_("No compiled in support for 64 bit object file "
14994 else if (strcmp (arg, "eabi") == 0)
14995 mips_abi = EABI_ABI;
14998 as_fatal (_("invalid abi -mabi=%s"), arg);
15002 #endif /* OBJ_ELF */
15004 case OPTION_M7000_HILO_FIX:
15005 mips_7000_hilo_fix = TRUE;
15008 case OPTION_MNO_7000_HILO_FIX:
15009 mips_7000_hilo_fix = FALSE;
15013 case OPTION_MDEBUG:
15014 mips_flag_mdebug = TRUE;
15017 case OPTION_NO_MDEBUG:
15018 mips_flag_mdebug = FALSE;
15022 mips_flag_pdr = TRUE;
15025 case OPTION_NO_PDR:
15026 mips_flag_pdr = FALSE;
15029 case OPTION_MVXWORKS_PIC:
15030 mips_pic = VXWORKS_PIC;
15032 #endif /* OBJ_ELF */
15038 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15043 /* Set up globals to generate code for the ISA or processor
15044 described by INFO. */
15047 mips_set_architecture (const struct mips_cpu_info *info)
15051 file_mips_arch = info->cpu;
15052 mips_opts.arch = info->cpu;
15053 mips_opts.isa = info->isa;
15058 /* Likewise for tuning. */
15061 mips_set_tune (const struct mips_cpu_info *info)
15064 mips_tune = info->cpu;
15069 mips_after_parse_args (void)
15071 const struct mips_cpu_info *arch_info = 0;
15072 const struct mips_cpu_info *tune_info = 0;
15074 /* GP relative stuff not working for PE */
15075 if (strncmp (TARGET_OS, "pe", 2) == 0)
15077 if (g_switch_seen && g_switch_value != 0)
15078 as_bad (_("-G not supported in this configuration."));
15079 g_switch_value = 0;
15082 if (mips_abi == NO_ABI)
15083 mips_abi = MIPS_DEFAULT_ABI;
15085 /* The following code determines the architecture and register size.
15086 Similar code was added to GCC 3.3 (see override_options() in
15087 config/mips/mips.c). The GAS and GCC code should be kept in sync
15088 as much as possible. */
15090 if (mips_arch_string != 0)
15091 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15093 if (file_mips_isa != ISA_UNKNOWN)
15095 /* Handle -mipsN. At this point, file_mips_isa contains the
15096 ISA level specified by -mipsN, while arch_info->isa contains
15097 the -march selection (if any). */
15098 if (arch_info != 0)
15100 /* -march takes precedence over -mipsN, since it is more descriptive.
15101 There's no harm in specifying both as long as the ISA levels
15103 if (file_mips_isa != arch_info->isa)
15104 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15105 mips_cpu_info_from_isa (file_mips_isa)->name,
15106 mips_cpu_info_from_isa (arch_info->isa)->name);
15109 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15112 if (arch_info == 0)
15114 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15115 gas_assert (arch_info);
15118 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15119 as_bad (_("-march=%s is not compatible with the selected ABI"),
15122 mips_set_architecture (arch_info);
15124 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15125 if (mips_tune_string != 0)
15126 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15128 if (tune_info == 0)
15129 mips_set_tune (arch_info);
15131 mips_set_tune (tune_info);
15133 if (file_mips_gp32 >= 0)
15135 /* The user specified the size of the integer registers. Make sure
15136 it agrees with the ABI and ISA. */
15137 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15138 as_bad (_("-mgp64 used with a 32-bit processor"));
15139 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15140 as_bad (_("-mgp32 used with a 64-bit ABI"));
15141 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15142 as_bad (_("-mgp64 used with a 32-bit ABI"));
15146 /* Infer the integer register size from the ABI and processor.
15147 Restrict ourselves to 32-bit registers if that's all the
15148 processor has, or if the ABI cannot handle 64-bit registers. */
15149 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15150 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15153 switch (file_mips_fp32)
15157 /* No user specified float register size.
15158 ??? GAS treats single-float processors as though they had 64-bit
15159 float registers (although it complains when double-precision
15160 instructions are used). As things stand, saying they have 32-bit
15161 registers would lead to spurious "register must be even" messages.
15162 So here we assume float registers are never smaller than the
15164 if (file_mips_gp32 == 0)
15165 /* 64-bit integer registers implies 64-bit float registers. */
15166 file_mips_fp32 = 0;
15167 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
15168 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15169 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15170 file_mips_fp32 = 0;
15172 /* 32-bit float registers. */
15173 file_mips_fp32 = 1;
15176 /* The user specified the size of the float registers. Check if it
15177 agrees with the ABI and ISA. */
15179 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15180 as_bad (_("-mfp64 used with a 32-bit fpu"));
15181 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15182 && !ISA_HAS_MXHC1 (mips_opts.isa))
15183 as_warn (_("-mfp64 used with a 32-bit ABI"));
15186 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15187 as_warn (_("-mfp32 used with a 64-bit ABI"));
15191 /* End of GCC-shared inference code. */
15193 /* This flag is set when we have a 64-bit capable CPU but use only
15194 32-bit wide registers. Note that EABI does not use it. */
15195 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15196 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15197 || mips_abi == O32_ABI))
15198 mips_32bitmode = 1;
15200 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15201 as_bad (_("trap exception not supported at ISA 1"));
15203 /* If the selected architecture includes support for ASEs, enable
15204 generation of code for them. */
15205 if (mips_opts.mips16 == -1)
15206 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15207 if (mips_opts.micromips == -1)
15208 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15209 if (mips_opts.ase_mips3d == -1)
15210 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
15211 && file_mips_fp32 == 0) ? 1 : 0;
15212 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
15213 as_bad (_("-mfp32 used with -mips3d"));
15215 if (mips_opts.ase_mdmx == -1)
15216 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
15217 && file_mips_fp32 == 0) ? 1 : 0;
15218 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
15219 as_bad (_("-mfp32 used with -mdmx"));
15221 if (mips_opts.ase_smartmips == -1)
15222 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
15223 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
15224 as_warn (_("%s ISA does not support SmartMIPS"),
15225 mips_cpu_info_from_isa (mips_opts.isa)->name);
15227 if (mips_opts.ase_dsp == -1)
15228 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15229 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
15230 as_warn (_("%s ISA does not support DSP ASE"),
15231 mips_cpu_info_from_isa (mips_opts.isa)->name);
15233 if (mips_opts.ase_dspr2 == -1)
15235 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
15236 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
15238 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
15239 as_warn (_("%s ISA does not support DSP R2 ASE"),
15240 mips_cpu_info_from_isa (mips_opts.isa)->name);
15242 if (mips_opts.ase_mt == -1)
15243 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
15244 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
15245 as_warn (_("%s ISA does not support MT ASE"),
15246 mips_cpu_info_from_isa (mips_opts.isa)->name);
15248 if (mips_opts.ase_mcu == -1)
15249 mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
15250 if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
15251 as_warn (_("%s ISA does not support MCU ASE"),
15252 mips_cpu_info_from_isa (mips_opts.isa)->name);
15254 file_mips_isa = mips_opts.isa;
15255 file_ase_mips3d = mips_opts.ase_mips3d;
15256 file_ase_mdmx = mips_opts.ase_mdmx;
15257 file_ase_smartmips = mips_opts.ase_smartmips;
15258 file_ase_dsp = mips_opts.ase_dsp;
15259 file_ase_dspr2 = mips_opts.ase_dspr2;
15260 file_ase_mt = mips_opts.ase_mt;
15261 mips_opts.gp32 = file_mips_gp32;
15262 mips_opts.fp32 = file_mips_fp32;
15263 mips_opts.soft_float = file_mips_soft_float;
15264 mips_opts.single_float = file_mips_single_float;
15266 if (mips_flag_mdebug < 0)
15268 #ifdef OBJ_MAYBE_ECOFF
15269 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
15270 mips_flag_mdebug = 1;
15272 #endif /* OBJ_MAYBE_ECOFF */
15273 mips_flag_mdebug = 0;
15278 mips_init_after_args (void)
15280 /* initialize opcodes */
15281 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15282 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15286 md_pcrel_from (fixS *fixP)
15288 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15289 switch (fixP->fx_r_type)
15291 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15292 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15293 /* Return the address of the delay slot. */
15296 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15297 case BFD_RELOC_MICROMIPS_JMP:
15298 case BFD_RELOC_16_PCREL_S2:
15299 case BFD_RELOC_MIPS_JMP:
15300 /* Return the address of the delay slot. */
15304 /* We have no relocation type for PC relative MIPS16 instructions. */
15305 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15306 as_bad_where (fixP->fx_file, fixP->fx_line,
15307 _("PC relative MIPS16 instruction references a different section"));
15312 /* This is called before the symbol table is processed. In order to
15313 work with gcc when using mips-tfile, we must keep all local labels.
15314 However, in other cases, we want to discard them. If we were
15315 called with -g, but we didn't see any debugging information, it may
15316 mean that gcc is smuggling debugging information through to
15317 mips-tfile, in which case we must generate all local labels. */
15320 mips_frob_file_before_adjust (void)
15322 #ifndef NO_ECOFF_DEBUGGING
15323 if (ECOFF_DEBUGGING
15325 && ! ecoff_debugging_seen)
15326 flag_keep_locals = 1;
15330 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15331 the corresponding LO16 reloc. This is called before md_apply_fix and
15332 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15333 relocation operators.
15335 For our purposes, a %lo() expression matches a %got() or %hi()
15338 (a) it refers to the same symbol; and
15339 (b) the offset applied in the %lo() expression is no lower than
15340 the offset applied in the %got() or %hi().
15342 (b) allows us to cope with code like:
15345 lh $4,%lo(foo+2)($4)
15347 ...which is legal on RELA targets, and has a well-defined behaviour
15348 if the user knows that adding 2 to "foo" will not induce a carry to
15351 When several %lo()s match a particular %got() or %hi(), we use the
15352 following rules to distinguish them:
15354 (1) %lo()s with smaller offsets are a better match than %lo()s with
15357 (2) %lo()s with no matching %got() or %hi() are better than those
15358 that already have a matching %got() or %hi().
15360 (3) later %lo()s are better than earlier %lo()s.
15362 These rules are applied in order.
15364 (1) means, among other things, that %lo()s with identical offsets are
15365 chosen if they exist.
15367 (2) means that we won't associate several high-part relocations with
15368 the same low-part relocation unless there's no alternative. Having
15369 several high parts for the same low part is a GNU extension; this rule
15370 allows careful users to avoid it.
15372 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15373 with the last high-part relocation being at the front of the list.
15374 It therefore makes sense to choose the last matching low-part
15375 relocation, all other things being equal. It's also easier
15376 to code that way. */
15379 mips_frob_file (void)
15381 struct mips_hi_fixup *l;
15382 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15384 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15386 segment_info_type *seginfo;
15387 bfd_boolean matched_lo_p;
15388 fixS **hi_pos, **lo_pos, **pos;
15390 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15392 /* If a GOT16 relocation turns out to be against a global symbol,
15393 there isn't supposed to be a matching LO. Ignore %gots against
15394 constants; we'll report an error for those later. */
15395 if (got16_reloc_p (l->fixp->fx_r_type)
15396 && !(l->fixp->fx_addsy
15397 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15400 /* Check quickly whether the next fixup happens to be a matching %lo. */
15401 if (fixup_has_matching_lo_p (l->fixp))
15404 seginfo = seg_info (l->seg);
15406 /* Set HI_POS to the position of this relocation in the chain.
15407 Set LO_POS to the position of the chosen low-part relocation.
15408 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15409 relocation that matches an immediately-preceding high-part
15413 matched_lo_p = FALSE;
15414 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15416 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15418 if (*pos == l->fixp)
15421 if ((*pos)->fx_r_type == looking_for_rtype
15422 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15423 && (*pos)->fx_offset >= l->fixp->fx_offset
15425 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15427 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15430 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15431 && fixup_has_matching_lo_p (*pos));
15434 /* If we found a match, remove the high-part relocation from its
15435 current position and insert it before the low-part relocation.
15436 Make the offsets match so that fixup_has_matching_lo_p()
15439 We don't warn about unmatched high-part relocations since some
15440 versions of gcc have been known to emit dead "lui ...%hi(...)"
15442 if (lo_pos != NULL)
15444 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15445 if (l->fixp->fx_next != *lo_pos)
15447 *hi_pos = l->fixp->fx_next;
15448 l->fixp->fx_next = *lo_pos;
15456 mips_force_relocation (fixS *fixp)
15458 if (generic_force_reloc (fixp))
15461 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15462 so that the linker relaxation can update targets. */
15463 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15464 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15465 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15471 /* Read the instruction associated with RELOC from BUF. */
15473 static unsigned int
15474 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15476 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15477 return read_compressed_insn (buf, 4);
15479 return read_insn (buf);
15482 /* Write instruction INSN to BUF, given that it has been relocated
15486 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15487 unsigned long insn)
15489 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15490 write_compressed_insn (buf, insn, 4);
15492 write_insn (buf, insn);
15495 /* Apply a fixup to the object file. */
15498 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15501 unsigned long insn;
15502 reloc_howto_type *howto;
15504 /* We ignore generic BFD relocations we don't know about. */
15505 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15509 gas_assert (fixP->fx_size == 2
15510 || fixP->fx_size == 4
15511 || fixP->fx_r_type == BFD_RELOC_16
15512 || fixP->fx_r_type == BFD_RELOC_64
15513 || fixP->fx_r_type == BFD_RELOC_CTOR
15514 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15515 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15516 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15517 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15518 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15520 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15522 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15523 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15524 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15525 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
15527 /* Don't treat parts of a composite relocation as done. There are two
15530 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15531 should nevertheless be emitted if the first part is.
15533 (2) In normal usage, composite relocations are never assembly-time
15534 constants. The easiest way of dealing with the pathological
15535 exceptions is to generate a relocation against STN_UNDEF and
15536 leave everything up to the linker. */
15537 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15540 switch (fixP->fx_r_type)
15542 case BFD_RELOC_MIPS_TLS_GD:
15543 case BFD_RELOC_MIPS_TLS_LDM:
15544 case BFD_RELOC_MIPS_TLS_DTPREL32:
15545 case BFD_RELOC_MIPS_TLS_DTPREL64:
15546 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15547 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15548 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15549 case BFD_RELOC_MIPS_TLS_TPREL32:
15550 case BFD_RELOC_MIPS_TLS_TPREL64:
15551 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15552 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15553 case BFD_RELOC_MICROMIPS_TLS_GD:
15554 case BFD_RELOC_MICROMIPS_TLS_LDM:
15555 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15556 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15557 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15558 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15559 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15560 case BFD_RELOC_MIPS16_TLS_GD:
15561 case BFD_RELOC_MIPS16_TLS_LDM:
15562 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15563 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15564 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15565 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15566 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15567 if (!fixP->fx_addsy)
15569 as_bad_where (fixP->fx_file, fixP->fx_line,
15570 _("TLS relocation against a constant"));
15573 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15576 case BFD_RELOC_MIPS_JMP:
15577 case BFD_RELOC_MIPS_SHIFT5:
15578 case BFD_RELOC_MIPS_SHIFT6:
15579 case BFD_RELOC_MIPS_GOT_DISP:
15580 case BFD_RELOC_MIPS_GOT_PAGE:
15581 case BFD_RELOC_MIPS_GOT_OFST:
15582 case BFD_RELOC_MIPS_SUB:
15583 case BFD_RELOC_MIPS_INSERT_A:
15584 case BFD_RELOC_MIPS_INSERT_B:
15585 case BFD_RELOC_MIPS_DELETE:
15586 case BFD_RELOC_MIPS_HIGHEST:
15587 case BFD_RELOC_MIPS_HIGHER:
15588 case BFD_RELOC_MIPS_SCN_DISP:
15589 case BFD_RELOC_MIPS_REL16:
15590 case BFD_RELOC_MIPS_RELGOT:
15591 case BFD_RELOC_MIPS_JALR:
15592 case BFD_RELOC_HI16:
15593 case BFD_RELOC_HI16_S:
15594 case BFD_RELOC_LO16:
15595 case BFD_RELOC_GPREL16:
15596 case BFD_RELOC_MIPS_LITERAL:
15597 case BFD_RELOC_MIPS_CALL16:
15598 case BFD_RELOC_MIPS_GOT16:
15599 case BFD_RELOC_GPREL32:
15600 case BFD_RELOC_MIPS_GOT_HI16:
15601 case BFD_RELOC_MIPS_GOT_LO16:
15602 case BFD_RELOC_MIPS_CALL_HI16:
15603 case BFD_RELOC_MIPS_CALL_LO16:
15604 case BFD_RELOC_MIPS16_GPREL:
15605 case BFD_RELOC_MIPS16_GOT16:
15606 case BFD_RELOC_MIPS16_CALL16:
15607 case BFD_RELOC_MIPS16_HI16:
15608 case BFD_RELOC_MIPS16_HI16_S:
15609 case BFD_RELOC_MIPS16_LO16:
15610 case BFD_RELOC_MIPS16_JMP:
15611 case BFD_RELOC_MICROMIPS_JMP:
15612 case BFD_RELOC_MICROMIPS_GOT_DISP:
15613 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15614 case BFD_RELOC_MICROMIPS_GOT_OFST:
15615 case BFD_RELOC_MICROMIPS_SUB:
15616 case BFD_RELOC_MICROMIPS_HIGHEST:
15617 case BFD_RELOC_MICROMIPS_HIGHER:
15618 case BFD_RELOC_MICROMIPS_SCN_DISP:
15619 case BFD_RELOC_MICROMIPS_JALR:
15620 case BFD_RELOC_MICROMIPS_HI16:
15621 case BFD_RELOC_MICROMIPS_HI16_S:
15622 case BFD_RELOC_MICROMIPS_LO16:
15623 case BFD_RELOC_MICROMIPS_GPREL16:
15624 case BFD_RELOC_MICROMIPS_LITERAL:
15625 case BFD_RELOC_MICROMIPS_CALL16:
15626 case BFD_RELOC_MICROMIPS_GOT16:
15627 case BFD_RELOC_MICROMIPS_GOT_HI16:
15628 case BFD_RELOC_MICROMIPS_GOT_LO16:
15629 case BFD_RELOC_MICROMIPS_CALL_HI16:
15630 case BFD_RELOC_MICROMIPS_CALL_LO16:
15635 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15637 insn = read_reloc_insn (buf, fixP->fx_r_type);
15638 if (mips16_reloc_p (fixP->fx_r_type))
15639 insn |= mips16_immed_extend (value, 16);
15641 insn |= (value & 0xffff);
15642 write_reloc_insn (buf, fixP->fx_r_type, insn);
15645 as_bad_where (fixP->fx_file, fixP->fx_line,
15646 _("Unsupported constant in relocation"));
15651 /* This is handled like BFD_RELOC_32, but we output a sign
15652 extended value if we are only 32 bits. */
15655 if (8 <= sizeof (valueT))
15656 md_number_to_chars (buf, *valP, 8);
15661 if ((*valP & 0x80000000) != 0)
15665 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15666 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15671 case BFD_RELOC_RVA:
15674 /* If we are deleting this reloc entry, we must fill in the
15675 value now. This can happen if we have a .word which is not
15676 resolved when it appears but is later defined. */
15678 md_number_to_chars (buf, *valP, fixP->fx_size);
15681 case BFD_RELOC_16_PCREL_S2:
15682 if ((*valP & 0x3) != 0)
15683 as_bad_where (fixP->fx_file, fixP->fx_line,
15684 _("Branch to misaligned address (%lx)"), (long) *valP);
15686 /* We need to save the bits in the instruction since fixup_segment()
15687 might be deleting the relocation entry (i.e., a branch within
15688 the current segment). */
15689 if (! fixP->fx_done)
15692 /* Update old instruction data. */
15693 insn = read_insn (buf);
15695 if (*valP + 0x20000 <= 0x3ffff)
15697 insn |= (*valP >> 2) & 0xffff;
15698 write_insn (buf, insn);
15700 else if (mips_pic == NO_PIC
15702 && fixP->fx_frag->fr_address >= text_section->vma
15703 && (fixP->fx_frag->fr_address
15704 < text_section->vma + bfd_get_section_size (text_section))
15705 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15706 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15707 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15709 /* The branch offset is too large. If this is an
15710 unconditional branch, and we are not generating PIC code,
15711 we can convert it to an absolute jump instruction. */
15712 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15713 insn = 0x0c000000; /* jal */
15715 insn = 0x08000000; /* j */
15716 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15718 fixP->fx_addsy = section_symbol (text_section);
15719 *valP += md_pcrel_from (fixP);
15720 write_insn (buf, insn);
15724 /* If we got here, we have branch-relaxation disabled,
15725 and there's nothing we can do to fix this instruction
15726 without turning it into a longer sequence. */
15727 as_bad_where (fixP->fx_file, fixP->fx_line,
15728 _("Branch out of range"));
15732 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15733 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15734 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15735 /* We adjust the offset back to even. */
15736 if ((*valP & 0x1) != 0)
15739 if (! fixP->fx_done)
15742 /* Should never visit here, because we keep the relocation. */
15746 case BFD_RELOC_VTABLE_INHERIT:
15749 && !S_IS_DEFINED (fixP->fx_addsy)
15750 && !S_IS_WEAK (fixP->fx_addsy))
15751 S_SET_WEAK (fixP->fx_addsy);
15754 case BFD_RELOC_VTABLE_ENTRY:
15762 /* Remember value for tc_gen_reloc. */
15763 fixP->fx_addnumber = *valP;
15773 name = input_line_pointer;
15774 c = get_symbol_end ();
15775 p = (symbolS *) symbol_find_or_make (name);
15776 *input_line_pointer = c;
15780 /* Align the current frag to a given power of two. If a particular
15781 fill byte should be used, FILL points to an integer that contains
15782 that byte, otherwise FILL is null.
15784 This function used to have the comment:
15786 The MIPS assembler also automatically adjusts any preceding label.
15788 The implementation therefore applied the adjustment to a maximum of
15789 one label. However, other label adjustments are applied to batches
15790 of labels, and adjusting just one caused problems when new labels
15791 were added for the sake of debugging or unwind information.
15792 We therefore adjust all preceding labels (given as LABELS) instead. */
15795 mips_align (int to, int *fill, struct insn_label_list *labels)
15797 mips_emit_delays ();
15798 mips_record_compressed_mode ();
15799 if (fill == NULL && subseg_text_p (now_seg))
15800 frag_align_code (to, 0);
15802 frag_align (to, fill ? *fill : 0, 0);
15803 record_alignment (now_seg, to);
15804 mips_move_labels (labels, FALSE);
15807 /* Align to a given power of two. .align 0 turns off the automatic
15808 alignment used by the data creating pseudo-ops. */
15811 s_align (int x ATTRIBUTE_UNUSED)
15813 int temp, fill_value, *fill_ptr;
15814 long max_alignment = 28;
15816 /* o Note that the assembler pulls down any immediately preceding label
15817 to the aligned address.
15818 o It's not documented but auto alignment is reinstated by
15819 a .align pseudo instruction.
15820 o Note also that after auto alignment is turned off the mips assembler
15821 issues an error on attempt to assemble an improperly aligned data item.
15824 temp = get_absolute_expression ();
15825 if (temp > max_alignment)
15826 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
15829 as_warn (_("Alignment negative: 0 assumed."));
15832 if (*input_line_pointer == ',')
15834 ++input_line_pointer;
15835 fill_value = get_absolute_expression ();
15836 fill_ptr = &fill_value;
15842 segment_info_type *si = seg_info (now_seg);
15843 struct insn_label_list *l = si->label_list;
15844 /* Auto alignment should be switched on by next section change. */
15846 mips_align (temp, fill_ptr, l);
15853 demand_empty_rest_of_line ();
15857 s_change_sec (int sec)
15862 /* The ELF backend needs to know that we are changing sections, so
15863 that .previous works correctly. We could do something like check
15864 for an obj_section_change_hook macro, but that might be confusing
15865 as it would not be appropriate to use it in the section changing
15866 functions in read.c, since obj-elf.c intercepts those. FIXME:
15867 This should be cleaner, somehow. */
15869 obj_elf_section_change_hook ();
15872 mips_emit_delays ();
15883 subseg_set (bss_section, (subsegT) get_absolute_expression ());
15884 demand_empty_rest_of_line ();
15888 seg = subseg_new (RDATA_SECTION_NAME,
15889 (subsegT) get_absolute_expression ());
15892 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
15893 | SEC_READONLY | SEC_RELOC
15895 if (strncmp (TARGET_OS, "elf", 3) != 0)
15896 record_alignment (seg, 4);
15898 demand_empty_rest_of_line ();
15902 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
15905 bfd_set_section_flags (stdoutput, seg,
15906 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
15907 if (strncmp (TARGET_OS, "elf", 3) != 0)
15908 record_alignment (seg, 4);
15910 demand_empty_rest_of_line ();
15914 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
15917 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
15918 if (strncmp (TARGET_OS, "elf", 3) != 0)
15919 record_alignment (seg, 4);
15921 demand_empty_rest_of_line ();
15929 s_change_section (int ignore ATTRIBUTE_UNUSED)
15932 char *section_name;
15937 int section_entry_size;
15938 int section_alignment;
15943 section_name = input_line_pointer;
15944 c = get_symbol_end ();
15946 next_c = *(input_line_pointer + 1);
15948 /* Do we have .section Name<,"flags">? */
15949 if (c != ',' || (c == ',' && next_c == '"'))
15951 /* just after name is now '\0'. */
15952 *input_line_pointer = c;
15953 input_line_pointer = section_name;
15954 obj_elf_section (ignore);
15957 input_line_pointer++;
15959 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
15961 section_type = get_absolute_expression ();
15964 if (*input_line_pointer++ == ',')
15965 section_flag = get_absolute_expression ();
15968 if (*input_line_pointer++ == ',')
15969 section_entry_size = get_absolute_expression ();
15971 section_entry_size = 0;
15972 if (*input_line_pointer++ == ',')
15973 section_alignment = get_absolute_expression ();
15975 section_alignment = 0;
15976 /* FIXME: really ignore? */
15977 (void) section_alignment;
15979 section_name = xstrdup (section_name);
15981 /* When using the generic form of .section (as implemented by obj-elf.c),
15982 there's no way to set the section type to SHT_MIPS_DWARF. Users have
15983 traditionally had to fall back on the more common @progbits instead.
15985 There's nothing really harmful in this, since bfd will correct
15986 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
15987 means that, for backwards compatibility, the special_section entries
15988 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
15990 Even so, we shouldn't force users of the MIPS .section syntax to
15991 incorrectly label the sections as SHT_PROGBITS. The best compromise
15992 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
15993 generic type-checking code. */
15994 if (section_type == SHT_MIPS_DWARF)
15995 section_type = SHT_PROGBITS;
15997 obj_elf_change_section (section_name, section_type, section_flag,
15998 section_entry_size, 0, 0, 0);
16000 if (now_seg->name != section_name)
16001 free (section_name);
16002 #endif /* OBJ_ELF */
16006 mips_enable_auto_align (void)
16012 s_cons (int log_size)
16014 segment_info_type *si = seg_info (now_seg);
16015 struct insn_label_list *l = si->label_list;
16017 mips_emit_delays ();
16018 if (log_size > 0 && auto_align)
16019 mips_align (log_size, 0, l);
16020 cons (1 << log_size);
16021 mips_clear_insn_labels ();
16025 s_float_cons (int type)
16027 segment_info_type *si = seg_info (now_seg);
16028 struct insn_label_list *l = si->label_list;
16030 mips_emit_delays ();
16035 mips_align (3, 0, l);
16037 mips_align (2, 0, l);
16041 mips_clear_insn_labels ();
16044 /* Handle .globl. We need to override it because on Irix 5 you are
16047 where foo is an undefined symbol, to mean that foo should be
16048 considered to be the address of a function. */
16051 s_mips_globl (int x ATTRIBUTE_UNUSED)
16060 name = input_line_pointer;
16061 c = get_symbol_end ();
16062 symbolP = symbol_find_or_make (name);
16063 S_SET_EXTERNAL (symbolP);
16065 *input_line_pointer = c;
16066 SKIP_WHITESPACE ();
16068 /* On Irix 5, every global symbol that is not explicitly labelled as
16069 being a function is apparently labelled as being an object. */
16072 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16073 && (*input_line_pointer != ','))
16078 secname = input_line_pointer;
16079 c = get_symbol_end ();
16080 sec = bfd_get_section_by_name (stdoutput, secname);
16082 as_bad (_("%s: no such section"), secname);
16083 *input_line_pointer = c;
16085 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16086 flag = BSF_FUNCTION;
16089 symbol_get_bfdsym (symbolP)->flags |= flag;
16091 c = *input_line_pointer;
16094 input_line_pointer++;
16095 SKIP_WHITESPACE ();
16096 if (is_end_of_line[(unsigned char) *input_line_pointer])
16102 demand_empty_rest_of_line ();
16106 s_option (int x ATTRIBUTE_UNUSED)
16111 opt = input_line_pointer;
16112 c = get_symbol_end ();
16116 /* FIXME: What does this mean? */
16118 else if (strncmp (opt, "pic", 3) == 0)
16122 i = atoi (opt + 3);
16127 mips_pic = SVR4_PIC;
16128 mips_abicalls = TRUE;
16131 as_bad (_(".option pic%d not supported"), i);
16133 if (mips_pic == SVR4_PIC)
16135 if (g_switch_seen && g_switch_value != 0)
16136 as_warn (_("-G may not be used with SVR4 PIC code"));
16137 g_switch_value = 0;
16138 bfd_set_gp_size (stdoutput, 0);
16142 as_warn (_("Unrecognized option \"%s\""), opt);
16144 *input_line_pointer = c;
16145 demand_empty_rest_of_line ();
16148 /* This structure is used to hold a stack of .set values. */
16150 struct mips_option_stack
16152 struct mips_option_stack *next;
16153 struct mips_set_options options;
16156 static struct mips_option_stack *mips_opts_stack;
16158 /* Handle the .set pseudo-op. */
16161 s_mipsset (int x ATTRIBUTE_UNUSED)
16163 char *name = input_line_pointer, ch;
16165 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16166 ++input_line_pointer;
16167 ch = *input_line_pointer;
16168 *input_line_pointer = '\0';
16170 if (strcmp (name, "reorder") == 0)
16172 if (mips_opts.noreorder)
16175 else if (strcmp (name, "noreorder") == 0)
16177 if (!mips_opts.noreorder)
16178 start_noreorder ();
16180 else if (strncmp (name, "at=", 3) == 0)
16182 char *s = name + 3;
16184 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16185 as_bad (_("Unrecognized register name `%s'"), s);
16187 else if (strcmp (name, "at") == 0)
16189 mips_opts.at = ATREG;
16191 else if (strcmp (name, "noat") == 0)
16193 mips_opts.at = ZERO;
16195 else if (strcmp (name, "macro") == 0)
16197 mips_opts.warn_about_macros = 0;
16199 else if (strcmp (name, "nomacro") == 0)
16201 if (mips_opts.noreorder == 0)
16202 as_bad (_("`noreorder' must be set before `nomacro'"));
16203 mips_opts.warn_about_macros = 1;
16205 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16207 mips_opts.nomove = 0;
16209 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16211 mips_opts.nomove = 1;
16213 else if (strcmp (name, "bopt") == 0)
16215 mips_opts.nobopt = 0;
16217 else if (strcmp (name, "nobopt") == 0)
16219 mips_opts.nobopt = 1;
16221 else if (strcmp (name, "gp=default") == 0)
16222 mips_opts.gp32 = file_mips_gp32;
16223 else if (strcmp (name, "gp=32") == 0)
16224 mips_opts.gp32 = 1;
16225 else if (strcmp (name, "gp=64") == 0)
16227 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16228 as_warn (_("%s isa does not support 64-bit registers"),
16229 mips_cpu_info_from_isa (mips_opts.isa)->name);
16230 mips_opts.gp32 = 0;
16232 else if (strcmp (name, "fp=default") == 0)
16233 mips_opts.fp32 = file_mips_fp32;
16234 else if (strcmp (name, "fp=32") == 0)
16235 mips_opts.fp32 = 1;
16236 else if (strcmp (name, "fp=64") == 0)
16238 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16239 as_warn (_("%s isa does not support 64-bit floating point registers"),
16240 mips_cpu_info_from_isa (mips_opts.isa)->name);
16241 mips_opts.fp32 = 0;
16243 else if (strcmp (name, "softfloat") == 0)
16244 mips_opts.soft_float = 1;
16245 else if (strcmp (name, "hardfloat") == 0)
16246 mips_opts.soft_float = 0;
16247 else if (strcmp (name, "singlefloat") == 0)
16248 mips_opts.single_float = 1;
16249 else if (strcmp (name, "doublefloat") == 0)
16250 mips_opts.single_float = 0;
16251 else if (strcmp (name, "mips16") == 0
16252 || strcmp (name, "MIPS-16") == 0)
16254 if (mips_opts.micromips == 1)
16255 as_fatal (_("`mips16' cannot be used with `micromips'"));
16256 mips_opts.mips16 = 1;
16258 else if (strcmp (name, "nomips16") == 0
16259 || strcmp (name, "noMIPS-16") == 0)
16260 mips_opts.mips16 = 0;
16261 else if (strcmp (name, "micromips") == 0)
16263 if (mips_opts.mips16 == 1)
16264 as_fatal (_("`micromips' cannot be used with `mips16'"));
16265 mips_opts.micromips = 1;
16267 else if (strcmp (name, "nomicromips") == 0)
16268 mips_opts.micromips = 0;
16269 else if (strcmp (name, "smartmips") == 0)
16271 if (!ISA_SUPPORTS_SMARTMIPS)
16272 as_warn (_("%s ISA does not support SmartMIPS ASE"),
16273 mips_cpu_info_from_isa (mips_opts.isa)->name);
16274 mips_opts.ase_smartmips = 1;
16276 else if (strcmp (name, "nosmartmips") == 0)
16277 mips_opts.ase_smartmips = 0;
16278 else if (strcmp (name, "mips3d") == 0)
16279 mips_opts.ase_mips3d = 1;
16280 else if (strcmp (name, "nomips3d") == 0)
16281 mips_opts.ase_mips3d = 0;
16282 else if (strcmp (name, "mdmx") == 0)
16283 mips_opts.ase_mdmx = 1;
16284 else if (strcmp (name, "nomdmx") == 0)
16285 mips_opts.ase_mdmx = 0;
16286 else if (strcmp (name, "dsp") == 0)
16288 if (!ISA_SUPPORTS_DSP_ASE)
16289 as_warn (_("%s ISA does not support DSP ASE"),
16290 mips_cpu_info_from_isa (mips_opts.isa)->name);
16291 mips_opts.ase_dsp = 1;
16292 mips_opts.ase_dspr2 = 0;
16294 else if (strcmp (name, "nodsp") == 0)
16296 mips_opts.ase_dsp = 0;
16297 mips_opts.ase_dspr2 = 0;
16299 else if (strcmp (name, "dspr2") == 0)
16301 if (!ISA_SUPPORTS_DSPR2_ASE)
16302 as_warn (_("%s ISA does not support DSP R2 ASE"),
16303 mips_cpu_info_from_isa (mips_opts.isa)->name);
16304 mips_opts.ase_dspr2 = 1;
16305 mips_opts.ase_dsp = 1;
16307 else if (strcmp (name, "nodspr2") == 0)
16309 mips_opts.ase_dspr2 = 0;
16310 mips_opts.ase_dsp = 0;
16312 else if (strcmp (name, "mt") == 0)
16314 if (!ISA_SUPPORTS_MT_ASE)
16315 as_warn (_("%s ISA does not support MT ASE"),
16316 mips_cpu_info_from_isa (mips_opts.isa)->name);
16317 mips_opts.ase_mt = 1;
16319 else if (strcmp (name, "nomt") == 0)
16320 mips_opts.ase_mt = 0;
16321 else if (strcmp (name, "mcu") == 0)
16322 mips_opts.ase_mcu = 1;
16323 else if (strcmp (name, "nomcu") == 0)
16324 mips_opts.ase_mcu = 0;
16325 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16329 /* Permit the user to change the ISA and architecture on the fly.
16330 Needless to say, misuse can cause serious problems. */
16331 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16334 mips_opts.isa = file_mips_isa;
16335 mips_opts.arch = file_mips_arch;
16337 else if (strncmp (name, "arch=", 5) == 0)
16339 const struct mips_cpu_info *p;
16341 p = mips_parse_cpu("internal use", name + 5);
16343 as_bad (_("unknown architecture %s"), name + 5);
16346 mips_opts.arch = p->cpu;
16347 mips_opts.isa = p->isa;
16350 else if (strncmp (name, "mips", 4) == 0)
16352 const struct mips_cpu_info *p;
16354 p = mips_parse_cpu("internal use", name);
16356 as_bad (_("unknown ISA level %s"), name + 4);
16359 mips_opts.arch = p->cpu;
16360 mips_opts.isa = p->isa;
16364 as_bad (_("unknown ISA or architecture %s"), name);
16366 switch (mips_opts.isa)
16374 mips_opts.gp32 = 1;
16375 mips_opts.fp32 = 1;
16382 mips_opts.gp32 = 0;
16383 mips_opts.fp32 = 0;
16386 as_bad (_("unknown ISA level %s"), name + 4);
16391 mips_opts.gp32 = file_mips_gp32;
16392 mips_opts.fp32 = file_mips_fp32;
16395 else if (strcmp (name, "autoextend") == 0)
16396 mips_opts.noautoextend = 0;
16397 else if (strcmp (name, "noautoextend") == 0)
16398 mips_opts.noautoextend = 1;
16399 else if (strcmp (name, "push") == 0)
16401 struct mips_option_stack *s;
16403 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16404 s->next = mips_opts_stack;
16405 s->options = mips_opts;
16406 mips_opts_stack = s;
16408 else if (strcmp (name, "pop") == 0)
16410 struct mips_option_stack *s;
16412 s = mips_opts_stack;
16414 as_bad (_(".set pop with no .set push"));
16417 /* If we're changing the reorder mode we need to handle
16418 delay slots correctly. */
16419 if (s->options.noreorder && ! mips_opts.noreorder)
16420 start_noreorder ();
16421 else if (! s->options.noreorder && mips_opts.noreorder)
16424 mips_opts = s->options;
16425 mips_opts_stack = s->next;
16429 else if (strcmp (name, "sym32") == 0)
16430 mips_opts.sym32 = TRUE;
16431 else if (strcmp (name, "nosym32") == 0)
16432 mips_opts.sym32 = FALSE;
16433 else if (strchr (name, ','))
16435 /* Generic ".set" directive; use the generic handler. */
16436 *input_line_pointer = ch;
16437 input_line_pointer = name;
16443 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16445 *input_line_pointer = ch;
16446 demand_empty_rest_of_line ();
16449 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16450 .option pic2. It means to generate SVR4 PIC calls. */
16453 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16455 mips_pic = SVR4_PIC;
16456 mips_abicalls = TRUE;
16458 if (g_switch_seen && g_switch_value != 0)
16459 as_warn (_("-G may not be used with SVR4 PIC code"));
16460 g_switch_value = 0;
16462 bfd_set_gp_size (stdoutput, 0);
16463 demand_empty_rest_of_line ();
16466 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16467 PIC code. It sets the $gp register for the function based on the
16468 function address, which is in the register named in the argument.
16469 This uses a relocation against _gp_disp, which is handled specially
16470 by the linker. The result is:
16471 lui $gp,%hi(_gp_disp)
16472 addiu $gp,$gp,%lo(_gp_disp)
16473 addu $gp,$gp,.cpload argument
16474 The .cpload argument is normally $25 == $t9.
16476 The -mno-shared option changes this to:
16477 lui $gp,%hi(__gnu_local_gp)
16478 addiu $gp,$gp,%lo(__gnu_local_gp)
16479 and the argument is ignored. This saves an instruction, but the
16480 resulting code is not position independent; it uses an absolute
16481 address for __gnu_local_gp. Thus code assembled with -mno-shared
16482 can go into an ordinary executable, but not into a shared library. */
16485 s_cpload (int ignore ATTRIBUTE_UNUSED)
16491 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16492 .cpload is ignored. */
16493 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16499 if (mips_opts.mips16)
16501 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16502 ignore_rest_of_line ();
16506 /* .cpload should be in a .set noreorder section. */
16507 if (mips_opts.noreorder == 0)
16508 as_warn (_(".cpload not in noreorder section"));
16510 reg = tc_get_register (0);
16512 /* If we need to produce a 64-bit address, we are better off using
16513 the default instruction sequence. */
16514 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16516 ex.X_op = O_symbol;
16517 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16519 ex.X_op_symbol = NULL;
16520 ex.X_add_number = 0;
16522 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16523 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16526 macro_build_lui (&ex, mips_gp_register);
16527 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16528 mips_gp_register, BFD_RELOC_LO16);
16530 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16531 mips_gp_register, reg);
16534 demand_empty_rest_of_line ();
16537 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16538 .cpsetup $reg1, offset|$reg2, label
16540 If offset is given, this results in:
16541 sd $gp, offset($sp)
16542 lui $gp, %hi(%neg(%gp_rel(label)))
16543 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16544 daddu $gp, $gp, $reg1
16546 If $reg2 is given, this results in:
16547 daddu $reg2, $gp, $0
16548 lui $gp, %hi(%neg(%gp_rel(label)))
16549 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16550 daddu $gp, $gp, $reg1
16551 $reg1 is normally $25 == $t9.
16553 The -mno-shared option replaces the last three instructions with
16555 addiu $gp,$gp,%lo(_gp) */
16558 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16560 expressionS ex_off;
16561 expressionS ex_sym;
16564 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16565 We also need NewABI support. */
16566 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16572 if (mips_opts.mips16)
16574 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16575 ignore_rest_of_line ();
16579 reg1 = tc_get_register (0);
16580 SKIP_WHITESPACE ();
16581 if (*input_line_pointer != ',')
16583 as_bad (_("missing argument separator ',' for .cpsetup"));
16587 ++input_line_pointer;
16588 SKIP_WHITESPACE ();
16589 if (*input_line_pointer == '$')
16591 mips_cpreturn_register = tc_get_register (0);
16592 mips_cpreturn_offset = -1;
16596 mips_cpreturn_offset = get_absolute_expression ();
16597 mips_cpreturn_register = -1;
16599 SKIP_WHITESPACE ();
16600 if (*input_line_pointer != ',')
16602 as_bad (_("missing argument separator ',' for .cpsetup"));
16606 ++input_line_pointer;
16607 SKIP_WHITESPACE ();
16608 expression (&ex_sym);
16611 if (mips_cpreturn_register == -1)
16613 ex_off.X_op = O_constant;
16614 ex_off.X_add_symbol = NULL;
16615 ex_off.X_op_symbol = NULL;
16616 ex_off.X_add_number = mips_cpreturn_offset;
16618 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16619 BFD_RELOC_LO16, SP);
16622 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16623 mips_gp_register, 0);
16625 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16627 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16628 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16631 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16632 mips_gp_register, -1, BFD_RELOC_GPREL16,
16633 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16635 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16636 mips_gp_register, reg1);
16642 ex.X_op = O_symbol;
16643 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16644 ex.X_op_symbol = NULL;
16645 ex.X_add_number = 0;
16647 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16648 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16650 macro_build_lui (&ex, mips_gp_register);
16651 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16652 mips_gp_register, BFD_RELOC_LO16);
16657 demand_empty_rest_of_line ();
16661 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16663 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16664 .cplocal is ignored. */
16665 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16671 if (mips_opts.mips16)
16673 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16674 ignore_rest_of_line ();
16678 mips_gp_register = tc_get_register (0);
16679 demand_empty_rest_of_line ();
16682 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16683 offset from $sp. The offset is remembered, and after making a PIC
16684 call $gp is restored from that location. */
16687 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16691 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16692 .cprestore is ignored. */
16693 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16699 if (mips_opts.mips16)
16701 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16702 ignore_rest_of_line ();
16706 mips_cprestore_offset = get_absolute_expression ();
16707 mips_cprestore_valid = 1;
16709 ex.X_op = O_constant;
16710 ex.X_add_symbol = NULL;
16711 ex.X_op_symbol = NULL;
16712 ex.X_add_number = mips_cprestore_offset;
16715 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16716 SP, HAVE_64BIT_ADDRESSES);
16719 demand_empty_rest_of_line ();
16722 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16723 was given in the preceding .cpsetup, it results in:
16724 ld $gp, offset($sp)
16726 If a register $reg2 was given there, it results in:
16727 daddu $gp, $reg2, $0 */
16730 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16734 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16735 We also need NewABI support. */
16736 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16742 if (mips_opts.mips16)
16744 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16745 ignore_rest_of_line ();
16750 if (mips_cpreturn_register == -1)
16752 ex.X_op = O_constant;
16753 ex.X_add_symbol = NULL;
16754 ex.X_op_symbol = NULL;
16755 ex.X_add_number = mips_cpreturn_offset;
16757 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16760 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16761 mips_cpreturn_register, 0);
16764 demand_empty_rest_of_line ();
16767 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16768 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16769 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16770 debug information or MIPS16 TLS. */
16773 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16774 bfd_reloc_code_real_type rtype)
16781 if (ex.X_op != O_symbol)
16783 as_bad (_("Unsupported use of %s"), dirstr);
16784 ignore_rest_of_line ();
16787 p = frag_more (bytes);
16788 md_number_to_chars (p, 0, bytes);
16789 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16790 demand_empty_rest_of_line ();
16791 mips_clear_insn_labels ();
16794 /* Handle .dtprelword. */
16797 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16799 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16802 /* Handle .dtpreldword. */
16805 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16807 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16810 /* Handle .tprelword. */
16813 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16815 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16818 /* Handle .tpreldword. */
16821 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16823 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16826 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16827 code. It sets the offset to use in gp_rel relocations. */
16830 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16832 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16833 We also need NewABI support. */
16834 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16840 mips_gprel_offset = get_absolute_expression ();
16842 demand_empty_rest_of_line ();
16845 /* Handle the .gpword pseudo-op. This is used when generating PIC
16846 code. It generates a 32 bit GP relative reloc. */
16849 s_gpword (int ignore ATTRIBUTE_UNUSED)
16851 segment_info_type *si;
16852 struct insn_label_list *l;
16856 /* When not generating PIC code, this is treated as .word. */
16857 if (mips_pic != SVR4_PIC)
16863 si = seg_info (now_seg);
16864 l = si->label_list;
16865 mips_emit_delays ();
16867 mips_align (2, 0, l);
16870 mips_clear_insn_labels ();
16872 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16874 as_bad (_("Unsupported use of .gpword"));
16875 ignore_rest_of_line ();
16879 md_number_to_chars (p, 0, 4);
16880 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16881 BFD_RELOC_GPREL32);
16883 demand_empty_rest_of_line ();
16887 s_gpdword (int ignore ATTRIBUTE_UNUSED)
16889 segment_info_type *si;
16890 struct insn_label_list *l;
16894 /* When not generating PIC code, this is treated as .dword. */
16895 if (mips_pic != SVR4_PIC)
16901 si = seg_info (now_seg);
16902 l = si->label_list;
16903 mips_emit_delays ();
16905 mips_align (3, 0, l);
16908 mips_clear_insn_labels ();
16910 if (ex.X_op != O_symbol || ex.X_add_number != 0)
16912 as_bad (_("Unsupported use of .gpdword"));
16913 ignore_rest_of_line ();
16917 md_number_to_chars (p, 0, 8);
16918 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
16919 BFD_RELOC_GPREL32)->fx_tcbit = 1;
16921 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
16922 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
16923 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
16925 demand_empty_rest_of_line ();
16928 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
16929 tables in SVR4 PIC code. */
16932 s_cpadd (int ignore ATTRIBUTE_UNUSED)
16936 /* This is ignored when not generating SVR4 PIC code. */
16937 if (mips_pic != SVR4_PIC)
16943 /* Add $gp to the register named as an argument. */
16945 reg = tc_get_register (0);
16946 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
16949 demand_empty_rest_of_line ();
16952 /* Handle the .insn pseudo-op. This marks instruction labels in
16953 mips16/micromips mode. This permits the linker to handle them specially,
16954 such as generating jalx instructions when needed. We also make
16955 them odd for the duration of the assembly, in order to generate the
16956 right sort of code. We will make them even in the adjust_symtab
16957 routine, while leaving them marked. This is convenient for the
16958 debugger and the disassembler. The linker knows to make them odd
16962 s_insn (int ignore ATTRIBUTE_UNUSED)
16964 mips_mark_labels ();
16966 demand_empty_rest_of_line ();
16969 /* Handle a .stabn directive. We need these in order to mark a label
16970 as being a mips16 text label correctly. Sometimes the compiler
16971 will emit a label, followed by a .stabn, and then switch sections.
16972 If the label and .stabn are in mips16 mode, then the label is
16973 really a mips16 text label. */
16976 s_mips_stab (int type)
16979 mips_mark_labels ();
16984 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
16987 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
16994 name = input_line_pointer;
16995 c = get_symbol_end ();
16996 symbolP = symbol_find_or_make (name);
16997 S_SET_WEAK (symbolP);
16998 *input_line_pointer = c;
17000 SKIP_WHITESPACE ();
17002 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17004 if (S_IS_DEFINED (symbolP))
17006 as_bad (_("ignoring attempt to redefine symbol %s"),
17007 S_GET_NAME (symbolP));
17008 ignore_rest_of_line ();
17012 if (*input_line_pointer == ',')
17014 ++input_line_pointer;
17015 SKIP_WHITESPACE ();
17019 if (exp.X_op != O_symbol)
17021 as_bad (_("bad .weakext directive"));
17022 ignore_rest_of_line ();
17025 symbol_set_value_expression (symbolP, &exp);
17028 demand_empty_rest_of_line ();
17031 /* Parse a register string into a number. Called from the ECOFF code
17032 to parse .frame. The argument is non-zero if this is the frame
17033 register, so that we can record it in mips_frame_reg. */
17036 tc_get_register (int frame)
17040 SKIP_WHITESPACE ();
17041 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17045 mips_frame_reg = reg != 0 ? reg : SP;
17046 mips_frame_reg_valid = 1;
17047 mips_cprestore_valid = 0;
17053 md_section_align (asection *seg, valueT addr)
17055 int align = bfd_get_section_alignment (stdoutput, seg);
17059 /* We don't need to align ELF sections to the full alignment.
17060 However, Irix 5 may prefer that we align them at least to a 16
17061 byte boundary. We don't bother to align the sections if we
17062 are targeted for an embedded system. */
17063 if (strncmp (TARGET_OS, "elf", 3) == 0)
17069 return ((addr + (1 << align) - 1) & (-1 << align));
17072 /* Utility routine, called from above as well. If called while the
17073 input file is still being read, it's only an approximation. (For
17074 example, a symbol may later become defined which appeared to be
17075 undefined earlier.) */
17078 nopic_need_relax (symbolS *sym, int before_relaxing)
17083 if (g_switch_value > 0)
17085 const char *symname;
17088 /* Find out whether this symbol can be referenced off the $gp
17089 register. It can be if it is smaller than the -G size or if
17090 it is in the .sdata or .sbss section. Certain symbols can
17091 not be referenced off the $gp, although it appears as though
17093 symname = S_GET_NAME (sym);
17094 if (symname != (const char *) NULL
17095 && (strcmp (symname, "eprol") == 0
17096 || strcmp (symname, "etext") == 0
17097 || strcmp (symname, "_gp") == 0
17098 || strcmp (symname, "edata") == 0
17099 || strcmp (symname, "_fbss") == 0
17100 || strcmp (symname, "_fdata") == 0
17101 || strcmp (symname, "_ftext") == 0
17102 || strcmp (symname, "end") == 0
17103 || strcmp (symname, "_gp_disp") == 0))
17105 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17107 #ifndef NO_ECOFF_DEBUGGING
17108 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17109 && (symbol_get_obj (sym)->ecoff_extern_size
17110 <= g_switch_value))
17112 /* We must defer this decision until after the whole
17113 file has been read, since there might be a .extern
17114 after the first use of this symbol. */
17115 || (before_relaxing
17116 #ifndef NO_ECOFF_DEBUGGING
17117 && symbol_get_obj (sym)->ecoff_extern_size == 0
17119 && S_GET_VALUE (sym) == 0)
17120 || (S_GET_VALUE (sym) != 0
17121 && S_GET_VALUE (sym) <= g_switch_value)))
17125 const char *segname;
17127 segname = segment_name (S_GET_SEGMENT (sym));
17128 gas_assert (strcmp (segname, ".lit8") != 0
17129 && strcmp (segname, ".lit4") != 0);
17130 change = (strcmp (segname, ".sdata") != 0
17131 && strcmp (segname, ".sbss") != 0
17132 && strncmp (segname, ".sdata.", 7) != 0
17133 && strncmp (segname, ".sbss.", 6) != 0
17134 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17135 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17140 /* We are not optimizing for the $gp register. */
17145 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17148 pic_need_relax (symbolS *sym, asection *segtype)
17152 /* Handle the case of a symbol equated to another symbol. */
17153 while (symbol_equated_reloc_p (sym))
17157 /* It's possible to get a loop here in a badly written program. */
17158 n = symbol_get_value_expression (sym)->X_add_symbol;
17164 if (symbol_section_p (sym))
17167 symsec = S_GET_SEGMENT (sym);
17169 /* This must duplicate the test in adjust_reloc_syms. */
17170 return (!bfd_is_und_section (symsec)
17171 && !bfd_is_abs_section (symsec)
17172 && !bfd_is_com_section (symsec)
17173 && !s_is_linkonce (sym, segtype)
17175 /* A global or weak symbol is treated as external. */
17176 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
17182 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17183 extended opcode. SEC is the section the frag is in. */
17186 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17189 const struct mips16_immed_operand *op;
17191 int mintiny, maxtiny;
17195 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17197 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17200 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17201 op = mips16_immed_operands;
17202 while (op->type != type)
17205 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17210 if (type == '<' || type == '>' || type == '[' || type == ']')
17213 maxtiny = 1 << op->nbits;
17218 maxtiny = (1 << op->nbits) - 1;
17223 mintiny = - (1 << (op->nbits - 1));
17224 maxtiny = (1 << (op->nbits - 1)) - 1;
17227 sym_frag = symbol_get_frag (fragp->fr_symbol);
17228 val = S_GET_VALUE (fragp->fr_symbol);
17229 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17235 /* We won't have the section when we are called from
17236 mips_relax_frag. However, we will always have been called
17237 from md_estimate_size_before_relax first. If this is a
17238 branch to a different section, we mark it as such. If SEC is
17239 NULL, and the frag is not marked, then it must be a branch to
17240 the same section. */
17243 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17248 /* Must have been called from md_estimate_size_before_relax. */
17251 fragp->fr_subtype =
17252 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17254 /* FIXME: We should support this, and let the linker
17255 catch branches and loads that are out of range. */
17256 as_bad_where (fragp->fr_file, fragp->fr_line,
17257 _("unsupported PC relative reference to different section"));
17261 if (fragp != sym_frag && sym_frag->fr_address == 0)
17262 /* Assume non-extended on the first relaxation pass.
17263 The address we have calculated will be bogus if this is
17264 a forward branch to another frag, as the forward frag
17265 will have fr_address == 0. */
17269 /* In this case, we know for sure that the symbol fragment is in
17270 the same section. If the relax_marker of the symbol fragment
17271 differs from the relax_marker of this fragment, we have not
17272 yet adjusted the symbol fragment fr_address. We want to add
17273 in STRETCH in order to get a better estimate of the address.
17274 This particularly matters because of the shift bits. */
17276 && sym_frag->relax_marker != fragp->relax_marker)
17280 /* Adjust stretch for any alignment frag. Note that if have
17281 been expanding the earlier code, the symbol may be
17282 defined in what appears to be an earlier frag. FIXME:
17283 This doesn't handle the fr_subtype field, which specifies
17284 a maximum number of bytes to skip when doing an
17286 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17288 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17291 stretch = - ((- stretch)
17292 & ~ ((1 << (int) f->fr_offset) - 1));
17294 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17303 addr = fragp->fr_address + fragp->fr_fix;
17305 /* The base address rules are complicated. The base address of
17306 a branch is the following instruction. The base address of a
17307 PC relative load or add is the instruction itself, but if it
17308 is in a delay slot (in which case it can not be extended) use
17309 the address of the instruction whose delay slot it is in. */
17310 if (type == 'p' || type == 'q')
17314 /* If we are currently assuming that this frag should be
17315 extended, then, the current address is two bytes
17317 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17320 /* Ignore the low bit in the target, since it will be set
17321 for a text label. */
17322 if ((val & 1) != 0)
17325 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17327 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17330 val -= addr & ~ ((1 << op->shift) - 1);
17332 /* Branch offsets have an implicit 0 in the lowest bit. */
17333 if (type == 'p' || type == 'q')
17336 /* If any of the shifted bits are set, we must use an extended
17337 opcode. If the address depends on the size of this
17338 instruction, this can lead to a loop, so we arrange to always
17339 use an extended opcode. We only check this when we are in
17340 the main relaxation loop, when SEC is NULL. */
17341 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17343 fragp->fr_subtype =
17344 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17348 /* If we are about to mark a frag as extended because the value
17349 is precisely maxtiny + 1, then there is a chance of an
17350 infinite loop as in the following code:
17355 In this case when the la is extended, foo is 0x3fc bytes
17356 away, so the la can be shrunk, but then foo is 0x400 away, so
17357 the la must be extended. To avoid this loop, we mark the
17358 frag as extended if it was small, and is about to become
17359 extended with a value of maxtiny + 1. */
17360 if (val == ((maxtiny + 1) << op->shift)
17361 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17364 fragp->fr_subtype =
17365 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17369 else if (symsec != absolute_section && sec != NULL)
17370 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17372 if ((val & ((1 << op->shift) - 1)) != 0
17373 || val < (mintiny << op->shift)
17374 || val > (maxtiny << op->shift))
17380 /* Compute the length of a branch sequence, and adjust the
17381 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17382 worst-case length is computed, with UPDATE being used to indicate
17383 whether an unconditional (-1), branch-likely (+1) or regular (0)
17384 branch is to be computed. */
17386 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17388 bfd_boolean toofar;
17392 && S_IS_DEFINED (fragp->fr_symbol)
17393 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17398 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17400 addr = fragp->fr_address + fragp->fr_fix + 4;
17404 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17407 /* If the symbol is not defined or it's in a different segment,
17408 assume the user knows what's going on and emit a short
17414 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17416 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17417 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17418 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17419 RELAX_BRANCH_LINK (fragp->fr_subtype),
17425 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17428 if (mips_pic != NO_PIC)
17430 /* Additional space for PIC loading of target address. */
17432 if (mips_opts.isa == ISA_MIPS1)
17433 /* Additional space for $at-stabilizing nop. */
17437 /* If branch is conditional. */
17438 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17445 /* Compute the length of a branch sequence, and adjust the
17446 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17447 worst-case length is computed, with UPDATE being used to indicate
17448 whether an unconditional (-1), or regular (0) branch is to be
17452 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17454 bfd_boolean toofar;
17458 && S_IS_DEFINED (fragp->fr_symbol)
17459 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17464 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17465 /* Ignore the low bit in the target, since it will be set
17466 for a text label. */
17467 if ((val & 1) != 0)
17470 addr = fragp->fr_address + fragp->fr_fix + 4;
17474 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17477 /* If the symbol is not defined or it's in a different segment,
17478 assume the user knows what's going on and emit a short
17484 if (fragp && update
17485 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17486 fragp->fr_subtype = (toofar
17487 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17488 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17493 bfd_boolean compact_known = fragp != NULL;
17494 bfd_boolean compact = FALSE;
17495 bfd_boolean uncond;
17498 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17500 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17502 uncond = update < 0;
17504 /* If label is out of range, we turn branch <br>:
17506 <br> label # 4 bytes
17512 nop # 2 bytes if compact && !PIC
17515 if (mips_pic == NO_PIC && (!compact_known || compact))
17518 /* If assembling PIC code, we further turn:
17524 lw/ld at, %got(label)(gp) # 4 bytes
17525 d/addiu at, %lo(label) # 4 bytes
17528 if (mips_pic != NO_PIC)
17531 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17533 <brneg> 0f # 4 bytes
17534 nop # 2 bytes if !compact
17537 length += (compact_known && compact) ? 4 : 6;
17543 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17544 bit accordingly. */
17547 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17549 bfd_boolean toofar;
17552 && S_IS_DEFINED (fragp->fr_symbol)
17553 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17559 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17560 /* Ignore the low bit in the target, since it will be set
17561 for a text label. */
17562 if ((val & 1) != 0)
17565 /* Assume this is a 2-byte branch. */
17566 addr = fragp->fr_address + fragp->fr_fix + 2;
17568 /* We try to avoid the infinite loop by not adding 2 more bytes for
17573 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17575 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17576 else if (type == 'E')
17577 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17582 /* If the symbol is not defined or it's in a different segment,
17583 we emit a normal 32-bit branch. */
17586 if (fragp && update
17587 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17589 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17590 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17598 /* Estimate the size of a frag before relaxing. Unless this is the
17599 mips16, we are not really relaxing here, and the final size is
17600 encoded in the subtype information. For the mips16, we have to
17601 decide whether we are using an extended opcode or not. */
17604 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17608 if (RELAX_BRANCH_P (fragp->fr_subtype))
17611 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17613 return fragp->fr_var;
17616 if (RELAX_MIPS16_P (fragp->fr_subtype))
17617 /* We don't want to modify the EXTENDED bit here; it might get us
17618 into infinite loops. We change it only in mips_relax_frag(). */
17619 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17621 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17625 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17626 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17627 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17628 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17629 fragp->fr_var = length;
17634 if (mips_pic == NO_PIC)
17635 change = nopic_need_relax (fragp->fr_symbol, 0);
17636 else if (mips_pic == SVR4_PIC)
17637 change = pic_need_relax (fragp->fr_symbol, segtype);
17638 else if (mips_pic == VXWORKS_PIC)
17639 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17646 fragp->fr_subtype |= RELAX_USE_SECOND;
17647 return -RELAX_FIRST (fragp->fr_subtype);
17650 return -RELAX_SECOND (fragp->fr_subtype);
17653 /* This is called to see whether a reloc against a defined symbol
17654 should be converted into a reloc against a section. */
17657 mips_fix_adjustable (fixS *fixp)
17659 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17660 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17663 if (fixp->fx_addsy == NULL)
17666 /* If symbol SYM is in a mergeable section, relocations of the form
17667 SYM + 0 can usually be made section-relative. The mergeable data
17668 is then identified by the section offset rather than by the symbol.
17670 However, if we're generating REL LO16 relocations, the offset is split
17671 between the LO16 and parterning high part relocation. The linker will
17672 need to recalculate the complete offset in order to correctly identify
17675 The linker has traditionally not looked for the parterning high part
17676 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17677 placed anywhere. Rather than break backwards compatibility by changing
17678 this, it seems better not to force the issue, and instead keep the
17679 original symbol. This will work with either linker behavior. */
17680 if ((lo16_reloc_p (fixp->fx_r_type)
17681 || reloc_needs_lo_p (fixp->fx_r_type))
17682 && HAVE_IN_PLACE_ADDENDS
17683 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17686 /* There is no place to store an in-place offset for JALR relocations.
17687 Likewise an in-range offset of PC-relative relocations may overflow
17688 the in-place relocatable field if recalculated against the start
17689 address of the symbol's containing section. */
17690 if (HAVE_IN_PLACE_ADDENDS
17691 && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type)))
17695 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17696 to a floating-point stub. The same is true for non-R_MIPS16_26
17697 relocations against MIPS16 functions; in this case, the stub becomes
17698 the function's canonical address.
17700 Floating-point stubs are stored in unique .mips16.call.* or
17701 .mips16.fn.* sections. If a stub T for function F is in section S,
17702 the first relocation in section S must be against F; this is how the
17703 linker determines the target function. All relocations that might
17704 resolve to T must also be against F. We therefore have the following
17705 restrictions, which are given in an intentionally-redundant way:
17707 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17710 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17711 if that stub might be used.
17713 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17716 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17717 that stub might be used.
17719 There is a further restriction:
17721 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17722 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17723 targets with in-place addends; the relocation field cannot
17724 encode the low bit.
17726 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17727 against a MIPS16 symbol. We deal with (5) by by not reducing any
17728 such relocations on REL targets.
17730 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17731 relocation against some symbol R, no relocation against R may be
17732 reduced. (Note that this deals with (2) as well as (1) because
17733 relocations against global symbols will never be reduced on ELF
17734 targets.) This approach is a little simpler than trying to detect
17735 stub sections, and gives the "all or nothing" per-symbol consistency
17736 that we have for MIPS16 symbols. */
17738 && fixp->fx_subsy == NULL
17739 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17740 || *symbol_get_tc (fixp->fx_addsy)
17741 || (HAVE_IN_PLACE_ADDENDS
17742 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17743 && jmp_reloc_p (fixp->fx_r_type))))
17750 /* Translate internal representation of relocation info to BFD target
17754 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17756 static arelent *retval[4];
17758 bfd_reloc_code_real_type code;
17760 memset (retval, 0, sizeof(retval));
17761 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17762 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17763 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17764 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17766 if (fixp->fx_pcrel)
17768 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17769 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17770 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17771 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1);
17773 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17774 Relocations want only the symbol offset. */
17775 reloc->addend = fixp->fx_addnumber + reloc->address;
17778 /* A gruesome hack which is a result of the gruesome gas
17779 reloc handling. What's worse, for COFF (as opposed to
17780 ECOFF), we might need yet another copy of reloc->address.
17781 See bfd_install_relocation. */
17782 reloc->addend += reloc->address;
17786 reloc->addend = fixp->fx_addnumber;
17788 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17789 entry to be used in the relocation's section offset. */
17790 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17792 reloc->address = reloc->addend;
17796 code = fixp->fx_r_type;
17798 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17799 if (reloc->howto == NULL)
17801 as_bad_where (fixp->fx_file, fixp->fx_line,
17802 _("Can not represent %s relocation in this object file format"),
17803 bfd_get_reloc_code_name (code));
17810 /* Relax a machine dependent frag. This returns the amount by which
17811 the current size of the frag should change. */
17814 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
17816 if (RELAX_BRANCH_P (fragp->fr_subtype))
17818 offsetT old_var = fragp->fr_var;
17820 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
17822 return fragp->fr_var - old_var;
17825 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17827 offsetT old_var = fragp->fr_var;
17828 offsetT new_var = 4;
17830 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17831 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
17832 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17833 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
17834 fragp->fr_var = new_var;
17836 return new_var - old_var;
17839 if (! RELAX_MIPS16_P (fragp->fr_subtype))
17842 if (mips16_extended_frag (fragp, NULL, stretch))
17844 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17846 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
17851 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17853 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
17860 /* Convert a machine dependent frag. */
17863 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
17865 if (RELAX_BRANCH_P (fragp->fr_subtype))
17868 unsigned long insn;
17872 buf = fragp->fr_literal + fragp->fr_fix;
17873 insn = read_insn (buf);
17875 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17877 /* We generate a fixup instead of applying it right now
17878 because, if there are linker relaxations, we're going to
17879 need the relocations. */
17880 exp.X_op = O_symbol;
17881 exp.X_add_symbol = fragp->fr_symbol;
17882 exp.X_add_number = fragp->fr_offset;
17884 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
17885 BFD_RELOC_16_PCREL_S2);
17886 fixp->fx_file = fragp->fr_file;
17887 fixp->fx_line = fragp->fr_line;
17889 buf = write_insn (buf, insn);
17895 as_warn_where (fragp->fr_file, fragp->fr_line,
17896 _("Relaxed out-of-range branch into a jump"));
17898 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
17901 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17903 /* Reverse the branch. */
17904 switch ((insn >> 28) & 0xf)
17907 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
17908 have the condition reversed by tweaking a single
17909 bit, and their opcodes all have 0x4???????. */
17910 gas_assert ((insn & 0xf1000000) == 0x41000000);
17911 insn ^= 0x00010000;
17915 /* bltz 0x04000000 bgez 0x04010000
17916 bltzal 0x04100000 bgezal 0x04110000 */
17917 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
17918 insn ^= 0x00010000;
17922 /* beq 0x10000000 bne 0x14000000
17923 blez 0x18000000 bgtz 0x1c000000 */
17924 insn ^= 0x04000000;
17932 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
17934 /* Clear the and-link bit. */
17935 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
17937 /* bltzal 0x04100000 bgezal 0x04110000
17938 bltzall 0x04120000 bgezall 0x04130000 */
17939 insn &= ~0x00100000;
17942 /* Branch over the branch (if the branch was likely) or the
17943 full jump (not likely case). Compute the offset from the
17944 current instruction to branch to. */
17945 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17949 /* How many bytes in instructions we've already emitted? */
17950 i = buf - fragp->fr_literal - fragp->fr_fix;
17951 /* How many bytes in instructions from here to the end? */
17952 i = fragp->fr_var - i;
17954 /* Convert to instruction count. */
17956 /* Branch counts from the next instruction. */
17959 /* Branch over the jump. */
17960 buf = write_insn (buf, insn);
17963 buf = write_insn (buf, 0);
17965 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
17967 /* beql $0, $0, 2f */
17969 /* Compute the PC offset from the current instruction to
17970 the end of the variable frag. */
17971 /* How many bytes in instructions we've already emitted? */
17972 i = buf - fragp->fr_literal - fragp->fr_fix;
17973 /* How many bytes in instructions from here to the end? */
17974 i = fragp->fr_var - i;
17975 /* Convert to instruction count. */
17977 /* Don't decrement i, because we want to branch over the
17981 buf = write_insn (buf, insn);
17982 buf = write_insn (buf, 0);
17986 if (mips_pic == NO_PIC)
17989 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
17990 ? 0x0c000000 : 0x08000000);
17991 exp.X_op = O_symbol;
17992 exp.X_add_symbol = fragp->fr_symbol;
17993 exp.X_add_number = fragp->fr_offset;
17995 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
17996 FALSE, BFD_RELOC_MIPS_JMP);
17997 fixp->fx_file = fragp->fr_file;
17998 fixp->fx_line = fragp->fr_line;
18000 buf = write_insn (buf, insn);
18004 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18006 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18007 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18008 insn |= at << OP_SH_RT;
18009 exp.X_op = O_symbol;
18010 exp.X_add_symbol = fragp->fr_symbol;
18011 exp.X_add_number = fragp->fr_offset;
18013 if (fragp->fr_offset)
18015 exp.X_add_symbol = make_expr_symbol (&exp);
18016 exp.X_add_number = 0;
18019 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18020 FALSE, BFD_RELOC_MIPS_GOT16);
18021 fixp->fx_file = fragp->fr_file;
18022 fixp->fx_line = fragp->fr_line;
18024 buf = write_insn (buf, insn);
18026 if (mips_opts.isa == ISA_MIPS1)
18028 buf = write_insn (buf, 0);
18030 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18031 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18032 insn |= at << OP_SH_RS | at << OP_SH_RT;
18034 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18035 FALSE, BFD_RELOC_LO16);
18036 fixp->fx_file = fragp->fr_file;
18037 fixp->fx_line = fragp->fr_line;
18039 buf = write_insn (buf, insn);
18042 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18046 insn |= at << OP_SH_RS;
18048 buf = write_insn (buf, insn);
18052 fragp->fr_fix += fragp->fr_var;
18053 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18057 /* Relax microMIPS branches. */
18058 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18060 char *buf = fragp->fr_literal + fragp->fr_fix;
18061 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18062 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18063 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18064 bfd_boolean short_ds;
18065 unsigned long insn;
18069 exp.X_op = O_symbol;
18070 exp.X_add_symbol = fragp->fr_symbol;
18071 exp.X_add_number = fragp->fr_offset;
18073 fragp->fr_fix += fragp->fr_var;
18075 /* Handle 16-bit branches that fit or are forced to fit. */
18076 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18078 /* We generate a fixup instead of applying it right now,
18079 because if there is linker relaxation, we're going to
18080 need the relocations. */
18082 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18083 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18084 else if (type == 'E')
18085 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18086 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18090 fixp->fx_file = fragp->fr_file;
18091 fixp->fx_line = fragp->fr_line;
18093 /* These relocations can have an addend that won't fit in
18095 fixp->fx_no_overflow = 1;
18100 /* Handle 32-bit branches that fit or are forced to fit. */
18101 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18102 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18104 /* We generate a fixup instead of applying it right now,
18105 because if there is linker relaxation, we're going to
18106 need the relocations. */
18107 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18108 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18109 fixp->fx_file = fragp->fr_file;
18110 fixp->fx_line = fragp->fr_line;
18116 /* Relax 16-bit branches to 32-bit branches. */
18119 insn = read_compressed_insn (buf, 2);
18121 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18122 insn = 0x94000000; /* beq */
18123 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18125 unsigned long regno;
18127 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18128 regno = micromips_to_32_reg_d_map [regno];
18129 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18130 insn |= regno << MICROMIPSOP_SH_RS;
18135 /* Nothing else to do, just write it out. */
18136 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18137 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18139 buf = write_compressed_insn (buf, insn, 4);
18140 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18145 insn = read_compressed_insn (buf, 4);
18147 /* Relax 32-bit branches to a sequence of instructions. */
18148 as_warn_where (fragp->fr_file, fragp->fr_line,
18149 _("Relaxed out-of-range branch into a jump"));
18151 /* Set the short-delay-slot bit. */
18152 short_ds = al && (insn & 0x02000000) != 0;
18154 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18158 /* Reverse the branch. */
18159 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18160 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18161 insn ^= 0x20000000;
18162 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18163 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18164 || (insn & 0xffe00000) == 0x40800000 /* blez */
18165 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18166 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18167 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18168 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18169 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18170 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18171 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18172 insn ^= 0x00400000;
18173 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18174 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18175 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18176 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18177 insn ^= 0x00200000;
18183 /* Clear the and-link and short-delay-slot bits. */
18184 gas_assert ((insn & 0xfda00000) == 0x40200000);
18186 /* bltzal 0x40200000 bgezal 0x40600000 */
18187 /* bltzals 0x42200000 bgezals 0x42600000 */
18188 insn &= ~0x02200000;
18191 /* Make a label at the end for use with the branch. */
18192 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18193 micromips_label_inc ();
18194 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
18196 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18200 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18201 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18202 fixp->fx_file = fragp->fr_file;
18203 fixp->fx_line = fragp->fr_line;
18205 /* Branch over the jump. */
18206 buf = write_compressed_insn (buf, insn, 4);
18209 buf = write_compressed_insn (buf, 0x0c00, 2);
18212 if (mips_pic == NO_PIC)
18214 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18216 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18217 insn = al ? jal : 0xd4000000;
18219 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18220 BFD_RELOC_MICROMIPS_JMP);
18221 fixp->fx_file = fragp->fr_file;
18222 fixp->fx_line = fragp->fr_line;
18224 buf = write_compressed_insn (buf, insn, 4);
18227 buf = write_compressed_insn (buf, 0x0c00, 2);
18231 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18232 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18233 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18235 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18236 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18237 insn |= at << MICROMIPSOP_SH_RT;
18239 if (exp.X_add_number)
18241 exp.X_add_symbol = make_expr_symbol (&exp);
18242 exp.X_add_number = 0;
18245 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18246 BFD_RELOC_MICROMIPS_GOT16);
18247 fixp->fx_file = fragp->fr_file;
18248 fixp->fx_line = fragp->fr_line;
18250 buf = write_compressed_insn (buf, insn, 4);
18252 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18253 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18254 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18256 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18257 BFD_RELOC_MICROMIPS_LO16);
18258 fixp->fx_file = fragp->fr_file;
18259 fixp->fx_line = fragp->fr_line;
18261 buf = write_compressed_insn (buf, insn, 4);
18263 /* jr/jrc/jalr/jalrs $at */
18264 insn = al ? jalr : jr;
18265 insn |= at << MICROMIPSOP_SH_MJ;
18267 buf = write_compressed_insn (buf, insn, 2);
18270 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18274 if (RELAX_MIPS16_P (fragp->fr_subtype))
18277 const struct mips16_immed_operand *op;
18280 unsigned int user_length, length;
18281 unsigned long insn;
18284 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18285 op = mips16_immed_operands;
18286 while (op->type != type)
18289 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18290 val = resolve_symbol_value (fragp->fr_symbol);
18295 addr = fragp->fr_address + fragp->fr_fix;
18297 /* The rules for the base address of a PC relative reloc are
18298 complicated; see mips16_extended_frag. */
18299 if (type == 'p' || type == 'q')
18304 /* Ignore the low bit in the target, since it will be
18305 set for a text label. */
18306 if ((val & 1) != 0)
18309 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18311 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18314 addr &= ~ (addressT) ((1 << op->shift) - 1);
18317 /* Make sure the section winds up with the alignment we have
18320 record_alignment (asec, op->shift);
18324 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18325 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18326 as_warn_where (fragp->fr_file, fragp->fr_line,
18327 _("extended instruction in delay slot"));
18329 buf = fragp->fr_literal + fragp->fr_fix;
18331 insn = read_compressed_insn (buf, 2);
18333 insn |= MIPS16_EXTEND;
18335 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18337 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18342 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18343 BFD_RELOC_UNUSED, val, user_length, &insn);
18345 length = (ext ? 4 : 2);
18346 gas_assert (mips16_opcode_length (insn) == length);
18347 write_compressed_insn (buf, insn, length);
18348 fragp->fr_fix += length;
18352 relax_substateT subtype = fragp->fr_subtype;
18353 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18354 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18358 first = RELAX_FIRST (subtype);
18359 second = RELAX_SECOND (subtype);
18360 fixp = (fixS *) fragp->fr_opcode;
18362 /* If the delay slot chosen does not match the size of the instruction,
18363 then emit a warning. */
18364 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18365 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18370 s = subtype & (RELAX_DELAY_SLOT_16BIT
18371 | RELAX_DELAY_SLOT_SIZE_FIRST
18372 | RELAX_DELAY_SLOT_SIZE_SECOND);
18373 msg = macro_warning (s);
18375 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18379 /* Possibly emit a warning if we've chosen the longer option. */
18380 if (use_second == second_longer)
18386 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18387 msg = macro_warning (s);
18389 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18393 /* Go through all the fixups for the first sequence. Disable them
18394 (by marking them as done) if we're going to use the second
18395 sequence instead. */
18397 && fixp->fx_frag == fragp
18398 && fixp->fx_where < fragp->fr_fix - second)
18400 if (subtype & RELAX_USE_SECOND)
18402 fixp = fixp->fx_next;
18405 /* Go through the fixups for the second sequence. Disable them if
18406 we're going to use the first sequence, otherwise adjust their
18407 addresses to account for the relaxation. */
18408 while (fixp && fixp->fx_frag == fragp)
18410 if (subtype & RELAX_USE_SECOND)
18411 fixp->fx_where -= first;
18414 fixp = fixp->fx_next;
18417 /* Now modify the frag contents. */
18418 if (subtype & RELAX_USE_SECOND)
18422 start = fragp->fr_literal + fragp->fr_fix - first - second;
18423 memmove (start, start + first, second);
18424 fragp->fr_fix -= first;
18427 fragp->fr_fix -= second;
18433 /* This function is called after the relocs have been generated.
18434 We've been storing mips16 text labels as odd. Here we convert them
18435 back to even for the convenience of the debugger. */
18438 mips_frob_file_after_relocs (void)
18441 unsigned int count, i;
18446 syms = bfd_get_outsymbols (stdoutput);
18447 count = bfd_get_symcount (stdoutput);
18448 for (i = 0; i < count; i++, syms++)
18449 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18450 && ((*syms)->value & 1) != 0)
18452 (*syms)->value &= ~1;
18453 /* If the symbol has an odd size, it was probably computed
18454 incorrectly, so adjust that as well. */
18455 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18456 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18462 /* This function is called whenever a label is defined, including fake
18463 labels instantiated off the dot special symbol. It is used when
18464 handling branch delays; if a branch has a label, we assume we cannot
18465 move it. This also bumps the value of the symbol by 1 in compressed
18469 mips_record_label (symbolS *sym)
18471 segment_info_type *si = seg_info (now_seg);
18472 struct insn_label_list *l;
18474 if (free_insn_labels == NULL)
18475 l = (struct insn_label_list *) xmalloc (sizeof *l);
18478 l = free_insn_labels;
18479 free_insn_labels = l->next;
18483 l->next = si->label_list;
18484 si->label_list = l;
18487 /* This function is called as tc_frob_label() whenever a label is defined
18488 and adds a DWARF-2 record we only want for true labels. */
18491 mips_define_label (symbolS *sym)
18493 mips_record_label (sym);
18495 dwarf2_emit_label (sym);
18499 /* This function is called by tc_new_dot_label whenever a new dot symbol
18503 mips_add_dot_label (symbolS *sym)
18505 mips_record_label (sym);
18506 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18507 mips_compressed_mark_label (sym);
18510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
18512 /* Some special processing for a MIPS ELF file. */
18515 mips_elf_final_processing (void)
18517 /* Write out the register information. */
18518 if (mips_abi != N64_ABI)
18522 s.ri_gprmask = mips_gprmask;
18523 s.ri_cprmask[0] = mips_cprmask[0];
18524 s.ri_cprmask[1] = mips_cprmask[1];
18525 s.ri_cprmask[2] = mips_cprmask[2];
18526 s.ri_cprmask[3] = mips_cprmask[3];
18527 /* The gp_value field is set by the MIPS ELF backend. */
18529 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18530 ((Elf32_External_RegInfo *)
18531 mips_regmask_frag));
18535 Elf64_Internal_RegInfo s;
18537 s.ri_gprmask = mips_gprmask;
18539 s.ri_cprmask[0] = mips_cprmask[0];
18540 s.ri_cprmask[1] = mips_cprmask[1];
18541 s.ri_cprmask[2] = mips_cprmask[2];
18542 s.ri_cprmask[3] = mips_cprmask[3];
18543 /* The gp_value field is set by the MIPS ELF backend. */
18545 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18546 ((Elf64_External_RegInfo *)
18547 mips_regmask_frag));
18550 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18551 sort of BFD interface for this. */
18552 if (mips_any_noreorder)
18553 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18554 if (mips_pic != NO_PIC)
18556 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18557 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18560 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18562 /* Set MIPS ELF flags for ASEs. */
18563 /* We may need to define a new flag for DSP ASE, and set this flag when
18564 file_ase_dsp is true. */
18565 /* Same for DSP R2. */
18566 /* We may need to define a new flag for MT ASE, and set this flag when
18567 file_ase_mt is true. */
18568 if (file_ase_mips16)
18569 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18570 if (file_ase_micromips)
18571 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18572 #if 0 /* XXX FIXME */
18573 if (file_ase_mips3d)
18574 elf_elfheader (stdoutput)->e_flags |= ???;
18577 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18579 /* Set the MIPS ELF ABI flags. */
18580 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18581 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18582 else if (mips_abi == O64_ABI)
18583 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18584 else if (mips_abi == EABI_ABI)
18586 if (!file_mips_gp32)
18587 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18589 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18591 else if (mips_abi == N32_ABI)
18592 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18594 /* Nothing to do for N64_ABI. */
18596 if (mips_32bitmode)
18597 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18599 #if 0 /* XXX FIXME */
18600 /* 32 bit code with 64 bit FP registers. */
18601 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18602 elf_elfheader (stdoutput)->e_flags |= ???;
18606 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
18608 typedef struct proc {
18610 symbolS *func_end_sym;
18611 unsigned long reg_mask;
18612 unsigned long reg_offset;
18613 unsigned long fpreg_mask;
18614 unsigned long fpreg_offset;
18615 unsigned long frame_offset;
18616 unsigned long frame_reg;
18617 unsigned long pc_reg;
18620 static procS cur_proc;
18621 static procS *cur_proc_ptr;
18622 static int numprocs;
18624 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18625 as "2", and a normal nop as "0". */
18627 #define NOP_OPCODE_MIPS 0
18628 #define NOP_OPCODE_MIPS16 1
18629 #define NOP_OPCODE_MICROMIPS 2
18632 mips_nop_opcode (void)
18634 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18635 return NOP_OPCODE_MICROMIPS;
18636 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18637 return NOP_OPCODE_MIPS16;
18639 return NOP_OPCODE_MIPS;
18642 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18643 32-bit microMIPS NOPs here (if applicable). */
18646 mips_handle_align (fragS *fragp)
18650 int bytes, size, excess;
18653 if (fragp->fr_type != rs_align_code)
18656 p = fragp->fr_literal + fragp->fr_fix;
18658 switch (nop_opcode)
18660 case NOP_OPCODE_MICROMIPS:
18661 opcode = micromips_nop32_insn.insn_opcode;
18664 case NOP_OPCODE_MIPS16:
18665 opcode = mips16_nop_insn.insn_opcode;
18668 case NOP_OPCODE_MIPS:
18670 opcode = nop_insn.insn_opcode;
18675 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18676 excess = bytes % size;
18678 /* Handle the leading part if we're not inserting a whole number of
18679 instructions, and make it the end of the fixed part of the frag.
18680 Try to fit in a short microMIPS NOP if applicable and possible,
18681 and use zeroes otherwise. */
18682 gas_assert (excess < 4);
18683 fragp->fr_fix += excess;
18688 /* Fall through. */
18690 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18692 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18696 /* Fall through. */
18699 /* Fall through. */
18704 md_number_to_chars (p, opcode, size);
18705 fragp->fr_var = size;
18709 md_obj_begin (void)
18716 /* Check for premature end, nesting errors, etc. */
18718 as_warn (_("missing .end at end of assembly"));
18727 if (*input_line_pointer == '-')
18729 ++input_line_pointer;
18732 if (!ISDIGIT (*input_line_pointer))
18733 as_bad (_("expected simple number"));
18734 if (input_line_pointer[0] == '0')
18736 if (input_line_pointer[1] == 'x')
18738 input_line_pointer += 2;
18739 while (ISXDIGIT (*input_line_pointer))
18742 val |= hex_value (*input_line_pointer++);
18744 return negative ? -val : val;
18748 ++input_line_pointer;
18749 while (ISDIGIT (*input_line_pointer))
18752 val |= *input_line_pointer++ - '0';
18754 return negative ? -val : val;
18757 if (!ISDIGIT (*input_line_pointer))
18759 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18760 *input_line_pointer, *input_line_pointer);
18761 as_warn (_("invalid number"));
18764 while (ISDIGIT (*input_line_pointer))
18767 val += *input_line_pointer++ - '0';
18769 return negative ? -val : val;
18772 /* The .file directive; just like the usual .file directive, but there
18773 is an initial number which is the ECOFF file index. In the non-ECOFF
18774 case .file implies DWARF-2. */
18777 s_mips_file (int x ATTRIBUTE_UNUSED)
18779 static int first_file_directive = 0;
18781 if (ECOFF_DEBUGGING)
18790 filename = dwarf2_directive_file (0);
18792 /* Versions of GCC up to 3.1 start files with a ".file"
18793 directive even for stabs output. Make sure that this
18794 ".file" is handled. Note that you need a version of GCC
18795 after 3.1 in order to support DWARF-2 on MIPS. */
18796 if (filename != NULL && ! first_file_directive)
18798 (void) new_logical_line (filename, -1);
18799 s_app_file_string (filename, 0);
18801 first_file_directive = 1;
18805 /* The .loc directive, implying DWARF-2. */
18808 s_mips_loc (int x ATTRIBUTE_UNUSED)
18810 if (!ECOFF_DEBUGGING)
18811 dwarf2_directive_loc (0);
18814 /* The .end directive. */
18817 s_mips_end (int x ATTRIBUTE_UNUSED)
18821 /* Following functions need their own .frame and .cprestore directives. */
18822 mips_frame_reg_valid = 0;
18823 mips_cprestore_valid = 0;
18825 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18828 demand_empty_rest_of_line ();
18833 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18834 as_warn (_(".end not in text section"));
18838 as_warn (_(".end directive without a preceding .ent directive."));
18839 demand_empty_rest_of_line ();
18845 gas_assert (S_GET_NAME (p));
18846 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
18847 as_warn (_(".end symbol does not match .ent symbol."));
18849 if (debug_type == DEBUG_STABS)
18850 stabs_generate_asm_endfunc (S_GET_NAME (p),
18854 as_warn (_(".end directive missing or unknown symbol"));
18857 /* Create an expression to calculate the size of the function. */
18858 if (p && cur_proc_ptr)
18860 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
18861 expressionS *exp = xmalloc (sizeof (expressionS));
18864 exp->X_op = O_subtract;
18865 exp->X_add_symbol = symbol_temp_new_now ();
18866 exp->X_op_symbol = p;
18867 exp->X_add_number = 0;
18869 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
18872 /* Generate a .pdr section. */
18873 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
18875 segT saved_seg = now_seg;
18876 subsegT saved_subseg = now_subseg;
18880 #ifdef md_flush_pending_output
18881 md_flush_pending_output ();
18884 gas_assert (pdr_seg);
18885 subseg_set (pdr_seg, 0);
18887 /* Write the symbol. */
18888 exp.X_op = O_symbol;
18889 exp.X_add_symbol = p;
18890 exp.X_add_number = 0;
18891 emit_expr (&exp, 4);
18893 fragp = frag_more (7 * 4);
18895 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
18896 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
18897 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
18898 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
18899 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
18900 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
18901 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
18903 subseg_set (saved_seg, saved_subseg);
18905 #endif /* OBJ_ELF */
18907 cur_proc_ptr = NULL;
18910 /* The .aent and .ent directives. */
18913 s_mips_ent (int aent)
18917 symbolP = get_symbol ();
18918 if (*input_line_pointer == ',')
18919 ++input_line_pointer;
18920 SKIP_WHITESPACE ();
18921 if (ISDIGIT (*input_line_pointer)
18922 || *input_line_pointer == '-')
18925 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
18926 as_warn (_(".ent or .aent not in text section."));
18928 if (!aent && cur_proc_ptr)
18929 as_warn (_("missing .end"));
18933 /* This function needs its own .frame and .cprestore directives. */
18934 mips_frame_reg_valid = 0;
18935 mips_cprestore_valid = 0;
18937 cur_proc_ptr = &cur_proc;
18938 memset (cur_proc_ptr, '\0', sizeof (procS));
18940 cur_proc_ptr->func_sym = symbolP;
18944 if (debug_type == DEBUG_STABS)
18945 stabs_generate_asm_func (S_GET_NAME (symbolP),
18946 S_GET_NAME (symbolP));
18949 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
18951 demand_empty_rest_of_line ();
18954 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
18955 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
18956 s_mips_frame is used so that we can set the PDR information correctly.
18957 We can't use the ecoff routines because they make reference to the ecoff
18958 symbol table (in the mdebug section). */
18961 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
18964 if (IS_ELF && !ECOFF_DEBUGGING)
18968 if (cur_proc_ptr == (procS *) NULL)
18970 as_warn (_(".frame outside of .ent"));
18971 demand_empty_rest_of_line ();
18975 cur_proc_ptr->frame_reg = tc_get_register (1);
18977 SKIP_WHITESPACE ();
18978 if (*input_line_pointer++ != ','
18979 || get_absolute_expression_and_terminator (&val) != ',')
18981 as_warn (_("Bad .frame directive"));
18982 --input_line_pointer;
18983 demand_empty_rest_of_line ();
18987 cur_proc_ptr->frame_offset = val;
18988 cur_proc_ptr->pc_reg = tc_get_register (0);
18990 demand_empty_rest_of_line ();
18993 #endif /* OBJ_ELF */
18997 /* The .fmask and .mask directives. If the mdebug section is present
18998 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
18999 embedded targets, s_mips_mask is used so that we can set the PDR
19000 information correctly. We can't use the ecoff routines because they
19001 make reference to the ecoff symbol table (in the mdebug section). */
19004 s_mips_mask (int reg_type)
19007 if (IS_ELF && !ECOFF_DEBUGGING)
19011 if (cur_proc_ptr == (procS *) NULL)
19013 as_warn (_(".mask/.fmask outside of .ent"));
19014 demand_empty_rest_of_line ();
19018 if (get_absolute_expression_and_terminator (&mask) != ',')
19020 as_warn (_("Bad .mask/.fmask directive"));
19021 --input_line_pointer;
19022 demand_empty_rest_of_line ();
19026 off = get_absolute_expression ();
19028 if (reg_type == 'F')
19030 cur_proc_ptr->fpreg_mask = mask;
19031 cur_proc_ptr->fpreg_offset = off;
19035 cur_proc_ptr->reg_mask = mask;
19036 cur_proc_ptr->reg_offset = off;
19039 demand_empty_rest_of_line ();
19042 #endif /* OBJ_ELF */
19043 s_ignore (reg_type);
19046 /* A table describing all the processors gas knows about. Names are
19047 matched in the order listed.
19049 To ease comparison, please keep this table in the same order as
19050 gcc's mips_cpu_info_table[]. */
19051 static const struct mips_cpu_info mips_cpu_info_table[] =
19053 /* Entries for generic ISAs */
19054 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
19055 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
19056 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
19057 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
19058 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
19059 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
19060 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
19061 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
19062 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
19065 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
19066 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
19067 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
19070 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
19073 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
19074 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
19075 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
19076 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
19077 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
19078 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
19079 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
19080 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
19081 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
19082 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
19083 { "orion", 0, ISA_MIPS3, CPU_R4600 },
19084 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
19085 /* ST Microelectronics Loongson 2E and 2F cores */
19086 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
19087 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
19090 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
19091 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
19092 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
19093 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
19094 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
19095 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
19096 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
19097 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
19098 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
19099 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
19100 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
19101 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
19102 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
19103 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
19104 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
19107 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
19108 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
19109 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
19110 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19112 /* MIPS 32 Release 2 */
19113 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19114 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19115 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19116 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19117 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19118 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19119 { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19120 { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19121 { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19122 ISA_MIPS32R2, CPU_MIPS32R2 },
19123 { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
19124 ISA_MIPS32R2, CPU_MIPS32R2 },
19125 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19126 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19127 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19128 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19129 /* Deprecated forms of the above. */
19130 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19131 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19132 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19133 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19134 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19135 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19136 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19137 /* Deprecated forms of the above. */
19138 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19139 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19140 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19141 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19142 ISA_MIPS32R2, CPU_MIPS32R2 },
19143 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19144 ISA_MIPS32R2, CPU_MIPS32R2 },
19145 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19146 ISA_MIPS32R2, CPU_MIPS32R2 },
19147 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19148 ISA_MIPS32R2, CPU_MIPS32R2 },
19149 /* Deprecated forms of the above. */
19150 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19151 ISA_MIPS32R2, CPU_MIPS32R2 },
19152 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19153 ISA_MIPS32R2, CPU_MIPS32R2 },
19154 /* 34Kn is a 34kc without DSP. */
19155 { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19156 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19157 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19158 ISA_MIPS32R2, CPU_MIPS32R2 },
19159 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19160 ISA_MIPS32R2, CPU_MIPS32R2 },
19161 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19162 ISA_MIPS32R2, CPU_MIPS32R2 },
19163 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19164 ISA_MIPS32R2, CPU_MIPS32R2 },
19165 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19166 ISA_MIPS32R2, CPU_MIPS32R2 },
19167 /* Deprecated forms of the above. */
19168 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19169 ISA_MIPS32R2, CPU_MIPS32R2 },
19170 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
19171 ISA_MIPS32R2, CPU_MIPS32R2 },
19172 /* 1004K cores are multiprocessor versions of the 34K. */
19173 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19174 ISA_MIPS32R2, CPU_MIPS32R2 },
19175 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19176 ISA_MIPS32R2, CPU_MIPS32R2 },
19177 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19178 ISA_MIPS32R2, CPU_MIPS32R2 },
19179 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
19180 ISA_MIPS32R2, CPU_MIPS32R2 },
19183 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
19184 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
19185 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19186 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19188 /* Broadcom SB-1 CPU core */
19189 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19190 ISA_MIPS64, CPU_SB1 },
19191 /* Broadcom SB-1A CPU core */
19192 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
19193 ISA_MIPS64, CPU_SB1 },
19195 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
19197 /* MIPS 64 Release 2 */
19199 /* Cavium Networks Octeon CPU core */
19200 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
19201 { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
19202 { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
19205 { "xlr", 0, ISA_MIPS64, CPU_XLR },
19208 XLP is mostly like XLR, with the prominent exception that it is
19209 MIPS64R2 rather than MIPS64. */
19210 { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
19217 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19218 with a final "000" replaced by "k". Ignore case.
19220 Note: this function is shared between GCC and GAS. */
19223 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19225 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19226 given++, canonical++;
19228 return ((*given == 0 && *canonical == 0)
19229 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19233 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19234 CPU name. We've traditionally allowed a lot of variation here.
19236 Note: this function is shared between GCC and GAS. */
19239 mips_matching_cpu_name_p (const char *canonical, const char *given)
19241 /* First see if the name matches exactly, or with a final "000"
19242 turned into "k". */
19243 if (mips_strict_matching_cpu_name_p (canonical, given))
19246 /* If not, try comparing based on numerical designation alone.
19247 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19248 if (TOLOWER (*given) == 'r')
19250 if (!ISDIGIT (*given))
19253 /* Skip over some well-known prefixes in the canonical name,
19254 hoping to find a number there too. */
19255 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19257 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19259 else if (TOLOWER (canonical[0]) == 'r')
19262 return mips_strict_matching_cpu_name_p (canonical, given);
19266 /* Parse an option that takes the name of a processor as its argument.
19267 OPTION is the name of the option and CPU_STRING is the argument.
19268 Return the corresponding processor enumeration if the CPU_STRING is
19269 recognized, otherwise report an error and return null.
19271 A similar function exists in GCC. */
19273 static const struct mips_cpu_info *
19274 mips_parse_cpu (const char *option, const char *cpu_string)
19276 const struct mips_cpu_info *p;
19278 /* 'from-abi' selects the most compatible architecture for the given
19279 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19280 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19281 version. Look first at the -mgp options, if given, otherwise base
19282 the choice on MIPS_DEFAULT_64BIT.
19284 Treat NO_ABI like the EABIs. One reason to do this is that the
19285 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19286 architecture. This code picks MIPS I for 'mips' and MIPS III for
19287 'mips64', just as we did in the days before 'from-abi'. */
19288 if (strcasecmp (cpu_string, "from-abi") == 0)
19290 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19291 return mips_cpu_info_from_isa (ISA_MIPS1);
19293 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19294 return mips_cpu_info_from_isa (ISA_MIPS3);
19296 if (file_mips_gp32 >= 0)
19297 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19299 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19304 /* 'default' has traditionally been a no-op. Probably not very useful. */
19305 if (strcasecmp (cpu_string, "default") == 0)
19308 for (p = mips_cpu_info_table; p->name != 0; p++)
19309 if (mips_matching_cpu_name_p (p->name, cpu_string))
19312 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19316 /* Return the canonical processor information for ISA (a member of the
19317 ISA_MIPS* enumeration). */
19319 static const struct mips_cpu_info *
19320 mips_cpu_info_from_isa (int isa)
19324 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19325 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19326 && isa == mips_cpu_info_table[i].isa)
19327 return (&mips_cpu_info_table[i]);
19332 static const struct mips_cpu_info *
19333 mips_cpu_info_from_arch (int arch)
19337 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19338 if (arch == mips_cpu_info_table[i].cpu)
19339 return (&mips_cpu_info_table[i]);
19345 show (FILE *stream, const char *string, int *col_p, int *first_p)
19349 fprintf (stream, "%24s", "");
19354 fprintf (stream, ", ");
19358 if (*col_p + strlen (string) > 72)
19360 fprintf (stream, "\n%24s", "");
19364 fprintf (stream, "%s", string);
19365 *col_p += strlen (string);
19371 md_show_usage (FILE *stream)
19376 fprintf (stream, _("\
19378 -EB generate big endian output\n\
19379 -EL generate little endian output\n\
19380 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19381 -G NUM allow referencing objects up to NUM bytes\n\
19382 implicitly with the gp register [default 8]\n"));
19383 fprintf (stream, _("\
19384 -mips1 generate MIPS ISA I instructions\n\
19385 -mips2 generate MIPS ISA II instructions\n\
19386 -mips3 generate MIPS ISA III instructions\n\
19387 -mips4 generate MIPS ISA IV instructions\n\
19388 -mips5 generate MIPS ISA V instructions\n\
19389 -mips32 generate MIPS32 ISA instructions\n\
19390 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19391 -mips64 generate MIPS64 ISA instructions\n\
19392 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19393 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19397 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19398 show (stream, mips_cpu_info_table[i].name, &column, &first);
19399 show (stream, "from-abi", &column, &first);
19400 fputc ('\n', stream);
19402 fprintf (stream, _("\
19403 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19404 -no-mCPU don't generate code specific to CPU.\n\
19405 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19409 show (stream, "3900", &column, &first);
19410 show (stream, "4010", &column, &first);
19411 show (stream, "4100", &column, &first);
19412 show (stream, "4650", &column, &first);
19413 fputc ('\n', stream);
19415 fprintf (stream, _("\
19416 -mips16 generate mips16 instructions\n\
19417 -no-mips16 do not generate mips16 instructions\n"));
19418 fprintf (stream, _("\
19419 -mmicromips generate microMIPS instructions\n\
19420 -mno-micromips do not generate microMIPS instructions\n"));
19421 fprintf (stream, _("\
19422 -msmartmips generate smartmips instructions\n\
19423 -mno-smartmips do not generate smartmips instructions\n"));
19424 fprintf (stream, _("\
19425 -mdsp generate DSP instructions\n\
19426 -mno-dsp do not generate DSP instructions\n"));
19427 fprintf (stream, _("\
19428 -mdspr2 generate DSP R2 instructions\n\
19429 -mno-dspr2 do not generate DSP R2 instructions\n"));
19430 fprintf (stream, _("\
19431 -mmt generate MT instructions\n\
19432 -mno-mt do not generate MT instructions\n"));
19433 fprintf (stream, _("\
19434 -mmcu generate MCU instructions\n\
19435 -mno-mcu do not generate MCU instructions\n"));
19436 fprintf (stream, _("\
19437 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19438 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19439 -mfix-vr4120 work around certain VR4120 errata\n\
19440 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19441 -mfix-24k insert a nop after ERET and DERET instructions\n\
19442 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19443 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19444 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19445 -msym32 assume all symbols have 32-bit values\n\
19446 -O0 remove unneeded NOPs, do not swap branches\n\
19447 -O remove unneeded NOPs and swap branches\n\
19448 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19449 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19450 fprintf (stream, _("\
19451 -mhard-float allow floating-point instructions\n\
19452 -msoft-float do not allow floating-point instructions\n\
19453 -msingle-float only allow 32-bit floating-point operations\n\
19454 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19455 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
19458 fprintf (stream, _("\
19459 -KPIC, -call_shared generate SVR4 position independent code\n\
19460 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19461 -mvxworks-pic generate VxWorks position independent code\n\
19462 -non_shared do not generate code that can operate with DSOs\n\
19463 -xgot assume a 32 bit GOT\n\
19464 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19465 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19466 position dependent (non shared) code\n\
19467 -mabi=ABI create ABI conformant object file for:\n"));
19471 show (stream, "32", &column, &first);
19472 show (stream, "o64", &column, &first);
19473 show (stream, "n32", &column, &first);
19474 show (stream, "64", &column, &first);
19475 show (stream, "eabi", &column, &first);
19477 fputc ('\n', stream);
19479 fprintf (stream, _("\
19480 -32 create o32 ABI object file (default)\n\
19481 -n32 create n32 ABI object file\n\
19482 -64 create 64 ABI object file\n"));
19488 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19490 if (HAVE_64BIT_SYMBOLS)
19491 return dwarf2_format_64bit_irix;
19493 return dwarf2_format_32bit;
19498 mips_dwarf2_addr_size (void)
19500 if (HAVE_64BIT_OBJECTS)
19506 /* Standard calling conventions leave the CFA at SP on entry. */
19508 mips_cfi_frame_initial_instructions (void)
19510 cfi_add_CFA_def_cfa_register (SP);
19514 tc_mips_regname_to_dw2regnum (char *regname)
19516 unsigned int regnum = -1;
19519 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))