1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug = -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr = FALSE;
86 int mips_flag_pdr = TRUE;
91 static char *mips_regmask_frag;
98 #define PIC_CALL_REG 25
106 #define ILLEGAL_REG (32)
108 #define AT mips_opts.at
110 extern int target_big_endian;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME ".rodata"
115 /* Ways in which an instruction can be "appended" to the output. */
117 /* Just add it normally. */
120 /* Add it normally and then add a nop. */
123 /* Turn an instruction with a delay slot into a "compact" version. */
126 /* Insert the instruction before the last one. */
130 /* Information about an instruction, including its format, operands
134 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
135 const struct mips_opcode *insn_mo;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. If we have
139 decided to use an extended MIPS16 instruction, this includes the
141 unsigned long insn_opcode;
143 /* The frag that contains the instruction. */
146 /* The offset into FRAG of the first instruction byte. */
149 /* The relocs associated with the instruction, if any. */
152 /* True if this entry cannot be moved from its current position. */
153 unsigned int fixed_p : 1;
155 /* True if this instruction occurred in a .set noreorder block. */
156 unsigned int noreorder_p : 1;
158 /* True for mips16 instructions that jump to an absolute address. */
159 unsigned int mips16_absolute_jump_p : 1;
161 /* True if this instruction is complete. */
162 unsigned int complete_p : 1;
164 /* True if this instruction is cleared from history by unconditional
166 unsigned int cleared_p : 1;
169 /* The ABI to use. */
180 /* MIPS ABI we are using for this output file. */
181 static enum mips_abi_level mips_abi = NO_ABI;
183 /* Whether or not we have code that can call pic code. */
184 int mips_abicalls = FALSE;
186 /* Whether or not we have code which can be put into a shared
188 static bfd_boolean mips_in_shared = TRUE;
190 /* This is the set of options which may be modified by the .set
191 pseudo-op. We use a struct so that .set push and .set pop are more
194 struct mips_set_options
196 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
197 if it has not been initialized. Changed by `.set mipsN', and the
198 -mipsN command line option, and the default CPU. */
200 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
201 <asename>', by command line options, and based on the default
204 /* Whether we are assembling for the mips16 processor. 0 if we are
205 not, 1 if we are, and -1 if the value has not been initialized.
206 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
207 -nomips16 command line options, and the default CPU. */
209 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
210 1 if we are, and -1 if the value has not been initialized. Changed
211 by `.set micromips' and `.set nomicromips', and the -mmicromips
212 and -mno-micromips command line options, and the default CPU. */
214 /* Non-zero if we should not reorder instructions. Changed by `.set
215 reorder' and `.set noreorder'. */
217 /* Non-zero if we should not permit the register designated "assembler
218 temporary" to be used in instructions. The value is the register
219 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
220 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
222 /* Non-zero if we should warn when a macro instruction expands into
223 more than one machine instruction. Changed by `.set nomacro' and
225 int warn_about_macros;
226 /* Non-zero if we should not move instructions. Changed by `.set
227 move', `.set volatile', `.set nomove', and `.set novolatile'. */
229 /* Non-zero if we should not optimize branches by moving the target
230 of the branch into the delay slot. Actually, we don't perform
231 this optimization anyhow. Changed by `.set bopt' and `.set
234 /* Non-zero if we should not autoextend mips16 instructions.
235 Changed by `.set autoextend' and `.set noautoextend'. */
237 /* True if we should only emit 32-bit microMIPS instructions.
238 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
239 and -mno-insn32 command line options. */
241 /* Restrict general purpose registers and floating point registers
242 to 32 bit. This is initially determined when -mgp32 or -mfp32
243 is passed but can changed if the assembler code uses .set mipsN. */
246 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
247 command line option, and the default CPU. */
249 /* True if ".set sym32" is in effect. */
251 /* True if floating-point operations are not allowed. Changed by .set
252 softfloat or .set hardfloat, by command line options -msoft-float or
253 -mhard-float. The default is false. */
254 bfd_boolean soft_float;
256 /* True if only single-precision floating-point operations are allowed.
257 Changed by .set singlefloat or .set doublefloat, command-line options
258 -msingle-float or -mdouble-float. The default is false. */
259 bfd_boolean single_float;
262 /* This is the struct we use to hold the current set of options. Note
263 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
264 -1 to indicate that they have not been initialized. */
266 /* True if -mgp32 was passed. */
267 static int file_mips_gp32 = -1;
269 /* True if -mfp32 was passed. */
270 static int file_mips_fp32 = -1;
272 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
273 static int file_mips_soft_float = 0;
275 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
276 static int file_mips_single_float = 0;
278 /* True if -mnan=2008, false if -mnan=legacy. */
279 static bfd_boolean mips_flag_nan2008 = FALSE;
281 static struct mips_set_options mips_opts =
283 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
284 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
285 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
286 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
287 /* soft_float */ FALSE, /* single_float */ FALSE
290 /* The set of ASEs that were selected on the command line, either
291 explicitly via ASE options or implicitly through things like -march. */
292 static unsigned int file_ase;
294 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
295 static unsigned int file_ase_explicit;
297 /* These variables are filled in with the masks of registers used.
298 The object format code reads them and puts them in the appropriate
300 unsigned long mips_gprmask;
301 unsigned long mips_cprmask[4];
303 /* MIPS ISA we are using for this output file. */
304 static int file_mips_isa = ISA_UNKNOWN;
306 /* True if any MIPS16 code was produced. */
307 static int file_ase_mips16;
309 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
310 || mips_opts.isa == ISA_MIPS32R2 \
311 || mips_opts.isa == ISA_MIPS64 \
312 || mips_opts.isa == ISA_MIPS64R2)
314 /* True if any microMIPS code was produced. */
315 static int file_ase_micromips;
317 /* True if we want to create R_MIPS_JALR for jalr $25. */
319 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
321 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
322 because there's no place for any addend, the only acceptable
323 expression is a bare symbol. */
324 #define MIPS_JALR_HINT_P(EXPR) \
325 (!HAVE_IN_PLACE_ADDENDS \
326 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
329 /* The argument of the -march= flag. The architecture we are assembling. */
330 static int file_mips_arch = CPU_UNKNOWN;
331 static const char *mips_arch_string;
333 /* The argument of the -mtune= flag. The architecture for which we
335 static int mips_tune = CPU_UNKNOWN;
336 static const char *mips_tune_string;
338 /* True when generating 32-bit code for a 64-bit processor. */
339 static int mips_32bitmode = 0;
341 /* True if the given ABI requires 32-bit registers. */
342 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
344 /* Likewise 64-bit registers. */
345 #define ABI_NEEDS_64BIT_REGS(ABI) \
347 || (ABI) == N64_ABI \
350 /* Return true if ISA supports 64 bit wide gp registers. */
351 #define ISA_HAS_64BIT_REGS(ISA) \
352 ((ISA) == ISA_MIPS3 \
353 || (ISA) == ISA_MIPS4 \
354 || (ISA) == ISA_MIPS5 \
355 || (ISA) == ISA_MIPS64 \
356 || (ISA) == ISA_MIPS64R2)
358 /* Return true if ISA supports 64 bit wide float registers. */
359 #define ISA_HAS_64BIT_FPRS(ISA) \
360 ((ISA) == ISA_MIPS3 \
361 || (ISA) == ISA_MIPS4 \
362 || (ISA) == ISA_MIPS5 \
363 || (ISA) == ISA_MIPS32R2 \
364 || (ISA) == ISA_MIPS64 \
365 || (ISA) == ISA_MIPS64R2)
367 /* Return true if ISA supports 64-bit right rotate (dror et al.)
369 #define ISA_HAS_DROR(ISA) \
370 ((ISA) == ISA_MIPS64R2 \
371 || (mips_opts.micromips \
372 && ISA_HAS_64BIT_REGS (ISA)) \
375 /* Return true if ISA supports 32-bit right rotate (ror et al.)
377 #define ISA_HAS_ROR(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2 \
380 || (mips_opts.ase & ASE_SMARTMIPS) \
381 || mips_opts.micromips \
384 /* Return true if ISA supports single-precision floats in odd registers. */
385 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
386 ((ISA) == ISA_MIPS32 \
387 || (ISA) == ISA_MIPS32R2 \
388 || (ISA) == ISA_MIPS64 \
389 || (ISA) == ISA_MIPS64R2)
391 /* Return true if ISA supports move to/from high part of a 64-bit
392 floating-point register. */
393 #define ISA_HAS_MXHC1(ISA) \
394 ((ISA) == ISA_MIPS32R2 \
395 || (ISA) == ISA_MIPS64R2)
397 #define HAVE_32BIT_GPRS \
398 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
400 #define HAVE_32BIT_FPRS \
401 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
403 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
404 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
406 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
408 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
410 /* True if relocations are stored in-place. */
411 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
413 /* The ABI-derived address size. */
414 #define HAVE_64BIT_ADDRESSES \
415 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
416 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
418 /* The size of symbolic constants (i.e., expressions of the form
419 "SYMBOL" or "SYMBOL + OFFSET"). */
420 #define HAVE_32BIT_SYMBOLS \
421 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
422 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
424 /* Addresses are loaded in different ways, depending on the address size
425 in use. The n32 ABI Documentation also mandates the use of additions
426 with overflow checking, but existing implementations don't follow it. */
427 #define ADDRESS_ADD_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
430 #define ADDRESS_ADDI_INSN \
431 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
433 #define ADDRESS_LOAD_INSN \
434 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
436 #define ADDRESS_STORE_INSN \
437 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
439 /* Return true if the given CPU supports the MIPS16 ASE. */
440 #define CPU_HAS_MIPS16(cpu) \
441 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
442 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
444 /* Return true if the given CPU supports the microMIPS ASE. */
445 #define CPU_HAS_MICROMIPS(cpu) 0
447 /* True if CPU has a dror instruction. */
448 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
450 /* True if CPU has a ror instruction. */
451 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
453 /* True if CPU is in the Octeon family */
454 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
456 /* True if CPU has seq/sne and seqi/snei instructions. */
457 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
459 /* True, if CPU has support for ldc1 and sdc1. */
460 #define CPU_HAS_LDC1_SDC1(CPU) \
461 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
463 /* True if mflo and mfhi can be immediately followed by instructions
464 which write to the HI and LO registers.
466 According to MIPS specifications, MIPS ISAs I, II, and III need
467 (at least) two instructions between the reads of HI/LO and
468 instructions which write them, and later ISAs do not. Contradicting
469 the MIPS specifications, some MIPS IV processor user manuals (e.g.
470 the UM for the NEC Vr5000) document needing the instructions between
471 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
472 MIPS64 and later ISAs to have the interlocks, plus any specific
473 earlier-ISA CPUs for which CPU documentation declares that the
474 instructions are really interlocked. */
475 #define hilo_interlocks \
476 (mips_opts.isa == ISA_MIPS32 \
477 || mips_opts.isa == ISA_MIPS32R2 \
478 || mips_opts.isa == ISA_MIPS64 \
479 || mips_opts.isa == ISA_MIPS64R2 \
480 || mips_opts.arch == CPU_R4010 \
481 || mips_opts.arch == CPU_R5900 \
482 || mips_opts.arch == CPU_R10000 \
483 || mips_opts.arch == CPU_R12000 \
484 || mips_opts.arch == CPU_R14000 \
485 || mips_opts.arch == CPU_R16000 \
486 || mips_opts.arch == CPU_RM7000 \
487 || mips_opts.arch == CPU_VR5500 \
488 || mips_opts.micromips \
491 /* Whether the processor uses hardware interlocks to protect reads
492 from the GPRs after they are loaded from memory, and thus does not
493 require nops to be inserted. This applies to instructions marked
494 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
495 level I and microMIPS mode instructions are always interlocked. */
496 #define gpr_interlocks \
497 (mips_opts.isa != ISA_MIPS1 \
498 || mips_opts.arch == CPU_R3900 \
499 || mips_opts.arch == CPU_R5900 \
500 || mips_opts.micromips \
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III and microMIPS mode instructions are always
511 /* Itbl support may require additional care here. */
512 #define cop_interlocks \
513 ((mips_opts.isa != ISA_MIPS1 \
514 && mips_opts.isa != ISA_MIPS2 \
515 && mips_opts.isa != ISA_MIPS3) \
516 || mips_opts.arch == CPU_R4300 \
517 || mips_opts.micromips \
520 /* Whether the processor uses hardware interlocks to protect reads
521 from coprocessor registers after they are loaded from memory, and
522 thus does not require nops to be inserted. This applies to
523 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
524 requires at MIPS ISA level I and microMIPS mode instructions are
525 always interlocked. */
526 #define cop_mem_interlocks \
527 (mips_opts.isa != ISA_MIPS1 \
528 || mips_opts.micromips \
531 /* Is this a mfhi or mflo instruction? */
532 #define MF_HILO_INSN(PINFO) \
533 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
535 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
536 has been selected. This implies, in particular, that addresses of text
537 labels have their LSB set. */
538 #define HAVE_CODE_COMPRESSION \
539 ((mips_opts.mips16 | mips_opts.micromips) != 0)
541 /* The minimum and maximum signed values that can be stored in a GPR. */
542 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
543 #define GPR_SMIN (-GPR_SMAX - 1)
545 /* MIPS PIC level. */
547 enum mips_pic_level mips_pic;
549 /* 1 if we should generate 32 bit offsets from the $gp register in
550 SVR4_PIC mode. Currently has no meaning in other modes. */
551 static int mips_big_got = 0;
553 /* 1 if trap instructions should used for overflow rather than break
555 static int mips_trap = 0;
557 /* 1 if double width floating point constants should not be constructed
558 by assembling two single width halves into two single width floating
559 point registers which just happen to alias the double width destination
560 register. On some architectures this aliasing can be disabled by a bit
561 in the status register, and the setting of this bit cannot be determined
562 automatically at assemble time. */
563 static int mips_disable_float_construction;
565 /* Non-zero if any .set noreorder directives were used. */
567 static int mips_any_noreorder;
569 /* Non-zero if nops should be inserted when the register referenced in
570 an mfhi/mflo instruction is read in the next two instructions. */
571 static int mips_7000_hilo_fix;
573 /* The size of objects in the small data section. */
574 static unsigned int g_switch_value = 8;
575 /* Whether the -G option was used. */
576 static int g_switch_seen = 0;
581 /* If we can determine in advance that GP optimization won't be
582 possible, we can skip the relaxation stuff that tries to produce
583 GP-relative references. This makes delay slot optimization work
586 This function can only provide a guess, but it seems to work for
587 gcc output. It needs to guess right for gcc, otherwise gcc
588 will put what it thinks is a GP-relative instruction in a branch
591 I don't know if a fix is needed for the SVR4_PIC mode. I've only
592 fixed it for the non-PIC mode. KR 95/04/07 */
593 static int nopic_need_relax (symbolS *, int);
595 /* handle of the OPCODE hash table */
596 static struct hash_control *op_hash = NULL;
598 /* The opcode hash table we use for the mips16. */
599 static struct hash_control *mips16_op_hash = NULL;
601 /* The opcode hash table we use for the microMIPS ASE. */
602 static struct hash_control *micromips_op_hash = NULL;
604 /* This array holds the chars that always start a comment. If the
605 pre-processor is disabled, these aren't very useful */
606 const char comment_chars[] = "#";
608 /* This array holds the chars that only start a comment at the beginning of
609 a line. If the line seems to have the form '# 123 filename'
610 .line and .file directives will appear in the pre-processed output */
611 /* Note that input_file.c hand checks for '#' at the beginning of the
612 first line of the input file. This is because the compiler outputs
613 #NO_APP at the beginning of its output. */
614 /* Also note that C style comments are always supported. */
615 const char line_comment_chars[] = "#";
617 /* This array holds machine specific line separator characters. */
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant from exp in floating point nums */
621 const char EXP_CHARS[] = "eE";
623 /* Chars that mean this number is a floating point constant */
626 const char FLT_CHARS[] = "rRsSfFdDxXpP";
628 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
629 changed in read.c . Ideally it shouldn't have to know about it at all,
630 but nothing is ideal around here.
633 /* Types of printf format used for instruction-related error messages.
634 "I" means int ("%d") and "S" means string ("%s"). */
635 enum mips_insn_error_format {
641 /* Information about an error that was found while assembling the current
643 struct mips_insn_error {
644 /* We sometimes need to match an instruction against more than one
645 opcode table entry. Errors found during this matching are reported
646 against a particular syntactic argument rather than against the
647 instruction as a whole. We grade these messages so that errors
648 against argument N have a greater priority than an error against
649 any argument < N, since the former implies that arguments up to N
650 were acceptable and that the opcode entry was therefore a closer match.
651 If several matches report an error against the same argument,
652 we only use that error if it is the same in all cases.
654 min_argnum is the minimum argument number for which an error message
655 should be accepted. It is 0 if MSG is against the instruction as
659 /* The printf()-style message, including its format and arguments. */
660 enum mips_insn_error_format format;
668 /* The error that should be reported for the current instruction. */
669 static struct mips_insn_error insn_error;
671 static int auto_align = 1;
673 /* When outputting SVR4 PIC code, the assembler needs to know the
674 offset in the stack frame from which to restore the $gp register.
675 This is set by the .cprestore pseudo-op, and saved in this
677 static offsetT mips_cprestore_offset = -1;
679 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
680 more optimizations, it can use a register value instead of a memory-saved
681 offset and even an other register than $gp as global pointer. */
682 static offsetT mips_cpreturn_offset = -1;
683 static int mips_cpreturn_register = -1;
684 static int mips_gp_register = GP;
685 static int mips_gprel_offset = 0;
687 /* Whether mips_cprestore_offset has been set in the current function
688 (or whether it has already been warned about, if not). */
689 static int mips_cprestore_valid = 0;
691 /* This is the register which holds the stack frame, as set by the
692 .frame pseudo-op. This is needed to implement .cprestore. */
693 static int mips_frame_reg = SP;
695 /* Whether mips_frame_reg has been set in the current function
696 (or whether it has already been warned about, if not). */
697 static int mips_frame_reg_valid = 0;
699 /* To output NOP instructions correctly, we need to keep information
700 about the previous two instructions. */
702 /* Whether we are optimizing. The default value of 2 means to remove
703 unneeded NOPs and swap branch instructions when possible. A value
704 of 1 means to not swap branches. A value of 0 means to always
706 static int mips_optimize = 2;
708 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
709 equivalent to seeing no -g option at all. */
710 static int mips_debug = 0;
712 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
713 #define MAX_VR4130_NOPS 4
715 /* The maximum number of NOPs needed to fill delay slots. */
716 #define MAX_DELAY_NOPS 2
718 /* The maximum number of NOPs needed for any purpose. */
721 /* A list of previous instructions, with index 0 being the most recent.
722 We need to look back MAX_NOPS instructions when filling delay slots
723 or working around processor errata. We need to look back one
724 instruction further if we're thinking about using history[0] to
725 fill a branch delay slot. */
726 static struct mips_cl_insn history[1 + MAX_NOPS];
728 /* Arrays of operands for each instruction. */
729 #define MAX_OPERANDS 6
730 struct mips_operand_array {
731 const struct mips_operand *operand[MAX_OPERANDS];
733 static struct mips_operand_array *mips_operands;
734 static struct mips_operand_array *mips16_operands;
735 static struct mips_operand_array *micromips_operands;
737 /* Nop instructions used by emit_nop. */
738 static struct mips_cl_insn nop_insn;
739 static struct mips_cl_insn mips16_nop_insn;
740 static struct mips_cl_insn micromips_nop16_insn;
741 static struct mips_cl_insn micromips_nop32_insn;
743 /* The appropriate nop for the current mode. */
744 #define NOP_INSN (mips_opts.mips16 \
746 : (mips_opts.micromips \
747 ? (mips_opts.insn32 \
748 ? µmips_nop32_insn \
749 : µmips_nop16_insn) \
752 /* The size of NOP_INSN in bytes. */
753 #define NOP_INSN_SIZE ((mips_opts.mips16 \
754 || (mips_opts.micromips && !mips_opts.insn32)) \
757 /* If this is set, it points to a frag holding nop instructions which
758 were inserted before the start of a noreorder section. If those
759 nops turn out to be unnecessary, the size of the frag can be
761 static fragS *prev_nop_frag;
763 /* The number of nop instructions we created in prev_nop_frag. */
764 static int prev_nop_frag_holds;
766 /* The number of nop instructions that we know we need in
768 static int prev_nop_frag_required;
770 /* The number of instructions we've seen since prev_nop_frag. */
771 static int prev_nop_frag_since;
773 /* Relocations against symbols are sometimes done in two parts, with a HI
774 relocation and a LO relocation. Each relocation has only 16 bits of
775 space to store an addend. This means that in order for the linker to
776 handle carries correctly, it must be able to locate both the HI and
777 the LO relocation. This means that the relocations must appear in
778 order in the relocation table.
780 In order to implement this, we keep track of each unmatched HI
781 relocation. We then sort them so that they immediately precede the
782 corresponding LO relocation. */
787 struct mips_hi_fixup *next;
790 /* The section this fixup is in. */
794 /* The list of unmatched HI relocs. */
796 static struct mips_hi_fixup *mips_hi_fixup_list;
798 /* The frag containing the last explicit relocation operator.
799 Null if explicit relocations have not been used. */
801 static fragS *prev_reloc_op_frag;
803 /* Map mips16 register numbers to normal MIPS register numbers. */
805 static const unsigned int mips16_to_32_reg_map[] =
807 16, 17, 2, 3, 4, 5, 6, 7
810 /* Map microMIPS register numbers to normal MIPS register numbers. */
812 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
814 /* The microMIPS registers with type h. */
815 static const unsigned int micromips_to_32_reg_h_map1[] =
817 5, 5, 6, 4, 4, 4, 4, 4
819 static const unsigned int micromips_to_32_reg_h_map2[] =
821 6, 7, 7, 21, 22, 5, 6, 7
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* Classifies the kind of instructions we're interested in when
833 implementing -mfix-vr4120. */
834 enum fix_vr4120_class
842 NUM_FIX_VR4120_CLASSES
845 /* ...likewise -mfix-loongson2f-jump. */
846 static bfd_boolean mips_fix_loongson2f_jump;
848 /* ...likewise -mfix-loongson2f-nop. */
849 static bfd_boolean mips_fix_loongson2f_nop;
851 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
852 static bfd_boolean mips_fix_loongson2f;
854 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
855 there must be at least one other instruction between an instruction
856 of type X and an instruction of type Y. */
857 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
859 /* True if -mfix-vr4120 is in force. */
860 static int mips_fix_vr4120;
862 /* ...likewise -mfix-vr4130. */
863 static int mips_fix_vr4130;
865 /* ...likewise -mfix-24k. */
866 static int mips_fix_24k;
868 /* ...likewise -mfix-cn63xxp1 */
869 static bfd_boolean mips_fix_cn63xxp1;
871 /* We don't relax branches by default, since this causes us to expand
872 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
873 fail to compute the offset before expanding the macro to the most
874 efficient expansion. */
876 static int mips_relax_branch;
878 /* The expansion of many macros depends on the type of symbol that
879 they refer to. For example, when generating position-dependent code,
880 a macro that refers to a symbol may have two different expansions,
881 one which uses GP-relative addresses and one which uses absolute
882 addresses. When generating SVR4-style PIC, a macro may have
883 different expansions for local and global symbols.
885 We handle these situations by generating both sequences and putting
886 them in variant frags. In position-dependent code, the first sequence
887 will be the GP-relative one and the second sequence will be the
888 absolute one. In SVR4 PIC, the first sequence will be for global
889 symbols and the second will be for local symbols.
891 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
892 SECOND are the lengths of the two sequences in bytes. These fields
893 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
894 the subtype has the following flags:
897 Set if it has been decided that we should use the second
898 sequence instead of the first.
901 Set in the first variant frag if the macro's second implementation
902 is longer than its first. This refers to the macro as a whole,
903 not an individual relaxation.
906 Set in the first variant frag if the macro appeared in a .set nomacro
907 block and if one alternative requires a warning but the other does not.
910 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
913 RELAX_DELAY_SLOT_16BIT
914 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
917 RELAX_DELAY_SLOT_SIZE_FIRST
918 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
919 the macro is of the wrong size for the branch delay slot.
921 RELAX_DELAY_SLOT_SIZE_SECOND
922 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
923 the macro is of the wrong size for the branch delay slot.
925 The frag's "opcode" points to the first fixup for relaxable code.
927 Relaxable macros are generated using a sequence such as:
929 relax_start (SYMBOL);
930 ... generate first expansion ...
932 ... generate second expansion ...
935 The code and fixups for the unwanted alternative are discarded
936 by md_convert_frag. */
937 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
939 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
940 #define RELAX_SECOND(X) ((X) & 0xff)
941 #define RELAX_USE_SECOND 0x10000
942 #define RELAX_SECOND_LONGER 0x20000
943 #define RELAX_NOMACRO 0x40000
944 #define RELAX_DELAY_SLOT 0x80000
945 #define RELAX_DELAY_SLOT_16BIT 0x100000
946 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
947 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
949 /* Branch without likely bit. If label is out of range, we turn:
951 beq reg1, reg2, label
961 with the following opcode replacements:
968 bltzal <-> bgezal (with jal label instead of j label)
970 Even though keeping the delay slot instruction in the delay slot of
971 the branch would be more efficient, it would be very tricky to do
972 correctly, because we'd have to introduce a variable frag *after*
973 the delay slot instruction, and expand that instead. Let's do it
974 the easy way for now, even if the branch-not-taken case now costs
975 one additional instruction. Out-of-range branches are not supposed
976 to be common, anyway.
978 Branch likely. If label is out of range, we turn:
980 beql reg1, reg2, label
981 delay slot (annulled if branch not taken)
990 delay slot (executed only if branch taken)
993 It would be possible to generate a shorter sequence by losing the
994 likely bit, generating something like:
999 delay slot (executed only if branch taken)
1011 bltzall -> bgezal (with jal label instead of j label)
1012 bgezall -> bltzal (ditto)
1015 but it's not clear that it would actually improve performance. */
1016 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1017 ((relax_substateT) \
1020 | ((toofar) ? 0x20 : 0) \
1021 | ((link) ? 0x40 : 0) \
1022 | ((likely) ? 0x80 : 0) \
1023 | ((uncond) ? 0x100 : 0)))
1024 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1025 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1026 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1027 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1028 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1029 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1031 /* For mips16 code, we use an entirely different form of relaxation.
1032 mips16 supports two versions of most instructions which take
1033 immediate values: a small one which takes some small value, and a
1034 larger one which takes a 16 bit value. Since branches also follow
1035 this pattern, relaxing these values is required.
1037 We can assemble both mips16 and normal MIPS code in a single
1038 object. Therefore, we need to support this type of relaxation at
1039 the same time that we support the relaxation described above. We
1040 use the high bit of the subtype field to distinguish these cases.
1042 The information we store for this type of relaxation is the
1043 argument code found in the opcode file for this relocation, whether
1044 the user explicitly requested a small or extended form, and whether
1045 the relocation is in a jump or jal delay slot. That tells us the
1046 size of the value, and how it should be stored. We also store
1047 whether the fragment is considered to be extended or not. We also
1048 store whether this is known to be a branch to a different section,
1049 whether we have tried to relax this frag yet, and whether we have
1050 ever extended a PC relative fragment because of a shift count. */
1051 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1054 | ((small) ? 0x100 : 0) \
1055 | ((ext) ? 0x200 : 0) \
1056 | ((dslot) ? 0x400 : 0) \
1057 | ((jal_dslot) ? 0x800 : 0))
1058 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1059 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1060 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1061 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1062 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1063 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1064 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1065 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1066 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1067 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1068 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1069 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1071 /* For microMIPS code, we use relaxation similar to one we use for
1072 MIPS16 code. Some instructions that take immediate values support
1073 two encodings: a small one which takes some small value, and a
1074 larger one which takes a 16 bit value. As some branches also follow
1075 this pattern, relaxing these values is required.
1077 We can assemble both microMIPS and normal MIPS code in a single
1078 object. Therefore, we need to support this type of relaxation at
1079 the same time that we support the relaxation described above. We
1080 use one of the high bits of the subtype field to distinguish these
1083 The information we store for this type of relaxation is the argument
1084 code found in the opcode file for this relocation, the register
1085 selected as the assembler temporary, whether the branch is
1086 unconditional, whether it is compact, whether it stores the link
1087 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1088 branches to a sequence of instructions is enabled, and whether the
1089 displacement of a branch is too large to fit as an immediate argument
1090 of a 16-bit and a 32-bit branch, respectively. */
1091 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1092 relax32, toofar16, toofar32) \
1095 | (((at) & 0x1f) << 8) \
1096 | ((uncond) ? 0x2000 : 0) \
1097 | ((compact) ? 0x4000 : 0) \
1098 | ((link) ? 0x8000 : 0) \
1099 | ((relax32) ? 0x10000 : 0) \
1100 | ((toofar16) ? 0x20000 : 0) \
1101 | ((toofar32) ? 0x40000 : 0))
1102 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1103 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1104 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1105 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1106 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1107 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1108 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1110 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1111 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1112 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1113 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1114 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1115 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1117 /* Sign-extend 16-bit value X. */
1118 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1120 /* Is the given value a sign-extended 32-bit value? */
1121 #define IS_SEXT_32BIT_NUM(x) \
1122 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1123 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1125 /* Is the given value a sign-extended 16-bit value? */
1126 #define IS_SEXT_16BIT_NUM(x) \
1127 (((x) &~ (offsetT) 0x7fff) == 0 \
1128 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1130 /* Is the given value a sign-extended 12-bit value? */
1131 #define IS_SEXT_12BIT_NUM(x) \
1132 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1134 /* Is the given value a sign-extended 9-bit value? */
1135 #define IS_SEXT_9BIT_NUM(x) \
1136 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1138 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1139 #define IS_ZEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0xffffffff) == 0 \
1141 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1143 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1145 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1146 (((STRUCT) >> (SHIFT)) & (MASK))
1148 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1149 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1151 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1152 : EXTRACT_BITS ((INSN).insn_opcode, \
1153 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1154 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1155 EXTRACT_BITS ((INSN).insn_opcode, \
1156 MIPS16OP_MASK_##FIELD, \
1157 MIPS16OP_SH_##FIELD)
1159 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1160 #define MIPS16_EXTEND (0xf000U << 16)
1162 /* Whether or not we are emitting a branch-likely macro. */
1163 static bfd_boolean emit_branch_likely_macro = FALSE;
1165 /* Global variables used when generating relaxable macros. See the
1166 comment above RELAX_ENCODE for more details about how relaxation
1169 /* 0 if we're not emitting a relaxable macro.
1170 1 if we're emitting the first of the two relaxation alternatives.
1171 2 if we're emitting the second alternative. */
1174 /* The first relaxable fixup in the current frag. (In other words,
1175 the first fixup that refers to relaxable code.) */
1178 /* sizes[0] says how many bytes of the first alternative are stored in
1179 the current frag. Likewise sizes[1] for the second alternative. */
1180 unsigned int sizes[2];
1182 /* The symbol on which the choice of sequence depends. */
1186 /* Global variables used to decide whether a macro needs a warning. */
1188 /* True if the macro is in a branch delay slot. */
1189 bfd_boolean delay_slot_p;
1191 /* Set to the length in bytes required if the macro is in a delay slot
1192 that requires a specific length of instruction, otherwise zero. */
1193 unsigned int delay_slot_length;
1195 /* For relaxable macros, sizes[0] is the length of the first alternative
1196 in bytes and sizes[1] is the length of the second alternative.
1197 For non-relaxable macros, both elements give the length of the
1199 unsigned int sizes[2];
1201 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1202 instruction of the first alternative in bytes and first_insn_sizes[1]
1203 is the length of the first instruction of the second alternative.
1204 For non-relaxable macros, both elements give the length of the first
1205 instruction in bytes.
1207 Set to zero if we haven't yet seen the first instruction. */
1208 unsigned int first_insn_sizes[2];
1210 /* For relaxable macros, insns[0] is the number of instructions for the
1211 first alternative and insns[1] is the number of instructions for the
1214 For non-relaxable macros, both elements give the number of
1215 instructions for the macro. */
1216 unsigned int insns[2];
1218 /* The first variant frag for this macro. */
1220 } mips_macro_warning;
1222 /* Prototypes for static functions. */
1224 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1226 static void append_insn
1227 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1228 bfd_boolean expansionp);
1229 static void mips_no_prev_insn (void);
1230 static void macro_build (expressionS *, const char *, const char *, ...);
1231 static void mips16_macro_build
1232 (expressionS *, const char *, const char *, va_list *);
1233 static void load_register (int, expressionS *, int);
1234 static void macro_start (void);
1235 static void macro_end (void);
1236 static void macro (struct mips_cl_insn *ip, char *str);
1237 static void mips16_macro (struct mips_cl_insn * ip);
1238 static void mips_ip (char *str, struct mips_cl_insn * ip);
1239 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1240 static void mips16_immed
1241 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1242 unsigned int, unsigned long *);
1243 static size_t my_getSmallExpression
1244 (expressionS *, bfd_reloc_code_real_type *, char *);
1245 static void my_getExpression (expressionS *, char *);
1246 static void s_align (int);
1247 static void s_change_sec (int);
1248 static void s_change_section (int);
1249 static void s_cons (int);
1250 static void s_float_cons (int);
1251 static void s_mips_globl (int);
1252 static void s_option (int);
1253 static void s_mipsset (int);
1254 static void s_abicalls (int);
1255 static void s_cpload (int);
1256 static void s_cpsetup (int);
1257 static void s_cplocal (int);
1258 static void s_cprestore (int);
1259 static void s_cpreturn (int);
1260 static void s_dtprelword (int);
1261 static void s_dtpreldword (int);
1262 static void s_tprelword (int);
1263 static void s_tpreldword (int);
1264 static void s_gpvalue (int);
1265 static void s_gpword (int);
1266 static void s_gpdword (int);
1267 static void s_ehword (int);
1268 static void s_cpadd (int);
1269 static void s_insn (int);
1270 static void s_nan (int);
1271 static void md_obj_begin (void);
1272 static void md_obj_end (void);
1273 static void s_mips_ent (int);
1274 static void s_mips_end (int);
1275 static void s_mips_frame (int);
1276 static void s_mips_mask (int reg_type);
1277 static void s_mips_stab (int);
1278 static void s_mips_weakext (int);
1279 static void s_mips_file (int);
1280 static void s_mips_loc (int);
1281 static bfd_boolean pic_need_relax (symbolS *, asection *);
1282 static int relaxed_branch_length (fragS *, asection *, int);
1283 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1284 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1286 /* Table and functions used to map between CPU/ISA names, and
1287 ISA levels, and CPU numbers. */
1289 struct mips_cpu_info
1291 const char *name; /* CPU or ISA name. */
1292 int flags; /* MIPS_CPU_* flags. */
1293 int ase; /* Set of ASEs implemented by the CPU. */
1294 int isa; /* ISA level. */
1295 int cpu; /* CPU number (default CPU if ISA). */
1298 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1300 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1301 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1302 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1304 /* Command-line options. */
1305 const char *md_shortopts = "O::g::G:";
1309 OPTION_MARCH = OPTION_MD_BASE,
1333 OPTION_NO_SMARTMIPS,
1339 OPTION_NO_MICROMIPS,
1342 OPTION_COMPAT_ARCH_BASE,
1351 OPTION_M7000_HILO_FIX,
1352 OPTION_MNO_7000_HILO_FIX,
1355 OPTION_FIX_LOONGSON2F_JUMP,
1356 OPTION_NO_FIX_LOONGSON2F_JUMP,
1357 OPTION_FIX_LOONGSON2F_NOP,
1358 OPTION_NO_FIX_LOONGSON2F_NOP,
1360 OPTION_NO_FIX_VR4120,
1362 OPTION_NO_FIX_VR4130,
1363 OPTION_FIX_CN63XXP1,
1364 OPTION_NO_FIX_CN63XXP1,
1371 OPTION_CONSTRUCT_FLOATS,
1372 OPTION_NO_CONSTRUCT_FLOATS,
1375 OPTION_RELAX_BRANCH,
1376 OPTION_NO_RELAX_BRANCH,
1385 OPTION_SINGLE_FLOAT,
1386 OPTION_DOUBLE_FLOAT,
1399 OPTION_MVXWORKS_PIC,
1404 struct option md_longopts[] =
1406 /* Options which specify architecture. */
1407 {"march", required_argument, NULL, OPTION_MARCH},
1408 {"mtune", required_argument, NULL, OPTION_MTUNE},
1409 {"mips0", no_argument, NULL, OPTION_MIPS1},
1410 {"mips1", no_argument, NULL, OPTION_MIPS1},
1411 {"mips2", no_argument, NULL, OPTION_MIPS2},
1412 {"mips3", no_argument, NULL, OPTION_MIPS3},
1413 {"mips4", no_argument, NULL, OPTION_MIPS4},
1414 {"mips5", no_argument, NULL, OPTION_MIPS5},
1415 {"mips32", no_argument, NULL, OPTION_MIPS32},
1416 {"mips64", no_argument, NULL, OPTION_MIPS64},
1417 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1418 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1420 /* Options which specify Application Specific Extensions (ASEs). */
1421 {"mips16", no_argument, NULL, OPTION_MIPS16},
1422 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1423 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1424 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1425 {"mdmx", no_argument, NULL, OPTION_MDMX},
1426 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1427 {"mdsp", no_argument, NULL, OPTION_DSP},
1428 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1429 {"mmt", no_argument, NULL, OPTION_MT},
1430 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1431 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1432 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1433 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1434 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1435 {"meva", no_argument, NULL, OPTION_EVA},
1436 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1437 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1438 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1439 {"mmcu", no_argument, NULL, OPTION_MCU},
1440 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1441 {"mvirt", no_argument, NULL, OPTION_VIRT},
1442 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1444 /* Old-style architecture options. Don't add more of these. */
1445 {"m4650", no_argument, NULL, OPTION_M4650},
1446 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1447 {"m4010", no_argument, NULL, OPTION_M4010},
1448 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1449 {"m4100", no_argument, NULL, OPTION_M4100},
1450 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1451 {"m3900", no_argument, NULL, OPTION_M3900},
1452 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1454 /* Options which enable bug fixes. */
1455 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1456 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1457 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1458 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1459 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1460 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1461 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1462 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1463 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1464 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1465 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1466 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1467 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1468 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1469 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1471 /* Miscellaneous options. */
1472 {"trap", no_argument, NULL, OPTION_TRAP},
1473 {"no-break", no_argument, NULL, OPTION_TRAP},
1474 {"break", no_argument, NULL, OPTION_BREAK},
1475 {"no-trap", no_argument, NULL, OPTION_BREAK},
1476 {"EB", no_argument, NULL, OPTION_EB},
1477 {"EL", no_argument, NULL, OPTION_EL},
1478 {"mfp32", no_argument, NULL, OPTION_FP32},
1479 {"mgp32", no_argument, NULL, OPTION_GP32},
1480 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1481 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1482 {"mfp64", no_argument, NULL, OPTION_FP64},
1483 {"mgp64", no_argument, NULL, OPTION_GP64},
1484 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1485 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1486 {"minsn32", no_argument, NULL, OPTION_INSN32},
1487 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1488 {"mshared", no_argument, NULL, OPTION_MSHARED},
1489 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1490 {"msym32", no_argument, NULL, OPTION_MSYM32},
1491 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1492 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1493 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1494 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1495 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1497 /* Strictly speaking this next option is ELF specific,
1498 but we allow it for other ports as well in order to
1499 make testing easier. */
1500 {"32", no_argument, NULL, OPTION_32},
1502 /* ELF-specific options. */
1503 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1504 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1505 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1506 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1507 {"xgot", no_argument, NULL, OPTION_XGOT},
1508 {"mabi", required_argument, NULL, OPTION_MABI},
1509 {"n32", no_argument, NULL, OPTION_N32},
1510 {"64", no_argument, NULL, OPTION_64},
1511 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1512 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1513 {"mpdr", no_argument, NULL, OPTION_PDR},
1514 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1515 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1516 {"mnan", required_argument, NULL, OPTION_NAN},
1518 {NULL, no_argument, NULL, 0}
1520 size_t md_longopts_size = sizeof (md_longopts);
1522 /* Information about either an Application Specific Extension or an
1523 optional architecture feature that, for simplicity, we treat in the
1524 same way as an ASE. */
1527 /* The name of the ASE, used in both the command-line and .set options. */
1530 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1531 and 64-bit architectures, the flags here refer to the subset that
1532 is available on both. */
1535 /* The ASE_* flag used for instructions that are available on 64-bit
1536 architectures but that are not included in FLAGS. */
1537 unsigned int flags64;
1539 /* The command-line options that turn the ASE on and off. */
1543 /* The minimum required architecture revisions for MIPS32, MIPS64,
1544 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1547 int micromips32_rev;
1548 int micromips64_rev;
1551 /* A table of all supported ASEs. */
1552 static const struct mips_ase mips_ases[] = {
1553 { "dsp", ASE_DSP, ASE_DSP64,
1554 OPTION_DSP, OPTION_NO_DSP,
1557 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1558 OPTION_DSPR2, OPTION_NO_DSPR2,
1561 { "eva", ASE_EVA, 0,
1562 OPTION_EVA, OPTION_NO_EVA,
1565 { "mcu", ASE_MCU, 0,
1566 OPTION_MCU, OPTION_NO_MCU,
1569 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1570 { "mdmx", ASE_MDMX, 0,
1571 OPTION_MDMX, OPTION_NO_MDMX,
1574 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1575 { "mips3d", ASE_MIPS3D, 0,
1576 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1580 OPTION_MT, OPTION_NO_MT,
1583 { "smartmips", ASE_SMARTMIPS, 0,
1584 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1587 { "virt", ASE_VIRT, ASE_VIRT64,
1588 OPTION_VIRT, OPTION_NO_VIRT,
1592 /* The set of ASEs that require -mfp64. */
1593 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1595 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1596 static const unsigned int mips_ase_groups[] = {
1602 The following pseudo-ops from the Kane and Heinrich MIPS book
1603 should be defined here, but are currently unsupported: .alias,
1604 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1606 The following pseudo-ops from the Kane and Heinrich MIPS book are
1607 specific to the type of debugging information being generated, and
1608 should be defined by the object format: .aent, .begin, .bend,
1609 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1612 The following pseudo-ops from the Kane and Heinrich MIPS book are
1613 not MIPS CPU specific, but are also not specific to the object file
1614 format. This file is probably the best place to define them, but
1615 they are not currently supported: .asm0, .endr, .lab, .struct. */
1617 static const pseudo_typeS mips_pseudo_table[] =
1619 /* MIPS specific pseudo-ops. */
1620 {"option", s_option, 0},
1621 {"set", s_mipsset, 0},
1622 {"rdata", s_change_sec, 'r'},
1623 {"sdata", s_change_sec, 's'},
1624 {"livereg", s_ignore, 0},
1625 {"abicalls", s_abicalls, 0},
1626 {"cpload", s_cpload, 0},
1627 {"cpsetup", s_cpsetup, 0},
1628 {"cplocal", s_cplocal, 0},
1629 {"cprestore", s_cprestore, 0},
1630 {"cpreturn", s_cpreturn, 0},
1631 {"dtprelword", s_dtprelword, 0},
1632 {"dtpreldword", s_dtpreldword, 0},
1633 {"tprelword", s_tprelword, 0},
1634 {"tpreldword", s_tpreldword, 0},
1635 {"gpvalue", s_gpvalue, 0},
1636 {"gpword", s_gpword, 0},
1637 {"gpdword", s_gpdword, 0},
1638 {"ehword", s_ehword, 0},
1639 {"cpadd", s_cpadd, 0},
1640 {"insn", s_insn, 0},
1643 /* Relatively generic pseudo-ops that happen to be used on MIPS
1645 {"asciiz", stringer, 8 + 1},
1646 {"bss", s_change_sec, 'b'},
1648 {"half", s_cons, 1},
1649 {"dword", s_cons, 3},
1650 {"weakext", s_mips_weakext, 0},
1651 {"origin", s_org, 0},
1652 {"repeat", s_rept, 0},
1654 /* For MIPS this is non-standard, but we define it for consistency. */
1655 {"sbss", s_change_sec, 'B'},
1657 /* These pseudo-ops are defined in read.c, but must be overridden
1658 here for one reason or another. */
1659 {"align", s_align, 0},
1660 {"byte", s_cons, 0},
1661 {"data", s_change_sec, 'd'},
1662 {"double", s_float_cons, 'd'},
1663 {"float", s_float_cons, 'f'},
1664 {"globl", s_mips_globl, 0},
1665 {"global", s_mips_globl, 0},
1666 {"hword", s_cons, 1},
1668 {"long", s_cons, 2},
1669 {"octa", s_cons, 4},
1670 {"quad", s_cons, 3},
1671 {"section", s_change_section, 0},
1672 {"short", s_cons, 1},
1673 {"single", s_float_cons, 'f'},
1674 {"stabd", s_mips_stab, 'd'},
1675 {"stabn", s_mips_stab, 'n'},
1676 {"stabs", s_mips_stab, 's'},
1677 {"text", s_change_sec, 't'},
1678 {"word", s_cons, 2},
1680 { "extern", ecoff_directive_extern, 0},
1685 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1687 /* These pseudo-ops should be defined by the object file format.
1688 However, a.out doesn't support them, so we have versions here. */
1689 {"aent", s_mips_ent, 1},
1690 {"bgnb", s_ignore, 0},
1691 {"end", s_mips_end, 0},
1692 {"endb", s_ignore, 0},
1693 {"ent", s_mips_ent, 0},
1694 {"file", s_mips_file, 0},
1695 {"fmask", s_mips_mask, 'F'},
1696 {"frame", s_mips_frame, 0},
1697 {"loc", s_mips_loc, 0},
1698 {"mask", s_mips_mask, 'R'},
1699 {"verstamp", s_ignore, 0},
1703 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1704 purpose of the `.dc.a' internal pseudo-op. */
1707 mips_address_bytes (void)
1709 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1712 extern void pop_insert (const pseudo_typeS *);
1715 mips_pop_insert (void)
1717 pop_insert (mips_pseudo_table);
1718 if (! ECOFF_DEBUGGING)
1719 pop_insert (mips_nonecoff_pseudo_table);
1722 /* Symbols labelling the current insn. */
1724 struct insn_label_list
1726 struct insn_label_list *next;
1730 static struct insn_label_list *free_insn_labels;
1731 #define label_list tc_segment_info_data.labels
1733 static void mips_clear_insn_labels (void);
1734 static void mips_mark_labels (void);
1735 static void mips_compressed_mark_labels (void);
1738 mips_clear_insn_labels (void)
1740 register struct insn_label_list **pl;
1741 segment_info_type *si;
1745 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1748 si = seg_info (now_seg);
1749 *pl = si->label_list;
1750 si->label_list = NULL;
1754 /* Mark instruction labels in MIPS16/microMIPS mode. */
1757 mips_mark_labels (void)
1759 if (HAVE_CODE_COMPRESSION)
1760 mips_compressed_mark_labels ();
1763 static char *expr_end;
1765 /* Expressions which appear in macro instructions. These are set by
1766 mips_ip and read by macro. */
1768 static expressionS imm_expr;
1769 static expressionS imm2_expr;
1771 /* The relocatable field in an instruction and the relocs associated
1772 with it. These variables are used for instructions like LUI and
1773 JAL as well as true offsets. They are also used for address
1774 operands in macros. */
1776 static expressionS offset_expr;
1777 static bfd_reloc_code_real_type offset_reloc[3]
1778 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1780 /* This is set to the resulting size of the instruction to be produced
1781 by mips16_ip if an explicit extension is used or by mips_ip if an
1782 explicit size is supplied. */
1784 static unsigned int forced_insn_length;
1786 /* True if we are assembling an instruction. All dot symbols defined during
1787 this time should be treated as code labels. */
1789 static bfd_boolean mips_assembling_insn;
1791 /* The pdr segment for per procedure frame/regmask info. Not used for
1794 static segT pdr_seg;
1796 /* The default target format to use. */
1798 #if defined (TE_FreeBSD)
1799 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1800 #elif defined (TE_TMIPS)
1801 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1803 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1807 mips_target_format (void)
1809 switch (OUTPUT_FLAVOR)
1811 case bfd_target_elf_flavour:
1813 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1814 return (target_big_endian
1815 ? "elf32-bigmips-vxworks"
1816 : "elf32-littlemips-vxworks");
1818 return (target_big_endian
1819 ? (HAVE_64BIT_OBJECTS
1820 ? ELF_TARGET ("elf64-", "big")
1822 ? ELF_TARGET ("elf32-n", "big")
1823 : ELF_TARGET ("elf32-", "big")))
1824 : (HAVE_64BIT_OBJECTS
1825 ? ELF_TARGET ("elf64-", "little")
1827 ? ELF_TARGET ("elf32-n", "little")
1828 : ELF_TARGET ("elf32-", "little"))));
1835 /* Return the ISA revision that is currently in use, or 0 if we are
1836 generating code for MIPS V or below. */
1841 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1844 /* microMIPS implies revision 2 or above. */
1845 if (mips_opts.micromips)
1848 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1854 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1857 mips_ase_mask (unsigned int flags)
1861 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1862 if (flags & mips_ase_groups[i])
1863 flags |= mips_ase_groups[i];
1867 /* Check whether the current ISA supports ASE. Issue a warning if
1871 mips_check_isa_supports_ase (const struct mips_ase *ase)
1875 static unsigned int warned_isa;
1876 static unsigned int warned_fp32;
1878 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1879 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1881 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1882 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1883 && (warned_isa & ase->flags) != ase->flags)
1885 warned_isa |= ase->flags;
1886 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1887 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1889 as_warn (_("The %d-bit %s architecture does not support the"
1890 " `%s' extension"), size, base, ase->name);
1892 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1893 ase->name, base, size, min_rev);
1895 if ((ase->flags & FP64_ASES)
1897 && (warned_fp32 & ase->flags) != ase->flags)
1899 warned_fp32 |= ase->flags;
1900 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1904 /* Check all enabled ASEs to see whether they are supported by the
1905 chosen architecture. */
1908 mips_check_isa_supports_ases (void)
1910 unsigned int i, mask;
1912 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1914 mask = mips_ase_mask (mips_ases[i].flags);
1915 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1916 mips_check_isa_supports_ase (&mips_ases[i]);
1920 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1921 that were affected. */
1924 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1928 mask = mips_ase_mask (ase->flags);
1929 mips_opts.ase &= ~mask;
1931 mips_opts.ase |= ase->flags;
1935 /* Return the ASE called NAME, or null if none. */
1937 static const struct mips_ase *
1938 mips_lookup_ase (const char *name)
1942 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1943 if (strcmp (name, mips_ases[i].name) == 0)
1944 return &mips_ases[i];
1948 /* Return the length of a microMIPS instruction in bytes. If bits of
1949 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1950 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1951 major opcode) will require further modifications to the opcode
1954 static inline unsigned int
1955 micromips_insn_length (const struct mips_opcode *mo)
1957 return (mo->mask >> 16) == 0 ? 2 : 4;
1960 /* Return the length of MIPS16 instruction OPCODE. */
1962 static inline unsigned int
1963 mips16_opcode_length (unsigned long opcode)
1965 return (opcode >> 16) == 0 ? 2 : 4;
1968 /* Return the length of instruction INSN. */
1970 static inline unsigned int
1971 insn_length (const struct mips_cl_insn *insn)
1973 if (mips_opts.micromips)
1974 return micromips_insn_length (insn->insn_mo);
1975 else if (mips_opts.mips16)
1976 return mips16_opcode_length (insn->insn_opcode);
1981 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1984 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1989 insn->insn_opcode = mo->match;
1992 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1993 insn->fixp[i] = NULL;
1994 insn->fixed_p = (mips_opts.noreorder > 0);
1995 insn->noreorder_p = (mips_opts.noreorder > 0);
1996 insn->mips16_absolute_jump_p = 0;
1997 insn->complete_p = 0;
1998 insn->cleared_p = 0;
2001 /* Get a list of all the operands in INSN. */
2003 static const struct mips_operand_array *
2004 insn_operands (const struct mips_cl_insn *insn)
2006 if (insn->insn_mo >= &mips_opcodes[0]
2007 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2008 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2010 if (insn->insn_mo >= &mips16_opcodes[0]
2011 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2012 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2014 if (insn->insn_mo >= µmips_opcodes[0]
2015 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2016 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2021 /* Get a description of operand OPNO of INSN. */
2023 static const struct mips_operand *
2024 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2026 const struct mips_operand_array *operands;
2028 operands = insn_operands (insn);
2029 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2031 return operands->operand[opno];
2034 /* Install UVAL as the value of OPERAND in INSN. */
2037 insn_insert_operand (struct mips_cl_insn *insn,
2038 const struct mips_operand *operand, unsigned int uval)
2040 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2043 /* Extract the value of OPERAND from INSN. */
2045 static inline unsigned
2046 insn_extract_operand (const struct mips_cl_insn *insn,
2047 const struct mips_operand *operand)
2049 return mips_extract_operand (operand, insn->insn_opcode);
2052 /* Record the current MIPS16/microMIPS mode in now_seg. */
2055 mips_record_compressed_mode (void)
2057 segment_info_type *si;
2059 si = seg_info (now_seg);
2060 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2061 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2062 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2063 si->tc_segment_info_data.micromips = mips_opts.micromips;
2066 /* Read a standard MIPS instruction from BUF. */
2068 static unsigned long
2069 read_insn (char *buf)
2071 if (target_big_endian)
2072 return bfd_getb32 ((bfd_byte *) buf);
2074 return bfd_getl32 ((bfd_byte *) buf);
2077 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2081 write_insn (char *buf, unsigned int insn)
2083 md_number_to_chars (buf, insn, 4);
2087 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2088 has length LENGTH. */
2090 static unsigned long
2091 read_compressed_insn (char *buf, unsigned int length)
2097 for (i = 0; i < length; i += 2)
2100 if (target_big_endian)
2101 insn |= bfd_getb16 ((char *) buf);
2103 insn |= bfd_getl16 ((char *) buf);
2109 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2110 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2113 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2117 for (i = 0; i < length; i += 2)
2118 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2119 return buf + length;
2122 /* Install INSN at the location specified by its "frag" and "where" fields. */
2125 install_insn (const struct mips_cl_insn *insn)
2127 char *f = insn->frag->fr_literal + insn->where;
2128 if (HAVE_CODE_COMPRESSION)
2129 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2131 write_insn (f, insn->insn_opcode);
2132 mips_record_compressed_mode ();
2135 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2136 and install the opcode in the new location. */
2139 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2144 insn->where = where;
2145 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2146 if (insn->fixp[i] != NULL)
2148 insn->fixp[i]->fx_frag = frag;
2149 insn->fixp[i]->fx_where = where;
2151 install_insn (insn);
2154 /* Add INSN to the end of the output. */
2157 add_fixed_insn (struct mips_cl_insn *insn)
2159 char *f = frag_more (insn_length (insn));
2160 move_insn (insn, frag_now, f - frag_now->fr_literal);
2163 /* Start a variant frag and move INSN to the start of the variant part,
2164 marking it as fixed. The other arguments are as for frag_var. */
2167 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2168 relax_substateT subtype, symbolS *symbol, offsetT offset)
2170 frag_grow (max_chars);
2171 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2173 frag_var (rs_machine_dependent, max_chars, var,
2174 subtype, symbol, offset, NULL);
2177 /* Insert N copies of INSN into the history buffer, starting at
2178 position FIRST. Neither FIRST nor N need to be clipped. */
2181 insert_into_history (unsigned int first, unsigned int n,
2182 const struct mips_cl_insn *insn)
2184 if (mips_relax.sequence != 2)
2188 for (i = ARRAY_SIZE (history); i-- > first;)
2190 history[i] = history[i - n];
2196 /* Clear the error in insn_error. */
2199 clear_insn_error (void)
2201 memset (&insn_error, 0, sizeof (insn_error));
2204 /* Possibly record error message MSG for the current instruction.
2205 If the error is about a particular argument, ARGNUM is the 1-based
2206 number of that argument, otherwise it is 0. FORMAT is the format
2207 of MSG. Return true if MSG was used, false if the current message
2211 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2216 /* Give priority to errors against specific arguments, and to
2217 the first whole-instruction message. */
2223 /* Keep insn_error if it is against a later argument. */
2224 if (argnum < insn_error.min_argnum)
2227 /* If both errors are against the same argument but are different,
2228 give up on reporting a specific error for this argument.
2229 See the comment about mips_insn_error for details. */
2230 if (argnum == insn_error.min_argnum
2232 && strcmp (insn_error.msg, msg) != 0)
2235 insn_error.min_argnum += 1;
2239 insn_error.min_argnum = argnum;
2240 insn_error.format = format;
2241 insn_error.msg = msg;
2245 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2246 as for set_insn_error_format. */
2249 set_insn_error (int argnum, const char *msg)
2251 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2254 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2255 as for set_insn_error_format. */
2258 set_insn_error_i (int argnum, const char *msg, int i)
2260 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2264 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2265 are as for set_insn_error_format. */
2268 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2270 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2272 insn_error.u.ss[0] = s1;
2273 insn_error.u.ss[1] = s2;
2277 /* Report the error in insn_error, which is against assembly code STR. */
2280 report_insn_error (const char *str)
2284 msg = ACONCAT ((insn_error.msg, " `%s'", NULL));
2285 switch (insn_error.format)
2292 as_bad (msg, insn_error.u.i, str);
2296 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2301 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2302 the idea is to make it obvious at a glance that each errata is
2306 init_vr4120_conflicts (void)
2308 #define CONFLICT(FIRST, SECOND) \
2309 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2311 /* Errata 21 - [D]DIV[U] after [D]MACC */
2312 CONFLICT (MACC, DIV);
2313 CONFLICT (DMACC, DIV);
2315 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2316 CONFLICT (DMULT, DMULT);
2317 CONFLICT (DMULT, DMACC);
2318 CONFLICT (DMACC, DMULT);
2319 CONFLICT (DMACC, DMACC);
2321 /* Errata 24 - MT{LO,HI} after [D]MACC */
2322 CONFLICT (MACC, MTHILO);
2323 CONFLICT (DMACC, MTHILO);
2325 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2326 instruction is executed immediately after a MACC or DMACC
2327 instruction, the result of [either instruction] is incorrect." */
2328 CONFLICT (MACC, MULT);
2329 CONFLICT (MACC, DMULT);
2330 CONFLICT (DMACC, MULT);
2331 CONFLICT (DMACC, DMULT);
2333 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2334 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2335 DDIV or DDIVU instruction, the result of the MACC or
2336 DMACC instruction is incorrect.". */
2337 CONFLICT (DMULT, MACC);
2338 CONFLICT (DMULT, DMACC);
2339 CONFLICT (DIV, MACC);
2340 CONFLICT (DIV, DMACC);
2350 #define RNUM_MASK 0x00000ff
2351 #define RTYPE_MASK 0x0efff00
2352 #define RTYPE_NUM 0x0000100
2353 #define RTYPE_FPU 0x0000200
2354 #define RTYPE_FCC 0x0000400
2355 #define RTYPE_VEC 0x0000800
2356 #define RTYPE_GP 0x0001000
2357 #define RTYPE_CP0 0x0002000
2358 #define RTYPE_PC 0x0004000
2359 #define RTYPE_ACC 0x0008000
2360 #define RTYPE_CCC 0x0010000
2361 #define RTYPE_VI 0x0020000
2362 #define RTYPE_VF 0x0040000
2363 #define RTYPE_R5900_I 0x0080000
2364 #define RTYPE_R5900_Q 0x0100000
2365 #define RTYPE_R5900_R 0x0200000
2366 #define RTYPE_R5900_ACC 0x0400000
2367 #define RWARN 0x8000000
2369 #define GENERIC_REGISTER_NUMBERS \
2370 {"$0", RTYPE_NUM | 0}, \
2371 {"$1", RTYPE_NUM | 1}, \
2372 {"$2", RTYPE_NUM | 2}, \
2373 {"$3", RTYPE_NUM | 3}, \
2374 {"$4", RTYPE_NUM | 4}, \
2375 {"$5", RTYPE_NUM | 5}, \
2376 {"$6", RTYPE_NUM | 6}, \
2377 {"$7", RTYPE_NUM | 7}, \
2378 {"$8", RTYPE_NUM | 8}, \
2379 {"$9", RTYPE_NUM | 9}, \
2380 {"$10", RTYPE_NUM | 10}, \
2381 {"$11", RTYPE_NUM | 11}, \
2382 {"$12", RTYPE_NUM | 12}, \
2383 {"$13", RTYPE_NUM | 13}, \
2384 {"$14", RTYPE_NUM | 14}, \
2385 {"$15", RTYPE_NUM | 15}, \
2386 {"$16", RTYPE_NUM | 16}, \
2387 {"$17", RTYPE_NUM | 17}, \
2388 {"$18", RTYPE_NUM | 18}, \
2389 {"$19", RTYPE_NUM | 19}, \
2390 {"$20", RTYPE_NUM | 20}, \
2391 {"$21", RTYPE_NUM | 21}, \
2392 {"$22", RTYPE_NUM | 22}, \
2393 {"$23", RTYPE_NUM | 23}, \
2394 {"$24", RTYPE_NUM | 24}, \
2395 {"$25", RTYPE_NUM | 25}, \
2396 {"$26", RTYPE_NUM | 26}, \
2397 {"$27", RTYPE_NUM | 27}, \
2398 {"$28", RTYPE_NUM | 28}, \
2399 {"$29", RTYPE_NUM | 29}, \
2400 {"$30", RTYPE_NUM | 30}, \
2401 {"$31", RTYPE_NUM | 31}
2403 #define FPU_REGISTER_NAMES \
2404 {"$f0", RTYPE_FPU | 0}, \
2405 {"$f1", RTYPE_FPU | 1}, \
2406 {"$f2", RTYPE_FPU | 2}, \
2407 {"$f3", RTYPE_FPU | 3}, \
2408 {"$f4", RTYPE_FPU | 4}, \
2409 {"$f5", RTYPE_FPU | 5}, \
2410 {"$f6", RTYPE_FPU | 6}, \
2411 {"$f7", RTYPE_FPU | 7}, \
2412 {"$f8", RTYPE_FPU | 8}, \
2413 {"$f9", RTYPE_FPU | 9}, \
2414 {"$f10", RTYPE_FPU | 10}, \
2415 {"$f11", RTYPE_FPU | 11}, \
2416 {"$f12", RTYPE_FPU | 12}, \
2417 {"$f13", RTYPE_FPU | 13}, \
2418 {"$f14", RTYPE_FPU | 14}, \
2419 {"$f15", RTYPE_FPU | 15}, \
2420 {"$f16", RTYPE_FPU | 16}, \
2421 {"$f17", RTYPE_FPU | 17}, \
2422 {"$f18", RTYPE_FPU | 18}, \
2423 {"$f19", RTYPE_FPU | 19}, \
2424 {"$f20", RTYPE_FPU | 20}, \
2425 {"$f21", RTYPE_FPU | 21}, \
2426 {"$f22", RTYPE_FPU | 22}, \
2427 {"$f23", RTYPE_FPU | 23}, \
2428 {"$f24", RTYPE_FPU | 24}, \
2429 {"$f25", RTYPE_FPU | 25}, \
2430 {"$f26", RTYPE_FPU | 26}, \
2431 {"$f27", RTYPE_FPU | 27}, \
2432 {"$f28", RTYPE_FPU | 28}, \
2433 {"$f29", RTYPE_FPU | 29}, \
2434 {"$f30", RTYPE_FPU | 30}, \
2435 {"$f31", RTYPE_FPU | 31}
2437 #define FPU_CONDITION_CODE_NAMES \
2438 {"$fcc0", RTYPE_FCC | 0}, \
2439 {"$fcc1", RTYPE_FCC | 1}, \
2440 {"$fcc2", RTYPE_FCC | 2}, \
2441 {"$fcc3", RTYPE_FCC | 3}, \
2442 {"$fcc4", RTYPE_FCC | 4}, \
2443 {"$fcc5", RTYPE_FCC | 5}, \
2444 {"$fcc6", RTYPE_FCC | 6}, \
2445 {"$fcc7", RTYPE_FCC | 7}
2447 #define COPROC_CONDITION_CODE_NAMES \
2448 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2449 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2450 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2451 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2452 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2453 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2454 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2455 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2457 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2458 {"$a4", RTYPE_GP | 8}, \
2459 {"$a5", RTYPE_GP | 9}, \
2460 {"$a6", RTYPE_GP | 10}, \
2461 {"$a7", RTYPE_GP | 11}, \
2462 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2463 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2464 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2465 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2466 {"$t0", RTYPE_GP | 12}, \
2467 {"$t1", RTYPE_GP | 13}, \
2468 {"$t2", RTYPE_GP | 14}, \
2469 {"$t3", RTYPE_GP | 15}
2471 #define O32_SYMBOLIC_REGISTER_NAMES \
2472 {"$t0", RTYPE_GP | 8}, \
2473 {"$t1", RTYPE_GP | 9}, \
2474 {"$t2", RTYPE_GP | 10}, \
2475 {"$t3", RTYPE_GP | 11}, \
2476 {"$t4", RTYPE_GP | 12}, \
2477 {"$t5", RTYPE_GP | 13}, \
2478 {"$t6", RTYPE_GP | 14}, \
2479 {"$t7", RTYPE_GP | 15}, \
2480 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2481 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2482 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2483 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2485 /* Remaining symbolic register names */
2486 #define SYMBOLIC_REGISTER_NAMES \
2487 {"$zero", RTYPE_GP | 0}, \
2488 {"$at", RTYPE_GP | 1}, \
2489 {"$AT", RTYPE_GP | 1}, \
2490 {"$v0", RTYPE_GP | 2}, \
2491 {"$v1", RTYPE_GP | 3}, \
2492 {"$a0", RTYPE_GP | 4}, \
2493 {"$a1", RTYPE_GP | 5}, \
2494 {"$a2", RTYPE_GP | 6}, \
2495 {"$a3", RTYPE_GP | 7}, \
2496 {"$s0", RTYPE_GP | 16}, \
2497 {"$s1", RTYPE_GP | 17}, \
2498 {"$s2", RTYPE_GP | 18}, \
2499 {"$s3", RTYPE_GP | 19}, \
2500 {"$s4", RTYPE_GP | 20}, \
2501 {"$s5", RTYPE_GP | 21}, \
2502 {"$s6", RTYPE_GP | 22}, \
2503 {"$s7", RTYPE_GP | 23}, \
2504 {"$t8", RTYPE_GP | 24}, \
2505 {"$t9", RTYPE_GP | 25}, \
2506 {"$k0", RTYPE_GP | 26}, \
2507 {"$kt0", RTYPE_GP | 26}, \
2508 {"$k1", RTYPE_GP | 27}, \
2509 {"$kt1", RTYPE_GP | 27}, \
2510 {"$gp", RTYPE_GP | 28}, \
2511 {"$sp", RTYPE_GP | 29}, \
2512 {"$s8", RTYPE_GP | 30}, \
2513 {"$fp", RTYPE_GP | 30}, \
2514 {"$ra", RTYPE_GP | 31}
2516 #define MIPS16_SPECIAL_REGISTER_NAMES \
2517 {"$pc", RTYPE_PC | 0}
2519 #define MDMX_VECTOR_REGISTER_NAMES \
2520 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2521 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2522 {"$v2", RTYPE_VEC | 2}, \
2523 {"$v3", RTYPE_VEC | 3}, \
2524 {"$v4", RTYPE_VEC | 4}, \
2525 {"$v5", RTYPE_VEC | 5}, \
2526 {"$v6", RTYPE_VEC | 6}, \
2527 {"$v7", RTYPE_VEC | 7}, \
2528 {"$v8", RTYPE_VEC | 8}, \
2529 {"$v9", RTYPE_VEC | 9}, \
2530 {"$v10", RTYPE_VEC | 10}, \
2531 {"$v11", RTYPE_VEC | 11}, \
2532 {"$v12", RTYPE_VEC | 12}, \
2533 {"$v13", RTYPE_VEC | 13}, \
2534 {"$v14", RTYPE_VEC | 14}, \
2535 {"$v15", RTYPE_VEC | 15}, \
2536 {"$v16", RTYPE_VEC | 16}, \
2537 {"$v17", RTYPE_VEC | 17}, \
2538 {"$v18", RTYPE_VEC | 18}, \
2539 {"$v19", RTYPE_VEC | 19}, \
2540 {"$v20", RTYPE_VEC | 20}, \
2541 {"$v21", RTYPE_VEC | 21}, \
2542 {"$v22", RTYPE_VEC | 22}, \
2543 {"$v23", RTYPE_VEC | 23}, \
2544 {"$v24", RTYPE_VEC | 24}, \
2545 {"$v25", RTYPE_VEC | 25}, \
2546 {"$v26", RTYPE_VEC | 26}, \
2547 {"$v27", RTYPE_VEC | 27}, \
2548 {"$v28", RTYPE_VEC | 28}, \
2549 {"$v29", RTYPE_VEC | 29}, \
2550 {"$v30", RTYPE_VEC | 30}, \
2551 {"$v31", RTYPE_VEC | 31}
2553 #define R5900_I_NAMES \
2554 {"$I", RTYPE_R5900_I | 0}
2556 #define R5900_Q_NAMES \
2557 {"$Q", RTYPE_R5900_Q | 0}
2559 #define R5900_R_NAMES \
2560 {"$R", RTYPE_R5900_R | 0}
2562 #define R5900_ACC_NAMES \
2563 {"$ACC", RTYPE_R5900_ACC | 0 }
2565 #define MIPS_DSP_ACCUMULATOR_NAMES \
2566 {"$ac0", RTYPE_ACC | 0}, \
2567 {"$ac1", RTYPE_ACC | 1}, \
2568 {"$ac2", RTYPE_ACC | 2}, \
2569 {"$ac3", RTYPE_ACC | 3}
2571 static const struct regname reg_names[] = {
2572 GENERIC_REGISTER_NUMBERS,
2574 FPU_CONDITION_CODE_NAMES,
2575 COPROC_CONDITION_CODE_NAMES,
2577 /* The $txx registers depends on the abi,
2578 these will be added later into the symbol table from
2579 one of the tables below once mips_abi is set after
2580 parsing of arguments from the command line. */
2581 SYMBOLIC_REGISTER_NAMES,
2583 MIPS16_SPECIAL_REGISTER_NAMES,
2584 MDMX_VECTOR_REGISTER_NAMES,
2589 MIPS_DSP_ACCUMULATOR_NAMES,
2593 static const struct regname reg_names_o32[] = {
2594 O32_SYMBOLIC_REGISTER_NAMES,
2598 static const struct regname reg_names_n32n64[] = {
2599 N32N64_SYMBOLIC_REGISTER_NAMES,
2603 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2604 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2605 of these register symbols, return the associated vector register,
2606 otherwise return SYMVAL itself. */
2609 mips_prefer_vec_regno (unsigned int symval)
2611 if ((symval & -2) == (RTYPE_GP | 2))
2612 return RTYPE_VEC | (symval & 1);
2616 /* Return true if string [S, E) is a valid register name, storing its
2617 symbol value in *SYMVAL_PTR if so. */
2620 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2625 /* Terminate name. */
2629 /* Look up the name. */
2630 symbol = symbol_find (s);
2633 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2636 *symval_ptr = S_GET_VALUE (symbol);
2640 /* Return true if the string at *SPTR is a valid register name. Allow it
2641 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2644 When returning true, move *SPTR past the register, store the
2645 register's symbol value in *SYMVAL_PTR and the channel mask in
2646 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2647 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2648 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2651 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2652 unsigned int *channels_ptr)
2656 unsigned int channels, symval, bit;
2658 /* Find end of name. */
2660 if (is_name_beginner (*e))
2662 while (is_part_of_name (*e))
2666 if (!mips_parse_register_1 (s, e, &symval))
2671 /* Eat characters from the end of the string that are valid
2672 channel suffixes. The preceding register must be $ACC or
2673 end with a digit, so there is no ambiguity. */
2676 for (q = "wzyx"; *q; q++, bit <<= 1)
2677 if (m > s && m[-1] == *q)
2684 || !mips_parse_register_1 (s, m, &symval)
2685 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
2690 *symval_ptr = symval;
2692 *channels_ptr = channels;
2696 /* Check if SPTR points at a valid register specifier according to TYPES.
2697 If so, then return 1, advance S to consume the specifier and store
2698 the register's number in REGNOP, otherwise return 0. */
2701 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2705 if (mips_parse_register (s, ®no, NULL))
2707 if (types & RTYPE_VEC)
2708 regno = mips_prefer_vec_regno (regno);
2717 as_warn (_("Unrecognized register name `%s'"), *s);
2722 return regno <= RNUM_MASK;
2725 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
2726 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
2729 mips_parse_vu0_channels (char *s, unsigned int *channels)
2734 for (i = 0; i < 4; i++)
2735 if (*s == "xyzw"[i])
2737 *channels |= 1 << (3 - i);
2743 /* Token types for parsed operand lists. */
2744 enum mips_operand_token_type {
2745 /* A plain register, e.g. $f2. */
2748 /* A 4-bit XYZW channel mask. */
2751 /* An element of a vector, e.g. $v0[1]. */
2754 /* A continuous range of registers, e.g. $s0-$s4. */
2757 /* A (possibly relocated) expression. */
2760 /* A floating-point value. */
2763 /* A single character. This can be '(', ')' or ',', but '(' only appears
2767 /* A doubled character, either "--" or "++". */
2770 /* The end of the operand list. */
2774 /* A parsed operand token. */
2775 struct mips_operand_token
2777 /* The type of token. */
2778 enum mips_operand_token_type type;
2781 /* The register symbol value for an OT_REG. */
2784 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
2785 unsigned int channels;
2787 /* The register symbol value and index for an OT_REG_ELEMENT. */
2793 /* The two register symbol values involved in an OT_REG_RANGE. */
2795 unsigned int regno1;
2796 unsigned int regno2;
2799 /* The value of an OT_INTEGER. The value is represented as an
2800 expression and the relocation operators that were applied to
2801 that expression. The reloc entries are BFD_RELOC_UNUSED if no
2802 relocation operators were used. */
2805 bfd_reloc_code_real_type relocs[3];
2808 /* The binary data for an OT_FLOAT constant, and the number of bytes
2811 unsigned char data[8];
2815 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
2820 /* An obstack used to construct lists of mips_operand_tokens. */
2821 static struct obstack mips_operand_tokens;
2823 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
2826 mips_add_token (struct mips_operand_token *token,
2827 enum mips_operand_token_type type)
2830 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
2833 /* Check whether S is '(' followed by a register name. Add OT_CHAR
2834 and OT_REG tokens for them if so, and return a pointer to the first
2835 unconsumed character. Return null otherwise. */
2838 mips_parse_base_start (char *s)
2840 struct mips_operand_token token;
2841 unsigned int regno, channels;
2842 bfd_boolean decrement_p;
2848 SKIP_SPACE_TABS (s);
2850 /* Only match "--" as part of a base expression. In other contexts "--X"
2851 is a double negative. */
2852 decrement_p = (s[0] == '-' && s[1] == '-');
2856 SKIP_SPACE_TABS (s);
2859 /* Allow a channel specifier because that leads to better error messages
2860 than treating something like "$vf0x++" as an expression. */
2861 if (!mips_parse_register (&s, ®no, &channels))
2865 mips_add_token (&token, OT_CHAR);
2870 mips_add_token (&token, OT_DOUBLE_CHAR);
2873 token.u.regno = regno;
2874 mips_add_token (&token, OT_REG);
2878 token.u.channels = channels;
2879 mips_add_token (&token, OT_CHANNELS);
2882 /* For consistency, only match "++" as part of base expressions too. */
2883 SKIP_SPACE_TABS (s);
2884 if (s[0] == '+' && s[1] == '+')
2888 mips_add_token (&token, OT_DOUBLE_CHAR);
2894 /* Parse one or more tokens from S. Return a pointer to the first
2895 unconsumed character on success. Return null if an error was found
2896 and store the error text in insn_error. FLOAT_FORMAT is as for
2897 mips_parse_arguments. */
2900 mips_parse_argument_token (char *s, char float_format)
2902 char *end, *save_in, *err;
2903 unsigned int regno1, regno2, channels;
2904 struct mips_operand_token token;
2906 /* First look for "($reg", since we want to treat that as an
2907 OT_CHAR and OT_REG rather than an expression. */
2908 end = mips_parse_base_start (s);
2912 /* Handle other characters that end up as OT_CHARs. */
2913 if (*s == ')' || *s == ',')
2916 mips_add_token (&token, OT_CHAR);
2921 /* Handle tokens that start with a register. */
2922 if (mips_parse_register (&s, ®no1, &channels))
2926 /* A register and a VU0 channel suffix. */
2927 token.u.regno = regno1;
2928 mips_add_token (&token, OT_REG);
2930 token.u.channels = channels;
2931 mips_add_token (&token, OT_CHANNELS);
2935 SKIP_SPACE_TABS (s);
2938 /* A register range. */
2940 SKIP_SPACE_TABS (s);
2941 if (!mips_parse_register (&s, ®no2, NULL))
2943 set_insn_error (0, _("Invalid register range"));
2947 token.u.reg_range.regno1 = regno1;
2948 token.u.reg_range.regno2 = regno2;
2949 mips_add_token (&token, OT_REG_RANGE);
2954 /* A vector element. */
2955 expressionS element;
2958 SKIP_SPACE_TABS (s);
2959 my_getExpression (&element, s);
2960 if (element.X_op != O_constant)
2962 set_insn_error (0, _("Vector element must be constant"));
2966 SKIP_SPACE_TABS (s);
2969 set_insn_error (0, _("Missing `]'"));
2974 token.u.reg_element.regno = regno1;
2975 token.u.reg_element.index = element.X_add_number;
2976 mips_add_token (&token, OT_REG_ELEMENT);
2980 /* Looks like just a plain register. */
2981 token.u.regno = regno1;
2982 mips_add_token (&token, OT_REG);
2988 /* First try to treat expressions as floats. */
2989 save_in = input_line_pointer;
2990 input_line_pointer = s;
2991 err = md_atof (float_format, (char *) token.u.flt.data,
2992 &token.u.flt.length);
2993 end = input_line_pointer;
2994 input_line_pointer = save_in;
2997 set_insn_error (0, err);
3002 mips_add_token (&token, OT_FLOAT);
3007 /* Treat everything else as an integer expression. */
3008 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3009 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3010 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3011 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3013 mips_add_token (&token, OT_INTEGER);
3017 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3018 if expressions should be treated as 32-bit floating-point constants,
3019 'd' if they should be treated as 64-bit floating-point constants,
3020 or 0 if they should be treated as integer expressions (the usual case).
3022 Return a list of tokens on success, otherwise return 0. The caller
3023 must obstack_free the list after use. */
3025 static struct mips_operand_token *
3026 mips_parse_arguments (char *s, char float_format)
3028 struct mips_operand_token token;
3030 SKIP_SPACE_TABS (s);
3033 s = mips_parse_argument_token (s, float_format);
3036 obstack_free (&mips_operand_tokens,
3037 obstack_finish (&mips_operand_tokens));
3040 SKIP_SPACE_TABS (s);
3042 mips_add_token (&token, OT_END);
3043 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3046 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3047 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3050 is_opcode_valid (const struct mips_opcode *mo)
3052 int isa = mips_opts.isa;
3053 int ase = mips_opts.ase;
3057 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3058 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3059 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3060 ase |= mips_ases[i].flags64;
3062 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3065 /* Check whether the instruction or macro requires single-precision or
3066 double-precision floating-point support. Note that this information is
3067 stored differently in the opcode table for insns and macros. */
3068 if (mo->pinfo == INSN_MACRO)
3070 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3071 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3075 fp_s = mo->pinfo & FP_S;
3076 fp_d = mo->pinfo & FP_D;
3079 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3082 if (fp_s && mips_opts.soft_float)
3088 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3089 selected ISA and architecture. */
3092 is_opcode_valid_16 (const struct mips_opcode *mo)
3094 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3097 /* Return TRUE if the size of the microMIPS opcode MO matches one
3098 explicitly requested. Always TRUE in the standard MIPS mode. */
3101 is_size_valid (const struct mips_opcode *mo)
3103 if (!mips_opts.micromips)
3106 if (mips_opts.insn32)
3108 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3110 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3113 if (!forced_insn_length)
3115 if (mo->pinfo == INSN_MACRO)
3117 return forced_insn_length == micromips_insn_length (mo);
3120 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3121 of the preceding instruction. Always TRUE in the standard MIPS mode.
3123 We don't accept macros in 16-bit delay slots to avoid a case where
3124 a macro expansion fails because it relies on a preceding 32-bit real
3125 instruction to have matched and does not handle the operands correctly.
3126 The only macros that may expand to 16-bit instructions are JAL that
3127 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3128 and BGT (that likewise cannot be placed in a delay slot) that decay to
3129 a NOP. In all these cases the macros precede any corresponding real
3130 instruction definitions in the opcode table, so they will match in the
3131 second pass where the size of the delay slot is ignored and therefore
3132 produce correct code. */
3135 is_delay_slot_valid (const struct mips_opcode *mo)
3137 if (!mips_opts.micromips)
3140 if (mo->pinfo == INSN_MACRO)
3141 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3142 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3143 && micromips_insn_length (mo) != 4)
3145 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3146 && micromips_insn_length (mo) != 2)
3152 /* For consistency checking, verify that all bits of OPCODE are specified
3153 either by the match/mask part of the instruction definition, or by the
3154 operand list. Also build up a list of operands in OPERANDS.
3156 INSN_BITS says which bits of the instruction are significant.
3157 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3158 provides the mips_operand description of each operand. DECODE_OPERAND
3159 is null for MIPS16 instructions. */
3162 validate_mips_insn (const struct mips_opcode *opcode,
3163 unsigned long insn_bits,
3164 const struct mips_operand *(*decode_operand) (const char *),
3165 struct mips_operand_array *operands)
3168 unsigned long used_bits, doubled, undefined, opno, mask;
3169 const struct mips_operand *operand;
3171 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3172 if ((mask & opcode->match) != opcode->match)
3174 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3175 opcode->name, opcode->args);
3180 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3181 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3182 for (s = opcode->args; *s; ++s)
3195 if (!decode_operand)
3196 operand = decode_mips16_operand (*s, FALSE);
3198 operand = decode_operand (s);
3199 if (!operand && opcode->pinfo != INSN_MACRO)
3201 as_bad (_("internal: unknown operand type: %s %s"),
3202 opcode->name, opcode->args);
3205 gas_assert (opno < MAX_OPERANDS);
3206 operands->operand[opno] = operand;
3207 if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3209 used_bits = mips_insert_operand (operand, used_bits, -1);
3210 if (operand->type == OP_MDMX_IMM_REG)
3211 /* Bit 5 is the format selector (OB vs QH). The opcode table
3212 has separate entries for each format. */
3213 used_bits &= ~(1 << (operand->lsb + 5));
3214 if (operand->type == OP_ENTRY_EXIT_LIST)
3215 used_bits &= ~(mask & 0x700);
3217 /* Skip prefix characters. */
3218 if (decode_operand && (*s == '+' || *s == 'm'))
3223 doubled = used_bits & mask & insn_bits;
3226 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3227 " %s %s"), doubled, opcode->name, opcode->args);
3231 undefined = ~used_bits & insn_bits;
3232 if (opcode->pinfo != INSN_MACRO && undefined)
3234 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3235 undefined, opcode->name, opcode->args);
3238 used_bits &= ~insn_bits;
3241 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3242 used_bits, opcode->name, opcode->args);
3248 /* The MIPS16 version of validate_mips_insn. */
3251 validate_mips16_insn (const struct mips_opcode *opcode,
3252 struct mips_operand_array *operands)
3254 if (opcode->args[0] == 'a' || opcode->args[0] == 'i')
3256 /* In this case OPCODE defines the first 16 bits in a 32-bit jump
3257 instruction. Use TMP to describe the full instruction. */
3258 struct mips_opcode tmp;
3263 return validate_mips_insn (&tmp, 0xffffffff, 0, operands);
3265 return validate_mips_insn (opcode, 0xffff, 0, operands);
3268 /* The microMIPS version of validate_mips_insn. */
3271 validate_micromips_insn (const struct mips_opcode *opc,
3272 struct mips_operand_array *operands)
3274 unsigned long insn_bits;
3275 unsigned long major;
3276 unsigned int length;
3278 if (opc->pinfo == INSN_MACRO)
3279 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3282 length = micromips_insn_length (opc);
3283 if (length != 2 && length != 4)
3285 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
3286 "%s %s"), length, opc->name, opc->args);
3289 major = opc->match >> (10 + 8 * (length - 2));
3290 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3291 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3293 as_bad (_("Internal error: bad microMIPS opcode "
3294 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3298 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3299 insn_bits = 1 << 4 * length;
3300 insn_bits <<= 4 * length;
3302 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3306 /* This function is called once, at assembler startup time. It should set up
3307 all the tables, etc. that the MD part of the assembler will need. */
3312 const char *retval = NULL;
3316 if (mips_pic != NO_PIC)
3318 if (g_switch_seen && g_switch_value != 0)
3319 as_bad (_("-G may not be used in position-independent code"));
3323 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
3324 as_warn (_("Could not set architecture and machine"));
3326 op_hash = hash_new ();
3328 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3329 for (i = 0; i < NUMOPCODES;)
3331 const char *name = mips_opcodes[i].name;
3333 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
3336 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
3337 mips_opcodes[i].name, retval);
3338 /* Probably a memory allocation problem? Give up now. */
3339 as_fatal (_("Broken assembler. No assembly attempted."));
3343 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3344 decode_mips_operand, &mips_operands[i]))
3346 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3348 create_insn (&nop_insn, mips_opcodes + i);
3349 if (mips_fix_loongson2f_nop)
3350 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3351 nop_insn.fixed_p = 1;
3355 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3358 mips16_op_hash = hash_new ();
3359 mips16_operands = XCNEWVEC (struct mips_operand_array,
3360 bfd_mips16_num_opcodes);
3363 while (i < bfd_mips16_num_opcodes)
3365 const char *name = mips16_opcodes[i].name;
3367 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
3369 as_fatal (_("internal: can't hash `%s': %s"),
3370 mips16_opcodes[i].name, retval);
3373 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3375 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3377 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3378 mips16_nop_insn.fixed_p = 1;
3382 while (i < bfd_mips16_num_opcodes
3383 && strcmp (mips16_opcodes[i].name, name) == 0);
3386 micromips_op_hash = hash_new ();
3387 micromips_operands = XCNEWVEC (struct mips_operand_array,
3388 bfd_micromips_num_opcodes);
3391 while (i < bfd_micromips_num_opcodes)
3393 const char *name = micromips_opcodes[i].name;
3395 retval = hash_insert (micromips_op_hash, name,
3396 (void *) µmips_opcodes[i]);
3398 as_fatal (_("internal: can't hash `%s': %s"),
3399 micromips_opcodes[i].name, retval);
3402 struct mips_cl_insn *micromips_nop_insn;
3404 if (!validate_micromips_insn (µmips_opcodes[i],
3405 µmips_operands[i]))
3408 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3410 if (micromips_insn_length (micromips_opcodes + i) == 2)
3411 micromips_nop_insn = µmips_nop16_insn;
3412 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3413 micromips_nop_insn = µmips_nop32_insn;
3417 if (micromips_nop_insn->insn_mo == NULL
3418 && strcmp (name, "nop") == 0)
3420 create_insn (micromips_nop_insn, micromips_opcodes + i);
3421 micromips_nop_insn->fixed_p = 1;
3425 while (++i < bfd_micromips_num_opcodes
3426 && strcmp (micromips_opcodes[i].name, name) == 0);
3430 as_fatal (_("Broken assembler. No assembly attempted."));
3432 /* We add all the general register names to the symbol table. This
3433 helps us detect invalid uses of them. */
3434 for (i = 0; reg_names[i].name; i++)
3435 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3436 reg_names[i].num, /* & RNUM_MASK, */
3437 &zero_address_frag));
3439 for (i = 0; reg_names_n32n64[i].name; i++)
3440 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3441 reg_names_n32n64[i].num, /* & RNUM_MASK, */
3442 &zero_address_frag));
3444 for (i = 0; reg_names_o32[i].name; i++)
3445 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3446 reg_names_o32[i].num, /* & RNUM_MASK, */
3447 &zero_address_frag));
3449 for (i = 0; i < 32; i++)
3453 /* R5900 VU0 floating-point register. */
3454 regname[sizeof (rename) - 1] = 0;
3455 snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
3456 symbol_table_insert (symbol_new (regname, reg_section,
3457 RTYPE_VF | i, &zero_address_frag));
3459 /* R5900 VU0 integer register. */
3460 snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
3461 symbol_table_insert (symbol_new (regname, reg_section,
3462 RTYPE_VI | i, &zero_address_frag));
3466 obstack_init (&mips_operand_tokens);
3468 mips_no_prev_insn ();
3471 mips_cprmask[0] = 0;
3472 mips_cprmask[1] = 0;
3473 mips_cprmask[2] = 0;
3474 mips_cprmask[3] = 0;
3476 /* set the default alignment for the text section (2**2) */
3477 record_alignment (text_section, 2);
3479 bfd_set_gp_size (stdoutput, g_switch_value);
3481 /* On a native system other than VxWorks, sections must be aligned
3482 to 16 byte boundaries. When configured for an embedded ELF
3483 target, we don't bother. */
3484 if (strncmp (TARGET_OS, "elf", 3) != 0
3485 && strncmp (TARGET_OS, "vxworks", 7) != 0)
3487 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
3488 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
3489 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
3492 /* Create a .reginfo section for register masks and a .mdebug
3493 section for debugging information. */
3501 subseg = now_subseg;
3503 /* The ABI says this section should be loaded so that the
3504 running program can access it. However, we don't load it
3505 if we are configured for an embedded target */
3506 flags = SEC_READONLY | SEC_DATA;
3507 if (strncmp (TARGET_OS, "elf", 3) != 0)
3508 flags |= SEC_ALLOC | SEC_LOAD;
3510 if (mips_abi != N64_ABI)
3512 sec = subseg_new (".reginfo", (subsegT) 0);
3514 bfd_set_section_flags (stdoutput, sec, flags);
3515 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
3517 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3521 /* The 64-bit ABI uses a .MIPS.options section rather than
3522 .reginfo section. */
3523 sec = subseg_new (".MIPS.options", (subsegT) 0);
3524 bfd_set_section_flags (stdoutput, sec, flags);
3525 bfd_set_section_alignment (stdoutput, sec, 3);
3527 /* Set up the option header. */
3529 Elf_Internal_Options opthdr;
3532 opthdr.kind = ODK_REGINFO;
3533 opthdr.size = (sizeof (Elf_External_Options)
3534 + sizeof (Elf64_External_RegInfo));
3537 f = frag_more (sizeof (Elf_External_Options));
3538 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3539 (Elf_External_Options *) f);
3541 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3545 if (ECOFF_DEBUGGING)
3547 sec = subseg_new (".mdebug", (subsegT) 0);
3548 (void) bfd_set_section_flags (stdoutput, sec,
3549 SEC_HAS_CONTENTS | SEC_READONLY);
3550 (void) bfd_set_section_alignment (stdoutput, sec, 2);
3552 else if (mips_flag_pdr)
3554 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3555 (void) bfd_set_section_flags (stdoutput, pdr_seg,
3556 SEC_READONLY | SEC_RELOC
3558 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
3561 subseg_set (seg, subseg);
3564 if (! ECOFF_DEBUGGING)
3567 if (mips_fix_vr4120)
3568 init_vr4120_conflicts ();
3574 mips_emit_delays ();
3575 if (! ECOFF_DEBUGGING)
3580 md_assemble (char *str)
3582 struct mips_cl_insn insn;
3583 bfd_reloc_code_real_type unused_reloc[3]
3584 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3586 imm_expr.X_op = O_absent;
3587 imm2_expr.X_op = O_absent;
3588 offset_expr.X_op = O_absent;
3589 offset_reloc[0] = BFD_RELOC_UNUSED;
3590 offset_reloc[1] = BFD_RELOC_UNUSED;
3591 offset_reloc[2] = BFD_RELOC_UNUSED;
3593 mips_mark_labels ();
3594 mips_assembling_insn = TRUE;
3595 clear_insn_error ();
3597 if (mips_opts.mips16)
3598 mips16_ip (str, &insn);
3601 mips_ip (str, &insn);
3602 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
3603 str, insn.insn_opcode));
3607 report_insn_error (str);
3608 else if (insn.insn_mo->pinfo == INSN_MACRO)
3611 if (mips_opts.mips16)
3612 mips16_macro (&insn);
3619 if (offset_expr.X_op != O_absent)
3620 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3622 append_insn (&insn, NULL, unused_reloc, FALSE);
3625 mips_assembling_insn = FALSE;
3628 /* Convenience functions for abstracting away the differences between
3629 MIPS16 and non-MIPS16 relocations. */
3631 static inline bfd_boolean
3632 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3636 case BFD_RELOC_MIPS16_JMP:
3637 case BFD_RELOC_MIPS16_GPREL:
3638 case BFD_RELOC_MIPS16_GOT16:
3639 case BFD_RELOC_MIPS16_CALL16:
3640 case BFD_RELOC_MIPS16_HI16_S:
3641 case BFD_RELOC_MIPS16_HI16:
3642 case BFD_RELOC_MIPS16_LO16:
3650 static inline bfd_boolean
3651 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3655 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3656 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3657 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3658 case BFD_RELOC_MICROMIPS_GPREL16:
3659 case BFD_RELOC_MICROMIPS_JMP:
3660 case BFD_RELOC_MICROMIPS_HI16:
3661 case BFD_RELOC_MICROMIPS_HI16_S:
3662 case BFD_RELOC_MICROMIPS_LO16:
3663 case BFD_RELOC_MICROMIPS_LITERAL:
3664 case BFD_RELOC_MICROMIPS_GOT16:
3665 case BFD_RELOC_MICROMIPS_CALL16:
3666 case BFD_RELOC_MICROMIPS_GOT_HI16:
3667 case BFD_RELOC_MICROMIPS_GOT_LO16:
3668 case BFD_RELOC_MICROMIPS_CALL_HI16:
3669 case BFD_RELOC_MICROMIPS_CALL_LO16:
3670 case BFD_RELOC_MICROMIPS_SUB:
3671 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3672 case BFD_RELOC_MICROMIPS_GOT_OFST:
3673 case BFD_RELOC_MICROMIPS_GOT_DISP:
3674 case BFD_RELOC_MICROMIPS_HIGHEST:
3675 case BFD_RELOC_MICROMIPS_HIGHER:
3676 case BFD_RELOC_MICROMIPS_SCN_DISP:
3677 case BFD_RELOC_MICROMIPS_JALR:
3685 static inline bfd_boolean
3686 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3688 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3691 static inline bfd_boolean
3692 got16_reloc_p (bfd_reloc_code_real_type reloc)
3694 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3695 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3698 static inline bfd_boolean
3699 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3701 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3702 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3705 static inline bfd_boolean
3706 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3708 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3709 || reloc == BFD_RELOC_MICROMIPS_LO16);
3712 static inline bfd_boolean
3713 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3715 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3718 static inline bfd_boolean
3719 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3721 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3722 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3725 /* Return true if RELOC is a PC-relative relocation that does not have
3726 full address range. */
3728 static inline bfd_boolean
3729 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3733 case BFD_RELOC_16_PCREL_S2:
3734 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3735 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3736 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3739 case BFD_RELOC_32_PCREL:
3740 return HAVE_64BIT_ADDRESSES;
3747 /* Return true if the given relocation might need a matching %lo().
3748 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3749 need a matching %lo() when applied to local symbols. */
3751 static inline bfd_boolean
3752 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3754 return (HAVE_IN_PLACE_ADDENDS
3755 && (hi16_reloc_p (reloc)
3756 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3757 all GOT16 relocations evaluate to "G". */
3758 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3761 /* Return the type of %lo() reloc needed by RELOC, given that
3762 reloc_needs_lo_p. */
3764 static inline bfd_reloc_code_real_type
3765 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3767 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3768 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3772 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3775 static inline bfd_boolean
3776 fixup_has_matching_lo_p (fixS *fixp)
3778 return (fixp->fx_next != NULL
3779 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3780 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3781 && fixp->fx_offset == fixp->fx_next->fx_offset);
3784 /* Move all labels in LABELS to the current insertion point. TEXT_P
3785 says whether the labels refer to text or data. */
3788 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3790 struct insn_label_list *l;
3793 for (l = labels; l != NULL; l = l->next)
3795 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3796 symbol_set_frag (l->label, frag_now);
3797 val = (valueT) frag_now_fix ();
3798 /* MIPS16/microMIPS text labels are stored as odd. */
3799 if (text_p && HAVE_CODE_COMPRESSION)
3801 S_SET_VALUE (l->label, val);
3805 /* Move all labels in insn_labels to the current insertion point
3806 and treat them as text labels. */
3809 mips_move_text_labels (void)
3811 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3815 s_is_linkonce (symbolS *sym, segT from_seg)
3817 bfd_boolean linkonce = FALSE;
3818 segT symseg = S_GET_SEGMENT (sym);
3820 if (symseg != from_seg && !S_IS_LOCAL (sym))
3822 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3824 /* The GNU toolchain uses an extension for ELF: a section
3825 beginning with the magic string .gnu.linkonce is a
3826 linkonce section. */
3827 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3828 sizeof ".gnu.linkonce" - 1) == 0)
3834 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3835 linker to handle them specially, such as generating jalx instructions
3836 when needed. We also make them odd for the duration of the assembly,
3837 in order to generate the right sort of code. We will make them even
3838 in the adjust_symtab routine, while leaving them marked. This is
3839 convenient for the debugger and the disassembler. The linker knows
3840 to make them odd again. */
3843 mips_compressed_mark_label (symbolS *label)
3845 gas_assert (HAVE_CODE_COMPRESSION);
3847 if (mips_opts.mips16)
3848 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3850 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3851 if ((S_GET_VALUE (label) & 1) == 0
3852 /* Don't adjust the address if the label is global or weak, or
3853 in a link-once section, since we'll be emitting symbol reloc
3854 references to it which will be patched up by the linker, and
3855 the final value of the symbol may or may not be MIPS16/microMIPS. */
3856 && !S_IS_WEAK (label)
3857 && !S_IS_EXTERNAL (label)
3858 && !s_is_linkonce (label, now_seg))
3859 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3862 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3865 mips_compressed_mark_labels (void)
3867 struct insn_label_list *l;
3869 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3870 mips_compressed_mark_label (l->label);
3873 /* End the current frag. Make it a variant frag and record the
3877 relax_close_frag (void)
3879 mips_macro_warning.first_frag = frag_now;
3880 frag_var (rs_machine_dependent, 0, 0,
3881 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3882 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3884 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3885 mips_relax.first_fixup = 0;
3888 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3889 See the comment above RELAX_ENCODE for more details. */
3892 relax_start (symbolS *symbol)
3894 gas_assert (mips_relax.sequence == 0);
3895 mips_relax.sequence = 1;
3896 mips_relax.symbol = symbol;
3899 /* Start generating the second version of a relaxable sequence.
3900 See the comment above RELAX_ENCODE for more details. */
3905 gas_assert (mips_relax.sequence == 1);
3906 mips_relax.sequence = 2;
3909 /* End the current relaxable sequence. */
3914 gas_assert (mips_relax.sequence == 2);
3915 relax_close_frag ();
3916 mips_relax.sequence = 0;
3919 /* Return true if IP is a delayed branch or jump. */
3921 static inline bfd_boolean
3922 delayed_branch_p (const struct mips_cl_insn *ip)
3924 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3925 | INSN_COND_BRANCH_DELAY
3926 | INSN_COND_BRANCH_LIKELY)) != 0;
3929 /* Return true if IP is a compact branch or jump. */
3931 static inline bfd_boolean
3932 compact_branch_p (const struct mips_cl_insn *ip)
3934 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3935 | INSN2_COND_BRANCH)) != 0;
3938 /* Return true if IP is an unconditional branch or jump. */
3940 static inline bfd_boolean
3941 uncond_branch_p (const struct mips_cl_insn *ip)
3943 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3944 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
3947 /* Return true if IP is a branch-likely instruction. */
3949 static inline bfd_boolean
3950 branch_likely_p (const struct mips_cl_insn *ip)
3952 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3955 /* Return the type of nop that should be used to fill the delay slot
3956 of delayed branch IP. */
3958 static struct mips_cl_insn *
3959 get_delay_slot_nop (const struct mips_cl_insn *ip)
3961 if (mips_opts.micromips
3962 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3963 return µmips_nop32_insn;
3967 /* Return a mask that has bit N set if OPCODE reads the register(s)
3971 insn_read_mask (const struct mips_opcode *opcode)
3973 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
3976 /* Return a mask that has bit N set if OPCODE writes to the register(s)
3980 insn_write_mask (const struct mips_opcode *opcode)
3982 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
3985 /* Return a mask of the registers specified by operand OPERAND of INSN.
3986 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
3990 operand_reg_mask (const struct mips_cl_insn *insn,
3991 const struct mips_operand *operand,
3992 unsigned int type_mask)
3994 unsigned int uval, vsel;
3996 switch (operand->type)
4003 case OP_ADDIUSP_INT:
4004 case OP_ENTRY_EXIT_LIST:
4005 case OP_REPEAT_DEST_REG:
4006 case OP_REPEAT_PREV_REG:
4009 case OP_VU0_MATCH_SUFFIX:
4013 case OP_OPTIONAL_REG:
4015 const struct mips_reg_operand *reg_op;
4017 reg_op = (const struct mips_reg_operand *) operand;
4018 if (!(type_mask & (1 << reg_op->reg_type)))
4020 uval = insn_extract_operand (insn, operand);
4021 return 1 << mips_decode_reg_operand (reg_op, uval);
4026 const struct mips_reg_pair_operand *pair_op;
4028 pair_op = (const struct mips_reg_pair_operand *) operand;
4029 if (!(type_mask & (1 << pair_op->reg_type)))
4031 uval = insn_extract_operand (insn, operand);
4032 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]);
4035 case OP_CLO_CLZ_DEST:
4036 if (!(type_mask & (1 << OP_REG_GP)))
4038 uval = insn_extract_operand (insn, operand);
4039 return (1 << (uval & 31)) | (1 << (uval >> 5));
4041 case OP_LWM_SWM_LIST:
4044 case OP_SAVE_RESTORE_LIST:
4047 case OP_MDMX_IMM_REG:
4048 if (!(type_mask & (1 << OP_REG_VEC)))
4050 uval = insn_extract_operand (insn, operand);
4052 if ((vsel & 0x18) == 0x18)
4054 return 1 << (uval & 31);
4059 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4060 where bit N of OPNO_MASK is set if operand N should be included.
4061 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4065 insn_reg_mask (const struct mips_cl_insn *insn,
4066 unsigned int type_mask, unsigned int opno_mask)
4068 unsigned int opno, reg_mask;
4072 while (opno_mask != 0)
4075 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4082 /* Return the mask of core registers that IP reads. */
4085 gpr_read_mask (const struct mips_cl_insn *ip)
4087 unsigned long pinfo, pinfo2;
4090 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4091 pinfo = ip->insn_mo->pinfo;
4092 pinfo2 = ip->insn_mo->pinfo2;
4093 if (pinfo & INSN_UDI)
4095 /* UDI instructions have traditionally been assumed to read RS
4097 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4098 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4100 if (pinfo & INSN_READ_GPR_24)
4102 if (pinfo2 & INSN2_READ_GPR_16)
4104 if (pinfo2 & INSN2_READ_SP)
4106 if (pinfo2 & INSN2_READ_GPR_31)
4108 /* Don't include register 0. */
4112 /* Return the mask of core registers that IP writes. */
4115 gpr_write_mask (const struct mips_cl_insn *ip)
4117 unsigned long pinfo, pinfo2;
4120 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4121 pinfo = ip->insn_mo->pinfo;
4122 pinfo2 = ip->insn_mo->pinfo2;
4123 if (pinfo & INSN_WRITE_GPR_24)
4125 if (pinfo & INSN_WRITE_GPR_31)
4127 if (pinfo & INSN_UDI)
4128 /* UDI instructions have traditionally been assumed to write to RD. */
4129 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4130 if (pinfo2 & INSN2_WRITE_SP)
4132 /* Don't include register 0. */
4136 /* Return the mask of floating-point registers that IP reads. */
4139 fpr_read_mask (const struct mips_cl_insn *ip)
4141 unsigned long pinfo;
4144 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4145 insn_read_mask (ip->insn_mo));
4146 pinfo = ip->insn_mo->pinfo;
4147 /* Conservatively treat all operands to an FP_D instruction are doubles.
4148 (This is overly pessimistic for things like cvt.d.s.) */
4149 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4154 /* Return the mask of floating-point registers that IP writes. */
4157 fpr_write_mask (const struct mips_cl_insn *ip)
4159 unsigned long pinfo;
4162 mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
4163 insn_write_mask (ip->insn_mo));
4164 pinfo = ip->insn_mo->pinfo;
4165 /* Conservatively treat all operands to an FP_D instruction are doubles.
4166 (This is overly pessimistic for things like cvt.s.d.) */
4167 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
4172 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4173 Check whether that is allowed. */
4176 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4178 const char *s = insn->name;
4180 if (insn->pinfo == INSN_MACRO)
4181 /* Let a macro pass, we'll catch it later when it is expanded. */
4184 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900)
4186 /* Allow odd registers for single-precision ops. */
4187 switch (insn->pinfo & (FP_S | FP_D))
4198 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4199 s = strchr (insn->name, '.');
4200 if (s != NULL && opnum == 2)
4201 s = strchr (s + 1, '.');
4202 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
4205 /* Single-precision coprocessor loads and moves are OK too. */
4206 if ((insn->pinfo & FP_S)
4207 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
4208 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
4214 /* Report that user-supplied argument ARGNUM for INSN was VAL, but should
4215 have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether
4216 this operand is normally printed in hex or decimal. */
4219 report_bad_range (struct mips_cl_insn *insn, int argnum,
4220 offsetT val, int min_val, int max_val,
4221 bfd_boolean print_hex)
4223 if (print_hex && val >= 0)
4224 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4226 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4228 as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x],"
4230 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4232 as_bad (_("Operand %d of `%s' must be in the range [%d, %d],"
4234 argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val);
4237 /* Report an invalid combination of position and size operands for a bitfield
4238 operation. POS and SIZE are the values that were given. */
4241 report_bad_field (offsetT pos, offsetT size)
4243 as_bad (_("Invalid field specification (position %ld, size %ld)"),
4244 (unsigned long) pos, (unsigned long) size);
4247 /* Information about an instruction argument that we're trying to match. */
4248 struct mips_arg_info
4250 /* The instruction so far. */
4251 struct mips_cl_insn *insn;
4253 /* The first unconsumed operand token. */
4254 struct mips_operand_token *token;
4256 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4259 /* The 1-based argument number, for error reporting. This does not
4260 count elided optional registers, etc.. */
4263 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4264 unsigned int last_regno;
4266 /* If the first operand was an OP_REG, this is the register that it
4267 specified, otherwise it is ILLEGAL_REG. */
4268 unsigned int dest_regno;
4270 /* The value of the last OP_INT operand. Only used for OP_MSB,
4271 where it gives the lsb position. */
4272 unsigned int last_op_int;
4274 /* If true, the OP_INT match routine should treat plain symbolic operands
4275 as if a relocation operator like %lo(...) had been used. This is only
4276 ever true if the operand can be relocated. */
4277 bfd_boolean allow_nonconst;
4279 /* When true, the OP_INT match routine should allow unsigned N-bit
4280 arguments to be used where a signed N-bit operand is expected. */
4281 bfd_boolean lax_max;
4283 /* True if a reference to the current AT register was seen. */
4284 bfd_boolean seen_at;
4287 /* Record that the argument is out of range. */
4290 match_out_of_range (struct mips_arg_info *arg)
4292 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4295 /* Record that the argument isn't constant but needs to be. */
4298 match_not_constant (struct mips_arg_info *arg)
4300 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4304 /* Try to match an OT_CHAR token for character CH. Consume the token
4305 and return true on success, otherwise return false. */
4308 match_char (struct mips_arg_info *arg, char ch)
4310 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4320 /* Try to get an expression from the next tokens in ARG. Consume the
4321 tokens and return true on success, storing the expression value in
4322 VALUE and relocation types in R. */
4325 match_expression (struct mips_arg_info *arg, expressionS *value,
4326 bfd_reloc_code_real_type *r)
4328 /* If the next token is a '(' that was parsed as being part of a base
4329 expression, assume we have an elided offset. The later match will fail
4330 if this turns out to be wrong. */
4331 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4333 value->X_op = O_constant;
4334 value->X_add_number = 0;
4335 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4339 /* Reject register-based expressions such as "0+$2" and "(($2))".
4340 For plain registers the default error seems more appropriate. */
4341 if (arg->token->type == OT_INTEGER
4342 && arg->token->u.integer.value.X_op == O_register)
4344 set_insn_error (arg->argnum, _("register value used as expression"));
4348 if (arg->token->type == OT_INTEGER)
4350 *value = arg->token->u.integer.value;
4351 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4357 (arg->argnum, _("operand %d must be an immediate expression"),
4362 /* Try to get a constant expression from the next tokens in ARG. Consume
4363 the tokens and return return true on success, storing the constant value
4364 in *VALUE. Use FALLBACK as the value if the match succeeded with an
4368 match_const_int (struct mips_arg_info *arg, offsetT *value)
4371 bfd_reloc_code_real_type r[3];
4373 if (!match_expression (arg, &ex, r))
4376 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
4377 *value = ex.X_add_number;
4380 match_not_constant (arg);
4386 /* Return the RTYPE_* flags for a register operand of type TYPE that
4387 appears in instruction OPCODE. */
4390 convert_reg_type (const struct mips_opcode *opcode,
4391 enum mips_reg_operand_type type)
4396 return RTYPE_NUM | RTYPE_GP;
4399 /* Allow vector register names for MDMX if the instruction is a 64-bit
4400 FPR load, store or move (including moves to and from GPRs). */
4401 if ((mips_opts.ase & ASE_MDMX)
4402 && (opcode->pinfo & FP_D)
4403 && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
4404 | INSN_COPROC_MEMORY_DELAY
4405 | INSN_LOAD_COPROC_DELAY
4406 | INSN_LOAD_MEMORY_DELAY
4407 | INSN_STORE_MEMORY)))
4408 return RTYPE_FPU | RTYPE_VEC;
4412 if (opcode->pinfo & (FP_D | FP_S))
4413 return RTYPE_CCC | RTYPE_FCC;
4417 if (opcode->membership & INSN_5400)
4419 return RTYPE_FPU | RTYPE_VEC;
4425 if (opcode->name[strlen (opcode->name) - 1] == '0')
4426 return RTYPE_NUM | RTYPE_CP0;
4433 return RTYPE_NUM | RTYPE_VI;
4436 return RTYPE_NUM | RTYPE_VF;
4438 case OP_REG_R5900_I:
4439 return RTYPE_R5900_I;
4441 case OP_REG_R5900_Q:
4442 return RTYPE_R5900_Q;
4444 case OP_REG_R5900_R:
4445 return RTYPE_R5900_R;
4447 case OP_REG_R5900_ACC:
4448 return RTYPE_R5900_ACC;
4453 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
4456 check_regno (struct mips_arg_info *arg,
4457 enum mips_reg_operand_type type, unsigned int regno)
4459 if (AT && type == OP_REG_GP && regno == AT)
4460 arg->seen_at = TRUE;
4462 if (type == OP_REG_FP
4465 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
4466 as_warn (_("Float register should be even, was %d"), regno);
4468 if (type == OP_REG_CCC)
4473 name = arg->insn->insn_mo->name;
4474 length = strlen (name);
4475 if ((regno & 1) != 0
4476 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
4477 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
4478 as_warn (_("Condition code register should be even for %s, was %d"),
4481 if ((regno & 3) != 0
4482 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
4483 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
4488 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
4489 a register of type TYPE. Return true on success, storing the register
4490 number in *REGNO and warning about any dubious uses. */
4493 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4494 unsigned int symval, unsigned int *regno)
4496 if (type == OP_REG_VEC)
4497 symval = mips_prefer_vec_regno (symval);
4498 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
4501 *regno = symval & RNUM_MASK;
4502 check_regno (arg, type, *regno);
4506 /* Try to interpret the next token in ARG as a register of type TYPE.
4507 Consume the token and return true on success, storing the register
4508 number in *REGNO. Return false on failure. */
4511 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4512 unsigned int *regno)
4514 if (arg->token->type == OT_REG
4515 && match_regno (arg, type, arg->token->u.regno, regno))
4523 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
4524 Consume the token and return true on success, storing the register numbers
4525 in *REGNO1 and *REGNO2. Return false on failure. */
4528 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
4529 unsigned int *regno1, unsigned int *regno2)
4531 if (match_reg (arg, type, regno1))
4536 if (arg->token->type == OT_REG_RANGE
4537 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
4538 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
4539 && *regno1 <= *regno2)
4547 /* OP_INT matcher. */
4550 match_int_operand (struct mips_arg_info *arg,
4551 const struct mips_operand *operand_base)
4553 const struct mips_int_operand *operand;
4555 int min_val, max_val, factor;
4558 operand = (const struct mips_int_operand *) operand_base;
4559 factor = 1 << operand->shift;
4560 min_val = mips_int_operand_min (operand);
4561 max_val = mips_int_operand_max (operand);
4563 max_val = ((1 << operand_base->size) - 1) << operand->shift;
4565 if (operand_base->lsb == 0
4566 && operand_base->size == 16
4567 && operand->shift == 0
4568 && operand->bias == 0
4569 && (operand->max_val == 32767 || operand->max_val == 65535))
4571 /* The operand can be relocated. */
4572 if (!match_expression (arg, &offset_expr, offset_reloc))
4575 if (offset_reloc[0] != BFD_RELOC_UNUSED)
4576 /* Relocation operators were used. Accept the arguent and
4577 leave the relocation value in offset_expr and offset_relocs
4578 for the caller to process. */
4581 if (offset_expr.X_op != O_constant)
4583 /* If non-constant operands are allowed then leave them for
4584 the caller to process, otherwise fail the match. */
4585 if (!arg->allow_nonconst)
4587 match_not_constant (arg);
4590 offset_reloc[0] = BFD_RELOC_LO16;
4594 /* Clear the global state; we're going to install the operand
4596 sval = offset_expr.X_add_number;
4597 offset_expr.X_op = O_absent;
4601 if (!match_const_int (arg, &sval))
4605 arg->last_op_int = sval;
4607 if (sval < min_val || sval > max_val || sval % factor)
4609 match_out_of_range (arg);
4613 uval = (unsigned int) sval >> operand->shift;
4614 uval -= operand->bias;
4616 /* Handle -mfix-cn63xxp1. */
4618 && mips_fix_cn63xxp1
4619 && !mips_opts.micromips
4620 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
4635 /* The rest must be changed to 28. */
4640 insn_insert_operand (arg->insn, operand_base, uval);
4644 /* OP_MAPPED_INT matcher. */
4647 match_mapped_int_operand (struct mips_arg_info *arg,
4648 const struct mips_operand *operand_base)
4650 const struct mips_mapped_int_operand *operand;
4651 unsigned int uval, num_vals;
4654 operand = (const struct mips_mapped_int_operand *) operand_base;
4655 if (!match_const_int (arg, &sval))
4658 num_vals = 1 << operand_base->size;
4659 for (uval = 0; uval < num_vals; uval++)
4660 if (operand->int_map[uval] == sval)
4662 if (uval == num_vals)
4664 match_out_of_range (arg);
4668 insn_insert_operand (arg->insn, operand_base, uval);
4672 /* OP_MSB matcher. */
4675 match_msb_operand (struct mips_arg_info *arg,
4676 const struct mips_operand *operand_base)
4678 const struct mips_msb_operand *operand;
4679 int min_val, max_val, max_high;
4680 offsetT size, sval, high;
4682 operand = (const struct mips_msb_operand *) operand_base;
4683 min_val = operand->bias;
4684 max_val = min_val + (1 << operand_base->size) - 1;
4685 max_high = operand->opsize;
4687 if (!match_const_int (arg, &size))
4690 high = size + arg->last_op_int;
4691 sval = operand->add_lsb ? high : size;
4693 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
4695 match_out_of_range (arg);
4698 insn_insert_operand (arg->insn, operand_base, sval - min_val);
4702 /* OP_REG matcher. */
4705 match_reg_operand (struct mips_arg_info *arg,
4706 const struct mips_operand *operand_base)
4708 const struct mips_reg_operand *operand;
4709 unsigned int regno, uval, num_vals;
4711 operand = (const struct mips_reg_operand *) operand_base;
4712 if (!match_reg (arg, operand->reg_type, ®no))
4715 if (operand->reg_map)
4717 num_vals = 1 << operand->root.size;
4718 for (uval = 0; uval < num_vals; uval++)
4719 if (operand->reg_map[uval] == regno)
4721 if (num_vals == uval)
4727 arg->last_regno = regno;
4728 if (arg->opnum == 1)
4729 arg->dest_regno = regno;
4730 insn_insert_operand (arg->insn, operand_base, uval);
4734 /* OP_REG_PAIR matcher. */
4737 match_reg_pair_operand (struct mips_arg_info *arg,
4738 const struct mips_operand *operand_base)
4740 const struct mips_reg_pair_operand *operand;
4741 unsigned int regno1, regno2, uval, num_vals;
4743 operand = (const struct mips_reg_pair_operand *) operand_base;
4744 if (!match_reg (arg, operand->reg_type, ®no1)
4745 || !match_char (arg, ',')
4746 || !match_reg (arg, operand->reg_type, ®no2))
4749 num_vals = 1 << operand_base->size;
4750 for (uval = 0; uval < num_vals; uval++)
4751 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
4753 if (uval == num_vals)
4756 insn_insert_operand (arg->insn, operand_base, uval);
4760 /* OP_PCREL matcher. The caller chooses the relocation type. */
4763 match_pcrel_operand (struct mips_arg_info *arg)
4765 bfd_reloc_code_real_type r[3];
4767 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
4770 /* OP_PERF_REG matcher. */
4773 match_perf_reg_operand (struct mips_arg_info *arg,
4774 const struct mips_operand *operand)
4778 if (!match_const_int (arg, &sval))
4783 || (mips_opts.arch == CPU_R5900
4784 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
4785 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
4787 set_insn_error (arg->argnum, _("invalid performance register"));
4791 insn_insert_operand (arg->insn, operand, sval);
4795 /* OP_ADDIUSP matcher. */
4798 match_addiusp_operand (struct mips_arg_info *arg,
4799 const struct mips_operand *operand)
4804 if (!match_const_int (arg, &sval))
4809 match_out_of_range (arg);
4814 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
4816 match_out_of_range (arg);
4820 uval = (unsigned int) sval;
4821 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
4822 insn_insert_operand (arg->insn, operand, uval);
4826 /* OP_CLO_CLZ_DEST matcher. */
4829 match_clo_clz_dest_operand (struct mips_arg_info *arg,
4830 const struct mips_operand *operand)
4834 if (!match_reg (arg, OP_REG_GP, ®no))
4837 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
4841 /* OP_LWM_SWM_LIST matcher. */
4844 match_lwm_swm_list_operand (struct mips_arg_info *arg,
4845 const struct mips_operand *operand)
4847 unsigned int reglist, sregs, ra, regno1, regno2;
4848 struct mips_arg_info reset;
4851 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4855 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
4860 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
4863 while (match_char (arg, ',')
4864 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
4867 if (operand->size == 2)
4869 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
4875 and any permutations of these. */
4876 if ((reglist & 0xfff1ffff) != 0x80010000)
4879 sregs = (reglist >> 17) & 7;
4884 /* The list must include at least one of ra and s0-sN,
4885 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
4886 which are $23 and $30 respectively.) E.g.:
4894 and any permutations of these. */
4895 if ((reglist & 0x3f00ffff) != 0)
4898 ra = (reglist >> 27) & 0x10;
4899 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
4902 if ((sregs & -sregs) != sregs)
4905 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
4909 /* OP_ENTRY_EXIT_LIST matcher. */
4912 match_entry_exit_operand (struct mips_arg_info *arg,
4913 const struct mips_operand *operand)
4916 bfd_boolean is_exit;
4918 /* The format is the same for both ENTRY and EXIT, but the constraints
4920 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
4921 mask = (is_exit ? 7 << 3 : 0);
4924 unsigned int regno1, regno2;
4925 bfd_boolean is_freg;
4927 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4929 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
4934 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
4937 mask |= (5 + regno2) << 3;
4939 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
4940 mask |= (regno2 - 3) << 3;
4941 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
4942 mask |= (regno2 - 15) << 1;
4943 else if (regno1 == RA && regno2 == RA)
4948 while (match_char (arg, ','));
4950 insn_insert_operand (arg->insn, operand, mask);
4954 /* OP_SAVE_RESTORE_LIST matcher. */
4957 match_save_restore_list_operand (struct mips_arg_info *arg)
4959 unsigned int opcode, args, statics, sregs;
4960 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
4963 opcode = arg->insn->insn_opcode;
4965 num_frame_sizes = 0;
4971 unsigned int regno1, regno2;
4973 if (arg->token->type == OT_INTEGER)
4975 /* Handle the frame size. */
4976 if (!match_const_int (arg, &frame_size))
4978 num_frame_sizes += 1;
4982 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
4985 while (regno1 <= regno2)
4987 if (regno1 >= 4 && regno1 <= 7)
4989 if (num_frame_sizes == 0)
4991 args |= 1 << (regno1 - 4);
4993 /* statics $a0-$a3 */
4994 statics |= 1 << (regno1 - 4);
4996 else if (regno1 >= 16 && regno1 <= 23)
4998 sregs |= 1 << (regno1 - 16);
4999 else if (regno1 == 30)
5002 else if (regno1 == 31)
5003 /* Add $ra to insn. */
5013 while (match_char (arg, ','));
5015 /* Encode args/statics combination. */
5018 else if (args == 0xf)
5019 /* All $a0-$a3 are args. */
5020 opcode |= MIPS16_ALL_ARGS << 16;
5021 else if (statics == 0xf)
5022 /* All $a0-$a3 are statics. */
5023 opcode |= MIPS16_ALL_STATICS << 16;
5026 /* Count arg registers. */
5036 /* Count static registers. */
5038 while (statics & 0x8)
5040 statics = (statics << 1) & 0xf;
5046 /* Encode args/statics. */
5047 opcode |= ((num_args << 2) | num_statics) << 16;
5050 /* Encode $s0/$s1. */
5051 if (sregs & (1 << 0)) /* $s0 */
5053 if (sregs & (1 << 1)) /* $s1 */
5057 /* Encode $s2-$s8. */
5066 opcode |= num_sregs << 24;
5068 /* Encode frame size. */
5069 if (num_frame_sizes == 0)
5071 set_insn_error (arg->argnum, _("missing frame size"));
5074 if (num_frame_sizes > 1)
5076 set_insn_error (arg->argnum, _("frame size specified twice"));
5079 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5081 set_insn_error (arg->argnum, _("invalid frame size"));
5084 if (frame_size != 128 || (opcode >> 16) != 0)
5087 opcode |= (((frame_size & 0xf0) << 16)
5088 | (frame_size & 0x0f));
5091 /* Finally build the instruction. */
5092 if ((opcode >> 16) != 0 || frame_size == 0)
5093 opcode |= MIPS16_EXTEND;
5094 arg->insn->insn_opcode = opcode;
5098 /* OP_MDMX_IMM_REG matcher. */
5101 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5102 const struct mips_operand *operand)
5104 unsigned int regno, uval;
5106 const struct mips_opcode *opcode;
5108 /* The mips_opcode records whether this is an octobyte or quadhalf
5109 instruction. Start out with that bit in place. */
5110 opcode = arg->insn->insn_mo;
5111 uval = mips_extract_operand (operand, opcode->match);
5112 is_qh = (uval != 0);
5114 if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT)
5116 if ((opcode->membership & INSN_5400)
5117 && strcmp (opcode->name, "rzu.ob") == 0)
5119 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5124 /* Check whether this is a vector register or a broadcast of
5125 a single element. */
5126 if (arg->token->type == OT_REG_ELEMENT)
5128 if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno,
5131 if (arg->token->u.reg_element.index > (is_qh ? 3 : 7))
5133 set_insn_error (arg->argnum, _("invalid element selector"));
5137 uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5;
5141 /* A full vector. */
5142 if ((opcode->membership & INSN_5400)
5143 && (strcmp (opcode->name, "sll.ob") == 0
5144 || strcmp (opcode->name, "srl.ob") == 0))
5146 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5151 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5154 uval |= MDMX_FMTSEL_VEC_QH << 5;
5156 uval |= MDMX_FMTSEL_VEC_OB << 5;
5165 if (!match_const_int (arg, &sval))
5167 if (sval < 0 || sval > 31)
5169 match_out_of_range (arg);
5172 uval |= (sval & 31);
5174 uval |= MDMX_FMTSEL_IMM_QH << 5;
5176 uval |= MDMX_FMTSEL_IMM_OB << 5;
5178 insn_insert_operand (arg->insn, operand, uval);
5182 /* OP_PC matcher. */
5185 match_pc_operand (struct mips_arg_info *arg)
5187 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
5195 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
5196 register that we need to match. */
5199 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
5203 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
5206 /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is
5207 the length of the value in bytes (4 for float, 8 for double) and
5208 USING_GPRS says whether the destination is a GPR rather than an FPR.
5210 Return the constant in IMM and OFFSET as follows:
5212 - If the constant should be loaded via memory, set IMM to O_absent and
5213 OFFSET to the memory address.
5215 - Otherwise, if the constant should be loaded into two 32-bit registers,
5216 set IMM to the O_constant to load into the high register and OFFSET
5217 to the corresponding value for the low register.
5219 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
5221 These constants only appear as the last operand in an instruction,
5222 and every instruction that accepts them in any variant accepts them
5223 in all variants. This means we don't have to worry about backing out
5224 any changes if the instruction does not match. We just match
5225 unconditionally and report an error if the constant is invalid. */
5228 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
5229 expressionS *offset, int length, bfd_boolean using_gprs)
5234 const char *newname;
5235 unsigned char *data;
5237 /* Where the constant is placed is based on how the MIPS assembler
5240 length == 4 && using_gprs -- immediate value only
5241 length == 8 && using_gprs -- .rdata or immediate value
5242 length == 4 && !using_gprs -- .lit4 or immediate value
5243 length == 8 && !using_gprs -- .lit8 or immediate value
5245 The .lit4 and .lit8 sections are only used if permitted by the
5247 if (arg->token->type != OT_FLOAT)
5249 set_insn_error (arg->argnum, _("floating-point expression required"));
5253 gas_assert (arg->token->u.flt.length == length);
5254 data = arg->token->u.flt.data;
5257 /* Handle 32-bit constants for which an immediate value is best. */
5260 || g_switch_value < 4
5261 || (data[0] == 0 && data[1] == 0)
5262 || (data[2] == 0 && data[3] == 0)))
5264 imm->X_op = O_constant;
5265 if (!target_big_endian)
5266 imm->X_add_number = bfd_getl32 (data);
5268 imm->X_add_number = bfd_getb32 (data);
5269 offset->X_op = O_absent;
5273 /* Handle 64-bit constants for which an immediate value is best. */
5275 && !mips_disable_float_construction
5276 /* Constants can only be constructed in GPRs and copied
5277 to FPRs if the GPRs are at least as wide as the FPRs.
5278 Force the constant into memory if we are using 64-bit FPRs
5279 but the GPRs are only 32 bits wide. */
5280 /* ??? No longer true with the addition of MTHC1, but this
5281 is legacy code... */
5282 && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
5283 && ((data[0] == 0 && data[1] == 0)
5284 || (data[2] == 0 && data[3] == 0))
5285 && ((data[4] == 0 && data[5] == 0)
5286 || (data[6] == 0 && data[7] == 0)))
5288 /* The value is simple enough to load with a couple of instructions.
5289 If using 32-bit registers, set IMM to the high order 32 bits and
5290 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
5292 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
5294 imm->X_op = O_constant;
5295 offset->X_op = O_constant;
5296 if (!target_big_endian)
5298 imm->X_add_number = bfd_getl32 (data + 4);
5299 offset->X_add_number = bfd_getl32 (data);
5303 imm->X_add_number = bfd_getb32 (data);
5304 offset->X_add_number = bfd_getb32 (data + 4);
5306 if (offset->X_add_number == 0)
5307 offset->X_op = O_absent;
5311 imm->X_op = O_constant;
5312 if (!target_big_endian)
5313 imm->X_add_number = bfd_getl64 (data);
5315 imm->X_add_number = bfd_getb64 (data);
5316 offset->X_op = O_absent;
5321 /* Switch to the right section. */
5323 subseg = now_subseg;
5326 gas_assert (!using_gprs && g_switch_value >= 4);
5331 if (using_gprs || g_switch_value < 8)
5332 newname = RDATA_SECTION_NAME;
5337 new_seg = subseg_new (newname, (subsegT) 0);
5338 bfd_set_section_flags (stdoutput, new_seg,
5339 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
5340 frag_align (length == 4 ? 2 : 3, 0, 0);
5341 if (strncmp (TARGET_OS, "elf", 3) != 0)
5342 record_alignment (new_seg, 4);
5344 record_alignment (new_seg, length == 4 ? 2 : 3);
5346 as_bad (_("Can't use floating point insn in this section"));
5348 /* Set the argument to the current address in the section. */
5349 imm->X_op = O_absent;
5350 offset->X_op = O_symbol;
5351 offset->X_add_symbol = symbol_temp_new_now ();
5352 offset->X_add_number = 0;
5354 /* Put the floating point number into the section. */
5355 p = frag_more (length);
5356 memcpy (p, data, length);
5358 /* Switch back to the original section. */
5359 subseg_set (seg, subseg);
5363 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
5367 match_vu0_suffix_operand (struct mips_arg_info *arg,
5368 const struct mips_operand *operand,
5369 bfd_boolean match_p)
5373 /* The operand can be an XYZW mask or a single 2-bit channel index
5374 (with X being 0). */
5375 gas_assert (operand->size == 2 || operand->size == 4);
5377 /* The suffix can be omitted when it is already part of the opcode. */
5378 if (arg->token->type != OT_CHANNELS)
5381 uval = arg->token->u.channels;
5382 if (operand->size == 2)
5384 /* Check that a single bit is set and convert it into a 2-bit index. */
5385 if ((uval & -uval) != uval)
5387 uval = 4 - ffs (uval);
5390 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
5395 insn_insert_operand (arg->insn, operand, uval);
5399 /* S is the text seen for ARG. Match it against OPERAND. Return the end
5400 of the argument text if the match is successful, otherwise return null. */
5403 match_operand (struct mips_arg_info *arg,
5404 const struct mips_operand *operand)
5406 switch (operand->type)
5409 return match_int_operand (arg, operand);
5412 return match_mapped_int_operand (arg, operand);
5415 return match_msb_operand (arg, operand);
5418 case OP_OPTIONAL_REG:
5419 return match_reg_operand (arg, operand);
5422 return match_reg_pair_operand (arg, operand);
5425 return match_pcrel_operand (arg);
5428 return match_perf_reg_operand (arg, operand);
5430 case OP_ADDIUSP_INT:
5431 return match_addiusp_operand (arg, operand);
5433 case OP_CLO_CLZ_DEST:
5434 return match_clo_clz_dest_operand (arg, operand);
5436 case OP_LWM_SWM_LIST:
5437 return match_lwm_swm_list_operand (arg, operand);
5439 case OP_ENTRY_EXIT_LIST:
5440 return match_entry_exit_operand (arg, operand);
5442 case OP_SAVE_RESTORE_LIST:
5443 return match_save_restore_list_operand (arg);
5445 case OP_MDMX_IMM_REG:
5446 return match_mdmx_imm_reg_operand (arg, operand);
5448 case OP_REPEAT_DEST_REG:
5449 return match_tied_reg_operand (arg, arg->dest_regno);
5451 case OP_REPEAT_PREV_REG:
5452 return match_tied_reg_operand (arg, arg->last_regno);
5455 return match_pc_operand (arg);
5458 return match_vu0_suffix_operand (arg, operand, FALSE);
5460 case OP_VU0_MATCH_SUFFIX:
5461 return match_vu0_suffix_operand (arg, operand, TRUE);
5466 /* ARG is the state after successfully matching an instruction.
5467 Issue any queued-up warnings. */
5470 check_completed_insn (struct mips_arg_info *arg)
5475 as_warn (_("Used $at without \".set noat\""));
5477 as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
5481 /* Return true if modifying general-purpose register REG needs a delay. */
5484 reg_needs_delay (unsigned int reg)
5486 unsigned long prev_pinfo;
5488 prev_pinfo = history[0].insn_mo->pinfo;
5489 if (!mips_opts.noreorder
5490 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
5491 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
5492 && (gpr_write_mask (&history[0]) & (1 << reg)))
5498 /* Classify an instruction according to the FIX_VR4120_* enumeration.
5499 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
5500 by VR4120 errata. */
5503 classify_vr4120_insn (const char *name)
5505 if (strncmp (name, "macc", 4) == 0)
5506 return FIX_VR4120_MACC;
5507 if (strncmp (name, "dmacc", 5) == 0)
5508 return FIX_VR4120_DMACC;
5509 if (strncmp (name, "mult", 4) == 0)
5510 return FIX_VR4120_MULT;
5511 if (strncmp (name, "dmult", 5) == 0)
5512 return FIX_VR4120_DMULT;
5513 if (strstr (name, "div"))
5514 return FIX_VR4120_DIV;
5515 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
5516 return FIX_VR4120_MTHILO;
5517 return NUM_FIX_VR4120_CLASSES;
5520 #define INSN_ERET 0x42000018
5521 #define INSN_DERET 0x4200001f
5523 /* Return the number of instructions that must separate INSN1 and INSN2,
5524 where INSN1 is the earlier instruction. Return the worst-case value
5525 for any INSN2 if INSN2 is null. */
5528 insns_between (const struct mips_cl_insn *insn1,
5529 const struct mips_cl_insn *insn2)
5531 unsigned long pinfo1, pinfo2;
5534 /* If INFO2 is null, pessimistically assume that all flags are set for
5535 the second instruction. */
5536 pinfo1 = insn1->insn_mo->pinfo;
5537 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
5539 /* For most targets, write-after-read dependencies on the HI and LO
5540 registers must be separated by at least two instructions. */
5541 if (!hilo_interlocks)
5543 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
5545 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
5549 /* If we're working around r7000 errata, there must be two instructions
5550 between an mfhi or mflo and any instruction that uses the result. */
5551 if (mips_7000_hilo_fix
5552 && !mips_opts.micromips
5553 && MF_HILO_INSN (pinfo1)
5554 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
5557 /* If we're working around 24K errata, one instruction is required
5558 if an ERET or DERET is followed by a branch instruction. */
5559 if (mips_fix_24k && !mips_opts.micromips)
5561 if (insn1->insn_opcode == INSN_ERET
5562 || insn1->insn_opcode == INSN_DERET)
5565 || insn2->insn_opcode == INSN_ERET
5566 || insn2->insn_opcode == INSN_DERET
5567 || delayed_branch_p (insn2))
5572 /* If working around VR4120 errata, check for combinations that need
5573 a single intervening instruction. */
5574 if (mips_fix_vr4120 && !mips_opts.micromips)
5576 unsigned int class1, class2;
5578 class1 = classify_vr4120_insn (insn1->insn_mo->name);
5579 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
5583 class2 = classify_vr4120_insn (insn2->insn_mo->name);
5584 if (vr4120_conflicts[class1] & (1 << class2))
5589 if (!HAVE_CODE_COMPRESSION)
5591 /* Check for GPR or coprocessor load delays. All such delays
5592 are on the RT register. */
5593 /* Itbl support may require additional care here. */
5594 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
5595 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
5597 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
5601 /* Check for generic coprocessor hazards.
5603 This case is not handled very well. There is no special
5604 knowledge of CP0 handling, and the coprocessors other than
5605 the floating point unit are not distinguished at all. */
5606 /* Itbl support may require additional care here. FIXME!
5607 Need to modify this to include knowledge about
5608 user specified delays! */
5609 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
5610 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
5612 /* Handle cases where INSN1 writes to a known general coprocessor
5613 register. There must be a one instruction delay before INSN2
5614 if INSN2 reads that register, otherwise no delay is needed. */
5615 mask = fpr_write_mask (insn1);
5618 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
5623 /* Read-after-write dependencies on the control registers
5624 require a two-instruction gap. */
5625 if ((pinfo1 & INSN_WRITE_COND_CODE)
5626 && (pinfo2 & INSN_READ_COND_CODE))
5629 /* We don't know exactly what INSN1 does. If INSN2 is
5630 also a coprocessor instruction, assume there must be
5631 a one instruction gap. */
5632 if (pinfo2 & INSN_COP)
5637 /* Check for read-after-write dependencies on the coprocessor
5638 control registers in cases where INSN1 does not need a general
5639 coprocessor delay. This means that INSN1 is a floating point
5640 comparison instruction. */
5641 /* Itbl support may require additional care here. */
5642 else if (!cop_interlocks
5643 && (pinfo1 & INSN_WRITE_COND_CODE)
5644 && (pinfo2 & INSN_READ_COND_CODE))
5651 /* Return the number of nops that would be needed to work around the
5652 VR4130 mflo/mfhi errata if instruction INSN immediately followed
5653 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
5654 that are contained within the first IGNORE instructions of HIST. */
5657 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
5658 const struct mips_cl_insn *insn)
5663 /* Check if the instruction writes to HI or LO. MTHI and MTLO
5664 are not affected by the errata. */
5666 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
5667 || strcmp (insn->insn_mo->name, "mtlo") == 0
5668 || strcmp (insn->insn_mo->name, "mthi") == 0))
5671 /* Search for the first MFLO or MFHI. */
5672 for (i = 0; i < MAX_VR4130_NOPS; i++)
5673 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
5675 /* Extract the destination register. */
5676 mask = gpr_write_mask (&hist[i]);
5678 /* No nops are needed if INSN reads that register. */
5679 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
5682 /* ...or if any of the intervening instructions do. */
5683 for (j = 0; j < i; j++)
5684 if (gpr_read_mask (&hist[j]) & mask)
5688 return MAX_VR4130_NOPS - i;
5693 #define BASE_REG_EQ(INSN1, INSN2) \
5694 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
5695 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
5697 /* Return the minimum alignment for this store instruction. */
5700 fix_24k_align_to (const struct mips_opcode *mo)
5702 if (strcmp (mo->name, "sh") == 0)
5705 if (strcmp (mo->name, "swc1") == 0
5706 || strcmp (mo->name, "swc2") == 0
5707 || strcmp (mo->name, "sw") == 0
5708 || strcmp (mo->name, "sc") == 0
5709 || strcmp (mo->name, "s.s") == 0)
5712 if (strcmp (mo->name, "sdc1") == 0
5713 || strcmp (mo->name, "sdc2") == 0
5714 || strcmp (mo->name, "s.d") == 0)
5721 struct fix_24k_store_info
5723 /* Immediate offset, if any, for this store instruction. */
5725 /* Alignment required by this store instruction. */
5727 /* True for register offsets. */
5728 int register_offset;
5731 /* Comparison function used by qsort. */
5734 fix_24k_sort (const void *a, const void *b)
5736 const struct fix_24k_store_info *pos1 = a;
5737 const struct fix_24k_store_info *pos2 = b;
5739 return (pos1->off - pos2->off);
5742 /* INSN is a store instruction. Try to record the store information
5743 in STINFO. Return false if the information isn't known. */
5746 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
5747 const struct mips_cl_insn *insn)
5749 /* The instruction must have a known offset. */
5750 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
5753 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
5754 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
5758 /* Return the number of nops that would be needed to work around the 24k
5759 "lost data on stores during refill" errata if instruction INSN
5760 immediately followed the 2 instructions described by HIST.
5761 Ignore hazards that are contained within the first IGNORE
5762 instructions of HIST.
5764 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
5765 for the data cache refills and store data. The following describes
5766 the scenario where the store data could be lost.
5768 * A data cache miss, due to either a load or a store, causing fill
5769 data to be supplied by the memory subsystem
5770 * The first three doublewords of fill data are returned and written
5772 * A sequence of four stores occurs in consecutive cycles around the
5773 final doubleword of the fill:
5777 * Zero, One or more instructions
5780 The four stores A-D must be to different doublewords of the line that
5781 is being filled. The fourth instruction in the sequence above permits
5782 the fill of the final doubleword to be transferred from the FSB into
5783 the cache. In the sequence above, the stores may be either integer
5784 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
5785 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
5786 different doublewords on the line. If the floating point unit is
5787 running in 1:2 mode, it is not possible to create the sequence above
5788 using only floating point store instructions.
5790 In this case, the cache line being filled is incorrectly marked
5791 invalid, thereby losing the data from any store to the line that
5792 occurs between the original miss and the completion of the five
5793 cycle sequence shown above.
5795 The workarounds are:
5797 * Run the data cache in write-through mode.
5798 * Insert a non-store instruction between
5799 Store A and Store B or Store B and Store C. */
5802 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
5803 const struct mips_cl_insn *insn)
5805 struct fix_24k_store_info pos[3];
5806 int align, i, base_offset;
5811 /* If the previous instruction wasn't a store, there's nothing to
5813 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5816 /* If the instructions after the previous one are unknown, we have
5817 to assume the worst. */
5821 /* Check whether we are dealing with three consecutive stores. */
5822 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
5823 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
5826 /* If we don't know the relationship between the store addresses,
5827 assume the worst. */
5828 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
5829 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
5832 if (!fix_24k_record_store_info (&pos[0], insn)
5833 || !fix_24k_record_store_info (&pos[1], &hist[0])
5834 || !fix_24k_record_store_info (&pos[2], &hist[1]))
5837 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
5839 /* Pick a value of ALIGN and X such that all offsets are adjusted by
5840 X bytes and such that the base register + X is known to be aligned
5843 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
5847 align = pos[0].align_to;
5848 base_offset = pos[0].off;
5849 for (i = 1; i < 3; i++)
5850 if (align < pos[i].align_to)
5852 align = pos[i].align_to;
5853 base_offset = pos[i].off;
5855 for (i = 0; i < 3; i++)
5856 pos[i].off -= base_offset;
5859 pos[0].off &= ~align + 1;
5860 pos[1].off &= ~align + 1;
5861 pos[2].off &= ~align + 1;
5863 /* If any two stores write to the same chunk, they also write to the
5864 same doubleword. The offsets are still sorted at this point. */
5865 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
5868 /* A range of at least 9 bytes is needed for the stores to be in
5869 non-overlapping doublewords. */
5870 if (pos[2].off - pos[0].off <= 8)
5873 if (pos[2].off - pos[1].off >= 24
5874 || pos[1].off - pos[0].off >= 24
5875 || pos[2].off - pos[0].off >= 32)
5881 /* Return the number of nops that would be needed if instruction INSN
5882 immediately followed the MAX_NOPS instructions given by HIST,
5883 where HIST[0] is the most recent instruction. Ignore hazards
5884 between INSN and the first IGNORE instructions in HIST.
5886 If INSN is null, return the worse-case number of nops for any
5890 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
5891 const struct mips_cl_insn *insn)
5893 int i, nops, tmp_nops;
5896 for (i = ignore; i < MAX_DELAY_NOPS; i++)
5898 tmp_nops = insns_between (hist + i, insn) - i;
5899 if (tmp_nops > nops)
5903 if (mips_fix_vr4130 && !mips_opts.micromips)
5905 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
5906 if (tmp_nops > nops)
5910 if (mips_fix_24k && !mips_opts.micromips)
5912 tmp_nops = nops_for_24k (ignore, hist, insn);
5913 if (tmp_nops > nops)
5920 /* The variable arguments provide NUM_INSNS extra instructions that
5921 might be added to HIST. Return the largest number of nops that
5922 would be needed after the extended sequence, ignoring hazards
5923 in the first IGNORE instructions. */
5926 nops_for_sequence (int num_insns, int ignore,
5927 const struct mips_cl_insn *hist, ...)
5930 struct mips_cl_insn buffer[MAX_NOPS];
5931 struct mips_cl_insn *cursor;
5934 va_start (args, hist);
5935 cursor = buffer + num_insns;
5936 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
5937 while (cursor > buffer)
5938 *--cursor = *va_arg (args, const struct mips_cl_insn *);
5940 nops = nops_for_insn (ignore, buffer, NULL);
5945 /* Like nops_for_insn, but if INSN is a branch, take into account the
5946 worst-case delay for the branch target. */
5949 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
5950 const struct mips_cl_insn *insn)
5954 nops = nops_for_insn (ignore, hist, insn);
5955 if (delayed_branch_p (insn))
5957 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
5958 hist, insn, get_delay_slot_nop (insn));
5959 if (tmp_nops > nops)
5962 else if (compact_branch_p (insn))
5964 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
5965 if (tmp_nops > nops)
5971 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5974 fix_loongson2f_nop (struct mips_cl_insn * ip)
5976 gas_assert (!HAVE_CODE_COMPRESSION);
5977 if (strcmp (ip->insn_mo->name, "nop") == 0)
5978 ip->insn_opcode = LOONGSON2F_NOP_INSN;
5981 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
5982 jr target pc &= 'hffff_ffff_cfff_ffff. */
5985 fix_loongson2f_jump (struct mips_cl_insn * ip)
5987 gas_assert (!HAVE_CODE_COMPRESSION);
5988 if (strcmp (ip->insn_mo->name, "j") == 0
5989 || strcmp (ip->insn_mo->name, "jr") == 0
5990 || strcmp (ip->insn_mo->name, "jalr") == 0)
5998 sreg = EXTRACT_OPERAND (0, RS, *ip);
5999 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6002 ep.X_op = O_constant;
6003 ep.X_add_number = 0xcfff0000;
6004 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6005 ep.X_add_number = 0xffff;
6006 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6007 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6012 fix_loongson2f (struct mips_cl_insn * ip)
6014 if (mips_fix_loongson2f_nop)
6015 fix_loongson2f_nop (ip);
6017 if (mips_fix_loongson2f_jump)
6018 fix_loongson2f_jump (ip);
6021 /* IP is a branch that has a delay slot, and we need to fill it
6022 automatically. Return true if we can do that by swapping IP
6023 with the previous instruction.
6024 ADDRESS_EXPR is an operand of the instruction to be used with
6028 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
6029 bfd_reloc_code_real_type *reloc_type)
6031 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
6032 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
6034 /* -O2 and above is required for this optimization. */
6035 if (mips_optimize < 2)
6038 /* If we have seen .set volatile or .set nomove, don't optimize. */
6039 if (mips_opts.nomove)
6042 /* We can't swap if the previous instruction's position is fixed. */
6043 if (history[0].fixed_p)
6046 /* If the previous previous insn was in a .set noreorder, we can't
6047 swap. Actually, the MIPS assembler will swap in this situation.
6048 However, gcc configured -with-gnu-as will generate code like
6056 in which we can not swap the bne and INSN. If gcc is not configured
6057 -with-gnu-as, it does not output the .set pseudo-ops. */
6058 if (history[1].noreorder_p)
6061 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
6062 This means that the previous instruction was a 4-byte one anyhow. */
6063 if (mips_opts.mips16 && history[0].fixp[0])
6066 /* If the branch is itself the target of a branch, we can not swap.
6067 We cheat on this; all we check for is whether there is a label on
6068 this instruction. If there are any branches to anything other than
6069 a label, users must use .set noreorder. */
6070 if (seg_info (now_seg)->label_list)
6073 /* If the previous instruction is in a variant frag other than this
6074 branch's one, we cannot do the swap. This does not apply to
6075 MIPS16 code, which uses variant frags for different purposes. */
6076 if (!mips_opts.mips16
6078 && history[0].frag->fr_type == rs_machine_dependent)
6081 /* We do not swap with instructions that cannot architecturally
6082 be placed in a branch delay slot, such as SYNC or ERET. We
6083 also refrain from swapping with a trap instruction, since it
6084 complicates trap handlers to have the trap instruction be in
6086 prev_pinfo = history[0].insn_mo->pinfo;
6087 if (prev_pinfo & INSN_NO_DELAY_SLOT)
6090 /* Check for conflicts between the branch and the instructions
6091 before the candidate delay slot. */
6092 if (nops_for_insn (0, history + 1, ip) > 0)
6095 /* Check for conflicts between the swapped sequence and the
6096 target of the branch. */
6097 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
6100 /* If the branch reads a register that the previous
6101 instruction sets, we can not swap. */
6102 gpr_read = gpr_read_mask (ip);
6103 prev_gpr_write = gpr_write_mask (&history[0]);
6104 if (gpr_read & prev_gpr_write)
6107 /* If the branch writes a register that the previous
6108 instruction sets, we can not swap. */
6109 gpr_write = gpr_write_mask (ip);
6110 if (gpr_write & prev_gpr_write)
6113 /* If the branch writes a register that the previous
6114 instruction reads, we can not swap. */
6115 prev_gpr_read = gpr_read_mask (&history[0]);
6116 if (gpr_write & prev_gpr_read)
6119 /* If one instruction sets a condition code and the
6120 other one uses a condition code, we can not swap. */
6121 pinfo = ip->insn_mo->pinfo;
6122 if ((pinfo & INSN_READ_COND_CODE)
6123 && (prev_pinfo & INSN_WRITE_COND_CODE))
6125 if ((pinfo & INSN_WRITE_COND_CODE)
6126 && (prev_pinfo & INSN_READ_COND_CODE))
6129 /* If the previous instruction uses the PC, we can not swap. */
6130 prev_pinfo2 = history[0].insn_mo->pinfo2;
6131 if (prev_pinfo2 & INSN2_READ_PC)
6134 /* If the previous instruction has an incorrect size for a fixed
6135 branch delay slot in microMIPS mode, we cannot swap. */
6136 pinfo2 = ip->insn_mo->pinfo2;
6137 if (mips_opts.micromips
6138 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
6139 && insn_length (history) != 2)
6141 if (mips_opts.micromips
6142 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
6143 && insn_length (history) != 4)
6146 /* On R5900 short loops need to be fixed by inserting a nop in
6147 the branch delay slots.
6148 A short loop can be terminated too early. */
6149 if (mips_opts.arch == CPU_R5900
6150 /* Check if instruction has a parameter, ignore "j $31". */
6151 && (address_expr != NULL)
6152 /* Parameter must be 16 bit. */
6153 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
6154 /* Branch to same segment. */
6155 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
6156 /* Branch to same code fragment. */
6157 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
6158 /* Can only calculate branch offset if value is known. */
6159 && symbol_constant_p(address_expr->X_add_symbol)
6160 /* Check if branch is really conditional. */
6161 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
6162 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
6163 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
6166 /* Check if loop is shorter than 6 instructions including
6167 branch and delay slot. */
6168 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
6175 /* When the loop includes branches or jumps,
6176 it is not a short loop. */
6177 for (i = 0; i < (distance / 4); i++)
6179 if ((history[i].cleared_p)
6180 || delayed_branch_p(&history[i]))
6188 /* Insert nop after branch to fix short loop. */
6197 /* Decide how we should add IP to the instruction stream.
6198 ADDRESS_EXPR is an operand of the instruction to be used with
6201 static enum append_method
6202 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
6203 bfd_reloc_code_real_type *reloc_type)
6205 /* The relaxed version of a macro sequence must be inherently
6207 if (mips_relax.sequence == 2)
6210 /* We must not dabble with instructions in a ".set norerorder" block. */
6211 if (mips_opts.noreorder)
6214 /* Otherwise, it's our responsibility to fill branch delay slots. */
6215 if (delayed_branch_p (ip))
6217 if (!branch_likely_p (ip)
6218 && can_swap_branch_p (ip, address_expr, reloc_type))
6221 if (mips_opts.mips16
6222 && ISA_SUPPORTS_MIPS16E
6223 && gpr_read_mask (ip) != 0)
6224 return APPEND_ADD_COMPACT;
6226 return APPEND_ADD_WITH_NOP;
6232 /* IP is a MIPS16 instruction whose opcode we have just changed.
6233 Point IP->insn_mo to the new opcode's definition. */
6236 find_altered_mips16_opcode (struct mips_cl_insn *ip)
6238 const struct mips_opcode *mo, *end;
6240 end = &mips16_opcodes[bfd_mips16_num_opcodes];
6241 for (mo = ip->insn_mo; mo < end; mo++)
6242 if ((ip->insn_opcode & mo->mask) == mo->match)
6250 /* For microMIPS macros, we need to generate a local number label
6251 as the target of branches. */
6252 #define MICROMIPS_LABEL_CHAR '\037'
6253 static unsigned long micromips_target_label;
6254 static char micromips_target_name[32];
6257 micromips_label_name (void)
6259 char *p = micromips_target_name;
6260 char symbol_name_temporary[24];
6268 l = micromips_target_label;
6269 #ifdef LOCAL_LABEL_PREFIX
6270 *p++ = LOCAL_LABEL_PREFIX;
6273 *p++ = MICROMIPS_LABEL_CHAR;
6276 symbol_name_temporary[i++] = l % 10 + '0';
6281 *p++ = symbol_name_temporary[--i];
6284 return micromips_target_name;
6288 micromips_label_expr (expressionS *label_expr)
6290 label_expr->X_op = O_symbol;
6291 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
6292 label_expr->X_add_number = 0;
6296 micromips_label_inc (void)
6298 micromips_target_label++;
6299 *micromips_target_name = '\0';
6303 micromips_add_label (void)
6307 s = colon (micromips_label_name ());
6308 micromips_label_inc ();
6309 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
6312 /* If assembling microMIPS code, then return the microMIPS reloc
6313 corresponding to the requested one if any. Otherwise return
6314 the reloc unchanged. */
6316 static bfd_reloc_code_real_type
6317 micromips_map_reloc (bfd_reloc_code_real_type reloc)
6319 static const bfd_reloc_code_real_type relocs[][2] =
6321 /* Keep sorted incrementally by the left-hand key. */
6322 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
6323 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
6324 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
6325 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
6326 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
6327 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
6328 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
6329 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
6330 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
6331 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
6332 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
6333 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
6334 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
6335 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
6336 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
6337 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
6338 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
6339 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
6340 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
6341 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
6342 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
6343 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
6344 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
6345 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
6346 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
6347 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
6348 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
6350 bfd_reloc_code_real_type r;
6353 if (!mips_opts.micromips)
6355 for (i = 0; i < ARRAY_SIZE (relocs); i++)
6361 return relocs[i][1];
6366 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
6367 Return true on success, storing the resolved value in RESULT. */
6370 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
6375 case BFD_RELOC_MIPS_HIGHEST:
6376 case BFD_RELOC_MICROMIPS_HIGHEST:
6377 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
6380 case BFD_RELOC_MIPS_HIGHER:
6381 case BFD_RELOC_MICROMIPS_HIGHER:
6382 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
6385 case BFD_RELOC_HI16_S:
6386 case BFD_RELOC_MICROMIPS_HI16_S:
6387 case BFD_RELOC_MIPS16_HI16_S:
6388 *result = ((operand + 0x8000) >> 16) & 0xffff;
6391 case BFD_RELOC_HI16:
6392 case BFD_RELOC_MICROMIPS_HI16:
6393 case BFD_RELOC_MIPS16_HI16:
6394 *result = (operand >> 16) & 0xffff;
6397 case BFD_RELOC_LO16:
6398 case BFD_RELOC_MICROMIPS_LO16:
6399 case BFD_RELOC_MIPS16_LO16:
6400 *result = operand & 0xffff;
6403 case BFD_RELOC_UNUSED:
6412 /* Output an instruction. IP is the instruction information.
6413 ADDRESS_EXPR is an operand of the instruction to be used with
6414 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
6415 a macro expansion. */
6418 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
6419 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
6421 unsigned long prev_pinfo2, pinfo;
6422 bfd_boolean relaxed_branch = FALSE;
6423 enum append_method method;
6424 bfd_boolean relax32;
6427 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
6428 fix_loongson2f (ip);
6430 file_ase_mips16 |= mips_opts.mips16;
6431 file_ase_micromips |= mips_opts.micromips;
6433 prev_pinfo2 = history[0].insn_mo->pinfo2;
6434 pinfo = ip->insn_mo->pinfo;
6436 if (mips_opts.micromips
6438 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
6439 && micromips_insn_length (ip->insn_mo) != 2)
6440 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
6441 && micromips_insn_length (ip->insn_mo) != 4)))
6442 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
6443 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
6445 if (address_expr == NULL)
6447 else if (reloc_type[0] <= BFD_RELOC_UNUSED
6448 && reloc_type[1] == BFD_RELOC_UNUSED
6449 && reloc_type[2] == BFD_RELOC_UNUSED
6450 && address_expr->X_op == O_constant)
6452 switch (*reloc_type)
6454 case BFD_RELOC_MIPS_JMP:
6458 shift = mips_opts.micromips ? 1 : 2;
6459 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6460 as_bad (_("jump to misaligned address (0x%lx)"),
6461 (unsigned long) address_expr->X_add_number);
6462 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6468 case BFD_RELOC_MIPS16_JMP:
6469 if ((address_expr->X_add_number & 3) != 0)
6470 as_bad (_("jump to misaligned address (0x%lx)"),
6471 (unsigned long) address_expr->X_add_number);
6473 (((address_expr->X_add_number & 0x7c0000) << 3)
6474 | ((address_expr->X_add_number & 0xf800000) >> 7)
6475 | ((address_expr->X_add_number & 0x3fffc) >> 2));
6479 case BFD_RELOC_16_PCREL_S2:
6483 shift = mips_opts.micromips ? 1 : 2;
6484 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
6485 as_bad (_("branch to misaligned address (0x%lx)"),
6486 (unsigned long) address_expr->X_add_number);
6487 if (!mips_relax_branch)
6489 if ((address_expr->X_add_number + (1 << (shift + 15)))
6490 & ~((1 << (shift + 16)) - 1))
6491 as_bad (_("branch address range overflow (0x%lx)"),
6492 (unsigned long) address_expr->X_add_number);
6493 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
6503 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
6506 ip->insn_opcode |= value & 0xffff;
6514 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
6516 /* There are a lot of optimizations we could do that we don't.
6517 In particular, we do not, in general, reorder instructions.
6518 If you use gcc with optimization, it will reorder
6519 instructions and generally do much more optimization then we
6520 do here; repeating all that work in the assembler would only
6521 benefit hand written assembly code, and does not seem worth
6523 int nops = (mips_optimize == 0
6524 ? nops_for_insn (0, history, NULL)
6525 : nops_for_insn_or_target (0, history, ip));
6529 unsigned long old_frag_offset;
6532 old_frag = frag_now;
6533 old_frag_offset = frag_now_fix ();
6535 for (i = 0; i < nops; i++)
6536 add_fixed_insn (NOP_INSN);
6537 insert_into_history (0, nops, NOP_INSN);
6541 listing_prev_line ();
6542 /* We may be at the start of a variant frag. In case we
6543 are, make sure there is enough space for the frag
6544 after the frags created by listing_prev_line. The
6545 argument to frag_grow here must be at least as large
6546 as the argument to all other calls to frag_grow in
6547 this file. We don't have to worry about being in the
6548 middle of a variant frag, because the variants insert
6549 all needed nop instructions themselves. */
6553 mips_move_text_labels ();
6555 #ifndef NO_ECOFF_DEBUGGING
6556 if (ECOFF_DEBUGGING)
6557 ecoff_fix_loc (old_frag, old_frag_offset);
6561 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
6565 /* Work out how many nops in prev_nop_frag are needed by IP,
6566 ignoring hazards generated by the first prev_nop_frag_since
6568 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
6569 gas_assert (nops <= prev_nop_frag_holds);
6571 /* Enforce NOPS as a minimum. */
6572 if (nops > prev_nop_frag_required)
6573 prev_nop_frag_required = nops;
6575 if (prev_nop_frag_holds == prev_nop_frag_required)
6577 /* Settle for the current number of nops. Update the history
6578 accordingly (for the benefit of any future .set reorder code). */
6579 prev_nop_frag = NULL;
6580 insert_into_history (prev_nop_frag_since,
6581 prev_nop_frag_holds, NOP_INSN);
6585 /* Allow this instruction to replace one of the nops that was
6586 tentatively added to prev_nop_frag. */
6587 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
6588 prev_nop_frag_holds--;
6589 prev_nop_frag_since++;
6593 method = get_append_method (ip, address_expr, reloc_type);
6594 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
6596 dwarf2_emit_insn (0);
6597 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
6598 so "move" the instruction address accordingly.
6600 Also, it doesn't seem appropriate for the assembler to reorder .loc
6601 entries. If this instruction is a branch that we are going to swap
6602 with the previous instruction, the two instructions should be
6603 treated as a unit, and the debug information for both instructions
6604 should refer to the start of the branch sequence. Using the
6605 current position is certainly wrong when swapping a 32-bit branch
6606 and a 16-bit delay slot, since the current position would then be
6607 in the middle of a branch. */
6608 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
6610 relax32 = (mips_relax_branch
6611 /* Don't try branch relaxation within .set nomacro, or within
6612 .set noat if we use $at for PIC computations. If it turns
6613 out that the branch was out-of-range, we'll get an error. */
6614 && !mips_opts.warn_about_macros
6615 && (mips_opts.at || mips_pic == NO_PIC)
6616 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
6617 as they have no complementing branches. */
6618 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
6620 if (!HAVE_CODE_COMPRESSION
6623 && *reloc_type == BFD_RELOC_16_PCREL_S2
6624 && delayed_branch_p (ip))
6626 relaxed_branch = TRUE;
6627 add_relaxed_insn (ip, (relaxed_branch_length
6629 uncond_branch_p (ip) ? -1
6630 : branch_likely_p (ip) ? 1
6634 uncond_branch_p (ip),
6635 branch_likely_p (ip),
6636 pinfo & INSN_WRITE_GPR_31,
6638 address_expr->X_add_symbol,
6639 address_expr->X_add_number);
6640 *reloc_type = BFD_RELOC_UNUSED;
6642 else if (mips_opts.micromips
6644 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
6645 || *reloc_type > BFD_RELOC_UNUSED)
6646 && (delayed_branch_p (ip) || compact_branch_p (ip))
6647 /* Don't try branch relaxation when users specify
6648 16-bit/32-bit instructions. */
6649 && !forced_insn_length)
6651 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
6652 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
6653 int uncond = uncond_branch_p (ip) ? -1 : 0;
6654 int compact = compact_branch_p (ip);
6655 int al = pinfo & INSN_WRITE_GPR_31;
6658 gas_assert (address_expr != NULL);
6659 gas_assert (!mips_relax.sequence);
6661 relaxed_branch = TRUE;
6662 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
6663 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
6664 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
6666 address_expr->X_add_symbol,
6667 address_expr->X_add_number);
6668 *reloc_type = BFD_RELOC_UNUSED;
6670 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
6672 /* We need to set up a variant frag. */
6673 gas_assert (address_expr != NULL);
6674 add_relaxed_insn (ip, 4, 0,
6676 (*reloc_type - BFD_RELOC_UNUSED,
6677 forced_insn_length == 2, forced_insn_length == 4,
6678 delayed_branch_p (&history[0]),
6679 history[0].mips16_absolute_jump_p),
6680 make_expr_symbol (address_expr), 0);
6682 else if (mips_opts.mips16 && insn_length (ip) == 2)
6684 if (!delayed_branch_p (ip))
6685 /* Make sure there is enough room to swap this instruction with
6686 a following jump instruction. */
6688 add_fixed_insn (ip);
6692 if (mips_opts.mips16
6693 && mips_opts.noreorder
6694 && delayed_branch_p (&history[0]))
6695 as_warn (_("extended instruction in delay slot"));
6697 if (mips_relax.sequence)
6699 /* If we've reached the end of this frag, turn it into a variant
6700 frag and record the information for the instructions we've
6702 if (frag_room () < 4)
6703 relax_close_frag ();
6704 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
6707 if (mips_relax.sequence != 2)
6709 if (mips_macro_warning.first_insn_sizes[0] == 0)
6710 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
6711 mips_macro_warning.sizes[0] += insn_length (ip);
6712 mips_macro_warning.insns[0]++;
6714 if (mips_relax.sequence != 1)
6716 if (mips_macro_warning.first_insn_sizes[1] == 0)
6717 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
6718 mips_macro_warning.sizes[1] += insn_length (ip);
6719 mips_macro_warning.insns[1]++;
6722 if (mips_opts.mips16)
6725 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
6727 add_fixed_insn (ip);
6730 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
6732 bfd_reloc_code_real_type final_type[3];
6733 reloc_howto_type *howto0;
6734 reloc_howto_type *howto;
6737 /* Perform any necessary conversion to microMIPS relocations
6738 and find out how many relocations there actually are. */
6739 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
6740 final_type[i] = micromips_map_reloc (reloc_type[i]);
6742 /* In a compound relocation, it is the final (outermost)
6743 operator that determines the relocated field. */
6744 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
6749 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
6750 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
6751 bfd_get_reloc_size (howto),
6753 howto0 && howto0->pc_relative,
6756 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
6757 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
6758 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
6760 /* These relocations can have an addend that won't fit in
6761 4 octets for 64bit assembly. */
6763 && ! howto->partial_inplace
6764 && (reloc_type[0] == BFD_RELOC_16
6765 || reloc_type[0] == BFD_RELOC_32
6766 || reloc_type[0] == BFD_RELOC_MIPS_JMP
6767 || reloc_type[0] == BFD_RELOC_GPREL16
6768 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
6769 || reloc_type[0] == BFD_RELOC_GPREL32
6770 || reloc_type[0] == BFD_RELOC_64
6771 || reloc_type[0] == BFD_RELOC_CTOR
6772 || reloc_type[0] == BFD_RELOC_MIPS_SUB
6773 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
6774 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
6775 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
6776 || reloc_type[0] == BFD_RELOC_MIPS_REL16
6777 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
6778 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
6779 || hi16_reloc_p (reloc_type[0])
6780 || lo16_reloc_p (reloc_type[0])))
6781 ip->fixp[0]->fx_no_overflow = 1;
6783 /* These relocations can have an addend that won't fit in 2 octets. */
6784 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
6785 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
6786 ip->fixp[0]->fx_no_overflow = 1;
6788 if (mips_relax.sequence)
6790 if (mips_relax.first_fixup == 0)
6791 mips_relax.first_fixup = ip->fixp[0];
6793 else if (reloc_needs_lo_p (*reloc_type))
6795 struct mips_hi_fixup *hi_fixup;
6797 /* Reuse the last entry if it already has a matching %lo. */
6798 hi_fixup = mips_hi_fixup_list;
6800 || !fixup_has_matching_lo_p (hi_fixup->fixp))
6802 hi_fixup = ((struct mips_hi_fixup *)
6803 xmalloc (sizeof (struct mips_hi_fixup)));
6804 hi_fixup->next = mips_hi_fixup_list;
6805 mips_hi_fixup_list = hi_fixup;
6807 hi_fixup->fixp = ip->fixp[0];
6808 hi_fixup->seg = now_seg;
6811 /* Add fixups for the second and third relocations, if given.
6812 Note that the ABI allows the second relocation to be
6813 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
6814 moment we only use RSS_UNDEF, but we could add support
6815 for the others if it ever becomes necessary. */
6816 for (i = 1; i < 3; i++)
6817 if (reloc_type[i] != BFD_RELOC_UNUSED)
6819 ip->fixp[i] = fix_new (ip->frag, ip->where,
6820 ip->fixp[0]->fx_size, NULL, 0,
6821 FALSE, final_type[i]);
6823 /* Use fx_tcbit to mark compound relocs. */
6824 ip->fixp[0]->fx_tcbit = 1;
6825 ip->fixp[i]->fx_tcbit = 1;
6830 /* Update the register mask information. */
6831 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
6832 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
6837 insert_into_history (0, 1, ip);
6840 case APPEND_ADD_WITH_NOP:
6842 struct mips_cl_insn *nop;
6844 insert_into_history (0, 1, ip);
6845 nop = get_delay_slot_nop (ip);
6846 add_fixed_insn (nop);
6847 insert_into_history (0, 1, nop);
6848 if (mips_relax.sequence)
6849 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
6853 case APPEND_ADD_COMPACT:
6854 /* Convert MIPS16 jr/jalr into a "compact" jump. */
6855 gas_assert (mips_opts.mips16);
6856 ip->insn_opcode |= 0x0080;
6857 find_altered_mips16_opcode (ip);
6859 insert_into_history (0, 1, ip);
6864 struct mips_cl_insn delay = history[0];
6865 if (mips_opts.mips16)
6867 know (delay.frag == ip->frag);
6868 move_insn (ip, delay.frag, delay.where);
6869 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
6871 else if (relaxed_branch || delay.frag != ip->frag)
6873 /* Add the delay slot instruction to the end of the
6874 current frag and shrink the fixed part of the
6875 original frag. If the branch occupies the tail of
6876 the latter, move it backwards to cover the gap. */
6877 delay.frag->fr_fix -= branch_disp;
6878 if (delay.frag == ip->frag)
6879 move_insn (ip, ip->frag, ip->where - branch_disp);
6880 add_fixed_insn (&delay);
6884 move_insn (&delay, ip->frag,
6885 ip->where - branch_disp + insn_length (ip));
6886 move_insn (ip, history[0].frag, history[0].where);
6890 insert_into_history (0, 1, &delay);
6895 /* If we have just completed an unconditional branch, clear the history. */
6896 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
6897 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
6901 mips_no_prev_insn ();
6903 for (i = 0; i < ARRAY_SIZE (history); i++)
6904 history[i].cleared_p = 1;
6907 /* We need to emit a label at the end of branch-likely macros. */
6908 if (emit_branch_likely_macro)
6910 emit_branch_likely_macro = FALSE;
6911 micromips_add_label ();
6914 /* We just output an insn, so the next one doesn't have a label. */
6915 mips_clear_insn_labels ();
6918 /* Forget that there was any previous instruction or label.
6919 When BRANCH is true, the branch history is also flushed. */
6922 mips_no_prev_insn (void)
6924 prev_nop_frag = NULL;
6925 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
6926 mips_clear_insn_labels ();
6929 /* This function must be called before we emit something other than
6930 instructions. It is like mips_no_prev_insn except that it inserts
6931 any NOPS that might be needed by previous instructions. */
6934 mips_emit_delays (void)
6936 if (! mips_opts.noreorder)
6938 int nops = nops_for_insn (0, history, NULL);
6942 add_fixed_insn (NOP_INSN);
6943 mips_move_text_labels ();
6946 mips_no_prev_insn ();
6949 /* Start a (possibly nested) noreorder block. */
6952 start_noreorder (void)
6954 if (mips_opts.noreorder == 0)
6959 /* None of the instructions before the .set noreorder can be moved. */
6960 for (i = 0; i < ARRAY_SIZE (history); i++)
6961 history[i].fixed_p = 1;
6963 /* Insert any nops that might be needed between the .set noreorder
6964 block and the previous instructions. We will later remove any
6965 nops that turn out not to be needed. */
6966 nops = nops_for_insn (0, history, NULL);
6969 if (mips_optimize != 0)
6971 /* Record the frag which holds the nop instructions, so
6972 that we can remove them if we don't need them. */
6973 frag_grow (nops * NOP_INSN_SIZE);
6974 prev_nop_frag = frag_now;
6975 prev_nop_frag_holds = nops;
6976 prev_nop_frag_required = 0;
6977 prev_nop_frag_since = 0;
6980 for (; nops > 0; --nops)
6981 add_fixed_insn (NOP_INSN);
6983 /* Move on to a new frag, so that it is safe to simply
6984 decrease the size of prev_nop_frag. */
6985 frag_wane (frag_now);
6987 mips_move_text_labels ();
6989 mips_mark_labels ();
6990 mips_clear_insn_labels ();
6992 mips_opts.noreorder++;
6993 mips_any_noreorder = 1;
6996 /* End a nested noreorder block. */
6999 end_noreorder (void)
7001 mips_opts.noreorder--;
7002 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
7004 /* Commit to inserting prev_nop_frag_required nops and go back to
7005 handling nop insertion the .set reorder way. */
7006 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
7008 insert_into_history (prev_nop_frag_since,
7009 prev_nop_frag_required, NOP_INSN);
7010 prev_nop_frag = NULL;
7014 /* Sign-extend 32-bit mode constants that have bit 31 set and all
7015 higher bits unset. */
7018 normalize_constant_expr (expressionS *ex)
7020 if (ex->X_op == O_constant
7021 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7022 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7026 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
7027 all higher bits unset. */
7030 normalize_address_expr (expressionS *ex)
7032 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
7033 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
7034 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
7035 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
7039 /* Try to match TOKENS against OPCODE, storing the result in INSN.
7040 Return true if the match was successful.
7042 OPCODE_EXTRA is a value that should be ORed into the opcode
7043 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
7044 there are more alternatives after OPCODE and SOFT_MATCH is
7045 as for mips_arg_info. */
7048 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7049 struct mips_operand_token *tokens, unsigned int opcode_extra,
7050 bfd_boolean more_alts)
7053 struct mips_arg_info arg;
7054 const struct mips_operand *operand;
7057 imm_expr.X_op = O_absent;
7058 imm2_expr.X_op = O_absent;
7059 offset_expr.X_op = O_absent;
7060 offset_reloc[0] = BFD_RELOC_UNUSED;
7061 offset_reloc[1] = BFD_RELOC_UNUSED;
7062 offset_reloc[2] = BFD_RELOC_UNUSED;
7064 create_insn (insn, opcode);
7065 insn->insn_opcode |= opcode_extra;
7066 memset (&arg, 0, sizeof (arg));
7070 arg.last_regno = ILLEGAL_REG;
7071 arg.dest_regno = ILLEGAL_REG;
7072 for (args = opcode->args;; ++args)
7074 if (arg.token->type == OT_END)
7076 /* Handle unary instructions in which only one operand is given.
7077 The source is then the same as the destination. */
7078 if (arg.opnum == 1 && *args == ',')
7080 operand = (mips_opts.micromips
7081 ? decode_micromips_operand (args + 1)
7082 : decode_mips_operand (args + 1));
7083 if (operand && mips_optional_operand_p (operand))
7091 /* Treat elided base registers as $0. */
7092 if (strcmp (args, "(b)") == 0)
7100 /* The register suffix is optional. */
7105 /* Fail the match if there were too few operands. */
7109 /* Successful match. */
7110 clear_insn_error ();
7111 if (arg.dest_regno == arg.last_regno
7112 && strncmp (insn->insn_mo->name, "jalr", 4) == 0)
7116 (0, _("Source and destination must be different"));
7117 else if (arg.last_regno == 31)
7119 (0, _("A destination register must be supplied"));
7121 check_completed_insn (&arg);
7125 /* Fail the match if the line has too many operands. */
7129 /* Handle characters that need to match exactly. */
7130 if (*args == '(' || *args == ')' || *args == ',')
7132 if (match_char (&arg, *args))
7139 if (arg.token->type == OT_DOUBLE_CHAR
7140 && arg.token->u.ch == *args)
7148 /* Handle special macro operands. Work out the properties of
7151 arg.lax_max = FALSE;
7158 /* "+I" is like "I", except that imm2_expr is used. */
7159 if (!match_const_int (&arg, &imm2_expr.X_add_number))
7161 imm2_expr.X_op = O_constant;
7162 if (HAVE_32BIT_GPRS)
7163 normalize_constant_expr (&imm2_expr);
7168 *offset_reloc = BFD_RELOC_MIPS_JMP;
7174 if (!match_const_int (&arg, &imm_expr.X_add_number))
7176 imm_expr.X_op = O_constant;
7177 if (HAVE_32BIT_GPRS)
7178 normalize_constant_expr (&imm_expr);
7182 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7184 /* Assume that the offset has been elided and that what
7185 we saw was a base register. The match will fail later
7186 if that assumption turns out to be wrong. */
7187 offset_expr.X_op = O_constant;
7188 offset_expr.X_add_number = 0;
7192 if (!match_expression (&arg, &offset_expr, offset_reloc))
7194 normalize_address_expr (&offset_expr);
7199 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7205 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7211 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7217 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
7222 /* ??? This is the traditional behavior, but is flaky if
7223 there are alternative versions of the same instruction
7224 for different subarchitectures. The next alternative
7225 might not be suitable. */
7227 /* For compatibility with older assemblers, we accept
7228 0x8000-0xffff as signed 16-bit numbers when only
7229 signed numbers are allowed. */
7230 arg.lax_max = !more_alts;
7232 /* Only accept non-constant operands if this is the
7233 final alternative. Later alternatives might include
7234 a macro implementation. */
7235 arg.allow_nonconst = !more_alts;
7239 /* There are no macro implementations for out-of-range values. */
7240 arg.allow_nonconst = TRUE;
7244 /* There should always be a macro implementation. */
7245 arg.allow_nonconst = FALSE;
7249 *offset_reloc = BFD_RELOC_16_PCREL_S2;
7253 *offset_reloc = BFD_RELOC_MIPS_JMP;
7257 gas_assert (mips_opts.micromips);
7263 if (!forced_insn_length)
7264 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
7266 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
7268 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
7274 operand = (mips_opts.micromips
7275 ? decode_micromips_operand (args)
7276 : decode_mips_operand (args));
7280 /* Skip prefixes. */
7281 if (*args == '+' || *args == 'm')
7284 if (mips_optional_operand_p (operand)
7286 && (arg.token[0].type != OT_REG
7287 || arg.token[1].type == OT_END))
7289 /* Assume that the register has been elided and is the
7290 same as the first operand. */
7295 if (!match_operand (&arg, operand))
7300 /* Like match_insn, but for MIPS16. */
7303 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
7304 struct mips_operand_token *tokens)
7307 const struct mips_operand *operand;
7308 const struct mips_operand *ext_operand;
7309 struct mips_arg_info arg;
7312 create_insn (insn, opcode);
7313 imm_expr.X_op = O_absent;
7314 imm2_expr.X_op = O_absent;
7315 offset_expr.X_op = O_absent;
7316 offset_reloc[0] = BFD_RELOC_UNUSED;
7317 offset_reloc[1] = BFD_RELOC_UNUSED;
7318 offset_reloc[2] = BFD_RELOC_UNUSED;
7321 memset (&arg, 0, sizeof (arg));
7325 arg.last_regno = ILLEGAL_REG;
7326 arg.dest_regno = ILLEGAL_REG;
7328 for (args = opcode->args;; ++args)
7332 if (arg.token->type == OT_END)
7336 /* Handle unary instructions in which only one operand is given.
7337 The source is then the same as the destination. */
7338 if (arg.opnum == 1 && *args == ',')
7340 operand = decode_mips16_operand (args[1], FALSE);
7341 if (operand && mips_optional_operand_p (operand))
7349 /* Fail the match if there were too few operands. */
7353 /* Successful match. Stuff the immediate value in now, if
7355 clear_insn_error ();
7356 if (opcode->pinfo == INSN_MACRO)
7358 gas_assert (relax_char == 0 || relax_char == 'p');
7359 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
7362 && offset_expr.X_op == O_constant
7363 && calculate_reloc (*offset_reloc,
7364 offset_expr.X_add_number,
7367 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
7368 forced_insn_length, &insn->insn_opcode);
7369 offset_expr.X_op = O_absent;
7370 *offset_reloc = BFD_RELOC_UNUSED;
7372 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
7374 if (forced_insn_length == 2)
7375 set_insn_error (0, _("invalid unextended operand value"));
7376 forced_insn_length = 4;
7377 insn->insn_opcode |= MIPS16_EXTEND;
7379 else if (relax_char)
7380 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
7382 check_completed_insn (&arg);
7386 /* Fail the match if the line has too many operands. */
7390 /* Handle characters that need to match exactly. */
7391 if (*args == '(' || *args == ')' || *args == ',')
7393 if (match_char (&arg, *args))
7411 if (!match_const_int (&arg, &imm_expr.X_add_number))
7413 imm_expr.X_op = O_constant;
7414 if (HAVE_32BIT_GPRS)
7415 normalize_constant_expr (&imm_expr);
7420 *offset_reloc = BFD_RELOC_MIPS16_JMP;
7421 insn->insn_opcode <<= 16;
7425 operand = decode_mips16_operand (c, FALSE);
7429 /* '6' is a special case. It is used for BREAK and SDBBP,
7430 whose operands are only meaningful to the software that decodes
7431 them. This means that there is no architectural reason why
7432 they cannot be prefixed by EXTEND, but in practice,
7433 exception handlers will only look at the instruction
7434 itself. We therefore allow '6' to be extended when
7435 disassembling but not when assembling. */
7436 if (operand->type != OP_PCREL && c != '6')
7438 ext_operand = decode_mips16_operand (c, TRUE);
7439 if (operand != ext_operand)
7441 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
7443 offset_expr.X_op = O_constant;
7444 offset_expr.X_add_number = 0;
7449 /* We need the OT_INTEGER check because some MIPS16
7450 immediate variants are listed before the register ones. */
7451 if (arg.token->type != OT_INTEGER
7452 || !match_expression (&arg, &offset_expr, offset_reloc))
7455 /* '8' is used for SLTI(U) and has traditionally not
7456 been allowed to take relocation operators. */
7457 if (offset_reloc[0] != BFD_RELOC_UNUSED
7458 && (ext_operand->size != 16 || c == '8'))
7466 if (mips_optional_operand_p (operand)
7468 && (arg.token[0].type != OT_REG
7469 || arg.token[1].type == OT_END))
7471 /* Assume that the register has been elided and is the
7472 same as the first operand. */
7477 if (!match_operand (&arg, operand))
7482 /* Set up global variables for the start of a new macro. */
7487 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
7488 memset (&mips_macro_warning.first_insn_sizes, 0,
7489 sizeof (mips_macro_warning.first_insn_sizes));
7490 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
7491 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
7492 && delayed_branch_p (&history[0]));
7493 switch (history[0].insn_mo->pinfo2
7494 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
7496 case INSN2_BRANCH_DELAY_32BIT:
7497 mips_macro_warning.delay_slot_length = 4;
7499 case INSN2_BRANCH_DELAY_16BIT:
7500 mips_macro_warning.delay_slot_length = 2;
7503 mips_macro_warning.delay_slot_length = 0;
7506 mips_macro_warning.first_frag = NULL;
7509 /* Given that a macro is longer than one instruction or of the wrong size,
7510 return the appropriate warning for it. Return null if no warning is
7511 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
7512 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
7513 and RELAX_NOMACRO. */
7516 macro_warning (relax_substateT subtype)
7518 if (subtype & RELAX_DELAY_SLOT)
7519 return _("Macro instruction expanded into multiple instructions"
7520 " in a branch delay slot");
7521 else if (subtype & RELAX_NOMACRO)
7522 return _("Macro instruction expanded into multiple instructions");
7523 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
7524 | RELAX_DELAY_SLOT_SIZE_SECOND))
7525 return ((subtype & RELAX_DELAY_SLOT_16BIT)
7526 ? _("Macro instruction expanded into a wrong size instruction"
7527 " in a 16-bit branch delay slot")
7528 : _("Macro instruction expanded into a wrong size instruction"
7529 " in a 32-bit branch delay slot"));
7534 /* Finish up a macro. Emit warnings as appropriate. */
7539 /* Relaxation warning flags. */
7540 relax_substateT subtype = 0;
7542 /* Check delay slot size requirements. */
7543 if (mips_macro_warning.delay_slot_length == 2)
7544 subtype |= RELAX_DELAY_SLOT_16BIT;
7545 if (mips_macro_warning.delay_slot_length != 0)
7547 if (mips_macro_warning.delay_slot_length
7548 != mips_macro_warning.first_insn_sizes[0])
7549 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
7550 if (mips_macro_warning.delay_slot_length
7551 != mips_macro_warning.first_insn_sizes[1])
7552 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
7555 /* Check instruction count requirements. */
7556 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
7558 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
7559 subtype |= RELAX_SECOND_LONGER;
7560 if (mips_opts.warn_about_macros)
7561 subtype |= RELAX_NOMACRO;
7562 if (mips_macro_warning.delay_slot_p)
7563 subtype |= RELAX_DELAY_SLOT;
7566 /* If both alternatives fail to fill a delay slot correctly,
7567 emit the warning now. */
7568 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
7569 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
7574 s = subtype & (RELAX_DELAY_SLOT_16BIT
7575 | RELAX_DELAY_SLOT_SIZE_FIRST
7576 | RELAX_DELAY_SLOT_SIZE_SECOND);
7577 msg = macro_warning (s);
7579 as_warn ("%s", msg);
7583 /* If both implementations are longer than 1 instruction, then emit the
7585 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
7590 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
7591 msg = macro_warning (s);
7593 as_warn ("%s", msg);
7597 /* If any flags still set, then one implementation might need a warning
7598 and the other either will need one of a different kind or none at all.
7599 Pass any remaining flags over to relaxation. */
7600 if (mips_macro_warning.first_frag != NULL)
7601 mips_macro_warning.first_frag->fr_subtype |= subtype;
7604 /* Instruction operand formats used in macros that vary between
7605 standard MIPS and microMIPS code. */
7607 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
7608 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
7609 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
7610 static const char * const lui_fmt[2] = { "t,u", "s,u" };
7611 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
7612 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
7613 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
7614 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
7616 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
7617 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
7618 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
7619 #define LUI_FMT (lui_fmt[mips_opts.micromips])
7620 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
7621 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
7622 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
7623 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
7625 /* Read a macro's relocation codes from *ARGS and store them in *R.
7626 The first argument in *ARGS will be either the code for a single
7627 relocation or -1 followed by the three codes that make up a
7628 composite relocation. */
7631 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
7635 next = va_arg (*args, int);
7637 r[0] = (bfd_reloc_code_real_type) next;
7640 for (i = 0; i < 3; i++)
7641 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
7642 /* This function is only used for 16-bit relocation fields.
7643 To make the macro code simpler, treat an unrelocated value
7644 in the same way as BFD_RELOC_LO16. */
7645 if (r[0] == BFD_RELOC_UNUSED)
7646 r[0] = BFD_RELOC_LO16;
7650 /* Build an instruction created by a macro expansion. This is passed
7651 a pointer to the count of instructions created so far, an
7652 expression, the name of the instruction to build, an operand format
7653 string, and corresponding arguments. */
7656 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
7658 const struct mips_opcode *mo = NULL;
7659 bfd_reloc_code_real_type r[3];
7660 const struct mips_opcode *amo;
7661 const struct mips_operand *operand;
7662 struct hash_control *hash;
7663 struct mips_cl_insn insn;
7667 va_start (args, fmt);
7669 if (mips_opts.mips16)
7671 mips16_macro_build (ep, name, fmt, &args);
7676 r[0] = BFD_RELOC_UNUSED;
7677 r[1] = BFD_RELOC_UNUSED;
7678 r[2] = BFD_RELOC_UNUSED;
7679 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
7680 amo = (struct mips_opcode *) hash_find (hash, name);
7682 gas_assert (strcmp (name, amo->name) == 0);
7686 /* Search until we get a match for NAME. It is assumed here that
7687 macros will never generate MDMX, MIPS-3D, or MT instructions.
7688 We try to match an instruction that fulfils the branch delay
7689 slot instruction length requirement (if any) of the previous
7690 instruction. While doing this we record the first instruction
7691 seen that matches all the other conditions and use it anyway
7692 if the requirement cannot be met; we will issue an appropriate
7693 warning later on. */
7694 if (strcmp (fmt, amo->args) == 0
7695 && amo->pinfo != INSN_MACRO
7696 && is_opcode_valid (amo)
7697 && is_size_valid (amo))
7699 if (is_delay_slot_valid (amo))
7709 gas_assert (amo->name);
7711 while (strcmp (name, amo->name) == 0);
7714 create_insn (&insn, mo);
7727 macro_read_relocs (&args, r);
7728 gas_assert (*r == BFD_RELOC_GPREL16
7729 || *r == BFD_RELOC_MIPS_HIGHER
7730 || *r == BFD_RELOC_HI16_S
7731 || *r == BFD_RELOC_LO16
7732 || *r == BFD_RELOC_MIPS_GOT_OFST);
7736 macro_read_relocs (&args, r);
7740 macro_read_relocs (&args, r);
7741 gas_assert (ep != NULL
7742 && (ep->X_op == O_constant
7743 || (ep->X_op == O_symbol
7744 && (*r == BFD_RELOC_MIPS_HIGHEST
7745 || *r == BFD_RELOC_HI16_S
7746 || *r == BFD_RELOC_HI16
7747 || *r == BFD_RELOC_GPREL16
7748 || *r == BFD_RELOC_MIPS_GOT_HI16
7749 || *r == BFD_RELOC_MIPS_CALL_HI16))));
7753 gas_assert (ep != NULL);
7756 * This allows macro() to pass an immediate expression for
7757 * creating short branches without creating a symbol.
7759 * We don't allow branch relaxation for these branches, as
7760 * they should only appear in ".set nomacro" anyway.
7762 if (ep->X_op == O_constant)
7764 /* For microMIPS we always use relocations for branches.
7765 So we should not resolve immediate values. */
7766 gas_assert (!mips_opts.micromips);
7768 if ((ep->X_add_number & 3) != 0)
7769 as_bad (_("branch to misaligned address (0x%lx)"),
7770 (unsigned long) ep->X_add_number);
7771 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
7772 as_bad (_("branch address range overflow (0x%lx)"),
7773 (unsigned long) ep->X_add_number);
7774 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
7778 *r = BFD_RELOC_16_PCREL_S2;
7782 gas_assert (ep != NULL);
7783 *r = BFD_RELOC_MIPS_JMP;
7787 operand = (mips_opts.micromips
7788 ? decode_micromips_operand (fmt)
7789 : decode_mips_operand (fmt));
7793 uval = va_arg (args, int);
7794 if (operand->type == OP_CLO_CLZ_DEST)
7795 uval |= (uval << 5);
7796 insn_insert_operand (&insn, operand, uval);
7798 if (*fmt == '+' || *fmt == 'm')
7804 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7806 append_insn (&insn, ep, r, TRUE);
7810 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
7813 struct mips_opcode *mo;
7814 struct mips_cl_insn insn;
7815 const struct mips_operand *operand;
7816 bfd_reloc_code_real_type r[3]
7817 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
7819 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
7821 gas_assert (strcmp (name, mo->name) == 0);
7823 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
7826 gas_assert (mo->name);
7827 gas_assert (strcmp (name, mo->name) == 0);
7830 create_insn (&insn, mo);
7868 gas_assert (ep != NULL);
7870 if (ep->X_op != O_constant)
7871 *r = (int) BFD_RELOC_UNUSED + c;
7872 else if (calculate_reloc (*r, ep->X_add_number, &value))
7874 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
7876 *r = BFD_RELOC_UNUSED;
7882 operand = decode_mips16_operand (c, FALSE);
7886 insn_insert_operand (&insn, operand, va_arg (*args, int));
7891 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
7893 append_insn (&insn, ep, r, TRUE);
7897 * Generate a "jalr" instruction with a relocation hint to the called
7898 * function. This occurs in NewABI PIC code.
7901 macro_build_jalr (expressionS *ep, int cprestore)
7903 static const bfd_reloc_code_real_type jalr_relocs[2]
7904 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
7905 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
7909 if (MIPS_JALR_HINT_P (ep))
7914 if (mips_opts.micromips)
7916 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
7917 ? "jalr" : "jalrs");
7918 if (MIPS_JALR_HINT_P (ep)
7920 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
7921 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
7923 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
7926 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
7927 if (MIPS_JALR_HINT_P (ep))
7928 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
7932 * Generate a "lui" instruction.
7935 macro_build_lui (expressionS *ep, int regnum)
7937 gas_assert (! mips_opts.mips16);
7939 if (ep->X_op != O_constant)
7941 gas_assert (ep->X_op == O_symbol);
7942 /* _gp_disp is a special case, used from s_cpload.
7943 __gnu_local_gp is used if mips_no_shared. */
7944 gas_assert (mips_pic == NO_PIC
7946 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
7947 || (! mips_in_shared
7948 && strcmp (S_GET_NAME (ep->X_add_symbol),
7949 "__gnu_local_gp") == 0));
7952 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
7955 /* Generate a sequence of instructions to do a load or store from a constant
7956 offset off of a base register (breg) into/from a target register (treg),
7957 using AT if necessary. */
7959 macro_build_ldst_constoffset (expressionS *ep, const char *op,
7960 int treg, int breg, int dbl)
7962 gas_assert (ep->X_op == O_constant);
7964 /* Sign-extending 32-bit constants makes their handling easier. */
7966 normalize_constant_expr (ep);
7968 /* Right now, this routine can only handle signed 32-bit constants. */
7969 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
7970 as_warn (_("operand overflow"));
7972 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
7974 /* Signed 16-bit offset will fit in the op. Easy! */
7975 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7979 /* 32-bit offset, need multiple instructions and AT, like:
7980 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
7981 addu $tempreg,$tempreg,$breg
7982 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
7983 to handle the complete offset. */
7984 macro_build_lui (ep, AT);
7985 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7986 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7989 as_bad (_("Macro used $at after \".set noat\""));
7994 * Generates code to set the $at register to true (one)
7995 * if reg is less than the immediate expression.
7998 set_at (int reg, int unsignedp)
8000 if (imm_expr.X_op == O_constant
8001 && imm_expr.X_add_number >= -0x8000
8002 && imm_expr.X_add_number < 0x8000)
8003 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
8004 AT, reg, BFD_RELOC_LO16);
8007 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8008 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
8012 /* Count the leading zeroes by performing a binary chop. This is a
8013 bulky bit of source, but performance is a LOT better for the
8014 majority of values than a simple loop to count the bits:
8015 for (lcnt = 0; (lcnt < 32); lcnt++)
8016 if ((v) & (1 << (31 - lcnt)))
8018 However it is not code size friendly, and the gain will drop a bit
8019 on certain cached systems.
8021 #define COUNT_TOP_ZEROES(v) \
8022 (((v) & ~0xffff) == 0 \
8023 ? ((v) & ~0xff) == 0 \
8024 ? ((v) & ~0xf) == 0 \
8025 ? ((v) & ~0x3) == 0 \
8026 ? ((v) & ~0x1) == 0 \
8031 : ((v) & ~0x7) == 0 \
8034 : ((v) & ~0x3f) == 0 \
8035 ? ((v) & ~0x1f) == 0 \
8038 : ((v) & ~0x7f) == 0 \
8041 : ((v) & ~0xfff) == 0 \
8042 ? ((v) & ~0x3ff) == 0 \
8043 ? ((v) & ~0x1ff) == 0 \
8046 : ((v) & ~0x7ff) == 0 \
8049 : ((v) & ~0x3fff) == 0 \
8050 ? ((v) & ~0x1fff) == 0 \
8053 : ((v) & ~0x7fff) == 0 \
8056 : ((v) & ~0xffffff) == 0 \
8057 ? ((v) & ~0xfffff) == 0 \
8058 ? ((v) & ~0x3ffff) == 0 \
8059 ? ((v) & ~0x1ffff) == 0 \
8062 : ((v) & ~0x7ffff) == 0 \
8065 : ((v) & ~0x3fffff) == 0 \
8066 ? ((v) & ~0x1fffff) == 0 \
8069 : ((v) & ~0x7fffff) == 0 \
8072 : ((v) & ~0xfffffff) == 0 \
8073 ? ((v) & ~0x3ffffff) == 0 \
8074 ? ((v) & ~0x1ffffff) == 0 \
8077 : ((v) & ~0x7ffffff) == 0 \
8080 : ((v) & ~0x3fffffff) == 0 \
8081 ? ((v) & ~0x1fffffff) == 0 \
8084 : ((v) & ~0x7fffffff) == 0 \
8089 * This routine generates the least number of instructions necessary to load
8090 * an absolute expression value into a register.
8093 load_register (int reg, expressionS *ep, int dbl)
8096 expressionS hi32, lo32;
8098 if (ep->X_op != O_big)
8100 gas_assert (ep->X_op == O_constant);
8102 /* Sign-extending 32-bit constants makes their handling easier. */
8104 normalize_constant_expr (ep);
8106 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
8108 /* We can handle 16 bit signed values with an addiu to
8109 $zero. No need to ever use daddiu here, since $zero and
8110 the result are always correct in 32 bit mode. */
8111 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8114 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
8116 /* We can handle 16 bit unsigned values with an ori to
8118 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8121 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
8123 /* 32 bit values require an lui. */
8124 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8125 if ((ep->X_add_number & 0xffff) != 0)
8126 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8131 /* The value is larger than 32 bits. */
8133 if (!dbl || HAVE_32BIT_GPRS)
8137 sprintf_vma (value, ep->X_add_number);
8138 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8139 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8143 if (ep->X_op != O_big)
8146 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8147 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
8148 hi32.X_add_number &= 0xffffffff;
8150 lo32.X_add_number &= 0xffffffff;
8154 gas_assert (ep->X_add_number > 2);
8155 if (ep->X_add_number == 3)
8156 generic_bignum[3] = 0;
8157 else if (ep->X_add_number > 4)
8158 as_bad (_("Number larger than 64 bits"));
8159 lo32.X_op = O_constant;
8160 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
8161 hi32.X_op = O_constant;
8162 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
8165 if (hi32.X_add_number == 0)
8170 unsigned long hi, lo;
8172 if (hi32.X_add_number == (offsetT) 0xffffffff)
8174 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
8176 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8179 if (lo32.X_add_number & 0x80000000)
8181 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8182 if (lo32.X_add_number & 0xffff)
8183 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
8188 /* Check for 16bit shifted constant. We know that hi32 is
8189 non-zero, so start the mask on the first bit of the hi32
8194 unsigned long himask, lomask;
8198 himask = 0xffff >> (32 - shift);
8199 lomask = (0xffff << shift) & 0xffffffff;
8203 himask = 0xffff << (shift - 32);
8206 if ((hi32.X_add_number & ~(offsetT) himask) == 0
8207 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
8211 tmp.X_op = O_constant;
8213 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
8214 | (lo32.X_add_number >> shift));
8216 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
8217 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
8218 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8219 reg, reg, (shift >= 32) ? shift - 32 : shift);
8224 while (shift <= (64 - 16));
8226 /* Find the bit number of the lowest one bit, and store the
8227 shifted value in hi/lo. */
8228 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
8229 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
8233 while ((lo & 1) == 0)
8238 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
8244 while ((hi & 1) == 0)
8253 /* Optimize if the shifted value is a (power of 2) - 1. */
8254 if ((hi == 0 && ((lo + 1) & lo) == 0)
8255 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
8257 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
8262 /* This instruction will set the register to be all
8264 tmp.X_op = O_constant;
8265 tmp.X_add_number = (offsetT) -1;
8266 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
8270 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
8271 reg, reg, (bit >= 32) ? bit - 32 : bit);
8273 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
8274 reg, reg, (shift >= 32) ? shift - 32 : shift);
8279 /* Sign extend hi32 before calling load_register, because we can
8280 generally get better code when we load a sign extended value. */
8281 if ((hi32.X_add_number & 0x80000000) != 0)
8282 hi32.X_add_number |= ~(offsetT) 0xffffffff;
8283 load_register (reg, &hi32, 0);
8286 if ((lo32.X_add_number & 0xffff0000) == 0)
8290 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
8298 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
8300 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
8301 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
8307 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
8311 mid16.X_add_number >>= 16;
8312 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8313 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8316 if ((lo32.X_add_number & 0xffff) != 0)
8317 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
8321 load_delay_nop (void)
8323 if (!gpr_interlocks)
8324 macro_build (NULL, "nop", "");
8327 /* Load an address into a register. */
8330 load_address (int reg, expressionS *ep, int *used_at)
8332 if (ep->X_op != O_constant
8333 && ep->X_op != O_symbol)
8335 as_bad (_("expression too complex"));
8336 ep->X_op = O_constant;
8339 if (ep->X_op == O_constant)
8341 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
8345 if (mips_pic == NO_PIC)
8347 /* If this is a reference to a GP relative symbol, we want
8348 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
8350 lui $reg,<sym> (BFD_RELOC_HI16_S)
8351 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8352 If we have an addend, we always use the latter form.
8354 With 64bit address space and a usable $at we want
8355 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8356 lui $at,<sym> (BFD_RELOC_HI16_S)
8357 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8358 daddiu $at,<sym> (BFD_RELOC_LO16)
8362 If $at is already in use, we use a path which is suboptimal
8363 on superscalar processors.
8364 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8365 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
8367 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
8369 daddiu $reg,<sym> (BFD_RELOC_LO16)
8371 For GP relative symbols in 64bit address space we can use
8372 the same sequence as in 32bit address space. */
8373 if (HAVE_64BIT_SYMBOLS)
8375 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8376 && !nopic_need_relax (ep->X_add_symbol, 1))
8378 relax_start (ep->X_add_symbol);
8379 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8380 mips_gp_register, BFD_RELOC_GPREL16);
8384 if (*used_at == 0 && mips_opts.at)
8386 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8387 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
8388 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8389 BFD_RELOC_MIPS_HIGHER);
8390 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
8391 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
8392 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
8397 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
8398 macro_build (ep, "daddiu", "t,r,j", reg, reg,
8399 BFD_RELOC_MIPS_HIGHER);
8400 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8401 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
8402 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
8403 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
8406 if (mips_relax.sequence)
8411 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
8412 && !nopic_need_relax (ep->X_add_symbol, 1))
8414 relax_start (ep->X_add_symbol);
8415 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
8416 mips_gp_register, BFD_RELOC_GPREL16);
8419 macro_build_lui (ep, reg);
8420 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
8421 reg, reg, BFD_RELOC_LO16);
8422 if (mips_relax.sequence)
8426 else if (!mips_big_got)
8430 /* If this is a reference to an external symbol, we want
8431 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8433 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8435 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8436 If there is a constant, it must be added in after.
8438 If we have NewABI, we want
8439 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
8440 unless we're referencing a global symbol with a non-zero
8441 offset, in which case cst must be added separately. */
8444 if (ep->X_add_number)
8446 ex.X_add_number = ep->X_add_number;
8447 ep->X_add_number = 0;
8448 relax_start (ep->X_add_symbol);
8449 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8450 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8451 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8452 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8453 ex.X_op = O_constant;
8454 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8455 reg, reg, BFD_RELOC_LO16);
8456 ep->X_add_number = ex.X_add_number;
8459 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8460 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
8461 if (mips_relax.sequence)
8466 ex.X_add_number = ep->X_add_number;
8467 ep->X_add_number = 0;
8468 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8469 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8471 relax_start (ep->X_add_symbol);
8473 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8477 if (ex.X_add_number != 0)
8479 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8480 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8481 ex.X_op = O_constant;
8482 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
8483 reg, reg, BFD_RELOC_LO16);
8487 else if (mips_big_got)
8491 /* This is the large GOT case. If this is a reference to an
8492 external symbol, we want
8493 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8495 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
8497 Otherwise, for a reference to a local symbol in old ABI, we want
8498 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8500 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
8501 If there is a constant, it must be added in after.
8503 In the NewABI, for local symbols, with or without offsets, we want:
8504 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8505 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8509 ex.X_add_number = ep->X_add_number;
8510 ep->X_add_number = 0;
8511 relax_start (ep->X_add_symbol);
8512 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8513 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8514 reg, reg, mips_gp_register);
8515 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8516 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8517 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8518 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8519 else if (ex.X_add_number)
8521 ex.X_op = O_constant;
8522 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8526 ep->X_add_number = ex.X_add_number;
8528 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8529 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8530 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8531 BFD_RELOC_MIPS_GOT_OFST);
8536 ex.X_add_number = ep->X_add_number;
8537 ep->X_add_number = 0;
8538 relax_start (ep->X_add_symbol);
8539 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
8540 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8541 reg, reg, mips_gp_register);
8542 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
8543 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
8545 if (reg_needs_delay (mips_gp_register))
8547 /* We need a nop before loading from $gp. This special
8548 check is required because the lui which starts the main
8549 instruction stream does not refer to $gp, and so will not
8550 insert the nop which may be required. */
8551 macro_build (NULL, "nop", "");
8553 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
8554 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8556 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8560 if (ex.X_add_number != 0)
8562 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
8563 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
8564 ex.X_op = O_constant;
8565 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
8573 if (!mips_opts.at && *used_at == 1)
8574 as_bad (_("Macro used $at after \".set noat\""));
8577 /* Move the contents of register SOURCE into register DEST. */
8580 move_register (int dest, int source)
8582 /* Prefer to use a 16-bit microMIPS instruction unless the previous
8583 instruction specifically requires a 32-bit one. */
8584 if (mips_opts.micromips
8585 && !mips_opts.insn32
8586 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8587 macro_build (NULL, "move", "mp,mj", dest, source);
8589 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
8593 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
8594 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
8595 The two alternatives are:
8597 Global symbol Local sybmol
8598 ------------- ------------
8599 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
8601 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
8603 load_got_offset emits the first instruction and add_got_offset
8604 emits the second for a 16-bit offset or add_got_offset_hilo emits
8605 a sequence to add a 32-bit offset using a scratch register. */
8608 load_got_offset (int dest, expressionS *local)
8613 global.X_add_number = 0;
8615 relax_start (local->X_add_symbol);
8616 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8617 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8619 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
8620 BFD_RELOC_MIPS_GOT16, mips_gp_register);
8625 add_got_offset (int dest, expressionS *local)
8629 global.X_op = O_constant;
8630 global.X_op_symbol = NULL;
8631 global.X_add_symbol = NULL;
8632 global.X_add_number = local->X_add_number;
8634 relax_start (local->X_add_symbol);
8635 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
8636 dest, dest, BFD_RELOC_LO16);
8638 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
8643 add_got_offset_hilo (int dest, expressionS *local, int tmp)
8646 int hold_mips_optimize;
8648 global.X_op = O_constant;
8649 global.X_op_symbol = NULL;
8650 global.X_add_symbol = NULL;
8651 global.X_add_number = local->X_add_number;
8653 relax_start (local->X_add_symbol);
8654 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
8656 /* Set mips_optimize around the lui instruction to avoid
8657 inserting an unnecessary nop after the lw. */
8658 hold_mips_optimize = mips_optimize;
8660 macro_build_lui (&global, tmp);
8661 mips_optimize = hold_mips_optimize;
8662 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
8665 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
8668 /* Emit a sequence of instructions to emulate a branch likely operation.
8669 BR is an ordinary branch corresponding to one to be emulated. BRNEG
8670 is its complementing branch with the original condition negated.
8671 CALL is set if the original branch specified the link operation.
8672 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
8674 Code like this is produced in the noreorder mode:
8679 delay slot (executed only if branch taken)
8687 delay slot (executed only if branch taken)
8690 In the reorder mode the delay slot would be filled with a nop anyway,
8691 so code produced is simply:
8696 This function is used when producing code for the microMIPS ASE that
8697 does not implement branch likely instructions in hardware. */
8700 macro_build_branch_likely (const char *br, const char *brneg,
8701 int call, expressionS *ep, const char *fmt,
8702 unsigned int sreg, unsigned int treg)
8704 int noreorder = mips_opts.noreorder;
8707 gas_assert (mips_opts.micromips);
8711 micromips_label_expr (&expr1);
8712 macro_build (&expr1, brneg, fmt, sreg, treg);
8713 macro_build (NULL, "nop", "");
8714 macro_build (ep, call ? "bal" : "b", "p");
8716 /* Set to true so that append_insn adds a label. */
8717 emit_branch_likely_macro = TRUE;
8721 macro_build (ep, br, fmt, sreg, treg);
8722 macro_build (NULL, "nop", "");
8727 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
8728 the condition code tested. EP specifies the branch target. */
8731 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
8758 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
8761 /* Emit a two-argument branch macro specified by TYPE, using SREG as
8762 the register tested. EP specifies the branch target. */
8765 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
8767 const char *brneg = NULL;
8777 br = mips_opts.micromips ? "bgez" : "bgezl";
8781 gas_assert (mips_opts.micromips);
8782 br = mips_opts.insn32 ? "bgezal" : "bgezals";
8790 br = mips_opts.micromips ? "bgtz" : "bgtzl";
8797 br = mips_opts.micromips ? "blez" : "blezl";
8804 br = mips_opts.micromips ? "bltz" : "bltzl";
8808 gas_assert (mips_opts.micromips);
8809 br = mips_opts.insn32 ? "bltzal" : "bltzals";
8816 if (mips_opts.micromips && brneg)
8817 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
8819 macro_build (ep, br, "s,p", sreg);
8822 /* Emit a three-argument branch macro specified by TYPE, using SREG and
8823 TREG as the registers tested. EP specifies the branch target. */
8826 macro_build_branch_rsrt (int type, expressionS *ep,
8827 unsigned int sreg, unsigned int treg)
8829 const char *brneg = NULL;
8841 br = mips_opts.micromips ? "beq" : "beql";
8850 br = mips_opts.micromips ? "bne" : "bnel";
8856 if (mips_opts.micromips && brneg)
8857 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
8859 macro_build (ep, br, "s,t,p", sreg, treg);
8862 /* Return the high part that should be loaded in order to make the low
8863 part of VALUE accessible using an offset of OFFBITS bits. */
8866 offset_high_part (offsetT value, unsigned int offbits)
8873 bias = 1 << (offbits - 1);
8874 low_mask = bias * 2 - 1;
8875 return (value + bias) & ~low_mask;
8878 /* Return true if the value stored in offset_expr and offset_reloc
8879 fits into a signed offset of OFFBITS bits. RANGE is the maximum
8880 amount that the caller wants to add without inducing overflow
8881 and ALIGN is the known alignment of the value in bytes. */
8884 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
8888 /* Accept any relocation operator if overflow isn't a concern. */
8889 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
8892 /* These relocations are guaranteed not to overflow in correct links. */
8893 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
8894 || gprel16_reloc_p (*offset_reloc))
8897 if (offset_expr.X_op == O_constant
8898 && offset_high_part (offset_expr.X_add_number, offbits) == 0
8899 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
8906 * This routine implements the seemingly endless macro or synthesized
8907 * instructions and addressing modes in the mips assembly language. Many
8908 * of these macros are simple and are similar to each other. These could
8909 * probably be handled by some kind of table or grammar approach instead of
8910 * this verbose method. Others are not simple macros but are more like
8911 * optimizing code generation.
8912 * One interesting optimization is when several store macros appear
8913 * consecutively that would load AT with the upper half of the same address.
8914 * The ensuing load upper instructions are ommited. This implies some kind
8915 * of global optimization. We currently only optimize within a single macro.
8916 * For many of the load and store macros if the address is specified as a
8917 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
8918 * first load register 'at' with zero and use it as the base register. The
8919 * mips assembler simply uses register $zero. Just one tiny optimization
8923 macro (struct mips_cl_insn *ip, char *str)
8925 const struct mips_operand_array *operands;
8926 unsigned int breg, i;
8927 unsigned int tempreg;
8930 expressionS label_expr;
8945 bfd_boolean large_offset;
8947 int hold_mips_optimize;
8949 unsigned int op[MAX_OPERANDS];
8951 gas_assert (! mips_opts.mips16);
8953 operands = insn_operands (ip);
8954 for (i = 0; i < MAX_OPERANDS; i++)
8955 if (operands->operand[i])
8956 op[i] = insn_extract_operand (ip, operands->operand[i]);
8960 mask = ip->insn_mo->mask;
8962 label_expr.X_op = O_constant;
8963 label_expr.X_op_symbol = NULL;
8964 label_expr.X_add_symbol = NULL;
8965 label_expr.X_add_number = 0;
8967 expr1.X_op = O_constant;
8968 expr1.X_op_symbol = NULL;
8969 expr1.X_add_symbol = NULL;
8970 expr1.X_add_number = 1;
8986 if (mips_opts.micromips)
8987 micromips_label_expr (&label_expr);
8989 label_expr.X_add_number = 8;
8990 macro_build (&label_expr, "bgez", "s,p", op[1]);
8992 macro_build (NULL, "nop", "");
8994 move_register (op[0], op[1]);
8995 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
8996 if (mips_opts.micromips)
8997 micromips_add_label ();
9014 if (!mips_opts.micromips)
9016 if (imm_expr.X_op == O_constant
9017 && imm_expr.X_add_number >= -0x200
9018 && imm_expr.X_add_number < 0x200)
9020 macro_build (NULL, s, "t,r,.", op[0], op[1], imm_expr.X_add_number);
9029 if (imm_expr.X_op == O_constant
9030 && imm_expr.X_add_number >= -0x8000
9031 && imm_expr.X_add_number < 0x8000)
9033 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
9038 load_register (AT, &imm_expr, dbl);
9039 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9058 if (imm_expr.X_op == O_constant
9059 && imm_expr.X_add_number >= 0
9060 && imm_expr.X_add_number < 0x10000)
9062 if (mask != M_NOR_I)
9063 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
9066 macro_build (&imm_expr, "ori", "t,r,i",
9067 op[0], op[1], BFD_RELOC_LO16);
9068 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
9074 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
9075 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
9079 switch (imm_expr.X_add_number)
9082 macro_build (NULL, "nop", "");
9085 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
9089 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
9090 (int) imm_expr.X_add_number);
9093 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
9094 (unsigned long) imm_expr.X_add_number);
9103 gas_assert (mips_opts.micromips);
9104 macro_build_branch_ccl (mask, &offset_expr,
9105 EXTRACT_OPERAND (1, BCC, *ip));
9112 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9118 load_register (op[1], &imm_expr, HAVE_64BIT_GPRS);
9123 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
9130 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
9131 else if (op[0] == 0)
9132 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
9136 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9137 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9138 &offset_expr, AT, ZERO);
9148 macro_build_branch_rs (mask, &offset_expr, op[0]);
9154 /* Check for > max integer. */
9155 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9158 /* Result is always false. */
9160 macro_build (NULL, "nop", "");
9162 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
9165 if (imm_expr.X_op != O_constant)
9166 as_bad (_("Unsupported large constant"));
9167 ++imm_expr.X_add_number;
9171 if (mask == M_BGEL_I)
9173 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9175 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
9176 &offset_expr, op[0]);
9179 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9181 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
9182 &offset_expr, op[0]);
9185 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
9188 /* result is always true */
9189 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
9190 macro_build (&offset_expr, "b", "p");
9195 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9196 &offset_expr, AT, ZERO);
9204 else if (op[0] == 0)
9205 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9206 &offset_expr, ZERO, op[1]);
9210 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9211 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9212 &offset_expr, AT, ZERO);
9221 && imm_expr.X_op == O_constant
9222 && imm_expr.X_add_number == -1))
9224 if (imm_expr.X_op != O_constant)
9225 as_bad (_("Unsupported large constant"));
9226 ++imm_expr.X_add_number;
9230 if (mask == M_BGEUL_I)
9232 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9234 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9235 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9236 &offset_expr, op[0], ZERO);
9241 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9242 &offset_expr, AT, ZERO);
9250 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
9251 else if (op[0] == 0)
9252 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
9256 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9257 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9258 &offset_expr, AT, ZERO);
9266 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9267 &offset_expr, op[0], ZERO);
9268 else if (op[0] == 0)
9273 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9274 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9275 &offset_expr, AT, ZERO);
9283 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9284 else if (op[0] == 0)
9285 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
9289 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
9290 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9291 &offset_expr, AT, ZERO);
9298 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
9300 if (imm_expr.X_op != O_constant)
9301 as_bad (_("Unsupported large constant"));
9302 ++imm_expr.X_add_number;
9306 if (mask == M_BLTL_I)
9308 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9309 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9310 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9311 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
9316 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9317 &offset_expr, AT, ZERO);
9325 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9326 &offset_expr, op[0], ZERO);
9327 else if (op[0] == 0)
9332 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
9333 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9334 &offset_expr, AT, ZERO);
9343 && imm_expr.X_op == O_constant
9344 && imm_expr.X_add_number == -1))
9346 if (imm_expr.X_op != O_constant)
9347 as_bad (_("Unsupported large constant"));
9348 ++imm_expr.X_add_number;
9352 if (mask == M_BLTUL_I)
9354 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9356 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9357 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
9358 &offset_expr, op[0], ZERO);
9363 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9364 &offset_expr, AT, ZERO);
9372 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
9373 else if (op[0] == 0)
9374 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
9378 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
9379 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9380 &offset_expr, AT, ZERO);
9389 else if (op[0] == 0)
9390 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9391 &offset_expr, ZERO, op[1]);
9395 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
9396 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
9397 &offset_expr, AT, ZERO);
9403 /* Use unsigned arithmetic. */
9407 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9409 as_bad (_("Unsupported large constant"));
9414 pos = imm_expr.X_add_number;
9415 size = imm2_expr.X_add_number;
9420 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9423 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9425 report_bad_field (pos, size);
9429 if (size <= 32 && pos < 32)
9434 else if (size <= 32)
9444 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9451 /* Use unsigned arithmetic. */
9455 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
9457 as_bad (_("Unsupported large constant"));
9462 pos = imm_expr.X_add_number;
9463 size = imm2_expr.X_add_number;
9468 report_bad_range (ip, 3, pos, 0, 63, FALSE);
9471 if (size == 0 || size > 64 || (pos + size - 1) > 63)
9473 report_bad_field (pos, size);
9477 if (pos < 32 && (pos + size - 1) < 32)
9492 macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos,
9493 (int) (pos + size - 1));
9509 as_warn (_("Divide by zero."));
9511 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9513 macro_build (NULL, "break", BRK_FMT, 7);
9520 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9521 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9525 if (mips_opts.micromips)
9526 micromips_label_expr (&label_expr);
9528 label_expr.X_add_number = 8;
9529 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9530 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
9531 macro_build (NULL, "break", BRK_FMT, 7);
9532 if (mips_opts.micromips)
9533 micromips_add_label ();
9535 expr1.X_add_number = -1;
9537 load_register (AT, &expr1, dbl);
9538 if (mips_opts.micromips)
9539 micromips_label_expr (&label_expr);
9541 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
9542 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
9545 expr1.X_add_number = 1;
9546 load_register (AT, &expr1, dbl);
9547 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
9551 expr1.X_add_number = 0x80000000;
9552 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
9556 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
9557 /* We want to close the noreorder block as soon as possible, so
9558 that later insns are available for delay slot filling. */
9563 if (mips_opts.micromips)
9564 micromips_label_expr (&label_expr);
9566 label_expr.X_add_number = 8;
9567 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
9568 macro_build (NULL, "nop", "");
9570 /* We want to close the noreorder block as soon as possible, so
9571 that later insns are available for delay slot filling. */
9574 macro_build (NULL, "break", BRK_FMT, 6);
9576 if (mips_opts.micromips)
9577 micromips_add_label ();
9578 macro_build (NULL, s, MFHL_FMT, op[0]);
9617 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
9619 as_warn (_("Divide by zero."));
9621 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
9623 macro_build (NULL, "break", BRK_FMT, 7);
9626 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
9628 if (strcmp (s2, "mflo") == 0)
9629 move_register (op[0], op[1]);
9631 move_register (op[0], ZERO);
9634 if (imm_expr.X_op == O_constant
9635 && imm_expr.X_add_number == -1
9636 && s[strlen (s) - 1] != 'u')
9638 if (strcmp (s2, "mflo") == 0)
9639 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
9641 move_register (op[0], ZERO);
9646 load_register (AT, &imm_expr, dbl);
9647 macro_build (NULL, s, "z,s,t", op[1], AT);
9648 macro_build (NULL, s2, MFHL_FMT, op[0]);
9670 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
9671 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9672 /* We want to close the noreorder block as soon as possible, so
9673 that later insns are available for delay slot filling. */
9678 if (mips_opts.micromips)
9679 micromips_label_expr (&label_expr);
9681 label_expr.X_add_number = 8;
9682 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
9683 macro_build (NULL, s, "z,s,t", op[1], op[2]);
9685 /* We want to close the noreorder block as soon as possible, so
9686 that later insns are available for delay slot filling. */
9688 macro_build (NULL, "break", BRK_FMT, 7);
9689 if (mips_opts.micromips)
9690 micromips_add_label ();
9692 macro_build (NULL, s2, MFHL_FMT, op[0]);
9704 /* Load the address of a symbol into a register. If breg is not
9705 zero, we then add a base register to it. */
9708 if (dbl && HAVE_32BIT_GPRS)
9709 as_warn (_("dla used to load 32-bit register"));
9711 if (!dbl && HAVE_64BIT_OBJECTS)
9712 as_warn (_("la used to load 64-bit address"));
9714 if (small_offset_p (0, align, 16))
9716 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
9717 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
9721 if (mips_opts.at && (op[0] == breg))
9729 if (offset_expr.X_op != O_symbol
9730 && offset_expr.X_op != O_constant)
9732 as_bad (_("Expression too complex"));
9733 offset_expr.X_op = O_constant;
9736 if (offset_expr.X_op == O_constant)
9737 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
9738 else if (mips_pic == NO_PIC)
9740 /* If this is a reference to a GP relative symbol, we want
9741 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
9743 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
9744 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9745 If we have a constant, we need two instructions anyhow,
9746 so we may as well always use the latter form.
9748 With 64bit address space and a usable $at we want
9749 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9750 lui $at,<sym> (BFD_RELOC_HI16_S)
9751 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9752 daddiu $at,<sym> (BFD_RELOC_LO16)
9754 daddu $tempreg,$tempreg,$at
9756 If $at is already in use, we use a path which is suboptimal
9757 on superscalar processors.
9758 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9759 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
9761 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
9763 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
9765 For GP relative symbols in 64bit address space we can use
9766 the same sequence as in 32bit address space. */
9767 if (HAVE_64BIT_SYMBOLS)
9769 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9770 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9772 relax_start (offset_expr.X_add_symbol);
9773 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9774 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9778 if (used_at == 0 && mips_opts.at)
9780 macro_build (&offset_expr, "lui", LUI_FMT,
9781 tempreg, BFD_RELOC_MIPS_HIGHEST);
9782 macro_build (&offset_expr, "lui", LUI_FMT,
9783 AT, BFD_RELOC_HI16_S);
9784 macro_build (&offset_expr, "daddiu", "t,r,j",
9785 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9786 macro_build (&offset_expr, "daddiu", "t,r,j",
9787 AT, AT, BFD_RELOC_LO16);
9788 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9789 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9794 macro_build (&offset_expr, "lui", LUI_FMT,
9795 tempreg, BFD_RELOC_MIPS_HIGHEST);
9796 macro_build (&offset_expr, "daddiu", "t,r,j",
9797 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
9798 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9799 macro_build (&offset_expr, "daddiu", "t,r,j",
9800 tempreg, tempreg, BFD_RELOC_HI16_S);
9801 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9802 macro_build (&offset_expr, "daddiu", "t,r,j",
9803 tempreg, tempreg, BFD_RELOC_LO16);
9806 if (mips_relax.sequence)
9811 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9812 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9814 relax_start (offset_expr.X_add_symbol);
9815 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9816 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
9819 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9820 as_bad (_("Offset too large"));
9821 macro_build_lui (&offset_expr, tempreg);
9822 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9823 tempreg, tempreg, BFD_RELOC_LO16);
9824 if (mips_relax.sequence)
9828 else if (!mips_big_got && !HAVE_NEWABI)
9830 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9832 /* If this is a reference to an external symbol, and there
9833 is no constant, we want
9834 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9835 or for lca or if tempreg is PIC_CALL_REG
9836 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9837 For a local symbol, we want
9838 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9840 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9842 If we have a small constant, and this is a reference to
9843 an external symbol, we want
9844 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9846 addiu $tempreg,$tempreg,<constant>
9847 For a local symbol, we want the same instruction
9848 sequence, but we output a BFD_RELOC_LO16 reloc on the
9851 If we have a large constant, and this is a reference to
9852 an external symbol, we want
9853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9854 lui $at,<hiconstant>
9855 addiu $at,$at,<loconstant>
9856 addu $tempreg,$tempreg,$at
9857 For a local symbol, we want the same instruction
9858 sequence, but we output a BFD_RELOC_LO16 reloc on the
9862 if (offset_expr.X_add_number == 0)
9864 if (mips_pic == SVR4_PIC
9866 && (call || tempreg == PIC_CALL_REG))
9867 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
9869 relax_start (offset_expr.X_add_symbol);
9870 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9871 lw_reloc_type, mips_gp_register);
9874 /* We're going to put in an addu instruction using
9875 tempreg, so we may as well insert the nop right
9880 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9881 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
9883 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
9884 tempreg, tempreg, BFD_RELOC_LO16);
9886 /* FIXME: If breg == 0, and the next instruction uses
9887 $tempreg, then if this variant case is used an extra
9888 nop will be generated. */
9890 else if (offset_expr.X_add_number >= -0x8000
9891 && offset_expr.X_add_number < 0x8000)
9893 load_got_offset (tempreg, &offset_expr);
9895 add_got_offset (tempreg, &offset_expr);
9899 expr1.X_add_number = offset_expr.X_add_number;
9900 offset_expr.X_add_number =
9901 SEXT_16BIT (offset_expr.X_add_number);
9902 load_got_offset (tempreg, &offset_expr);
9903 offset_expr.X_add_number = expr1.X_add_number;
9904 /* If we are going to add in a base register, and the
9905 target register and the base register are the same,
9906 then we are using AT as a temporary register. Since
9907 we want to load the constant into AT, we add our
9908 current AT (from the global offset table) and the
9909 register into the register now, and pretend we were
9910 not using a base register. */
9914 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9919 add_got_offset_hilo (tempreg, &offset_expr, AT);
9923 else if (!mips_big_got && HAVE_NEWABI)
9925 int add_breg_early = 0;
9927 /* If this is a reference to an external, and there is no
9928 constant, or local symbol (*), with or without a
9930 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9931 or for lca or if tempreg is PIC_CALL_REG
9932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
9934 If we have a small constant, and this is a reference to
9935 an external symbol, we want
9936 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9937 addiu $tempreg,$tempreg,<constant>
9939 If we have a large constant, and this is a reference to
9940 an external symbol, we want
9941 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9942 lui $at,<hiconstant>
9943 addiu $at,$at,<loconstant>
9944 addu $tempreg,$tempreg,$at
9946 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
9947 local symbols, even though it introduces an additional
9950 if (offset_expr.X_add_number)
9952 expr1.X_add_number = offset_expr.X_add_number;
9953 offset_expr.X_add_number = 0;
9955 relax_start (offset_expr.X_add_symbol);
9956 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9957 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9959 if (expr1.X_add_number >= -0x8000
9960 && expr1.X_add_number < 0x8000)
9962 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
9963 tempreg, tempreg, BFD_RELOC_LO16);
9965 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
9969 /* If we are going to add in a base register, and the
9970 target register and the base register are the same,
9971 then we are using AT as a temporary register. Since
9972 we want to load the constant into AT, we add our
9973 current AT (from the global offset table) and the
9974 register into the register now, and pretend we were
9975 not using a base register. */
9980 gas_assert (tempreg == AT);
9981 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9987 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
9988 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9994 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
9997 offset_expr.X_add_number = expr1.X_add_number;
9999 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10000 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10001 if (add_breg_early)
10003 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10004 op[0], tempreg, breg);
10010 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
10012 relax_start (offset_expr.X_add_symbol);
10013 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10014 BFD_RELOC_MIPS_CALL16, mips_gp_register);
10016 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10017 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10022 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10023 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
10026 else if (mips_big_got && !HAVE_NEWABI)
10029 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10030 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10031 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
10033 /* This is the large GOT case. If this is a reference to an
10034 external symbol, and there is no constant, we want
10035 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10036 addu $tempreg,$tempreg,$gp
10037 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10038 or for lca or if tempreg is PIC_CALL_REG
10039 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10040 addu $tempreg,$tempreg,$gp
10041 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10042 For a local symbol, we want
10043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10045 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
10047 If we have a small constant, and this is a reference to
10048 an external symbol, we want
10049 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10050 addu $tempreg,$tempreg,$gp
10051 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10053 addiu $tempreg,$tempreg,<constant>
10054 For a local symbol, we want
10055 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10057 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
10059 If we have a large constant, and this is a reference to
10060 an external symbol, we want
10061 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10062 addu $tempreg,$tempreg,$gp
10063 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10064 lui $at,<hiconstant>
10065 addiu $at,$at,<loconstant>
10066 addu $tempreg,$tempreg,$at
10067 For a local symbol, we want
10068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10069 lui $at,<hiconstant>
10070 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
10071 addu $tempreg,$tempreg,$at
10074 expr1.X_add_number = offset_expr.X_add_number;
10075 offset_expr.X_add_number = 0;
10076 relax_start (offset_expr.X_add_symbol);
10077 gpdelay = reg_needs_delay (mips_gp_register);
10078 if (expr1.X_add_number == 0 && breg == 0
10079 && (call || tempreg == PIC_CALL_REG))
10081 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10082 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10084 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10085 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10086 tempreg, tempreg, mips_gp_register);
10087 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10088 tempreg, lw_reloc_type, tempreg);
10089 if (expr1.X_add_number == 0)
10093 /* We're going to put in an addu instruction using
10094 tempreg, so we may as well insert the nop right
10099 else if (expr1.X_add_number >= -0x8000
10100 && expr1.X_add_number < 0x8000)
10103 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10104 tempreg, tempreg, BFD_RELOC_LO16);
10110 /* If we are going to add in a base register, and the
10111 target register and the base register are the same,
10112 then we are using AT as a temporary register. Since
10113 we want to load the constant into AT, we add our
10114 current AT (from the global offset table) and the
10115 register into the register now, and pretend we were
10116 not using a base register. */
10121 gas_assert (tempreg == AT);
10123 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10128 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10129 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10133 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
10138 /* This is needed because this instruction uses $gp, but
10139 the first instruction on the main stream does not. */
10140 macro_build (NULL, "nop", "");
10143 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10144 local_reloc_type, mips_gp_register);
10145 if (expr1.X_add_number >= -0x8000
10146 && expr1.X_add_number < 0x8000)
10149 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10150 tempreg, tempreg, BFD_RELOC_LO16);
10151 /* FIXME: If add_number is 0, and there was no base
10152 register, the external symbol case ended with a load,
10153 so if the symbol turns out to not be external, and
10154 the next instruction uses tempreg, an unnecessary nop
10155 will be inserted. */
10161 /* We must add in the base register now, as in the
10162 external symbol case. */
10163 gas_assert (tempreg == AT);
10165 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10168 /* We set breg to 0 because we have arranged to add
10169 it in in both cases. */
10173 macro_build_lui (&expr1, AT);
10174 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10175 AT, AT, BFD_RELOC_LO16);
10176 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10177 tempreg, tempreg, AT);
10182 else if (mips_big_got && HAVE_NEWABI)
10184 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
10185 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
10186 int add_breg_early = 0;
10188 /* This is the large GOT case. If this is a reference to an
10189 external symbol, and there is no constant, we want
10190 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10191 add $tempreg,$tempreg,$gp
10192 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10193 or for lca or if tempreg is PIC_CALL_REG
10194 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10195 add $tempreg,$tempreg,$gp
10196 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
10198 If we have a small constant, and this is a reference to
10199 an external symbol, we want
10200 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10201 add $tempreg,$tempreg,$gp
10202 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10203 addi $tempreg,$tempreg,<constant>
10205 If we have a large constant, and this is a reference to
10206 an external symbol, we want
10207 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
10208 addu $tempreg,$tempreg,$gp
10209 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
10210 lui $at,<hiconstant>
10211 addi $at,$at,<loconstant>
10212 add $tempreg,$tempreg,$at
10214 If we have NewABI, and we know it's a local symbol, we want
10215 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
10216 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
10217 otherwise we have to resort to GOT_HI16/GOT_LO16. */
10219 relax_start (offset_expr.X_add_symbol);
10221 expr1.X_add_number = offset_expr.X_add_number;
10222 offset_expr.X_add_number = 0;
10224 if (expr1.X_add_number == 0 && breg == 0
10225 && (call || tempreg == PIC_CALL_REG))
10227 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
10228 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
10230 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
10231 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10232 tempreg, tempreg, mips_gp_register);
10233 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10234 tempreg, lw_reloc_type, tempreg);
10236 if (expr1.X_add_number == 0)
10238 else if (expr1.X_add_number >= -0x8000
10239 && expr1.X_add_number < 0x8000)
10241 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
10242 tempreg, tempreg, BFD_RELOC_LO16);
10244 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
10248 /* If we are going to add in a base register, and the
10249 target register and the base register are the same,
10250 then we are using AT as a temporary register. Since
10251 we want to load the constant into AT, we add our
10252 current AT (from the global offset table) and the
10253 register into the register now, and pretend we were
10254 not using a base register. */
10259 gas_assert (tempreg == AT);
10260 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10263 add_breg_early = 1;
10266 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
10267 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
10272 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
10275 offset_expr.X_add_number = expr1.X_add_number;
10276 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
10277 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
10278 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
10279 tempreg, BFD_RELOC_MIPS_GOT_OFST);
10280 if (add_breg_early)
10282 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10283 op[0], tempreg, breg);
10293 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
10297 gas_assert (!mips_opts.micromips);
10298 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
10302 gas_assert (!mips_opts.micromips);
10303 macro_build (NULL, "c2", "C", 0x02);
10307 gas_assert (!mips_opts.micromips);
10308 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
10312 gas_assert (!mips_opts.micromips);
10313 macro_build (NULL, "c2", "C", 3);
10317 gas_assert (!mips_opts.micromips);
10318 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
10322 /* The j instruction may not be used in PIC code, since it
10323 requires an absolute address. We convert it to a b
10325 if (mips_pic == NO_PIC)
10326 macro_build (&offset_expr, "j", "a");
10328 macro_build (&offset_expr, "b", "p");
10331 /* The jal instructions must be handled as macros because when
10332 generating PIC code they expand to multi-instruction
10333 sequences. Normally they are simple instructions. */
10337 /* Fall through. */
10339 gas_assert (mips_opts.micromips);
10340 if (mips_opts.insn32)
10342 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10350 /* Fall through. */
10353 if (mips_pic == NO_PIC)
10355 s = jals ? "jalrs" : "jalr";
10356 if (mips_opts.micromips
10357 && !mips_opts.insn32
10359 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10360 macro_build (NULL, s, "mj", op[1]);
10362 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10366 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
10367 && mips_cprestore_offset >= 0);
10369 if (op[1] != PIC_CALL_REG)
10370 as_warn (_("MIPS PIC call to register other than $25"));
10372 s = ((mips_opts.micromips
10373 && !mips_opts.insn32
10374 && (!mips_opts.noreorder || cprestore))
10375 ? "jalrs" : "jalr");
10376 if (mips_opts.micromips
10377 && !mips_opts.insn32
10379 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10380 macro_build (NULL, s, "mj", op[1]);
10382 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
10383 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
10385 if (mips_cprestore_offset < 0)
10386 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10389 if (!mips_frame_reg_valid)
10391 as_warn (_("No .frame pseudo-op used in PIC code"));
10392 /* Quiet this warning. */
10393 mips_frame_reg_valid = 1;
10395 if (!mips_cprestore_valid)
10397 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10398 /* Quiet this warning. */
10399 mips_cprestore_valid = 1;
10401 if (mips_opts.noreorder)
10402 macro_build (NULL, "nop", "");
10403 expr1.X_add_number = mips_cprestore_offset;
10404 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10407 HAVE_64BIT_ADDRESSES);
10415 gas_assert (mips_opts.micromips);
10416 if (mips_opts.insn32)
10418 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
10422 /* Fall through. */
10424 if (mips_pic == NO_PIC)
10425 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
10426 else if (mips_pic == SVR4_PIC)
10428 /* If this is a reference to an external symbol, and we are
10429 using a small GOT, we want
10430 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
10434 lw $gp,cprestore($sp)
10435 The cprestore value is set using the .cprestore
10436 pseudo-op. If we are using a big GOT, we want
10437 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
10439 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
10443 lw $gp,cprestore($sp)
10444 If the symbol is not external, we want
10445 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
10447 addiu $25,$25,<sym> (BFD_RELOC_LO16)
10450 lw $gp,cprestore($sp)
10452 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
10453 sequences above, minus nops, unless the symbol is local,
10454 which enables us to use GOT_PAGE/GOT_OFST (big got) or
10460 relax_start (offset_expr.X_add_symbol);
10461 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10462 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10465 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10466 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
10472 relax_start (offset_expr.X_add_symbol);
10473 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10474 BFD_RELOC_MIPS_CALL_HI16);
10475 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10476 PIC_CALL_REG, mips_gp_register);
10477 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10478 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10481 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10482 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
10484 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10485 PIC_CALL_REG, PIC_CALL_REG,
10486 BFD_RELOC_MIPS_GOT_OFST);
10490 macro_build_jalr (&offset_expr, 0);
10494 relax_start (offset_expr.X_add_symbol);
10497 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10498 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
10507 gpdelay = reg_needs_delay (mips_gp_register);
10508 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
10509 BFD_RELOC_MIPS_CALL_HI16);
10510 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
10511 PIC_CALL_REG, mips_gp_register);
10512 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10513 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
10518 macro_build (NULL, "nop", "");
10520 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
10521 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
10524 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10525 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
10527 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
10529 if (mips_cprestore_offset < 0)
10530 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10533 if (!mips_frame_reg_valid)
10535 as_warn (_("No .frame pseudo-op used in PIC code"));
10536 /* Quiet this warning. */
10537 mips_frame_reg_valid = 1;
10539 if (!mips_cprestore_valid)
10541 as_warn (_("No .cprestore pseudo-op used in PIC code"));
10542 /* Quiet this warning. */
10543 mips_cprestore_valid = 1;
10545 if (mips_opts.noreorder)
10546 macro_build (NULL, "nop", "");
10547 expr1.X_add_number = mips_cprestore_offset;
10548 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
10551 HAVE_64BIT_ADDRESSES);
10555 else if (mips_pic == VXWORKS_PIC)
10556 as_bad (_("Non-PIC jump used in PIC library"));
10663 gas_assert (!mips_opts.micromips);
10666 /* Itbl support may require additional care here. */
10672 /* Itbl support may require additional care here. */
10678 offbits = (mips_opts.micromips ? 12 : 16);
10679 /* Itbl support may require additional care here. */
10683 gas_assert (!mips_opts.micromips);
10686 /* Itbl support may require additional care here. */
10692 offbits = (mips_opts.micromips ? 12 : 16);
10697 offbits = (mips_opts.micromips ? 12 : 16);
10702 /* Itbl support may require additional care here. */
10708 offbits = (mips_opts.micromips ? 12 : 16);
10709 /* Itbl support may require additional care here. */
10715 /* Itbl support may require additional care here. */
10721 /* Itbl support may require additional care here. */
10727 offbits = (mips_opts.micromips ? 12 : 16);
10732 offbits = (mips_opts.micromips ? 12 : 16);
10737 offbits = (mips_opts.micromips ? 12 : 16);
10742 offbits = (mips_opts.micromips ? 12 : 16);
10747 offbits = (mips_opts.micromips ? 12 : 16);
10750 gas_assert (mips_opts.micromips);
10757 gas_assert (mips_opts.micromips);
10764 gas_assert (mips_opts.micromips);
10770 gas_assert (mips_opts.micromips);
10777 /* We don't want to use $0 as tempreg. */
10778 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
10781 tempreg = op[0] + lp;
10797 gas_assert (!mips_opts.micromips);
10800 /* Itbl support may require additional care here. */
10806 /* Itbl support may require additional care here. */
10812 offbits = (mips_opts.micromips ? 12 : 16);
10813 /* Itbl support may require additional care here. */
10817 gas_assert (!mips_opts.micromips);
10820 /* Itbl support may require additional care here. */
10826 offbits = (mips_opts.micromips ? 12 : 16);
10831 offbits = (mips_opts.micromips ? 12 : 16);
10836 offbits = (mips_opts.micromips ? 12 : 16);
10841 offbits = (mips_opts.micromips ? 12 : 16);
10845 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
10846 offbits = (mips_opts.micromips ? 12 : 16);
10855 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
10856 offbits = (mips_opts.micromips ? 12 : 16);
10867 /* Itbl support may require additional care here. */
10872 offbits = (mips_opts.micromips ? 12 : 16);
10873 /* Itbl support may require additional care here. */
10879 /* Itbl support may require additional care here. */
10883 gas_assert (!mips_opts.micromips);
10886 /* Itbl support may require additional care here. */
10892 offbits = (mips_opts.micromips ? 12 : 16);
10897 offbits = (mips_opts.micromips ? 12 : 16);
10900 gas_assert (mips_opts.micromips);
10906 gas_assert (mips_opts.micromips);
10912 gas_assert (mips_opts.micromips);
10918 gas_assert (mips_opts.micromips);
10927 if (small_offset_p (0, align, 16))
10929 /* The first case exists for M_LD_AB and M_SD_AB, which are
10930 macros for o32 but which should act like normal instructions
10933 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
10934 offset_reloc[1], offset_reloc[2], breg);
10935 else if (small_offset_p (0, align, offbits))
10938 macro_build (NULL, s, fmt, op[0], breg);
10940 macro_build (NULL, s, fmt, op[0],
10941 (int) offset_expr.X_add_number, breg);
10947 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
10948 tempreg, breg, -1, offset_reloc[0],
10949 offset_reloc[1], offset_reloc[2]);
10951 macro_build (NULL, s, fmt, op[0], tempreg);
10953 macro_build (NULL, s, fmt, op[0], 0, tempreg);
10961 if (offset_expr.X_op != O_constant
10962 && offset_expr.X_op != O_symbol)
10964 as_bad (_("Expression too complex"));
10965 offset_expr.X_op = O_constant;
10968 if (HAVE_32BIT_ADDRESSES
10969 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
10973 sprintf_vma (value, offset_expr.X_add_number);
10974 as_bad (_("Number (0x%s) larger than 32 bits"), value);
10977 /* A constant expression in PIC code can be handled just as it
10978 is in non PIC code. */
10979 if (offset_expr.X_op == O_constant)
10981 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
10982 offbits == 0 ? 16 : offbits);
10983 offset_expr.X_add_number -= expr1.X_add_number;
10985 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
10987 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10988 tempreg, tempreg, breg);
10991 if (offset_expr.X_add_number != 0)
10992 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
10993 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
10994 macro_build (NULL, s, fmt, op[0], tempreg);
10996 else if (offbits == 16)
10997 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
10999 macro_build (NULL, s, fmt, op[0],
11000 (int) offset_expr.X_add_number, tempreg);
11002 else if (offbits != 16)
11004 /* The offset field is too narrow to be used for a low-part
11005 relocation, so load the whole address into the auxillary
11007 load_address (tempreg, &offset_expr, &used_at);
11009 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11010 tempreg, tempreg, breg);
11012 macro_build (NULL, s, fmt, op[0], tempreg);
11014 macro_build (NULL, s, fmt, op[0], 0, tempreg);
11016 else if (mips_pic == NO_PIC)
11018 /* If this is a reference to a GP relative symbol, and there
11019 is no base register, we want
11020 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11021 Otherwise, if there is no base register, we want
11022 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11023 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11024 If we have a constant, we need two instructions anyhow,
11025 so we always use the latter form.
11027 If we have a base register, and this is a reference to a
11028 GP relative symbol, we want
11029 addu $tempreg,$breg,$gp
11030 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
11032 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11033 addu $tempreg,$tempreg,$breg
11034 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11035 With a constant we always use the latter case.
11037 With 64bit address space and no base register and $at usable,
11039 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11040 lui $at,<sym> (BFD_RELOC_HI16_S)
11041 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11044 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11045 If we have a base register, we want
11046 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11047 lui $at,<sym> (BFD_RELOC_HI16_S)
11048 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11052 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11054 Without $at we can't generate the optimal path for superscalar
11055 processors here since this would require two temporary registers.
11056 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11057 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11059 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11061 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11062 If we have a base register, we want
11063 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11064 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11066 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11068 daddu $tempreg,$tempreg,$breg
11069 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
11071 For GP relative symbols in 64bit address space we can use
11072 the same sequence as in 32bit address space. */
11073 if (HAVE_64BIT_SYMBOLS)
11075 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11076 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11078 relax_start (offset_expr.X_add_symbol);
11081 macro_build (&offset_expr, s, fmt, op[0],
11082 BFD_RELOC_GPREL16, mips_gp_register);
11086 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11087 tempreg, breg, mips_gp_register);
11088 macro_build (&offset_expr, s, fmt, op[0],
11089 BFD_RELOC_GPREL16, tempreg);
11094 if (used_at == 0 && mips_opts.at)
11096 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11097 BFD_RELOC_MIPS_HIGHEST);
11098 macro_build (&offset_expr, "lui", LUI_FMT, AT,
11100 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11101 tempreg, BFD_RELOC_MIPS_HIGHER);
11103 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
11104 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11105 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11106 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
11112 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11113 BFD_RELOC_MIPS_HIGHEST);
11114 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11115 tempreg, BFD_RELOC_MIPS_HIGHER);
11116 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11117 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
11118 tempreg, BFD_RELOC_HI16_S);
11119 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11121 macro_build (NULL, "daddu", "d,v,t",
11122 tempreg, tempreg, breg);
11123 macro_build (&offset_expr, s, fmt, op[0],
11124 BFD_RELOC_LO16, tempreg);
11127 if (mips_relax.sequence)
11134 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11135 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11137 relax_start (offset_expr.X_add_symbol);
11138 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
11142 macro_build_lui (&offset_expr, tempreg);
11143 macro_build (&offset_expr, s, fmt, op[0],
11144 BFD_RELOC_LO16, tempreg);
11145 if (mips_relax.sequence)
11150 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11151 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11153 relax_start (offset_expr.X_add_symbol);
11154 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11155 tempreg, breg, mips_gp_register);
11156 macro_build (&offset_expr, s, fmt, op[0],
11157 BFD_RELOC_GPREL16, tempreg);
11160 macro_build_lui (&offset_expr, tempreg);
11161 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11162 tempreg, tempreg, breg);
11163 macro_build (&offset_expr, s, fmt, op[0],
11164 BFD_RELOC_LO16, tempreg);
11165 if (mips_relax.sequence)
11169 else if (!mips_big_got)
11171 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11173 /* If this is a reference to an external symbol, we want
11174 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11176 <op> op[0],0($tempreg)
11178 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11180 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11181 <op> op[0],0($tempreg)
11183 For NewABI, we want
11184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11185 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
11187 If there is a base register, we add it to $tempreg before
11188 the <op>. If there is a constant, we stick it in the
11189 <op> instruction. We don't handle constants larger than
11190 16 bits, because we have no way to load the upper 16 bits
11191 (actually, we could handle them for the subset of cases
11192 in which we are not using $at). */
11193 gas_assert (offset_expr.X_op == O_symbol);
11196 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11197 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11199 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11200 tempreg, tempreg, breg);
11201 macro_build (&offset_expr, s, fmt, op[0],
11202 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11205 expr1.X_add_number = offset_expr.X_add_number;
11206 offset_expr.X_add_number = 0;
11207 if (expr1.X_add_number < -0x8000
11208 || expr1.X_add_number >= 0x8000)
11209 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11210 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11211 lw_reloc_type, mips_gp_register);
11213 relax_start (offset_expr.X_add_symbol);
11215 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11216 tempreg, BFD_RELOC_LO16);
11219 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11220 tempreg, tempreg, breg);
11221 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11223 else if (mips_big_got && !HAVE_NEWABI)
11227 /* If this is a reference to an external symbol, we want
11228 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11229 addu $tempreg,$tempreg,$gp
11230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11231 <op> op[0],0($tempreg)
11233 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11235 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11236 <op> op[0],0($tempreg)
11237 If there is a base register, we add it to $tempreg before
11238 the <op>. If there is a constant, we stick it in the
11239 <op> instruction. We don't handle constants larger than
11240 16 bits, because we have no way to load the upper 16 bits
11241 (actually, we could handle them for the subset of cases
11242 in which we are not using $at). */
11243 gas_assert (offset_expr.X_op == O_symbol);
11244 expr1.X_add_number = offset_expr.X_add_number;
11245 offset_expr.X_add_number = 0;
11246 if (expr1.X_add_number < -0x8000
11247 || expr1.X_add_number >= 0x8000)
11248 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11249 gpdelay = reg_needs_delay (mips_gp_register);
11250 relax_start (offset_expr.X_add_symbol);
11251 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11252 BFD_RELOC_MIPS_GOT_HI16);
11253 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11255 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11256 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11259 macro_build (NULL, "nop", "");
11260 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11261 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11263 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11264 tempreg, BFD_RELOC_LO16);
11268 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11269 tempreg, tempreg, breg);
11270 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11272 else if (mips_big_got && HAVE_NEWABI)
11274 /* If this is a reference to an external symbol, we want
11275 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11276 add $tempreg,$tempreg,$gp
11277 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11278 <op> op[0],<ofst>($tempreg)
11279 Otherwise, for local symbols, we want:
11280 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11281 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
11282 gas_assert (offset_expr.X_op == O_symbol);
11283 expr1.X_add_number = offset_expr.X_add_number;
11284 offset_expr.X_add_number = 0;
11285 if (expr1.X_add_number < -0x8000
11286 || expr1.X_add_number >= 0x8000)
11287 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11288 relax_start (offset_expr.X_add_symbol);
11289 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
11290 BFD_RELOC_MIPS_GOT_HI16);
11291 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
11293 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11294 BFD_RELOC_MIPS_GOT_LO16, tempreg);
11296 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11297 tempreg, tempreg, breg);
11298 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
11301 offset_expr.X_add_number = expr1.X_add_number;
11302 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11303 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11305 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11306 tempreg, tempreg, breg);
11307 macro_build (&offset_expr, s, fmt, op[0],
11308 BFD_RELOC_MIPS_GOT_OFST, tempreg);
11317 gas_assert (mips_opts.micromips);
11318 gas_assert (mips_opts.insn32);
11319 start_noreorder ();
11320 macro_build (NULL, "jr", "s", RA);
11321 expr1.X_add_number = op[0] << 2;
11322 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
11327 gas_assert (mips_opts.micromips);
11328 gas_assert (mips_opts.insn32);
11329 macro_build (NULL, "jr", "s", op[0]);
11330 if (mips_opts.noreorder)
11331 macro_build (NULL, "nop", "");
11336 load_register (op[0], &imm_expr, 0);
11340 load_register (op[0], &imm_expr, 1);
11344 if (imm_expr.X_op == O_constant)
11347 load_register (AT, &imm_expr, 0);
11348 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11353 gas_assert (offset_expr.X_op == O_symbol
11354 && strcmp (segment_name (S_GET_SEGMENT
11355 (offset_expr.X_add_symbol)),
11357 && offset_expr.X_add_number == 0);
11358 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
11359 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
11364 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
11365 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
11366 order 32 bits of the value and the low order 32 bits are either
11367 zero or in OFFSET_EXPR. */
11368 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11370 if (HAVE_64BIT_GPRS)
11371 load_register (op[0], &imm_expr, 1);
11376 if (target_big_endian)
11388 load_register (hreg, &imm_expr, 0);
11391 if (offset_expr.X_op == O_absent)
11392 move_register (lreg, 0);
11395 gas_assert (offset_expr.X_op == O_constant);
11396 load_register (lreg, &offset_expr, 0);
11403 /* We know that sym is in the .rdata section. First we get the
11404 upper 16 bits of the address. */
11405 if (mips_pic == NO_PIC)
11407 macro_build_lui (&offset_expr, AT);
11412 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11413 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11417 /* Now we load the register(s). */
11418 if (HAVE_64BIT_GPRS)
11421 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
11422 BFD_RELOC_LO16, AT);
11427 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
11428 BFD_RELOC_LO16, AT);
11431 /* FIXME: How in the world do we deal with the possible
11433 offset_expr.X_add_number += 4;
11434 macro_build (&offset_expr, "lw", "t,o(b)",
11435 op[0] + 1, BFD_RELOC_LO16, AT);
11441 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
11442 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
11443 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
11444 the value and the low order 32 bits are either zero or in
11446 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
11449 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
11450 if (HAVE_64BIT_FPRS)
11452 gas_assert (HAVE_64BIT_GPRS);
11453 macro_build (NULL, "dmtc1", "t,S", AT, op[0]);
11457 macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1);
11458 if (offset_expr.X_op == O_absent)
11459 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
11462 gas_assert (offset_expr.X_op == O_constant);
11463 load_register (AT, &offset_expr, 0);
11464 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
11470 gas_assert (offset_expr.X_op == O_symbol
11471 && offset_expr.X_add_number == 0);
11472 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
11473 if (strcmp (s, ".lit8") == 0)
11475 op[2] = mips_gp_register;
11476 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
11477 offset_reloc[1] = BFD_RELOC_UNUSED;
11478 offset_reloc[2] = BFD_RELOC_UNUSED;
11482 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
11484 if (mips_pic != NO_PIC)
11485 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11486 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11489 /* FIXME: This won't work for a 64 bit address. */
11490 macro_build_lui (&offset_expr, AT);
11494 offset_reloc[0] = BFD_RELOC_LO16;
11495 offset_reloc[1] = BFD_RELOC_UNUSED;
11496 offset_reloc[2] = BFD_RELOC_UNUSED;
11503 * The MIPS assembler seems to check for X_add_number not
11504 * being double aligned and generating:
11505 * lui at,%hi(foo+1)
11507 * addiu at,at,%lo(foo+1)
11510 * But, the resulting address is the same after relocation so why
11511 * generate the extra instruction?
11513 /* Itbl support may require additional care here. */
11516 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11525 gas_assert (!mips_opts.micromips);
11526 /* Itbl support may require additional care here. */
11529 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
11549 if (HAVE_64BIT_GPRS)
11559 if (HAVE_64BIT_GPRS)
11567 /* Even on a big endian machine $fn comes before $fn+1. We have
11568 to adjust when loading from memory. We set coproc if we must
11569 load $fn+1 first. */
11570 /* Itbl support may require additional care here. */
11571 if (!target_big_endian)
11575 if (small_offset_p (0, align, 16))
11578 if (!small_offset_p (4, align, 16))
11580 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
11581 -1, offset_reloc[0], offset_reloc[1],
11583 expr1.X_add_number = 0;
11587 offset_reloc[0] = BFD_RELOC_LO16;
11588 offset_reloc[1] = BFD_RELOC_UNUSED;
11589 offset_reloc[2] = BFD_RELOC_UNUSED;
11591 if (strcmp (s, "lw") == 0 && op[0] == breg)
11593 ep->X_add_number += 4;
11594 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
11595 offset_reloc[1], offset_reloc[2], breg);
11596 ep->X_add_number -= 4;
11597 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
11598 offset_reloc[1], offset_reloc[2], breg);
11602 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
11603 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11605 ep->X_add_number += 4;
11606 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
11607 offset_reloc[0], offset_reloc[1], offset_reloc[2],
11613 if (offset_expr.X_op != O_symbol
11614 && offset_expr.X_op != O_constant)
11616 as_bad (_("Expression too complex"));
11617 offset_expr.X_op = O_constant;
11620 if (HAVE_32BIT_ADDRESSES
11621 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11625 sprintf_vma (value, offset_expr.X_add_number);
11626 as_bad (_("Number (0x%s) larger than 32 bits"), value);
11629 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
11631 /* If this is a reference to a GP relative symbol, we want
11632 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
11633 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
11634 If we have a base register, we use this
11636 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
11637 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
11638 If this is not a GP relative symbol, we want
11639 lui $at,<sym> (BFD_RELOC_HI16_S)
11640 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11641 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11642 If there is a base register, we add it to $at after the
11643 lui instruction. If there is a constant, we always use
11645 if (offset_expr.X_op == O_symbol
11646 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11647 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11649 relax_start (offset_expr.X_add_symbol);
11652 tempreg = mips_gp_register;
11656 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11657 AT, breg, mips_gp_register);
11662 /* Itbl support may require additional care here. */
11663 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11664 BFD_RELOC_GPREL16, tempreg);
11665 offset_expr.X_add_number += 4;
11667 /* Set mips_optimize to 2 to avoid inserting an
11669 hold_mips_optimize = mips_optimize;
11671 /* Itbl support may require additional care here. */
11672 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11673 BFD_RELOC_GPREL16, tempreg);
11674 mips_optimize = hold_mips_optimize;
11678 offset_expr.X_add_number -= 4;
11681 if (offset_high_part (offset_expr.X_add_number, 16)
11682 != offset_high_part (offset_expr.X_add_number + 4, 16))
11684 load_address (AT, &offset_expr, &used_at);
11685 offset_expr.X_op = O_constant;
11686 offset_expr.X_add_number = 0;
11689 macro_build_lui (&offset_expr, AT);
11691 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11692 /* Itbl support may require additional care here. */
11693 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11694 BFD_RELOC_LO16, AT);
11695 /* FIXME: How do we handle overflow here? */
11696 offset_expr.X_add_number += 4;
11697 /* Itbl support may require additional care here. */
11698 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11699 BFD_RELOC_LO16, AT);
11700 if (mips_relax.sequence)
11703 else if (!mips_big_got)
11705 /* If this is a reference to an external symbol, we want
11706 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11709 <op> op[0]+1,4($at)
11711 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11713 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11714 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11715 If there is a base register we add it to $at before the
11716 lwc1 instructions. If there is a constant we include it
11717 in the lwc1 instructions. */
11719 expr1.X_add_number = offset_expr.X_add_number;
11720 if (expr1.X_add_number < -0x8000
11721 || expr1.X_add_number >= 0x8000 - 4)
11722 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11723 load_got_offset (AT, &offset_expr);
11726 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11728 /* Set mips_optimize to 2 to avoid inserting an undesired
11730 hold_mips_optimize = mips_optimize;
11733 /* Itbl support may require additional care here. */
11734 relax_start (offset_expr.X_add_symbol);
11735 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11736 BFD_RELOC_LO16, AT);
11737 expr1.X_add_number += 4;
11738 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11739 BFD_RELOC_LO16, AT);
11741 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11742 BFD_RELOC_LO16, AT);
11743 offset_expr.X_add_number += 4;
11744 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11745 BFD_RELOC_LO16, AT);
11748 mips_optimize = hold_mips_optimize;
11750 else if (mips_big_got)
11754 /* If this is a reference to an external symbol, we want
11755 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11757 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
11760 <op> op[0]+1,4($at)
11762 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11764 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
11765 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
11766 If there is a base register we add it to $at before the
11767 lwc1 instructions. If there is a constant we include it
11768 in the lwc1 instructions. */
11770 expr1.X_add_number = offset_expr.X_add_number;
11771 offset_expr.X_add_number = 0;
11772 if (expr1.X_add_number < -0x8000
11773 || expr1.X_add_number >= 0x8000 - 4)
11774 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
11775 gpdelay = reg_needs_delay (mips_gp_register);
11776 relax_start (offset_expr.X_add_symbol);
11777 macro_build (&offset_expr, "lui", LUI_FMT,
11778 AT, BFD_RELOC_MIPS_GOT_HI16);
11779 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11780 AT, AT, mips_gp_register);
11781 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11782 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
11785 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11786 /* Itbl support may require additional care here. */
11787 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
11788 BFD_RELOC_LO16, AT);
11789 expr1.X_add_number += 4;
11791 /* Set mips_optimize to 2 to avoid inserting an undesired
11793 hold_mips_optimize = mips_optimize;
11795 /* Itbl support may require additional care here. */
11796 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
11797 BFD_RELOC_LO16, AT);
11798 mips_optimize = hold_mips_optimize;
11799 expr1.X_add_number -= 4;
11802 offset_expr.X_add_number = expr1.X_add_number;
11804 macro_build (NULL, "nop", "");
11805 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
11806 BFD_RELOC_MIPS_GOT16, mips_gp_register);
11809 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
11810 /* Itbl support may require additional care here. */
11811 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
11812 BFD_RELOC_LO16, AT);
11813 offset_expr.X_add_number += 4;
11815 /* Set mips_optimize to 2 to avoid inserting an undesired
11817 hold_mips_optimize = mips_optimize;
11819 /* Itbl support may require additional care here. */
11820 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
11821 BFD_RELOC_LO16, AT);
11822 mips_optimize = hold_mips_optimize;
11841 /* New code added to support COPZ instructions.
11842 This code builds table entries out of the macros in mip_opcodes.
11843 R4000 uses interlocks to handle coproc delays.
11844 Other chips (like the R3000) require nops to be inserted for delays.
11846 FIXME: Currently, we require that the user handle delays.
11847 In order to fill delay slots for non-interlocked chips,
11848 we must have a way to specify delays based on the coprocessor.
11849 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
11850 What are the side-effects of the cop instruction?
11851 What cache support might we have and what are its effects?
11852 Both coprocessor & memory require delays. how long???
11853 What registers are read/set/modified?
11855 If an itbl is provided to interpret cop instructions,
11856 this knowledge can be encoded in the itbl spec. */
11870 gas_assert (!mips_opts.micromips);
11871 /* For now we just do C (same as Cz). The parameter will be
11872 stored in insn_opcode by mips_ip. */
11873 macro_build (NULL, s, "C", (int) ip->insn_opcode);
11877 move_register (op[0], op[1]);
11881 gas_assert (mips_opts.micromips);
11882 gas_assert (mips_opts.insn32);
11883 move_register (micromips_to_32_reg_h_map1[op[0]],
11884 micromips_to_32_reg_m_map[op[1]]);
11885 move_register (micromips_to_32_reg_h_map2[op[0]],
11886 micromips_to_32_reg_n_map[op[2]]);
11892 if (mips_opts.arch == CPU_R5900)
11893 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
11897 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
11898 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11905 /* The MIPS assembler some times generates shifts and adds. I'm
11906 not trying to be that fancy. GCC should do this for us
11909 load_register (AT, &imm_expr, dbl);
11910 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
11911 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11924 start_noreorder ();
11927 load_register (AT, &imm_expr, dbl);
11928 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
11929 op[1], imm ? AT : op[2]);
11930 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11931 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
11932 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11934 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
11937 if (mips_opts.micromips)
11938 micromips_label_expr (&label_expr);
11940 label_expr.X_add_number = 8;
11941 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
11942 macro_build (NULL, "nop", "");
11943 macro_build (NULL, "break", BRK_FMT, 6);
11944 if (mips_opts.micromips)
11945 micromips_add_label ();
11948 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11961 start_noreorder ();
11964 load_register (AT, &imm_expr, dbl);
11965 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
11966 op[1], imm ? AT : op[2]);
11967 macro_build (NULL, "mfhi", MFHL_FMT, AT);
11968 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
11970 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
11973 if (mips_opts.micromips)
11974 micromips_label_expr (&label_expr);
11976 label_expr.X_add_number = 8;
11977 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
11978 macro_build (NULL, "nop", "");
11979 macro_build (NULL, "break", BRK_FMT, 6);
11980 if (mips_opts.micromips)
11981 micromips_add_label ();
11987 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
11989 if (op[0] == op[1])
11996 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
11997 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
12001 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12002 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
12003 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
12004 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12008 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12010 if (op[0] == op[1])
12017 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
12018 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
12022 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12023 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
12024 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
12025 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12034 if (imm_expr.X_op != O_constant)
12035 as_bad (_("Improper rotate count"));
12036 rot = imm_expr.X_add_number & 0x3f;
12037 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12039 rot = (64 - rot) & 0x3f;
12041 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12043 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12048 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12051 l = (rot < 0x20) ? "dsll" : "dsll32";
12052 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
12055 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
12056 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12057 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12065 if (imm_expr.X_op != O_constant)
12066 as_bad (_("Improper rotate count"));
12067 rot = imm_expr.X_add_number & 0x1f;
12068 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12070 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
12071 (32 - rot) & 0x1f);
12076 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12080 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
12081 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12082 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12087 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12089 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
12093 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
12094 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
12095 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
12096 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12100 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12102 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
12106 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
12107 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
12108 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
12109 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12118 if (imm_expr.X_op != O_constant)
12119 as_bad (_("Improper rotate count"));
12120 rot = imm_expr.X_add_number & 0x3f;
12121 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12124 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
12126 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
12131 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
12134 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
12135 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
12138 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
12139 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12140 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12148 if (imm_expr.X_op != O_constant)
12149 as_bad (_("Improper rotate count"));
12150 rot = imm_expr.X_add_number & 0x1f;
12151 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12153 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
12158 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
12162 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
12163 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
12164 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12170 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
12171 else if (op[2] == 0)
12172 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12175 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12176 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12181 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12183 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12188 as_warn (_("Instruction %s: result is always false"),
12189 ip->insn_mo->name);
12190 move_register (op[0], 0);
12193 if (CPU_HAS_SEQ (mips_opts.arch)
12194 && -512 <= imm_expr.X_add_number
12195 && imm_expr.X_add_number < 512)
12197 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
12198 (int) imm_expr.X_add_number);
12201 if (imm_expr.X_op == O_constant
12202 && imm_expr.X_add_number >= 0
12203 && imm_expr.X_add_number < 0x10000)
12204 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
12205 else if (imm_expr.X_op == O_constant
12206 && imm_expr.X_add_number > -0x8000
12207 && imm_expr.X_add_number < 0)
12209 imm_expr.X_add_number = -imm_expr.X_add_number;
12210 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12211 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12213 else if (CPU_HAS_SEQ (mips_opts.arch))
12216 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12217 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
12222 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12223 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12226 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
12229 case M_SGE: /* X >= Y <==> not (X < Y) */
12235 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
12236 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12239 case M_SGE_I: /* X >= I <==> not (X < I) */
12241 if (imm_expr.X_op == O_constant
12242 && imm_expr.X_add_number >= -0x8000
12243 && imm_expr.X_add_number < 0x8000)
12244 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
12245 op[0], op[1], BFD_RELOC_LO16);
12248 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12249 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
12253 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12256 case M_SGT: /* X > Y <==> Y < X */
12262 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12265 case M_SGT_I: /* X > I <==> I < X */
12272 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12273 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12276 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */
12282 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
12283 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12286 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
12293 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12294 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
12295 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
12299 if (imm_expr.X_op == O_constant
12300 && imm_expr.X_add_number >= -0x8000
12301 && imm_expr.X_add_number < 0x8000)
12303 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
12308 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12309 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
12313 if (imm_expr.X_op == O_constant
12314 && imm_expr.X_add_number >= -0x8000
12315 && imm_expr.X_add_number < 0x8000)
12317 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
12322 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12323 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
12328 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
12329 else if (op[2] == 0)
12330 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12333 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
12334 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12339 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
12341 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
12346 as_warn (_("Instruction %s: result is always true"),
12347 ip->insn_mo->name);
12348 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
12349 op[0], 0, BFD_RELOC_LO16);
12352 if (CPU_HAS_SEQ (mips_opts.arch)
12353 && -512 <= imm_expr.X_add_number
12354 && imm_expr.X_add_number < 512)
12356 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
12357 (int) imm_expr.X_add_number);
12360 if (imm_expr.X_op == O_constant
12361 && imm_expr.X_add_number >= 0
12362 && imm_expr.X_add_number < 0x10000)
12364 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
12367 else if (imm_expr.X_op == O_constant
12368 && imm_expr.X_add_number > -0x8000
12369 && imm_expr.X_add_number < 0)
12371 imm_expr.X_add_number = -imm_expr.X_add_number;
12372 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
12373 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12375 else if (CPU_HAS_SEQ (mips_opts.arch))
12378 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12379 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
12384 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12385 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
12388 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
12403 if (!mips_opts.micromips)
12405 if (imm_expr.X_op == O_constant
12406 && imm_expr.X_add_number > -0x200
12407 && imm_expr.X_add_number <= 0x200)
12409 macro_build (NULL, s, "t,r,.", op[0], op[1], -imm_expr.X_add_number);
12418 if (imm_expr.X_op == O_constant
12419 && imm_expr.X_add_number > -0x8000
12420 && imm_expr.X_add_number <= 0x8000)
12422 imm_expr.X_add_number = -imm_expr.X_add_number;
12423 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
12428 load_register (AT, &imm_expr, dbl);
12429 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
12451 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
12452 macro_build (NULL, s, "s,t", op[0], AT);
12457 gas_assert (!mips_opts.micromips);
12458 gas_assert (mips_opts.isa == ISA_MIPS1);
12462 * Is the double cfc1 instruction a bug in the mips assembler;
12463 * or is there a reason for it?
12465 start_noreorder ();
12466 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12467 macro_build (NULL, "cfc1", "t,G", op[2], RA);
12468 macro_build (NULL, "nop", "");
12469 expr1.X_add_number = 3;
12470 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
12471 expr1.X_add_number = 2;
12472 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
12473 macro_build (NULL, "ctc1", "t,G", AT, RA);
12474 macro_build (NULL, "nop", "");
12475 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
12477 macro_build (NULL, "ctc1", "t,G", op[2], RA);
12478 macro_build (NULL, "nop", "");
12495 offbits = (mips_opts.micromips ? 12 : 16);
12501 offbits = (mips_opts.micromips ? 12 : 16);
12513 offbits = (mips_opts.micromips ? 12 : 16);
12520 offbits = (mips_opts.micromips ? 12 : 16);
12526 large_offset = !small_offset_p (off, align, offbits);
12528 expr1.X_add_number = 0;
12533 if (small_offset_p (0, align, 16))
12534 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
12535 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
12538 load_address (tempreg, ep, &used_at);
12540 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12541 tempreg, tempreg, breg);
12543 offset_reloc[0] = BFD_RELOC_LO16;
12544 offset_reloc[1] = BFD_RELOC_UNUSED;
12545 offset_reloc[2] = BFD_RELOC_UNUSED;
12550 else if (!ust && op[0] == breg)
12561 if (!target_big_endian)
12562 ep->X_add_number += off;
12564 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
12566 macro_build (ep, s, "t,o(b)", tempreg, -1,
12567 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12569 if (!target_big_endian)
12570 ep->X_add_number -= off;
12572 ep->X_add_number += off;
12574 macro_build (NULL, s2, "t,~(b)",
12575 tempreg, (int) ep->X_add_number, breg);
12577 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12578 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12580 /* If necessary, move the result in tempreg to the final destination. */
12581 if (!ust && op[0] != tempreg)
12583 /* Protect second load's delay slot. */
12585 move_register (op[0], tempreg);
12591 if (target_big_endian == ust)
12592 ep->X_add_number += off;
12593 tempreg = ust || large_offset ? op[0] : AT;
12594 macro_build (ep, s, "t,o(b)", tempreg, -1,
12595 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12597 /* For halfword transfers we need a temporary register to shuffle
12598 bytes. Unfortunately for M_USH_A we have none available before
12599 the next store as AT holds the base address. We deal with this
12600 case by clobbering TREG and then restoring it as with ULH. */
12601 tempreg = ust == large_offset ? op[0] : AT;
12603 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
12605 if (target_big_endian == ust)
12606 ep->X_add_number -= off;
12608 ep->X_add_number += off;
12609 macro_build (ep, s2, "t,o(b)", tempreg, -1,
12610 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
12612 /* For M_USH_A re-retrieve the LSB. */
12613 if (ust && large_offset)
12615 if (target_big_endian)
12616 ep->X_add_number += off;
12618 ep->X_add_number -= off;
12619 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
12620 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
12622 /* For ULH and M_USH_A OR the LSB in. */
12623 if (!ust || large_offset)
12625 tempreg = !large_offset ? AT : op[0];
12626 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
12627 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
12632 /* FIXME: Check if this is one of the itbl macros, since they
12633 are added dynamically. */
12634 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
12637 if (!mips_opts.at && used_at)
12638 as_bad (_("Macro used $at after \".set noat\""));
12641 /* Implement macros in mips16 mode. */
12644 mips16_macro (struct mips_cl_insn *ip)
12646 const struct mips_operand_array *operands;
12651 const char *s, *s2, *s3;
12652 unsigned int op[MAX_OPERANDS];
12655 mask = ip->insn_mo->mask;
12657 operands = insn_operands (ip);
12658 for (i = 0; i < MAX_OPERANDS; i++)
12659 if (operands->operand[i])
12660 op[i] = insn_extract_operand (ip, operands->operand[i]);
12664 expr1.X_op = O_constant;
12665 expr1.X_op_symbol = NULL;
12666 expr1.X_add_symbol = NULL;
12667 expr1.X_add_number = 1;
12686 start_noreorder ();
12687 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", op[1], op[2]);
12688 expr1.X_add_number = 2;
12689 macro_build (&expr1, "bnez", "x,p", op[2]);
12690 macro_build (NULL, "break", "6", 7);
12692 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
12693 since that causes an overflow. We should do that as well,
12694 but I don't see how to do the comparisons without a temporary
12697 macro_build (NULL, s, "x", op[0]);
12716 start_noreorder ();
12717 macro_build (NULL, s, "0,x,y", op[1], op[2]);
12718 expr1.X_add_number = 2;
12719 macro_build (&expr1, "bnez", "x,p", op[2]);
12720 macro_build (NULL, "break", "6", 7);
12722 macro_build (NULL, s2, "x", op[0]);
12728 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
12729 macro_build (NULL, "mflo", "x", op[0]);
12737 if (imm_expr.X_op != O_constant)
12738 as_bad (_("Unsupported large constant"));
12739 imm_expr.X_add_number = -imm_expr.X_add_number;
12740 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", op[0], op[1]);
12744 if (imm_expr.X_op != O_constant)
12745 as_bad (_("Unsupported large constant"));
12746 imm_expr.X_add_number = -imm_expr.X_add_number;
12747 macro_build (&imm_expr, "addiu", "x,k", op[0]);
12751 if (imm_expr.X_op != O_constant)
12752 as_bad (_("Unsupported large constant"));
12753 imm_expr.X_add_number = -imm_expr.X_add_number;
12754 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
12776 goto do_reverse_branch;
12780 goto do_reverse_branch;
12792 goto do_reverse_branch;
12803 macro_build (NULL, s, "x,y", op[0], op[1]);
12804 macro_build (&offset_expr, s2, "p");
12831 goto do_addone_branch_i;
12836 goto do_addone_branch_i;
12851 goto do_addone_branch_i;
12857 do_addone_branch_i:
12858 if (imm_expr.X_op != O_constant)
12859 as_bad (_("Unsupported large constant"));
12860 ++imm_expr.X_add_number;
12863 macro_build (&imm_expr, s, s3, op[0]);
12864 macro_build (&offset_expr, s2, "p");
12868 expr1.X_add_number = 0;
12869 macro_build (&expr1, "slti", "x,8", op[1]);
12870 if (op[0] != op[1])
12871 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
12872 expr1.X_add_number = 2;
12873 macro_build (&expr1, "bteqz", "p");
12874 macro_build (NULL, "neg", "x,w", op[0], op[0]);
12879 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
12880 opcode bits in *OPCODE_EXTRA. */
12882 static struct mips_opcode *
12883 mips_lookup_insn (struct hash_control *hash, const char *start,
12884 ssize_t length, unsigned int *opcode_extra)
12886 char *name, *dot, *p;
12887 unsigned int mask, suffix;
12889 struct mips_opcode *insn;
12891 /* Make a copy of the instruction so that we can fiddle with it. */
12892 name = alloca (length + 1);
12893 memcpy (name, start, length);
12894 name[length] = '\0';
12896 /* Look up the instruction as-is. */
12897 insn = (struct mips_opcode *) hash_find (hash, name);
12901 dot = strchr (name, '.');
12904 /* Try to interpret the text after the dot as a VU0 channel suffix. */
12905 p = mips_parse_vu0_channels (dot + 1, &mask);
12906 if (*p == 0 && mask != 0)
12909 insn = (struct mips_opcode *) hash_find (hash, name);
12911 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
12913 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
12919 if (mips_opts.micromips)
12921 /* See if there's an instruction size override suffix,
12922 either `16' or `32', at the end of the mnemonic proper,
12923 that defines the operation, i.e. before the first `.'
12924 character if any. Strip it and retry. */
12925 opend = dot != NULL ? dot - name : length;
12926 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
12928 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
12934 memcpy (name + opend - 2, name + opend, length - opend + 1);
12935 insn = (struct mips_opcode *) hash_find (hash, name);
12938 forced_insn_length = suffix;
12947 /* Assemble an instruction into its binary format. If the instruction
12948 is a macro, set imm_expr, imm2_expr and offset_expr to the values
12949 associated with "I", "+I" and "A" operands respectively. Otherwise
12950 store the value of the relocatable field (if any) in offset_expr.
12951 In both cases set offset_reloc to the relocation operators applied
12955 mips_ip (char *str, struct mips_cl_insn *ip)
12957 bfd_boolean wrong_delay_slot_insns = FALSE;
12958 bfd_boolean need_delay_slot_ok = TRUE;
12959 struct mips_opcode *firstinsn = NULL;
12960 const struct mips_opcode *past;
12961 struct hash_control *hash;
12962 struct mips_opcode *first, *insn;
12965 struct mips_operand_token *tokens;
12966 unsigned int opcode_extra;
12968 if (mips_opts.micromips)
12970 hash = micromips_op_hash;
12971 past = µmips_opcodes[bfd_micromips_num_opcodes];
12976 past = &mips_opcodes[NUMOPCODES];
12978 forced_insn_length = 0;
12982 /* We first try to match an instruction up to a space or to the end. */
12983 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
12986 first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
12989 set_insn_error (0, _("Unrecognized opcode"));
12992 /* When no opcode suffix is specified, assume ".xyzw". */
12993 if ((insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
12994 opcode_extra = 0xf << mips_vu0_channel_mask.lsb;
12996 if (strcmp (insn->name, "li.s") == 0)
12998 else if (strcmp (insn->name, "li.d") == 0)
13002 tokens = mips_parse_arguments (str + end, format);
13006 /* For microMIPS instructions placed in a fixed-length branch delay slot
13007 we make up to two passes over the relevant fragment of the opcode
13008 table. First we try instructions that meet the delay slot's length
13009 requirement. If none matched, then we retry with the remaining ones
13010 and if one matches, then we use it and then issue an appropriate
13011 warning later on. */
13014 bfd_boolean delay_slot_ok;
13015 bfd_boolean size_ok;
13017 bfd_boolean more_alts;
13019 gas_assert (strcmp (insn->name, first->name) == 0);
13021 ok = is_opcode_valid (insn);
13022 size_ok = is_size_valid (insn);
13023 delay_slot_ok = is_delay_slot_valid (insn);
13024 if (!delay_slot_ok && !wrong_delay_slot_insns)
13027 wrong_delay_slot_insns = TRUE;
13029 more_alts = (insn + 1 < past
13030 && strcmp (insn[0].name, insn[1].name) == 0);
13031 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
13038 if (wrong_delay_slot_insns && need_delay_slot_ok)
13040 gas_assert (firstinsn);
13041 need_delay_slot_ok = FALSE;
13049 (0, _("Opcode not supported on this processor: %s (%s)"),
13050 mips_cpu_info_from_arch (mips_opts.arch)->name,
13051 mips_cpu_info_from_isa (mips_opts.isa)->name);
13052 else if (mips_opts.insn32)
13054 (0, _("Opcode not supported in the `insn32' mode"));
13057 (0, _("Unrecognized %d-bit version of microMIPS opcode"),
13058 8 * forced_insn_length);
13062 if (match_insn (ip, insn, tokens, opcode_extra,
13063 more_alts || (wrong_delay_slot_insns
13064 && need_delay_slot_ok)))
13067 /* Args don't match. */
13068 set_insn_error (0, _("Illegal operands"));
13074 if (wrong_delay_slot_insns && need_delay_slot_ok)
13076 gas_assert (firstinsn);
13077 need_delay_slot_ok = FALSE;
13084 obstack_free (&mips_operand_tokens, tokens);
13087 /* As for mips_ip, but used when assembling MIPS16 code.
13088 Also set forced_insn_length to the resulting instruction size in
13089 bytes if the user explicitly requested a small or extended instruction. */
13092 mips16_ip (char *str, struct mips_cl_insn *ip)
13095 struct mips_opcode *insn, *first;
13096 struct mips_operand_token *tokens;
13098 forced_insn_length = 0;
13100 for (s = str; ISLOWER (*s); ++s)
13114 if (s[1] == 't' && s[2] == ' ')
13116 forced_insn_length = 2;
13120 else if (s[1] == 'e' && s[2] == ' ')
13122 forced_insn_length = 4;
13126 /* Fall through. */
13128 set_insn_error (0, _("Unrecognized opcode"));
13132 if (mips_opts.noautoextend && !forced_insn_length)
13133 forced_insn_length = 2;
13136 first = insn = (struct mips_opcode *) hash_find (mips16_op_hash, str);
13141 set_insn_error (0, _("Unrecognized opcode"));
13145 tokens = mips_parse_arguments (s, 0);
13152 bfd_boolean more_alts;
13154 gas_assert (strcmp (insn->name, first->name) == 0);
13156 ok = is_opcode_valid_16 (insn);
13157 more_alts = (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13158 && strcmp (insn[0].name, insn[1].name) == 0);
13169 (0, _("Opcode not supported on this processor: %s (%s)"),
13170 mips_cpu_info_from_arch (mips_opts.arch)->name,
13171 mips_cpu_info_from_isa (mips_opts.isa)->name);
13176 if (match_mips16_insn (ip, insn, tokens))
13179 /* Args don't match. */
13180 set_insn_error (0, _("Illegal operands"));
13188 obstack_free (&mips_operand_tokens, tokens);
13191 /* Marshal immediate value VAL for an extended MIPS16 instruction.
13192 NBITS is the number of significant bits in VAL. */
13194 static unsigned long
13195 mips16_immed_extend (offsetT val, unsigned int nbits)
13200 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
13203 else if (nbits == 15)
13205 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
13210 extval = ((val & 0x1f) << 6) | (val & 0x20);
13213 return (extval << 16) | val;
13216 /* Like decode_mips16_operand, but require the operand to be defined and
13217 require it to be an integer. */
13219 static const struct mips_int_operand *
13220 mips16_immed_operand (int type, bfd_boolean extended_p)
13222 const struct mips_operand *operand;
13224 operand = decode_mips16_operand (type, extended_p);
13225 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
13227 return (const struct mips_int_operand *) operand;
13230 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
13233 mips16_immed_in_range_p (const struct mips_int_operand *operand,
13234 bfd_reloc_code_real_type reloc, offsetT sval)
13236 int min_val, max_val;
13238 min_val = mips_int_operand_min (operand);
13239 max_val = mips_int_operand_max (operand);
13240 if (reloc != BFD_RELOC_UNUSED)
13243 sval = SEXT_16BIT (sval);
13248 return (sval >= min_val
13250 && (sval & ((1 << operand->shift) - 1)) == 0);
13253 /* Install immediate value VAL into MIPS16 instruction *INSN,
13254 extending it if necessary. The instruction in *INSN may
13255 already be extended.
13257 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
13258 if none. In the former case, VAL is a 16-bit number with no
13259 defined signedness.
13261 TYPE is the type of the immediate field. USER_INSN_LENGTH
13262 is the length that the user requested, or 0 if none. */
13265 mips16_immed (char *file, unsigned int line, int type,
13266 bfd_reloc_code_real_type reloc, offsetT val,
13267 unsigned int user_insn_length, unsigned long *insn)
13269 const struct mips_int_operand *operand;
13270 unsigned int uval, length;
13272 operand = mips16_immed_operand (type, FALSE);
13273 if (!mips16_immed_in_range_p (operand, reloc, val))
13275 /* We need an extended instruction. */
13276 if (user_insn_length == 2)
13277 as_bad_where (file, line, _("invalid unextended operand value"));
13279 *insn |= MIPS16_EXTEND;
13281 else if (user_insn_length == 4)
13283 /* The operand doesn't force an unextended instruction to be extended.
13284 Warn if the user wanted an extended instruction anyway. */
13285 *insn |= MIPS16_EXTEND;
13286 as_warn_where (file, line,
13287 _("extended operand requested but not required"));
13290 length = mips16_opcode_length (*insn);
13293 operand = mips16_immed_operand (type, TRUE);
13294 if (!mips16_immed_in_range_p (operand, reloc, val))
13295 as_bad_where (file, line,
13296 _("operand value out of range for instruction"));
13298 uval = ((unsigned int) val >> operand->shift) - operand->bias;
13300 *insn = mips_insert_operand (&operand->root, *insn, uval);
13302 *insn |= mips16_immed_extend (uval, operand->root.size);
13305 struct percent_op_match
13308 bfd_reloc_code_real_type reloc;
13311 static const struct percent_op_match mips_percent_op[] =
13313 {"%lo", BFD_RELOC_LO16},
13314 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
13315 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
13316 {"%call16", BFD_RELOC_MIPS_CALL16},
13317 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
13318 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
13319 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
13320 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
13321 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
13322 {"%got", BFD_RELOC_MIPS_GOT16},
13323 {"%gp_rel", BFD_RELOC_GPREL16},
13324 {"%half", BFD_RELOC_16},
13325 {"%highest", BFD_RELOC_MIPS_HIGHEST},
13326 {"%higher", BFD_RELOC_MIPS_HIGHER},
13327 {"%neg", BFD_RELOC_MIPS_SUB},
13328 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
13329 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
13330 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
13331 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
13332 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
13333 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
13334 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
13335 {"%hi", BFD_RELOC_HI16_S}
13338 static const struct percent_op_match mips16_percent_op[] =
13340 {"%lo", BFD_RELOC_MIPS16_LO16},
13341 {"%gprel", BFD_RELOC_MIPS16_GPREL},
13342 {"%got", BFD_RELOC_MIPS16_GOT16},
13343 {"%call16", BFD_RELOC_MIPS16_CALL16},
13344 {"%hi", BFD_RELOC_MIPS16_HI16_S},
13345 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
13346 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
13347 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
13348 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
13349 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
13350 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
13351 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
13355 /* Return true if *STR points to a relocation operator. When returning true,
13356 move *STR over the operator and store its relocation code in *RELOC.
13357 Leave both *STR and *RELOC alone when returning false. */
13360 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
13362 const struct percent_op_match *percent_op;
13365 if (mips_opts.mips16)
13367 percent_op = mips16_percent_op;
13368 limit = ARRAY_SIZE (mips16_percent_op);
13372 percent_op = mips_percent_op;
13373 limit = ARRAY_SIZE (mips_percent_op);
13376 for (i = 0; i < limit; i++)
13377 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
13379 int len = strlen (percent_op[i].str);
13381 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
13384 *str += strlen (percent_op[i].str);
13385 *reloc = percent_op[i].reloc;
13387 /* Check whether the output BFD supports this relocation.
13388 If not, issue an error and fall back on something safe. */
13389 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
13391 as_bad (_("relocation %s isn't supported by the current ABI"),
13392 percent_op[i].str);
13393 *reloc = BFD_RELOC_UNUSED;
13401 /* Parse string STR as a 16-bit relocatable operand. Store the
13402 expression in *EP and the relocations in the array starting
13403 at RELOC. Return the number of relocation operators used.
13405 On exit, EXPR_END points to the first character after the expression. */
13408 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
13411 bfd_reloc_code_real_type reversed_reloc[3];
13412 size_t reloc_index, i;
13413 int crux_depth, str_depth;
13416 /* Search for the start of the main expression, recoding relocations
13417 in REVERSED_RELOC. End the loop with CRUX pointing to the start
13418 of the main expression and with CRUX_DEPTH containing the number
13419 of open brackets at that point. */
13426 crux_depth = str_depth;
13428 /* Skip over whitespace and brackets, keeping count of the number
13430 while (*str == ' ' || *str == '\t' || *str == '(')
13435 && reloc_index < (HAVE_NEWABI ? 3 : 1)
13436 && parse_relocation (&str, &reversed_reloc[reloc_index]));
13438 my_getExpression (ep, crux);
13441 /* Match every open bracket. */
13442 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
13446 if (crux_depth > 0)
13447 as_bad (_("unclosed '('"));
13451 if (reloc_index != 0)
13453 prev_reloc_op_frag = frag_now;
13454 for (i = 0; i < reloc_index; i++)
13455 reloc[i] = reversed_reloc[reloc_index - 1 - i];
13458 return reloc_index;
13462 my_getExpression (expressionS *ep, char *str)
13466 save_in = input_line_pointer;
13467 input_line_pointer = str;
13469 expr_end = input_line_pointer;
13470 input_line_pointer = save_in;
13474 md_atof (int type, char *litP, int *sizeP)
13476 return ieee_md_atof (type, litP, sizeP, target_big_endian);
13480 md_number_to_chars (char *buf, valueT val, int n)
13482 if (target_big_endian)
13483 number_to_chars_bigendian (buf, val, n);
13485 number_to_chars_littleendian (buf, val, n);
13488 static int support_64bit_objects(void)
13490 const char **list, **l;
13493 list = bfd_target_list ();
13494 for (l = list; *l != NULL; l++)
13495 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
13496 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
13498 yes = (*l != NULL);
13503 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
13504 NEW_VALUE. Warn if another value was already specified. Note:
13505 we have to defer parsing the -march and -mtune arguments in order
13506 to handle 'from-abi' correctly, since the ABI might be specified
13507 in a later argument. */
13510 mips_set_option_string (const char **string_ptr, const char *new_value)
13512 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
13513 as_warn (_("A different %s was already specified, is now %s"),
13514 string_ptr == &mips_arch_string ? "-march" : "-mtune",
13517 *string_ptr = new_value;
13521 md_parse_option (int c, char *arg)
13525 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
13526 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
13528 file_ase_explicit |= mips_set_ase (&mips_ases[i],
13529 c == mips_ases[i].option_on);
13535 case OPTION_CONSTRUCT_FLOATS:
13536 mips_disable_float_construction = 0;
13539 case OPTION_NO_CONSTRUCT_FLOATS:
13540 mips_disable_float_construction = 1;
13552 target_big_endian = 1;
13556 target_big_endian = 0;
13562 else if (arg[0] == '0')
13564 else if (arg[0] == '1')
13574 mips_debug = atoi (arg);
13578 file_mips_isa = ISA_MIPS1;
13582 file_mips_isa = ISA_MIPS2;
13586 file_mips_isa = ISA_MIPS3;
13590 file_mips_isa = ISA_MIPS4;
13594 file_mips_isa = ISA_MIPS5;
13597 case OPTION_MIPS32:
13598 file_mips_isa = ISA_MIPS32;
13601 case OPTION_MIPS32R2:
13602 file_mips_isa = ISA_MIPS32R2;
13605 case OPTION_MIPS64R2:
13606 file_mips_isa = ISA_MIPS64R2;
13609 case OPTION_MIPS64:
13610 file_mips_isa = ISA_MIPS64;
13614 mips_set_option_string (&mips_tune_string, arg);
13618 mips_set_option_string (&mips_arch_string, arg);
13622 mips_set_option_string (&mips_arch_string, "4650");
13623 mips_set_option_string (&mips_tune_string, "4650");
13626 case OPTION_NO_M4650:
13630 mips_set_option_string (&mips_arch_string, "4010");
13631 mips_set_option_string (&mips_tune_string, "4010");
13634 case OPTION_NO_M4010:
13638 mips_set_option_string (&mips_arch_string, "4100");
13639 mips_set_option_string (&mips_tune_string, "4100");
13642 case OPTION_NO_M4100:
13646 mips_set_option_string (&mips_arch_string, "3900");
13647 mips_set_option_string (&mips_tune_string, "3900");
13650 case OPTION_NO_M3900:
13653 case OPTION_MICROMIPS:
13654 if (mips_opts.mips16 == 1)
13656 as_bad (_("-mmicromips cannot be used with -mips16"));
13659 mips_opts.micromips = 1;
13660 mips_no_prev_insn ();
13663 case OPTION_NO_MICROMIPS:
13664 mips_opts.micromips = 0;
13665 mips_no_prev_insn ();
13668 case OPTION_MIPS16:
13669 if (mips_opts.micromips == 1)
13671 as_bad (_("-mips16 cannot be used with -micromips"));
13674 mips_opts.mips16 = 1;
13675 mips_no_prev_insn ();
13678 case OPTION_NO_MIPS16:
13679 mips_opts.mips16 = 0;
13680 mips_no_prev_insn ();
13683 case OPTION_FIX_24K:
13687 case OPTION_NO_FIX_24K:
13691 case OPTION_FIX_LOONGSON2F_JUMP:
13692 mips_fix_loongson2f_jump = TRUE;
13695 case OPTION_NO_FIX_LOONGSON2F_JUMP:
13696 mips_fix_loongson2f_jump = FALSE;
13699 case OPTION_FIX_LOONGSON2F_NOP:
13700 mips_fix_loongson2f_nop = TRUE;
13703 case OPTION_NO_FIX_LOONGSON2F_NOP:
13704 mips_fix_loongson2f_nop = FALSE;
13707 case OPTION_FIX_VR4120:
13708 mips_fix_vr4120 = 1;
13711 case OPTION_NO_FIX_VR4120:
13712 mips_fix_vr4120 = 0;
13715 case OPTION_FIX_VR4130:
13716 mips_fix_vr4130 = 1;
13719 case OPTION_NO_FIX_VR4130:
13720 mips_fix_vr4130 = 0;
13723 case OPTION_FIX_CN63XXP1:
13724 mips_fix_cn63xxp1 = TRUE;
13727 case OPTION_NO_FIX_CN63XXP1:
13728 mips_fix_cn63xxp1 = FALSE;
13731 case OPTION_RELAX_BRANCH:
13732 mips_relax_branch = 1;
13735 case OPTION_NO_RELAX_BRANCH:
13736 mips_relax_branch = 0;
13739 case OPTION_INSN32:
13740 mips_opts.insn32 = TRUE;
13743 case OPTION_NO_INSN32:
13744 mips_opts.insn32 = FALSE;
13747 case OPTION_MSHARED:
13748 mips_in_shared = TRUE;
13751 case OPTION_MNO_SHARED:
13752 mips_in_shared = FALSE;
13755 case OPTION_MSYM32:
13756 mips_opts.sym32 = TRUE;
13759 case OPTION_MNO_SYM32:
13760 mips_opts.sym32 = FALSE;
13763 /* When generating ELF code, we permit -KPIC and -call_shared to
13764 select SVR4_PIC, and -non_shared to select no PIC. This is
13765 intended to be compatible with Irix 5. */
13766 case OPTION_CALL_SHARED:
13767 mips_pic = SVR4_PIC;
13768 mips_abicalls = TRUE;
13771 case OPTION_CALL_NONPIC:
13773 mips_abicalls = TRUE;
13776 case OPTION_NON_SHARED:
13778 mips_abicalls = FALSE;
13781 /* The -xgot option tells the assembler to use 32 bit offsets
13782 when accessing the got in SVR4_PIC mode. It is for Irix
13789 g_switch_value = atoi (arg);
13793 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
13796 mips_abi = O32_ABI;
13800 mips_abi = N32_ABI;
13804 mips_abi = N64_ABI;
13805 if (!support_64bit_objects())
13806 as_fatal (_("No compiled in support for 64 bit object file format"));
13810 file_mips_gp32 = 1;
13814 file_mips_gp32 = 0;
13818 file_mips_fp32 = 1;
13822 file_mips_fp32 = 0;
13825 case OPTION_SINGLE_FLOAT:
13826 file_mips_single_float = 1;
13829 case OPTION_DOUBLE_FLOAT:
13830 file_mips_single_float = 0;
13833 case OPTION_SOFT_FLOAT:
13834 file_mips_soft_float = 1;
13837 case OPTION_HARD_FLOAT:
13838 file_mips_soft_float = 0;
13842 if (strcmp (arg, "32") == 0)
13843 mips_abi = O32_ABI;
13844 else if (strcmp (arg, "o64") == 0)
13845 mips_abi = O64_ABI;
13846 else if (strcmp (arg, "n32") == 0)
13847 mips_abi = N32_ABI;
13848 else if (strcmp (arg, "64") == 0)
13850 mips_abi = N64_ABI;
13851 if (! support_64bit_objects())
13852 as_fatal (_("No compiled in support for 64 bit object file "
13855 else if (strcmp (arg, "eabi") == 0)
13856 mips_abi = EABI_ABI;
13859 as_fatal (_("invalid abi -mabi=%s"), arg);
13864 case OPTION_M7000_HILO_FIX:
13865 mips_7000_hilo_fix = TRUE;
13868 case OPTION_MNO_7000_HILO_FIX:
13869 mips_7000_hilo_fix = FALSE;
13872 case OPTION_MDEBUG:
13873 mips_flag_mdebug = TRUE;
13876 case OPTION_NO_MDEBUG:
13877 mips_flag_mdebug = FALSE;
13881 mips_flag_pdr = TRUE;
13884 case OPTION_NO_PDR:
13885 mips_flag_pdr = FALSE;
13888 case OPTION_MVXWORKS_PIC:
13889 mips_pic = VXWORKS_PIC;
13893 if (strcmp (arg, "2008") == 0)
13894 mips_flag_nan2008 = TRUE;
13895 else if (strcmp (arg, "legacy") == 0)
13896 mips_flag_nan2008 = FALSE;
13899 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
13908 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
13913 /* Set up globals to generate code for the ISA or processor
13914 described by INFO. */
13917 mips_set_architecture (const struct mips_cpu_info *info)
13921 file_mips_arch = info->cpu;
13922 mips_opts.arch = info->cpu;
13923 mips_opts.isa = info->isa;
13928 /* Likewise for tuning. */
13931 mips_set_tune (const struct mips_cpu_info *info)
13934 mips_tune = info->cpu;
13939 mips_after_parse_args (void)
13941 const struct mips_cpu_info *arch_info = 0;
13942 const struct mips_cpu_info *tune_info = 0;
13944 /* GP relative stuff not working for PE */
13945 if (strncmp (TARGET_OS, "pe", 2) == 0)
13947 if (g_switch_seen && g_switch_value != 0)
13948 as_bad (_("-G not supported in this configuration."));
13949 g_switch_value = 0;
13952 if (mips_abi == NO_ABI)
13953 mips_abi = MIPS_DEFAULT_ABI;
13955 /* The following code determines the architecture and register size.
13956 Similar code was added to GCC 3.3 (see override_options() in
13957 config/mips/mips.c). The GAS and GCC code should be kept in sync
13958 as much as possible. */
13960 if (mips_arch_string != 0)
13961 arch_info = mips_parse_cpu ("-march", mips_arch_string);
13963 if (file_mips_isa != ISA_UNKNOWN)
13965 /* Handle -mipsN. At this point, file_mips_isa contains the
13966 ISA level specified by -mipsN, while arch_info->isa contains
13967 the -march selection (if any). */
13968 if (arch_info != 0)
13970 /* -march takes precedence over -mipsN, since it is more descriptive.
13971 There's no harm in specifying both as long as the ISA levels
13973 if (file_mips_isa != arch_info->isa)
13974 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
13975 mips_cpu_info_from_isa (file_mips_isa)->name,
13976 mips_cpu_info_from_isa (arch_info->isa)->name);
13979 arch_info = mips_cpu_info_from_isa (file_mips_isa);
13982 if (arch_info == 0)
13984 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
13985 gas_assert (arch_info);
13988 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
13989 as_bad (_("-march=%s is not compatible with the selected ABI"),
13992 mips_set_architecture (arch_info);
13994 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
13995 if (mips_tune_string != 0)
13996 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
13998 if (tune_info == 0)
13999 mips_set_tune (arch_info);
14001 mips_set_tune (tune_info);
14003 if (file_mips_gp32 >= 0)
14005 /* The user specified the size of the integer registers. Make sure
14006 it agrees with the ABI and ISA. */
14007 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
14008 as_bad (_("-mgp64 used with a 32-bit processor"));
14009 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
14010 as_bad (_("-mgp32 used with a 64-bit ABI"));
14011 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
14012 as_bad (_("-mgp64 used with a 32-bit ABI"));
14016 /* Infer the integer register size from the ABI and processor.
14017 Restrict ourselves to 32-bit registers if that's all the
14018 processor has, or if the ABI cannot handle 64-bit registers. */
14019 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
14020 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
14023 switch (file_mips_fp32)
14027 /* No user specified float register size.
14028 ??? GAS treats single-float processors as though they had 64-bit
14029 float registers (although it complains when double-precision
14030 instructions are used). As things stand, saying they have 32-bit
14031 registers would lead to spurious "register must be even" messages.
14032 So here we assume float registers are never smaller than the
14034 if (file_mips_gp32 == 0)
14035 /* 64-bit integer registers implies 64-bit float registers. */
14036 file_mips_fp32 = 0;
14037 else if ((mips_opts.ase & FP64_ASES)
14038 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
14039 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
14040 file_mips_fp32 = 0;
14042 /* 32-bit float registers. */
14043 file_mips_fp32 = 1;
14046 /* The user specified the size of the float registers. Check if it
14047 agrees with the ABI and ISA. */
14049 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
14050 as_bad (_("-mfp64 used with a 32-bit fpu"));
14051 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
14052 && !ISA_HAS_MXHC1 (mips_opts.isa))
14053 as_warn (_("-mfp64 used with a 32-bit ABI"));
14056 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14057 as_warn (_("-mfp32 used with a 64-bit ABI"));
14061 /* End of GCC-shared inference code. */
14063 /* This flag is set when we have a 64-bit capable CPU but use only
14064 32-bit wide registers. Note that EABI does not use it. */
14065 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
14066 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
14067 || mips_abi == O32_ABI))
14068 mips_32bitmode = 1;
14070 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
14071 as_bad (_("trap exception not supported at ISA 1"));
14073 /* If the selected architecture includes support for ASEs, enable
14074 generation of code for them. */
14075 if (mips_opts.mips16 == -1)
14076 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
14077 if (mips_opts.micromips == -1)
14078 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
14080 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
14081 ASEs from being selected implicitly. */
14082 if (file_mips_fp32 == 1)
14083 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
14085 /* If the user didn't explicitly select or deselect a particular ASE,
14086 use the default setting for the CPU. */
14087 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
14089 file_mips_isa = mips_opts.isa;
14090 file_ase = mips_opts.ase;
14091 mips_opts.gp32 = file_mips_gp32;
14092 mips_opts.fp32 = file_mips_fp32;
14093 mips_opts.soft_float = file_mips_soft_float;
14094 mips_opts.single_float = file_mips_single_float;
14096 mips_check_isa_supports_ases ();
14098 if (mips_flag_mdebug < 0)
14099 mips_flag_mdebug = 0;
14103 mips_init_after_args (void)
14105 /* initialize opcodes */
14106 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
14107 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
14111 md_pcrel_from (fixS *fixP)
14113 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
14114 switch (fixP->fx_r_type)
14116 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14117 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14118 /* Return the address of the delay slot. */
14121 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14122 case BFD_RELOC_MICROMIPS_JMP:
14123 case BFD_RELOC_16_PCREL_S2:
14124 case BFD_RELOC_MIPS_JMP:
14125 /* Return the address of the delay slot. */
14128 case BFD_RELOC_32_PCREL:
14132 /* We have no relocation type for PC relative MIPS16 instructions. */
14133 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
14134 as_bad_where (fixP->fx_file, fixP->fx_line,
14135 _("PC relative MIPS16 instruction references a different section"));
14140 /* This is called before the symbol table is processed. In order to
14141 work with gcc when using mips-tfile, we must keep all local labels.
14142 However, in other cases, we want to discard them. If we were
14143 called with -g, but we didn't see any debugging information, it may
14144 mean that gcc is smuggling debugging information through to
14145 mips-tfile, in which case we must generate all local labels. */
14148 mips_frob_file_before_adjust (void)
14150 #ifndef NO_ECOFF_DEBUGGING
14151 if (ECOFF_DEBUGGING
14153 && ! ecoff_debugging_seen)
14154 flag_keep_locals = 1;
14158 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
14159 the corresponding LO16 reloc. This is called before md_apply_fix and
14160 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
14161 relocation operators.
14163 For our purposes, a %lo() expression matches a %got() or %hi()
14166 (a) it refers to the same symbol; and
14167 (b) the offset applied in the %lo() expression is no lower than
14168 the offset applied in the %got() or %hi().
14170 (b) allows us to cope with code like:
14173 lh $4,%lo(foo+2)($4)
14175 ...which is legal on RELA targets, and has a well-defined behaviour
14176 if the user knows that adding 2 to "foo" will not induce a carry to
14179 When several %lo()s match a particular %got() or %hi(), we use the
14180 following rules to distinguish them:
14182 (1) %lo()s with smaller offsets are a better match than %lo()s with
14185 (2) %lo()s with no matching %got() or %hi() are better than those
14186 that already have a matching %got() or %hi().
14188 (3) later %lo()s are better than earlier %lo()s.
14190 These rules are applied in order.
14192 (1) means, among other things, that %lo()s with identical offsets are
14193 chosen if they exist.
14195 (2) means that we won't associate several high-part relocations with
14196 the same low-part relocation unless there's no alternative. Having
14197 several high parts for the same low part is a GNU extension; this rule
14198 allows careful users to avoid it.
14200 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
14201 with the last high-part relocation being at the front of the list.
14202 It therefore makes sense to choose the last matching low-part
14203 relocation, all other things being equal. It's also easier
14204 to code that way. */
14207 mips_frob_file (void)
14209 struct mips_hi_fixup *l;
14210 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
14212 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
14214 segment_info_type *seginfo;
14215 bfd_boolean matched_lo_p;
14216 fixS **hi_pos, **lo_pos, **pos;
14218 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
14220 /* If a GOT16 relocation turns out to be against a global symbol,
14221 there isn't supposed to be a matching LO. Ignore %gots against
14222 constants; we'll report an error for those later. */
14223 if (got16_reloc_p (l->fixp->fx_r_type)
14224 && !(l->fixp->fx_addsy
14225 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
14228 /* Check quickly whether the next fixup happens to be a matching %lo. */
14229 if (fixup_has_matching_lo_p (l->fixp))
14232 seginfo = seg_info (l->seg);
14234 /* Set HI_POS to the position of this relocation in the chain.
14235 Set LO_POS to the position of the chosen low-part relocation.
14236 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
14237 relocation that matches an immediately-preceding high-part
14241 matched_lo_p = FALSE;
14242 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
14244 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
14246 if (*pos == l->fixp)
14249 if ((*pos)->fx_r_type == looking_for_rtype
14250 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
14251 && (*pos)->fx_offset >= l->fixp->fx_offset
14253 || (*pos)->fx_offset < (*lo_pos)->fx_offset
14255 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
14258 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
14259 && fixup_has_matching_lo_p (*pos));
14262 /* If we found a match, remove the high-part relocation from its
14263 current position and insert it before the low-part relocation.
14264 Make the offsets match so that fixup_has_matching_lo_p()
14267 We don't warn about unmatched high-part relocations since some
14268 versions of gcc have been known to emit dead "lui ...%hi(...)"
14270 if (lo_pos != NULL)
14272 l->fixp->fx_offset = (*lo_pos)->fx_offset;
14273 if (l->fixp->fx_next != *lo_pos)
14275 *hi_pos = l->fixp->fx_next;
14276 l->fixp->fx_next = *lo_pos;
14284 mips_force_relocation (fixS *fixp)
14286 if (generic_force_reloc (fixp))
14289 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
14290 so that the linker relaxation can update targets. */
14291 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14292 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14293 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
14299 /* Read the instruction associated with RELOC from BUF. */
14301 static unsigned int
14302 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
14304 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14305 return read_compressed_insn (buf, 4);
14307 return read_insn (buf);
14310 /* Write instruction INSN to BUF, given that it has been relocated
14314 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
14315 unsigned long insn)
14317 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
14318 write_compressed_insn (buf, insn, 4);
14320 write_insn (buf, insn);
14323 /* Apply a fixup to the object file. */
14326 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
14329 unsigned long insn;
14330 reloc_howto_type *howto;
14332 /* We ignore generic BFD relocations we don't know about. */
14333 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
14337 gas_assert (fixP->fx_size == 2
14338 || fixP->fx_size == 4
14339 || fixP->fx_r_type == BFD_RELOC_16
14340 || fixP->fx_r_type == BFD_RELOC_64
14341 || fixP->fx_r_type == BFD_RELOC_CTOR
14342 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
14343 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
14344 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14345 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
14346 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
14348 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
14350 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
14351 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
14352 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
14353 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
14354 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
14356 /* Don't treat parts of a composite relocation as done. There are two
14359 (1) The second and third parts will be against 0 (RSS_UNDEF) but
14360 should nevertheless be emitted if the first part is.
14362 (2) In normal usage, composite relocations are never assembly-time
14363 constants. The easiest way of dealing with the pathological
14364 exceptions is to generate a relocation against STN_UNDEF and
14365 leave everything up to the linker. */
14366 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
14369 switch (fixP->fx_r_type)
14371 case BFD_RELOC_MIPS_TLS_GD:
14372 case BFD_RELOC_MIPS_TLS_LDM:
14373 case BFD_RELOC_MIPS_TLS_DTPREL32:
14374 case BFD_RELOC_MIPS_TLS_DTPREL64:
14375 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
14376 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
14377 case BFD_RELOC_MIPS_TLS_GOTTPREL:
14378 case BFD_RELOC_MIPS_TLS_TPREL32:
14379 case BFD_RELOC_MIPS_TLS_TPREL64:
14380 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
14381 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
14382 case BFD_RELOC_MICROMIPS_TLS_GD:
14383 case BFD_RELOC_MICROMIPS_TLS_LDM:
14384 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
14385 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
14386 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
14387 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
14388 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
14389 case BFD_RELOC_MIPS16_TLS_GD:
14390 case BFD_RELOC_MIPS16_TLS_LDM:
14391 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
14392 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
14393 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
14394 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
14395 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
14396 if (!fixP->fx_addsy)
14398 as_bad_where (fixP->fx_file, fixP->fx_line,
14399 _("TLS relocation against a constant"));
14402 S_SET_THREAD_LOCAL (fixP->fx_addsy);
14405 case BFD_RELOC_MIPS_JMP:
14406 case BFD_RELOC_MIPS_SHIFT5:
14407 case BFD_RELOC_MIPS_SHIFT6:
14408 case BFD_RELOC_MIPS_GOT_DISP:
14409 case BFD_RELOC_MIPS_GOT_PAGE:
14410 case BFD_RELOC_MIPS_GOT_OFST:
14411 case BFD_RELOC_MIPS_SUB:
14412 case BFD_RELOC_MIPS_INSERT_A:
14413 case BFD_RELOC_MIPS_INSERT_B:
14414 case BFD_RELOC_MIPS_DELETE:
14415 case BFD_RELOC_MIPS_HIGHEST:
14416 case BFD_RELOC_MIPS_HIGHER:
14417 case BFD_RELOC_MIPS_SCN_DISP:
14418 case BFD_RELOC_MIPS_REL16:
14419 case BFD_RELOC_MIPS_RELGOT:
14420 case BFD_RELOC_MIPS_JALR:
14421 case BFD_RELOC_HI16:
14422 case BFD_RELOC_HI16_S:
14423 case BFD_RELOC_LO16:
14424 case BFD_RELOC_GPREL16:
14425 case BFD_RELOC_MIPS_LITERAL:
14426 case BFD_RELOC_MIPS_CALL16:
14427 case BFD_RELOC_MIPS_GOT16:
14428 case BFD_RELOC_GPREL32:
14429 case BFD_RELOC_MIPS_GOT_HI16:
14430 case BFD_RELOC_MIPS_GOT_LO16:
14431 case BFD_RELOC_MIPS_CALL_HI16:
14432 case BFD_RELOC_MIPS_CALL_LO16:
14433 case BFD_RELOC_MIPS16_GPREL:
14434 case BFD_RELOC_MIPS16_GOT16:
14435 case BFD_RELOC_MIPS16_CALL16:
14436 case BFD_RELOC_MIPS16_HI16:
14437 case BFD_RELOC_MIPS16_HI16_S:
14438 case BFD_RELOC_MIPS16_LO16:
14439 case BFD_RELOC_MIPS16_JMP:
14440 case BFD_RELOC_MICROMIPS_JMP:
14441 case BFD_RELOC_MICROMIPS_GOT_DISP:
14442 case BFD_RELOC_MICROMIPS_GOT_PAGE:
14443 case BFD_RELOC_MICROMIPS_GOT_OFST:
14444 case BFD_RELOC_MICROMIPS_SUB:
14445 case BFD_RELOC_MICROMIPS_HIGHEST:
14446 case BFD_RELOC_MICROMIPS_HIGHER:
14447 case BFD_RELOC_MICROMIPS_SCN_DISP:
14448 case BFD_RELOC_MICROMIPS_JALR:
14449 case BFD_RELOC_MICROMIPS_HI16:
14450 case BFD_RELOC_MICROMIPS_HI16_S:
14451 case BFD_RELOC_MICROMIPS_LO16:
14452 case BFD_RELOC_MICROMIPS_GPREL16:
14453 case BFD_RELOC_MICROMIPS_LITERAL:
14454 case BFD_RELOC_MICROMIPS_CALL16:
14455 case BFD_RELOC_MICROMIPS_GOT16:
14456 case BFD_RELOC_MICROMIPS_GOT_HI16:
14457 case BFD_RELOC_MICROMIPS_GOT_LO16:
14458 case BFD_RELOC_MICROMIPS_CALL_HI16:
14459 case BFD_RELOC_MICROMIPS_CALL_LO16:
14460 case BFD_RELOC_MIPS_EH:
14465 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
14467 insn = read_reloc_insn (buf, fixP->fx_r_type);
14468 if (mips16_reloc_p (fixP->fx_r_type))
14469 insn |= mips16_immed_extend (value, 16);
14471 insn |= (value & 0xffff);
14472 write_reloc_insn (buf, fixP->fx_r_type, insn);
14475 as_bad_where (fixP->fx_file, fixP->fx_line,
14476 _("Unsupported constant in relocation"));
14481 /* This is handled like BFD_RELOC_32, but we output a sign
14482 extended value if we are only 32 bits. */
14485 if (8 <= sizeof (valueT))
14486 md_number_to_chars (buf, *valP, 8);
14491 if ((*valP & 0x80000000) != 0)
14495 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
14496 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
14501 case BFD_RELOC_RVA:
14503 case BFD_RELOC_32_PCREL:
14505 /* If we are deleting this reloc entry, we must fill in the
14506 value now. This can happen if we have a .word which is not
14507 resolved when it appears but is later defined. */
14509 md_number_to_chars (buf, *valP, fixP->fx_size);
14512 case BFD_RELOC_16_PCREL_S2:
14513 if ((*valP & 0x3) != 0)
14514 as_bad_where (fixP->fx_file, fixP->fx_line,
14515 _("Branch to misaligned address (%lx)"), (long) *valP);
14517 /* We need to save the bits in the instruction since fixup_segment()
14518 might be deleting the relocation entry (i.e., a branch within
14519 the current segment). */
14520 if (! fixP->fx_done)
14523 /* Update old instruction data. */
14524 insn = read_insn (buf);
14526 if (*valP + 0x20000 <= 0x3ffff)
14528 insn |= (*valP >> 2) & 0xffff;
14529 write_insn (buf, insn);
14531 else if (mips_pic == NO_PIC
14533 && fixP->fx_frag->fr_address >= text_section->vma
14534 && (fixP->fx_frag->fr_address
14535 < text_section->vma + bfd_get_section_size (text_section))
14536 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
14537 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
14538 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
14540 /* The branch offset is too large. If this is an
14541 unconditional branch, and we are not generating PIC code,
14542 we can convert it to an absolute jump instruction. */
14543 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
14544 insn = 0x0c000000; /* jal */
14546 insn = 0x08000000; /* j */
14547 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
14549 fixP->fx_addsy = section_symbol (text_section);
14550 *valP += md_pcrel_from (fixP);
14551 write_insn (buf, insn);
14555 /* If we got here, we have branch-relaxation disabled,
14556 and there's nothing we can do to fix this instruction
14557 without turning it into a longer sequence. */
14558 as_bad_where (fixP->fx_file, fixP->fx_line,
14559 _("Branch out of range"));
14563 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
14564 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
14565 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
14566 /* We adjust the offset back to even. */
14567 if ((*valP & 0x1) != 0)
14570 if (! fixP->fx_done)
14573 /* Should never visit here, because we keep the relocation. */
14577 case BFD_RELOC_VTABLE_INHERIT:
14580 && !S_IS_DEFINED (fixP->fx_addsy)
14581 && !S_IS_WEAK (fixP->fx_addsy))
14582 S_SET_WEAK (fixP->fx_addsy);
14585 case BFD_RELOC_VTABLE_ENTRY:
14593 /* Remember value for tc_gen_reloc. */
14594 fixP->fx_addnumber = *valP;
14604 name = input_line_pointer;
14605 c = get_symbol_end ();
14606 p = (symbolS *) symbol_find_or_make (name);
14607 *input_line_pointer = c;
14611 /* Align the current frag to a given power of two. If a particular
14612 fill byte should be used, FILL points to an integer that contains
14613 that byte, otherwise FILL is null.
14615 This function used to have the comment:
14617 The MIPS assembler also automatically adjusts any preceding label.
14619 The implementation therefore applied the adjustment to a maximum of
14620 one label. However, other label adjustments are applied to batches
14621 of labels, and adjusting just one caused problems when new labels
14622 were added for the sake of debugging or unwind information.
14623 We therefore adjust all preceding labels (given as LABELS) instead. */
14626 mips_align (int to, int *fill, struct insn_label_list *labels)
14628 mips_emit_delays ();
14629 mips_record_compressed_mode ();
14630 if (fill == NULL && subseg_text_p (now_seg))
14631 frag_align_code (to, 0);
14633 frag_align (to, fill ? *fill : 0, 0);
14634 record_alignment (now_seg, to);
14635 mips_move_labels (labels, FALSE);
14638 /* Align to a given power of two. .align 0 turns off the automatic
14639 alignment used by the data creating pseudo-ops. */
14642 s_align (int x ATTRIBUTE_UNUSED)
14644 int temp, fill_value, *fill_ptr;
14645 long max_alignment = 28;
14647 /* o Note that the assembler pulls down any immediately preceding label
14648 to the aligned address.
14649 o It's not documented but auto alignment is reinstated by
14650 a .align pseudo instruction.
14651 o Note also that after auto alignment is turned off the mips assembler
14652 issues an error on attempt to assemble an improperly aligned data item.
14655 temp = get_absolute_expression ();
14656 if (temp > max_alignment)
14657 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
14660 as_warn (_("Alignment negative: 0 assumed."));
14663 if (*input_line_pointer == ',')
14665 ++input_line_pointer;
14666 fill_value = get_absolute_expression ();
14667 fill_ptr = &fill_value;
14673 segment_info_type *si = seg_info (now_seg);
14674 struct insn_label_list *l = si->label_list;
14675 /* Auto alignment should be switched on by next section change. */
14677 mips_align (temp, fill_ptr, l);
14684 demand_empty_rest_of_line ();
14688 s_change_sec (int sec)
14692 /* The ELF backend needs to know that we are changing sections, so
14693 that .previous works correctly. We could do something like check
14694 for an obj_section_change_hook macro, but that might be confusing
14695 as it would not be appropriate to use it in the section changing
14696 functions in read.c, since obj-elf.c intercepts those. FIXME:
14697 This should be cleaner, somehow. */
14698 obj_elf_section_change_hook ();
14700 mips_emit_delays ();
14711 subseg_set (bss_section, (subsegT) get_absolute_expression ());
14712 demand_empty_rest_of_line ();
14716 seg = subseg_new (RDATA_SECTION_NAME,
14717 (subsegT) get_absolute_expression ());
14718 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
14719 | SEC_READONLY | SEC_RELOC
14721 if (strncmp (TARGET_OS, "elf", 3) != 0)
14722 record_alignment (seg, 4);
14723 demand_empty_rest_of_line ();
14727 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
14728 bfd_set_section_flags (stdoutput, seg,
14729 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
14730 if (strncmp (TARGET_OS, "elf", 3) != 0)
14731 record_alignment (seg, 4);
14732 demand_empty_rest_of_line ();
14736 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
14737 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
14738 if (strncmp (TARGET_OS, "elf", 3) != 0)
14739 record_alignment (seg, 4);
14740 demand_empty_rest_of_line ();
14748 s_change_section (int ignore ATTRIBUTE_UNUSED)
14750 char *section_name;
14755 int section_entry_size;
14756 int section_alignment;
14758 section_name = input_line_pointer;
14759 c = get_symbol_end ();
14761 next_c = *(input_line_pointer + 1);
14763 /* Do we have .section Name<,"flags">? */
14764 if (c != ',' || (c == ',' && next_c == '"'))
14766 /* just after name is now '\0'. */
14767 *input_line_pointer = c;
14768 input_line_pointer = section_name;
14769 obj_elf_section (ignore);
14772 input_line_pointer++;
14774 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
14776 section_type = get_absolute_expression ();
14779 if (*input_line_pointer++ == ',')
14780 section_flag = get_absolute_expression ();
14783 if (*input_line_pointer++ == ',')
14784 section_entry_size = get_absolute_expression ();
14786 section_entry_size = 0;
14787 if (*input_line_pointer++ == ',')
14788 section_alignment = get_absolute_expression ();
14790 section_alignment = 0;
14791 /* FIXME: really ignore? */
14792 (void) section_alignment;
14794 section_name = xstrdup (section_name);
14796 /* When using the generic form of .section (as implemented by obj-elf.c),
14797 there's no way to set the section type to SHT_MIPS_DWARF. Users have
14798 traditionally had to fall back on the more common @progbits instead.
14800 There's nothing really harmful in this, since bfd will correct
14801 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
14802 means that, for backwards compatibility, the special_section entries
14803 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
14805 Even so, we shouldn't force users of the MIPS .section syntax to
14806 incorrectly label the sections as SHT_PROGBITS. The best compromise
14807 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
14808 generic type-checking code. */
14809 if (section_type == SHT_MIPS_DWARF)
14810 section_type = SHT_PROGBITS;
14812 obj_elf_change_section (section_name, section_type, section_flag,
14813 section_entry_size, 0, 0, 0);
14815 if (now_seg->name != section_name)
14816 free (section_name);
14820 mips_enable_auto_align (void)
14826 s_cons (int log_size)
14828 segment_info_type *si = seg_info (now_seg);
14829 struct insn_label_list *l = si->label_list;
14831 mips_emit_delays ();
14832 if (log_size > 0 && auto_align)
14833 mips_align (log_size, 0, l);
14834 cons (1 << log_size);
14835 mips_clear_insn_labels ();
14839 s_float_cons (int type)
14841 segment_info_type *si = seg_info (now_seg);
14842 struct insn_label_list *l = si->label_list;
14844 mips_emit_delays ();
14849 mips_align (3, 0, l);
14851 mips_align (2, 0, l);
14855 mips_clear_insn_labels ();
14858 /* Handle .globl. We need to override it because on Irix 5 you are
14861 where foo is an undefined symbol, to mean that foo should be
14862 considered to be the address of a function. */
14865 s_mips_globl (int x ATTRIBUTE_UNUSED)
14874 name = input_line_pointer;
14875 c = get_symbol_end ();
14876 symbolP = symbol_find_or_make (name);
14877 S_SET_EXTERNAL (symbolP);
14879 *input_line_pointer = c;
14880 SKIP_WHITESPACE ();
14882 /* On Irix 5, every global symbol that is not explicitly labelled as
14883 being a function is apparently labelled as being an object. */
14886 if (!is_end_of_line[(unsigned char) *input_line_pointer]
14887 && (*input_line_pointer != ','))
14892 secname = input_line_pointer;
14893 c = get_symbol_end ();
14894 sec = bfd_get_section_by_name (stdoutput, secname);
14896 as_bad (_("%s: no such section"), secname);
14897 *input_line_pointer = c;
14899 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
14900 flag = BSF_FUNCTION;
14903 symbol_get_bfdsym (symbolP)->flags |= flag;
14905 c = *input_line_pointer;
14908 input_line_pointer++;
14909 SKIP_WHITESPACE ();
14910 if (is_end_of_line[(unsigned char) *input_line_pointer])
14916 demand_empty_rest_of_line ();
14920 s_option (int x ATTRIBUTE_UNUSED)
14925 opt = input_line_pointer;
14926 c = get_symbol_end ();
14930 /* FIXME: What does this mean? */
14932 else if (strncmp (opt, "pic", 3) == 0)
14936 i = atoi (opt + 3);
14941 mips_pic = SVR4_PIC;
14942 mips_abicalls = TRUE;
14945 as_bad (_(".option pic%d not supported"), i);
14947 if (mips_pic == SVR4_PIC)
14949 if (g_switch_seen && g_switch_value != 0)
14950 as_warn (_("-G may not be used with SVR4 PIC code"));
14951 g_switch_value = 0;
14952 bfd_set_gp_size (stdoutput, 0);
14956 as_warn (_("Unrecognized option \"%s\""), opt);
14958 *input_line_pointer = c;
14959 demand_empty_rest_of_line ();
14962 /* This structure is used to hold a stack of .set values. */
14964 struct mips_option_stack
14966 struct mips_option_stack *next;
14967 struct mips_set_options options;
14970 static struct mips_option_stack *mips_opts_stack;
14972 /* Handle the .set pseudo-op. */
14975 s_mipsset (int x ATTRIBUTE_UNUSED)
14977 char *name = input_line_pointer, ch;
14978 const struct mips_ase *ase;
14980 while (!is_end_of_line[(unsigned char) *input_line_pointer])
14981 ++input_line_pointer;
14982 ch = *input_line_pointer;
14983 *input_line_pointer = '\0';
14985 if (strcmp (name, "reorder") == 0)
14987 if (mips_opts.noreorder)
14990 else if (strcmp (name, "noreorder") == 0)
14992 if (!mips_opts.noreorder)
14993 start_noreorder ();
14995 else if (strncmp (name, "at=", 3) == 0)
14997 char *s = name + 3;
14999 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
15000 as_bad (_("Unrecognized register name `%s'"), s);
15002 else if (strcmp (name, "at") == 0)
15004 mips_opts.at = ATREG;
15006 else if (strcmp (name, "noat") == 0)
15008 mips_opts.at = ZERO;
15010 else if (strcmp (name, "macro") == 0)
15012 mips_opts.warn_about_macros = 0;
15014 else if (strcmp (name, "nomacro") == 0)
15016 if (mips_opts.noreorder == 0)
15017 as_bad (_("`noreorder' must be set before `nomacro'"));
15018 mips_opts.warn_about_macros = 1;
15020 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
15022 mips_opts.nomove = 0;
15024 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
15026 mips_opts.nomove = 1;
15028 else if (strcmp (name, "bopt") == 0)
15030 mips_opts.nobopt = 0;
15032 else if (strcmp (name, "nobopt") == 0)
15034 mips_opts.nobopt = 1;
15036 else if (strcmp (name, "gp=default") == 0)
15037 mips_opts.gp32 = file_mips_gp32;
15038 else if (strcmp (name, "gp=32") == 0)
15039 mips_opts.gp32 = 1;
15040 else if (strcmp (name, "gp=64") == 0)
15042 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
15043 as_warn (_("%s isa does not support 64-bit registers"),
15044 mips_cpu_info_from_isa (mips_opts.isa)->name);
15045 mips_opts.gp32 = 0;
15047 else if (strcmp (name, "fp=default") == 0)
15048 mips_opts.fp32 = file_mips_fp32;
15049 else if (strcmp (name, "fp=32") == 0)
15050 mips_opts.fp32 = 1;
15051 else if (strcmp (name, "fp=64") == 0)
15053 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15054 as_warn (_("%s isa does not support 64-bit floating point registers"),
15055 mips_cpu_info_from_isa (mips_opts.isa)->name);
15056 mips_opts.fp32 = 0;
15058 else if (strcmp (name, "softfloat") == 0)
15059 mips_opts.soft_float = 1;
15060 else if (strcmp (name, "hardfloat") == 0)
15061 mips_opts.soft_float = 0;
15062 else if (strcmp (name, "singlefloat") == 0)
15063 mips_opts.single_float = 1;
15064 else if (strcmp (name, "doublefloat") == 0)
15065 mips_opts.single_float = 0;
15066 else if (strcmp (name, "mips16") == 0
15067 || strcmp (name, "MIPS-16") == 0)
15069 if (mips_opts.micromips == 1)
15070 as_fatal (_("`mips16' cannot be used with `micromips'"));
15071 mips_opts.mips16 = 1;
15073 else if (strcmp (name, "nomips16") == 0
15074 || strcmp (name, "noMIPS-16") == 0)
15075 mips_opts.mips16 = 0;
15076 else if (strcmp (name, "micromips") == 0)
15078 if (mips_opts.mips16 == 1)
15079 as_fatal (_("`micromips' cannot be used with `mips16'"));
15080 mips_opts.micromips = 1;
15082 else if (strcmp (name, "nomicromips") == 0)
15083 mips_opts.micromips = 0;
15084 else if (name[0] == 'n'
15086 && (ase = mips_lookup_ase (name + 2)))
15087 mips_set_ase (ase, FALSE);
15088 else if ((ase = mips_lookup_ase (name)))
15089 mips_set_ase (ase, TRUE);
15090 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
15094 /* Permit the user to change the ISA and architecture on the fly.
15095 Needless to say, misuse can cause serious problems. */
15096 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
15099 mips_opts.isa = file_mips_isa;
15100 mips_opts.arch = file_mips_arch;
15102 else if (strncmp (name, "arch=", 5) == 0)
15104 const struct mips_cpu_info *p;
15106 p = mips_parse_cpu("internal use", name + 5);
15108 as_bad (_("unknown architecture %s"), name + 5);
15111 mips_opts.arch = p->cpu;
15112 mips_opts.isa = p->isa;
15115 else if (strncmp (name, "mips", 4) == 0)
15117 const struct mips_cpu_info *p;
15119 p = mips_parse_cpu("internal use", name);
15121 as_bad (_("unknown ISA level %s"), name + 4);
15124 mips_opts.arch = p->cpu;
15125 mips_opts.isa = p->isa;
15129 as_bad (_("unknown ISA or architecture %s"), name);
15131 switch (mips_opts.isa)
15139 mips_opts.gp32 = 1;
15140 mips_opts.fp32 = 1;
15147 mips_opts.gp32 = 0;
15148 if (mips_opts.arch == CPU_R5900)
15150 mips_opts.fp32 = 1;
15154 mips_opts.fp32 = 0;
15158 as_bad (_("unknown ISA level %s"), name + 4);
15163 mips_opts.gp32 = file_mips_gp32;
15164 mips_opts.fp32 = file_mips_fp32;
15167 else if (strcmp (name, "autoextend") == 0)
15168 mips_opts.noautoextend = 0;
15169 else if (strcmp (name, "noautoextend") == 0)
15170 mips_opts.noautoextend = 1;
15171 else if (strcmp (name, "insn32") == 0)
15172 mips_opts.insn32 = TRUE;
15173 else if (strcmp (name, "noinsn32") == 0)
15174 mips_opts.insn32 = FALSE;
15175 else if (strcmp (name, "push") == 0)
15177 struct mips_option_stack *s;
15179 s = (struct mips_option_stack *) xmalloc (sizeof *s);
15180 s->next = mips_opts_stack;
15181 s->options = mips_opts;
15182 mips_opts_stack = s;
15184 else if (strcmp (name, "pop") == 0)
15186 struct mips_option_stack *s;
15188 s = mips_opts_stack;
15190 as_bad (_(".set pop with no .set push"));
15193 /* If we're changing the reorder mode we need to handle
15194 delay slots correctly. */
15195 if (s->options.noreorder && ! mips_opts.noreorder)
15196 start_noreorder ();
15197 else if (! s->options.noreorder && mips_opts.noreorder)
15200 mips_opts = s->options;
15201 mips_opts_stack = s->next;
15205 else if (strcmp (name, "sym32") == 0)
15206 mips_opts.sym32 = TRUE;
15207 else if (strcmp (name, "nosym32") == 0)
15208 mips_opts.sym32 = FALSE;
15209 else if (strchr (name, ','))
15211 /* Generic ".set" directive; use the generic handler. */
15212 *input_line_pointer = ch;
15213 input_line_pointer = name;
15219 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
15221 mips_check_isa_supports_ases ();
15222 *input_line_pointer = ch;
15223 demand_empty_rest_of_line ();
15226 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
15227 .option pic2. It means to generate SVR4 PIC calls. */
15230 s_abicalls (int ignore ATTRIBUTE_UNUSED)
15232 mips_pic = SVR4_PIC;
15233 mips_abicalls = TRUE;
15235 if (g_switch_seen && g_switch_value != 0)
15236 as_warn (_("-G may not be used with SVR4 PIC code"));
15237 g_switch_value = 0;
15239 bfd_set_gp_size (stdoutput, 0);
15240 demand_empty_rest_of_line ();
15243 /* Handle the .cpload pseudo-op. This is used when generating SVR4
15244 PIC code. It sets the $gp register for the function based on the
15245 function address, which is in the register named in the argument.
15246 This uses a relocation against _gp_disp, which is handled specially
15247 by the linker. The result is:
15248 lui $gp,%hi(_gp_disp)
15249 addiu $gp,$gp,%lo(_gp_disp)
15250 addu $gp,$gp,.cpload argument
15251 The .cpload argument is normally $25 == $t9.
15253 The -mno-shared option changes this to:
15254 lui $gp,%hi(__gnu_local_gp)
15255 addiu $gp,$gp,%lo(__gnu_local_gp)
15256 and the argument is ignored. This saves an instruction, but the
15257 resulting code is not position independent; it uses an absolute
15258 address for __gnu_local_gp. Thus code assembled with -mno-shared
15259 can go into an ordinary executable, but not into a shared library. */
15262 s_cpload (int ignore ATTRIBUTE_UNUSED)
15268 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15269 .cpload is ignored. */
15270 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15276 if (mips_opts.mips16)
15278 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
15279 ignore_rest_of_line ();
15283 /* .cpload should be in a .set noreorder section. */
15284 if (mips_opts.noreorder == 0)
15285 as_warn (_(".cpload not in noreorder section"));
15287 reg = tc_get_register (0);
15289 /* If we need to produce a 64-bit address, we are better off using
15290 the default instruction sequence. */
15291 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
15293 ex.X_op = O_symbol;
15294 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
15296 ex.X_op_symbol = NULL;
15297 ex.X_add_number = 0;
15299 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15300 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15302 mips_mark_labels ();
15303 mips_assembling_insn = TRUE;
15306 macro_build_lui (&ex, mips_gp_register);
15307 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15308 mips_gp_register, BFD_RELOC_LO16);
15310 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
15311 mips_gp_register, reg);
15314 mips_assembling_insn = FALSE;
15315 demand_empty_rest_of_line ();
15318 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
15319 .cpsetup $reg1, offset|$reg2, label
15321 If offset is given, this results in:
15322 sd $gp, offset($sp)
15323 lui $gp, %hi(%neg(%gp_rel(label)))
15324 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15325 daddu $gp, $gp, $reg1
15327 If $reg2 is given, this results in:
15328 daddu $reg2, $gp, $0
15329 lui $gp, %hi(%neg(%gp_rel(label)))
15330 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
15331 daddu $gp, $gp, $reg1
15332 $reg1 is normally $25 == $t9.
15334 The -mno-shared option replaces the last three instructions with
15336 addiu $gp,$gp,%lo(_gp) */
15339 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
15341 expressionS ex_off;
15342 expressionS ex_sym;
15345 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
15346 We also need NewABI support. */
15347 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15353 if (mips_opts.mips16)
15355 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
15356 ignore_rest_of_line ();
15360 reg1 = tc_get_register (0);
15361 SKIP_WHITESPACE ();
15362 if (*input_line_pointer != ',')
15364 as_bad (_("missing argument separator ',' for .cpsetup"));
15368 ++input_line_pointer;
15369 SKIP_WHITESPACE ();
15370 if (*input_line_pointer == '$')
15372 mips_cpreturn_register = tc_get_register (0);
15373 mips_cpreturn_offset = -1;
15377 mips_cpreturn_offset = get_absolute_expression ();
15378 mips_cpreturn_register = -1;
15380 SKIP_WHITESPACE ();
15381 if (*input_line_pointer != ',')
15383 as_bad (_("missing argument separator ',' for .cpsetup"));
15387 ++input_line_pointer;
15388 SKIP_WHITESPACE ();
15389 expression (&ex_sym);
15391 mips_mark_labels ();
15392 mips_assembling_insn = TRUE;
15395 if (mips_cpreturn_register == -1)
15397 ex_off.X_op = O_constant;
15398 ex_off.X_add_symbol = NULL;
15399 ex_off.X_op_symbol = NULL;
15400 ex_off.X_add_number = mips_cpreturn_offset;
15402 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
15403 BFD_RELOC_LO16, SP);
15406 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
15407 mips_gp_register, 0);
15409 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
15411 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
15412 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
15415 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
15416 mips_gp_register, -1, BFD_RELOC_GPREL16,
15417 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
15419 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
15420 mips_gp_register, reg1);
15426 ex.X_op = O_symbol;
15427 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
15428 ex.X_op_symbol = NULL;
15429 ex.X_add_number = 0;
15431 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
15432 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
15434 macro_build_lui (&ex, mips_gp_register);
15435 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
15436 mips_gp_register, BFD_RELOC_LO16);
15441 mips_assembling_insn = FALSE;
15442 demand_empty_rest_of_line ();
15446 s_cplocal (int ignore ATTRIBUTE_UNUSED)
15448 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
15449 .cplocal is ignored. */
15450 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15456 if (mips_opts.mips16)
15458 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
15459 ignore_rest_of_line ();
15463 mips_gp_register = tc_get_register (0);
15464 demand_empty_rest_of_line ();
15467 /* Handle the .cprestore pseudo-op. This stores $gp into a given
15468 offset from $sp. The offset is remembered, and after making a PIC
15469 call $gp is restored from that location. */
15472 s_cprestore (int ignore ATTRIBUTE_UNUSED)
15476 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
15477 .cprestore is ignored. */
15478 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
15484 if (mips_opts.mips16)
15486 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
15487 ignore_rest_of_line ();
15491 mips_cprestore_offset = get_absolute_expression ();
15492 mips_cprestore_valid = 1;
15494 ex.X_op = O_constant;
15495 ex.X_add_symbol = NULL;
15496 ex.X_op_symbol = NULL;
15497 ex.X_add_number = mips_cprestore_offset;
15499 mips_mark_labels ();
15500 mips_assembling_insn = TRUE;
15503 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
15504 SP, HAVE_64BIT_ADDRESSES);
15507 mips_assembling_insn = FALSE;
15508 demand_empty_rest_of_line ();
15511 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
15512 was given in the preceding .cpsetup, it results in:
15513 ld $gp, offset($sp)
15515 If a register $reg2 was given there, it results in:
15516 daddu $gp, $reg2, $0 */
15519 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
15523 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
15524 We also need NewABI support. */
15525 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15531 if (mips_opts.mips16)
15533 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
15534 ignore_rest_of_line ();
15538 mips_mark_labels ();
15539 mips_assembling_insn = TRUE;
15542 if (mips_cpreturn_register == -1)
15544 ex.X_op = O_constant;
15545 ex.X_add_symbol = NULL;
15546 ex.X_op_symbol = NULL;
15547 ex.X_add_number = mips_cpreturn_offset;
15549 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
15552 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
15553 mips_cpreturn_register, 0);
15556 mips_assembling_insn = FALSE;
15557 demand_empty_rest_of_line ();
15560 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
15561 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
15562 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
15563 debug information or MIPS16 TLS. */
15566 s_tls_rel_directive (const size_t bytes, const char *dirstr,
15567 bfd_reloc_code_real_type rtype)
15574 if (ex.X_op != O_symbol)
15576 as_bad (_("Unsupported use of %s"), dirstr);
15577 ignore_rest_of_line ();
15580 p = frag_more (bytes);
15581 md_number_to_chars (p, 0, bytes);
15582 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
15583 demand_empty_rest_of_line ();
15584 mips_clear_insn_labels ();
15587 /* Handle .dtprelword. */
15590 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
15592 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
15595 /* Handle .dtpreldword. */
15598 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
15600 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
15603 /* Handle .tprelword. */
15606 s_tprelword (int ignore ATTRIBUTE_UNUSED)
15608 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
15611 /* Handle .tpreldword. */
15614 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
15616 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
15619 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
15620 code. It sets the offset to use in gp_rel relocations. */
15623 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
15625 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
15626 We also need NewABI support. */
15627 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
15633 mips_gprel_offset = get_absolute_expression ();
15635 demand_empty_rest_of_line ();
15638 /* Handle the .gpword pseudo-op. This is used when generating PIC
15639 code. It generates a 32 bit GP relative reloc. */
15642 s_gpword (int ignore ATTRIBUTE_UNUSED)
15644 segment_info_type *si;
15645 struct insn_label_list *l;
15649 /* When not generating PIC code, this is treated as .word. */
15650 if (mips_pic != SVR4_PIC)
15656 si = seg_info (now_seg);
15657 l = si->label_list;
15658 mips_emit_delays ();
15660 mips_align (2, 0, l);
15663 mips_clear_insn_labels ();
15665 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15667 as_bad (_("Unsupported use of .gpword"));
15668 ignore_rest_of_line ();
15672 md_number_to_chars (p, 0, 4);
15673 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15674 BFD_RELOC_GPREL32);
15676 demand_empty_rest_of_line ();
15680 s_gpdword (int ignore ATTRIBUTE_UNUSED)
15682 segment_info_type *si;
15683 struct insn_label_list *l;
15687 /* When not generating PIC code, this is treated as .dword. */
15688 if (mips_pic != SVR4_PIC)
15694 si = seg_info (now_seg);
15695 l = si->label_list;
15696 mips_emit_delays ();
15698 mips_align (3, 0, l);
15701 mips_clear_insn_labels ();
15703 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15705 as_bad (_("Unsupported use of .gpdword"));
15706 ignore_rest_of_line ();
15710 md_number_to_chars (p, 0, 8);
15711 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15712 BFD_RELOC_GPREL32)->fx_tcbit = 1;
15714 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
15715 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
15716 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
15718 demand_empty_rest_of_line ();
15721 /* Handle the .ehword pseudo-op. This is used when generating unwinding
15722 tables. It generates a R_MIPS_EH reloc. */
15725 s_ehword (int ignore ATTRIBUTE_UNUSED)
15730 mips_emit_delays ();
15733 mips_clear_insn_labels ();
15735 if (ex.X_op != O_symbol || ex.X_add_number != 0)
15737 as_bad (_("Unsupported use of .ehword"));
15738 ignore_rest_of_line ();
15742 md_number_to_chars (p, 0, 4);
15743 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
15744 BFD_RELOC_MIPS_EH);
15746 demand_empty_rest_of_line ();
15749 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
15750 tables in SVR4 PIC code. */
15753 s_cpadd (int ignore ATTRIBUTE_UNUSED)
15757 /* This is ignored when not generating SVR4 PIC code. */
15758 if (mips_pic != SVR4_PIC)
15764 mips_mark_labels ();
15765 mips_assembling_insn = TRUE;
15767 /* Add $gp to the register named as an argument. */
15769 reg = tc_get_register (0);
15770 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
15773 mips_assembling_insn = FALSE;
15774 demand_empty_rest_of_line ();
15777 /* Handle the .insn pseudo-op. This marks instruction labels in
15778 mips16/micromips mode. This permits the linker to handle them specially,
15779 such as generating jalx instructions when needed. We also make
15780 them odd for the duration of the assembly, in order to generate the
15781 right sort of code. We will make them even in the adjust_symtab
15782 routine, while leaving them marked. This is convenient for the
15783 debugger and the disassembler. The linker knows to make them odd
15787 s_insn (int ignore ATTRIBUTE_UNUSED)
15789 mips_mark_labels ();
15791 demand_empty_rest_of_line ();
15794 /* Handle the .nan pseudo-op. */
15797 s_nan (int ignore ATTRIBUTE_UNUSED)
15799 static const char str_legacy[] = "legacy";
15800 static const char str_2008[] = "2008";
15803 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
15805 if (i == sizeof (str_2008) - 1
15806 && memcmp (input_line_pointer, str_2008, i) == 0)
15807 mips_flag_nan2008 = TRUE;
15808 else if (i == sizeof (str_legacy) - 1
15809 && memcmp (input_line_pointer, str_legacy, i) == 0)
15810 mips_flag_nan2008 = FALSE;
15812 as_bad (_("Bad .nan directive"));
15814 input_line_pointer += i;
15815 demand_empty_rest_of_line ();
15818 /* Handle a .stab[snd] directive. Ideally these directives would be
15819 implemented in a transparent way, so that removing them would not
15820 have any effect on the generated instructions. However, s_stab
15821 internally changes the section, so in practice we need to decide
15822 now whether the preceding label marks compressed code. We do not
15823 support changing the compression mode of a label after a .stab*
15824 directive, such as in:
15830 so the current mode wins. */
15833 s_mips_stab (int type)
15835 mips_mark_labels ();
15839 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
15842 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
15849 name = input_line_pointer;
15850 c = get_symbol_end ();
15851 symbolP = symbol_find_or_make (name);
15852 S_SET_WEAK (symbolP);
15853 *input_line_pointer = c;
15855 SKIP_WHITESPACE ();
15857 if (! is_end_of_line[(unsigned char) *input_line_pointer])
15859 if (S_IS_DEFINED (symbolP))
15861 as_bad (_("ignoring attempt to redefine symbol %s"),
15862 S_GET_NAME (symbolP));
15863 ignore_rest_of_line ();
15867 if (*input_line_pointer == ',')
15869 ++input_line_pointer;
15870 SKIP_WHITESPACE ();
15874 if (exp.X_op != O_symbol)
15876 as_bad (_("bad .weakext directive"));
15877 ignore_rest_of_line ();
15880 symbol_set_value_expression (symbolP, &exp);
15883 demand_empty_rest_of_line ();
15886 /* Parse a register string into a number. Called from the ECOFF code
15887 to parse .frame. The argument is non-zero if this is the frame
15888 register, so that we can record it in mips_frame_reg. */
15891 tc_get_register (int frame)
15895 SKIP_WHITESPACE ();
15896 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
15900 mips_frame_reg = reg != 0 ? reg : SP;
15901 mips_frame_reg_valid = 1;
15902 mips_cprestore_valid = 0;
15908 md_section_align (asection *seg, valueT addr)
15910 int align = bfd_get_section_alignment (stdoutput, seg);
15912 /* We don't need to align ELF sections to the full alignment.
15913 However, Irix 5 may prefer that we align them at least to a 16
15914 byte boundary. We don't bother to align the sections if we
15915 are targeted for an embedded system. */
15916 if (strncmp (TARGET_OS, "elf", 3) == 0)
15921 return ((addr + (1 << align) - 1) & (-1 << align));
15924 /* Utility routine, called from above as well. If called while the
15925 input file is still being read, it's only an approximation. (For
15926 example, a symbol may later become defined which appeared to be
15927 undefined earlier.) */
15930 nopic_need_relax (symbolS *sym, int before_relaxing)
15935 if (g_switch_value > 0)
15937 const char *symname;
15940 /* Find out whether this symbol can be referenced off the $gp
15941 register. It can be if it is smaller than the -G size or if
15942 it is in the .sdata or .sbss section. Certain symbols can
15943 not be referenced off the $gp, although it appears as though
15945 symname = S_GET_NAME (sym);
15946 if (symname != (const char *) NULL
15947 && (strcmp (symname, "eprol") == 0
15948 || strcmp (symname, "etext") == 0
15949 || strcmp (symname, "_gp") == 0
15950 || strcmp (symname, "edata") == 0
15951 || strcmp (symname, "_fbss") == 0
15952 || strcmp (symname, "_fdata") == 0
15953 || strcmp (symname, "_ftext") == 0
15954 || strcmp (symname, "end") == 0
15955 || strcmp (symname, "_gp_disp") == 0))
15957 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
15959 #ifndef NO_ECOFF_DEBUGGING
15960 || (symbol_get_obj (sym)->ecoff_extern_size != 0
15961 && (symbol_get_obj (sym)->ecoff_extern_size
15962 <= g_switch_value))
15964 /* We must defer this decision until after the whole
15965 file has been read, since there might be a .extern
15966 after the first use of this symbol. */
15967 || (before_relaxing
15968 #ifndef NO_ECOFF_DEBUGGING
15969 && symbol_get_obj (sym)->ecoff_extern_size == 0
15971 && S_GET_VALUE (sym) == 0)
15972 || (S_GET_VALUE (sym) != 0
15973 && S_GET_VALUE (sym) <= g_switch_value)))
15977 const char *segname;
15979 segname = segment_name (S_GET_SEGMENT (sym));
15980 gas_assert (strcmp (segname, ".lit8") != 0
15981 && strcmp (segname, ".lit4") != 0);
15982 change = (strcmp (segname, ".sdata") != 0
15983 && strcmp (segname, ".sbss") != 0
15984 && strncmp (segname, ".sdata.", 7) != 0
15985 && strncmp (segname, ".sbss.", 6) != 0
15986 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
15987 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
15992 /* We are not optimizing for the $gp register. */
15997 /* Return true if the given symbol should be considered local for SVR4 PIC. */
16000 pic_need_relax (symbolS *sym, asection *segtype)
16004 /* Handle the case of a symbol equated to another symbol. */
16005 while (symbol_equated_reloc_p (sym))
16009 /* It's possible to get a loop here in a badly written program. */
16010 n = symbol_get_value_expression (sym)->X_add_symbol;
16016 if (symbol_section_p (sym))
16019 symsec = S_GET_SEGMENT (sym);
16021 /* This must duplicate the test in adjust_reloc_syms. */
16022 return (!bfd_is_und_section (symsec)
16023 && !bfd_is_abs_section (symsec)
16024 && !bfd_is_com_section (symsec)
16025 && !s_is_linkonce (sym, segtype)
16026 /* A global or weak symbol is treated as external. */
16027 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
16031 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
16032 extended opcode. SEC is the section the frag is in. */
16035 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
16038 const struct mips_int_operand *operand;
16043 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
16045 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
16048 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
16049 operand = mips16_immed_operand (type, FALSE);
16051 sym_frag = symbol_get_frag (fragp->fr_symbol);
16052 val = S_GET_VALUE (fragp->fr_symbol);
16053 symsec = S_GET_SEGMENT (fragp->fr_symbol);
16055 if (operand->root.type == OP_PCREL)
16057 const struct mips_pcrel_operand *pcrel_op;
16061 /* We won't have the section when we are called from
16062 mips_relax_frag. However, we will always have been called
16063 from md_estimate_size_before_relax first. If this is a
16064 branch to a different section, we mark it as such. If SEC is
16065 NULL, and the frag is not marked, then it must be a branch to
16066 the same section. */
16067 pcrel_op = (const struct mips_pcrel_operand *) operand;
16070 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
16075 /* Must have been called from md_estimate_size_before_relax. */
16078 fragp->fr_subtype =
16079 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16081 /* FIXME: We should support this, and let the linker
16082 catch branches and loads that are out of range. */
16083 as_bad_where (fragp->fr_file, fragp->fr_line,
16084 _("unsupported PC relative reference to different section"));
16088 if (fragp != sym_frag && sym_frag->fr_address == 0)
16089 /* Assume non-extended on the first relaxation pass.
16090 The address we have calculated will be bogus if this is
16091 a forward branch to another frag, as the forward frag
16092 will have fr_address == 0. */
16096 /* In this case, we know for sure that the symbol fragment is in
16097 the same section. If the relax_marker of the symbol fragment
16098 differs from the relax_marker of this fragment, we have not
16099 yet adjusted the symbol fragment fr_address. We want to add
16100 in STRETCH in order to get a better estimate of the address.
16101 This particularly matters because of the shift bits. */
16103 && sym_frag->relax_marker != fragp->relax_marker)
16107 /* Adjust stretch for any alignment frag. Note that if have
16108 been expanding the earlier code, the symbol may be
16109 defined in what appears to be an earlier frag. FIXME:
16110 This doesn't handle the fr_subtype field, which specifies
16111 a maximum number of bytes to skip when doing an
16113 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
16115 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
16118 stretch = - ((- stretch)
16119 & ~ ((1 << (int) f->fr_offset) - 1));
16121 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
16130 addr = fragp->fr_address + fragp->fr_fix;
16132 /* The base address rules are complicated. The base address of
16133 a branch is the following instruction. The base address of a
16134 PC relative load or add is the instruction itself, but if it
16135 is in a delay slot (in which case it can not be extended) use
16136 the address of the instruction whose delay slot it is in. */
16137 if (pcrel_op->include_isa_bit)
16141 /* If we are currently assuming that this frag should be
16142 extended, then, the current address is two bytes
16144 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16147 /* Ignore the low bit in the target, since it will be set
16148 for a text label. */
16151 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
16153 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
16156 val -= addr & -(1 << pcrel_op->align_log2);
16158 /* If any of the shifted bits are set, we must use an extended
16159 opcode. If the address depends on the size of this
16160 instruction, this can lead to a loop, so we arrange to always
16161 use an extended opcode. We only check this when we are in
16162 the main relaxation loop, when SEC is NULL. */
16163 if ((val & ((1 << operand->shift) - 1)) != 0 && sec == NULL)
16165 fragp->fr_subtype =
16166 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16170 /* If we are about to mark a frag as extended because the value
16171 is precisely the next value above maxtiny, then there is a
16172 chance of an infinite loop as in the following code:
16177 In this case when the la is extended, foo is 0x3fc bytes
16178 away, so the la can be shrunk, but then foo is 0x400 away, so
16179 the la must be extended. To avoid this loop, we mark the
16180 frag as extended if it was small, and is about to become
16181 extended with the next value above maxtiny. */
16182 maxtiny = mips_int_operand_max (operand);
16183 if (val == maxtiny + (1 << operand->shift)
16184 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
16187 fragp->fr_subtype =
16188 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
16192 else if (symsec != absolute_section && sec != NULL)
16193 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
16195 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
16198 /* Compute the length of a branch sequence, and adjust the
16199 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
16200 worst-case length is computed, with UPDATE being used to indicate
16201 whether an unconditional (-1), branch-likely (+1) or regular (0)
16202 branch is to be computed. */
16204 relaxed_branch_length (fragS *fragp, asection *sec, int update)
16206 bfd_boolean toofar;
16210 && S_IS_DEFINED (fragp->fr_symbol)
16211 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16216 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16218 addr = fragp->fr_address + fragp->fr_fix + 4;
16222 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
16225 /* If the symbol is not defined or it's in a different segment,
16226 assume the user knows what's going on and emit a short
16232 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16234 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
16235 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
16236 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
16237 RELAX_BRANCH_LINK (fragp->fr_subtype),
16243 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
16246 if (mips_pic != NO_PIC)
16248 /* Additional space for PIC loading of target address. */
16250 if (mips_opts.isa == ISA_MIPS1)
16251 /* Additional space for $at-stabilizing nop. */
16255 /* If branch is conditional. */
16256 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
16263 /* Compute the length of a branch sequence, and adjust the
16264 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
16265 worst-case length is computed, with UPDATE being used to indicate
16266 whether an unconditional (-1), or regular (0) branch is to be
16270 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
16272 bfd_boolean toofar;
16276 && S_IS_DEFINED (fragp->fr_symbol)
16277 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16282 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16283 /* Ignore the low bit in the target, since it will be set
16284 for a text label. */
16285 if ((val & 1) != 0)
16288 addr = fragp->fr_address + fragp->fr_fix + 4;
16292 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
16295 /* If the symbol is not defined or it's in a different segment,
16296 assume the user knows what's going on and emit a short
16302 if (fragp && update
16303 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16304 fragp->fr_subtype = (toofar
16305 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
16306 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
16311 bfd_boolean compact_known = fragp != NULL;
16312 bfd_boolean compact = FALSE;
16313 bfd_boolean uncond;
16316 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16318 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
16320 uncond = update < 0;
16322 /* If label is out of range, we turn branch <br>:
16324 <br> label # 4 bytes
16330 nop # 2 bytes if compact && !PIC
16333 if (mips_pic == NO_PIC && (!compact_known || compact))
16336 /* If assembling PIC code, we further turn:
16342 lw/ld at, %got(label)(gp) # 4 bytes
16343 d/addiu at, %lo(label) # 4 bytes
16346 if (mips_pic != NO_PIC)
16349 /* If branch <br> is conditional, we prepend negated branch <brneg>:
16351 <brneg> 0f # 4 bytes
16352 nop # 2 bytes if !compact
16355 length += (compact_known && compact) ? 4 : 6;
16361 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
16362 bit accordingly. */
16365 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
16367 bfd_boolean toofar;
16370 && S_IS_DEFINED (fragp->fr_symbol)
16371 && sec == S_GET_SEGMENT (fragp->fr_symbol))
16377 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
16378 /* Ignore the low bit in the target, since it will be set
16379 for a text label. */
16380 if ((val & 1) != 0)
16383 /* Assume this is a 2-byte branch. */
16384 addr = fragp->fr_address + fragp->fr_fix + 2;
16386 /* We try to avoid the infinite loop by not adding 2 more bytes for
16391 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16393 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
16394 else if (type == 'E')
16395 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
16400 /* If the symbol is not defined or it's in a different segment,
16401 we emit a normal 32-bit branch. */
16404 if (fragp && update
16405 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16407 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
16408 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
16416 /* Estimate the size of a frag before relaxing. Unless this is the
16417 mips16, we are not really relaxing here, and the final size is
16418 encoded in the subtype information. For the mips16, we have to
16419 decide whether we are using an extended opcode or not. */
16422 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
16426 if (RELAX_BRANCH_P (fragp->fr_subtype))
16429 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
16431 return fragp->fr_var;
16434 if (RELAX_MIPS16_P (fragp->fr_subtype))
16435 /* We don't want to modify the EXTENDED bit here; it might get us
16436 into infinite loops. We change it only in mips_relax_frag(). */
16437 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
16439 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16443 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16444 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
16445 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16446 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
16447 fragp->fr_var = length;
16452 if (mips_pic == NO_PIC)
16453 change = nopic_need_relax (fragp->fr_symbol, 0);
16454 else if (mips_pic == SVR4_PIC)
16455 change = pic_need_relax (fragp->fr_symbol, segtype);
16456 else if (mips_pic == VXWORKS_PIC)
16457 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
16464 fragp->fr_subtype |= RELAX_USE_SECOND;
16465 return -RELAX_FIRST (fragp->fr_subtype);
16468 return -RELAX_SECOND (fragp->fr_subtype);
16471 /* This is called to see whether a reloc against a defined symbol
16472 should be converted into a reloc against a section. */
16475 mips_fix_adjustable (fixS *fixp)
16477 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
16478 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16481 if (fixp->fx_addsy == NULL)
16484 /* If symbol SYM is in a mergeable section, relocations of the form
16485 SYM + 0 can usually be made section-relative. The mergeable data
16486 is then identified by the section offset rather than by the symbol.
16488 However, if we're generating REL LO16 relocations, the offset is split
16489 between the LO16 and parterning high part relocation. The linker will
16490 need to recalculate the complete offset in order to correctly identify
16493 The linker has traditionally not looked for the parterning high part
16494 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
16495 placed anywhere. Rather than break backwards compatibility by changing
16496 this, it seems better not to force the issue, and instead keep the
16497 original symbol. This will work with either linker behavior. */
16498 if ((lo16_reloc_p (fixp->fx_r_type)
16499 || reloc_needs_lo_p (fixp->fx_r_type))
16500 && HAVE_IN_PLACE_ADDENDS
16501 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
16504 /* There is no place to store an in-place offset for JALR relocations.
16505 Likewise an in-range offset of limited PC-relative relocations may
16506 overflow the in-place relocatable field if recalculated against the
16507 start address of the symbol's containing section. */
16508 if (HAVE_IN_PLACE_ADDENDS
16509 && (limited_pcrel_reloc_p (fixp->fx_r_type)
16510 || jalr_reloc_p (fixp->fx_r_type)))
16513 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
16514 to a floating-point stub. The same is true for non-R_MIPS16_26
16515 relocations against MIPS16 functions; in this case, the stub becomes
16516 the function's canonical address.
16518 Floating-point stubs are stored in unique .mips16.call.* or
16519 .mips16.fn.* sections. If a stub T for function F is in section S,
16520 the first relocation in section S must be against F; this is how the
16521 linker determines the target function. All relocations that might
16522 resolve to T must also be against F. We therefore have the following
16523 restrictions, which are given in an intentionally-redundant way:
16525 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
16528 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
16529 if that stub might be used.
16531 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
16534 4. We cannot reduce a stub's relocations against MIPS16 symbols if
16535 that stub might be used.
16537 There is a further restriction:
16539 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
16540 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
16541 targets with in-place addends; the relocation field cannot
16542 encode the low bit.
16544 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
16545 against a MIPS16 symbol. We deal with (5) by by not reducing any
16546 such relocations on REL targets.
16548 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
16549 relocation against some symbol R, no relocation against R may be
16550 reduced. (Note that this deals with (2) as well as (1) because
16551 relocations against global symbols will never be reduced on ELF
16552 targets.) This approach is a little simpler than trying to detect
16553 stub sections, and gives the "all or nothing" per-symbol consistency
16554 that we have for MIPS16 symbols. */
16555 if (fixp->fx_subsy == NULL
16556 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
16557 || *symbol_get_tc (fixp->fx_addsy)
16558 || (HAVE_IN_PLACE_ADDENDS
16559 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
16560 && jmp_reloc_p (fixp->fx_r_type))))
16566 /* Translate internal representation of relocation info to BFD target
16570 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
16572 static arelent *retval[4];
16574 bfd_reloc_code_real_type code;
16576 memset (retval, 0, sizeof(retval));
16577 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
16578 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
16579 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
16580 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
16582 if (fixp->fx_pcrel)
16584 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
16585 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
16586 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
16587 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
16588 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
16590 /* At this point, fx_addnumber is "symbol offset - pcrel address".
16591 Relocations want only the symbol offset. */
16592 reloc->addend = fixp->fx_addnumber + reloc->address;
16595 reloc->addend = fixp->fx_addnumber;
16597 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
16598 entry to be used in the relocation's section offset. */
16599 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
16601 reloc->address = reloc->addend;
16605 code = fixp->fx_r_type;
16607 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
16608 if (reloc->howto == NULL)
16610 as_bad_where (fixp->fx_file, fixp->fx_line,
16611 _("Can not represent %s relocation in this object file format"),
16612 bfd_get_reloc_code_name (code));
16619 /* Relax a machine dependent frag. This returns the amount by which
16620 the current size of the frag should change. */
16623 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
16625 if (RELAX_BRANCH_P (fragp->fr_subtype))
16627 offsetT old_var = fragp->fr_var;
16629 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
16631 return fragp->fr_var - old_var;
16634 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16636 offsetT old_var = fragp->fr_var;
16637 offsetT new_var = 4;
16639 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
16640 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
16641 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
16642 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
16643 fragp->fr_var = new_var;
16645 return new_var - old_var;
16648 if (! RELAX_MIPS16_P (fragp->fr_subtype))
16651 if (mips16_extended_frag (fragp, NULL, stretch))
16653 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16655 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
16660 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
16662 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
16669 /* Convert a machine dependent frag. */
16672 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
16674 if (RELAX_BRANCH_P (fragp->fr_subtype))
16677 unsigned long insn;
16681 buf = fragp->fr_literal + fragp->fr_fix;
16682 insn = read_insn (buf);
16684 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
16686 /* We generate a fixup instead of applying it right now
16687 because, if there are linker relaxations, we're going to
16688 need the relocations. */
16689 exp.X_op = O_symbol;
16690 exp.X_add_symbol = fragp->fr_symbol;
16691 exp.X_add_number = fragp->fr_offset;
16693 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16694 BFD_RELOC_16_PCREL_S2);
16695 fixp->fx_file = fragp->fr_file;
16696 fixp->fx_line = fragp->fr_line;
16698 buf = write_insn (buf, insn);
16704 as_warn_where (fragp->fr_file, fragp->fr_line,
16705 _("Relaxed out-of-range branch into a jump"));
16707 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
16710 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16712 /* Reverse the branch. */
16713 switch ((insn >> 28) & 0xf)
16716 /* bc[0-3][tf]l? instructions can have the condition
16717 reversed by tweaking a single TF bit, and their
16718 opcodes all have 0x4???????. */
16719 gas_assert ((insn & 0xf3e00000) == 0x41000000);
16720 insn ^= 0x00010000;
16724 /* bltz 0x04000000 bgez 0x04010000
16725 bltzal 0x04100000 bgezal 0x04110000 */
16726 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
16727 insn ^= 0x00010000;
16731 /* beq 0x10000000 bne 0x14000000
16732 blez 0x18000000 bgtz 0x1c000000 */
16733 insn ^= 0x04000000;
16741 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16743 /* Clear the and-link bit. */
16744 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
16746 /* bltzal 0x04100000 bgezal 0x04110000
16747 bltzall 0x04120000 bgezall 0x04130000 */
16748 insn &= ~0x00100000;
16751 /* Branch over the branch (if the branch was likely) or the
16752 full jump (not likely case). Compute the offset from the
16753 current instruction to branch to. */
16754 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16758 /* How many bytes in instructions we've already emitted? */
16759 i = buf - fragp->fr_literal - fragp->fr_fix;
16760 /* How many bytes in instructions from here to the end? */
16761 i = fragp->fr_var - i;
16763 /* Convert to instruction count. */
16765 /* Branch counts from the next instruction. */
16768 /* Branch over the jump. */
16769 buf = write_insn (buf, insn);
16772 buf = write_insn (buf, 0);
16774 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
16776 /* beql $0, $0, 2f */
16778 /* Compute the PC offset from the current instruction to
16779 the end of the variable frag. */
16780 /* How many bytes in instructions we've already emitted? */
16781 i = buf - fragp->fr_literal - fragp->fr_fix;
16782 /* How many bytes in instructions from here to the end? */
16783 i = fragp->fr_var - i;
16784 /* Convert to instruction count. */
16786 /* Don't decrement i, because we want to branch over the
16790 buf = write_insn (buf, insn);
16791 buf = write_insn (buf, 0);
16795 if (mips_pic == NO_PIC)
16798 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
16799 ? 0x0c000000 : 0x08000000);
16800 exp.X_op = O_symbol;
16801 exp.X_add_symbol = fragp->fr_symbol;
16802 exp.X_add_number = fragp->fr_offset;
16804 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16805 FALSE, BFD_RELOC_MIPS_JMP);
16806 fixp->fx_file = fragp->fr_file;
16807 fixp->fx_line = fragp->fr_line;
16809 buf = write_insn (buf, insn);
16813 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
16815 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
16816 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
16817 insn |= at << OP_SH_RT;
16818 exp.X_op = O_symbol;
16819 exp.X_add_symbol = fragp->fr_symbol;
16820 exp.X_add_number = fragp->fr_offset;
16822 if (fragp->fr_offset)
16824 exp.X_add_symbol = make_expr_symbol (&exp);
16825 exp.X_add_number = 0;
16828 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16829 FALSE, BFD_RELOC_MIPS_GOT16);
16830 fixp->fx_file = fragp->fr_file;
16831 fixp->fx_line = fragp->fr_line;
16833 buf = write_insn (buf, insn);
16835 if (mips_opts.isa == ISA_MIPS1)
16837 buf = write_insn (buf, 0);
16839 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
16840 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
16841 insn |= at << OP_SH_RS | at << OP_SH_RT;
16843 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
16844 FALSE, BFD_RELOC_LO16);
16845 fixp->fx_file = fragp->fr_file;
16846 fixp->fx_line = fragp->fr_line;
16848 buf = write_insn (buf, insn);
16851 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
16855 insn |= at << OP_SH_RS;
16857 buf = write_insn (buf, insn);
16861 fragp->fr_fix += fragp->fr_var;
16862 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16866 /* Relax microMIPS branches. */
16867 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
16869 char *buf = fragp->fr_literal + fragp->fr_fix;
16870 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
16871 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
16872 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
16873 bfd_boolean short_ds;
16874 unsigned long insn;
16878 exp.X_op = O_symbol;
16879 exp.X_add_symbol = fragp->fr_symbol;
16880 exp.X_add_number = fragp->fr_offset;
16882 fragp->fr_fix += fragp->fr_var;
16884 /* Handle 16-bit branches that fit or are forced to fit. */
16885 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
16887 /* We generate a fixup instead of applying it right now,
16888 because if there is linker relaxation, we're going to
16889 need the relocations. */
16891 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16892 BFD_RELOC_MICROMIPS_10_PCREL_S1);
16893 else if (type == 'E')
16894 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
16895 BFD_RELOC_MICROMIPS_7_PCREL_S1);
16899 fixp->fx_file = fragp->fr_file;
16900 fixp->fx_line = fragp->fr_line;
16902 /* These relocations can have an addend that won't fit in
16904 fixp->fx_no_overflow = 1;
16909 /* Handle 32-bit branches that fit or are forced to fit. */
16910 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16911 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16913 /* We generate a fixup instead of applying it right now,
16914 because if there is linker relaxation, we're going to
16915 need the relocations. */
16916 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
16917 BFD_RELOC_MICROMIPS_16_PCREL_S1);
16918 fixp->fx_file = fragp->fr_file;
16919 fixp->fx_line = fragp->fr_line;
16925 /* Relax 16-bit branches to 32-bit branches. */
16928 insn = read_compressed_insn (buf, 2);
16930 if ((insn & 0xfc00) == 0xcc00) /* b16 */
16931 insn = 0x94000000; /* beq */
16932 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
16934 unsigned long regno;
16936 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
16937 regno = micromips_to_32_reg_d_map [regno];
16938 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
16939 insn |= regno << MICROMIPSOP_SH_RS;
16944 /* Nothing else to do, just write it out. */
16945 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
16946 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
16948 buf = write_compressed_insn (buf, insn, 4);
16949 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
16954 insn = read_compressed_insn (buf, 4);
16956 /* Relax 32-bit branches to a sequence of instructions. */
16957 as_warn_where (fragp->fr_file, fragp->fr_line,
16958 _("Relaxed out-of-range branch into a jump"));
16960 /* Set the short-delay-slot bit. */
16961 short_ds = al && (insn & 0x02000000) != 0;
16963 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
16967 /* Reverse the branch. */
16968 if ((insn & 0xfc000000) == 0x94000000 /* beq */
16969 || (insn & 0xfc000000) == 0xb4000000) /* bne */
16970 insn ^= 0x20000000;
16971 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
16972 || (insn & 0xffe00000) == 0x40400000 /* bgez */
16973 || (insn & 0xffe00000) == 0x40800000 /* blez */
16974 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
16975 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
16976 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
16977 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
16978 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
16979 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
16980 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
16981 insn ^= 0x00400000;
16982 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
16983 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
16984 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
16985 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
16986 insn ^= 0x00200000;
16992 /* Clear the and-link and short-delay-slot bits. */
16993 gas_assert ((insn & 0xfda00000) == 0x40200000);
16995 /* bltzal 0x40200000 bgezal 0x40600000 */
16996 /* bltzals 0x42200000 bgezals 0x42600000 */
16997 insn &= ~0x02200000;
17000 /* Make a label at the end for use with the branch. */
17001 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
17002 micromips_label_inc ();
17003 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
17006 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
17007 BFD_RELOC_MICROMIPS_16_PCREL_S1);
17008 fixp->fx_file = fragp->fr_file;
17009 fixp->fx_line = fragp->fr_line;
17011 /* Branch over the jump. */
17012 buf = write_compressed_insn (buf, insn, 4);
17015 buf = write_compressed_insn (buf, 0x0c00, 2);
17018 if (mips_pic == NO_PIC)
17020 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
17022 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
17023 insn = al ? jal : 0xd4000000;
17025 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17026 BFD_RELOC_MICROMIPS_JMP);
17027 fixp->fx_file = fragp->fr_file;
17028 fixp->fx_line = fragp->fr_line;
17030 buf = write_compressed_insn (buf, insn, 4);
17033 buf = write_compressed_insn (buf, 0x0c00, 2);
17037 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
17038 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
17039 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
17041 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
17042 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
17043 insn |= at << MICROMIPSOP_SH_RT;
17045 if (exp.X_add_number)
17047 exp.X_add_symbol = make_expr_symbol (&exp);
17048 exp.X_add_number = 0;
17051 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17052 BFD_RELOC_MICROMIPS_GOT16);
17053 fixp->fx_file = fragp->fr_file;
17054 fixp->fx_line = fragp->fr_line;
17056 buf = write_compressed_insn (buf, insn, 4);
17058 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
17059 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
17060 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
17062 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
17063 BFD_RELOC_MICROMIPS_LO16);
17064 fixp->fx_file = fragp->fr_file;
17065 fixp->fx_line = fragp->fr_line;
17067 buf = write_compressed_insn (buf, insn, 4);
17069 /* jr/jrc/jalr/jalrs $at */
17070 insn = al ? jalr : jr;
17071 insn |= at << MICROMIPSOP_SH_MJ;
17073 buf = write_compressed_insn (buf, insn, 2);
17076 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
17080 if (RELAX_MIPS16_P (fragp->fr_subtype))
17083 const struct mips_int_operand *operand;
17086 unsigned int user_length, length;
17087 unsigned long insn;
17090 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17091 operand = mips16_immed_operand (type, FALSE);
17093 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
17094 val = resolve_symbol_value (fragp->fr_symbol);
17095 if (operand->root.type == OP_PCREL)
17097 const struct mips_pcrel_operand *pcrel_op;
17100 pcrel_op = (const struct mips_pcrel_operand *) operand;
17101 addr = fragp->fr_address + fragp->fr_fix;
17103 /* The rules for the base address of a PC relative reloc are
17104 complicated; see mips16_extended_frag. */
17105 if (pcrel_op->include_isa_bit)
17110 /* Ignore the low bit in the target, since it will be
17111 set for a text label. */
17114 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17116 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17119 addr &= -(1 << pcrel_op->align_log2);
17122 /* Make sure the section winds up with the alignment we have
17124 if (operand->shift > 0)
17125 record_alignment (asec, operand->shift);
17129 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
17130 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
17131 as_warn_where (fragp->fr_file, fragp->fr_line,
17132 _("extended instruction in delay slot"));
17134 buf = fragp->fr_literal + fragp->fr_fix;
17136 insn = read_compressed_insn (buf, 2);
17138 insn |= MIPS16_EXTEND;
17140 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17142 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17147 mips16_immed (fragp->fr_file, fragp->fr_line, type,
17148 BFD_RELOC_UNUSED, val, user_length, &insn);
17150 length = (ext ? 4 : 2);
17151 gas_assert (mips16_opcode_length (insn) == length);
17152 write_compressed_insn (buf, insn, length);
17153 fragp->fr_fix += length;
17157 relax_substateT subtype = fragp->fr_subtype;
17158 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
17159 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
17163 first = RELAX_FIRST (subtype);
17164 second = RELAX_SECOND (subtype);
17165 fixp = (fixS *) fragp->fr_opcode;
17167 /* If the delay slot chosen does not match the size of the instruction,
17168 then emit a warning. */
17169 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
17170 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
17175 s = subtype & (RELAX_DELAY_SLOT_16BIT
17176 | RELAX_DELAY_SLOT_SIZE_FIRST
17177 | RELAX_DELAY_SLOT_SIZE_SECOND);
17178 msg = macro_warning (s);
17180 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17184 /* Possibly emit a warning if we've chosen the longer option. */
17185 if (use_second == second_longer)
17191 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
17192 msg = macro_warning (s);
17194 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
17198 /* Go through all the fixups for the first sequence. Disable them
17199 (by marking them as done) if we're going to use the second
17200 sequence instead. */
17202 && fixp->fx_frag == fragp
17203 && fixp->fx_where < fragp->fr_fix - second)
17205 if (subtype & RELAX_USE_SECOND)
17207 fixp = fixp->fx_next;
17210 /* Go through the fixups for the second sequence. Disable them if
17211 we're going to use the first sequence, otherwise adjust their
17212 addresses to account for the relaxation. */
17213 while (fixp && fixp->fx_frag == fragp)
17215 if (subtype & RELAX_USE_SECOND)
17216 fixp->fx_where -= first;
17219 fixp = fixp->fx_next;
17222 /* Now modify the frag contents. */
17223 if (subtype & RELAX_USE_SECOND)
17227 start = fragp->fr_literal + fragp->fr_fix - first - second;
17228 memmove (start, start + first, second);
17229 fragp->fr_fix -= first;
17232 fragp->fr_fix -= second;
17236 /* This function is called after the relocs have been generated.
17237 We've been storing mips16 text labels as odd. Here we convert them
17238 back to even for the convenience of the debugger. */
17241 mips_frob_file_after_relocs (void)
17244 unsigned int count, i;
17246 syms = bfd_get_outsymbols (stdoutput);
17247 count = bfd_get_symcount (stdoutput);
17248 for (i = 0; i < count; i++, syms++)
17249 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
17250 && ((*syms)->value & 1) != 0)
17252 (*syms)->value &= ~1;
17253 /* If the symbol has an odd size, it was probably computed
17254 incorrectly, so adjust that as well. */
17255 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
17256 ++elf_symbol (*syms)->internal_elf_sym.st_size;
17260 /* This function is called whenever a label is defined, including fake
17261 labels instantiated off the dot special symbol. It is used when
17262 handling branch delays; if a branch has a label, we assume we cannot
17263 move it. This also bumps the value of the symbol by 1 in compressed
17267 mips_record_label (symbolS *sym)
17269 segment_info_type *si = seg_info (now_seg);
17270 struct insn_label_list *l;
17272 if (free_insn_labels == NULL)
17273 l = (struct insn_label_list *) xmalloc (sizeof *l);
17276 l = free_insn_labels;
17277 free_insn_labels = l->next;
17281 l->next = si->label_list;
17282 si->label_list = l;
17285 /* This function is called as tc_frob_label() whenever a label is defined
17286 and adds a DWARF-2 record we only want for true labels. */
17289 mips_define_label (symbolS *sym)
17291 mips_record_label (sym);
17292 dwarf2_emit_label (sym);
17295 /* This function is called by tc_new_dot_label whenever a new dot symbol
17299 mips_add_dot_label (symbolS *sym)
17301 mips_record_label (sym);
17302 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
17303 mips_compressed_mark_label (sym);
17306 /* Some special processing for a MIPS ELF file. */
17309 mips_elf_final_processing (void)
17311 /* Write out the register information. */
17312 if (mips_abi != N64_ABI)
17316 s.ri_gprmask = mips_gprmask;
17317 s.ri_cprmask[0] = mips_cprmask[0];
17318 s.ri_cprmask[1] = mips_cprmask[1];
17319 s.ri_cprmask[2] = mips_cprmask[2];
17320 s.ri_cprmask[3] = mips_cprmask[3];
17321 /* The gp_value field is set by the MIPS ELF backend. */
17323 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
17324 ((Elf32_External_RegInfo *)
17325 mips_regmask_frag));
17329 Elf64_Internal_RegInfo s;
17331 s.ri_gprmask = mips_gprmask;
17333 s.ri_cprmask[0] = mips_cprmask[0];
17334 s.ri_cprmask[1] = mips_cprmask[1];
17335 s.ri_cprmask[2] = mips_cprmask[2];
17336 s.ri_cprmask[3] = mips_cprmask[3];
17337 /* The gp_value field is set by the MIPS ELF backend. */
17339 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
17340 ((Elf64_External_RegInfo *)
17341 mips_regmask_frag));
17344 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
17345 sort of BFD interface for this. */
17346 if (mips_any_noreorder)
17347 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
17348 if (mips_pic != NO_PIC)
17350 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
17351 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17354 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
17356 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
17357 defined at present; this might need to change in future. */
17358 if (file_ase_mips16)
17359 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
17360 if (file_ase_micromips)
17361 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
17362 if (file_ase & ASE_MDMX)
17363 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
17365 /* Set the MIPS ELF ABI flags. */
17366 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
17367 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
17368 else if (mips_abi == O64_ABI)
17369 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
17370 else if (mips_abi == EABI_ABI)
17372 if (!file_mips_gp32)
17373 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
17375 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
17377 else if (mips_abi == N32_ABI)
17378 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
17380 /* Nothing to do for N64_ABI. */
17382 if (mips_32bitmode)
17383 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
17385 if (mips_flag_nan2008)
17386 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
17388 #if 0 /* XXX FIXME */
17389 /* 32 bit code with 64 bit FP registers. */
17390 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
17391 elf_elfheader (stdoutput)->e_flags |= ???;
17395 typedef struct proc {
17397 symbolS *func_end_sym;
17398 unsigned long reg_mask;
17399 unsigned long reg_offset;
17400 unsigned long fpreg_mask;
17401 unsigned long fpreg_offset;
17402 unsigned long frame_offset;
17403 unsigned long frame_reg;
17404 unsigned long pc_reg;
17407 static procS cur_proc;
17408 static procS *cur_proc_ptr;
17409 static int numprocs;
17411 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
17412 as "2", and a normal nop as "0". */
17414 #define NOP_OPCODE_MIPS 0
17415 #define NOP_OPCODE_MIPS16 1
17416 #define NOP_OPCODE_MICROMIPS 2
17419 mips_nop_opcode (void)
17421 if (seg_info (now_seg)->tc_segment_info_data.micromips)
17422 return NOP_OPCODE_MICROMIPS;
17423 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
17424 return NOP_OPCODE_MIPS16;
17426 return NOP_OPCODE_MIPS;
17429 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
17430 32-bit microMIPS NOPs here (if applicable). */
17433 mips_handle_align (fragS *fragp)
17437 int bytes, size, excess;
17440 if (fragp->fr_type != rs_align_code)
17443 p = fragp->fr_literal + fragp->fr_fix;
17445 switch (nop_opcode)
17447 case NOP_OPCODE_MICROMIPS:
17448 opcode = micromips_nop32_insn.insn_opcode;
17451 case NOP_OPCODE_MIPS16:
17452 opcode = mips16_nop_insn.insn_opcode;
17455 case NOP_OPCODE_MIPS:
17457 opcode = nop_insn.insn_opcode;
17462 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
17463 excess = bytes % size;
17465 /* Handle the leading part if we're not inserting a whole number of
17466 instructions, and make it the end of the fixed part of the frag.
17467 Try to fit in a short microMIPS NOP if applicable and possible,
17468 and use zeroes otherwise. */
17469 gas_assert (excess < 4);
17470 fragp->fr_fix += excess;
17475 /* Fall through. */
17477 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
17479 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
17483 /* Fall through. */
17486 /* Fall through. */
17491 md_number_to_chars (p, opcode, size);
17492 fragp->fr_var = size;
17496 md_obj_begin (void)
17503 /* Check for premature end, nesting errors, etc. */
17505 as_warn (_("missing .end at end of assembly"));
17514 if (*input_line_pointer == '-')
17516 ++input_line_pointer;
17519 if (!ISDIGIT (*input_line_pointer))
17520 as_bad (_("expected simple number"));
17521 if (input_line_pointer[0] == '0')
17523 if (input_line_pointer[1] == 'x')
17525 input_line_pointer += 2;
17526 while (ISXDIGIT (*input_line_pointer))
17529 val |= hex_value (*input_line_pointer++);
17531 return negative ? -val : val;
17535 ++input_line_pointer;
17536 while (ISDIGIT (*input_line_pointer))
17539 val |= *input_line_pointer++ - '0';
17541 return negative ? -val : val;
17544 if (!ISDIGIT (*input_line_pointer))
17546 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
17547 *input_line_pointer, *input_line_pointer);
17548 as_warn (_("invalid number"));
17551 while (ISDIGIT (*input_line_pointer))
17554 val += *input_line_pointer++ - '0';
17556 return negative ? -val : val;
17559 /* The .file directive; just like the usual .file directive, but there
17560 is an initial number which is the ECOFF file index. In the non-ECOFF
17561 case .file implies DWARF-2. */
17564 s_mips_file (int x ATTRIBUTE_UNUSED)
17566 static int first_file_directive = 0;
17568 if (ECOFF_DEBUGGING)
17577 filename = dwarf2_directive_file (0);
17579 /* Versions of GCC up to 3.1 start files with a ".file"
17580 directive even for stabs output. Make sure that this
17581 ".file" is handled. Note that you need a version of GCC
17582 after 3.1 in order to support DWARF-2 on MIPS. */
17583 if (filename != NULL && ! first_file_directive)
17585 (void) new_logical_line (filename, -1);
17586 s_app_file_string (filename, 0);
17588 first_file_directive = 1;
17592 /* The .loc directive, implying DWARF-2. */
17595 s_mips_loc (int x ATTRIBUTE_UNUSED)
17597 if (!ECOFF_DEBUGGING)
17598 dwarf2_directive_loc (0);
17601 /* The .end directive. */
17604 s_mips_end (int x ATTRIBUTE_UNUSED)
17608 /* Following functions need their own .frame and .cprestore directives. */
17609 mips_frame_reg_valid = 0;
17610 mips_cprestore_valid = 0;
17612 if (!is_end_of_line[(unsigned char) *input_line_pointer])
17615 demand_empty_rest_of_line ();
17620 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17621 as_warn (_(".end not in text section"));
17625 as_warn (_(".end directive without a preceding .ent directive."));
17626 demand_empty_rest_of_line ();
17632 gas_assert (S_GET_NAME (p));
17633 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
17634 as_warn (_(".end symbol does not match .ent symbol."));
17636 if (debug_type == DEBUG_STABS)
17637 stabs_generate_asm_endfunc (S_GET_NAME (p),
17641 as_warn (_(".end directive missing or unknown symbol"));
17643 /* Create an expression to calculate the size of the function. */
17644 if (p && cur_proc_ptr)
17646 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
17647 expressionS *exp = xmalloc (sizeof (expressionS));
17650 exp->X_op = O_subtract;
17651 exp->X_add_symbol = symbol_temp_new_now ();
17652 exp->X_op_symbol = p;
17653 exp->X_add_number = 0;
17655 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
17658 /* Generate a .pdr section. */
17659 if (!ECOFF_DEBUGGING && mips_flag_pdr)
17661 segT saved_seg = now_seg;
17662 subsegT saved_subseg = now_subseg;
17666 #ifdef md_flush_pending_output
17667 md_flush_pending_output ();
17670 gas_assert (pdr_seg);
17671 subseg_set (pdr_seg, 0);
17673 /* Write the symbol. */
17674 exp.X_op = O_symbol;
17675 exp.X_add_symbol = p;
17676 exp.X_add_number = 0;
17677 emit_expr (&exp, 4);
17679 fragp = frag_more (7 * 4);
17681 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
17682 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
17683 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
17684 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
17685 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
17686 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
17687 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
17689 subseg_set (saved_seg, saved_subseg);
17692 cur_proc_ptr = NULL;
17695 /* The .aent and .ent directives. */
17698 s_mips_ent (int aent)
17702 symbolP = get_symbol ();
17703 if (*input_line_pointer == ',')
17704 ++input_line_pointer;
17705 SKIP_WHITESPACE ();
17706 if (ISDIGIT (*input_line_pointer)
17707 || *input_line_pointer == '-')
17710 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
17711 as_warn (_(".ent or .aent not in text section."));
17713 if (!aent && cur_proc_ptr)
17714 as_warn (_("missing .end"));
17718 /* This function needs its own .frame and .cprestore directives. */
17719 mips_frame_reg_valid = 0;
17720 mips_cprestore_valid = 0;
17722 cur_proc_ptr = &cur_proc;
17723 memset (cur_proc_ptr, '\0', sizeof (procS));
17725 cur_proc_ptr->func_sym = symbolP;
17729 if (debug_type == DEBUG_STABS)
17730 stabs_generate_asm_func (S_GET_NAME (symbolP),
17731 S_GET_NAME (symbolP));
17734 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
17736 demand_empty_rest_of_line ();
17739 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
17740 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
17741 s_mips_frame is used so that we can set the PDR information correctly.
17742 We can't use the ecoff routines because they make reference to the ecoff
17743 symbol table (in the mdebug section). */
17746 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
17748 if (ECOFF_DEBUGGING)
17754 if (cur_proc_ptr == (procS *) NULL)
17756 as_warn (_(".frame outside of .ent"));
17757 demand_empty_rest_of_line ();
17761 cur_proc_ptr->frame_reg = tc_get_register (1);
17763 SKIP_WHITESPACE ();
17764 if (*input_line_pointer++ != ','
17765 || get_absolute_expression_and_terminator (&val) != ',')
17767 as_warn (_("Bad .frame directive"));
17768 --input_line_pointer;
17769 demand_empty_rest_of_line ();
17773 cur_proc_ptr->frame_offset = val;
17774 cur_proc_ptr->pc_reg = tc_get_register (0);
17776 demand_empty_rest_of_line ();
17780 /* The .fmask and .mask directives. If the mdebug section is present
17781 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
17782 embedded targets, s_mips_mask is used so that we can set the PDR
17783 information correctly. We can't use the ecoff routines because they
17784 make reference to the ecoff symbol table (in the mdebug section). */
17787 s_mips_mask (int reg_type)
17789 if (ECOFF_DEBUGGING)
17790 s_ignore (reg_type);
17795 if (cur_proc_ptr == (procS *) NULL)
17797 as_warn (_(".mask/.fmask outside of .ent"));
17798 demand_empty_rest_of_line ();
17802 if (get_absolute_expression_and_terminator (&mask) != ',')
17804 as_warn (_("Bad .mask/.fmask directive"));
17805 --input_line_pointer;
17806 demand_empty_rest_of_line ();
17810 off = get_absolute_expression ();
17812 if (reg_type == 'F')
17814 cur_proc_ptr->fpreg_mask = mask;
17815 cur_proc_ptr->fpreg_offset = off;
17819 cur_proc_ptr->reg_mask = mask;
17820 cur_proc_ptr->reg_offset = off;
17823 demand_empty_rest_of_line ();
17827 /* A table describing all the processors gas knows about. Names are
17828 matched in the order listed.
17830 To ease comparison, please keep this table in the same order as
17831 gcc's mips_cpu_info_table[]. */
17832 static const struct mips_cpu_info mips_cpu_info_table[] =
17834 /* Entries for generic ISAs */
17835 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
17836 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
17837 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
17838 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
17839 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
17840 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
17841 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17842 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
17843 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
17846 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
17847 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
17848 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
17851 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
17854 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
17855 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
17856 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
17857 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
17858 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
17859 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
17860 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
17861 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
17862 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
17863 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
17864 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
17865 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
17866 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
17867 /* ST Microelectronics Loongson 2E and 2F cores */
17868 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
17869 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
17872 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
17873 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
17874 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
17875 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
17876 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
17877 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
17878 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
17879 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
17880 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
17881 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
17882 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
17883 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
17884 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
17885 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
17886 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
17889 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17890 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17891 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
17892 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
17894 /* MIPS 32 Release 2 */
17895 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17896 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17897 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17898 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
17899 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17900 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17901 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17902 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
17903 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17904 ISA_MIPS32R2, CPU_MIPS32R2 },
17905 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
17906 ISA_MIPS32R2, CPU_MIPS32R2 },
17907 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17908 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17909 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17910 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17911 /* Deprecated forms of the above. */
17912 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17913 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
17914 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
17915 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17916 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17917 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17918 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17919 /* Deprecated forms of the above. */
17920 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17921 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
17922 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
17923 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17924 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17925 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17926 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17927 /* Deprecated forms of the above. */
17928 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17929 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17930 /* 34Kn is a 34kc without DSP. */
17931 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17932 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
17933 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17934 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17935 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17936 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17937 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17938 /* Deprecated forms of the above. */
17939 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17940 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
17941 /* 1004K cores are multiprocessor versions of the 34K. */
17942 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17943 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17944 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17945 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
17948 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17949 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
17950 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17951 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
17953 /* Broadcom SB-1 CPU core */
17954 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17955 /* Broadcom SB-1A CPU core */
17956 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
17958 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
17960 /* MIPS 64 Release 2 */
17962 /* Cavium Networks Octeon CPU core */
17963 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
17964 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
17965 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
17968 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
17971 XLP is mostly like XLR, with the prominent exception that it is
17972 MIPS64R2 rather than MIPS64. */
17973 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
17976 { NULL, 0, 0, 0, 0 }
17980 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
17981 with a final "000" replaced by "k". Ignore case.
17983 Note: this function is shared between GCC and GAS. */
17986 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
17988 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
17989 given++, canonical++;
17991 return ((*given == 0 && *canonical == 0)
17992 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
17996 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
17997 CPU name. We've traditionally allowed a lot of variation here.
17999 Note: this function is shared between GCC and GAS. */
18002 mips_matching_cpu_name_p (const char *canonical, const char *given)
18004 /* First see if the name matches exactly, or with a final "000"
18005 turned into "k". */
18006 if (mips_strict_matching_cpu_name_p (canonical, given))
18009 /* If not, try comparing based on numerical designation alone.
18010 See if GIVEN is an unadorned number, or 'r' followed by a number. */
18011 if (TOLOWER (*given) == 'r')
18013 if (!ISDIGIT (*given))
18016 /* Skip over some well-known prefixes in the canonical name,
18017 hoping to find a number there too. */
18018 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
18020 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
18022 else if (TOLOWER (canonical[0]) == 'r')
18025 return mips_strict_matching_cpu_name_p (canonical, given);
18029 /* Parse an option that takes the name of a processor as its argument.
18030 OPTION is the name of the option and CPU_STRING is the argument.
18031 Return the corresponding processor enumeration if the CPU_STRING is
18032 recognized, otherwise report an error and return null.
18034 A similar function exists in GCC. */
18036 static const struct mips_cpu_info *
18037 mips_parse_cpu (const char *option, const char *cpu_string)
18039 const struct mips_cpu_info *p;
18041 /* 'from-abi' selects the most compatible architecture for the given
18042 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
18043 EABIs, we have to decide whether we're using the 32-bit or 64-bit
18044 version. Look first at the -mgp options, if given, otherwise base
18045 the choice on MIPS_DEFAULT_64BIT.
18047 Treat NO_ABI like the EABIs. One reason to do this is that the
18048 plain 'mips' and 'mips64' configs have 'from-abi' as their default
18049 architecture. This code picks MIPS I for 'mips' and MIPS III for
18050 'mips64', just as we did in the days before 'from-abi'. */
18051 if (strcasecmp (cpu_string, "from-abi") == 0)
18053 if (ABI_NEEDS_32BIT_REGS (mips_abi))
18054 return mips_cpu_info_from_isa (ISA_MIPS1);
18056 if (ABI_NEEDS_64BIT_REGS (mips_abi))
18057 return mips_cpu_info_from_isa (ISA_MIPS3);
18059 if (file_mips_gp32 >= 0)
18060 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
18062 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
18067 /* 'default' has traditionally been a no-op. Probably not very useful. */
18068 if (strcasecmp (cpu_string, "default") == 0)
18071 for (p = mips_cpu_info_table; p->name != 0; p++)
18072 if (mips_matching_cpu_name_p (p->name, cpu_string))
18075 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
18079 /* Return the canonical processor information for ISA (a member of the
18080 ISA_MIPS* enumeration). */
18082 static const struct mips_cpu_info *
18083 mips_cpu_info_from_isa (int isa)
18087 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18088 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
18089 && isa == mips_cpu_info_table[i].isa)
18090 return (&mips_cpu_info_table[i]);
18095 static const struct mips_cpu_info *
18096 mips_cpu_info_from_arch (int arch)
18100 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18101 if (arch == mips_cpu_info_table[i].cpu)
18102 return (&mips_cpu_info_table[i]);
18108 show (FILE *stream, const char *string, int *col_p, int *first_p)
18112 fprintf (stream, "%24s", "");
18117 fprintf (stream, ", ");
18121 if (*col_p + strlen (string) > 72)
18123 fprintf (stream, "\n%24s", "");
18127 fprintf (stream, "%s", string);
18128 *col_p += strlen (string);
18134 md_show_usage (FILE *stream)
18139 fprintf (stream, _("\
18141 -EB generate big endian output\n\
18142 -EL generate little endian output\n\
18143 -g, -g2 do not remove unneeded NOPs or swap branches\n\
18144 -G NUM allow referencing objects up to NUM bytes\n\
18145 implicitly with the gp register [default 8]\n"));
18146 fprintf (stream, _("\
18147 -mips1 generate MIPS ISA I instructions\n\
18148 -mips2 generate MIPS ISA II instructions\n\
18149 -mips3 generate MIPS ISA III instructions\n\
18150 -mips4 generate MIPS ISA IV instructions\n\
18151 -mips5 generate MIPS ISA V instructions\n\
18152 -mips32 generate MIPS32 ISA instructions\n\
18153 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
18154 -mips64 generate MIPS64 ISA instructions\n\
18155 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
18156 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
18160 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
18161 show (stream, mips_cpu_info_table[i].name, &column, &first);
18162 show (stream, "from-abi", &column, &first);
18163 fputc ('\n', stream);
18165 fprintf (stream, _("\
18166 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
18167 -no-mCPU don't generate code specific to CPU.\n\
18168 For -mCPU and -no-mCPU, CPU must be one of:\n"));
18172 show (stream, "3900", &column, &first);
18173 show (stream, "4010", &column, &first);
18174 show (stream, "4100", &column, &first);
18175 show (stream, "4650", &column, &first);
18176 fputc ('\n', stream);
18178 fprintf (stream, _("\
18179 -mips16 generate mips16 instructions\n\
18180 -no-mips16 do not generate mips16 instructions\n"));
18181 fprintf (stream, _("\
18182 -mmicromips generate microMIPS instructions\n\
18183 -mno-micromips do not generate microMIPS instructions\n"));
18184 fprintf (stream, _("\
18185 -msmartmips generate smartmips instructions\n\
18186 -mno-smartmips do not generate smartmips instructions\n"));
18187 fprintf (stream, _("\
18188 -mdsp generate DSP instructions\n\
18189 -mno-dsp do not generate DSP instructions\n"));
18190 fprintf (stream, _("\
18191 -mdspr2 generate DSP R2 instructions\n\
18192 -mno-dspr2 do not generate DSP R2 instructions\n"));
18193 fprintf (stream, _("\
18194 -mmt generate MT instructions\n\
18195 -mno-mt do not generate MT instructions\n"));
18196 fprintf (stream, _("\
18197 -mmcu generate MCU instructions\n\
18198 -mno-mcu do not generate MCU instructions\n"));
18199 fprintf (stream, _("\
18200 -mvirt generate Virtualization instructions\n\
18201 -mno-virt do not generate Virtualization instructions\n"));
18202 fprintf (stream, _("\
18203 -minsn32 only generate 32-bit microMIPS instructions\n\
18204 -mno-insn32 generate all microMIPS instructions\n"));
18205 fprintf (stream, _("\
18206 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
18207 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
18208 -mfix-vr4120 work around certain VR4120 errata\n\
18209 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
18210 -mfix-24k insert a nop after ERET and DERET instructions\n\
18211 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
18212 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
18213 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
18214 -msym32 assume all symbols have 32-bit values\n\
18215 -O0 remove unneeded NOPs, do not swap branches\n\
18216 -O remove unneeded NOPs and swap branches\n\
18217 --trap, --no-break trap exception on div by 0 and mult overflow\n\
18218 --break, --no-trap break exception on div by 0 and mult overflow\n"));
18219 fprintf (stream, _("\
18220 -mhard-float allow floating-point instructions\n\
18221 -msoft-float do not allow floating-point instructions\n\
18222 -msingle-float only allow 32-bit floating-point operations\n\
18223 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
18224 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
18225 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
18226 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
18230 show (stream, "legacy", &column, &first);
18231 show (stream, "2008", &column, &first);
18233 fputc ('\n', stream);
18235 fprintf (stream, _("\
18236 -KPIC, -call_shared generate SVR4 position independent code\n\
18237 -call_nonpic generate non-PIC code that can operate with DSOs\n\
18238 -mvxworks-pic generate VxWorks position independent code\n\
18239 -non_shared do not generate code that can operate with DSOs\n\
18240 -xgot assume a 32 bit GOT\n\
18241 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
18242 -mshared, -mno-shared disable/enable .cpload optimization for\n\
18243 position dependent (non shared) code\n\
18244 -mabi=ABI create ABI conformant object file for:\n"));
18248 show (stream, "32", &column, &first);
18249 show (stream, "o64", &column, &first);
18250 show (stream, "n32", &column, &first);
18251 show (stream, "64", &column, &first);
18252 show (stream, "eabi", &column, &first);
18254 fputc ('\n', stream);
18256 fprintf (stream, _("\
18257 -32 create o32 ABI object file (default)\n\
18258 -n32 create n32 ABI object file\n\
18259 -64 create 64 ABI object file\n"));
18264 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
18266 if (HAVE_64BIT_SYMBOLS)
18267 return dwarf2_format_64bit_irix;
18269 return dwarf2_format_32bit;
18274 mips_dwarf2_addr_size (void)
18276 if (HAVE_64BIT_OBJECTS)
18282 /* Standard calling conventions leave the CFA at SP on entry. */
18284 mips_cfi_frame_initial_instructions (void)
18286 cfi_add_CFA_def_cfa_register (SP);
18290 tc_mips_regname_to_dw2regnum (char *regname)
18292 unsigned int regnum = -1;
18295 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))