1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* True if we should only emit 32-bit microMIPS instructions.
235 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
236 and -mno-insn32 command line options. */
238 /* Restrict general purpose registers and floating point registers
239 to 32 bit. This is initially determined when -mgp32 or -mfp32
240 is passed but can changed if the assembler code uses .set mipsN. */
243 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
244 command line option, and the default CPU. */
246 /* True if ".set sym32" is in effect. */
248 /* True if floating-point operations are not allowed. Changed by .set
249 softfloat or .set hardfloat, by command line options -msoft-float or
250 -mhard-float. The default is false. */
251 bfd_boolean soft_float;
253 /* True if only single-precision floating-point operations are allowed.
254 Changed by .set singlefloat or .set doublefloat, command-line options
255 -msingle-float or -mdouble-float. The default is false. */
256 bfd_boolean single_float;
259 /* This is the struct we use to hold the current set of options. Note
260 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
261 -1 to indicate that they have not been initialized. */
263 /* True if -mgp32 was passed. */
264 static int file_mips_gp32 = -1;
266 /* True if -mfp32 was passed. */
267 static int file_mips_fp32 = -1;
269 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
270 static int file_mips_soft_float = 0;
272 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
273 static int file_mips_single_float = 0;
275 /* True if -mnan=2008, false if -mnan=legacy. */
276 static bfd_boolean mips_flag_nan2008 = FALSE;
278 static struct mips_set_options mips_opts =
280 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
281 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
282 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
283 /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
284 /* soft_float */ FALSE, /* single_float */ FALSE
287 /* The set of ASEs that were selected on the command line, either
288 explicitly via ASE options or implicitly through things like -march. */
289 static unsigned int file_ase;
291 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
292 static unsigned int file_ase_explicit;
294 /* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
297 unsigned long mips_gprmask;
298 unsigned long mips_cprmask[4];
300 /* MIPS ISA we are using for this output file. */
301 static int file_mips_isa = ISA_UNKNOWN;
303 /* True if any MIPS16 code was produced. */
304 static int file_ase_mips16;
306 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
311 /* True if any microMIPS code was produced. */
312 static int file_ase_micromips;
314 /* True if we want to create R_MIPS_JALR for jalr $25. */
316 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
318 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
319 because there's no place for any addend, the only acceptable
320 expression is a bare symbol. */
321 #define MIPS_JALR_HINT_P(EXPR) \
322 (!HAVE_IN_PLACE_ADDENDS \
323 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
326 /* The argument of the -march= flag. The architecture we are assembling. */
327 static int file_mips_arch = CPU_UNKNOWN;
328 static const char *mips_arch_string;
330 /* The argument of the -mtune= flag. The architecture for which we
332 static int mips_tune = CPU_UNKNOWN;
333 static const char *mips_tune_string;
335 /* True when generating 32-bit code for a 64-bit processor. */
336 static int mips_32bitmode = 0;
338 /* True if the given ABI requires 32-bit registers. */
339 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
341 /* Likewise 64-bit registers. */
342 #define ABI_NEEDS_64BIT_REGS(ABI) \
344 || (ABI) == N64_ABI \
347 /* Return true if ISA supports 64 bit wide gp registers. */
348 #define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
355 /* Return true if ISA supports 64 bit wide float registers. */
356 #define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
364 /* Return true if ISA supports 64-bit right rotate (dror et al.)
366 #define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2 \
368 || (mips_opts.micromips \
369 && ISA_HAS_64BIT_REGS (ISA)) \
372 /* Return true if ISA supports 32-bit right rotate (ror et al.)
374 #define ISA_HAS_ROR(ISA) \
375 ((ISA) == ISA_MIPS32R2 \
376 || (ISA) == ISA_MIPS64R2 \
377 || (mips_opts.ase & ASE_SMARTMIPS) \
378 || mips_opts.micromips \
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* Return true if the given CPU supports the microMIPS ASE. */
442 #define CPU_HAS_MICROMIPS(cpu) 0
444 /* True if CPU has a dror instruction. */
445 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
447 /* True if CPU has a ror instruction. */
448 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
450 /* True if CPU is in the Octeon family */
451 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
453 /* True if CPU has seq/sne and seqi/snei instructions. */
454 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
456 /* True, if CPU has support for ldc1 and sdc1. */
457 #define CPU_HAS_LDC1_SDC1(CPU) \
458 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
460 /* True if mflo and mfhi can be immediately followed by instructions
461 which write to the HI and LO registers.
463 According to MIPS specifications, MIPS ISAs I, II, and III need
464 (at least) two instructions between the reads of HI/LO and
465 instructions which write them, and later ISAs do not. Contradicting
466 the MIPS specifications, some MIPS IV processor user manuals (e.g.
467 the UM for the NEC Vr5000) document needing the instructions between
468 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
469 MIPS64 and later ISAs to have the interlocks, plus any specific
470 earlier-ISA CPUs for which CPU documentation declares that the
471 instructions are really interlocked. */
472 #define hilo_interlocks \
473 (mips_opts.isa == ISA_MIPS32 \
474 || mips_opts.isa == ISA_MIPS32R2 \
475 || mips_opts.isa == ISA_MIPS64 \
476 || mips_opts.isa == ISA_MIPS64R2 \
477 || mips_opts.arch == CPU_R4010 \
478 || mips_opts.arch == CPU_R5900 \
479 || mips_opts.arch == CPU_R10000 \
480 || mips_opts.arch == CPU_R12000 \
481 || mips_opts.arch == CPU_R14000 \
482 || mips_opts.arch == CPU_R16000 \
483 || mips_opts.arch == CPU_RM7000 \
484 || mips_opts.arch == CPU_VR5500 \
485 || mips_opts.micromips \
488 /* Whether the processor uses hardware interlocks to protect reads
489 from the GPRs after they are loaded from memory, and thus does not
490 require nops to be inserted. This applies to instructions marked
491 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
492 level I and microMIPS mode instructions are always interlocked. */
493 #define gpr_interlocks \
494 (mips_opts.isa != ISA_MIPS1 \
495 || mips_opts.arch == CPU_R3900 \
496 || mips_opts.arch == CPU_R5900 \
497 || mips_opts.micromips \
500 /* Whether the processor uses hardware interlocks to avoid delays
501 required by coprocessor instructions, and thus does not require
502 nops to be inserted. This applies to instructions marked
503 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
504 between instructions marked INSN_WRITE_COND_CODE and ones marked
505 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
506 levels I, II, and III and microMIPS mode instructions are always
508 /* Itbl support may require additional care here. */
509 #define cop_interlocks \
510 ((mips_opts.isa != ISA_MIPS1 \
511 && mips_opts.isa != ISA_MIPS2 \
512 && mips_opts.isa != ISA_MIPS3) \
513 || mips_opts.arch == CPU_R4300 \
514 || mips_opts.micromips \
517 /* Whether the processor uses hardware interlocks to protect reads
518 from coprocessor registers after they are loaded from memory, and
519 thus does not require nops to be inserted. This applies to
520 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
521 requires at MIPS ISA level I and microMIPS mode instructions are
522 always interlocked. */
523 #define cop_mem_interlocks \
524 (mips_opts.isa != ISA_MIPS1 \
525 || mips_opts.micromips \
528 /* Is this a mfhi or mflo instruction? */
529 #define MF_HILO_INSN(PINFO) \
530 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
532 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
533 has been selected. This implies, in particular, that addresses of text
534 labels have their LSB set. */
535 #define HAVE_CODE_COMPRESSION \
536 ((mips_opts.mips16 | mips_opts.micromips) != 0)
538 /* The minimum and maximum signed values that can be stored in a GPR. */
539 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
540 #define GPR_SMIN (-GPR_SMAX - 1)
542 /* MIPS PIC level. */
544 enum mips_pic_level mips_pic;
546 /* 1 if we should generate 32 bit offsets from the $gp register in
547 SVR4_PIC mode. Currently has no meaning in other modes. */
548 static int mips_big_got = 0;
550 /* 1 if trap instructions should used for overflow rather than break
552 static int mips_trap = 0;
554 /* 1 if double width floating point constants should not be constructed
555 by assembling two single width halves into two single width floating
556 point registers which just happen to alias the double width destination
557 register. On some architectures this aliasing can be disabled by a bit
558 in the status register, and the setting of this bit cannot be determined
559 automatically at assemble time. */
560 static int mips_disable_float_construction;
562 /* Non-zero if any .set noreorder directives were used. */
564 static int mips_any_noreorder;
566 /* Non-zero if nops should be inserted when the register referenced in
567 an mfhi/mflo instruction is read in the next two instructions. */
568 static int mips_7000_hilo_fix;
570 /* The size of objects in the small data section. */
571 static unsigned int g_switch_value = 8;
572 /* Whether the -G option was used. */
573 static int g_switch_seen = 0;
578 /* If we can determine in advance that GP optimization won't be
579 possible, we can skip the relaxation stuff that tries to produce
580 GP-relative references. This makes delay slot optimization work
583 This function can only provide a guess, but it seems to work for
584 gcc output. It needs to guess right for gcc, otherwise gcc
585 will put what it thinks is a GP-relative instruction in a branch
588 I don't know if a fix is needed for the SVR4_PIC mode. I've only
589 fixed it for the non-PIC mode. KR 95/04/07 */
590 static int nopic_need_relax (symbolS *, int);
592 /* handle of the OPCODE hash table */
593 static struct hash_control *op_hash = NULL;
595 /* The opcode hash table we use for the mips16. */
596 static struct hash_control *mips16_op_hash = NULL;
598 /* The opcode hash table we use for the microMIPS ASE. */
599 static struct hash_control *micromips_op_hash = NULL;
601 /* This array holds the chars that always start a comment. If the
602 pre-processor is disabled, these aren't very useful */
603 const char comment_chars[] = "#";
605 /* This array holds the chars that only start a comment at the beginning of
606 a line. If the line seems to have the form '# 123 filename'
607 .line and .file directives will appear in the pre-processed output */
608 /* Note that input_file.c hand checks for '#' at the beginning of the
609 first line of the input file. This is because the compiler outputs
610 #NO_APP at the beginning of its output. */
611 /* Also note that C style comments are always supported. */
612 const char line_comment_chars[] = "#";
614 /* This array holds machine specific line separator characters. */
615 const char line_separator_chars[] = ";";
617 /* Chars that can be used to separate mant from exp in floating point nums */
618 const char EXP_CHARS[] = "eE";
620 /* Chars that mean this number is a floating point constant */
623 const char FLT_CHARS[] = "rRsSfFdDxXpP";
625 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
626 changed in read.c . Ideally it shouldn't have to know about it at all,
627 but nothing is ideal around here.
630 static char *insn_error;
632 static int auto_align = 1;
634 /* When outputting SVR4 PIC code, the assembler needs to know the
635 offset in the stack frame from which to restore the $gp register.
636 This is set by the .cprestore pseudo-op, and saved in this
638 static offsetT mips_cprestore_offset = -1;
640 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
641 more optimizations, it can use a register value instead of a memory-saved
642 offset and even an other register than $gp as global pointer. */
643 static offsetT mips_cpreturn_offset = -1;
644 static int mips_cpreturn_register = -1;
645 static int mips_gp_register = GP;
646 static int mips_gprel_offset = 0;
648 /* Whether mips_cprestore_offset has been set in the current function
649 (or whether it has already been warned about, if not). */
650 static int mips_cprestore_valid = 0;
652 /* This is the register which holds the stack frame, as set by the
653 .frame pseudo-op. This is needed to implement .cprestore. */
654 static int mips_frame_reg = SP;
656 /* Whether mips_frame_reg has been set in the current function
657 (or whether it has already been warned about, if not). */
658 static int mips_frame_reg_valid = 0;
660 /* To output NOP instructions correctly, we need to keep information
661 about the previous two instructions. */
663 /* Whether we are optimizing. The default value of 2 means to remove
664 unneeded NOPs and swap branch instructions when possible. A value
665 of 1 means to not swap branches. A value of 0 means to always
667 static int mips_optimize = 2;
669 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
670 equivalent to seeing no -g option at all. */
671 static int mips_debug = 0;
673 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
674 #define MAX_VR4130_NOPS 4
676 /* The maximum number of NOPs needed to fill delay slots. */
677 #define MAX_DELAY_NOPS 2
679 /* The maximum number of NOPs needed for any purpose. */
682 /* A list of previous instructions, with index 0 being the most recent.
683 We need to look back MAX_NOPS instructions when filling delay slots
684 or working around processor errata. We need to look back one
685 instruction further if we're thinking about using history[0] to
686 fill a branch delay slot. */
687 static struct mips_cl_insn history[1 + MAX_NOPS];
689 /* Nop instructions used by emit_nop. */
690 static struct mips_cl_insn nop_insn;
691 static struct mips_cl_insn mips16_nop_insn;
692 static struct mips_cl_insn micromips_nop16_insn;
693 static struct mips_cl_insn micromips_nop32_insn;
695 /* The appropriate nop for the current mode. */
696 #define NOP_INSN (mips_opts.mips16 \
698 : (mips_opts.micromips \
699 ? (mips_opts.insn32 \
700 ? µmips_nop32_insn \
701 : µmips_nop16_insn) \
704 /* The size of NOP_INSN in bytes. */
705 #define NOP_INSN_SIZE ((mips_opts.mips16 \
706 || (mips_opts.micromips && !mips_opts.insn32)) \
709 /* If this is set, it points to a frag holding nop instructions which
710 were inserted before the start of a noreorder section. If those
711 nops turn out to be unnecessary, the size of the frag can be
713 static fragS *prev_nop_frag;
715 /* The number of nop instructions we created in prev_nop_frag. */
716 static int prev_nop_frag_holds;
718 /* The number of nop instructions that we know we need in
720 static int prev_nop_frag_required;
722 /* The number of instructions we've seen since prev_nop_frag. */
723 static int prev_nop_frag_since;
725 /* Relocations against symbols are sometimes done in two parts, with a HI
726 relocation and a LO relocation. Each relocation has only 16 bits of
727 space to store an addend. This means that in order for the linker to
728 handle carries correctly, it must be able to locate both the HI and
729 the LO relocation. This means that the relocations must appear in
730 order in the relocation table.
732 In order to implement this, we keep track of each unmatched HI
733 relocation. We then sort them so that they immediately precede the
734 corresponding LO relocation. */
739 struct mips_hi_fixup *next;
742 /* The section this fixup is in. */
746 /* The list of unmatched HI relocs. */
748 static struct mips_hi_fixup *mips_hi_fixup_list;
750 /* The frag containing the last explicit relocation operator.
751 Null if explicit relocations have not been used. */
753 static fragS *prev_reloc_op_frag;
755 /* Map normal MIPS register numbers to mips16 register numbers. */
757 #define X ILLEGAL_REG
758 static const int mips32_to_16_reg_map[] =
760 X, X, 2, 3, 4, 5, 6, 7,
761 X, X, X, X, X, X, X, X,
762 0, 1, X, X, X, X, X, X,
763 X, X, X, X, X, X, X, X
767 /* Map mips16 register numbers to normal MIPS register numbers. */
769 static const unsigned int mips16_to_32_reg_map[] =
771 16, 17, 2, 3, 4, 5, 6, 7
774 /* Map normal MIPS register numbers to microMIPS register numbers. */
776 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
777 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
778 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
779 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
780 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
781 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
782 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
784 #define X ILLEGAL_REG
785 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
786 static const int mips32_to_micromips_reg_m_map[] =
788 0, X, 2, 3, X, X, X, X,
789 X, X, X, X, X, X, X, X,
790 4, 1, 5, 6, 7, X, X, X,
791 X, X, X, X, X, X, X, X
794 /* reg type q: 0, 2-7. 17. */
795 static const int mips32_to_micromips_reg_q_map[] =
797 0, X, 2, 3, 4, 5, 6, 7,
798 X, X, X, X, X, X, X, X,
799 X, 1, X, X, X, X, X, X,
800 X, X, X, X, X, X, X, X
803 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
806 /* Map microMIPS register numbers to normal MIPS register numbers. */
808 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
809 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
810 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
811 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
812 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
813 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
815 /* The microMIPS registers with type h. */
816 static const unsigned int micromips_to_32_reg_h_map1[] =
818 5, 5, 6, 4, 4, 4, 4, 4
820 static const unsigned int micromips_to_32_reg_h_map2[] =
822 6, 7, 7, 21, 22, 5, 6, 7
825 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
827 /* The microMIPS registers with type m. */
828 static const unsigned int micromips_to_32_reg_m_map[] =
830 0, 17, 2, 3, 16, 18, 19, 20
833 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
835 /* The microMIPS registers with type q. */
836 static const unsigned int micromips_to_32_reg_q_map[] =
838 0, 17, 2, 3, 4, 5, 6, 7
841 /* microMIPS imm type B. */
842 static const int micromips_imm_b_map[] =
844 1, 4, 8, 12, 16, 20, 24, -1
847 /* microMIPS imm type C. */
848 static const int micromips_imm_c_map[] =
850 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
853 /* Classifies the kind of instructions we're interested in when
854 implementing -mfix-vr4120. */
855 enum fix_vr4120_class
863 NUM_FIX_VR4120_CLASSES
866 /* ...likewise -mfix-loongson2f-jump. */
867 static bfd_boolean mips_fix_loongson2f_jump;
869 /* ...likewise -mfix-loongson2f-nop. */
870 static bfd_boolean mips_fix_loongson2f_nop;
872 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
873 static bfd_boolean mips_fix_loongson2f;
875 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
876 there must be at least one other instruction between an instruction
877 of type X and an instruction of type Y. */
878 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
880 /* True if -mfix-vr4120 is in force. */
881 static int mips_fix_vr4120;
883 /* ...likewise -mfix-vr4130. */
884 static int mips_fix_vr4130;
886 /* ...likewise -mfix-24k. */
887 static int mips_fix_24k;
889 /* ...likewise -mfix-cn63xxp1 */
890 static bfd_boolean mips_fix_cn63xxp1;
892 /* We don't relax branches by default, since this causes us to expand
893 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
894 fail to compute the offset before expanding the macro to the most
895 efficient expansion. */
897 static int mips_relax_branch;
899 /* The expansion of many macros depends on the type of symbol that
900 they refer to. For example, when generating position-dependent code,
901 a macro that refers to a symbol may have two different expansions,
902 one which uses GP-relative addresses and one which uses absolute
903 addresses. When generating SVR4-style PIC, a macro may have
904 different expansions for local and global symbols.
906 We handle these situations by generating both sequences and putting
907 them in variant frags. In position-dependent code, the first sequence
908 will be the GP-relative one and the second sequence will be the
909 absolute one. In SVR4 PIC, the first sequence will be for global
910 symbols and the second will be for local symbols.
912 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
913 SECOND are the lengths of the two sequences in bytes. These fields
914 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
915 the subtype has the following flags:
918 Set if it has been decided that we should use the second
919 sequence instead of the first.
922 Set in the first variant frag if the macro's second implementation
923 is longer than its first. This refers to the macro as a whole,
924 not an individual relaxation.
927 Set in the first variant frag if the macro appeared in a .set nomacro
928 block and if one alternative requires a warning but the other does not.
931 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
934 RELAX_DELAY_SLOT_16BIT
935 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
938 RELAX_DELAY_SLOT_SIZE_FIRST
939 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
940 the macro is of the wrong size for the branch delay slot.
942 RELAX_DELAY_SLOT_SIZE_SECOND
943 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
944 the macro is of the wrong size for the branch delay slot.
946 The frag's "opcode" points to the first fixup for relaxable code.
948 Relaxable macros are generated using a sequence such as:
950 relax_start (SYMBOL);
951 ... generate first expansion ...
953 ... generate second expansion ...
956 The code and fixups for the unwanted alternative are discarded
957 by md_convert_frag. */
958 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
960 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
961 #define RELAX_SECOND(X) ((X) & 0xff)
962 #define RELAX_USE_SECOND 0x10000
963 #define RELAX_SECOND_LONGER 0x20000
964 #define RELAX_NOMACRO 0x40000
965 #define RELAX_DELAY_SLOT 0x80000
966 #define RELAX_DELAY_SLOT_16BIT 0x100000
967 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
968 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
970 /* Branch without likely bit. If label is out of range, we turn:
972 beq reg1, reg2, label
982 with the following opcode replacements:
989 bltzal <-> bgezal (with jal label instead of j label)
991 Even though keeping the delay slot instruction in the delay slot of
992 the branch would be more efficient, it would be very tricky to do
993 correctly, because we'd have to introduce a variable frag *after*
994 the delay slot instruction, and expand that instead. Let's do it
995 the easy way for now, even if the branch-not-taken case now costs
996 one additional instruction. Out-of-range branches are not supposed
997 to be common, anyway.
999 Branch likely. If label is out of range, we turn:
1001 beql reg1, reg2, label
1002 delay slot (annulled if branch not taken)
1011 delay slot (executed only if branch taken)
1014 It would be possible to generate a shorter sequence by losing the
1015 likely bit, generating something like:
1020 delay slot (executed only if branch taken)
1032 bltzall -> bgezal (with jal label instead of j label)
1033 bgezall -> bltzal (ditto)
1036 but it's not clear that it would actually improve performance. */
1037 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1038 ((relax_substateT) \
1041 | ((toofar) ? 0x20 : 0) \
1042 | ((link) ? 0x40 : 0) \
1043 | ((likely) ? 0x80 : 0) \
1044 | ((uncond) ? 0x100 : 0)))
1045 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1046 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1047 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1048 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1049 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1050 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1052 /* For mips16 code, we use an entirely different form of relaxation.
1053 mips16 supports two versions of most instructions which take
1054 immediate values: a small one which takes some small value, and a
1055 larger one which takes a 16 bit value. Since branches also follow
1056 this pattern, relaxing these values is required.
1058 We can assemble both mips16 and normal MIPS code in a single
1059 object. Therefore, we need to support this type of relaxation at
1060 the same time that we support the relaxation described above. We
1061 use the high bit of the subtype field to distinguish these cases.
1063 The information we store for this type of relaxation is the
1064 argument code found in the opcode file for this relocation, whether
1065 the user explicitly requested a small or extended form, and whether
1066 the relocation is in a jump or jal delay slot. That tells us the
1067 size of the value, and how it should be stored. We also store
1068 whether the fragment is considered to be extended or not. We also
1069 store whether this is known to be a branch to a different section,
1070 whether we have tried to relax this frag yet, and whether we have
1071 ever extended a PC relative fragment because of a shift count. */
1072 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1075 | ((small) ? 0x100 : 0) \
1076 | ((ext) ? 0x200 : 0) \
1077 | ((dslot) ? 0x400 : 0) \
1078 | ((jal_dslot) ? 0x800 : 0))
1079 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1080 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1081 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1082 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1083 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1084 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1085 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1086 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1087 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1088 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1089 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1090 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1092 /* For microMIPS code, we use relaxation similar to one we use for
1093 MIPS16 code. Some instructions that take immediate values support
1094 two encodings: a small one which takes some small value, and a
1095 larger one which takes a 16 bit value. As some branches also follow
1096 this pattern, relaxing these values is required.
1098 We can assemble both microMIPS and normal MIPS code in a single
1099 object. Therefore, we need to support this type of relaxation at
1100 the same time that we support the relaxation described above. We
1101 use one of the high bits of the subtype field to distinguish these
1104 The information we store for this type of relaxation is the argument
1105 code found in the opcode file for this relocation, the register
1106 selected as the assembler temporary, whether the branch is
1107 unconditional, whether it is compact, whether it stores the link
1108 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1109 branches to a sequence of instructions is enabled, and whether the
1110 displacement of a branch is too large to fit as an immediate argument
1111 of a 16-bit and a 32-bit branch, respectively. */
1112 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1113 relax32, toofar16, toofar32) \
1116 | (((at) & 0x1f) << 8) \
1117 | ((uncond) ? 0x2000 : 0) \
1118 | ((compact) ? 0x4000 : 0) \
1119 | ((link) ? 0x8000 : 0) \
1120 | ((relax32) ? 0x10000 : 0) \
1121 | ((toofar16) ? 0x20000 : 0) \
1122 | ((toofar32) ? 0x40000 : 0))
1123 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1124 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1125 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1126 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1127 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1128 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1129 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1131 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1134 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1135 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1136 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1138 /* Sign-extend 16-bit value X. */
1139 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1141 /* Is the given value a sign-extended 32-bit value? */
1142 #define IS_SEXT_32BIT_NUM(x) \
1143 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1144 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1146 /* Is the given value a sign-extended 16-bit value? */
1147 #define IS_SEXT_16BIT_NUM(x) \
1148 (((x) &~ (offsetT) 0x7fff) == 0 \
1149 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1151 /* Is the given value a sign-extended 12-bit value? */
1152 #define IS_SEXT_12BIT_NUM(x) \
1153 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1155 /* Is the given value a sign-extended 9-bit value? */
1156 #define IS_SEXT_9BIT_NUM(x) \
1157 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1159 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1160 #define IS_ZEXT_32BIT_NUM(x) \
1161 (((x) &~ (offsetT) 0xffffffff) == 0 \
1162 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1164 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1165 VALUE << SHIFT. VALUE is evaluated exactly once. */
1166 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1167 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1168 | (((VALUE) & (MASK)) << (SHIFT)))
1170 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1172 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1173 (((STRUCT) >> (SHIFT)) & (MASK))
1175 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1176 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1178 include/opcode/mips.h specifies operand fields using the macros
1179 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1180 with "MIPS16OP" instead of "OP". */
1181 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 OP_MASK_##FIELD, OP_SH_##FIELD); \
1187 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1188 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1190 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1191 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1192 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1194 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1195 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1197 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1198 : EXTRACT_BITS ((INSN).insn_opcode, \
1199 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1200 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1201 EXTRACT_BITS ((INSN).insn_opcode, \
1202 MIPS16OP_MASK_##FIELD, \
1203 MIPS16OP_SH_##FIELD)
1205 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1206 #define MIPS16_EXTEND (0xf000U << 16)
1208 /* Whether or not we are emitting a branch-likely macro. */
1209 static bfd_boolean emit_branch_likely_macro = FALSE;
1211 /* Global variables used when generating relaxable macros. See the
1212 comment above RELAX_ENCODE for more details about how relaxation
1215 /* 0 if we're not emitting a relaxable macro.
1216 1 if we're emitting the first of the two relaxation alternatives.
1217 2 if we're emitting the second alternative. */
1220 /* The first relaxable fixup in the current frag. (In other words,
1221 the first fixup that refers to relaxable code.) */
1224 /* sizes[0] says how many bytes of the first alternative are stored in
1225 the current frag. Likewise sizes[1] for the second alternative. */
1226 unsigned int sizes[2];
1228 /* The symbol on which the choice of sequence depends. */
1232 /* Global variables used to decide whether a macro needs a warning. */
1234 /* True if the macro is in a branch delay slot. */
1235 bfd_boolean delay_slot_p;
1237 /* Set to the length in bytes required if the macro is in a delay slot
1238 that requires a specific length of instruction, otherwise zero. */
1239 unsigned int delay_slot_length;
1241 /* For relaxable macros, sizes[0] is the length of the first alternative
1242 in bytes and sizes[1] is the length of the second alternative.
1243 For non-relaxable macros, both elements give the length of the
1245 unsigned int sizes[2];
1247 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1248 instruction of the first alternative in bytes and first_insn_sizes[1]
1249 is the length of the first instruction of the second alternative.
1250 For non-relaxable macros, both elements give the length of the first
1251 instruction in bytes.
1253 Set to zero if we haven't yet seen the first instruction. */
1254 unsigned int first_insn_sizes[2];
1256 /* For relaxable macros, insns[0] is the number of instructions for the
1257 first alternative and insns[1] is the number of instructions for the
1260 For non-relaxable macros, both elements give the number of
1261 instructions for the macro. */
1262 unsigned int insns[2];
1264 /* The first variant frag for this macro. */
1266 } mips_macro_warning;
1268 /* Prototypes for static functions. */
1270 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1272 static void append_insn
1273 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1274 bfd_boolean expansionp);
1275 static void mips_no_prev_insn (void);
1276 static void macro_build (expressionS *, const char *, const char *, ...);
1277 static void mips16_macro_build
1278 (expressionS *, const char *, const char *, va_list *);
1279 static void load_register (int, expressionS *, int);
1280 static void macro_start (void);
1281 static void macro_end (void);
1282 static void macro (struct mips_cl_insn *ip, char *str);
1283 static void mips16_macro (struct mips_cl_insn * ip);
1284 static void mips_ip (char *str, struct mips_cl_insn * ip);
1285 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1286 static void mips16_immed
1287 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1288 unsigned int, unsigned long *);
1289 static size_t my_getSmallExpression
1290 (expressionS *, bfd_reloc_code_real_type *, char *);
1291 static void my_getExpression (expressionS *, char *);
1292 static void s_align (int);
1293 static void s_change_sec (int);
1294 static void s_change_section (int);
1295 static void s_cons (int);
1296 static void s_float_cons (int);
1297 static void s_mips_globl (int);
1298 static void s_option (int);
1299 static void s_mipsset (int);
1300 static void s_abicalls (int);
1301 static void s_cpload (int);
1302 static void s_cpsetup (int);
1303 static void s_cplocal (int);
1304 static void s_cprestore (int);
1305 static void s_cpreturn (int);
1306 static void s_dtprelword (int);
1307 static void s_dtpreldword (int);
1308 static void s_tprelword (int);
1309 static void s_tpreldword (int);
1310 static void s_gpvalue (int);
1311 static void s_gpword (int);
1312 static void s_gpdword (int);
1313 static void s_ehword (int);
1314 static void s_cpadd (int);
1315 static void s_insn (int);
1316 static void s_nan (int);
1317 static void md_obj_begin (void);
1318 static void md_obj_end (void);
1319 static void s_mips_ent (int);
1320 static void s_mips_end (int);
1321 static void s_mips_frame (int);
1322 static void s_mips_mask (int reg_type);
1323 static void s_mips_stab (int);
1324 static void s_mips_weakext (int);
1325 static void s_mips_file (int);
1326 static void s_mips_loc (int);
1327 static bfd_boolean pic_need_relax (symbolS *, asection *);
1328 static int relaxed_branch_length (fragS *, asection *, int);
1329 static int validate_mips_insn (const struct mips_opcode *);
1330 static int validate_micromips_insn (const struct mips_opcode *);
1331 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1332 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1334 /* Table and functions used to map between CPU/ISA names, and
1335 ISA levels, and CPU numbers. */
1337 struct mips_cpu_info
1339 const char *name; /* CPU or ISA name. */
1340 int flags; /* MIPS_CPU_* flags. */
1341 int ase; /* Set of ASEs implemented by the CPU. */
1342 int isa; /* ISA level. */
1343 int cpu; /* CPU number (default CPU if ISA). */
1346 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1348 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1349 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1350 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1352 /* Command-line options. */
1353 const char *md_shortopts = "O::g::G:";
1357 OPTION_MARCH = OPTION_MD_BASE,
1381 OPTION_NO_SMARTMIPS,
1387 OPTION_NO_MICROMIPS,
1390 OPTION_COMPAT_ARCH_BASE,
1399 OPTION_M7000_HILO_FIX,
1400 OPTION_MNO_7000_HILO_FIX,
1403 OPTION_FIX_LOONGSON2F_JUMP,
1404 OPTION_NO_FIX_LOONGSON2F_JUMP,
1405 OPTION_FIX_LOONGSON2F_NOP,
1406 OPTION_NO_FIX_LOONGSON2F_NOP,
1408 OPTION_NO_FIX_VR4120,
1410 OPTION_NO_FIX_VR4130,
1411 OPTION_FIX_CN63XXP1,
1412 OPTION_NO_FIX_CN63XXP1,
1419 OPTION_CONSTRUCT_FLOATS,
1420 OPTION_NO_CONSTRUCT_FLOATS,
1423 OPTION_RELAX_BRANCH,
1424 OPTION_NO_RELAX_BRANCH,
1433 OPTION_SINGLE_FLOAT,
1434 OPTION_DOUBLE_FLOAT,
1447 OPTION_MVXWORKS_PIC,
1452 struct option md_longopts[] =
1454 /* Options which specify architecture. */
1455 {"march", required_argument, NULL, OPTION_MARCH},
1456 {"mtune", required_argument, NULL, OPTION_MTUNE},
1457 {"mips0", no_argument, NULL, OPTION_MIPS1},
1458 {"mips1", no_argument, NULL, OPTION_MIPS1},
1459 {"mips2", no_argument, NULL, OPTION_MIPS2},
1460 {"mips3", no_argument, NULL, OPTION_MIPS3},
1461 {"mips4", no_argument, NULL, OPTION_MIPS4},
1462 {"mips5", no_argument, NULL, OPTION_MIPS5},
1463 {"mips32", no_argument, NULL, OPTION_MIPS32},
1464 {"mips64", no_argument, NULL, OPTION_MIPS64},
1465 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1466 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1468 /* Options which specify Application Specific Extensions (ASEs). */
1469 {"mips16", no_argument, NULL, OPTION_MIPS16},
1470 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1471 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1472 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1473 {"mdmx", no_argument, NULL, OPTION_MDMX},
1474 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1475 {"mdsp", no_argument, NULL, OPTION_DSP},
1476 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1477 {"mmt", no_argument, NULL, OPTION_MT},
1478 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1479 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1480 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1481 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1482 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1483 {"meva", no_argument, NULL, OPTION_EVA},
1484 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1485 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1486 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1487 {"mmcu", no_argument, NULL, OPTION_MCU},
1488 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1489 {"mvirt", no_argument, NULL, OPTION_VIRT},
1490 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1492 /* Old-style architecture options. Don't add more of these. */
1493 {"m4650", no_argument, NULL, OPTION_M4650},
1494 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1495 {"m4010", no_argument, NULL, OPTION_M4010},
1496 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1497 {"m4100", no_argument, NULL, OPTION_M4100},
1498 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1499 {"m3900", no_argument, NULL, OPTION_M3900},
1500 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1502 /* Options which enable bug fixes. */
1503 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1504 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1505 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1506 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1507 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1508 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1509 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1510 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1511 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1512 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1513 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1514 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1515 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1516 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1517 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1519 /* Miscellaneous options. */
1520 {"trap", no_argument, NULL, OPTION_TRAP},
1521 {"no-break", no_argument, NULL, OPTION_TRAP},
1522 {"break", no_argument, NULL, OPTION_BREAK},
1523 {"no-trap", no_argument, NULL, OPTION_BREAK},
1524 {"EB", no_argument, NULL, OPTION_EB},
1525 {"EL", no_argument, NULL, OPTION_EL},
1526 {"mfp32", no_argument, NULL, OPTION_FP32},
1527 {"mgp32", no_argument, NULL, OPTION_GP32},
1528 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1529 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1530 {"mfp64", no_argument, NULL, OPTION_FP64},
1531 {"mgp64", no_argument, NULL, OPTION_GP64},
1532 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1533 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1534 {"minsn32", no_argument, NULL, OPTION_INSN32},
1535 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1536 {"mshared", no_argument, NULL, OPTION_MSHARED},
1537 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1538 {"msym32", no_argument, NULL, OPTION_MSYM32},
1539 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1540 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1541 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1542 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1543 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1545 /* Strictly speaking this next option is ELF specific,
1546 but we allow it for other ports as well in order to
1547 make testing easier. */
1548 {"32", no_argument, NULL, OPTION_32},
1550 /* ELF-specific options. */
1551 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1552 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1553 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1554 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1555 {"xgot", no_argument, NULL, OPTION_XGOT},
1556 {"mabi", required_argument, NULL, OPTION_MABI},
1557 {"n32", no_argument, NULL, OPTION_N32},
1558 {"64", no_argument, NULL, OPTION_64},
1559 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1560 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1561 {"mpdr", no_argument, NULL, OPTION_PDR},
1562 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1563 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1564 {"mnan", required_argument, NULL, OPTION_NAN},
1566 {NULL, no_argument, NULL, 0}
1568 size_t md_longopts_size = sizeof (md_longopts);
1570 /* Information about either an Application Specific Extension or an
1571 optional architecture feature that, for simplicity, we treat in the
1572 same way as an ASE. */
1575 /* The name of the ASE, used in both the command-line and .set options. */
1578 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1579 and 64-bit architectures, the flags here refer to the subset that
1580 is available on both. */
1583 /* The ASE_* flag used for instructions that are available on 64-bit
1584 architectures but that are not included in FLAGS. */
1585 unsigned int flags64;
1587 /* The command-line options that turn the ASE on and off. */
1591 /* The minimum required architecture revisions for MIPS32, MIPS64,
1592 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1595 int micromips32_rev;
1596 int micromips64_rev;
1599 /* A table of all supported ASEs. */
1600 static const struct mips_ase mips_ases[] = {
1601 { "dsp", ASE_DSP, ASE_DSP64,
1602 OPTION_DSP, OPTION_NO_DSP,
1605 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1606 OPTION_DSPR2, OPTION_NO_DSPR2,
1609 { "eva", ASE_EVA, 0,
1610 OPTION_EVA, OPTION_NO_EVA,
1613 { "mcu", ASE_MCU, 0,
1614 OPTION_MCU, OPTION_NO_MCU,
1617 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1618 { "mdmx", ASE_MDMX, 0,
1619 OPTION_MDMX, OPTION_NO_MDMX,
1622 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1623 { "mips3d", ASE_MIPS3D, 0,
1624 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1628 OPTION_MT, OPTION_NO_MT,
1631 { "smartmips", ASE_SMARTMIPS, 0,
1632 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1635 { "virt", ASE_VIRT, ASE_VIRT64,
1636 OPTION_VIRT, OPTION_NO_VIRT,
1640 /* The set of ASEs that require -mfp64. */
1641 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1643 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1644 static const unsigned int mips_ase_groups[] = {
1650 The following pseudo-ops from the Kane and Heinrich MIPS book
1651 should be defined here, but are currently unsupported: .alias,
1652 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1654 The following pseudo-ops from the Kane and Heinrich MIPS book are
1655 specific to the type of debugging information being generated, and
1656 should be defined by the object format: .aent, .begin, .bend,
1657 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1660 The following pseudo-ops from the Kane and Heinrich MIPS book are
1661 not MIPS CPU specific, but are also not specific to the object file
1662 format. This file is probably the best place to define them, but
1663 they are not currently supported: .asm0, .endr, .lab, .struct. */
1665 static const pseudo_typeS mips_pseudo_table[] =
1667 /* MIPS specific pseudo-ops. */
1668 {"option", s_option, 0},
1669 {"set", s_mipsset, 0},
1670 {"rdata", s_change_sec, 'r'},
1671 {"sdata", s_change_sec, 's'},
1672 {"livereg", s_ignore, 0},
1673 {"abicalls", s_abicalls, 0},
1674 {"cpload", s_cpload, 0},
1675 {"cpsetup", s_cpsetup, 0},
1676 {"cplocal", s_cplocal, 0},
1677 {"cprestore", s_cprestore, 0},
1678 {"cpreturn", s_cpreturn, 0},
1679 {"dtprelword", s_dtprelword, 0},
1680 {"dtpreldword", s_dtpreldword, 0},
1681 {"tprelword", s_tprelword, 0},
1682 {"tpreldword", s_tpreldword, 0},
1683 {"gpvalue", s_gpvalue, 0},
1684 {"gpword", s_gpword, 0},
1685 {"gpdword", s_gpdword, 0},
1686 {"ehword", s_ehword, 0},
1687 {"cpadd", s_cpadd, 0},
1688 {"insn", s_insn, 0},
1691 /* Relatively generic pseudo-ops that happen to be used on MIPS
1693 {"asciiz", stringer, 8 + 1},
1694 {"bss", s_change_sec, 'b'},
1696 {"half", s_cons, 1},
1697 {"dword", s_cons, 3},
1698 {"weakext", s_mips_weakext, 0},
1699 {"origin", s_org, 0},
1700 {"repeat", s_rept, 0},
1702 /* For MIPS this is non-standard, but we define it for consistency. */
1703 {"sbss", s_change_sec, 'B'},
1705 /* These pseudo-ops are defined in read.c, but must be overridden
1706 here for one reason or another. */
1707 {"align", s_align, 0},
1708 {"byte", s_cons, 0},
1709 {"data", s_change_sec, 'd'},
1710 {"double", s_float_cons, 'd'},
1711 {"float", s_float_cons, 'f'},
1712 {"globl", s_mips_globl, 0},
1713 {"global", s_mips_globl, 0},
1714 {"hword", s_cons, 1},
1716 {"long", s_cons, 2},
1717 {"octa", s_cons, 4},
1718 {"quad", s_cons, 3},
1719 {"section", s_change_section, 0},
1720 {"short", s_cons, 1},
1721 {"single", s_float_cons, 'f'},
1722 {"stabd", s_mips_stab, 'd'},
1723 {"stabn", s_mips_stab, 'n'},
1724 {"stabs", s_mips_stab, 's'},
1725 {"text", s_change_sec, 't'},
1726 {"word", s_cons, 2},
1728 { "extern", ecoff_directive_extern, 0},
1733 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1735 /* These pseudo-ops should be defined by the object file format.
1736 However, a.out doesn't support them, so we have versions here. */
1737 {"aent", s_mips_ent, 1},
1738 {"bgnb", s_ignore, 0},
1739 {"end", s_mips_end, 0},
1740 {"endb", s_ignore, 0},
1741 {"ent", s_mips_ent, 0},
1742 {"file", s_mips_file, 0},
1743 {"fmask", s_mips_mask, 'F'},
1744 {"frame", s_mips_frame, 0},
1745 {"loc", s_mips_loc, 0},
1746 {"mask", s_mips_mask, 'R'},
1747 {"verstamp", s_ignore, 0},
1751 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1752 purpose of the `.dc.a' internal pseudo-op. */
1755 mips_address_bytes (void)
1757 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1760 extern void pop_insert (const pseudo_typeS *);
1763 mips_pop_insert (void)
1765 pop_insert (mips_pseudo_table);
1766 if (! ECOFF_DEBUGGING)
1767 pop_insert (mips_nonecoff_pseudo_table);
1770 /* Symbols labelling the current insn. */
1772 struct insn_label_list
1774 struct insn_label_list *next;
1778 static struct insn_label_list *free_insn_labels;
1779 #define label_list tc_segment_info_data.labels
1781 static void mips_clear_insn_labels (void);
1782 static void mips_mark_labels (void);
1783 static void mips_compressed_mark_labels (void);
1786 mips_clear_insn_labels (void)
1788 register struct insn_label_list **pl;
1789 segment_info_type *si;
1793 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1796 si = seg_info (now_seg);
1797 *pl = si->label_list;
1798 si->label_list = NULL;
1802 /* Mark instruction labels in MIPS16/microMIPS mode. */
1805 mips_mark_labels (void)
1807 if (HAVE_CODE_COMPRESSION)
1808 mips_compressed_mark_labels ();
1811 static char *expr_end;
1813 /* Expressions which appear in macro instructions. These are set by
1814 mips_ip and read by macro. */
1816 static expressionS imm_expr;
1817 static expressionS imm2_expr;
1819 /* The relocatable field in an instruction and the relocs associated
1820 with it. These variables are used for instructions like LUI and
1821 JAL as well as true offsets. They are also used for address
1822 operands in macros. */
1824 static expressionS offset_expr;
1825 static bfd_reloc_code_real_type offset_reloc[3]
1826 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1828 /* This is set to the resulting size of the instruction to be produced
1829 by mips16_ip if an explicit extension is used or by mips_ip if an
1830 explicit size is supplied. */
1832 static unsigned int forced_insn_length;
1834 /* True if we are assembling an instruction. All dot symbols defined during
1835 this time should be treated as code labels. */
1837 static bfd_boolean mips_assembling_insn;
1839 /* The pdr segment for per procedure frame/regmask info. Not used for
1842 static segT pdr_seg;
1844 /* The default target format to use. */
1846 #if defined (TE_FreeBSD)
1847 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1848 #elif defined (TE_TMIPS)
1849 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1851 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1855 mips_target_format (void)
1857 switch (OUTPUT_FLAVOR)
1859 case bfd_target_elf_flavour:
1861 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1862 return (target_big_endian
1863 ? "elf32-bigmips-vxworks"
1864 : "elf32-littlemips-vxworks");
1866 return (target_big_endian
1867 ? (HAVE_64BIT_OBJECTS
1868 ? ELF_TARGET ("elf64-", "big")
1870 ? ELF_TARGET ("elf32-n", "big")
1871 : ELF_TARGET ("elf32-", "big")))
1872 : (HAVE_64BIT_OBJECTS
1873 ? ELF_TARGET ("elf64-", "little")
1875 ? ELF_TARGET ("elf32-n", "little")
1876 : ELF_TARGET ("elf32-", "little"))));
1883 /* Return the ISA revision that is currently in use, or 0 if we are
1884 generating code for MIPS V or below. */
1889 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1892 /* microMIPS implies revision 2 or above. */
1893 if (mips_opts.micromips)
1896 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1902 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1905 mips_ase_mask (unsigned int flags)
1909 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1910 if (flags & mips_ase_groups[i])
1911 flags |= mips_ase_groups[i];
1915 /* Check whether the current ISA supports ASE. Issue a warning if
1919 mips_check_isa_supports_ase (const struct mips_ase *ase)
1923 static unsigned int warned_isa;
1924 static unsigned int warned_fp32;
1926 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1927 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1929 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1930 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1931 && (warned_isa & ase->flags) != ase->flags)
1933 warned_isa |= ase->flags;
1934 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1935 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1937 as_warn (_("The %d-bit %s architecture does not support the"
1938 " `%s' extension"), size, base, ase->name);
1940 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1941 ase->name, base, size, min_rev);
1943 if ((ase->flags & FP64_ASES)
1945 && (warned_fp32 & ase->flags) != ase->flags)
1947 warned_fp32 |= ase->flags;
1948 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1952 /* Check all enabled ASEs to see whether they are supported by the
1953 chosen architecture. */
1956 mips_check_isa_supports_ases (void)
1958 unsigned int i, mask;
1960 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1962 mask = mips_ase_mask (mips_ases[i].flags);
1963 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1964 mips_check_isa_supports_ase (&mips_ases[i]);
1968 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1969 that were affected. */
1972 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1976 mask = mips_ase_mask (ase->flags);
1977 mips_opts.ase &= ~mask;
1979 mips_opts.ase |= ase->flags;
1983 /* Return the ASE called NAME, or null if none. */
1985 static const struct mips_ase *
1986 mips_lookup_ase (const char *name)
1990 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1991 if (strcmp (name, mips_ases[i].name) == 0)
1992 return &mips_ases[i];
1996 /* Return the length of a microMIPS instruction in bytes. If bits of
1997 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1998 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1999 major opcode) will require further modifications to the opcode
2002 static inline unsigned int
2003 micromips_insn_length (const struct mips_opcode *mo)
2005 return (mo->mask >> 16) == 0 ? 2 : 4;
2008 /* Return the length of MIPS16 instruction OPCODE. */
2010 static inline unsigned int
2011 mips16_opcode_length (unsigned long opcode)
2013 return (opcode >> 16) == 0 ? 2 : 4;
2016 /* Return the length of instruction INSN. */
2018 static inline unsigned int
2019 insn_length (const struct mips_cl_insn *insn)
2021 if (mips_opts.micromips)
2022 return micromips_insn_length (insn->insn_mo);
2023 else if (mips_opts.mips16)
2024 return mips16_opcode_length (insn->insn_opcode);
2029 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2032 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2037 insn->insn_opcode = mo->match;
2040 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2041 insn->fixp[i] = NULL;
2042 insn->fixed_p = (mips_opts.noreorder > 0);
2043 insn->noreorder_p = (mips_opts.noreorder > 0);
2044 insn->mips16_absolute_jump_p = 0;
2045 insn->complete_p = 0;
2046 insn->cleared_p = 0;
2049 /* Record the current MIPS16/microMIPS mode in now_seg. */
2052 mips_record_compressed_mode (void)
2054 segment_info_type *si;
2056 si = seg_info (now_seg);
2057 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2058 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2059 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2060 si->tc_segment_info_data.micromips = mips_opts.micromips;
2063 /* Read a standard MIPS instruction from BUF. */
2065 static unsigned long
2066 read_insn (char *buf)
2068 if (target_big_endian)
2069 return bfd_getb32 ((bfd_byte *) buf);
2071 return bfd_getl32 ((bfd_byte *) buf);
2074 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2078 write_insn (char *buf, unsigned int insn)
2080 md_number_to_chars (buf, insn, 4);
2084 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2085 has length LENGTH. */
2087 static unsigned long
2088 read_compressed_insn (char *buf, unsigned int length)
2094 for (i = 0; i < length; i += 2)
2097 if (target_big_endian)
2098 insn |= bfd_getb16 ((char *) buf);
2100 insn |= bfd_getl16 ((char *) buf);
2106 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2107 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2110 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2114 for (i = 0; i < length; i += 2)
2115 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2116 return buf + length;
2119 /* Install INSN at the location specified by its "frag" and "where" fields. */
2122 install_insn (const struct mips_cl_insn *insn)
2124 char *f = insn->frag->fr_literal + insn->where;
2125 if (HAVE_CODE_COMPRESSION)
2126 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2128 write_insn (f, insn->insn_opcode);
2129 mips_record_compressed_mode ();
2132 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2133 and install the opcode in the new location. */
2136 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2141 insn->where = where;
2142 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2143 if (insn->fixp[i] != NULL)
2145 insn->fixp[i]->fx_frag = frag;
2146 insn->fixp[i]->fx_where = where;
2148 install_insn (insn);
2151 /* Add INSN to the end of the output. */
2154 add_fixed_insn (struct mips_cl_insn *insn)
2156 char *f = frag_more (insn_length (insn));
2157 move_insn (insn, frag_now, f - frag_now->fr_literal);
2160 /* Start a variant frag and move INSN to the start of the variant part,
2161 marking it as fixed. The other arguments are as for frag_var. */
2164 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2165 relax_substateT subtype, symbolS *symbol, offsetT offset)
2167 frag_grow (max_chars);
2168 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2170 frag_var (rs_machine_dependent, max_chars, var,
2171 subtype, symbol, offset, NULL);
2174 /* Insert N copies of INSN into the history buffer, starting at
2175 position FIRST. Neither FIRST nor N need to be clipped. */
2178 insert_into_history (unsigned int first, unsigned int n,
2179 const struct mips_cl_insn *insn)
2181 if (mips_relax.sequence != 2)
2185 for (i = ARRAY_SIZE (history); i-- > first;)
2187 history[i] = history[i - n];
2193 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2194 the idea is to make it obvious at a glance that each errata is
2198 init_vr4120_conflicts (void)
2200 #define CONFLICT(FIRST, SECOND) \
2201 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2203 /* Errata 21 - [D]DIV[U] after [D]MACC */
2204 CONFLICT (MACC, DIV);
2205 CONFLICT (DMACC, DIV);
2207 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2208 CONFLICT (DMULT, DMULT);
2209 CONFLICT (DMULT, DMACC);
2210 CONFLICT (DMACC, DMULT);
2211 CONFLICT (DMACC, DMACC);
2213 /* Errata 24 - MT{LO,HI} after [D]MACC */
2214 CONFLICT (MACC, MTHILO);
2215 CONFLICT (DMACC, MTHILO);
2217 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2218 instruction is executed immediately after a MACC or DMACC
2219 instruction, the result of [either instruction] is incorrect." */
2220 CONFLICT (MACC, MULT);
2221 CONFLICT (MACC, DMULT);
2222 CONFLICT (DMACC, MULT);
2223 CONFLICT (DMACC, DMULT);
2225 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2226 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2227 DDIV or DDIVU instruction, the result of the MACC or
2228 DMACC instruction is incorrect.". */
2229 CONFLICT (DMULT, MACC);
2230 CONFLICT (DMULT, DMACC);
2231 CONFLICT (DIV, MACC);
2232 CONFLICT (DIV, DMACC);
2242 #define RTYPE_MASK 0x1ff00
2243 #define RTYPE_NUM 0x00100
2244 #define RTYPE_FPU 0x00200
2245 #define RTYPE_FCC 0x00400
2246 #define RTYPE_VEC 0x00800
2247 #define RTYPE_GP 0x01000
2248 #define RTYPE_CP0 0x02000
2249 #define RTYPE_PC 0x04000
2250 #define RTYPE_ACC 0x08000
2251 #define RTYPE_CCC 0x10000
2252 #define RNUM_MASK 0x000ff
2253 #define RWARN 0x80000
2255 #define GENERIC_REGISTER_NUMBERS \
2256 {"$0", RTYPE_NUM | 0}, \
2257 {"$1", RTYPE_NUM | 1}, \
2258 {"$2", RTYPE_NUM | 2}, \
2259 {"$3", RTYPE_NUM | 3}, \
2260 {"$4", RTYPE_NUM | 4}, \
2261 {"$5", RTYPE_NUM | 5}, \
2262 {"$6", RTYPE_NUM | 6}, \
2263 {"$7", RTYPE_NUM | 7}, \
2264 {"$8", RTYPE_NUM | 8}, \
2265 {"$9", RTYPE_NUM | 9}, \
2266 {"$10", RTYPE_NUM | 10}, \
2267 {"$11", RTYPE_NUM | 11}, \
2268 {"$12", RTYPE_NUM | 12}, \
2269 {"$13", RTYPE_NUM | 13}, \
2270 {"$14", RTYPE_NUM | 14}, \
2271 {"$15", RTYPE_NUM | 15}, \
2272 {"$16", RTYPE_NUM | 16}, \
2273 {"$17", RTYPE_NUM | 17}, \
2274 {"$18", RTYPE_NUM | 18}, \
2275 {"$19", RTYPE_NUM | 19}, \
2276 {"$20", RTYPE_NUM | 20}, \
2277 {"$21", RTYPE_NUM | 21}, \
2278 {"$22", RTYPE_NUM | 22}, \
2279 {"$23", RTYPE_NUM | 23}, \
2280 {"$24", RTYPE_NUM | 24}, \
2281 {"$25", RTYPE_NUM | 25}, \
2282 {"$26", RTYPE_NUM | 26}, \
2283 {"$27", RTYPE_NUM | 27}, \
2284 {"$28", RTYPE_NUM | 28}, \
2285 {"$29", RTYPE_NUM | 29}, \
2286 {"$30", RTYPE_NUM | 30}, \
2287 {"$31", RTYPE_NUM | 31}
2289 #define FPU_REGISTER_NAMES \
2290 {"$f0", RTYPE_FPU | 0}, \
2291 {"$f1", RTYPE_FPU | 1}, \
2292 {"$f2", RTYPE_FPU | 2}, \
2293 {"$f3", RTYPE_FPU | 3}, \
2294 {"$f4", RTYPE_FPU | 4}, \
2295 {"$f5", RTYPE_FPU | 5}, \
2296 {"$f6", RTYPE_FPU | 6}, \
2297 {"$f7", RTYPE_FPU | 7}, \
2298 {"$f8", RTYPE_FPU | 8}, \
2299 {"$f9", RTYPE_FPU | 9}, \
2300 {"$f10", RTYPE_FPU | 10}, \
2301 {"$f11", RTYPE_FPU | 11}, \
2302 {"$f12", RTYPE_FPU | 12}, \
2303 {"$f13", RTYPE_FPU | 13}, \
2304 {"$f14", RTYPE_FPU | 14}, \
2305 {"$f15", RTYPE_FPU | 15}, \
2306 {"$f16", RTYPE_FPU | 16}, \
2307 {"$f17", RTYPE_FPU | 17}, \
2308 {"$f18", RTYPE_FPU | 18}, \
2309 {"$f19", RTYPE_FPU | 19}, \
2310 {"$f20", RTYPE_FPU | 20}, \
2311 {"$f21", RTYPE_FPU | 21}, \
2312 {"$f22", RTYPE_FPU | 22}, \
2313 {"$f23", RTYPE_FPU | 23}, \
2314 {"$f24", RTYPE_FPU | 24}, \
2315 {"$f25", RTYPE_FPU | 25}, \
2316 {"$f26", RTYPE_FPU | 26}, \
2317 {"$f27", RTYPE_FPU | 27}, \
2318 {"$f28", RTYPE_FPU | 28}, \
2319 {"$f29", RTYPE_FPU | 29}, \
2320 {"$f30", RTYPE_FPU | 30}, \
2321 {"$f31", RTYPE_FPU | 31}
2323 #define FPU_CONDITION_CODE_NAMES \
2324 {"$fcc0", RTYPE_FCC | 0}, \
2325 {"$fcc1", RTYPE_FCC | 1}, \
2326 {"$fcc2", RTYPE_FCC | 2}, \
2327 {"$fcc3", RTYPE_FCC | 3}, \
2328 {"$fcc4", RTYPE_FCC | 4}, \
2329 {"$fcc5", RTYPE_FCC | 5}, \
2330 {"$fcc6", RTYPE_FCC | 6}, \
2331 {"$fcc7", RTYPE_FCC | 7}
2333 #define COPROC_CONDITION_CODE_NAMES \
2334 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2335 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2336 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2337 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2338 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2339 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2340 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2341 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2343 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2344 {"$a4", RTYPE_GP | 8}, \
2345 {"$a5", RTYPE_GP | 9}, \
2346 {"$a6", RTYPE_GP | 10}, \
2347 {"$a7", RTYPE_GP | 11}, \
2348 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2349 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2350 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2351 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2352 {"$t0", RTYPE_GP | 12}, \
2353 {"$t1", RTYPE_GP | 13}, \
2354 {"$t2", RTYPE_GP | 14}, \
2355 {"$t3", RTYPE_GP | 15}
2357 #define O32_SYMBOLIC_REGISTER_NAMES \
2358 {"$t0", RTYPE_GP | 8}, \
2359 {"$t1", RTYPE_GP | 9}, \
2360 {"$t2", RTYPE_GP | 10}, \
2361 {"$t3", RTYPE_GP | 11}, \
2362 {"$t4", RTYPE_GP | 12}, \
2363 {"$t5", RTYPE_GP | 13}, \
2364 {"$t6", RTYPE_GP | 14}, \
2365 {"$t7", RTYPE_GP | 15}, \
2366 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2367 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2368 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2369 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2371 /* Remaining symbolic register names */
2372 #define SYMBOLIC_REGISTER_NAMES \
2373 {"$zero", RTYPE_GP | 0}, \
2374 {"$at", RTYPE_GP | 1}, \
2375 {"$AT", RTYPE_GP | 1}, \
2376 {"$v0", RTYPE_GP | 2}, \
2377 {"$v1", RTYPE_GP | 3}, \
2378 {"$a0", RTYPE_GP | 4}, \
2379 {"$a1", RTYPE_GP | 5}, \
2380 {"$a2", RTYPE_GP | 6}, \
2381 {"$a3", RTYPE_GP | 7}, \
2382 {"$s0", RTYPE_GP | 16}, \
2383 {"$s1", RTYPE_GP | 17}, \
2384 {"$s2", RTYPE_GP | 18}, \
2385 {"$s3", RTYPE_GP | 19}, \
2386 {"$s4", RTYPE_GP | 20}, \
2387 {"$s5", RTYPE_GP | 21}, \
2388 {"$s6", RTYPE_GP | 22}, \
2389 {"$s7", RTYPE_GP | 23}, \
2390 {"$t8", RTYPE_GP | 24}, \
2391 {"$t9", RTYPE_GP | 25}, \
2392 {"$k0", RTYPE_GP | 26}, \
2393 {"$kt0", RTYPE_GP | 26}, \
2394 {"$k1", RTYPE_GP | 27}, \
2395 {"$kt1", RTYPE_GP | 27}, \
2396 {"$gp", RTYPE_GP | 28}, \
2397 {"$sp", RTYPE_GP | 29}, \
2398 {"$s8", RTYPE_GP | 30}, \
2399 {"$fp", RTYPE_GP | 30}, \
2400 {"$ra", RTYPE_GP | 31}
2402 #define MIPS16_SPECIAL_REGISTER_NAMES \
2403 {"$pc", RTYPE_PC | 0}
2405 #define MDMX_VECTOR_REGISTER_NAMES \
2406 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2407 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2408 {"$v2", RTYPE_VEC | 2}, \
2409 {"$v3", RTYPE_VEC | 3}, \
2410 {"$v4", RTYPE_VEC | 4}, \
2411 {"$v5", RTYPE_VEC | 5}, \
2412 {"$v6", RTYPE_VEC | 6}, \
2413 {"$v7", RTYPE_VEC | 7}, \
2414 {"$v8", RTYPE_VEC | 8}, \
2415 {"$v9", RTYPE_VEC | 9}, \
2416 {"$v10", RTYPE_VEC | 10}, \
2417 {"$v11", RTYPE_VEC | 11}, \
2418 {"$v12", RTYPE_VEC | 12}, \
2419 {"$v13", RTYPE_VEC | 13}, \
2420 {"$v14", RTYPE_VEC | 14}, \
2421 {"$v15", RTYPE_VEC | 15}, \
2422 {"$v16", RTYPE_VEC | 16}, \
2423 {"$v17", RTYPE_VEC | 17}, \
2424 {"$v18", RTYPE_VEC | 18}, \
2425 {"$v19", RTYPE_VEC | 19}, \
2426 {"$v20", RTYPE_VEC | 20}, \
2427 {"$v21", RTYPE_VEC | 21}, \
2428 {"$v22", RTYPE_VEC | 22}, \
2429 {"$v23", RTYPE_VEC | 23}, \
2430 {"$v24", RTYPE_VEC | 24}, \
2431 {"$v25", RTYPE_VEC | 25}, \
2432 {"$v26", RTYPE_VEC | 26}, \
2433 {"$v27", RTYPE_VEC | 27}, \
2434 {"$v28", RTYPE_VEC | 28}, \
2435 {"$v29", RTYPE_VEC | 29}, \
2436 {"$v30", RTYPE_VEC | 30}, \
2437 {"$v31", RTYPE_VEC | 31}
2439 #define MIPS_DSP_ACCUMULATOR_NAMES \
2440 {"$ac0", RTYPE_ACC | 0}, \
2441 {"$ac1", RTYPE_ACC | 1}, \
2442 {"$ac2", RTYPE_ACC | 2}, \
2443 {"$ac3", RTYPE_ACC | 3}
2445 static const struct regname reg_names[] = {
2446 GENERIC_REGISTER_NUMBERS,
2448 FPU_CONDITION_CODE_NAMES,
2449 COPROC_CONDITION_CODE_NAMES,
2451 /* The $txx registers depends on the abi,
2452 these will be added later into the symbol table from
2453 one of the tables below once mips_abi is set after
2454 parsing of arguments from the command line. */
2455 SYMBOLIC_REGISTER_NAMES,
2457 MIPS16_SPECIAL_REGISTER_NAMES,
2458 MDMX_VECTOR_REGISTER_NAMES,
2459 MIPS_DSP_ACCUMULATOR_NAMES,
2463 static const struct regname reg_names_o32[] = {
2464 O32_SYMBOLIC_REGISTER_NAMES,
2468 static const struct regname reg_names_n32n64[] = {
2469 N32N64_SYMBOLIC_REGISTER_NAMES,
2473 /* Check if S points at a valid register specifier according to TYPES.
2474 If so, then return 1, advance S to consume the specifier and store
2475 the register's number in REGNOP, otherwise return 0. */
2478 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2485 /* Find end of name. */
2487 if (is_name_beginner (*e))
2489 while (is_part_of_name (*e))
2492 /* Terminate name. */
2496 /* Look for a register symbol. */
2497 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2499 int r = S_GET_VALUE (symbolP);
2501 reg = r & RNUM_MASK;
2502 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2503 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2504 reg = (r & RNUM_MASK) - 2;
2506 /* Else see if this is a register defined in an itbl entry. */
2507 else if ((types & RTYPE_GP) && itbl_have_entries)
2514 if (itbl_get_reg_val (n, &r))
2515 reg = r & RNUM_MASK;
2518 /* Advance to next token if a register was recognised. */
2521 else if (types & RWARN)
2522 as_warn (_("Unrecognized register name `%s'"), *s);
2530 /* Check if S points at a valid register list according to TYPES.
2531 If so, then return 1, advance S to consume the list and store
2532 the registers present on the list as a bitmask of ones in REGLISTP,
2533 otherwise return 0. A valid list comprises a comma-separated
2534 enumeration of valid single registers and/or dash-separated
2535 contiguous register ranges as determined by their numbers.
2537 As a special exception if one of s0-s7 registers is specified as
2538 the range's lower delimiter and s8 (fp) is its upper one, then no
2539 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2540 are selected; they have to be listed separately if needed. */
2543 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2545 unsigned int reglist = 0;
2546 unsigned int lastregno;
2547 bfd_boolean ok = TRUE;
2548 unsigned int regmask;
2549 char *s_endlist = *s;
2553 while (reg_lookup (s, types, ®no))
2559 ok = reg_lookup (s, types, &lastregno);
2560 if (ok && lastregno < regno)
2566 if (lastregno == FP && regno >= S0 && regno <= S7)
2571 regmask = 1 << lastregno;
2572 regmask = (regmask << 1) - 1;
2573 regmask ^= (1 << regno) - 1;
2587 *reglistp = reglist;
2588 return ok && reglist != 0;
2592 mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
2593 const unsigned int *map1, const unsigned int *map2,
2598 for (i = 0; i < count; i++)
2599 if (map1[i] == regno1 && map2[i] == regno2)
2604 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2605 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2608 is_opcode_valid (const struct mips_opcode *mo)
2610 int isa = mips_opts.isa;
2611 int ase = mips_opts.ase;
2615 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2616 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2617 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2618 ase |= mips_ases[i].flags64;
2620 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2623 /* Check whether the instruction or macro requires single-precision or
2624 double-precision floating-point support. Note that this information is
2625 stored differently in the opcode table for insns and macros. */
2626 if (mo->pinfo == INSN_MACRO)
2628 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2629 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2633 fp_s = mo->pinfo & FP_S;
2634 fp_d = mo->pinfo & FP_D;
2637 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2640 if (fp_s && mips_opts.soft_float)
2646 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2647 selected ISA and architecture. */
2650 is_opcode_valid_16 (const struct mips_opcode *mo)
2652 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2655 /* Return TRUE if the size of the microMIPS opcode MO matches one
2656 explicitly requested. Always TRUE in the standard MIPS mode. */
2659 is_size_valid (const struct mips_opcode *mo)
2661 if (!mips_opts.micromips)
2664 if (mips_opts.insn32)
2666 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
2668 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
2671 if (!forced_insn_length)
2673 if (mo->pinfo == INSN_MACRO)
2675 return forced_insn_length == micromips_insn_length (mo);
2678 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2679 of the preceding instruction. Always TRUE in the standard MIPS mode.
2681 We don't accept macros in 16-bit delay slots to avoid a case where
2682 a macro expansion fails because it relies on a preceding 32-bit real
2683 instruction to have matched and does not handle the operands correctly.
2684 The only macros that may expand to 16-bit instructions are JAL that
2685 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2686 and BGT (that likewise cannot be placed in a delay slot) that decay to
2687 a NOP. In all these cases the macros precede any corresponding real
2688 instruction definitions in the opcode table, so they will match in the
2689 second pass where the size of the delay slot is ignored and therefore
2690 produce correct code. */
2693 is_delay_slot_valid (const struct mips_opcode *mo)
2695 if (!mips_opts.micromips)
2698 if (mo->pinfo == INSN_MACRO)
2699 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2700 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2701 && micromips_insn_length (mo) != 4)
2703 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2704 && micromips_insn_length (mo) != 2)
2710 /* This function is called once, at assembler startup time. It should set up
2711 all the tables, etc. that the MD part of the assembler will need. */
2716 const char *retval = NULL;
2720 if (mips_pic != NO_PIC)
2722 if (g_switch_seen && g_switch_value != 0)
2723 as_bad (_("-G may not be used in position-independent code"));
2727 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2728 as_warn (_("Could not set architecture and machine"));
2730 op_hash = hash_new ();
2732 for (i = 0; i < NUMOPCODES;)
2734 const char *name = mips_opcodes[i].name;
2736 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2739 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2740 mips_opcodes[i].name, retval);
2741 /* Probably a memory allocation problem? Give up now. */
2742 as_fatal (_("Broken assembler. No assembly attempted."));
2746 if (mips_opcodes[i].pinfo != INSN_MACRO)
2748 if (!validate_mips_insn (&mips_opcodes[i]))
2750 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2752 create_insn (&nop_insn, mips_opcodes + i);
2753 if (mips_fix_loongson2f_nop)
2754 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2755 nop_insn.fixed_p = 1;
2760 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2763 mips16_op_hash = hash_new ();
2766 while (i < bfd_mips16_num_opcodes)
2768 const char *name = mips16_opcodes[i].name;
2770 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2772 as_fatal (_("internal: can't hash `%s': %s"),
2773 mips16_opcodes[i].name, retval);
2776 if (mips16_opcodes[i].pinfo != INSN_MACRO
2777 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2778 != mips16_opcodes[i].match))
2780 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2781 mips16_opcodes[i].name, mips16_opcodes[i].args);
2784 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2786 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2787 mips16_nop_insn.fixed_p = 1;
2791 while (i < bfd_mips16_num_opcodes
2792 && strcmp (mips16_opcodes[i].name, name) == 0);
2795 micromips_op_hash = hash_new ();
2798 while (i < bfd_micromips_num_opcodes)
2800 const char *name = micromips_opcodes[i].name;
2802 retval = hash_insert (micromips_op_hash, name,
2803 (void *) µmips_opcodes[i]);
2805 as_fatal (_("internal: can't hash `%s': %s"),
2806 micromips_opcodes[i].name, retval);
2808 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2810 struct mips_cl_insn *micromips_nop_insn;
2812 if (!validate_micromips_insn (µmips_opcodes[i]))
2815 if (micromips_insn_length (micromips_opcodes + i) == 2)
2816 micromips_nop_insn = µmips_nop16_insn;
2817 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2818 micromips_nop_insn = µmips_nop32_insn;
2822 if (micromips_nop_insn->insn_mo == NULL
2823 && strcmp (name, "nop") == 0)
2825 create_insn (micromips_nop_insn, micromips_opcodes + i);
2826 micromips_nop_insn->fixed_p = 1;
2829 while (++i < bfd_micromips_num_opcodes
2830 && strcmp (micromips_opcodes[i].name, name) == 0);
2834 as_fatal (_("Broken assembler. No assembly attempted."));
2836 /* We add all the general register names to the symbol table. This
2837 helps us detect invalid uses of them. */
2838 for (i = 0; reg_names[i].name; i++)
2839 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2840 reg_names[i].num, /* & RNUM_MASK, */
2841 &zero_address_frag));
2843 for (i = 0; reg_names_n32n64[i].name; i++)
2844 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2845 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2846 &zero_address_frag));
2848 for (i = 0; reg_names_o32[i].name; i++)
2849 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2850 reg_names_o32[i].num, /* & RNUM_MASK, */
2851 &zero_address_frag));
2853 mips_no_prev_insn ();
2856 mips_cprmask[0] = 0;
2857 mips_cprmask[1] = 0;
2858 mips_cprmask[2] = 0;
2859 mips_cprmask[3] = 0;
2861 /* set the default alignment for the text section (2**2) */
2862 record_alignment (text_section, 2);
2864 bfd_set_gp_size (stdoutput, g_switch_value);
2866 /* On a native system other than VxWorks, sections must be aligned
2867 to 16 byte boundaries. When configured for an embedded ELF
2868 target, we don't bother. */
2869 if (strncmp (TARGET_OS, "elf", 3) != 0
2870 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2872 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2873 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2874 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2877 /* Create a .reginfo section for register masks and a .mdebug
2878 section for debugging information. */
2886 subseg = now_subseg;
2888 /* The ABI says this section should be loaded so that the
2889 running program can access it. However, we don't load it
2890 if we are configured for an embedded target */
2891 flags = SEC_READONLY | SEC_DATA;
2892 if (strncmp (TARGET_OS, "elf", 3) != 0)
2893 flags |= SEC_ALLOC | SEC_LOAD;
2895 if (mips_abi != N64_ABI)
2897 sec = subseg_new (".reginfo", (subsegT) 0);
2899 bfd_set_section_flags (stdoutput, sec, flags);
2900 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2902 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2906 /* The 64-bit ABI uses a .MIPS.options section rather than
2907 .reginfo section. */
2908 sec = subseg_new (".MIPS.options", (subsegT) 0);
2909 bfd_set_section_flags (stdoutput, sec, flags);
2910 bfd_set_section_alignment (stdoutput, sec, 3);
2912 /* Set up the option header. */
2914 Elf_Internal_Options opthdr;
2917 opthdr.kind = ODK_REGINFO;
2918 opthdr.size = (sizeof (Elf_External_Options)
2919 + sizeof (Elf64_External_RegInfo));
2922 f = frag_more (sizeof (Elf_External_Options));
2923 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2924 (Elf_External_Options *) f);
2926 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2930 if (ECOFF_DEBUGGING)
2932 sec = subseg_new (".mdebug", (subsegT) 0);
2933 (void) bfd_set_section_flags (stdoutput, sec,
2934 SEC_HAS_CONTENTS | SEC_READONLY);
2935 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2937 else if (mips_flag_pdr)
2939 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2940 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2941 SEC_READONLY | SEC_RELOC
2943 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2946 subseg_set (seg, subseg);
2949 if (! ECOFF_DEBUGGING)
2952 if (mips_fix_vr4120)
2953 init_vr4120_conflicts ();
2959 mips_emit_delays ();
2960 if (! ECOFF_DEBUGGING)
2965 md_assemble (char *str)
2967 struct mips_cl_insn insn;
2968 bfd_reloc_code_real_type unused_reloc[3]
2969 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2971 imm_expr.X_op = O_absent;
2972 imm2_expr.X_op = O_absent;
2973 offset_expr.X_op = O_absent;
2974 offset_reloc[0] = BFD_RELOC_UNUSED;
2975 offset_reloc[1] = BFD_RELOC_UNUSED;
2976 offset_reloc[2] = BFD_RELOC_UNUSED;
2978 mips_mark_labels ();
2979 mips_assembling_insn = TRUE;
2981 if (mips_opts.mips16)
2982 mips16_ip (str, &insn);
2985 mips_ip (str, &insn);
2986 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2987 str, insn.insn_opcode));
2991 as_bad ("%s `%s'", insn_error, str);
2992 else if (insn.insn_mo->pinfo == INSN_MACRO)
2995 if (mips_opts.mips16)
2996 mips16_macro (&insn);
3003 if (offset_expr.X_op != O_absent)
3004 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
3006 append_insn (&insn, NULL, unused_reloc, FALSE);
3009 mips_assembling_insn = FALSE;
3012 /* Convenience functions for abstracting away the differences between
3013 MIPS16 and non-MIPS16 relocations. */
3015 static inline bfd_boolean
3016 mips16_reloc_p (bfd_reloc_code_real_type reloc)
3020 case BFD_RELOC_MIPS16_JMP:
3021 case BFD_RELOC_MIPS16_GPREL:
3022 case BFD_RELOC_MIPS16_GOT16:
3023 case BFD_RELOC_MIPS16_CALL16:
3024 case BFD_RELOC_MIPS16_HI16_S:
3025 case BFD_RELOC_MIPS16_HI16:
3026 case BFD_RELOC_MIPS16_LO16:
3034 static inline bfd_boolean
3035 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3039 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3040 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3041 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3042 case BFD_RELOC_MICROMIPS_GPREL16:
3043 case BFD_RELOC_MICROMIPS_JMP:
3044 case BFD_RELOC_MICROMIPS_HI16:
3045 case BFD_RELOC_MICROMIPS_HI16_S:
3046 case BFD_RELOC_MICROMIPS_LO16:
3047 case BFD_RELOC_MICROMIPS_LITERAL:
3048 case BFD_RELOC_MICROMIPS_GOT16:
3049 case BFD_RELOC_MICROMIPS_CALL16:
3050 case BFD_RELOC_MICROMIPS_GOT_HI16:
3051 case BFD_RELOC_MICROMIPS_GOT_LO16:
3052 case BFD_RELOC_MICROMIPS_CALL_HI16:
3053 case BFD_RELOC_MICROMIPS_CALL_LO16:
3054 case BFD_RELOC_MICROMIPS_SUB:
3055 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3056 case BFD_RELOC_MICROMIPS_GOT_OFST:
3057 case BFD_RELOC_MICROMIPS_GOT_DISP:
3058 case BFD_RELOC_MICROMIPS_HIGHEST:
3059 case BFD_RELOC_MICROMIPS_HIGHER:
3060 case BFD_RELOC_MICROMIPS_SCN_DISP:
3061 case BFD_RELOC_MICROMIPS_JALR:
3069 static inline bfd_boolean
3070 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3072 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3075 static inline bfd_boolean
3076 got16_reloc_p (bfd_reloc_code_real_type reloc)
3078 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3079 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3082 static inline bfd_boolean
3083 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3085 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3086 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3089 static inline bfd_boolean
3090 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3092 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3093 || reloc == BFD_RELOC_MICROMIPS_LO16);
3096 static inline bfd_boolean
3097 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3099 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3102 static inline bfd_boolean
3103 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
3105 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
3106 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
3109 /* Return true if RELOC is a PC-relative relocation that does not have
3110 full address range. */
3112 static inline bfd_boolean
3113 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3117 case BFD_RELOC_16_PCREL_S2:
3118 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3119 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3120 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3123 case BFD_RELOC_32_PCREL:
3124 return HAVE_64BIT_ADDRESSES;
3131 /* Return true if the given relocation might need a matching %lo().
3132 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3133 need a matching %lo() when applied to local symbols. */
3135 static inline bfd_boolean
3136 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3138 return (HAVE_IN_PLACE_ADDENDS
3139 && (hi16_reloc_p (reloc)
3140 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3141 all GOT16 relocations evaluate to "G". */
3142 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3145 /* Return the type of %lo() reloc needed by RELOC, given that
3146 reloc_needs_lo_p. */
3148 static inline bfd_reloc_code_real_type
3149 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3151 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3152 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3156 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3159 static inline bfd_boolean
3160 fixup_has_matching_lo_p (fixS *fixp)
3162 return (fixp->fx_next != NULL
3163 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3164 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3165 && fixp->fx_offset == fixp->fx_next->fx_offset);
3168 /* This function returns true if modifying a register requires a
3172 reg_needs_delay (unsigned int reg)
3174 unsigned long prev_pinfo;
3176 prev_pinfo = history[0].insn_mo->pinfo;
3177 if (! mips_opts.noreorder
3178 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3179 && ! gpr_interlocks)
3180 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3181 && ! cop_interlocks)))
3183 /* A load from a coprocessor or from memory. All load delays
3184 delay the use of general register rt for one instruction. */
3185 /* Itbl support may require additional care here. */
3186 know (prev_pinfo & INSN_WRITE_GPR_T);
3187 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3194 /* Move all labels in LABELS to the current insertion point. TEXT_P
3195 says whether the labels refer to text or data. */
3198 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3200 struct insn_label_list *l;
3203 for (l = labels; l != NULL; l = l->next)
3205 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3206 symbol_set_frag (l->label, frag_now);
3207 val = (valueT) frag_now_fix ();
3208 /* MIPS16/microMIPS text labels are stored as odd. */
3209 if (text_p && HAVE_CODE_COMPRESSION)
3211 S_SET_VALUE (l->label, val);
3215 /* Move all labels in insn_labels to the current insertion point
3216 and treat them as text labels. */
3219 mips_move_text_labels (void)
3221 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3225 s_is_linkonce (symbolS *sym, segT from_seg)
3227 bfd_boolean linkonce = FALSE;
3228 segT symseg = S_GET_SEGMENT (sym);
3230 if (symseg != from_seg && !S_IS_LOCAL (sym))
3232 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3234 /* The GNU toolchain uses an extension for ELF: a section
3235 beginning with the magic string .gnu.linkonce is a
3236 linkonce section. */
3237 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3238 sizeof ".gnu.linkonce" - 1) == 0)
3244 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3245 linker to handle them specially, such as generating jalx instructions
3246 when needed. We also make them odd for the duration of the assembly,
3247 in order to generate the right sort of code. We will make them even
3248 in the adjust_symtab routine, while leaving them marked. This is
3249 convenient for the debugger and the disassembler. The linker knows
3250 to make them odd again. */
3253 mips_compressed_mark_label (symbolS *label)
3255 gas_assert (HAVE_CODE_COMPRESSION);
3257 if (mips_opts.mips16)
3258 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3260 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3261 if ((S_GET_VALUE (label) & 1) == 0
3262 /* Don't adjust the address if the label is global or weak, or
3263 in a link-once section, since we'll be emitting symbol reloc
3264 references to it which will be patched up by the linker, and
3265 the final value of the symbol may or may not be MIPS16/microMIPS. */
3266 && !S_IS_WEAK (label)
3267 && !S_IS_EXTERNAL (label)
3268 && !s_is_linkonce (label, now_seg))
3269 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3272 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3275 mips_compressed_mark_labels (void)
3277 struct insn_label_list *l;
3279 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3280 mips_compressed_mark_label (l->label);
3283 /* End the current frag. Make it a variant frag and record the
3287 relax_close_frag (void)
3289 mips_macro_warning.first_frag = frag_now;
3290 frag_var (rs_machine_dependent, 0, 0,
3291 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3292 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3294 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3295 mips_relax.first_fixup = 0;
3298 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3299 See the comment above RELAX_ENCODE for more details. */
3302 relax_start (symbolS *symbol)
3304 gas_assert (mips_relax.sequence == 0);
3305 mips_relax.sequence = 1;
3306 mips_relax.symbol = symbol;
3309 /* Start generating the second version of a relaxable sequence.
3310 See the comment above RELAX_ENCODE for more details. */
3315 gas_assert (mips_relax.sequence == 1);
3316 mips_relax.sequence = 2;
3319 /* End the current relaxable sequence. */
3324 gas_assert (mips_relax.sequence == 2);
3325 relax_close_frag ();
3326 mips_relax.sequence = 0;
3329 /* Return true if IP is a delayed branch or jump. */
3331 static inline bfd_boolean
3332 delayed_branch_p (const struct mips_cl_insn *ip)
3334 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3335 | INSN_COND_BRANCH_DELAY
3336 | INSN_COND_BRANCH_LIKELY)) != 0;
3339 /* Return true if IP is a compact branch or jump. */
3341 static inline bfd_boolean
3342 compact_branch_p (const struct mips_cl_insn *ip)
3344 if (mips_opts.mips16)
3345 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3346 | MIPS16_INSN_COND_BRANCH)) != 0;
3348 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3349 | INSN2_COND_BRANCH)) != 0;
3352 /* Return true if IP is an unconditional branch or jump. */
3354 static inline bfd_boolean
3355 uncond_branch_p (const struct mips_cl_insn *ip)
3357 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3358 || (mips_opts.mips16
3359 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3360 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3363 /* Return true if IP is a branch-likely instruction. */
3365 static inline bfd_boolean
3366 branch_likely_p (const struct mips_cl_insn *ip)
3368 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3371 /* Return the type of nop that should be used to fill the delay slot
3372 of delayed branch IP. */
3374 static struct mips_cl_insn *
3375 get_delay_slot_nop (const struct mips_cl_insn *ip)
3377 if (mips_opts.micromips
3378 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3379 return µmips_nop32_insn;
3383 /* Return the mask of core registers that IP reads or writes. */
3386 gpr_mod_mask (const struct mips_cl_insn *ip)
3388 unsigned long pinfo2;
3392 pinfo2 = ip->insn_mo->pinfo2;
3393 if (mips_opts.micromips)
3395 if (pinfo2 & INSN2_MOD_GPR_MD)
3396 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3397 if (pinfo2 & INSN2_MOD_GPR_MF)
3398 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3399 if (pinfo2 & INSN2_MOD_SP)
3405 /* Return the mask of core registers that IP reads. */
3408 gpr_read_mask (const struct mips_cl_insn *ip)
3410 unsigned long pinfo, pinfo2;
3413 mask = gpr_mod_mask (ip);
3414 pinfo = ip->insn_mo->pinfo;
3415 pinfo2 = ip->insn_mo->pinfo2;
3416 if (mips_opts.mips16)
3418 if (pinfo & MIPS16_INSN_READ_X)
3419 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3420 if (pinfo & MIPS16_INSN_READ_Y)
3421 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3422 if (pinfo & MIPS16_INSN_READ_T)
3424 if (pinfo & MIPS16_INSN_READ_SP)
3426 if (pinfo & MIPS16_INSN_READ_31)
3428 if (pinfo & MIPS16_INSN_READ_Z)
3429 mask |= 1 << (mips16_to_32_reg_map
3430 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3431 if (pinfo & MIPS16_INSN_READ_GPR_X)
3432 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3436 if (pinfo2 & INSN2_READ_GPR_D)
3437 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3438 if (pinfo & INSN_READ_GPR_T)
3439 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3440 if (pinfo & INSN_READ_GPR_S)
3441 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3442 if (pinfo2 & INSN2_READ_GP)
3444 if (pinfo2 & INSN2_READ_GPR_31)
3446 if (pinfo2 & INSN2_READ_GPR_Z)
3447 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3449 if (mips_opts.micromips)
3451 if (pinfo2 & INSN2_READ_GPR_MC)
3452 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3453 if (pinfo2 & INSN2_READ_GPR_ME)
3454 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3455 if (pinfo2 & INSN2_READ_GPR_MG)
3456 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3457 if (pinfo2 & INSN2_READ_GPR_MJ)
3458 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3459 if (pinfo2 & INSN2_READ_GPR_MMN)
3461 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3462 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3464 if (pinfo2 & INSN2_READ_GPR_MP)
3465 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3466 if (pinfo2 & INSN2_READ_GPR_MQ)
3467 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3469 /* Don't include register 0. */
3473 /* Return the mask of core registers that IP writes. */
3476 gpr_write_mask (const struct mips_cl_insn *ip)
3478 unsigned long pinfo, pinfo2;
3481 mask = gpr_mod_mask (ip);
3482 pinfo = ip->insn_mo->pinfo;
3483 pinfo2 = ip->insn_mo->pinfo2;
3484 if (mips_opts.mips16)
3486 if (pinfo & MIPS16_INSN_WRITE_X)
3487 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3488 if (pinfo & MIPS16_INSN_WRITE_Y)
3489 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3490 if (pinfo & MIPS16_INSN_WRITE_Z)
3491 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3492 if (pinfo & MIPS16_INSN_WRITE_T)
3494 if (pinfo & MIPS16_INSN_WRITE_SP)
3496 if (pinfo & MIPS16_INSN_WRITE_31)
3498 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3499 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3503 if (pinfo & INSN_WRITE_GPR_D)
3504 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3505 if (pinfo & INSN_WRITE_GPR_T)
3506 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3507 if (pinfo & INSN_WRITE_GPR_S)
3508 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3509 if (pinfo & INSN_WRITE_GPR_31)
3511 if (pinfo2 & INSN2_WRITE_GPR_Z)
3512 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3514 if (mips_opts.micromips)
3516 if (pinfo2 & INSN2_WRITE_GPR_MB)
3517 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3518 if (pinfo2 & INSN2_WRITE_GPR_MH)
3520 mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
3521 mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
3523 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3524 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3525 if (pinfo2 & INSN2_WRITE_GPR_MP)
3526 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3528 /* Don't include register 0. */
3532 /* Return the mask of floating-point registers that IP reads. */
3535 fpr_read_mask (const struct mips_cl_insn *ip)
3537 unsigned long pinfo, pinfo2;
3541 pinfo = ip->insn_mo->pinfo;
3542 pinfo2 = ip->insn_mo->pinfo2;
3543 if (!mips_opts.mips16)
3545 if (pinfo2 & INSN2_READ_FPR_D)
3546 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3547 if (pinfo & INSN_READ_FPR_S)
3548 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3549 if (pinfo & INSN_READ_FPR_T)
3550 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3551 if (pinfo & INSN_READ_FPR_R)
3552 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3553 if (pinfo2 & INSN2_READ_FPR_Z)
3554 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3556 /* Conservatively treat all operands to an FP_D instruction are doubles.
3557 (This is overly pessimistic for things like cvt.d.s.) */
3558 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3563 /* Return the mask of floating-point registers that IP writes. */
3566 fpr_write_mask (const struct mips_cl_insn *ip)
3568 unsigned long pinfo, pinfo2;
3572 pinfo = ip->insn_mo->pinfo;
3573 pinfo2 = ip->insn_mo->pinfo2;
3574 if (!mips_opts.mips16)
3576 if (pinfo & INSN_WRITE_FPR_D)
3577 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3578 if (pinfo & INSN_WRITE_FPR_S)
3579 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3580 if (pinfo & INSN_WRITE_FPR_T)
3581 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3582 if (pinfo2 & INSN2_WRITE_FPR_Z)
3583 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3585 /* Conservatively treat all operands to an FP_D instruction are doubles.
3586 (This is overly pessimistic for things like cvt.s.d.) */
3587 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3592 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3593 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3594 by VR4120 errata. */
3597 classify_vr4120_insn (const char *name)
3599 if (strncmp (name, "macc", 4) == 0)
3600 return FIX_VR4120_MACC;
3601 if (strncmp (name, "dmacc", 5) == 0)
3602 return FIX_VR4120_DMACC;
3603 if (strncmp (name, "mult", 4) == 0)
3604 return FIX_VR4120_MULT;
3605 if (strncmp (name, "dmult", 5) == 0)
3606 return FIX_VR4120_DMULT;
3607 if (strstr (name, "div"))
3608 return FIX_VR4120_DIV;
3609 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3610 return FIX_VR4120_MTHILO;
3611 return NUM_FIX_VR4120_CLASSES;
3614 #define INSN_ERET 0x42000018
3615 #define INSN_DERET 0x4200001f
3617 /* Return the number of instructions that must separate INSN1 and INSN2,
3618 where INSN1 is the earlier instruction. Return the worst-case value
3619 for any INSN2 if INSN2 is null. */
3622 insns_between (const struct mips_cl_insn *insn1,
3623 const struct mips_cl_insn *insn2)
3625 unsigned long pinfo1, pinfo2;
3628 /* This function needs to know which pinfo flags are set for INSN2
3629 and which registers INSN2 uses. The former is stored in PINFO2 and
3630 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3631 will have every flag set and INSN2_USES_GPR will always return true. */
3632 pinfo1 = insn1->insn_mo->pinfo;
3633 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3635 #define INSN2_USES_GPR(REG) \
3636 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3638 /* For most targets, write-after-read dependencies on the HI and LO
3639 registers must be separated by at least two instructions. */
3640 if (!hilo_interlocks)
3642 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3644 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3648 /* If we're working around r7000 errata, there must be two instructions
3649 between an mfhi or mflo and any instruction that uses the result. */
3650 if (mips_7000_hilo_fix
3651 && !mips_opts.micromips
3652 && MF_HILO_INSN (pinfo1)
3653 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3656 /* If we're working around 24K errata, one instruction is required
3657 if an ERET or DERET is followed by a branch instruction. */
3658 if (mips_fix_24k && !mips_opts.micromips)
3660 if (insn1->insn_opcode == INSN_ERET
3661 || insn1->insn_opcode == INSN_DERET)
3664 || insn2->insn_opcode == INSN_ERET
3665 || insn2->insn_opcode == INSN_DERET
3666 || delayed_branch_p (insn2))
3671 /* If working around VR4120 errata, check for combinations that need
3672 a single intervening instruction. */
3673 if (mips_fix_vr4120 && !mips_opts.micromips)
3675 unsigned int class1, class2;
3677 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3678 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3682 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3683 if (vr4120_conflicts[class1] & (1 << class2))
3688 if (!HAVE_CODE_COMPRESSION)
3690 /* Check for GPR or coprocessor load delays. All such delays
3691 are on the RT register. */
3692 /* Itbl support may require additional care here. */
3693 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3694 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3696 know (pinfo1 & INSN_WRITE_GPR_T);
3697 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3701 /* Check for generic coprocessor hazards.
3703 This case is not handled very well. There is no special
3704 knowledge of CP0 handling, and the coprocessors other than
3705 the floating point unit are not distinguished at all. */
3706 /* Itbl support may require additional care here. FIXME!
3707 Need to modify this to include knowledge about
3708 user specified delays! */
3709 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3710 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3712 /* Handle cases where INSN1 writes to a known general coprocessor
3713 register. There must be a one instruction delay before INSN2
3714 if INSN2 reads that register, otherwise no delay is needed. */
3715 mask = fpr_write_mask (insn1);
3718 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3723 /* Read-after-write dependencies on the control registers
3724 require a two-instruction gap. */
3725 if ((pinfo1 & INSN_WRITE_COND_CODE)
3726 && (pinfo2 & INSN_READ_COND_CODE))
3729 /* We don't know exactly what INSN1 does. If INSN2 is
3730 also a coprocessor instruction, assume there must be
3731 a one instruction gap. */
3732 if (pinfo2 & INSN_COP)
3737 /* Check for read-after-write dependencies on the coprocessor
3738 control registers in cases where INSN1 does not need a general
3739 coprocessor delay. This means that INSN1 is a floating point
3740 comparison instruction. */
3741 /* Itbl support may require additional care here. */
3742 else if (!cop_interlocks
3743 && (pinfo1 & INSN_WRITE_COND_CODE)
3744 && (pinfo2 & INSN_READ_COND_CODE))
3748 #undef INSN2_USES_GPR
3753 /* Return the number of nops that would be needed to work around the
3754 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3755 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3756 that are contained within the first IGNORE instructions of HIST. */
3759 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3760 const struct mips_cl_insn *insn)
3765 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3766 are not affected by the errata. */
3768 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3769 || strcmp (insn->insn_mo->name, "mtlo") == 0
3770 || strcmp (insn->insn_mo->name, "mthi") == 0))
3773 /* Search for the first MFLO or MFHI. */
3774 for (i = 0; i < MAX_VR4130_NOPS; i++)
3775 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3777 /* Extract the destination register. */
3778 mask = gpr_write_mask (&hist[i]);
3780 /* No nops are needed if INSN reads that register. */
3781 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3784 /* ...or if any of the intervening instructions do. */
3785 for (j = 0; j < i; j++)
3786 if (gpr_read_mask (&hist[j]) & mask)
3790 return MAX_VR4130_NOPS - i;
3795 #define BASE_REG_EQ(INSN1, INSN2) \
3796 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3797 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3799 /* Return the minimum alignment for this store instruction. */
3802 fix_24k_align_to (const struct mips_opcode *mo)
3804 if (strcmp (mo->name, "sh") == 0)
3807 if (strcmp (mo->name, "swc1") == 0
3808 || strcmp (mo->name, "swc2") == 0
3809 || strcmp (mo->name, "sw") == 0
3810 || strcmp (mo->name, "sc") == 0
3811 || strcmp (mo->name, "s.s") == 0)
3814 if (strcmp (mo->name, "sdc1") == 0
3815 || strcmp (mo->name, "sdc2") == 0
3816 || strcmp (mo->name, "s.d") == 0)
3823 struct fix_24k_store_info
3825 /* Immediate offset, if any, for this store instruction. */
3827 /* Alignment required by this store instruction. */
3829 /* True for register offsets. */
3830 int register_offset;
3833 /* Comparison function used by qsort. */
3836 fix_24k_sort (const void *a, const void *b)
3838 const struct fix_24k_store_info *pos1 = a;
3839 const struct fix_24k_store_info *pos2 = b;
3841 return (pos1->off - pos2->off);
3844 /* INSN is a store instruction. Try to record the store information
3845 in STINFO. Return false if the information isn't known. */
3848 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3849 const struct mips_cl_insn *insn)
3851 /* The instruction must have a known offset. */
3852 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3855 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3856 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3860 /* Return the number of nops that would be needed to work around the 24k
3861 "lost data on stores during refill" errata if instruction INSN
3862 immediately followed the 2 instructions described by HIST.
3863 Ignore hazards that are contained within the first IGNORE
3864 instructions of HIST.
3866 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3867 for the data cache refills and store data. The following describes
3868 the scenario where the store data could be lost.
3870 * A data cache miss, due to either a load or a store, causing fill
3871 data to be supplied by the memory subsystem
3872 * The first three doublewords of fill data are returned and written
3874 * A sequence of four stores occurs in consecutive cycles around the
3875 final doubleword of the fill:
3879 * Zero, One or more instructions
3882 The four stores A-D must be to different doublewords of the line that
3883 is being filled. The fourth instruction in the sequence above permits
3884 the fill of the final doubleword to be transferred from the FSB into
3885 the cache. In the sequence above, the stores may be either integer
3886 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3887 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3888 different doublewords on the line. If the floating point unit is
3889 running in 1:2 mode, it is not possible to create the sequence above
3890 using only floating point store instructions.
3892 In this case, the cache line being filled is incorrectly marked
3893 invalid, thereby losing the data from any store to the line that
3894 occurs between the original miss and the completion of the five
3895 cycle sequence shown above.
3897 The workarounds are:
3899 * Run the data cache in write-through mode.
3900 * Insert a non-store instruction between
3901 Store A and Store B or Store B and Store C. */
3904 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3905 const struct mips_cl_insn *insn)
3907 struct fix_24k_store_info pos[3];
3908 int align, i, base_offset;
3913 /* If the previous instruction wasn't a store, there's nothing to
3915 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3918 /* If the instructions after the previous one are unknown, we have
3919 to assume the worst. */
3923 /* Check whether we are dealing with three consecutive stores. */
3924 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3925 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3928 /* If we don't know the relationship between the store addresses,
3929 assume the worst. */
3930 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3931 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3934 if (!fix_24k_record_store_info (&pos[0], insn)
3935 || !fix_24k_record_store_info (&pos[1], &hist[0])
3936 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3939 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3941 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3942 X bytes and such that the base register + X is known to be aligned
3945 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3949 align = pos[0].align_to;
3950 base_offset = pos[0].off;
3951 for (i = 1; i < 3; i++)
3952 if (align < pos[i].align_to)
3954 align = pos[i].align_to;
3955 base_offset = pos[i].off;
3957 for (i = 0; i < 3; i++)
3958 pos[i].off -= base_offset;
3961 pos[0].off &= ~align + 1;
3962 pos[1].off &= ~align + 1;
3963 pos[2].off &= ~align + 1;
3965 /* If any two stores write to the same chunk, they also write to the
3966 same doubleword. The offsets are still sorted at this point. */
3967 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3970 /* A range of at least 9 bytes is needed for the stores to be in
3971 non-overlapping doublewords. */
3972 if (pos[2].off - pos[0].off <= 8)
3975 if (pos[2].off - pos[1].off >= 24
3976 || pos[1].off - pos[0].off >= 24
3977 || pos[2].off - pos[0].off >= 32)
3983 /* Return the number of nops that would be needed if instruction INSN
3984 immediately followed the MAX_NOPS instructions given by HIST,
3985 where HIST[0] is the most recent instruction. Ignore hazards
3986 between INSN and the first IGNORE instructions in HIST.
3988 If INSN is null, return the worse-case number of nops for any
3992 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3993 const struct mips_cl_insn *insn)
3995 int i, nops, tmp_nops;
3998 for (i = ignore; i < MAX_DELAY_NOPS; i++)
4000 tmp_nops = insns_between (hist + i, insn) - i;
4001 if (tmp_nops > nops)
4005 if (mips_fix_vr4130 && !mips_opts.micromips)
4007 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
4008 if (tmp_nops > nops)
4012 if (mips_fix_24k && !mips_opts.micromips)
4014 tmp_nops = nops_for_24k (ignore, hist, insn);
4015 if (tmp_nops > nops)
4022 /* The variable arguments provide NUM_INSNS extra instructions that
4023 might be added to HIST. Return the largest number of nops that
4024 would be needed after the extended sequence, ignoring hazards
4025 in the first IGNORE instructions. */
4028 nops_for_sequence (int num_insns, int ignore,
4029 const struct mips_cl_insn *hist, ...)
4032 struct mips_cl_insn buffer[MAX_NOPS];
4033 struct mips_cl_insn *cursor;
4036 va_start (args, hist);
4037 cursor = buffer + num_insns;
4038 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4039 while (cursor > buffer)
4040 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4042 nops = nops_for_insn (ignore, buffer, NULL);
4047 /* Like nops_for_insn, but if INSN is a branch, take into account the
4048 worst-case delay for the branch target. */
4051 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4052 const struct mips_cl_insn *insn)
4056 nops = nops_for_insn (ignore, hist, insn);
4057 if (delayed_branch_p (insn))
4059 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4060 hist, insn, get_delay_slot_nop (insn));
4061 if (tmp_nops > nops)
4064 else if (compact_branch_p (insn))
4066 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4067 if (tmp_nops > nops)
4073 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4076 fix_loongson2f_nop (struct mips_cl_insn * ip)
4078 gas_assert (!HAVE_CODE_COMPRESSION);
4079 if (strcmp (ip->insn_mo->name, "nop") == 0)
4080 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4083 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4084 jr target pc &= 'hffff_ffff_cfff_ffff. */
4087 fix_loongson2f_jump (struct mips_cl_insn * ip)
4089 gas_assert (!HAVE_CODE_COMPRESSION);
4090 if (strcmp (ip->insn_mo->name, "j") == 0
4091 || strcmp (ip->insn_mo->name, "jr") == 0
4092 || strcmp (ip->insn_mo->name, "jalr") == 0)
4100 sreg = EXTRACT_OPERAND (0, RS, *ip);
4101 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4104 ep.X_op = O_constant;
4105 ep.X_add_number = 0xcfff0000;
4106 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4107 ep.X_add_number = 0xffff;
4108 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4109 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4114 fix_loongson2f (struct mips_cl_insn * ip)
4116 if (mips_fix_loongson2f_nop)
4117 fix_loongson2f_nop (ip);
4119 if (mips_fix_loongson2f_jump)
4120 fix_loongson2f_jump (ip);
4123 /* IP is a branch that has a delay slot, and we need to fill it
4124 automatically. Return true if we can do that by swapping IP
4125 with the previous instruction.
4126 ADDRESS_EXPR is an operand of the instruction to be used with
4130 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4131 bfd_reloc_code_real_type *reloc_type)
4133 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4134 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4136 /* -O2 and above is required for this optimization. */
4137 if (mips_optimize < 2)
4140 /* If we have seen .set volatile or .set nomove, don't optimize. */
4141 if (mips_opts.nomove)
4144 /* We can't swap if the previous instruction's position is fixed. */
4145 if (history[0].fixed_p)
4148 /* If the previous previous insn was in a .set noreorder, we can't
4149 swap. Actually, the MIPS assembler will swap in this situation.
4150 However, gcc configured -with-gnu-as will generate code like
4158 in which we can not swap the bne and INSN. If gcc is not configured
4159 -with-gnu-as, it does not output the .set pseudo-ops. */
4160 if (history[1].noreorder_p)
4163 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4164 This means that the previous instruction was a 4-byte one anyhow. */
4165 if (mips_opts.mips16 && history[0].fixp[0])
4168 /* If the branch is itself the target of a branch, we can not swap.
4169 We cheat on this; all we check for is whether there is a label on
4170 this instruction. If there are any branches to anything other than
4171 a label, users must use .set noreorder. */
4172 if (seg_info (now_seg)->label_list)
4175 /* If the previous instruction is in a variant frag other than this
4176 branch's one, we cannot do the swap. This does not apply to
4177 MIPS16 code, which uses variant frags for different purposes. */
4178 if (!mips_opts.mips16
4180 && history[0].frag->fr_type == rs_machine_dependent)
4183 /* We do not swap with instructions that cannot architecturally
4184 be placed in a branch delay slot, such as SYNC or ERET. We
4185 also refrain from swapping with a trap instruction, since it
4186 complicates trap handlers to have the trap instruction be in
4188 prev_pinfo = history[0].insn_mo->pinfo;
4189 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4192 /* Check for conflicts between the branch and the instructions
4193 before the candidate delay slot. */
4194 if (nops_for_insn (0, history + 1, ip) > 0)
4197 /* Check for conflicts between the swapped sequence and the
4198 target of the branch. */
4199 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4202 /* If the branch reads a register that the previous
4203 instruction sets, we can not swap. */
4204 gpr_read = gpr_read_mask (ip);
4205 prev_gpr_write = gpr_write_mask (&history[0]);
4206 if (gpr_read & prev_gpr_write)
4209 /* If the branch writes a register that the previous
4210 instruction sets, we can not swap. */
4211 gpr_write = gpr_write_mask (ip);
4212 if (gpr_write & prev_gpr_write)
4215 /* If the branch writes a register that the previous
4216 instruction reads, we can not swap. */
4217 prev_gpr_read = gpr_read_mask (&history[0]);
4218 if (gpr_write & prev_gpr_read)
4221 /* If one instruction sets a condition code and the
4222 other one uses a condition code, we can not swap. */
4223 pinfo = ip->insn_mo->pinfo;
4224 if ((pinfo & INSN_READ_COND_CODE)
4225 && (prev_pinfo & INSN_WRITE_COND_CODE))
4227 if ((pinfo & INSN_WRITE_COND_CODE)
4228 && (prev_pinfo & INSN_READ_COND_CODE))
4231 /* If the previous instruction uses the PC, we can not swap. */
4232 prev_pinfo2 = history[0].insn_mo->pinfo2;
4233 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4235 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4238 /* If the previous instruction has an incorrect size for a fixed
4239 branch delay slot in microMIPS mode, we cannot swap. */
4240 pinfo2 = ip->insn_mo->pinfo2;
4241 if (mips_opts.micromips
4242 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4243 && insn_length (history) != 2)
4245 if (mips_opts.micromips
4246 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4247 && insn_length (history) != 4)
4250 /* On R5900 short loops need to be fixed by inserting a nop in
4251 the branch delay slots.
4252 A short loop can be terminated too early. */
4253 if (mips_opts.arch == CPU_R5900
4254 /* Check if instruction has a parameter, ignore "j $31". */
4255 && (address_expr != NULL)
4256 /* Parameter must be 16 bit. */
4257 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4258 /* Branch to same segment. */
4259 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4260 /* Branch to same code fragment. */
4261 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4262 /* Can only calculate branch offset if value is known. */
4263 && symbol_constant_p(address_expr->X_add_symbol)
4264 /* Check if branch is really conditional. */
4265 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4266 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4267 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4270 /* Check if loop is shorter than 6 instructions including
4271 branch and delay slot. */
4272 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4279 /* When the loop includes branches or jumps,
4280 it is not a short loop. */
4281 for (i = 0; i < (distance / 4); i++)
4283 if ((history[i].cleared_p)
4284 || delayed_branch_p(&history[i]))
4292 /* Insert nop after branch to fix short loop. */
4301 /* Decide how we should add IP to the instruction stream.
4302 ADDRESS_EXPR is an operand of the instruction to be used with
4305 static enum append_method
4306 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4307 bfd_reloc_code_real_type *reloc_type)
4309 unsigned long pinfo;
4311 /* The relaxed version of a macro sequence must be inherently
4313 if (mips_relax.sequence == 2)
4316 /* We must not dabble with instructions in a ".set norerorder" block. */
4317 if (mips_opts.noreorder)
4320 /* Otherwise, it's our responsibility to fill branch delay slots. */
4321 if (delayed_branch_p (ip))
4323 if (!branch_likely_p (ip)
4324 && can_swap_branch_p (ip, address_expr, reloc_type))
4327 pinfo = ip->insn_mo->pinfo;
4328 if (mips_opts.mips16
4329 && ISA_SUPPORTS_MIPS16E
4330 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4331 return APPEND_ADD_COMPACT;
4333 return APPEND_ADD_WITH_NOP;
4339 /* IP is a MIPS16 instruction whose opcode we have just changed.
4340 Point IP->insn_mo to the new opcode's definition. */
4343 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4345 const struct mips_opcode *mo, *end;
4347 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4348 for (mo = ip->insn_mo; mo < end; mo++)
4349 if ((ip->insn_opcode & mo->mask) == mo->match)
4357 /* For microMIPS macros, we need to generate a local number label
4358 as the target of branches. */
4359 #define MICROMIPS_LABEL_CHAR '\037'
4360 static unsigned long micromips_target_label;
4361 static char micromips_target_name[32];
4364 micromips_label_name (void)
4366 char *p = micromips_target_name;
4367 char symbol_name_temporary[24];
4375 l = micromips_target_label;
4376 #ifdef LOCAL_LABEL_PREFIX
4377 *p++ = LOCAL_LABEL_PREFIX;
4380 *p++ = MICROMIPS_LABEL_CHAR;
4383 symbol_name_temporary[i++] = l % 10 + '0';
4388 *p++ = symbol_name_temporary[--i];
4391 return micromips_target_name;
4395 micromips_label_expr (expressionS *label_expr)
4397 label_expr->X_op = O_symbol;
4398 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4399 label_expr->X_add_number = 0;
4403 micromips_label_inc (void)
4405 micromips_target_label++;
4406 *micromips_target_name = '\0';
4410 micromips_add_label (void)
4414 s = colon (micromips_label_name ());
4415 micromips_label_inc ();
4416 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4419 /* If assembling microMIPS code, then return the microMIPS reloc
4420 corresponding to the requested one if any. Otherwise return
4421 the reloc unchanged. */
4423 static bfd_reloc_code_real_type
4424 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4426 static const bfd_reloc_code_real_type relocs[][2] =
4428 /* Keep sorted incrementally by the left-hand key. */
4429 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4430 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4431 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4432 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4433 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4434 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4435 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4436 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4437 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4438 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4439 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4440 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4441 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4442 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4443 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4444 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4445 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4446 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4447 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4448 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4449 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4450 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4451 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4452 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4453 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4454 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4455 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4457 bfd_reloc_code_real_type r;
4460 if (!mips_opts.micromips)
4462 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4468 return relocs[i][1];
4473 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4474 Return true on success, storing the resolved value in RESULT. */
4477 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4482 case BFD_RELOC_MIPS_HIGHEST:
4483 case BFD_RELOC_MICROMIPS_HIGHEST:
4484 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4487 case BFD_RELOC_MIPS_HIGHER:
4488 case BFD_RELOC_MICROMIPS_HIGHER:
4489 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4492 case BFD_RELOC_HI16_S:
4493 case BFD_RELOC_MICROMIPS_HI16_S:
4494 case BFD_RELOC_MIPS16_HI16_S:
4495 *result = ((operand + 0x8000) >> 16) & 0xffff;
4498 case BFD_RELOC_HI16:
4499 case BFD_RELOC_MICROMIPS_HI16:
4500 case BFD_RELOC_MIPS16_HI16:
4501 *result = (operand >> 16) & 0xffff;
4504 case BFD_RELOC_LO16:
4505 case BFD_RELOC_MICROMIPS_LO16:
4506 case BFD_RELOC_MIPS16_LO16:
4507 *result = operand & 0xffff;
4510 case BFD_RELOC_UNUSED:
4519 /* Output an instruction. IP is the instruction information.
4520 ADDRESS_EXPR is an operand of the instruction to be used with
4521 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4522 a macro expansion. */
4525 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4526 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4528 unsigned long prev_pinfo2, pinfo;
4529 bfd_boolean relaxed_branch = FALSE;
4530 enum append_method method;
4531 bfd_boolean relax32;
4534 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4535 fix_loongson2f (ip);
4537 file_ase_mips16 |= mips_opts.mips16;
4538 file_ase_micromips |= mips_opts.micromips;
4540 prev_pinfo2 = history[0].insn_mo->pinfo2;
4541 pinfo = ip->insn_mo->pinfo;
4543 if (mips_opts.micromips
4545 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4546 && micromips_insn_length (ip->insn_mo) != 2)
4547 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4548 && micromips_insn_length (ip->insn_mo) != 4)))
4549 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4550 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4552 if (address_expr == NULL)
4554 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4555 && reloc_type[1] == BFD_RELOC_UNUSED
4556 && reloc_type[2] == BFD_RELOC_UNUSED
4557 && address_expr->X_op == O_constant)
4559 switch (*reloc_type)
4561 case BFD_RELOC_MIPS_JMP:
4565 shift = mips_opts.micromips ? 1 : 2;
4566 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4567 as_bad (_("jump to misaligned address (0x%lx)"),
4568 (unsigned long) address_expr->X_add_number);
4569 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4575 case BFD_RELOC_MIPS16_JMP:
4576 if ((address_expr->X_add_number & 3) != 0)
4577 as_bad (_("jump to misaligned address (0x%lx)"),
4578 (unsigned long) address_expr->X_add_number);
4580 (((address_expr->X_add_number & 0x7c0000) << 3)
4581 | ((address_expr->X_add_number & 0xf800000) >> 7)
4582 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4586 case BFD_RELOC_16_PCREL_S2:
4590 shift = mips_opts.micromips ? 1 : 2;
4591 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4592 as_bad (_("branch to misaligned address (0x%lx)"),
4593 (unsigned long) address_expr->X_add_number);
4594 if (!mips_relax_branch)
4596 if ((address_expr->X_add_number + (1 << (shift + 15)))
4597 & ~((1 << (shift + 16)) - 1))
4598 as_bad (_("branch address range overflow (0x%lx)"),
4599 (unsigned long) address_expr->X_add_number);
4600 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4610 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4613 ip->insn_opcode |= value & 0xffff;
4621 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4623 /* There are a lot of optimizations we could do that we don't.
4624 In particular, we do not, in general, reorder instructions.
4625 If you use gcc with optimization, it will reorder
4626 instructions and generally do much more optimization then we
4627 do here; repeating all that work in the assembler would only
4628 benefit hand written assembly code, and does not seem worth
4630 int nops = (mips_optimize == 0
4631 ? nops_for_insn (0, history, NULL)
4632 : nops_for_insn_or_target (0, history, ip));
4636 unsigned long old_frag_offset;
4639 old_frag = frag_now;
4640 old_frag_offset = frag_now_fix ();
4642 for (i = 0; i < nops; i++)
4643 add_fixed_insn (NOP_INSN);
4644 insert_into_history (0, nops, NOP_INSN);
4648 listing_prev_line ();
4649 /* We may be at the start of a variant frag. In case we
4650 are, make sure there is enough space for the frag
4651 after the frags created by listing_prev_line. The
4652 argument to frag_grow here must be at least as large
4653 as the argument to all other calls to frag_grow in
4654 this file. We don't have to worry about being in the
4655 middle of a variant frag, because the variants insert
4656 all needed nop instructions themselves. */
4660 mips_move_text_labels ();
4662 #ifndef NO_ECOFF_DEBUGGING
4663 if (ECOFF_DEBUGGING)
4664 ecoff_fix_loc (old_frag, old_frag_offset);
4668 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4672 /* Work out how many nops in prev_nop_frag are needed by IP,
4673 ignoring hazards generated by the first prev_nop_frag_since
4675 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4676 gas_assert (nops <= prev_nop_frag_holds);
4678 /* Enforce NOPS as a minimum. */
4679 if (nops > prev_nop_frag_required)
4680 prev_nop_frag_required = nops;
4682 if (prev_nop_frag_holds == prev_nop_frag_required)
4684 /* Settle for the current number of nops. Update the history
4685 accordingly (for the benefit of any future .set reorder code). */
4686 prev_nop_frag = NULL;
4687 insert_into_history (prev_nop_frag_since,
4688 prev_nop_frag_holds, NOP_INSN);
4692 /* Allow this instruction to replace one of the nops that was
4693 tentatively added to prev_nop_frag. */
4694 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4695 prev_nop_frag_holds--;
4696 prev_nop_frag_since++;
4700 method = get_append_method (ip, address_expr, reloc_type);
4701 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4703 dwarf2_emit_insn (0);
4704 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4705 so "move" the instruction address accordingly.
4707 Also, it doesn't seem appropriate for the assembler to reorder .loc
4708 entries. If this instruction is a branch that we are going to swap
4709 with the previous instruction, the two instructions should be
4710 treated as a unit, and the debug information for both instructions
4711 should refer to the start of the branch sequence. Using the
4712 current position is certainly wrong when swapping a 32-bit branch
4713 and a 16-bit delay slot, since the current position would then be
4714 in the middle of a branch. */
4715 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4717 relax32 = (mips_relax_branch
4718 /* Don't try branch relaxation within .set nomacro, or within
4719 .set noat if we use $at for PIC computations. If it turns
4720 out that the branch was out-of-range, we'll get an error. */
4721 && !mips_opts.warn_about_macros
4722 && (mips_opts.at || mips_pic == NO_PIC)
4723 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4724 as they have no complementing branches. */
4725 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4727 if (!HAVE_CODE_COMPRESSION
4730 && *reloc_type == BFD_RELOC_16_PCREL_S2
4731 && delayed_branch_p (ip))
4733 relaxed_branch = TRUE;
4734 add_relaxed_insn (ip, (relaxed_branch_length
4736 uncond_branch_p (ip) ? -1
4737 : branch_likely_p (ip) ? 1
4741 uncond_branch_p (ip),
4742 branch_likely_p (ip),
4743 pinfo & INSN_WRITE_GPR_31,
4745 address_expr->X_add_symbol,
4746 address_expr->X_add_number);
4747 *reloc_type = BFD_RELOC_UNUSED;
4749 else if (mips_opts.micromips
4751 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4752 || *reloc_type > BFD_RELOC_UNUSED)
4753 && (delayed_branch_p (ip) || compact_branch_p (ip))
4754 /* Don't try branch relaxation when users specify
4755 16-bit/32-bit instructions. */
4756 && !forced_insn_length)
4758 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4759 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4760 int uncond = uncond_branch_p (ip) ? -1 : 0;
4761 int compact = compact_branch_p (ip);
4762 int al = pinfo & INSN_WRITE_GPR_31;
4765 gas_assert (address_expr != NULL);
4766 gas_assert (!mips_relax.sequence);
4768 relaxed_branch = TRUE;
4769 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4770 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4771 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4773 address_expr->X_add_symbol,
4774 address_expr->X_add_number);
4775 *reloc_type = BFD_RELOC_UNUSED;
4777 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4779 /* We need to set up a variant frag. */
4780 gas_assert (address_expr != NULL);
4781 add_relaxed_insn (ip, 4, 0,
4783 (*reloc_type - BFD_RELOC_UNUSED,
4784 forced_insn_length == 2, forced_insn_length == 4,
4785 delayed_branch_p (&history[0]),
4786 history[0].mips16_absolute_jump_p),
4787 make_expr_symbol (address_expr), 0);
4789 else if (mips_opts.mips16 && insn_length (ip) == 2)
4791 if (!delayed_branch_p (ip))
4792 /* Make sure there is enough room to swap this instruction with
4793 a following jump instruction. */
4795 add_fixed_insn (ip);
4799 if (mips_opts.mips16
4800 && mips_opts.noreorder
4801 && delayed_branch_p (&history[0]))
4802 as_warn (_("extended instruction in delay slot"));
4804 if (mips_relax.sequence)
4806 /* If we've reached the end of this frag, turn it into a variant
4807 frag and record the information for the instructions we've
4809 if (frag_room () < 4)
4810 relax_close_frag ();
4811 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4814 if (mips_relax.sequence != 2)
4816 if (mips_macro_warning.first_insn_sizes[0] == 0)
4817 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4818 mips_macro_warning.sizes[0] += insn_length (ip);
4819 mips_macro_warning.insns[0]++;
4821 if (mips_relax.sequence != 1)
4823 if (mips_macro_warning.first_insn_sizes[1] == 0)
4824 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4825 mips_macro_warning.sizes[1] += insn_length (ip);
4826 mips_macro_warning.insns[1]++;
4829 if (mips_opts.mips16)
4832 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4834 add_fixed_insn (ip);
4837 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4839 bfd_reloc_code_real_type final_type[3];
4840 reloc_howto_type *howto0;
4841 reloc_howto_type *howto;
4844 /* Perform any necessary conversion to microMIPS relocations
4845 and find out how many relocations there actually are. */
4846 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4847 final_type[i] = micromips_map_reloc (reloc_type[i]);
4849 /* In a compound relocation, it is the final (outermost)
4850 operator that determines the relocated field. */
4851 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4856 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4857 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4858 bfd_get_reloc_size (howto),
4860 howto0 && howto0->pc_relative,
4863 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4864 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4865 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4867 /* These relocations can have an addend that won't fit in
4868 4 octets for 64bit assembly. */
4870 && ! howto->partial_inplace
4871 && (reloc_type[0] == BFD_RELOC_16
4872 || reloc_type[0] == BFD_RELOC_32
4873 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4874 || reloc_type[0] == BFD_RELOC_GPREL16
4875 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4876 || reloc_type[0] == BFD_RELOC_GPREL32
4877 || reloc_type[0] == BFD_RELOC_64
4878 || reloc_type[0] == BFD_RELOC_CTOR
4879 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4880 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4881 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4882 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4883 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4884 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4885 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4886 || hi16_reloc_p (reloc_type[0])
4887 || lo16_reloc_p (reloc_type[0])))
4888 ip->fixp[0]->fx_no_overflow = 1;
4890 /* These relocations can have an addend that won't fit in 2 octets. */
4891 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4892 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4893 ip->fixp[0]->fx_no_overflow = 1;
4895 if (mips_relax.sequence)
4897 if (mips_relax.first_fixup == 0)
4898 mips_relax.first_fixup = ip->fixp[0];
4900 else if (reloc_needs_lo_p (*reloc_type))
4902 struct mips_hi_fixup *hi_fixup;
4904 /* Reuse the last entry if it already has a matching %lo. */
4905 hi_fixup = mips_hi_fixup_list;
4907 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4909 hi_fixup = ((struct mips_hi_fixup *)
4910 xmalloc (sizeof (struct mips_hi_fixup)));
4911 hi_fixup->next = mips_hi_fixup_list;
4912 mips_hi_fixup_list = hi_fixup;
4914 hi_fixup->fixp = ip->fixp[0];
4915 hi_fixup->seg = now_seg;
4918 /* Add fixups for the second and third relocations, if given.
4919 Note that the ABI allows the second relocation to be
4920 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4921 moment we only use RSS_UNDEF, but we could add support
4922 for the others if it ever becomes necessary. */
4923 for (i = 1; i < 3; i++)
4924 if (reloc_type[i] != BFD_RELOC_UNUSED)
4926 ip->fixp[i] = fix_new (ip->frag, ip->where,
4927 ip->fixp[0]->fx_size, NULL, 0,
4928 FALSE, final_type[i]);
4930 /* Use fx_tcbit to mark compound relocs. */
4931 ip->fixp[0]->fx_tcbit = 1;
4932 ip->fixp[i]->fx_tcbit = 1;
4937 /* Update the register mask information. */
4938 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4939 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4944 insert_into_history (0, 1, ip);
4947 case APPEND_ADD_WITH_NOP:
4949 struct mips_cl_insn *nop;
4951 insert_into_history (0, 1, ip);
4952 nop = get_delay_slot_nop (ip);
4953 add_fixed_insn (nop);
4954 insert_into_history (0, 1, nop);
4955 if (mips_relax.sequence)
4956 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4960 case APPEND_ADD_COMPACT:
4961 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4962 gas_assert (mips_opts.mips16);
4963 ip->insn_opcode |= 0x0080;
4964 find_altered_mips16_opcode (ip);
4966 insert_into_history (0, 1, ip);
4971 struct mips_cl_insn delay = history[0];
4972 if (mips_opts.mips16)
4974 know (delay.frag == ip->frag);
4975 move_insn (ip, delay.frag, delay.where);
4976 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4978 else if (relaxed_branch || delay.frag != ip->frag)
4980 /* Add the delay slot instruction to the end of the
4981 current frag and shrink the fixed part of the
4982 original frag. If the branch occupies the tail of
4983 the latter, move it backwards to cover the gap. */
4984 delay.frag->fr_fix -= branch_disp;
4985 if (delay.frag == ip->frag)
4986 move_insn (ip, ip->frag, ip->where - branch_disp);
4987 add_fixed_insn (&delay);
4991 move_insn (&delay, ip->frag,
4992 ip->where - branch_disp + insn_length (ip));
4993 move_insn (ip, history[0].frag, history[0].where);
4997 insert_into_history (0, 1, &delay);
5002 /* If we have just completed an unconditional branch, clear the history. */
5003 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
5004 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
5008 mips_no_prev_insn ();
5010 for (i = 0; i < ARRAY_SIZE (history); i++)
5011 history[i].cleared_p = 1;
5014 /* We need to emit a label at the end of branch-likely macros. */
5015 if (emit_branch_likely_macro)
5017 emit_branch_likely_macro = FALSE;
5018 micromips_add_label ();
5021 /* We just output an insn, so the next one doesn't have a label. */
5022 mips_clear_insn_labels ();
5025 /* Forget that there was any previous instruction or label.
5026 When BRANCH is true, the branch history is also flushed. */
5029 mips_no_prev_insn (void)
5031 prev_nop_frag = NULL;
5032 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
5033 mips_clear_insn_labels ();
5036 /* This function must be called before we emit something other than
5037 instructions. It is like mips_no_prev_insn except that it inserts
5038 any NOPS that might be needed by previous instructions. */
5041 mips_emit_delays (void)
5043 if (! mips_opts.noreorder)
5045 int nops = nops_for_insn (0, history, NULL);
5049 add_fixed_insn (NOP_INSN);
5050 mips_move_text_labels ();
5053 mips_no_prev_insn ();
5056 /* Start a (possibly nested) noreorder block. */
5059 start_noreorder (void)
5061 if (mips_opts.noreorder == 0)
5066 /* None of the instructions before the .set noreorder can be moved. */
5067 for (i = 0; i < ARRAY_SIZE (history); i++)
5068 history[i].fixed_p = 1;
5070 /* Insert any nops that might be needed between the .set noreorder
5071 block and the previous instructions. We will later remove any
5072 nops that turn out not to be needed. */
5073 nops = nops_for_insn (0, history, NULL);
5076 if (mips_optimize != 0)
5078 /* Record the frag which holds the nop instructions, so
5079 that we can remove them if we don't need them. */
5080 frag_grow (nops * NOP_INSN_SIZE);
5081 prev_nop_frag = frag_now;
5082 prev_nop_frag_holds = nops;
5083 prev_nop_frag_required = 0;
5084 prev_nop_frag_since = 0;
5087 for (; nops > 0; --nops)
5088 add_fixed_insn (NOP_INSN);
5090 /* Move on to a new frag, so that it is safe to simply
5091 decrease the size of prev_nop_frag. */
5092 frag_wane (frag_now);
5094 mips_move_text_labels ();
5096 mips_mark_labels ();
5097 mips_clear_insn_labels ();
5099 mips_opts.noreorder++;
5100 mips_any_noreorder = 1;
5103 /* End a nested noreorder block. */
5106 end_noreorder (void)
5108 mips_opts.noreorder--;
5109 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5111 /* Commit to inserting prev_nop_frag_required nops and go back to
5112 handling nop insertion the .set reorder way. */
5113 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5115 insert_into_history (prev_nop_frag_since,
5116 prev_nop_frag_required, NOP_INSN);
5117 prev_nop_frag = NULL;
5121 /* Set up global variables for the start of a new macro. */
5126 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5127 memset (&mips_macro_warning.first_insn_sizes, 0,
5128 sizeof (mips_macro_warning.first_insn_sizes));
5129 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5130 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5131 && delayed_branch_p (&history[0]));
5132 switch (history[0].insn_mo->pinfo2
5133 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5135 case INSN2_BRANCH_DELAY_32BIT:
5136 mips_macro_warning.delay_slot_length = 4;
5138 case INSN2_BRANCH_DELAY_16BIT:
5139 mips_macro_warning.delay_slot_length = 2;
5142 mips_macro_warning.delay_slot_length = 0;
5145 mips_macro_warning.first_frag = NULL;
5148 /* Given that a macro is longer than one instruction or of the wrong size,
5149 return the appropriate warning for it. Return null if no warning is
5150 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5151 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5152 and RELAX_NOMACRO. */
5155 macro_warning (relax_substateT subtype)
5157 if (subtype & RELAX_DELAY_SLOT)
5158 return _("Macro instruction expanded into multiple instructions"
5159 " in a branch delay slot");
5160 else if (subtype & RELAX_NOMACRO)
5161 return _("Macro instruction expanded into multiple instructions");
5162 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5163 | RELAX_DELAY_SLOT_SIZE_SECOND))
5164 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5165 ? _("Macro instruction expanded into a wrong size instruction"
5166 " in a 16-bit branch delay slot")
5167 : _("Macro instruction expanded into a wrong size instruction"
5168 " in a 32-bit branch delay slot"));
5173 /* Finish up a macro. Emit warnings as appropriate. */
5178 /* Relaxation warning flags. */
5179 relax_substateT subtype = 0;
5181 /* Check delay slot size requirements. */
5182 if (mips_macro_warning.delay_slot_length == 2)
5183 subtype |= RELAX_DELAY_SLOT_16BIT;
5184 if (mips_macro_warning.delay_slot_length != 0)
5186 if (mips_macro_warning.delay_slot_length
5187 != mips_macro_warning.first_insn_sizes[0])
5188 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5189 if (mips_macro_warning.delay_slot_length
5190 != mips_macro_warning.first_insn_sizes[1])
5191 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5194 /* Check instruction count requirements. */
5195 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5197 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5198 subtype |= RELAX_SECOND_LONGER;
5199 if (mips_opts.warn_about_macros)
5200 subtype |= RELAX_NOMACRO;
5201 if (mips_macro_warning.delay_slot_p)
5202 subtype |= RELAX_DELAY_SLOT;
5205 /* If both alternatives fail to fill a delay slot correctly,
5206 emit the warning now. */
5207 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5208 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5213 s = subtype & (RELAX_DELAY_SLOT_16BIT
5214 | RELAX_DELAY_SLOT_SIZE_FIRST
5215 | RELAX_DELAY_SLOT_SIZE_SECOND);
5216 msg = macro_warning (s);
5218 as_warn ("%s", msg);
5222 /* If both implementations are longer than 1 instruction, then emit the
5224 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5229 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5230 msg = macro_warning (s);
5232 as_warn ("%s", msg);
5236 /* If any flags still set, then one implementation might need a warning
5237 and the other either will need one of a different kind or none at all.
5238 Pass any remaining flags over to relaxation. */
5239 if (mips_macro_warning.first_frag != NULL)
5240 mips_macro_warning.first_frag->fr_subtype |= subtype;
5243 /* Instruction operand formats used in macros that vary between
5244 standard MIPS and microMIPS code. */
5246 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
5247 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5248 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5249 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5250 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5251 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
5252 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5253 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5255 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
5256 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5257 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5258 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5259 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5260 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
5261 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5262 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5264 /* Read a macro's relocation codes from *ARGS and store them in *R.
5265 The first argument in *ARGS will be either the code for a single
5266 relocation or -1 followed by the three codes that make up a
5267 composite relocation. */
5270 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5274 next = va_arg (*args, int);
5276 r[0] = (bfd_reloc_code_real_type) next;
5279 for (i = 0; i < 3; i++)
5280 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5281 /* This function is only used for 16-bit relocation fields.
5282 To make the macro code simpler, treat an unrelocated value
5283 in the same way as BFD_RELOC_LO16. */
5284 if (r[0] == BFD_RELOC_UNUSED)
5285 r[0] = BFD_RELOC_LO16;
5289 /* Build an instruction created by a macro expansion. This is passed
5290 a pointer to the count of instructions created so far, an
5291 expression, the name of the instruction to build, an operand format
5292 string, and corresponding arguments. */
5295 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5297 const struct mips_opcode *mo = NULL;
5298 bfd_reloc_code_real_type r[3];
5299 const struct mips_opcode *amo;
5300 struct hash_control *hash;
5301 struct mips_cl_insn insn;
5304 va_start (args, fmt);
5306 if (mips_opts.mips16)
5308 mips16_macro_build (ep, name, fmt, &args);
5313 r[0] = BFD_RELOC_UNUSED;
5314 r[1] = BFD_RELOC_UNUSED;
5315 r[2] = BFD_RELOC_UNUSED;
5316 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5317 amo = (struct mips_opcode *) hash_find (hash, name);
5319 gas_assert (strcmp (name, amo->name) == 0);
5323 /* Search until we get a match for NAME. It is assumed here that
5324 macros will never generate MDMX, MIPS-3D, or MT instructions.
5325 We try to match an instruction that fulfils the branch delay
5326 slot instruction length requirement (if any) of the previous
5327 instruction. While doing this we record the first instruction
5328 seen that matches all the other conditions and use it anyway
5329 if the requirement cannot be met; we will issue an appropriate
5330 warning later on. */
5331 if (strcmp (fmt, amo->args) == 0
5332 && amo->pinfo != INSN_MACRO
5333 && is_opcode_valid (amo)
5334 && is_size_valid (amo))
5336 if (is_delay_slot_valid (amo))
5346 gas_assert (amo->name);
5348 while (strcmp (name, amo->name) == 0);
5351 create_insn (&insn, mo);
5369 INSERT_OPERAND (mips_opts.micromips,
5370 EXTLSB, insn, va_arg (args, int));
5375 /* Note that in the macro case, these arguments are already
5376 in MSB form. (When handling the instruction in the
5377 non-macro case, these arguments are sizes from which
5378 MSB values must be calculated.) */
5379 INSERT_OPERAND (mips_opts.micromips,
5380 INSMSB, insn, va_arg (args, int));
5384 gas_assert (!mips_opts.micromips);
5385 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5391 /* Note that in the macro case, these arguments are already
5392 in MSBD form. (When handling the instruction in the
5393 non-macro case, these arguments are sizes from which
5394 MSBD values must be calculated.) */
5395 INSERT_OPERAND (mips_opts.micromips,
5396 EXTMSBD, insn, va_arg (args, int));
5400 gas_assert (!mips_opts.micromips);
5401 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5405 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5414 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5418 gas_assert (mips_opts.micromips);
5422 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5426 INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int));
5430 gas_assert (!mips_opts.micromips);
5432 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5436 if (mips_opts.micromips)
5437 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5439 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5443 gas_assert (!mips_opts.micromips);
5445 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5449 gas_assert (!mips_opts.micromips);
5451 int tmp = va_arg (args, int);
5453 INSERT_OPERAND (0, RT, insn, tmp);
5454 INSERT_OPERAND (0, RD, insn, tmp);
5460 gas_assert (!mips_opts.micromips);
5461 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5468 INSERT_OPERAND (mips_opts.micromips,
5469 SHAMT, insn, va_arg (args, int));
5473 gas_assert (!mips_opts.micromips);
5474 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5478 gas_assert (!mips_opts.micromips);
5479 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5483 gas_assert (!mips_opts.micromips);
5484 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5488 gas_assert (!mips_opts.micromips);
5489 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5496 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5501 macro_read_relocs (&args, r);
5502 gas_assert (*r == BFD_RELOC_GPREL16
5503 || *r == BFD_RELOC_MIPS_HIGHER
5504 || *r == BFD_RELOC_HI16_S
5505 || *r == BFD_RELOC_LO16
5506 || *r == BFD_RELOC_MIPS_GOT_OFST);
5510 macro_read_relocs (&args, r);
5514 macro_read_relocs (&args, r);
5515 gas_assert (ep != NULL
5516 && (ep->X_op == O_constant
5517 || (ep->X_op == O_symbol
5518 && (*r == BFD_RELOC_MIPS_HIGHEST
5519 || *r == BFD_RELOC_HI16_S
5520 || *r == BFD_RELOC_HI16
5521 || *r == BFD_RELOC_GPREL16
5522 || *r == BFD_RELOC_MIPS_GOT_HI16
5523 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5527 gas_assert (ep != NULL);
5530 * This allows macro() to pass an immediate expression for
5531 * creating short branches without creating a symbol.
5533 * We don't allow branch relaxation for these branches, as
5534 * they should only appear in ".set nomacro" anyway.
5536 if (ep->X_op == O_constant)
5538 /* For microMIPS we always use relocations for branches.
5539 So we should not resolve immediate values. */
5540 gas_assert (!mips_opts.micromips);
5542 if ((ep->X_add_number & 3) != 0)
5543 as_bad (_("branch to misaligned address (0x%lx)"),
5544 (unsigned long) ep->X_add_number);
5545 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5546 as_bad (_("branch address range overflow (0x%lx)"),
5547 (unsigned long) ep->X_add_number);
5548 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5552 *r = BFD_RELOC_16_PCREL_S2;
5556 gas_assert (ep != NULL);
5557 *r = BFD_RELOC_MIPS_JMP;
5561 gas_assert (!mips_opts.micromips);
5562 INSERT_OPERAND (0, COPZ, insn, va_arg (args, int));
5566 INSERT_OPERAND (mips_opts.micromips,
5567 CACHE, insn, va_arg (args, int));
5571 gas_assert (mips_opts.micromips);
5572 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5576 gas_assert (mips_opts.micromips);
5577 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5581 INSERT_OPERAND (mips_opts.micromips,
5582 3BITPOS, insn, va_arg (args, int));
5586 INSERT_OPERAND (mips_opts.micromips,
5587 OFFSET12, insn, va_arg (args, int));
5591 gas_assert (mips_opts.micromips);
5592 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5595 case 'm': /* Opcode extension character. */
5596 gas_assert (mips_opts.micromips);
5600 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5604 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5608 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5622 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5624 append_insn (&insn, ep, r, TRUE);
5628 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5631 struct mips_opcode *mo;
5632 struct mips_cl_insn insn;
5633 bfd_reloc_code_real_type r[3]
5634 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5636 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5638 gas_assert (strcmp (name, mo->name) == 0);
5640 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5643 gas_assert (mo->name);
5644 gas_assert (strcmp (name, mo->name) == 0);
5647 create_insn (&insn, mo);
5665 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5670 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5674 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5678 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5688 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5695 regno = va_arg (*args, int);
5696 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5697 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5720 gas_assert (ep != NULL);
5722 if (ep->X_op != O_constant)
5723 *r = (int) BFD_RELOC_UNUSED + c;
5724 else if (calculate_reloc (*r, ep->X_add_number, &value))
5726 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5728 *r = BFD_RELOC_UNUSED;
5734 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5741 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5743 append_insn (&insn, ep, r, TRUE);
5747 * Sign-extend 32-bit mode constants that have bit 31 set and all
5748 * higher bits unset.
5751 normalize_constant_expr (expressionS *ex)
5753 if (ex->X_op == O_constant
5754 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5755 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5760 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5761 * all higher bits unset.
5764 normalize_address_expr (expressionS *ex)
5766 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5767 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5768 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5769 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5774 * Generate a "jalr" instruction with a relocation hint to the called
5775 * function. This occurs in NewABI PIC code.
5778 macro_build_jalr (expressionS *ep, int cprestore)
5780 static const bfd_reloc_code_real_type jalr_relocs[2]
5781 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5782 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5786 if (MIPS_JALR_HINT_P (ep))
5791 if (mips_opts.micromips)
5793 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
5794 ? "jalr" : "jalrs");
5795 if (MIPS_JALR_HINT_P (ep)
5797 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5798 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5800 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5803 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5804 if (MIPS_JALR_HINT_P (ep))
5805 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5809 * Generate a "lui" instruction.
5812 macro_build_lui (expressionS *ep, int regnum)
5814 gas_assert (! mips_opts.mips16);
5816 if (ep->X_op != O_constant)
5818 gas_assert (ep->X_op == O_symbol);
5819 /* _gp_disp is a special case, used from s_cpload.
5820 __gnu_local_gp is used if mips_no_shared. */
5821 gas_assert (mips_pic == NO_PIC
5823 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5824 || (! mips_in_shared
5825 && strcmp (S_GET_NAME (ep->X_add_symbol),
5826 "__gnu_local_gp") == 0));
5829 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5832 /* Generate a sequence of instructions to do a load or store from a constant
5833 offset off of a base register (breg) into/from a target register (treg),
5834 using AT if necessary. */
5836 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5837 int treg, int breg, int dbl)
5839 gas_assert (ep->X_op == O_constant);
5841 /* Sign-extending 32-bit constants makes their handling easier. */
5843 normalize_constant_expr (ep);
5845 /* Right now, this routine can only handle signed 32-bit constants. */
5846 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5847 as_warn (_("operand overflow"));
5849 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5851 /* Signed 16-bit offset will fit in the op. Easy! */
5852 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5856 /* 32-bit offset, need multiple instructions and AT, like:
5857 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5858 addu $tempreg,$tempreg,$breg
5859 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5860 to handle the complete offset. */
5861 macro_build_lui (ep, AT);
5862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5863 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5866 as_bad (_("Macro used $at after \".set noat\""));
5871 * Generates code to set the $at register to true (one)
5872 * if reg is less than the immediate expression.
5875 set_at (int reg, int unsignedp)
5877 if (imm_expr.X_op == O_constant
5878 && imm_expr.X_add_number >= -0x8000
5879 && imm_expr.X_add_number < 0x8000)
5880 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5881 AT, reg, BFD_RELOC_LO16);
5884 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5885 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5889 /* Warn if an expression is not a constant. */
5892 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5894 if (ex->X_op == O_big)
5895 as_bad (_("unsupported large constant"));
5896 else if (ex->X_op != O_constant)
5897 as_bad (_("Instruction %s requires absolute expression"),
5900 if (HAVE_32BIT_GPRS)
5901 normalize_constant_expr (ex);
5904 /* Count the leading zeroes by performing a binary chop. This is a
5905 bulky bit of source, but performance is a LOT better for the
5906 majority of values than a simple loop to count the bits:
5907 for (lcnt = 0; (lcnt < 32); lcnt++)
5908 if ((v) & (1 << (31 - lcnt)))
5910 However it is not code size friendly, and the gain will drop a bit
5911 on certain cached systems.
5913 #define COUNT_TOP_ZEROES(v) \
5914 (((v) & ~0xffff) == 0 \
5915 ? ((v) & ~0xff) == 0 \
5916 ? ((v) & ~0xf) == 0 \
5917 ? ((v) & ~0x3) == 0 \
5918 ? ((v) & ~0x1) == 0 \
5923 : ((v) & ~0x7) == 0 \
5926 : ((v) & ~0x3f) == 0 \
5927 ? ((v) & ~0x1f) == 0 \
5930 : ((v) & ~0x7f) == 0 \
5933 : ((v) & ~0xfff) == 0 \
5934 ? ((v) & ~0x3ff) == 0 \
5935 ? ((v) & ~0x1ff) == 0 \
5938 : ((v) & ~0x7ff) == 0 \
5941 : ((v) & ~0x3fff) == 0 \
5942 ? ((v) & ~0x1fff) == 0 \
5945 : ((v) & ~0x7fff) == 0 \
5948 : ((v) & ~0xffffff) == 0 \
5949 ? ((v) & ~0xfffff) == 0 \
5950 ? ((v) & ~0x3ffff) == 0 \
5951 ? ((v) & ~0x1ffff) == 0 \
5954 : ((v) & ~0x7ffff) == 0 \
5957 : ((v) & ~0x3fffff) == 0 \
5958 ? ((v) & ~0x1fffff) == 0 \
5961 : ((v) & ~0x7fffff) == 0 \
5964 : ((v) & ~0xfffffff) == 0 \
5965 ? ((v) & ~0x3ffffff) == 0 \
5966 ? ((v) & ~0x1ffffff) == 0 \
5969 : ((v) & ~0x7ffffff) == 0 \
5972 : ((v) & ~0x3fffffff) == 0 \
5973 ? ((v) & ~0x1fffffff) == 0 \
5976 : ((v) & ~0x7fffffff) == 0 \
5981 * This routine generates the least number of instructions necessary to load
5982 * an absolute expression value into a register.
5985 load_register (int reg, expressionS *ep, int dbl)
5988 expressionS hi32, lo32;
5990 if (ep->X_op != O_big)
5992 gas_assert (ep->X_op == O_constant);
5994 /* Sign-extending 32-bit constants makes their handling easier. */
5996 normalize_constant_expr (ep);
5998 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
6000 /* We can handle 16 bit signed values with an addiu to
6001 $zero. No need to ever use daddiu here, since $zero and
6002 the result are always correct in 32 bit mode. */
6003 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6006 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
6008 /* We can handle 16 bit unsigned values with an ori to
6010 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6013 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
6015 /* 32 bit values require an lui. */
6016 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6017 if ((ep->X_add_number & 0xffff) != 0)
6018 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6023 /* The value is larger than 32 bits. */
6025 if (!dbl || HAVE_32BIT_GPRS)
6029 sprintf_vma (value, ep->X_add_number);
6030 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6031 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6035 if (ep->X_op != O_big)
6038 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6039 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
6040 hi32.X_add_number &= 0xffffffff;
6042 lo32.X_add_number &= 0xffffffff;
6046 gas_assert (ep->X_add_number > 2);
6047 if (ep->X_add_number == 3)
6048 generic_bignum[3] = 0;
6049 else if (ep->X_add_number > 4)
6050 as_bad (_("Number larger than 64 bits"));
6051 lo32.X_op = O_constant;
6052 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6053 hi32.X_op = O_constant;
6054 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6057 if (hi32.X_add_number == 0)
6062 unsigned long hi, lo;
6064 if (hi32.X_add_number == (offsetT) 0xffffffff)
6066 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6068 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6071 if (lo32.X_add_number & 0x80000000)
6073 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6074 if (lo32.X_add_number & 0xffff)
6075 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6080 /* Check for 16bit shifted constant. We know that hi32 is
6081 non-zero, so start the mask on the first bit of the hi32
6086 unsigned long himask, lomask;
6090 himask = 0xffff >> (32 - shift);
6091 lomask = (0xffff << shift) & 0xffffffff;
6095 himask = 0xffff << (shift - 32);
6098 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6099 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6103 tmp.X_op = O_constant;
6105 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6106 | (lo32.X_add_number >> shift));
6108 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6109 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6110 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6111 reg, reg, (shift >= 32) ? shift - 32 : shift);
6116 while (shift <= (64 - 16));
6118 /* Find the bit number of the lowest one bit, and store the
6119 shifted value in hi/lo. */
6120 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6121 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6125 while ((lo & 1) == 0)
6130 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6136 while ((hi & 1) == 0)
6145 /* Optimize if the shifted value is a (power of 2) - 1. */
6146 if ((hi == 0 && ((lo + 1) & lo) == 0)
6147 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6149 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6154 /* This instruction will set the register to be all
6156 tmp.X_op = O_constant;
6157 tmp.X_add_number = (offsetT) -1;
6158 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6162 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6163 reg, reg, (bit >= 32) ? bit - 32 : bit);
6165 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6166 reg, reg, (shift >= 32) ? shift - 32 : shift);
6171 /* Sign extend hi32 before calling load_register, because we can
6172 generally get better code when we load a sign extended value. */
6173 if ((hi32.X_add_number & 0x80000000) != 0)
6174 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6175 load_register (reg, &hi32, 0);
6178 if ((lo32.X_add_number & 0xffff0000) == 0)
6182 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6190 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6192 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6193 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6199 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6203 mid16.X_add_number >>= 16;
6204 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6205 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6208 if ((lo32.X_add_number & 0xffff) != 0)
6209 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6213 load_delay_nop (void)
6215 if (!gpr_interlocks)
6216 macro_build (NULL, "nop", "");
6219 /* Load an address into a register. */
6222 load_address (int reg, expressionS *ep, int *used_at)
6224 if (ep->X_op != O_constant
6225 && ep->X_op != O_symbol)
6227 as_bad (_("expression too complex"));
6228 ep->X_op = O_constant;
6231 if (ep->X_op == O_constant)
6233 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6237 if (mips_pic == NO_PIC)
6239 /* If this is a reference to a GP relative symbol, we want
6240 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6242 lui $reg,<sym> (BFD_RELOC_HI16_S)
6243 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6244 If we have an addend, we always use the latter form.
6246 With 64bit address space and a usable $at we want
6247 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6248 lui $at,<sym> (BFD_RELOC_HI16_S)
6249 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6250 daddiu $at,<sym> (BFD_RELOC_LO16)
6254 If $at is already in use, we use a path which is suboptimal
6255 on superscalar processors.
6256 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6257 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6259 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6261 daddiu $reg,<sym> (BFD_RELOC_LO16)
6263 For GP relative symbols in 64bit address space we can use
6264 the same sequence as in 32bit address space. */
6265 if (HAVE_64BIT_SYMBOLS)
6267 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6268 && !nopic_need_relax (ep->X_add_symbol, 1))
6270 relax_start (ep->X_add_symbol);
6271 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6272 mips_gp_register, BFD_RELOC_GPREL16);
6276 if (*used_at == 0 && mips_opts.at)
6278 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6279 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6280 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6281 BFD_RELOC_MIPS_HIGHER);
6282 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6283 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6284 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6289 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6290 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6291 BFD_RELOC_MIPS_HIGHER);
6292 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6293 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6294 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6295 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6298 if (mips_relax.sequence)
6303 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6304 && !nopic_need_relax (ep->X_add_symbol, 1))
6306 relax_start (ep->X_add_symbol);
6307 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6308 mips_gp_register, BFD_RELOC_GPREL16);
6311 macro_build_lui (ep, reg);
6312 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6313 reg, reg, BFD_RELOC_LO16);
6314 if (mips_relax.sequence)
6318 else if (!mips_big_got)
6322 /* If this is a reference to an external symbol, we want
6323 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6325 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6327 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6328 If there is a constant, it must be added in after.
6330 If we have NewABI, we want
6331 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6332 unless we're referencing a global symbol with a non-zero
6333 offset, in which case cst must be added separately. */
6336 if (ep->X_add_number)
6338 ex.X_add_number = ep->X_add_number;
6339 ep->X_add_number = 0;
6340 relax_start (ep->X_add_symbol);
6341 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6342 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6343 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6344 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6345 ex.X_op = O_constant;
6346 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6347 reg, reg, BFD_RELOC_LO16);
6348 ep->X_add_number = ex.X_add_number;
6351 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6352 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6353 if (mips_relax.sequence)
6358 ex.X_add_number = ep->X_add_number;
6359 ep->X_add_number = 0;
6360 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6361 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6363 relax_start (ep->X_add_symbol);
6365 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6369 if (ex.X_add_number != 0)
6371 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6372 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6373 ex.X_op = O_constant;
6374 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6375 reg, reg, BFD_RELOC_LO16);
6379 else if (mips_big_got)
6383 /* This is the large GOT case. If this is a reference to an
6384 external symbol, we want
6385 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6387 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6389 Otherwise, for a reference to a local symbol in old ABI, we want
6390 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6392 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6393 If there is a constant, it must be added in after.
6395 In the NewABI, for local symbols, with or without offsets, we want:
6396 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6397 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6401 ex.X_add_number = ep->X_add_number;
6402 ep->X_add_number = 0;
6403 relax_start (ep->X_add_symbol);
6404 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6405 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6406 reg, reg, mips_gp_register);
6407 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6408 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6409 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6410 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6411 else if (ex.X_add_number)
6413 ex.X_op = O_constant;
6414 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6418 ep->X_add_number = ex.X_add_number;
6420 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6421 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6422 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6423 BFD_RELOC_MIPS_GOT_OFST);
6428 ex.X_add_number = ep->X_add_number;
6429 ep->X_add_number = 0;
6430 relax_start (ep->X_add_symbol);
6431 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6432 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6433 reg, reg, mips_gp_register);
6434 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6435 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6437 if (reg_needs_delay (mips_gp_register))
6439 /* We need a nop before loading from $gp. This special
6440 check is required because the lui which starts the main
6441 instruction stream does not refer to $gp, and so will not
6442 insert the nop which may be required. */
6443 macro_build (NULL, "nop", "");
6445 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6446 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6448 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6452 if (ex.X_add_number != 0)
6454 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6455 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6456 ex.X_op = O_constant;
6457 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6465 if (!mips_opts.at && *used_at == 1)
6466 as_bad (_("Macro used $at after \".set noat\""));
6469 /* Move the contents of register SOURCE into register DEST. */
6472 move_register (int dest, int source)
6474 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6475 instruction specifically requires a 32-bit one. */
6476 if (mips_opts.micromips
6477 && !mips_opts.insn32
6478 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6479 macro_build (NULL, "move", "mp,mj", dest, source);
6481 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6485 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6486 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6487 The two alternatives are:
6489 Global symbol Local sybmol
6490 ------------- ------------
6491 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6493 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6495 load_got_offset emits the first instruction and add_got_offset
6496 emits the second for a 16-bit offset or add_got_offset_hilo emits
6497 a sequence to add a 32-bit offset using a scratch register. */
6500 load_got_offset (int dest, expressionS *local)
6505 global.X_add_number = 0;
6507 relax_start (local->X_add_symbol);
6508 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6509 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6511 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6512 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6517 add_got_offset (int dest, expressionS *local)
6521 global.X_op = O_constant;
6522 global.X_op_symbol = NULL;
6523 global.X_add_symbol = NULL;
6524 global.X_add_number = local->X_add_number;
6526 relax_start (local->X_add_symbol);
6527 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6528 dest, dest, BFD_RELOC_LO16);
6530 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6535 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6538 int hold_mips_optimize;
6540 global.X_op = O_constant;
6541 global.X_op_symbol = NULL;
6542 global.X_add_symbol = NULL;
6543 global.X_add_number = local->X_add_number;
6545 relax_start (local->X_add_symbol);
6546 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6548 /* Set mips_optimize around the lui instruction to avoid
6549 inserting an unnecessary nop after the lw. */
6550 hold_mips_optimize = mips_optimize;
6552 macro_build_lui (&global, tmp);
6553 mips_optimize = hold_mips_optimize;
6554 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6557 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6560 /* Emit a sequence of instructions to emulate a branch likely operation.
6561 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6562 is its complementing branch with the original condition negated.
6563 CALL is set if the original branch specified the link operation.
6564 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6566 Code like this is produced in the noreorder mode:
6571 delay slot (executed only if branch taken)
6579 delay slot (executed only if branch taken)
6582 In the reorder mode the delay slot would be filled with a nop anyway,
6583 so code produced is simply:
6588 This function is used when producing code for the microMIPS ASE that
6589 does not implement branch likely instructions in hardware. */
6592 macro_build_branch_likely (const char *br, const char *brneg,
6593 int call, expressionS *ep, const char *fmt,
6594 unsigned int sreg, unsigned int treg)
6596 int noreorder = mips_opts.noreorder;
6599 gas_assert (mips_opts.micromips);
6603 micromips_label_expr (&expr1);
6604 macro_build (&expr1, brneg, fmt, sreg, treg);
6605 macro_build (NULL, "nop", "");
6606 macro_build (ep, call ? "bal" : "b", "p");
6608 /* Set to true so that append_insn adds a label. */
6609 emit_branch_likely_macro = TRUE;
6613 macro_build (ep, br, fmt, sreg, treg);
6614 macro_build (NULL, "nop", "");
6619 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6620 the condition code tested. EP specifies the branch target. */
6623 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6650 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6653 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6654 the register tested. EP specifies the branch target. */
6657 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6659 const char *brneg = NULL;
6669 br = mips_opts.micromips ? "bgez" : "bgezl";
6673 gas_assert (mips_opts.micromips);
6674 br = mips_opts.insn32 ? "bgezal" : "bgezals";
6682 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6689 br = mips_opts.micromips ? "blez" : "blezl";
6696 br = mips_opts.micromips ? "bltz" : "bltzl";
6700 gas_assert (mips_opts.micromips);
6701 br = mips_opts.insn32 ? "bltzal" : "bltzals";
6708 if (mips_opts.micromips && brneg)
6709 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6711 macro_build (ep, br, "s,p", sreg);
6714 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6715 TREG as the registers tested. EP specifies the branch target. */
6718 macro_build_branch_rsrt (int type, expressionS *ep,
6719 unsigned int sreg, unsigned int treg)
6721 const char *brneg = NULL;
6733 br = mips_opts.micromips ? "beq" : "beql";
6742 br = mips_opts.micromips ? "bne" : "bnel";
6748 if (mips_opts.micromips && brneg)
6749 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6751 macro_build (ep, br, "s,t,p", sreg, treg);
6754 /* Return the high part that should be loaded in order to make the low
6755 part of VALUE accessible using an offset of OFFBITS bits. */
6758 offset_high_part (offsetT value, unsigned int offbits)
6765 bias = 1 << (offbits - 1);
6766 low_mask = bias * 2 - 1;
6767 return (value + bias) & ~low_mask;
6770 /* Return true if the value stored in offset_expr and offset_reloc
6771 fits into a signed offset of OFFBITS bits. RANGE is the maximum
6772 amount that the caller wants to add without inducing overflow
6773 and ALIGN is the known alignment of the value in bytes. */
6776 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
6780 /* Accept any relocation operator if overflow isn't a concern. */
6781 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
6784 /* These relocations are guaranteed not to overflow in correct links. */
6785 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
6786 || gprel16_reloc_p (*offset_reloc))
6789 if (offset_expr.X_op == O_constant
6790 && offset_high_part (offset_expr.X_add_number, offbits) == 0
6791 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
6798 * This routine implements the seemingly endless macro or synthesized
6799 * instructions and addressing modes in the mips assembly language. Many
6800 * of these macros are simple and are similar to each other. These could
6801 * probably be handled by some kind of table or grammar approach instead of
6802 * this verbose method. Others are not simple macros but are more like
6803 * optimizing code generation.
6804 * One interesting optimization is when several store macros appear
6805 * consecutively that would load AT with the upper half of the same address.
6806 * The ensuing load upper instructions are ommited. This implies some kind
6807 * of global optimization. We currently only optimize within a single macro.
6808 * For many of the load and store macros if the address is specified as a
6809 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6810 * first load register 'at' with zero and use it as the base register. The
6811 * mips assembler simply uses register $zero. Just one tiny optimization
6815 macro (struct mips_cl_insn *ip, char *str)
6817 unsigned int treg, sreg, dreg, breg;
6818 unsigned int tempreg;
6821 expressionS label_expr;
6836 bfd_boolean large_offset;
6838 int hold_mips_optimize;
6841 gas_assert (! mips_opts.mips16);
6843 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6844 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6845 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6846 mask = ip->insn_mo->mask;
6848 label_expr.X_op = O_constant;
6849 label_expr.X_op_symbol = NULL;
6850 label_expr.X_add_symbol = NULL;
6851 label_expr.X_add_number = 0;
6853 expr1.X_op = O_constant;
6854 expr1.X_op_symbol = NULL;
6855 expr1.X_add_symbol = NULL;
6856 expr1.X_add_number = 1;
6872 if (mips_opts.micromips)
6873 micromips_label_expr (&label_expr);
6875 label_expr.X_add_number = 8;
6876 macro_build (&label_expr, "bgez", "s,p", sreg);
6878 macro_build (NULL, "nop", "");
6880 move_register (dreg, sreg);
6881 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6882 if (mips_opts.micromips)
6883 micromips_add_label ();
6900 if (!mips_opts.micromips)
6902 if (imm_expr.X_op == O_constant
6903 && imm_expr.X_add_number >= -0x200
6904 && imm_expr.X_add_number < 0x200)
6906 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6915 if (imm_expr.X_op == O_constant
6916 && imm_expr.X_add_number >= -0x8000
6917 && imm_expr.X_add_number < 0x8000)
6919 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6924 load_register (AT, &imm_expr, dbl);
6925 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6944 if (imm_expr.X_op == O_constant
6945 && imm_expr.X_add_number >= 0
6946 && imm_expr.X_add_number < 0x10000)
6948 if (mask != M_NOR_I)
6949 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6952 macro_build (&imm_expr, "ori", "t,r,i",
6953 treg, sreg, BFD_RELOC_LO16);
6954 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6960 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6961 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6965 switch (imm_expr.X_add_number)
6968 macro_build (NULL, "nop", "");
6971 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6975 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6976 (int) imm_expr.X_add_number);
6979 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6980 (unsigned long) imm_expr.X_add_number);
6989 gas_assert (mips_opts.micromips);
6990 macro_build_branch_ccl (mask, &offset_expr,
6991 EXTRACT_OPERAND (1, BCC, *ip));
6998 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7004 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
7009 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
7016 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
7018 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
7022 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7023 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7024 &offset_expr, AT, ZERO);
7034 macro_build_branch_rs (mask, &offset_expr, sreg);
7040 /* Check for > max integer. */
7041 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7044 /* Result is always false. */
7046 macro_build (NULL, "nop", "");
7048 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
7051 if (imm_expr.X_op != O_constant)
7052 as_bad (_("Unsupported large constant"));
7053 ++imm_expr.X_add_number;
7057 if (mask == M_BGEL_I)
7059 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7061 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
7062 &offset_expr, sreg);
7065 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7067 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
7068 &offset_expr, sreg);
7071 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
7074 /* result is always true */
7075 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
7076 macro_build (&offset_expr, "b", "p");
7081 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7082 &offset_expr, AT, ZERO);
7091 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7092 &offset_expr, ZERO, treg);
7096 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7097 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7098 &offset_expr, AT, ZERO);
7107 && imm_expr.X_op == O_constant
7108 && imm_expr.X_add_number == -1))
7110 if (imm_expr.X_op != O_constant)
7111 as_bad (_("Unsupported large constant"));
7112 ++imm_expr.X_add_number;
7116 if (mask == M_BGEUL_I)
7118 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7120 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7121 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7122 &offset_expr, sreg, ZERO);
7127 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7128 &offset_expr, AT, ZERO);
7136 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7138 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7142 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7143 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7144 &offset_expr, AT, ZERO);
7152 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7153 &offset_expr, sreg, ZERO);
7159 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7160 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7161 &offset_expr, AT, ZERO);
7169 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7171 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7175 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7176 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7177 &offset_expr, AT, ZERO);
7184 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7186 if (imm_expr.X_op != O_constant)
7187 as_bad (_("Unsupported large constant"));
7188 ++imm_expr.X_add_number;
7192 if (mask == M_BLTL_I)
7194 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7195 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7196 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7197 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7202 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7203 &offset_expr, AT, ZERO);
7211 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7212 &offset_expr, sreg, ZERO);
7218 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7219 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7220 &offset_expr, AT, ZERO);
7229 && imm_expr.X_op == O_constant
7230 && imm_expr.X_add_number == -1))
7232 if (imm_expr.X_op != O_constant)
7233 as_bad (_("Unsupported large constant"));
7234 ++imm_expr.X_add_number;
7238 if (mask == M_BLTUL_I)
7240 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7242 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7243 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7244 &offset_expr, sreg, ZERO);
7249 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7250 &offset_expr, AT, ZERO);
7258 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7260 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7264 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7265 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7266 &offset_expr, AT, ZERO);
7276 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7277 &offset_expr, ZERO, treg);
7281 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7282 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7283 &offset_expr, AT, ZERO);
7289 /* Use unsigned arithmetic. */
7293 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7295 as_bad (_("Unsupported large constant"));
7300 pos = imm_expr.X_add_number;
7301 size = imm2_expr.X_add_number;
7306 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7309 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7311 as_bad (_("Improper extract size (%lu, position %lu)"),
7312 (unsigned long) size, (unsigned long) pos);
7316 if (size <= 32 && pos < 32)
7321 else if (size <= 32)
7331 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7338 /* Use unsigned arithmetic. */
7342 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7344 as_bad (_("Unsupported large constant"));
7349 pos = imm_expr.X_add_number;
7350 size = imm2_expr.X_add_number;
7355 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7358 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7360 as_bad (_("Improper insert size (%lu, position %lu)"),
7361 (unsigned long) size, (unsigned long) pos);
7365 if (pos < 32 && (pos + size - 1) < 32)
7380 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7381 (int) (pos + size - 1));
7397 as_warn (_("Divide by zero."));
7399 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7401 macro_build (NULL, "break", BRK_FMT, 7);
7408 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7409 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7413 if (mips_opts.micromips)
7414 micromips_label_expr (&label_expr);
7416 label_expr.X_add_number = 8;
7417 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7418 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7419 macro_build (NULL, "break", BRK_FMT, 7);
7420 if (mips_opts.micromips)
7421 micromips_add_label ();
7423 expr1.X_add_number = -1;
7425 load_register (AT, &expr1, dbl);
7426 if (mips_opts.micromips)
7427 micromips_label_expr (&label_expr);
7429 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7430 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7433 expr1.X_add_number = 1;
7434 load_register (AT, &expr1, dbl);
7435 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7439 expr1.X_add_number = 0x80000000;
7440 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7444 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7445 /* We want to close the noreorder block as soon as possible, so
7446 that later insns are available for delay slot filling. */
7451 if (mips_opts.micromips)
7452 micromips_label_expr (&label_expr);
7454 label_expr.X_add_number = 8;
7455 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7456 macro_build (NULL, "nop", "");
7458 /* We want to close the noreorder block as soon as possible, so
7459 that later insns are available for delay slot filling. */
7462 macro_build (NULL, "break", BRK_FMT, 6);
7464 if (mips_opts.micromips)
7465 micromips_add_label ();
7466 macro_build (NULL, s, MFHL_FMT, dreg);
7505 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7507 as_warn (_("Divide by zero."));
7509 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7511 macro_build (NULL, "break", BRK_FMT, 7);
7514 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7516 if (strcmp (s2, "mflo") == 0)
7517 move_register (dreg, sreg);
7519 move_register (dreg, ZERO);
7522 if (imm_expr.X_op == O_constant
7523 && imm_expr.X_add_number == -1
7524 && s[strlen (s) - 1] != 'u')
7526 if (strcmp (s2, "mflo") == 0)
7528 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7531 move_register (dreg, ZERO);
7536 load_register (AT, &imm_expr, dbl);
7537 macro_build (NULL, s, "z,s,t", sreg, AT);
7538 macro_build (NULL, s2, MFHL_FMT, dreg);
7560 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7561 macro_build (NULL, s, "z,s,t", sreg, treg);
7562 /* We want to close the noreorder block as soon as possible, so
7563 that later insns are available for delay slot filling. */
7568 if (mips_opts.micromips)
7569 micromips_label_expr (&label_expr);
7571 label_expr.X_add_number = 8;
7572 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7573 macro_build (NULL, s, "z,s,t", sreg, treg);
7575 /* We want to close the noreorder block as soon as possible, so
7576 that later insns are available for delay slot filling. */
7578 macro_build (NULL, "break", BRK_FMT, 7);
7579 if (mips_opts.micromips)
7580 micromips_add_label ();
7582 macro_build (NULL, s2, MFHL_FMT, dreg);
7594 /* Load the address of a symbol into a register. If breg is not
7595 zero, we then add a base register to it. */
7597 if (dbl && HAVE_32BIT_GPRS)
7598 as_warn (_("dla used to load 32-bit register"));
7600 if (!dbl && HAVE_64BIT_OBJECTS)
7601 as_warn (_("la used to load 64-bit address"));
7603 if (small_offset_p (0, align, 16))
7605 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg,
7606 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
7610 if (mips_opts.at && (treg == breg))
7620 if (offset_expr.X_op != O_symbol
7621 && offset_expr.X_op != O_constant)
7623 as_bad (_("Expression too complex"));
7624 offset_expr.X_op = O_constant;
7627 if (offset_expr.X_op == O_constant)
7628 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7629 else if (mips_pic == NO_PIC)
7631 /* If this is a reference to a GP relative symbol, we want
7632 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7634 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7635 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7636 If we have a constant, we need two instructions anyhow,
7637 so we may as well always use the latter form.
7639 With 64bit address space and a usable $at we want
7640 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7641 lui $at,<sym> (BFD_RELOC_HI16_S)
7642 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7643 daddiu $at,<sym> (BFD_RELOC_LO16)
7645 daddu $tempreg,$tempreg,$at
7647 If $at is already in use, we use a path which is suboptimal
7648 on superscalar processors.
7649 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7650 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7652 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7654 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7656 For GP relative symbols in 64bit address space we can use
7657 the same sequence as in 32bit address space. */
7658 if (HAVE_64BIT_SYMBOLS)
7660 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7661 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7663 relax_start (offset_expr.X_add_symbol);
7664 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7665 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7669 if (used_at == 0 && mips_opts.at)
7671 macro_build (&offset_expr, "lui", LUI_FMT,
7672 tempreg, BFD_RELOC_MIPS_HIGHEST);
7673 macro_build (&offset_expr, "lui", LUI_FMT,
7674 AT, BFD_RELOC_HI16_S);
7675 macro_build (&offset_expr, "daddiu", "t,r,j",
7676 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7677 macro_build (&offset_expr, "daddiu", "t,r,j",
7678 AT, AT, BFD_RELOC_LO16);
7679 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7680 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7685 macro_build (&offset_expr, "lui", LUI_FMT,
7686 tempreg, BFD_RELOC_MIPS_HIGHEST);
7687 macro_build (&offset_expr, "daddiu", "t,r,j",
7688 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7689 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7690 macro_build (&offset_expr, "daddiu", "t,r,j",
7691 tempreg, tempreg, BFD_RELOC_HI16_S);
7692 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7693 macro_build (&offset_expr, "daddiu", "t,r,j",
7694 tempreg, tempreg, BFD_RELOC_LO16);
7697 if (mips_relax.sequence)
7702 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7703 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7705 relax_start (offset_expr.X_add_symbol);
7706 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7707 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7710 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7711 as_bad (_("Offset too large"));
7712 macro_build_lui (&offset_expr, tempreg);
7713 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7714 tempreg, tempreg, BFD_RELOC_LO16);
7715 if (mips_relax.sequence)
7719 else if (!mips_big_got && !HAVE_NEWABI)
7721 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7723 /* If this is a reference to an external symbol, and there
7724 is no constant, we want
7725 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7726 or for lca or if tempreg is PIC_CALL_REG
7727 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7728 For a local symbol, we want
7729 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7731 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7733 If we have a small constant, and this is a reference to
7734 an external symbol, we want
7735 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7737 addiu $tempreg,$tempreg,<constant>
7738 For a local symbol, we want the same instruction
7739 sequence, but we output a BFD_RELOC_LO16 reloc on the
7742 If we have a large constant, and this is a reference to
7743 an external symbol, we want
7744 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7745 lui $at,<hiconstant>
7746 addiu $at,$at,<loconstant>
7747 addu $tempreg,$tempreg,$at
7748 For a local symbol, we want the same instruction
7749 sequence, but we output a BFD_RELOC_LO16 reloc on the
7753 if (offset_expr.X_add_number == 0)
7755 if (mips_pic == SVR4_PIC
7757 && (call || tempreg == PIC_CALL_REG))
7758 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7760 relax_start (offset_expr.X_add_symbol);
7761 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7762 lw_reloc_type, mips_gp_register);
7765 /* We're going to put in an addu instruction using
7766 tempreg, so we may as well insert the nop right
7771 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7772 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7774 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7775 tempreg, tempreg, BFD_RELOC_LO16);
7777 /* FIXME: If breg == 0, and the next instruction uses
7778 $tempreg, then if this variant case is used an extra
7779 nop will be generated. */
7781 else if (offset_expr.X_add_number >= -0x8000
7782 && offset_expr.X_add_number < 0x8000)
7784 load_got_offset (tempreg, &offset_expr);
7786 add_got_offset (tempreg, &offset_expr);
7790 expr1.X_add_number = offset_expr.X_add_number;
7791 offset_expr.X_add_number =
7792 SEXT_16BIT (offset_expr.X_add_number);
7793 load_got_offset (tempreg, &offset_expr);
7794 offset_expr.X_add_number = expr1.X_add_number;
7795 /* If we are going to add in a base register, and the
7796 target register and the base register are the same,
7797 then we are using AT as a temporary register. Since
7798 we want to load the constant into AT, we add our
7799 current AT (from the global offset table) and the
7800 register into the register now, and pretend we were
7801 not using a base register. */
7805 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7810 add_got_offset_hilo (tempreg, &offset_expr, AT);
7814 else if (!mips_big_got && HAVE_NEWABI)
7816 int add_breg_early = 0;
7818 /* If this is a reference to an external, and there is no
7819 constant, or local symbol (*), with or without a
7821 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7822 or for lca or if tempreg is PIC_CALL_REG
7823 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7825 If we have a small constant, and this is a reference to
7826 an external symbol, we want
7827 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7828 addiu $tempreg,$tempreg,<constant>
7830 If we have a large constant, and this is a reference to
7831 an external symbol, we want
7832 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7833 lui $at,<hiconstant>
7834 addiu $at,$at,<loconstant>
7835 addu $tempreg,$tempreg,$at
7837 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7838 local symbols, even though it introduces an additional
7841 if (offset_expr.X_add_number)
7843 expr1.X_add_number = offset_expr.X_add_number;
7844 offset_expr.X_add_number = 0;
7846 relax_start (offset_expr.X_add_symbol);
7847 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7848 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7850 if (expr1.X_add_number >= -0x8000
7851 && expr1.X_add_number < 0x8000)
7853 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7854 tempreg, tempreg, BFD_RELOC_LO16);
7856 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7858 /* If we are going to add in a base register, and the
7859 target register and the base register are the same,
7860 then we are using AT as a temporary register. Since
7861 we want to load the constant into AT, we add our
7862 current AT (from the global offset table) and the
7863 register into the register now, and pretend we were
7864 not using a base register. */
7869 gas_assert (tempreg == AT);
7870 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7876 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7877 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7883 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7886 offset_expr.X_add_number = expr1.X_add_number;
7888 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7889 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7892 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7893 treg, tempreg, breg);
7899 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7901 relax_start (offset_expr.X_add_symbol);
7902 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7903 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7905 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7906 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7911 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7912 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7915 else if (mips_big_got && !HAVE_NEWABI)
7918 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7919 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7920 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7922 /* This is the large GOT case. If this is a reference to an
7923 external symbol, and there is no constant, we want
7924 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7925 addu $tempreg,$tempreg,$gp
7926 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7927 or for lca or if tempreg is PIC_CALL_REG
7928 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7929 addu $tempreg,$tempreg,$gp
7930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7931 For a local symbol, we want
7932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7936 If we have a small constant, and this is a reference to
7937 an external symbol, we want
7938 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7939 addu $tempreg,$tempreg,$gp
7940 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7942 addiu $tempreg,$tempreg,<constant>
7943 For a local symbol, we want
7944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7946 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7948 If we have a large constant, and this is a reference to
7949 an external symbol, we want
7950 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7951 addu $tempreg,$tempreg,$gp
7952 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7953 lui $at,<hiconstant>
7954 addiu $at,$at,<loconstant>
7955 addu $tempreg,$tempreg,$at
7956 For a local symbol, we want
7957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7958 lui $at,<hiconstant>
7959 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7960 addu $tempreg,$tempreg,$at
7963 expr1.X_add_number = offset_expr.X_add_number;
7964 offset_expr.X_add_number = 0;
7965 relax_start (offset_expr.X_add_symbol);
7966 gpdelay = reg_needs_delay (mips_gp_register);
7967 if (expr1.X_add_number == 0 && breg == 0
7968 && (call || tempreg == PIC_CALL_REG))
7970 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7971 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7973 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7974 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7975 tempreg, tempreg, mips_gp_register);
7976 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7977 tempreg, lw_reloc_type, tempreg);
7978 if (expr1.X_add_number == 0)
7982 /* We're going to put in an addu instruction using
7983 tempreg, so we may as well insert the nop right
7988 else if (expr1.X_add_number >= -0x8000
7989 && expr1.X_add_number < 0x8000)
7992 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7993 tempreg, tempreg, BFD_RELOC_LO16);
7997 /* If we are going to add in a base register, and the
7998 target register and the base register are the same,
7999 then we are using AT as a temporary register. Since
8000 we want to load the constant into AT, we add our
8001 current AT (from the global offset table) and the
8002 register into the register now, and pretend we were
8003 not using a base register. */
8008 gas_assert (tempreg == AT);
8010 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8015 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8016 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8020 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
8025 /* This is needed because this instruction uses $gp, but
8026 the first instruction on the main stream does not. */
8027 macro_build (NULL, "nop", "");
8030 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8031 local_reloc_type, mips_gp_register);
8032 if (expr1.X_add_number >= -0x8000
8033 && expr1.X_add_number < 0x8000)
8036 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8037 tempreg, tempreg, BFD_RELOC_LO16);
8038 /* FIXME: If add_number is 0, and there was no base
8039 register, the external symbol case ended with a load,
8040 so if the symbol turns out to not be external, and
8041 the next instruction uses tempreg, an unnecessary nop
8042 will be inserted. */
8048 /* We must add in the base register now, as in the
8049 external symbol case. */
8050 gas_assert (tempreg == AT);
8052 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8055 /* We set breg to 0 because we have arranged to add
8056 it in in both cases. */
8060 macro_build_lui (&expr1, AT);
8061 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8062 AT, AT, BFD_RELOC_LO16);
8063 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8064 tempreg, tempreg, AT);
8069 else if (mips_big_got && HAVE_NEWABI)
8071 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
8072 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
8073 int add_breg_early = 0;
8075 /* This is the large GOT case. If this is a reference to an
8076 external symbol, and there is no constant, we want
8077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8078 add $tempreg,$tempreg,$gp
8079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8080 or for lca or if tempreg is PIC_CALL_REG
8081 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8082 add $tempreg,$tempreg,$gp
8083 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8085 If we have a small constant, and this is a reference to
8086 an external symbol, we want
8087 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8088 add $tempreg,$tempreg,$gp
8089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8090 addi $tempreg,$tempreg,<constant>
8092 If we have a large constant, and this is a reference to
8093 an external symbol, we want
8094 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8095 addu $tempreg,$tempreg,$gp
8096 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8097 lui $at,<hiconstant>
8098 addi $at,$at,<loconstant>
8099 add $tempreg,$tempreg,$at
8101 If we have NewABI, and we know it's a local symbol, we want
8102 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8103 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8104 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8106 relax_start (offset_expr.X_add_symbol);
8108 expr1.X_add_number = offset_expr.X_add_number;
8109 offset_expr.X_add_number = 0;
8111 if (expr1.X_add_number == 0 && breg == 0
8112 && (call || tempreg == PIC_CALL_REG))
8114 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8115 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8117 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8119 tempreg, tempreg, mips_gp_register);
8120 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8121 tempreg, lw_reloc_type, tempreg);
8123 if (expr1.X_add_number == 0)
8125 else if (expr1.X_add_number >= -0x8000
8126 && expr1.X_add_number < 0x8000)
8128 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8129 tempreg, tempreg, BFD_RELOC_LO16);
8131 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8133 /* If we are going to add in a base register, and the
8134 target register and the base register are the same,
8135 then we are using AT as a temporary register. Since
8136 we want to load the constant into AT, we add our
8137 current AT (from the global offset table) and the
8138 register into the register now, and pretend we were
8139 not using a base register. */
8144 gas_assert (tempreg == AT);
8145 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8151 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8157 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8160 offset_expr.X_add_number = expr1.X_add_number;
8161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8162 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8163 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8164 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8167 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8168 treg, tempreg, breg);
8178 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8182 gas_assert (!mips_opts.micromips);
8183 macro_build (NULL, "c2", "C", (treg << 16) | 0x01);
8187 gas_assert (!mips_opts.micromips);
8188 macro_build (NULL, "c2", "C", 0x02);
8192 gas_assert (!mips_opts.micromips);
8193 macro_build (NULL, "c2", "C", (treg << 16) | 0x02);
8197 gas_assert (!mips_opts.micromips);
8198 macro_build (NULL, "c2", "C", 3);
8202 gas_assert (!mips_opts.micromips);
8203 macro_build (NULL, "c2", "C", (treg << 16) | 0x03);
8207 /* The j instruction may not be used in PIC code, since it
8208 requires an absolute address. We convert it to a b
8210 if (mips_pic == NO_PIC)
8211 macro_build (&offset_expr, "j", "a");
8213 macro_build (&offset_expr, "b", "p");
8216 /* The jal instructions must be handled as macros because when
8217 generating PIC code they expand to multi-instruction
8218 sequences. Normally they are simple instructions. */
8223 gas_assert (mips_opts.micromips);
8224 if (mips_opts.insn32)
8226 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8236 if (mips_pic == NO_PIC)
8238 s = jals ? "jalrs" : "jalr";
8239 if (mips_opts.micromips
8240 && !mips_opts.insn32
8242 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8243 macro_build (NULL, s, "mj", sreg);
8245 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8249 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8250 && mips_cprestore_offset >= 0);
8252 if (sreg != PIC_CALL_REG)
8253 as_warn (_("MIPS PIC call to register other than $25"));
8255 s = ((mips_opts.micromips
8256 && !mips_opts.insn32
8257 && (!mips_opts.noreorder || cprestore))
8258 ? "jalrs" : "jalr");
8259 if (mips_opts.micromips
8260 && !mips_opts.insn32
8262 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8263 macro_build (NULL, s, "mj", sreg);
8265 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8266 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8268 if (mips_cprestore_offset < 0)
8269 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8272 if (!mips_frame_reg_valid)
8274 as_warn (_("No .frame pseudo-op used in PIC code"));
8275 /* Quiet this warning. */
8276 mips_frame_reg_valid = 1;
8278 if (!mips_cprestore_valid)
8280 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8281 /* Quiet this warning. */
8282 mips_cprestore_valid = 1;
8284 if (mips_opts.noreorder)
8285 macro_build (NULL, "nop", "");
8286 expr1.X_add_number = mips_cprestore_offset;
8287 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8290 HAVE_64BIT_ADDRESSES);
8298 gas_assert (mips_opts.micromips);
8299 if (mips_opts.insn32)
8301 as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
8307 if (mips_pic == NO_PIC)
8308 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8309 else if (mips_pic == SVR4_PIC)
8311 /* If this is a reference to an external symbol, and we are
8312 using a small GOT, we want
8313 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8317 lw $gp,cprestore($sp)
8318 The cprestore value is set using the .cprestore
8319 pseudo-op. If we are using a big GOT, we want
8320 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8322 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8326 lw $gp,cprestore($sp)
8327 If the symbol is not external, we want
8328 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8330 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8333 lw $gp,cprestore($sp)
8335 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8336 sequences above, minus nops, unless the symbol is local,
8337 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8343 relax_start (offset_expr.X_add_symbol);
8344 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8345 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8348 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8349 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8355 relax_start (offset_expr.X_add_symbol);
8356 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8357 BFD_RELOC_MIPS_CALL_HI16);
8358 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8359 PIC_CALL_REG, mips_gp_register);
8360 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8361 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8364 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8365 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8367 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8368 PIC_CALL_REG, PIC_CALL_REG,
8369 BFD_RELOC_MIPS_GOT_OFST);
8373 macro_build_jalr (&offset_expr, 0);
8377 relax_start (offset_expr.X_add_symbol);
8380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8381 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8390 gpdelay = reg_needs_delay (mips_gp_register);
8391 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8392 BFD_RELOC_MIPS_CALL_HI16);
8393 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8394 PIC_CALL_REG, mips_gp_register);
8395 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8396 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8401 macro_build (NULL, "nop", "");
8403 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8404 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8407 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8408 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8410 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8412 if (mips_cprestore_offset < 0)
8413 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8416 if (!mips_frame_reg_valid)
8418 as_warn (_("No .frame pseudo-op used in PIC code"));
8419 /* Quiet this warning. */
8420 mips_frame_reg_valid = 1;
8422 if (!mips_cprestore_valid)
8424 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8425 /* Quiet this warning. */
8426 mips_cprestore_valid = 1;
8428 if (mips_opts.noreorder)
8429 macro_build (NULL, "nop", "");
8430 expr1.X_add_number = mips_cprestore_offset;
8431 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8434 HAVE_64BIT_ADDRESSES);
8438 else if (mips_pic == VXWORKS_PIC)
8439 as_bad (_("Non-PIC jump used in PIC library"));
8517 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8523 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8548 gas_assert (!mips_opts.micromips);
8551 /* Itbl support may require additional care here. */
8557 /* Itbl support may require additional care here. */
8563 offbits = (mips_opts.micromips ? 12 : 16);
8564 /* Itbl support may require additional care here. */
8568 gas_assert (!mips_opts.micromips);
8571 /* Itbl support may require additional care here. */
8577 offbits = (mips_opts.micromips ? 12 : 16);
8582 offbits = (mips_opts.micromips ? 12 : 16);
8587 /* Itbl support may require additional care here. */
8593 offbits = (mips_opts.micromips ? 12 : 16);
8594 /* Itbl support may require additional care here. */
8600 /* Itbl support may require additional care here. */
8606 /* Itbl support may require additional care here. */
8612 offbits = (mips_opts.micromips ? 12 : 16);
8617 offbits = (mips_opts.micromips ? 12 : 16);
8622 offbits = (mips_opts.micromips ? 12 : 16);
8627 offbits = (mips_opts.micromips ? 12 : 16);
8632 offbits = (mips_opts.micromips ? 12 : 16);
8635 gas_assert (mips_opts.micromips);
8642 gas_assert (mips_opts.micromips);
8649 gas_assert (mips_opts.micromips);
8655 gas_assert (mips_opts.micromips);
8662 /* We don't want to use $0 as tempreg. */
8663 if (breg == treg + lp || treg + lp == ZERO)
8666 tempreg = treg + lp;
8682 gas_assert (!mips_opts.micromips);
8685 /* Itbl support may require additional care here. */
8691 /* Itbl support may require additional care here. */
8697 offbits = (mips_opts.micromips ? 12 : 16);
8698 /* Itbl support may require additional care here. */
8702 gas_assert (!mips_opts.micromips);
8705 /* Itbl support may require additional care here. */
8711 offbits = (mips_opts.micromips ? 12 : 16);
8716 offbits = (mips_opts.micromips ? 12 : 16);
8721 offbits = (mips_opts.micromips ? 12 : 16);
8726 offbits = (mips_opts.micromips ? 12 : 16);
8730 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8731 offbits = (mips_opts.micromips ? 12 : 16);
8740 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8741 offbits = (mips_opts.micromips ? 12 : 16);
8752 /* Itbl support may require additional care here. */
8757 offbits = (mips_opts.micromips ? 12 : 16);
8758 /* Itbl support may require additional care here. */
8764 /* Itbl support may require additional care here. */
8768 gas_assert (!mips_opts.micromips);
8771 /* Itbl support may require additional care here. */
8777 offbits = (mips_opts.micromips ? 12 : 16);
8782 offbits = (mips_opts.micromips ? 12 : 16);
8785 gas_assert (mips_opts.micromips);
8791 gas_assert (mips_opts.micromips);
8797 gas_assert (mips_opts.micromips);
8803 gas_assert (mips_opts.micromips);
8811 if (small_offset_p (0, align, 16))
8813 /* The first case exists for M_LD_AB and M_SD_AB, which are
8814 macros for o32 but which should act like normal instructions
8817 macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0],
8818 offset_reloc[1], offset_reloc[2], breg);
8819 else if (small_offset_p (0, align, offbits))
8822 macro_build (NULL, s, fmt, treg, breg);
8824 macro_build (NULL, s, fmt, treg,
8825 (int) offset_expr.X_add_number, breg);
8831 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8832 tempreg, breg, -1, offset_reloc[0],
8833 offset_reloc[1], offset_reloc[2]);
8835 macro_build (NULL, s, fmt, treg, tempreg);
8837 macro_build (NULL, s, fmt, treg, 0, tempreg);
8845 if (offset_expr.X_op != O_constant
8846 && offset_expr.X_op != O_symbol)
8848 as_bad (_("Expression too complex"));
8849 offset_expr.X_op = O_constant;
8852 if (HAVE_32BIT_ADDRESSES
8853 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8857 sprintf_vma (value, offset_expr.X_add_number);
8858 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8861 /* A constant expression in PIC code can be handled just as it
8862 is in non PIC code. */
8863 if (offset_expr.X_op == O_constant)
8865 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
8866 offbits == 0 ? 16 : offbits);
8867 offset_expr.X_add_number -= expr1.X_add_number;
8869 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8871 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8872 tempreg, tempreg, breg);
8875 if (offset_expr.X_add_number != 0)
8876 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8877 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
8878 macro_build (NULL, s, fmt, treg, tempreg);
8880 else if (offbits == 16)
8881 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
8883 macro_build (NULL, s, fmt, treg,
8884 (int) offset_expr.X_add_number, tempreg);
8886 else if (offbits != 16)
8888 /* The offset field is too narrow to be used for a low-part
8889 relocation, so load the whole address into the auxillary
8891 load_address (tempreg, &offset_expr, &used_at);
8893 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8894 tempreg, tempreg, breg);
8896 macro_build (NULL, s, fmt, treg, tempreg);
8898 macro_build (NULL, s, fmt, treg, 0, tempreg);
8900 else if (mips_pic == NO_PIC)
8902 /* If this is a reference to a GP relative symbol, and there
8903 is no base register, we want
8904 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8905 Otherwise, if there is no base register, we want
8906 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8907 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8908 If we have a constant, we need two instructions anyhow,
8909 so we always use the latter form.
8911 If we have a base register, and this is a reference to a
8912 GP relative symbol, we want
8913 addu $tempreg,$breg,$gp
8914 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8916 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8917 addu $tempreg,$tempreg,$breg
8918 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8919 With a constant we always use the latter case.
8921 With 64bit address space and no base register and $at usable,
8923 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8924 lui $at,<sym> (BFD_RELOC_HI16_S)
8925 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8928 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8929 If we have a base register, we want
8930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8931 lui $at,<sym> (BFD_RELOC_HI16_S)
8932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8936 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8938 Without $at we can't generate the optimal path for superscalar
8939 processors here since this would require two temporary registers.
8940 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8943 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8945 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8946 If we have a base register, we want
8947 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8948 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8950 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8952 daddu $tempreg,$tempreg,$breg
8953 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8955 For GP relative symbols in 64bit address space we can use
8956 the same sequence as in 32bit address space. */
8957 if (HAVE_64BIT_SYMBOLS)
8959 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8960 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8962 relax_start (offset_expr.X_add_symbol);
8965 macro_build (&offset_expr, s, fmt, treg,
8966 BFD_RELOC_GPREL16, mips_gp_register);
8970 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8971 tempreg, breg, mips_gp_register);
8972 macro_build (&offset_expr, s, fmt, treg,
8973 BFD_RELOC_GPREL16, tempreg);
8978 if (used_at == 0 && mips_opts.at)
8980 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8981 BFD_RELOC_MIPS_HIGHEST);
8982 macro_build (&offset_expr, "lui", LUI_FMT, AT,
8984 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8985 tempreg, BFD_RELOC_MIPS_HIGHER);
8987 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
8988 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
8989 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
8990 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
8996 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
8997 BFD_RELOC_MIPS_HIGHEST);
8998 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
8999 tempreg, BFD_RELOC_MIPS_HIGHER);
9000 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9001 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9002 tempreg, BFD_RELOC_HI16_S);
9003 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9005 macro_build (NULL, "daddu", "d,v,t",
9006 tempreg, tempreg, breg);
9007 macro_build (&offset_expr, s, fmt, treg,
9008 BFD_RELOC_LO16, tempreg);
9011 if (mips_relax.sequence)
9018 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9019 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9021 relax_start (offset_expr.X_add_symbol);
9022 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9026 macro_build_lui (&offset_expr, tempreg);
9027 macro_build (&offset_expr, s, fmt, treg,
9028 BFD_RELOC_LO16, tempreg);
9029 if (mips_relax.sequence)
9034 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9035 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9037 relax_start (offset_expr.X_add_symbol);
9038 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9039 tempreg, breg, mips_gp_register);
9040 macro_build (&offset_expr, s, fmt, treg,
9041 BFD_RELOC_GPREL16, tempreg);
9044 macro_build_lui (&offset_expr, tempreg);
9045 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9046 tempreg, tempreg, breg);
9047 macro_build (&offset_expr, s, fmt, treg,
9048 BFD_RELOC_LO16, tempreg);
9049 if (mips_relax.sequence)
9053 else if (!mips_big_got)
9055 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9057 /* If this is a reference to an external symbol, we want
9058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9060 <op> $treg,0($tempreg)
9062 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9064 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9065 <op> $treg,0($tempreg)
9068 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9069 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9071 If there is a base register, we add it to $tempreg before
9072 the <op>. If there is a constant, we stick it in the
9073 <op> instruction. We don't handle constants larger than
9074 16 bits, because we have no way to load the upper 16 bits
9075 (actually, we could handle them for the subset of cases
9076 in which we are not using $at). */
9077 gas_assert (offset_expr.X_op == O_symbol);
9080 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9081 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9084 tempreg, tempreg, breg);
9085 macro_build (&offset_expr, s, fmt, treg,
9086 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9089 expr1.X_add_number = offset_expr.X_add_number;
9090 offset_expr.X_add_number = 0;
9091 if (expr1.X_add_number < -0x8000
9092 || expr1.X_add_number >= 0x8000)
9093 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9094 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9095 lw_reloc_type, mips_gp_register);
9097 relax_start (offset_expr.X_add_symbol);
9099 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9100 tempreg, BFD_RELOC_LO16);
9103 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9104 tempreg, tempreg, breg);
9105 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9107 else if (mips_big_got && !HAVE_NEWABI)
9111 /* If this is a reference to an external symbol, we want
9112 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9113 addu $tempreg,$tempreg,$gp
9114 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9115 <op> $treg,0($tempreg)
9117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9119 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9120 <op> $treg,0($tempreg)
9121 If there is a base register, we add it to $tempreg before
9122 the <op>. If there is a constant, we stick it in the
9123 <op> instruction. We don't handle constants larger than
9124 16 bits, because we have no way to load the upper 16 bits
9125 (actually, we could handle them for the subset of cases
9126 in which we are not using $at). */
9127 gas_assert (offset_expr.X_op == O_symbol);
9128 expr1.X_add_number = offset_expr.X_add_number;
9129 offset_expr.X_add_number = 0;
9130 if (expr1.X_add_number < -0x8000
9131 || expr1.X_add_number >= 0x8000)
9132 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9133 gpdelay = reg_needs_delay (mips_gp_register);
9134 relax_start (offset_expr.X_add_symbol);
9135 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9136 BFD_RELOC_MIPS_GOT_HI16);
9137 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9139 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9140 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9143 macro_build (NULL, "nop", "");
9144 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9145 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9147 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9148 tempreg, BFD_RELOC_LO16);
9152 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9153 tempreg, tempreg, breg);
9154 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9156 else if (mips_big_got && HAVE_NEWABI)
9158 /* If this is a reference to an external symbol, we want
9159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9160 add $tempreg,$tempreg,$gp
9161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9162 <op> $treg,<ofst>($tempreg)
9163 Otherwise, for local symbols, we want:
9164 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9165 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9166 gas_assert (offset_expr.X_op == O_symbol);
9167 expr1.X_add_number = offset_expr.X_add_number;
9168 offset_expr.X_add_number = 0;
9169 if (expr1.X_add_number < -0x8000
9170 || expr1.X_add_number >= 0x8000)
9171 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9172 relax_start (offset_expr.X_add_symbol);
9173 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9174 BFD_RELOC_MIPS_GOT_HI16);
9175 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9177 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9178 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9180 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9181 tempreg, tempreg, breg);
9182 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9185 offset_expr.X_add_number = expr1.X_add_number;
9186 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9187 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9189 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9190 tempreg, tempreg, breg);
9191 macro_build (&offset_expr, s, fmt, treg,
9192 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9201 gas_assert (mips_opts.micromips);
9202 gas_assert (mips_opts.insn32);
9204 macro_build (NULL, "jr", "s", RA);
9205 expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2;
9206 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
9211 gas_assert (mips_opts.micromips);
9212 gas_assert (mips_opts.insn32);
9213 macro_build (NULL, "jr", "s", sreg);
9214 if (mips_opts.noreorder)
9215 macro_build (NULL, "nop", "");
9220 load_register (treg, &imm_expr, 0);
9224 load_register (treg, &imm_expr, 1);
9228 if (imm_expr.X_op == O_constant)
9231 load_register (AT, &imm_expr, 0);
9232 macro_build (NULL, "mtc1", "t,G", AT, treg);
9237 gas_assert (offset_expr.X_op == O_symbol
9238 && strcmp (segment_name (S_GET_SEGMENT
9239 (offset_expr.X_add_symbol)),
9241 && offset_expr.X_add_number == 0);
9242 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9243 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9248 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9249 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9250 order 32 bits of the value and the low order 32 bits are either
9251 zero or in OFFSET_EXPR. */
9252 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9254 if (HAVE_64BIT_GPRS)
9255 load_register (treg, &imm_expr, 1);
9260 if (target_big_endian)
9272 load_register (hreg, &imm_expr, 0);
9275 if (offset_expr.X_op == O_absent)
9276 move_register (lreg, 0);
9279 gas_assert (offset_expr.X_op == O_constant);
9280 load_register (lreg, &offset_expr, 0);
9287 /* We know that sym is in the .rdata section. First we get the
9288 upper 16 bits of the address. */
9289 if (mips_pic == NO_PIC)
9291 macro_build_lui (&offset_expr, AT);
9296 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9297 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9301 /* Now we load the register(s). */
9302 if (HAVE_64BIT_GPRS)
9305 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9310 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9313 /* FIXME: How in the world do we deal with the possible
9315 offset_expr.X_add_number += 4;
9316 macro_build (&offset_expr, "lw", "t,o(b)",
9317 treg + 1, BFD_RELOC_LO16, AT);
9323 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9324 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9325 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9326 the value and the low order 32 bits are either zero or in
9328 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9331 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9332 if (HAVE_64BIT_FPRS)
9334 gas_assert (HAVE_64BIT_GPRS);
9335 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9339 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9340 if (offset_expr.X_op == O_absent)
9341 macro_build (NULL, "mtc1", "t,G", 0, treg);
9344 gas_assert (offset_expr.X_op == O_constant);
9345 load_register (AT, &offset_expr, 0);
9346 macro_build (NULL, "mtc1", "t,G", AT, treg);
9352 gas_assert (offset_expr.X_op == O_symbol
9353 && offset_expr.X_add_number == 0);
9354 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9355 if (strcmp (s, ".lit8") == 0)
9357 breg = mips_gp_register;
9358 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
9359 offset_reloc[1] = BFD_RELOC_UNUSED;
9360 offset_reloc[2] = BFD_RELOC_UNUSED;
9364 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9366 if (mips_pic != NO_PIC)
9367 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9368 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9371 /* FIXME: This won't work for a 64 bit address. */
9372 macro_build_lui (&offset_expr, AT);
9376 offset_reloc[0] = BFD_RELOC_LO16;
9377 offset_reloc[1] = BFD_RELOC_UNUSED;
9378 offset_reloc[2] = BFD_RELOC_UNUSED;
9385 * The MIPS assembler seems to check for X_add_number not
9386 * being double aligned and generating:
9389 * addiu at,at,%lo(foo+1)
9392 * But, the resulting address is the same after relocation so why
9393 * generate the extra instruction?
9395 /* Itbl support may require additional care here. */
9398 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9407 gas_assert (!mips_opts.micromips);
9408 /* Itbl support may require additional care here. */
9411 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9431 if (HAVE_64BIT_GPRS)
9441 if (HAVE_64BIT_GPRS)
9449 /* Even on a big endian machine $fn comes before $fn+1. We have
9450 to adjust when loading from memory. We set coproc if we must
9451 load $fn+1 first. */
9452 /* Itbl support may require additional care here. */
9453 if (!target_big_endian)
9456 if (small_offset_p (0, align, 16))
9459 if (!small_offset_p (4, align, 16))
9461 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
9462 -1, offset_reloc[0], offset_reloc[1],
9464 expr1.X_add_number = 0;
9468 offset_reloc[0] = BFD_RELOC_LO16;
9469 offset_reloc[1] = BFD_RELOC_UNUSED;
9470 offset_reloc[2] = BFD_RELOC_UNUSED;
9472 if (strcmp (s, "lw") == 0 && treg == breg)
9474 ep->X_add_number += 4;
9475 macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0],
9476 offset_reloc[1], offset_reloc[2], breg);
9477 ep->X_add_number -= 4;
9478 macro_build (ep, s, fmt, treg, -1, offset_reloc[0],
9479 offset_reloc[1], offset_reloc[2], breg);
9483 macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1,
9484 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9486 ep->X_add_number += 4;
9487 macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1,
9488 offset_reloc[0], offset_reloc[1], offset_reloc[2],
9494 if (offset_expr.X_op != O_symbol
9495 && offset_expr.X_op != O_constant)
9497 as_bad (_("Expression too complex"));
9498 offset_expr.X_op = O_constant;
9501 if (HAVE_32BIT_ADDRESSES
9502 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9506 sprintf_vma (value, offset_expr.X_add_number);
9507 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9510 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9512 /* If this is a reference to a GP relative symbol, we want
9513 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9514 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9515 If we have a base register, we use this
9517 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9518 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9519 If this is not a GP relative symbol, we want
9520 lui $at,<sym> (BFD_RELOC_HI16_S)
9521 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9522 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9523 If there is a base register, we add it to $at after the
9524 lui instruction. If there is a constant, we always use
9526 if (offset_expr.X_op == O_symbol
9527 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9528 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9530 relax_start (offset_expr.X_add_symbol);
9533 tempreg = mips_gp_register;
9537 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9538 AT, breg, mips_gp_register);
9543 /* Itbl support may require additional care here. */
9544 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9545 BFD_RELOC_GPREL16, tempreg);
9546 offset_expr.X_add_number += 4;
9548 /* Set mips_optimize to 2 to avoid inserting an
9550 hold_mips_optimize = mips_optimize;
9552 /* Itbl support may require additional care here. */
9553 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9554 BFD_RELOC_GPREL16, tempreg);
9555 mips_optimize = hold_mips_optimize;
9559 offset_expr.X_add_number -= 4;
9562 if (offset_high_part (offset_expr.X_add_number, 16)
9563 != offset_high_part (offset_expr.X_add_number + 4, 16))
9565 load_address (AT, &offset_expr, &used_at);
9566 offset_expr.X_op = O_constant;
9567 offset_expr.X_add_number = 0;
9570 macro_build_lui (&offset_expr, AT);
9572 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9573 /* Itbl support may require additional care here. */
9574 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9575 BFD_RELOC_LO16, AT);
9576 /* FIXME: How do we handle overflow here? */
9577 offset_expr.X_add_number += 4;
9578 /* Itbl support may require additional care here. */
9579 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9580 BFD_RELOC_LO16, AT);
9581 if (mips_relax.sequence)
9584 else if (!mips_big_got)
9586 /* If this is a reference to an external symbol, we want
9587 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9592 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9594 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9595 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9596 If there is a base register we add it to $at before the
9597 lwc1 instructions. If there is a constant we include it
9598 in the lwc1 instructions. */
9600 expr1.X_add_number = offset_expr.X_add_number;
9601 if (expr1.X_add_number < -0x8000
9602 || expr1.X_add_number >= 0x8000 - 4)
9603 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9604 load_got_offset (AT, &offset_expr);
9607 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9609 /* Set mips_optimize to 2 to avoid inserting an undesired
9611 hold_mips_optimize = mips_optimize;
9614 /* Itbl support may require additional care here. */
9615 relax_start (offset_expr.X_add_symbol);
9616 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9617 BFD_RELOC_LO16, AT);
9618 expr1.X_add_number += 4;
9619 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9620 BFD_RELOC_LO16, AT);
9622 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9623 BFD_RELOC_LO16, AT);
9624 offset_expr.X_add_number += 4;
9625 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9626 BFD_RELOC_LO16, AT);
9629 mips_optimize = hold_mips_optimize;
9631 else if (mips_big_got)
9635 /* If this is a reference to an external symbol, we want
9636 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9638 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9643 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9645 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9646 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9647 If there is a base register we add it to $at before the
9648 lwc1 instructions. If there is a constant we include it
9649 in the lwc1 instructions. */
9651 expr1.X_add_number = offset_expr.X_add_number;
9652 offset_expr.X_add_number = 0;
9653 if (expr1.X_add_number < -0x8000
9654 || expr1.X_add_number >= 0x8000 - 4)
9655 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9656 gpdelay = reg_needs_delay (mips_gp_register);
9657 relax_start (offset_expr.X_add_symbol);
9658 macro_build (&offset_expr, "lui", LUI_FMT,
9659 AT, BFD_RELOC_MIPS_GOT_HI16);
9660 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9661 AT, AT, mips_gp_register);
9662 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9663 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9666 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9667 /* Itbl support may require additional care here. */
9668 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9669 BFD_RELOC_LO16, AT);
9670 expr1.X_add_number += 4;
9672 /* Set mips_optimize to 2 to avoid inserting an undesired
9674 hold_mips_optimize = mips_optimize;
9676 /* Itbl support may require additional care here. */
9677 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9678 BFD_RELOC_LO16, AT);
9679 mips_optimize = hold_mips_optimize;
9680 expr1.X_add_number -= 4;
9683 offset_expr.X_add_number = expr1.X_add_number;
9685 macro_build (NULL, "nop", "");
9686 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9687 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9690 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9691 /* Itbl support may require additional care here. */
9692 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9693 BFD_RELOC_LO16, AT);
9694 offset_expr.X_add_number += 4;
9696 /* Set mips_optimize to 2 to avoid inserting an undesired
9698 hold_mips_optimize = mips_optimize;
9700 /* Itbl support may require additional care here. */
9701 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9702 BFD_RELOC_LO16, AT);
9703 mips_optimize = hold_mips_optimize;
9722 /* New code added to support COPZ instructions.
9723 This code builds table entries out of the macros in mip_opcodes.
9724 R4000 uses interlocks to handle coproc delays.
9725 Other chips (like the R3000) require nops to be inserted for delays.
9727 FIXME: Currently, we require that the user handle delays.
9728 In order to fill delay slots for non-interlocked chips,
9729 we must have a way to specify delays based on the coprocessor.
9730 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9731 What are the side-effects of the cop instruction?
9732 What cache support might we have and what are its effects?
9733 Both coprocessor & memory require delays. how long???
9734 What registers are read/set/modified?
9736 If an itbl is provided to interpret cop instructions,
9737 this knowledge can be encoded in the itbl spec. */
9751 gas_assert (!mips_opts.micromips);
9752 /* For now we just do C (same as Cz). The parameter will be
9753 stored in insn_opcode by mips_ip. */
9754 macro_build (NULL, s, "C", (int) ip->insn_opcode);
9758 move_register (dreg, sreg);
9762 gas_assert (mips_opts.micromips);
9763 gas_assert (mips_opts.insn32);
9764 dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
9765 breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
9766 sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
9767 treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
9768 move_register (dreg, sreg);
9769 move_register (breg, treg);
9775 if (mips_opts.arch == CPU_R5900)
9777 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9781 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9782 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9789 /* The MIPS assembler some times generates shifts and adds. I'm
9790 not trying to be that fancy. GCC should do this for us
9793 load_register (AT, &imm_expr, dbl);
9794 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9795 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9811 load_register (AT, &imm_expr, dbl);
9812 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9813 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9814 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9815 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9817 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9820 if (mips_opts.micromips)
9821 micromips_label_expr (&label_expr);
9823 label_expr.X_add_number = 8;
9824 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9825 macro_build (NULL, "nop", "");
9826 macro_build (NULL, "break", BRK_FMT, 6);
9827 if (mips_opts.micromips)
9828 micromips_add_label ();
9831 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9847 load_register (AT, &imm_expr, dbl);
9848 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9849 sreg, imm ? AT : treg);
9850 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9851 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9853 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9856 if (mips_opts.micromips)
9857 micromips_label_expr (&label_expr);
9859 label_expr.X_add_number = 8;
9860 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9861 macro_build (NULL, "nop", "");
9862 macro_build (NULL, "break", BRK_FMT, 6);
9863 if (mips_opts.micromips)
9864 micromips_add_label ();
9870 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9881 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9882 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9886 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9887 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9888 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9889 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9893 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9904 macro_build (NULL, "negu", "d,w", tempreg, treg);
9905 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9909 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9910 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9911 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9912 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9921 if (imm_expr.X_op != O_constant)
9922 as_bad (_("Improper rotate count"));
9923 rot = imm_expr.X_add_number & 0x3f;
9924 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9926 rot = (64 - rot) & 0x3f;
9928 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9930 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9935 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9938 l = (rot < 0x20) ? "dsll" : "dsll32";
9939 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9942 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9943 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9944 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9952 if (imm_expr.X_op != O_constant)
9953 as_bad (_("Improper rotate count"));
9954 rot = imm_expr.X_add_number & 0x1f;
9955 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9957 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9962 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9966 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9967 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9968 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9973 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9975 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9979 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9980 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9981 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9982 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9986 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9988 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
9992 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9993 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
9994 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
9995 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10004 if (imm_expr.X_op != O_constant)
10005 as_bad (_("Improper rotate count"));
10006 rot = imm_expr.X_add_number & 0x3f;
10007 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10010 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10012 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10017 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10020 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10021 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10024 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10025 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10026 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10034 if (imm_expr.X_op != O_constant)
10035 as_bad (_("Improper rotate count"));
10036 rot = imm_expr.X_add_number & 0x1f;
10037 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10039 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10044 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10048 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10049 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10050 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10056 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10057 else if (treg == 0)
10058 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10061 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10062 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10067 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10069 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10074 as_warn (_("Instruction %s: result is always false"),
10075 ip->insn_mo->name);
10076 move_register (dreg, 0);
10079 if (CPU_HAS_SEQ (mips_opts.arch)
10080 && -512 <= imm_expr.X_add_number
10081 && imm_expr.X_add_number < 512)
10083 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10084 (int) imm_expr.X_add_number);
10087 if (imm_expr.X_op == O_constant
10088 && imm_expr.X_add_number >= 0
10089 && imm_expr.X_add_number < 0x10000)
10091 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10093 else if (imm_expr.X_op == O_constant
10094 && imm_expr.X_add_number > -0x8000
10095 && imm_expr.X_add_number < 0)
10097 imm_expr.X_add_number = -imm_expr.X_add_number;
10098 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10099 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10101 else if (CPU_HAS_SEQ (mips_opts.arch))
10104 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10105 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10110 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10111 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10114 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10117 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10123 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10124 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10127 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10129 if (imm_expr.X_op == O_constant
10130 && imm_expr.X_add_number >= -0x8000
10131 && imm_expr.X_add_number < 0x8000)
10133 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10134 dreg, sreg, BFD_RELOC_LO16);
10138 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10139 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10143 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10146 case M_SGT: /* sreg > treg <==> treg < sreg */
10152 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10155 case M_SGT_I: /* sreg > I <==> I < sreg */
10162 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10163 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10166 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10172 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10173 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10176 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10183 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10184 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10185 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10189 if (imm_expr.X_op == O_constant
10190 && imm_expr.X_add_number >= -0x8000
10191 && imm_expr.X_add_number < 0x8000)
10193 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10197 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10198 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10202 if (imm_expr.X_op == O_constant
10203 && imm_expr.X_add_number >= -0x8000
10204 && imm_expr.X_add_number < 0x8000)
10206 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10211 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10212 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10217 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10218 else if (treg == 0)
10219 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10222 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10223 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10228 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10230 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10235 as_warn (_("Instruction %s: result is always true"),
10236 ip->insn_mo->name);
10237 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10238 dreg, 0, BFD_RELOC_LO16);
10241 if (CPU_HAS_SEQ (mips_opts.arch)
10242 && -512 <= imm_expr.X_add_number
10243 && imm_expr.X_add_number < 512)
10245 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10246 (int) imm_expr.X_add_number);
10249 if (imm_expr.X_op == O_constant
10250 && imm_expr.X_add_number >= 0
10251 && imm_expr.X_add_number < 0x10000)
10253 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10255 else if (imm_expr.X_op == O_constant
10256 && imm_expr.X_add_number > -0x8000
10257 && imm_expr.X_add_number < 0)
10259 imm_expr.X_add_number = -imm_expr.X_add_number;
10260 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10261 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10263 else if (CPU_HAS_SEQ (mips_opts.arch))
10266 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10267 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10272 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10273 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10276 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10291 if (!mips_opts.micromips)
10293 if (imm_expr.X_op == O_constant
10294 && imm_expr.X_add_number > -0x200
10295 && imm_expr.X_add_number <= 0x200)
10297 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10306 if (imm_expr.X_op == O_constant
10307 && imm_expr.X_add_number > -0x8000
10308 && imm_expr.X_add_number <= 0x8000)
10310 imm_expr.X_add_number = -imm_expr.X_add_number;
10311 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10316 load_register (AT, &imm_expr, dbl);
10317 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10339 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10340 macro_build (NULL, s, "s,t", sreg, AT);
10345 gas_assert (!mips_opts.micromips);
10346 gas_assert (mips_opts.isa == ISA_MIPS1);
10348 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10349 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10352 * Is the double cfc1 instruction a bug in the mips assembler;
10353 * or is there a reason for it?
10355 start_noreorder ();
10356 macro_build (NULL, "cfc1", "t,G", treg, RA);
10357 macro_build (NULL, "cfc1", "t,G", treg, RA);
10358 macro_build (NULL, "nop", "");
10359 expr1.X_add_number = 3;
10360 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10361 expr1.X_add_number = 2;
10362 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10363 macro_build (NULL, "ctc1", "t,G", AT, RA);
10364 macro_build (NULL, "nop", "");
10365 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10367 macro_build (NULL, "ctc1", "t,G", treg, RA);
10368 macro_build (NULL, "nop", "");
10385 offbits = (mips_opts.micromips ? 12 : 16);
10391 offbits = (mips_opts.micromips ? 12 : 16);
10403 offbits = (mips_opts.micromips ? 12 : 16);
10410 offbits = (mips_opts.micromips ? 12 : 16);
10415 large_offset = !small_offset_p (off, align, offbits);
10417 expr1.X_add_number = 0;
10422 if (small_offset_p (0, align, 16))
10423 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
10424 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10427 load_address (tempreg, ep, &used_at);
10429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10430 tempreg, tempreg, breg);
10432 offset_reloc[0] = BFD_RELOC_LO16;
10433 offset_reloc[1] = BFD_RELOC_UNUSED;
10434 offset_reloc[2] = BFD_RELOC_UNUSED;
10439 else if (!ust && treg == breg)
10450 if (!target_big_endian)
10451 ep->X_add_number += off;
10453 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
10455 macro_build (ep, s, "t,o(b)", tempreg, -1,
10456 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10458 if (!target_big_endian)
10459 ep->X_add_number -= off;
10461 ep->X_add_number += off;
10463 macro_build (NULL, s2, "t,~(b)",
10464 tempreg, (int) ep->X_add_number, breg);
10466 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10467 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10469 /* If necessary, move the result in tempreg to the final destination. */
10470 if (!ust && treg != tempreg)
10472 /* Protect second load's delay slot. */
10474 move_register (treg, tempreg);
10480 if (target_big_endian == ust)
10481 ep->X_add_number += off;
10482 tempreg = ust || large_offset ? treg : AT;
10483 macro_build (ep, s, "t,o(b)", tempreg, -1,
10484 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10486 /* For halfword transfers we need a temporary register to shuffle
10487 bytes. Unfortunately for M_USH_A we have none available before
10488 the next store as AT holds the base address. We deal with this
10489 case by clobbering TREG and then restoring it as with ULH. */
10490 tempreg = ust == large_offset ? treg : AT;
10492 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10494 if (target_big_endian == ust)
10495 ep->X_add_number -= off;
10497 ep->X_add_number += off;
10498 macro_build (ep, s2, "t,o(b)", tempreg, -1,
10499 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
10501 /* For M_USH_A re-retrieve the LSB. */
10502 if (ust && large_offset)
10504 if (target_big_endian)
10505 ep->X_add_number += off;
10507 ep->X_add_number -= off;
10508 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
10509 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
10511 /* For ULH and M_USH_A OR the LSB in. */
10512 if (!ust || large_offset)
10514 tempreg = !large_offset ? AT : treg;
10515 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10516 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10521 /* FIXME: Check if this is one of the itbl macros, since they
10522 are added dynamically. */
10523 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10526 if (!mips_opts.at && used_at)
10527 as_bad (_("Macro used $at after \".set noat\""));
10530 /* Implement macros in mips16 mode. */
10533 mips16_macro (struct mips_cl_insn *ip)
10536 int xreg, yreg, zreg, tmp;
10539 const char *s, *s2, *s3;
10541 mask = ip->insn_mo->mask;
10543 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10544 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10545 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10547 expr1.X_op = O_constant;
10548 expr1.X_op_symbol = NULL;
10549 expr1.X_add_symbol = NULL;
10550 expr1.X_add_number = 1;
10569 start_noreorder ();
10570 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10571 expr1.X_add_number = 2;
10572 macro_build (&expr1, "bnez", "x,p", yreg);
10573 macro_build (NULL, "break", "6", 7);
10575 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10576 since that causes an overflow. We should do that as well,
10577 but I don't see how to do the comparisons without a temporary
10580 macro_build (NULL, s, "x", zreg);
10599 start_noreorder ();
10600 macro_build (NULL, s, "0,x,y", xreg, yreg);
10601 expr1.X_add_number = 2;
10602 macro_build (&expr1, "bnez", "x,p", yreg);
10603 macro_build (NULL, "break", "6", 7);
10605 macro_build (NULL, s2, "x", zreg);
10611 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10612 macro_build (NULL, "mflo", "x", zreg);
10620 if (imm_expr.X_op != O_constant)
10621 as_bad (_("Unsupported large constant"));
10622 imm_expr.X_add_number = -imm_expr.X_add_number;
10623 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10627 if (imm_expr.X_op != O_constant)
10628 as_bad (_("Unsupported large constant"));
10629 imm_expr.X_add_number = -imm_expr.X_add_number;
10630 macro_build (&imm_expr, "addiu", "x,k", xreg);
10634 if (imm_expr.X_op != O_constant)
10635 as_bad (_("Unsupported large constant"));
10636 imm_expr.X_add_number = -imm_expr.X_add_number;
10637 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10659 goto do_reverse_branch;
10663 goto do_reverse_branch;
10675 goto do_reverse_branch;
10686 macro_build (NULL, s, "x,y", xreg, yreg);
10687 macro_build (&offset_expr, s2, "p");
10714 goto do_addone_branch_i;
10719 goto do_addone_branch_i;
10734 goto do_addone_branch_i;
10740 do_addone_branch_i:
10741 if (imm_expr.X_op != O_constant)
10742 as_bad (_("Unsupported large constant"));
10743 ++imm_expr.X_add_number;
10746 macro_build (&imm_expr, s, s3, xreg);
10747 macro_build (&offset_expr, s2, "p");
10751 expr1.X_add_number = 0;
10752 macro_build (&expr1, "slti", "x,8", yreg);
10754 move_register (xreg, yreg);
10755 expr1.X_add_number = 2;
10756 macro_build (&expr1, "bteqz", "p");
10757 macro_build (NULL, "neg", "x,w", xreg, xreg);
10761 /* For consistency checking, verify that all bits are specified either
10762 by the match/mask part of the instruction definition, or by the
10765 validate_mips_insn (const struct mips_opcode *opc)
10767 const char *p = opc->args;
10769 unsigned long used_bits = opc->mask;
10771 if ((used_bits & opc->match) != opc->match)
10773 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10774 opc->name, opc->args);
10777 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10787 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10788 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10789 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10790 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10791 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10792 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10793 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10794 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10795 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10796 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10797 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10799 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10800 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10801 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10802 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10803 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10804 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10805 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10806 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10807 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10808 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10809 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10810 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10811 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10812 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10813 case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10814 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10817 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10818 c, opc->name, opc->args);
10822 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10823 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10825 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10826 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10827 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10828 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10830 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10831 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10833 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10834 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10836 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10837 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10838 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10839 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10840 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10841 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10842 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10843 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10844 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10845 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10846 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10847 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10848 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10849 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10850 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10851 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10852 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10854 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10855 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10856 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10857 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10859 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10860 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10861 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10862 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10863 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10864 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10865 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10866 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10867 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10870 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10871 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10872 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10873 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10874 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10875 case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break;
10876 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10877 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10878 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10879 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10880 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10881 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10882 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10883 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10884 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10885 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10886 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10887 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10888 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10889 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10890 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10891 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10892 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10893 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10894 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10896 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10897 c, opc->name, opc->args);
10901 if (used_bits != 0xffffffff)
10903 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10904 ~used_bits & 0xffffffff, opc->name, opc->args);
10910 /* For consistency checking, verify that the length implied matches the
10911 major opcode and that all bits are specified either by the match/mask
10912 part of the instruction definition, or by the operand list. */
10915 validate_micromips_insn (const struct mips_opcode *opc)
10917 unsigned long match = opc->match;
10918 unsigned long mask = opc->mask;
10919 const char *p = opc->args;
10920 unsigned long insn_bits;
10921 unsigned long used_bits;
10922 unsigned long major;
10923 unsigned int length;
10927 if ((mask & match) != match)
10929 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10930 opc->name, opc->args);
10933 length = micromips_insn_length (opc);
10934 if (length != 2 && length != 4)
10936 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10937 "%s %s"), length, opc->name, opc->args);
10940 major = match >> (10 + 8 * (length - 2));
10941 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10942 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10944 as_bad (_("Internal error: bad microMIPS opcode "
10945 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10949 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10950 insn_bits = 1 << 4 * length;
10951 insn_bits <<= 4 * length;
10954 #define USE_BITS(field) \
10955 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
10966 case 'A': USE_BITS (EXTLSB); break;
10967 case 'B': USE_BITS (INSMSB); break;
10968 case 'C': USE_BITS (EXTMSBD); break;
10969 case 'E': USE_BITS (EXTLSB); break;
10970 case 'F': USE_BITS (INSMSB); break;
10971 case 'G': USE_BITS (EXTMSBD); break;
10972 case 'H': USE_BITS (EXTMSBD); break;
10973 case 'i': USE_BITS (TARGET); break;
10974 case 'j': USE_BITS (EVAOFFSET); break;
10976 as_bad (_("Internal error: bad mips opcode "
10977 "(unknown extension operand type `%c%c'): %s %s"),
10978 e, c, opc->name, opc->args);
10986 case 'A': USE_BITS (IMMA); break;
10987 case 'B': USE_BITS (IMMB); break;
10988 case 'C': USE_BITS (IMMC); break;
10989 case 'D': USE_BITS (IMMD); break;
10990 case 'E': USE_BITS (IMME); break;
10991 case 'F': USE_BITS (IMMF); break;
10992 case 'G': USE_BITS (IMMG); break;
10993 case 'H': USE_BITS (IMMH); break;
10994 case 'I': USE_BITS (IMMI); break;
10995 case 'J': USE_BITS (IMMJ); break;
10996 case 'L': USE_BITS (IMML); break;
10997 case 'M': USE_BITS (IMMM); break;
10998 case 'N': USE_BITS (IMMN); break;
10999 case 'O': USE_BITS (IMMO); break;
11000 case 'P': USE_BITS (IMMP); break;
11001 case 'Q': USE_BITS (IMMQ); break;
11002 case 'U': USE_BITS (IMMU); break;
11003 case 'W': USE_BITS (IMMW); break;
11004 case 'X': USE_BITS (IMMX); break;
11005 case 'Y': USE_BITS (IMMY); break;
11008 case 'b': USE_BITS (MB); break;
11009 case 'c': USE_BITS (MC); break;
11010 case 'd': USE_BITS (MD); break;
11011 case 'e': USE_BITS (ME); break;
11012 case 'f': USE_BITS (MF); break;
11013 case 'g': USE_BITS (MG); break;
11014 case 'h': USE_BITS (MH); break;
11015 case 'j': USE_BITS (MJ); break;
11016 case 'l': USE_BITS (ML); break;
11017 case 'm': USE_BITS (MM); break;
11018 case 'n': USE_BITS (MN); break;
11019 case 'p': USE_BITS (MP); break;
11020 case 'q': USE_BITS (MQ); break;
11028 as_bad (_("Internal error: bad mips opcode "
11029 "(unknown extension operand type `%c%c'): %s %s"),
11030 e, c, opc->name, opc->args);
11034 case '.': USE_BITS (OFFSET10); break;
11035 case '1': USE_BITS (STYPE); break;
11036 case '2': USE_BITS (BP); break;
11037 case '3': USE_BITS (SA3); break;
11038 case '4': USE_BITS (SA4); break;
11039 case '5': USE_BITS (IMM8); break;
11040 case '6': USE_BITS (RS); break;
11041 case '7': USE_BITS (DSPACC); break;
11042 case '8': USE_BITS (WRDSP); break;
11043 case '0': USE_BITS (DSPSFT); break;
11044 case '<': USE_BITS (SHAMT); break;
11045 case '>': USE_BITS (SHAMT); break;
11046 case '@': USE_BITS (IMM10); break;
11047 case 'B': USE_BITS (CODE10); break;
11048 case 'C': USE_BITS (COPZ); break;
11049 case 'D': USE_BITS (FD); break;
11050 case 'E': USE_BITS (RT); break;
11051 case 'G': USE_BITS (RS); break;
11052 case 'H': USE_BITS (SEL); break;
11053 case 'K': USE_BITS (RS); break;
11054 case 'M': USE_BITS (CCC); break;
11055 case 'N': USE_BITS (BCC); break;
11056 case 'R': USE_BITS (FR); break;
11057 case 'S': USE_BITS (FS); break;
11058 case 'T': USE_BITS (FT); break;
11059 case 'V': USE_BITS (FS); break;
11060 case '\\': USE_BITS (3BITPOS); break;
11061 case '^': USE_BITS (RD); break;
11062 case 'a': USE_BITS (TARGET); break;
11063 case 'b': USE_BITS (RS); break;
11064 case 'c': USE_BITS (CODE); break;
11065 case 'd': USE_BITS (RD); break;
11066 case 'h': USE_BITS (PREFX); break;
11067 case 'i': USE_BITS (IMMEDIATE); break;
11068 case 'j': USE_BITS (DELTA); break;
11069 case 'k': USE_BITS (CACHE); break;
11070 case 'n': USE_BITS (RT); break;
11071 case 'o': USE_BITS (DELTA); break;
11072 case 'p': USE_BITS (DELTA); break;
11073 case 'q': USE_BITS (CODE2); break;
11074 case 'r': USE_BITS (RS); break;
11075 case 's': USE_BITS (RS); break;
11076 case 't': USE_BITS (RT); break;
11077 case 'u': USE_BITS (IMMEDIATE); break;
11078 case 'v': USE_BITS (RS); break;
11079 case 'w': USE_BITS (RT); break;
11080 case 'y': USE_BITS (RS3); break;
11082 case '|': USE_BITS (TRAP); break;
11083 case '~': USE_BITS (OFFSET12); break;
11085 as_bad (_("Internal error: bad microMIPS opcode "
11086 "(unknown operand type `%c'): %s %s"),
11087 c, opc->name, opc->args);
11091 if (used_bits != insn_bits)
11093 if (~used_bits & insn_bits)
11094 as_bad (_("Internal error: bad microMIPS opcode "
11095 "(bits 0x%lx undefined): %s %s"),
11096 ~used_bits & insn_bits, opc->name, opc->args);
11097 if (used_bits & ~insn_bits)
11098 as_bad (_("Internal error: bad microMIPS opcode "
11099 "(bits 0x%lx defined): %s %s"),
11100 used_bits & ~insn_bits, opc->name, opc->args);
11106 /* UDI immediates. */
11107 struct mips_immed {
11109 unsigned int shift;
11110 unsigned long mask;
11114 static const struct mips_immed mips_immed[] = {
11115 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11116 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11117 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11118 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11122 /* Check whether an odd floating-point register is allowed. */
11124 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11126 const char *s = insn->name;
11128 if (insn->pinfo == INSN_MACRO)
11129 /* Let a macro pass, we'll catch it later when it is expanded. */
11132 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11134 /* Allow odd registers for single-precision ops. */
11135 switch (insn->pinfo & (FP_S | FP_D))
11139 return 1; /* both single precision - ok */
11141 return 0; /* both double precision - fail */
11146 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11147 s = strchr (insn->name, '.');
11149 s = s != NULL ? strchr (s + 1, '.') : NULL;
11150 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11153 /* Single-precision coprocessor loads and moves are OK too. */
11154 if ((insn->pinfo & FP_S)
11155 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11156 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11162 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11163 taking bits from BIT up. */
11165 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11167 return (ep->X_op == O_constant
11168 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11169 && ep->X_add_number >= min << bit
11170 && ep->X_add_number < max << bit);
11173 /* Assemble an instruction into its binary format. If the instruction
11174 is a macro, set imm_expr, imm2_expr and offset_expr to the values
11175 associated with "I", "+I" and "A" operands respectively. Otherwise
11176 store the value of the relocatable field (if any) in offset_expr.
11177 In both cases set offset_reloc to the relocation operators applied
11181 mips_ip (char *str, struct mips_cl_insn *ip)
11183 bfd_boolean wrong_delay_slot_insns = FALSE;
11184 bfd_boolean need_delay_slot_ok = TRUE;
11185 struct mips_opcode *firstinsn = NULL;
11186 const struct mips_opcode *past;
11187 struct hash_control *hash;
11191 struct mips_opcode *insn;
11193 unsigned int regno, regno2;
11194 unsigned int lastregno;
11195 unsigned int destregno = 0;
11196 unsigned int lastpos = 0;
11197 unsigned int limlo, limhi;
11200 offsetT min_range, max_range;
11204 unsigned int rtype;
11210 if (mips_opts.micromips)
11212 hash = micromips_op_hash;
11213 past = µmips_opcodes[bfd_micromips_num_opcodes];
11218 past = &mips_opcodes[NUMOPCODES];
11220 forced_insn_length = 0;
11223 /* We first try to match an instruction up to a space or to the end. */
11224 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11227 /* Make a copy of the instruction so that we can fiddle with it. */
11228 name = alloca (end + 1);
11229 memcpy (name, str, end);
11234 insn = (struct mips_opcode *) hash_find (hash, name);
11236 if (insn != NULL || !mips_opts.micromips)
11238 if (forced_insn_length)
11241 /* See if there's an instruction size override suffix,
11242 either `16' or `32', at the end of the mnemonic proper,
11243 that defines the operation, i.e. before the first `.'
11244 character if any. Strip it and retry. */
11245 dot = strchr (name, '.');
11246 opend = dot != NULL ? dot - name : end;
11249 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11250 forced_insn_length = 2;
11251 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11252 forced_insn_length = 4;
11255 memcpy (name + opend - 2, name + opend, end - opend + 1);
11259 insn_error = _("Unrecognized opcode");
11263 /* For microMIPS instructions placed in a fixed-length branch delay slot
11264 we make up to two passes over the relevant fragment of the opcode
11265 table. First we try instructions that meet the delay slot's length
11266 requirement. If none matched, then we retry with the remaining ones
11267 and if one matches, then we use it and then issue an appropriate
11268 warning later on. */
11269 argsStart = s = str + end;
11272 bfd_boolean delay_slot_ok;
11273 bfd_boolean size_ok;
11276 gas_assert (strcmp (insn->name, name) == 0);
11278 ok = is_opcode_valid (insn);
11279 size_ok = is_size_valid (insn);
11280 delay_slot_ok = is_delay_slot_valid (insn);
11281 if (!delay_slot_ok && !wrong_delay_slot_insns)
11284 wrong_delay_slot_insns = TRUE;
11286 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11288 static char buf[256];
11290 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11295 if (wrong_delay_slot_insns && need_delay_slot_ok)
11297 gas_assert (firstinsn);
11298 need_delay_slot_ok = FALSE;
11308 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11309 mips_cpu_info_from_arch (mips_opts.arch)->name,
11310 mips_cpu_info_from_isa (mips_opts.isa)->name);
11311 else if (mips_opts.insn32)
11312 sprintf (buf, _("Opcode not supported in the `insn32' mode"));
11314 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11315 8 * forced_insn_length);
11321 imm_expr.X_op = O_absent;
11322 imm2_expr.X_op = O_absent;
11323 offset_expr.X_op = O_absent;
11324 offset_reloc[0] = BFD_RELOC_UNUSED;
11325 offset_reloc[1] = BFD_RELOC_UNUSED;
11326 offset_reloc[2] = BFD_RELOC_UNUSED;
11328 create_insn (ip, insn);
11331 lastregno = 0xffffffff;
11332 for (args = insn->args;; ++args)
11336 s += strspn (s, " \t");
11340 case '\0': /* end of args */
11346 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11347 code) or 14 (for microMIPS code). */
11348 my_getExpression (&imm_expr, s);
11349 check_absolute_expr (ip, &imm_expr);
11350 if ((unsigned long) imm_expr.X_add_number != 1
11351 && (unsigned long) imm_expr.X_add_number != 3)
11353 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11354 (unsigned long) imm_expr.X_add_number);
11356 INSERT_OPERAND (mips_opts.micromips,
11357 BP, *ip, imm_expr.X_add_number);
11358 imm_expr.X_op = O_absent;
11363 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11364 code) or 13 (for microMIPS code). */
11366 unsigned long mask = (mips_opts.micromips
11367 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11369 my_getExpression (&imm_expr, s);
11370 check_absolute_expr (ip, &imm_expr);
11371 if ((unsigned long) imm_expr.X_add_number > mask)
11372 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11373 mask, (unsigned long) imm_expr.X_add_number);
11374 INSERT_OPERAND (mips_opts.micromips,
11375 SA3, *ip, imm_expr.X_add_number);
11376 imm_expr.X_op = O_absent;
11382 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11383 code) or 12 (for microMIPS code). */
11385 unsigned long mask = (mips_opts.micromips
11386 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11388 my_getExpression (&imm_expr, s);
11389 check_absolute_expr (ip, &imm_expr);
11390 if ((unsigned long) imm_expr.X_add_number > mask)
11391 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11392 mask, (unsigned long) imm_expr.X_add_number);
11393 INSERT_OPERAND (mips_opts.micromips,
11394 SA4, *ip, imm_expr.X_add_number);
11395 imm_expr.X_op = O_absent;
11401 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11402 code) or 13 (for microMIPS code). */
11404 unsigned long mask = (mips_opts.micromips
11405 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11407 my_getExpression (&imm_expr, s);
11408 check_absolute_expr (ip, &imm_expr);
11409 if ((unsigned long) imm_expr.X_add_number > mask)
11410 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11411 mask, (unsigned long) imm_expr.X_add_number);
11412 INSERT_OPERAND (mips_opts.micromips,
11413 IMM8, *ip, imm_expr.X_add_number);
11414 imm_expr.X_op = O_absent;
11420 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11421 code) or 16 (for microMIPS code). */
11423 unsigned long mask = (mips_opts.micromips
11424 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11426 my_getExpression (&imm_expr, s);
11427 check_absolute_expr (ip, &imm_expr);
11428 if ((unsigned long) imm_expr.X_add_number > mask)
11429 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11430 mask, (unsigned long) imm_expr.X_add_number);
11431 INSERT_OPERAND (mips_opts.micromips,
11432 RS, *ip, imm_expr.X_add_number);
11433 imm_expr.X_op = O_absent;
11439 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11440 or 14 (for microMIPS code). */
11441 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11442 && s[3] >= '0' && s[3] <= '3')
11444 regno = s[3] - '0';
11446 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11450 as_bad (_("Invalid dsp acc register"));
11454 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11455 code) or 14 (for microMIPS code). */
11457 unsigned long mask = (mips_opts.micromips
11458 ? MICROMIPSOP_MASK_WRDSP
11461 my_getExpression (&imm_expr, s);
11462 check_absolute_expr (ip, &imm_expr);
11463 if ((unsigned long) imm_expr.X_add_number > mask)
11464 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11465 mask, (unsigned long) imm_expr.X_add_number);
11466 INSERT_OPERAND (mips_opts.micromips,
11467 WRDSP, *ip, imm_expr.X_add_number);
11468 imm_expr.X_op = O_absent;
11473 case '9': /* Four DSP accumulators in bits 21,22. */
11474 gas_assert (!mips_opts.micromips);
11475 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11476 && s[3] >= '0' && s[3] <= '3')
11478 regno = s[3] - '0';
11480 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11484 as_bad (_("Invalid dsp acc register"));
11488 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11489 code) or 16 (for microMIPS code). */
11491 long mask = (mips_opts.micromips
11492 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11494 my_getExpression (&imm_expr, s);
11495 check_absolute_expr (ip, &imm_expr);
11496 min_range = -((mask + 1) >> 1);
11497 max_range = ((mask + 1) >> 1) - 1;
11498 if (imm_expr.X_add_number < min_range
11499 || imm_expr.X_add_number > max_range)
11500 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11501 (long) min_range, (long) max_range,
11502 (long) imm_expr.X_add_number);
11503 INSERT_OPERAND (mips_opts.micromips,
11504 DSPSFT, *ip, imm_expr.X_add_number);
11505 imm_expr.X_op = O_absent;
11510 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11511 gas_assert (!mips_opts.micromips);
11512 my_getExpression (&imm_expr, s);
11513 check_absolute_expr (ip, &imm_expr);
11514 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11516 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11518 (unsigned long) imm_expr.X_add_number);
11520 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11521 imm_expr.X_op = O_absent;
11525 case ':': /* DSP 7-bit signed immediate in bit 19. */
11526 gas_assert (!mips_opts.micromips);
11527 my_getExpression (&imm_expr, s);
11528 check_absolute_expr (ip, &imm_expr);
11529 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11530 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11531 if (imm_expr.X_add_number < min_range ||
11532 imm_expr.X_add_number > max_range)
11534 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11535 (long) min_range, (long) max_range,
11536 (long) imm_expr.X_add_number);
11538 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11539 imm_expr.X_op = O_absent;
11543 case '@': /* DSP 10-bit signed immediate in bit 16. */
11545 long mask = (mips_opts.micromips
11546 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11548 my_getExpression (&imm_expr, s);
11549 check_absolute_expr (ip, &imm_expr);
11550 min_range = -((mask + 1) >> 1);
11551 max_range = ((mask + 1) >> 1) - 1;
11552 if (imm_expr.X_add_number < min_range
11553 || imm_expr.X_add_number > max_range)
11554 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11555 (long) min_range, (long) max_range,
11556 (long) imm_expr.X_add_number);
11557 INSERT_OPERAND (mips_opts.micromips,
11558 IMM10, *ip, imm_expr.X_add_number);
11559 imm_expr.X_op = O_absent;
11564 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11565 gas_assert (mips_opts.micromips);
11566 my_getExpression (&imm_expr, s);
11567 check_absolute_expr (ip, &imm_expr);
11568 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11569 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11570 MICROMIPSOP_MASK_RD,
11571 (unsigned long) imm_expr.X_add_number);
11572 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11573 imm_expr.X_op = O_absent;
11577 case '!': /* MT usermode flag bit. */
11578 gas_assert (!mips_opts.micromips);
11579 my_getExpression (&imm_expr, s);
11580 check_absolute_expr (ip, &imm_expr);
11581 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11582 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11583 (unsigned long) imm_expr.X_add_number);
11584 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11585 imm_expr.X_op = O_absent;
11589 case '$': /* MT load high flag bit. */
11590 gas_assert (!mips_opts.micromips);
11591 my_getExpression (&imm_expr, s);
11592 check_absolute_expr (ip, &imm_expr);
11593 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11594 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11595 (unsigned long) imm_expr.X_add_number);
11596 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11597 imm_expr.X_op = O_absent;
11601 case '*': /* Four DSP accumulators in bits 18,19. */
11602 gas_assert (!mips_opts.micromips);
11603 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11604 s[3] >= '0' && s[3] <= '3')
11606 regno = s[3] - '0';
11608 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11612 as_bad (_("Invalid dsp/smartmips acc register"));
11615 case '&': /* Four DSP accumulators in bits 13,14. */
11616 gas_assert (!mips_opts.micromips);
11617 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11618 s[3] >= '0' && s[3] <= '3')
11620 regno = s[3] - '0';
11622 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11626 as_bad (_("Invalid dsp/smartmips acc register"));
11629 case '\\': /* 3-bit bit position. */
11631 unsigned long mask = (mips_opts.micromips
11632 ? MICROMIPSOP_MASK_3BITPOS
11633 : OP_MASK_3BITPOS);
11635 my_getExpression (&imm_expr, s);
11636 check_absolute_expr (ip, &imm_expr);
11637 if ((unsigned long) imm_expr.X_add_number > mask)
11638 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11640 mask, (unsigned long) imm_expr.X_add_number);
11641 INSERT_OPERAND (mips_opts.micromips,
11642 3BITPOS, *ip, imm_expr.X_add_number);
11643 imm_expr.X_op = O_absent;
11657 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11661 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11665 gas_assert (!mips_opts.micromips);
11666 INSERT_OPERAND (0, FT, *ip, lastregno);
11670 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11676 /* Handle optional base register.
11677 Either the base register is omitted or
11678 we must have a left paren. */
11679 /* This is dependent on the next operand specifier
11680 is a base register specification. */
11681 gas_assert (args[1] == 'b'
11682 || (mips_opts.micromips
11684 && (args[2] == 'l' || args[2] == 'n'
11685 || args[2] == 's' || args[2] == 'a')));
11686 if (*s == '\0' && args[1] == 'b')
11688 /* Fall through. */
11690 case ')': /* These must match exactly. */
11695 case '+': /* Opcode extension character. */
11698 case '1': /* UDI immediates. */
11702 gas_assert (!mips_opts.micromips);
11704 const struct mips_immed *imm = mips_immed;
11706 while (imm->type && imm->type != *args)
11710 my_getExpression (&imm_expr, s);
11711 check_absolute_expr (ip, &imm_expr);
11712 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11714 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11715 imm->desc ? imm->desc : ip->insn_mo->name,
11716 (unsigned long) imm_expr.X_add_number,
11717 (unsigned long) imm_expr.X_add_number);
11718 imm_expr.X_add_number &= imm->mask;
11720 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11722 imm_expr.X_op = O_absent;
11727 case 'J': /* 10-bit hypcall code. */
11728 gas_assert (!mips_opts.micromips);
11730 unsigned long mask = OP_MASK_CODE10;
11732 my_getExpression (&imm_expr, s);
11733 check_absolute_expr (ip, &imm_expr);
11734 if ((unsigned long) imm_expr.X_add_number > mask)
11735 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11737 mask, (unsigned long) imm_expr.X_add_number);
11738 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11739 imm_expr.X_op = O_absent;
11744 case 'A': /* ins/ext position, becomes LSB. */
11753 my_getExpression (&imm_expr, s);
11754 check_absolute_expr (ip, &imm_expr);
11755 if ((unsigned long) imm_expr.X_add_number < limlo
11756 || (unsigned long) imm_expr.X_add_number > limhi)
11758 as_bad (_("Improper position (%lu)"),
11759 (unsigned long) imm_expr.X_add_number);
11760 imm_expr.X_add_number = limlo;
11762 lastpos = imm_expr.X_add_number;
11763 INSERT_OPERAND (mips_opts.micromips,
11764 EXTLSB, *ip, imm_expr.X_add_number);
11765 imm_expr.X_op = O_absent;
11769 case 'B': /* ins size, becomes MSB. */
11778 my_getExpression (&imm_expr, s);
11779 check_absolute_expr (ip, &imm_expr);
11780 /* Check for negative input so that small negative numbers
11781 will not succeed incorrectly. The checks against
11782 (pos+size) transitively check "size" itself,
11783 assuming that "pos" is reasonable. */
11784 if ((long) imm_expr.X_add_number < 0
11785 || ((unsigned long) imm_expr.X_add_number
11787 || ((unsigned long) imm_expr.X_add_number
11788 + lastpos) > limhi)
11790 as_bad (_("Improper insert size (%lu, position %lu)"),
11791 (unsigned long) imm_expr.X_add_number,
11792 (unsigned long) lastpos);
11793 imm_expr.X_add_number = limlo - lastpos;
11795 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11796 lastpos + imm_expr.X_add_number - 1);
11797 imm_expr.X_op = O_absent;
11801 case 'C': /* ext size, becomes MSBD. */
11817 my_getExpression (&imm_expr, s);
11818 check_absolute_expr (ip, &imm_expr);
11819 /* The checks against (pos+size) don't transitively check
11820 "size" itself, assuming that "pos" is reasonable.
11821 We also need to check the lower bound of "size". */
11822 if ((long) imm_expr.X_add_number < sizelo
11823 || ((unsigned long) imm_expr.X_add_number
11825 || ((unsigned long) imm_expr.X_add_number
11826 + lastpos) > limhi)
11828 as_bad (_("Improper extract size (%lu, position %lu)"),
11829 (unsigned long) imm_expr.X_add_number,
11830 (unsigned long) lastpos);
11831 imm_expr.X_add_number = limlo - lastpos;
11833 INSERT_OPERAND (mips_opts.micromips,
11834 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11835 imm_expr.X_op = O_absent;
11840 /* "+I" is like "I", except that imm2_expr is used. */
11841 my_getExpression (&imm2_expr, s);
11842 if (imm2_expr.X_op != O_big
11843 && imm2_expr.X_op != O_constant)
11844 insn_error = _("absolute expression required");
11845 if (HAVE_32BIT_GPRS)
11846 normalize_constant_expr (&imm2_expr);
11850 case 't': /* Coprocessor register number. */
11851 gas_assert (!mips_opts.micromips);
11852 if (s[0] == '$' && ISDIGIT (s[1]))
11862 while (ISDIGIT (*s));
11864 as_bad (_("Invalid register number (%d)"), regno);
11867 INSERT_OPERAND (0, RT, *ip, regno);
11872 as_bad (_("Invalid coprocessor 0 register number"));
11876 /* bbit[01] and bbit[01]32 bit index. Give error if index
11877 is not in the valid range. */
11878 gas_assert (!mips_opts.micromips);
11879 my_getExpression (&imm_expr, s);
11880 check_absolute_expr (ip, &imm_expr);
11881 if ((unsigned) imm_expr.X_add_number > 31)
11883 as_bad (_("Improper bit index (%lu)"),
11884 (unsigned long) imm_expr.X_add_number);
11885 imm_expr.X_add_number = 0;
11887 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11888 imm_expr.X_op = O_absent;
11893 /* bbit[01] bit index when bbit is used but we generate
11894 bbit[01]32 because the index is over 32. Move to the
11895 next candidate if index is not in the valid range. */
11896 gas_assert (!mips_opts.micromips);
11897 my_getExpression (&imm_expr, s);
11898 check_absolute_expr (ip, &imm_expr);
11899 if ((unsigned) imm_expr.X_add_number < 32
11900 || (unsigned) imm_expr.X_add_number > 63)
11902 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11903 imm_expr.X_op = O_absent;
11908 /* cins, cins32, exts and exts32 position field. Give error
11909 if it's not in the valid range. */
11910 gas_assert (!mips_opts.micromips);
11911 my_getExpression (&imm_expr, s);
11912 check_absolute_expr (ip, &imm_expr);
11913 if ((unsigned) imm_expr.X_add_number > 31)
11915 as_bad (_("Improper position (%lu)"),
11916 (unsigned long) imm_expr.X_add_number);
11917 imm_expr.X_add_number = 0;
11919 lastpos = imm_expr.X_add_number;
11920 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11921 imm_expr.X_op = O_absent;
11926 /* cins, cins32, exts and exts32 position field. Move to
11927 the next candidate if it's not in the valid range. */
11928 gas_assert (!mips_opts.micromips);
11929 my_getExpression (&imm_expr, s);
11930 check_absolute_expr (ip, &imm_expr);
11931 if ((unsigned) imm_expr.X_add_number < 32
11932 || (unsigned) imm_expr.X_add_number > 63)
11934 lastpos = imm_expr.X_add_number;
11935 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11936 imm_expr.X_op = O_absent;
11941 /* cins32 and exts32 length-minus-one field. */
11942 gas_assert (!mips_opts.micromips);
11943 my_getExpression (&imm_expr, s);
11944 check_absolute_expr (ip, &imm_expr);
11945 if ((unsigned long) imm_expr.X_add_number > 31
11946 || (unsigned long) imm_expr.X_add_number + lastpos > 31)
11948 as_bad (_("Improper size (%lu)"),
11949 (unsigned long) imm_expr.X_add_number);
11950 imm_expr.X_add_number = 0;
11952 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11953 imm_expr.X_op = O_absent;
11958 /* cins/exts length-minus-one field. */
11959 gas_assert (!mips_opts.micromips);
11960 my_getExpression (&imm_expr, s);
11961 check_absolute_expr (ip, &imm_expr);
11962 if ((unsigned long) imm_expr.X_add_number > 31
11963 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
11965 as_bad (_("Improper size (%lu)"),
11966 (unsigned long) imm_expr.X_add_number);
11967 imm_expr.X_add_number = 0;
11969 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11970 imm_expr.X_op = O_absent;
11975 /* seqi/snei immediate field. */
11976 gas_assert (!mips_opts.micromips);
11977 my_getExpression (&imm_expr, s);
11978 check_absolute_expr (ip, &imm_expr);
11979 if ((long) imm_expr.X_add_number < -512
11980 || (long) imm_expr.X_add_number >= 512)
11982 as_bad (_("Improper immediate (%ld)"),
11983 (long) imm_expr.X_add_number);
11984 imm_expr.X_add_number = 0;
11986 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
11987 imm_expr.X_op = O_absent;
11991 case 'a': /* 8-bit signed offset in bit 6 */
11992 gas_assert (!mips_opts.micromips);
11993 my_getExpression (&imm_expr, s);
11994 check_absolute_expr (ip, &imm_expr);
11995 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
11996 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
11997 if (imm_expr.X_add_number < min_range
11998 || imm_expr.X_add_number > max_range)
12000 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12001 (long) min_range, (long) max_range,
12002 (long) imm_expr.X_add_number);
12004 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
12005 imm_expr.X_op = O_absent;
12009 case 'b': /* 8-bit signed offset in bit 3 */
12010 gas_assert (!mips_opts.micromips);
12011 my_getExpression (&imm_expr, s);
12012 check_absolute_expr (ip, &imm_expr);
12013 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12014 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12015 if (imm_expr.X_add_number < min_range
12016 || imm_expr.X_add_number > max_range)
12018 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12019 (long) min_range, (long) max_range,
12020 (long) imm_expr.X_add_number);
12022 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12023 imm_expr.X_op = O_absent;
12027 case 'c': /* 9-bit signed offset in bit 6 */
12028 gas_assert (!mips_opts.micromips);
12029 my_getExpression (&imm_expr, s);
12030 check_absolute_expr (ip, &imm_expr);
12031 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12032 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12033 /* We check the offset range before adjusted. */
12036 if (imm_expr.X_add_number < min_range
12037 || imm_expr.X_add_number > max_range)
12039 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12040 (long) min_range, (long) max_range,
12041 (long) imm_expr.X_add_number);
12043 if (imm_expr.X_add_number & 0xf)
12045 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12046 (long) imm_expr.X_add_number);
12048 /* Right shift 4 bits to adjust the offset operand. */
12049 INSERT_OPERAND (0, OFFSET_C, *ip,
12050 imm_expr.X_add_number >> 4);
12051 imm_expr.X_op = O_absent;
12056 gas_assert (!mips_opts.micromips);
12057 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12059 if (regno == AT && mips_opts.at)
12061 if (mips_opts.at == ATREG)
12062 as_warn (_("used $at without \".set noat\""));
12064 as_warn (_("used $%u with \".set at=$%u\""),
12065 regno, mips_opts.at);
12067 INSERT_OPERAND (0, RZ, *ip, regno);
12071 gas_assert (!mips_opts.micromips);
12072 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12074 INSERT_OPERAND (0, FZ, *ip, regno);
12084 bfd_reloc_code_real_type r[3];
12086 /* Check whether there is only a single bracketed expression
12087 left. If so, it must be the base register and the
12088 constant must be zero. */
12089 if (*s == '(' && strchr (s + 1, '(') == 0)
12092 /* If this value won't fit into the offset, then go find
12093 a macro that will generate a 16- or 32-bit offset code
12095 i = my_getSmallExpression (&imm_expr, r, s);
12096 if ((i == 0 && (imm_expr.X_op != O_constant
12097 || imm_expr.X_add_number >= 1 << shift
12098 || imm_expr.X_add_number < -1 << shift))
12101 imm_expr.X_op = O_absent;
12104 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12105 imm_expr.X_add_number);
12106 imm_expr.X_op = O_absent;
12112 as_bad (_("Internal error: bad %s opcode "
12113 "(unknown extension operand type `+%c'): %s %s"),
12114 mips_opts.micromips ? "microMIPS" : "MIPS",
12115 *args, insn->name, insn->args);
12116 /* Further processing is fruitless. */
12121 case '.': /* 10-bit offset. */
12122 gas_assert (mips_opts.micromips);
12123 case '~': /* 12-bit offset. */
12125 int shift = *args == '.' ? 9 : 11;
12127 bfd_reloc_code_real_type r[3];
12129 /* Check whether there is only a single bracketed expression
12130 left. If so, it must be the base register and the
12131 constant must be zero. */
12132 if (*s == '(' && strchr (s + 1, '(') == 0)
12135 /* If this value won't fit into the offset, then go find
12136 a macro that will generate a 16- or 32-bit offset code
12138 i = my_getSmallExpression (&imm_expr, r, s);
12139 if ((i == 0 && (imm_expr.X_op != O_constant
12140 || imm_expr.X_add_number >= 1 << shift
12141 || imm_expr.X_add_number < -1 << shift))
12144 imm_expr.X_op = O_absent;
12148 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12150 INSERT_OPERAND (mips_opts.micromips,
12151 OFFSET12, *ip, imm_expr.X_add_number);
12152 imm_expr.X_op = O_absent;
12157 case '<': /* must be at least one digit */
12159 * According to the manual, if the shift amount is greater
12160 * than 31 or less than 0, then the shift amount should be
12161 * mod 32. In reality the mips assembler issues an error.
12162 * We issue a warning and mask out all but the low 5 bits.
12164 my_getExpression (&imm_expr, s);
12165 check_absolute_expr (ip, &imm_expr);
12166 if ((unsigned long) imm_expr.X_add_number > 31)
12167 as_warn (_("Improper shift amount (%lu)"),
12168 (unsigned long) imm_expr.X_add_number);
12169 INSERT_OPERAND (mips_opts.micromips,
12170 SHAMT, *ip, imm_expr.X_add_number);
12171 imm_expr.X_op = O_absent;
12175 case '>': /* shift amount minus 32 */
12176 my_getExpression (&imm_expr, s);
12177 check_absolute_expr (ip, &imm_expr);
12178 if ((unsigned long) imm_expr.X_add_number < 32
12179 || (unsigned long) imm_expr.X_add_number > 63)
12181 INSERT_OPERAND (mips_opts.micromips,
12182 SHAMT, *ip, imm_expr.X_add_number - 32);
12183 imm_expr.X_op = O_absent;
12187 case 'k': /* CACHE code. */
12188 case 'h': /* PREFX code. */
12189 case '1': /* SYNC type. */
12190 my_getExpression (&imm_expr, s);
12191 check_absolute_expr (ip, &imm_expr);
12192 if ((unsigned long) imm_expr.X_add_number > 31)
12193 as_warn (_("Invalid value for `%s' (%lu)"),
12195 (unsigned long) imm_expr.X_add_number);
12199 if (mips_fix_cn63xxp1
12200 && !mips_opts.micromips
12201 && strcmp ("pref", insn->name) == 0)
12202 switch (imm_expr.X_add_number)
12211 case 31: /* These are ok. */
12214 default: /* The rest must be changed to 28. */
12215 imm_expr.X_add_number = 28;
12218 INSERT_OPERAND (mips_opts.micromips,
12219 CACHE, *ip, imm_expr.X_add_number);
12222 INSERT_OPERAND (mips_opts.micromips,
12223 PREFX, *ip, imm_expr.X_add_number);
12226 INSERT_OPERAND (mips_opts.micromips,
12227 STYPE, *ip, imm_expr.X_add_number);
12230 imm_expr.X_op = O_absent;
12234 case 'c': /* BREAK code. */
12236 unsigned long mask = (mips_opts.micromips
12237 ? MICROMIPSOP_MASK_CODE
12240 my_getExpression (&imm_expr, s);
12241 check_absolute_expr (ip, &imm_expr);
12242 if ((unsigned long) imm_expr.X_add_number > mask)
12243 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12245 mask, (unsigned long) imm_expr.X_add_number);
12246 INSERT_OPERAND (mips_opts.micromips,
12247 CODE, *ip, imm_expr.X_add_number);
12248 imm_expr.X_op = O_absent;
12253 case 'q': /* Lower BREAK code. */
12255 unsigned long mask = (mips_opts.micromips
12256 ? MICROMIPSOP_MASK_CODE2
12259 my_getExpression (&imm_expr, s);
12260 check_absolute_expr (ip, &imm_expr);
12261 if ((unsigned long) imm_expr.X_add_number > mask)
12262 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12264 mask, (unsigned long) imm_expr.X_add_number);
12265 INSERT_OPERAND (mips_opts.micromips,
12266 CODE2, *ip, imm_expr.X_add_number);
12267 imm_expr.X_op = O_absent;
12272 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12274 unsigned long mask = (mips_opts.micromips
12275 ? MICROMIPSOP_MASK_CODE10
12278 my_getExpression (&imm_expr, s);
12279 check_absolute_expr (ip, &imm_expr);
12280 if ((unsigned long) imm_expr.X_add_number > mask)
12281 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12283 mask, (unsigned long) imm_expr.X_add_number);
12284 if (mips_opts.micromips)
12285 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12287 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12288 imm_expr.X_op = O_absent;
12293 case 'C': /* 25- or 23-bit coprocessor code. */
12295 unsigned long mask = (mips_opts.micromips
12296 ? MICROMIPSOP_MASK_COPZ
12299 my_getExpression (&imm_expr, s);
12300 check_absolute_expr (ip, &imm_expr);
12301 if ((unsigned long) imm_expr.X_add_number > mask)
12302 as_warn (_("Coproccesor code > %u bits (%lu)"),
12303 mips_opts.micromips ? 23U : 25U,
12304 (unsigned long) imm_expr.X_add_number);
12305 INSERT_OPERAND (mips_opts.micromips,
12306 COPZ, *ip, imm_expr.X_add_number);
12307 imm_expr.X_op = O_absent;
12312 case 'J': /* 19-bit WAIT code. */
12313 gas_assert (!mips_opts.micromips);
12314 my_getExpression (&imm_expr, s);
12315 check_absolute_expr (ip, &imm_expr);
12316 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12318 as_warn (_("Illegal 19-bit code (%lu)"),
12319 (unsigned long) imm_expr.X_add_number);
12320 imm_expr.X_add_number &= OP_MASK_CODE19;
12322 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12323 imm_expr.X_op = O_absent;
12327 case 'P': /* Performance register. */
12328 gas_assert (!mips_opts.micromips);
12329 my_getExpression (&imm_expr, s);
12330 check_absolute_expr (ip, &imm_expr);
12331 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12332 as_warn (_("Invalid performance register (%lu)"),
12333 (unsigned long) imm_expr.X_add_number);
12334 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12335 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12336 as_warn (_("Invalid performance register (%lu)"),
12337 (unsigned long) imm_expr.X_add_number);
12338 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12339 imm_expr.X_op = O_absent;
12343 case 'G': /* Coprocessor destination register. */
12345 unsigned long opcode = ip->insn_opcode;
12346 unsigned long mask;
12347 unsigned int types;
12350 if (mips_opts.micromips)
12352 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12353 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12354 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12358 case 0x000000fc: /* mfc0 */
12359 case 0x000002fc: /* mtc0 */
12360 case 0x580000fc: /* dmfc0 */
12361 case 0x580002fc: /* dmtc0 */
12371 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12372 cop0 = opcode == OP_OP_COP0;
12374 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12375 ok = reg_lookup (&s, types, ®no);
12376 if (mips_opts.micromips)
12377 INSERT_OPERAND (1, RS, *ip, regno);
12379 INSERT_OPERAND (0, RD, *ip, regno);
12388 case 'y': /* ALNV.PS source register. */
12389 gas_assert (mips_opts.micromips);
12391 case 'x': /* Ignore register name. */
12392 case 'U': /* Destination register (CLO/CLZ). */
12393 case 'g': /* Coprocessor destination register. */
12394 gas_assert (!mips_opts.micromips);
12395 case 'b': /* Base register. */
12396 case 'd': /* Destination register. */
12397 case 's': /* Source register. */
12398 case 't': /* Target register. */
12399 case 'r': /* Both target and source. */
12400 case 'v': /* Both dest and source. */
12401 case 'w': /* Both dest and target. */
12402 case 'E': /* Coprocessor target register. */
12403 case 'K': /* RDHWR destination register. */
12404 case 'z': /* Must be zero register. */
12407 if (*args == 'E' || *args == 'K')
12408 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12411 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12412 if (regno == AT && mips_opts.at)
12414 if (mips_opts.at == ATREG)
12415 as_warn (_("Used $at without \".set noat\""));
12417 as_warn (_("Used $%u with \".set at=$%u\""),
12418 regno, mips_opts.at);
12428 if (c == 'r' || c == 'v' || c == 'w')
12435 /* 'z' only matches $0. */
12436 if (c == 'z' && regno != 0)
12439 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12441 if (regno == lastregno)
12444 = _("Source and destination must be different");
12447 if (regno == 31 && lastregno == 0xffffffff)
12450 = _("A destination register must be supplied");
12454 /* Now that we have assembled one operand, we use the args
12455 string to figure out where it goes in the instruction. */
12462 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12466 if (mips_opts.micromips)
12467 INSERT_OPERAND (1, RS, *ip, regno);
12469 INSERT_OPERAND (0, RD, *ip, regno);
12474 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12478 gas_assert (!mips_opts.micromips);
12479 INSERT_OPERAND (0, RD, *ip, regno);
12480 INSERT_OPERAND (0, RT, *ip, regno);
12486 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12490 gas_assert (mips_opts.micromips);
12491 INSERT_OPERAND (1, RS3, *ip, regno);
12495 /* This case exists because on the r3000 trunc
12496 expands into a macro which requires a gp
12497 register. On the r6000 or r4000 it is
12498 assembled into a single instruction which
12499 ignores the register. Thus the insn version
12500 is MIPS_ISA2 and uses 'x', and the macro
12501 version is MIPS_ISA1 and uses 't'. */
12505 /* This case is for the div instruction, which
12506 acts differently if the destination argument
12507 is $0. This only matches $0, and is checked
12508 outside the switch. */
12518 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12522 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12527 case 'O': /* MDMX alignment immediate constant. */
12528 gas_assert (!mips_opts.micromips);
12529 my_getExpression (&imm_expr, s);
12530 check_absolute_expr (ip, &imm_expr);
12531 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12532 as_warn (_("Improper align amount (%ld), using low bits"),
12533 (long) imm_expr.X_add_number);
12534 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12535 imm_expr.X_op = O_absent;
12539 case 'Q': /* MDMX vector, element sel, or const. */
12542 /* MDMX Immediate. */
12543 gas_assert (!mips_opts.micromips);
12544 my_getExpression (&imm_expr, s);
12545 check_absolute_expr (ip, &imm_expr);
12546 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12547 as_warn (_("Invalid MDMX Immediate (%ld)"),
12548 (long) imm_expr.X_add_number);
12549 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12550 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12551 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12553 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12554 imm_expr.X_op = O_absent;
12558 /* Not MDMX Immediate. Fall through. */
12559 case 'X': /* MDMX destination register. */
12560 case 'Y': /* MDMX source register. */
12561 case 'Z': /* MDMX target register. */
12562 is_mdmx = !(insn->membership & INSN_5400);
12564 gas_assert (!mips_opts.micromips);
12565 case 'D': /* Floating point destination register. */
12566 case 'S': /* Floating point source register. */
12567 case 'T': /* Floating point target register. */
12568 case 'R': /* Floating point source register. */
12572 || ((mips_opts.ase & ASE_MDMX)
12573 && (ip->insn_mo->pinfo & FP_D)
12574 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12575 | INSN_COPROC_MEMORY_DELAY
12576 | INSN_LOAD_COPROC_DELAY
12577 | INSN_LOAD_MEMORY_DELAY
12578 | INSN_STORE_MEMORY))))
12579 rtype |= RTYPE_VEC;
12581 if (reg_lookup (&s, rtype, ®no))
12583 if ((regno & 1) != 0
12585 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12586 as_warn (_("Float register should be even, was %d"),
12594 if (c == 'V' || c == 'W')
12605 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12611 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12615 /* This is like 'Z', but also needs to fix the MDMX
12616 vector/scalar select bits. Note that the
12617 scalar immediate case is handled above. */
12618 if ((ip->insn_mo->membership & INSN_5400)
12619 && strcmp (insn->name, "rzu.ob") == 0)
12620 as_bad (_("Operand %d of `%s' must be an immediate"),
12621 argnum, ip->insn_mo->name);
12625 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12626 int max_el = (is_qh ? 3 : 7);
12628 my_getExpression(&imm_expr, s);
12629 check_absolute_expr (ip, &imm_expr);
12631 if (imm_expr.X_add_number > max_el)
12632 as_bad (_("Bad element selector %ld"),
12633 (long) imm_expr.X_add_number);
12634 imm_expr.X_add_number &= max_el;
12635 ip->insn_opcode |= (imm_expr.X_add_number
12638 imm_expr.X_op = O_absent;
12640 as_warn (_("Expecting ']' found '%s'"), s);
12646 if ((ip->insn_mo->membership & INSN_5400)
12647 && (strcmp (insn->name, "sll.ob") == 0
12648 || strcmp (insn->name, "srl.ob") == 0))
12649 as_bad (_("Operand %d of `%s' must be scalar"),
12650 argnum, ip->insn_mo->name);
12652 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12653 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12656 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12659 /* Fall through. */
12663 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12667 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12677 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12681 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12687 my_getExpression (&imm_expr, s);
12688 if (imm_expr.X_op != O_big
12689 && imm_expr.X_op != O_constant)
12690 insn_error = _("absolute expression required");
12691 if (HAVE_32BIT_GPRS)
12692 normalize_constant_expr (&imm_expr);
12697 my_getSmallExpression (&offset_expr, offset_reloc, s);
12698 if (offset_expr.X_op == O_register)
12700 /* Assume that the offset has been elided and that what
12701 we saw was a base register. The match will fail later
12702 if that assumption turns out to be wrong. */
12703 offset_expr.X_op = O_constant;
12704 offset_expr.X_add_number = 0;
12708 normalize_address_expr (&offset_expr);
12722 unsigned char temp[8];
12724 unsigned int length;
12729 /* These only appear as the last operand in an
12730 instruction, and every instruction that accepts
12731 them in any variant accepts them in all variants.
12732 This means we don't have to worry about backing out
12733 any changes if the instruction does not match.
12735 The difference between them is the size of the
12736 floating point constant and where it goes. For 'F'
12737 and 'L' the constant is 64 bits; for 'f' and 'l' it
12738 is 32 bits. Where the constant is placed is based
12739 on how the MIPS assembler does things:
12742 f -- immediate value
12745 The .lit4 and .lit8 sections are only used if
12746 permitted by the -G argument.
12748 The code below needs to know whether the target register
12749 is 32 or 64 bits wide. It relies on the fact 'f' and
12750 'F' are used with GPR-based instructions and 'l' and
12751 'L' are used with FPR-based instructions. */
12753 f64 = *args == 'F' || *args == 'L';
12754 using_gprs = *args == 'F' || *args == 'f';
12756 save_in = input_line_pointer;
12757 input_line_pointer = s;
12758 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12760 s = input_line_pointer;
12761 input_line_pointer = save_in;
12762 if (err != NULL && *err != '\0')
12764 as_bad (_("Bad floating point constant: %s"), err);
12765 memset (temp, '\0', sizeof temp);
12766 length = f64 ? 8 : 4;
12769 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12773 && (g_switch_value < 4
12774 || (temp[0] == 0 && temp[1] == 0)
12775 || (temp[2] == 0 && temp[3] == 0))))
12777 imm_expr.X_op = O_constant;
12778 if (!target_big_endian)
12779 imm_expr.X_add_number = bfd_getl32 (temp);
12781 imm_expr.X_add_number = bfd_getb32 (temp);
12783 else if (length > 4
12784 && !mips_disable_float_construction
12785 /* Constants can only be constructed in GPRs and
12786 copied to FPRs if the GPRs are at least as wide
12787 as the FPRs. Force the constant into memory if
12788 we are using 64-bit FPRs but the GPRs are only
12791 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12792 && ((temp[0] == 0 && temp[1] == 0)
12793 || (temp[2] == 0 && temp[3] == 0))
12794 && ((temp[4] == 0 && temp[5] == 0)
12795 || (temp[6] == 0 && temp[7] == 0)))
12797 /* The value is simple enough to load with a couple of
12798 instructions. If using 32-bit registers, set
12799 imm_expr to the high order 32 bits and offset_expr to
12800 the low order 32 bits. Otherwise, set imm_expr to
12801 the entire 64 bit constant. */
12802 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12804 imm_expr.X_op = O_constant;
12805 offset_expr.X_op = O_constant;
12806 if (!target_big_endian)
12808 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12809 offset_expr.X_add_number = bfd_getl32 (temp);
12813 imm_expr.X_add_number = bfd_getb32 (temp);
12814 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12816 if (offset_expr.X_add_number == 0)
12817 offset_expr.X_op = O_absent;
12821 imm_expr.X_op = O_constant;
12822 if (!target_big_endian)
12823 imm_expr.X_add_number = bfd_getl64 (temp);
12825 imm_expr.X_add_number = bfd_getb64 (temp);
12830 const char *newname;
12833 /* Switch to the right section. */
12835 subseg = now_subseg;
12838 default: /* unused default case avoids warnings. */
12840 newname = RDATA_SECTION_NAME;
12841 if (g_switch_value >= 8)
12845 newname = RDATA_SECTION_NAME;
12848 gas_assert (g_switch_value >= 4);
12852 new_seg = subseg_new (newname, (subsegT) 0);
12853 bfd_set_section_flags (stdoutput, new_seg,
12858 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12859 if (strncmp (TARGET_OS, "elf", 3) != 0)
12860 record_alignment (new_seg, 4);
12862 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12863 if (seg == now_seg)
12864 as_bad (_("Can't use floating point insn in this section"));
12866 /* Set the argument to the current address in the
12868 offset_expr.X_op = O_symbol;
12869 offset_expr.X_add_symbol = symbol_temp_new_now ();
12870 offset_expr.X_add_number = 0;
12872 /* Put the floating point number into the section. */
12873 p = frag_more ((int) length);
12874 memcpy (p, temp, length);
12876 /* Switch back to the original section. */
12877 subseg_set (seg, subseg);
12882 case 'i': /* 16-bit unsigned immediate. */
12883 case 'j': /* 16-bit signed immediate. */
12884 *offset_reloc = BFD_RELOC_LO16;
12885 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0)
12888 offsetT minval, maxval;
12890 more = (insn + 1 < past
12891 && strcmp (insn->name, insn[1].name) == 0);
12893 /* For compatibility with older assemblers, we accept
12894 0x8000-0xffff as signed 16-bit numbers when only
12895 signed numbers are allowed. */
12897 minval = 0, maxval = 0xffff;
12899 minval = -0x8000, maxval = 0x7fff;
12901 minval = -0x8000, maxval = 0xffff;
12903 if (offset_expr.X_op != O_constant
12904 || offset_expr.X_add_number < minval
12905 || offset_expr.X_add_number > maxval)
12909 if (offset_expr.X_op == O_constant
12910 || offset_expr.X_op == O_big)
12911 as_bad (_("Expression out of range"));
12917 case 'o': /* 16-bit offset. */
12918 offset_reloc[0] = BFD_RELOC_LO16;
12919 offset_reloc[1] = BFD_RELOC_UNUSED;
12920 offset_reloc[2] = BFD_RELOC_UNUSED;
12922 /* Check whether there is only a single bracketed expression
12923 left. If so, it must be the base register and the
12924 constant must be zero. */
12925 if (*s == '(' && strchr (s + 1, '(') == 0)
12927 offset_expr.X_op = O_constant;
12928 offset_expr.X_add_number = 0;
12932 /* If this value won't fit into a 16 bit offset, then go
12933 find a macro that will generate the 32 bit offset
12935 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12936 && (offset_expr.X_op != O_constant
12937 || offset_expr.X_add_number >= 0x8000
12938 || offset_expr.X_add_number < -0x8000))
12944 case 'p': /* PC-relative offset. */
12945 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12946 my_getExpression (&offset_expr, s);
12950 case 'u': /* Upper 16 bits. */
12951 *offset_reloc = BFD_RELOC_LO16;
12952 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12953 && offset_expr.X_op == O_constant
12954 && (offset_expr.X_add_number < 0
12955 || offset_expr.X_add_number >= 0x10000))
12956 as_bad (_("lui expression (%lu) not in range 0..65535"),
12957 (unsigned long) offset_expr.X_add_number);
12961 case 'a': /* 26-bit address. */
12963 *offset_reloc = BFD_RELOC_MIPS_JMP;
12964 my_getExpression (&offset_expr, s);
12968 case 'N': /* 3-bit branch condition code. */
12969 case 'M': /* 3-bit compare condition code. */
12971 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12972 rtype |= RTYPE_FCC;
12973 if (!reg_lookup (&s, rtype, ®no))
12975 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12976 || strcmp (str + strlen (str) - 5, "any2f") == 0
12977 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12978 && (regno & 1) != 0)
12979 as_warn (_("Condition code register should be even for %s, "
12982 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12983 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12984 && (regno & 3) != 0)
12985 as_warn (_("Condition code register should be 0 or 4 for %s, "
12989 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
12991 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
12995 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
13006 while (ISDIGIT (*s));
13009 c = 8; /* Invalid sel value. */
13012 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13013 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13017 gas_assert (!mips_opts.micromips);
13018 /* Must be at least one digit. */
13019 my_getExpression (&imm_expr, s);
13020 check_absolute_expr (ip, &imm_expr);
13022 if ((unsigned long) imm_expr.X_add_number
13023 > (unsigned long) OP_MASK_VECBYTE)
13025 as_bad (_("bad byte vector index (%ld)"),
13026 (long) imm_expr.X_add_number);
13027 imm_expr.X_add_number = 0;
13030 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13031 imm_expr.X_op = O_absent;
13036 gas_assert (!mips_opts.micromips);
13037 my_getExpression (&imm_expr, s);
13038 check_absolute_expr (ip, &imm_expr);
13040 if ((unsigned long) imm_expr.X_add_number
13041 > (unsigned long) OP_MASK_VECALIGN)
13043 as_bad (_("bad byte vector index (%ld)"),
13044 (long) imm_expr.X_add_number);
13045 imm_expr.X_add_number = 0;
13048 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13049 imm_expr.X_op = O_absent;
13053 case 'm': /* Opcode extension character. */
13054 gas_assert (mips_opts.micromips);
13059 if (strncmp (s, "$pc", 3) == 0)
13086 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13087 if (regno == AT && mips_opts.at)
13089 if (mips_opts.at == ATREG)
13090 as_warn (_("Used $at without \".set noat\""));
13092 as_warn (_("Used $%u with \".set at=$%u\""),
13093 regno, mips_opts.at);
13099 gas_assert (args[1] == ',');
13105 gas_assert (args[1] == ',');
13107 continue; /* Nothing to do. */
13113 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13115 if (regno == lastregno)
13118 = _("Source and destination must be different");
13121 if (regno == 31 && lastregno == 0xffffffff)
13124 = _("A destination register must be supplied");
13135 gas_assert (args[1] == ',');
13142 gas_assert (args[1] == ',');
13145 continue; /* Nothing to do. */
13149 /* Make sure regno is the same as lastregno. */
13150 if (c == 't' && regno != lastregno)
13153 /* Make sure regno is the same as destregno. */
13154 if (c == 'x' && regno != destregno)
13157 /* We need to save regno, before regno maps to the
13158 microMIPS register encoding. */
13168 regno = ILLEGAL_REG;
13172 regno = mips32_to_micromips_reg_b_map[regno];
13176 regno = mips32_to_micromips_reg_c_map[regno];
13180 regno = mips32_to_micromips_reg_d_map[regno];
13184 regno = mips32_to_micromips_reg_e_map[regno];
13188 regno = mips32_to_micromips_reg_f_map[regno];
13192 regno = mips32_to_micromips_reg_g_map[regno];
13196 s += strspn (s, " \t");
13199 regno = ILLEGAL_REG;
13203 s += strspn (s, " \t");
13204 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
13207 regno = ILLEGAL_REG;
13210 if (regno2 == AT && mips_opts.at)
13212 if (mips_opts.at == ATREG)
13213 as_warn (_("Used $at without \".set noat\""));
13215 as_warn (_("Used $%u with \".set at=$%u\""),
13216 regno2, mips_opts.at);
13218 regno = (mips_lookup_reg_pair
13220 micromips_to_32_reg_h_map1,
13221 micromips_to_32_reg_h_map2, 8));
13225 regno = mips32_to_micromips_reg_l_map[regno];
13229 regno = mips32_to_micromips_reg_m_map[regno];
13233 regno = mips32_to_micromips_reg_n_map[regno];
13237 regno = mips32_to_micromips_reg_q_map[regno];
13242 regno = ILLEGAL_REG;
13247 regno = ILLEGAL_REG;
13252 regno = ILLEGAL_REG;
13255 case 'j': /* Do nothing. */
13265 if (regno == ILLEGAL_REG)
13271 INSERT_OPERAND (1, MB, *ip, regno);
13275 INSERT_OPERAND (1, MC, *ip, regno);
13279 INSERT_OPERAND (1, MD, *ip, regno);
13283 INSERT_OPERAND (1, ME, *ip, regno);
13287 INSERT_OPERAND (1, MF, *ip, regno);
13291 INSERT_OPERAND (1, MG, *ip, regno);
13295 INSERT_OPERAND (1, MH, *ip, regno);
13299 INSERT_OPERAND (1, MJ, *ip, regno);
13303 INSERT_OPERAND (1, ML, *ip, regno);
13307 INSERT_OPERAND (1, MM, *ip, regno);
13311 INSERT_OPERAND (1, MN, *ip, regno);
13315 INSERT_OPERAND (1, MP, *ip, regno);
13319 INSERT_OPERAND (1, MQ, *ip, regno);
13322 case 'a': /* Do nothing. */
13323 case 's': /* Do nothing. */
13324 case 't': /* Do nothing. */
13325 case 'x': /* Do nothing. */
13326 case 'y': /* Do nothing. */
13327 case 'z': /* Do nothing. */
13337 bfd_reloc_code_real_type r[3];
13341 /* Check whether there is only a single bracketed
13342 expression left. If so, it must be the base register
13343 and the constant must be zero. */
13344 if (*s == '(' && strchr (s + 1, '(') == 0)
13346 INSERT_OPERAND (1, IMMA, *ip, 0);
13350 if (my_getSmallExpression (&ep, r, s) > 0
13351 || !expr_const_in_range (&ep, -64, 64, 2))
13354 imm = ep.X_add_number >> 2;
13355 INSERT_OPERAND (1, IMMA, *ip, imm);
13362 bfd_reloc_code_real_type r[3];
13366 if (my_getSmallExpression (&ep, r, s) > 0
13367 || ep.X_op != O_constant)
13370 for (imm = 0; imm < 8; imm++)
13371 if (micromips_imm_b_map[imm] == ep.X_add_number)
13376 INSERT_OPERAND (1, IMMB, *ip, imm);
13383 bfd_reloc_code_real_type r[3];
13387 if (my_getSmallExpression (&ep, r, s) > 0
13388 || ep.X_op != O_constant)
13391 for (imm = 0; imm < 16; imm++)
13392 if (micromips_imm_c_map[imm] == ep.X_add_number)
13397 INSERT_OPERAND (1, IMMC, *ip, imm);
13402 case 'D': /* pc relative offset */
13403 case 'E': /* pc relative offset */
13404 my_getExpression (&offset_expr, s);
13405 if (offset_expr.X_op == O_register)
13408 if (!forced_insn_length)
13409 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13411 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13413 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13419 bfd_reloc_code_real_type r[3];
13423 if (my_getSmallExpression (&ep, r, s) > 0
13424 || !expr_const_in_range (&ep, 0, 16, 0))
13427 imm = ep.X_add_number;
13428 INSERT_OPERAND (1, IMMF, *ip, imm);
13435 bfd_reloc_code_real_type r[3];
13439 /* Check whether there is only a single bracketed
13440 expression left. If so, it must be the base register
13441 and the constant must be zero. */
13442 if (*s == '(' && strchr (s + 1, '(') == 0)
13444 INSERT_OPERAND (1, IMMG, *ip, 0);
13448 if (my_getSmallExpression (&ep, r, s) > 0
13449 || !expr_const_in_range (&ep, -1, 15, 0))
13452 imm = ep.X_add_number & 15;
13453 INSERT_OPERAND (1, IMMG, *ip, imm);
13460 bfd_reloc_code_real_type r[3];
13464 /* Check whether there is only a single bracketed
13465 expression left. If so, it must be the base register
13466 and the constant must be zero. */
13467 if (*s == '(' && strchr (s + 1, '(') == 0)
13469 INSERT_OPERAND (1, IMMH, *ip, 0);
13473 if (my_getSmallExpression (&ep, r, s) > 0
13474 || !expr_const_in_range (&ep, 0, 16, 1))
13477 imm = ep.X_add_number >> 1;
13478 INSERT_OPERAND (1, IMMH, *ip, imm);
13485 bfd_reloc_code_real_type r[3];
13489 if (my_getSmallExpression (&ep, r, s) > 0
13490 || !expr_const_in_range (&ep, -1, 127, 0))
13493 imm = ep.X_add_number & 127;
13494 INSERT_OPERAND (1, IMMI, *ip, imm);
13501 bfd_reloc_code_real_type r[3];
13505 /* Check whether there is only a single bracketed
13506 expression left. If so, it must be the base register
13507 and the constant must be zero. */
13508 if (*s == '(' && strchr (s + 1, '(') == 0)
13510 INSERT_OPERAND (1, IMMJ, *ip, 0);
13514 if (my_getSmallExpression (&ep, r, s) > 0
13515 || !expr_const_in_range (&ep, 0, 16, 2))
13518 imm = ep.X_add_number >> 2;
13519 INSERT_OPERAND (1, IMMJ, *ip, imm);
13526 bfd_reloc_code_real_type r[3];
13530 /* Check whether there is only a single bracketed
13531 expression left. If so, it must be the base register
13532 and the constant must be zero. */
13533 if (*s == '(' && strchr (s + 1, '(') == 0)
13535 INSERT_OPERAND (1, IMML, *ip, 0);
13539 if (my_getSmallExpression (&ep, r, s) > 0
13540 || !expr_const_in_range (&ep, 0, 16, 0))
13543 imm = ep.X_add_number;
13544 INSERT_OPERAND (1, IMML, *ip, imm);
13551 bfd_reloc_code_real_type r[3];
13555 if (my_getSmallExpression (&ep, r, s) > 0
13556 || !expr_const_in_range (&ep, 1, 9, 0))
13559 imm = ep.X_add_number & 7;
13560 INSERT_OPERAND (1, IMMM, *ip, imm);
13565 case 'N': /* Register list for lwm and swm. */
13567 /* A comma-separated list of registers and/or
13568 dash-separated contiguous ranges including
13569 both ra and a set of one or more registers
13570 starting at s0 up to s3 which have to be
13577 and any permutations of these. */
13578 unsigned int reglist;
13581 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13584 if ((reglist & 0xfff1ffff) != 0x80010000)
13587 reglist = (reglist >> 17) & 7;
13589 if ((reglist & -reglist) != reglist)
13592 imm = ffs (reglist) - 1;
13593 INSERT_OPERAND (1, IMMN, *ip, imm);
13597 case 'O': /* sdbbp 4-bit code. */
13599 bfd_reloc_code_real_type r[3];
13603 if (my_getSmallExpression (&ep, r, s) > 0
13604 || !expr_const_in_range (&ep, 0, 16, 0))
13607 imm = ep.X_add_number;
13608 INSERT_OPERAND (1, IMMO, *ip, imm);
13615 bfd_reloc_code_real_type r[3];
13619 if (my_getSmallExpression (&ep, r, s) > 0
13620 || !expr_const_in_range (&ep, 0, 32, 2))
13623 imm = ep.X_add_number >> 2;
13624 INSERT_OPERAND (1, IMMP, *ip, imm);
13631 bfd_reloc_code_real_type r[3];
13635 if (my_getSmallExpression (&ep, r, s) > 0
13636 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13639 imm = ep.X_add_number >> 2;
13640 INSERT_OPERAND (1, IMMQ, *ip, imm);
13647 bfd_reloc_code_real_type r[3];
13651 /* Check whether there is only a single bracketed
13652 expression left. If so, it must be the base register
13653 and the constant must be zero. */
13654 if (*s == '(' && strchr (s + 1, '(') == 0)
13656 INSERT_OPERAND (1, IMMU, *ip, 0);
13660 if (my_getSmallExpression (&ep, r, s) > 0
13661 || !expr_const_in_range (&ep, 0, 32, 2))
13664 imm = ep.X_add_number >> 2;
13665 INSERT_OPERAND (1, IMMU, *ip, imm);
13672 bfd_reloc_code_real_type r[3];
13676 if (my_getSmallExpression (&ep, r, s) > 0
13677 || !expr_const_in_range (&ep, 0, 64, 2))
13680 imm = ep.X_add_number >> 2;
13681 INSERT_OPERAND (1, IMMW, *ip, imm);
13688 bfd_reloc_code_real_type r[3];
13692 if (my_getSmallExpression (&ep, r, s) > 0
13693 || !expr_const_in_range (&ep, -8, 8, 0))
13696 imm = ep.X_add_number;
13697 INSERT_OPERAND (1, IMMX, *ip, imm);
13704 bfd_reloc_code_real_type r[3];
13708 if (my_getSmallExpression (&ep, r, s) > 0
13709 || expr_const_in_range (&ep, -2, 2, 2)
13710 || !expr_const_in_range (&ep, -258, 258, 2))
13713 imm = ep.X_add_number >> 2;
13714 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13715 INSERT_OPERAND (1, IMMY, *ip, imm);
13722 bfd_reloc_code_real_type r[3];
13725 if (my_getSmallExpression (&ep, r, s) > 0
13726 || !expr_const_in_range (&ep, 0, 1, 0))
13733 as_bad (_("Internal error: bad microMIPS opcode "
13734 "(unknown extension operand type `m%c'): %s %s"),
13735 *args, insn->name, insn->args);
13736 /* Further processing is fruitless. */
13741 case 'n': /* Register list for 32-bit lwm and swm. */
13742 gas_assert (mips_opts.micromips);
13744 /* A comma-separated list of registers and/or
13745 dash-separated contiguous ranges including
13746 at least one of ra and a set of one or more
13747 registers starting at s0 up to s7 and then
13748 s8 which have to be consecutive, e.g.:
13756 and any permutations of these. */
13757 unsigned int reglist;
13761 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13764 if ((reglist & 0x3f00ffff) != 0)
13767 ra = (reglist >> 27) & 0x10;
13768 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13770 if ((reglist & -reglist) != reglist)
13773 imm = (ffs (reglist) - 1) | ra;
13774 INSERT_OPERAND (1, RT, *ip, imm);
13775 imm_expr.X_op = O_absent;
13779 case '|': /* 4-bit trap code. */
13780 gas_assert (mips_opts.micromips);
13781 my_getExpression (&imm_expr, s);
13782 check_absolute_expr (ip, &imm_expr);
13783 if ((unsigned long) imm_expr.X_add_number
13784 > MICROMIPSOP_MASK_TRAP)
13785 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13786 (unsigned long) imm_expr.X_add_number,
13787 ip->insn_mo->name);
13788 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13789 imm_expr.X_op = O_absent;
13794 as_bad (_("Bad char = '%c'\n"), *args);
13799 /* Args don't match. */
13801 insn_error = _("Illegal operands");
13802 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13807 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13809 gas_assert (firstinsn);
13810 need_delay_slot_ok = FALSE;
13819 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13821 /* As for mips_ip, but used when assembling MIPS16 code.
13822 Also set forced_insn_length to the resulting instruction size in
13823 bytes if the user explicitly requested a small or extended instruction. */
13826 mips16_ip (char *str, struct mips_cl_insn *ip)
13830 struct mips_opcode *insn;
13832 unsigned int regno;
13833 unsigned int lastregno = 0;
13839 forced_insn_length = 0;
13841 for (s = str; ISLOWER (*s); ++s)
13853 if (s[1] == 't' && s[2] == ' ')
13856 forced_insn_length = 2;
13860 else if (s[1] == 'e' && s[2] == ' ')
13863 forced_insn_length = 4;
13867 /* Fall through. */
13869 insn_error = _("unknown opcode");
13873 if (mips_opts.noautoextend && !forced_insn_length)
13874 forced_insn_length = 2;
13876 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13878 insn_error = _("unrecognized opcode");
13888 gas_assert (strcmp (insn->name, str) == 0);
13890 ok = is_opcode_valid_16 (insn);
13893 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13894 && strcmp (insn->name, insn[1].name) == 0)
13903 static char buf[100];
13905 _("Opcode not supported on this processor: %s (%s)"),
13906 mips_cpu_info_from_arch (mips_opts.arch)->name,
13907 mips_cpu_info_from_isa (mips_opts.isa)->name);
13914 create_insn (ip, insn);
13915 imm_expr.X_op = O_absent;
13916 imm2_expr.X_op = O_absent;
13917 offset_expr.X_op = O_absent;
13918 offset_reloc[0] = BFD_RELOC_UNUSED;
13919 offset_reloc[1] = BFD_RELOC_UNUSED;
13920 offset_reloc[2] = BFD_RELOC_UNUSED;
13922 for (args = insn->args; 1; ++args)
13929 /* In this switch statement we call break if we did not find
13930 a match, continue if we did find a match, or return if we
13941 /* Stuff the immediate value in now, if we can. */
13942 if (insn->pinfo == INSN_MACRO)
13944 gas_assert (relax_char == 0);
13945 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
13947 else if (relax_char
13948 && offset_expr.X_op == O_constant
13949 && calculate_reloc (*offset_reloc,
13950 offset_expr.X_add_number,
13953 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
13954 forced_insn_length, &ip->insn_opcode);
13955 offset_expr.X_op = O_absent;
13956 *offset_reloc = BFD_RELOC_UNUSED;
13958 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
13960 if (forced_insn_length == 2)
13961 as_bad (_("invalid unextended operand value"));
13962 forced_insn_length = 4;
13963 ip->insn_opcode |= MIPS16_EXTEND;
13965 else if (relax_char)
13966 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
13979 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
13982 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
13998 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14000 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14004 /* Fall through. */
14015 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14017 if (c == 'v' || c == 'w')
14020 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14022 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14033 if (c == 'v' || c == 'w')
14035 regno = mips16_to_32_reg_map[lastregno];
14049 regno = mips32_to_16_reg_map[regno];
14054 regno = ILLEGAL_REG;
14059 regno = ILLEGAL_REG;
14064 regno = ILLEGAL_REG;
14069 if (regno == AT && mips_opts.at)
14071 if (mips_opts.at == ATREG)
14072 as_warn (_("used $at without \".set noat\""));
14074 as_warn (_("used $%u with \".set at=$%u\""),
14075 regno, mips_opts.at);
14083 if (regno == ILLEGAL_REG)
14090 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14094 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14097 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14100 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14106 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14109 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14110 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14120 if (strncmp (s, "$pc", 3) == 0)
14137 i = my_getSmallExpression (&offset_expr, offset_reloc, s);
14144 *offset_reloc = BFD_RELOC_UNUSED;
14145 /* Fall through. */
14152 my_getExpression (&offset_expr, s);
14153 if (offset_expr.X_op == O_register)
14155 /* What we thought was an expression turned out to
14158 if (s[0] == '(' && args[1] == '(')
14160 /* It looks like the expression was omitted
14161 before a register indirection, which means
14162 that the expression is implicitly zero. We
14163 still set up offset_expr, so that we handle
14164 explicit extensions correctly. */
14165 offset_expr.X_op = O_constant;
14166 offset_expr.X_add_number = 0;
14174 /* We need to relax this instruction. */
14184 /* We use offset_reloc rather than imm_reloc for the PC
14185 relative operands. This lets macros with both
14186 immediate and address operands work correctly. */
14187 my_getExpression (&offset_expr, s);
14189 if (offset_expr.X_op == O_register)
14192 /* We need to relax this instruction. */
14197 case '6': /* break code */
14198 my_getExpression (&imm_expr, s);
14199 check_absolute_expr (ip, &imm_expr);
14200 if ((unsigned long) imm_expr.X_add_number > 63)
14201 as_warn (_("Invalid value for `%s' (%lu)"),
14203 (unsigned long) imm_expr.X_add_number);
14204 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14205 imm_expr.X_op = O_absent;
14210 my_getExpression (&imm_expr, s);
14211 if (imm_expr.X_op != O_big
14212 && imm_expr.X_op != O_constant)
14213 insn_error = _("absolute expression required");
14214 if (HAVE_32BIT_GPRS)
14215 normalize_constant_expr (&imm_expr);
14219 case 'a': /* 26 bit address */
14221 my_getExpression (&offset_expr, s);
14223 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14224 ip->insn_opcode <<= 16;
14227 case 'l': /* register list for entry macro */
14228 case 'L': /* register list for exit macro */
14238 unsigned int freg, reg1, reg2;
14240 while (*s == ' ' || *s == ',')
14242 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14244 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14248 as_bad (_("can't parse register list"));
14258 if (!reg_lookup (&s, freg ? RTYPE_FPU
14259 : (RTYPE_GP | RTYPE_NUM), ®2))
14261 as_bad (_("invalid register list"));
14265 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14267 mask &= ~ (7 << 3);
14270 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14272 mask &= ~ (7 << 3);
14275 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14276 mask |= (reg2 - 3) << 3;
14277 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14278 mask |= (reg2 - 15) << 1;
14279 else if (reg1 == RA && reg2 == RA)
14283 as_bad (_("invalid register list"));
14287 /* The mask is filled in in the opcode table for the
14288 benefit of the disassembler. We remove it before
14289 applying the actual mask. */
14290 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14291 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14295 case 'm': /* Register list for save insn. */
14296 case 'M': /* Register list for restore insn. */
14298 int opcode = ip->insn_opcode;
14299 int framesz = 0, seen_framesz = 0;
14300 int nargs = 0, statics = 0, sregs = 0;
14304 unsigned int reg1, reg2;
14306 SKIP_SPACE_TABS (s);
14309 SKIP_SPACE_TABS (s);
14311 my_getExpression (&imm_expr, s);
14312 if (imm_expr.X_op == O_constant)
14314 /* Handle the frame size. */
14317 as_bad (_("more than one frame size in list"));
14321 framesz = imm_expr.X_add_number;
14322 imm_expr.X_op = O_absent;
14327 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14329 as_bad (_("can't parse register list"));
14341 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14344 as_bad (_("can't parse register list"));
14349 while (reg1 <= reg2)
14351 if (reg1 >= 4 && reg1 <= 7)
14355 nargs |= 1 << (reg1 - 4);
14357 /* statics $a0-$a3 */
14358 statics |= 1 << (reg1 - 4);
14360 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14363 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14365 else if (reg1 == 31)
14367 /* Add $ra to insn. */
14372 as_bad (_("unexpected register in list"));
14380 /* Encode args/statics combination. */
14381 if (nargs & statics)
14382 as_bad (_("arg/static registers overlap"));
14383 else if (nargs == 0xf)
14384 /* All $a0-$a3 are args. */
14385 opcode |= MIPS16_ALL_ARGS << 16;
14386 else if (statics == 0xf)
14387 /* All $a0-$a3 are statics. */
14388 opcode |= MIPS16_ALL_STATICS << 16;
14391 int narg = 0, nstat = 0;
14393 /* Count arg registers. */
14394 while (nargs & 0x1)
14400 as_bad (_("invalid arg register list"));
14402 /* Count static registers. */
14403 while (statics & 0x8)
14405 statics = (statics << 1) & 0xf;
14409 as_bad (_("invalid static register list"));
14411 /* Encode args/statics. */
14412 opcode |= ((narg << 2) | nstat) << 16;
14415 /* Encode $s0/$s1. */
14416 if (sregs & (1 << 0)) /* $s0 */
14418 if (sregs & (1 << 1)) /* $s1 */
14424 /* Count regs $s2-$s8. */
14432 as_bad (_("invalid static register list"));
14433 /* Encode $s2-$s8. */
14434 opcode |= nsreg << 24;
14437 /* Encode frame size. */
14439 as_bad (_("missing frame size"));
14440 else if ((framesz & 7) != 0 || framesz < 0
14441 || framesz > 0xff * 8)
14442 as_bad (_("invalid frame size"));
14443 else if (framesz != 128 || (opcode >> 16) != 0)
14446 opcode |= (((framesz & 0xf0) << 16)
14447 | (framesz & 0x0f));
14450 /* Finally build the instruction. */
14451 if ((opcode >> 16) != 0 || framesz == 0)
14452 opcode |= MIPS16_EXTEND;
14453 ip->insn_opcode = opcode;
14457 case 'e': /* extend code */
14458 my_getExpression (&imm_expr, s);
14459 check_absolute_expr (ip, &imm_expr);
14460 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14462 as_warn (_("Invalid value for `%s' (%lu)"),
14464 (unsigned long) imm_expr.X_add_number);
14465 imm_expr.X_add_number &= 0x7ff;
14467 ip->insn_opcode |= imm_expr.X_add_number;
14468 imm_expr.X_op = O_absent;
14478 /* Args don't match. */
14479 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14480 strcmp (insn->name, insn[1].name) == 0)
14487 insn_error = _("illegal operands");
14493 /* This structure holds information we know about a mips16 immediate
14496 struct mips16_immed_operand
14498 /* The type code used in the argument string in the opcode table. */
14500 /* The number of bits in the short form of the opcode. */
14502 /* The number of bits in the extended form of the opcode. */
14504 /* The amount by which the short form is shifted when it is used;
14505 for example, the sw instruction has a shift count of 2. */
14507 /* The amount by which the short form is shifted when it is stored
14508 into the instruction code. */
14510 /* Non-zero if the short form is unsigned. */
14512 /* Non-zero if the extended form is unsigned. */
14514 /* Non-zero if the value is PC relative. */
14518 /* The mips16 immediate operand types. */
14520 static const struct mips16_immed_operand mips16_immed_operands[] =
14522 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14523 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14524 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14525 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14526 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14527 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14528 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14529 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14530 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14531 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14532 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14533 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14534 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14535 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14536 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14537 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14538 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14539 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14540 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14541 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14542 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14545 #define MIPS16_NUM_IMMED \
14546 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14548 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14549 NBITS is the number of significant bits in VAL. */
14551 static unsigned long
14552 mips16_immed_extend (offsetT val, unsigned int nbits)
14557 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14560 else if (nbits == 15)
14562 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14567 extval = ((val & 0x1f) << 6) | (val & 0x20);
14570 return (extval << 16) | val;
14573 /* Install immediate value VAL into MIPS16 instruction *INSN,
14574 extending it if necessary. The instruction in *INSN may
14575 already be extended.
14577 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14578 if none. In the former case, VAL is a 16-bit number with no
14579 defined signedness.
14581 TYPE is the type of the immediate field. USER_INSN_LENGTH
14582 is the length that the user requested, or 0 if none. */
14585 mips16_immed (char *file, unsigned int line, int type,
14586 bfd_reloc_code_real_type reloc, offsetT val,
14587 unsigned int user_insn_length, unsigned long *insn)
14589 const struct mips16_immed_operand *op;
14590 int mintiny, maxtiny;
14592 op = mips16_immed_operands;
14593 while (op->type != type)
14596 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14601 if (type == '<' || type == '>' || type == '[' || type == ']')
14604 maxtiny = 1 << op->nbits;
14609 maxtiny = (1 << op->nbits) - 1;
14611 if (reloc != BFD_RELOC_UNUSED)
14616 mintiny = - (1 << (op->nbits - 1));
14617 maxtiny = (1 << (op->nbits - 1)) - 1;
14618 if (reloc != BFD_RELOC_UNUSED)
14619 val = SEXT_16BIT (val);
14622 /* Branch offsets have an implicit 0 in the lowest bit. */
14623 if (type == 'p' || type == 'q')
14626 if ((val & ((1 << op->shift) - 1)) != 0
14627 || val < (mintiny << op->shift)
14628 || val > (maxtiny << op->shift))
14630 /* We need an extended instruction. */
14631 if (user_insn_length == 2)
14632 as_bad_where (file, line, _("invalid unextended operand value"));
14634 *insn |= MIPS16_EXTEND;
14636 else if (user_insn_length == 4)
14638 /* The operand doesn't force an unextended instruction to be extended.
14639 Warn if the user wanted an extended instruction anyway. */
14640 *insn |= MIPS16_EXTEND;
14641 as_warn_where (file, line,
14642 _("extended operand requested but not required"));
14645 if (mips16_opcode_length (*insn) == 2)
14649 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14650 insnval <<= op->op_shift;
14655 long minext, maxext;
14657 if (reloc == BFD_RELOC_UNUSED)
14662 maxext = (1 << op->extbits) - 1;
14666 minext = - (1 << (op->extbits - 1));
14667 maxext = (1 << (op->extbits - 1)) - 1;
14669 if (val < minext || val > maxext)
14670 as_bad_where (file, line,
14671 _("operand value out of range for instruction"));
14674 *insn |= mips16_immed_extend (val, op->extbits);
14678 struct percent_op_match
14681 bfd_reloc_code_real_type reloc;
14684 static const struct percent_op_match mips_percent_op[] =
14686 {"%lo", BFD_RELOC_LO16},
14687 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14688 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14689 {"%call16", BFD_RELOC_MIPS_CALL16},
14690 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14691 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14692 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14693 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14694 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14695 {"%got", BFD_RELOC_MIPS_GOT16},
14696 {"%gp_rel", BFD_RELOC_GPREL16},
14697 {"%half", BFD_RELOC_16},
14698 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14699 {"%higher", BFD_RELOC_MIPS_HIGHER},
14700 {"%neg", BFD_RELOC_MIPS_SUB},
14701 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14702 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14703 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14704 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14705 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14706 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14707 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14708 {"%hi", BFD_RELOC_HI16_S}
14711 static const struct percent_op_match mips16_percent_op[] =
14713 {"%lo", BFD_RELOC_MIPS16_LO16},
14714 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14715 {"%got", BFD_RELOC_MIPS16_GOT16},
14716 {"%call16", BFD_RELOC_MIPS16_CALL16},
14717 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14718 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14719 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14720 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14721 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14722 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14723 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14724 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14728 /* Return true if *STR points to a relocation operator. When returning true,
14729 move *STR over the operator and store its relocation code in *RELOC.
14730 Leave both *STR and *RELOC alone when returning false. */
14733 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14735 const struct percent_op_match *percent_op;
14738 if (mips_opts.mips16)
14740 percent_op = mips16_percent_op;
14741 limit = ARRAY_SIZE (mips16_percent_op);
14745 percent_op = mips_percent_op;
14746 limit = ARRAY_SIZE (mips_percent_op);
14749 for (i = 0; i < limit; i++)
14750 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14752 int len = strlen (percent_op[i].str);
14754 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14757 *str += strlen (percent_op[i].str);
14758 *reloc = percent_op[i].reloc;
14760 /* Check whether the output BFD supports this relocation.
14761 If not, issue an error and fall back on something safe. */
14762 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14764 as_bad (_("relocation %s isn't supported by the current ABI"),
14765 percent_op[i].str);
14766 *reloc = BFD_RELOC_UNUSED;
14774 /* Parse string STR as a 16-bit relocatable operand. Store the
14775 expression in *EP and the relocations in the array starting
14776 at RELOC. Return the number of relocation operators used.
14778 On exit, EXPR_END points to the first character after the expression. */
14781 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14784 bfd_reloc_code_real_type reversed_reloc[3];
14785 size_t reloc_index, i;
14786 int crux_depth, str_depth;
14789 /* Search for the start of the main expression, recoding relocations
14790 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14791 of the main expression and with CRUX_DEPTH containing the number
14792 of open brackets at that point. */
14799 crux_depth = str_depth;
14801 /* Skip over whitespace and brackets, keeping count of the number
14803 while (*str == ' ' || *str == '\t' || *str == '(')
14808 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14809 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14811 my_getExpression (ep, crux);
14814 /* Match every open bracket. */
14815 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14819 if (crux_depth > 0)
14820 as_bad (_("unclosed '('"));
14824 if (reloc_index != 0)
14826 prev_reloc_op_frag = frag_now;
14827 for (i = 0; i < reloc_index; i++)
14828 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14831 return reloc_index;
14835 my_getExpression (expressionS *ep, char *str)
14839 save_in = input_line_pointer;
14840 input_line_pointer = str;
14842 expr_end = input_line_pointer;
14843 input_line_pointer = save_in;
14847 md_atof (int type, char *litP, int *sizeP)
14849 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14853 md_number_to_chars (char *buf, valueT val, int n)
14855 if (target_big_endian)
14856 number_to_chars_bigendian (buf, val, n);
14858 number_to_chars_littleendian (buf, val, n);
14861 static int support_64bit_objects(void)
14863 const char **list, **l;
14866 list = bfd_target_list ();
14867 for (l = list; *l != NULL; l++)
14868 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14869 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14871 yes = (*l != NULL);
14876 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14877 NEW_VALUE. Warn if another value was already specified. Note:
14878 we have to defer parsing the -march and -mtune arguments in order
14879 to handle 'from-abi' correctly, since the ABI might be specified
14880 in a later argument. */
14883 mips_set_option_string (const char **string_ptr, const char *new_value)
14885 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14886 as_warn (_("A different %s was already specified, is now %s"),
14887 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14890 *string_ptr = new_value;
14894 md_parse_option (int c, char *arg)
14898 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14899 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14901 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14902 c == mips_ases[i].option_on);
14908 case OPTION_CONSTRUCT_FLOATS:
14909 mips_disable_float_construction = 0;
14912 case OPTION_NO_CONSTRUCT_FLOATS:
14913 mips_disable_float_construction = 1;
14925 target_big_endian = 1;
14929 target_big_endian = 0;
14935 else if (arg[0] == '0')
14937 else if (arg[0] == '1')
14947 mips_debug = atoi (arg);
14951 file_mips_isa = ISA_MIPS1;
14955 file_mips_isa = ISA_MIPS2;
14959 file_mips_isa = ISA_MIPS3;
14963 file_mips_isa = ISA_MIPS4;
14967 file_mips_isa = ISA_MIPS5;
14970 case OPTION_MIPS32:
14971 file_mips_isa = ISA_MIPS32;
14974 case OPTION_MIPS32R2:
14975 file_mips_isa = ISA_MIPS32R2;
14978 case OPTION_MIPS64R2:
14979 file_mips_isa = ISA_MIPS64R2;
14982 case OPTION_MIPS64:
14983 file_mips_isa = ISA_MIPS64;
14987 mips_set_option_string (&mips_tune_string, arg);
14991 mips_set_option_string (&mips_arch_string, arg);
14995 mips_set_option_string (&mips_arch_string, "4650");
14996 mips_set_option_string (&mips_tune_string, "4650");
14999 case OPTION_NO_M4650:
15003 mips_set_option_string (&mips_arch_string, "4010");
15004 mips_set_option_string (&mips_tune_string, "4010");
15007 case OPTION_NO_M4010:
15011 mips_set_option_string (&mips_arch_string, "4100");
15012 mips_set_option_string (&mips_tune_string, "4100");
15015 case OPTION_NO_M4100:
15019 mips_set_option_string (&mips_arch_string, "3900");
15020 mips_set_option_string (&mips_tune_string, "3900");
15023 case OPTION_NO_M3900:
15026 case OPTION_MICROMIPS:
15027 if (mips_opts.mips16 == 1)
15029 as_bad (_("-mmicromips cannot be used with -mips16"));
15032 mips_opts.micromips = 1;
15033 mips_no_prev_insn ();
15036 case OPTION_NO_MICROMIPS:
15037 mips_opts.micromips = 0;
15038 mips_no_prev_insn ();
15041 case OPTION_MIPS16:
15042 if (mips_opts.micromips == 1)
15044 as_bad (_("-mips16 cannot be used with -micromips"));
15047 mips_opts.mips16 = 1;
15048 mips_no_prev_insn ();
15051 case OPTION_NO_MIPS16:
15052 mips_opts.mips16 = 0;
15053 mips_no_prev_insn ();
15056 case OPTION_FIX_24K:
15060 case OPTION_NO_FIX_24K:
15064 case OPTION_FIX_LOONGSON2F_JUMP:
15065 mips_fix_loongson2f_jump = TRUE;
15068 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15069 mips_fix_loongson2f_jump = FALSE;
15072 case OPTION_FIX_LOONGSON2F_NOP:
15073 mips_fix_loongson2f_nop = TRUE;
15076 case OPTION_NO_FIX_LOONGSON2F_NOP:
15077 mips_fix_loongson2f_nop = FALSE;
15080 case OPTION_FIX_VR4120:
15081 mips_fix_vr4120 = 1;
15084 case OPTION_NO_FIX_VR4120:
15085 mips_fix_vr4120 = 0;
15088 case OPTION_FIX_VR4130:
15089 mips_fix_vr4130 = 1;
15092 case OPTION_NO_FIX_VR4130:
15093 mips_fix_vr4130 = 0;
15096 case OPTION_FIX_CN63XXP1:
15097 mips_fix_cn63xxp1 = TRUE;
15100 case OPTION_NO_FIX_CN63XXP1:
15101 mips_fix_cn63xxp1 = FALSE;
15104 case OPTION_RELAX_BRANCH:
15105 mips_relax_branch = 1;
15108 case OPTION_NO_RELAX_BRANCH:
15109 mips_relax_branch = 0;
15112 case OPTION_INSN32:
15113 mips_opts.insn32 = TRUE;
15116 case OPTION_NO_INSN32:
15117 mips_opts.insn32 = FALSE;
15120 case OPTION_MSHARED:
15121 mips_in_shared = TRUE;
15124 case OPTION_MNO_SHARED:
15125 mips_in_shared = FALSE;
15128 case OPTION_MSYM32:
15129 mips_opts.sym32 = TRUE;
15132 case OPTION_MNO_SYM32:
15133 mips_opts.sym32 = FALSE;
15136 /* When generating ELF code, we permit -KPIC and -call_shared to
15137 select SVR4_PIC, and -non_shared to select no PIC. This is
15138 intended to be compatible with Irix 5. */
15139 case OPTION_CALL_SHARED:
15140 mips_pic = SVR4_PIC;
15141 mips_abicalls = TRUE;
15144 case OPTION_CALL_NONPIC:
15146 mips_abicalls = TRUE;
15149 case OPTION_NON_SHARED:
15151 mips_abicalls = FALSE;
15154 /* The -xgot option tells the assembler to use 32 bit offsets
15155 when accessing the got in SVR4_PIC mode. It is for Irix
15162 g_switch_value = atoi (arg);
15166 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15169 mips_abi = O32_ABI;
15173 mips_abi = N32_ABI;
15177 mips_abi = N64_ABI;
15178 if (!support_64bit_objects())
15179 as_fatal (_("No compiled in support for 64 bit object file format"));
15183 file_mips_gp32 = 1;
15187 file_mips_gp32 = 0;
15191 file_mips_fp32 = 1;
15195 file_mips_fp32 = 0;
15198 case OPTION_SINGLE_FLOAT:
15199 file_mips_single_float = 1;
15202 case OPTION_DOUBLE_FLOAT:
15203 file_mips_single_float = 0;
15206 case OPTION_SOFT_FLOAT:
15207 file_mips_soft_float = 1;
15210 case OPTION_HARD_FLOAT:
15211 file_mips_soft_float = 0;
15215 if (strcmp (arg, "32") == 0)
15216 mips_abi = O32_ABI;
15217 else if (strcmp (arg, "o64") == 0)
15218 mips_abi = O64_ABI;
15219 else if (strcmp (arg, "n32") == 0)
15220 mips_abi = N32_ABI;
15221 else if (strcmp (arg, "64") == 0)
15223 mips_abi = N64_ABI;
15224 if (! support_64bit_objects())
15225 as_fatal (_("No compiled in support for 64 bit object file "
15228 else if (strcmp (arg, "eabi") == 0)
15229 mips_abi = EABI_ABI;
15232 as_fatal (_("invalid abi -mabi=%s"), arg);
15237 case OPTION_M7000_HILO_FIX:
15238 mips_7000_hilo_fix = TRUE;
15241 case OPTION_MNO_7000_HILO_FIX:
15242 mips_7000_hilo_fix = FALSE;
15245 case OPTION_MDEBUG:
15246 mips_flag_mdebug = TRUE;
15249 case OPTION_NO_MDEBUG:
15250 mips_flag_mdebug = FALSE;
15254 mips_flag_pdr = TRUE;
15257 case OPTION_NO_PDR:
15258 mips_flag_pdr = FALSE;
15261 case OPTION_MVXWORKS_PIC:
15262 mips_pic = VXWORKS_PIC;
15266 if (strcmp (arg, "2008") == 0)
15267 mips_flag_nan2008 = TRUE;
15268 else if (strcmp (arg, "legacy") == 0)
15269 mips_flag_nan2008 = FALSE;
15272 as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
15281 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15286 /* Set up globals to generate code for the ISA or processor
15287 described by INFO. */
15290 mips_set_architecture (const struct mips_cpu_info *info)
15294 file_mips_arch = info->cpu;
15295 mips_opts.arch = info->cpu;
15296 mips_opts.isa = info->isa;
15301 /* Likewise for tuning. */
15304 mips_set_tune (const struct mips_cpu_info *info)
15307 mips_tune = info->cpu;
15312 mips_after_parse_args (void)
15314 const struct mips_cpu_info *arch_info = 0;
15315 const struct mips_cpu_info *tune_info = 0;
15317 /* GP relative stuff not working for PE */
15318 if (strncmp (TARGET_OS, "pe", 2) == 0)
15320 if (g_switch_seen && g_switch_value != 0)
15321 as_bad (_("-G not supported in this configuration."));
15322 g_switch_value = 0;
15325 if (mips_abi == NO_ABI)
15326 mips_abi = MIPS_DEFAULT_ABI;
15328 /* The following code determines the architecture and register size.
15329 Similar code was added to GCC 3.3 (see override_options() in
15330 config/mips/mips.c). The GAS and GCC code should be kept in sync
15331 as much as possible. */
15333 if (mips_arch_string != 0)
15334 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15336 if (file_mips_isa != ISA_UNKNOWN)
15338 /* Handle -mipsN. At this point, file_mips_isa contains the
15339 ISA level specified by -mipsN, while arch_info->isa contains
15340 the -march selection (if any). */
15341 if (arch_info != 0)
15343 /* -march takes precedence over -mipsN, since it is more descriptive.
15344 There's no harm in specifying both as long as the ISA levels
15346 if (file_mips_isa != arch_info->isa)
15347 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15348 mips_cpu_info_from_isa (file_mips_isa)->name,
15349 mips_cpu_info_from_isa (arch_info->isa)->name);
15352 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15355 if (arch_info == 0)
15357 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15358 gas_assert (arch_info);
15361 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15362 as_bad (_("-march=%s is not compatible with the selected ABI"),
15365 mips_set_architecture (arch_info);
15367 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15368 if (mips_tune_string != 0)
15369 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15371 if (tune_info == 0)
15372 mips_set_tune (arch_info);
15374 mips_set_tune (tune_info);
15376 if (file_mips_gp32 >= 0)
15378 /* The user specified the size of the integer registers. Make sure
15379 it agrees with the ABI and ISA. */
15380 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15381 as_bad (_("-mgp64 used with a 32-bit processor"));
15382 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15383 as_bad (_("-mgp32 used with a 64-bit ABI"));
15384 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15385 as_bad (_("-mgp64 used with a 32-bit ABI"));
15389 /* Infer the integer register size from the ABI and processor.
15390 Restrict ourselves to 32-bit registers if that's all the
15391 processor has, or if the ABI cannot handle 64-bit registers. */
15392 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15393 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15396 switch (file_mips_fp32)
15400 /* No user specified float register size.
15401 ??? GAS treats single-float processors as though they had 64-bit
15402 float registers (although it complains when double-precision
15403 instructions are used). As things stand, saying they have 32-bit
15404 registers would lead to spurious "register must be even" messages.
15405 So here we assume float registers are never smaller than the
15407 if (file_mips_gp32 == 0)
15408 /* 64-bit integer registers implies 64-bit float registers. */
15409 file_mips_fp32 = 0;
15410 else if ((mips_opts.ase & FP64_ASES)
15411 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15412 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15413 file_mips_fp32 = 0;
15415 /* 32-bit float registers. */
15416 file_mips_fp32 = 1;
15419 /* The user specified the size of the float registers. Check if it
15420 agrees with the ABI and ISA. */
15422 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15423 as_bad (_("-mfp64 used with a 32-bit fpu"));
15424 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15425 && !ISA_HAS_MXHC1 (mips_opts.isa))
15426 as_warn (_("-mfp64 used with a 32-bit ABI"));
15429 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15430 as_warn (_("-mfp32 used with a 64-bit ABI"));
15434 /* End of GCC-shared inference code. */
15436 /* This flag is set when we have a 64-bit capable CPU but use only
15437 32-bit wide registers. Note that EABI does not use it. */
15438 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15439 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15440 || mips_abi == O32_ABI))
15441 mips_32bitmode = 1;
15443 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15444 as_bad (_("trap exception not supported at ISA 1"));
15446 /* If the selected architecture includes support for ASEs, enable
15447 generation of code for them. */
15448 if (mips_opts.mips16 == -1)
15449 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15450 if (mips_opts.micromips == -1)
15451 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15453 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15454 ASEs from being selected implicitly. */
15455 if (file_mips_fp32 == 1)
15456 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15458 /* If the user didn't explicitly select or deselect a particular ASE,
15459 use the default setting for the CPU. */
15460 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15462 file_mips_isa = mips_opts.isa;
15463 file_ase = mips_opts.ase;
15464 mips_opts.gp32 = file_mips_gp32;
15465 mips_opts.fp32 = file_mips_fp32;
15466 mips_opts.soft_float = file_mips_soft_float;
15467 mips_opts.single_float = file_mips_single_float;
15469 mips_check_isa_supports_ases ();
15471 if (mips_flag_mdebug < 0)
15472 mips_flag_mdebug = 0;
15476 mips_init_after_args (void)
15478 /* initialize opcodes */
15479 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15480 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15484 md_pcrel_from (fixS *fixP)
15486 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15487 switch (fixP->fx_r_type)
15489 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15490 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15491 /* Return the address of the delay slot. */
15494 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15495 case BFD_RELOC_MICROMIPS_JMP:
15496 case BFD_RELOC_16_PCREL_S2:
15497 case BFD_RELOC_MIPS_JMP:
15498 /* Return the address of the delay slot. */
15501 case BFD_RELOC_32_PCREL:
15505 /* We have no relocation type for PC relative MIPS16 instructions. */
15506 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15507 as_bad_where (fixP->fx_file, fixP->fx_line,
15508 _("PC relative MIPS16 instruction references a different section"));
15513 /* This is called before the symbol table is processed. In order to
15514 work with gcc when using mips-tfile, we must keep all local labels.
15515 However, in other cases, we want to discard them. If we were
15516 called with -g, but we didn't see any debugging information, it may
15517 mean that gcc is smuggling debugging information through to
15518 mips-tfile, in which case we must generate all local labels. */
15521 mips_frob_file_before_adjust (void)
15523 #ifndef NO_ECOFF_DEBUGGING
15524 if (ECOFF_DEBUGGING
15526 && ! ecoff_debugging_seen)
15527 flag_keep_locals = 1;
15531 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15532 the corresponding LO16 reloc. This is called before md_apply_fix and
15533 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15534 relocation operators.
15536 For our purposes, a %lo() expression matches a %got() or %hi()
15539 (a) it refers to the same symbol; and
15540 (b) the offset applied in the %lo() expression is no lower than
15541 the offset applied in the %got() or %hi().
15543 (b) allows us to cope with code like:
15546 lh $4,%lo(foo+2)($4)
15548 ...which is legal on RELA targets, and has a well-defined behaviour
15549 if the user knows that adding 2 to "foo" will not induce a carry to
15552 When several %lo()s match a particular %got() or %hi(), we use the
15553 following rules to distinguish them:
15555 (1) %lo()s with smaller offsets are a better match than %lo()s with
15558 (2) %lo()s with no matching %got() or %hi() are better than those
15559 that already have a matching %got() or %hi().
15561 (3) later %lo()s are better than earlier %lo()s.
15563 These rules are applied in order.
15565 (1) means, among other things, that %lo()s with identical offsets are
15566 chosen if they exist.
15568 (2) means that we won't associate several high-part relocations with
15569 the same low-part relocation unless there's no alternative. Having
15570 several high parts for the same low part is a GNU extension; this rule
15571 allows careful users to avoid it.
15573 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15574 with the last high-part relocation being at the front of the list.
15575 It therefore makes sense to choose the last matching low-part
15576 relocation, all other things being equal. It's also easier
15577 to code that way. */
15580 mips_frob_file (void)
15582 struct mips_hi_fixup *l;
15583 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15585 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15587 segment_info_type *seginfo;
15588 bfd_boolean matched_lo_p;
15589 fixS **hi_pos, **lo_pos, **pos;
15591 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15593 /* If a GOT16 relocation turns out to be against a global symbol,
15594 there isn't supposed to be a matching LO. Ignore %gots against
15595 constants; we'll report an error for those later. */
15596 if (got16_reloc_p (l->fixp->fx_r_type)
15597 && !(l->fixp->fx_addsy
15598 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15601 /* Check quickly whether the next fixup happens to be a matching %lo. */
15602 if (fixup_has_matching_lo_p (l->fixp))
15605 seginfo = seg_info (l->seg);
15607 /* Set HI_POS to the position of this relocation in the chain.
15608 Set LO_POS to the position of the chosen low-part relocation.
15609 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15610 relocation that matches an immediately-preceding high-part
15614 matched_lo_p = FALSE;
15615 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15617 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15619 if (*pos == l->fixp)
15622 if ((*pos)->fx_r_type == looking_for_rtype
15623 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15624 && (*pos)->fx_offset >= l->fixp->fx_offset
15626 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15628 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15631 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15632 && fixup_has_matching_lo_p (*pos));
15635 /* If we found a match, remove the high-part relocation from its
15636 current position and insert it before the low-part relocation.
15637 Make the offsets match so that fixup_has_matching_lo_p()
15640 We don't warn about unmatched high-part relocations since some
15641 versions of gcc have been known to emit dead "lui ...%hi(...)"
15643 if (lo_pos != NULL)
15645 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15646 if (l->fixp->fx_next != *lo_pos)
15648 *hi_pos = l->fixp->fx_next;
15649 l->fixp->fx_next = *lo_pos;
15657 mips_force_relocation (fixS *fixp)
15659 if (generic_force_reloc (fixp))
15662 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15663 so that the linker relaxation can update targets. */
15664 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15665 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15666 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15672 /* Read the instruction associated with RELOC from BUF. */
15674 static unsigned int
15675 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15677 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15678 return read_compressed_insn (buf, 4);
15680 return read_insn (buf);
15683 /* Write instruction INSN to BUF, given that it has been relocated
15687 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15688 unsigned long insn)
15690 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15691 write_compressed_insn (buf, insn, 4);
15693 write_insn (buf, insn);
15696 /* Apply a fixup to the object file. */
15699 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15702 unsigned long insn;
15703 reloc_howto_type *howto;
15705 /* We ignore generic BFD relocations we don't know about. */
15706 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15710 gas_assert (fixP->fx_size == 2
15711 || fixP->fx_size == 4
15712 || fixP->fx_r_type == BFD_RELOC_16
15713 || fixP->fx_r_type == BFD_RELOC_64
15714 || fixP->fx_r_type == BFD_RELOC_CTOR
15715 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15716 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15717 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15718 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15719 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15721 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15723 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15724 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15725 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15726 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15727 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15729 /* Don't treat parts of a composite relocation as done. There are two
15732 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15733 should nevertheless be emitted if the first part is.
15735 (2) In normal usage, composite relocations are never assembly-time
15736 constants. The easiest way of dealing with the pathological
15737 exceptions is to generate a relocation against STN_UNDEF and
15738 leave everything up to the linker. */
15739 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15742 switch (fixP->fx_r_type)
15744 case BFD_RELOC_MIPS_TLS_GD:
15745 case BFD_RELOC_MIPS_TLS_LDM:
15746 case BFD_RELOC_MIPS_TLS_DTPREL32:
15747 case BFD_RELOC_MIPS_TLS_DTPREL64:
15748 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15749 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15750 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15751 case BFD_RELOC_MIPS_TLS_TPREL32:
15752 case BFD_RELOC_MIPS_TLS_TPREL64:
15753 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15754 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15755 case BFD_RELOC_MICROMIPS_TLS_GD:
15756 case BFD_RELOC_MICROMIPS_TLS_LDM:
15757 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15758 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15759 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15760 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15761 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15762 case BFD_RELOC_MIPS16_TLS_GD:
15763 case BFD_RELOC_MIPS16_TLS_LDM:
15764 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15765 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15766 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15767 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15768 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15769 if (!fixP->fx_addsy)
15771 as_bad_where (fixP->fx_file, fixP->fx_line,
15772 _("TLS relocation against a constant"));
15775 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15778 case BFD_RELOC_MIPS_JMP:
15779 case BFD_RELOC_MIPS_SHIFT5:
15780 case BFD_RELOC_MIPS_SHIFT6:
15781 case BFD_RELOC_MIPS_GOT_DISP:
15782 case BFD_RELOC_MIPS_GOT_PAGE:
15783 case BFD_RELOC_MIPS_GOT_OFST:
15784 case BFD_RELOC_MIPS_SUB:
15785 case BFD_RELOC_MIPS_INSERT_A:
15786 case BFD_RELOC_MIPS_INSERT_B:
15787 case BFD_RELOC_MIPS_DELETE:
15788 case BFD_RELOC_MIPS_HIGHEST:
15789 case BFD_RELOC_MIPS_HIGHER:
15790 case BFD_RELOC_MIPS_SCN_DISP:
15791 case BFD_RELOC_MIPS_REL16:
15792 case BFD_RELOC_MIPS_RELGOT:
15793 case BFD_RELOC_MIPS_JALR:
15794 case BFD_RELOC_HI16:
15795 case BFD_RELOC_HI16_S:
15796 case BFD_RELOC_LO16:
15797 case BFD_RELOC_GPREL16:
15798 case BFD_RELOC_MIPS_LITERAL:
15799 case BFD_RELOC_MIPS_CALL16:
15800 case BFD_RELOC_MIPS_GOT16:
15801 case BFD_RELOC_GPREL32:
15802 case BFD_RELOC_MIPS_GOT_HI16:
15803 case BFD_RELOC_MIPS_GOT_LO16:
15804 case BFD_RELOC_MIPS_CALL_HI16:
15805 case BFD_RELOC_MIPS_CALL_LO16:
15806 case BFD_RELOC_MIPS16_GPREL:
15807 case BFD_RELOC_MIPS16_GOT16:
15808 case BFD_RELOC_MIPS16_CALL16:
15809 case BFD_RELOC_MIPS16_HI16:
15810 case BFD_RELOC_MIPS16_HI16_S:
15811 case BFD_RELOC_MIPS16_LO16:
15812 case BFD_RELOC_MIPS16_JMP:
15813 case BFD_RELOC_MICROMIPS_JMP:
15814 case BFD_RELOC_MICROMIPS_GOT_DISP:
15815 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15816 case BFD_RELOC_MICROMIPS_GOT_OFST:
15817 case BFD_RELOC_MICROMIPS_SUB:
15818 case BFD_RELOC_MICROMIPS_HIGHEST:
15819 case BFD_RELOC_MICROMIPS_HIGHER:
15820 case BFD_RELOC_MICROMIPS_SCN_DISP:
15821 case BFD_RELOC_MICROMIPS_JALR:
15822 case BFD_RELOC_MICROMIPS_HI16:
15823 case BFD_RELOC_MICROMIPS_HI16_S:
15824 case BFD_RELOC_MICROMIPS_LO16:
15825 case BFD_RELOC_MICROMIPS_GPREL16:
15826 case BFD_RELOC_MICROMIPS_LITERAL:
15827 case BFD_RELOC_MICROMIPS_CALL16:
15828 case BFD_RELOC_MICROMIPS_GOT16:
15829 case BFD_RELOC_MICROMIPS_GOT_HI16:
15830 case BFD_RELOC_MICROMIPS_GOT_LO16:
15831 case BFD_RELOC_MICROMIPS_CALL_HI16:
15832 case BFD_RELOC_MICROMIPS_CALL_LO16:
15833 case BFD_RELOC_MIPS_EH:
15838 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15840 insn = read_reloc_insn (buf, fixP->fx_r_type);
15841 if (mips16_reloc_p (fixP->fx_r_type))
15842 insn |= mips16_immed_extend (value, 16);
15844 insn |= (value & 0xffff);
15845 write_reloc_insn (buf, fixP->fx_r_type, insn);
15848 as_bad_where (fixP->fx_file, fixP->fx_line,
15849 _("Unsupported constant in relocation"));
15854 /* This is handled like BFD_RELOC_32, but we output a sign
15855 extended value if we are only 32 bits. */
15858 if (8 <= sizeof (valueT))
15859 md_number_to_chars (buf, *valP, 8);
15864 if ((*valP & 0x80000000) != 0)
15868 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15869 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15874 case BFD_RELOC_RVA:
15876 case BFD_RELOC_32_PCREL:
15878 /* If we are deleting this reloc entry, we must fill in the
15879 value now. This can happen if we have a .word which is not
15880 resolved when it appears but is later defined. */
15882 md_number_to_chars (buf, *valP, fixP->fx_size);
15885 case BFD_RELOC_16_PCREL_S2:
15886 if ((*valP & 0x3) != 0)
15887 as_bad_where (fixP->fx_file, fixP->fx_line,
15888 _("Branch to misaligned address (%lx)"), (long) *valP);
15890 /* We need to save the bits in the instruction since fixup_segment()
15891 might be deleting the relocation entry (i.e., a branch within
15892 the current segment). */
15893 if (! fixP->fx_done)
15896 /* Update old instruction data. */
15897 insn = read_insn (buf);
15899 if (*valP + 0x20000 <= 0x3ffff)
15901 insn |= (*valP >> 2) & 0xffff;
15902 write_insn (buf, insn);
15904 else if (mips_pic == NO_PIC
15906 && fixP->fx_frag->fr_address >= text_section->vma
15907 && (fixP->fx_frag->fr_address
15908 < text_section->vma + bfd_get_section_size (text_section))
15909 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15910 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15911 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15913 /* The branch offset is too large. If this is an
15914 unconditional branch, and we are not generating PIC code,
15915 we can convert it to an absolute jump instruction. */
15916 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15917 insn = 0x0c000000; /* jal */
15919 insn = 0x08000000; /* j */
15920 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15922 fixP->fx_addsy = section_symbol (text_section);
15923 *valP += md_pcrel_from (fixP);
15924 write_insn (buf, insn);
15928 /* If we got here, we have branch-relaxation disabled,
15929 and there's nothing we can do to fix this instruction
15930 without turning it into a longer sequence. */
15931 as_bad_where (fixP->fx_file, fixP->fx_line,
15932 _("Branch out of range"));
15936 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15937 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15938 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15939 /* We adjust the offset back to even. */
15940 if ((*valP & 0x1) != 0)
15943 if (! fixP->fx_done)
15946 /* Should never visit here, because we keep the relocation. */
15950 case BFD_RELOC_VTABLE_INHERIT:
15953 && !S_IS_DEFINED (fixP->fx_addsy)
15954 && !S_IS_WEAK (fixP->fx_addsy))
15955 S_SET_WEAK (fixP->fx_addsy);
15958 case BFD_RELOC_VTABLE_ENTRY:
15966 /* Remember value for tc_gen_reloc. */
15967 fixP->fx_addnumber = *valP;
15977 name = input_line_pointer;
15978 c = get_symbol_end ();
15979 p = (symbolS *) symbol_find_or_make (name);
15980 *input_line_pointer = c;
15984 /* Align the current frag to a given power of two. If a particular
15985 fill byte should be used, FILL points to an integer that contains
15986 that byte, otherwise FILL is null.
15988 This function used to have the comment:
15990 The MIPS assembler also automatically adjusts any preceding label.
15992 The implementation therefore applied the adjustment to a maximum of
15993 one label. However, other label adjustments are applied to batches
15994 of labels, and adjusting just one caused problems when new labels
15995 were added for the sake of debugging or unwind information.
15996 We therefore adjust all preceding labels (given as LABELS) instead. */
15999 mips_align (int to, int *fill, struct insn_label_list *labels)
16001 mips_emit_delays ();
16002 mips_record_compressed_mode ();
16003 if (fill == NULL && subseg_text_p (now_seg))
16004 frag_align_code (to, 0);
16006 frag_align (to, fill ? *fill : 0, 0);
16007 record_alignment (now_seg, to);
16008 mips_move_labels (labels, FALSE);
16011 /* Align to a given power of two. .align 0 turns off the automatic
16012 alignment used by the data creating pseudo-ops. */
16015 s_align (int x ATTRIBUTE_UNUSED)
16017 int temp, fill_value, *fill_ptr;
16018 long max_alignment = 28;
16020 /* o Note that the assembler pulls down any immediately preceding label
16021 to the aligned address.
16022 o It's not documented but auto alignment is reinstated by
16023 a .align pseudo instruction.
16024 o Note also that after auto alignment is turned off the mips assembler
16025 issues an error on attempt to assemble an improperly aligned data item.
16028 temp = get_absolute_expression ();
16029 if (temp > max_alignment)
16030 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16033 as_warn (_("Alignment negative: 0 assumed."));
16036 if (*input_line_pointer == ',')
16038 ++input_line_pointer;
16039 fill_value = get_absolute_expression ();
16040 fill_ptr = &fill_value;
16046 segment_info_type *si = seg_info (now_seg);
16047 struct insn_label_list *l = si->label_list;
16048 /* Auto alignment should be switched on by next section change. */
16050 mips_align (temp, fill_ptr, l);
16057 demand_empty_rest_of_line ();
16061 s_change_sec (int sec)
16065 /* The ELF backend needs to know that we are changing sections, so
16066 that .previous works correctly. We could do something like check
16067 for an obj_section_change_hook macro, but that might be confusing
16068 as it would not be appropriate to use it in the section changing
16069 functions in read.c, since obj-elf.c intercepts those. FIXME:
16070 This should be cleaner, somehow. */
16071 obj_elf_section_change_hook ();
16073 mips_emit_delays ();
16084 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16085 demand_empty_rest_of_line ();
16089 seg = subseg_new (RDATA_SECTION_NAME,
16090 (subsegT) get_absolute_expression ());
16091 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16092 | SEC_READONLY | SEC_RELOC
16094 if (strncmp (TARGET_OS, "elf", 3) != 0)
16095 record_alignment (seg, 4);
16096 demand_empty_rest_of_line ();
16100 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16101 bfd_set_section_flags (stdoutput, seg,
16102 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16103 if (strncmp (TARGET_OS, "elf", 3) != 0)
16104 record_alignment (seg, 4);
16105 demand_empty_rest_of_line ();
16109 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16110 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16111 if (strncmp (TARGET_OS, "elf", 3) != 0)
16112 record_alignment (seg, 4);
16113 demand_empty_rest_of_line ();
16121 s_change_section (int ignore ATTRIBUTE_UNUSED)
16123 char *section_name;
16128 int section_entry_size;
16129 int section_alignment;
16131 section_name = input_line_pointer;
16132 c = get_symbol_end ();
16134 next_c = *(input_line_pointer + 1);
16136 /* Do we have .section Name<,"flags">? */
16137 if (c != ',' || (c == ',' && next_c == '"'))
16139 /* just after name is now '\0'. */
16140 *input_line_pointer = c;
16141 input_line_pointer = section_name;
16142 obj_elf_section (ignore);
16145 input_line_pointer++;
16147 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16149 section_type = get_absolute_expression ();
16152 if (*input_line_pointer++ == ',')
16153 section_flag = get_absolute_expression ();
16156 if (*input_line_pointer++ == ',')
16157 section_entry_size = get_absolute_expression ();
16159 section_entry_size = 0;
16160 if (*input_line_pointer++ == ',')
16161 section_alignment = get_absolute_expression ();
16163 section_alignment = 0;
16164 /* FIXME: really ignore? */
16165 (void) section_alignment;
16167 section_name = xstrdup (section_name);
16169 /* When using the generic form of .section (as implemented by obj-elf.c),
16170 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16171 traditionally had to fall back on the more common @progbits instead.
16173 There's nothing really harmful in this, since bfd will correct
16174 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16175 means that, for backwards compatibility, the special_section entries
16176 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16178 Even so, we shouldn't force users of the MIPS .section syntax to
16179 incorrectly label the sections as SHT_PROGBITS. The best compromise
16180 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16181 generic type-checking code. */
16182 if (section_type == SHT_MIPS_DWARF)
16183 section_type = SHT_PROGBITS;
16185 obj_elf_change_section (section_name, section_type, section_flag,
16186 section_entry_size, 0, 0, 0);
16188 if (now_seg->name != section_name)
16189 free (section_name);
16193 mips_enable_auto_align (void)
16199 s_cons (int log_size)
16201 segment_info_type *si = seg_info (now_seg);
16202 struct insn_label_list *l = si->label_list;
16204 mips_emit_delays ();
16205 if (log_size > 0 && auto_align)
16206 mips_align (log_size, 0, l);
16207 cons (1 << log_size);
16208 mips_clear_insn_labels ();
16212 s_float_cons (int type)
16214 segment_info_type *si = seg_info (now_seg);
16215 struct insn_label_list *l = si->label_list;
16217 mips_emit_delays ();
16222 mips_align (3, 0, l);
16224 mips_align (2, 0, l);
16228 mips_clear_insn_labels ();
16231 /* Handle .globl. We need to override it because on Irix 5 you are
16234 where foo is an undefined symbol, to mean that foo should be
16235 considered to be the address of a function. */
16238 s_mips_globl (int x ATTRIBUTE_UNUSED)
16247 name = input_line_pointer;
16248 c = get_symbol_end ();
16249 symbolP = symbol_find_or_make (name);
16250 S_SET_EXTERNAL (symbolP);
16252 *input_line_pointer = c;
16253 SKIP_WHITESPACE ();
16255 /* On Irix 5, every global symbol that is not explicitly labelled as
16256 being a function is apparently labelled as being an object. */
16259 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16260 && (*input_line_pointer != ','))
16265 secname = input_line_pointer;
16266 c = get_symbol_end ();
16267 sec = bfd_get_section_by_name (stdoutput, secname);
16269 as_bad (_("%s: no such section"), secname);
16270 *input_line_pointer = c;
16272 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16273 flag = BSF_FUNCTION;
16276 symbol_get_bfdsym (symbolP)->flags |= flag;
16278 c = *input_line_pointer;
16281 input_line_pointer++;
16282 SKIP_WHITESPACE ();
16283 if (is_end_of_line[(unsigned char) *input_line_pointer])
16289 demand_empty_rest_of_line ();
16293 s_option (int x ATTRIBUTE_UNUSED)
16298 opt = input_line_pointer;
16299 c = get_symbol_end ();
16303 /* FIXME: What does this mean? */
16305 else if (strncmp (opt, "pic", 3) == 0)
16309 i = atoi (opt + 3);
16314 mips_pic = SVR4_PIC;
16315 mips_abicalls = TRUE;
16318 as_bad (_(".option pic%d not supported"), i);
16320 if (mips_pic == SVR4_PIC)
16322 if (g_switch_seen && g_switch_value != 0)
16323 as_warn (_("-G may not be used with SVR4 PIC code"));
16324 g_switch_value = 0;
16325 bfd_set_gp_size (stdoutput, 0);
16329 as_warn (_("Unrecognized option \"%s\""), opt);
16331 *input_line_pointer = c;
16332 demand_empty_rest_of_line ();
16335 /* This structure is used to hold a stack of .set values. */
16337 struct mips_option_stack
16339 struct mips_option_stack *next;
16340 struct mips_set_options options;
16343 static struct mips_option_stack *mips_opts_stack;
16345 /* Handle the .set pseudo-op. */
16348 s_mipsset (int x ATTRIBUTE_UNUSED)
16350 char *name = input_line_pointer, ch;
16351 const struct mips_ase *ase;
16353 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16354 ++input_line_pointer;
16355 ch = *input_line_pointer;
16356 *input_line_pointer = '\0';
16358 if (strcmp (name, "reorder") == 0)
16360 if (mips_opts.noreorder)
16363 else if (strcmp (name, "noreorder") == 0)
16365 if (!mips_opts.noreorder)
16366 start_noreorder ();
16368 else if (strncmp (name, "at=", 3) == 0)
16370 char *s = name + 3;
16372 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16373 as_bad (_("Unrecognized register name `%s'"), s);
16375 else if (strcmp (name, "at") == 0)
16377 mips_opts.at = ATREG;
16379 else if (strcmp (name, "noat") == 0)
16381 mips_opts.at = ZERO;
16383 else if (strcmp (name, "macro") == 0)
16385 mips_opts.warn_about_macros = 0;
16387 else if (strcmp (name, "nomacro") == 0)
16389 if (mips_opts.noreorder == 0)
16390 as_bad (_("`noreorder' must be set before `nomacro'"));
16391 mips_opts.warn_about_macros = 1;
16393 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16395 mips_opts.nomove = 0;
16397 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16399 mips_opts.nomove = 1;
16401 else if (strcmp (name, "bopt") == 0)
16403 mips_opts.nobopt = 0;
16405 else if (strcmp (name, "nobopt") == 0)
16407 mips_opts.nobopt = 1;
16409 else if (strcmp (name, "gp=default") == 0)
16410 mips_opts.gp32 = file_mips_gp32;
16411 else if (strcmp (name, "gp=32") == 0)
16412 mips_opts.gp32 = 1;
16413 else if (strcmp (name, "gp=64") == 0)
16415 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16416 as_warn (_("%s isa does not support 64-bit registers"),
16417 mips_cpu_info_from_isa (mips_opts.isa)->name);
16418 mips_opts.gp32 = 0;
16420 else if (strcmp (name, "fp=default") == 0)
16421 mips_opts.fp32 = file_mips_fp32;
16422 else if (strcmp (name, "fp=32") == 0)
16423 mips_opts.fp32 = 1;
16424 else if (strcmp (name, "fp=64") == 0)
16426 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16427 as_warn (_("%s isa does not support 64-bit floating point registers"),
16428 mips_cpu_info_from_isa (mips_opts.isa)->name);
16429 mips_opts.fp32 = 0;
16431 else if (strcmp (name, "softfloat") == 0)
16432 mips_opts.soft_float = 1;
16433 else if (strcmp (name, "hardfloat") == 0)
16434 mips_opts.soft_float = 0;
16435 else if (strcmp (name, "singlefloat") == 0)
16436 mips_opts.single_float = 1;
16437 else if (strcmp (name, "doublefloat") == 0)
16438 mips_opts.single_float = 0;
16439 else if (strcmp (name, "mips16") == 0
16440 || strcmp (name, "MIPS-16") == 0)
16442 if (mips_opts.micromips == 1)
16443 as_fatal (_("`mips16' cannot be used with `micromips'"));
16444 mips_opts.mips16 = 1;
16446 else if (strcmp (name, "nomips16") == 0
16447 || strcmp (name, "noMIPS-16") == 0)
16448 mips_opts.mips16 = 0;
16449 else if (strcmp (name, "micromips") == 0)
16451 if (mips_opts.mips16 == 1)
16452 as_fatal (_("`micromips' cannot be used with `mips16'"));
16453 mips_opts.micromips = 1;
16455 else if (strcmp (name, "nomicromips") == 0)
16456 mips_opts.micromips = 0;
16457 else if (name[0] == 'n'
16459 && (ase = mips_lookup_ase (name + 2)))
16460 mips_set_ase (ase, FALSE);
16461 else if ((ase = mips_lookup_ase (name)))
16462 mips_set_ase (ase, TRUE);
16463 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16467 /* Permit the user to change the ISA and architecture on the fly.
16468 Needless to say, misuse can cause serious problems. */
16469 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16472 mips_opts.isa = file_mips_isa;
16473 mips_opts.arch = file_mips_arch;
16475 else if (strncmp (name, "arch=", 5) == 0)
16477 const struct mips_cpu_info *p;
16479 p = mips_parse_cpu("internal use", name + 5);
16481 as_bad (_("unknown architecture %s"), name + 5);
16484 mips_opts.arch = p->cpu;
16485 mips_opts.isa = p->isa;
16488 else if (strncmp (name, "mips", 4) == 0)
16490 const struct mips_cpu_info *p;
16492 p = mips_parse_cpu("internal use", name);
16494 as_bad (_("unknown ISA level %s"), name + 4);
16497 mips_opts.arch = p->cpu;
16498 mips_opts.isa = p->isa;
16502 as_bad (_("unknown ISA or architecture %s"), name);
16504 switch (mips_opts.isa)
16512 mips_opts.gp32 = 1;
16513 mips_opts.fp32 = 1;
16520 mips_opts.gp32 = 0;
16521 if (mips_opts.arch == CPU_R5900)
16523 mips_opts.fp32 = 1;
16527 mips_opts.fp32 = 0;
16531 as_bad (_("unknown ISA level %s"), name + 4);
16536 mips_opts.gp32 = file_mips_gp32;
16537 mips_opts.fp32 = file_mips_fp32;
16540 else if (strcmp (name, "autoextend") == 0)
16541 mips_opts.noautoextend = 0;
16542 else if (strcmp (name, "noautoextend") == 0)
16543 mips_opts.noautoextend = 1;
16544 else if (strcmp (name, "insn32") == 0)
16545 mips_opts.insn32 = TRUE;
16546 else if (strcmp (name, "noinsn32") == 0)
16547 mips_opts.insn32 = FALSE;
16548 else if (strcmp (name, "push") == 0)
16550 struct mips_option_stack *s;
16552 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16553 s->next = mips_opts_stack;
16554 s->options = mips_opts;
16555 mips_opts_stack = s;
16557 else if (strcmp (name, "pop") == 0)
16559 struct mips_option_stack *s;
16561 s = mips_opts_stack;
16563 as_bad (_(".set pop with no .set push"));
16566 /* If we're changing the reorder mode we need to handle
16567 delay slots correctly. */
16568 if (s->options.noreorder && ! mips_opts.noreorder)
16569 start_noreorder ();
16570 else if (! s->options.noreorder && mips_opts.noreorder)
16573 mips_opts = s->options;
16574 mips_opts_stack = s->next;
16578 else if (strcmp (name, "sym32") == 0)
16579 mips_opts.sym32 = TRUE;
16580 else if (strcmp (name, "nosym32") == 0)
16581 mips_opts.sym32 = FALSE;
16582 else if (strchr (name, ','))
16584 /* Generic ".set" directive; use the generic handler. */
16585 *input_line_pointer = ch;
16586 input_line_pointer = name;
16592 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16594 mips_check_isa_supports_ases ();
16595 *input_line_pointer = ch;
16596 demand_empty_rest_of_line ();
16599 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16600 .option pic2. It means to generate SVR4 PIC calls. */
16603 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16605 mips_pic = SVR4_PIC;
16606 mips_abicalls = TRUE;
16608 if (g_switch_seen && g_switch_value != 0)
16609 as_warn (_("-G may not be used with SVR4 PIC code"));
16610 g_switch_value = 0;
16612 bfd_set_gp_size (stdoutput, 0);
16613 demand_empty_rest_of_line ();
16616 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16617 PIC code. It sets the $gp register for the function based on the
16618 function address, which is in the register named in the argument.
16619 This uses a relocation against _gp_disp, which is handled specially
16620 by the linker. The result is:
16621 lui $gp,%hi(_gp_disp)
16622 addiu $gp,$gp,%lo(_gp_disp)
16623 addu $gp,$gp,.cpload argument
16624 The .cpload argument is normally $25 == $t9.
16626 The -mno-shared option changes this to:
16627 lui $gp,%hi(__gnu_local_gp)
16628 addiu $gp,$gp,%lo(__gnu_local_gp)
16629 and the argument is ignored. This saves an instruction, but the
16630 resulting code is not position independent; it uses an absolute
16631 address for __gnu_local_gp. Thus code assembled with -mno-shared
16632 can go into an ordinary executable, but not into a shared library. */
16635 s_cpload (int ignore ATTRIBUTE_UNUSED)
16641 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16642 .cpload is ignored. */
16643 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16649 if (mips_opts.mips16)
16651 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16652 ignore_rest_of_line ();
16656 /* .cpload should be in a .set noreorder section. */
16657 if (mips_opts.noreorder == 0)
16658 as_warn (_(".cpload not in noreorder section"));
16660 reg = tc_get_register (0);
16662 /* If we need to produce a 64-bit address, we are better off using
16663 the default instruction sequence. */
16664 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16666 ex.X_op = O_symbol;
16667 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16669 ex.X_op_symbol = NULL;
16670 ex.X_add_number = 0;
16672 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16673 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16675 mips_mark_labels ();
16676 mips_assembling_insn = TRUE;
16679 macro_build_lui (&ex, mips_gp_register);
16680 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16681 mips_gp_register, BFD_RELOC_LO16);
16683 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16684 mips_gp_register, reg);
16687 mips_assembling_insn = FALSE;
16688 demand_empty_rest_of_line ();
16691 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16692 .cpsetup $reg1, offset|$reg2, label
16694 If offset is given, this results in:
16695 sd $gp, offset($sp)
16696 lui $gp, %hi(%neg(%gp_rel(label)))
16697 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16698 daddu $gp, $gp, $reg1
16700 If $reg2 is given, this results in:
16701 daddu $reg2, $gp, $0
16702 lui $gp, %hi(%neg(%gp_rel(label)))
16703 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16704 daddu $gp, $gp, $reg1
16705 $reg1 is normally $25 == $t9.
16707 The -mno-shared option replaces the last three instructions with
16709 addiu $gp,$gp,%lo(_gp) */
16712 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16714 expressionS ex_off;
16715 expressionS ex_sym;
16718 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16719 We also need NewABI support. */
16720 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16726 if (mips_opts.mips16)
16728 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16729 ignore_rest_of_line ();
16733 reg1 = tc_get_register (0);
16734 SKIP_WHITESPACE ();
16735 if (*input_line_pointer != ',')
16737 as_bad (_("missing argument separator ',' for .cpsetup"));
16741 ++input_line_pointer;
16742 SKIP_WHITESPACE ();
16743 if (*input_line_pointer == '$')
16745 mips_cpreturn_register = tc_get_register (0);
16746 mips_cpreturn_offset = -1;
16750 mips_cpreturn_offset = get_absolute_expression ();
16751 mips_cpreturn_register = -1;
16753 SKIP_WHITESPACE ();
16754 if (*input_line_pointer != ',')
16756 as_bad (_("missing argument separator ',' for .cpsetup"));
16760 ++input_line_pointer;
16761 SKIP_WHITESPACE ();
16762 expression (&ex_sym);
16764 mips_mark_labels ();
16765 mips_assembling_insn = TRUE;
16768 if (mips_cpreturn_register == -1)
16770 ex_off.X_op = O_constant;
16771 ex_off.X_add_symbol = NULL;
16772 ex_off.X_op_symbol = NULL;
16773 ex_off.X_add_number = mips_cpreturn_offset;
16775 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16776 BFD_RELOC_LO16, SP);
16779 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16780 mips_gp_register, 0);
16782 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16784 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16785 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16788 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16789 mips_gp_register, -1, BFD_RELOC_GPREL16,
16790 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16792 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16793 mips_gp_register, reg1);
16799 ex.X_op = O_symbol;
16800 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16801 ex.X_op_symbol = NULL;
16802 ex.X_add_number = 0;
16804 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16805 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16807 macro_build_lui (&ex, mips_gp_register);
16808 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16809 mips_gp_register, BFD_RELOC_LO16);
16814 mips_assembling_insn = FALSE;
16815 demand_empty_rest_of_line ();
16819 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16821 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16822 .cplocal is ignored. */
16823 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16829 if (mips_opts.mips16)
16831 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16832 ignore_rest_of_line ();
16836 mips_gp_register = tc_get_register (0);
16837 demand_empty_rest_of_line ();
16840 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16841 offset from $sp. The offset is remembered, and after making a PIC
16842 call $gp is restored from that location. */
16845 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16849 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16850 .cprestore is ignored. */
16851 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16857 if (mips_opts.mips16)
16859 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16860 ignore_rest_of_line ();
16864 mips_cprestore_offset = get_absolute_expression ();
16865 mips_cprestore_valid = 1;
16867 ex.X_op = O_constant;
16868 ex.X_add_symbol = NULL;
16869 ex.X_op_symbol = NULL;
16870 ex.X_add_number = mips_cprestore_offset;
16872 mips_mark_labels ();
16873 mips_assembling_insn = TRUE;
16876 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16877 SP, HAVE_64BIT_ADDRESSES);
16880 mips_assembling_insn = FALSE;
16881 demand_empty_rest_of_line ();
16884 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16885 was given in the preceding .cpsetup, it results in:
16886 ld $gp, offset($sp)
16888 If a register $reg2 was given there, it results in:
16889 daddu $gp, $reg2, $0 */
16892 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16896 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16897 We also need NewABI support. */
16898 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16904 if (mips_opts.mips16)
16906 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16907 ignore_rest_of_line ();
16911 mips_mark_labels ();
16912 mips_assembling_insn = TRUE;
16915 if (mips_cpreturn_register == -1)
16917 ex.X_op = O_constant;
16918 ex.X_add_symbol = NULL;
16919 ex.X_op_symbol = NULL;
16920 ex.X_add_number = mips_cpreturn_offset;
16922 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16925 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16926 mips_cpreturn_register, 0);
16929 mips_assembling_insn = FALSE;
16930 demand_empty_rest_of_line ();
16933 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16934 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16935 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16936 debug information or MIPS16 TLS. */
16939 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16940 bfd_reloc_code_real_type rtype)
16947 if (ex.X_op != O_symbol)
16949 as_bad (_("Unsupported use of %s"), dirstr);
16950 ignore_rest_of_line ();
16953 p = frag_more (bytes);
16954 md_number_to_chars (p, 0, bytes);
16955 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16956 demand_empty_rest_of_line ();
16957 mips_clear_insn_labels ();
16960 /* Handle .dtprelword. */
16963 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16965 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16968 /* Handle .dtpreldword. */
16971 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16973 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16976 /* Handle .tprelword. */
16979 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16981 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16984 /* Handle .tpreldword. */
16987 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16989 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16992 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16993 code. It sets the offset to use in gp_rel relocations. */
16996 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
16998 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
16999 We also need NewABI support. */
17000 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17006 mips_gprel_offset = get_absolute_expression ();
17008 demand_empty_rest_of_line ();
17011 /* Handle the .gpword pseudo-op. This is used when generating PIC
17012 code. It generates a 32 bit GP relative reloc. */
17015 s_gpword (int ignore ATTRIBUTE_UNUSED)
17017 segment_info_type *si;
17018 struct insn_label_list *l;
17022 /* When not generating PIC code, this is treated as .word. */
17023 if (mips_pic != SVR4_PIC)
17029 si = seg_info (now_seg);
17030 l = si->label_list;
17031 mips_emit_delays ();
17033 mips_align (2, 0, l);
17036 mips_clear_insn_labels ();
17038 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17040 as_bad (_("Unsupported use of .gpword"));
17041 ignore_rest_of_line ();
17045 md_number_to_chars (p, 0, 4);
17046 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17047 BFD_RELOC_GPREL32);
17049 demand_empty_rest_of_line ();
17053 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17055 segment_info_type *si;
17056 struct insn_label_list *l;
17060 /* When not generating PIC code, this is treated as .dword. */
17061 if (mips_pic != SVR4_PIC)
17067 si = seg_info (now_seg);
17068 l = si->label_list;
17069 mips_emit_delays ();
17071 mips_align (3, 0, l);
17074 mips_clear_insn_labels ();
17076 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17078 as_bad (_("Unsupported use of .gpdword"));
17079 ignore_rest_of_line ();
17083 md_number_to_chars (p, 0, 8);
17084 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17085 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17087 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17088 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17089 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17091 demand_empty_rest_of_line ();
17094 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17095 tables. It generates a R_MIPS_EH reloc. */
17098 s_ehword (int ignore ATTRIBUTE_UNUSED)
17103 mips_emit_delays ();
17106 mips_clear_insn_labels ();
17108 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17110 as_bad (_("Unsupported use of .ehword"));
17111 ignore_rest_of_line ();
17115 md_number_to_chars (p, 0, 4);
17116 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17117 BFD_RELOC_MIPS_EH);
17119 demand_empty_rest_of_line ();
17122 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17123 tables in SVR4 PIC code. */
17126 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17130 /* This is ignored when not generating SVR4 PIC code. */
17131 if (mips_pic != SVR4_PIC)
17137 mips_mark_labels ();
17138 mips_assembling_insn = TRUE;
17140 /* Add $gp to the register named as an argument. */
17142 reg = tc_get_register (0);
17143 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17146 mips_assembling_insn = FALSE;
17147 demand_empty_rest_of_line ();
17150 /* Handle the .insn pseudo-op. This marks instruction labels in
17151 mips16/micromips mode. This permits the linker to handle them specially,
17152 such as generating jalx instructions when needed. We also make
17153 them odd for the duration of the assembly, in order to generate the
17154 right sort of code. We will make them even in the adjust_symtab
17155 routine, while leaving them marked. This is convenient for the
17156 debugger and the disassembler. The linker knows to make them odd
17160 s_insn (int ignore ATTRIBUTE_UNUSED)
17162 mips_mark_labels ();
17164 demand_empty_rest_of_line ();
17167 /* Handle the .nan pseudo-op. */
17170 s_nan (int ignore ATTRIBUTE_UNUSED)
17172 static const char str_legacy[] = "legacy";
17173 static const char str_2008[] = "2008";
17176 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17178 if (i == sizeof (str_2008) - 1
17179 && memcmp (input_line_pointer, str_2008, i) == 0)
17180 mips_flag_nan2008 = TRUE;
17181 else if (i == sizeof (str_legacy) - 1
17182 && memcmp (input_line_pointer, str_legacy, i) == 0)
17183 mips_flag_nan2008 = FALSE;
17185 as_bad (_("Bad .nan directive"));
17187 input_line_pointer += i;
17188 demand_empty_rest_of_line ();
17191 /* Handle a .stab[snd] directive. Ideally these directives would be
17192 implemented in a transparent way, so that removing them would not
17193 have any effect on the generated instructions. However, s_stab
17194 internally changes the section, so in practice we need to decide
17195 now whether the preceding label marks compressed code. We do not
17196 support changing the compression mode of a label after a .stab*
17197 directive, such as in:
17203 so the current mode wins. */
17206 s_mips_stab (int type)
17208 mips_mark_labels ();
17212 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17215 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17222 name = input_line_pointer;
17223 c = get_symbol_end ();
17224 symbolP = symbol_find_or_make (name);
17225 S_SET_WEAK (symbolP);
17226 *input_line_pointer = c;
17228 SKIP_WHITESPACE ();
17230 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17232 if (S_IS_DEFINED (symbolP))
17234 as_bad (_("ignoring attempt to redefine symbol %s"),
17235 S_GET_NAME (symbolP));
17236 ignore_rest_of_line ();
17240 if (*input_line_pointer == ',')
17242 ++input_line_pointer;
17243 SKIP_WHITESPACE ();
17247 if (exp.X_op != O_symbol)
17249 as_bad (_("bad .weakext directive"));
17250 ignore_rest_of_line ();
17253 symbol_set_value_expression (symbolP, &exp);
17256 demand_empty_rest_of_line ();
17259 /* Parse a register string into a number. Called from the ECOFF code
17260 to parse .frame. The argument is non-zero if this is the frame
17261 register, so that we can record it in mips_frame_reg. */
17264 tc_get_register (int frame)
17268 SKIP_WHITESPACE ();
17269 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17273 mips_frame_reg = reg != 0 ? reg : SP;
17274 mips_frame_reg_valid = 1;
17275 mips_cprestore_valid = 0;
17281 md_section_align (asection *seg, valueT addr)
17283 int align = bfd_get_section_alignment (stdoutput, seg);
17285 /* We don't need to align ELF sections to the full alignment.
17286 However, Irix 5 may prefer that we align them at least to a 16
17287 byte boundary. We don't bother to align the sections if we
17288 are targeted for an embedded system. */
17289 if (strncmp (TARGET_OS, "elf", 3) == 0)
17294 return ((addr + (1 << align) - 1) & (-1 << align));
17297 /* Utility routine, called from above as well. If called while the
17298 input file is still being read, it's only an approximation. (For
17299 example, a symbol may later become defined which appeared to be
17300 undefined earlier.) */
17303 nopic_need_relax (symbolS *sym, int before_relaxing)
17308 if (g_switch_value > 0)
17310 const char *symname;
17313 /* Find out whether this symbol can be referenced off the $gp
17314 register. It can be if it is smaller than the -G size or if
17315 it is in the .sdata or .sbss section. Certain symbols can
17316 not be referenced off the $gp, although it appears as though
17318 symname = S_GET_NAME (sym);
17319 if (symname != (const char *) NULL
17320 && (strcmp (symname, "eprol") == 0
17321 || strcmp (symname, "etext") == 0
17322 || strcmp (symname, "_gp") == 0
17323 || strcmp (symname, "edata") == 0
17324 || strcmp (symname, "_fbss") == 0
17325 || strcmp (symname, "_fdata") == 0
17326 || strcmp (symname, "_ftext") == 0
17327 || strcmp (symname, "end") == 0
17328 || strcmp (symname, "_gp_disp") == 0))
17330 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17332 #ifndef NO_ECOFF_DEBUGGING
17333 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17334 && (symbol_get_obj (sym)->ecoff_extern_size
17335 <= g_switch_value))
17337 /* We must defer this decision until after the whole
17338 file has been read, since there might be a .extern
17339 after the first use of this symbol. */
17340 || (before_relaxing
17341 #ifndef NO_ECOFF_DEBUGGING
17342 && symbol_get_obj (sym)->ecoff_extern_size == 0
17344 && S_GET_VALUE (sym) == 0)
17345 || (S_GET_VALUE (sym) != 0
17346 && S_GET_VALUE (sym) <= g_switch_value)))
17350 const char *segname;
17352 segname = segment_name (S_GET_SEGMENT (sym));
17353 gas_assert (strcmp (segname, ".lit8") != 0
17354 && strcmp (segname, ".lit4") != 0);
17355 change = (strcmp (segname, ".sdata") != 0
17356 && strcmp (segname, ".sbss") != 0
17357 && strncmp (segname, ".sdata.", 7) != 0
17358 && strncmp (segname, ".sbss.", 6) != 0
17359 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17360 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17365 /* We are not optimizing for the $gp register. */
17370 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17373 pic_need_relax (symbolS *sym, asection *segtype)
17377 /* Handle the case of a symbol equated to another symbol. */
17378 while (symbol_equated_reloc_p (sym))
17382 /* It's possible to get a loop here in a badly written program. */
17383 n = symbol_get_value_expression (sym)->X_add_symbol;
17389 if (symbol_section_p (sym))
17392 symsec = S_GET_SEGMENT (sym);
17394 /* This must duplicate the test in adjust_reloc_syms. */
17395 return (!bfd_is_und_section (symsec)
17396 && !bfd_is_abs_section (symsec)
17397 && !bfd_is_com_section (symsec)
17398 && !s_is_linkonce (sym, segtype)
17399 /* A global or weak symbol is treated as external. */
17400 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17404 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17405 extended opcode. SEC is the section the frag is in. */
17408 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17411 const struct mips16_immed_operand *op;
17413 int mintiny, maxtiny;
17417 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17419 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17422 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17423 op = mips16_immed_operands;
17424 while (op->type != type)
17427 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17432 if (type == '<' || type == '>' || type == '[' || type == ']')
17435 maxtiny = 1 << op->nbits;
17440 maxtiny = (1 << op->nbits) - 1;
17445 mintiny = - (1 << (op->nbits - 1));
17446 maxtiny = (1 << (op->nbits - 1)) - 1;
17449 sym_frag = symbol_get_frag (fragp->fr_symbol);
17450 val = S_GET_VALUE (fragp->fr_symbol);
17451 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17457 /* We won't have the section when we are called from
17458 mips_relax_frag. However, we will always have been called
17459 from md_estimate_size_before_relax first. If this is a
17460 branch to a different section, we mark it as such. If SEC is
17461 NULL, and the frag is not marked, then it must be a branch to
17462 the same section. */
17465 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17470 /* Must have been called from md_estimate_size_before_relax. */
17473 fragp->fr_subtype =
17474 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17476 /* FIXME: We should support this, and let the linker
17477 catch branches and loads that are out of range. */
17478 as_bad_where (fragp->fr_file, fragp->fr_line,
17479 _("unsupported PC relative reference to different section"));
17483 if (fragp != sym_frag && sym_frag->fr_address == 0)
17484 /* Assume non-extended on the first relaxation pass.
17485 The address we have calculated will be bogus if this is
17486 a forward branch to another frag, as the forward frag
17487 will have fr_address == 0. */
17491 /* In this case, we know for sure that the symbol fragment is in
17492 the same section. If the relax_marker of the symbol fragment
17493 differs from the relax_marker of this fragment, we have not
17494 yet adjusted the symbol fragment fr_address. We want to add
17495 in STRETCH in order to get a better estimate of the address.
17496 This particularly matters because of the shift bits. */
17498 && sym_frag->relax_marker != fragp->relax_marker)
17502 /* Adjust stretch for any alignment frag. Note that if have
17503 been expanding the earlier code, the symbol may be
17504 defined in what appears to be an earlier frag. FIXME:
17505 This doesn't handle the fr_subtype field, which specifies
17506 a maximum number of bytes to skip when doing an
17508 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17510 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17513 stretch = - ((- stretch)
17514 & ~ ((1 << (int) f->fr_offset) - 1));
17516 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17525 addr = fragp->fr_address + fragp->fr_fix;
17527 /* The base address rules are complicated. The base address of
17528 a branch is the following instruction. The base address of a
17529 PC relative load or add is the instruction itself, but if it
17530 is in a delay slot (in which case it can not be extended) use
17531 the address of the instruction whose delay slot it is in. */
17532 if (type == 'p' || type == 'q')
17536 /* If we are currently assuming that this frag should be
17537 extended, then, the current address is two bytes
17539 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17542 /* Ignore the low bit in the target, since it will be set
17543 for a text label. */
17544 if ((val & 1) != 0)
17547 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17549 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17552 val -= addr & ~ ((1 << op->shift) - 1);
17554 /* Branch offsets have an implicit 0 in the lowest bit. */
17555 if (type == 'p' || type == 'q')
17558 /* If any of the shifted bits are set, we must use an extended
17559 opcode. If the address depends on the size of this
17560 instruction, this can lead to a loop, so we arrange to always
17561 use an extended opcode. We only check this when we are in
17562 the main relaxation loop, when SEC is NULL. */
17563 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17565 fragp->fr_subtype =
17566 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17570 /* If we are about to mark a frag as extended because the value
17571 is precisely maxtiny + 1, then there is a chance of an
17572 infinite loop as in the following code:
17577 In this case when the la is extended, foo is 0x3fc bytes
17578 away, so the la can be shrunk, but then foo is 0x400 away, so
17579 the la must be extended. To avoid this loop, we mark the
17580 frag as extended if it was small, and is about to become
17581 extended with a value of maxtiny + 1. */
17582 if (val == ((maxtiny + 1) << op->shift)
17583 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17586 fragp->fr_subtype =
17587 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17591 else if (symsec != absolute_section && sec != NULL)
17592 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17594 if ((val & ((1 << op->shift) - 1)) != 0
17595 || val < (mintiny << op->shift)
17596 || val > (maxtiny << op->shift))
17602 /* Compute the length of a branch sequence, and adjust the
17603 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17604 worst-case length is computed, with UPDATE being used to indicate
17605 whether an unconditional (-1), branch-likely (+1) or regular (0)
17606 branch is to be computed. */
17608 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17610 bfd_boolean toofar;
17614 && S_IS_DEFINED (fragp->fr_symbol)
17615 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17620 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17622 addr = fragp->fr_address + fragp->fr_fix + 4;
17626 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17629 /* If the symbol is not defined or it's in a different segment,
17630 assume the user knows what's going on and emit a short
17636 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17638 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17639 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17640 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17641 RELAX_BRANCH_LINK (fragp->fr_subtype),
17647 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17650 if (mips_pic != NO_PIC)
17652 /* Additional space for PIC loading of target address. */
17654 if (mips_opts.isa == ISA_MIPS1)
17655 /* Additional space for $at-stabilizing nop. */
17659 /* If branch is conditional. */
17660 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17667 /* Compute the length of a branch sequence, and adjust the
17668 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17669 worst-case length is computed, with UPDATE being used to indicate
17670 whether an unconditional (-1), or regular (0) branch is to be
17674 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17676 bfd_boolean toofar;
17680 && S_IS_DEFINED (fragp->fr_symbol)
17681 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17686 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17687 /* Ignore the low bit in the target, since it will be set
17688 for a text label. */
17689 if ((val & 1) != 0)
17692 addr = fragp->fr_address + fragp->fr_fix + 4;
17696 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17699 /* If the symbol is not defined or it's in a different segment,
17700 assume the user knows what's going on and emit a short
17706 if (fragp && update
17707 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17708 fragp->fr_subtype = (toofar
17709 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17710 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17715 bfd_boolean compact_known = fragp != NULL;
17716 bfd_boolean compact = FALSE;
17717 bfd_boolean uncond;
17720 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17722 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17724 uncond = update < 0;
17726 /* If label is out of range, we turn branch <br>:
17728 <br> label # 4 bytes
17734 nop # 2 bytes if compact && !PIC
17737 if (mips_pic == NO_PIC && (!compact_known || compact))
17740 /* If assembling PIC code, we further turn:
17746 lw/ld at, %got(label)(gp) # 4 bytes
17747 d/addiu at, %lo(label) # 4 bytes
17750 if (mips_pic != NO_PIC)
17753 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17755 <brneg> 0f # 4 bytes
17756 nop # 2 bytes if !compact
17759 length += (compact_known && compact) ? 4 : 6;
17765 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17766 bit accordingly. */
17769 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17771 bfd_boolean toofar;
17774 && S_IS_DEFINED (fragp->fr_symbol)
17775 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17781 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17782 /* Ignore the low bit in the target, since it will be set
17783 for a text label. */
17784 if ((val & 1) != 0)
17787 /* Assume this is a 2-byte branch. */
17788 addr = fragp->fr_address + fragp->fr_fix + 2;
17790 /* We try to avoid the infinite loop by not adding 2 more bytes for
17795 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17797 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17798 else if (type == 'E')
17799 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17804 /* If the symbol is not defined or it's in a different segment,
17805 we emit a normal 32-bit branch. */
17808 if (fragp && update
17809 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17811 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17812 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17820 /* Estimate the size of a frag before relaxing. Unless this is the
17821 mips16, we are not really relaxing here, and the final size is
17822 encoded in the subtype information. For the mips16, we have to
17823 decide whether we are using an extended opcode or not. */
17826 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17830 if (RELAX_BRANCH_P (fragp->fr_subtype))
17833 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17835 return fragp->fr_var;
17838 if (RELAX_MIPS16_P (fragp->fr_subtype))
17839 /* We don't want to modify the EXTENDED bit here; it might get us
17840 into infinite loops. We change it only in mips_relax_frag(). */
17841 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17843 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17847 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17848 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17849 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17850 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17851 fragp->fr_var = length;
17856 if (mips_pic == NO_PIC)
17857 change = nopic_need_relax (fragp->fr_symbol, 0);
17858 else if (mips_pic == SVR4_PIC)
17859 change = pic_need_relax (fragp->fr_symbol, segtype);
17860 else if (mips_pic == VXWORKS_PIC)
17861 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17868 fragp->fr_subtype |= RELAX_USE_SECOND;
17869 return -RELAX_FIRST (fragp->fr_subtype);
17872 return -RELAX_SECOND (fragp->fr_subtype);
17875 /* This is called to see whether a reloc against a defined symbol
17876 should be converted into a reloc against a section. */
17879 mips_fix_adjustable (fixS *fixp)
17881 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17882 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17885 if (fixp->fx_addsy == NULL)
17888 /* If symbol SYM is in a mergeable section, relocations of the form
17889 SYM + 0 can usually be made section-relative. The mergeable data
17890 is then identified by the section offset rather than by the symbol.
17892 However, if we're generating REL LO16 relocations, the offset is split
17893 between the LO16 and parterning high part relocation. The linker will
17894 need to recalculate the complete offset in order to correctly identify
17897 The linker has traditionally not looked for the parterning high part
17898 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17899 placed anywhere. Rather than break backwards compatibility by changing
17900 this, it seems better not to force the issue, and instead keep the
17901 original symbol. This will work with either linker behavior. */
17902 if ((lo16_reloc_p (fixp->fx_r_type)
17903 || reloc_needs_lo_p (fixp->fx_r_type))
17904 && HAVE_IN_PLACE_ADDENDS
17905 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17908 /* There is no place to store an in-place offset for JALR relocations.
17909 Likewise an in-range offset of limited PC-relative relocations may
17910 overflow the in-place relocatable field if recalculated against the
17911 start address of the symbol's containing section. */
17912 if (HAVE_IN_PLACE_ADDENDS
17913 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17914 || jalr_reloc_p (fixp->fx_r_type)))
17917 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17918 to a floating-point stub. The same is true for non-R_MIPS16_26
17919 relocations against MIPS16 functions; in this case, the stub becomes
17920 the function's canonical address.
17922 Floating-point stubs are stored in unique .mips16.call.* or
17923 .mips16.fn.* sections. If a stub T for function F is in section S,
17924 the first relocation in section S must be against F; this is how the
17925 linker determines the target function. All relocations that might
17926 resolve to T must also be against F. We therefore have the following
17927 restrictions, which are given in an intentionally-redundant way:
17929 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17932 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17933 if that stub might be used.
17935 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17938 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17939 that stub might be used.
17941 There is a further restriction:
17943 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17944 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17945 targets with in-place addends; the relocation field cannot
17946 encode the low bit.
17948 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17949 against a MIPS16 symbol. We deal with (5) by by not reducing any
17950 such relocations on REL targets.
17952 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17953 relocation against some symbol R, no relocation against R may be
17954 reduced. (Note that this deals with (2) as well as (1) because
17955 relocations against global symbols will never be reduced on ELF
17956 targets.) This approach is a little simpler than trying to detect
17957 stub sections, and gives the "all or nothing" per-symbol consistency
17958 that we have for MIPS16 symbols. */
17959 if (fixp->fx_subsy == NULL
17960 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17961 || *symbol_get_tc (fixp->fx_addsy)
17962 || (HAVE_IN_PLACE_ADDENDS
17963 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17964 && jmp_reloc_p (fixp->fx_r_type))))
17970 /* Translate internal representation of relocation info to BFD target
17974 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17976 static arelent *retval[4];
17978 bfd_reloc_code_real_type code;
17980 memset (retval, 0, sizeof(retval));
17981 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17982 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17983 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17984 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17986 if (fixp->fx_pcrel)
17988 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17989 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17990 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17991 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17992 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
17994 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17995 Relocations want only the symbol offset. */
17996 reloc->addend = fixp->fx_addnumber + reloc->address;
17999 reloc->addend = fixp->fx_addnumber;
18001 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18002 entry to be used in the relocation's section offset. */
18003 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18005 reloc->address = reloc->addend;
18009 code = fixp->fx_r_type;
18011 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18012 if (reloc->howto == NULL)
18014 as_bad_where (fixp->fx_file, fixp->fx_line,
18015 _("Can not represent %s relocation in this object file format"),
18016 bfd_get_reloc_code_name (code));
18023 /* Relax a machine dependent frag. This returns the amount by which
18024 the current size of the frag should change. */
18027 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18029 if (RELAX_BRANCH_P (fragp->fr_subtype))
18031 offsetT old_var = fragp->fr_var;
18033 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18035 return fragp->fr_var - old_var;
18038 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18040 offsetT old_var = fragp->fr_var;
18041 offsetT new_var = 4;
18043 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18044 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18045 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18046 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18047 fragp->fr_var = new_var;
18049 return new_var - old_var;
18052 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18055 if (mips16_extended_frag (fragp, NULL, stretch))
18057 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18059 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18064 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18066 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18073 /* Convert a machine dependent frag. */
18076 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18078 if (RELAX_BRANCH_P (fragp->fr_subtype))
18081 unsigned long insn;
18085 buf = fragp->fr_literal + fragp->fr_fix;
18086 insn = read_insn (buf);
18088 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18090 /* We generate a fixup instead of applying it right now
18091 because, if there are linker relaxations, we're going to
18092 need the relocations. */
18093 exp.X_op = O_symbol;
18094 exp.X_add_symbol = fragp->fr_symbol;
18095 exp.X_add_number = fragp->fr_offset;
18097 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18098 BFD_RELOC_16_PCREL_S2);
18099 fixp->fx_file = fragp->fr_file;
18100 fixp->fx_line = fragp->fr_line;
18102 buf = write_insn (buf, insn);
18108 as_warn_where (fragp->fr_file, fragp->fr_line,
18109 _("Relaxed out-of-range branch into a jump"));
18111 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18114 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18116 /* Reverse the branch. */
18117 switch ((insn >> 28) & 0xf)
18120 /* bc[0-3][tf]l? instructions can have the condition
18121 reversed by tweaking a single TF bit, and their
18122 opcodes all have 0x4???????. */
18123 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18124 insn ^= 0x00010000;
18128 /* bltz 0x04000000 bgez 0x04010000
18129 bltzal 0x04100000 bgezal 0x04110000 */
18130 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18131 insn ^= 0x00010000;
18135 /* beq 0x10000000 bne 0x14000000
18136 blez 0x18000000 bgtz 0x1c000000 */
18137 insn ^= 0x04000000;
18145 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18147 /* Clear the and-link bit. */
18148 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18150 /* bltzal 0x04100000 bgezal 0x04110000
18151 bltzall 0x04120000 bgezall 0x04130000 */
18152 insn &= ~0x00100000;
18155 /* Branch over the branch (if the branch was likely) or the
18156 full jump (not likely case). Compute the offset from the
18157 current instruction to branch to. */
18158 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18162 /* How many bytes in instructions we've already emitted? */
18163 i = buf - fragp->fr_literal - fragp->fr_fix;
18164 /* How many bytes in instructions from here to the end? */
18165 i = fragp->fr_var - i;
18167 /* Convert to instruction count. */
18169 /* Branch counts from the next instruction. */
18172 /* Branch over the jump. */
18173 buf = write_insn (buf, insn);
18176 buf = write_insn (buf, 0);
18178 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18180 /* beql $0, $0, 2f */
18182 /* Compute the PC offset from the current instruction to
18183 the end of the variable frag. */
18184 /* How many bytes in instructions we've already emitted? */
18185 i = buf - fragp->fr_literal - fragp->fr_fix;
18186 /* How many bytes in instructions from here to the end? */
18187 i = fragp->fr_var - i;
18188 /* Convert to instruction count. */
18190 /* Don't decrement i, because we want to branch over the
18194 buf = write_insn (buf, insn);
18195 buf = write_insn (buf, 0);
18199 if (mips_pic == NO_PIC)
18202 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18203 ? 0x0c000000 : 0x08000000);
18204 exp.X_op = O_symbol;
18205 exp.X_add_symbol = fragp->fr_symbol;
18206 exp.X_add_number = fragp->fr_offset;
18208 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18209 FALSE, BFD_RELOC_MIPS_JMP);
18210 fixp->fx_file = fragp->fr_file;
18211 fixp->fx_line = fragp->fr_line;
18213 buf = write_insn (buf, insn);
18217 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18219 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18220 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18221 insn |= at << OP_SH_RT;
18222 exp.X_op = O_symbol;
18223 exp.X_add_symbol = fragp->fr_symbol;
18224 exp.X_add_number = fragp->fr_offset;
18226 if (fragp->fr_offset)
18228 exp.X_add_symbol = make_expr_symbol (&exp);
18229 exp.X_add_number = 0;
18232 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18233 FALSE, BFD_RELOC_MIPS_GOT16);
18234 fixp->fx_file = fragp->fr_file;
18235 fixp->fx_line = fragp->fr_line;
18237 buf = write_insn (buf, insn);
18239 if (mips_opts.isa == ISA_MIPS1)
18241 buf = write_insn (buf, 0);
18243 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18244 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18245 insn |= at << OP_SH_RS | at << OP_SH_RT;
18247 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18248 FALSE, BFD_RELOC_LO16);
18249 fixp->fx_file = fragp->fr_file;
18250 fixp->fx_line = fragp->fr_line;
18252 buf = write_insn (buf, insn);
18255 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18259 insn |= at << OP_SH_RS;
18261 buf = write_insn (buf, insn);
18265 fragp->fr_fix += fragp->fr_var;
18266 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18270 /* Relax microMIPS branches. */
18271 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18273 char *buf = fragp->fr_literal + fragp->fr_fix;
18274 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18275 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18276 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18277 bfd_boolean short_ds;
18278 unsigned long insn;
18282 exp.X_op = O_symbol;
18283 exp.X_add_symbol = fragp->fr_symbol;
18284 exp.X_add_number = fragp->fr_offset;
18286 fragp->fr_fix += fragp->fr_var;
18288 /* Handle 16-bit branches that fit or are forced to fit. */
18289 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18291 /* We generate a fixup instead of applying it right now,
18292 because if there is linker relaxation, we're going to
18293 need the relocations. */
18295 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18296 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18297 else if (type == 'E')
18298 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18299 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18303 fixp->fx_file = fragp->fr_file;
18304 fixp->fx_line = fragp->fr_line;
18306 /* These relocations can have an addend that won't fit in
18308 fixp->fx_no_overflow = 1;
18313 /* Handle 32-bit branches that fit or are forced to fit. */
18314 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18315 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18317 /* We generate a fixup instead of applying it right now,
18318 because if there is linker relaxation, we're going to
18319 need the relocations. */
18320 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18321 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18322 fixp->fx_file = fragp->fr_file;
18323 fixp->fx_line = fragp->fr_line;
18329 /* Relax 16-bit branches to 32-bit branches. */
18332 insn = read_compressed_insn (buf, 2);
18334 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18335 insn = 0x94000000; /* beq */
18336 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18338 unsigned long regno;
18340 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18341 regno = micromips_to_32_reg_d_map [regno];
18342 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18343 insn |= regno << MICROMIPSOP_SH_RS;
18348 /* Nothing else to do, just write it out. */
18349 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18350 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18352 buf = write_compressed_insn (buf, insn, 4);
18353 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18358 insn = read_compressed_insn (buf, 4);
18360 /* Relax 32-bit branches to a sequence of instructions. */
18361 as_warn_where (fragp->fr_file, fragp->fr_line,
18362 _("Relaxed out-of-range branch into a jump"));
18364 /* Set the short-delay-slot bit. */
18365 short_ds = al && (insn & 0x02000000) != 0;
18367 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18371 /* Reverse the branch. */
18372 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18373 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18374 insn ^= 0x20000000;
18375 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18376 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18377 || (insn & 0xffe00000) == 0x40800000 /* blez */
18378 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18379 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18380 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18381 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18382 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18383 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18384 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18385 insn ^= 0x00400000;
18386 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18387 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18388 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18389 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18390 insn ^= 0x00200000;
18396 /* Clear the and-link and short-delay-slot bits. */
18397 gas_assert ((insn & 0xfda00000) == 0x40200000);
18399 /* bltzal 0x40200000 bgezal 0x40600000 */
18400 /* bltzals 0x42200000 bgezals 0x42600000 */
18401 insn &= ~0x02200000;
18404 /* Make a label at the end for use with the branch. */
18405 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18406 micromips_label_inc ();
18407 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18410 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18411 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18412 fixp->fx_file = fragp->fr_file;
18413 fixp->fx_line = fragp->fr_line;
18415 /* Branch over the jump. */
18416 buf = write_compressed_insn (buf, insn, 4);
18419 buf = write_compressed_insn (buf, 0x0c00, 2);
18422 if (mips_pic == NO_PIC)
18424 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18426 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18427 insn = al ? jal : 0xd4000000;
18429 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18430 BFD_RELOC_MICROMIPS_JMP);
18431 fixp->fx_file = fragp->fr_file;
18432 fixp->fx_line = fragp->fr_line;
18434 buf = write_compressed_insn (buf, insn, 4);
18437 buf = write_compressed_insn (buf, 0x0c00, 2);
18441 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18442 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18443 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18445 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18446 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18447 insn |= at << MICROMIPSOP_SH_RT;
18449 if (exp.X_add_number)
18451 exp.X_add_symbol = make_expr_symbol (&exp);
18452 exp.X_add_number = 0;
18455 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18456 BFD_RELOC_MICROMIPS_GOT16);
18457 fixp->fx_file = fragp->fr_file;
18458 fixp->fx_line = fragp->fr_line;
18460 buf = write_compressed_insn (buf, insn, 4);
18462 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18463 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18464 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18466 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18467 BFD_RELOC_MICROMIPS_LO16);
18468 fixp->fx_file = fragp->fr_file;
18469 fixp->fx_line = fragp->fr_line;
18471 buf = write_compressed_insn (buf, insn, 4);
18473 /* jr/jrc/jalr/jalrs $at */
18474 insn = al ? jalr : jr;
18475 insn |= at << MICROMIPSOP_SH_MJ;
18477 buf = write_compressed_insn (buf, insn, 2);
18480 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18484 if (RELAX_MIPS16_P (fragp->fr_subtype))
18487 const struct mips16_immed_operand *op;
18490 unsigned int user_length, length;
18491 unsigned long insn;
18494 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18495 op = mips16_immed_operands;
18496 while (op->type != type)
18499 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18500 val = resolve_symbol_value (fragp->fr_symbol);
18505 addr = fragp->fr_address + fragp->fr_fix;
18507 /* The rules for the base address of a PC relative reloc are
18508 complicated; see mips16_extended_frag. */
18509 if (type == 'p' || type == 'q')
18514 /* Ignore the low bit in the target, since it will be
18515 set for a text label. */
18516 if ((val & 1) != 0)
18519 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18521 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18524 addr &= ~ (addressT) ((1 << op->shift) - 1);
18527 /* Make sure the section winds up with the alignment we have
18530 record_alignment (asec, op->shift);
18534 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18535 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18536 as_warn_where (fragp->fr_file, fragp->fr_line,
18537 _("extended instruction in delay slot"));
18539 buf = fragp->fr_literal + fragp->fr_fix;
18541 insn = read_compressed_insn (buf, 2);
18543 insn |= MIPS16_EXTEND;
18545 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18547 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18552 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18553 BFD_RELOC_UNUSED, val, user_length, &insn);
18555 length = (ext ? 4 : 2);
18556 gas_assert (mips16_opcode_length (insn) == length);
18557 write_compressed_insn (buf, insn, length);
18558 fragp->fr_fix += length;
18562 relax_substateT subtype = fragp->fr_subtype;
18563 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18564 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18568 first = RELAX_FIRST (subtype);
18569 second = RELAX_SECOND (subtype);
18570 fixp = (fixS *) fragp->fr_opcode;
18572 /* If the delay slot chosen does not match the size of the instruction,
18573 then emit a warning. */
18574 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18575 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18580 s = subtype & (RELAX_DELAY_SLOT_16BIT
18581 | RELAX_DELAY_SLOT_SIZE_FIRST
18582 | RELAX_DELAY_SLOT_SIZE_SECOND);
18583 msg = macro_warning (s);
18585 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18589 /* Possibly emit a warning if we've chosen the longer option. */
18590 if (use_second == second_longer)
18596 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18597 msg = macro_warning (s);
18599 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18603 /* Go through all the fixups for the first sequence. Disable them
18604 (by marking them as done) if we're going to use the second
18605 sequence instead. */
18607 && fixp->fx_frag == fragp
18608 && fixp->fx_where < fragp->fr_fix - second)
18610 if (subtype & RELAX_USE_SECOND)
18612 fixp = fixp->fx_next;
18615 /* Go through the fixups for the second sequence. Disable them if
18616 we're going to use the first sequence, otherwise adjust their
18617 addresses to account for the relaxation. */
18618 while (fixp && fixp->fx_frag == fragp)
18620 if (subtype & RELAX_USE_SECOND)
18621 fixp->fx_where -= first;
18624 fixp = fixp->fx_next;
18627 /* Now modify the frag contents. */
18628 if (subtype & RELAX_USE_SECOND)
18632 start = fragp->fr_literal + fragp->fr_fix - first - second;
18633 memmove (start, start + first, second);
18634 fragp->fr_fix -= first;
18637 fragp->fr_fix -= second;
18641 /* This function is called after the relocs have been generated.
18642 We've been storing mips16 text labels as odd. Here we convert them
18643 back to even for the convenience of the debugger. */
18646 mips_frob_file_after_relocs (void)
18649 unsigned int count, i;
18651 syms = bfd_get_outsymbols (stdoutput);
18652 count = bfd_get_symcount (stdoutput);
18653 for (i = 0; i < count; i++, syms++)
18654 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18655 && ((*syms)->value & 1) != 0)
18657 (*syms)->value &= ~1;
18658 /* If the symbol has an odd size, it was probably computed
18659 incorrectly, so adjust that as well. */
18660 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18661 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18665 /* This function is called whenever a label is defined, including fake
18666 labels instantiated off the dot special symbol. It is used when
18667 handling branch delays; if a branch has a label, we assume we cannot
18668 move it. This also bumps the value of the symbol by 1 in compressed
18672 mips_record_label (symbolS *sym)
18674 segment_info_type *si = seg_info (now_seg);
18675 struct insn_label_list *l;
18677 if (free_insn_labels == NULL)
18678 l = (struct insn_label_list *) xmalloc (sizeof *l);
18681 l = free_insn_labels;
18682 free_insn_labels = l->next;
18686 l->next = si->label_list;
18687 si->label_list = l;
18690 /* This function is called as tc_frob_label() whenever a label is defined
18691 and adds a DWARF-2 record we only want for true labels. */
18694 mips_define_label (symbolS *sym)
18696 mips_record_label (sym);
18697 dwarf2_emit_label (sym);
18700 /* This function is called by tc_new_dot_label whenever a new dot symbol
18704 mips_add_dot_label (symbolS *sym)
18706 mips_record_label (sym);
18707 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18708 mips_compressed_mark_label (sym);
18711 /* Some special processing for a MIPS ELF file. */
18714 mips_elf_final_processing (void)
18716 /* Write out the register information. */
18717 if (mips_abi != N64_ABI)
18721 s.ri_gprmask = mips_gprmask;
18722 s.ri_cprmask[0] = mips_cprmask[0];
18723 s.ri_cprmask[1] = mips_cprmask[1];
18724 s.ri_cprmask[2] = mips_cprmask[2];
18725 s.ri_cprmask[3] = mips_cprmask[3];
18726 /* The gp_value field is set by the MIPS ELF backend. */
18728 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18729 ((Elf32_External_RegInfo *)
18730 mips_regmask_frag));
18734 Elf64_Internal_RegInfo s;
18736 s.ri_gprmask = mips_gprmask;
18738 s.ri_cprmask[0] = mips_cprmask[0];
18739 s.ri_cprmask[1] = mips_cprmask[1];
18740 s.ri_cprmask[2] = mips_cprmask[2];
18741 s.ri_cprmask[3] = mips_cprmask[3];
18742 /* The gp_value field is set by the MIPS ELF backend. */
18744 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18745 ((Elf64_External_RegInfo *)
18746 mips_regmask_frag));
18749 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18750 sort of BFD interface for this. */
18751 if (mips_any_noreorder)
18752 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18753 if (mips_pic != NO_PIC)
18755 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18756 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18759 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18761 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18762 defined at present; this might need to change in future. */
18763 if (file_ase_mips16)
18764 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18765 if (file_ase_micromips)
18766 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18767 if (file_ase & ASE_MDMX)
18768 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18770 /* Set the MIPS ELF ABI flags. */
18771 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18772 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18773 else if (mips_abi == O64_ABI)
18774 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18775 else if (mips_abi == EABI_ABI)
18777 if (!file_mips_gp32)
18778 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18780 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18782 else if (mips_abi == N32_ABI)
18783 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18785 /* Nothing to do for N64_ABI. */
18787 if (mips_32bitmode)
18788 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18790 if (mips_flag_nan2008)
18791 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
18793 #if 0 /* XXX FIXME */
18794 /* 32 bit code with 64 bit FP registers. */
18795 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18796 elf_elfheader (stdoutput)->e_flags |= ???;
18800 typedef struct proc {
18802 symbolS *func_end_sym;
18803 unsigned long reg_mask;
18804 unsigned long reg_offset;
18805 unsigned long fpreg_mask;
18806 unsigned long fpreg_offset;
18807 unsigned long frame_offset;
18808 unsigned long frame_reg;
18809 unsigned long pc_reg;
18812 static procS cur_proc;
18813 static procS *cur_proc_ptr;
18814 static int numprocs;
18816 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18817 as "2", and a normal nop as "0". */
18819 #define NOP_OPCODE_MIPS 0
18820 #define NOP_OPCODE_MIPS16 1
18821 #define NOP_OPCODE_MICROMIPS 2
18824 mips_nop_opcode (void)
18826 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18827 return NOP_OPCODE_MICROMIPS;
18828 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18829 return NOP_OPCODE_MIPS16;
18831 return NOP_OPCODE_MIPS;
18834 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18835 32-bit microMIPS NOPs here (if applicable). */
18838 mips_handle_align (fragS *fragp)
18842 int bytes, size, excess;
18845 if (fragp->fr_type != rs_align_code)
18848 p = fragp->fr_literal + fragp->fr_fix;
18850 switch (nop_opcode)
18852 case NOP_OPCODE_MICROMIPS:
18853 opcode = micromips_nop32_insn.insn_opcode;
18856 case NOP_OPCODE_MIPS16:
18857 opcode = mips16_nop_insn.insn_opcode;
18860 case NOP_OPCODE_MIPS:
18862 opcode = nop_insn.insn_opcode;
18867 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18868 excess = bytes % size;
18870 /* Handle the leading part if we're not inserting a whole number of
18871 instructions, and make it the end of the fixed part of the frag.
18872 Try to fit in a short microMIPS NOP if applicable and possible,
18873 and use zeroes otherwise. */
18874 gas_assert (excess < 4);
18875 fragp->fr_fix += excess;
18880 /* Fall through. */
18882 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
18884 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18888 /* Fall through. */
18891 /* Fall through. */
18896 md_number_to_chars (p, opcode, size);
18897 fragp->fr_var = size;
18901 md_obj_begin (void)
18908 /* Check for premature end, nesting errors, etc. */
18910 as_warn (_("missing .end at end of assembly"));
18919 if (*input_line_pointer == '-')
18921 ++input_line_pointer;
18924 if (!ISDIGIT (*input_line_pointer))
18925 as_bad (_("expected simple number"));
18926 if (input_line_pointer[0] == '0')
18928 if (input_line_pointer[1] == 'x')
18930 input_line_pointer += 2;
18931 while (ISXDIGIT (*input_line_pointer))
18934 val |= hex_value (*input_line_pointer++);
18936 return negative ? -val : val;
18940 ++input_line_pointer;
18941 while (ISDIGIT (*input_line_pointer))
18944 val |= *input_line_pointer++ - '0';
18946 return negative ? -val : val;
18949 if (!ISDIGIT (*input_line_pointer))
18951 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18952 *input_line_pointer, *input_line_pointer);
18953 as_warn (_("invalid number"));
18956 while (ISDIGIT (*input_line_pointer))
18959 val += *input_line_pointer++ - '0';
18961 return negative ? -val : val;
18964 /* The .file directive; just like the usual .file directive, but there
18965 is an initial number which is the ECOFF file index. In the non-ECOFF
18966 case .file implies DWARF-2. */
18969 s_mips_file (int x ATTRIBUTE_UNUSED)
18971 static int first_file_directive = 0;
18973 if (ECOFF_DEBUGGING)
18982 filename = dwarf2_directive_file (0);
18984 /* Versions of GCC up to 3.1 start files with a ".file"
18985 directive even for stabs output. Make sure that this
18986 ".file" is handled. Note that you need a version of GCC
18987 after 3.1 in order to support DWARF-2 on MIPS. */
18988 if (filename != NULL && ! first_file_directive)
18990 (void) new_logical_line (filename, -1);
18991 s_app_file_string (filename, 0);
18993 first_file_directive = 1;
18997 /* The .loc directive, implying DWARF-2. */
19000 s_mips_loc (int x ATTRIBUTE_UNUSED)
19002 if (!ECOFF_DEBUGGING)
19003 dwarf2_directive_loc (0);
19006 /* The .end directive. */
19009 s_mips_end (int x ATTRIBUTE_UNUSED)
19013 /* Following functions need their own .frame and .cprestore directives. */
19014 mips_frame_reg_valid = 0;
19015 mips_cprestore_valid = 0;
19017 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19020 demand_empty_rest_of_line ();
19025 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19026 as_warn (_(".end not in text section"));
19030 as_warn (_(".end directive without a preceding .ent directive."));
19031 demand_empty_rest_of_line ();
19037 gas_assert (S_GET_NAME (p));
19038 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19039 as_warn (_(".end symbol does not match .ent symbol."));
19041 if (debug_type == DEBUG_STABS)
19042 stabs_generate_asm_endfunc (S_GET_NAME (p),
19046 as_warn (_(".end directive missing or unknown symbol"));
19048 /* Create an expression to calculate the size of the function. */
19049 if (p && cur_proc_ptr)
19051 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19052 expressionS *exp = xmalloc (sizeof (expressionS));
19055 exp->X_op = O_subtract;
19056 exp->X_add_symbol = symbol_temp_new_now ();
19057 exp->X_op_symbol = p;
19058 exp->X_add_number = 0;
19060 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19063 /* Generate a .pdr section. */
19064 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19066 segT saved_seg = now_seg;
19067 subsegT saved_subseg = now_subseg;
19071 #ifdef md_flush_pending_output
19072 md_flush_pending_output ();
19075 gas_assert (pdr_seg);
19076 subseg_set (pdr_seg, 0);
19078 /* Write the symbol. */
19079 exp.X_op = O_symbol;
19080 exp.X_add_symbol = p;
19081 exp.X_add_number = 0;
19082 emit_expr (&exp, 4);
19084 fragp = frag_more (7 * 4);
19086 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19087 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19088 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19089 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19090 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19091 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19092 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19094 subseg_set (saved_seg, saved_subseg);
19097 cur_proc_ptr = NULL;
19100 /* The .aent and .ent directives. */
19103 s_mips_ent (int aent)
19107 symbolP = get_symbol ();
19108 if (*input_line_pointer == ',')
19109 ++input_line_pointer;
19110 SKIP_WHITESPACE ();
19111 if (ISDIGIT (*input_line_pointer)
19112 || *input_line_pointer == '-')
19115 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19116 as_warn (_(".ent or .aent not in text section."));
19118 if (!aent && cur_proc_ptr)
19119 as_warn (_("missing .end"));
19123 /* This function needs its own .frame and .cprestore directives. */
19124 mips_frame_reg_valid = 0;
19125 mips_cprestore_valid = 0;
19127 cur_proc_ptr = &cur_proc;
19128 memset (cur_proc_ptr, '\0', sizeof (procS));
19130 cur_proc_ptr->func_sym = symbolP;
19134 if (debug_type == DEBUG_STABS)
19135 stabs_generate_asm_func (S_GET_NAME (symbolP),
19136 S_GET_NAME (symbolP));
19139 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19141 demand_empty_rest_of_line ();
19144 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19145 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19146 s_mips_frame is used so that we can set the PDR information correctly.
19147 We can't use the ecoff routines because they make reference to the ecoff
19148 symbol table (in the mdebug section). */
19151 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19153 if (ECOFF_DEBUGGING)
19159 if (cur_proc_ptr == (procS *) NULL)
19161 as_warn (_(".frame outside of .ent"));
19162 demand_empty_rest_of_line ();
19166 cur_proc_ptr->frame_reg = tc_get_register (1);
19168 SKIP_WHITESPACE ();
19169 if (*input_line_pointer++ != ','
19170 || get_absolute_expression_and_terminator (&val) != ',')
19172 as_warn (_("Bad .frame directive"));
19173 --input_line_pointer;
19174 demand_empty_rest_of_line ();
19178 cur_proc_ptr->frame_offset = val;
19179 cur_proc_ptr->pc_reg = tc_get_register (0);
19181 demand_empty_rest_of_line ();
19185 /* The .fmask and .mask directives. If the mdebug section is present
19186 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19187 embedded targets, s_mips_mask is used so that we can set the PDR
19188 information correctly. We can't use the ecoff routines because they
19189 make reference to the ecoff symbol table (in the mdebug section). */
19192 s_mips_mask (int reg_type)
19194 if (ECOFF_DEBUGGING)
19195 s_ignore (reg_type);
19200 if (cur_proc_ptr == (procS *) NULL)
19202 as_warn (_(".mask/.fmask outside of .ent"));
19203 demand_empty_rest_of_line ();
19207 if (get_absolute_expression_and_terminator (&mask) != ',')
19209 as_warn (_("Bad .mask/.fmask directive"));
19210 --input_line_pointer;
19211 demand_empty_rest_of_line ();
19215 off = get_absolute_expression ();
19217 if (reg_type == 'F')
19219 cur_proc_ptr->fpreg_mask = mask;
19220 cur_proc_ptr->fpreg_offset = off;
19224 cur_proc_ptr->reg_mask = mask;
19225 cur_proc_ptr->reg_offset = off;
19228 demand_empty_rest_of_line ();
19232 /* A table describing all the processors gas knows about. Names are
19233 matched in the order listed.
19235 To ease comparison, please keep this table in the same order as
19236 gcc's mips_cpu_info_table[]. */
19237 static const struct mips_cpu_info mips_cpu_info_table[] =
19239 /* Entries for generic ISAs */
19240 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19241 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19242 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19243 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19244 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19245 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19246 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19247 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19248 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19251 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19252 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19253 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19256 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19259 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19260 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19261 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19262 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19263 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19264 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19265 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19266 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19267 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19268 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19269 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19270 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19271 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19272 /* ST Microelectronics Loongson 2E and 2F cores */
19273 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19274 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19277 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19278 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19279 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19280 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19281 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19282 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19283 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19284 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19285 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19286 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19287 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19288 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19289 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19290 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19291 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19294 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19295 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19296 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19297 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19299 /* MIPS 32 Release 2 */
19300 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19301 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19302 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19303 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19305 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19307 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19308 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19309 ISA_MIPS32R2, CPU_MIPS32R2 },
19310 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19311 ISA_MIPS32R2, CPU_MIPS32R2 },
19312 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19313 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19315 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19316 /* Deprecated forms of the above. */
19317 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19318 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19319 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19320 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19322 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19323 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19324 /* Deprecated forms of the above. */
19325 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19326 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19327 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19328 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19329 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19330 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19331 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19332 /* Deprecated forms of the above. */
19333 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19334 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19335 /* 34Kn is a 34kc without DSP. */
19336 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19337 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19338 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19339 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19340 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19341 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19342 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19343 /* Deprecated forms of the above. */
19344 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19345 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19346 /* 1004K cores are multiprocessor versions of the 34K. */
19347 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19348 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19349 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19350 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19353 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19354 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19355 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19356 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19358 /* Broadcom SB-1 CPU core */
19359 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19360 /* Broadcom SB-1A CPU core */
19361 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19363 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19365 /* MIPS 64 Release 2 */
19367 /* Cavium Networks Octeon CPU core */
19368 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19369 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19370 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19373 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19376 XLP is mostly like XLR, with the prominent exception that it is
19377 MIPS64R2 rather than MIPS64. */
19378 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19381 { NULL, 0, 0, 0, 0 }
19385 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19386 with a final "000" replaced by "k". Ignore case.
19388 Note: this function is shared between GCC and GAS. */
19391 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19393 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19394 given++, canonical++;
19396 return ((*given == 0 && *canonical == 0)
19397 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19401 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19402 CPU name. We've traditionally allowed a lot of variation here.
19404 Note: this function is shared between GCC and GAS. */
19407 mips_matching_cpu_name_p (const char *canonical, const char *given)
19409 /* First see if the name matches exactly, or with a final "000"
19410 turned into "k". */
19411 if (mips_strict_matching_cpu_name_p (canonical, given))
19414 /* If not, try comparing based on numerical designation alone.
19415 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19416 if (TOLOWER (*given) == 'r')
19418 if (!ISDIGIT (*given))
19421 /* Skip over some well-known prefixes in the canonical name,
19422 hoping to find a number there too. */
19423 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19425 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19427 else if (TOLOWER (canonical[0]) == 'r')
19430 return mips_strict_matching_cpu_name_p (canonical, given);
19434 /* Parse an option that takes the name of a processor as its argument.
19435 OPTION is the name of the option and CPU_STRING is the argument.
19436 Return the corresponding processor enumeration if the CPU_STRING is
19437 recognized, otherwise report an error and return null.
19439 A similar function exists in GCC. */
19441 static const struct mips_cpu_info *
19442 mips_parse_cpu (const char *option, const char *cpu_string)
19444 const struct mips_cpu_info *p;
19446 /* 'from-abi' selects the most compatible architecture for the given
19447 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19448 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19449 version. Look first at the -mgp options, if given, otherwise base
19450 the choice on MIPS_DEFAULT_64BIT.
19452 Treat NO_ABI like the EABIs. One reason to do this is that the
19453 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19454 architecture. This code picks MIPS I for 'mips' and MIPS III for
19455 'mips64', just as we did in the days before 'from-abi'. */
19456 if (strcasecmp (cpu_string, "from-abi") == 0)
19458 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19459 return mips_cpu_info_from_isa (ISA_MIPS1);
19461 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19462 return mips_cpu_info_from_isa (ISA_MIPS3);
19464 if (file_mips_gp32 >= 0)
19465 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19467 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19472 /* 'default' has traditionally been a no-op. Probably not very useful. */
19473 if (strcasecmp (cpu_string, "default") == 0)
19476 for (p = mips_cpu_info_table; p->name != 0; p++)
19477 if (mips_matching_cpu_name_p (p->name, cpu_string))
19480 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19484 /* Return the canonical processor information for ISA (a member of the
19485 ISA_MIPS* enumeration). */
19487 static const struct mips_cpu_info *
19488 mips_cpu_info_from_isa (int isa)
19492 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19493 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19494 && isa == mips_cpu_info_table[i].isa)
19495 return (&mips_cpu_info_table[i]);
19500 static const struct mips_cpu_info *
19501 mips_cpu_info_from_arch (int arch)
19505 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19506 if (arch == mips_cpu_info_table[i].cpu)
19507 return (&mips_cpu_info_table[i]);
19513 show (FILE *stream, const char *string, int *col_p, int *first_p)
19517 fprintf (stream, "%24s", "");
19522 fprintf (stream, ", ");
19526 if (*col_p + strlen (string) > 72)
19528 fprintf (stream, "\n%24s", "");
19532 fprintf (stream, "%s", string);
19533 *col_p += strlen (string);
19539 md_show_usage (FILE *stream)
19544 fprintf (stream, _("\
19546 -EB generate big endian output\n\
19547 -EL generate little endian output\n\
19548 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19549 -G NUM allow referencing objects up to NUM bytes\n\
19550 implicitly with the gp register [default 8]\n"));
19551 fprintf (stream, _("\
19552 -mips1 generate MIPS ISA I instructions\n\
19553 -mips2 generate MIPS ISA II instructions\n\
19554 -mips3 generate MIPS ISA III instructions\n\
19555 -mips4 generate MIPS ISA IV instructions\n\
19556 -mips5 generate MIPS ISA V instructions\n\
19557 -mips32 generate MIPS32 ISA instructions\n\
19558 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19559 -mips64 generate MIPS64 ISA instructions\n\
19560 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19561 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19565 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19566 show (stream, mips_cpu_info_table[i].name, &column, &first);
19567 show (stream, "from-abi", &column, &first);
19568 fputc ('\n', stream);
19570 fprintf (stream, _("\
19571 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19572 -no-mCPU don't generate code specific to CPU.\n\
19573 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19577 show (stream, "3900", &column, &first);
19578 show (stream, "4010", &column, &first);
19579 show (stream, "4100", &column, &first);
19580 show (stream, "4650", &column, &first);
19581 fputc ('\n', stream);
19583 fprintf (stream, _("\
19584 -mips16 generate mips16 instructions\n\
19585 -no-mips16 do not generate mips16 instructions\n"));
19586 fprintf (stream, _("\
19587 -mmicromips generate microMIPS instructions\n\
19588 -mno-micromips do not generate microMIPS instructions\n"));
19589 fprintf (stream, _("\
19590 -msmartmips generate smartmips instructions\n\
19591 -mno-smartmips do not generate smartmips instructions\n"));
19592 fprintf (stream, _("\
19593 -mdsp generate DSP instructions\n\
19594 -mno-dsp do not generate DSP instructions\n"));
19595 fprintf (stream, _("\
19596 -mdspr2 generate DSP R2 instructions\n\
19597 -mno-dspr2 do not generate DSP R2 instructions\n"));
19598 fprintf (stream, _("\
19599 -mmt generate MT instructions\n\
19600 -mno-mt do not generate MT instructions\n"));
19601 fprintf (stream, _("\
19602 -mmcu generate MCU instructions\n\
19603 -mno-mcu do not generate MCU instructions\n"));
19604 fprintf (stream, _("\
19605 -mvirt generate Virtualization instructions\n\
19606 -mno-virt do not generate Virtualization instructions\n"));
19607 fprintf (stream, _("\
19608 -minsn32 only generate 32-bit microMIPS instructions\n\
19609 -mno-insn32 generate all microMIPS instructions\n"));
19610 fprintf (stream, _("\
19611 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19612 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19613 -mfix-vr4120 work around certain VR4120 errata\n\
19614 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19615 -mfix-24k insert a nop after ERET and DERET instructions\n\
19616 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19617 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19618 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19619 -msym32 assume all symbols have 32-bit values\n\
19620 -O0 remove unneeded NOPs, do not swap branches\n\
19621 -O remove unneeded NOPs and swap branches\n\
19622 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19623 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19624 fprintf (stream, _("\
19625 -mhard-float allow floating-point instructions\n\
19626 -msoft-float do not allow floating-point instructions\n\
19627 -msingle-float only allow 32-bit floating-point operations\n\
19628 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19629 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19630 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
19631 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
19635 show (stream, "legacy", &column, &first);
19636 show (stream, "2008", &column, &first);
19638 fputc ('\n', stream);
19640 fprintf (stream, _("\
19641 -KPIC, -call_shared generate SVR4 position independent code\n\
19642 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19643 -mvxworks-pic generate VxWorks position independent code\n\
19644 -non_shared do not generate code that can operate with DSOs\n\
19645 -xgot assume a 32 bit GOT\n\
19646 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19647 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19648 position dependent (non shared) code\n\
19649 -mabi=ABI create ABI conformant object file for:\n"));
19653 show (stream, "32", &column, &first);
19654 show (stream, "o64", &column, &first);
19655 show (stream, "n32", &column, &first);
19656 show (stream, "64", &column, &first);
19657 show (stream, "eabi", &column, &first);
19659 fputc ('\n', stream);
19661 fprintf (stream, _("\
19662 -32 create o32 ABI object file (default)\n\
19663 -n32 create n32 ABI object file\n\
19664 -64 create 64 ABI object file\n"));
19669 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19671 if (HAVE_64BIT_SYMBOLS)
19672 return dwarf2_format_64bit_irix;
19674 return dwarf2_format_32bit;
19679 mips_dwarf2_addr_size (void)
19681 if (HAVE_64BIT_OBJECTS)
19687 /* Standard calling conventions leave the CFA at SP on entry. */
19689 mips_cfi_frame_initial_instructions (void)
19691 cfi_add_CFA_def_cfa_register (SP);
19695 tc_mips_regname_to_dw2regnum (char *regname)
19697 unsigned int regnum = -1;
19700 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))