1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
37 /* Check assumptions made in this file. */
38 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
39 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
42 #define DBG(x) printf x
47 /* Clean up namespace so we can include obj-elf.h too. */
48 static int mips_output_flavor (void);
49 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
50 #undef OBJ_PROCESS_STAB
57 #undef obj_frob_file_after_relocs
58 #undef obj_frob_symbol
60 #undef obj_sec_sym_ok_for_reloc
61 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
64 /* Fix any of them that we actually care about. */
66 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 extern int target_big_endian;
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME ".rodata"
112 /* Ways in which an instruction can be "appended" to the output. */
114 /* Just add it normally. */
117 /* Add it normally and then add a nop. */
120 /* Turn an instruction with a delay slot into a "compact" version. */
123 /* Insert the instruction before the last one. */
127 /* Information about an instruction, including its format, operands
131 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
132 const struct mips_opcode *insn_mo;
134 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
135 a copy of INSN_MO->match with the operands filled in. If we have
136 decided to use an extended MIPS16 instruction, this includes the
138 unsigned long insn_opcode;
140 /* The frag that contains the instruction. */
143 /* The offset into FRAG of the first instruction byte. */
146 /* The relocs associated with the instruction, if any. */
149 /* True if this entry cannot be moved from its current position. */
150 unsigned int fixed_p : 1;
152 /* True if this instruction occurred in a .set noreorder block. */
153 unsigned int noreorder_p : 1;
155 /* True for mips16 instructions that jump to an absolute address. */
156 unsigned int mips16_absolute_jump_p : 1;
158 /* True if this instruction is complete. */
159 unsigned int complete_p : 1;
161 /* True if this instruction is cleared from history by unconditional
163 unsigned int cleared_p : 1;
166 /* The ABI to use. */
177 /* MIPS ABI we are using for this output file. */
178 static enum mips_abi_level mips_abi = NO_ABI;
180 /* Whether or not we have code that can call pic code. */
181 int mips_abicalls = FALSE;
183 /* Whether or not we have code which can be put into a shared
185 static bfd_boolean mips_in_shared = TRUE;
187 /* This is the set of options which may be modified by the .set
188 pseudo-op. We use a struct so that .set push and .set pop are more
191 struct mips_set_options
193 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
194 if it has not been initialized. Changed by `.set mipsN', and the
195 -mipsN command line option, and the default CPU. */
197 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
198 <asename>', by command line options, and based on the default
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
207 1 if we are, and -1 if the value has not been initialized. Changed
208 by `.set micromips' and `.set nomicromips', and the -mmicromips
209 and -mno-micromips command line options, and the default CPU. */
211 /* Non-zero if we should not reorder instructions. Changed by `.set
212 reorder' and `.set noreorder'. */
214 /* Non-zero if we should not permit the register designated "assembler
215 temporary" to be used in instructions. The value is the register
216 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
217 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
219 /* Non-zero if we should warn when a macro instruction expands into
220 more than one machine instruction. Changed by `.set nomacro' and
222 int warn_about_macros;
223 /* Non-zero if we should not move instructions. Changed by `.set
224 move', `.set volatile', `.set nomove', and `.set novolatile'. */
226 /* Non-zero if we should not optimize branches by moving the target
227 of the branch into the delay slot. Actually, we don't perform
228 this optimization anyhow. Changed by `.set bopt' and `.set
231 /* Non-zero if we should not autoextend mips16 instructions.
232 Changed by `.set autoextend' and `.set noautoextend'. */
234 /* Restrict general purpose registers and floating point registers
235 to 32 bit. This is initially determined when -mgp32 or -mfp32
236 is passed but can changed if the assembler code uses .set mipsN. */
239 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
240 command line option, and the default CPU. */
242 /* True if ".set sym32" is in effect. */
244 /* True if floating-point operations are not allowed. Changed by .set
245 softfloat or .set hardfloat, by command line options -msoft-float or
246 -mhard-float. The default is false. */
247 bfd_boolean soft_float;
249 /* True if only single-precision floating-point operations are allowed.
250 Changed by .set singlefloat or .set doublefloat, command-line options
251 -msingle-float or -mdouble-float. The default is false. */
252 bfd_boolean single_float;
255 /* This is the struct we use to hold the current set of options. Note
256 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
257 -1 to indicate that they have not been initialized. */
259 /* True if -mgp32 was passed. */
260 static int file_mips_gp32 = -1;
262 /* True if -mfp32 was passed. */
263 static int file_mips_fp32 = -1;
265 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
266 static int file_mips_soft_float = 0;
268 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
269 static int file_mips_single_float = 0;
271 static struct mips_set_options mips_opts =
273 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
274 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
275 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
276 /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
277 /* soft_float */ FALSE, /* single_float */ FALSE
280 /* The set of ASEs that were selected on the command line, either
281 explicitly via ASE options or implicitly through things like -march. */
282 static unsigned int file_ase;
284 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
285 static unsigned int file_ase_explicit;
287 /* These variables are filled in with the masks of registers used.
288 The object format code reads them and puts them in the appropriate
290 unsigned long mips_gprmask;
291 unsigned long mips_cprmask[4];
293 /* MIPS ISA we are using for this output file. */
294 static int file_mips_isa = ISA_UNKNOWN;
296 /* True if any MIPS16 code was produced. */
297 static int file_ase_mips16;
299 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
300 || mips_opts.isa == ISA_MIPS32R2 \
301 || mips_opts.isa == ISA_MIPS64 \
302 || mips_opts.isa == ISA_MIPS64R2)
304 /* True if any microMIPS code was produced. */
305 static int file_ase_micromips;
307 /* True if we want to create R_MIPS_JALR for jalr $25. */
309 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
311 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
312 because there's no place for any addend, the only acceptable
313 expression is a bare symbol. */
314 #define MIPS_JALR_HINT_P(EXPR) \
315 (!HAVE_IN_PLACE_ADDENDS \
316 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
319 /* The argument of the -march= flag. The architecture we are assembling. */
320 static int file_mips_arch = CPU_UNKNOWN;
321 static const char *mips_arch_string;
323 /* The argument of the -mtune= flag. The architecture for which we
325 static int mips_tune = CPU_UNKNOWN;
326 static const char *mips_tune_string;
328 /* True when generating 32-bit code for a 64-bit processor. */
329 static int mips_32bitmode = 0;
331 /* True if the given ABI requires 32-bit registers. */
332 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
334 /* Likewise 64-bit registers. */
335 #define ABI_NEEDS_64BIT_REGS(ABI) \
337 || (ABI) == N64_ABI \
340 /* Return true if ISA supports 64 bit wide gp registers. */
341 #define ISA_HAS_64BIT_REGS(ISA) \
342 ((ISA) == ISA_MIPS3 \
343 || (ISA) == ISA_MIPS4 \
344 || (ISA) == ISA_MIPS5 \
345 || (ISA) == ISA_MIPS64 \
346 || (ISA) == ISA_MIPS64R2)
348 /* Return true if ISA supports 64 bit wide float registers. */
349 #define ISA_HAS_64BIT_FPRS(ISA) \
350 ((ISA) == ISA_MIPS3 \
351 || (ISA) == ISA_MIPS4 \
352 || (ISA) == ISA_MIPS5 \
353 || (ISA) == ISA_MIPS32R2 \
354 || (ISA) == ISA_MIPS64 \
355 || (ISA) == ISA_MIPS64R2)
357 /* Return true if ISA supports 64-bit right rotate (dror et al.)
359 #define ISA_HAS_DROR(ISA) \
360 ((ISA) == ISA_MIPS64R2 \
361 || (mips_opts.micromips \
362 && ISA_HAS_64BIT_REGS (ISA)) \
365 /* Return true if ISA supports 32-bit right rotate (ror et al.)
367 #define ISA_HAS_ROR(ISA) \
368 ((ISA) == ISA_MIPS32R2 \
369 || (ISA) == ISA_MIPS64R2 \
370 || (mips_opts.ase & ASE_SMARTMIPS) \
371 || mips_opts.micromips \
374 /* Return true if ISA supports single-precision floats in odd registers. */
375 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
376 ((ISA) == ISA_MIPS32 \
377 || (ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64 \
379 || (ISA) == ISA_MIPS64R2)
381 /* Return true if ISA supports move to/from high part of a 64-bit
382 floating-point register. */
383 #define ISA_HAS_MXHC1(ISA) \
384 ((ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64R2)
387 #define HAVE_32BIT_GPRS \
388 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
390 #define HAVE_32BIT_FPRS \
391 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
393 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
394 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
396 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
398 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
400 /* True if relocations are stored in-place. */
401 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
403 /* The ABI-derived address size. */
404 #define HAVE_64BIT_ADDRESSES \
405 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
406 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
408 /* The size of symbolic constants (i.e., expressions of the form
409 "SYMBOL" or "SYMBOL + OFFSET"). */
410 #define HAVE_32BIT_SYMBOLS \
411 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
412 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
414 /* Addresses are loaded in different ways, depending on the address size
415 in use. The n32 ABI Documentation also mandates the use of additions
416 with overflow checking, but existing implementations don't follow it. */
417 #define ADDRESS_ADD_INSN \
418 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
420 #define ADDRESS_ADDI_INSN \
421 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
423 #define ADDRESS_LOAD_INSN \
424 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
426 #define ADDRESS_STORE_INSN \
427 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
429 /* Return true if the given CPU supports the MIPS16 ASE. */
430 #define CPU_HAS_MIPS16(cpu) \
431 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
432 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
434 /* Return true if the given CPU supports the microMIPS ASE. */
435 #define CPU_HAS_MICROMIPS(cpu) 0
437 /* True if CPU has a dror instruction. */
438 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
440 /* True if CPU has a ror instruction. */
441 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
443 /* True if CPU is in the Octeon family */
444 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2)
446 /* True if CPU has seq/sne and seqi/snei instructions. */
447 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
449 /* True, if CPU has support for ldc1 and sdc1. */
450 #define CPU_HAS_LDC1_SDC1(CPU) \
451 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
453 /* True if mflo and mfhi can be immediately followed by instructions
454 which write to the HI and LO registers.
456 According to MIPS specifications, MIPS ISAs I, II, and III need
457 (at least) two instructions between the reads of HI/LO and
458 instructions which write them, and later ISAs do not. Contradicting
459 the MIPS specifications, some MIPS IV processor user manuals (e.g.
460 the UM for the NEC Vr5000) document needing the instructions between
461 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
462 MIPS64 and later ISAs to have the interlocks, plus any specific
463 earlier-ISA CPUs for which CPU documentation declares that the
464 instructions are really interlocked. */
465 #define hilo_interlocks \
466 (mips_opts.isa == ISA_MIPS32 \
467 || mips_opts.isa == ISA_MIPS32R2 \
468 || mips_opts.isa == ISA_MIPS64 \
469 || mips_opts.isa == ISA_MIPS64R2 \
470 || mips_opts.arch == CPU_R4010 \
471 || mips_opts.arch == CPU_R5900 \
472 || mips_opts.arch == CPU_R10000 \
473 || mips_opts.arch == CPU_R12000 \
474 || mips_opts.arch == CPU_R14000 \
475 || mips_opts.arch == CPU_R16000 \
476 || mips_opts.arch == CPU_RM7000 \
477 || mips_opts.arch == CPU_VR5500 \
478 || mips_opts.micromips \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
485 level I and microMIPS mode instructions are always interlocked. */
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900 \
489 || mips_opts.arch == CPU_R5900 \
490 || mips_opts.micromips \
493 /* Whether the processor uses hardware interlocks to avoid delays
494 required by coprocessor instructions, and thus does not require
495 nops to be inserted. This applies to instructions marked
496 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
497 between instructions marked INSN_WRITE_COND_CODE and ones marked
498 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
499 levels I, II, and III and microMIPS mode instructions are always
501 /* Itbl support may require additional care here. */
502 #define cop_interlocks \
503 ((mips_opts.isa != ISA_MIPS1 \
504 && mips_opts.isa != ISA_MIPS2 \
505 && mips_opts.isa != ISA_MIPS3) \
506 || mips_opts.arch == CPU_R4300 \
507 || mips_opts.micromips \
510 /* Whether the processor uses hardware interlocks to protect reads
511 from coprocessor registers after they are loaded from memory, and
512 thus does not require nops to be inserted. This applies to
513 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
514 requires at MIPS ISA level I and microMIPS mode instructions are
515 always interlocked. */
516 #define cop_mem_interlocks \
517 (mips_opts.isa != ISA_MIPS1 \
518 || mips_opts.micromips \
521 /* Is this a mfhi or mflo instruction? */
522 #define MF_HILO_INSN(PINFO) \
523 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
525 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
526 has been selected. This implies, in particular, that addresses of text
527 labels have their LSB set. */
528 #define HAVE_CODE_COMPRESSION \
529 ((mips_opts.mips16 | mips_opts.micromips) != 0)
531 /* The minimum and maximum signed values that can be stored in a GPR. */
532 #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1))
533 #define GPR_SMIN (-GPR_SMAX - 1)
535 /* MIPS PIC level. */
537 enum mips_pic_level mips_pic;
539 /* 1 if we should generate 32 bit offsets from the $gp register in
540 SVR4_PIC mode. Currently has no meaning in other modes. */
541 static int mips_big_got = 0;
543 /* 1 if trap instructions should used for overflow rather than break
545 static int mips_trap = 0;
547 /* 1 if double width floating point constants should not be constructed
548 by assembling two single width halves into two single width floating
549 point registers which just happen to alias the double width destination
550 register. On some architectures this aliasing can be disabled by a bit
551 in the status register, and the setting of this bit cannot be determined
552 automatically at assemble time. */
553 static int mips_disable_float_construction;
555 /* Non-zero if any .set noreorder directives were used. */
557 static int mips_any_noreorder;
559 /* Non-zero if nops should be inserted when the register referenced in
560 an mfhi/mflo instruction is read in the next two instructions. */
561 static int mips_7000_hilo_fix;
563 /* The size of objects in the small data section. */
564 static unsigned int g_switch_value = 8;
565 /* Whether the -G option was used. */
566 static int g_switch_seen = 0;
571 /* If we can determine in advance that GP optimization won't be
572 possible, we can skip the relaxation stuff that tries to produce
573 GP-relative references. This makes delay slot optimization work
576 This function can only provide a guess, but it seems to work for
577 gcc output. It needs to guess right for gcc, otherwise gcc
578 will put what it thinks is a GP-relative instruction in a branch
581 I don't know if a fix is needed for the SVR4_PIC mode. I've only
582 fixed it for the non-PIC mode. KR 95/04/07 */
583 static int nopic_need_relax (symbolS *, int);
585 /* handle of the OPCODE hash table */
586 static struct hash_control *op_hash = NULL;
588 /* The opcode hash table we use for the mips16. */
589 static struct hash_control *mips16_op_hash = NULL;
591 /* The opcode hash table we use for the microMIPS ASE. */
592 static struct hash_control *micromips_op_hash = NULL;
594 /* This array holds the chars that always start a comment. If the
595 pre-processor is disabled, these aren't very useful */
596 const char comment_chars[] = "#";
598 /* This array holds the chars that only start a comment at the beginning of
599 a line. If the line seems to have the form '# 123 filename'
600 .line and .file directives will appear in the pre-processed output */
601 /* Note that input_file.c hand checks for '#' at the beginning of the
602 first line of the input file. This is because the compiler outputs
603 #NO_APP at the beginning of its output. */
604 /* Also note that C style comments are always supported. */
605 const char line_comment_chars[] = "#";
607 /* This array holds machine specific line separator characters. */
608 const char line_separator_chars[] = ";";
610 /* Chars that can be used to separate mant from exp in floating point nums */
611 const char EXP_CHARS[] = "eE";
613 /* Chars that mean this number is a floating point constant */
616 const char FLT_CHARS[] = "rRsSfFdDxXpP";
618 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
619 changed in read.c . Ideally it shouldn't have to know about it at all,
620 but nothing is ideal around here.
623 static char *insn_error;
625 static int auto_align = 1;
627 /* When outputting SVR4 PIC code, the assembler needs to know the
628 offset in the stack frame from which to restore the $gp register.
629 This is set by the .cprestore pseudo-op, and saved in this
631 static offsetT mips_cprestore_offset = -1;
633 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
634 more optimizations, it can use a register value instead of a memory-saved
635 offset and even an other register than $gp as global pointer. */
636 static offsetT mips_cpreturn_offset = -1;
637 static int mips_cpreturn_register = -1;
638 static int mips_gp_register = GP;
639 static int mips_gprel_offset = 0;
641 /* Whether mips_cprestore_offset has been set in the current function
642 (or whether it has already been warned about, if not). */
643 static int mips_cprestore_valid = 0;
645 /* This is the register which holds the stack frame, as set by the
646 .frame pseudo-op. This is needed to implement .cprestore. */
647 static int mips_frame_reg = SP;
649 /* Whether mips_frame_reg has been set in the current function
650 (or whether it has already been warned about, if not). */
651 static int mips_frame_reg_valid = 0;
653 /* To output NOP instructions correctly, we need to keep information
654 about the previous two instructions. */
656 /* Whether we are optimizing. The default value of 2 means to remove
657 unneeded NOPs and swap branch instructions when possible. A value
658 of 1 means to not swap branches. A value of 0 means to always
660 static int mips_optimize = 2;
662 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
663 equivalent to seeing no -g option at all. */
664 static int mips_debug = 0;
666 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
667 #define MAX_VR4130_NOPS 4
669 /* The maximum number of NOPs needed to fill delay slots. */
670 #define MAX_DELAY_NOPS 2
672 /* The maximum number of NOPs needed for any purpose. */
675 /* A list of previous instructions, with index 0 being the most recent.
676 We need to look back MAX_NOPS instructions when filling delay slots
677 or working around processor errata. We need to look back one
678 instruction further if we're thinking about using history[0] to
679 fill a branch delay slot. */
680 static struct mips_cl_insn history[1 + MAX_NOPS];
682 /* Nop instructions used by emit_nop. */
683 static struct mips_cl_insn nop_insn;
684 static struct mips_cl_insn mips16_nop_insn;
685 static struct mips_cl_insn micromips_nop16_insn;
686 static struct mips_cl_insn micromips_nop32_insn;
688 /* The appropriate nop for the current mode. */
689 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \
690 : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn))
692 /* The size of NOP_INSN in bytes. */
693 #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4)
695 /* If this is set, it points to a frag holding nop instructions which
696 were inserted before the start of a noreorder section. If those
697 nops turn out to be unnecessary, the size of the frag can be
699 static fragS *prev_nop_frag;
701 /* The number of nop instructions we created in prev_nop_frag. */
702 static int prev_nop_frag_holds;
704 /* The number of nop instructions that we know we need in
706 static int prev_nop_frag_required;
708 /* The number of instructions we've seen since prev_nop_frag. */
709 static int prev_nop_frag_since;
711 /* Relocations against symbols are sometimes done in two parts, with a HI
712 relocation and a LO relocation. Each relocation has only 16 bits of
713 space to store an addend. This means that in order for the linker to
714 handle carries correctly, it must be able to locate both the HI and
715 the LO relocation. This means that the relocations must appear in
716 order in the relocation table.
718 In order to implement this, we keep track of each unmatched HI
719 relocation. We then sort them so that they immediately precede the
720 corresponding LO relocation. */
725 struct mips_hi_fixup *next;
728 /* The section this fixup is in. */
732 /* The list of unmatched HI relocs. */
734 static struct mips_hi_fixup *mips_hi_fixup_list;
736 /* The frag containing the last explicit relocation operator.
737 Null if explicit relocations have not been used. */
739 static fragS *prev_reloc_op_frag;
741 /* Map normal MIPS register numbers to mips16 register numbers. */
743 #define X ILLEGAL_REG
744 static const int mips32_to_16_reg_map[] =
746 X, X, 2, 3, 4, 5, 6, 7,
747 X, X, X, X, X, X, X, X,
748 0, 1, X, X, X, X, X, X,
749 X, X, X, X, X, X, X, X
753 /* Map mips16 register numbers to normal MIPS register numbers. */
755 static const unsigned int mips16_to_32_reg_map[] =
757 16, 17, 2, 3, 4, 5, 6, 7
760 /* Map normal MIPS register numbers to microMIPS register numbers. */
762 #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map
763 #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map
764 #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map
765 #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map
766 #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map
767 #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map
768 #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
770 #define X ILLEGAL_REG
771 /* reg type h: 4, 5, 6. */
772 static const int mips32_to_micromips_reg_h_map[] =
774 X, X, X, X, 4, 5, 6, X,
775 X, X, X, X, X, X, X, X,
776 X, X, X, X, X, X, X, X,
777 X, X, X, X, X, X, X, X
780 /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
781 static const int mips32_to_micromips_reg_m_map[] =
783 0, X, 2, 3, X, X, X, X,
784 X, X, X, X, X, X, X, X,
785 4, 1, 5, 6, 7, X, X, X,
786 X, X, X, X, X, X, X, X
789 /* reg type q: 0, 2-7. 17. */
790 static const int mips32_to_micromips_reg_q_map[] =
792 0, X, 2, 3, 4, 5, 6, 7,
793 X, X, X, X, X, X, X, X,
794 X, 1, X, X, X, X, X, X,
795 X, X, X, X, X, X, X, X
798 #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map
801 /* Map microMIPS register numbers to normal MIPS register numbers. */
803 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
804 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
805 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
806 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
807 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
808 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
810 /* The microMIPS registers with type h. */
811 static const unsigned int micromips_to_32_reg_h_map[] =
813 5, 5, 6, 4, 4, 4, 4, 4
816 /* The microMIPS registers with type i. */
817 static const unsigned int micromips_to_32_reg_i_map[] =
819 6, 7, 7, 21, 22, 5, 6, 7
822 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
824 /* The microMIPS registers with type m. */
825 static const unsigned int micromips_to_32_reg_m_map[] =
827 0, 17, 2, 3, 16, 18, 19, 20
830 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
832 /* The microMIPS registers with type q. */
833 static const unsigned int micromips_to_32_reg_q_map[] =
835 0, 17, 2, 3, 4, 5, 6, 7
838 /* microMIPS imm type B. */
839 static const int micromips_imm_b_map[] =
841 1, 4, 8, 12, 16, 20, 24, -1
844 /* microMIPS imm type C. */
845 static const int micromips_imm_c_map[] =
847 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
850 /* Classifies the kind of instructions we're interested in when
851 implementing -mfix-vr4120. */
852 enum fix_vr4120_class
860 NUM_FIX_VR4120_CLASSES
863 /* ...likewise -mfix-loongson2f-jump. */
864 static bfd_boolean mips_fix_loongson2f_jump;
866 /* ...likewise -mfix-loongson2f-nop. */
867 static bfd_boolean mips_fix_loongson2f_nop;
869 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
870 static bfd_boolean mips_fix_loongson2f;
872 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
873 there must be at least one other instruction between an instruction
874 of type X and an instruction of type Y. */
875 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
877 /* True if -mfix-vr4120 is in force. */
878 static int mips_fix_vr4120;
880 /* ...likewise -mfix-vr4130. */
881 static int mips_fix_vr4130;
883 /* ...likewise -mfix-24k. */
884 static int mips_fix_24k;
886 /* ...likewise -mfix-cn63xxp1 */
887 static bfd_boolean mips_fix_cn63xxp1;
889 /* We don't relax branches by default, since this causes us to expand
890 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
891 fail to compute the offset before expanding the macro to the most
892 efficient expansion. */
894 static int mips_relax_branch;
896 /* The expansion of many macros depends on the type of symbol that
897 they refer to. For example, when generating position-dependent code,
898 a macro that refers to a symbol may have two different expansions,
899 one which uses GP-relative addresses and one which uses absolute
900 addresses. When generating SVR4-style PIC, a macro may have
901 different expansions for local and global symbols.
903 We handle these situations by generating both sequences and putting
904 them in variant frags. In position-dependent code, the first sequence
905 will be the GP-relative one and the second sequence will be the
906 absolute one. In SVR4 PIC, the first sequence will be for global
907 symbols and the second will be for local symbols.
909 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
910 SECOND are the lengths of the two sequences in bytes. These fields
911 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
912 the subtype has the following flags:
915 Set if it has been decided that we should use the second
916 sequence instead of the first.
919 Set in the first variant frag if the macro's second implementation
920 is longer than its first. This refers to the macro as a whole,
921 not an individual relaxation.
924 Set in the first variant frag if the macro appeared in a .set nomacro
925 block and if one alternative requires a warning but the other does not.
928 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
931 RELAX_DELAY_SLOT_16BIT
932 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
935 RELAX_DELAY_SLOT_SIZE_FIRST
936 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
937 the macro is of the wrong size for the branch delay slot.
939 RELAX_DELAY_SLOT_SIZE_SECOND
940 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
941 the macro is of the wrong size for the branch delay slot.
943 The frag's "opcode" points to the first fixup for relaxable code.
945 Relaxable macros are generated using a sequence such as:
947 relax_start (SYMBOL);
948 ... generate first expansion ...
950 ... generate second expansion ...
953 The code and fixups for the unwanted alternative are discarded
954 by md_convert_frag. */
955 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
957 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
958 #define RELAX_SECOND(X) ((X) & 0xff)
959 #define RELAX_USE_SECOND 0x10000
960 #define RELAX_SECOND_LONGER 0x20000
961 #define RELAX_NOMACRO 0x40000
962 #define RELAX_DELAY_SLOT 0x80000
963 #define RELAX_DELAY_SLOT_16BIT 0x100000
964 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000
965 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000
967 /* Branch without likely bit. If label is out of range, we turn:
969 beq reg1, reg2, label
979 with the following opcode replacements:
986 bltzal <-> bgezal (with jal label instead of j label)
988 Even though keeping the delay slot instruction in the delay slot of
989 the branch would be more efficient, it would be very tricky to do
990 correctly, because we'd have to introduce a variable frag *after*
991 the delay slot instruction, and expand that instead. Let's do it
992 the easy way for now, even if the branch-not-taken case now costs
993 one additional instruction. Out-of-range branches are not supposed
994 to be common, anyway.
996 Branch likely. If label is out of range, we turn:
998 beql reg1, reg2, label
999 delay slot (annulled if branch not taken)
1008 delay slot (executed only if branch taken)
1011 It would be possible to generate a shorter sequence by losing the
1012 likely bit, generating something like:
1017 delay slot (executed only if branch taken)
1029 bltzall -> bgezal (with jal label instead of j label)
1030 bgezall -> bltzal (ditto)
1033 but it's not clear that it would actually improve performance. */
1034 #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
1035 ((relax_substateT) \
1038 | ((toofar) ? 0x20 : 0) \
1039 | ((link) ? 0x40 : 0) \
1040 | ((likely) ? 0x80 : 0) \
1041 | ((uncond) ? 0x100 : 0)))
1042 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1043 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
1044 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
1045 #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
1046 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
1047 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1049 /* For mips16 code, we use an entirely different form of relaxation.
1050 mips16 supports two versions of most instructions which take
1051 immediate values: a small one which takes some small value, and a
1052 larger one which takes a 16 bit value. Since branches also follow
1053 this pattern, relaxing these values is required.
1055 We can assemble both mips16 and normal MIPS code in a single
1056 object. Therefore, we need to support this type of relaxation at
1057 the same time that we support the relaxation described above. We
1058 use the high bit of the subtype field to distinguish these cases.
1060 The information we store for this type of relaxation is the
1061 argument code found in the opcode file for this relocation, whether
1062 the user explicitly requested a small or extended form, and whether
1063 the relocation is in a jump or jal delay slot. That tells us the
1064 size of the value, and how it should be stored. We also store
1065 whether the fragment is considered to be extended or not. We also
1066 store whether this is known to be a branch to a different section,
1067 whether we have tried to relax this frag yet, and whether we have
1068 ever extended a PC relative fragment because of a shift count. */
1069 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
1072 | ((small) ? 0x100 : 0) \
1073 | ((ext) ? 0x200 : 0) \
1074 | ((dslot) ? 0x400 : 0) \
1075 | ((jal_dslot) ? 0x800 : 0))
1076 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1077 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1078 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
1079 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
1080 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
1081 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
1082 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
1083 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
1084 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
1085 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
1086 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
1087 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
1089 /* For microMIPS code, we use relaxation similar to one we use for
1090 MIPS16 code. Some instructions that take immediate values support
1091 two encodings: a small one which takes some small value, and a
1092 larger one which takes a 16 bit value. As some branches also follow
1093 this pattern, relaxing these values is required.
1095 We can assemble both microMIPS and normal MIPS code in a single
1096 object. Therefore, we need to support this type of relaxation at
1097 the same time that we support the relaxation described above. We
1098 use one of the high bits of the subtype field to distinguish these
1101 The information we store for this type of relaxation is the argument
1102 code found in the opcode file for this relocation, the register
1103 selected as the assembler temporary, whether the branch is
1104 unconditional, whether it is compact, whether it stores the link
1105 address implicitly in $ra, whether relaxation of out-of-range 32-bit
1106 branches to a sequence of instructions is enabled, and whether the
1107 displacement of a branch is too large to fit as an immediate argument
1108 of a 16-bit and a 32-bit branch, respectively. */
1109 #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \
1110 relax32, toofar16, toofar32) \
1113 | (((at) & 0x1f) << 8) \
1114 | ((uncond) ? 0x2000 : 0) \
1115 | ((compact) ? 0x4000 : 0) \
1116 | ((link) ? 0x8000 : 0) \
1117 | ((relax32) ? 0x10000 : 0) \
1118 | ((toofar16) ? 0x20000 : 0) \
1119 | ((toofar32) ? 0x40000 : 0))
1120 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1121 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1122 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1123 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0)
1124 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0)
1125 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0)
1126 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0)
1128 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0)
1129 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000)
1130 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000)
1131 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0)
1132 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000)
1133 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000)
1135 /* Sign-extend 16-bit value X. */
1136 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1138 /* Is the given value a sign-extended 32-bit value? */
1139 #define IS_SEXT_32BIT_NUM(x) \
1140 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1141 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1143 /* Is the given value a sign-extended 16-bit value? */
1144 #define IS_SEXT_16BIT_NUM(x) \
1145 (((x) &~ (offsetT) 0x7fff) == 0 \
1146 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1148 /* Is the given value a sign-extended 12-bit value? */
1149 #define IS_SEXT_12BIT_NUM(x) \
1150 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1152 /* Is the given value a sign-extended 9-bit value? */
1153 #define IS_SEXT_9BIT_NUM(x) \
1154 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1156 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1157 #define IS_ZEXT_32BIT_NUM(x) \
1158 (((x) &~ (offsetT) 0xffffffff) == 0 \
1159 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1161 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1162 VALUE << SHIFT. VALUE is evaluated exactly once. */
1163 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1164 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1165 | (((VALUE) & (MASK)) << (SHIFT)))
1167 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1169 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1170 (((STRUCT) >> (SHIFT)) & (MASK))
1172 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1173 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1175 include/opcode/mips.h specifies operand fields using the macros
1176 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1177 with "MIPS16OP" instead of "OP". */
1178 #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \
1181 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1182 OP_MASK_##FIELD, OP_SH_##FIELD); \
1184 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1185 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \
1187 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1188 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1189 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1191 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1192 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1194 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1195 : EXTRACT_BITS ((INSN).insn_opcode, \
1196 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1197 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1198 EXTRACT_BITS ((INSN).insn_opcode, \
1199 MIPS16OP_MASK_##FIELD, \
1200 MIPS16OP_SH_##FIELD)
1202 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1203 #define MIPS16_EXTEND (0xf000U << 16)
1205 /* Whether or not we are emitting a branch-likely macro. */
1206 static bfd_boolean emit_branch_likely_macro = FALSE;
1208 /* Global variables used when generating relaxable macros. See the
1209 comment above RELAX_ENCODE for more details about how relaxation
1212 /* 0 if we're not emitting a relaxable macro.
1213 1 if we're emitting the first of the two relaxation alternatives.
1214 2 if we're emitting the second alternative. */
1217 /* The first relaxable fixup in the current frag. (In other words,
1218 the first fixup that refers to relaxable code.) */
1221 /* sizes[0] says how many bytes of the first alternative are stored in
1222 the current frag. Likewise sizes[1] for the second alternative. */
1223 unsigned int sizes[2];
1225 /* The symbol on which the choice of sequence depends. */
1229 /* Global variables used to decide whether a macro needs a warning. */
1231 /* True if the macro is in a branch delay slot. */
1232 bfd_boolean delay_slot_p;
1234 /* Set to the length in bytes required if the macro is in a delay slot
1235 that requires a specific length of instruction, otherwise zero. */
1236 unsigned int delay_slot_length;
1238 /* For relaxable macros, sizes[0] is the length of the first alternative
1239 in bytes and sizes[1] is the length of the second alternative.
1240 For non-relaxable macros, both elements give the length of the
1242 unsigned int sizes[2];
1244 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1245 instruction of the first alternative in bytes and first_insn_sizes[1]
1246 is the length of the first instruction of the second alternative.
1247 For non-relaxable macros, both elements give the length of the first
1248 instruction in bytes.
1250 Set to zero if we haven't yet seen the first instruction. */
1251 unsigned int first_insn_sizes[2];
1253 /* For relaxable macros, insns[0] is the number of instructions for the
1254 first alternative and insns[1] is the number of instructions for the
1257 For non-relaxable macros, both elements give the number of
1258 instructions for the macro. */
1259 unsigned int insns[2];
1261 /* The first variant frag for this macro. */
1263 } mips_macro_warning;
1265 /* Prototypes for static functions. */
1267 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1269 static void append_insn
1270 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1271 bfd_boolean expansionp);
1272 static void mips_no_prev_insn (void);
1273 static void macro_build (expressionS *, const char *, const char *, ...);
1274 static void mips16_macro_build
1275 (expressionS *, const char *, const char *, va_list *);
1276 static void load_register (int, expressionS *, int);
1277 static void macro_start (void);
1278 static void macro_end (void);
1279 static void macro (struct mips_cl_insn * ip);
1280 static void mips16_macro (struct mips_cl_insn * ip);
1281 static void mips_ip (char *str, struct mips_cl_insn * ip);
1282 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1283 static void mips16_immed
1284 (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1285 unsigned int, unsigned long *);
1286 static size_t my_getSmallExpression
1287 (expressionS *, bfd_reloc_code_real_type *, char *);
1288 static void my_getExpression (expressionS *, char *);
1289 static void s_align (int);
1290 static void s_change_sec (int);
1291 static void s_change_section (int);
1292 static void s_cons (int);
1293 static void s_float_cons (int);
1294 static void s_mips_globl (int);
1295 static void s_option (int);
1296 static void s_mipsset (int);
1297 static void s_abicalls (int);
1298 static void s_cpload (int);
1299 static void s_cpsetup (int);
1300 static void s_cplocal (int);
1301 static void s_cprestore (int);
1302 static void s_cpreturn (int);
1303 static void s_dtprelword (int);
1304 static void s_dtpreldword (int);
1305 static void s_tprelword (int);
1306 static void s_tpreldword (int);
1307 static void s_gpvalue (int);
1308 static void s_gpword (int);
1309 static void s_gpdword (int);
1310 static void s_ehword (int);
1311 static void s_cpadd (int);
1312 static void s_insn (int);
1313 static void md_obj_begin (void);
1314 static void md_obj_end (void);
1315 static void s_mips_ent (int);
1316 static void s_mips_end (int);
1317 static void s_mips_frame (int);
1318 static void s_mips_mask (int reg_type);
1319 static void s_mips_stab (int);
1320 static void s_mips_weakext (int);
1321 static void s_mips_file (int);
1322 static void s_mips_loc (int);
1323 static bfd_boolean pic_need_relax (symbolS *, asection *);
1324 static int relaxed_branch_length (fragS *, asection *, int);
1325 static int validate_mips_insn (const struct mips_opcode *);
1326 static int validate_micromips_insn (const struct mips_opcode *);
1327 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1328 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1330 /* Table and functions used to map between CPU/ISA names, and
1331 ISA levels, and CPU numbers. */
1333 struct mips_cpu_info
1335 const char *name; /* CPU or ISA name. */
1336 int flags; /* MIPS_CPU_* flags. */
1337 int ase; /* Set of ASEs implemented by the CPU. */
1338 int isa; /* ISA level. */
1339 int cpu; /* CPU number (default CPU if ISA). */
1342 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1344 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1345 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1346 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1348 /* Command-line options. */
1349 const char *md_shortopts = "O::g::G:";
1353 OPTION_MARCH = OPTION_MD_BASE,
1377 OPTION_NO_SMARTMIPS,
1383 OPTION_NO_MICROMIPS,
1386 OPTION_COMPAT_ARCH_BASE,
1395 OPTION_M7000_HILO_FIX,
1396 OPTION_MNO_7000_HILO_FIX,
1399 OPTION_FIX_LOONGSON2F_JUMP,
1400 OPTION_NO_FIX_LOONGSON2F_JUMP,
1401 OPTION_FIX_LOONGSON2F_NOP,
1402 OPTION_NO_FIX_LOONGSON2F_NOP,
1404 OPTION_NO_FIX_VR4120,
1406 OPTION_NO_FIX_VR4130,
1407 OPTION_FIX_CN63XXP1,
1408 OPTION_NO_FIX_CN63XXP1,
1415 OPTION_CONSTRUCT_FLOATS,
1416 OPTION_NO_CONSTRUCT_FLOATS,
1419 OPTION_RELAX_BRANCH,
1420 OPTION_NO_RELAX_BRANCH,
1427 OPTION_SINGLE_FLOAT,
1428 OPTION_DOUBLE_FLOAT,
1441 OPTION_MVXWORKS_PIC,
1445 struct option md_longopts[] =
1447 /* Options which specify architecture. */
1448 {"march", required_argument, NULL, OPTION_MARCH},
1449 {"mtune", required_argument, NULL, OPTION_MTUNE},
1450 {"mips0", no_argument, NULL, OPTION_MIPS1},
1451 {"mips1", no_argument, NULL, OPTION_MIPS1},
1452 {"mips2", no_argument, NULL, OPTION_MIPS2},
1453 {"mips3", no_argument, NULL, OPTION_MIPS3},
1454 {"mips4", no_argument, NULL, OPTION_MIPS4},
1455 {"mips5", no_argument, NULL, OPTION_MIPS5},
1456 {"mips32", no_argument, NULL, OPTION_MIPS32},
1457 {"mips64", no_argument, NULL, OPTION_MIPS64},
1458 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1459 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1461 /* Options which specify Application Specific Extensions (ASEs). */
1462 {"mips16", no_argument, NULL, OPTION_MIPS16},
1463 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1464 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1465 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1466 {"mdmx", no_argument, NULL, OPTION_MDMX},
1467 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1468 {"mdsp", no_argument, NULL, OPTION_DSP},
1469 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1470 {"mmt", no_argument, NULL, OPTION_MT},
1471 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1472 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1473 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1474 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1475 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1476 {"meva", no_argument, NULL, OPTION_EVA},
1477 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1478 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1479 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1480 {"mmcu", no_argument, NULL, OPTION_MCU},
1481 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1482 {"mvirt", no_argument, NULL, OPTION_VIRT},
1483 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1485 /* Old-style architecture options. Don't add more of these. */
1486 {"m4650", no_argument, NULL, OPTION_M4650},
1487 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1488 {"m4010", no_argument, NULL, OPTION_M4010},
1489 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1490 {"m4100", no_argument, NULL, OPTION_M4100},
1491 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1492 {"m3900", no_argument, NULL, OPTION_M3900},
1493 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1495 /* Options which enable bug fixes. */
1496 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1497 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1498 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1499 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1500 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1501 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1502 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1503 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1504 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1505 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1506 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1507 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1508 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1509 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1510 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1512 /* Miscellaneous options. */
1513 {"trap", no_argument, NULL, OPTION_TRAP},
1514 {"no-break", no_argument, NULL, OPTION_TRAP},
1515 {"break", no_argument, NULL, OPTION_BREAK},
1516 {"no-trap", no_argument, NULL, OPTION_BREAK},
1517 {"EB", no_argument, NULL, OPTION_EB},
1518 {"EL", no_argument, NULL, OPTION_EL},
1519 {"mfp32", no_argument, NULL, OPTION_FP32},
1520 {"mgp32", no_argument, NULL, OPTION_GP32},
1521 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1522 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1523 {"mfp64", no_argument, NULL, OPTION_FP64},
1524 {"mgp64", no_argument, NULL, OPTION_GP64},
1525 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1526 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1527 {"mshared", no_argument, NULL, OPTION_MSHARED},
1528 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1529 {"msym32", no_argument, NULL, OPTION_MSYM32},
1530 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1531 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1532 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1533 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1534 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1536 /* Strictly speaking this next option is ELF specific,
1537 but we allow it for other ports as well in order to
1538 make testing easier. */
1539 {"32", no_argument, NULL, OPTION_32},
1541 /* ELF-specific options. */
1542 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1543 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1544 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1545 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1546 {"xgot", no_argument, NULL, OPTION_XGOT},
1547 {"mabi", required_argument, NULL, OPTION_MABI},
1548 {"n32", no_argument, NULL, OPTION_N32},
1549 {"64", no_argument, NULL, OPTION_64},
1550 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1551 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1552 {"mpdr", no_argument, NULL, OPTION_PDR},
1553 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1554 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1556 {NULL, no_argument, NULL, 0}
1558 size_t md_longopts_size = sizeof (md_longopts);
1560 /* Information about either an Application Specific Extension or an
1561 optional architecture feature that, for simplicity, we treat in the
1562 same way as an ASE. */
1565 /* The name of the ASE, used in both the command-line and .set options. */
1568 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1569 and 64-bit architectures, the flags here refer to the subset that
1570 is available on both. */
1573 /* The ASE_* flag used for instructions that are available on 64-bit
1574 architectures but that are not included in FLAGS. */
1575 unsigned int flags64;
1577 /* The command-line options that turn the ASE on and off. */
1581 /* The minimum required architecture revisions for MIPS32, MIPS64,
1582 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1585 int micromips32_rev;
1586 int micromips64_rev;
1589 /* A table of all supported ASEs. */
1590 static const struct mips_ase mips_ases[] = {
1591 { "dsp", ASE_DSP, ASE_DSP64,
1592 OPTION_DSP, OPTION_NO_DSP,
1595 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1596 OPTION_DSPR2, OPTION_NO_DSPR2,
1599 { "eva", ASE_EVA, 0,
1600 OPTION_EVA, OPTION_NO_EVA,
1603 { "mcu", ASE_MCU, 0,
1604 OPTION_MCU, OPTION_NO_MCU,
1607 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1608 { "mdmx", ASE_MDMX, 0,
1609 OPTION_MDMX, OPTION_NO_MDMX,
1612 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1613 { "mips3d", ASE_MIPS3D, 0,
1614 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1618 OPTION_MT, OPTION_NO_MT,
1621 { "smartmips", ASE_SMARTMIPS, 0,
1622 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1625 { "virt", ASE_VIRT, ASE_VIRT64,
1626 OPTION_VIRT, OPTION_NO_VIRT,
1630 /* The set of ASEs that require -mfp64. */
1631 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX)
1633 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1634 static const unsigned int mips_ase_groups[] = {
1640 The following pseudo-ops from the Kane and Heinrich MIPS book
1641 should be defined here, but are currently unsupported: .alias,
1642 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1644 The following pseudo-ops from the Kane and Heinrich MIPS book are
1645 specific to the type of debugging information being generated, and
1646 should be defined by the object format: .aent, .begin, .bend,
1647 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1650 The following pseudo-ops from the Kane and Heinrich MIPS book are
1651 not MIPS CPU specific, but are also not specific to the object file
1652 format. This file is probably the best place to define them, but
1653 they are not currently supported: .asm0, .endr, .lab, .struct. */
1655 static const pseudo_typeS mips_pseudo_table[] =
1657 /* MIPS specific pseudo-ops. */
1658 {"option", s_option, 0},
1659 {"set", s_mipsset, 0},
1660 {"rdata", s_change_sec, 'r'},
1661 {"sdata", s_change_sec, 's'},
1662 {"livereg", s_ignore, 0},
1663 {"abicalls", s_abicalls, 0},
1664 {"cpload", s_cpload, 0},
1665 {"cpsetup", s_cpsetup, 0},
1666 {"cplocal", s_cplocal, 0},
1667 {"cprestore", s_cprestore, 0},
1668 {"cpreturn", s_cpreturn, 0},
1669 {"dtprelword", s_dtprelword, 0},
1670 {"dtpreldword", s_dtpreldword, 0},
1671 {"tprelword", s_tprelword, 0},
1672 {"tpreldword", s_tpreldword, 0},
1673 {"gpvalue", s_gpvalue, 0},
1674 {"gpword", s_gpword, 0},
1675 {"gpdword", s_gpdword, 0},
1676 {"ehword", s_ehword, 0},
1677 {"cpadd", s_cpadd, 0},
1678 {"insn", s_insn, 0},
1680 /* Relatively generic pseudo-ops that happen to be used on MIPS
1682 {"asciiz", stringer, 8 + 1},
1683 {"bss", s_change_sec, 'b'},
1685 {"half", s_cons, 1},
1686 {"dword", s_cons, 3},
1687 {"weakext", s_mips_weakext, 0},
1688 {"origin", s_org, 0},
1689 {"repeat", s_rept, 0},
1691 /* For MIPS this is non-standard, but we define it for consistency. */
1692 {"sbss", s_change_sec, 'B'},
1694 /* These pseudo-ops are defined in read.c, but must be overridden
1695 here for one reason or another. */
1696 {"align", s_align, 0},
1697 {"byte", s_cons, 0},
1698 {"data", s_change_sec, 'd'},
1699 {"double", s_float_cons, 'd'},
1700 {"float", s_float_cons, 'f'},
1701 {"globl", s_mips_globl, 0},
1702 {"global", s_mips_globl, 0},
1703 {"hword", s_cons, 1},
1705 {"long", s_cons, 2},
1706 {"octa", s_cons, 4},
1707 {"quad", s_cons, 3},
1708 {"section", s_change_section, 0},
1709 {"short", s_cons, 1},
1710 {"single", s_float_cons, 'f'},
1711 {"stabd", s_mips_stab, 'd'},
1712 {"stabn", s_mips_stab, 'n'},
1713 {"stabs", s_mips_stab, 's'},
1714 {"text", s_change_sec, 't'},
1715 {"word", s_cons, 2},
1717 { "extern", ecoff_directive_extern, 0},
1722 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1724 /* These pseudo-ops should be defined by the object file format.
1725 However, a.out doesn't support them, so we have versions here. */
1726 {"aent", s_mips_ent, 1},
1727 {"bgnb", s_ignore, 0},
1728 {"end", s_mips_end, 0},
1729 {"endb", s_ignore, 0},
1730 {"ent", s_mips_ent, 0},
1731 {"file", s_mips_file, 0},
1732 {"fmask", s_mips_mask, 'F'},
1733 {"frame", s_mips_frame, 0},
1734 {"loc", s_mips_loc, 0},
1735 {"mask", s_mips_mask, 'R'},
1736 {"verstamp", s_ignore, 0},
1740 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1741 purpose of the `.dc.a' internal pseudo-op. */
1744 mips_address_bytes (void)
1746 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1749 extern void pop_insert (const pseudo_typeS *);
1752 mips_pop_insert (void)
1754 pop_insert (mips_pseudo_table);
1755 if (! ECOFF_DEBUGGING)
1756 pop_insert (mips_nonecoff_pseudo_table);
1759 /* Symbols labelling the current insn. */
1761 struct insn_label_list
1763 struct insn_label_list *next;
1767 static struct insn_label_list *free_insn_labels;
1768 #define label_list tc_segment_info_data.labels
1770 static void mips_clear_insn_labels (void);
1771 static void mips_mark_labels (void);
1772 static void mips_compressed_mark_labels (void);
1775 mips_clear_insn_labels (void)
1777 register struct insn_label_list **pl;
1778 segment_info_type *si;
1782 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1785 si = seg_info (now_seg);
1786 *pl = si->label_list;
1787 si->label_list = NULL;
1791 /* Mark instruction labels in MIPS16/microMIPS mode. */
1794 mips_mark_labels (void)
1796 if (HAVE_CODE_COMPRESSION)
1797 mips_compressed_mark_labels ();
1800 static char *expr_end;
1802 /* Expressions which appear in instructions. These are set by
1805 static expressionS imm_expr;
1806 static expressionS imm2_expr;
1807 static expressionS offset_expr;
1809 /* Relocs associated with imm_expr and offset_expr. */
1811 static bfd_reloc_code_real_type imm_reloc[3]
1812 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1813 static bfd_reloc_code_real_type offset_reloc[3]
1814 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1816 /* This is set to the resulting size of the instruction to be produced
1817 by mips16_ip if an explicit extension is used or by mips_ip if an
1818 explicit size is supplied. */
1820 static unsigned int forced_insn_length;
1822 /* True if we are assembling an instruction. All dot symbols defined during
1823 this time should be treated as code labels. */
1825 static bfd_boolean mips_assembling_insn;
1827 /* The pdr segment for per procedure frame/regmask info. Not used for
1830 static segT pdr_seg;
1832 /* The default target format to use. */
1834 #if defined (TE_FreeBSD)
1835 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1836 #elif defined (TE_TMIPS)
1837 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1839 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1843 mips_target_format (void)
1845 switch (OUTPUT_FLAVOR)
1847 case bfd_target_elf_flavour:
1849 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1850 return (target_big_endian
1851 ? "elf32-bigmips-vxworks"
1852 : "elf32-littlemips-vxworks");
1854 return (target_big_endian
1855 ? (HAVE_64BIT_OBJECTS
1856 ? ELF_TARGET ("elf64-", "big")
1858 ? ELF_TARGET ("elf32-n", "big")
1859 : ELF_TARGET ("elf32-", "big")))
1860 : (HAVE_64BIT_OBJECTS
1861 ? ELF_TARGET ("elf64-", "little")
1863 ? ELF_TARGET ("elf32-n", "little")
1864 : ELF_TARGET ("elf32-", "little"))));
1871 /* Return the ISA revision that is currently in use, or 0 if we are
1872 generating code for MIPS V or below. */
1877 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1880 /* microMIPS implies revision 2 or above. */
1881 if (mips_opts.micromips)
1884 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
1890 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
1893 mips_ase_mask (unsigned int flags)
1897 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
1898 if (flags & mips_ase_groups[i])
1899 flags |= mips_ase_groups[i];
1903 /* Check whether the current ISA supports ASE. Issue a warning if
1907 mips_check_isa_supports_ase (const struct mips_ase *ase)
1911 static unsigned int warned_isa;
1912 static unsigned int warned_fp32;
1914 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
1915 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
1917 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
1918 if ((min_rev < 0 || mips_isa_rev () < min_rev)
1919 && (warned_isa & ase->flags) != ase->flags)
1921 warned_isa |= ase->flags;
1922 base = mips_opts.micromips ? "microMIPS" : "MIPS";
1923 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
1925 as_warn (_("The %d-bit %s architecture does not support the"
1926 " `%s' extension"), size, base, ase->name);
1928 as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
1929 ase->name, base, size, min_rev);
1931 if ((ase->flags & FP64_ASES)
1933 && (warned_fp32 & ase->flags) != ase->flags)
1935 warned_fp32 |= ase->flags;
1936 as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
1940 /* Check all enabled ASEs to see whether they are supported by the
1941 chosen architecture. */
1944 mips_check_isa_supports_ases (void)
1946 unsigned int i, mask;
1948 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1950 mask = mips_ase_mask (mips_ases[i].flags);
1951 if ((mips_opts.ase & mask) == mips_ases[i].flags)
1952 mips_check_isa_supports_ase (&mips_ases[i]);
1956 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
1957 that were affected. */
1960 mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p)
1964 mask = mips_ase_mask (ase->flags);
1965 mips_opts.ase &= ~mask;
1967 mips_opts.ase |= ase->flags;
1971 /* Return the ASE called NAME, or null if none. */
1973 static const struct mips_ase *
1974 mips_lookup_ase (const char *name)
1978 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
1979 if (strcmp (name, mips_ases[i].name) == 0)
1980 return &mips_ases[i];
1984 /* Return the length of a microMIPS instruction in bytes. If bits of
1985 the mask beyond the low 16 are 0, then it is a 16-bit instruction.
1986 Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f
1987 major opcode) will require further modifications to the opcode
1990 static inline unsigned int
1991 micromips_insn_length (const struct mips_opcode *mo)
1993 return (mo->mask >> 16) == 0 ? 2 : 4;
1996 /* Return the length of MIPS16 instruction OPCODE. */
1998 static inline unsigned int
1999 mips16_opcode_length (unsigned long opcode)
2001 return (opcode >> 16) == 0 ? 2 : 4;
2004 /* Return the length of instruction INSN. */
2006 static inline unsigned int
2007 insn_length (const struct mips_cl_insn *insn)
2009 if (mips_opts.micromips)
2010 return micromips_insn_length (insn->insn_mo);
2011 else if (mips_opts.mips16)
2012 return mips16_opcode_length (insn->insn_opcode);
2017 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2020 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2025 insn->insn_opcode = mo->match;
2028 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2029 insn->fixp[i] = NULL;
2030 insn->fixed_p = (mips_opts.noreorder > 0);
2031 insn->noreorder_p = (mips_opts.noreorder > 0);
2032 insn->mips16_absolute_jump_p = 0;
2033 insn->complete_p = 0;
2034 insn->cleared_p = 0;
2037 /* Record the current MIPS16/microMIPS mode in now_seg. */
2040 mips_record_compressed_mode (void)
2042 segment_info_type *si;
2044 si = seg_info (now_seg);
2045 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2046 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2047 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2048 si->tc_segment_info_data.micromips = mips_opts.micromips;
2051 /* Read a standard MIPS instruction from BUF. */
2053 static unsigned long
2054 read_insn (char *buf)
2056 if (target_big_endian)
2057 return bfd_getb32 ((bfd_byte *) buf);
2059 return bfd_getl32 ((bfd_byte *) buf);
2062 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2066 write_insn (char *buf, unsigned int insn)
2068 md_number_to_chars (buf, insn, 4);
2072 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2073 has length LENGTH. */
2075 static unsigned long
2076 read_compressed_insn (char *buf, unsigned int length)
2082 for (i = 0; i < length; i += 2)
2085 if (target_big_endian)
2086 insn |= bfd_getb16 ((char *) buf);
2088 insn |= bfd_getl16 ((char *) buf);
2094 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2095 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2098 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2102 for (i = 0; i < length; i += 2)
2103 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2104 return buf + length;
2107 /* Install INSN at the location specified by its "frag" and "where" fields. */
2110 install_insn (const struct mips_cl_insn *insn)
2112 char *f = insn->frag->fr_literal + insn->where;
2113 if (HAVE_CODE_COMPRESSION)
2114 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2116 write_insn (f, insn->insn_opcode);
2117 mips_record_compressed_mode ();
2120 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2121 and install the opcode in the new location. */
2124 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2129 insn->where = where;
2130 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2131 if (insn->fixp[i] != NULL)
2133 insn->fixp[i]->fx_frag = frag;
2134 insn->fixp[i]->fx_where = where;
2136 install_insn (insn);
2139 /* Add INSN to the end of the output. */
2142 add_fixed_insn (struct mips_cl_insn *insn)
2144 char *f = frag_more (insn_length (insn));
2145 move_insn (insn, frag_now, f - frag_now->fr_literal);
2148 /* Start a variant frag and move INSN to the start of the variant part,
2149 marking it as fixed. The other arguments are as for frag_var. */
2152 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2153 relax_substateT subtype, symbolS *symbol, offsetT offset)
2155 frag_grow (max_chars);
2156 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2158 frag_var (rs_machine_dependent, max_chars, var,
2159 subtype, symbol, offset, NULL);
2162 /* Insert N copies of INSN into the history buffer, starting at
2163 position FIRST. Neither FIRST nor N need to be clipped. */
2166 insert_into_history (unsigned int first, unsigned int n,
2167 const struct mips_cl_insn *insn)
2169 if (mips_relax.sequence != 2)
2173 for (i = ARRAY_SIZE (history); i-- > first;)
2175 history[i] = history[i - n];
2181 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2182 the idea is to make it obvious at a glance that each errata is
2186 init_vr4120_conflicts (void)
2188 #define CONFLICT(FIRST, SECOND) \
2189 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2191 /* Errata 21 - [D]DIV[U] after [D]MACC */
2192 CONFLICT (MACC, DIV);
2193 CONFLICT (DMACC, DIV);
2195 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2196 CONFLICT (DMULT, DMULT);
2197 CONFLICT (DMULT, DMACC);
2198 CONFLICT (DMACC, DMULT);
2199 CONFLICT (DMACC, DMACC);
2201 /* Errata 24 - MT{LO,HI} after [D]MACC */
2202 CONFLICT (MACC, MTHILO);
2203 CONFLICT (DMACC, MTHILO);
2205 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2206 instruction is executed immediately after a MACC or DMACC
2207 instruction, the result of [either instruction] is incorrect." */
2208 CONFLICT (MACC, MULT);
2209 CONFLICT (MACC, DMULT);
2210 CONFLICT (DMACC, MULT);
2211 CONFLICT (DMACC, DMULT);
2213 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2214 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2215 DDIV or DDIVU instruction, the result of the MACC or
2216 DMACC instruction is incorrect.". */
2217 CONFLICT (DMULT, MACC);
2218 CONFLICT (DMULT, DMACC);
2219 CONFLICT (DIV, MACC);
2220 CONFLICT (DIV, DMACC);
2230 #define RTYPE_MASK 0x1ff00
2231 #define RTYPE_NUM 0x00100
2232 #define RTYPE_FPU 0x00200
2233 #define RTYPE_FCC 0x00400
2234 #define RTYPE_VEC 0x00800
2235 #define RTYPE_GP 0x01000
2236 #define RTYPE_CP0 0x02000
2237 #define RTYPE_PC 0x04000
2238 #define RTYPE_ACC 0x08000
2239 #define RTYPE_CCC 0x10000
2240 #define RNUM_MASK 0x000ff
2241 #define RWARN 0x80000
2243 #define GENERIC_REGISTER_NUMBERS \
2244 {"$0", RTYPE_NUM | 0}, \
2245 {"$1", RTYPE_NUM | 1}, \
2246 {"$2", RTYPE_NUM | 2}, \
2247 {"$3", RTYPE_NUM | 3}, \
2248 {"$4", RTYPE_NUM | 4}, \
2249 {"$5", RTYPE_NUM | 5}, \
2250 {"$6", RTYPE_NUM | 6}, \
2251 {"$7", RTYPE_NUM | 7}, \
2252 {"$8", RTYPE_NUM | 8}, \
2253 {"$9", RTYPE_NUM | 9}, \
2254 {"$10", RTYPE_NUM | 10}, \
2255 {"$11", RTYPE_NUM | 11}, \
2256 {"$12", RTYPE_NUM | 12}, \
2257 {"$13", RTYPE_NUM | 13}, \
2258 {"$14", RTYPE_NUM | 14}, \
2259 {"$15", RTYPE_NUM | 15}, \
2260 {"$16", RTYPE_NUM | 16}, \
2261 {"$17", RTYPE_NUM | 17}, \
2262 {"$18", RTYPE_NUM | 18}, \
2263 {"$19", RTYPE_NUM | 19}, \
2264 {"$20", RTYPE_NUM | 20}, \
2265 {"$21", RTYPE_NUM | 21}, \
2266 {"$22", RTYPE_NUM | 22}, \
2267 {"$23", RTYPE_NUM | 23}, \
2268 {"$24", RTYPE_NUM | 24}, \
2269 {"$25", RTYPE_NUM | 25}, \
2270 {"$26", RTYPE_NUM | 26}, \
2271 {"$27", RTYPE_NUM | 27}, \
2272 {"$28", RTYPE_NUM | 28}, \
2273 {"$29", RTYPE_NUM | 29}, \
2274 {"$30", RTYPE_NUM | 30}, \
2275 {"$31", RTYPE_NUM | 31}
2277 #define FPU_REGISTER_NAMES \
2278 {"$f0", RTYPE_FPU | 0}, \
2279 {"$f1", RTYPE_FPU | 1}, \
2280 {"$f2", RTYPE_FPU | 2}, \
2281 {"$f3", RTYPE_FPU | 3}, \
2282 {"$f4", RTYPE_FPU | 4}, \
2283 {"$f5", RTYPE_FPU | 5}, \
2284 {"$f6", RTYPE_FPU | 6}, \
2285 {"$f7", RTYPE_FPU | 7}, \
2286 {"$f8", RTYPE_FPU | 8}, \
2287 {"$f9", RTYPE_FPU | 9}, \
2288 {"$f10", RTYPE_FPU | 10}, \
2289 {"$f11", RTYPE_FPU | 11}, \
2290 {"$f12", RTYPE_FPU | 12}, \
2291 {"$f13", RTYPE_FPU | 13}, \
2292 {"$f14", RTYPE_FPU | 14}, \
2293 {"$f15", RTYPE_FPU | 15}, \
2294 {"$f16", RTYPE_FPU | 16}, \
2295 {"$f17", RTYPE_FPU | 17}, \
2296 {"$f18", RTYPE_FPU | 18}, \
2297 {"$f19", RTYPE_FPU | 19}, \
2298 {"$f20", RTYPE_FPU | 20}, \
2299 {"$f21", RTYPE_FPU | 21}, \
2300 {"$f22", RTYPE_FPU | 22}, \
2301 {"$f23", RTYPE_FPU | 23}, \
2302 {"$f24", RTYPE_FPU | 24}, \
2303 {"$f25", RTYPE_FPU | 25}, \
2304 {"$f26", RTYPE_FPU | 26}, \
2305 {"$f27", RTYPE_FPU | 27}, \
2306 {"$f28", RTYPE_FPU | 28}, \
2307 {"$f29", RTYPE_FPU | 29}, \
2308 {"$f30", RTYPE_FPU | 30}, \
2309 {"$f31", RTYPE_FPU | 31}
2311 #define FPU_CONDITION_CODE_NAMES \
2312 {"$fcc0", RTYPE_FCC | 0}, \
2313 {"$fcc1", RTYPE_FCC | 1}, \
2314 {"$fcc2", RTYPE_FCC | 2}, \
2315 {"$fcc3", RTYPE_FCC | 3}, \
2316 {"$fcc4", RTYPE_FCC | 4}, \
2317 {"$fcc5", RTYPE_FCC | 5}, \
2318 {"$fcc6", RTYPE_FCC | 6}, \
2319 {"$fcc7", RTYPE_FCC | 7}
2321 #define COPROC_CONDITION_CODE_NAMES \
2322 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2323 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2324 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2325 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2326 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2327 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2328 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2329 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2331 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2332 {"$a4", RTYPE_GP | 8}, \
2333 {"$a5", RTYPE_GP | 9}, \
2334 {"$a6", RTYPE_GP | 10}, \
2335 {"$a7", RTYPE_GP | 11}, \
2336 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2337 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2338 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2339 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2340 {"$t0", RTYPE_GP | 12}, \
2341 {"$t1", RTYPE_GP | 13}, \
2342 {"$t2", RTYPE_GP | 14}, \
2343 {"$t3", RTYPE_GP | 15}
2345 #define O32_SYMBOLIC_REGISTER_NAMES \
2346 {"$t0", RTYPE_GP | 8}, \
2347 {"$t1", RTYPE_GP | 9}, \
2348 {"$t2", RTYPE_GP | 10}, \
2349 {"$t3", RTYPE_GP | 11}, \
2350 {"$t4", RTYPE_GP | 12}, \
2351 {"$t5", RTYPE_GP | 13}, \
2352 {"$t6", RTYPE_GP | 14}, \
2353 {"$t7", RTYPE_GP | 15}, \
2354 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2355 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2356 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2357 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2359 /* Remaining symbolic register names */
2360 #define SYMBOLIC_REGISTER_NAMES \
2361 {"$zero", RTYPE_GP | 0}, \
2362 {"$at", RTYPE_GP | 1}, \
2363 {"$AT", RTYPE_GP | 1}, \
2364 {"$v0", RTYPE_GP | 2}, \
2365 {"$v1", RTYPE_GP | 3}, \
2366 {"$a0", RTYPE_GP | 4}, \
2367 {"$a1", RTYPE_GP | 5}, \
2368 {"$a2", RTYPE_GP | 6}, \
2369 {"$a3", RTYPE_GP | 7}, \
2370 {"$s0", RTYPE_GP | 16}, \
2371 {"$s1", RTYPE_GP | 17}, \
2372 {"$s2", RTYPE_GP | 18}, \
2373 {"$s3", RTYPE_GP | 19}, \
2374 {"$s4", RTYPE_GP | 20}, \
2375 {"$s5", RTYPE_GP | 21}, \
2376 {"$s6", RTYPE_GP | 22}, \
2377 {"$s7", RTYPE_GP | 23}, \
2378 {"$t8", RTYPE_GP | 24}, \
2379 {"$t9", RTYPE_GP | 25}, \
2380 {"$k0", RTYPE_GP | 26}, \
2381 {"$kt0", RTYPE_GP | 26}, \
2382 {"$k1", RTYPE_GP | 27}, \
2383 {"$kt1", RTYPE_GP | 27}, \
2384 {"$gp", RTYPE_GP | 28}, \
2385 {"$sp", RTYPE_GP | 29}, \
2386 {"$s8", RTYPE_GP | 30}, \
2387 {"$fp", RTYPE_GP | 30}, \
2388 {"$ra", RTYPE_GP | 31}
2390 #define MIPS16_SPECIAL_REGISTER_NAMES \
2391 {"$pc", RTYPE_PC | 0}
2393 #define MDMX_VECTOR_REGISTER_NAMES \
2394 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
2395 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
2396 {"$v2", RTYPE_VEC | 2}, \
2397 {"$v3", RTYPE_VEC | 3}, \
2398 {"$v4", RTYPE_VEC | 4}, \
2399 {"$v5", RTYPE_VEC | 5}, \
2400 {"$v6", RTYPE_VEC | 6}, \
2401 {"$v7", RTYPE_VEC | 7}, \
2402 {"$v8", RTYPE_VEC | 8}, \
2403 {"$v9", RTYPE_VEC | 9}, \
2404 {"$v10", RTYPE_VEC | 10}, \
2405 {"$v11", RTYPE_VEC | 11}, \
2406 {"$v12", RTYPE_VEC | 12}, \
2407 {"$v13", RTYPE_VEC | 13}, \
2408 {"$v14", RTYPE_VEC | 14}, \
2409 {"$v15", RTYPE_VEC | 15}, \
2410 {"$v16", RTYPE_VEC | 16}, \
2411 {"$v17", RTYPE_VEC | 17}, \
2412 {"$v18", RTYPE_VEC | 18}, \
2413 {"$v19", RTYPE_VEC | 19}, \
2414 {"$v20", RTYPE_VEC | 20}, \
2415 {"$v21", RTYPE_VEC | 21}, \
2416 {"$v22", RTYPE_VEC | 22}, \
2417 {"$v23", RTYPE_VEC | 23}, \
2418 {"$v24", RTYPE_VEC | 24}, \
2419 {"$v25", RTYPE_VEC | 25}, \
2420 {"$v26", RTYPE_VEC | 26}, \
2421 {"$v27", RTYPE_VEC | 27}, \
2422 {"$v28", RTYPE_VEC | 28}, \
2423 {"$v29", RTYPE_VEC | 29}, \
2424 {"$v30", RTYPE_VEC | 30}, \
2425 {"$v31", RTYPE_VEC | 31}
2427 #define MIPS_DSP_ACCUMULATOR_NAMES \
2428 {"$ac0", RTYPE_ACC | 0}, \
2429 {"$ac1", RTYPE_ACC | 1}, \
2430 {"$ac2", RTYPE_ACC | 2}, \
2431 {"$ac3", RTYPE_ACC | 3}
2433 static const struct regname reg_names[] = {
2434 GENERIC_REGISTER_NUMBERS,
2436 FPU_CONDITION_CODE_NAMES,
2437 COPROC_CONDITION_CODE_NAMES,
2439 /* The $txx registers depends on the abi,
2440 these will be added later into the symbol table from
2441 one of the tables below once mips_abi is set after
2442 parsing of arguments from the command line. */
2443 SYMBOLIC_REGISTER_NAMES,
2445 MIPS16_SPECIAL_REGISTER_NAMES,
2446 MDMX_VECTOR_REGISTER_NAMES,
2447 MIPS_DSP_ACCUMULATOR_NAMES,
2451 static const struct regname reg_names_o32[] = {
2452 O32_SYMBOLIC_REGISTER_NAMES,
2456 static const struct regname reg_names_n32n64[] = {
2457 N32N64_SYMBOLIC_REGISTER_NAMES,
2461 /* Check if S points at a valid register specifier according to TYPES.
2462 If so, then return 1, advance S to consume the specifier and store
2463 the register's number in REGNOP, otherwise return 0. */
2466 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
2473 /* Find end of name. */
2475 if (is_name_beginner (*e))
2477 while (is_part_of_name (*e))
2480 /* Terminate name. */
2484 /* Look for a register symbol. */
2485 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
2487 int r = S_GET_VALUE (symbolP);
2489 reg = r & RNUM_MASK;
2490 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
2491 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
2492 reg = (r & RNUM_MASK) - 2;
2494 /* Else see if this is a register defined in an itbl entry. */
2495 else if ((types & RTYPE_GP) && itbl_have_entries)
2502 if (itbl_get_reg_val (n, &r))
2503 reg = r & RNUM_MASK;
2506 /* Advance to next token if a register was recognised. */
2509 else if (types & RWARN)
2510 as_warn (_("Unrecognized register name `%s'"), *s);
2518 /* Check if S points at a valid register list according to TYPES.
2519 If so, then return 1, advance S to consume the list and store
2520 the registers present on the list as a bitmask of ones in REGLISTP,
2521 otherwise return 0. A valid list comprises a comma-separated
2522 enumeration of valid single registers and/or dash-separated
2523 contiguous register ranges as determined by their numbers.
2525 As a special exception if one of s0-s7 registers is specified as
2526 the range's lower delimiter and s8 (fp) is its upper one, then no
2527 registers whose numbers place them between s7 and s8 (i.e. $24-$29)
2528 are selected; they have to be listed separately if needed. */
2531 reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
2533 unsigned int reglist = 0;
2534 unsigned int lastregno;
2535 bfd_boolean ok = TRUE;
2536 unsigned int regmask;
2537 char *s_endlist = *s;
2541 while (reg_lookup (s, types, ®no))
2547 ok = reg_lookup (s, types, &lastregno);
2548 if (ok && lastregno < regno)
2554 if (lastregno == FP && regno >= S0 && regno <= S7)
2559 regmask = 1 << lastregno;
2560 regmask = (regmask << 1) - 1;
2561 regmask ^= (1 << regno) - 1;
2575 *reglistp = reglist;
2576 return ok && reglist != 0;
2579 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
2580 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
2583 is_opcode_valid (const struct mips_opcode *mo)
2585 int isa = mips_opts.isa;
2586 int ase = mips_opts.ase;
2590 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2591 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2592 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
2593 ase |= mips_ases[i].flags64;
2595 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
2598 /* Check whether the instruction or macro requires single-precision or
2599 double-precision floating-point support. Note that this information is
2600 stored differently in the opcode table for insns and macros. */
2601 if (mo->pinfo == INSN_MACRO)
2603 fp_s = mo->pinfo2 & INSN2_M_FP_S;
2604 fp_d = mo->pinfo2 & INSN2_M_FP_D;
2608 fp_s = mo->pinfo & FP_S;
2609 fp_d = mo->pinfo & FP_D;
2612 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
2615 if (fp_s && mips_opts.soft_float)
2621 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
2622 selected ISA and architecture. */
2625 is_opcode_valid_16 (const struct mips_opcode *mo)
2627 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
2630 /* Return TRUE if the size of the microMIPS opcode MO matches one
2631 explicitly requested. Always TRUE in the standard MIPS mode. */
2634 is_size_valid (const struct mips_opcode *mo)
2636 if (!mips_opts.micromips)
2639 if (!forced_insn_length)
2641 if (mo->pinfo == INSN_MACRO)
2643 return forced_insn_length == micromips_insn_length (mo);
2646 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
2647 of the preceding instruction. Always TRUE in the standard MIPS mode.
2649 We don't accept macros in 16-bit delay slots to avoid a case where
2650 a macro expansion fails because it relies on a preceding 32-bit real
2651 instruction to have matched and does not handle the operands correctly.
2652 The only macros that may expand to 16-bit instructions are JAL that
2653 cannot be placed in a delay slot anyway, and corner cases of BALIGN
2654 and BGT (that likewise cannot be placed in a delay slot) that decay to
2655 a NOP. In all these cases the macros precede any corresponding real
2656 instruction definitions in the opcode table, so they will match in the
2657 second pass where the size of the delay slot is ignored and therefore
2658 produce correct code. */
2661 is_delay_slot_valid (const struct mips_opcode *mo)
2663 if (!mips_opts.micromips)
2666 if (mo->pinfo == INSN_MACRO)
2667 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
2668 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
2669 && micromips_insn_length (mo) != 4)
2671 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
2672 && micromips_insn_length (mo) != 2)
2678 /* This function is called once, at assembler startup time. It should set up
2679 all the tables, etc. that the MD part of the assembler will need. */
2684 const char *retval = NULL;
2688 if (mips_pic != NO_PIC)
2690 if (g_switch_seen && g_switch_value != 0)
2691 as_bad (_("-G may not be used in position-independent code"));
2695 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
2696 as_warn (_("Could not set architecture and machine"));
2698 op_hash = hash_new ();
2700 for (i = 0; i < NUMOPCODES;)
2702 const char *name = mips_opcodes[i].name;
2704 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
2707 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
2708 mips_opcodes[i].name, retval);
2709 /* Probably a memory allocation problem? Give up now. */
2710 as_fatal (_("Broken assembler. No assembly attempted."));
2714 if (mips_opcodes[i].pinfo != INSN_MACRO)
2716 if (!validate_mips_insn (&mips_opcodes[i]))
2718 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2720 create_insn (&nop_insn, mips_opcodes + i);
2721 if (mips_fix_loongson2f_nop)
2722 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
2723 nop_insn.fixed_p = 1;
2728 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
2731 mips16_op_hash = hash_new ();
2734 while (i < bfd_mips16_num_opcodes)
2736 const char *name = mips16_opcodes[i].name;
2738 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
2740 as_fatal (_("internal: can't hash `%s': %s"),
2741 mips16_opcodes[i].name, retval);
2744 if (mips16_opcodes[i].pinfo != INSN_MACRO
2745 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
2746 != mips16_opcodes[i].match))
2748 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
2749 mips16_opcodes[i].name, mips16_opcodes[i].args);
2752 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
2754 create_insn (&mips16_nop_insn, mips16_opcodes + i);
2755 mips16_nop_insn.fixed_p = 1;
2759 while (i < bfd_mips16_num_opcodes
2760 && strcmp (mips16_opcodes[i].name, name) == 0);
2763 micromips_op_hash = hash_new ();
2766 while (i < bfd_micromips_num_opcodes)
2768 const char *name = micromips_opcodes[i].name;
2770 retval = hash_insert (micromips_op_hash, name,
2771 (void *) µmips_opcodes[i]);
2773 as_fatal (_("internal: can't hash `%s': %s"),
2774 micromips_opcodes[i].name, retval);
2776 if (micromips_opcodes[i].pinfo != INSN_MACRO)
2778 struct mips_cl_insn *micromips_nop_insn;
2780 if (!validate_micromips_insn (µmips_opcodes[i]))
2783 if (micromips_insn_length (micromips_opcodes + i) == 2)
2784 micromips_nop_insn = µmips_nop16_insn;
2785 else if (micromips_insn_length (micromips_opcodes + i) == 4)
2786 micromips_nop_insn = µmips_nop32_insn;
2790 if (micromips_nop_insn->insn_mo == NULL
2791 && strcmp (name, "nop") == 0)
2793 create_insn (micromips_nop_insn, micromips_opcodes + i);
2794 micromips_nop_insn->fixed_p = 1;
2797 while (++i < bfd_micromips_num_opcodes
2798 && strcmp (micromips_opcodes[i].name, name) == 0);
2802 as_fatal (_("Broken assembler. No assembly attempted."));
2804 /* We add all the general register names to the symbol table. This
2805 helps us detect invalid uses of them. */
2806 for (i = 0; reg_names[i].name; i++)
2807 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2808 reg_names[i].num, /* & RNUM_MASK, */
2809 &zero_address_frag));
2811 for (i = 0; reg_names_n32n64[i].name; i++)
2812 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2813 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2814 &zero_address_frag));
2816 for (i = 0; reg_names_o32[i].name; i++)
2817 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2818 reg_names_o32[i].num, /* & RNUM_MASK, */
2819 &zero_address_frag));
2821 mips_no_prev_insn ();
2824 mips_cprmask[0] = 0;
2825 mips_cprmask[1] = 0;
2826 mips_cprmask[2] = 0;
2827 mips_cprmask[3] = 0;
2829 /* set the default alignment for the text section (2**2) */
2830 record_alignment (text_section, 2);
2832 bfd_set_gp_size (stdoutput, g_switch_value);
2834 /* On a native system other than VxWorks, sections must be aligned
2835 to 16 byte boundaries. When configured for an embedded ELF
2836 target, we don't bother. */
2837 if (strncmp (TARGET_OS, "elf", 3) != 0
2838 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2840 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2841 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2842 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2845 /* Create a .reginfo section for register masks and a .mdebug
2846 section for debugging information. */
2854 subseg = now_subseg;
2856 /* The ABI says this section should be loaded so that the
2857 running program can access it. However, we don't load it
2858 if we are configured for an embedded target */
2859 flags = SEC_READONLY | SEC_DATA;
2860 if (strncmp (TARGET_OS, "elf", 3) != 0)
2861 flags |= SEC_ALLOC | SEC_LOAD;
2863 if (mips_abi != N64_ABI)
2865 sec = subseg_new (".reginfo", (subsegT) 0);
2867 bfd_set_section_flags (stdoutput, sec, flags);
2868 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2870 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2874 /* The 64-bit ABI uses a .MIPS.options section rather than
2875 .reginfo section. */
2876 sec = subseg_new (".MIPS.options", (subsegT) 0);
2877 bfd_set_section_flags (stdoutput, sec, flags);
2878 bfd_set_section_alignment (stdoutput, sec, 3);
2880 /* Set up the option header. */
2882 Elf_Internal_Options opthdr;
2885 opthdr.kind = ODK_REGINFO;
2886 opthdr.size = (sizeof (Elf_External_Options)
2887 + sizeof (Elf64_External_RegInfo));
2890 f = frag_more (sizeof (Elf_External_Options));
2891 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2892 (Elf_External_Options *) f);
2894 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2898 if (ECOFF_DEBUGGING)
2900 sec = subseg_new (".mdebug", (subsegT) 0);
2901 (void) bfd_set_section_flags (stdoutput, sec,
2902 SEC_HAS_CONTENTS | SEC_READONLY);
2903 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2905 else if (mips_flag_pdr)
2907 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2908 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2909 SEC_READONLY | SEC_RELOC
2911 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2914 subseg_set (seg, subseg);
2917 if (! ECOFF_DEBUGGING)
2920 if (mips_fix_vr4120)
2921 init_vr4120_conflicts ();
2927 mips_emit_delays ();
2928 if (! ECOFF_DEBUGGING)
2933 md_assemble (char *str)
2935 struct mips_cl_insn insn;
2936 bfd_reloc_code_real_type unused_reloc[3]
2937 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2939 imm_expr.X_op = O_absent;
2940 imm2_expr.X_op = O_absent;
2941 offset_expr.X_op = O_absent;
2942 imm_reloc[0] = BFD_RELOC_UNUSED;
2943 imm_reloc[1] = BFD_RELOC_UNUSED;
2944 imm_reloc[2] = BFD_RELOC_UNUSED;
2945 offset_reloc[0] = BFD_RELOC_UNUSED;
2946 offset_reloc[1] = BFD_RELOC_UNUSED;
2947 offset_reloc[2] = BFD_RELOC_UNUSED;
2949 mips_mark_labels ();
2950 mips_assembling_insn = TRUE;
2952 if (mips_opts.mips16)
2953 mips16_ip (str, &insn);
2956 mips_ip (str, &insn);
2957 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2958 str, insn.insn_opcode));
2962 as_bad ("%s `%s'", insn_error, str);
2963 else if (insn.insn_mo->pinfo == INSN_MACRO)
2966 if (mips_opts.mips16)
2967 mips16_macro (&insn);
2974 if (imm_expr.X_op != O_absent)
2975 append_insn (&insn, &imm_expr, imm_reloc, FALSE);
2976 else if (offset_expr.X_op != O_absent)
2977 append_insn (&insn, &offset_expr, offset_reloc, FALSE);
2979 append_insn (&insn, NULL, unused_reloc, FALSE);
2982 mips_assembling_insn = FALSE;
2985 /* Convenience functions for abstracting away the differences between
2986 MIPS16 and non-MIPS16 relocations. */
2988 static inline bfd_boolean
2989 mips16_reloc_p (bfd_reloc_code_real_type reloc)
2993 case BFD_RELOC_MIPS16_JMP:
2994 case BFD_RELOC_MIPS16_GPREL:
2995 case BFD_RELOC_MIPS16_GOT16:
2996 case BFD_RELOC_MIPS16_CALL16:
2997 case BFD_RELOC_MIPS16_HI16_S:
2998 case BFD_RELOC_MIPS16_HI16:
2999 case BFD_RELOC_MIPS16_LO16:
3007 static inline bfd_boolean
3008 micromips_reloc_p (bfd_reloc_code_real_type reloc)
3012 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3013 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3014 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3015 case BFD_RELOC_MICROMIPS_GPREL16:
3016 case BFD_RELOC_MICROMIPS_JMP:
3017 case BFD_RELOC_MICROMIPS_HI16:
3018 case BFD_RELOC_MICROMIPS_HI16_S:
3019 case BFD_RELOC_MICROMIPS_LO16:
3020 case BFD_RELOC_MICROMIPS_LITERAL:
3021 case BFD_RELOC_MICROMIPS_GOT16:
3022 case BFD_RELOC_MICROMIPS_CALL16:
3023 case BFD_RELOC_MICROMIPS_GOT_HI16:
3024 case BFD_RELOC_MICROMIPS_GOT_LO16:
3025 case BFD_RELOC_MICROMIPS_CALL_HI16:
3026 case BFD_RELOC_MICROMIPS_CALL_LO16:
3027 case BFD_RELOC_MICROMIPS_SUB:
3028 case BFD_RELOC_MICROMIPS_GOT_PAGE:
3029 case BFD_RELOC_MICROMIPS_GOT_OFST:
3030 case BFD_RELOC_MICROMIPS_GOT_DISP:
3031 case BFD_RELOC_MICROMIPS_HIGHEST:
3032 case BFD_RELOC_MICROMIPS_HIGHER:
3033 case BFD_RELOC_MICROMIPS_SCN_DISP:
3034 case BFD_RELOC_MICROMIPS_JALR:
3042 static inline bfd_boolean
3043 jmp_reloc_p (bfd_reloc_code_real_type reloc)
3045 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
3048 static inline bfd_boolean
3049 got16_reloc_p (bfd_reloc_code_real_type reloc)
3051 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
3052 || reloc == BFD_RELOC_MICROMIPS_GOT16);
3055 static inline bfd_boolean
3056 hi16_reloc_p (bfd_reloc_code_real_type reloc)
3058 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
3059 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
3062 static inline bfd_boolean
3063 lo16_reloc_p (bfd_reloc_code_real_type reloc)
3065 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
3066 || reloc == BFD_RELOC_MICROMIPS_LO16);
3069 static inline bfd_boolean
3070 jalr_reloc_p (bfd_reloc_code_real_type reloc)
3072 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
3075 /* Return true if RELOC is a PC-relative relocation that does not have
3076 full address range. */
3078 static inline bfd_boolean
3079 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
3083 case BFD_RELOC_16_PCREL_S2:
3084 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
3085 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
3086 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
3089 case BFD_RELOC_32_PCREL:
3090 return HAVE_64BIT_ADDRESSES;
3097 /* Return true if the given relocation might need a matching %lo().
3098 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
3099 need a matching %lo() when applied to local symbols. */
3101 static inline bfd_boolean
3102 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
3104 return (HAVE_IN_PLACE_ADDENDS
3105 && (hi16_reloc_p (reloc)
3106 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
3107 all GOT16 relocations evaluate to "G". */
3108 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
3111 /* Return the type of %lo() reloc needed by RELOC, given that
3112 reloc_needs_lo_p. */
3114 static inline bfd_reloc_code_real_type
3115 matching_lo_reloc (bfd_reloc_code_real_type reloc)
3117 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
3118 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
3122 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
3125 static inline bfd_boolean
3126 fixup_has_matching_lo_p (fixS *fixp)
3128 return (fixp->fx_next != NULL
3129 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
3130 && fixp->fx_addsy == fixp->fx_next->fx_addsy
3131 && fixp->fx_offset == fixp->fx_next->fx_offset);
3134 /* This function returns true if modifying a register requires a
3138 reg_needs_delay (unsigned int reg)
3140 unsigned long prev_pinfo;
3142 prev_pinfo = history[0].insn_mo->pinfo;
3143 if (! mips_opts.noreorder
3144 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
3145 && ! gpr_interlocks)
3146 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
3147 && ! cop_interlocks)))
3149 /* A load from a coprocessor or from memory. All load delays
3150 delay the use of general register rt for one instruction. */
3151 /* Itbl support may require additional care here. */
3152 know (prev_pinfo & INSN_WRITE_GPR_T);
3153 if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0]))
3160 /* Move all labels in LABELS to the current insertion point. TEXT_P
3161 says whether the labels refer to text or data. */
3164 mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p)
3166 struct insn_label_list *l;
3169 for (l = labels; l != NULL; l = l->next)
3171 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
3172 symbol_set_frag (l->label, frag_now);
3173 val = (valueT) frag_now_fix ();
3174 /* MIPS16/microMIPS text labels are stored as odd. */
3175 if (text_p && HAVE_CODE_COMPRESSION)
3177 S_SET_VALUE (l->label, val);
3181 /* Move all labels in insn_labels to the current insertion point
3182 and treat them as text labels. */
3185 mips_move_text_labels (void)
3187 mips_move_labels (seg_info (now_seg)->label_list, TRUE);
3191 s_is_linkonce (symbolS *sym, segT from_seg)
3193 bfd_boolean linkonce = FALSE;
3194 segT symseg = S_GET_SEGMENT (sym);
3196 if (symseg != from_seg && !S_IS_LOCAL (sym))
3198 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
3200 /* The GNU toolchain uses an extension for ELF: a section
3201 beginning with the magic string .gnu.linkonce is a
3202 linkonce section. */
3203 if (strncmp (segment_name (symseg), ".gnu.linkonce",
3204 sizeof ".gnu.linkonce" - 1) == 0)
3210 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
3211 linker to handle them specially, such as generating jalx instructions
3212 when needed. We also make them odd for the duration of the assembly,
3213 in order to generate the right sort of code. We will make them even
3214 in the adjust_symtab routine, while leaving them marked. This is
3215 convenient for the debugger and the disassembler. The linker knows
3216 to make them odd again. */
3219 mips_compressed_mark_label (symbolS *label)
3221 gas_assert (HAVE_CODE_COMPRESSION);
3223 if (mips_opts.mips16)
3224 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
3226 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
3227 if ((S_GET_VALUE (label) & 1) == 0
3228 /* Don't adjust the address if the label is global or weak, or
3229 in a link-once section, since we'll be emitting symbol reloc
3230 references to it which will be patched up by the linker, and
3231 the final value of the symbol may or may not be MIPS16/microMIPS. */
3232 && !S_IS_WEAK (label)
3233 && !S_IS_EXTERNAL (label)
3234 && !s_is_linkonce (label, now_seg))
3235 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
3238 /* Mark preceding MIPS16 or microMIPS instruction labels. */
3241 mips_compressed_mark_labels (void)
3243 struct insn_label_list *l;
3245 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
3246 mips_compressed_mark_label (l->label);
3249 /* End the current frag. Make it a variant frag and record the
3253 relax_close_frag (void)
3255 mips_macro_warning.first_frag = frag_now;
3256 frag_var (rs_machine_dependent, 0, 0,
3257 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
3258 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
3260 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
3261 mips_relax.first_fixup = 0;
3264 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
3265 See the comment above RELAX_ENCODE for more details. */
3268 relax_start (symbolS *symbol)
3270 gas_assert (mips_relax.sequence == 0);
3271 mips_relax.sequence = 1;
3272 mips_relax.symbol = symbol;
3275 /* Start generating the second version of a relaxable sequence.
3276 See the comment above RELAX_ENCODE for more details. */
3281 gas_assert (mips_relax.sequence == 1);
3282 mips_relax.sequence = 2;
3285 /* End the current relaxable sequence. */
3290 gas_assert (mips_relax.sequence == 2);
3291 relax_close_frag ();
3292 mips_relax.sequence = 0;
3295 /* Return true if IP is a delayed branch or jump. */
3297 static inline bfd_boolean
3298 delayed_branch_p (const struct mips_cl_insn *ip)
3300 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3301 | INSN_COND_BRANCH_DELAY
3302 | INSN_COND_BRANCH_LIKELY)) != 0;
3305 /* Return true if IP is a compact branch or jump. */
3307 static inline bfd_boolean
3308 compact_branch_p (const struct mips_cl_insn *ip)
3310 if (mips_opts.mips16)
3311 return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3312 | MIPS16_INSN_COND_BRANCH)) != 0;
3314 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
3315 | INSN2_COND_BRANCH)) != 0;
3318 /* Return true if IP is an unconditional branch or jump. */
3320 static inline bfd_boolean
3321 uncond_branch_p (const struct mips_cl_insn *ip)
3323 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
3324 || (mips_opts.mips16
3325 ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
3326 : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
3329 /* Return true if IP is a branch-likely instruction. */
3331 static inline bfd_boolean
3332 branch_likely_p (const struct mips_cl_insn *ip)
3334 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
3337 /* Return the type of nop that should be used to fill the delay slot
3338 of delayed branch IP. */
3340 static struct mips_cl_insn *
3341 get_delay_slot_nop (const struct mips_cl_insn *ip)
3343 if (mips_opts.micromips
3344 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
3345 return µmips_nop32_insn;
3349 /* Return the mask of core registers that IP reads or writes. */
3352 gpr_mod_mask (const struct mips_cl_insn *ip)
3354 unsigned long pinfo2;
3358 pinfo2 = ip->insn_mo->pinfo2;
3359 if (mips_opts.micromips)
3361 if (pinfo2 & INSN2_MOD_GPR_MD)
3362 mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
3363 if (pinfo2 & INSN2_MOD_GPR_MF)
3364 mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
3365 if (pinfo2 & INSN2_MOD_SP)
3371 /* Return the mask of core registers that IP reads. */
3374 gpr_read_mask (const struct mips_cl_insn *ip)
3376 unsigned long pinfo, pinfo2;
3379 mask = gpr_mod_mask (ip);
3380 pinfo = ip->insn_mo->pinfo;
3381 pinfo2 = ip->insn_mo->pinfo2;
3382 if (mips_opts.mips16)
3384 if (pinfo & MIPS16_INSN_READ_X)
3385 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3386 if (pinfo & MIPS16_INSN_READ_Y)
3387 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3388 if (pinfo & MIPS16_INSN_READ_T)
3390 if (pinfo & MIPS16_INSN_READ_SP)
3392 if (pinfo & MIPS16_INSN_READ_31)
3394 if (pinfo & MIPS16_INSN_READ_Z)
3395 mask |= 1 << (mips16_to_32_reg_map
3396 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
3397 if (pinfo & MIPS16_INSN_READ_GPR_X)
3398 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
3402 if (pinfo2 & INSN2_READ_GPR_D)
3403 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3404 if (pinfo & INSN_READ_GPR_T)
3405 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3406 if (pinfo & INSN_READ_GPR_S)
3407 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3408 if (pinfo2 & INSN2_READ_GP)
3410 if (pinfo2 & INSN2_READ_GPR_31)
3412 if (pinfo2 & INSN2_READ_GPR_Z)
3413 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3415 if (mips_opts.micromips)
3417 if (pinfo2 & INSN2_READ_GPR_MC)
3418 mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)];
3419 if (pinfo2 & INSN2_READ_GPR_ME)
3420 mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)];
3421 if (pinfo2 & INSN2_READ_GPR_MG)
3422 mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)];
3423 if (pinfo2 & INSN2_READ_GPR_MJ)
3424 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3425 if (pinfo2 & INSN2_READ_GPR_MMN)
3427 mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
3428 mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
3430 if (pinfo2 & INSN2_READ_GPR_MP)
3431 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3432 if (pinfo2 & INSN2_READ_GPR_MQ)
3433 mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)];
3435 /* Don't include register 0. */
3439 /* Return the mask of core registers that IP writes. */
3442 gpr_write_mask (const struct mips_cl_insn *ip)
3444 unsigned long pinfo, pinfo2;
3447 mask = gpr_mod_mask (ip);
3448 pinfo = ip->insn_mo->pinfo;
3449 pinfo2 = ip->insn_mo->pinfo2;
3450 if (mips_opts.mips16)
3452 if (pinfo & MIPS16_INSN_WRITE_X)
3453 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
3454 if (pinfo & MIPS16_INSN_WRITE_Y)
3455 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
3456 if (pinfo & MIPS16_INSN_WRITE_Z)
3457 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
3458 if (pinfo & MIPS16_INSN_WRITE_T)
3460 if (pinfo & MIPS16_INSN_WRITE_SP)
3462 if (pinfo & MIPS16_INSN_WRITE_31)
3464 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
3465 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
3469 if (pinfo & INSN_WRITE_GPR_D)
3470 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
3471 if (pinfo & INSN_WRITE_GPR_T)
3472 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
3473 if (pinfo & INSN_WRITE_GPR_S)
3474 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
3475 if (pinfo & INSN_WRITE_GPR_31)
3477 if (pinfo2 & INSN2_WRITE_GPR_Z)
3478 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
3480 if (mips_opts.micromips)
3482 if (pinfo2 & INSN2_WRITE_GPR_MB)
3483 mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
3484 if (pinfo2 & INSN2_WRITE_GPR_MHI)
3486 mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
3487 mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
3489 if (pinfo2 & INSN2_WRITE_GPR_MJ)
3490 mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
3491 if (pinfo2 & INSN2_WRITE_GPR_MP)
3492 mask |= 1 << EXTRACT_OPERAND (1, MP, *ip);
3494 /* Don't include register 0. */
3498 /* Return the mask of floating-point registers that IP reads. */
3501 fpr_read_mask (const struct mips_cl_insn *ip)
3503 unsigned long pinfo, pinfo2;
3507 pinfo = ip->insn_mo->pinfo;
3508 pinfo2 = ip->insn_mo->pinfo2;
3509 if (!mips_opts.mips16)
3511 if (pinfo2 & INSN2_READ_FPR_D)
3512 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3513 if (pinfo & INSN_READ_FPR_S)
3514 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3515 if (pinfo & INSN_READ_FPR_T)
3516 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3517 if (pinfo & INSN_READ_FPR_R)
3518 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip);
3519 if (pinfo2 & INSN2_READ_FPR_Z)
3520 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3522 /* Conservatively treat all operands to an FP_D instruction are doubles.
3523 (This is overly pessimistic for things like cvt.d.s.) */
3524 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3529 /* Return the mask of floating-point registers that IP writes. */
3532 fpr_write_mask (const struct mips_cl_insn *ip)
3534 unsigned long pinfo, pinfo2;
3538 pinfo = ip->insn_mo->pinfo;
3539 pinfo2 = ip->insn_mo->pinfo2;
3540 if (!mips_opts.mips16)
3542 if (pinfo & INSN_WRITE_FPR_D)
3543 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip);
3544 if (pinfo & INSN_WRITE_FPR_S)
3545 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip);
3546 if (pinfo & INSN_WRITE_FPR_T)
3547 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip);
3548 if (pinfo2 & INSN2_WRITE_FPR_Z)
3549 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip);
3551 /* Conservatively treat all operands to an FP_D instruction are doubles.
3552 (This is overly pessimistic for things like cvt.s.d.) */
3553 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
3558 /* Classify an instruction according to the FIX_VR4120_* enumeration.
3559 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
3560 by VR4120 errata. */
3563 classify_vr4120_insn (const char *name)
3565 if (strncmp (name, "macc", 4) == 0)
3566 return FIX_VR4120_MACC;
3567 if (strncmp (name, "dmacc", 5) == 0)
3568 return FIX_VR4120_DMACC;
3569 if (strncmp (name, "mult", 4) == 0)
3570 return FIX_VR4120_MULT;
3571 if (strncmp (name, "dmult", 5) == 0)
3572 return FIX_VR4120_DMULT;
3573 if (strstr (name, "div"))
3574 return FIX_VR4120_DIV;
3575 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
3576 return FIX_VR4120_MTHILO;
3577 return NUM_FIX_VR4120_CLASSES;
3580 #define INSN_ERET 0x42000018
3581 #define INSN_DERET 0x4200001f
3583 /* Return the number of instructions that must separate INSN1 and INSN2,
3584 where INSN1 is the earlier instruction. Return the worst-case value
3585 for any INSN2 if INSN2 is null. */
3588 insns_between (const struct mips_cl_insn *insn1,
3589 const struct mips_cl_insn *insn2)
3591 unsigned long pinfo1, pinfo2;
3594 /* This function needs to know which pinfo flags are set for INSN2
3595 and which registers INSN2 uses. The former is stored in PINFO2 and
3596 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
3597 will have every flag set and INSN2_USES_GPR will always return true. */
3598 pinfo1 = insn1->insn_mo->pinfo;
3599 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
3601 #define INSN2_USES_GPR(REG) \
3602 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
3604 /* For most targets, write-after-read dependencies on the HI and LO
3605 registers must be separated by at least two instructions. */
3606 if (!hilo_interlocks)
3608 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
3610 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
3614 /* If we're working around r7000 errata, there must be two instructions
3615 between an mfhi or mflo and any instruction that uses the result. */
3616 if (mips_7000_hilo_fix
3617 && !mips_opts.micromips
3618 && MF_HILO_INSN (pinfo1)
3619 && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1)))
3622 /* If we're working around 24K errata, one instruction is required
3623 if an ERET or DERET is followed by a branch instruction. */
3624 if (mips_fix_24k && !mips_opts.micromips)
3626 if (insn1->insn_opcode == INSN_ERET
3627 || insn1->insn_opcode == INSN_DERET)
3630 || insn2->insn_opcode == INSN_ERET
3631 || insn2->insn_opcode == INSN_DERET
3632 || delayed_branch_p (insn2))
3637 /* If working around VR4120 errata, check for combinations that need
3638 a single intervening instruction. */
3639 if (mips_fix_vr4120 && !mips_opts.micromips)
3641 unsigned int class1, class2;
3643 class1 = classify_vr4120_insn (insn1->insn_mo->name);
3644 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
3648 class2 = classify_vr4120_insn (insn2->insn_mo->name);
3649 if (vr4120_conflicts[class1] & (1 << class2))
3654 if (!HAVE_CODE_COMPRESSION)
3656 /* Check for GPR or coprocessor load delays. All such delays
3657 are on the RT register. */
3658 /* Itbl support may require additional care here. */
3659 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
3660 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
3662 know (pinfo1 & INSN_WRITE_GPR_T);
3663 if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1)))
3667 /* Check for generic coprocessor hazards.
3669 This case is not handled very well. There is no special
3670 knowledge of CP0 handling, and the coprocessors other than
3671 the floating point unit are not distinguished at all. */
3672 /* Itbl support may require additional care here. FIXME!
3673 Need to modify this to include knowledge about
3674 user specified delays! */
3675 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
3676 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
3678 /* Handle cases where INSN1 writes to a known general coprocessor
3679 register. There must be a one instruction delay before INSN2
3680 if INSN2 reads that register, otherwise no delay is needed. */
3681 mask = fpr_write_mask (insn1);
3684 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
3689 /* Read-after-write dependencies on the control registers
3690 require a two-instruction gap. */
3691 if ((pinfo1 & INSN_WRITE_COND_CODE)
3692 && (pinfo2 & INSN_READ_COND_CODE))
3695 /* We don't know exactly what INSN1 does. If INSN2 is
3696 also a coprocessor instruction, assume there must be
3697 a one instruction gap. */
3698 if (pinfo2 & INSN_COP)
3703 /* Check for read-after-write dependencies on the coprocessor
3704 control registers in cases where INSN1 does not need a general
3705 coprocessor delay. This means that INSN1 is a floating point
3706 comparison instruction. */
3707 /* Itbl support may require additional care here. */
3708 else if (!cop_interlocks
3709 && (pinfo1 & INSN_WRITE_COND_CODE)
3710 && (pinfo2 & INSN_READ_COND_CODE))
3714 #undef INSN2_USES_GPR
3719 /* Return the number of nops that would be needed to work around the
3720 VR4130 mflo/mfhi errata if instruction INSN immediately followed
3721 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
3722 that are contained within the first IGNORE instructions of HIST. */
3725 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
3726 const struct mips_cl_insn *insn)
3731 /* Check if the instruction writes to HI or LO. MTHI and MTLO
3732 are not affected by the errata. */
3734 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
3735 || strcmp (insn->insn_mo->name, "mtlo") == 0
3736 || strcmp (insn->insn_mo->name, "mthi") == 0))
3739 /* Search for the first MFLO or MFHI. */
3740 for (i = 0; i < MAX_VR4130_NOPS; i++)
3741 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
3743 /* Extract the destination register. */
3744 mask = gpr_write_mask (&hist[i]);
3746 /* No nops are needed if INSN reads that register. */
3747 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
3750 /* ...or if any of the intervening instructions do. */
3751 for (j = 0; j < i; j++)
3752 if (gpr_read_mask (&hist[j]) & mask)
3756 return MAX_VR4130_NOPS - i;
3761 #define BASE_REG_EQ(INSN1, INSN2) \
3762 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
3763 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
3765 /* Return the minimum alignment for this store instruction. */
3768 fix_24k_align_to (const struct mips_opcode *mo)
3770 if (strcmp (mo->name, "sh") == 0)
3773 if (strcmp (mo->name, "swc1") == 0
3774 || strcmp (mo->name, "swc2") == 0
3775 || strcmp (mo->name, "sw") == 0
3776 || strcmp (mo->name, "sc") == 0
3777 || strcmp (mo->name, "s.s") == 0)
3780 if (strcmp (mo->name, "sdc1") == 0
3781 || strcmp (mo->name, "sdc2") == 0
3782 || strcmp (mo->name, "s.d") == 0)
3789 struct fix_24k_store_info
3791 /* Immediate offset, if any, for this store instruction. */
3793 /* Alignment required by this store instruction. */
3795 /* True for register offsets. */
3796 int register_offset;
3799 /* Comparison function used by qsort. */
3802 fix_24k_sort (const void *a, const void *b)
3804 const struct fix_24k_store_info *pos1 = a;
3805 const struct fix_24k_store_info *pos2 = b;
3807 return (pos1->off - pos2->off);
3810 /* INSN is a store instruction. Try to record the store information
3811 in STINFO. Return false if the information isn't known. */
3814 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
3815 const struct mips_cl_insn *insn)
3817 /* The instruction must have a known offset. */
3818 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
3821 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
3822 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
3826 /* Return the number of nops that would be needed to work around the 24k
3827 "lost data on stores during refill" errata if instruction INSN
3828 immediately followed the 2 instructions described by HIST.
3829 Ignore hazards that are contained within the first IGNORE
3830 instructions of HIST.
3832 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
3833 for the data cache refills and store data. The following describes
3834 the scenario where the store data could be lost.
3836 * A data cache miss, due to either a load or a store, causing fill
3837 data to be supplied by the memory subsystem
3838 * The first three doublewords of fill data are returned and written
3840 * A sequence of four stores occurs in consecutive cycles around the
3841 final doubleword of the fill:
3845 * Zero, One or more instructions
3848 The four stores A-D must be to different doublewords of the line that
3849 is being filled. The fourth instruction in the sequence above permits
3850 the fill of the final doubleword to be transferred from the FSB into
3851 the cache. In the sequence above, the stores may be either integer
3852 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
3853 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
3854 different doublewords on the line. If the floating point unit is
3855 running in 1:2 mode, it is not possible to create the sequence above
3856 using only floating point store instructions.
3858 In this case, the cache line being filled is incorrectly marked
3859 invalid, thereby losing the data from any store to the line that
3860 occurs between the original miss and the completion of the five
3861 cycle sequence shown above.
3863 The workarounds are:
3865 * Run the data cache in write-through mode.
3866 * Insert a non-store instruction between
3867 Store A and Store B or Store B and Store C. */
3870 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
3871 const struct mips_cl_insn *insn)
3873 struct fix_24k_store_info pos[3];
3874 int align, i, base_offset;
3879 /* If the previous instruction wasn't a store, there's nothing to
3881 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3884 /* If the instructions after the previous one are unknown, we have
3885 to assume the worst. */
3889 /* Check whether we are dealing with three consecutive stores. */
3890 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
3891 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
3894 /* If we don't know the relationship between the store addresses,
3895 assume the worst. */
3896 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
3897 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
3900 if (!fix_24k_record_store_info (&pos[0], insn)
3901 || !fix_24k_record_store_info (&pos[1], &hist[0])
3902 || !fix_24k_record_store_info (&pos[2], &hist[1]))
3905 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
3907 /* Pick a value of ALIGN and X such that all offsets are adjusted by
3908 X bytes and such that the base register + X is known to be aligned
3911 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
3915 align = pos[0].align_to;
3916 base_offset = pos[0].off;
3917 for (i = 1; i < 3; i++)
3918 if (align < pos[i].align_to)
3920 align = pos[i].align_to;
3921 base_offset = pos[i].off;
3923 for (i = 0; i < 3; i++)
3924 pos[i].off -= base_offset;
3927 pos[0].off &= ~align + 1;
3928 pos[1].off &= ~align + 1;
3929 pos[2].off &= ~align + 1;
3931 /* If any two stores write to the same chunk, they also write to the
3932 same doubleword. The offsets are still sorted at this point. */
3933 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
3936 /* A range of at least 9 bytes is needed for the stores to be in
3937 non-overlapping doublewords. */
3938 if (pos[2].off - pos[0].off <= 8)
3941 if (pos[2].off - pos[1].off >= 24
3942 || pos[1].off - pos[0].off >= 24
3943 || pos[2].off - pos[0].off >= 32)
3949 /* Return the number of nops that would be needed if instruction INSN
3950 immediately followed the MAX_NOPS instructions given by HIST,
3951 where HIST[0] is the most recent instruction. Ignore hazards
3952 between INSN and the first IGNORE instructions in HIST.
3954 If INSN is null, return the worse-case number of nops for any
3958 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
3959 const struct mips_cl_insn *insn)
3961 int i, nops, tmp_nops;
3964 for (i = ignore; i < MAX_DELAY_NOPS; i++)
3966 tmp_nops = insns_between (hist + i, insn) - i;
3967 if (tmp_nops > nops)
3971 if (mips_fix_vr4130 && !mips_opts.micromips)
3973 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
3974 if (tmp_nops > nops)
3978 if (mips_fix_24k && !mips_opts.micromips)
3980 tmp_nops = nops_for_24k (ignore, hist, insn);
3981 if (tmp_nops > nops)
3988 /* The variable arguments provide NUM_INSNS extra instructions that
3989 might be added to HIST. Return the largest number of nops that
3990 would be needed after the extended sequence, ignoring hazards
3991 in the first IGNORE instructions. */
3994 nops_for_sequence (int num_insns, int ignore,
3995 const struct mips_cl_insn *hist, ...)
3998 struct mips_cl_insn buffer[MAX_NOPS];
3999 struct mips_cl_insn *cursor;
4002 va_start (args, hist);
4003 cursor = buffer + num_insns;
4004 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
4005 while (cursor > buffer)
4006 *--cursor = *va_arg (args, const struct mips_cl_insn *);
4008 nops = nops_for_insn (ignore, buffer, NULL);
4013 /* Like nops_for_insn, but if INSN is a branch, take into account the
4014 worst-case delay for the branch target. */
4017 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
4018 const struct mips_cl_insn *insn)
4022 nops = nops_for_insn (ignore, hist, insn);
4023 if (delayed_branch_p (insn))
4025 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
4026 hist, insn, get_delay_slot_nop (insn));
4027 if (tmp_nops > nops)
4030 else if (compact_branch_p (insn))
4032 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
4033 if (tmp_nops > nops)
4039 /* Fix NOP issue: Replace nops by "or at,at,zero". */
4042 fix_loongson2f_nop (struct mips_cl_insn * ip)
4044 gas_assert (!HAVE_CODE_COMPRESSION);
4045 if (strcmp (ip->insn_mo->name, "nop") == 0)
4046 ip->insn_opcode = LOONGSON2F_NOP_INSN;
4049 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
4050 jr target pc &= 'hffff_ffff_cfff_ffff. */
4053 fix_loongson2f_jump (struct mips_cl_insn * ip)
4055 gas_assert (!HAVE_CODE_COMPRESSION);
4056 if (strcmp (ip->insn_mo->name, "j") == 0
4057 || strcmp (ip->insn_mo->name, "jr") == 0
4058 || strcmp (ip->insn_mo->name, "jalr") == 0)
4066 sreg = EXTRACT_OPERAND (0, RS, *ip);
4067 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
4070 ep.X_op = O_constant;
4071 ep.X_add_number = 0xcfff0000;
4072 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
4073 ep.X_add_number = 0xffff;
4074 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
4075 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
4080 fix_loongson2f (struct mips_cl_insn * ip)
4082 if (mips_fix_loongson2f_nop)
4083 fix_loongson2f_nop (ip);
4085 if (mips_fix_loongson2f_jump)
4086 fix_loongson2f_jump (ip);
4089 /* IP is a branch that has a delay slot, and we need to fill it
4090 automatically. Return true if we can do that by swapping IP
4091 with the previous instruction.
4092 ADDRESS_EXPR is an operand of the instruction to be used with
4096 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
4097 bfd_reloc_code_real_type *reloc_type)
4099 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
4100 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
4102 /* -O2 and above is required for this optimization. */
4103 if (mips_optimize < 2)
4106 /* If we have seen .set volatile or .set nomove, don't optimize. */
4107 if (mips_opts.nomove)
4110 /* We can't swap if the previous instruction's position is fixed. */
4111 if (history[0].fixed_p)
4114 /* If the previous previous insn was in a .set noreorder, we can't
4115 swap. Actually, the MIPS assembler will swap in this situation.
4116 However, gcc configured -with-gnu-as will generate code like
4124 in which we can not swap the bne and INSN. If gcc is not configured
4125 -with-gnu-as, it does not output the .set pseudo-ops. */
4126 if (history[1].noreorder_p)
4129 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
4130 This means that the previous instruction was a 4-byte one anyhow. */
4131 if (mips_opts.mips16 && history[0].fixp[0])
4134 /* If the branch is itself the target of a branch, we can not swap.
4135 We cheat on this; all we check for is whether there is a label on
4136 this instruction. If there are any branches to anything other than
4137 a label, users must use .set noreorder. */
4138 if (seg_info (now_seg)->label_list)
4141 /* If the previous instruction is in a variant frag other than this
4142 branch's one, we cannot do the swap. This does not apply to
4143 MIPS16 code, which uses variant frags for different purposes. */
4144 if (!mips_opts.mips16
4146 && history[0].frag->fr_type == rs_machine_dependent)
4149 /* We do not swap with instructions that cannot architecturally
4150 be placed in a branch delay slot, such as SYNC or ERET. We
4151 also refrain from swapping with a trap instruction, since it
4152 complicates trap handlers to have the trap instruction be in
4154 prev_pinfo = history[0].insn_mo->pinfo;
4155 if (prev_pinfo & INSN_NO_DELAY_SLOT)
4158 /* Check for conflicts between the branch and the instructions
4159 before the candidate delay slot. */
4160 if (nops_for_insn (0, history + 1, ip) > 0)
4163 /* Check for conflicts between the swapped sequence and the
4164 target of the branch. */
4165 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
4168 /* If the branch reads a register that the previous
4169 instruction sets, we can not swap. */
4170 gpr_read = gpr_read_mask (ip);
4171 prev_gpr_write = gpr_write_mask (&history[0]);
4172 if (gpr_read & prev_gpr_write)
4175 /* If the branch writes a register that the previous
4176 instruction sets, we can not swap. */
4177 gpr_write = gpr_write_mask (ip);
4178 if (gpr_write & prev_gpr_write)
4181 /* If the branch writes a register that the previous
4182 instruction reads, we can not swap. */
4183 prev_gpr_read = gpr_read_mask (&history[0]);
4184 if (gpr_write & prev_gpr_read)
4187 /* If one instruction sets a condition code and the
4188 other one uses a condition code, we can not swap. */
4189 pinfo = ip->insn_mo->pinfo;
4190 if ((pinfo & INSN_READ_COND_CODE)
4191 && (prev_pinfo & INSN_WRITE_COND_CODE))
4193 if ((pinfo & INSN_WRITE_COND_CODE)
4194 && (prev_pinfo & INSN_READ_COND_CODE))
4197 /* If the previous instruction uses the PC, we can not swap. */
4198 prev_pinfo2 = history[0].insn_mo->pinfo2;
4199 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
4201 if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
4204 /* If the previous instruction has an incorrect size for a fixed
4205 branch delay slot in microMIPS mode, we cannot swap. */
4206 pinfo2 = ip->insn_mo->pinfo2;
4207 if (mips_opts.micromips
4208 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
4209 && insn_length (history) != 2)
4211 if (mips_opts.micromips
4212 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
4213 && insn_length (history) != 4)
4216 /* On R5900 short loops need to be fixed by inserting a nop in
4217 the branch delay slots.
4218 A short loop can be terminated too early. */
4219 if (mips_opts.arch == CPU_R5900
4220 /* Check if instruction has a parameter, ignore "j $31". */
4221 && (address_expr != NULL)
4222 /* Parameter must be 16 bit. */
4223 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
4224 /* Branch to same segment. */
4225 && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
4226 /* Branch to same code fragment. */
4227 && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
4228 /* Can only calculate branch offset if value is known. */
4229 && symbol_constant_p(address_expr->X_add_symbol)
4230 /* Check if branch is really conditional. */
4231 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
4232 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
4233 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
4236 /* Check if loop is shorter than 6 instructions including
4237 branch and delay slot. */
4238 distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
4245 /* When the loop includes branches or jumps,
4246 it is not a short loop. */
4247 for (i = 0; i < (distance / 4); i++)
4249 if ((history[i].cleared_p)
4250 || delayed_branch_p(&history[i]))
4258 /* Insert nop after branch to fix short loop. */
4267 /* Decide how we should add IP to the instruction stream.
4268 ADDRESS_EXPR is an operand of the instruction to be used with
4271 static enum append_method
4272 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
4273 bfd_reloc_code_real_type *reloc_type)
4275 unsigned long pinfo;
4277 /* The relaxed version of a macro sequence must be inherently
4279 if (mips_relax.sequence == 2)
4282 /* We must not dabble with instructions in a ".set norerorder" block. */
4283 if (mips_opts.noreorder)
4286 /* Otherwise, it's our responsibility to fill branch delay slots. */
4287 if (delayed_branch_p (ip))
4289 if (!branch_likely_p (ip)
4290 && can_swap_branch_p (ip, address_expr, reloc_type))
4293 pinfo = ip->insn_mo->pinfo;
4294 if (mips_opts.mips16
4295 && ISA_SUPPORTS_MIPS16E
4296 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
4297 return APPEND_ADD_COMPACT;
4299 return APPEND_ADD_WITH_NOP;
4305 /* IP is a MIPS16 instruction whose opcode we have just changed.
4306 Point IP->insn_mo to the new opcode's definition. */
4309 find_altered_mips16_opcode (struct mips_cl_insn *ip)
4311 const struct mips_opcode *mo, *end;
4313 end = &mips16_opcodes[bfd_mips16_num_opcodes];
4314 for (mo = ip->insn_mo; mo < end; mo++)
4315 if ((ip->insn_opcode & mo->mask) == mo->match)
4323 /* For microMIPS macros, we need to generate a local number label
4324 as the target of branches. */
4325 #define MICROMIPS_LABEL_CHAR '\037'
4326 static unsigned long micromips_target_label;
4327 static char micromips_target_name[32];
4330 micromips_label_name (void)
4332 char *p = micromips_target_name;
4333 char symbol_name_temporary[24];
4341 l = micromips_target_label;
4342 #ifdef LOCAL_LABEL_PREFIX
4343 *p++ = LOCAL_LABEL_PREFIX;
4346 *p++ = MICROMIPS_LABEL_CHAR;
4349 symbol_name_temporary[i++] = l % 10 + '0';
4354 *p++ = symbol_name_temporary[--i];
4357 return micromips_target_name;
4361 micromips_label_expr (expressionS *label_expr)
4363 label_expr->X_op = O_symbol;
4364 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
4365 label_expr->X_add_number = 0;
4369 micromips_label_inc (void)
4371 micromips_target_label++;
4372 *micromips_target_name = '\0';
4376 micromips_add_label (void)
4380 s = colon (micromips_label_name ());
4381 micromips_label_inc ();
4382 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
4385 /* If assembling microMIPS code, then return the microMIPS reloc
4386 corresponding to the requested one if any. Otherwise return
4387 the reloc unchanged. */
4389 static bfd_reloc_code_real_type
4390 micromips_map_reloc (bfd_reloc_code_real_type reloc)
4392 static const bfd_reloc_code_real_type relocs[][2] =
4394 /* Keep sorted incrementally by the left-hand key. */
4395 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
4396 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
4397 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
4398 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
4399 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
4400 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
4401 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
4402 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
4403 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
4404 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
4405 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
4406 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
4407 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
4408 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
4409 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
4410 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
4411 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
4412 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
4413 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
4414 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
4415 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
4416 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
4417 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
4418 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
4419 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
4420 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
4421 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
4423 bfd_reloc_code_real_type r;
4426 if (!mips_opts.micromips)
4428 for (i = 0; i < ARRAY_SIZE (relocs); i++)
4434 return relocs[i][1];
4439 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
4440 Return true on success, storing the resolved value in RESULT. */
4443 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
4448 case BFD_RELOC_MIPS_HIGHEST:
4449 case BFD_RELOC_MICROMIPS_HIGHEST:
4450 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
4453 case BFD_RELOC_MIPS_HIGHER:
4454 case BFD_RELOC_MICROMIPS_HIGHER:
4455 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
4458 case BFD_RELOC_HI16_S:
4459 case BFD_RELOC_MICROMIPS_HI16_S:
4460 case BFD_RELOC_MIPS16_HI16_S:
4461 *result = ((operand + 0x8000) >> 16) & 0xffff;
4464 case BFD_RELOC_HI16:
4465 case BFD_RELOC_MICROMIPS_HI16:
4466 case BFD_RELOC_MIPS16_HI16:
4467 *result = (operand >> 16) & 0xffff;
4470 case BFD_RELOC_LO16:
4471 case BFD_RELOC_MICROMIPS_LO16:
4472 case BFD_RELOC_MIPS16_LO16:
4473 *result = operand & 0xffff;
4476 case BFD_RELOC_UNUSED:
4485 /* Output an instruction. IP is the instruction information.
4486 ADDRESS_EXPR is an operand of the instruction to be used with
4487 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
4488 a macro expansion. */
4491 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
4492 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp)
4494 unsigned long prev_pinfo2, pinfo;
4495 bfd_boolean relaxed_branch = FALSE;
4496 enum append_method method;
4497 bfd_boolean relax32;
4500 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
4501 fix_loongson2f (ip);
4503 file_ase_mips16 |= mips_opts.mips16;
4504 file_ase_micromips |= mips_opts.micromips;
4506 prev_pinfo2 = history[0].insn_mo->pinfo2;
4507 pinfo = ip->insn_mo->pinfo;
4509 if (mips_opts.micromips
4511 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
4512 && micromips_insn_length (ip->insn_mo) != 2)
4513 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
4514 && micromips_insn_length (ip->insn_mo) != 4)))
4515 as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
4516 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
4518 if (address_expr == NULL)
4520 else if (reloc_type[0] <= BFD_RELOC_UNUSED
4521 && reloc_type[1] == BFD_RELOC_UNUSED
4522 && reloc_type[2] == BFD_RELOC_UNUSED
4523 && address_expr->X_op == O_constant)
4525 switch (*reloc_type)
4527 case BFD_RELOC_MIPS_JMP:
4531 shift = mips_opts.micromips ? 1 : 2;
4532 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4533 as_bad (_("jump to misaligned address (0x%lx)"),
4534 (unsigned long) address_expr->X_add_number);
4535 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4541 case BFD_RELOC_MIPS16_JMP:
4542 if ((address_expr->X_add_number & 3) != 0)
4543 as_bad (_("jump to misaligned address (0x%lx)"),
4544 (unsigned long) address_expr->X_add_number);
4546 (((address_expr->X_add_number & 0x7c0000) << 3)
4547 | ((address_expr->X_add_number & 0xf800000) >> 7)
4548 | ((address_expr->X_add_number & 0x3fffc) >> 2));
4552 case BFD_RELOC_16_PCREL_S2:
4556 shift = mips_opts.micromips ? 1 : 2;
4557 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
4558 as_bad (_("branch to misaligned address (0x%lx)"),
4559 (unsigned long) address_expr->X_add_number);
4560 if (!mips_relax_branch)
4562 if ((address_expr->X_add_number + (1 << (shift + 15)))
4563 & ~((1 << (shift + 16)) - 1))
4564 as_bad (_("branch address range overflow (0x%lx)"),
4565 (unsigned long) address_expr->X_add_number);
4566 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
4576 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
4579 ip->insn_opcode |= value & 0xffff;
4587 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
4589 /* There are a lot of optimizations we could do that we don't.
4590 In particular, we do not, in general, reorder instructions.
4591 If you use gcc with optimization, it will reorder
4592 instructions and generally do much more optimization then we
4593 do here; repeating all that work in the assembler would only
4594 benefit hand written assembly code, and does not seem worth
4596 int nops = (mips_optimize == 0
4597 ? nops_for_insn (0, history, NULL)
4598 : nops_for_insn_or_target (0, history, ip));
4602 unsigned long old_frag_offset;
4605 old_frag = frag_now;
4606 old_frag_offset = frag_now_fix ();
4608 for (i = 0; i < nops; i++)
4609 add_fixed_insn (NOP_INSN);
4610 insert_into_history (0, nops, NOP_INSN);
4614 listing_prev_line ();
4615 /* We may be at the start of a variant frag. In case we
4616 are, make sure there is enough space for the frag
4617 after the frags created by listing_prev_line. The
4618 argument to frag_grow here must be at least as large
4619 as the argument to all other calls to frag_grow in
4620 this file. We don't have to worry about being in the
4621 middle of a variant frag, because the variants insert
4622 all needed nop instructions themselves. */
4626 mips_move_text_labels ();
4628 #ifndef NO_ECOFF_DEBUGGING
4629 if (ECOFF_DEBUGGING)
4630 ecoff_fix_loc (old_frag, old_frag_offset);
4634 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
4638 /* Work out how many nops in prev_nop_frag are needed by IP,
4639 ignoring hazards generated by the first prev_nop_frag_since
4641 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
4642 gas_assert (nops <= prev_nop_frag_holds);
4644 /* Enforce NOPS as a minimum. */
4645 if (nops > prev_nop_frag_required)
4646 prev_nop_frag_required = nops;
4648 if (prev_nop_frag_holds == prev_nop_frag_required)
4650 /* Settle for the current number of nops. Update the history
4651 accordingly (for the benefit of any future .set reorder code). */
4652 prev_nop_frag = NULL;
4653 insert_into_history (prev_nop_frag_since,
4654 prev_nop_frag_holds, NOP_INSN);
4658 /* Allow this instruction to replace one of the nops that was
4659 tentatively added to prev_nop_frag. */
4660 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
4661 prev_nop_frag_holds--;
4662 prev_nop_frag_since++;
4666 method = get_append_method (ip, address_expr, reloc_type);
4667 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
4669 dwarf2_emit_insn (0);
4670 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
4671 so "move" the instruction address accordingly.
4673 Also, it doesn't seem appropriate for the assembler to reorder .loc
4674 entries. If this instruction is a branch that we are going to swap
4675 with the previous instruction, the two instructions should be
4676 treated as a unit, and the debug information for both instructions
4677 should refer to the start of the branch sequence. Using the
4678 current position is certainly wrong when swapping a 32-bit branch
4679 and a 16-bit delay slot, since the current position would then be
4680 in the middle of a branch. */
4681 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
4683 relax32 = (mips_relax_branch
4684 /* Don't try branch relaxation within .set nomacro, or within
4685 .set noat if we use $at for PIC computations. If it turns
4686 out that the branch was out-of-range, we'll get an error. */
4687 && !mips_opts.warn_about_macros
4688 && (mips_opts.at || mips_pic == NO_PIC)
4689 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
4690 as they have no complementing branches. */
4691 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
4693 if (!HAVE_CODE_COMPRESSION
4696 && *reloc_type == BFD_RELOC_16_PCREL_S2
4697 && delayed_branch_p (ip))
4699 relaxed_branch = TRUE;
4700 add_relaxed_insn (ip, (relaxed_branch_length
4702 uncond_branch_p (ip) ? -1
4703 : branch_likely_p (ip) ? 1
4707 uncond_branch_p (ip),
4708 branch_likely_p (ip),
4709 pinfo & INSN_WRITE_GPR_31,
4711 address_expr->X_add_symbol,
4712 address_expr->X_add_number);
4713 *reloc_type = BFD_RELOC_UNUSED;
4715 else if (mips_opts.micromips
4717 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
4718 || *reloc_type > BFD_RELOC_UNUSED)
4719 && (delayed_branch_p (ip) || compact_branch_p (ip))
4720 /* Don't try branch relaxation when users specify
4721 16-bit/32-bit instructions. */
4722 && !forced_insn_length)
4724 bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED;
4725 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
4726 int uncond = uncond_branch_p (ip) ? -1 : 0;
4727 int compact = compact_branch_p (ip);
4728 int al = pinfo & INSN_WRITE_GPR_31;
4731 gas_assert (address_expr != NULL);
4732 gas_assert (!mips_relax.sequence);
4734 relaxed_branch = TRUE;
4735 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
4736 add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4,
4737 RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al,
4739 address_expr->X_add_symbol,
4740 address_expr->X_add_number);
4741 *reloc_type = BFD_RELOC_UNUSED;
4743 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
4745 /* We need to set up a variant frag. */
4746 gas_assert (address_expr != NULL);
4747 add_relaxed_insn (ip, 4, 0,
4749 (*reloc_type - BFD_RELOC_UNUSED,
4750 forced_insn_length == 2, forced_insn_length == 4,
4751 delayed_branch_p (&history[0]),
4752 history[0].mips16_absolute_jump_p),
4753 make_expr_symbol (address_expr), 0);
4755 else if (mips_opts.mips16 && insn_length (ip) == 2)
4757 if (!delayed_branch_p (ip))
4758 /* Make sure there is enough room to swap this instruction with
4759 a following jump instruction. */
4761 add_fixed_insn (ip);
4765 if (mips_opts.mips16
4766 && mips_opts.noreorder
4767 && delayed_branch_p (&history[0]))
4768 as_warn (_("extended instruction in delay slot"));
4770 if (mips_relax.sequence)
4772 /* If we've reached the end of this frag, turn it into a variant
4773 frag and record the information for the instructions we've
4775 if (frag_room () < 4)
4776 relax_close_frag ();
4777 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
4780 if (mips_relax.sequence != 2)
4782 if (mips_macro_warning.first_insn_sizes[0] == 0)
4783 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
4784 mips_macro_warning.sizes[0] += insn_length (ip);
4785 mips_macro_warning.insns[0]++;
4787 if (mips_relax.sequence != 1)
4789 if (mips_macro_warning.first_insn_sizes[1] == 0)
4790 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
4791 mips_macro_warning.sizes[1] += insn_length (ip);
4792 mips_macro_warning.insns[1]++;
4795 if (mips_opts.mips16)
4798 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
4800 add_fixed_insn (ip);
4803 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
4805 bfd_reloc_code_real_type final_type[3];
4806 reloc_howto_type *howto0;
4807 reloc_howto_type *howto;
4810 /* Perform any necessary conversion to microMIPS relocations
4811 and find out how many relocations there actually are. */
4812 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
4813 final_type[i] = micromips_map_reloc (reloc_type[i]);
4815 /* In a compound relocation, it is the final (outermost)
4816 operator that determines the relocated field. */
4817 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
4822 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
4823 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
4824 bfd_get_reloc_size (howto),
4826 howto0 && howto0->pc_relative,
4829 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
4830 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
4831 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
4833 /* These relocations can have an addend that won't fit in
4834 4 octets for 64bit assembly. */
4836 && ! howto->partial_inplace
4837 && (reloc_type[0] == BFD_RELOC_16
4838 || reloc_type[0] == BFD_RELOC_32
4839 || reloc_type[0] == BFD_RELOC_MIPS_JMP
4840 || reloc_type[0] == BFD_RELOC_GPREL16
4841 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
4842 || reloc_type[0] == BFD_RELOC_GPREL32
4843 || reloc_type[0] == BFD_RELOC_64
4844 || reloc_type[0] == BFD_RELOC_CTOR
4845 || reloc_type[0] == BFD_RELOC_MIPS_SUB
4846 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
4847 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
4848 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
4849 || reloc_type[0] == BFD_RELOC_MIPS_REL16
4850 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
4851 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
4852 || hi16_reloc_p (reloc_type[0])
4853 || lo16_reloc_p (reloc_type[0])))
4854 ip->fixp[0]->fx_no_overflow = 1;
4856 /* These relocations can have an addend that won't fit in 2 octets. */
4857 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
4858 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
4859 ip->fixp[0]->fx_no_overflow = 1;
4861 if (mips_relax.sequence)
4863 if (mips_relax.first_fixup == 0)
4864 mips_relax.first_fixup = ip->fixp[0];
4866 else if (reloc_needs_lo_p (*reloc_type))
4868 struct mips_hi_fixup *hi_fixup;
4870 /* Reuse the last entry if it already has a matching %lo. */
4871 hi_fixup = mips_hi_fixup_list;
4873 || !fixup_has_matching_lo_p (hi_fixup->fixp))
4875 hi_fixup = ((struct mips_hi_fixup *)
4876 xmalloc (sizeof (struct mips_hi_fixup)));
4877 hi_fixup->next = mips_hi_fixup_list;
4878 mips_hi_fixup_list = hi_fixup;
4880 hi_fixup->fixp = ip->fixp[0];
4881 hi_fixup->seg = now_seg;
4884 /* Add fixups for the second and third relocations, if given.
4885 Note that the ABI allows the second relocation to be
4886 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
4887 moment we only use RSS_UNDEF, but we could add support
4888 for the others if it ever becomes necessary. */
4889 for (i = 1; i < 3; i++)
4890 if (reloc_type[i] != BFD_RELOC_UNUSED)
4892 ip->fixp[i] = fix_new (ip->frag, ip->where,
4893 ip->fixp[0]->fx_size, NULL, 0,
4894 FALSE, final_type[i]);
4896 /* Use fx_tcbit to mark compound relocs. */
4897 ip->fixp[0]->fx_tcbit = 1;
4898 ip->fixp[i]->fx_tcbit = 1;
4903 /* Update the register mask information. */
4904 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
4905 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
4910 insert_into_history (0, 1, ip);
4913 case APPEND_ADD_WITH_NOP:
4915 struct mips_cl_insn *nop;
4917 insert_into_history (0, 1, ip);
4918 nop = get_delay_slot_nop (ip);
4919 add_fixed_insn (nop);
4920 insert_into_history (0, 1, nop);
4921 if (mips_relax.sequence)
4922 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
4926 case APPEND_ADD_COMPACT:
4927 /* Convert MIPS16 jr/jalr into a "compact" jump. */
4928 gas_assert (mips_opts.mips16);
4929 ip->insn_opcode |= 0x0080;
4930 find_altered_mips16_opcode (ip);
4932 insert_into_history (0, 1, ip);
4937 struct mips_cl_insn delay = history[0];
4938 if (mips_opts.mips16)
4940 know (delay.frag == ip->frag);
4941 move_insn (ip, delay.frag, delay.where);
4942 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
4944 else if (relaxed_branch || delay.frag != ip->frag)
4946 /* Add the delay slot instruction to the end of the
4947 current frag and shrink the fixed part of the
4948 original frag. If the branch occupies the tail of
4949 the latter, move it backwards to cover the gap. */
4950 delay.frag->fr_fix -= branch_disp;
4951 if (delay.frag == ip->frag)
4952 move_insn (ip, ip->frag, ip->where - branch_disp);
4953 add_fixed_insn (&delay);
4957 move_insn (&delay, ip->frag,
4958 ip->where - branch_disp + insn_length (ip));
4959 move_insn (ip, history[0].frag, history[0].where);
4963 insert_into_history (0, 1, &delay);
4968 /* If we have just completed an unconditional branch, clear the history. */
4969 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
4970 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
4974 mips_no_prev_insn ();
4976 for (i = 0; i < ARRAY_SIZE (history); i++)
4977 history[i].cleared_p = 1;
4980 /* We need to emit a label at the end of branch-likely macros. */
4981 if (emit_branch_likely_macro)
4983 emit_branch_likely_macro = FALSE;
4984 micromips_add_label ();
4987 /* We just output an insn, so the next one doesn't have a label. */
4988 mips_clear_insn_labels ();
4991 /* Forget that there was any previous instruction or label.
4992 When BRANCH is true, the branch history is also flushed. */
4995 mips_no_prev_insn (void)
4997 prev_nop_frag = NULL;
4998 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
4999 mips_clear_insn_labels ();
5002 /* This function must be called before we emit something other than
5003 instructions. It is like mips_no_prev_insn except that it inserts
5004 any NOPS that might be needed by previous instructions. */
5007 mips_emit_delays (void)
5009 if (! mips_opts.noreorder)
5011 int nops = nops_for_insn (0, history, NULL);
5015 add_fixed_insn (NOP_INSN);
5016 mips_move_text_labels ();
5019 mips_no_prev_insn ();
5022 /* Start a (possibly nested) noreorder block. */
5025 start_noreorder (void)
5027 if (mips_opts.noreorder == 0)
5032 /* None of the instructions before the .set noreorder can be moved. */
5033 for (i = 0; i < ARRAY_SIZE (history); i++)
5034 history[i].fixed_p = 1;
5036 /* Insert any nops that might be needed between the .set noreorder
5037 block and the previous instructions. We will later remove any
5038 nops that turn out not to be needed. */
5039 nops = nops_for_insn (0, history, NULL);
5042 if (mips_optimize != 0)
5044 /* Record the frag which holds the nop instructions, so
5045 that we can remove them if we don't need them. */
5046 frag_grow (nops * NOP_INSN_SIZE);
5047 prev_nop_frag = frag_now;
5048 prev_nop_frag_holds = nops;
5049 prev_nop_frag_required = 0;
5050 prev_nop_frag_since = 0;
5053 for (; nops > 0; --nops)
5054 add_fixed_insn (NOP_INSN);
5056 /* Move on to a new frag, so that it is safe to simply
5057 decrease the size of prev_nop_frag. */
5058 frag_wane (frag_now);
5060 mips_move_text_labels ();
5062 mips_mark_labels ();
5063 mips_clear_insn_labels ();
5065 mips_opts.noreorder++;
5066 mips_any_noreorder = 1;
5069 /* End a nested noreorder block. */
5072 end_noreorder (void)
5074 mips_opts.noreorder--;
5075 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
5077 /* Commit to inserting prev_nop_frag_required nops and go back to
5078 handling nop insertion the .set reorder way. */
5079 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
5081 insert_into_history (prev_nop_frag_since,
5082 prev_nop_frag_required, NOP_INSN);
5083 prev_nop_frag = NULL;
5087 /* Set up global variables for the start of a new macro. */
5092 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
5093 memset (&mips_macro_warning.first_insn_sizes, 0,
5094 sizeof (mips_macro_warning.first_insn_sizes));
5095 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
5096 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
5097 && delayed_branch_p (&history[0]));
5098 switch (history[0].insn_mo->pinfo2
5099 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
5101 case INSN2_BRANCH_DELAY_32BIT:
5102 mips_macro_warning.delay_slot_length = 4;
5104 case INSN2_BRANCH_DELAY_16BIT:
5105 mips_macro_warning.delay_slot_length = 2;
5108 mips_macro_warning.delay_slot_length = 0;
5111 mips_macro_warning.first_frag = NULL;
5114 /* Given that a macro is longer than one instruction or of the wrong size,
5115 return the appropriate warning for it. Return null if no warning is
5116 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
5117 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
5118 and RELAX_NOMACRO. */
5121 macro_warning (relax_substateT subtype)
5123 if (subtype & RELAX_DELAY_SLOT)
5124 return _("Macro instruction expanded into multiple instructions"
5125 " in a branch delay slot");
5126 else if (subtype & RELAX_NOMACRO)
5127 return _("Macro instruction expanded into multiple instructions");
5128 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
5129 | RELAX_DELAY_SLOT_SIZE_SECOND))
5130 return ((subtype & RELAX_DELAY_SLOT_16BIT)
5131 ? _("Macro instruction expanded into a wrong size instruction"
5132 " in a 16-bit branch delay slot")
5133 : _("Macro instruction expanded into a wrong size instruction"
5134 " in a 32-bit branch delay slot"));
5139 /* Finish up a macro. Emit warnings as appropriate. */
5144 /* Relaxation warning flags. */
5145 relax_substateT subtype = 0;
5147 /* Check delay slot size requirements. */
5148 if (mips_macro_warning.delay_slot_length == 2)
5149 subtype |= RELAX_DELAY_SLOT_16BIT;
5150 if (mips_macro_warning.delay_slot_length != 0)
5152 if (mips_macro_warning.delay_slot_length
5153 != mips_macro_warning.first_insn_sizes[0])
5154 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
5155 if (mips_macro_warning.delay_slot_length
5156 != mips_macro_warning.first_insn_sizes[1])
5157 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
5160 /* Check instruction count requirements. */
5161 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
5163 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
5164 subtype |= RELAX_SECOND_LONGER;
5165 if (mips_opts.warn_about_macros)
5166 subtype |= RELAX_NOMACRO;
5167 if (mips_macro_warning.delay_slot_p)
5168 subtype |= RELAX_DELAY_SLOT;
5171 /* If both alternatives fail to fill a delay slot correctly,
5172 emit the warning now. */
5173 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
5174 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
5179 s = subtype & (RELAX_DELAY_SLOT_16BIT
5180 | RELAX_DELAY_SLOT_SIZE_FIRST
5181 | RELAX_DELAY_SLOT_SIZE_SECOND);
5182 msg = macro_warning (s);
5184 as_warn ("%s", msg);
5188 /* If both implementations are longer than 1 instruction, then emit the
5190 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
5195 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
5196 msg = macro_warning (s);
5198 as_warn ("%s", msg);
5202 /* If any flags still set, then one implementation might need a warning
5203 and the other either will need one of a different kind or none at all.
5204 Pass any remaining flags over to relaxation. */
5205 if (mips_macro_warning.first_frag != NULL)
5206 mips_macro_warning.first_frag->fr_subtype |= subtype;
5209 /* Instruction operand formats used in macros that vary between
5210 standard MIPS and microMIPS code. */
5212 static const char * const brk_fmt[2] = { "c", "mF" };
5213 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
5214 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
5215 static const char * const lui_fmt[2] = { "t,u", "s,u" };
5216 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
5217 static const char * const mfhl_fmt[2] = { "d", "mj" };
5218 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
5219 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
5221 #define BRK_FMT (brk_fmt[mips_opts.micromips])
5222 #define COP12_FMT (cop12_fmt[mips_opts.micromips])
5223 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
5224 #define LUI_FMT (lui_fmt[mips_opts.micromips])
5225 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
5226 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips])
5227 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
5228 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
5230 /* Read a macro's relocation codes from *ARGS and store them in *R.
5231 The first argument in *ARGS will be either the code for a single
5232 relocation or -1 followed by the three codes that make up a
5233 composite relocation. */
5236 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
5240 next = va_arg (*args, int);
5242 r[0] = (bfd_reloc_code_real_type) next;
5244 for (i = 0; i < 3; i++)
5245 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
5248 /* Build an instruction created by a macro expansion. This is passed
5249 a pointer to the count of instructions created so far, an
5250 expression, the name of the instruction to build, an operand format
5251 string, and corresponding arguments. */
5254 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
5256 const struct mips_opcode *mo = NULL;
5257 bfd_reloc_code_real_type r[3];
5258 const struct mips_opcode *amo;
5259 struct hash_control *hash;
5260 struct mips_cl_insn insn;
5263 va_start (args, fmt);
5265 if (mips_opts.mips16)
5267 mips16_macro_build (ep, name, fmt, &args);
5272 r[0] = BFD_RELOC_UNUSED;
5273 r[1] = BFD_RELOC_UNUSED;
5274 r[2] = BFD_RELOC_UNUSED;
5275 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
5276 amo = (struct mips_opcode *) hash_find (hash, name);
5278 gas_assert (strcmp (name, amo->name) == 0);
5282 /* Search until we get a match for NAME. It is assumed here that
5283 macros will never generate MDMX, MIPS-3D, or MT instructions.
5284 We try to match an instruction that fulfils the branch delay
5285 slot instruction length requirement (if any) of the previous
5286 instruction. While doing this we record the first instruction
5287 seen that matches all the other conditions and use it anyway
5288 if the requirement cannot be met; we will issue an appropriate
5289 warning later on. */
5290 if (strcmp (fmt, amo->args) == 0
5291 && amo->pinfo != INSN_MACRO
5292 && is_opcode_valid (amo)
5293 && is_size_valid (amo))
5295 if (is_delay_slot_valid (amo))
5305 gas_assert (amo->name);
5307 while (strcmp (name, amo->name) == 0);
5310 create_insn (&insn, mo);
5328 INSERT_OPERAND (mips_opts.micromips,
5329 EXTLSB, insn, va_arg (args, int));
5334 /* Note that in the macro case, these arguments are already
5335 in MSB form. (When handling the instruction in the
5336 non-macro case, these arguments are sizes from which
5337 MSB values must be calculated.) */
5338 INSERT_OPERAND (mips_opts.micromips,
5339 INSMSB, insn, va_arg (args, int));
5343 gas_assert (!mips_opts.micromips);
5344 INSERT_OPERAND (0, CODE10, insn, va_arg (args, int));
5350 /* Note that in the macro case, these arguments are already
5351 in MSBD form. (When handling the instruction in the
5352 non-macro case, these arguments are sizes from which
5353 MSBD values must be calculated.) */
5354 INSERT_OPERAND (mips_opts.micromips,
5355 EXTMSBD, insn, va_arg (args, int));
5359 gas_assert (!mips_opts.micromips);
5360 INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
5364 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
5373 INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int));
5377 gas_assert (mips_opts.micromips);
5381 INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int));
5385 gas_assert (!mips_opts.micromips);
5386 INSERT_OPERAND (0, CODE, insn, va_arg (args, int));
5390 gas_assert (!mips_opts.micromips);
5392 INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int));
5396 if (mips_opts.micromips)
5397 INSERT_OPERAND (1, RS, insn, va_arg (args, int));
5399 INSERT_OPERAND (0, RD, insn, va_arg (args, int));
5403 gas_assert (!mips_opts.micromips);
5405 INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int));
5409 gas_assert (!mips_opts.micromips);
5411 int tmp = va_arg (args, int);
5413 INSERT_OPERAND (0, RT, insn, tmp);
5414 INSERT_OPERAND (0, RD, insn, tmp);
5420 gas_assert (!mips_opts.micromips);
5421 INSERT_OPERAND (0, FS, insn, va_arg (args, int));
5428 INSERT_OPERAND (mips_opts.micromips,
5429 SHAMT, insn, va_arg (args, int));
5433 gas_assert (!mips_opts.micromips);
5434 INSERT_OPERAND (0, FD, insn, va_arg (args, int));
5438 gas_assert (!mips_opts.micromips);
5439 INSERT_OPERAND (0, CODE20, insn, va_arg (args, int));
5443 gas_assert (!mips_opts.micromips);
5444 INSERT_OPERAND (0, CODE19, insn, va_arg (args, int));
5448 gas_assert (!mips_opts.micromips);
5449 INSERT_OPERAND (0, CODE2, insn, va_arg (args, int));
5456 INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int));
5461 macro_read_relocs (&args, r);
5462 gas_assert (*r == BFD_RELOC_GPREL16
5463 || *r == BFD_RELOC_MIPS_HIGHER
5464 || *r == BFD_RELOC_HI16_S
5465 || *r == BFD_RELOC_LO16
5466 || *r == BFD_RELOC_MIPS_GOT_OFST);
5470 macro_read_relocs (&args, r);
5474 macro_read_relocs (&args, r);
5475 gas_assert (ep != NULL
5476 && (ep->X_op == O_constant
5477 || (ep->X_op == O_symbol
5478 && (*r == BFD_RELOC_MIPS_HIGHEST
5479 || *r == BFD_RELOC_HI16_S
5480 || *r == BFD_RELOC_HI16
5481 || *r == BFD_RELOC_GPREL16
5482 || *r == BFD_RELOC_MIPS_GOT_HI16
5483 || *r == BFD_RELOC_MIPS_CALL_HI16))));
5487 gas_assert (ep != NULL);
5490 * This allows macro() to pass an immediate expression for
5491 * creating short branches without creating a symbol.
5493 * We don't allow branch relaxation for these branches, as
5494 * they should only appear in ".set nomacro" anyway.
5496 if (ep->X_op == O_constant)
5498 /* For microMIPS we always use relocations for branches.
5499 So we should not resolve immediate values. */
5500 gas_assert (!mips_opts.micromips);
5502 if ((ep->X_add_number & 3) != 0)
5503 as_bad (_("branch to misaligned address (0x%lx)"),
5504 (unsigned long) ep->X_add_number);
5505 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
5506 as_bad (_("branch address range overflow (0x%lx)"),
5507 (unsigned long) ep->X_add_number);
5508 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
5512 *r = BFD_RELOC_16_PCREL_S2;
5516 gas_assert (ep != NULL);
5517 *r = BFD_RELOC_MIPS_JMP;
5521 gas_assert (!mips_opts.micromips);
5522 INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long));
5526 INSERT_OPERAND (mips_opts.micromips,
5527 CACHE, insn, va_arg (args, unsigned long));
5531 gas_assert (mips_opts.micromips);
5532 INSERT_OPERAND (1, TRAP, insn, va_arg (args, int));
5536 gas_assert (mips_opts.micromips);
5537 INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int));
5541 INSERT_OPERAND (mips_opts.micromips,
5542 3BITPOS, insn, va_arg (args, unsigned int));
5546 INSERT_OPERAND (mips_opts.micromips,
5547 OFFSET12, insn, va_arg (args, unsigned long));
5551 gas_assert (mips_opts.micromips);
5552 INSERT_OPERAND (1, BCC, insn, va_arg (args, int));
5555 case 'm': /* Opcode extension character. */
5556 gas_assert (mips_opts.micromips);
5560 INSERT_OPERAND (1, MJ, insn, va_arg (args, int));
5564 INSERT_OPERAND (1, MP, insn, va_arg (args, int));
5568 INSERT_OPERAND (1, IMMF, insn, va_arg (args, int));
5582 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5584 append_insn (&insn, ep, r, TRUE);
5588 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
5591 struct mips_opcode *mo;
5592 struct mips_cl_insn insn;
5593 bfd_reloc_code_real_type r[3]
5594 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
5596 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
5598 gas_assert (strcmp (name, mo->name) == 0);
5600 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
5603 gas_assert (mo->name);
5604 gas_assert (strcmp (name, mo->name) == 0);
5607 create_insn (&insn, mo);
5625 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
5630 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
5634 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
5638 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
5648 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
5655 regno = va_arg (*args, int);
5656 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
5657 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
5680 gas_assert (ep != NULL);
5682 if (ep->X_op != O_constant)
5683 *r = (int) BFD_RELOC_UNUSED + c;
5684 else if (calculate_reloc (*r, ep->X_add_number, &value))
5686 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
5688 *r = BFD_RELOC_UNUSED;
5694 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
5701 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
5703 append_insn (&insn, ep, r, TRUE);
5707 * Sign-extend 32-bit mode constants that have bit 31 set and all
5708 * higher bits unset.
5711 normalize_constant_expr (expressionS *ex)
5713 if (ex->X_op == O_constant
5714 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5715 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5720 * Sign-extend 32-bit mode address offsets that have bit 31 set and
5721 * all higher bits unset.
5724 normalize_address_expr (expressionS *ex)
5726 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
5727 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
5728 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
5729 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
5734 * Generate a "jalr" instruction with a relocation hint to the called
5735 * function. This occurs in NewABI PIC code.
5738 macro_build_jalr (expressionS *ep, int cprestore)
5740 static const bfd_reloc_code_real_type jalr_relocs[2]
5741 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
5742 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
5746 if (MIPS_JALR_HINT_P (ep))
5751 if (mips_opts.micromips)
5753 jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs";
5754 if (MIPS_JALR_HINT_P (ep)
5755 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
5756 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
5758 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
5761 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
5762 if (MIPS_JALR_HINT_P (ep))
5763 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc);
5767 * Generate a "lui" instruction.
5770 macro_build_lui (expressionS *ep, int regnum)
5772 gas_assert (! mips_opts.mips16);
5774 if (ep->X_op != O_constant)
5776 gas_assert (ep->X_op == O_symbol);
5777 /* _gp_disp is a special case, used from s_cpload.
5778 __gnu_local_gp is used if mips_no_shared. */
5779 gas_assert (mips_pic == NO_PIC
5781 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
5782 || (! mips_in_shared
5783 && strcmp (S_GET_NAME (ep->X_add_symbol),
5784 "__gnu_local_gp") == 0));
5787 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
5790 /* Generate a sequence of instructions to do a load or store from a constant
5791 offset off of a base register (breg) into/from a target register (treg),
5792 using AT if necessary. */
5794 macro_build_ldst_constoffset (expressionS *ep, const char *op,
5795 int treg, int breg, int dbl)
5797 gas_assert (ep->X_op == O_constant);
5799 /* Sign-extending 32-bit constants makes their handling easier. */
5801 normalize_constant_expr (ep);
5803 /* Right now, this routine can only handle signed 32-bit constants. */
5804 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
5805 as_warn (_("operand overflow"));
5807 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
5809 /* Signed 16-bit offset will fit in the op. Easy! */
5810 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
5814 /* 32-bit offset, need multiple instructions and AT, like:
5815 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
5816 addu $tempreg,$tempreg,$breg
5817 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
5818 to handle the complete offset. */
5819 macro_build_lui (ep, AT);
5820 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
5821 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
5824 as_bad (_("Macro used $at after \".set noat\""));
5829 * Generates code to set the $at register to true (one)
5830 * if reg is less than the immediate expression.
5833 set_at (int reg, int unsignedp)
5835 if (imm_expr.X_op == O_constant
5836 && imm_expr.X_add_number >= -0x8000
5837 && imm_expr.X_add_number < 0x8000)
5838 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
5839 AT, reg, BFD_RELOC_LO16);
5842 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5843 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
5847 /* Warn if an expression is not a constant. */
5850 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
5852 if (ex->X_op == O_big)
5853 as_bad (_("unsupported large constant"));
5854 else if (ex->X_op != O_constant)
5855 as_bad (_("Instruction %s requires absolute expression"),
5858 if (HAVE_32BIT_GPRS)
5859 normalize_constant_expr (ex);
5862 /* Count the leading zeroes by performing a binary chop. This is a
5863 bulky bit of source, but performance is a LOT better for the
5864 majority of values than a simple loop to count the bits:
5865 for (lcnt = 0; (lcnt < 32); lcnt++)
5866 if ((v) & (1 << (31 - lcnt)))
5868 However it is not code size friendly, and the gain will drop a bit
5869 on certain cached systems.
5871 #define COUNT_TOP_ZEROES(v) \
5872 (((v) & ~0xffff) == 0 \
5873 ? ((v) & ~0xff) == 0 \
5874 ? ((v) & ~0xf) == 0 \
5875 ? ((v) & ~0x3) == 0 \
5876 ? ((v) & ~0x1) == 0 \
5881 : ((v) & ~0x7) == 0 \
5884 : ((v) & ~0x3f) == 0 \
5885 ? ((v) & ~0x1f) == 0 \
5888 : ((v) & ~0x7f) == 0 \
5891 : ((v) & ~0xfff) == 0 \
5892 ? ((v) & ~0x3ff) == 0 \
5893 ? ((v) & ~0x1ff) == 0 \
5896 : ((v) & ~0x7ff) == 0 \
5899 : ((v) & ~0x3fff) == 0 \
5900 ? ((v) & ~0x1fff) == 0 \
5903 : ((v) & ~0x7fff) == 0 \
5906 : ((v) & ~0xffffff) == 0 \
5907 ? ((v) & ~0xfffff) == 0 \
5908 ? ((v) & ~0x3ffff) == 0 \
5909 ? ((v) & ~0x1ffff) == 0 \
5912 : ((v) & ~0x7ffff) == 0 \
5915 : ((v) & ~0x3fffff) == 0 \
5916 ? ((v) & ~0x1fffff) == 0 \
5919 : ((v) & ~0x7fffff) == 0 \
5922 : ((v) & ~0xfffffff) == 0 \
5923 ? ((v) & ~0x3ffffff) == 0 \
5924 ? ((v) & ~0x1ffffff) == 0 \
5927 : ((v) & ~0x7ffffff) == 0 \
5930 : ((v) & ~0x3fffffff) == 0 \
5931 ? ((v) & ~0x1fffffff) == 0 \
5934 : ((v) & ~0x7fffffff) == 0 \
5939 * This routine generates the least number of instructions necessary to load
5940 * an absolute expression value into a register.
5943 load_register (int reg, expressionS *ep, int dbl)
5946 expressionS hi32, lo32;
5948 if (ep->X_op != O_big)
5950 gas_assert (ep->X_op == O_constant);
5952 /* Sign-extending 32-bit constants makes their handling easier. */
5954 normalize_constant_expr (ep);
5956 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
5958 /* We can handle 16 bit signed values with an addiu to
5959 $zero. No need to ever use daddiu here, since $zero and
5960 the result are always correct in 32 bit mode. */
5961 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5964 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
5966 /* We can handle 16 bit unsigned values with an ori to
5968 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
5971 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
5973 /* 32 bit values require an lui. */
5974 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
5975 if ((ep->X_add_number & 0xffff) != 0)
5976 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
5981 /* The value is larger than 32 bits. */
5983 if (!dbl || HAVE_32BIT_GPRS)
5987 sprintf_vma (value, ep->X_add_number);
5988 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5989 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
5993 if (ep->X_op != O_big)
5996 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5997 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
5998 hi32.X_add_number &= 0xffffffff;
6000 lo32.X_add_number &= 0xffffffff;
6004 gas_assert (ep->X_add_number > 2);
6005 if (ep->X_add_number == 3)
6006 generic_bignum[3] = 0;
6007 else if (ep->X_add_number > 4)
6008 as_bad (_("Number larger than 64 bits"));
6009 lo32.X_op = O_constant;
6010 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
6011 hi32.X_op = O_constant;
6012 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
6015 if (hi32.X_add_number == 0)
6020 unsigned long hi, lo;
6022 if (hi32.X_add_number == (offsetT) 0xffffffff)
6024 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
6026 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6029 if (lo32.X_add_number & 0x80000000)
6031 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6032 if (lo32.X_add_number & 0xffff)
6033 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
6038 /* Check for 16bit shifted constant. We know that hi32 is
6039 non-zero, so start the mask on the first bit of the hi32
6044 unsigned long himask, lomask;
6048 himask = 0xffff >> (32 - shift);
6049 lomask = (0xffff << shift) & 0xffffffff;
6053 himask = 0xffff << (shift - 32);
6056 if ((hi32.X_add_number & ~(offsetT) himask) == 0
6057 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
6061 tmp.X_op = O_constant;
6063 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
6064 | (lo32.X_add_number >> shift));
6066 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
6067 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
6068 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6069 reg, reg, (shift >= 32) ? shift - 32 : shift);
6074 while (shift <= (64 - 16));
6076 /* Find the bit number of the lowest one bit, and store the
6077 shifted value in hi/lo. */
6078 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
6079 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
6083 while ((lo & 1) == 0)
6088 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
6094 while ((hi & 1) == 0)
6103 /* Optimize if the shifted value is a (power of 2) - 1. */
6104 if ((hi == 0 && ((lo + 1) & lo) == 0)
6105 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
6107 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
6112 /* This instruction will set the register to be all
6114 tmp.X_op = O_constant;
6115 tmp.X_add_number = (offsetT) -1;
6116 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
6120 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
6121 reg, reg, (bit >= 32) ? bit - 32 : bit);
6123 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
6124 reg, reg, (shift >= 32) ? shift - 32 : shift);
6129 /* Sign extend hi32 before calling load_register, because we can
6130 generally get better code when we load a sign extended value. */
6131 if ((hi32.X_add_number & 0x80000000) != 0)
6132 hi32.X_add_number |= ~(offsetT) 0xffffffff;
6133 load_register (reg, &hi32, 0);
6136 if ((lo32.X_add_number & 0xffff0000) == 0)
6140 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
6148 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
6150 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
6151 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
6157 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
6161 mid16.X_add_number >>= 16;
6162 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6163 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6166 if ((lo32.X_add_number & 0xffff) != 0)
6167 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
6171 load_delay_nop (void)
6173 if (!gpr_interlocks)
6174 macro_build (NULL, "nop", "");
6177 /* Load an address into a register. */
6180 load_address (int reg, expressionS *ep, int *used_at)
6182 if (ep->X_op != O_constant
6183 && ep->X_op != O_symbol)
6185 as_bad (_("expression too complex"));
6186 ep->X_op = O_constant;
6189 if (ep->X_op == O_constant)
6191 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
6195 if (mips_pic == NO_PIC)
6197 /* If this is a reference to a GP relative symbol, we want
6198 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
6200 lui $reg,<sym> (BFD_RELOC_HI16_S)
6201 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6202 If we have an addend, we always use the latter form.
6204 With 64bit address space and a usable $at we want
6205 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6206 lui $at,<sym> (BFD_RELOC_HI16_S)
6207 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6208 daddiu $at,<sym> (BFD_RELOC_LO16)
6212 If $at is already in use, we use a path which is suboptimal
6213 on superscalar processors.
6214 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6215 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
6217 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
6219 daddiu $reg,<sym> (BFD_RELOC_LO16)
6221 For GP relative symbols in 64bit address space we can use
6222 the same sequence as in 32bit address space. */
6223 if (HAVE_64BIT_SYMBOLS)
6225 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6226 && !nopic_need_relax (ep->X_add_symbol, 1))
6228 relax_start (ep->X_add_symbol);
6229 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6230 mips_gp_register, BFD_RELOC_GPREL16);
6234 if (*used_at == 0 && mips_opts.at)
6236 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6237 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
6238 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6239 BFD_RELOC_MIPS_HIGHER);
6240 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
6241 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
6242 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
6247 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
6248 macro_build (ep, "daddiu", "t,r,j", reg, reg,
6249 BFD_RELOC_MIPS_HIGHER);
6250 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6251 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
6252 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
6253 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
6256 if (mips_relax.sequence)
6261 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
6262 && !nopic_need_relax (ep->X_add_symbol, 1))
6264 relax_start (ep->X_add_symbol);
6265 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
6266 mips_gp_register, BFD_RELOC_GPREL16);
6269 macro_build_lui (ep, reg);
6270 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
6271 reg, reg, BFD_RELOC_LO16);
6272 if (mips_relax.sequence)
6276 else if (!mips_big_got)
6280 /* If this is a reference to an external symbol, we want
6281 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6283 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6285 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6286 If there is a constant, it must be added in after.
6288 If we have NewABI, we want
6289 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6290 unless we're referencing a global symbol with a non-zero
6291 offset, in which case cst must be added separately. */
6294 if (ep->X_add_number)
6296 ex.X_add_number = ep->X_add_number;
6297 ep->X_add_number = 0;
6298 relax_start (ep->X_add_symbol);
6299 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6300 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6301 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6302 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6303 ex.X_op = O_constant;
6304 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6305 reg, reg, BFD_RELOC_LO16);
6306 ep->X_add_number = ex.X_add_number;
6309 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6310 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6311 if (mips_relax.sequence)
6316 ex.X_add_number = ep->X_add_number;
6317 ep->X_add_number = 0;
6318 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6319 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6321 relax_start (ep->X_add_symbol);
6323 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6327 if (ex.X_add_number != 0)
6329 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6330 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6331 ex.X_op = O_constant;
6332 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
6333 reg, reg, BFD_RELOC_LO16);
6337 else if (mips_big_got)
6341 /* This is the large GOT case. If this is a reference to an
6342 external symbol, we want
6343 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6345 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
6347 Otherwise, for a reference to a local symbol in old ABI, we want
6348 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6350 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
6351 If there is a constant, it must be added in after.
6353 In the NewABI, for local symbols, with or without offsets, we want:
6354 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6355 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6359 ex.X_add_number = ep->X_add_number;
6360 ep->X_add_number = 0;
6361 relax_start (ep->X_add_symbol);
6362 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6363 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6364 reg, reg, mips_gp_register);
6365 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6366 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6367 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6368 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6369 else if (ex.X_add_number)
6371 ex.X_op = O_constant;
6372 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6376 ep->X_add_number = ex.X_add_number;
6378 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6379 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6380 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6381 BFD_RELOC_MIPS_GOT_OFST);
6386 ex.X_add_number = ep->X_add_number;
6387 ep->X_add_number = 0;
6388 relax_start (ep->X_add_symbol);
6389 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
6390 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6391 reg, reg, mips_gp_register);
6392 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
6393 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
6395 if (reg_needs_delay (mips_gp_register))
6397 /* We need a nop before loading from $gp. This special
6398 check is required because the lui which starts the main
6399 instruction stream does not refer to $gp, and so will not
6400 insert the nop which may be required. */
6401 macro_build (NULL, "nop", "");
6403 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
6404 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6406 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6410 if (ex.X_add_number != 0)
6412 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
6413 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6414 ex.X_op = O_constant;
6415 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
6423 if (!mips_opts.at && *used_at == 1)
6424 as_bad (_("Macro used $at after \".set noat\""));
6427 /* Move the contents of register SOURCE into register DEST. */
6430 move_register (int dest, int source)
6432 /* Prefer to use a 16-bit microMIPS instruction unless the previous
6433 instruction specifically requires a 32-bit one. */
6434 if (mips_opts.micromips
6435 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
6436 macro_build (NULL, "move", "mp,mj", dest, source);
6438 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
6442 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
6443 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
6444 The two alternatives are:
6446 Global symbol Local sybmol
6447 ------------- ------------
6448 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
6450 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
6452 load_got_offset emits the first instruction and add_got_offset
6453 emits the second for a 16-bit offset or add_got_offset_hilo emits
6454 a sequence to add a 32-bit offset using a scratch register. */
6457 load_got_offset (int dest, expressionS *local)
6462 global.X_add_number = 0;
6464 relax_start (local->X_add_symbol);
6465 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6466 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6468 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
6469 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6474 add_got_offset (int dest, expressionS *local)
6478 global.X_op = O_constant;
6479 global.X_op_symbol = NULL;
6480 global.X_add_symbol = NULL;
6481 global.X_add_number = local->X_add_number;
6483 relax_start (local->X_add_symbol);
6484 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
6485 dest, dest, BFD_RELOC_LO16);
6487 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
6492 add_got_offset_hilo (int dest, expressionS *local, int tmp)
6495 int hold_mips_optimize;
6497 global.X_op = O_constant;
6498 global.X_op_symbol = NULL;
6499 global.X_add_symbol = NULL;
6500 global.X_add_number = local->X_add_number;
6502 relax_start (local->X_add_symbol);
6503 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
6505 /* Set mips_optimize around the lui instruction to avoid
6506 inserting an unnecessary nop after the lw. */
6507 hold_mips_optimize = mips_optimize;
6509 macro_build_lui (&global, tmp);
6510 mips_optimize = hold_mips_optimize;
6511 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
6514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
6517 /* Emit a sequence of instructions to emulate a branch likely operation.
6518 BR is an ordinary branch corresponding to one to be emulated. BRNEG
6519 is its complementing branch with the original condition negated.
6520 CALL is set if the original branch specified the link operation.
6521 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
6523 Code like this is produced in the noreorder mode:
6528 delay slot (executed only if branch taken)
6536 delay slot (executed only if branch taken)
6539 In the reorder mode the delay slot would be filled with a nop anyway,
6540 so code produced is simply:
6545 This function is used when producing code for the microMIPS ASE that
6546 does not implement branch likely instructions in hardware. */
6549 macro_build_branch_likely (const char *br, const char *brneg,
6550 int call, expressionS *ep, const char *fmt,
6551 unsigned int sreg, unsigned int treg)
6553 int noreorder = mips_opts.noreorder;
6556 gas_assert (mips_opts.micromips);
6560 micromips_label_expr (&expr1);
6561 macro_build (&expr1, brneg, fmt, sreg, treg);
6562 macro_build (NULL, "nop", "");
6563 macro_build (ep, call ? "bal" : "b", "p");
6565 /* Set to true so that append_insn adds a label. */
6566 emit_branch_likely_macro = TRUE;
6570 macro_build (ep, br, fmt, sreg, treg);
6571 macro_build (NULL, "nop", "");
6576 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
6577 the condition code tested. EP specifies the branch target. */
6580 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
6607 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
6610 /* Emit a two-argument branch macro specified by TYPE, using SREG as
6611 the register tested. EP specifies the branch target. */
6614 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
6616 const char *brneg = NULL;
6626 br = mips_opts.micromips ? "bgez" : "bgezl";
6630 gas_assert (mips_opts.micromips);
6639 br = mips_opts.micromips ? "bgtz" : "bgtzl";
6646 br = mips_opts.micromips ? "blez" : "blezl";
6653 br = mips_opts.micromips ? "bltz" : "bltzl";
6657 gas_assert (mips_opts.micromips);
6665 if (mips_opts.micromips && brneg)
6666 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
6668 macro_build (ep, br, "s,p", sreg);
6671 /* Emit a three-argument branch macro specified by TYPE, using SREG and
6672 TREG as the registers tested. EP specifies the branch target. */
6675 macro_build_branch_rsrt (int type, expressionS *ep,
6676 unsigned int sreg, unsigned int treg)
6678 const char *brneg = NULL;
6690 br = mips_opts.micromips ? "beq" : "beql";
6699 br = mips_opts.micromips ? "bne" : "bnel";
6705 if (mips_opts.micromips && brneg)
6706 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
6708 macro_build (ep, br, "s,t,p", sreg, treg);
6713 * This routine implements the seemingly endless macro or synthesized
6714 * instructions and addressing modes in the mips assembly language. Many
6715 * of these macros are simple and are similar to each other. These could
6716 * probably be handled by some kind of table or grammar approach instead of
6717 * this verbose method. Others are not simple macros but are more like
6718 * optimizing code generation.
6719 * One interesting optimization is when several store macros appear
6720 * consecutively that would load AT with the upper half of the same address.
6721 * The ensuing load upper instructions are ommited. This implies some kind
6722 * of global optimization. We currently only optimize within a single macro.
6723 * For many of the load and store macros if the address is specified as a
6724 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
6725 * first load register 'at' with zero and use it as the base register. The
6726 * mips assembler simply uses register $zero. Just one tiny optimization
6730 macro (struct mips_cl_insn *ip)
6732 unsigned int treg, sreg, dreg, breg;
6733 unsigned int tempreg;
6736 expressionS label_expr;
6753 bfd_reloc_code_real_type r;
6754 int hold_mips_optimize;
6756 gas_assert (! mips_opts.mips16);
6758 treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
6759 dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
6760 sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
6761 mask = ip->insn_mo->mask;
6763 label_expr.X_op = O_constant;
6764 label_expr.X_op_symbol = NULL;
6765 label_expr.X_add_symbol = NULL;
6766 label_expr.X_add_number = 0;
6768 expr1.X_op = O_constant;
6769 expr1.X_op_symbol = NULL;
6770 expr1.X_add_symbol = NULL;
6771 expr1.X_add_number = 1;
6786 if (mips_opts.micromips)
6787 micromips_label_expr (&label_expr);
6789 label_expr.X_add_number = 8;
6790 macro_build (&label_expr, "bgez", "s,p", sreg);
6792 macro_build (NULL, "nop", "");
6794 move_register (dreg, sreg);
6795 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
6796 if (mips_opts.micromips)
6797 micromips_add_label ();
6814 if (!mips_opts.micromips)
6816 if (imm_expr.X_op == O_constant
6817 && imm_expr.X_add_number >= -0x200
6818 && imm_expr.X_add_number < 0x200)
6820 macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number);
6829 if (imm_expr.X_op == O_constant
6830 && imm_expr.X_add_number >= -0x8000
6831 && imm_expr.X_add_number < 0x8000)
6833 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
6838 load_register (AT, &imm_expr, dbl);
6839 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6858 if (imm_expr.X_op == O_constant
6859 && imm_expr.X_add_number >= 0
6860 && imm_expr.X_add_number < 0x10000)
6862 if (mask != M_NOR_I)
6863 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
6866 macro_build (&imm_expr, "ori", "t,r,i",
6867 treg, sreg, BFD_RELOC_LO16);
6868 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
6874 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
6875 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
6879 switch (imm_expr.X_add_number)
6882 macro_build (NULL, "nop", "");
6885 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
6889 macro_build (NULL, "balign", "t,s,2", treg, sreg,
6890 (int) imm_expr.X_add_number);
6893 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
6894 (unsigned long) imm_expr.X_add_number);
6903 gas_assert (mips_opts.micromips);
6904 macro_build_branch_ccl (mask, &offset_expr,
6905 EXTRACT_OPERAND (1, BCC, *ip));
6912 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6918 load_register (treg, &imm_expr, HAVE_64BIT_GPRS);
6923 macro_build_branch_rsrt (mask, &offset_expr, sreg, treg);
6930 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg);
6932 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg);
6936 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
6937 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6938 &offset_expr, AT, ZERO);
6948 macro_build_branch_rs (mask, &offset_expr, sreg);
6954 /* Check for > max integer. */
6955 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
6958 /* Result is always false. */
6960 macro_build (NULL, "nop", "");
6962 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
6965 if (imm_expr.X_op != O_constant)
6966 as_bad (_("Unsupported large constant"));
6967 ++imm_expr.X_add_number;
6971 if (mask == M_BGEL_I)
6973 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6975 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
6976 &offset_expr, sreg);
6979 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
6981 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
6982 &offset_expr, sreg);
6985 if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN)
6988 /* result is always true */
6989 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
6990 macro_build (&offset_expr, "b", "p");
6995 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
6996 &offset_expr, AT, ZERO);
7005 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7006 &offset_expr, ZERO, treg);
7010 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7011 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7012 &offset_expr, AT, ZERO);
7021 && imm_expr.X_op == O_constant
7022 && imm_expr.X_add_number == -1))
7024 if (imm_expr.X_op != O_constant)
7025 as_bad (_("Unsupported large constant"));
7026 ++imm_expr.X_add_number;
7030 if (mask == M_BGEUL_I)
7032 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7034 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7035 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7036 &offset_expr, sreg, ZERO);
7041 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7042 &offset_expr, AT, ZERO);
7050 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg);
7052 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg);
7056 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7057 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7058 &offset_expr, AT, ZERO);
7066 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7067 &offset_expr, sreg, ZERO);
7073 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7074 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7075 &offset_expr, AT, ZERO);
7083 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7085 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg);
7089 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
7090 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7091 &offset_expr, AT, ZERO);
7098 if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX)
7100 if (imm_expr.X_op != O_constant)
7101 as_bad (_("Unsupported large constant"));
7102 ++imm_expr.X_add_number;
7106 if (mask == M_BLTL_I)
7108 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7109 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7110 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7111 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg);
7116 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7117 &offset_expr, AT, ZERO);
7125 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7126 &offset_expr, sreg, ZERO);
7132 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
7133 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7134 &offset_expr, AT, ZERO);
7143 && imm_expr.X_op == O_constant
7144 && imm_expr.X_add_number == -1))
7146 if (imm_expr.X_op != O_constant)
7147 as_bad (_("Unsupported large constant"));
7148 ++imm_expr.X_add_number;
7152 if (mask == M_BLTUL_I)
7154 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7156 else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7157 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
7158 &offset_expr, sreg, ZERO);
7163 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7164 &offset_expr, AT, ZERO);
7172 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg);
7174 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg);
7178 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
7179 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7180 &offset_expr, AT, ZERO);
7190 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7191 &offset_expr, ZERO, treg);
7195 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
7196 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
7197 &offset_expr, AT, ZERO);
7203 /* Use unsigned arithmetic. */
7207 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7209 as_bad (_("Unsupported large constant"));
7214 pos = imm_expr.X_add_number;
7215 size = imm2_expr.X_add_number;
7220 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7223 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7225 as_bad (_("Improper extract size (%lu, position %lu)"),
7226 (unsigned long) size, (unsigned long) pos);
7230 if (size <= 32 && pos < 32)
7235 else if (size <= 32)
7245 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7252 /* Use unsigned arithmetic. */
7256 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
7258 as_bad (_("Unsupported large constant"));
7263 pos = imm_expr.X_add_number;
7264 size = imm2_expr.X_add_number;
7269 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
7272 if (size == 0 || size > 64 || (pos + size - 1) > 63)
7274 as_bad (_("Improper insert size (%lu, position %lu)"),
7275 (unsigned long) size, (unsigned long) pos);
7279 if (pos < 32 && (pos + size - 1) < 32)
7294 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
7295 (int) (pos + size - 1));
7311 as_warn (_("Divide by zero."));
7313 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7315 macro_build (NULL, "break", BRK_FMT, 7);
7322 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7323 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7327 if (mips_opts.micromips)
7328 micromips_label_expr (&label_expr);
7330 label_expr.X_add_number = 8;
7331 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7332 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
7333 macro_build (NULL, "break", BRK_FMT, 7);
7334 if (mips_opts.micromips)
7335 micromips_add_label ();
7337 expr1.X_add_number = -1;
7339 load_register (AT, &expr1, dbl);
7340 if (mips_opts.micromips)
7341 micromips_label_expr (&label_expr);
7343 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
7344 macro_build (&label_expr, "bne", "s,t,p", treg, AT);
7347 expr1.X_add_number = 1;
7348 load_register (AT, &expr1, dbl);
7349 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
7353 expr1.X_add_number = 0x80000000;
7354 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
7358 macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6);
7359 /* We want to close the noreorder block as soon as possible, so
7360 that later insns are available for delay slot filling. */
7365 if (mips_opts.micromips)
7366 micromips_label_expr (&label_expr);
7368 label_expr.X_add_number = 8;
7369 macro_build (&label_expr, "bne", "s,t,p", sreg, AT);
7370 macro_build (NULL, "nop", "");
7372 /* We want to close the noreorder block as soon as possible, so
7373 that later insns are available for delay slot filling. */
7376 macro_build (NULL, "break", BRK_FMT, 6);
7378 if (mips_opts.micromips)
7379 micromips_add_label ();
7380 macro_build (NULL, s, MFHL_FMT, dreg);
7419 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7421 as_warn (_("Divide by zero."));
7423 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
7425 macro_build (NULL, "break", BRK_FMT, 7);
7428 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
7430 if (strcmp (s2, "mflo") == 0)
7431 move_register (dreg, sreg);
7433 move_register (dreg, ZERO);
7436 if (imm_expr.X_op == O_constant
7437 && imm_expr.X_add_number == -1
7438 && s[strlen (s) - 1] != 'u')
7440 if (strcmp (s2, "mflo") == 0)
7442 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
7445 move_register (dreg, ZERO);
7450 load_register (AT, &imm_expr, dbl);
7451 macro_build (NULL, s, "z,s,t", sreg, AT);
7452 macro_build (NULL, s2, MFHL_FMT, dreg);
7474 macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7);
7475 macro_build (NULL, s, "z,s,t", sreg, treg);
7476 /* We want to close the noreorder block as soon as possible, so
7477 that later insns are available for delay slot filling. */
7482 if (mips_opts.micromips)
7483 micromips_label_expr (&label_expr);
7485 label_expr.X_add_number = 8;
7486 macro_build (&label_expr, "bne", "s,t,p", treg, ZERO);
7487 macro_build (NULL, s, "z,s,t", sreg, treg);
7489 /* We want to close the noreorder block as soon as possible, so
7490 that later insns are available for delay slot filling. */
7492 macro_build (NULL, "break", BRK_FMT, 7);
7493 if (mips_opts.micromips)
7494 micromips_add_label ();
7496 macro_build (NULL, s2, MFHL_FMT, dreg);
7508 /* Load the address of a symbol into a register. If breg is not
7509 zero, we then add a base register to it. */
7511 if (dbl && HAVE_32BIT_GPRS)
7512 as_warn (_("dla used to load 32-bit register"));
7514 if (!dbl && HAVE_64BIT_OBJECTS)
7515 as_warn (_("la used to load 64-bit address"));
7517 if (offset_expr.X_op == O_constant
7518 && offset_expr.X_add_number >= -0x8000
7519 && offset_expr.X_add_number < 0x8000)
7521 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
7522 "t,r,j", treg, sreg, BFD_RELOC_LO16);
7526 if (mips_opts.at && (treg == breg))
7536 if (offset_expr.X_op != O_symbol
7537 && offset_expr.X_op != O_constant)
7539 as_bad (_("Expression too complex"));
7540 offset_expr.X_op = O_constant;
7543 if (offset_expr.X_op == O_constant)
7544 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
7545 else if (mips_pic == NO_PIC)
7547 /* If this is a reference to a GP relative symbol, we want
7548 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
7550 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
7551 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7552 If we have a constant, we need two instructions anyhow,
7553 so we may as well always use the latter form.
7555 With 64bit address space and a usable $at we want
7556 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7557 lui $at,<sym> (BFD_RELOC_HI16_S)
7558 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7559 daddiu $at,<sym> (BFD_RELOC_LO16)
7561 daddu $tempreg,$tempreg,$at
7563 If $at is already in use, we use a path which is suboptimal
7564 on superscalar processors.
7565 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
7566 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
7568 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
7570 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
7572 For GP relative symbols in 64bit address space we can use
7573 the same sequence as in 32bit address space. */
7574 if (HAVE_64BIT_SYMBOLS)
7576 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7577 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7579 relax_start (offset_expr.X_add_symbol);
7580 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7581 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7585 if (used_at == 0 && mips_opts.at)
7587 macro_build (&offset_expr, "lui", LUI_FMT,
7588 tempreg, BFD_RELOC_MIPS_HIGHEST);
7589 macro_build (&offset_expr, "lui", LUI_FMT,
7590 AT, BFD_RELOC_HI16_S);
7591 macro_build (&offset_expr, "daddiu", "t,r,j",
7592 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7593 macro_build (&offset_expr, "daddiu", "t,r,j",
7594 AT, AT, BFD_RELOC_LO16);
7595 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
7596 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
7601 macro_build (&offset_expr, "lui", LUI_FMT,
7602 tempreg, BFD_RELOC_MIPS_HIGHEST);
7603 macro_build (&offset_expr, "daddiu", "t,r,j",
7604 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
7605 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7606 macro_build (&offset_expr, "daddiu", "t,r,j",
7607 tempreg, tempreg, BFD_RELOC_HI16_S);
7608 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
7609 macro_build (&offset_expr, "daddiu", "t,r,j",
7610 tempreg, tempreg, BFD_RELOC_LO16);
7613 if (mips_relax.sequence)
7618 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7619 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7621 relax_start (offset_expr.X_add_symbol);
7622 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7623 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
7626 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7627 as_bad (_("Offset too large"));
7628 macro_build_lui (&offset_expr, tempreg);
7629 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7630 tempreg, tempreg, BFD_RELOC_LO16);
7631 if (mips_relax.sequence)
7635 else if (!mips_big_got && !HAVE_NEWABI)
7637 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7639 /* If this is a reference to an external symbol, and there
7640 is no constant, we want
7641 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7642 or for lca or if tempreg is PIC_CALL_REG
7643 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7644 For a local symbol, we want
7645 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7647 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7649 If we have a small constant, and this is a reference to
7650 an external symbol, we want
7651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7653 addiu $tempreg,$tempreg,<constant>
7654 For a local symbol, we want the same instruction
7655 sequence, but we output a BFD_RELOC_LO16 reloc on the
7658 If we have a large constant, and this is a reference to
7659 an external symbol, we want
7660 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7661 lui $at,<hiconstant>
7662 addiu $at,$at,<loconstant>
7663 addu $tempreg,$tempreg,$at
7664 For a local symbol, we want the same instruction
7665 sequence, but we output a BFD_RELOC_LO16 reloc on the
7669 if (offset_expr.X_add_number == 0)
7671 if (mips_pic == SVR4_PIC
7673 && (call || tempreg == PIC_CALL_REG))
7674 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
7676 relax_start (offset_expr.X_add_symbol);
7677 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7678 lw_reloc_type, mips_gp_register);
7681 /* We're going to put in an addu instruction using
7682 tempreg, so we may as well insert the nop right
7687 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7688 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
7690 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7691 tempreg, tempreg, BFD_RELOC_LO16);
7693 /* FIXME: If breg == 0, and the next instruction uses
7694 $tempreg, then if this variant case is used an extra
7695 nop will be generated. */
7697 else if (offset_expr.X_add_number >= -0x8000
7698 && offset_expr.X_add_number < 0x8000)
7700 load_got_offset (tempreg, &offset_expr);
7702 add_got_offset (tempreg, &offset_expr);
7706 expr1.X_add_number = offset_expr.X_add_number;
7707 offset_expr.X_add_number =
7708 SEXT_16BIT (offset_expr.X_add_number);
7709 load_got_offset (tempreg, &offset_expr);
7710 offset_expr.X_add_number = expr1.X_add_number;
7711 /* If we are going to add in a base register, and the
7712 target register and the base register are the same,
7713 then we are using AT as a temporary register. Since
7714 we want to load the constant into AT, we add our
7715 current AT (from the global offset table) and the
7716 register into the register now, and pretend we were
7717 not using a base register. */
7721 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7726 add_got_offset_hilo (tempreg, &offset_expr, AT);
7730 else if (!mips_big_got && HAVE_NEWABI)
7732 int add_breg_early = 0;
7734 /* If this is a reference to an external, and there is no
7735 constant, or local symbol (*), with or without a
7737 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7738 or for lca or if tempreg is PIC_CALL_REG
7739 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
7741 If we have a small constant, and this is a reference to
7742 an external symbol, we want
7743 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7744 addiu $tempreg,$tempreg,<constant>
7746 If we have a large constant, and this is a reference to
7747 an external symbol, we want
7748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
7749 lui $at,<hiconstant>
7750 addiu $at,$at,<loconstant>
7751 addu $tempreg,$tempreg,$at
7753 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
7754 local symbols, even though it introduces an additional
7757 if (offset_expr.X_add_number)
7759 expr1.X_add_number = offset_expr.X_add_number;
7760 offset_expr.X_add_number = 0;
7762 relax_start (offset_expr.X_add_symbol);
7763 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7764 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7766 if (expr1.X_add_number >= -0x8000
7767 && expr1.X_add_number < 0x8000)
7769 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7770 tempreg, tempreg, BFD_RELOC_LO16);
7772 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
7774 /* If we are going to add in a base register, and the
7775 target register and the base register are the same,
7776 then we are using AT as a temporary register. Since
7777 we want to load the constant into AT, we add our
7778 current AT (from the global offset table) and the
7779 register into the register now, and pretend we were
7780 not using a base register. */
7785 gas_assert (tempreg == AT);
7786 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7792 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7793 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7799 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
7802 offset_expr.X_add_number = expr1.X_add_number;
7804 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7805 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7808 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7809 treg, tempreg, breg);
7815 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
7817 relax_start (offset_expr.X_add_symbol);
7818 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7819 BFD_RELOC_MIPS_CALL16, mips_gp_register);
7821 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7822 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7827 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7828 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
7831 else if (mips_big_got && !HAVE_NEWABI)
7834 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7835 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7836 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7838 /* This is the large GOT case. If this is a reference to an
7839 external symbol, and there is no constant, we want
7840 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7841 addu $tempreg,$tempreg,$gp
7842 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7843 or for lca or if tempreg is PIC_CALL_REG
7844 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7845 addu $tempreg,$tempreg,$gp
7846 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
7847 For a local symbol, we want
7848 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7850 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7852 If we have a small constant, and this is a reference to
7853 an external symbol, we want
7854 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7855 addu $tempreg,$tempreg,$gp
7856 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7858 addiu $tempreg,$tempreg,<constant>
7859 For a local symbol, we want
7860 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7862 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
7864 If we have a large constant, and this is a reference to
7865 an external symbol, we want
7866 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7867 addu $tempreg,$tempreg,$gp
7868 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7869 lui $at,<hiconstant>
7870 addiu $at,$at,<loconstant>
7871 addu $tempreg,$tempreg,$at
7872 For a local symbol, we want
7873 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7874 lui $at,<hiconstant>
7875 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
7876 addu $tempreg,$tempreg,$at
7879 expr1.X_add_number = offset_expr.X_add_number;
7880 offset_expr.X_add_number = 0;
7881 relax_start (offset_expr.X_add_symbol);
7882 gpdelay = reg_needs_delay (mips_gp_register);
7883 if (expr1.X_add_number == 0 && breg == 0
7884 && (call || tempreg == PIC_CALL_REG))
7886 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
7887 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
7889 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
7890 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7891 tempreg, tempreg, mips_gp_register);
7892 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7893 tempreg, lw_reloc_type, tempreg);
7894 if (expr1.X_add_number == 0)
7898 /* We're going to put in an addu instruction using
7899 tempreg, so we may as well insert the nop right
7904 else if (expr1.X_add_number >= -0x8000
7905 && expr1.X_add_number < 0x8000)
7908 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
7909 tempreg, tempreg, BFD_RELOC_LO16);
7913 /* If we are going to add in a base register, and the
7914 target register and the base register are the same,
7915 then we are using AT as a temporary register. Since
7916 we want to load the constant into AT, we add our
7917 current AT (from the global offset table) and the
7918 register into the register now, and pretend we were
7919 not using a base register. */
7924 gas_assert (tempreg == AT);
7926 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7931 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
7932 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
7936 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
7941 /* This is needed because this instruction uses $gp, but
7942 the first instruction on the main stream does not. */
7943 macro_build (NULL, "nop", "");
7946 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7947 local_reloc_type, mips_gp_register);
7948 if (expr1.X_add_number >= -0x8000
7949 && expr1.X_add_number < 0x8000)
7952 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7953 tempreg, tempreg, BFD_RELOC_LO16);
7954 /* FIXME: If add_number is 0, and there was no base
7955 register, the external symbol case ended with a load,
7956 so if the symbol turns out to not be external, and
7957 the next instruction uses tempreg, an unnecessary nop
7958 will be inserted. */
7964 /* We must add in the base register now, as in the
7965 external symbol case. */
7966 gas_assert (tempreg == AT);
7968 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7971 /* We set breg to 0 because we have arranged to add
7972 it in in both cases. */
7976 macro_build_lui (&expr1, AT);
7977 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
7978 AT, AT, BFD_RELOC_LO16);
7979 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7980 tempreg, tempreg, AT);
7985 else if (mips_big_got && HAVE_NEWABI)
7987 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
7988 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
7989 int add_breg_early = 0;
7991 /* This is the large GOT case. If this is a reference to an
7992 external symbol, and there is no constant, we want
7993 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7994 add $tempreg,$tempreg,$gp
7995 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7996 or for lca or if tempreg is PIC_CALL_REG
7997 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
7998 add $tempreg,$tempreg,$gp
7999 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
8001 If we have a small constant, and this is a reference to
8002 an external symbol, we want
8003 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8004 add $tempreg,$tempreg,$gp
8005 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8006 addi $tempreg,$tempreg,<constant>
8008 If we have a large constant, and this is a reference to
8009 an external symbol, we want
8010 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
8011 addu $tempreg,$tempreg,$gp
8012 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
8013 lui $at,<hiconstant>
8014 addi $at,$at,<loconstant>
8015 add $tempreg,$tempreg,$at
8017 If we have NewABI, and we know it's a local symbol, we want
8018 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
8019 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
8020 otherwise we have to resort to GOT_HI16/GOT_LO16. */
8022 relax_start (offset_expr.X_add_symbol);
8024 expr1.X_add_number = offset_expr.X_add_number;
8025 offset_expr.X_add_number = 0;
8027 if (expr1.X_add_number == 0 && breg == 0
8028 && (call || tempreg == PIC_CALL_REG))
8030 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
8031 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
8033 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
8034 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8035 tempreg, tempreg, mips_gp_register);
8036 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8037 tempreg, lw_reloc_type, tempreg);
8039 if (expr1.X_add_number == 0)
8041 else if (expr1.X_add_number >= -0x8000
8042 && expr1.X_add_number < 0x8000)
8044 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
8045 tempreg, tempreg, BFD_RELOC_LO16);
8047 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
8049 /* If we are going to add in a base register, and the
8050 target register and the base register are the same,
8051 then we are using AT as a temporary register. Since
8052 we want to load the constant into AT, we add our
8053 current AT (from the global offset table) and the
8054 register into the register now, and pretend we were
8055 not using a base register. */
8060 gas_assert (tempreg == AT);
8061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8067 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
8068 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
8073 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
8076 offset_expr.X_add_number = expr1.X_add_number;
8077 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
8078 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
8079 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
8080 tempreg, BFD_RELOC_MIPS_GOT_OFST);
8083 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8084 treg, tempreg, breg);
8094 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
8098 gas_assert (!mips_opts.micromips);
8100 unsigned long temp = (treg << 16) | (0x01);
8101 macro_build (NULL, "c2", "C", temp);
8106 gas_assert (!mips_opts.micromips);
8108 unsigned long temp = (0x02);
8109 macro_build (NULL, "c2", "C", temp);
8114 gas_assert (!mips_opts.micromips);
8116 unsigned long temp = (treg << 16) | (0x02);
8117 macro_build (NULL, "c2", "C", temp);
8122 gas_assert (!mips_opts.micromips);
8123 macro_build (NULL, "c2", "C", 3);
8127 gas_assert (!mips_opts.micromips);
8129 unsigned long temp = (treg << 16) | 0x03;
8130 macro_build (NULL, "c2", "C", temp);
8135 /* The j instruction may not be used in PIC code, since it
8136 requires an absolute address. We convert it to a b
8138 if (mips_pic == NO_PIC)
8139 macro_build (&offset_expr, "j", "a");
8141 macro_build (&offset_expr, "b", "p");
8144 /* The jal instructions must be handled as macros because when
8145 generating PIC code they expand to multi-instruction
8146 sequences. Normally they are simple instructions. */
8151 gas_assert (mips_opts.micromips);
8159 if (mips_pic == NO_PIC)
8161 s = jals ? "jalrs" : "jalr";
8162 if (mips_opts.micromips
8164 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8165 macro_build (NULL, s, "mj", sreg);
8167 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8171 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
8172 && mips_cprestore_offset >= 0);
8174 if (sreg != PIC_CALL_REG)
8175 as_warn (_("MIPS PIC call to register other than $25"));
8177 s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore)
8178 ? "jalrs" : "jalr");
8179 if (mips_opts.micromips
8181 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
8182 macro_build (NULL, s, "mj", sreg);
8184 macro_build (NULL, s, JALR_FMT, dreg, sreg);
8185 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
8187 if (mips_cprestore_offset < 0)
8188 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8191 if (!mips_frame_reg_valid)
8193 as_warn (_("No .frame pseudo-op used in PIC code"));
8194 /* Quiet this warning. */
8195 mips_frame_reg_valid = 1;
8197 if (!mips_cprestore_valid)
8199 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8200 /* Quiet this warning. */
8201 mips_cprestore_valid = 1;
8203 if (mips_opts.noreorder)
8204 macro_build (NULL, "nop", "");
8205 expr1.X_add_number = mips_cprestore_offset;
8206 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8209 HAVE_64BIT_ADDRESSES);
8217 gas_assert (mips_opts.micromips);
8221 if (mips_pic == NO_PIC)
8222 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
8223 else if (mips_pic == SVR4_PIC)
8225 /* If this is a reference to an external symbol, and we are
8226 using a small GOT, we want
8227 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
8231 lw $gp,cprestore($sp)
8232 The cprestore value is set using the .cprestore
8233 pseudo-op. If we are using a big GOT, we want
8234 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
8236 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
8240 lw $gp,cprestore($sp)
8241 If the symbol is not external, we want
8242 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
8244 addiu $25,$25,<sym> (BFD_RELOC_LO16)
8247 lw $gp,cprestore($sp)
8249 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
8250 sequences above, minus nops, unless the symbol is local,
8251 which enables us to use GOT_PAGE/GOT_OFST (big got) or
8257 relax_start (offset_expr.X_add_symbol);
8258 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8259 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8262 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8263 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
8269 relax_start (offset_expr.X_add_symbol);
8270 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8271 BFD_RELOC_MIPS_CALL_HI16);
8272 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8273 PIC_CALL_REG, mips_gp_register);
8274 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8275 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8278 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8279 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
8281 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8282 PIC_CALL_REG, PIC_CALL_REG,
8283 BFD_RELOC_MIPS_GOT_OFST);
8287 macro_build_jalr (&offset_expr, 0);
8291 relax_start (offset_expr.X_add_symbol);
8294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8295 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
8304 gpdelay = reg_needs_delay (mips_gp_register);
8305 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
8306 BFD_RELOC_MIPS_CALL_HI16);
8307 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
8308 PIC_CALL_REG, mips_gp_register);
8309 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8310 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
8315 macro_build (NULL, "nop", "");
8317 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
8318 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
8321 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8322 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
8324 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
8326 if (mips_cprestore_offset < 0)
8327 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8330 if (!mips_frame_reg_valid)
8332 as_warn (_("No .frame pseudo-op used in PIC code"));
8333 /* Quiet this warning. */
8334 mips_frame_reg_valid = 1;
8336 if (!mips_cprestore_valid)
8338 as_warn (_("No .cprestore pseudo-op used in PIC code"));
8339 /* Quiet this warning. */
8340 mips_cprestore_valid = 1;
8342 if (mips_opts.noreorder)
8343 macro_build (NULL, "nop", "");
8344 expr1.X_add_number = mips_cprestore_offset;
8345 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
8348 HAVE_64BIT_ADDRESSES);
8352 else if (mips_pic == VXWORKS_PIC)
8353 as_bad (_("Non-PIC jump used in PIC library"));
8461 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8469 treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
8500 gas_assert (!mips_opts.micromips);
8503 /* Itbl support may require additional care here. */
8510 /* Itbl support may require additional care here. */
8518 offbits = (mips_opts.micromips ? 12 : 16);
8519 /* Itbl support may require additional care here. */
8524 gas_assert (!mips_opts.micromips);
8527 /* Itbl support may require additional care here. */
8535 offbits = (mips_opts.micromips ? 12 : 16);
8542 offbits = (mips_opts.micromips ? 12 : 16);
8548 /* Itbl support may require additional care here. */
8556 offbits = (mips_opts.micromips ? 12 : 16);
8557 /* Itbl support may require additional care here. */
8564 /* Itbl support may require additional care here. */
8571 /* Itbl support may require additional care here. */
8579 offbits = (mips_opts.micromips ? 12 : 16);
8586 offbits = (mips_opts.micromips ? 12 : 16);
8593 offbits = (mips_opts.micromips ? 12 : 16);
8600 offbits = (mips_opts.micromips ? 12 : 16);
8607 offbits = (mips_opts.micromips ? 12 : 16);
8612 gas_assert (mips_opts.micromips);
8621 gas_assert (mips_opts.micromips);
8630 gas_assert (mips_opts.micromips);
8638 gas_assert (mips_opts.micromips);
8645 /* We don't want to use $0 as tempreg. */
8646 if (breg == treg + lp || treg + lp == ZERO)
8649 tempreg = treg + lp;
8669 gas_assert (!mips_opts.micromips);
8672 /* Itbl support may require additional care here. */
8679 /* Itbl support may require additional care here. */
8687 offbits = (mips_opts.micromips ? 12 : 16);
8688 /* Itbl support may require additional care here. */
8693 gas_assert (!mips_opts.micromips);
8696 /* Itbl support may require additional care here. */
8704 offbits = (mips_opts.micromips ? 12 : 16);
8711 offbits = (mips_opts.micromips ? 12 : 16);
8718 offbits = (mips_opts.micromips ? 12 : 16);
8725 offbits = (mips_opts.micromips ? 12 : 16);
8731 fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
8732 offbits = (mips_opts.micromips ? 12 : 16);
8745 fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
8746 offbits = (mips_opts.micromips ? 12 : 16);
8760 /* Itbl support may require additional care here. */
8767 offbits = (mips_opts.micromips ? 12 : 16);
8768 /* Itbl support may require additional care here. */
8775 /* Itbl support may require additional care here. */
8780 gas_assert (!mips_opts.micromips);
8783 /* Itbl support may require additional care here. */
8791 offbits = (mips_opts.micromips ? 12 : 16);
8798 offbits = (mips_opts.micromips ? 12 : 16);
8803 gas_assert (mips_opts.micromips);
8811 gas_assert (mips_opts.micromips);
8819 gas_assert (mips_opts.micromips);
8827 gas_assert (mips_opts.micromips);
8836 if (offset_expr.X_op != O_constant
8837 && offset_expr.X_op != O_symbol)
8839 as_bad (_("Expression too complex"));
8840 offset_expr.X_op = O_constant;
8843 if (HAVE_32BIT_ADDRESSES
8844 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
8848 sprintf_vma (value, offset_expr.X_add_number);
8849 as_bad (_("Number (0x%s) larger than 32 bits"), value);
8852 /* A constant expression in PIC code can be handled just as it
8853 is in non PIC code. */
8854 if (offset_expr.X_op == O_constant)
8858 expr1.X_add_number = offset_expr.X_add_number;
8859 normalize_address_expr (&expr1);
8860 if ((offbits == 0 || offbits == 16)
8861 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
8863 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
8864 & ~(bfd_vma) 0xffff);
8867 else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
8869 expr1.X_add_number = ((expr1.X_add_number + 0x800)
8870 & ~(bfd_vma) 0xfff);
8873 else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number))
8875 expr1.X_add_number = ((expr1.X_add_number + 0x100)
8876 & ~(bfd_vma) 0x1ff);
8881 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
8883 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8884 tempreg, tempreg, breg);
8889 if (offset_expr.X_add_number == 0)
8892 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
8893 "t,r,j", tempreg, breg, BFD_RELOC_LO16);
8894 macro_build (NULL, s, fmt, treg, tempreg);
8896 else if (offbits == 16)
8897 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
8899 macro_build (NULL, s, fmt,
8900 treg, (unsigned long) offset_expr.X_add_number, breg);
8902 else if (offbits != 16)
8904 /* The offset field is too narrow to be used for a low-part
8905 relocation, so load the whole address into the auxillary
8906 register. In the case of "A(b)" addresses, we first load
8907 absolute address "A" into the register and then add base
8908 register "b". In the case of "o(b)" addresses, we simply
8909 need to add 16-bit offset "o" to base register "b", and
8910 offset_reloc already contains the relocations associated
8914 load_address (tempreg, &offset_expr, &used_at);
8916 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
8917 tempreg, tempreg, breg);
8920 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
8922 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
8923 expr1.X_add_number = 0;
8925 macro_build (NULL, s, fmt, treg, tempreg);
8927 macro_build (NULL, s, fmt,
8928 treg, (unsigned long) expr1.X_add_number, tempreg);
8930 else if (mips_pic == NO_PIC)
8932 /* If this is a reference to a GP relative symbol, and there
8933 is no base register, we want
8934 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
8935 Otherwise, if there is no base register, we want
8936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8937 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8938 If we have a constant, we need two instructions anyhow,
8939 so we always use the latter form.
8941 If we have a base register, and this is a reference to a
8942 GP relative symbol, we want
8943 addu $tempreg,$breg,$gp
8944 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
8946 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
8947 addu $tempreg,$tempreg,$breg
8948 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8949 With a constant we always use the latter case.
8951 With 64bit address space and no base register and $at usable,
8953 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8954 lui $at,<sym> (BFD_RELOC_HI16_S)
8955 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8958 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8959 If we have a base register, we want
8960 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8961 lui $at,<sym> (BFD_RELOC_HI16_S)
8962 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8966 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8968 Without $at we can't generate the optimal path for superscalar
8969 processors here since this would require two temporary registers.
8970 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8971 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8973 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8975 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8976 If we have a base register, we want
8977 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
8978 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
8980 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
8982 daddu $tempreg,$tempreg,$breg
8983 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
8985 For GP relative symbols in 64bit address space we can use
8986 the same sequence as in 32bit address space. */
8987 if (HAVE_64BIT_SYMBOLS)
8989 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
8990 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
8992 relax_start (offset_expr.X_add_symbol);
8995 macro_build (&offset_expr, s, fmt, treg,
8996 BFD_RELOC_GPREL16, mips_gp_register);
9000 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9001 tempreg, breg, mips_gp_register);
9002 macro_build (&offset_expr, s, fmt, treg,
9003 BFD_RELOC_GPREL16, tempreg);
9008 if (used_at == 0 && mips_opts.at)
9010 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9011 BFD_RELOC_MIPS_HIGHEST);
9012 macro_build (&offset_expr, "lui", LUI_FMT, AT,
9014 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9015 tempreg, BFD_RELOC_MIPS_HIGHER);
9017 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
9018 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
9019 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
9020 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
9026 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9027 BFD_RELOC_MIPS_HIGHEST);
9028 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9029 tempreg, BFD_RELOC_MIPS_HIGHER);
9030 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9031 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
9032 tempreg, BFD_RELOC_HI16_S);
9033 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
9035 macro_build (NULL, "daddu", "d,v,t",
9036 tempreg, tempreg, breg);
9037 macro_build (&offset_expr, s, fmt, treg,
9038 BFD_RELOC_LO16, tempreg);
9041 if (mips_relax.sequence)
9048 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9049 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9051 relax_start (offset_expr.X_add_symbol);
9052 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
9056 macro_build_lui (&offset_expr, tempreg);
9057 macro_build (&offset_expr, s, fmt, treg,
9058 BFD_RELOC_LO16, tempreg);
9059 if (mips_relax.sequence)
9064 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9065 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9067 relax_start (offset_expr.X_add_symbol);
9068 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9069 tempreg, breg, mips_gp_register);
9070 macro_build (&offset_expr, s, fmt, treg,
9071 BFD_RELOC_GPREL16, tempreg);
9074 macro_build_lui (&offset_expr, tempreg);
9075 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9076 tempreg, tempreg, breg);
9077 macro_build (&offset_expr, s, fmt, treg,
9078 BFD_RELOC_LO16, tempreg);
9079 if (mips_relax.sequence)
9083 else if (!mips_big_got)
9085 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
9087 /* If this is a reference to an external symbol, we want
9088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9090 <op> $treg,0($tempreg)
9092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9094 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9095 <op> $treg,0($tempreg)
9098 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9099 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
9101 If there is a base register, we add it to $tempreg before
9102 the <op>. If there is a constant, we stick it in the
9103 <op> instruction. We don't handle constants larger than
9104 16 bits, because we have no way to load the upper 16 bits
9105 (actually, we could handle them for the subset of cases
9106 in which we are not using $at). */
9107 gas_assert (offset_expr.X_op == O_symbol);
9110 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9111 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9113 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9114 tempreg, tempreg, breg);
9115 macro_build (&offset_expr, s, fmt, treg,
9116 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9119 expr1.X_add_number = offset_expr.X_add_number;
9120 offset_expr.X_add_number = 0;
9121 if (expr1.X_add_number < -0x8000
9122 || expr1.X_add_number >= 0x8000)
9123 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9124 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9125 lw_reloc_type, mips_gp_register);
9127 relax_start (offset_expr.X_add_symbol);
9129 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9130 tempreg, BFD_RELOC_LO16);
9133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9134 tempreg, tempreg, breg);
9135 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9137 else if (mips_big_got && !HAVE_NEWABI)
9141 /* If this is a reference to an external symbol, we want
9142 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9143 addu $tempreg,$tempreg,$gp
9144 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9145 <op> $treg,0($tempreg)
9147 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9149 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
9150 <op> $treg,0($tempreg)
9151 If there is a base register, we add it to $tempreg before
9152 the <op>. If there is a constant, we stick it in the
9153 <op> instruction. We don't handle constants larger than
9154 16 bits, because we have no way to load the upper 16 bits
9155 (actually, we could handle them for the subset of cases
9156 in which we are not using $at). */
9157 gas_assert (offset_expr.X_op == O_symbol);
9158 expr1.X_add_number = offset_expr.X_add_number;
9159 offset_expr.X_add_number = 0;
9160 if (expr1.X_add_number < -0x8000
9161 || expr1.X_add_number >= 0x8000)
9162 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9163 gpdelay = reg_needs_delay (mips_gp_register);
9164 relax_start (offset_expr.X_add_symbol);
9165 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9166 BFD_RELOC_MIPS_GOT_HI16);
9167 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9169 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9170 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9173 macro_build (NULL, "nop", "");
9174 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9175 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9177 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
9178 tempreg, BFD_RELOC_LO16);
9182 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9183 tempreg, tempreg, breg);
9184 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9186 else if (mips_big_got && HAVE_NEWABI)
9188 /* If this is a reference to an external symbol, we want
9189 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9190 add $tempreg,$tempreg,$gp
9191 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
9192 <op> $treg,<ofst>($tempreg)
9193 Otherwise, for local symbols, we want:
9194 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9195 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
9196 gas_assert (offset_expr.X_op == O_symbol);
9197 expr1.X_add_number = offset_expr.X_add_number;
9198 offset_expr.X_add_number = 0;
9199 if (expr1.X_add_number < -0x8000
9200 || expr1.X_add_number >= 0x8000)
9201 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9202 relax_start (offset_expr.X_add_symbol);
9203 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
9204 BFD_RELOC_MIPS_GOT_HI16);
9205 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
9207 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9208 BFD_RELOC_MIPS_GOT_LO16, tempreg);
9210 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9211 tempreg, tempreg, breg);
9212 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
9215 offset_expr.X_add_number = expr1.X_add_number;
9216 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
9217 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9219 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9220 tempreg, tempreg, breg);
9221 macro_build (&offset_expr, s, fmt, treg,
9222 BFD_RELOC_MIPS_GOT_OFST, tempreg);
9232 load_register (treg, &imm_expr, 0);
9236 load_register (treg, &imm_expr, 1);
9240 if (imm_expr.X_op == O_constant)
9243 load_register (AT, &imm_expr, 0);
9244 macro_build (NULL, "mtc1", "t,G", AT, treg);
9249 gas_assert (offset_expr.X_op == O_symbol
9250 && strcmp (segment_name (S_GET_SEGMENT
9251 (offset_expr.X_add_symbol)),
9253 && offset_expr.X_add_number == 0);
9254 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
9255 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9260 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
9261 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
9262 order 32 bits of the value and the low order 32 bits are either
9263 zero or in OFFSET_EXPR. */
9264 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9266 if (HAVE_64BIT_GPRS)
9267 load_register (treg, &imm_expr, 1);
9272 if (target_big_endian)
9284 load_register (hreg, &imm_expr, 0);
9287 if (offset_expr.X_op == O_absent)
9288 move_register (lreg, 0);
9291 gas_assert (offset_expr.X_op == O_constant);
9292 load_register (lreg, &offset_expr, 0);
9299 /* We know that sym is in the .rdata section. First we get the
9300 upper 16 bits of the address. */
9301 if (mips_pic == NO_PIC)
9303 macro_build_lui (&offset_expr, AT);
9308 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9309 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9313 /* Now we load the register(s). */
9314 if (HAVE_64BIT_GPRS)
9317 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9322 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
9325 /* FIXME: How in the world do we deal with the possible
9327 offset_expr.X_add_number += 4;
9328 macro_build (&offset_expr, "lw", "t,o(b)",
9329 treg + 1, BFD_RELOC_LO16, AT);
9335 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
9336 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
9337 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
9338 the value and the low order 32 bits are either zero or in
9340 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
9343 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
9344 if (HAVE_64BIT_FPRS)
9346 gas_assert (HAVE_64BIT_GPRS);
9347 macro_build (NULL, "dmtc1", "t,S", AT, treg);
9351 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
9352 if (offset_expr.X_op == O_absent)
9353 macro_build (NULL, "mtc1", "t,G", 0, treg);
9356 gas_assert (offset_expr.X_op == O_constant);
9357 load_register (AT, &offset_expr, 0);
9358 macro_build (NULL, "mtc1", "t,G", AT, treg);
9364 gas_assert (offset_expr.X_op == O_symbol
9365 && offset_expr.X_add_number == 0);
9366 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
9367 if (strcmp (s, ".lit8") == 0)
9369 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9371 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
9372 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
9375 breg = mips_gp_register;
9376 r = BFD_RELOC_MIPS_LITERAL;
9381 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
9383 if (mips_pic != NO_PIC)
9384 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9385 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9388 /* FIXME: This won't work for a 64 bit address. */
9389 macro_build_lui (&offset_expr, AT);
9392 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips)
9394 macro_build (&offset_expr, "ldc1", "T,o(b)",
9395 treg, BFD_RELOC_LO16, AT);
9404 /* Even on a big endian machine $fn comes before $fn+1. We have
9405 to adjust when loading from memory. */
9408 gas_assert (!mips_opts.micromips);
9409 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9410 macro_build (&offset_expr, "lwc1", "T,o(b)",
9411 target_big_endian ? treg + 1 : treg, r, breg);
9412 /* FIXME: A possible overflow which I don't know how to deal
9414 offset_expr.X_add_number += 4;
9415 macro_build (&offset_expr, "lwc1", "T,o(b)",
9416 target_big_endian ? treg : treg + 1, r, breg);
9420 gas_assert (!mips_opts.micromips);
9421 gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch));
9422 /* Even on a big endian machine $fn comes before $fn+1. We have
9423 to adjust when storing to memory. */
9424 macro_build (&offset_expr, "swc1", "T,o(b)",
9425 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
9426 offset_expr.X_add_number += 4;
9427 macro_build (&offset_expr, "swc1", "T,o(b)",
9428 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
9432 gas_assert (!mips_opts.micromips);
9434 * The MIPS assembler seems to check for X_add_number not
9435 * being double aligned and generating:
9438 * addiu at,at,%lo(foo+1)
9441 * But, the resulting address is the same after relocation so why
9442 * generate the extra instruction?
9444 /* Itbl support may require additional care here. */
9447 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9456 gas_assert (!mips_opts.micromips);
9457 /* Itbl support may require additional care here. */
9460 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
9480 if (HAVE_64BIT_GPRS)
9490 if (HAVE_64BIT_GPRS)
9498 if (offset_expr.X_op != O_symbol
9499 && offset_expr.X_op != O_constant)
9501 as_bad (_("Expression too complex"));
9502 offset_expr.X_op = O_constant;
9505 if (HAVE_32BIT_ADDRESSES
9506 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
9510 sprintf_vma (value, offset_expr.X_add_number);
9511 as_bad (_("Number (0x%s) larger than 32 bits"), value);
9514 /* Even on a big endian machine $fn comes before $fn+1. We have
9515 to adjust when loading from memory. We set coproc if we must
9516 load $fn+1 first. */
9517 /* Itbl support may require additional care here. */
9518 if (!target_big_endian)
9521 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
9523 /* If this is a reference to a GP relative symbol, we want
9524 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
9525 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
9526 If we have a base register, we use this
9528 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
9529 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
9530 If this is not a GP relative symbol, we want
9531 lui $at,<sym> (BFD_RELOC_HI16_S)
9532 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9533 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9534 If there is a base register, we add it to $at after the
9535 lui instruction. If there is a constant, we always use
9537 if (offset_expr.X_op == O_symbol
9538 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
9539 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
9541 relax_start (offset_expr.X_add_symbol);
9544 tempreg = mips_gp_register;
9548 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9549 AT, breg, mips_gp_register);
9554 /* Itbl support may require additional care here. */
9555 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9556 BFD_RELOC_GPREL16, tempreg);
9557 offset_expr.X_add_number += 4;
9559 /* Set mips_optimize to 2 to avoid inserting an
9561 hold_mips_optimize = mips_optimize;
9563 /* Itbl support may require additional care here. */
9564 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9565 BFD_RELOC_GPREL16, tempreg);
9566 mips_optimize = hold_mips_optimize;
9570 offset_expr.X_add_number -= 4;
9573 macro_build_lui (&offset_expr, AT);
9575 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9576 /* Itbl support may require additional care here. */
9577 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9578 BFD_RELOC_LO16, AT);
9579 /* FIXME: How do we handle overflow here? */
9580 offset_expr.X_add_number += 4;
9581 /* Itbl support may require additional care here. */
9582 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9583 BFD_RELOC_LO16, AT);
9584 if (mips_relax.sequence)
9587 else if (!mips_big_got)
9589 /* If this is a reference to an external symbol, we want
9590 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9595 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9597 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9598 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9599 If there is a base register we add it to $at before the
9600 lwc1 instructions. If there is a constant we include it
9601 in the lwc1 instructions. */
9603 expr1.X_add_number = offset_expr.X_add_number;
9604 if (expr1.X_add_number < -0x8000
9605 || expr1.X_add_number >= 0x8000 - 4)
9606 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9607 load_got_offset (AT, &offset_expr);
9610 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9612 /* Set mips_optimize to 2 to avoid inserting an undesired
9614 hold_mips_optimize = mips_optimize;
9617 /* Itbl support may require additional care here. */
9618 relax_start (offset_expr.X_add_symbol);
9619 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9620 BFD_RELOC_LO16, AT);
9621 expr1.X_add_number += 4;
9622 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9623 BFD_RELOC_LO16, AT);
9625 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9626 BFD_RELOC_LO16, AT);
9627 offset_expr.X_add_number += 4;
9628 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9629 BFD_RELOC_LO16, AT);
9632 mips_optimize = hold_mips_optimize;
9634 else if (mips_big_got)
9638 /* If this is a reference to an external symbol, we want
9639 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9641 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
9646 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9648 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
9649 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
9650 If there is a base register we add it to $at before the
9651 lwc1 instructions. If there is a constant we include it
9652 in the lwc1 instructions. */
9654 expr1.X_add_number = offset_expr.X_add_number;
9655 offset_expr.X_add_number = 0;
9656 if (expr1.X_add_number < -0x8000
9657 || expr1.X_add_number >= 0x8000 - 4)
9658 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9659 gpdelay = reg_needs_delay (mips_gp_register);
9660 relax_start (offset_expr.X_add_symbol);
9661 macro_build (&offset_expr, "lui", LUI_FMT,
9662 AT, BFD_RELOC_MIPS_GOT_HI16);
9663 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9664 AT, AT, mips_gp_register);
9665 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
9666 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
9669 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9670 /* Itbl support may require additional care here. */
9671 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
9672 BFD_RELOC_LO16, AT);
9673 expr1.X_add_number += 4;
9675 /* Set mips_optimize to 2 to avoid inserting an undesired
9677 hold_mips_optimize = mips_optimize;
9679 /* Itbl support may require additional care here. */
9680 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
9681 BFD_RELOC_LO16, AT);
9682 mips_optimize = hold_mips_optimize;
9683 expr1.X_add_number -= 4;
9686 offset_expr.X_add_number = expr1.X_add_number;
9688 macro_build (NULL, "nop", "");
9689 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
9690 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9693 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
9694 /* Itbl support may require additional care here. */
9695 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
9696 BFD_RELOC_LO16, AT);
9697 offset_expr.X_add_number += 4;
9699 /* Set mips_optimize to 2 to avoid inserting an undesired
9701 hold_mips_optimize = mips_optimize;
9703 /* Itbl support may require additional care here. */
9704 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
9705 BFD_RELOC_LO16, AT);
9706 mips_optimize = hold_mips_optimize;
9715 s = HAVE_64BIT_GPRS ? "ld" : "lw";
9718 s = HAVE_64BIT_GPRS ? "sd" : "sw";
9720 macro_build (&offset_expr, s, "t,o(b)", treg,
9721 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9723 if (!HAVE_64BIT_GPRS)
9725 offset_expr.X_add_number += 4;
9726 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
9727 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
9748 /* New code added to support COPZ instructions.
9749 This code builds table entries out of the macros in mip_opcodes.
9750 R4000 uses interlocks to handle coproc delays.
9751 Other chips (like the R3000) require nops to be inserted for delays.
9753 FIXME: Currently, we require that the user handle delays.
9754 In order to fill delay slots for non-interlocked chips,
9755 we must have a way to specify delays based on the coprocessor.
9756 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
9757 What are the side-effects of the cop instruction?
9758 What cache support might we have and what are its effects?
9759 Both coprocessor & memory require delays. how long???
9760 What registers are read/set/modified?
9762 If an itbl is provided to interpret cop instructions,
9763 this knowledge can be encoded in the itbl spec. */
9777 gas_assert (!mips_opts.micromips);
9778 /* For now we just do C (same as Cz). The parameter will be
9779 stored in insn_opcode by mips_ip. */
9780 macro_build (NULL, s, "C", ip->insn_opcode);
9784 move_register (dreg, sreg);
9790 if (mips_opts.arch == CPU_R5900)
9792 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
9796 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
9797 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9804 /* The MIPS assembler some times generates shifts and adds. I'm
9805 not trying to be that fancy. GCC should do this for us
9808 load_register (AT, &imm_expr, dbl);
9809 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
9810 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9826 load_register (AT, &imm_expr, dbl);
9827 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
9828 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9829 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA);
9830 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9832 macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6);
9835 if (mips_opts.micromips)
9836 micromips_label_expr (&label_expr);
9838 label_expr.X_add_number = 8;
9839 macro_build (&label_expr, "beq", "s,t,p", dreg, AT);
9840 macro_build (NULL, "nop", "");
9841 macro_build (NULL, "break", BRK_FMT, 6);
9842 if (mips_opts.micromips)
9843 micromips_add_label ();
9846 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9862 load_register (AT, &imm_expr, dbl);
9863 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
9864 sreg, imm ? AT : treg);
9865 macro_build (NULL, "mfhi", MFHL_FMT, AT);
9866 macro_build (NULL, "mflo", MFHL_FMT, dreg);
9868 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
9871 if (mips_opts.micromips)
9872 micromips_label_expr (&label_expr);
9874 label_expr.X_add_number = 8;
9875 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
9876 macro_build (NULL, "nop", "");
9877 macro_build (NULL, "break", BRK_FMT, 6);
9878 if (mips_opts.micromips)
9879 micromips_add_label ();
9885 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9896 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
9897 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
9901 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9902 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
9903 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
9904 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9908 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9919 macro_build (NULL, "negu", "d,w", tempreg, treg);
9920 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
9924 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
9925 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
9926 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
9927 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9936 if (imm_expr.X_op != O_constant)
9937 as_bad (_("Improper rotate count"));
9938 rot = imm_expr.X_add_number & 0x3f;
9939 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9941 rot = (64 - rot) & 0x3f;
9943 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
9945 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
9950 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
9953 l = (rot < 0x20) ? "dsll" : "dsll32";
9954 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
9957 macro_build (NULL, l, SHFT_FMT, AT, sreg, rot);
9958 macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9959 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9967 if (imm_expr.X_op != O_constant)
9968 as_bad (_("Improper rotate count"));
9969 rot = imm_expr.X_add_number & 0x1f;
9970 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
9972 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f);
9977 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
9981 macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot);
9982 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
9983 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
9988 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
9990 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
9994 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
9995 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
9996 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
9997 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10001 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10003 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
10007 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
10008 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
10009 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
10010 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10019 if (imm_expr.X_op != O_constant)
10020 as_bad (_("Improper rotate count"));
10021 rot = imm_expr.X_add_number & 0x3f;
10022 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
10025 macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32);
10027 macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot);
10032 macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0);
10035 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
10036 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
10039 macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot);
10040 macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10041 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10049 if (imm_expr.X_op != O_constant)
10050 as_bad (_("Improper rotate count"));
10051 rot = imm_expr.X_add_number & 0x1f;
10052 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
10054 macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot);
10059 macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0);
10063 macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot);
10064 macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f);
10065 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
10071 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
10072 else if (treg == 0)
10073 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10076 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10077 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10082 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10084 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10089 as_warn (_("Instruction %s: result is always false"),
10090 ip->insn_mo->name);
10091 move_register (dreg, 0);
10094 if (CPU_HAS_SEQ (mips_opts.arch)
10095 && -512 <= imm_expr.X_add_number
10096 && imm_expr.X_add_number < 512)
10098 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
10099 (int) imm_expr.X_add_number);
10102 if (imm_expr.X_op == O_constant
10103 && imm_expr.X_add_number >= 0
10104 && imm_expr.X_add_number < 0x10000)
10106 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10108 else if (imm_expr.X_op == O_constant
10109 && imm_expr.X_add_number > -0x8000
10110 && imm_expr.X_add_number < 0)
10112 imm_expr.X_add_number = -imm_expr.X_add_number;
10113 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10114 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10116 else if (CPU_HAS_SEQ (mips_opts.arch))
10119 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10120 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
10125 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10126 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10129 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
10132 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
10138 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
10139 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10142 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
10144 if (imm_expr.X_op == O_constant
10145 && imm_expr.X_add_number >= -0x8000
10146 && imm_expr.X_add_number < 0x8000)
10148 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
10149 dreg, sreg, BFD_RELOC_LO16);
10153 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10154 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
10158 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10161 case M_SGT: /* sreg > treg <==> treg < sreg */
10167 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10170 case M_SGT_I: /* sreg > I <==> I < sreg */
10177 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10178 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10181 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
10187 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
10188 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10191 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
10198 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10199 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
10200 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
10204 if (imm_expr.X_op == O_constant
10205 && imm_expr.X_add_number >= -0x8000
10206 && imm_expr.X_add_number < 0x8000)
10208 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10212 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10213 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
10217 if (imm_expr.X_op == O_constant
10218 && imm_expr.X_add_number >= -0x8000
10219 && imm_expr.X_add_number < 0x8000)
10221 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
10226 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10227 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
10232 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
10233 else if (treg == 0)
10234 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10237 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
10238 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10243 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
10245 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
10250 as_warn (_("Instruction %s: result is always true"),
10251 ip->insn_mo->name);
10252 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
10253 dreg, 0, BFD_RELOC_LO16);
10256 if (CPU_HAS_SEQ (mips_opts.arch)
10257 && -512 <= imm_expr.X_add_number
10258 && imm_expr.X_add_number < 512)
10260 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
10261 (int) imm_expr.X_add_number);
10264 if (imm_expr.X_op == O_constant
10265 && imm_expr.X_add_number >= 0
10266 && imm_expr.X_add_number < 0x10000)
10268 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
10270 else if (imm_expr.X_op == O_constant
10271 && imm_expr.X_add_number > -0x8000
10272 && imm_expr.X_add_number < 0)
10274 imm_expr.X_add_number = -imm_expr.X_add_number;
10275 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
10276 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10278 else if (CPU_HAS_SEQ (mips_opts.arch))
10281 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10282 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
10287 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10288 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
10291 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
10306 if (!mips_opts.micromips)
10308 if (imm_expr.X_op == O_constant
10309 && imm_expr.X_add_number > -0x200
10310 && imm_expr.X_add_number <= 0x200)
10312 macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number);
10321 if (imm_expr.X_op == O_constant
10322 && imm_expr.X_add_number > -0x8000
10323 && imm_expr.X_add_number <= 0x8000)
10325 imm_expr.X_add_number = -imm_expr.X_add_number;
10326 macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16);
10331 load_register (AT, &imm_expr, dbl);
10332 macro_build (NULL, s2, "d,v,t", dreg, sreg, AT);
10354 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
10355 macro_build (NULL, s, "s,t", sreg, AT);
10360 gas_assert (!mips_opts.micromips);
10361 gas_assert (mips_opts.isa == ISA_MIPS1);
10363 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
10364 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
10367 * Is the double cfc1 instruction a bug in the mips assembler;
10368 * or is there a reason for it?
10370 start_noreorder ();
10371 macro_build (NULL, "cfc1", "t,G", treg, RA);
10372 macro_build (NULL, "cfc1", "t,G", treg, RA);
10373 macro_build (NULL, "nop", "");
10374 expr1.X_add_number = 3;
10375 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
10376 expr1.X_add_number = 2;
10377 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
10378 macro_build (NULL, "ctc1", "t,G", AT, RA);
10379 macro_build (NULL, "nop", "");
10380 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
10382 macro_build (NULL, "ctc1", "t,G", treg, RA);
10383 macro_build (NULL, "nop", "");
10406 offbits = (mips_opts.micromips ? 12 : 16);
10414 offbits = (mips_opts.micromips ? 12 : 16);
10430 offbits = (mips_opts.micromips ? 12 : 16);
10439 offbits = (mips_opts.micromips ? 12 : 16);
10444 if (!ab && offset_expr.X_add_number >= 0x8000 - off)
10445 as_bad (_("Operand overflow"));
10448 expr1.X_add_number = 0;
10453 load_address (tempreg, ep, &used_at);
10455 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
10456 tempreg, tempreg, breg);
10461 else if (offbits == 12
10462 && (offset_expr.X_op != O_constant
10463 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
10464 || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
10468 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg,
10469 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
10474 else if (!ust && treg == breg)
10485 if (!target_big_endian)
10486 ep->X_add_number += off;
10488 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10490 macro_build (NULL, s, "t,~(b)",
10491 tempreg, (unsigned long) ep->X_add_number, breg);
10493 if (!target_big_endian)
10494 ep->X_add_number -= off;
10496 ep->X_add_number += off;
10498 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10500 macro_build (NULL, s2, "t,~(b)",
10501 tempreg, (unsigned long) ep->X_add_number, breg);
10503 /* If necessary, move the result in tempreg to the final destination. */
10504 if (!ust && treg != tempreg)
10506 /* Protect second load's delay slot. */
10508 move_register (treg, tempreg);
10514 if (target_big_endian == ust)
10515 ep->X_add_number += off;
10516 tempreg = ust || ab ? treg : AT;
10517 macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10519 /* For halfword transfers we need a temporary register to shuffle
10520 bytes. Unfortunately for M_USH_A we have none available before
10521 the next store as AT holds the base address. We deal with this
10522 case by clobbering TREG and then restoring it as with ULH. */
10523 tempreg = ust == ab ? treg : AT;
10525 macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8);
10527 if (target_big_endian == ust)
10528 ep->X_add_number -= off;
10530 ep->X_add_number += off;
10531 macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
10533 /* For M_USH_A re-retrieve the LSB. */
10536 if (target_big_endian)
10537 ep->X_add_number += off;
10539 ep->X_add_number -= off;
10540 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
10542 /* For ULH and M_USH_A OR the LSB in. */
10545 tempreg = !ab ? AT : treg;
10546 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
10547 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
10552 /* FIXME: Check if this is one of the itbl macros, since they
10553 are added dynamically. */
10554 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
10557 if (!mips_opts.at && used_at)
10558 as_bad (_("Macro used $at after \".set noat\""));
10561 /* Implement macros in mips16 mode. */
10564 mips16_macro (struct mips_cl_insn *ip)
10567 int xreg, yreg, zreg, tmp;
10570 const char *s, *s2, *s3;
10572 mask = ip->insn_mo->mask;
10574 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
10575 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
10576 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
10578 expr1.X_op = O_constant;
10579 expr1.X_op_symbol = NULL;
10580 expr1.X_add_symbol = NULL;
10581 expr1.X_add_number = 1;
10600 start_noreorder ();
10601 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
10602 expr1.X_add_number = 2;
10603 macro_build (&expr1, "bnez", "x,p", yreg);
10604 macro_build (NULL, "break", "6", 7);
10606 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
10607 since that causes an overflow. We should do that as well,
10608 but I don't see how to do the comparisons without a temporary
10611 macro_build (NULL, s, "x", zreg);
10630 start_noreorder ();
10631 macro_build (NULL, s, "0,x,y", xreg, yreg);
10632 expr1.X_add_number = 2;
10633 macro_build (&expr1, "bnez", "x,p", yreg);
10634 macro_build (NULL, "break", "6", 7);
10636 macro_build (NULL, s2, "x", zreg);
10642 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
10643 macro_build (NULL, "mflo", "x", zreg);
10651 if (imm_expr.X_op != O_constant)
10652 as_bad (_("Unsupported large constant"));
10653 imm_expr.X_add_number = -imm_expr.X_add_number;
10654 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
10658 if (imm_expr.X_op != O_constant)
10659 as_bad (_("Unsupported large constant"));
10660 imm_expr.X_add_number = -imm_expr.X_add_number;
10661 macro_build (&imm_expr, "addiu", "x,k", xreg);
10665 if (imm_expr.X_op != O_constant)
10666 as_bad (_("Unsupported large constant"));
10667 imm_expr.X_add_number = -imm_expr.X_add_number;
10668 macro_build (&imm_expr, "daddiu", "y,j", yreg);
10690 goto do_reverse_branch;
10694 goto do_reverse_branch;
10706 goto do_reverse_branch;
10717 macro_build (NULL, s, "x,y", xreg, yreg);
10718 macro_build (&offset_expr, s2, "p");
10745 goto do_addone_branch_i;
10750 goto do_addone_branch_i;
10765 goto do_addone_branch_i;
10771 do_addone_branch_i:
10772 if (imm_expr.X_op != O_constant)
10773 as_bad (_("Unsupported large constant"));
10774 ++imm_expr.X_add_number;
10777 macro_build (&imm_expr, s, s3, xreg);
10778 macro_build (&offset_expr, s2, "p");
10782 expr1.X_add_number = 0;
10783 macro_build (&expr1, "slti", "x,8", yreg);
10785 move_register (xreg, yreg);
10786 expr1.X_add_number = 2;
10787 macro_build (&expr1, "bteqz", "p");
10788 macro_build (NULL, "neg", "x,w", xreg, xreg);
10792 /* For consistency checking, verify that all bits are specified either
10793 by the match/mask part of the instruction definition, or by the
10796 validate_mips_insn (const struct mips_opcode *opc)
10798 const char *p = opc->args;
10800 unsigned long used_bits = opc->mask;
10802 if ((used_bits & opc->match) != opc->match)
10804 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
10805 opc->name, opc->args);
10808 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
10818 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
10819 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
10820 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
10821 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
10822 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10823 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10824 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10825 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
10826 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10827 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10828 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
10829 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10830 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
10832 case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break;
10833 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10834 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
10835 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10836 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10837 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
10838 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10839 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
10840 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
10841 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10842 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
10843 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
10844 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
10845 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
10846 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
10847 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
10848 case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
10851 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
10852 c, opc->name, opc->args);
10856 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10857 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10859 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
10860 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
10861 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10862 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10864 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10865 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
10867 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
10868 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10870 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
10871 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
10872 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
10873 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
10874 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10875 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
10876 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10877 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10878 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10879 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10880 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
10881 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
10882 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
10883 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
10884 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10885 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
10886 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10888 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
10889 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10890 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10891 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
10893 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10894 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
10895 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
10896 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10897 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10898 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10899 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
10900 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10901 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10904 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
10905 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
10906 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
10907 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
10908 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
10911 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
10912 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
10913 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
10914 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
10915 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
10916 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
10917 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
10918 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
10919 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
10920 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
10921 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
10922 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
10923 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
10924 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
10925 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
10926 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
10927 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
10928 case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break;
10929 case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break;
10930 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
10932 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
10933 c, opc->name, opc->args);
10937 if (used_bits != 0xffffffff)
10939 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
10940 ~used_bits & 0xffffffff, opc->name, opc->args);
10946 /* For consistency checking, verify that the length implied matches the
10947 major opcode and that all bits are specified either by the match/mask
10948 part of the instruction definition, or by the operand list. */
10951 validate_micromips_insn (const struct mips_opcode *opc)
10953 unsigned long match = opc->match;
10954 unsigned long mask = opc->mask;
10955 const char *p = opc->args;
10956 unsigned long insn_bits;
10957 unsigned long used_bits;
10958 unsigned long major;
10959 unsigned int length;
10963 if ((mask & match) != match)
10965 as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"),
10966 opc->name, opc->args);
10969 length = micromips_insn_length (opc);
10970 if (length != 2 && length != 4)
10972 as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
10973 "%s %s"), length, opc->name, opc->args);
10976 major = match >> (10 + 8 * (length - 2));
10977 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
10978 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
10980 as_bad (_("Internal error: bad microMIPS opcode "
10981 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
10985 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
10986 insn_bits = 1 << 4 * length;
10987 insn_bits <<= 4 * length;
10990 #define USE_BITS(field) \
10991 (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field)
11002 case 'A': USE_BITS (EXTLSB); break;
11003 case 'B': USE_BITS (INSMSB); break;
11004 case 'C': USE_BITS (EXTMSBD); break;
11005 case 'D': USE_BITS (RS); USE_BITS (SEL); break;
11006 case 'E': USE_BITS (EXTLSB); break;
11007 case 'F': USE_BITS (INSMSB); break;
11008 case 'G': USE_BITS (EXTMSBD); break;
11009 case 'H': USE_BITS (EXTMSBD); break;
11010 case 'j': USE_BITS (EVAOFFSET); break;
11012 as_bad (_("Internal error: bad mips opcode "
11013 "(unknown extension operand type `%c%c'): %s %s"),
11014 e, c, opc->name, opc->args);
11022 case 'A': USE_BITS (IMMA); break;
11023 case 'B': USE_BITS (IMMB); break;
11024 case 'C': USE_BITS (IMMC); break;
11025 case 'D': USE_BITS (IMMD); break;
11026 case 'E': USE_BITS (IMME); break;
11027 case 'F': USE_BITS (IMMF); break;
11028 case 'G': USE_BITS (IMMG); break;
11029 case 'H': USE_BITS (IMMH); break;
11030 case 'I': USE_BITS (IMMI); break;
11031 case 'J': USE_BITS (IMMJ); break;
11032 case 'L': USE_BITS (IMML); break;
11033 case 'M': USE_BITS (IMMM); break;
11034 case 'N': USE_BITS (IMMN); break;
11035 case 'O': USE_BITS (IMMO); break;
11036 case 'P': USE_BITS (IMMP); break;
11037 case 'Q': USE_BITS (IMMQ); break;
11038 case 'U': USE_BITS (IMMU); break;
11039 case 'W': USE_BITS (IMMW); break;
11040 case 'X': USE_BITS (IMMX); break;
11041 case 'Y': USE_BITS (IMMY); break;
11044 case 'b': USE_BITS (MB); break;
11045 case 'c': USE_BITS (MC); break;
11046 case 'd': USE_BITS (MD); break;
11047 case 'e': USE_BITS (ME); break;
11048 case 'f': USE_BITS (MF); break;
11049 case 'g': USE_BITS (MG); break;
11050 case 'h': USE_BITS (MH); break;
11051 case 'i': USE_BITS (MI); break;
11052 case 'j': USE_BITS (MJ); break;
11053 case 'l': USE_BITS (ML); break;
11054 case 'm': USE_BITS (MM); break;
11055 case 'n': USE_BITS (MN); break;
11056 case 'p': USE_BITS (MP); break;
11057 case 'q': USE_BITS (MQ); break;
11065 as_bad (_("Internal error: bad mips opcode "
11066 "(unknown extension operand type `%c%c'): %s %s"),
11067 e, c, opc->name, opc->args);
11071 case '.': USE_BITS (OFFSET10); break;
11072 case '1': USE_BITS (STYPE); break;
11073 case '2': USE_BITS (BP); break;
11074 case '3': USE_BITS (SA3); break;
11075 case '4': USE_BITS (SA4); break;
11076 case '5': USE_BITS (IMM8); break;
11077 case '6': USE_BITS (RS); break;
11078 case '7': USE_BITS (DSPACC); break;
11079 case '8': USE_BITS (WRDSP); break;
11080 case '0': USE_BITS (DSPSFT); break;
11081 case '<': USE_BITS (SHAMT); break;
11082 case '>': USE_BITS (SHAMT); break;
11083 case '@': USE_BITS (IMM10); break;
11084 case 'B': USE_BITS (CODE10); break;
11085 case 'C': USE_BITS (COPZ); break;
11086 case 'D': USE_BITS (FD); break;
11087 case 'E': USE_BITS (RT); break;
11088 case 'G': USE_BITS (RS); break;
11089 case 'H': USE_BITS (SEL); break;
11090 case 'K': USE_BITS (RS); break;
11091 case 'M': USE_BITS (CCC); break;
11092 case 'N': USE_BITS (BCC); break;
11093 case 'R': USE_BITS (FR); break;
11094 case 'S': USE_BITS (FS); break;
11095 case 'T': USE_BITS (FT); break;
11096 case 'V': USE_BITS (FS); break;
11097 case '\\': USE_BITS (3BITPOS); break;
11098 case '^': USE_BITS (RD); break;
11099 case 'a': USE_BITS (TARGET); break;
11100 case 'b': USE_BITS (RS); break;
11101 case 'c': USE_BITS (CODE); break;
11102 case 'd': USE_BITS (RD); break;
11103 case 'h': USE_BITS (PREFX); break;
11104 case 'i': USE_BITS (IMMEDIATE); break;
11105 case 'j': USE_BITS (DELTA); break;
11106 case 'k': USE_BITS (CACHE); break;
11107 case 'n': USE_BITS (RT); break;
11108 case 'o': USE_BITS (DELTA); break;
11109 case 'p': USE_BITS (DELTA); break;
11110 case 'q': USE_BITS (CODE2); break;
11111 case 'r': USE_BITS (RS); break;
11112 case 's': USE_BITS (RS); break;
11113 case 't': USE_BITS (RT); break;
11114 case 'u': USE_BITS (IMMEDIATE); break;
11115 case 'v': USE_BITS (RS); break;
11116 case 'w': USE_BITS (RT); break;
11117 case 'y': USE_BITS (RS3); break;
11119 case '|': USE_BITS (TRAP); break;
11120 case '~': USE_BITS (OFFSET12); break;
11122 as_bad (_("Internal error: bad microMIPS opcode "
11123 "(unknown operand type `%c'): %s %s"),
11124 c, opc->name, opc->args);
11128 if (used_bits != insn_bits)
11130 if (~used_bits & insn_bits)
11131 as_bad (_("Internal error: bad microMIPS opcode "
11132 "(bits 0x%lx undefined): %s %s"),
11133 ~used_bits & insn_bits, opc->name, opc->args);
11134 if (used_bits & ~insn_bits)
11135 as_bad (_("Internal error: bad microMIPS opcode "
11136 "(bits 0x%lx defined): %s %s"),
11137 used_bits & ~insn_bits, opc->name, opc->args);
11143 /* UDI immediates. */
11144 struct mips_immed {
11146 unsigned int shift;
11147 unsigned long mask;
11151 static const struct mips_immed mips_immed[] = {
11152 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
11153 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
11154 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
11155 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
11159 /* Check whether an odd floating-point register is allowed. */
11161 mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
11163 const char *s = insn->name;
11165 if (insn->pinfo == INSN_MACRO)
11166 /* Let a macro pass, we'll catch it later when it is expanded. */
11169 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
11171 /* Allow odd registers for single-precision ops. */
11172 switch (insn->pinfo & (FP_S | FP_D))
11176 return 1; /* both single precision - ok */
11178 return 0; /* both double precision - fail */
11183 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
11184 s = strchr (insn->name, '.');
11186 s = s != NULL ? strchr (s + 1, '.') : NULL;
11187 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
11190 /* Single-precision coprocessor loads and moves are OK too. */
11191 if ((insn->pinfo & FP_S)
11192 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
11193 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
11199 /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive)
11200 taking bits from BIT up. */
11202 expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit)
11204 return (ep->X_op == O_constant
11205 && (ep->X_add_number & ((1 << bit) - 1)) == 0
11206 && ep->X_add_number >= min << bit
11207 && ep->X_add_number < max << bit);
11210 /* This routine assembles an instruction into its binary format. As a
11211 side effect, it sets one of the global variables imm_reloc or
11212 offset_reloc to the type of relocation to do if one of the operands
11213 is an address expression. */
11216 mips_ip (char *str, struct mips_cl_insn *ip)
11218 bfd_boolean wrong_delay_slot_insns = FALSE;
11219 bfd_boolean need_delay_slot_ok = TRUE;
11220 struct mips_opcode *firstinsn = NULL;
11221 const struct mips_opcode *past;
11222 struct hash_control *hash;
11226 struct mips_opcode *insn;
11228 unsigned int regno;
11229 unsigned int lastregno;
11230 unsigned int destregno = 0;
11231 unsigned int lastpos = 0;
11232 unsigned int limlo, limhi;
11235 offsetT min_range, max_range;
11239 unsigned int rtype;
11245 if (mips_opts.micromips)
11247 hash = micromips_op_hash;
11248 past = µmips_opcodes[bfd_micromips_num_opcodes];
11253 past = &mips_opcodes[NUMOPCODES];
11255 forced_insn_length = 0;
11258 /* We first try to match an instruction up to a space or to the end. */
11259 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
11262 /* Make a copy of the instruction so that we can fiddle with it. */
11263 name = alloca (end + 1);
11264 memcpy (name, str, end);
11269 insn = (struct mips_opcode *) hash_find (hash, name);
11271 if (insn != NULL || !mips_opts.micromips)
11273 if (forced_insn_length)
11276 /* See if there's an instruction size override suffix,
11277 either `16' or `32', at the end of the mnemonic proper,
11278 that defines the operation, i.e. before the first `.'
11279 character if any. Strip it and retry. */
11280 dot = strchr (name, '.');
11281 opend = dot != NULL ? dot - name : end;
11284 if (name[opend - 2] == '1' && name[opend - 1] == '6')
11285 forced_insn_length = 2;
11286 else if (name[opend - 2] == '3' && name[opend - 1] == '2')
11287 forced_insn_length = 4;
11290 memcpy (name + opend - 2, name + opend, end - opend + 1);
11294 insn_error = _("Unrecognized opcode");
11298 /* For microMIPS instructions placed in a fixed-length branch delay slot
11299 we make up to two passes over the relevant fragment of the opcode
11300 table. First we try instructions that meet the delay slot's length
11301 requirement. If none matched, then we retry with the remaining ones
11302 and if one matches, then we use it and then issue an appropriate
11303 warning later on. */
11304 argsStart = s = str + end;
11307 bfd_boolean delay_slot_ok;
11308 bfd_boolean size_ok;
11311 gas_assert (strcmp (insn->name, name) == 0);
11313 ok = is_opcode_valid (insn);
11314 size_ok = is_size_valid (insn);
11315 delay_slot_ok = is_delay_slot_valid (insn);
11316 if (!delay_slot_ok && !wrong_delay_slot_insns)
11319 wrong_delay_slot_insns = TRUE;
11321 if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok)
11323 static char buf[256];
11325 if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0)
11330 if (wrong_delay_slot_insns && need_delay_slot_ok)
11332 gas_assert (firstinsn);
11333 need_delay_slot_ok = FALSE;
11343 sprintf (buf, _("Opcode not supported on this processor: %s (%s)"),
11344 mips_cpu_info_from_arch (mips_opts.arch)->name,
11345 mips_cpu_info_from_isa (mips_opts.isa)->name);
11347 sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"),
11348 8 * forced_insn_length);
11354 create_insn (ip, insn);
11357 lastregno = 0xffffffff;
11358 for (args = insn->args;; ++args)
11362 s += strspn (s, " \t");
11366 case '\0': /* end of args */
11372 /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS
11373 code) or 14 (for microMIPS code). */
11374 my_getExpression (&imm_expr, s);
11375 check_absolute_expr (ip, &imm_expr);
11376 if ((unsigned long) imm_expr.X_add_number != 1
11377 && (unsigned long) imm_expr.X_add_number != 3)
11379 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
11380 (unsigned long) imm_expr.X_add_number);
11382 INSERT_OPERAND (mips_opts.micromips,
11383 BP, *ip, imm_expr.X_add_number);
11384 imm_expr.X_op = O_absent;
11389 /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS
11390 code) or 13 (for microMIPS code). */
11392 unsigned long mask = (mips_opts.micromips
11393 ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3);
11395 my_getExpression (&imm_expr, s);
11396 check_absolute_expr (ip, &imm_expr);
11397 if ((unsigned long) imm_expr.X_add_number > mask)
11398 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11399 mask, (unsigned long) imm_expr.X_add_number);
11400 INSERT_OPERAND (mips_opts.micromips,
11401 SA3, *ip, imm_expr.X_add_number);
11402 imm_expr.X_op = O_absent;
11408 /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS
11409 code) or 12 (for microMIPS code). */
11411 unsigned long mask = (mips_opts.micromips
11412 ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4);
11414 my_getExpression (&imm_expr, s);
11415 check_absolute_expr (ip, &imm_expr);
11416 if ((unsigned long) imm_expr.X_add_number > mask)
11417 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11418 mask, (unsigned long) imm_expr.X_add_number);
11419 INSERT_OPERAND (mips_opts.micromips,
11420 SA4, *ip, imm_expr.X_add_number);
11421 imm_expr.X_op = O_absent;
11427 /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS
11428 code) or 13 (for microMIPS code). */
11430 unsigned long mask = (mips_opts.micromips
11431 ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8);
11433 my_getExpression (&imm_expr, s);
11434 check_absolute_expr (ip, &imm_expr);
11435 if ((unsigned long) imm_expr.X_add_number > mask)
11436 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11437 mask, (unsigned long) imm_expr.X_add_number);
11438 INSERT_OPERAND (mips_opts.micromips,
11439 IMM8, *ip, imm_expr.X_add_number);
11440 imm_expr.X_op = O_absent;
11446 /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS
11447 code) or 16 (for microMIPS code). */
11449 unsigned long mask = (mips_opts.micromips
11450 ? MICROMIPSOP_MASK_RS : OP_MASK_RS);
11452 my_getExpression (&imm_expr, s);
11453 check_absolute_expr (ip, &imm_expr);
11454 if ((unsigned long) imm_expr.X_add_number > mask)
11455 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11456 mask, (unsigned long) imm_expr.X_add_number);
11457 INSERT_OPERAND (mips_opts.micromips,
11458 RS, *ip, imm_expr.X_add_number);
11459 imm_expr.X_op = O_absent;
11465 /* Four DSP accumulators in bit 11 (for standard MIPS code)
11466 or 14 (for microMIPS code). */
11467 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11468 && s[3] >= '0' && s[3] <= '3')
11470 regno = s[3] - '0';
11472 INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno);
11476 as_bad (_("Invalid dsp acc register"));
11480 /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS
11481 code) or 14 (for microMIPS code). */
11483 unsigned long mask = (mips_opts.micromips
11484 ? MICROMIPSOP_MASK_WRDSP
11487 my_getExpression (&imm_expr, s);
11488 check_absolute_expr (ip, &imm_expr);
11489 if ((unsigned long) imm_expr.X_add_number > mask)
11490 as_bad (_("DSP immediate not in range 0..%lu (%lu)"),
11491 mask, (unsigned long) imm_expr.X_add_number);
11492 INSERT_OPERAND (mips_opts.micromips,
11493 WRDSP, *ip, imm_expr.X_add_number);
11494 imm_expr.X_op = O_absent;
11499 case '9': /* Four DSP accumulators in bits 21,22. */
11500 gas_assert (!mips_opts.micromips);
11501 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c'
11502 && s[3] >= '0' && s[3] <= '3')
11504 regno = s[3] - '0';
11506 INSERT_OPERAND (0, DSPACC_S, *ip, regno);
11510 as_bad (_("Invalid dsp acc register"));
11514 /* DSP 6-bit signed immediate in bit 20 (for standard MIPS
11515 code) or 16 (for microMIPS code). */
11517 long mask = (mips_opts.micromips
11518 ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT);
11520 my_getExpression (&imm_expr, s);
11521 check_absolute_expr (ip, &imm_expr);
11522 min_range = -((mask + 1) >> 1);
11523 max_range = ((mask + 1) >> 1) - 1;
11524 if (imm_expr.X_add_number < min_range
11525 || imm_expr.X_add_number > max_range)
11526 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11527 (long) min_range, (long) max_range,
11528 (long) imm_expr.X_add_number);
11529 INSERT_OPERAND (mips_opts.micromips,
11530 DSPSFT, *ip, imm_expr.X_add_number);
11531 imm_expr.X_op = O_absent;
11536 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
11537 gas_assert (!mips_opts.micromips);
11538 my_getExpression (&imm_expr, s);
11539 check_absolute_expr (ip, &imm_expr);
11540 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
11542 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11544 (unsigned long) imm_expr.X_add_number);
11546 INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number);
11547 imm_expr.X_op = O_absent;
11551 case ':': /* DSP 7-bit signed immediate in bit 19. */
11552 gas_assert (!mips_opts.micromips);
11553 my_getExpression (&imm_expr, s);
11554 check_absolute_expr (ip, &imm_expr);
11555 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
11556 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
11557 if (imm_expr.X_add_number < min_range ||
11558 imm_expr.X_add_number > max_range)
11560 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11561 (long) min_range, (long) max_range,
11562 (long) imm_expr.X_add_number);
11564 INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number);
11565 imm_expr.X_op = O_absent;
11569 case '@': /* DSP 10-bit signed immediate in bit 16. */
11571 long mask = (mips_opts.micromips
11572 ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10);
11574 my_getExpression (&imm_expr, s);
11575 check_absolute_expr (ip, &imm_expr);
11576 min_range = -((mask + 1) >> 1);
11577 max_range = ((mask + 1) >> 1) - 1;
11578 if (imm_expr.X_add_number < min_range
11579 || imm_expr.X_add_number > max_range)
11580 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
11581 (long) min_range, (long) max_range,
11582 (long) imm_expr.X_add_number);
11583 INSERT_OPERAND (mips_opts.micromips,
11584 IMM10, *ip, imm_expr.X_add_number);
11585 imm_expr.X_op = O_absent;
11590 case '^': /* DSP 5-bit unsigned immediate in bit 11. */
11591 gas_assert (mips_opts.micromips);
11592 my_getExpression (&imm_expr, s);
11593 check_absolute_expr (ip, &imm_expr);
11594 if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD)
11595 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
11596 MICROMIPSOP_MASK_RD,
11597 (unsigned long) imm_expr.X_add_number);
11598 INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number);
11599 imm_expr.X_op = O_absent;
11603 case '!': /* MT usermode flag bit. */
11604 gas_assert (!mips_opts.micromips);
11605 my_getExpression (&imm_expr, s);
11606 check_absolute_expr (ip, &imm_expr);
11607 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
11608 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
11609 (unsigned long) imm_expr.X_add_number);
11610 INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number);
11611 imm_expr.X_op = O_absent;
11615 case '$': /* MT load high flag bit. */
11616 gas_assert (!mips_opts.micromips);
11617 my_getExpression (&imm_expr, s);
11618 check_absolute_expr (ip, &imm_expr);
11619 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
11620 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
11621 (unsigned long) imm_expr.X_add_number);
11622 INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number);
11623 imm_expr.X_op = O_absent;
11627 case '*': /* Four DSP accumulators in bits 18,19. */
11628 gas_assert (!mips_opts.micromips);
11629 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11630 s[3] >= '0' && s[3] <= '3')
11632 regno = s[3] - '0';
11634 INSERT_OPERAND (0, MTACC_T, *ip, regno);
11638 as_bad (_("Invalid dsp/smartmips acc register"));
11641 case '&': /* Four DSP accumulators in bits 13,14. */
11642 gas_assert (!mips_opts.micromips);
11643 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
11644 s[3] >= '0' && s[3] <= '3')
11646 regno = s[3] - '0';
11648 INSERT_OPERAND (0, MTACC_D, *ip, regno);
11652 as_bad (_("Invalid dsp/smartmips acc register"));
11655 case '\\': /* 3-bit bit position. */
11657 unsigned long mask = (mips_opts.micromips
11658 ? MICROMIPSOP_MASK_3BITPOS
11659 : OP_MASK_3BITPOS);
11661 my_getExpression (&imm_expr, s);
11662 check_absolute_expr (ip, &imm_expr);
11663 if ((unsigned long) imm_expr.X_add_number > mask)
11664 as_warn (_("Bit position for %s not in range 0..%lu (%lu)"),
11666 mask, (unsigned long) imm_expr.X_add_number);
11667 INSERT_OPERAND (mips_opts.micromips,
11668 3BITPOS, *ip, imm_expr.X_add_number);
11669 imm_expr.X_op = O_absent;
11683 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
11687 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
11691 gas_assert (!mips_opts.micromips);
11692 INSERT_OPERAND (0, FT, *ip, lastregno);
11696 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
11702 /* Handle optional base register.
11703 Either the base register is omitted or
11704 we must have a left paren. */
11705 /* This is dependent on the next operand specifier
11706 is a base register specification. */
11707 gas_assert (args[1] == 'b'
11708 || (mips_opts.micromips
11710 && (args[2] == 'l' || args[2] == 'n'
11711 || args[2] == 's' || args[2] == 'a')));
11712 if (*s == '\0' && args[1] == 'b')
11714 /* Fall through. */
11716 case ')': /* These must match exactly. */
11721 case '[': /* These must match exactly. */
11723 gas_assert (!mips_opts.micromips);
11728 case '+': /* Opcode extension character. */
11731 case '1': /* UDI immediates. */
11735 gas_assert (!mips_opts.micromips);
11737 const struct mips_immed *imm = mips_immed;
11739 while (imm->type && imm->type != *args)
11743 my_getExpression (&imm_expr, s);
11744 check_absolute_expr (ip, &imm_expr);
11745 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
11747 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
11748 imm->desc ? imm->desc : ip->insn_mo->name,
11749 (unsigned long) imm_expr.X_add_number,
11750 (unsigned long) imm_expr.X_add_number);
11751 imm_expr.X_add_number &= imm->mask;
11753 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
11755 imm_expr.X_op = O_absent;
11760 case 'J': /* 10-bit hypcall code. */
11761 gas_assert (!mips_opts.micromips);
11763 unsigned long mask = OP_MASK_CODE10;
11765 my_getExpression (&imm_expr, s);
11766 check_absolute_expr (ip, &imm_expr);
11767 if ((unsigned long) imm_expr.X_add_number > mask)
11768 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
11770 mask, (unsigned long) imm_expr.X_add_number);
11771 INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number);
11772 imm_expr.X_op = O_absent;
11777 case 'A': /* ins/ext position, becomes LSB. */
11786 my_getExpression (&imm_expr, s);
11787 check_absolute_expr (ip, &imm_expr);
11788 if ((unsigned long) imm_expr.X_add_number < limlo
11789 || (unsigned long) imm_expr.X_add_number > limhi)
11791 as_bad (_("Improper position (%lu)"),
11792 (unsigned long) imm_expr.X_add_number);
11793 imm_expr.X_add_number = limlo;
11795 lastpos = imm_expr.X_add_number;
11796 INSERT_OPERAND (mips_opts.micromips,
11797 EXTLSB, *ip, imm_expr.X_add_number);
11798 imm_expr.X_op = O_absent;
11802 case 'B': /* ins size, becomes MSB. */
11811 my_getExpression (&imm_expr, s);
11812 check_absolute_expr (ip, &imm_expr);
11813 /* Check for negative input so that small negative numbers
11814 will not succeed incorrectly. The checks against
11815 (pos+size) transitively check "size" itself,
11816 assuming that "pos" is reasonable. */
11817 if ((long) imm_expr.X_add_number < 0
11818 || ((unsigned long) imm_expr.X_add_number
11820 || ((unsigned long) imm_expr.X_add_number
11821 + lastpos) > limhi)
11823 as_bad (_("Improper insert size (%lu, position %lu)"),
11824 (unsigned long) imm_expr.X_add_number,
11825 (unsigned long) lastpos);
11826 imm_expr.X_add_number = limlo - lastpos;
11828 INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip,
11829 lastpos + imm_expr.X_add_number - 1);
11830 imm_expr.X_op = O_absent;
11834 case 'C': /* ext size, becomes MSBD. */
11850 my_getExpression (&imm_expr, s);
11851 check_absolute_expr (ip, &imm_expr);
11852 /* The checks against (pos+size) don't transitively check
11853 "size" itself, assuming that "pos" is reasonable.
11854 We also need to check the lower bound of "size". */
11855 if ((long) imm_expr.X_add_number < sizelo
11856 || ((unsigned long) imm_expr.X_add_number
11858 || ((unsigned long) imm_expr.X_add_number
11859 + lastpos) > limhi)
11861 as_bad (_("Improper extract size (%lu, position %lu)"),
11862 (unsigned long) imm_expr.X_add_number,
11863 (unsigned long) lastpos);
11864 imm_expr.X_add_number = limlo - lastpos;
11866 INSERT_OPERAND (mips_opts.micromips,
11867 EXTMSBD, *ip, imm_expr.X_add_number - 1);
11868 imm_expr.X_op = O_absent;
11873 /* +D is for disassembly only; never match. */
11877 /* "+I" is like "I", except that imm2_expr is used. */
11878 my_getExpression (&imm2_expr, s);
11879 if (imm2_expr.X_op != O_big
11880 && imm2_expr.X_op != O_constant)
11881 insn_error = _("absolute expression required");
11882 if (HAVE_32BIT_GPRS)
11883 normalize_constant_expr (&imm2_expr);
11887 case 'T': /* Coprocessor register. */
11888 gas_assert (!mips_opts.micromips);
11889 /* +T is for disassembly only; never match. */
11892 case 't': /* Coprocessor register number. */
11893 gas_assert (!mips_opts.micromips);
11894 if (s[0] == '$' && ISDIGIT (s[1]))
11904 while (ISDIGIT (*s));
11906 as_bad (_("Invalid register number (%d)"), regno);
11909 INSERT_OPERAND (0, RT, *ip, regno);
11914 as_bad (_("Invalid coprocessor 0 register number"));
11918 /* bbit[01] and bbit[01]32 bit index. Give error if index
11919 is not in the valid range. */
11920 gas_assert (!mips_opts.micromips);
11921 my_getExpression (&imm_expr, s);
11922 check_absolute_expr (ip, &imm_expr);
11923 if ((unsigned) imm_expr.X_add_number > 31)
11925 as_bad (_("Improper bit index (%lu)"),
11926 (unsigned long) imm_expr.X_add_number);
11927 imm_expr.X_add_number = 0;
11929 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number);
11930 imm_expr.X_op = O_absent;
11935 /* bbit[01] bit index when bbit is used but we generate
11936 bbit[01]32 because the index is over 32. Move to the
11937 next candidate if index is not in the valid range. */
11938 gas_assert (!mips_opts.micromips);
11939 my_getExpression (&imm_expr, s);
11940 check_absolute_expr (ip, &imm_expr);
11941 if ((unsigned) imm_expr.X_add_number < 32
11942 || (unsigned) imm_expr.X_add_number > 63)
11944 INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32);
11945 imm_expr.X_op = O_absent;
11950 /* cins, cins32, exts and exts32 position field. Give error
11951 if it's not in the valid range. */
11952 gas_assert (!mips_opts.micromips);
11953 my_getExpression (&imm_expr, s);
11954 check_absolute_expr (ip, &imm_expr);
11955 if ((unsigned) imm_expr.X_add_number > 31)
11957 as_bad (_("Improper position (%lu)"),
11958 (unsigned long) imm_expr.X_add_number);
11959 imm_expr.X_add_number = 0;
11961 /* Make the pos explicit to simplify +S. */
11962 lastpos = imm_expr.X_add_number + 32;
11963 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number);
11964 imm_expr.X_op = O_absent;
11969 /* cins, cins32, exts and exts32 position field. Move to
11970 the next candidate if it's not in the valid range. */
11971 gas_assert (!mips_opts.micromips);
11972 my_getExpression (&imm_expr, s);
11973 check_absolute_expr (ip, &imm_expr);
11974 if ((unsigned) imm_expr.X_add_number < 32
11975 || (unsigned) imm_expr.X_add_number > 63)
11977 lastpos = imm_expr.X_add_number;
11978 INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32);
11979 imm_expr.X_op = O_absent;
11984 /* cins and exts length-minus-one field. */
11985 gas_assert (!mips_opts.micromips);
11986 my_getExpression (&imm_expr, s);
11987 check_absolute_expr (ip, &imm_expr);
11988 if ((unsigned long) imm_expr.X_add_number > 31)
11990 as_bad (_("Improper size (%lu)"),
11991 (unsigned long) imm_expr.X_add_number);
11992 imm_expr.X_add_number = 0;
11994 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
11995 imm_expr.X_op = O_absent;
12000 /* cins32/exts32 and cins/exts aliasing cint32/exts32
12001 length-minus-one field. */
12002 gas_assert (!mips_opts.micromips);
12003 my_getExpression (&imm_expr, s);
12004 check_absolute_expr (ip, &imm_expr);
12005 if ((long) imm_expr.X_add_number < 0
12006 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
12008 as_bad (_("Improper size (%lu)"),
12009 (unsigned long) imm_expr.X_add_number);
12010 imm_expr.X_add_number = 0;
12012 INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number);
12013 imm_expr.X_op = O_absent;
12018 /* seqi/snei immediate field. */
12019 gas_assert (!mips_opts.micromips);
12020 my_getExpression (&imm_expr, s);
12021 check_absolute_expr (ip, &imm_expr);
12022 if ((long) imm_expr.X_add_number < -512
12023 || (long) imm_expr.X_add_number >= 512)
12025 as_bad (_("Improper immediate (%ld)"),
12026 (long) imm_expr.X_add_number);
12027 imm_expr.X_add_number = 0;
12029 INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number);
12030 imm_expr.X_op = O_absent;
12034 case 'a': /* 8-bit signed offset in bit 6 */
12035 gas_assert (!mips_opts.micromips);
12036 my_getExpression (&imm_expr, s);
12037 check_absolute_expr (ip, &imm_expr);
12038 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
12039 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
12040 if (imm_expr.X_add_number < min_range
12041 || imm_expr.X_add_number > max_range)
12043 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12044 (long) min_range, (long) max_range,
12045 (long) imm_expr.X_add_number);
12047 INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number);
12048 imm_expr.X_op = O_absent;
12052 case 'b': /* 8-bit signed offset in bit 3 */
12053 gas_assert (!mips_opts.micromips);
12054 my_getExpression (&imm_expr, s);
12055 check_absolute_expr (ip, &imm_expr);
12056 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
12057 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
12058 if (imm_expr.X_add_number < min_range
12059 || imm_expr.X_add_number > max_range)
12061 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12062 (long) min_range, (long) max_range,
12063 (long) imm_expr.X_add_number);
12065 INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number);
12066 imm_expr.X_op = O_absent;
12070 case 'c': /* 9-bit signed offset in bit 6 */
12071 gas_assert (!mips_opts.micromips);
12072 my_getExpression (&imm_expr, s);
12073 check_absolute_expr (ip, &imm_expr);
12074 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
12075 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
12076 /* We check the offset range before adjusted. */
12079 if (imm_expr.X_add_number < min_range
12080 || imm_expr.X_add_number > max_range)
12082 as_bad (_("Offset not in range %ld..%ld (%ld)"),
12083 (long) min_range, (long) max_range,
12084 (long) imm_expr.X_add_number);
12086 if (imm_expr.X_add_number & 0xf)
12088 as_bad (_("Offset not 16 bytes alignment (%ld)"),
12089 (long) imm_expr.X_add_number);
12091 /* Right shift 4 bits to adjust the offset operand. */
12092 INSERT_OPERAND (0, OFFSET_C, *ip,
12093 imm_expr.X_add_number >> 4);
12094 imm_expr.X_op = O_absent;
12099 gas_assert (!mips_opts.micromips);
12100 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
12102 if (regno == AT && mips_opts.at)
12104 if (mips_opts.at == ATREG)
12105 as_warn (_("used $at without \".set noat\""));
12107 as_warn (_("used $%u with \".set at=$%u\""),
12108 regno, mips_opts.at);
12110 INSERT_OPERAND (0, RZ, *ip, regno);
12114 gas_assert (!mips_opts.micromips);
12115 if (!reg_lookup (&s, RTYPE_FPU, ®no))
12117 INSERT_OPERAND (0, FZ, *ip, regno);
12124 /* Check whether there is only a single bracketed expression
12125 left. If so, it must be the base register and the
12126 constant must be zero. */
12127 if (*s == '(' && strchr (s + 1, '(') == 0)
12130 /* If this value won't fit into the offset, then go find
12131 a macro that will generate a 16- or 32-bit offset code
12133 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12134 if ((i == 0 && (imm_expr.X_op != O_constant
12135 || imm_expr.X_add_number >= 1 << shift
12136 || imm_expr.X_add_number < -1 << shift))
12139 imm_expr.X_op = O_absent;
12142 INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
12143 imm_expr.X_add_number);
12144 imm_expr.X_op = O_absent;
12150 as_bad (_("Internal error: bad %s opcode "
12151 "(unknown extension operand type `+%c'): %s %s"),
12152 mips_opts.micromips ? "microMIPS" : "MIPS",
12153 *args, insn->name, insn->args);
12154 /* Further processing is fruitless. */
12159 case '.': /* 10-bit offset. */
12160 gas_assert (mips_opts.micromips);
12161 case '~': /* 12-bit offset. */
12163 int shift = *args == '.' ? 9 : 11;
12166 /* Check whether there is only a single bracketed expression
12167 left. If so, it must be the base register and the
12168 constant must be zero. */
12169 if (*s == '(' && strchr (s + 1, '(') == 0)
12172 /* If this value won't fit into the offset, then go find
12173 a macro that will generate a 16- or 32-bit offset code
12175 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
12176 if ((i == 0 && (imm_expr.X_op != O_constant
12177 || imm_expr.X_add_number >= 1 << shift
12178 || imm_expr.X_add_number < -1 << shift))
12181 imm_expr.X_op = O_absent;
12185 INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number);
12187 INSERT_OPERAND (mips_opts.micromips,
12188 OFFSET12, *ip, imm_expr.X_add_number);
12189 imm_expr.X_op = O_absent;
12194 case '<': /* must be at least one digit */
12196 * According to the manual, if the shift amount is greater
12197 * than 31 or less than 0, then the shift amount should be
12198 * mod 32. In reality the mips assembler issues an error.
12199 * We issue a warning and mask out all but the low 5 bits.
12201 my_getExpression (&imm_expr, s);
12202 check_absolute_expr (ip, &imm_expr);
12203 if ((unsigned long) imm_expr.X_add_number > 31)
12204 as_warn (_("Improper shift amount (%lu)"),
12205 (unsigned long) imm_expr.X_add_number);
12206 INSERT_OPERAND (mips_opts.micromips,
12207 SHAMT, *ip, imm_expr.X_add_number);
12208 imm_expr.X_op = O_absent;
12212 case '>': /* shift amount minus 32 */
12213 my_getExpression (&imm_expr, s);
12214 check_absolute_expr (ip, &imm_expr);
12215 if ((unsigned long) imm_expr.X_add_number < 32
12216 || (unsigned long) imm_expr.X_add_number > 63)
12218 INSERT_OPERAND (mips_opts.micromips,
12219 SHAMT, *ip, imm_expr.X_add_number - 32);
12220 imm_expr.X_op = O_absent;
12224 case 'k': /* CACHE code. */
12225 case 'h': /* PREFX code. */
12226 case '1': /* SYNC type. */
12227 my_getExpression (&imm_expr, s);
12228 check_absolute_expr (ip, &imm_expr);
12229 if ((unsigned long) imm_expr.X_add_number > 31)
12230 as_warn (_("Invalid value for `%s' (%lu)"),
12232 (unsigned long) imm_expr.X_add_number);
12236 if (mips_fix_cn63xxp1
12237 && !mips_opts.micromips
12238 && strcmp ("pref", insn->name) == 0)
12239 switch (imm_expr.X_add_number)
12248 case 31: /* These are ok. */
12251 default: /* The rest must be changed to 28. */
12252 imm_expr.X_add_number = 28;
12255 INSERT_OPERAND (mips_opts.micromips,
12256 CACHE, *ip, imm_expr.X_add_number);
12259 INSERT_OPERAND (mips_opts.micromips,
12260 PREFX, *ip, imm_expr.X_add_number);
12263 INSERT_OPERAND (mips_opts.micromips,
12264 STYPE, *ip, imm_expr.X_add_number);
12267 imm_expr.X_op = O_absent;
12271 case 'c': /* BREAK code. */
12273 unsigned long mask = (mips_opts.micromips
12274 ? MICROMIPSOP_MASK_CODE
12277 my_getExpression (&imm_expr, s);
12278 check_absolute_expr (ip, &imm_expr);
12279 if ((unsigned long) imm_expr.X_add_number > mask)
12280 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12282 mask, (unsigned long) imm_expr.X_add_number);
12283 INSERT_OPERAND (mips_opts.micromips,
12284 CODE, *ip, imm_expr.X_add_number);
12285 imm_expr.X_op = O_absent;
12290 case 'q': /* Lower BREAK code. */
12292 unsigned long mask = (mips_opts.micromips
12293 ? MICROMIPSOP_MASK_CODE2
12296 my_getExpression (&imm_expr, s);
12297 check_absolute_expr (ip, &imm_expr);
12298 if ((unsigned long) imm_expr.X_add_number > mask)
12299 as_warn (_("Lower code for %s not in range 0..%lu (%lu)"),
12301 mask, (unsigned long) imm_expr.X_add_number);
12302 INSERT_OPERAND (mips_opts.micromips,
12303 CODE2, *ip, imm_expr.X_add_number);
12304 imm_expr.X_op = O_absent;
12309 case 'B': /* 20- or 10-bit syscall/break/wait code. */
12311 unsigned long mask = (mips_opts.micromips
12312 ? MICROMIPSOP_MASK_CODE10
12315 my_getExpression (&imm_expr, s);
12316 check_absolute_expr (ip, &imm_expr);
12317 if ((unsigned long) imm_expr.X_add_number > mask)
12318 as_warn (_("Code for %s not in range 0..%lu (%lu)"),
12320 mask, (unsigned long) imm_expr.X_add_number);
12321 if (mips_opts.micromips)
12322 INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number);
12324 INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number);
12325 imm_expr.X_op = O_absent;
12330 case 'C': /* 25- or 23-bit coprocessor code. */
12332 unsigned long mask = (mips_opts.micromips
12333 ? MICROMIPSOP_MASK_COPZ
12336 my_getExpression (&imm_expr, s);
12337 check_absolute_expr (ip, &imm_expr);
12338 if ((unsigned long) imm_expr.X_add_number > mask)
12339 as_warn (_("Coproccesor code > %u bits (%lu)"),
12340 mips_opts.micromips ? 23U : 25U,
12341 (unsigned long) imm_expr.X_add_number);
12342 INSERT_OPERAND (mips_opts.micromips,
12343 COPZ, *ip, imm_expr.X_add_number);
12344 imm_expr.X_op = O_absent;
12349 case 'J': /* 19-bit WAIT code. */
12350 gas_assert (!mips_opts.micromips);
12351 my_getExpression (&imm_expr, s);
12352 check_absolute_expr (ip, &imm_expr);
12353 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
12355 as_warn (_("Illegal 19-bit code (%lu)"),
12356 (unsigned long) imm_expr.X_add_number);
12357 imm_expr.X_add_number &= OP_MASK_CODE19;
12359 INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number);
12360 imm_expr.X_op = O_absent;
12364 case 'P': /* Performance register. */
12365 gas_assert (!mips_opts.micromips);
12366 my_getExpression (&imm_expr, s);
12367 check_absolute_expr (ip, &imm_expr);
12368 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
12369 as_warn (_("Invalid performance register (%lu)"),
12370 (unsigned long) imm_expr.X_add_number);
12371 if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
12372 && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
12373 as_warn (_("Invalid performance register (%lu)"),
12374 (unsigned long) imm_expr.X_add_number);
12375 INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
12376 imm_expr.X_op = O_absent;
12380 case 'G': /* Coprocessor destination register. */
12382 unsigned long opcode = ip->insn_opcode;
12383 unsigned long mask;
12384 unsigned int types;
12387 if (mips_opts.micromips)
12389 mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
12390 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)
12391 | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL));
12395 case 0x000000fc: /* mfc0 */
12396 case 0x000002fc: /* mtc0 */
12397 case 0x580000fc: /* dmfc0 */
12398 case 0x580002fc: /* dmtc0 */
12408 opcode = (opcode >> OP_SH_OP) & OP_MASK_OP;
12409 cop0 = opcode == OP_OP_COP0;
12411 types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP);
12412 ok = reg_lookup (&s, types, ®no);
12413 if (mips_opts.micromips)
12414 INSERT_OPERAND (1, RS, *ip, regno);
12416 INSERT_OPERAND (0, RD, *ip, regno);
12425 case 'y': /* ALNV.PS source register. */
12426 gas_assert (mips_opts.micromips);
12428 case 'x': /* Ignore register name. */
12429 case 'U': /* Destination register (CLO/CLZ). */
12430 case 'g': /* Coprocessor destination register. */
12431 gas_assert (!mips_opts.micromips);
12432 case 'b': /* Base register. */
12433 case 'd': /* Destination register. */
12434 case 's': /* Source register. */
12435 case 't': /* Target register. */
12436 case 'r': /* Both target and source. */
12437 case 'v': /* Both dest and source. */
12438 case 'w': /* Both dest and target. */
12439 case 'E': /* Coprocessor target register. */
12440 case 'K': /* RDHWR destination register. */
12441 case 'z': /* Must be zero register. */
12444 if (*args == 'E' || *args == 'K')
12445 ok = reg_lookup (&s, RTYPE_NUM, ®no);
12448 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
12449 if (regno == AT && mips_opts.at)
12451 if (mips_opts.at == ATREG)
12452 as_warn (_("Used $at without \".set noat\""));
12454 as_warn (_("Used $%u with \".set at=$%u\""),
12455 regno, mips_opts.at);
12465 if (c == 'r' || c == 'v' || c == 'w')
12472 /* 'z' only matches $0. */
12473 if (c == 'z' && regno != 0)
12476 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
12478 if (regno == lastregno)
12481 = _("Source and destination must be different");
12484 if (regno == 31 && lastregno == 0xffffffff)
12487 = _("A destination register must be supplied");
12491 /* Now that we have assembled one operand, we use the args
12492 string to figure out where it goes in the instruction. */
12499 INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno);
12503 if (mips_opts.micromips)
12504 INSERT_OPERAND (1, RS, *ip, regno);
12506 INSERT_OPERAND (0, RD, *ip, regno);
12511 INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno);
12515 gas_assert (!mips_opts.micromips);
12516 INSERT_OPERAND (0, RD, *ip, regno);
12517 INSERT_OPERAND (0, RT, *ip, regno);
12523 INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno);
12527 gas_assert (mips_opts.micromips);
12528 INSERT_OPERAND (1, RS3, *ip, regno);
12532 /* This case exists because on the r3000 trunc
12533 expands into a macro which requires a gp
12534 register. On the r6000 or r4000 it is
12535 assembled into a single instruction which
12536 ignores the register. Thus the insn version
12537 is MIPS_ISA2 and uses 'x', and the macro
12538 version is MIPS_ISA1 and uses 't'. */
12542 /* This case is for the div instruction, which
12543 acts differently if the destination argument
12544 is $0. This only matches $0, and is checked
12545 outside the switch. */
12555 INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno);
12559 INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno);
12564 case 'O': /* MDMX alignment immediate constant. */
12565 gas_assert (!mips_opts.micromips);
12566 my_getExpression (&imm_expr, s);
12567 check_absolute_expr (ip, &imm_expr);
12568 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
12569 as_warn (_("Improper align amount (%ld), using low bits"),
12570 (long) imm_expr.X_add_number);
12571 INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number);
12572 imm_expr.X_op = O_absent;
12576 case 'Q': /* MDMX vector, element sel, or const. */
12579 /* MDMX Immediate. */
12580 gas_assert (!mips_opts.micromips);
12581 my_getExpression (&imm_expr, s);
12582 check_absolute_expr (ip, &imm_expr);
12583 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
12584 as_warn (_("Invalid MDMX Immediate (%ld)"),
12585 (long) imm_expr.X_add_number);
12586 INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number);
12587 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12588 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
12590 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
12591 imm_expr.X_op = O_absent;
12595 /* Not MDMX Immediate. Fall through. */
12596 case 'X': /* MDMX destination register. */
12597 case 'Y': /* MDMX source register. */
12598 case 'Z': /* MDMX target register. */
12601 gas_assert (!mips_opts.micromips);
12602 case 'D': /* Floating point destination register. */
12603 case 'S': /* Floating point source register. */
12604 case 'T': /* Floating point target register. */
12605 case 'R': /* Floating point source register. */
12609 || ((mips_opts.ase & ASE_MDMX)
12610 && (ip->insn_mo->pinfo & FP_D)
12611 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
12612 | INSN_COPROC_MEMORY_DELAY
12613 | INSN_LOAD_COPROC_DELAY
12614 | INSN_LOAD_MEMORY_DELAY
12615 | INSN_STORE_MEMORY))))
12616 rtype |= RTYPE_VEC;
12618 if (reg_lookup (&s, rtype, ®no))
12620 if ((regno & 1) != 0
12622 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
12623 as_warn (_("Float register should be even, was %d"),
12631 if (c == 'V' || c == 'W')
12642 INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno);
12648 INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno);
12652 /* This is like 'Z', but also needs to fix the MDMX
12653 vector/scalar select bits. Note that the
12654 scalar immediate case is handled above. */
12657 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
12658 int max_el = (is_qh ? 3 : 7);
12660 my_getExpression(&imm_expr, s);
12661 check_absolute_expr (ip, &imm_expr);
12663 if (imm_expr.X_add_number > max_el)
12664 as_bad (_("Bad element selector %ld"),
12665 (long) imm_expr.X_add_number);
12666 imm_expr.X_add_number &= max_el;
12667 ip->insn_opcode |= (imm_expr.X_add_number
12670 imm_expr.X_op = O_absent;
12672 as_warn (_("Expecting ']' found '%s'"), s);
12678 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
12679 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
12682 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
12685 /* Fall through. */
12689 INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno);
12693 INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno);
12703 INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno);
12707 INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno);
12713 my_getExpression (&imm_expr, s);
12714 if (imm_expr.X_op != O_big
12715 && imm_expr.X_op != O_constant)
12716 insn_error = _("absolute expression required");
12717 if (HAVE_32BIT_GPRS)
12718 normalize_constant_expr (&imm_expr);
12723 my_getExpression (&offset_expr, s);
12724 normalize_address_expr (&offset_expr);
12725 *imm_reloc = BFD_RELOC_32;
12738 unsigned char temp[8];
12740 unsigned int length;
12745 /* These only appear as the last operand in an
12746 instruction, and every instruction that accepts
12747 them in any variant accepts them in all variants.
12748 This means we don't have to worry about backing out
12749 any changes if the instruction does not match.
12751 The difference between them is the size of the
12752 floating point constant and where it goes. For 'F'
12753 and 'L' the constant is 64 bits; for 'f' and 'l' it
12754 is 32 bits. Where the constant is placed is based
12755 on how the MIPS assembler does things:
12758 f -- immediate value
12761 The .lit4 and .lit8 sections are only used if
12762 permitted by the -G argument.
12764 The code below needs to know whether the target register
12765 is 32 or 64 bits wide. It relies on the fact 'f' and
12766 'F' are used with GPR-based instructions and 'l' and
12767 'L' are used with FPR-based instructions. */
12769 f64 = *args == 'F' || *args == 'L';
12770 using_gprs = *args == 'F' || *args == 'f';
12772 save_in = input_line_pointer;
12773 input_line_pointer = s;
12774 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
12776 s = input_line_pointer;
12777 input_line_pointer = save_in;
12778 if (err != NULL && *err != '\0')
12780 as_bad (_("Bad floating point constant: %s"), err);
12781 memset (temp, '\0', sizeof temp);
12782 length = f64 ? 8 : 4;
12785 gas_assert (length == (unsigned) (f64 ? 8 : 4));
12789 && (g_switch_value < 4
12790 || (temp[0] == 0 && temp[1] == 0)
12791 || (temp[2] == 0 && temp[3] == 0))))
12793 imm_expr.X_op = O_constant;
12794 if (!target_big_endian)
12795 imm_expr.X_add_number = bfd_getl32 (temp);
12797 imm_expr.X_add_number = bfd_getb32 (temp);
12799 else if (length > 4
12800 && !mips_disable_float_construction
12801 /* Constants can only be constructed in GPRs and
12802 copied to FPRs if the GPRs are at least as wide
12803 as the FPRs. Force the constant into memory if
12804 we are using 64-bit FPRs but the GPRs are only
12807 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
12808 && ((temp[0] == 0 && temp[1] == 0)
12809 || (temp[2] == 0 && temp[3] == 0))
12810 && ((temp[4] == 0 && temp[5] == 0)
12811 || (temp[6] == 0 && temp[7] == 0)))
12813 /* The value is simple enough to load with a couple of
12814 instructions. If using 32-bit registers, set
12815 imm_expr to the high order 32 bits and offset_expr to
12816 the low order 32 bits. Otherwise, set imm_expr to
12817 the entire 64 bit constant. */
12818 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
12820 imm_expr.X_op = O_constant;
12821 offset_expr.X_op = O_constant;
12822 if (!target_big_endian)
12824 imm_expr.X_add_number = bfd_getl32 (temp + 4);
12825 offset_expr.X_add_number = bfd_getl32 (temp);
12829 imm_expr.X_add_number = bfd_getb32 (temp);
12830 offset_expr.X_add_number = bfd_getb32 (temp + 4);
12832 if (offset_expr.X_add_number == 0)
12833 offset_expr.X_op = O_absent;
12837 imm_expr.X_op = O_constant;
12838 if (!target_big_endian)
12839 imm_expr.X_add_number = bfd_getl64 (temp);
12841 imm_expr.X_add_number = bfd_getb64 (temp);
12846 const char *newname;
12849 /* Switch to the right section. */
12851 subseg = now_subseg;
12854 default: /* unused default case avoids warnings. */
12856 newname = RDATA_SECTION_NAME;
12857 if (g_switch_value >= 8)
12861 newname = RDATA_SECTION_NAME;
12864 gas_assert (g_switch_value >= 4);
12868 new_seg = subseg_new (newname, (subsegT) 0);
12869 bfd_set_section_flags (stdoutput, new_seg,
12874 frag_align (*args == 'l' ? 2 : 3, 0, 0);
12875 if (strncmp (TARGET_OS, "elf", 3) != 0)
12876 record_alignment (new_seg, 4);
12878 record_alignment (new_seg, *args == 'l' ? 2 : 3);
12879 if (seg == now_seg)
12880 as_bad (_("Can't use floating point insn in this section"));
12882 /* Set the argument to the current address in the
12884 offset_expr.X_op = O_symbol;
12885 offset_expr.X_add_symbol = symbol_temp_new_now ();
12886 offset_expr.X_add_number = 0;
12888 /* Put the floating point number into the section. */
12889 p = frag_more ((int) length);
12890 memcpy (p, temp, length);
12892 /* Switch back to the original section. */
12893 subseg_set (seg, subseg);
12898 case 'i': /* 16-bit unsigned immediate. */
12899 case 'j': /* 16-bit signed immediate. */
12900 *imm_reloc = BFD_RELOC_LO16;
12901 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
12904 offsetT minval, maxval;
12906 more = (insn + 1 < past
12907 && strcmp (insn->name, insn[1].name) == 0);
12909 /* For compatibility with older assemblers, we accept
12910 0x8000-0xffff as signed 16-bit numbers when only
12911 signed numbers are allowed. */
12913 minval = 0, maxval = 0xffff;
12915 minval = -0x8000, maxval = 0x7fff;
12917 minval = -0x8000, maxval = 0xffff;
12919 if (imm_expr.X_op != O_constant
12920 || imm_expr.X_add_number < minval
12921 || imm_expr.X_add_number > maxval)
12925 if (imm_expr.X_op == O_constant
12926 || imm_expr.X_op == O_big)
12927 as_bad (_("Expression out of range"));
12933 case 'o': /* 16-bit offset. */
12934 offset_reloc[0] = BFD_RELOC_LO16;
12935 offset_reloc[1] = BFD_RELOC_UNUSED;
12936 offset_reloc[2] = BFD_RELOC_UNUSED;
12938 /* Check whether there is only a single bracketed expression
12939 left. If so, it must be the base register and the
12940 constant must be zero. */
12941 if (*s == '(' && strchr (s + 1, '(') == 0)
12943 offset_expr.X_op = O_constant;
12944 offset_expr.X_add_number = 0;
12948 /* If this value won't fit into a 16 bit offset, then go
12949 find a macro that will generate the 32 bit offset
12951 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
12952 && (offset_expr.X_op != O_constant
12953 || offset_expr.X_add_number >= 0x8000
12954 || offset_expr.X_add_number < -0x8000))
12960 case 'p': /* PC-relative offset. */
12961 *offset_reloc = BFD_RELOC_16_PCREL_S2;
12962 my_getExpression (&offset_expr, s);
12966 case 'u': /* Upper 16 bits. */
12967 *imm_reloc = BFD_RELOC_LO16;
12968 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
12969 && imm_expr.X_op == O_constant
12970 && (imm_expr.X_add_number < 0
12971 || imm_expr.X_add_number >= 0x10000))
12972 as_bad (_("lui expression (%lu) not in range 0..65535"),
12973 (unsigned long) imm_expr.X_add_number);
12977 case 'a': /* 26-bit address. */
12978 *offset_reloc = BFD_RELOC_MIPS_JMP;
12979 my_getExpression (&offset_expr, s);
12983 case 'N': /* 3-bit branch condition code. */
12984 case 'M': /* 3-bit compare condition code. */
12986 if (ip->insn_mo->pinfo & (FP_D | FP_S))
12987 rtype |= RTYPE_FCC;
12988 if (!reg_lookup (&s, rtype, ®no))
12990 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
12991 || strcmp (str + strlen (str) - 5, "any2f") == 0
12992 || strcmp (str + strlen (str) - 5, "any2t") == 0)
12993 && (regno & 1) != 0)
12994 as_warn (_("Condition code register should be even for %s, "
12997 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
12998 || strcmp (str + strlen (str) - 5, "any4t") == 0)
12999 && (regno & 3) != 0)
13000 as_warn (_("Condition code register should be 0 or 4 for %s, "
13004 INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno);
13006 INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno);
13010 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
13021 while (ISDIGIT (*s));
13024 c = 8; /* Invalid sel value. */
13027 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
13028 INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c);
13032 gas_assert (!mips_opts.micromips);
13033 /* Must be at least one digit. */
13034 my_getExpression (&imm_expr, s);
13035 check_absolute_expr (ip, &imm_expr);
13037 if ((unsigned long) imm_expr.X_add_number
13038 > (unsigned long) OP_MASK_VECBYTE)
13040 as_bad (_("bad byte vector index (%ld)"),
13041 (long) imm_expr.X_add_number);
13042 imm_expr.X_add_number = 0;
13045 INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number);
13046 imm_expr.X_op = O_absent;
13051 gas_assert (!mips_opts.micromips);
13052 my_getExpression (&imm_expr, s);
13053 check_absolute_expr (ip, &imm_expr);
13055 if ((unsigned long) imm_expr.X_add_number
13056 > (unsigned long) OP_MASK_VECALIGN)
13058 as_bad (_("bad byte vector index (%ld)"),
13059 (long) imm_expr.X_add_number);
13060 imm_expr.X_add_number = 0;
13063 INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number);
13064 imm_expr.X_op = O_absent;
13068 case 'm': /* Opcode extension character. */
13069 gas_assert (mips_opts.micromips);
13074 if (strncmp (s, "$pc", 3) == 0)
13102 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no);
13103 if (regno == AT && mips_opts.at)
13105 if (mips_opts.at == ATREG)
13106 as_warn (_("Used $at without \".set noat\""));
13108 as_warn (_("Used $%u with \".set at=$%u\""),
13109 regno, mips_opts.at);
13115 gas_assert (args[1] == ',');
13121 gas_assert (args[1] == ',');
13123 continue; /* Nothing to do. */
13129 if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4))
13131 if (regno == lastregno)
13134 = _("Source and destination must be different");
13137 if (regno == 31 && lastregno == 0xffffffff)
13140 = _("A destination register must be supplied");
13151 gas_assert (args[1] == ',');
13158 gas_assert (args[1] == ',');
13161 continue; /* Nothing to do. */
13165 /* Make sure regno is the same as lastregno. */
13166 if (c == 't' && regno != lastregno)
13169 /* Make sure regno is the same as destregno. */
13170 if (c == 'x' && regno != destregno)
13173 /* We need to save regno, before regno maps to the
13174 microMIPS register encoding. */
13184 regno = ILLEGAL_REG;
13188 regno = mips32_to_micromips_reg_b_map[regno];
13192 regno = mips32_to_micromips_reg_c_map[regno];
13196 regno = mips32_to_micromips_reg_d_map[regno];
13200 regno = mips32_to_micromips_reg_e_map[regno];
13204 regno = mips32_to_micromips_reg_f_map[regno];
13208 regno = mips32_to_micromips_reg_g_map[regno];
13212 regno = mips32_to_micromips_reg_h_map[regno];
13216 switch (EXTRACT_OPERAND (1, MI, *ip))
13221 else if (regno == 22)
13223 else if (regno == 5)
13225 else if (regno == 6)
13227 else if (regno == 7)
13230 regno = ILLEGAL_REG;
13236 else if (regno == 7)
13239 regno = ILLEGAL_REG;
13246 regno = ILLEGAL_REG;
13250 regno = ILLEGAL_REG;
13256 regno = mips32_to_micromips_reg_l_map[regno];
13260 regno = mips32_to_micromips_reg_m_map[regno];
13264 regno = mips32_to_micromips_reg_n_map[regno];
13268 regno = mips32_to_micromips_reg_q_map[regno];
13273 regno = ILLEGAL_REG;
13278 regno = ILLEGAL_REG;
13283 regno = ILLEGAL_REG;
13286 case 'j': /* Do nothing. */
13296 if (regno == ILLEGAL_REG)
13302 INSERT_OPERAND (1, MB, *ip, regno);
13306 INSERT_OPERAND (1, MC, *ip, regno);
13310 INSERT_OPERAND (1, MD, *ip, regno);
13314 INSERT_OPERAND (1, ME, *ip, regno);
13318 INSERT_OPERAND (1, MF, *ip, regno);
13322 INSERT_OPERAND (1, MG, *ip, regno);
13326 INSERT_OPERAND (1, MH, *ip, regno);
13330 INSERT_OPERAND (1, MI, *ip, regno);
13334 INSERT_OPERAND (1, MJ, *ip, regno);
13338 INSERT_OPERAND (1, ML, *ip, regno);
13342 INSERT_OPERAND (1, MM, *ip, regno);
13346 INSERT_OPERAND (1, MN, *ip, regno);
13350 INSERT_OPERAND (1, MP, *ip, regno);
13354 INSERT_OPERAND (1, MQ, *ip, regno);
13357 case 'a': /* Do nothing. */
13358 case 's': /* Do nothing. */
13359 case 't': /* Do nothing. */
13360 case 'x': /* Do nothing. */
13361 case 'y': /* Do nothing. */
13362 case 'z': /* Do nothing. */
13372 bfd_reloc_code_real_type r[3];
13376 /* Check whether there is only a single bracketed
13377 expression left. If so, it must be the base register
13378 and the constant must be zero. */
13379 if (*s == '(' && strchr (s + 1, '(') == 0)
13381 INSERT_OPERAND (1, IMMA, *ip, 0);
13385 if (my_getSmallExpression (&ep, r, s) > 0
13386 || !expr_const_in_range (&ep, -64, 64, 2))
13389 imm = ep.X_add_number >> 2;
13390 INSERT_OPERAND (1, IMMA, *ip, imm);
13397 bfd_reloc_code_real_type r[3];
13401 if (my_getSmallExpression (&ep, r, s) > 0
13402 || ep.X_op != O_constant)
13405 for (imm = 0; imm < 8; imm++)
13406 if (micromips_imm_b_map[imm] == ep.X_add_number)
13411 INSERT_OPERAND (1, IMMB, *ip, imm);
13418 bfd_reloc_code_real_type r[3];
13422 if (my_getSmallExpression (&ep, r, s) > 0
13423 || ep.X_op != O_constant)
13426 for (imm = 0; imm < 16; imm++)
13427 if (micromips_imm_c_map[imm] == ep.X_add_number)
13432 INSERT_OPERAND (1, IMMC, *ip, imm);
13437 case 'D': /* pc relative offset */
13438 case 'E': /* pc relative offset */
13439 my_getExpression (&offset_expr, s);
13440 if (offset_expr.X_op == O_register)
13443 if (!forced_insn_length)
13444 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
13446 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
13448 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
13454 bfd_reloc_code_real_type r[3];
13458 if (my_getSmallExpression (&ep, r, s) > 0
13459 || !expr_const_in_range (&ep, 0, 16, 0))
13462 imm = ep.X_add_number;
13463 INSERT_OPERAND (1, IMMF, *ip, imm);
13470 bfd_reloc_code_real_type r[3];
13474 /* Check whether there is only a single bracketed
13475 expression left. If so, it must be the base register
13476 and the constant must be zero. */
13477 if (*s == '(' && strchr (s + 1, '(') == 0)
13479 INSERT_OPERAND (1, IMMG, *ip, 0);
13483 if (my_getSmallExpression (&ep, r, s) > 0
13484 || !expr_const_in_range (&ep, -1, 15, 0))
13487 imm = ep.X_add_number & 15;
13488 INSERT_OPERAND (1, IMMG, *ip, imm);
13495 bfd_reloc_code_real_type r[3];
13499 /* Check whether there is only a single bracketed
13500 expression left. If so, it must be the base register
13501 and the constant must be zero. */
13502 if (*s == '(' && strchr (s + 1, '(') == 0)
13504 INSERT_OPERAND (1, IMMH, *ip, 0);
13508 if (my_getSmallExpression (&ep, r, s) > 0
13509 || !expr_const_in_range (&ep, 0, 16, 1))
13512 imm = ep.X_add_number >> 1;
13513 INSERT_OPERAND (1, IMMH, *ip, imm);
13520 bfd_reloc_code_real_type r[3];
13524 if (my_getSmallExpression (&ep, r, s) > 0
13525 || !expr_const_in_range (&ep, -1, 127, 0))
13528 imm = ep.X_add_number & 127;
13529 INSERT_OPERAND (1, IMMI, *ip, imm);
13536 bfd_reloc_code_real_type r[3];
13540 /* Check whether there is only a single bracketed
13541 expression left. If so, it must be the base register
13542 and the constant must be zero. */
13543 if (*s == '(' && strchr (s + 1, '(') == 0)
13545 INSERT_OPERAND (1, IMMJ, *ip, 0);
13549 if (my_getSmallExpression (&ep, r, s) > 0
13550 || !expr_const_in_range (&ep, 0, 16, 2))
13553 imm = ep.X_add_number >> 2;
13554 INSERT_OPERAND (1, IMMJ, *ip, imm);
13561 bfd_reloc_code_real_type r[3];
13565 /* Check whether there is only a single bracketed
13566 expression left. If so, it must be the base register
13567 and the constant must be zero. */
13568 if (*s == '(' && strchr (s + 1, '(') == 0)
13570 INSERT_OPERAND (1, IMML, *ip, 0);
13574 if (my_getSmallExpression (&ep, r, s) > 0
13575 || !expr_const_in_range (&ep, 0, 16, 0))
13578 imm = ep.X_add_number;
13579 INSERT_OPERAND (1, IMML, *ip, imm);
13586 bfd_reloc_code_real_type r[3];
13590 if (my_getSmallExpression (&ep, r, s) > 0
13591 || !expr_const_in_range (&ep, 1, 9, 0))
13594 imm = ep.X_add_number & 7;
13595 INSERT_OPERAND (1, IMMM, *ip, imm);
13600 case 'N': /* Register list for lwm and swm. */
13602 /* A comma-separated list of registers and/or
13603 dash-separated contiguous ranges including
13604 both ra and a set of one or more registers
13605 starting at s0 up to s3 which have to be
13612 and any permutations of these. */
13613 unsigned int reglist;
13616 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13619 if ((reglist & 0xfff1ffff) != 0x80010000)
13622 reglist = (reglist >> 17) & 7;
13624 if ((reglist & -reglist) != reglist)
13627 imm = ffs (reglist) - 1;
13628 INSERT_OPERAND (1, IMMN, *ip, imm);
13632 case 'O': /* sdbbp 4-bit code. */
13634 bfd_reloc_code_real_type r[3];
13638 if (my_getSmallExpression (&ep, r, s) > 0
13639 || !expr_const_in_range (&ep, 0, 16, 0))
13642 imm = ep.X_add_number;
13643 INSERT_OPERAND (1, IMMO, *ip, imm);
13650 bfd_reloc_code_real_type r[3];
13654 if (my_getSmallExpression (&ep, r, s) > 0
13655 || !expr_const_in_range (&ep, 0, 32, 2))
13658 imm = ep.X_add_number >> 2;
13659 INSERT_OPERAND (1, IMMP, *ip, imm);
13666 bfd_reloc_code_real_type r[3];
13670 if (my_getSmallExpression (&ep, r, s) > 0
13671 || !expr_const_in_range (&ep, -0x400000, 0x400000, 2))
13674 imm = ep.X_add_number >> 2;
13675 INSERT_OPERAND (1, IMMQ, *ip, imm);
13682 bfd_reloc_code_real_type r[3];
13686 /* Check whether there is only a single bracketed
13687 expression left. If so, it must be the base register
13688 and the constant must be zero. */
13689 if (*s == '(' && strchr (s + 1, '(') == 0)
13691 INSERT_OPERAND (1, IMMU, *ip, 0);
13695 if (my_getSmallExpression (&ep, r, s) > 0
13696 || !expr_const_in_range (&ep, 0, 32, 2))
13699 imm = ep.X_add_number >> 2;
13700 INSERT_OPERAND (1, IMMU, *ip, imm);
13707 bfd_reloc_code_real_type r[3];
13711 if (my_getSmallExpression (&ep, r, s) > 0
13712 || !expr_const_in_range (&ep, 0, 64, 2))
13715 imm = ep.X_add_number >> 2;
13716 INSERT_OPERAND (1, IMMW, *ip, imm);
13723 bfd_reloc_code_real_type r[3];
13727 if (my_getSmallExpression (&ep, r, s) > 0
13728 || !expr_const_in_range (&ep, -8, 8, 0))
13731 imm = ep.X_add_number;
13732 INSERT_OPERAND (1, IMMX, *ip, imm);
13739 bfd_reloc_code_real_type r[3];
13743 if (my_getSmallExpression (&ep, r, s) > 0
13744 || expr_const_in_range (&ep, -2, 2, 2)
13745 || !expr_const_in_range (&ep, -258, 258, 2))
13748 imm = ep.X_add_number >> 2;
13749 imm = ((imm >> 1) & ~0xff) | (imm & 0xff);
13750 INSERT_OPERAND (1, IMMY, *ip, imm);
13757 bfd_reloc_code_real_type r[3];
13760 if (my_getSmallExpression (&ep, r, s) > 0
13761 || !expr_const_in_range (&ep, 0, 1, 0))
13768 as_bad (_("Internal error: bad microMIPS opcode "
13769 "(unknown extension operand type `m%c'): %s %s"),
13770 *args, insn->name, insn->args);
13771 /* Further processing is fruitless. */
13776 case 'n': /* Register list for 32-bit lwm and swm. */
13777 gas_assert (mips_opts.micromips);
13779 /* A comma-separated list of registers and/or
13780 dash-separated contiguous ranges including
13781 at least one of ra and a set of one or more
13782 registers starting at s0 up to s7 and then
13783 s8 which have to be consecutive, e.g.:
13791 and any permutations of these. */
13792 unsigned int reglist;
13796 if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list))
13799 if ((reglist & 0x3f00ffff) != 0)
13802 ra = (reglist >> 27) & 0x10;
13803 reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
13805 if ((reglist & -reglist) != reglist)
13808 imm = (ffs (reglist) - 1) | ra;
13809 INSERT_OPERAND (1, RT, *ip, imm);
13810 imm_expr.X_op = O_absent;
13814 case '|': /* 4-bit trap code. */
13815 gas_assert (mips_opts.micromips);
13816 my_getExpression (&imm_expr, s);
13817 check_absolute_expr (ip, &imm_expr);
13818 if ((unsigned long) imm_expr.X_add_number
13819 > MICROMIPSOP_MASK_TRAP)
13820 as_bad (_("Trap code (%lu) for %s not in 0..15 range"),
13821 (unsigned long) imm_expr.X_add_number,
13822 ip->insn_mo->name);
13823 INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number);
13824 imm_expr.X_op = O_absent;
13829 as_bad (_("Bad char = '%c'\n"), *args);
13834 /* Args don't match. */
13836 insn_error = _("Illegal operands");
13837 if (insn + 1 < past && !strcmp (insn->name, insn[1].name))
13842 else if (wrong_delay_slot_insns && need_delay_slot_ok)
13844 gas_assert (firstinsn);
13845 need_delay_slot_ok = FALSE;
13854 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
13856 /* This routine assembles an instruction into its binary format when
13857 assembling for the mips16. As a side effect, it sets one of the
13858 global variables imm_reloc or offset_reloc to the type of relocation
13859 to do if one of the operands is an address expression. It also sets
13860 forced_insn_length to the resulting instruction size in bytes if the
13861 user explicitly requested a small or extended instruction. */
13864 mips16_ip (char *str, struct mips_cl_insn *ip)
13868 struct mips_opcode *insn;
13870 unsigned int regno;
13871 unsigned int lastregno = 0;
13877 forced_insn_length = 0;
13879 for (s = str; ISLOWER (*s); ++s)
13891 if (s[1] == 't' && s[2] == ' ')
13894 forced_insn_length = 2;
13898 else if (s[1] == 'e' && s[2] == ' ')
13901 forced_insn_length = 4;
13905 /* Fall through. */
13907 insn_error = _("unknown opcode");
13911 if (mips_opts.noautoextend && !forced_insn_length)
13912 forced_insn_length = 2;
13914 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
13916 insn_error = _("unrecognized opcode");
13925 gas_assert (strcmp (insn->name, str) == 0);
13927 ok = is_opcode_valid_16 (insn);
13930 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
13931 && strcmp (insn->name, insn[1].name) == 0)
13940 static char buf[100];
13942 _("Opcode not supported on this processor: %s (%s)"),
13943 mips_cpu_info_from_arch (mips_opts.arch)->name,
13944 mips_cpu_info_from_isa (mips_opts.isa)->name);
13951 create_insn (ip, insn);
13952 imm_expr.X_op = O_absent;
13953 imm_reloc[0] = BFD_RELOC_UNUSED;
13954 imm_reloc[1] = BFD_RELOC_UNUSED;
13955 imm_reloc[2] = BFD_RELOC_UNUSED;
13956 imm2_expr.X_op = O_absent;
13957 offset_expr.X_op = O_absent;
13958 offset_reloc[0] = BFD_RELOC_UNUSED;
13959 offset_reloc[1] = BFD_RELOC_UNUSED;
13960 offset_reloc[2] = BFD_RELOC_UNUSED;
13961 for (args = insn->args; 1; ++args)
13968 /* In this switch statement we call break if we did not find
13969 a match, continue if we did find a match, or return if we
13980 /* Stuff the immediate value in now, if we can. */
13981 if (imm_expr.X_op == O_constant
13982 && *imm_reloc > BFD_RELOC_UNUSED
13983 && insn->pinfo != INSN_MACRO
13984 && calculate_reloc (*offset_reloc,
13985 imm_expr.X_add_number, &value))
13987 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
13988 *offset_reloc, value, forced_insn_length,
13990 imm_expr.X_op = O_absent;
13991 *imm_reloc = BFD_RELOC_UNUSED;
13992 *offset_reloc = BFD_RELOC_UNUSED;
14006 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14009 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14025 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14027 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14031 /* Fall through. */
14042 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no))
14044 if (c == 'v' || c == 'w')
14047 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
14049 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
14060 if (c == 'v' || c == 'w')
14062 regno = mips16_to_32_reg_map[lastregno];
14076 regno = mips32_to_16_reg_map[regno];
14081 regno = ILLEGAL_REG;
14086 regno = ILLEGAL_REG;
14091 regno = ILLEGAL_REG;
14096 if (regno == AT && mips_opts.at)
14098 if (mips_opts.at == ATREG)
14099 as_warn (_("used $at without \".set noat\""));
14101 as_warn (_("used $%u with \".set at=$%u\""),
14102 regno, mips_opts.at);
14110 if (regno == ILLEGAL_REG)
14117 MIPS16_INSERT_OPERAND (RX, *ip, regno);
14121 MIPS16_INSERT_OPERAND (RY, *ip, regno);
14124 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
14127 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
14133 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
14136 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
14137 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
14147 if (strncmp (s, "$pc", 3) == 0)
14164 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
14167 if (imm_expr.X_op != O_constant)
14169 forced_insn_length = 4;
14170 ip->insn_opcode |= MIPS16_EXTEND;
14174 /* We need to relax this instruction. */
14175 *offset_reloc = *imm_reloc;
14176 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14181 *imm_reloc = BFD_RELOC_UNUSED;
14182 /* Fall through. */
14189 my_getExpression (&imm_expr, s);
14190 if (imm_expr.X_op == O_register)
14192 /* What we thought was an expression turned out to
14195 if (s[0] == '(' && args[1] == '(')
14197 /* It looks like the expression was omitted
14198 before a register indirection, which means
14199 that the expression is implicitly zero. We
14200 still set up imm_expr, so that we handle
14201 explicit extensions correctly. */
14202 imm_expr.X_op = O_constant;
14203 imm_expr.X_add_number = 0;
14204 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14211 /* We need to relax this instruction. */
14212 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
14221 /* We use offset_reloc rather than imm_reloc for the PC
14222 relative operands. This lets macros with both
14223 immediate and address operands work correctly. */
14224 my_getExpression (&offset_expr, s);
14226 if (offset_expr.X_op == O_register)
14229 /* We need to relax this instruction. */
14230 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
14234 case '6': /* break code */
14235 my_getExpression (&imm_expr, s);
14236 check_absolute_expr (ip, &imm_expr);
14237 if ((unsigned long) imm_expr.X_add_number > 63)
14238 as_warn (_("Invalid value for `%s' (%lu)"),
14240 (unsigned long) imm_expr.X_add_number);
14241 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
14242 imm_expr.X_op = O_absent;
14246 case 'a': /* 26 bit address */
14247 my_getExpression (&offset_expr, s);
14249 *offset_reloc = BFD_RELOC_MIPS16_JMP;
14250 ip->insn_opcode <<= 16;
14253 case 'l': /* register list for entry macro */
14254 case 'L': /* register list for exit macro */
14264 unsigned int freg, reg1, reg2;
14266 while (*s == ' ' || *s == ',')
14268 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14270 else if (reg_lookup (&s, RTYPE_FPU, ®1))
14274 as_bad (_("can't parse register list"));
14284 if (!reg_lookup (&s, freg ? RTYPE_FPU
14285 : (RTYPE_GP | RTYPE_NUM), ®2))
14287 as_bad (_("invalid register list"));
14291 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
14293 mask &= ~ (7 << 3);
14296 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
14298 mask &= ~ (7 << 3);
14301 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
14302 mask |= (reg2 - 3) << 3;
14303 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
14304 mask |= (reg2 - 15) << 1;
14305 else if (reg1 == RA && reg2 == RA)
14309 as_bad (_("invalid register list"));
14313 /* The mask is filled in in the opcode table for the
14314 benefit of the disassembler. We remove it before
14315 applying the actual mask. */
14316 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
14317 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
14321 case 'm': /* Register list for save insn. */
14322 case 'M': /* Register list for restore insn. */
14324 int opcode = ip->insn_opcode;
14325 int framesz = 0, seen_framesz = 0;
14326 int nargs = 0, statics = 0, sregs = 0;
14330 unsigned int reg1, reg2;
14332 SKIP_SPACE_TABS (s);
14335 SKIP_SPACE_TABS (s);
14337 my_getExpression (&imm_expr, s);
14338 if (imm_expr.X_op == O_constant)
14340 /* Handle the frame size. */
14343 as_bad (_("more than one frame size in list"));
14347 framesz = imm_expr.X_add_number;
14348 imm_expr.X_op = O_absent;
14353 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1))
14355 as_bad (_("can't parse register list"));
14367 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2)
14370 as_bad (_("can't parse register list"));
14375 while (reg1 <= reg2)
14377 if (reg1 >= 4 && reg1 <= 7)
14381 nargs |= 1 << (reg1 - 4);
14383 /* statics $a0-$a3 */
14384 statics |= 1 << (reg1 - 4);
14386 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
14389 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
14391 else if (reg1 == 31)
14393 /* Add $ra to insn. */
14398 as_bad (_("unexpected register in list"));
14406 /* Encode args/statics combination. */
14407 if (nargs & statics)
14408 as_bad (_("arg/static registers overlap"));
14409 else if (nargs == 0xf)
14410 /* All $a0-$a3 are args. */
14411 opcode |= MIPS16_ALL_ARGS << 16;
14412 else if (statics == 0xf)
14413 /* All $a0-$a3 are statics. */
14414 opcode |= MIPS16_ALL_STATICS << 16;
14417 int narg = 0, nstat = 0;
14419 /* Count arg registers. */
14420 while (nargs & 0x1)
14426 as_bad (_("invalid arg register list"));
14428 /* Count static registers. */
14429 while (statics & 0x8)
14431 statics = (statics << 1) & 0xf;
14435 as_bad (_("invalid static register list"));
14437 /* Encode args/statics. */
14438 opcode |= ((narg << 2) | nstat) << 16;
14441 /* Encode $s0/$s1. */
14442 if (sregs & (1 << 0)) /* $s0 */
14444 if (sregs & (1 << 1)) /* $s1 */
14450 /* Count regs $s2-$s8. */
14458 as_bad (_("invalid static register list"));
14459 /* Encode $s2-$s8. */
14460 opcode |= nsreg << 24;
14463 /* Encode frame size. */
14465 as_bad (_("missing frame size"));
14466 else if ((framesz & 7) != 0 || framesz < 0
14467 || framesz > 0xff * 8)
14468 as_bad (_("invalid frame size"));
14469 else if (framesz != 128 || (opcode >> 16) != 0)
14472 opcode |= (((framesz & 0xf0) << 16)
14473 | (framesz & 0x0f));
14476 /* Finally build the instruction. */
14477 if ((opcode >> 16) != 0 || framesz == 0)
14478 opcode |= MIPS16_EXTEND;
14479 ip->insn_opcode = opcode;
14483 case 'e': /* extend code */
14484 my_getExpression (&imm_expr, s);
14485 check_absolute_expr (ip, &imm_expr);
14486 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
14488 as_warn (_("Invalid value for `%s' (%lu)"),
14490 (unsigned long) imm_expr.X_add_number);
14491 imm_expr.X_add_number &= 0x7ff;
14493 ip->insn_opcode |= imm_expr.X_add_number;
14494 imm_expr.X_op = O_absent;
14504 /* Args don't match. */
14505 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
14506 strcmp (insn->name, insn[1].name) == 0)
14513 insn_error = _("illegal operands");
14519 /* This structure holds information we know about a mips16 immediate
14522 struct mips16_immed_operand
14524 /* The type code used in the argument string in the opcode table. */
14526 /* The number of bits in the short form of the opcode. */
14528 /* The number of bits in the extended form of the opcode. */
14530 /* The amount by which the short form is shifted when it is used;
14531 for example, the sw instruction has a shift count of 2. */
14533 /* The amount by which the short form is shifted when it is stored
14534 into the instruction code. */
14536 /* Non-zero if the short form is unsigned. */
14538 /* Non-zero if the extended form is unsigned. */
14540 /* Non-zero if the value is PC relative. */
14544 /* The mips16 immediate operand types. */
14546 static const struct mips16_immed_operand mips16_immed_operands[] =
14548 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14549 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14550 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
14551 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
14552 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
14553 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
14554 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
14555 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
14556 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
14557 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
14558 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
14559 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
14560 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
14561 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
14562 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
14563 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
14564 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14565 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
14566 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
14567 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
14568 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
14571 #define MIPS16_NUM_IMMED \
14572 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
14574 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14575 NBITS is the number of significant bits in VAL. */
14577 static unsigned long
14578 mips16_immed_extend (offsetT val, unsigned int nbits)
14583 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14586 else if (nbits == 15)
14588 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14593 extval = ((val & 0x1f) << 6) | (val & 0x20);
14596 return (extval << 16) | val;
14599 /* Install immediate value VAL into MIPS16 instruction *INSN,
14600 extending it if necessary. The instruction in *INSN may
14601 already be extended.
14603 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14604 if none. In the former case, VAL is a 16-bit number with no
14605 defined signedness.
14607 TYPE is the type of the immediate field. USER_INSN_LENGTH
14608 is the length that the user requested, or 0 if none. */
14611 mips16_immed (char *file, unsigned int line, int type,
14612 bfd_reloc_code_real_type reloc, offsetT val,
14613 unsigned int user_insn_length, unsigned long *insn)
14615 const struct mips16_immed_operand *op;
14616 int mintiny, maxtiny;
14618 op = mips16_immed_operands;
14619 while (op->type != type)
14622 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14627 if (type == '<' || type == '>' || type == '[' || type == ']')
14630 maxtiny = 1 << op->nbits;
14635 maxtiny = (1 << op->nbits) - 1;
14637 if (reloc != BFD_RELOC_UNUSED)
14642 mintiny = - (1 << (op->nbits - 1));
14643 maxtiny = (1 << (op->nbits - 1)) - 1;
14644 if (reloc != BFD_RELOC_UNUSED)
14645 val = SEXT_16BIT (val);
14648 /* Branch offsets have an implicit 0 in the lowest bit. */
14649 if (type == 'p' || type == 'q')
14652 if ((val & ((1 << op->shift) - 1)) != 0
14653 || val < (mintiny << op->shift)
14654 || val > (maxtiny << op->shift))
14656 /* We need an extended instruction. */
14657 if (user_insn_length == 2)
14658 as_bad_where (file, line, _("invalid unextended operand value"));
14660 *insn |= MIPS16_EXTEND;
14662 else if (user_insn_length == 4)
14664 /* The operand doesn't force an unextended instruction to be extended.
14665 Warn if the user wanted an extended instruction anyway. */
14666 *insn |= MIPS16_EXTEND;
14667 as_warn_where (file, line,
14668 _("extended operand requested but not required"));
14671 if (mips16_opcode_length (*insn) == 2)
14675 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
14676 insnval <<= op->op_shift;
14681 long minext, maxext;
14683 if (reloc == BFD_RELOC_UNUSED)
14688 maxext = (1 << op->extbits) - 1;
14692 minext = - (1 << (op->extbits - 1));
14693 maxext = (1 << (op->extbits - 1)) - 1;
14695 if (val < minext || val > maxext)
14696 as_bad_where (file, line,
14697 _("operand value out of range for instruction"));
14700 *insn |= mips16_immed_extend (val, op->extbits);
14704 struct percent_op_match
14707 bfd_reloc_code_real_type reloc;
14710 static const struct percent_op_match mips_percent_op[] =
14712 {"%lo", BFD_RELOC_LO16},
14713 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14714 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14715 {"%call16", BFD_RELOC_MIPS_CALL16},
14716 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14717 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14718 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14719 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14720 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14721 {"%got", BFD_RELOC_MIPS_GOT16},
14722 {"%gp_rel", BFD_RELOC_GPREL16},
14723 {"%half", BFD_RELOC_16},
14724 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14725 {"%higher", BFD_RELOC_MIPS_HIGHER},
14726 {"%neg", BFD_RELOC_MIPS_SUB},
14727 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14728 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14729 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14730 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14731 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14732 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14733 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14734 {"%hi", BFD_RELOC_HI16_S}
14737 static const struct percent_op_match mips16_percent_op[] =
14739 {"%lo", BFD_RELOC_MIPS16_LO16},
14740 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14741 {"%got", BFD_RELOC_MIPS16_GOT16},
14742 {"%call16", BFD_RELOC_MIPS16_CALL16},
14743 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14744 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14745 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14746 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14747 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14748 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14749 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14750 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14754 /* Return true if *STR points to a relocation operator. When returning true,
14755 move *STR over the operator and store its relocation code in *RELOC.
14756 Leave both *STR and *RELOC alone when returning false. */
14759 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14761 const struct percent_op_match *percent_op;
14764 if (mips_opts.mips16)
14766 percent_op = mips16_percent_op;
14767 limit = ARRAY_SIZE (mips16_percent_op);
14771 percent_op = mips_percent_op;
14772 limit = ARRAY_SIZE (mips_percent_op);
14775 for (i = 0; i < limit; i++)
14776 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14778 int len = strlen (percent_op[i].str);
14780 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14783 *str += strlen (percent_op[i].str);
14784 *reloc = percent_op[i].reloc;
14786 /* Check whether the output BFD supports this relocation.
14787 If not, issue an error and fall back on something safe. */
14788 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14790 as_bad (_("relocation %s isn't supported by the current ABI"),
14791 percent_op[i].str);
14792 *reloc = BFD_RELOC_UNUSED;
14800 /* Parse string STR as a 16-bit relocatable operand. Store the
14801 expression in *EP and the relocations in the array starting
14802 at RELOC. Return the number of relocation operators used.
14804 On exit, EXPR_END points to the first character after the expression. */
14807 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14810 bfd_reloc_code_real_type reversed_reloc[3];
14811 size_t reloc_index, i;
14812 int crux_depth, str_depth;
14815 /* Search for the start of the main expression, recoding relocations
14816 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14817 of the main expression and with CRUX_DEPTH containing the number
14818 of open brackets at that point. */
14825 crux_depth = str_depth;
14827 /* Skip over whitespace and brackets, keeping count of the number
14829 while (*str == ' ' || *str == '\t' || *str == '(')
14834 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14835 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14837 my_getExpression (ep, crux);
14840 /* Match every open bracket. */
14841 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14845 if (crux_depth > 0)
14846 as_bad (_("unclosed '('"));
14850 if (reloc_index != 0)
14852 prev_reloc_op_frag = frag_now;
14853 for (i = 0; i < reloc_index; i++)
14854 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14857 return reloc_index;
14861 my_getExpression (expressionS *ep, char *str)
14865 save_in = input_line_pointer;
14866 input_line_pointer = str;
14868 expr_end = input_line_pointer;
14869 input_line_pointer = save_in;
14873 md_atof (int type, char *litP, int *sizeP)
14875 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14879 md_number_to_chars (char *buf, valueT val, int n)
14881 if (target_big_endian)
14882 number_to_chars_bigendian (buf, val, n);
14884 number_to_chars_littleendian (buf, val, n);
14887 static int support_64bit_objects(void)
14889 const char **list, **l;
14892 list = bfd_target_list ();
14893 for (l = list; *l != NULL; l++)
14894 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14895 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14897 yes = (*l != NULL);
14902 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14903 NEW_VALUE. Warn if another value was already specified. Note:
14904 we have to defer parsing the -march and -mtune arguments in order
14905 to handle 'from-abi' correctly, since the ABI might be specified
14906 in a later argument. */
14909 mips_set_option_string (const char **string_ptr, const char *new_value)
14911 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14912 as_warn (_("A different %s was already specified, is now %s"),
14913 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14916 *string_ptr = new_value;
14920 md_parse_option (int c, char *arg)
14924 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14925 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14927 file_ase_explicit |= mips_set_ase (&mips_ases[i],
14928 c == mips_ases[i].option_on);
14934 case OPTION_CONSTRUCT_FLOATS:
14935 mips_disable_float_construction = 0;
14938 case OPTION_NO_CONSTRUCT_FLOATS:
14939 mips_disable_float_construction = 1;
14951 target_big_endian = 1;
14955 target_big_endian = 0;
14961 else if (arg[0] == '0')
14963 else if (arg[0] == '1')
14973 mips_debug = atoi (arg);
14977 file_mips_isa = ISA_MIPS1;
14981 file_mips_isa = ISA_MIPS2;
14985 file_mips_isa = ISA_MIPS3;
14989 file_mips_isa = ISA_MIPS4;
14993 file_mips_isa = ISA_MIPS5;
14996 case OPTION_MIPS32:
14997 file_mips_isa = ISA_MIPS32;
15000 case OPTION_MIPS32R2:
15001 file_mips_isa = ISA_MIPS32R2;
15004 case OPTION_MIPS64R2:
15005 file_mips_isa = ISA_MIPS64R2;
15008 case OPTION_MIPS64:
15009 file_mips_isa = ISA_MIPS64;
15013 mips_set_option_string (&mips_tune_string, arg);
15017 mips_set_option_string (&mips_arch_string, arg);
15021 mips_set_option_string (&mips_arch_string, "4650");
15022 mips_set_option_string (&mips_tune_string, "4650");
15025 case OPTION_NO_M4650:
15029 mips_set_option_string (&mips_arch_string, "4010");
15030 mips_set_option_string (&mips_tune_string, "4010");
15033 case OPTION_NO_M4010:
15037 mips_set_option_string (&mips_arch_string, "4100");
15038 mips_set_option_string (&mips_tune_string, "4100");
15041 case OPTION_NO_M4100:
15045 mips_set_option_string (&mips_arch_string, "3900");
15046 mips_set_option_string (&mips_tune_string, "3900");
15049 case OPTION_NO_M3900:
15052 case OPTION_MICROMIPS:
15053 if (mips_opts.mips16 == 1)
15055 as_bad (_("-mmicromips cannot be used with -mips16"));
15058 mips_opts.micromips = 1;
15059 mips_no_prev_insn ();
15062 case OPTION_NO_MICROMIPS:
15063 mips_opts.micromips = 0;
15064 mips_no_prev_insn ();
15067 case OPTION_MIPS16:
15068 if (mips_opts.micromips == 1)
15070 as_bad (_("-mips16 cannot be used with -micromips"));
15073 mips_opts.mips16 = 1;
15074 mips_no_prev_insn ();
15077 case OPTION_NO_MIPS16:
15078 mips_opts.mips16 = 0;
15079 mips_no_prev_insn ();
15082 case OPTION_FIX_24K:
15086 case OPTION_NO_FIX_24K:
15090 case OPTION_FIX_LOONGSON2F_JUMP:
15091 mips_fix_loongson2f_jump = TRUE;
15094 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15095 mips_fix_loongson2f_jump = FALSE;
15098 case OPTION_FIX_LOONGSON2F_NOP:
15099 mips_fix_loongson2f_nop = TRUE;
15102 case OPTION_NO_FIX_LOONGSON2F_NOP:
15103 mips_fix_loongson2f_nop = FALSE;
15106 case OPTION_FIX_VR4120:
15107 mips_fix_vr4120 = 1;
15110 case OPTION_NO_FIX_VR4120:
15111 mips_fix_vr4120 = 0;
15114 case OPTION_FIX_VR4130:
15115 mips_fix_vr4130 = 1;
15118 case OPTION_NO_FIX_VR4130:
15119 mips_fix_vr4130 = 0;
15122 case OPTION_FIX_CN63XXP1:
15123 mips_fix_cn63xxp1 = TRUE;
15126 case OPTION_NO_FIX_CN63XXP1:
15127 mips_fix_cn63xxp1 = FALSE;
15130 case OPTION_RELAX_BRANCH:
15131 mips_relax_branch = 1;
15134 case OPTION_NO_RELAX_BRANCH:
15135 mips_relax_branch = 0;
15138 case OPTION_MSHARED:
15139 mips_in_shared = TRUE;
15142 case OPTION_MNO_SHARED:
15143 mips_in_shared = FALSE;
15146 case OPTION_MSYM32:
15147 mips_opts.sym32 = TRUE;
15150 case OPTION_MNO_SYM32:
15151 mips_opts.sym32 = FALSE;
15154 /* When generating ELF code, we permit -KPIC and -call_shared to
15155 select SVR4_PIC, and -non_shared to select no PIC. This is
15156 intended to be compatible with Irix 5. */
15157 case OPTION_CALL_SHARED:
15158 mips_pic = SVR4_PIC;
15159 mips_abicalls = TRUE;
15162 case OPTION_CALL_NONPIC:
15164 mips_abicalls = TRUE;
15167 case OPTION_NON_SHARED:
15169 mips_abicalls = FALSE;
15172 /* The -xgot option tells the assembler to use 32 bit offsets
15173 when accessing the got in SVR4_PIC mode. It is for Irix
15180 g_switch_value = atoi (arg);
15184 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15187 mips_abi = O32_ABI;
15191 mips_abi = N32_ABI;
15195 mips_abi = N64_ABI;
15196 if (!support_64bit_objects())
15197 as_fatal (_("No compiled in support for 64 bit object file format"));
15201 file_mips_gp32 = 1;
15205 file_mips_gp32 = 0;
15209 file_mips_fp32 = 1;
15213 file_mips_fp32 = 0;
15216 case OPTION_SINGLE_FLOAT:
15217 file_mips_single_float = 1;
15220 case OPTION_DOUBLE_FLOAT:
15221 file_mips_single_float = 0;
15224 case OPTION_SOFT_FLOAT:
15225 file_mips_soft_float = 1;
15228 case OPTION_HARD_FLOAT:
15229 file_mips_soft_float = 0;
15233 if (strcmp (arg, "32") == 0)
15234 mips_abi = O32_ABI;
15235 else if (strcmp (arg, "o64") == 0)
15236 mips_abi = O64_ABI;
15237 else if (strcmp (arg, "n32") == 0)
15238 mips_abi = N32_ABI;
15239 else if (strcmp (arg, "64") == 0)
15241 mips_abi = N64_ABI;
15242 if (! support_64bit_objects())
15243 as_fatal (_("No compiled in support for 64 bit object file "
15246 else if (strcmp (arg, "eabi") == 0)
15247 mips_abi = EABI_ABI;
15250 as_fatal (_("invalid abi -mabi=%s"), arg);
15255 case OPTION_M7000_HILO_FIX:
15256 mips_7000_hilo_fix = TRUE;
15259 case OPTION_MNO_7000_HILO_FIX:
15260 mips_7000_hilo_fix = FALSE;
15263 case OPTION_MDEBUG:
15264 mips_flag_mdebug = TRUE;
15267 case OPTION_NO_MDEBUG:
15268 mips_flag_mdebug = FALSE;
15272 mips_flag_pdr = TRUE;
15275 case OPTION_NO_PDR:
15276 mips_flag_pdr = FALSE;
15279 case OPTION_MVXWORKS_PIC:
15280 mips_pic = VXWORKS_PIC;
15287 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15292 /* Set up globals to generate code for the ISA or processor
15293 described by INFO. */
15296 mips_set_architecture (const struct mips_cpu_info *info)
15300 file_mips_arch = info->cpu;
15301 mips_opts.arch = info->cpu;
15302 mips_opts.isa = info->isa;
15307 /* Likewise for tuning. */
15310 mips_set_tune (const struct mips_cpu_info *info)
15313 mips_tune = info->cpu;
15318 mips_after_parse_args (void)
15320 const struct mips_cpu_info *arch_info = 0;
15321 const struct mips_cpu_info *tune_info = 0;
15323 /* GP relative stuff not working for PE */
15324 if (strncmp (TARGET_OS, "pe", 2) == 0)
15326 if (g_switch_seen && g_switch_value != 0)
15327 as_bad (_("-G not supported in this configuration."));
15328 g_switch_value = 0;
15331 if (mips_abi == NO_ABI)
15332 mips_abi = MIPS_DEFAULT_ABI;
15334 /* The following code determines the architecture and register size.
15335 Similar code was added to GCC 3.3 (see override_options() in
15336 config/mips/mips.c). The GAS and GCC code should be kept in sync
15337 as much as possible. */
15339 if (mips_arch_string != 0)
15340 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15342 if (file_mips_isa != ISA_UNKNOWN)
15344 /* Handle -mipsN. At this point, file_mips_isa contains the
15345 ISA level specified by -mipsN, while arch_info->isa contains
15346 the -march selection (if any). */
15347 if (arch_info != 0)
15349 /* -march takes precedence over -mipsN, since it is more descriptive.
15350 There's no harm in specifying both as long as the ISA levels
15352 if (file_mips_isa != arch_info->isa)
15353 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
15354 mips_cpu_info_from_isa (file_mips_isa)->name,
15355 mips_cpu_info_from_isa (arch_info->isa)->name);
15358 arch_info = mips_cpu_info_from_isa (file_mips_isa);
15361 if (arch_info == 0)
15363 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15364 gas_assert (arch_info);
15367 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15368 as_bad (_("-march=%s is not compatible with the selected ABI"),
15371 mips_set_architecture (arch_info);
15373 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
15374 if (mips_tune_string != 0)
15375 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15377 if (tune_info == 0)
15378 mips_set_tune (arch_info);
15380 mips_set_tune (tune_info);
15382 if (file_mips_gp32 >= 0)
15384 /* The user specified the size of the integer registers. Make sure
15385 it agrees with the ABI and ISA. */
15386 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
15387 as_bad (_("-mgp64 used with a 32-bit processor"));
15388 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
15389 as_bad (_("-mgp32 used with a 64-bit ABI"));
15390 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
15391 as_bad (_("-mgp64 used with a 32-bit ABI"));
15395 /* Infer the integer register size from the ABI and processor.
15396 Restrict ourselves to 32-bit registers if that's all the
15397 processor has, or if the ABI cannot handle 64-bit registers. */
15398 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
15399 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
15402 switch (file_mips_fp32)
15406 /* No user specified float register size.
15407 ??? GAS treats single-float processors as though they had 64-bit
15408 float registers (although it complains when double-precision
15409 instructions are used). As things stand, saying they have 32-bit
15410 registers would lead to spurious "register must be even" messages.
15411 So here we assume float registers are never smaller than the
15413 if (file_mips_gp32 == 0)
15414 /* 64-bit integer registers implies 64-bit float registers. */
15415 file_mips_fp32 = 0;
15416 else if ((mips_opts.ase & FP64_ASES)
15417 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
15418 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
15419 file_mips_fp32 = 0;
15421 /* 32-bit float registers. */
15422 file_mips_fp32 = 1;
15425 /* The user specified the size of the float registers. Check if it
15426 agrees with the ABI and ISA. */
15428 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
15429 as_bad (_("-mfp64 used with a 32-bit fpu"));
15430 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
15431 && !ISA_HAS_MXHC1 (mips_opts.isa))
15432 as_warn (_("-mfp64 used with a 32-bit ABI"));
15435 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15436 as_warn (_("-mfp32 used with a 64-bit ABI"));
15440 /* End of GCC-shared inference code. */
15442 /* This flag is set when we have a 64-bit capable CPU but use only
15443 32-bit wide registers. Note that EABI does not use it. */
15444 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
15445 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
15446 || mips_abi == O32_ABI))
15447 mips_32bitmode = 1;
15449 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
15450 as_bad (_("trap exception not supported at ISA 1"));
15452 /* If the selected architecture includes support for ASEs, enable
15453 generation of code for them. */
15454 if (mips_opts.mips16 == -1)
15455 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
15456 if (mips_opts.micromips == -1)
15457 mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
15459 /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
15460 ASEs from being selected implicitly. */
15461 if (file_mips_fp32 == 1)
15462 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
15464 /* If the user didn't explicitly select or deselect a particular ASE,
15465 use the default setting for the CPU. */
15466 mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
15468 file_mips_isa = mips_opts.isa;
15469 file_ase = mips_opts.ase;
15470 mips_opts.gp32 = file_mips_gp32;
15471 mips_opts.fp32 = file_mips_fp32;
15472 mips_opts.soft_float = file_mips_soft_float;
15473 mips_opts.single_float = file_mips_single_float;
15475 mips_check_isa_supports_ases ();
15477 if (mips_flag_mdebug < 0)
15478 mips_flag_mdebug = 0;
15482 mips_init_after_args (void)
15484 /* initialize opcodes */
15485 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15486 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15490 md_pcrel_from (fixS *fixP)
15492 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15493 switch (fixP->fx_r_type)
15495 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15496 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15497 /* Return the address of the delay slot. */
15500 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15501 case BFD_RELOC_MICROMIPS_JMP:
15502 case BFD_RELOC_16_PCREL_S2:
15503 case BFD_RELOC_MIPS_JMP:
15504 /* Return the address of the delay slot. */
15507 case BFD_RELOC_32_PCREL:
15511 /* We have no relocation type for PC relative MIPS16 instructions. */
15512 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
15513 as_bad_where (fixP->fx_file, fixP->fx_line,
15514 _("PC relative MIPS16 instruction references a different section"));
15519 /* This is called before the symbol table is processed. In order to
15520 work with gcc when using mips-tfile, we must keep all local labels.
15521 However, in other cases, we want to discard them. If we were
15522 called with -g, but we didn't see any debugging information, it may
15523 mean that gcc is smuggling debugging information through to
15524 mips-tfile, in which case we must generate all local labels. */
15527 mips_frob_file_before_adjust (void)
15529 #ifndef NO_ECOFF_DEBUGGING
15530 if (ECOFF_DEBUGGING
15532 && ! ecoff_debugging_seen)
15533 flag_keep_locals = 1;
15537 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15538 the corresponding LO16 reloc. This is called before md_apply_fix and
15539 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15540 relocation operators.
15542 For our purposes, a %lo() expression matches a %got() or %hi()
15545 (a) it refers to the same symbol; and
15546 (b) the offset applied in the %lo() expression is no lower than
15547 the offset applied in the %got() or %hi().
15549 (b) allows us to cope with code like:
15552 lh $4,%lo(foo+2)($4)
15554 ...which is legal on RELA targets, and has a well-defined behaviour
15555 if the user knows that adding 2 to "foo" will not induce a carry to
15558 When several %lo()s match a particular %got() or %hi(), we use the
15559 following rules to distinguish them:
15561 (1) %lo()s with smaller offsets are a better match than %lo()s with
15564 (2) %lo()s with no matching %got() or %hi() are better than those
15565 that already have a matching %got() or %hi().
15567 (3) later %lo()s are better than earlier %lo()s.
15569 These rules are applied in order.
15571 (1) means, among other things, that %lo()s with identical offsets are
15572 chosen if they exist.
15574 (2) means that we won't associate several high-part relocations with
15575 the same low-part relocation unless there's no alternative. Having
15576 several high parts for the same low part is a GNU extension; this rule
15577 allows careful users to avoid it.
15579 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15580 with the last high-part relocation being at the front of the list.
15581 It therefore makes sense to choose the last matching low-part
15582 relocation, all other things being equal. It's also easier
15583 to code that way. */
15586 mips_frob_file (void)
15588 struct mips_hi_fixup *l;
15589 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15591 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15593 segment_info_type *seginfo;
15594 bfd_boolean matched_lo_p;
15595 fixS **hi_pos, **lo_pos, **pos;
15597 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15599 /* If a GOT16 relocation turns out to be against a global symbol,
15600 there isn't supposed to be a matching LO. Ignore %gots against
15601 constants; we'll report an error for those later. */
15602 if (got16_reloc_p (l->fixp->fx_r_type)
15603 && !(l->fixp->fx_addsy
15604 && pic_need_relax (l->fixp->fx_addsy, l->seg)))
15607 /* Check quickly whether the next fixup happens to be a matching %lo. */
15608 if (fixup_has_matching_lo_p (l->fixp))
15611 seginfo = seg_info (l->seg);
15613 /* Set HI_POS to the position of this relocation in the chain.
15614 Set LO_POS to the position of the chosen low-part relocation.
15615 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15616 relocation that matches an immediately-preceding high-part
15620 matched_lo_p = FALSE;
15621 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15623 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15625 if (*pos == l->fixp)
15628 if ((*pos)->fx_r_type == looking_for_rtype
15629 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15630 && (*pos)->fx_offset >= l->fixp->fx_offset
15632 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15634 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15637 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15638 && fixup_has_matching_lo_p (*pos));
15641 /* If we found a match, remove the high-part relocation from its
15642 current position and insert it before the low-part relocation.
15643 Make the offsets match so that fixup_has_matching_lo_p()
15646 We don't warn about unmatched high-part relocations since some
15647 versions of gcc have been known to emit dead "lui ...%hi(...)"
15649 if (lo_pos != NULL)
15651 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15652 if (l->fixp->fx_next != *lo_pos)
15654 *hi_pos = l->fixp->fx_next;
15655 l->fixp->fx_next = *lo_pos;
15663 mips_force_relocation (fixS *fixp)
15665 if (generic_force_reloc (fixp))
15668 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15669 so that the linker relaxation can update targets. */
15670 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15671 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15672 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15678 /* Read the instruction associated with RELOC from BUF. */
15680 static unsigned int
15681 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15683 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15684 return read_compressed_insn (buf, 4);
15686 return read_insn (buf);
15689 /* Write instruction INSN to BUF, given that it has been relocated
15693 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15694 unsigned long insn)
15696 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15697 write_compressed_insn (buf, insn, 4);
15699 write_insn (buf, insn);
15702 /* Apply a fixup to the object file. */
15705 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15708 unsigned long insn;
15709 reloc_howto_type *howto;
15711 /* We ignore generic BFD relocations we don't know about. */
15712 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15716 gas_assert (fixP->fx_size == 2
15717 || fixP->fx_size == 4
15718 || fixP->fx_r_type == BFD_RELOC_16
15719 || fixP->fx_r_type == BFD_RELOC_64
15720 || fixP->fx_r_type == BFD_RELOC_CTOR
15721 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15722 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15723 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15724 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15725 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
15727 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15729 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
15730 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15731 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15732 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
15733 || fixP->fx_r_type == BFD_RELOC_32_PCREL);
15735 /* Don't treat parts of a composite relocation as done. There are two
15738 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15739 should nevertheless be emitted if the first part is.
15741 (2) In normal usage, composite relocations are never assembly-time
15742 constants. The easiest way of dealing with the pathological
15743 exceptions is to generate a relocation against STN_UNDEF and
15744 leave everything up to the linker. */
15745 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15748 switch (fixP->fx_r_type)
15750 case BFD_RELOC_MIPS_TLS_GD:
15751 case BFD_RELOC_MIPS_TLS_LDM:
15752 case BFD_RELOC_MIPS_TLS_DTPREL32:
15753 case BFD_RELOC_MIPS_TLS_DTPREL64:
15754 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15755 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15756 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15757 case BFD_RELOC_MIPS_TLS_TPREL32:
15758 case BFD_RELOC_MIPS_TLS_TPREL64:
15759 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15760 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
15761 case BFD_RELOC_MICROMIPS_TLS_GD:
15762 case BFD_RELOC_MICROMIPS_TLS_LDM:
15763 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
15764 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
15765 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
15766 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
15767 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
15768 case BFD_RELOC_MIPS16_TLS_GD:
15769 case BFD_RELOC_MIPS16_TLS_LDM:
15770 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
15771 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
15772 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
15773 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
15774 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
15775 if (!fixP->fx_addsy)
15777 as_bad_where (fixP->fx_file, fixP->fx_line,
15778 _("TLS relocation against a constant"));
15781 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15784 case BFD_RELOC_MIPS_JMP:
15785 case BFD_RELOC_MIPS_SHIFT5:
15786 case BFD_RELOC_MIPS_SHIFT6:
15787 case BFD_RELOC_MIPS_GOT_DISP:
15788 case BFD_RELOC_MIPS_GOT_PAGE:
15789 case BFD_RELOC_MIPS_GOT_OFST:
15790 case BFD_RELOC_MIPS_SUB:
15791 case BFD_RELOC_MIPS_INSERT_A:
15792 case BFD_RELOC_MIPS_INSERT_B:
15793 case BFD_RELOC_MIPS_DELETE:
15794 case BFD_RELOC_MIPS_HIGHEST:
15795 case BFD_RELOC_MIPS_HIGHER:
15796 case BFD_RELOC_MIPS_SCN_DISP:
15797 case BFD_RELOC_MIPS_REL16:
15798 case BFD_RELOC_MIPS_RELGOT:
15799 case BFD_RELOC_MIPS_JALR:
15800 case BFD_RELOC_HI16:
15801 case BFD_RELOC_HI16_S:
15802 case BFD_RELOC_LO16:
15803 case BFD_RELOC_GPREL16:
15804 case BFD_RELOC_MIPS_LITERAL:
15805 case BFD_RELOC_MIPS_CALL16:
15806 case BFD_RELOC_MIPS_GOT16:
15807 case BFD_RELOC_GPREL32:
15808 case BFD_RELOC_MIPS_GOT_HI16:
15809 case BFD_RELOC_MIPS_GOT_LO16:
15810 case BFD_RELOC_MIPS_CALL_HI16:
15811 case BFD_RELOC_MIPS_CALL_LO16:
15812 case BFD_RELOC_MIPS16_GPREL:
15813 case BFD_RELOC_MIPS16_GOT16:
15814 case BFD_RELOC_MIPS16_CALL16:
15815 case BFD_RELOC_MIPS16_HI16:
15816 case BFD_RELOC_MIPS16_HI16_S:
15817 case BFD_RELOC_MIPS16_LO16:
15818 case BFD_RELOC_MIPS16_JMP:
15819 case BFD_RELOC_MICROMIPS_JMP:
15820 case BFD_RELOC_MICROMIPS_GOT_DISP:
15821 case BFD_RELOC_MICROMIPS_GOT_PAGE:
15822 case BFD_RELOC_MICROMIPS_GOT_OFST:
15823 case BFD_RELOC_MICROMIPS_SUB:
15824 case BFD_RELOC_MICROMIPS_HIGHEST:
15825 case BFD_RELOC_MICROMIPS_HIGHER:
15826 case BFD_RELOC_MICROMIPS_SCN_DISP:
15827 case BFD_RELOC_MICROMIPS_JALR:
15828 case BFD_RELOC_MICROMIPS_HI16:
15829 case BFD_RELOC_MICROMIPS_HI16_S:
15830 case BFD_RELOC_MICROMIPS_LO16:
15831 case BFD_RELOC_MICROMIPS_GPREL16:
15832 case BFD_RELOC_MICROMIPS_LITERAL:
15833 case BFD_RELOC_MICROMIPS_CALL16:
15834 case BFD_RELOC_MICROMIPS_GOT16:
15835 case BFD_RELOC_MICROMIPS_GOT_HI16:
15836 case BFD_RELOC_MICROMIPS_GOT_LO16:
15837 case BFD_RELOC_MICROMIPS_CALL_HI16:
15838 case BFD_RELOC_MICROMIPS_CALL_LO16:
15839 case BFD_RELOC_MIPS_EH:
15844 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
15846 insn = read_reloc_insn (buf, fixP->fx_r_type);
15847 if (mips16_reloc_p (fixP->fx_r_type))
15848 insn |= mips16_immed_extend (value, 16);
15850 insn |= (value & 0xffff);
15851 write_reloc_insn (buf, fixP->fx_r_type, insn);
15854 as_bad_where (fixP->fx_file, fixP->fx_line,
15855 _("Unsupported constant in relocation"));
15860 /* This is handled like BFD_RELOC_32, but we output a sign
15861 extended value if we are only 32 bits. */
15864 if (8 <= sizeof (valueT))
15865 md_number_to_chars (buf, *valP, 8);
15870 if ((*valP & 0x80000000) != 0)
15874 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
15875 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
15880 case BFD_RELOC_RVA:
15882 case BFD_RELOC_32_PCREL:
15884 /* If we are deleting this reloc entry, we must fill in the
15885 value now. This can happen if we have a .word which is not
15886 resolved when it appears but is later defined. */
15888 md_number_to_chars (buf, *valP, fixP->fx_size);
15891 case BFD_RELOC_16_PCREL_S2:
15892 if ((*valP & 0x3) != 0)
15893 as_bad_where (fixP->fx_file, fixP->fx_line,
15894 _("Branch to misaligned address (%lx)"), (long) *valP);
15896 /* We need to save the bits in the instruction since fixup_segment()
15897 might be deleting the relocation entry (i.e., a branch within
15898 the current segment). */
15899 if (! fixP->fx_done)
15902 /* Update old instruction data. */
15903 insn = read_insn (buf);
15905 if (*valP + 0x20000 <= 0x3ffff)
15907 insn |= (*valP >> 2) & 0xffff;
15908 write_insn (buf, insn);
15910 else if (mips_pic == NO_PIC
15912 && fixP->fx_frag->fr_address >= text_section->vma
15913 && (fixP->fx_frag->fr_address
15914 < text_section->vma + bfd_get_section_size (text_section))
15915 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
15916 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
15917 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
15919 /* The branch offset is too large. If this is an
15920 unconditional branch, and we are not generating PIC code,
15921 we can convert it to an absolute jump instruction. */
15922 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
15923 insn = 0x0c000000; /* jal */
15925 insn = 0x08000000; /* j */
15926 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
15928 fixP->fx_addsy = section_symbol (text_section);
15929 *valP += md_pcrel_from (fixP);
15930 write_insn (buf, insn);
15934 /* If we got here, we have branch-relaxation disabled,
15935 and there's nothing we can do to fix this instruction
15936 without turning it into a longer sequence. */
15937 as_bad_where (fixP->fx_file, fixP->fx_line,
15938 _("Branch out of range"));
15942 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15943 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15944 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15945 /* We adjust the offset back to even. */
15946 if ((*valP & 0x1) != 0)
15949 if (! fixP->fx_done)
15952 /* Should never visit here, because we keep the relocation. */
15956 case BFD_RELOC_VTABLE_INHERIT:
15959 && !S_IS_DEFINED (fixP->fx_addsy)
15960 && !S_IS_WEAK (fixP->fx_addsy))
15961 S_SET_WEAK (fixP->fx_addsy);
15964 case BFD_RELOC_VTABLE_ENTRY:
15972 /* Remember value for tc_gen_reloc. */
15973 fixP->fx_addnumber = *valP;
15983 name = input_line_pointer;
15984 c = get_symbol_end ();
15985 p = (symbolS *) symbol_find_or_make (name);
15986 *input_line_pointer = c;
15990 /* Align the current frag to a given power of two. If a particular
15991 fill byte should be used, FILL points to an integer that contains
15992 that byte, otherwise FILL is null.
15994 This function used to have the comment:
15996 The MIPS assembler also automatically adjusts any preceding label.
15998 The implementation therefore applied the adjustment to a maximum of
15999 one label. However, other label adjustments are applied to batches
16000 of labels, and adjusting just one caused problems when new labels
16001 were added for the sake of debugging or unwind information.
16002 We therefore adjust all preceding labels (given as LABELS) instead. */
16005 mips_align (int to, int *fill, struct insn_label_list *labels)
16007 mips_emit_delays ();
16008 mips_record_compressed_mode ();
16009 if (fill == NULL && subseg_text_p (now_seg))
16010 frag_align_code (to, 0);
16012 frag_align (to, fill ? *fill : 0, 0);
16013 record_alignment (now_seg, to);
16014 mips_move_labels (labels, FALSE);
16017 /* Align to a given power of two. .align 0 turns off the automatic
16018 alignment used by the data creating pseudo-ops. */
16021 s_align (int x ATTRIBUTE_UNUSED)
16023 int temp, fill_value, *fill_ptr;
16024 long max_alignment = 28;
16026 /* o Note that the assembler pulls down any immediately preceding label
16027 to the aligned address.
16028 o It's not documented but auto alignment is reinstated by
16029 a .align pseudo instruction.
16030 o Note also that after auto alignment is turned off the mips assembler
16031 issues an error on attempt to assemble an improperly aligned data item.
16034 temp = get_absolute_expression ();
16035 if (temp > max_alignment)
16036 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
16039 as_warn (_("Alignment negative: 0 assumed."));
16042 if (*input_line_pointer == ',')
16044 ++input_line_pointer;
16045 fill_value = get_absolute_expression ();
16046 fill_ptr = &fill_value;
16052 segment_info_type *si = seg_info (now_seg);
16053 struct insn_label_list *l = si->label_list;
16054 /* Auto alignment should be switched on by next section change. */
16056 mips_align (temp, fill_ptr, l);
16063 demand_empty_rest_of_line ();
16067 s_change_sec (int sec)
16071 /* The ELF backend needs to know that we are changing sections, so
16072 that .previous works correctly. We could do something like check
16073 for an obj_section_change_hook macro, but that might be confusing
16074 as it would not be appropriate to use it in the section changing
16075 functions in read.c, since obj-elf.c intercepts those. FIXME:
16076 This should be cleaner, somehow. */
16077 obj_elf_section_change_hook ();
16079 mips_emit_delays ();
16090 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16091 demand_empty_rest_of_line ();
16095 seg = subseg_new (RDATA_SECTION_NAME,
16096 (subsegT) get_absolute_expression ());
16097 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
16098 | SEC_READONLY | SEC_RELOC
16100 if (strncmp (TARGET_OS, "elf", 3) != 0)
16101 record_alignment (seg, 4);
16102 demand_empty_rest_of_line ();
16106 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16107 bfd_set_section_flags (stdoutput, seg,
16108 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
16109 if (strncmp (TARGET_OS, "elf", 3) != 0)
16110 record_alignment (seg, 4);
16111 demand_empty_rest_of_line ();
16115 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16116 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
16117 if (strncmp (TARGET_OS, "elf", 3) != 0)
16118 record_alignment (seg, 4);
16119 demand_empty_rest_of_line ();
16127 s_change_section (int ignore ATTRIBUTE_UNUSED)
16129 char *section_name;
16134 int section_entry_size;
16135 int section_alignment;
16137 section_name = input_line_pointer;
16138 c = get_symbol_end ();
16140 next_c = *(input_line_pointer + 1);
16142 /* Do we have .section Name<,"flags">? */
16143 if (c != ',' || (c == ',' && next_c == '"'))
16145 /* just after name is now '\0'. */
16146 *input_line_pointer = c;
16147 input_line_pointer = section_name;
16148 obj_elf_section (ignore);
16151 input_line_pointer++;
16153 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16155 section_type = get_absolute_expression ();
16158 if (*input_line_pointer++ == ',')
16159 section_flag = get_absolute_expression ();
16162 if (*input_line_pointer++ == ',')
16163 section_entry_size = get_absolute_expression ();
16165 section_entry_size = 0;
16166 if (*input_line_pointer++ == ',')
16167 section_alignment = get_absolute_expression ();
16169 section_alignment = 0;
16170 /* FIXME: really ignore? */
16171 (void) section_alignment;
16173 section_name = xstrdup (section_name);
16175 /* When using the generic form of .section (as implemented by obj-elf.c),
16176 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16177 traditionally had to fall back on the more common @progbits instead.
16179 There's nothing really harmful in this, since bfd will correct
16180 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16181 means that, for backwards compatibility, the special_section entries
16182 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16184 Even so, we shouldn't force users of the MIPS .section syntax to
16185 incorrectly label the sections as SHT_PROGBITS. The best compromise
16186 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16187 generic type-checking code. */
16188 if (section_type == SHT_MIPS_DWARF)
16189 section_type = SHT_PROGBITS;
16191 obj_elf_change_section (section_name, section_type, section_flag,
16192 section_entry_size, 0, 0, 0);
16194 if (now_seg->name != section_name)
16195 free (section_name);
16199 mips_enable_auto_align (void)
16205 s_cons (int log_size)
16207 segment_info_type *si = seg_info (now_seg);
16208 struct insn_label_list *l = si->label_list;
16210 mips_emit_delays ();
16211 if (log_size > 0 && auto_align)
16212 mips_align (log_size, 0, l);
16213 cons (1 << log_size);
16214 mips_clear_insn_labels ();
16218 s_float_cons (int type)
16220 segment_info_type *si = seg_info (now_seg);
16221 struct insn_label_list *l = si->label_list;
16223 mips_emit_delays ();
16228 mips_align (3, 0, l);
16230 mips_align (2, 0, l);
16234 mips_clear_insn_labels ();
16237 /* Handle .globl. We need to override it because on Irix 5 you are
16240 where foo is an undefined symbol, to mean that foo should be
16241 considered to be the address of a function. */
16244 s_mips_globl (int x ATTRIBUTE_UNUSED)
16253 name = input_line_pointer;
16254 c = get_symbol_end ();
16255 symbolP = symbol_find_or_make (name);
16256 S_SET_EXTERNAL (symbolP);
16258 *input_line_pointer = c;
16259 SKIP_WHITESPACE ();
16261 /* On Irix 5, every global symbol that is not explicitly labelled as
16262 being a function is apparently labelled as being an object. */
16265 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16266 && (*input_line_pointer != ','))
16271 secname = input_line_pointer;
16272 c = get_symbol_end ();
16273 sec = bfd_get_section_by_name (stdoutput, secname);
16275 as_bad (_("%s: no such section"), secname);
16276 *input_line_pointer = c;
16278 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16279 flag = BSF_FUNCTION;
16282 symbol_get_bfdsym (symbolP)->flags |= flag;
16284 c = *input_line_pointer;
16287 input_line_pointer++;
16288 SKIP_WHITESPACE ();
16289 if (is_end_of_line[(unsigned char) *input_line_pointer])
16295 demand_empty_rest_of_line ();
16299 s_option (int x ATTRIBUTE_UNUSED)
16304 opt = input_line_pointer;
16305 c = get_symbol_end ();
16309 /* FIXME: What does this mean? */
16311 else if (strncmp (opt, "pic", 3) == 0)
16315 i = atoi (opt + 3);
16320 mips_pic = SVR4_PIC;
16321 mips_abicalls = TRUE;
16324 as_bad (_(".option pic%d not supported"), i);
16326 if (mips_pic == SVR4_PIC)
16328 if (g_switch_seen && g_switch_value != 0)
16329 as_warn (_("-G may not be used with SVR4 PIC code"));
16330 g_switch_value = 0;
16331 bfd_set_gp_size (stdoutput, 0);
16335 as_warn (_("Unrecognized option \"%s\""), opt);
16337 *input_line_pointer = c;
16338 demand_empty_rest_of_line ();
16341 /* This structure is used to hold a stack of .set values. */
16343 struct mips_option_stack
16345 struct mips_option_stack *next;
16346 struct mips_set_options options;
16349 static struct mips_option_stack *mips_opts_stack;
16351 /* Handle the .set pseudo-op. */
16354 s_mipsset (int x ATTRIBUTE_UNUSED)
16356 char *name = input_line_pointer, ch;
16357 const struct mips_ase *ase;
16359 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16360 ++input_line_pointer;
16361 ch = *input_line_pointer;
16362 *input_line_pointer = '\0';
16364 if (strcmp (name, "reorder") == 0)
16366 if (mips_opts.noreorder)
16369 else if (strcmp (name, "noreorder") == 0)
16371 if (!mips_opts.noreorder)
16372 start_noreorder ();
16374 else if (strncmp (name, "at=", 3) == 0)
16376 char *s = name + 3;
16378 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16379 as_bad (_("Unrecognized register name `%s'"), s);
16381 else if (strcmp (name, "at") == 0)
16383 mips_opts.at = ATREG;
16385 else if (strcmp (name, "noat") == 0)
16387 mips_opts.at = ZERO;
16389 else if (strcmp (name, "macro") == 0)
16391 mips_opts.warn_about_macros = 0;
16393 else if (strcmp (name, "nomacro") == 0)
16395 if (mips_opts.noreorder == 0)
16396 as_bad (_("`noreorder' must be set before `nomacro'"));
16397 mips_opts.warn_about_macros = 1;
16399 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16401 mips_opts.nomove = 0;
16403 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16405 mips_opts.nomove = 1;
16407 else if (strcmp (name, "bopt") == 0)
16409 mips_opts.nobopt = 0;
16411 else if (strcmp (name, "nobopt") == 0)
16413 mips_opts.nobopt = 1;
16415 else if (strcmp (name, "gp=default") == 0)
16416 mips_opts.gp32 = file_mips_gp32;
16417 else if (strcmp (name, "gp=32") == 0)
16418 mips_opts.gp32 = 1;
16419 else if (strcmp (name, "gp=64") == 0)
16421 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
16422 as_warn (_("%s isa does not support 64-bit registers"),
16423 mips_cpu_info_from_isa (mips_opts.isa)->name);
16424 mips_opts.gp32 = 0;
16426 else if (strcmp (name, "fp=default") == 0)
16427 mips_opts.fp32 = file_mips_fp32;
16428 else if (strcmp (name, "fp=32") == 0)
16429 mips_opts.fp32 = 1;
16430 else if (strcmp (name, "fp=64") == 0)
16432 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
16433 as_warn (_("%s isa does not support 64-bit floating point registers"),
16434 mips_cpu_info_from_isa (mips_opts.isa)->name);
16435 mips_opts.fp32 = 0;
16437 else if (strcmp (name, "softfloat") == 0)
16438 mips_opts.soft_float = 1;
16439 else if (strcmp (name, "hardfloat") == 0)
16440 mips_opts.soft_float = 0;
16441 else if (strcmp (name, "singlefloat") == 0)
16442 mips_opts.single_float = 1;
16443 else if (strcmp (name, "doublefloat") == 0)
16444 mips_opts.single_float = 0;
16445 else if (strcmp (name, "mips16") == 0
16446 || strcmp (name, "MIPS-16") == 0)
16448 if (mips_opts.micromips == 1)
16449 as_fatal (_("`mips16' cannot be used with `micromips'"));
16450 mips_opts.mips16 = 1;
16452 else if (strcmp (name, "nomips16") == 0
16453 || strcmp (name, "noMIPS-16") == 0)
16454 mips_opts.mips16 = 0;
16455 else if (strcmp (name, "micromips") == 0)
16457 if (mips_opts.mips16 == 1)
16458 as_fatal (_("`micromips' cannot be used with `mips16'"));
16459 mips_opts.micromips = 1;
16461 else if (strcmp (name, "nomicromips") == 0)
16462 mips_opts.micromips = 0;
16463 else if (name[0] == 'n'
16465 && (ase = mips_lookup_ase (name + 2)))
16466 mips_set_ase (ase, FALSE);
16467 else if ((ase = mips_lookup_ase (name)))
16468 mips_set_ase (ase, TRUE);
16469 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
16473 /* Permit the user to change the ISA and architecture on the fly.
16474 Needless to say, misuse can cause serious problems. */
16475 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16478 mips_opts.isa = file_mips_isa;
16479 mips_opts.arch = file_mips_arch;
16481 else if (strncmp (name, "arch=", 5) == 0)
16483 const struct mips_cpu_info *p;
16485 p = mips_parse_cpu("internal use", name + 5);
16487 as_bad (_("unknown architecture %s"), name + 5);
16490 mips_opts.arch = p->cpu;
16491 mips_opts.isa = p->isa;
16494 else if (strncmp (name, "mips", 4) == 0)
16496 const struct mips_cpu_info *p;
16498 p = mips_parse_cpu("internal use", name);
16500 as_bad (_("unknown ISA level %s"), name + 4);
16503 mips_opts.arch = p->cpu;
16504 mips_opts.isa = p->isa;
16508 as_bad (_("unknown ISA or architecture %s"), name);
16510 switch (mips_opts.isa)
16518 mips_opts.gp32 = 1;
16519 mips_opts.fp32 = 1;
16526 mips_opts.gp32 = 0;
16527 if (mips_opts.arch == CPU_R5900)
16529 mips_opts.fp32 = 1;
16533 mips_opts.fp32 = 0;
16537 as_bad (_("unknown ISA level %s"), name + 4);
16542 mips_opts.gp32 = file_mips_gp32;
16543 mips_opts.fp32 = file_mips_fp32;
16546 else if (strcmp (name, "autoextend") == 0)
16547 mips_opts.noautoextend = 0;
16548 else if (strcmp (name, "noautoextend") == 0)
16549 mips_opts.noautoextend = 1;
16550 else if (strcmp (name, "push") == 0)
16552 struct mips_option_stack *s;
16554 s = (struct mips_option_stack *) xmalloc (sizeof *s);
16555 s->next = mips_opts_stack;
16556 s->options = mips_opts;
16557 mips_opts_stack = s;
16559 else if (strcmp (name, "pop") == 0)
16561 struct mips_option_stack *s;
16563 s = mips_opts_stack;
16565 as_bad (_(".set pop with no .set push"));
16568 /* If we're changing the reorder mode we need to handle
16569 delay slots correctly. */
16570 if (s->options.noreorder && ! mips_opts.noreorder)
16571 start_noreorder ();
16572 else if (! s->options.noreorder && mips_opts.noreorder)
16575 mips_opts = s->options;
16576 mips_opts_stack = s->next;
16580 else if (strcmp (name, "sym32") == 0)
16581 mips_opts.sym32 = TRUE;
16582 else if (strcmp (name, "nosym32") == 0)
16583 mips_opts.sym32 = FALSE;
16584 else if (strchr (name, ','))
16586 /* Generic ".set" directive; use the generic handler. */
16587 *input_line_pointer = ch;
16588 input_line_pointer = name;
16594 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
16596 mips_check_isa_supports_ases ();
16597 *input_line_pointer = ch;
16598 demand_empty_rest_of_line ();
16601 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16602 .option pic2. It means to generate SVR4 PIC calls. */
16605 s_abicalls (int ignore ATTRIBUTE_UNUSED)
16607 mips_pic = SVR4_PIC;
16608 mips_abicalls = TRUE;
16610 if (g_switch_seen && g_switch_value != 0)
16611 as_warn (_("-G may not be used with SVR4 PIC code"));
16612 g_switch_value = 0;
16614 bfd_set_gp_size (stdoutput, 0);
16615 demand_empty_rest_of_line ();
16618 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16619 PIC code. It sets the $gp register for the function based on the
16620 function address, which is in the register named in the argument.
16621 This uses a relocation against _gp_disp, which is handled specially
16622 by the linker. The result is:
16623 lui $gp,%hi(_gp_disp)
16624 addiu $gp,$gp,%lo(_gp_disp)
16625 addu $gp,$gp,.cpload argument
16626 The .cpload argument is normally $25 == $t9.
16628 The -mno-shared option changes this to:
16629 lui $gp,%hi(__gnu_local_gp)
16630 addiu $gp,$gp,%lo(__gnu_local_gp)
16631 and the argument is ignored. This saves an instruction, but the
16632 resulting code is not position independent; it uses an absolute
16633 address for __gnu_local_gp. Thus code assembled with -mno-shared
16634 can go into an ordinary executable, but not into a shared library. */
16637 s_cpload (int ignore ATTRIBUTE_UNUSED)
16643 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16644 .cpload is ignored. */
16645 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16651 if (mips_opts.mips16)
16653 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16654 ignore_rest_of_line ();
16658 /* .cpload should be in a .set noreorder section. */
16659 if (mips_opts.noreorder == 0)
16660 as_warn (_(".cpload not in noreorder section"));
16662 reg = tc_get_register (0);
16664 /* If we need to produce a 64-bit address, we are better off using
16665 the default instruction sequence. */
16666 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
16668 ex.X_op = O_symbol;
16669 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
16671 ex.X_op_symbol = NULL;
16672 ex.X_add_number = 0;
16674 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16675 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16677 mips_mark_labels ();
16678 mips_assembling_insn = TRUE;
16681 macro_build_lui (&ex, mips_gp_register);
16682 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16683 mips_gp_register, BFD_RELOC_LO16);
16685 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
16686 mips_gp_register, reg);
16689 mips_assembling_insn = FALSE;
16690 demand_empty_rest_of_line ();
16693 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16694 .cpsetup $reg1, offset|$reg2, label
16696 If offset is given, this results in:
16697 sd $gp, offset($sp)
16698 lui $gp, %hi(%neg(%gp_rel(label)))
16699 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16700 daddu $gp, $gp, $reg1
16702 If $reg2 is given, this results in:
16703 daddu $reg2, $gp, $0
16704 lui $gp, %hi(%neg(%gp_rel(label)))
16705 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16706 daddu $gp, $gp, $reg1
16707 $reg1 is normally $25 == $t9.
16709 The -mno-shared option replaces the last three instructions with
16711 addiu $gp,$gp,%lo(_gp) */
16714 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
16716 expressionS ex_off;
16717 expressionS ex_sym;
16720 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
16721 We also need NewABI support. */
16722 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16728 if (mips_opts.mips16)
16730 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
16731 ignore_rest_of_line ();
16735 reg1 = tc_get_register (0);
16736 SKIP_WHITESPACE ();
16737 if (*input_line_pointer != ',')
16739 as_bad (_("missing argument separator ',' for .cpsetup"));
16743 ++input_line_pointer;
16744 SKIP_WHITESPACE ();
16745 if (*input_line_pointer == '$')
16747 mips_cpreturn_register = tc_get_register (0);
16748 mips_cpreturn_offset = -1;
16752 mips_cpreturn_offset = get_absolute_expression ();
16753 mips_cpreturn_register = -1;
16755 SKIP_WHITESPACE ();
16756 if (*input_line_pointer != ',')
16758 as_bad (_("missing argument separator ',' for .cpsetup"));
16762 ++input_line_pointer;
16763 SKIP_WHITESPACE ();
16764 expression (&ex_sym);
16766 mips_mark_labels ();
16767 mips_assembling_insn = TRUE;
16770 if (mips_cpreturn_register == -1)
16772 ex_off.X_op = O_constant;
16773 ex_off.X_add_symbol = NULL;
16774 ex_off.X_op_symbol = NULL;
16775 ex_off.X_add_number = mips_cpreturn_offset;
16777 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
16778 BFD_RELOC_LO16, SP);
16781 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
16782 mips_gp_register, 0);
16784 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
16786 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
16787 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
16790 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
16791 mips_gp_register, -1, BFD_RELOC_GPREL16,
16792 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
16794 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
16795 mips_gp_register, reg1);
16801 ex.X_op = O_symbol;
16802 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
16803 ex.X_op_symbol = NULL;
16804 ex.X_add_number = 0;
16806 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16807 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
16809 macro_build_lui (&ex, mips_gp_register);
16810 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
16811 mips_gp_register, BFD_RELOC_LO16);
16816 mips_assembling_insn = FALSE;
16817 demand_empty_rest_of_line ();
16821 s_cplocal (int ignore ATTRIBUTE_UNUSED)
16823 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
16824 .cplocal is ignored. */
16825 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16831 if (mips_opts.mips16)
16833 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
16834 ignore_rest_of_line ();
16838 mips_gp_register = tc_get_register (0);
16839 demand_empty_rest_of_line ();
16842 /* Handle the .cprestore pseudo-op. This stores $gp into a given
16843 offset from $sp. The offset is remembered, and after making a PIC
16844 call $gp is restored from that location. */
16847 s_cprestore (int ignore ATTRIBUTE_UNUSED)
16851 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16852 .cprestore is ignored. */
16853 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
16859 if (mips_opts.mips16)
16861 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
16862 ignore_rest_of_line ();
16866 mips_cprestore_offset = get_absolute_expression ();
16867 mips_cprestore_valid = 1;
16869 ex.X_op = O_constant;
16870 ex.X_add_symbol = NULL;
16871 ex.X_op_symbol = NULL;
16872 ex.X_add_number = mips_cprestore_offset;
16874 mips_mark_labels ();
16875 mips_assembling_insn = TRUE;
16878 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
16879 SP, HAVE_64BIT_ADDRESSES);
16882 mips_assembling_insn = FALSE;
16883 demand_empty_rest_of_line ();
16886 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
16887 was given in the preceding .cpsetup, it results in:
16888 ld $gp, offset($sp)
16890 If a register $reg2 was given there, it results in:
16891 daddu $gp, $reg2, $0 */
16894 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
16898 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
16899 We also need NewABI support. */
16900 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
16906 if (mips_opts.mips16)
16908 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
16909 ignore_rest_of_line ();
16913 mips_mark_labels ();
16914 mips_assembling_insn = TRUE;
16917 if (mips_cpreturn_register == -1)
16919 ex.X_op = O_constant;
16920 ex.X_add_symbol = NULL;
16921 ex.X_op_symbol = NULL;
16922 ex.X_add_number = mips_cpreturn_offset;
16924 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
16927 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
16928 mips_cpreturn_register, 0);
16931 mips_assembling_insn = FALSE;
16932 demand_empty_rest_of_line ();
16935 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
16936 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
16937 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
16938 debug information or MIPS16 TLS. */
16941 s_tls_rel_directive (const size_t bytes, const char *dirstr,
16942 bfd_reloc_code_real_type rtype)
16949 if (ex.X_op != O_symbol)
16951 as_bad (_("Unsupported use of %s"), dirstr);
16952 ignore_rest_of_line ();
16955 p = frag_more (bytes);
16956 md_number_to_chars (p, 0, bytes);
16957 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype);
16958 demand_empty_rest_of_line ();
16959 mips_clear_insn_labels ();
16962 /* Handle .dtprelword. */
16965 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
16967 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
16970 /* Handle .dtpreldword. */
16973 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
16975 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
16978 /* Handle .tprelword. */
16981 s_tprelword (int ignore ATTRIBUTE_UNUSED)
16983 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
16986 /* Handle .tpreldword. */
16989 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
16991 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
16994 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
16995 code. It sets the offset to use in gp_rel relocations. */
16998 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17000 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17001 We also need NewABI support. */
17002 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17008 mips_gprel_offset = get_absolute_expression ();
17010 demand_empty_rest_of_line ();
17013 /* Handle the .gpword pseudo-op. This is used when generating PIC
17014 code. It generates a 32 bit GP relative reloc. */
17017 s_gpword (int ignore ATTRIBUTE_UNUSED)
17019 segment_info_type *si;
17020 struct insn_label_list *l;
17024 /* When not generating PIC code, this is treated as .word. */
17025 if (mips_pic != SVR4_PIC)
17031 si = seg_info (now_seg);
17032 l = si->label_list;
17033 mips_emit_delays ();
17035 mips_align (2, 0, l);
17038 mips_clear_insn_labels ();
17040 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17042 as_bad (_("Unsupported use of .gpword"));
17043 ignore_rest_of_line ();
17047 md_number_to_chars (p, 0, 4);
17048 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17049 BFD_RELOC_GPREL32);
17051 demand_empty_rest_of_line ();
17055 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17057 segment_info_type *si;
17058 struct insn_label_list *l;
17062 /* When not generating PIC code, this is treated as .dword. */
17063 if (mips_pic != SVR4_PIC)
17069 si = seg_info (now_seg);
17070 l = si->label_list;
17071 mips_emit_delays ();
17073 mips_align (3, 0, l);
17076 mips_clear_insn_labels ();
17078 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17080 as_bad (_("Unsupported use of .gpdword"));
17081 ignore_rest_of_line ();
17085 md_number_to_chars (p, 0, 8);
17086 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17087 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17089 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17090 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17091 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
17093 demand_empty_rest_of_line ();
17096 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17097 tables. It generates a R_MIPS_EH reloc. */
17100 s_ehword (int ignore ATTRIBUTE_UNUSED)
17105 mips_emit_delays ();
17108 mips_clear_insn_labels ();
17110 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17112 as_bad (_("Unsupported use of .ehword"));
17113 ignore_rest_of_line ();
17117 md_number_to_chars (p, 0, 4);
17118 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
17119 BFD_RELOC_MIPS_EH);
17121 demand_empty_rest_of_line ();
17124 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17125 tables in SVR4 PIC code. */
17128 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17132 /* This is ignored when not generating SVR4 PIC code. */
17133 if (mips_pic != SVR4_PIC)
17139 mips_mark_labels ();
17140 mips_assembling_insn = TRUE;
17142 /* Add $gp to the register named as an argument. */
17144 reg = tc_get_register (0);
17145 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17148 mips_assembling_insn = FALSE;
17149 demand_empty_rest_of_line ();
17152 /* Handle the .insn pseudo-op. This marks instruction labels in
17153 mips16/micromips mode. This permits the linker to handle them specially,
17154 such as generating jalx instructions when needed. We also make
17155 them odd for the duration of the assembly, in order to generate the
17156 right sort of code. We will make them even in the adjust_symtab
17157 routine, while leaving them marked. This is convenient for the
17158 debugger and the disassembler. The linker knows to make them odd
17162 s_insn (int ignore ATTRIBUTE_UNUSED)
17164 mips_mark_labels ();
17166 demand_empty_rest_of_line ();
17169 /* Handle a .stab[snd] directive. Ideally these directives would be
17170 implemented in a transparent way, so that removing them would not
17171 have any effect on the generated instructions. However, s_stab
17172 internally changes the section, so in practice we need to decide
17173 now whether the preceding label marks compressed code. We do not
17174 support changing the compression mode of a label after a .stab*
17175 directive, such as in:
17181 so the current mode wins. */
17184 s_mips_stab (int type)
17186 mips_mark_labels ();
17190 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17193 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17200 name = input_line_pointer;
17201 c = get_symbol_end ();
17202 symbolP = symbol_find_or_make (name);
17203 S_SET_WEAK (symbolP);
17204 *input_line_pointer = c;
17206 SKIP_WHITESPACE ();
17208 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17210 if (S_IS_DEFINED (symbolP))
17212 as_bad (_("ignoring attempt to redefine symbol %s"),
17213 S_GET_NAME (symbolP));
17214 ignore_rest_of_line ();
17218 if (*input_line_pointer == ',')
17220 ++input_line_pointer;
17221 SKIP_WHITESPACE ();
17225 if (exp.X_op != O_symbol)
17227 as_bad (_("bad .weakext directive"));
17228 ignore_rest_of_line ();
17231 symbol_set_value_expression (symbolP, &exp);
17234 demand_empty_rest_of_line ();
17237 /* Parse a register string into a number. Called from the ECOFF code
17238 to parse .frame. The argument is non-zero if this is the frame
17239 register, so that we can record it in mips_frame_reg. */
17242 tc_get_register (int frame)
17246 SKIP_WHITESPACE ();
17247 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17251 mips_frame_reg = reg != 0 ? reg : SP;
17252 mips_frame_reg_valid = 1;
17253 mips_cprestore_valid = 0;
17259 md_section_align (asection *seg, valueT addr)
17261 int align = bfd_get_section_alignment (stdoutput, seg);
17263 /* We don't need to align ELF sections to the full alignment.
17264 However, Irix 5 may prefer that we align them at least to a 16
17265 byte boundary. We don't bother to align the sections if we
17266 are targeted for an embedded system. */
17267 if (strncmp (TARGET_OS, "elf", 3) == 0)
17272 return ((addr + (1 << align) - 1) & (-1 << align));
17275 /* Utility routine, called from above as well. If called while the
17276 input file is still being read, it's only an approximation. (For
17277 example, a symbol may later become defined which appeared to be
17278 undefined earlier.) */
17281 nopic_need_relax (symbolS *sym, int before_relaxing)
17286 if (g_switch_value > 0)
17288 const char *symname;
17291 /* Find out whether this symbol can be referenced off the $gp
17292 register. It can be if it is smaller than the -G size or if
17293 it is in the .sdata or .sbss section. Certain symbols can
17294 not be referenced off the $gp, although it appears as though
17296 symname = S_GET_NAME (sym);
17297 if (symname != (const char *) NULL
17298 && (strcmp (symname, "eprol") == 0
17299 || strcmp (symname, "etext") == 0
17300 || strcmp (symname, "_gp") == 0
17301 || strcmp (symname, "edata") == 0
17302 || strcmp (symname, "_fbss") == 0
17303 || strcmp (symname, "_fdata") == 0
17304 || strcmp (symname, "_ftext") == 0
17305 || strcmp (symname, "end") == 0
17306 || strcmp (symname, "_gp_disp") == 0))
17308 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17310 #ifndef NO_ECOFF_DEBUGGING
17311 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17312 && (symbol_get_obj (sym)->ecoff_extern_size
17313 <= g_switch_value))
17315 /* We must defer this decision until after the whole
17316 file has been read, since there might be a .extern
17317 after the first use of this symbol. */
17318 || (before_relaxing
17319 #ifndef NO_ECOFF_DEBUGGING
17320 && symbol_get_obj (sym)->ecoff_extern_size == 0
17322 && S_GET_VALUE (sym) == 0)
17323 || (S_GET_VALUE (sym) != 0
17324 && S_GET_VALUE (sym) <= g_switch_value)))
17328 const char *segname;
17330 segname = segment_name (S_GET_SEGMENT (sym));
17331 gas_assert (strcmp (segname, ".lit8") != 0
17332 && strcmp (segname, ".lit4") != 0);
17333 change = (strcmp (segname, ".sdata") != 0
17334 && strcmp (segname, ".sbss") != 0
17335 && strncmp (segname, ".sdata.", 7) != 0
17336 && strncmp (segname, ".sbss.", 6) != 0
17337 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
17338 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
17343 /* We are not optimizing for the $gp register. */
17348 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17351 pic_need_relax (symbolS *sym, asection *segtype)
17355 /* Handle the case of a symbol equated to another symbol. */
17356 while (symbol_equated_reloc_p (sym))
17360 /* It's possible to get a loop here in a badly written program. */
17361 n = symbol_get_value_expression (sym)->X_add_symbol;
17367 if (symbol_section_p (sym))
17370 symsec = S_GET_SEGMENT (sym);
17372 /* This must duplicate the test in adjust_reloc_syms. */
17373 return (!bfd_is_und_section (symsec)
17374 && !bfd_is_abs_section (symsec)
17375 && !bfd_is_com_section (symsec)
17376 && !s_is_linkonce (sym, segtype)
17377 /* A global or weak symbol is treated as external. */
17378 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17382 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17383 extended opcode. SEC is the section the frag is in. */
17386 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17389 const struct mips16_immed_operand *op;
17391 int mintiny, maxtiny;
17395 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17397 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17400 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17401 op = mips16_immed_operands;
17402 while (op->type != type)
17405 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
17410 if (type == '<' || type == '>' || type == '[' || type == ']')
17413 maxtiny = 1 << op->nbits;
17418 maxtiny = (1 << op->nbits) - 1;
17423 mintiny = - (1 << (op->nbits - 1));
17424 maxtiny = (1 << (op->nbits - 1)) - 1;
17427 sym_frag = symbol_get_frag (fragp->fr_symbol);
17428 val = S_GET_VALUE (fragp->fr_symbol);
17429 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17435 /* We won't have the section when we are called from
17436 mips_relax_frag. However, we will always have been called
17437 from md_estimate_size_before_relax first. If this is a
17438 branch to a different section, we mark it as such. If SEC is
17439 NULL, and the frag is not marked, then it must be a branch to
17440 the same section. */
17443 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
17448 /* Must have been called from md_estimate_size_before_relax. */
17451 fragp->fr_subtype =
17452 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17454 /* FIXME: We should support this, and let the linker
17455 catch branches and loads that are out of range. */
17456 as_bad_where (fragp->fr_file, fragp->fr_line,
17457 _("unsupported PC relative reference to different section"));
17461 if (fragp != sym_frag && sym_frag->fr_address == 0)
17462 /* Assume non-extended on the first relaxation pass.
17463 The address we have calculated will be bogus if this is
17464 a forward branch to another frag, as the forward frag
17465 will have fr_address == 0. */
17469 /* In this case, we know for sure that the symbol fragment is in
17470 the same section. If the relax_marker of the symbol fragment
17471 differs from the relax_marker of this fragment, we have not
17472 yet adjusted the symbol fragment fr_address. We want to add
17473 in STRETCH in order to get a better estimate of the address.
17474 This particularly matters because of the shift bits. */
17476 && sym_frag->relax_marker != fragp->relax_marker)
17480 /* Adjust stretch for any alignment frag. Note that if have
17481 been expanding the earlier code, the symbol may be
17482 defined in what appears to be an earlier frag. FIXME:
17483 This doesn't handle the fr_subtype field, which specifies
17484 a maximum number of bytes to skip when doing an
17486 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17488 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17491 stretch = - ((- stretch)
17492 & ~ ((1 << (int) f->fr_offset) - 1));
17494 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
17503 addr = fragp->fr_address + fragp->fr_fix;
17505 /* The base address rules are complicated. The base address of
17506 a branch is the following instruction. The base address of a
17507 PC relative load or add is the instruction itself, but if it
17508 is in a delay slot (in which case it can not be extended) use
17509 the address of the instruction whose delay slot it is in. */
17510 if (type == 'p' || type == 'q')
17514 /* If we are currently assuming that this frag should be
17515 extended, then, the current address is two bytes
17517 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17520 /* Ignore the low bit in the target, since it will be set
17521 for a text label. */
17522 if ((val & 1) != 0)
17525 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17527 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17530 val -= addr & ~ ((1 << op->shift) - 1);
17532 /* Branch offsets have an implicit 0 in the lowest bit. */
17533 if (type == 'p' || type == 'q')
17536 /* If any of the shifted bits are set, we must use an extended
17537 opcode. If the address depends on the size of this
17538 instruction, this can lead to a loop, so we arrange to always
17539 use an extended opcode. We only check this when we are in
17540 the main relaxation loop, when SEC is NULL. */
17541 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
17543 fragp->fr_subtype =
17544 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17548 /* If we are about to mark a frag as extended because the value
17549 is precisely maxtiny + 1, then there is a chance of an
17550 infinite loop as in the following code:
17555 In this case when the la is extended, foo is 0x3fc bytes
17556 away, so the la can be shrunk, but then foo is 0x400 away, so
17557 the la must be extended. To avoid this loop, we mark the
17558 frag as extended if it was small, and is about to become
17559 extended with a value of maxtiny + 1. */
17560 if (val == ((maxtiny + 1) << op->shift)
17561 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
17564 fragp->fr_subtype =
17565 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
17569 else if (symsec != absolute_section && sec != NULL)
17570 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
17572 if ((val & ((1 << op->shift) - 1)) != 0
17573 || val < (mintiny << op->shift)
17574 || val > (maxtiny << op->shift))
17580 /* Compute the length of a branch sequence, and adjust the
17581 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17582 worst-case length is computed, with UPDATE being used to indicate
17583 whether an unconditional (-1), branch-likely (+1) or regular (0)
17584 branch is to be computed. */
17586 relaxed_branch_length (fragS *fragp, asection *sec, int update)
17588 bfd_boolean toofar;
17592 && S_IS_DEFINED (fragp->fr_symbol)
17593 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17598 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17600 addr = fragp->fr_address + fragp->fr_fix + 4;
17604 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
17607 /* If the symbol is not defined or it's in a different segment,
17608 assume the user knows what's going on and emit a short
17614 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
17616 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
17617 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
17618 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
17619 RELAX_BRANCH_LINK (fragp->fr_subtype),
17625 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
17628 if (mips_pic != NO_PIC)
17630 /* Additional space for PIC loading of target address. */
17632 if (mips_opts.isa == ISA_MIPS1)
17633 /* Additional space for $at-stabilizing nop. */
17637 /* If branch is conditional. */
17638 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
17645 /* Compute the length of a branch sequence, and adjust the
17646 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
17647 worst-case length is computed, with UPDATE being used to indicate
17648 whether an unconditional (-1), or regular (0) branch is to be
17652 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
17654 bfd_boolean toofar;
17658 && S_IS_DEFINED (fragp->fr_symbol)
17659 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17664 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17665 /* Ignore the low bit in the target, since it will be set
17666 for a text label. */
17667 if ((val & 1) != 0)
17670 addr = fragp->fr_address + fragp->fr_fix + 4;
17674 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
17677 /* If the symbol is not defined or it's in a different segment,
17678 assume the user knows what's going on and emit a short
17684 if (fragp && update
17685 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
17686 fragp->fr_subtype = (toofar
17687 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
17688 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
17693 bfd_boolean compact_known = fragp != NULL;
17694 bfd_boolean compact = FALSE;
17695 bfd_boolean uncond;
17698 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
17700 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
17702 uncond = update < 0;
17704 /* If label is out of range, we turn branch <br>:
17706 <br> label # 4 bytes
17712 nop # 2 bytes if compact && !PIC
17715 if (mips_pic == NO_PIC && (!compact_known || compact))
17718 /* If assembling PIC code, we further turn:
17724 lw/ld at, %got(label)(gp) # 4 bytes
17725 d/addiu at, %lo(label) # 4 bytes
17728 if (mips_pic != NO_PIC)
17731 /* If branch <br> is conditional, we prepend negated branch <brneg>:
17733 <brneg> 0f # 4 bytes
17734 nop # 2 bytes if !compact
17737 length += (compact_known && compact) ? 4 : 6;
17743 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
17744 bit accordingly. */
17747 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
17749 bfd_boolean toofar;
17752 && S_IS_DEFINED (fragp->fr_symbol)
17753 && sec == S_GET_SEGMENT (fragp->fr_symbol))
17759 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17760 /* Ignore the low bit in the target, since it will be set
17761 for a text label. */
17762 if ((val & 1) != 0)
17765 /* Assume this is a 2-byte branch. */
17766 addr = fragp->fr_address + fragp->fr_fix + 2;
17768 /* We try to avoid the infinite loop by not adding 2 more bytes for
17773 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
17775 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
17776 else if (type == 'E')
17777 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
17782 /* If the symbol is not defined or it's in a different segment,
17783 we emit a normal 32-bit branch. */
17786 if (fragp && update
17787 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
17789 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
17790 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
17798 /* Estimate the size of a frag before relaxing. Unless this is the
17799 mips16, we are not really relaxing here, and the final size is
17800 encoded in the subtype information. For the mips16, we have to
17801 decide whether we are using an extended opcode or not. */
17804 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
17808 if (RELAX_BRANCH_P (fragp->fr_subtype))
17811 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
17813 return fragp->fr_var;
17816 if (RELAX_MIPS16_P (fragp->fr_subtype))
17817 /* We don't want to modify the EXTENDED bit here; it might get us
17818 into infinite loops. We change it only in mips_relax_frag(). */
17819 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
17821 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
17825 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
17826 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE);
17827 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
17828 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE);
17829 fragp->fr_var = length;
17834 if (mips_pic == NO_PIC)
17835 change = nopic_need_relax (fragp->fr_symbol, 0);
17836 else if (mips_pic == SVR4_PIC)
17837 change = pic_need_relax (fragp->fr_symbol, segtype);
17838 else if (mips_pic == VXWORKS_PIC)
17839 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
17846 fragp->fr_subtype |= RELAX_USE_SECOND;
17847 return -RELAX_FIRST (fragp->fr_subtype);
17850 return -RELAX_SECOND (fragp->fr_subtype);
17853 /* This is called to see whether a reloc against a defined symbol
17854 should be converted into a reloc against a section. */
17857 mips_fix_adjustable (fixS *fixp)
17859 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
17860 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17863 if (fixp->fx_addsy == NULL)
17866 /* If symbol SYM is in a mergeable section, relocations of the form
17867 SYM + 0 can usually be made section-relative. The mergeable data
17868 is then identified by the section offset rather than by the symbol.
17870 However, if we're generating REL LO16 relocations, the offset is split
17871 between the LO16 and parterning high part relocation. The linker will
17872 need to recalculate the complete offset in order to correctly identify
17875 The linker has traditionally not looked for the parterning high part
17876 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
17877 placed anywhere. Rather than break backwards compatibility by changing
17878 this, it seems better not to force the issue, and instead keep the
17879 original symbol. This will work with either linker behavior. */
17880 if ((lo16_reloc_p (fixp->fx_r_type)
17881 || reloc_needs_lo_p (fixp->fx_r_type))
17882 && HAVE_IN_PLACE_ADDENDS
17883 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
17886 /* There is no place to store an in-place offset for JALR relocations.
17887 Likewise an in-range offset of limited PC-relative relocations may
17888 overflow the in-place relocatable field if recalculated against the
17889 start address of the symbol's containing section. */
17890 if (HAVE_IN_PLACE_ADDENDS
17891 && (limited_pcrel_reloc_p (fixp->fx_r_type)
17892 || jalr_reloc_p (fixp->fx_r_type)))
17895 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
17896 to a floating-point stub. The same is true for non-R_MIPS16_26
17897 relocations against MIPS16 functions; in this case, the stub becomes
17898 the function's canonical address.
17900 Floating-point stubs are stored in unique .mips16.call.* or
17901 .mips16.fn.* sections. If a stub T for function F is in section S,
17902 the first relocation in section S must be against F; this is how the
17903 linker determines the target function. All relocations that might
17904 resolve to T must also be against F. We therefore have the following
17905 restrictions, which are given in an intentionally-redundant way:
17907 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
17910 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
17911 if that stub might be used.
17913 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
17916 4. We cannot reduce a stub's relocations against MIPS16 symbols if
17917 that stub might be used.
17919 There is a further restriction:
17921 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
17922 R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on
17923 targets with in-place addends; the relocation field cannot
17924 encode the low bit.
17926 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
17927 against a MIPS16 symbol. We deal with (5) by by not reducing any
17928 such relocations on REL targets.
17930 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
17931 relocation against some symbol R, no relocation against R may be
17932 reduced. (Note that this deals with (2) as well as (1) because
17933 relocations against global symbols will never be reduced on ELF
17934 targets.) This approach is a little simpler than trying to detect
17935 stub sections, and gives the "all or nothing" per-symbol consistency
17936 that we have for MIPS16 symbols. */
17937 if (fixp->fx_subsy == NULL
17938 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
17939 || *symbol_get_tc (fixp->fx_addsy)
17940 || (HAVE_IN_PLACE_ADDENDS
17941 && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
17942 && jmp_reloc_p (fixp->fx_r_type))))
17948 /* Translate internal representation of relocation info to BFD target
17952 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17954 static arelent *retval[4];
17956 bfd_reloc_code_real_type code;
17958 memset (retval, 0, sizeof(retval));
17959 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
17960 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
17961 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17962 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
17964 if (fixp->fx_pcrel)
17966 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
17967 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
17968 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
17969 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
17970 || fixp->fx_r_type == BFD_RELOC_32_PCREL);
17972 /* At this point, fx_addnumber is "symbol offset - pcrel address".
17973 Relocations want only the symbol offset. */
17974 reloc->addend = fixp->fx_addnumber + reloc->address;
17977 reloc->addend = fixp->fx_addnumber;
17979 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
17980 entry to be used in the relocation's section offset. */
17981 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17983 reloc->address = reloc->addend;
17987 code = fixp->fx_r_type;
17989 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
17990 if (reloc->howto == NULL)
17992 as_bad_where (fixp->fx_file, fixp->fx_line,
17993 _("Can not represent %s relocation in this object file format"),
17994 bfd_get_reloc_code_name (code));
18001 /* Relax a machine dependent frag. This returns the amount by which
18002 the current size of the frag should change. */
18005 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18007 if (RELAX_BRANCH_P (fragp->fr_subtype))
18009 offsetT old_var = fragp->fr_var;
18011 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
18013 return fragp->fr_var - old_var;
18016 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18018 offsetT old_var = fragp->fr_var;
18019 offsetT new_var = 4;
18021 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18022 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE);
18023 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18024 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE);
18025 fragp->fr_var = new_var;
18027 return new_var - old_var;
18030 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18033 if (mips16_extended_frag (fragp, NULL, stretch))
18035 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18037 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18042 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18044 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18051 /* Convert a machine dependent frag. */
18054 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18056 if (RELAX_BRANCH_P (fragp->fr_subtype))
18059 unsigned long insn;
18063 buf = fragp->fr_literal + fragp->fr_fix;
18064 insn = read_insn (buf);
18066 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18068 /* We generate a fixup instead of applying it right now
18069 because, if there are linker relaxations, we're going to
18070 need the relocations. */
18071 exp.X_op = O_symbol;
18072 exp.X_add_symbol = fragp->fr_symbol;
18073 exp.X_add_number = fragp->fr_offset;
18075 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18076 BFD_RELOC_16_PCREL_S2);
18077 fixp->fx_file = fragp->fr_file;
18078 fixp->fx_line = fragp->fr_line;
18080 buf = write_insn (buf, insn);
18086 as_warn_where (fragp->fr_file, fragp->fr_line,
18087 _("Relaxed out-of-range branch into a jump"));
18089 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18092 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18094 /* Reverse the branch. */
18095 switch ((insn >> 28) & 0xf)
18098 /* bc[0-3][tf]l? instructions can have the condition
18099 reversed by tweaking a single TF bit, and their
18100 opcodes all have 0x4???????. */
18101 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18102 insn ^= 0x00010000;
18106 /* bltz 0x04000000 bgez 0x04010000
18107 bltzal 0x04100000 bgezal 0x04110000 */
18108 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18109 insn ^= 0x00010000;
18113 /* beq 0x10000000 bne 0x14000000
18114 blez 0x18000000 bgtz 0x1c000000 */
18115 insn ^= 0x04000000;
18123 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18125 /* Clear the and-link bit. */
18126 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18128 /* bltzal 0x04100000 bgezal 0x04110000
18129 bltzall 0x04120000 bgezall 0x04130000 */
18130 insn &= ~0x00100000;
18133 /* Branch over the branch (if the branch was likely) or the
18134 full jump (not likely case). Compute the offset from the
18135 current instruction to branch to. */
18136 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18140 /* How many bytes in instructions we've already emitted? */
18141 i = buf - fragp->fr_literal - fragp->fr_fix;
18142 /* How many bytes in instructions from here to the end? */
18143 i = fragp->fr_var - i;
18145 /* Convert to instruction count. */
18147 /* Branch counts from the next instruction. */
18150 /* Branch over the jump. */
18151 buf = write_insn (buf, insn);
18154 buf = write_insn (buf, 0);
18156 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18158 /* beql $0, $0, 2f */
18160 /* Compute the PC offset from the current instruction to
18161 the end of the variable frag. */
18162 /* How many bytes in instructions we've already emitted? */
18163 i = buf - fragp->fr_literal - fragp->fr_fix;
18164 /* How many bytes in instructions from here to the end? */
18165 i = fragp->fr_var - i;
18166 /* Convert to instruction count. */
18168 /* Don't decrement i, because we want to branch over the
18172 buf = write_insn (buf, insn);
18173 buf = write_insn (buf, 0);
18177 if (mips_pic == NO_PIC)
18180 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18181 ? 0x0c000000 : 0x08000000);
18182 exp.X_op = O_symbol;
18183 exp.X_add_symbol = fragp->fr_symbol;
18184 exp.X_add_number = fragp->fr_offset;
18186 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18187 FALSE, BFD_RELOC_MIPS_JMP);
18188 fixp->fx_file = fragp->fr_file;
18189 fixp->fx_line = fragp->fr_line;
18191 buf = write_insn (buf, insn);
18195 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18197 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18198 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18199 insn |= at << OP_SH_RT;
18200 exp.X_op = O_symbol;
18201 exp.X_add_symbol = fragp->fr_symbol;
18202 exp.X_add_number = fragp->fr_offset;
18204 if (fragp->fr_offset)
18206 exp.X_add_symbol = make_expr_symbol (&exp);
18207 exp.X_add_number = 0;
18210 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18211 FALSE, BFD_RELOC_MIPS_GOT16);
18212 fixp->fx_file = fragp->fr_file;
18213 fixp->fx_line = fragp->fr_line;
18215 buf = write_insn (buf, insn);
18217 if (mips_opts.isa == ISA_MIPS1)
18219 buf = write_insn (buf, 0);
18221 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18222 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18223 insn |= at << OP_SH_RS | at << OP_SH_RT;
18225 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
18226 FALSE, BFD_RELOC_LO16);
18227 fixp->fx_file = fragp->fr_file;
18228 fixp->fx_line = fragp->fr_line;
18230 buf = write_insn (buf, insn);
18233 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18237 insn |= at << OP_SH_RS;
18239 buf = write_insn (buf, insn);
18243 fragp->fr_fix += fragp->fr_var;
18244 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18248 /* Relax microMIPS branches. */
18249 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18251 char *buf = fragp->fr_literal + fragp->fr_fix;
18252 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18253 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18254 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18255 bfd_boolean short_ds;
18256 unsigned long insn;
18260 exp.X_op = O_symbol;
18261 exp.X_add_symbol = fragp->fr_symbol;
18262 exp.X_add_number = fragp->fr_offset;
18264 fragp->fr_fix += fragp->fr_var;
18266 /* Handle 16-bit branches that fit or are forced to fit. */
18267 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18269 /* We generate a fixup instead of applying it right now,
18270 because if there is linker relaxation, we're going to
18271 need the relocations. */
18273 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18274 BFD_RELOC_MICROMIPS_10_PCREL_S1);
18275 else if (type == 'E')
18276 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE,
18277 BFD_RELOC_MICROMIPS_7_PCREL_S1);
18281 fixp->fx_file = fragp->fr_file;
18282 fixp->fx_line = fragp->fr_line;
18284 /* These relocations can have an addend that won't fit in
18286 fixp->fx_no_overflow = 1;
18291 /* Handle 32-bit branches that fit or are forced to fit. */
18292 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18293 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18295 /* We generate a fixup instead of applying it right now,
18296 because if there is linker relaxation, we're going to
18297 need the relocations. */
18298 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE,
18299 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18300 fixp->fx_file = fragp->fr_file;
18301 fixp->fx_line = fragp->fr_line;
18307 /* Relax 16-bit branches to 32-bit branches. */
18310 insn = read_compressed_insn (buf, 2);
18312 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18313 insn = 0x94000000; /* beq */
18314 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18316 unsigned long regno;
18318 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18319 regno = micromips_to_32_reg_d_map [regno];
18320 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18321 insn |= regno << MICROMIPSOP_SH_RS;
18326 /* Nothing else to do, just write it out. */
18327 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18328 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18330 buf = write_compressed_insn (buf, insn, 4);
18331 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18336 insn = read_compressed_insn (buf, 4);
18338 /* Relax 32-bit branches to a sequence of instructions. */
18339 as_warn_where (fragp->fr_file, fragp->fr_line,
18340 _("Relaxed out-of-range branch into a jump"));
18342 /* Set the short-delay-slot bit. */
18343 short_ds = al && (insn & 0x02000000) != 0;
18345 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18349 /* Reverse the branch. */
18350 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18351 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18352 insn ^= 0x20000000;
18353 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18354 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18355 || (insn & 0xffe00000) == 0x40800000 /* blez */
18356 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18357 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18358 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18359 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18360 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18361 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18362 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18363 insn ^= 0x00400000;
18364 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18365 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18366 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18367 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18368 insn ^= 0x00200000;
18374 /* Clear the and-link and short-delay-slot bits. */
18375 gas_assert ((insn & 0xfda00000) == 0x40200000);
18377 /* bltzal 0x40200000 bgezal 0x40600000 */
18378 /* bltzals 0x42200000 bgezals 0x42600000 */
18379 insn &= ~0x02200000;
18382 /* Make a label at the end for use with the branch. */
18383 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp);
18384 micromips_label_inc ();
18385 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18388 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE,
18389 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18390 fixp->fx_file = fragp->fr_file;
18391 fixp->fx_line = fragp->fr_line;
18393 /* Branch over the jump. */
18394 buf = write_compressed_insn (buf, insn, 4);
18397 buf = write_compressed_insn (buf, 0x0c00, 2);
18400 if (mips_pic == NO_PIC)
18402 unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */
18404 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18405 insn = al ? jal : 0xd4000000;
18407 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18408 BFD_RELOC_MICROMIPS_JMP);
18409 fixp->fx_file = fragp->fr_file;
18410 fixp->fx_line = fragp->fr_line;
18412 buf = write_compressed_insn (buf, insn, 4);
18415 buf = write_compressed_insn (buf, 0x0c00, 2);
18419 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
18420 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
18421 unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */
18423 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18424 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
18425 insn |= at << MICROMIPSOP_SH_RT;
18427 if (exp.X_add_number)
18429 exp.X_add_symbol = make_expr_symbol (&exp);
18430 exp.X_add_number = 0;
18433 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18434 BFD_RELOC_MICROMIPS_GOT16);
18435 fixp->fx_file = fragp->fr_file;
18436 fixp->fx_line = fragp->fr_line;
18438 buf = write_compressed_insn (buf, insn, 4);
18440 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18441 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
18442 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
18444 fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE,
18445 BFD_RELOC_MICROMIPS_LO16);
18446 fixp->fx_file = fragp->fr_file;
18447 fixp->fx_line = fragp->fr_line;
18449 buf = write_compressed_insn (buf, insn, 4);
18451 /* jr/jrc/jalr/jalrs $at */
18452 insn = al ? jalr : jr;
18453 insn |= at << MICROMIPSOP_SH_MJ;
18455 buf = write_compressed_insn (buf, insn, 2);
18458 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18462 if (RELAX_MIPS16_P (fragp->fr_subtype))
18465 const struct mips16_immed_operand *op;
18468 unsigned int user_length, length;
18469 unsigned long insn;
18472 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18473 op = mips16_immed_operands;
18474 while (op->type != type)
18477 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
18478 val = resolve_symbol_value (fragp->fr_symbol);
18483 addr = fragp->fr_address + fragp->fr_fix;
18485 /* The rules for the base address of a PC relative reloc are
18486 complicated; see mips16_extended_frag. */
18487 if (type == 'p' || type == 'q')
18492 /* Ignore the low bit in the target, since it will be
18493 set for a text label. */
18494 if ((val & 1) != 0)
18497 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
18499 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
18502 addr &= ~ (addressT) ((1 << op->shift) - 1);
18505 /* Make sure the section winds up with the alignment we have
18508 record_alignment (asec, op->shift);
18512 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
18513 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
18514 as_warn_where (fragp->fr_file, fragp->fr_line,
18515 _("extended instruction in delay slot"));
18517 buf = fragp->fr_literal + fragp->fr_fix;
18519 insn = read_compressed_insn (buf, 2);
18521 insn |= MIPS16_EXTEND;
18523 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18525 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
18530 mips16_immed (fragp->fr_file, fragp->fr_line, type,
18531 BFD_RELOC_UNUSED, val, user_length, &insn);
18533 length = (ext ? 4 : 2);
18534 gas_assert (mips16_opcode_length (insn) == length);
18535 write_compressed_insn (buf, insn, length);
18536 fragp->fr_fix += length;
18540 relax_substateT subtype = fragp->fr_subtype;
18541 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
18542 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0;
18546 first = RELAX_FIRST (subtype);
18547 second = RELAX_SECOND (subtype);
18548 fixp = (fixS *) fragp->fr_opcode;
18550 /* If the delay slot chosen does not match the size of the instruction,
18551 then emit a warning. */
18552 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
18553 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
18558 s = subtype & (RELAX_DELAY_SLOT_16BIT
18559 | RELAX_DELAY_SLOT_SIZE_FIRST
18560 | RELAX_DELAY_SLOT_SIZE_SECOND);
18561 msg = macro_warning (s);
18563 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18567 /* Possibly emit a warning if we've chosen the longer option. */
18568 if (use_second == second_longer)
18574 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
18575 msg = macro_warning (s);
18577 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
18581 /* Go through all the fixups for the first sequence. Disable them
18582 (by marking them as done) if we're going to use the second
18583 sequence instead. */
18585 && fixp->fx_frag == fragp
18586 && fixp->fx_where < fragp->fr_fix - second)
18588 if (subtype & RELAX_USE_SECOND)
18590 fixp = fixp->fx_next;
18593 /* Go through the fixups for the second sequence. Disable them if
18594 we're going to use the first sequence, otherwise adjust their
18595 addresses to account for the relaxation. */
18596 while (fixp && fixp->fx_frag == fragp)
18598 if (subtype & RELAX_USE_SECOND)
18599 fixp->fx_where -= first;
18602 fixp = fixp->fx_next;
18605 /* Now modify the frag contents. */
18606 if (subtype & RELAX_USE_SECOND)
18610 start = fragp->fr_literal + fragp->fr_fix - first - second;
18611 memmove (start, start + first, second);
18612 fragp->fr_fix -= first;
18615 fragp->fr_fix -= second;
18619 /* This function is called after the relocs have been generated.
18620 We've been storing mips16 text labels as odd. Here we convert them
18621 back to even for the convenience of the debugger. */
18624 mips_frob_file_after_relocs (void)
18627 unsigned int count, i;
18629 syms = bfd_get_outsymbols (stdoutput);
18630 count = bfd_get_symcount (stdoutput);
18631 for (i = 0; i < count; i++, syms++)
18632 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
18633 && ((*syms)->value & 1) != 0)
18635 (*syms)->value &= ~1;
18636 /* If the symbol has an odd size, it was probably computed
18637 incorrectly, so adjust that as well. */
18638 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
18639 ++elf_symbol (*syms)->internal_elf_sym.st_size;
18643 /* This function is called whenever a label is defined, including fake
18644 labels instantiated off the dot special symbol. It is used when
18645 handling branch delays; if a branch has a label, we assume we cannot
18646 move it. This also bumps the value of the symbol by 1 in compressed
18650 mips_record_label (symbolS *sym)
18652 segment_info_type *si = seg_info (now_seg);
18653 struct insn_label_list *l;
18655 if (free_insn_labels == NULL)
18656 l = (struct insn_label_list *) xmalloc (sizeof *l);
18659 l = free_insn_labels;
18660 free_insn_labels = l->next;
18664 l->next = si->label_list;
18665 si->label_list = l;
18668 /* This function is called as tc_frob_label() whenever a label is defined
18669 and adds a DWARF-2 record we only want for true labels. */
18672 mips_define_label (symbolS *sym)
18674 mips_record_label (sym);
18675 dwarf2_emit_label (sym);
18678 /* This function is called by tc_new_dot_label whenever a new dot symbol
18682 mips_add_dot_label (symbolS *sym)
18684 mips_record_label (sym);
18685 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
18686 mips_compressed_mark_label (sym);
18689 /* Some special processing for a MIPS ELF file. */
18692 mips_elf_final_processing (void)
18694 /* Write out the register information. */
18695 if (mips_abi != N64_ABI)
18699 s.ri_gprmask = mips_gprmask;
18700 s.ri_cprmask[0] = mips_cprmask[0];
18701 s.ri_cprmask[1] = mips_cprmask[1];
18702 s.ri_cprmask[2] = mips_cprmask[2];
18703 s.ri_cprmask[3] = mips_cprmask[3];
18704 /* The gp_value field is set by the MIPS ELF backend. */
18706 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
18707 ((Elf32_External_RegInfo *)
18708 mips_regmask_frag));
18712 Elf64_Internal_RegInfo s;
18714 s.ri_gprmask = mips_gprmask;
18716 s.ri_cprmask[0] = mips_cprmask[0];
18717 s.ri_cprmask[1] = mips_cprmask[1];
18718 s.ri_cprmask[2] = mips_cprmask[2];
18719 s.ri_cprmask[3] = mips_cprmask[3];
18720 /* The gp_value field is set by the MIPS ELF backend. */
18722 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
18723 ((Elf64_External_RegInfo *)
18724 mips_regmask_frag));
18727 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
18728 sort of BFD interface for this. */
18729 if (mips_any_noreorder)
18730 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
18731 if (mips_pic != NO_PIC)
18733 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
18734 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18737 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
18739 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
18740 defined at present; this might need to change in future. */
18741 if (file_ase_mips16)
18742 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
18743 if (file_ase_micromips)
18744 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
18745 if (file_ase & ASE_MDMX)
18746 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
18748 /* Set the MIPS ELF ABI flags. */
18749 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
18750 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
18751 else if (mips_abi == O64_ABI)
18752 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
18753 else if (mips_abi == EABI_ABI)
18755 if (!file_mips_gp32)
18756 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
18758 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
18760 else if (mips_abi == N32_ABI)
18761 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
18763 /* Nothing to do for N64_ABI. */
18765 if (mips_32bitmode)
18766 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
18768 #if 0 /* XXX FIXME */
18769 /* 32 bit code with 64 bit FP registers. */
18770 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
18771 elf_elfheader (stdoutput)->e_flags |= ???;
18775 typedef struct proc {
18777 symbolS *func_end_sym;
18778 unsigned long reg_mask;
18779 unsigned long reg_offset;
18780 unsigned long fpreg_mask;
18781 unsigned long fpreg_offset;
18782 unsigned long frame_offset;
18783 unsigned long frame_reg;
18784 unsigned long pc_reg;
18787 static procS cur_proc;
18788 static procS *cur_proc_ptr;
18789 static int numprocs;
18791 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
18792 as "2", and a normal nop as "0". */
18794 #define NOP_OPCODE_MIPS 0
18795 #define NOP_OPCODE_MIPS16 1
18796 #define NOP_OPCODE_MICROMIPS 2
18799 mips_nop_opcode (void)
18801 if (seg_info (now_seg)->tc_segment_info_data.micromips)
18802 return NOP_OPCODE_MICROMIPS;
18803 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
18804 return NOP_OPCODE_MIPS16;
18806 return NOP_OPCODE_MIPS;
18809 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
18810 32-bit microMIPS NOPs here (if applicable). */
18813 mips_handle_align (fragS *fragp)
18817 int bytes, size, excess;
18820 if (fragp->fr_type != rs_align_code)
18823 p = fragp->fr_literal + fragp->fr_fix;
18825 switch (nop_opcode)
18827 case NOP_OPCODE_MICROMIPS:
18828 opcode = micromips_nop32_insn.insn_opcode;
18831 case NOP_OPCODE_MIPS16:
18832 opcode = mips16_nop_insn.insn_opcode;
18835 case NOP_OPCODE_MIPS:
18837 opcode = nop_insn.insn_opcode;
18842 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
18843 excess = bytes % size;
18845 /* Handle the leading part if we're not inserting a whole number of
18846 instructions, and make it the end of the fixed part of the frag.
18847 Try to fit in a short microMIPS NOP if applicable and possible,
18848 and use zeroes otherwise. */
18849 gas_assert (excess < 4);
18850 fragp->fr_fix += excess;
18855 /* Fall through. */
18857 if (nop_opcode == NOP_OPCODE_MICROMIPS)
18859 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
18863 /* Fall through. */
18866 /* Fall through. */
18871 md_number_to_chars (p, opcode, size);
18872 fragp->fr_var = size;
18876 md_obj_begin (void)
18883 /* Check for premature end, nesting errors, etc. */
18885 as_warn (_("missing .end at end of assembly"));
18894 if (*input_line_pointer == '-')
18896 ++input_line_pointer;
18899 if (!ISDIGIT (*input_line_pointer))
18900 as_bad (_("expected simple number"));
18901 if (input_line_pointer[0] == '0')
18903 if (input_line_pointer[1] == 'x')
18905 input_line_pointer += 2;
18906 while (ISXDIGIT (*input_line_pointer))
18909 val |= hex_value (*input_line_pointer++);
18911 return negative ? -val : val;
18915 ++input_line_pointer;
18916 while (ISDIGIT (*input_line_pointer))
18919 val |= *input_line_pointer++ - '0';
18921 return negative ? -val : val;
18924 if (!ISDIGIT (*input_line_pointer))
18926 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
18927 *input_line_pointer, *input_line_pointer);
18928 as_warn (_("invalid number"));
18931 while (ISDIGIT (*input_line_pointer))
18934 val += *input_line_pointer++ - '0';
18936 return negative ? -val : val;
18939 /* The .file directive; just like the usual .file directive, but there
18940 is an initial number which is the ECOFF file index. In the non-ECOFF
18941 case .file implies DWARF-2. */
18944 s_mips_file (int x ATTRIBUTE_UNUSED)
18946 static int first_file_directive = 0;
18948 if (ECOFF_DEBUGGING)
18957 filename = dwarf2_directive_file (0);
18959 /* Versions of GCC up to 3.1 start files with a ".file"
18960 directive even for stabs output. Make sure that this
18961 ".file" is handled. Note that you need a version of GCC
18962 after 3.1 in order to support DWARF-2 on MIPS. */
18963 if (filename != NULL && ! first_file_directive)
18965 (void) new_logical_line (filename, -1);
18966 s_app_file_string (filename, 0);
18968 first_file_directive = 1;
18972 /* The .loc directive, implying DWARF-2. */
18975 s_mips_loc (int x ATTRIBUTE_UNUSED)
18977 if (!ECOFF_DEBUGGING)
18978 dwarf2_directive_loc (0);
18981 /* The .end directive. */
18984 s_mips_end (int x ATTRIBUTE_UNUSED)
18988 /* Following functions need their own .frame and .cprestore directives. */
18989 mips_frame_reg_valid = 0;
18990 mips_cprestore_valid = 0;
18992 if (!is_end_of_line[(unsigned char) *input_line_pointer])
18995 demand_empty_rest_of_line ();
19000 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19001 as_warn (_(".end not in text section"));
19005 as_warn (_(".end directive without a preceding .ent directive."));
19006 demand_empty_rest_of_line ();
19012 gas_assert (S_GET_NAME (p));
19013 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19014 as_warn (_(".end symbol does not match .ent symbol."));
19016 if (debug_type == DEBUG_STABS)
19017 stabs_generate_asm_endfunc (S_GET_NAME (p),
19021 as_warn (_(".end directive missing or unknown symbol"));
19023 /* Create an expression to calculate the size of the function. */
19024 if (p && cur_proc_ptr)
19026 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19027 expressionS *exp = xmalloc (sizeof (expressionS));
19030 exp->X_op = O_subtract;
19031 exp->X_add_symbol = symbol_temp_new_now ();
19032 exp->X_op_symbol = p;
19033 exp->X_add_number = 0;
19035 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19038 /* Generate a .pdr section. */
19039 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19041 segT saved_seg = now_seg;
19042 subsegT saved_subseg = now_subseg;
19046 #ifdef md_flush_pending_output
19047 md_flush_pending_output ();
19050 gas_assert (pdr_seg);
19051 subseg_set (pdr_seg, 0);
19053 /* Write the symbol. */
19054 exp.X_op = O_symbol;
19055 exp.X_add_symbol = p;
19056 exp.X_add_number = 0;
19057 emit_expr (&exp, 4);
19059 fragp = frag_more (7 * 4);
19061 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19062 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19063 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19064 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19065 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19066 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19067 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19069 subseg_set (saved_seg, saved_subseg);
19072 cur_proc_ptr = NULL;
19075 /* The .aent and .ent directives. */
19078 s_mips_ent (int aent)
19082 symbolP = get_symbol ();
19083 if (*input_line_pointer == ',')
19084 ++input_line_pointer;
19085 SKIP_WHITESPACE ();
19086 if (ISDIGIT (*input_line_pointer)
19087 || *input_line_pointer == '-')
19090 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
19091 as_warn (_(".ent or .aent not in text section."));
19093 if (!aent && cur_proc_ptr)
19094 as_warn (_("missing .end"));
19098 /* This function needs its own .frame and .cprestore directives. */
19099 mips_frame_reg_valid = 0;
19100 mips_cprestore_valid = 0;
19102 cur_proc_ptr = &cur_proc;
19103 memset (cur_proc_ptr, '\0', sizeof (procS));
19105 cur_proc_ptr->func_sym = symbolP;
19109 if (debug_type == DEBUG_STABS)
19110 stabs_generate_asm_func (S_GET_NAME (symbolP),
19111 S_GET_NAME (symbolP));
19114 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
19116 demand_empty_rest_of_line ();
19119 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19120 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19121 s_mips_frame is used so that we can set the PDR information correctly.
19122 We can't use the ecoff routines because they make reference to the ecoff
19123 symbol table (in the mdebug section). */
19126 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
19128 if (ECOFF_DEBUGGING)
19134 if (cur_proc_ptr == (procS *) NULL)
19136 as_warn (_(".frame outside of .ent"));
19137 demand_empty_rest_of_line ();
19141 cur_proc_ptr->frame_reg = tc_get_register (1);
19143 SKIP_WHITESPACE ();
19144 if (*input_line_pointer++ != ','
19145 || get_absolute_expression_and_terminator (&val) != ',')
19147 as_warn (_("Bad .frame directive"));
19148 --input_line_pointer;
19149 demand_empty_rest_of_line ();
19153 cur_proc_ptr->frame_offset = val;
19154 cur_proc_ptr->pc_reg = tc_get_register (0);
19156 demand_empty_rest_of_line ();
19160 /* The .fmask and .mask directives. If the mdebug section is present
19161 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19162 embedded targets, s_mips_mask is used so that we can set the PDR
19163 information correctly. We can't use the ecoff routines because they
19164 make reference to the ecoff symbol table (in the mdebug section). */
19167 s_mips_mask (int reg_type)
19169 if (ECOFF_DEBUGGING)
19170 s_ignore (reg_type);
19175 if (cur_proc_ptr == (procS *) NULL)
19177 as_warn (_(".mask/.fmask outside of .ent"));
19178 demand_empty_rest_of_line ();
19182 if (get_absolute_expression_and_terminator (&mask) != ',')
19184 as_warn (_("Bad .mask/.fmask directive"));
19185 --input_line_pointer;
19186 demand_empty_rest_of_line ();
19190 off = get_absolute_expression ();
19192 if (reg_type == 'F')
19194 cur_proc_ptr->fpreg_mask = mask;
19195 cur_proc_ptr->fpreg_offset = off;
19199 cur_proc_ptr->reg_mask = mask;
19200 cur_proc_ptr->reg_offset = off;
19203 demand_empty_rest_of_line ();
19207 /* A table describing all the processors gas knows about. Names are
19208 matched in the order listed.
19210 To ease comparison, please keep this table in the same order as
19211 gcc's mips_cpu_info_table[]. */
19212 static const struct mips_cpu_info mips_cpu_info_table[] =
19214 /* Entries for generic ISAs */
19215 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
19216 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
19217 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
19218 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
19219 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
19220 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
19221 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19222 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
19223 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
19226 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
19227 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
19228 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
19231 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
19234 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
19235 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
19236 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
19237 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
19238 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
19239 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
19240 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
19241 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
19242 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
19243 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
19244 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
19245 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
19246 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
19247 /* ST Microelectronics Loongson 2E and 2F cores */
19248 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
19249 { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
19252 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
19253 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
19254 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
19255 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
19256 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
19257 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
19258 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
19259 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
19260 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
19261 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
19262 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
19263 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
19264 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
19265 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
19266 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
19269 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19270 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19271 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
19272 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
19274 /* MIPS 32 Release 2 */
19275 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19276 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19277 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19278 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
19279 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19280 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19281 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19282 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
19283 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19284 ISA_MIPS32R2, CPU_MIPS32R2 },
19285 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
19286 ISA_MIPS32R2, CPU_MIPS32R2 },
19287 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19288 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19289 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19290 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19291 /* Deprecated forms of the above. */
19292 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19293 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
19294 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
19295 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19296 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19297 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19298 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19299 /* Deprecated forms of the above. */
19300 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19301 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
19302 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
19303 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19304 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19305 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19306 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19307 /* Deprecated forms of the above. */
19308 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19309 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19310 /* 34Kn is a 34kc without DSP. */
19311 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19312 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
19313 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19314 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19315 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19316 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19317 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19318 /* Deprecated forms of the above. */
19319 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19320 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
19321 /* 1004K cores are multiprocessor versions of the 34K. */
19322 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19323 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19324 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19325 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
19328 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19329 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
19330 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19331 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
19333 /* Broadcom SB-1 CPU core */
19334 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19335 /* Broadcom SB-1A CPU core */
19336 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
19338 { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
19340 /* MIPS 64 Release 2 */
19342 /* Cavium Networks Octeon CPU core */
19343 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
19344 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
19345 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
19348 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
19351 XLP is mostly like XLR, with the prominent exception that it is
19352 MIPS64R2 rather than MIPS64. */
19353 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
19356 { NULL, 0, 0, 0, 0 }
19360 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
19361 with a final "000" replaced by "k". Ignore case.
19363 Note: this function is shared between GCC and GAS. */
19366 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
19368 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
19369 given++, canonical++;
19371 return ((*given == 0 && *canonical == 0)
19372 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
19376 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
19377 CPU name. We've traditionally allowed a lot of variation here.
19379 Note: this function is shared between GCC and GAS. */
19382 mips_matching_cpu_name_p (const char *canonical, const char *given)
19384 /* First see if the name matches exactly, or with a final "000"
19385 turned into "k". */
19386 if (mips_strict_matching_cpu_name_p (canonical, given))
19389 /* If not, try comparing based on numerical designation alone.
19390 See if GIVEN is an unadorned number, or 'r' followed by a number. */
19391 if (TOLOWER (*given) == 'r')
19393 if (!ISDIGIT (*given))
19396 /* Skip over some well-known prefixes in the canonical name,
19397 hoping to find a number there too. */
19398 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
19400 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
19402 else if (TOLOWER (canonical[0]) == 'r')
19405 return mips_strict_matching_cpu_name_p (canonical, given);
19409 /* Parse an option that takes the name of a processor as its argument.
19410 OPTION is the name of the option and CPU_STRING is the argument.
19411 Return the corresponding processor enumeration if the CPU_STRING is
19412 recognized, otherwise report an error and return null.
19414 A similar function exists in GCC. */
19416 static const struct mips_cpu_info *
19417 mips_parse_cpu (const char *option, const char *cpu_string)
19419 const struct mips_cpu_info *p;
19421 /* 'from-abi' selects the most compatible architecture for the given
19422 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
19423 EABIs, we have to decide whether we're using the 32-bit or 64-bit
19424 version. Look first at the -mgp options, if given, otherwise base
19425 the choice on MIPS_DEFAULT_64BIT.
19427 Treat NO_ABI like the EABIs. One reason to do this is that the
19428 plain 'mips' and 'mips64' configs have 'from-abi' as their default
19429 architecture. This code picks MIPS I for 'mips' and MIPS III for
19430 'mips64', just as we did in the days before 'from-abi'. */
19431 if (strcasecmp (cpu_string, "from-abi") == 0)
19433 if (ABI_NEEDS_32BIT_REGS (mips_abi))
19434 return mips_cpu_info_from_isa (ISA_MIPS1);
19436 if (ABI_NEEDS_64BIT_REGS (mips_abi))
19437 return mips_cpu_info_from_isa (ISA_MIPS3);
19439 if (file_mips_gp32 >= 0)
19440 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
19442 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
19447 /* 'default' has traditionally been a no-op. Probably not very useful. */
19448 if (strcasecmp (cpu_string, "default") == 0)
19451 for (p = mips_cpu_info_table; p->name != 0; p++)
19452 if (mips_matching_cpu_name_p (p->name, cpu_string))
19455 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
19459 /* Return the canonical processor information for ISA (a member of the
19460 ISA_MIPS* enumeration). */
19462 static const struct mips_cpu_info *
19463 mips_cpu_info_from_isa (int isa)
19467 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19468 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
19469 && isa == mips_cpu_info_table[i].isa)
19470 return (&mips_cpu_info_table[i]);
19475 static const struct mips_cpu_info *
19476 mips_cpu_info_from_arch (int arch)
19480 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19481 if (arch == mips_cpu_info_table[i].cpu)
19482 return (&mips_cpu_info_table[i]);
19488 show (FILE *stream, const char *string, int *col_p, int *first_p)
19492 fprintf (stream, "%24s", "");
19497 fprintf (stream, ", ");
19501 if (*col_p + strlen (string) > 72)
19503 fprintf (stream, "\n%24s", "");
19507 fprintf (stream, "%s", string);
19508 *col_p += strlen (string);
19514 md_show_usage (FILE *stream)
19519 fprintf (stream, _("\
19521 -EB generate big endian output\n\
19522 -EL generate little endian output\n\
19523 -g, -g2 do not remove unneeded NOPs or swap branches\n\
19524 -G NUM allow referencing objects up to NUM bytes\n\
19525 implicitly with the gp register [default 8]\n"));
19526 fprintf (stream, _("\
19527 -mips1 generate MIPS ISA I instructions\n\
19528 -mips2 generate MIPS ISA II instructions\n\
19529 -mips3 generate MIPS ISA III instructions\n\
19530 -mips4 generate MIPS ISA IV instructions\n\
19531 -mips5 generate MIPS ISA V instructions\n\
19532 -mips32 generate MIPS32 ISA instructions\n\
19533 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19534 -mips64 generate MIPS64 ISA instructions\n\
19535 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19536 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
19540 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
19541 show (stream, mips_cpu_info_table[i].name, &column, &first);
19542 show (stream, "from-abi", &column, &first);
19543 fputc ('\n', stream);
19545 fprintf (stream, _("\
19546 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
19547 -no-mCPU don't generate code specific to CPU.\n\
19548 For -mCPU and -no-mCPU, CPU must be one of:\n"));
19552 show (stream, "3900", &column, &first);
19553 show (stream, "4010", &column, &first);
19554 show (stream, "4100", &column, &first);
19555 show (stream, "4650", &column, &first);
19556 fputc ('\n', stream);
19558 fprintf (stream, _("\
19559 -mips16 generate mips16 instructions\n\
19560 -no-mips16 do not generate mips16 instructions\n"));
19561 fprintf (stream, _("\
19562 -mmicromips generate microMIPS instructions\n\
19563 -mno-micromips do not generate microMIPS instructions\n"));
19564 fprintf (stream, _("\
19565 -msmartmips generate smartmips instructions\n\
19566 -mno-smartmips do not generate smartmips instructions\n"));
19567 fprintf (stream, _("\
19568 -mdsp generate DSP instructions\n\
19569 -mno-dsp do not generate DSP instructions\n"));
19570 fprintf (stream, _("\
19571 -mdspr2 generate DSP R2 instructions\n\
19572 -mno-dspr2 do not generate DSP R2 instructions\n"));
19573 fprintf (stream, _("\
19574 -mmt generate MT instructions\n\
19575 -mno-mt do not generate MT instructions\n"));
19576 fprintf (stream, _("\
19577 -mmcu generate MCU instructions\n\
19578 -mno-mcu do not generate MCU instructions\n"));
19579 fprintf (stream, _("\
19580 -mvirt generate Virtualization instructions\n\
19581 -mno-virt do not generate Virtualization instructions\n"));
19582 fprintf (stream, _("\
19583 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
19584 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
19585 -mfix-vr4120 work around certain VR4120 errata\n\
19586 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
19587 -mfix-24k insert a nop after ERET and DERET instructions\n\
19588 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
19589 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19590 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
19591 -msym32 assume all symbols have 32-bit values\n\
19592 -O0 remove unneeded NOPs, do not swap branches\n\
19593 -O remove unneeded NOPs and swap branches\n\
19594 --trap, --no-break trap exception on div by 0 and mult overflow\n\
19595 --break, --no-trap break exception on div by 0 and mult overflow\n"));
19596 fprintf (stream, _("\
19597 -mhard-float allow floating-point instructions\n\
19598 -msoft-float do not allow floating-point instructions\n\
19599 -msingle-float only allow 32-bit floating-point operations\n\
19600 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
19601 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
19602 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
19604 fprintf (stream, _("\
19605 -KPIC, -call_shared generate SVR4 position independent code\n\
19606 -call_nonpic generate non-PIC code that can operate with DSOs\n\
19607 -mvxworks-pic generate VxWorks position independent code\n\
19608 -non_shared do not generate code that can operate with DSOs\n\
19609 -xgot assume a 32 bit GOT\n\
19610 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
19611 -mshared, -mno-shared disable/enable .cpload optimization for\n\
19612 position dependent (non shared) code\n\
19613 -mabi=ABI create ABI conformant object file for:\n"));
19617 show (stream, "32", &column, &first);
19618 show (stream, "o64", &column, &first);
19619 show (stream, "n32", &column, &first);
19620 show (stream, "64", &column, &first);
19621 show (stream, "eabi", &column, &first);
19623 fputc ('\n', stream);
19625 fprintf (stream, _("\
19626 -32 create o32 ABI object file (default)\n\
19627 -n32 create n32 ABI object file\n\
19628 -64 create 64 ABI object file\n"));
19633 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
19635 if (HAVE_64BIT_SYMBOLS)
19636 return dwarf2_format_64bit_irix;
19638 return dwarf2_format_32bit;
19643 mips_dwarf2_addr_size (void)
19645 if (HAVE_64BIT_OBJECTS)
19651 /* Standard calling conventions leave the CFA at SP on entry. */
19653 mips_cfi_frame_initial_instructions (void)
19655 cfi_add_CFA_def_cfa_register (SP);
19659 tc_mips_regname_to_dw2regnum (char *regname)
19661 unsigned int regnum = -1;
19664 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))